/u-boot.sha1
/u-boot.dis
/u-boot.lds
+/u-boot.lst
/u-boot.ubl
/u-boot.ais
/u-boot.dtb
Matthias Fuchs <matthias.fuchs@esd-electronics.com>
- ADCIOP IOP480 (PPC401)
APC405 PPC405GP
AR405 PPC405GP
ASH405 PPC405EP
CPCI405AB PPC405GP
CPCI405DT PPC405GP
CPCIISER4 PPC405GP
- DASA_SIM IOP480 (PPC401)
DP405 PPC405EP
DU405 PPC405GP
DU440 PPC440EPx
Paul Gortmaker <paul.gortmaker@windriver.com>
sbc8349 MPC8349
- sbc8540 MPC8540
sbc8548 MPC8548
- sbc8560 MPC8560
sbc8641d MPC8641D
Frank Gottschling <fgottschling@eltec.de>
uc101 MPC5200
ve8313 MPC8313
-Peter De Schrijver <p2@mind.be>
-
- ML2 PPC4xx
-
Andre Schwarz <andre.schwarz@matrix-vision.de>
mergerbox MPC8377
twister omap3
vision2 i.MX51
+Lukasz Dalek <luk0104@gmail.com>
+
+ h2200 xscale/pxa
+
Jason Liu <r64343@freescale.com>
mx53evk i.MX53
mx31pdk i.MX31
mx53ard i.MX53
mx53smd i.MX53
+ mx6qsabresd i.MX6Q
+ mx6qsabreauto i.MX6Q
Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
Thierry Reding <thierry.reding@avionic-design.de>
plutux Tegra20 (ARM7 & A9 Dual Core)
- medcom Tegra20 (ARM7 & A9 Dual Core)
+ medcom-wide Tegra20 (ARM7 & A9 Dual Core)
tec Tegra20 (ARM7 & A9 Dual Core)
Christian Riesch <christian.riesch@omicron.at>
-------------------------------------------------------------------------
Unknown / orphaned boards:
- Board CPU Last known maintainer / Comment
+ Board CPU Last known maintainer / Comment
.........................................................................
omap1510inn ARM925T Kshitij Gupta <kshitij@ti.com>
incaip MIPS32 4Kc
-Thomas Lange <thomas@corelatus.se>
- dbau1x00 MIPS32 Au1000
- gth2 MIPS32 Au1000
-
Vlad Lungu <vlad.lungu@windriver.com>
qemu_mips MIPS32
qi_lb60 MIPS32 (XBurst Jz4740 SoC)
+-------------------------------------------------------------------------
+
+Unknown / orphaned boards:
+ Board CPU Last known maintainer / Comment
+.........................................................................
+
+ dbau1x00 MIPS32 Au1000 Thomas Lange <thomas@corelatus.se>
+
#########################################################################
# Nios-II Systems: #
# #
-l, --list List all targets to be built
-m, --maintainers List all targets and maintainer email
-M, --mails List all targets and all affilated emails
+ -C, --check Enable build checking
-h, --help This help output
Selections by these options are logically ANDed; if the same option
exit ${ret}
}
-SHORT_OPTS="ha:c:v:s:lmM"
-LONG_OPTS="help,arch:,cpu:,vendor:,soc:,list,maintainers,mails"
+SHORT_OPTS="ha:c:v:s:lmMC"
+LONG_OPTS="help,arch:,cpu:,vendor:,soc:,list,maintainers,mails,check"
# Option processing based on util-linux-2.13/getopt-parse.bash
fi
SELECTED='y'
shift 2 ;;
+ -C|--check)
+ CHECK='C=1'
+ shift ;;
-l|--list)
ONLY_LIST='y'
shift ;;
dbau1100 \
dbau1500 \
dbau1550 \
- gth2 \
"
LIST_mips=" \
${MAKE} distclean >/dev/null
${MAKE} -s ${target}_config
- ${MAKE} ${JOBS} all \
+ ${MAKE} ${JOBS} ${CHECK} all \
>${LOG_DIR}/$target.MAKELOG 2> ${LOG_DIR}/$target.ERR
# Check for 'make' errors
endif
endif
+# Call a source code checker (by default, "sparse") as part of the
+# C compilation.
+#
+# Use 'make C=1' to enable checking of re-compiled files.
+#
+# See the linux kernel file "Documentation/sparse.txt" for more details,
+# including where to get the "sparse" utility.
+
+ifdef C
+ifeq ("$(origin C)", "command line")
+CHECKSRC := $(C)
+endif
+endif
+ifndef CHECKSRC
+ CHECKSRC = 0
+endif
+export CHECKSRC
+
ifneq ($(BUILD_DIR),)
saved-output := $(BUILD_DIR)
endif
LIBS-$(CONFIG_OF_EMBED) += dts/libdts.o
LIBS-y += arch/$(ARCH)/lib/lib$(ARCH).o
-LIBS-y += fs/cramfs/libcramfs.o \
+LIBS-y += fs/cbfs/libcbfs.o \
+ fs/cramfs/libcramfs.o \
fs/ext4/libext4fs.o \
fs/fat/libfat.o \
fs/fdos/libfdos.o \
endif
ifeq ($(SOC),tegra20)
LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
+LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o
+LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o
endif
LIBS := $(addprefix $(obj),$(sort $(LIBS-y)))
$(PLATFORM_LIBS) -Wl,-Map -Wl,u-boot.map -o u-boot
else
GEN_UBOOT = \
- UNDEF_SYM=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \
- sed -n -e 's/.*\($(SYM_PREFIX)__u_boot_cmd_.*\)/-u\1/p'|sort|uniq`;\
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) $$UNDEF_SYM $(__OBJS) \
+ UNDEF_LST=`$(OBJDUMP) -x $(LIBBOARD) $(LIBS) | \
+ sed -n -e 's/.*\($(SYM_PREFIX)_u_boot_list_.*\)/-u\1/p'|sort|uniq`;\
+ cd $(LNDIR) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \
+ $$UNDEF_LST $(__OBJS) \
--start-group $(__LIBS) --end-group $(PLATFORM_LIBS) \
-Map u-boot.map -o u-boot
endif
$(LDSCRIPT): depend
$(MAKE) -C $(dir $@) $(notdir $@)
-$(obj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+# The following line expands into whole rule which generates u-boot.lst,
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(obj)include/u-boot.lst, $(LIBBOARD) $(LIBS)))
+$(obj)u-boot.lds: $(LDSCRIPT) $(obj)include/u-boot.lst
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$< >$@
nand_spl: $(TIMESTAMP_FILE) $(VERSION_FILE) depend
$(MAKE) -C nand_spl/board/$(BOARDDIR) all
$(MAKE) -C tools/$@ all MTD_VERSION=${MTD_VERSION}
gdbtools: gdb
+xmldocs pdfdocs psdocs htmldocs mandocs: tools/kernel-doc/docproc
+ $(MAKE) U_BOOT_VERSION=$(U_BOOT_VERSION) -C doc/DocBook/ $@
+
tools-all: easylogo env gdb $(VERSION_FILE) $(TIMESTAMP_FILE)
$(MAKE) -C tools HOST_TOOLS_ALL=y
$(obj)tools/mk{env,}image $(obj)tools/mpc86x_clk \
$(obj)tools/mk{smdk5250,}spl \
$(obj)tools/mxsboot \
- $(obj)tools/ncb $(obj)tools/ubsha1
+ $(obj)tools/ncb $(obj)tools/ubsha1 \
+ $(obj)tools/kernel-doc/docproc
@rm -f $(obj)board/cray/L1/{bootscript.c,bootscript.image} \
$(obj)board/matrix_vision/*/bootscript.img \
$(obj)board/voiceblue/eeprom \
$(obj)u-boot.lds \
+ $(obj)include/u-boot.lst \
$(obj)arch/blackfin/cpu/bootrom-asm-offsets.[chs] \
$(obj)arch/blackfin/cpu/init.{lds,elf}
@rm -f $(obj)include/bmp_logo.h
@rm -f $(obj)include/generated/asm-offsets.h
@rm -f $(obj)$(CPUDIR)/$(SOC)/asm-offsets.s
@rm -f $(TIMESTAMP_FILE) $(VERSION_FILE)
+ @$(MAKE) -C doc/DocBook/ cleandocs
@find $(OBJTREE) -type f \
\( -name 'core' -o -name '*.bak' -o -name '*~' -o -name '*.su' \
-o -name '*.o' -o -name '*.a' -o -name '*.exe' \) -print \
@rm -f $(obj)u-boot.dtb
@rm -f $(obj)u-boot.sb
@rm -f $(obj)u-boot.spr
- @rm -f $(obj)nand_spl/{u-boot.lds,u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map,System.map}
- @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.lds,u-boot-spl.map}
+ @rm -f $(obj)nand_spl/{u-boot.{lds,lst},System.map}
+ @rm -f $(obj)nand_spl/{u-boot-nand_spl.lds,u-boot-spl,u-boot-spl.map}
+ @rm -f $(obj)spl/{u-boot-spl,u-boot-spl.bin,u-boot-spl.map}
+ @rm -f $(obj)spl/{u-boot-spl.lds,u-boot.lst}
@rm -f $(obj)MLO
@rm -f $(obj)tools/xway-swap-bytes
@rm -f $(obj)arch/powerpc/cpu/mpc824x/bedbug_603e.c
CONFIG_CALXEDA_XGMAC
Support for the Calxeda XGMAC device
- CONFIG_DRIVER_LAN91C96
+ CONFIG_LAN91C96
Support for SMSC's LAN91C96 chips.
CONFIG_LAN91C96_BASE
CONFIG_LAN91C96_USE_32_BIT
Define this to enable 32 bit addressing
- CONFIG_DRIVER_SMC91111
+ CONFIG_SMC91111
Support for SMSC's LAN91C111 chip
CONFIG_SMC91111_BASE
viewport is supported.
To enable the ULPI layer support, define CONFIG_USB_ULPI and
CONFIG_USB_ULPI_VIEWPORT in your board configuration file.
+ If your ULPI phy needs a different reference clock than the
+ standard 24 MHz then you have to define CONFIG_ULPI_REF_CLK to
+ the appropriate value in Hz.
- MMC Support:
The MMC controller on the Intel PXA is supported. To
This will also enable the command "fatwrite" enabling the
user to write files to FAT.
+CBFS (Coreboot Filesystem) support
+ CONFIG_CMD_CBFS
+
+ Define this to enable support for reading from a Coreboot
+ filesystem. Available commands are cbfsinit, cbfsinfo, cbfsls
+ and cbfsload.
+
- Keyboard Support:
CONFIG_ISA_KEYBOARD
29,916,167 26,005,792 bootm_start
30,361,327 445,160 start_kernel
+ CONFIG_CMD_BOOTSTAGE
+ Add a 'bootstage' command which supports printing a report
+ and un/stashing of bootstage data.
+
+ CONFIG_BOOTSTAGE_FDT
+ Stash the bootstage information in the FDT. A root 'bootstage'
+ node is created with each bootstage id as a child. Each child
+ has a 'name' property and either 'mark' containing the
+ mark time in microsecond, or 'accum' containing the
+ accumulated time for that bootstage id in microseconds.
+ For example:
+
+ bootstage {
+ 154 {
+ name = "board_init_f";
+ mark = <3575678>;
+ };
+ 170 {
+ name = "lcd";
+ accum = <33482>;
+ };
+ };
+
+ Code in the Linux kernel can find this in /proc/devicetree.
+
Legacy uImage format:
Arg Where When
case MXC_CSPI_CLK:
case MXC_UART_CLK:
case MXC_ESDHC_CLK:
+ case MXC_I2C_CLK:
return mx31_get_ipg_clk();
case MXC_IPU_CLK:
return mx31_get_hsp_clk();
int main(void)
{
-
/* Round up to make sure size gives nice stack alignment */
DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
DEFINE(CLKCTL_CGR0, offsetof(struct ccm_regs, cgr0));
DEFINE(CLKCTL_CGR1, offsetof(struct ccm_regs, cgr1));
DEFINE(CLKCTL_CGR2, offsetof(struct ccm_regs, cgr2));
+ DEFINE(CLKCTL_CGR3, offsetof(struct ccm_regs, cgr3));
+
+ /* Multi-Layer AHB Crossbar Switch */
+ DEFINE(MAX_MPR0, offsetof(struct max_regs, mpr0));
+ DEFINE(MAX_SGPCR0, offsetof(struct max_regs, sgpcr0));
+ DEFINE(MAX_MPR1, offsetof(struct max_regs, mpr1));
+ DEFINE(MAX_SGPCR1, offsetof(struct max_regs, sgpcr1));
+ DEFINE(MAX_MPR2, offsetof(struct max_regs, mpr2));
+ DEFINE(MAX_SGPCR2, offsetof(struct max_regs, sgpcr2));
+ DEFINE(MAX_MPR3, offsetof(struct max_regs, mpr3));
+ DEFINE(MAX_SGPCR3, offsetof(struct max_regs, sgpcr3));
+ DEFINE(MAX_MPR4, offsetof(struct max_regs, mpr4));
+ DEFINE(MAX_SGPCR4, offsetof(struct max_regs, sgpcr4));
+ DEFINE(MAX_MGPCR0, offsetof(struct max_regs, mgpcr0));
+ DEFINE(MAX_MGPCR1, offsetof(struct max_regs, mgpcr1));
+ DEFINE(MAX_MGPCR2, offsetof(struct max_regs, mgpcr2));
+ DEFINE(MAX_MGPCR3, offsetof(struct max_regs, mgpcr3));
+ DEFINE(MAX_MGPCR4, offsetof(struct max_regs, mgpcr4));
+ DEFINE(MAX_MGPCR5, offsetof(struct max_regs, mgpcr5));
+
+ /* AHB <-> IP-Bus Interface */
+ DEFINE(AIPS_MPR_0_7, offsetof(struct aips_regs, mpr_0_7));
+ DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
+ DEFINE(AIPS_PACR_0_7, offsetof(struct aips_regs, pacr_0_7));
+ DEFINE(AIPS_PACR_8_15, offsetof(struct aips_regs, pacr_8_15));
+ DEFINE(AIPS_PACR_16_23, offsetof(struct aips_regs, pacr_16_23));
+ DEFINE(AIPS_PACR_24_31, offsetof(struct aips_regs, pacr_24_31));
+ DEFINE(AIPS_OPACR_0_7, offsetof(struct aips_regs, opacr_0_7));
+ DEFINE(AIPS_OPACR_8_15, offsetof(struct aips_regs, opacr_8_15));
+ DEFINE(AIPS_OPACR_16_23, offsetof(struct aips_regs, opacr_16_23));
+ DEFINE(AIPS_OPACR_24_31, offsetof(struct aips_regs, opacr_24_31));
+ DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
return 0;
}
case MXC_IPG_CLK:
return get_ipg_clk();
case MXC_IPG_PERCLK:
+ case MXC_I2C_CLK:
return get_ipg_per_clk();
case MXC_UART_CLK:
return imx_get_uartclk();
LIB = $(obj)lib$(SOC).o
-COBJS += aemif.o clock.o init.o mux.o timer.o wdt.o
+COBJS += aemif.o clock.o init.o mux.o timer.o
SOBJS += lowlevel_init.o
SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
#
-# (C) Copyright 2005-2006
+# (C) Copyright 2010,2011 Nvidia Corporation.
+#
+# (C) Copyright 2000-2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).o
+LIB = $(obj)libtegra-common.o
+
+COBJS-$(CONFIG_SPL_BUILD) += spl.o
-COBJS = $(BOARD).o flash.o ee_access.o
-SOBJS = lowlevel_init.o
+SRCS := $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+all: $(obj).depend $(LIB)
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+$(LIB): $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
#include <common.h>
#include <asm/u-boot.h>
#include <asm/utils.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/clock.h>
#include <nand.h>
#include <mmc.h>
#include <fat.h>
#include <image.h>
#include <malloc.h>
#include <linux/compiler.h>
-#include "board.h"
#include "cpu.h"
#include <asm/io.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
-#include <asm/arch/pmc.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/scu.h>
-#include <common.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/board.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/scu.h>
+#include <asm/arch-tegra/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
board_init_uart_f();
/* Initialize periph GPIOs */
-#ifdef CONFIG_SPI_UART_SWITCH
gpio_early_init_uart();
-#else
- gpio_config_uart();
-#endif
/*
* We call relocate_code() with relocation target same as the
LIB = $(obj)lib$(SOC).o
COBJS-y += cpu.o
-COBJS-$(CONFIG_SPL_BUILD) += spl.o
SRCS := $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
* MA 02111-1307 USA
*/
+#include <common.h>
#include <asm/io.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
-#include <asm/arch/pmc.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/scu.h>
-#include <common.h>
-#include "cpu.h"
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/scu.h>
+#include "../tegra-common/cpu.h"
/* Returns 1 if the current CPU executing is a Cortex-A9, else 0 */
int ap20_cpu_is_cortexa9(void)
.got : { *(.got) }
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
__bss_start = .;
COBJS-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o
COBJS-y += speed.o
COBJS-y += timer.o
-COBJS-y += usb.o
-COBJS-y += usb_ohci.o
-
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+++ /dev/null
-/*
- * (C) Copyright 2006
- * DENX Software Engineering <mk@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#if defined(CONFIG_USB_OHCI_NEW) && \
- defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
- defined(CONFIG_S3C24X0)
-
-#include <asm/arch/s3c24x0_cpu.h>
-#include <asm/io.h>
-
-int usb_cpu_init(void)
-{
- struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
- struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
-
- /*
- * Set the 48 MHz UPLL clocking. Values are taken from
- * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
- */
- writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon);
- /* 1 = use pads related USB for USB host */
- writel(readl(&gpio->misccr) | 0x8, &gpio->misccr);
-
- /*
- * Enable USB host clock.
- */
- writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
-
- return 0;
-}
-
-int usb_cpu_stop(void)
-{
- struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
- /* may not want to do this */
- writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
- return 0;
-}
-
-int usb_cpu_init_fail(void)
-{
- struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
- writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
- return 0;
-}
-
-#endif /* defined(CONFIG_USB_OHCI_NEW) && \
- defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
- defined(CONFIG_S3C24X0) */
#include <asm/arch/imx-regs.h>
#include <asm/arch/imx25-pinmux.h>
#include <asm/arch/clock.h>
-#ifdef CONFIG_MXC_MMC
-#include <asm/arch/mxcmmc.h>
-#endif
#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+
DECLARE_GLOBAL_DATA_PTR;
#endif
{
unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
& CCM_PLL_MFI_MASK;
- unsigned int mfn = (pll >> CCM_PLL_MFN_SHIFT)
+ int mfn = (pll >> CCM_PLL_MFN_SHIFT)
& CCM_PLL_MFN_MASK;
unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
& CCM_PLL_MFD_MASK;
& CCM_PLL_PD_MASK;
mfi = mfi <= 5 ? 5 : mfi;
+ mfn = mfn >= 512 ? mfn - 1024 : mfn;
+ mfd += 1;
+ pd += 1;
- return lldiv(2 * (u64) f_ref * (mfi * (mfd + 1) + mfn),
- (mfd + 1) * (pd + 1));
+ return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
+ mfd * pd);
}
static ulong imx_get_mpllclk(void)
return imx_decode_pll(readl(&ccm->mpctl), fref);
}
-ulong imx_get_armclk(void)
+static ulong imx_get_armclk(void)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong cctl = readl(&ccm->cctl);
ulong div;
if (cctl & CCM_CCTL_ARM_SRC)
- fref = lldiv((fref * 3), 4);
+ fref = lldiv((u64) fref * 3, 4);
div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
& CCM_CCTL_ARM_DIV_MASK) + 1;
- return lldiv(fref, div);
+ return fref / div;
}
-ulong imx_get_ahbclk(void)
+static ulong imx_get_ahbclk(void)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong cctl = readl(&ccm->cctl);
div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
& CCM_CCTL_AHB_DIV_MASK) + 1;
- return lldiv(fref, div);
+ return fref / div;
+}
+
+static ulong imx_get_ipgclk(void)
+{
+ return imx_get_ahbclk() / 2;
}
-ulong imx_get_perclk(int clk)
+static ulong imx_get_perclk(int clk)
{
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong fref = imx_get_ahbclk();
div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
- return lldiv(fref, div);
+ return fref / div;
}
unsigned int mxc_get_clock(enum mxc_clock clk)
switch (clk) {
case MXC_ARM_CLK:
return imx_get_armclk();
- case MXC_FEC_CLK:
+ case MXC_AHB_CLK:
return imx_get_ahbclk();
+ case MXC_IPG_CLK:
+ case MXC_CSPI_CLK:
+ case MXC_FEC_CLK:
+ return imx_get_ipgclk();
default:
return imx_get_perclk(clk);
}
case 0x01:
system_rev |= CHIP_REV_1_1;
break;
+ case 0x02:
+ system_rev |= CHIP_REV_1_2;
+ break;
default:
system_rev |= 0x8000;
break;
#endif
}
+#if defined(CONFIG_FEC_MXC)
+/*
+ * Initializes on-chip ethernet controllers.
+ * to override, implement board_eth_init()
+ */
int cpu_eth_init(bd_t *bis)
{
-#if defined(CONFIG_FEC_MXC)
struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
ulong val;
val |= (1 << 23);
writel(val, &ccm->cgr0);
return fecmxc_initialize(bis);
-#else
- return 0;
-#endif
}
+#endif
int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC
- gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
+ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#else
+ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
+#endif
#endif
return 0;
}
+#ifdef CONFIG_FSL_ESDHC
/*
* Initializes on-chip MMC controllers.
* to override, implement board_mmc_init()
*/
int cpu_mmc_init(bd_t *bis)
{
-#ifdef CONFIG_MXC_MMC
- return mxc_mmc_init(bis);
-#else
- return 0;
-#endif
+ return fsl_esdhc_mmc_init(bis);
}
+#endif
#ifdef CONFIG_MXC_UART
void mx25_uart1_init_pins(void)
;
}
-#ifndef CONFIG_SPL_SERIAL_SUPPORT
-void serial_putc(const char c) {}
-void serial_puts(const char *s) {}
-#endif
void hang(void) __attribute__ ((noreturn));
void hang(void)
{
}
. = ALIGN(4);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
*/
int print_cpuinfo(void)
{
- char dev_str[] = "0x0000";
- char rev_str[] = "0x00";
+ char dev_str[7]; /* room enough for 0x0000 plus null byte */
+ char rev_str[5]; /* room enough for 0x00 plus null byte */
char *dev_name = NULL;
char *rev_name = NULL;
}
. = ALIGN(4);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
# supported by more tool-chains
PF_CPPFLAGS_ARMV7 := $(call cc-option, -march=armv7-a, -march=armv5)
PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_ARMV7)
-PF_CPPFLAGS_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,)
-PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_NO_UNALIGNED)
# =========================================================================
#
# =========================================================================
PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
+
+# SEE README.arm-unaligned-accesses
+PF_NO_UNALIGNED := $(call cc-option, -mno-unaligned-access,)
+PLATFORM_NO_UNALIGNED := $(PF_NO_UNALIGNED)
+
ifneq ($(CONFIG_IMX_CONFIG),)
ALL-y += $(obj)u-boot.imx
endif
PLL1_CLOCK = 0,
PLL2_CLOCK,
PLL3_CLOCK,
+#ifdef CONFIG_MX53
PLL4_CLOCK,
+#endif
PLL_CLOCKS,
};
};
const struct fixed_pll_mfd fixed_mfd[] = {
- {CONFIG_SYS_MX5_HCLK, 24 * 16},
+ {MXC_HCLK, 24 * 16},
};
struct pll_param {
void set_usboh3_clk(void)
{
- unsigned int reg;
-
- reg = readl(&mxc_ccm->cscmr1) &
- ~MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK;
- reg |= 1 << MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET;
- writel(reg, &mxc_ccm->cscmr1);
-
- reg = readl(&mxc_ccm->cscdr1);
- reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK;
- reg &= ~MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK;
- reg |= 4 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET;
- reg |= 1 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET;
-
- writel(reg, &mxc_ccm->cscdr1);
+ clrsetbits_le32(&mxc_ccm->cscmr1,
+ MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK,
+ MXC_CCM_CSCMR1_USBOH3_CLK_SEL(1));
+ clrsetbits_le32(&mxc_ccm->cscdr1,
+ MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK |
+ MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK,
+ MXC_CCM_CSCDR1_USBOH3_CLK_PRED(4) |
+ MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
}
void enable_usboh3_clk(unsigned char enable)
{
- unsigned int reg;
+ unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
- reg = readl(&mxc_ccm->CCGR2);
- if (enable)
- reg |= 1 << MXC_CCM_CCGR2_CG14_OFFSET;
- else
- reg &= ~(1 << MXC_CCM_CCGR2_CG14_OFFSET);
- writel(reg, &mxc_ccm->CCGR2);
+ clrsetbits_le32(&mxc_ccm->CCGR2,
+ MXC_CCM_CCGR2_USBOH3_60M(MXC_CCM_CCGR_CG_MASK),
+ MXC_CCM_CCGR2_USBOH3_60M(cg));
}
#ifdef CONFIG_I2C_MXC
-/* i2c_num can be from 0 - 2 */
+/* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */
int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
{
- u32 reg;
u32 mask;
+#if defined(CONFIG_MX51)
+ if (i2c_num > 1)
+#elif defined(CONFIG_MX53)
if (i2c_num > 2)
+#endif
return -EINVAL;
- mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 9) << 1);
- reg = __raw_readl(&mxc_ccm->CCGR1);
+ mask = MXC_CCM_CCGR_CG_MASK <<
+ (MXC_CCM_CCGR1_I2C1_OFFSET + (i2c_num << 1));
if (enable)
- reg |= mask;
+ setbits_le32(&mxc_ccm->CCGR1, mask);
else
- reg &= ~mask;
- __raw_writel(reg, &mxc_ccm->CCGR1);
+ clrbits_le32(&mxc_ccm->CCGR1, mask);
return 0;
}
#endif
-void set_usb_phy1_clk(void)
+void set_usb_phy_clk(void)
{
- unsigned int reg;
-
- reg = readl(&mxc_ccm->cscmr1);
- reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
- writel(reg, &mxc_ccm->cscmr1);
+ clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
}
+#if defined(CONFIG_MX51)
void enable_usb_phy1_clk(unsigned char enable)
{
- unsigned int reg;
+ unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
- reg = readl(&mxc_ccm->CCGR4);
- if (enable)
- reg |= 1 << MXC_CCM_CCGR4_CG5_OFFSET;
- else
- reg &= ~(1 << MXC_CCM_CCGR4_CG5_OFFSET);
- writel(reg, &mxc_ccm->CCGR4);
+ clrsetbits_le32(&mxc_ccm->CCGR2,
+ MXC_CCM_CCGR2_USB_PHY(MXC_CCM_CCGR_CG_MASK),
+ MXC_CCM_CCGR2_USB_PHY(cg));
}
-void set_usb_phy2_clk(void)
+void enable_usb_phy2_clk(unsigned char enable)
{
- unsigned int reg;
+ /* i.MX51 has a single USB PHY clock, so do nothing here. */
+}
+#elif defined(CONFIG_MX53)
+void enable_usb_phy1_clk(unsigned char enable)
+{
+ unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
- reg = readl(&mxc_ccm->cscmr1);
- reg &= ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
- writel(reg, &mxc_ccm->cscmr1);
+ clrsetbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_USB_PHY1(MXC_CCM_CCGR_CG_MASK),
+ MXC_CCM_CCGR4_USB_PHY1(cg));
}
void enable_usb_phy2_clk(unsigned char enable)
{
- unsigned int reg;
+ unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
- reg = readl(&mxc_ccm->CCGR4);
- if (enable)
- reg |= 1 << MXC_CCM_CCGR4_CG6_OFFSET;
- else
- reg &= ~(1 << MXC_CCM_CCGR4_CG6_OFFSET);
- writel(reg, &mxc_ccm->CCGR4);
+ clrsetbits_le32(&mxc_ccm->CCGR4,
+ MXC_CCM_CCGR4_USB_PHY2(MXC_CCM_CCGR_CG_MASK),
+ MXC_CCM_CCGR4_USB_PHY2(cg));
}
+#endif
/*
* Calculate the frequency of PLLn.
ctrl = readl(&pll->ctrl);
if (ctrl & MXC_DPLLC_CTL_HFSM) {
- mfn = __raw_readl(&pll->hfs_mfn);
- mfd = __raw_readl(&pll->hfs_mfd);
- op = __raw_readl(&pll->hfs_op);
+ mfn = readl(&pll->hfs_mfn);
+ mfd = readl(&pll->hfs_mfd);
+ op = readl(&pll->hfs_op);
} else {
- mfn = __raw_readl(&pll->mfn);
- mfd = __raw_readl(&pll->mfd);
- op = __raw_readl(&pll->op);
+ mfn = readl(&pll->mfn);
+ mfd = readl(&pll->mfd);
+ op = readl(&pll->op);
}
mfd &= MXC_DPLLC_MFD_MFD_MASK;
mfn &= MXC_DPLLC_MFN_MFN_MASK;
pdf = op & MXC_DPLLC_OP_PDF_MASK;
- mfi = (op & MXC_DPLLC_OP_MFI_MASK) >> MXC_DPLLC_OP_MFI_OFFSET;
+ mfi = MXC_DPLLC_OP_MFI_RD(op);
/* 21.2.3 */
if (mfi < 5)
return ret;
}
+#ifdef CONFIG_MX51
+/*
+ * This function returns the Frequency Pre-Multiplier clock.
+ */
+static u32 get_fpm(void)
+{
+ u32 mult;
+ u32 ccr = readl(&mxc_ccm->ccr);
+
+ if (ccr & MXC_CCM_CCR_FPM_MULT)
+ mult = 1024;
+ else
+ mult = 512;
+
+ return MXC_CLK32 * mult;
+}
+#endif
+
+/*
+ * This function returns the low power audio clock.
+ */
+static u32 get_lp_apm(void)
+{
+ u32 ret_val = 0;
+ u32 ccsr = readl(&mxc_ccm->ccsr);
+
+ if (ccsr & MXC_CCM_CCSR_LP_APM)
+#if defined(CONFIG_MX51)
+ ret_val = get_fpm();
+#elif defined(CONFIG_MX53)
+ ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
+#endif
+ else
+ ret_val = MXC_HCLK;
+
+ return ret_val;
+}
+
/*
* Get mcu main rate
*/
{
u32 reg, freq;
- reg = (__raw_readl(&mxc_ccm->cacrr) & MXC_CCM_CACRR_ARM_PODF_MASK) >>
- MXC_CCM_CACRR_ARM_PODF_OFFSET;
- freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
+ reg = MXC_CCM_CACRR_ARM_PODF_RD(readl(&mxc_ccm->cacrr));
+ freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
return freq / (reg + 1);
}
{
u32 reg;
- reg = __raw_readl(&mxc_ccm->cbcdr);
+ reg = readl(&mxc_ccm->cbcdr);
if (!(reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL))
- return decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
- reg = __raw_readl(&mxc_ccm->cbcmr);
- switch ((reg & MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >>
- MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
+ return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
+ reg = readl(&mxc_ccm->cbcmr);
+ switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(reg)) {
case 0:
- return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
+ return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
case 1:
- return decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
+ return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
+ case 2:
+ return get_lp_apm();
default:
return 0;
}
freq = get_ahb_clk();
- reg = __raw_readl(&mxc_ccm->cbcdr);
- div = ((reg & MXC_CCM_CBCDR_IPG_PODF_MASK) >>
- MXC_CCM_CBCDR_IPG_PODF_OFFSET) + 1;
+ reg = readl(&mxc_ccm->cbcdr);
+ div = MXC_CCM_CBCDR_IPG_PODF_RD(reg) + 1;
return freq / div;
}
*/
static u32 get_ipg_per_clk(void)
{
- u32 pred1, pred2, podf;
+ u32 freq, pred1, pred2, podf;
- if (__raw_readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
+ if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL)
return get_ipg_clk();
- /* Fixme: not handle what about lpm*/
- podf = __raw_readl(&mxc_ccm->cbcdr);
- pred1 = (podf & MXC_CCM_CBCDR_PERCLK_PRED1_MASK) >>
- MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET;
- pred2 = (podf & MXC_CCM_CBCDR_PERCLK_PRED2_MASK) >>
- MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET;
- podf = (podf & MXC_CCM_CBCDR_PERCLK_PODF_MASK) >>
- MXC_CCM_CBCDR_PERCLK_PODF_OFFSET;
- return get_periph_clk() / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
+ if (readl(&mxc_ccm->cbcmr) & MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL)
+ freq = get_lp_apm();
+ else
+ freq = get_periph_clk();
+ podf = readl(&mxc_ccm->cbcdr);
+ pred1 = MXC_CCM_CBCDR_PERCLK_PRED1_RD(podf);
+ pred2 = MXC_CCM_CBCDR_PERCLK_PRED2_RD(podf);
+ podf = MXC_CCM_CBCDR_PERCLK_PODF_RD(podf);
+ return freq / ((pred1 + 1) * (pred2 + 1) * (podf + 1));
}
-/*
- * Get the rate of uart clk.
- */
-static u32 get_uart_clk(void)
+/* Get the output clock rate of a standard PLL MUX for peripherals. */
+static u32 get_standard_pll_sel_clk(u32 clk_sel)
{
- unsigned int freq, reg, pred, podf;
+ u32 freq;
- reg = __raw_readl(&mxc_ccm->cscmr1);
- switch ((reg & MXC_CCM_CSCMR1_UART_CLK_SEL_MASK) >>
- MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET) {
- case 0x0:
- freq = decode_pll(mxc_plls[PLL1_CLOCK],
- CONFIG_SYS_MX5_HCLK);
+ switch (clk_sel & 0x3) {
+ case 0:
+ freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
+ break;
+ case 1:
+ freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
break;
- case 0x1:
- freq = decode_pll(mxc_plls[PLL2_CLOCK],
- CONFIG_SYS_MX5_HCLK);
+ case 2:
+ freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
break;
- case 0x2:
- freq = decode_pll(mxc_plls[PLL3_CLOCK],
- CONFIG_SYS_MX5_HCLK);
+ case 3:
+ freq = get_lp_apm();
break;
- default:
- return 66500000;
}
- reg = __raw_readl(&mxc_ccm->cscdr1);
+ return freq;
+}
+
+/*
+ * Get the rate of uart clk.
+ */
+static u32 get_uart_clk(void)
+{
+ unsigned int clk_sel, freq, reg, pred, podf;
- pred = (reg & MXC_CCM_CSCDR1_UART_CLK_PRED_MASK) >>
- MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET;
+ reg = readl(&mxc_ccm->cscmr1);
+ clk_sel = MXC_CCM_CSCMR1_UART_CLK_SEL_RD(reg);
+ freq = get_standard_pll_sel_clk(clk_sel);
- podf = (reg & MXC_CCM_CSCDR1_UART_CLK_PODF_MASK) >>
- MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
+ reg = readl(&mxc_ccm->cscdr1);
+ pred = MXC_CCM_CSCDR1_UART_CLK_PRED_RD(reg);
+ podf = MXC_CCM_CSCDR1_UART_CLK_PODF_RD(reg);
freq /= (pred + 1) * (podf + 1);
return freq;
}
/*
- * This function returns the low power audio clock.
+ * get cspi clock rate.
*/
-static u32 get_lp_apm(void)
+static u32 imx_get_cspiclk(void)
{
- u32 ret_val = 0;
- u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
-
- if (((ccsr >> 9) & 1) == 0)
- ret_val = CONFIG_SYS_MX5_HCLK;
- else
- ret_val = ((32768 * 1024));
+ u32 ret_val = 0, pdf, pre_pdf, clk_sel, freq;
+ u32 cscmr1 = readl(&mxc_ccm->cscmr1);
+ u32 cscdr2 = readl(&mxc_ccm->cscdr2);
+ pre_pdf = MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(cscdr2);
+ pdf = MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(cscdr2);
+ clk_sel = MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(cscmr1);
+ freq = get_standard_pll_sel_clk(clk_sel);
+ ret_val = freq / ((pre_pdf + 1) * (pdf + 1));
return ret_val;
}
/*
- * get cspi clock rate.
+ * get esdhc clock rate.
*/
-static u32 imx_get_cspiclk(void)
+static u32 get_esdhc_clk(u32 port)
{
- u32 ret_val = 0, pdf, pre_pdf, clk_sel;
- u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1);
- u32 cscdr2 = __raw_readl(&mxc_ccm->cscdr2);
+ u32 clk_sel = 0, pred = 0, podf = 0, freq = 0;
+ u32 cscmr1 = readl(&mxc_ccm->cscmr1);
+ u32 cscdr1 = readl(&mxc_ccm->cscdr1);
- pre_pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) \
- >> MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
- pdf = (cscdr2 & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) \
- >> MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
- clk_sel = (cscmr1 & MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK) \
- >> MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
-
- switch (clk_sel) {
+ switch (port) {
case 0:
- ret_val = decode_pll(mxc_plls[PLL1_CLOCK],
- CONFIG_SYS_MX5_HCLK) /
- ((pre_pdf + 1) * (pdf + 1));
+ clk_sel = MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(cscmr1);
+ pred = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(cscdr1);
+ podf = MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(cscdr1);
break;
case 1:
- ret_val = decode_pll(mxc_plls[PLL2_CLOCK],
- CONFIG_SYS_MX5_HCLK) /
- ((pre_pdf + 1) * (pdf + 1));
+ clk_sel = MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(cscmr1);
+ pred = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(cscdr1);
+ podf = MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(cscdr1);
break;
case 2:
- ret_val = decode_pll(mxc_plls[PLL3_CLOCK],
- CONFIG_SYS_MX5_HCLK) /
- ((pre_pdf + 1) * (pdf + 1));
- break;
+ if (cscmr1 & MXC_CCM_CSCMR1_ESDHC3_CLK_SEL)
+ return get_esdhc_clk(1);
+ else
+ return get_esdhc_clk(0);
+ case 3:
+ if (cscmr1 & MXC_CCM_CSCMR1_ESDHC4_CLK_SEL)
+ return get_esdhc_clk(1);
+ else
+ return get_esdhc_clk(0);
default:
- ret_val = get_lp_apm() / ((pre_pdf + 1) * (pdf + 1));
break;
}
- return ret_val;
+ freq = get_standard_pll_sel_clk(clk_sel) / ((pred + 1) * (podf + 1));
+ return freq;
}
static u32 get_axi_a_clk(void)
{
- u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
- u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_A_PODF_MASK) \
- >> MXC_CCM_CBCDR_AXI_A_PODF_OFFSET;
+ u32 cbcdr = readl(&mxc_ccm->cbcdr);
+ u32 pdf = MXC_CCM_CBCDR_AXI_A_PODF_RD(cbcdr);
return get_periph_clk() / (pdf + 1);
}
static u32 get_axi_b_clk(void)
{
- u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
- u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_B_PODF_MASK) \
- >> MXC_CCM_CBCDR_AXI_B_PODF_OFFSET;
+ u32 cbcdr = readl(&mxc_ccm->cbcdr);
+ u32 pdf = MXC_CCM_CBCDR_AXI_B_PODF_RD(cbcdr);
return get_periph_clk() / (pdf + 1);
}
static u32 get_emi_slow_clk(void)
{
- u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+ u32 cbcdr = readl(&mxc_ccm->cbcdr);
u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
- u32 pdf = (cbcdr & MXC_CCM_CBCDR_EMI_PODF_MASK) \
- >> MXC_CCM_CBCDR_EMI_PODF_OFFSET;
+ u32 pdf = MXC_CCM_CBCDR_EMI_PODF_RD(cbcdr);
if (emi_clk_sel)
return get_ahb_clk() / (pdf + 1);
static u32 get_ddr_clk(void)
{
u32 ret_val = 0;
- u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
- u32 ddr_clk_sel = (cbcmr & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) \
- >> MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET;
+ u32 cbcmr = readl(&mxc_ccm->cbcmr);
+ u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
#ifdef CONFIG_MX51
- u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+ u32 cbcdr = readl(&mxc_ccm->cbcdr);
if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
- u32 ddr_clk_podf = (cbcdr & MXC_CCM_CBCDR_DDR_PODF_MASK) >> \
- MXC_CCM_CBCDR_DDR_PODF_OFFSET;
+ u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
- ret_val = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
+ ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
ret_val /= ddr_clk_podf + 1;
return ret_val;
case MXC_IPG_CLK:
return get_ipg_clk();
case MXC_IPG_PERCLK:
+ case MXC_I2C_CLK:
return get_ipg_per_clk();
case MXC_UART_CLK:
return get_uart_clk();
case MXC_CSPI_CLK:
return imx_get_cspiclk();
+ case MXC_ESDHC_CLK:
+ return get_esdhc_clk(0);
+ case MXC_ESDHC2_CLK:
+ return get_esdhc_clk(1);
+ case MXC_ESDHC3_CLK:
+ return get_esdhc_clk(2);
+ case MXC_ESDHC4_CLK:
+ return get_esdhc_clk(3);
case MXC_FEC_CLK:
- return decode_pll(mxc_plls[PLL1_CLOCK],
- CONFIG_SYS_MX5_HCLK);
+ return get_ipg_clk();
case MXC_SATA_CLK:
return get_ahb_clk();
case MXC_DDR_CLK:
return get_uart_clk();
}
-
u32 imx_get_fecclk(void)
{
- return mxc_get_clock(MXC_IPG_CLK);
+ return get_ipg_clk();
}
static int gcd(int m, int n)
#define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
{ \
- __raw_writel(0x1232, &pll->ctrl); \
- __raw_writel(0x2, &pll->config); \
- __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \
- &pll->op); \
- __raw_writel(fn, &(pll->mfn)); \
- __raw_writel((fd) - 1, &pll->mfd); \
- __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \
- &pll->hfs_op); \
- __raw_writel(fn, &pll->hfs_mfn); \
- __raw_writel((fd) - 1, &pll->hfs_mfd); \
- __raw_writel(0x1232, &pll->ctrl); \
- while (!__raw_readl(&pll->ctrl) & 0x1) \
+ writel(0x1232, &pll->ctrl); \
+ writel(0x2, &pll->config); \
+ writel((((pd) - 1) << 0) | ((fi) << 4), \
+ &pll->op); \
+ writel(fn, &(pll->mfn)); \
+ writel((fd) - 1, &pll->mfd); \
+ writel((((pd) - 1) << 0) | ((fi) << 4), \
+ &pll->hfs_op); \
+ writel(fn, &pll->hfs_mfn); \
+ writel((fd) - 1, &pll->hfs_mfd); \
+ writel(0x1232, &pll->ctrl); \
+ while (!readl(&pll->ctrl) & 0x1) \
;\
}
static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
{
- u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
+ u32 ccsr = readl(&mxc_ccm->ccsr);
struct mxc_pll_reg *pll = mxc_plls[index];
switch (index) {
case PLL1_CLOCK:
/* Switch ARM to PLL2 clock */
- __raw_writel(ccsr | 0x4, &mxc_ccm->ccsr);
+ writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
CHANGE_PLL_SETTINGS(pll, pll_param->pd,
pll_param->mfi, pll_param->mfn,
pll_param->mfd);
/* Switch back */
- __raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr);
+ writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
break;
case PLL2_CLOCK:
/* Switch to pll2 bypass clock */
- __raw_writel(ccsr | 0x2, &mxc_ccm->ccsr);
+ writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
CHANGE_PLL_SETTINGS(pll, pll_param->pd,
pll_param->mfi, pll_param->mfn,
pll_param->mfd);
/* Switch back */
- __raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr);
+ writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
break;
case PLL3_CLOCK:
/* Switch to pll3 bypass clock */
- __raw_writel(ccsr | 0x1, &mxc_ccm->ccsr);
+ writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
CHANGE_PLL_SETTINGS(pll, pll_param->pd,
pll_param->mfi, pll_param->mfn,
pll_param->mfd);
/* Switch back */
- __raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr);
+ writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
break;
+#ifdef CONFIG_MX53
case PLL4_CLOCK:
/* Switch to pll4 bypass clock */
- __raw_writel(ccsr | 0x20, &mxc_ccm->ccsr);
+ writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
CHANGE_PLL_SETTINGS(pll, pll_param->pd,
pll_param->mfi, pll_param->mfn,
pll_param->mfd);
/* Switch back */
- __raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr);
+ writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL,
+ &mxc_ccm->ccsr);
break;
+#endif
default:
return -EINVAL;
}
static int config_nfc_clk(u32 nfc_clk)
{
- u32 reg;
u32 parent_rate = get_emi_slow_clk();
u32 div = parent_rate / nfc_clk;
div++;
if (parent_rate / div > NFC_CLK_MAX)
div++;
- reg = __raw_readl(&mxc_ccm->cbcdr);
- reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
- reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
- __raw_writel(reg, &mxc_ccm->cbcdr);
- while (__raw_readl(&mxc_ccm->cdhipr) != 0)
+ clrsetbits_le32(&mxc_ccm->cbcdr,
+ MXC_CCM_CBCDR_NFC_PODF_MASK,
+ MXC_CCM_CBCDR_NFC_PODF(div - 1));
+ while (readl(&mxc_ccm->cdhipr) != 0)
;
return 0;
}
memset(&pll_param, 0, sizeof(struct pll_param));
- if (__raw_readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
+ if (readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
ret = calc_pll_params(ref, freq, &pll_param);
if (ret != 0) {
printf("Error:Can't find pll parameters: %d\n",
ret);
return ret;
}
- switch ((__raw_readl(&mxc_ccm->cbcmr) & \
- MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> \
- MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {
+ switch (MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(
+ readl(&mxc_ccm->cbcmr))) {
case 0:
return config_pll_clk(PLL1_CLOCK, &pll_param);
break;
{
u32 clk_src;
s32 shift = 0, clk_sel, div = 1;
- u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
- u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
+ u32 cbcmr = readl(&mxc_ccm->cbcmr);
if (emi_clk > MAX_DDR_CLK) {
printf("Warning:DDR clock should not exceed %d MHz\n",
clk_src = get_periph_clk();
/* Find DDR clock input */
- clk_sel = (cbcmr >> 10) & 0x3;
+ clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
switch (clk_sel) {
case 0:
shift = 16;
if (div > 8)
div = 8;
- cbcdr = cbcdr & ~(0x7 << shift);
- cbcdr |= ((div - 1) << shift);
- __raw_writel(cbcdr, &mxc_ccm->cbcdr);
- while (__raw_readl(&mxc_ccm->cdhipr) != 0)
+ clrsetbits_le32(&mxc_ccm->cbcdr, 0x7 << shift, (div - 1) << shift);
+ while (readl(&mxc_ccm->cdhipr) != 0)
;
- __raw_writel(0x0, &mxc_ccm->ccdr);
+ writel(0x0, &mxc_ccm->ccdr);
return 0;
}
u32 *tmp_base =
(u32 *)(IIM_BASE_ADDR + 0x180c);
- set_usb_phy1_clk();
+ set_usb_phy_clk();
- writel((readl(tmp_base) & (~0x6)) | 0x4, tmp_base);
+ clrsetbits_le32(tmp_base, 0x6, 0x4);
}
#endif
{
u32 freq;
- freq = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);
+ freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK);
printf("PLL1 %8d MHz\n", freq / 1000000);
- freq = decode_pll(mxc_plls[PLL2_CLOCK], CONFIG_SYS_MX5_HCLK);
+ freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK);
printf("PLL2 %8d MHz\n", freq / 1000000);
- freq = decode_pll(mxc_plls[PLL3_CLOCK], CONFIG_SYS_MX5_HCLK);
+ freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
printf("PLL3 %8d MHz\n", freq / 1000000);
#ifdef CONFIG_MX53
- freq = decode_pll(mxc_plls[PLL4_CLOCK], CONFIG_SYS_MX5_HCLK);
+ freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
printf("PLL4 %8d MHz\n", freq / 1000000);
#endif
#include <generated/asm-offsets.h>
#include <linux/linkage.h>
+.section ".text.init", "x"
+
/*
* L2CC Cache setup/invalidation/disable
*/
mcr 15, 0, r0, c1, c0, 1
/* reconfigure L2 cache aux control reg */
- mov r0, #0xC0 /* tag RAM */
- add r0, r0, #0x4 /* data RAM */
- orr r0, r0, #1 << 24 /* disable write allocate delay */
- orr r0, r0, #1 << 23 /* disable write allocate combine */
- orr r0, r0, #1 << 22 /* disable write allocate */
+ ldr r0, =0xC0 | /* tag RAM */ \
+ 0x4 | /* data RAM */ \
+ 1 << 24 | /* disable write allocate delay */ \
+ 1 << 23 | /* disable write allocate combine */ \
+ 1 << 22 /* disable write allocate */
#if defined(CONFIG_MX51)
- ldr r1, =0x0
- ldr r3, [r1, #ROM_SI_REV]
+ ldr r3, [r4, #ROM_SI_REV]
cmp r3, #0x10
/* disable write combine for TO 2 and lower revs */
ldr r1, =0x00000203
str r1, [r0, #0x40]
- ldr r1, =0x0
- str r1, [r0, #0x44]
+ str r4, [r0, #0x44]
ldr r1, =0x00120125
str r1, [r0, #0x9C]
.macro setup_pll pll, freq
ldr r0, =\pll
+ adr r2, W_DP_\freq
+ bl setup_pll_func
+.endm
+
+#define W_DP_OP 0
+#define W_DP_MFD 4
+#define W_DP_MFN 8
+
+setup_pll_func:
ldr r1, =0x00001232
str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit): BRMO=1 */
mov r1, #0x2
str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
- ldr r1, W_DP_OP_\freq
+ ldr r1, [r2, #W_DP_OP]
str r1, [r0, #PLL_DP_OP]
str r1, [r0, #PLL_DP_HFS_OP]
- ldr r1, W_DP_MFD_\freq
+ ldr r1, [r2, #W_DP_MFD]
str r1, [r0, #PLL_DP_MFD]
str r1, [r0, #PLL_DP_HFS_MFD]
- ldr r1, W_DP_MFN_\freq
+ ldr r1, [r2, #W_DP_MFN]
str r1, [r0, #PLL_DP_MFN]
str r1, [r0, #PLL_DP_HFS_MFN]
1: ldr r1, [r0, #PLL_DP_CTL]
ands r1, r1, #0x1
beq 1b
-.endm
+
+ /* r10 saved upper lr */
+ mov pc, lr
.macro setup_pll_errata pll, freq
ldr r2, =\pll
- mov r1, #0x0
- str r1, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
+ str r4, [r2, #PLL_DP_CONFIG] /* Disable auto-restart AREN bit */
ldr r1, =0x00001236
str r1, [r2, #PLL_DP_CTL] /* Restart PLL with PLM=1 */
1: ldr r1, [r2, #PLL_DP_CTL] /* Wait for lock */
/* Gate of clocks to the peripherals first */
ldr r1, =0x3FFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
- ldr r1, =0x0
- str r1, [r0, #CLKCTL_CCGR1]
- str r1, [r0, #CLKCTL_CCGR2]
- str r1, [r0, #CLKCTL_CCGR3]
+ str r4, [r0, #CLKCTL_CCGR1]
+ str r4, [r0, #CLKCTL_CCGR2]
+ str r4, [r0, #CLKCTL_CCGR3]
ldr r1, =0x00030000
str r1, [r0, #CLKCTL_CCGR4]
#else
ldr r1, =0x3FFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
- ldr r1, =0x0
- str r1, [r0, #CLKCTL_CCGR1]
- str r1, [r0, #CLKCTL_CCGR2]
- str r1, [r0, #CLKCTL_CCGR3]
- str r1, [r0, #CLKCTL_CCGR7]
+ str r4, [r0, #CLKCTL_CCGR1]
+ str r4, [r0, #CLKCTL_CCGR2]
+ str r4, [r0, #CLKCTL_CCGR3]
+ str r4, [r0, #CLKCTL_CCGR7]
ldr r1, =0x00030000
str r1, [r0, #CLKCTL_CCGR4]
/* Switch peripheral to PLL 3 */
ldr r0, =CCM_BASE_ADDR
- ldr r1, =0x000010C0
- orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
+ ldr r1, =0x000010C0 | CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
ldr r1, =0x13239145
str r1, [r0, #CLKCTL_CBCDR]
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x19239145
str r1, [r0, #CLKCTL_CBCDR]
- ldr r1, =0x000020C0
- orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
+ ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
#endif
setup_pll PLL3_BASE_ADDR, 216
#if defined(CONFIG_MX51)
/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
- ldr r1, =0x0
- ldr r3, [r1, #ROM_SI_REV]
+ ldr r3, [r4, #ROM_SI_REV]
cmp r3, #0x10
movls r1, #0x1
movhi r1, #0
str r1, [r0, #CLKCTL_CACRR]
/* Switch ARM back to PLL 1 */
- mov r1, #0
- str r1, [r0, #CLKCTL_CCSR]
+ str r4, [r0, #CLKCTL_CCSR]
#if defined(CONFIG_MX51)
/* setup the rest */
/* Use lp_apm (24MHz) source for perclk */
- ldr r1, =0x000020C2
- orr r1,r1,#CONFIG_SYS_DDR_CLKSEL
+ ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
ldr r1, =CONFIG_SYS_CLKTL_CBCDR
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x00808145
orr r1, r1, #2 << 10
- orr r1, r1, #0 << 16
orr r1, r1, #1 << 19
str r1, [r0, #CLKCTL_CBCDR]
cmp r1, #0x0
bne 1b
- mov r1, #0x0
- str r1, [r0, #CLKCTL_CCDR]
+ str r4, [r0, #CLKCTL_CCDR]
/* for cko - for ARM div by 8 */
mov r1, #0x000A0000
strh r1, [r0]
.endm
-.section ".text.init", "x"
-
ENTRY(lowlevel_init)
+ mov r10, lr
+ mov r4, #0 /* Fix R4 to 0 */
+
#if defined(CONFIG_MX51)
ldr r0, =GPIO1_BASE_ADDR
ldr r1, [r0, #0x0]
init_clock
- /* r12 saved upper lr*/
- mov pc,lr
+ mov pc, r10
ENDPROC(lowlevel_init)
/* Board level setting value */
-W_DP_OP_864: .word DP_OP_864
-W_DP_MFD_864: .word DP_MFD_864
-W_DP_MFN_864: .word DP_MFN_864
+#if defined(CONFIG_MX51_PLL_ERRATA)
+W_DP_864: .word DP_OP_864
+ .word DP_MFD_864
+ .word DP_MFN_864
W_DP_MFN_800_DIT: .word DP_MFN_800_DIT
-W_DP_OP_800: .word DP_OP_800
-W_DP_MFD_800: .word DP_MFD_800
-W_DP_MFN_800: .word DP_MFN_800
-W_DP_OP_665: .word DP_OP_665
-W_DP_MFD_665: .word DP_MFD_665
-W_DP_MFN_665: .word DP_MFN_665
-W_DP_OP_216: .word DP_OP_216
-W_DP_MFD_216: .word DP_MFD_216
-W_DP_MFN_216: .word DP_MFN_216
+#else
+W_DP_800: .word DP_OP_800
+ .word DP_MFD_800
+ .word DP_MFN_800
+#endif
+#if defined(CONFIG_MX51)
+W_DP_665: .word DP_OP_665
+ .word DP_MFD_665
+ .word DP_MFN_665
+#endif
+W_DP_216: .word DP_OP_216
+ .word DP_MFD_216
+ .word DP_MFN_216
reg = __raw_readl(&imx_ccm->CCGR6);
if (enable)
- reg |= MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET;
+ reg |= MXC_CCM_CCGR6_USBOH3_MASK;
else
- reg &= ~(MXC_CCM_CCGR_CG_MASK << MXC_CCM_CCGR0_CG0_OFFSET);
+ reg &= ~(MXC_CCM_CCGR6_USBOH3_MASK);
__raw_writel(reg, &imx_ccm->CCGR6);
}
if (i2c_num > 2)
return -EINVAL;
- mask = MXC_CCM_CCGR_CG_MASK << ((i2c_num + 3) << 1);
+
+ mask = MXC_CCM_CCGR_CG_MASK
+ << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
reg = __raw_readl(&imx_ccm->CCGR2);
if (enable)
reg |= mask;
reg = __raw_readl(&imx_ccm->cacrr);
reg &= MXC_CCM_CACRR_ARM_PODF_MASK;
reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET;
- freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
+ freq = decode_pll(PLL_SYS, MXC_HCLK);
return freq / (reg + 1);
}
switch (reg) {
case 0:
- freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
+ freq = decode_pll(PLL_USBOTG, MXC_HCLK);
break;
case 1:
case 2:
- freq = CONFIG_SYS_MX6_HCLK;
+ freq = MXC_HCLK;
break;
default:
break;
switch (reg) {
case 0:
- freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
+ freq = decode_pll(PLL_BUS, MXC_HCLK);
break;
case 1:
freq = PLL2_PFD2_FREQ;
root_freq = get_axi_clk();
break;
case 1:
- root_freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
+ root_freq = decode_pll(PLL_USBOTG, MXC_HCLK);
break;
case 2:
root_freq = PLL2_PFD2_FREQ;
u32 imx_get_fecclk(void)
{
- return decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
+ return decode_pll(PLL_ENET, MXC_HCLK);
}
int enable_sata_clock(void)
/* Enable sata clock */
reg = readl(&imx_ccm->CCGR5); /* CCGR5 */
- reg |= MXC_CCM_CCGR5_CG2_MASK;
+ reg |= MXC_CCM_CCGR5_SATA_MASK;
writel(reg, &imx_ccm->CCGR5);
/* Enable PLLs */
case MXC_IPG_CLK:
return get_ipg_clk();
case MXC_IPG_PERCLK:
+ case MXC_I2C_CLK:
return get_ipg_per_clk();
case MXC_UART_CLK:
return get_uart_clk();
int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
u32 freq;
- freq = decode_pll(PLL_SYS, CONFIG_SYS_MX6_HCLK);
+ freq = decode_pll(PLL_SYS, MXC_HCLK);
printf("PLL_SYS %8d MHz\n", freq / 1000000);
- freq = decode_pll(PLL_BUS, CONFIG_SYS_MX6_HCLK);
+ freq = decode_pll(PLL_BUS, MXC_HCLK);
printf("PLL_BUS %8d MHz\n", freq / 1000000);
- freq = decode_pll(PLL_USBOTG, CONFIG_SYS_MX6_HCLK);
+ freq = decode_pll(PLL_USBOTG, MXC_HCLK);
printf("PLL_OTG %8d MHz\n", freq / 1000000);
- freq = decode_pll(PLL_ENET, CONFIG_SYS_MX6_HCLK);
+ freq = decode_pll(PLL_ENET, MXC_HCLK);
printf("PLL_NET %8d MHz\n", freq / 1000000);
printf("\n");
void boot_mode_apply(unsigned cfg_val)
{
unsigned reg;
- struct src_regs *psrc = (struct src_regs *)SRC_BASE_ADDR;
+ struct src *psrc = (struct src *)SRC_BASE_ADDR;
writel(cfg_val, &psrc->gpr9);
reg = readl(&psrc->gpr10);
if (cfg_val)
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
+
. = ALIGN(4);
__image_copy_end = .;
_end = .;
#
-# (C) Copyright 2000-2006
+# (C) Copyright 2010,2011 Nvidia Corporation.
+#
+# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).o
+LIB = $(obj)libtegra-common.o
-COBJS = $(BOARD).o flash.o serial.o pci.o powerspan.o
-SOBJS = init.o
+COBJS-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+COBJS := $(COBJS-y)
+SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-all: $(LIB) $(SOBJS)
+all: $(obj).depend $(LIB)
$(LIB): $(OBJS)
- $(call cmd_link_o_target, $^)
+ $(call cmd_link_o_target, $(OBJS))
#########################################################################
*/
#include <common.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/pmc.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/pmc.h>
static int do_enterrcm(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
LIB = $(obj)lib$(SOC).o
COBJS-$(CONFIG_USB_EHCI_TEGRA) += usb.o
-COBJS-$(CONFIG_CMD_ENTERRCM) += cmd_enterrcm.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
#include <common.h>
#include <asm/io.h>
#include <asm-generic/gpio.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/uart.h>
+#include <asm/arch/tegra.h>
#include <asm/arch/usb.h>
+#include <usb/ulpi.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/sys_proto.h>
+#include <asm/arch-tegra/uart.h>
#include <libfdt.h>
#include <fdtdec.h>
+#ifdef CONFIG_USB_ULPI
+ #ifndef CONFIG_USB_ULPI_VIEWPORT
+ #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \
+ define CONFIG_USB_ULPI_VIEWPORT"
+ #endif
+#endif
+
enum {
USB_PORTS_MAX = 4, /* Maximum ports we allow */
};
struct fdt_usb {
struct usb_ctlr *reg; /* address of registers in physical memory */
unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */
+ unsigned ulpi:1; /* 1 if port has external ULPI transceiver */
unsigned enabled:1; /* 1 to enable, 0 to disable */
unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
enum dr_mode dr_mode; /* dual role mode */
enum periph_id periph_id;/* peripheral id */
struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */
+ struct fdt_gpio_state phy_reset_gpio; /* GPIO to reset ULPI phy */
};
static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */
static unsigned port_count; /* Number of available ports */
-static int port_current; /* Current port (-1 = none) */
/*
* This table has USB timing parameters for each Oscillator frequency we
*/
}
-/* set up the USB controller with the parameters provided */
-static int init_usb_controller(struct fdt_usb *config,
+/* set up the UTMI USB controller with the parameters provided */
+static int init_utmi_usb_controller(struct fdt_usb *config,
struct usb_ctlr *usbctlr, const u32 timing[])
{
u32 val;
if (!loop_count)
return -1;
- return 0;
-}
+ /* Disable ICUSB FS/LS transceiver */
+ clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
+
+ /* Select UTMI parallel interface */
+ clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
+ PTS_UTMI << PTS_SHIFT);
+ clrbits_le32(&usbctlr->port_sc1, STS);
-static void power_up_port(struct usb_ctlr *usbctlr)
-{
/* Deassert power down state */
clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
+
+ return 0;
+}
+
+#ifdef CONFIG_USB_ULPI
+/* if board file does not set a ULPI reference frequency we default to 24MHz */
+#ifndef CONFIG_ULPI_REF_CLK
+#define CONFIG_ULPI_REF_CLK 24000000
+#endif
+
+/* set up the ULPI USB controller with the parameters provided */
+static int init_ulpi_usb_controller(struct fdt_usb *config,
+ struct usb_ctlr *usbctlr)
+{
+ u32 val;
+ int loop_count;
+ struct ulpi_viewport ulpi_vp;
+
+ /* set up ULPI reference clock on pllp_out4 */
+ clock_enable(PERIPH_ID_DEV2_OUT);
+ clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK);
+
+ /* reset ULPI phy */
+ if (fdt_gpio_isvalid(&config->phy_reset_gpio)) {
+ fdtdec_setup_gpio(&config->phy_reset_gpio);
+ gpio_direction_output(config->phy_reset_gpio.gpio, 0);
+ mdelay(5);
+ gpio_set_value(config->phy_reset_gpio.gpio, 1);
+ }
+
+ /* Reset the usb controller */
+ clock_enable(config->periph_id);
+ usbf_reset_controller(config, usbctlr);
+
+ /* enable pinmux bypass */
+ setbits_le32(&usbctlr->ulpi_timing_ctrl_0,
+ ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP);
+
+ /* Select ULPI parallel interface */
+ clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT);
+
+ /* enable ULPI transceiver */
+ setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
+
+ /* configure ULPI transceiver timings */
+ val = 0;
+ writel(val, &usbctlr->ulpi_timing_ctrl_1);
+
+ val |= ULPI_DATA_TRIMMER_SEL(4);
+ val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
+ val |= ULPI_DIR_TRIMMER_SEL(4);
+ writel(val, &usbctlr->ulpi_timing_ctrl_1);
+ udelay(10);
+
+ val |= ULPI_DATA_TRIMMER_LOAD;
+ val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
+ val |= ULPI_DIR_TRIMMER_LOAD;
+ writel(val, &usbctlr->ulpi_timing_ctrl_1);
+
+ /* set up phy for host operation with external vbus supply */
+ ulpi_vp.port_num = 0;
+ ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport;
+
+ if (ulpi_init(&ulpi_vp)) {
+ printf("Tegra ULPI viewport init failed\n");
+ return -1;
+ }
+
+ ulpi_set_vbus(&ulpi_vp, 1, 1);
+ ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0);
+
+ /* enable wakeup events */
+ setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC);
+
+ /* Enable and wait for the phy clock to become valid in 100 ms */
+ setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
+ for (loop_count = 100000; loop_count != 0; loop_count--) {
+ if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
+ break;
+ udelay(1);
+ }
+ if (!loop_count)
+ return -1;
+ clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
+
+ return 0;
+}
+#else
+static int init_ulpi_usb_controller(struct fdt_usb *config,
+ struct usb_ctlr *usbctlr)
+{
+ printf("No code to set up ULPI controller, please enable"
+ "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT");
+ return -1;
}
+#endif
static void config_clock(const u32 timing[])
{
struct usb_ctlr *usbctlr = config->reg;
if (port_count == USB_PORTS_MAX) {
- debug("tegrausb: Cannot register more than %d ports\n",
+ printf("tegrausb: Cannot register more than %d ports\n",
USB_PORTS_MAX);
return -1;
}
- if (init_usb_controller(config, usbctlr, timing)) {
- debug("tegrausb: Cannot init port\n");
+
+ if (config->utmi && init_utmi_usb_controller(config, usbctlr, timing)) {
+ printf("tegrausb: Cannot init port\n");
return -1;
}
- if (config->utmi) {
- /* Disable ICUSB FS/LS transceiver */
- clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
-
- /* Select UTMI parallel interface */
- clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
- PTS_UTMI << PTS_SHIFT);
- clrbits_le32(&usbctlr->port_sc1, STS);
- power_up_port(usbctlr);
+
+ if (config->ulpi && init_ulpi_usb_controller(config, usbctlr)) {
+ printf("tegrausb: Cannot init port\n");
+ return -1;
}
+
port[port_count++] = *config;
return 0;
}
-int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor)
+int tegrausb_start_port(int portnum, u32 *hccr, u32 *hcor)
{
struct usb_ctlr *usbctlr;
if (portnum >= port_count)
return -1;
- tegrausb_stop_port();
set_host_mode(&port[portnum]);
usbctlr = port[portnum].reg;
*hccr = (u32)&usbctlr->cap_length;
*hcor = (u32)&usbctlr->usb_cmd;
- port_current = portnum;
return 0;
}
-int tegrausb_stop_port(void)
+int tegrausb_stop_port(int portnum)
{
struct usb_ctlr *usbctlr;
- if (port_current == -1)
- return -1;
-
- usbctlr = port[port_current].reg;
+ usbctlr = port[portnum].reg;
/* Stop controller */
writel(0, &usbctlr->usb_cmd);
/* Initiate controller reset */
writel(2, &usbctlr->usb_cmd);
udelay(1000);
- port_current = -1;
+
return 0;
}
phy = fdt_getprop(blob, node, "phy_type", NULL);
config->utmi = phy && 0 == strcmp("utmi", phy);
+ config->ulpi = phy && 0 == strcmp("ulpi", phy);
config->enabled = fdtdec_get_is_enabled(blob, node);
config->has_legacy_mode = fdtdec_get_bool(blob, node,
"nvidia,has-legacy-mode");
return -FDT_ERR_NOTFOUND;
}
fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio);
- debug("enabled=%d, legacy_mode=%d, utmi=%d, periph_id=%d, vbus=%d, "
- "dr_mode=%d\n", config->enabled, config->has_legacy_mode,
- config->utmi, config->periph_id, config->vbus_gpio.gpio,
- config->dr_mode);
+ fdtdec_decode_gpio(blob, node, "nvidia,phy-reset-gpio",
+ &config->phy_reset_gpio);
+ debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, "
+ "vbus=%d, phy_reset=%d, dr_mode=%d\n",
+ config->enabled, config->has_legacy_mode, config->utmi,
+ config->ulpi, config->periph_id, config->vbus_gpio.gpio,
+ config->phy_reset_gpio.gpio, config->dr_mode);
return 0;
}
return -1;
set_host_mode(&config);
}
- port_current = -1;
return 0;
}
. = ALIGN(4);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
+++ /dev/null
-#
-# (C) Copyright 2002
-# Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
-
-PLATFORM_CPPFLAGS += -march=armv4
-# =========================================================================
-#
-# Supply options according to compiler version
-#
-# ========================================================================
-PF_RELFLAGS_SLB_AT := $(call cc-option,-mshort-load-bytes,$(call cc-option,-malignment-traps,))
-PLATFORM_RELFLAGS += $(PF_RELFLAGS_SLB_AT)
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * CPU specific code
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/system.h>
-
-static void cache_flush(void);
-
-int cleanup_before_linux (void)
-{
- /*
- * this function is called just before we call linux
- * it prepares the processor for linux
- *
- * we turn off caches etc ...
- */
-
- disable_interrupts ();
-
- /* turn off I/D-cache */
- icache_disable();
- dcache_disable();
-
- /* flush I/D-cache */
- cache_flush();
-
- return 0;
-}
-
-/* flush I/D-cache */
-static void cache_flush (void)
-{
- unsigned long i = 0;
-
- asm ("mcr p15, 0, %0, c7, c7, 0": :"r" (i));
-}
+++ /dev/null
-/*
- * (C) Copyright 2001-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * David Mueller, ELSOFT AG, d.mueller@elsoft.ch
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <lh7a40x.h>
-
-
-/* ------------------------------------------------------------------------- */
-/* NOTE: This describes the proper use of this file.
- *
- * CONFIG_SYS_CLK_FREQ should be defined as the input frequency of the PLL.
- *
- * get_FCLK(), get_HCLK(), get_PCLK() return the clock of
- * the specified bus in HZ.
- */
-/* ------------------------------------------------------------------------- */
-
-ulong get_PLLCLK (void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
-/* return FCLK frequency */
-ulong get_FCLK (void)
-{
- lh7a40x_csc_t* csc = LH7A40X_CSC_PTR;
- ulong maindiv1, maindiv2, prediv, ps;
-
- /*
- * from userguide 6.1.1.2
- *
- * FCLK = ((MAINDIV1 +2) * (MAINDIV2 +2) * 14.7456MHz) /
- * ((PREDIV+2) * (2^PS))
- */
- maindiv2 = (csc->clkset & CLKSET_MAINDIV2) >> 11;
- maindiv1 = (csc->clkset & CLKSET_MAINDIV1) >> 7;
- prediv = (csc->clkset & CLKSET_PREDIV) >> 2;
- ps = (csc->clkset & CLKSET_PS) >> 16;
-
- return (((maindiv2 + 2) * (maindiv1 + 2) * CONFIG_SYS_CLK_FREQ) /
- ((prediv + 2) * (1 << ps)));
-}
-
-
-/* return HCLK frequency */
-ulong get_HCLK (void)
-{
- lh7a40x_csc_t* csc = LH7A40X_CSC_PTR;
-
- return (get_FCLK () / ((csc->clkset & CLKSET_HCLKDIV) + 1));
-}
-
-/* return PCLK frequency */
-ulong get_PCLK (void)
-{
- lh7a40x_csc_t* csc = LH7A40X_CSC_PTR;
-
- return (get_HCLK () /
- (1 << (((csc->clkset & CLKSET_PCLKDIV) >> 16) + 1)));
-}
+++ /dev/null
-/*
- * armboot - Startup Code for ARM920 CPU-core
- *
- * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
- * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
- * Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <asm-offsets.h>
-#include <config.h>
-#include <version.h>
-
-/*
- *************************************************************************
- *
- * Jump vector table as in table 3.1 in [1]
- *
- *************************************************************************
- */
-
-
-.globl _start
-_start: b reset
- ldr pc, _undefined_instruction
- ldr pc, _software_interrupt
- ldr pc, _prefetch_abort
- ldr pc, _data_abort
- ldr pc, _not_used
- ldr pc, _irq
- ldr pc, _fiq
-
-_undefined_instruction: .word undefined_instruction
-_software_interrupt: .word software_interrupt
-_prefetch_abort: .word prefetch_abort
-_data_abort: .word data_abort
-_not_used: .word not_used
-_irq: .word irq
-_fiq: .word fiq
-
- .balignl 16,0xdeadbeef
-
-
-/*
- *************************************************************************
- *
- * Startup Code (reset vector)
- *
- * do important init only if we don't start from memory!
- * relocate armboot to ram
- * setup stack
- * jump to second stage
- *
- *************************************************************************
- */
-
-.globl _TEXT_BASE
-_TEXT_BASE:
- .word CONFIG_SYS_TEXT_BASE
-
-/*
- * These are defined in the board-specific linker script.
- * Subtracting _start from them lets the linker put their
- * relative position in the executable instead of leaving
- * them null.
- */
-.globl _bss_start_ofs
-_bss_start_ofs:
- .word __bss_start - _start
-
-.globl _bss_end_ofs
-_bss_end_ofs:
- .word __bss_end__ - _start
-
-.globl _end_ofs
-_end_ofs:
- .word _end - _start
-
-#ifdef CONFIG_USE_IRQ
-/* IRQ stack memory (calculated at run-time) */
-.globl IRQ_STACK_START
-IRQ_STACK_START:
- .word 0x0badc0de
-
-/* IRQ stack memory (calculated at run-time) */
-.globl FIQ_STACK_START
-FIQ_STACK_START:
- .word 0x0badc0de
-#endif
-
-/* IRQ stack memory (calculated at run-time) + 8 bytes */
-.globl IRQ_STACK_START_IN
-IRQ_STACK_START_IN:
- .word 0x0badc0de
-
-/*
- * the actual reset code
- */
-
-reset:
- /*
- * set the cpu to SVC32 mode
- */
- mrs r0,cpsr
- bic r0,r0,#0x1f
- orr r0,r0,#0xd3
- msr cpsr,r0
-
-#define pWDTCTL 0x80001400 /* Watchdog Timer control register */
-#define pINTENC 0x8000050C /* Interrupt-Controller enable clear register */
-#define pCLKSET 0x80000420 /* clock divisor register */
-
- /* disable watchdog, set watchdog control register to
- * all zeros (default reset)
- */
- ldr r0, =pWDTCTL
- mov r1, #0x0
- str r1, [r0]
-
- /*
- * mask all IRQs by setting all bits in the INTENC register (default)
- */
- mov r1, #0xffffffff
- ldr r0, =pINTENC
- str r1, [r0]
-
- /* FCLK:HCLK:PCLK = 1:2:2 */
- /* default FCLK is 200 MHz, using 14.7456 MHz fin */
- ldr r0, =pCLKSET
- ldr r1, =0x0004ee39
-@ ldr r1, =0x0005ee39 @ 1: 2: 4
- str r1, [r0]
-
- /*
- * we do sys-critical inits only at reboot,
- * not when booting from ram!
- */
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
- bl cpu_init_crit
-#endif
-
-/* Set stackpointer in internal RAM to call board_init_f */
-call_board_init_f:
- ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
- bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
- ldr r0,=0x00000000
- bl board_init_f
-
-/*------------------------------------------------------------------------------*/
-
-/*
- * void relocate_code (addr_sp, gd, addr_moni)
- *
- * This "function" does not return, instead it continues in RAM
- * after relocating the monitor code.
- *
- */
- .globl relocate_code
-relocate_code:
- mov r4, r0 /* save addr_sp */
- mov r5, r1 /* save addr of gd */
- mov r6, r2 /* save addr of destination */
-
- /* Set up the stack */
-stack_setup:
- mov sp, r4
-
- adr r0, _start
- cmp r0, r6
- moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
- beq clear_bss /* skip relocation */
- mov r1, r6 /* r1 <- scratch for copy_loop */
- ldr r3, _bss_start_ofs
- add r2, r0, r3 /* r2 <- source end address */
-
-copy_loop:
- ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r1!, {r9-r10} /* copy to target address [r1] */
- cmp r0, r2 /* until source end address [r2] */
- blo copy_loop
-
-#ifndef CONFIG_SPL_BUILD
- /*
- * fix .rel.dyn relocations
- */
- ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r6, r0 /* r9 <- relocation offset */
- ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
- add r10, r10, r0 /* r10 <- sym table in FLASH */
- ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
- add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
- ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
- add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
-fixloop:
- ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
- add r0, r0, r9 /* r0 <- location to fix up in RAM */
- ldr r1, [r2, #4]
- and r7, r1, #0xff
- cmp r7, #23 /* relative fixup? */
- beq fixrel
- cmp r7, #2 /* absolute fixup? */
- beq fixabs
- /* ignore unknown type of fixup */
- b fixnext
-fixabs:
- /* absolute fix: set location to (offset) symbol value */
- mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
- add r1, r10, r1 /* r1 <- address of symbol in table */
- ldr r1, [r1, #4] /* r1 <- symbol value */
- add r1, r1, r9 /* r1 <- relocated sym addr */
- b fixnext
-fixrel:
- /* relative fix: increase location by offset */
- ldr r1, [r0]
- add r1, r1, r9
-fixnext:
- str r1, [r0]
- add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
- cmp r2, r3
- blo fixloop
-#endif
-
-clear_bss:
-#ifndef CONFIG_SPL_BUILD
- ldr r0, _bss_start_ofs
- ldr r1, _bss_end_ofs
- mov r4, r6 /* reloc addr */
- add r0, r0, r4
- add r1, r1, r4
- mov r2, #0x00000000 /* clear */
-
-clbss_l:cmp r0, r1 /* clear loop... */
- bhs clbss_e /* if reached end of bss, exit */
- str r2, [r0]
- add r0, r0, #4
- b clbss_l
-clbss_e:
-#endif
-
-/*
- * We are done. Do not return, instead branch to second part of board
- * initialization, now running from RAM.
- */
- ldr r0, _board_init_r_ofs
- adr r1, _start
- add lr, r0, r1
- add lr, lr, r9
- /* setup parameters for board_init_r */
- mov r0, r5 /* gd_t */
- mov r1, r6 /* dest_addr */
- /* jump to it ... */
- mov pc, lr
-
-_board_init_r_ofs:
- .word board_init_r - _start
-
-_rel_dyn_start_ofs:
- .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
- .word __rel_dyn_end - _start
-_dynsym_start_ofs:
- .word __dynsym_start - _start
-
-/*
- *************************************************************************
- *
- * CPU_init_critical registers
- *
- * setup important registers
- * setup memory timing
- *
- *************************************************************************
- */
-
-
-cpu_init_crit:
- /*
- * flush v4 I/D caches
- */
- mov r0, #0
- mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
- mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
-
- /*
- * disable MMU stuff and caches
- */
- mrc p15, 0, r0, c1, c0, 0
- bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
- bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
- orr r0, r0, #0x00000002 @ set bit 2 (A) Align
- orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
- orr r0, r0, #0x40000000 @ set bit 30 (nF) notFastBus
- mcr p15, 0, r0, c1, c0, 0
-
-
- /*
- * before relocating, we have to setup RAM timing
- * because memory timing is board-dependend, you will
- * find a lowlevel_init.S in your board directory.
- */
- mov ip, lr
- bl lowlevel_init
- mov lr, ip
-
- mov pc, lr
-
-
-/*
- *************************************************************************
- *
- * Interrupt handling
- *
- *************************************************************************
- */
-
-@
-@ IRQ stack frame.
-@
-#define S_FRAME_SIZE 72
-
-#define S_OLD_R0 68
-#define S_PSR 64
-#define S_PC 60
-#define S_LR 56
-#define S_SP 52
-
-#define S_IP 48
-#define S_FP 44
-#define S_R10 40
-#define S_R9 36
-#define S_R8 32
-#define S_R7 28
-#define S_R6 24
-#define S_R5 20
-#define S_R4 16
-#define S_R3 12
-#define S_R2 8
-#define S_R1 4
-#define S_R0 0
-
-#define MODE_SVC 0x13
-#define I_BIT 0x80
-
-/*
- * use bad_save_user_regs for abort/prefetch/undef/swi ...
- * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
- */
-
- .macro bad_save_user_regs
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} @ Calling r0-r12
- ldr r2, IRQ_STACK_START_IN
- ldmia r2, {r2 - r3} @ get pc, cpsr
- add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
-
- add r5, sp, #S_SP
- mov r1, lr
- stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr
- mov r0, sp
- .endm
-
- .macro irq_save_user_regs
- sub sp, sp, #S_FRAME_SIZE
- stmia sp, {r0 - r12} @ Calling r0-r12
- add r8, sp, #S_PC
- stmdb r8, {sp, lr}^ @ Calling SP, LR
- str lr, [r8, #0] @ Save calling PC
- mrs r6, spsr
- str r6, [r8, #4] @ Save CPSR
- str r0, [r8, #8] @ Save OLD_R0
- mov r0, sp
- .endm
-
- .macro irq_restore_user_regs
- ldmia sp, {r0 - lr}^ @ Calling r0 - lr
- mov r0, r0
- ldr lr, [sp, #S_PC] @ Get PC
- add sp, sp, #S_FRAME_SIZE
- subs pc, lr, #4 @ return & move spsr_svc into cpsr
- .endm
-
- .macro get_bad_stack
- ldr r13, IRQ_STACK_START_IN @ setup our mode stack
-
- str lr, [r13] @ save caller lr / spsr
- mrs lr, spsr
- str lr, [r13, #4]
-
- mov r13, #MODE_SVC @ prepare SVC-Mode
- @ msr spsr_c, r13
- msr spsr, r13
- mov lr, pc
- movs pc, lr
- .endm
-
- .macro get_irq_stack @ setup IRQ stack
- ldr sp, IRQ_STACK_START
- .endm
-
- .macro get_fiq_stack @ setup FIQ stack
- ldr sp, FIQ_STACK_START
- .endm
-
-/*
- * exception handlers
- */
- .align 5
-undefined_instruction:
- get_bad_stack
- bad_save_user_regs
- bl do_undefined_instruction
-
- .align 5
-software_interrupt:
- get_bad_stack
- bad_save_user_regs
- bl do_software_interrupt
-
- .align 5
-prefetch_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_prefetch_abort
-
- .align 5
-data_abort:
- get_bad_stack
- bad_save_user_regs
- bl do_data_abort
-
- .align 5
-not_used:
- get_bad_stack
- bad_save_user_regs
- bl do_not_used
-
-#ifdef CONFIG_USE_IRQ
-
- .align 5
-irq:
- get_irq_stack
- irq_save_user_regs
- bl do_irq
- irq_restore_user_regs
-
- .align 5
-fiq:
- get_fiq_stack
- /* someone ought to write a more effiction fiq_save_user_regs */
- irq_save_user_regs
- bl do_fiq
- irq_restore_user_regs
-
-#else
-
- .align 5
-irq:
- get_bad_stack
- bad_save_user_regs
- bl do_irq
-
- .align 5
-fiq:
- get_bad_stack
- bad_save_user_regs
- bl do_fiq
-
-#endif
-
- .align 5
-.globl reset_cpu
-reset_cpu:
- bl disable_interrupts
-
- /* Disable watchdog */
- ldr r1, =pWDTCTL
- mov r3, #0
- str r3, [r1]
-
- /* reset counter */
- ldr r3, =0x00001984
- str r3, [r1, #4]
-
- /* Enable the watchdog */
- mov r3, #1
- str r3, [r1]
-
-_loop_forever:
- b _loop_forever
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <lh7a40x.h>
-
-static ulong timer_load_val = 0;
-
-/* macro to read the 16 bit timer */
-static inline ulong READ_TIMER(void)
-{
- lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR;
- lh7a40x_timer_t* timer = &timers->timer1;
-
- return (timer->value & 0x0000ffff);
-}
-
-static ulong timestamp;
-static ulong lastdec;
-
-int timer_init (void)
-{
- lh7a40x_timers_t* timers = LH7A40X_TIMERS_PTR;
- lh7a40x_timer_t* timer = &timers->timer1;
-
- /* a periodic timer using the 508kHz source */
- timer->control = (TIMER_PER | TIMER_CLK508K);
-
- if (timer_load_val == 0) {
- /*
- * 10ms period with 508.469kHz clock = 5084
- */
- timer_load_val = CONFIG_SYS_HZ/100;
- }
-
- /* load value for 10 ms timeout */
- lastdec = timer->load = timer_load_val;
-
- /* auto load, start timer */
- timer->control = timer->control | TIMER_EN;
- timestamp = 0;
-
- return (0);
-}
-
-/*
- * timer without interrupts
- */
-ulong get_timer (ulong base)
-{
- return (get_timer_masked() - base);
-}
-
-void __udelay (unsigned long usec)
-{
- ulong tmo,tmp;
-
- /* normalize */
- if (usec >= 1000) {
- tmo = usec / 1000;
- tmo *= CONFIG_SYS_HZ;
- tmo /= 1000;
- }
- else {
- if (usec > 1) {
- tmo = usec * CONFIG_SYS_HZ;
- tmo /= (1000*1000);
- }
- else
- tmo = 1;
- }
-
- /* check for rollover during this delay */
- tmp = get_timer (0);
- if ((tmp + tmo) < tmp )
- reset_timer_masked(); /* timer would roll over */
- else
- tmo += tmp;
-
- while (get_timer_masked () < tmo);
-}
-
-void reset_timer_masked (void)
-{
- /* reset time */
- lastdec = READ_TIMER();
- timestamp = 0;
-}
-
-ulong get_timer_masked (void)
-{
- ulong now = READ_TIMER();
-
- if (lastdec >= now) {
- /* normal mode */
- timestamp += (lastdec - now);
- } else {
- /* we have an overflow ... */
- timestamp += ((lastdec + timer_load_val) - now);
- }
- lastdec = now;
-
- return timestamp;
-}
-
-void udelay_masked (unsigned long usec)
-{
- ulong tmo;
- ulong endtime;
- signed long diff;
-
- /* normalize */
- if (usec >= 1000) {
- tmo = usec / 1000;
- tmo *= CONFIG_SYS_HZ;
- tmo /= 1000;
- } else {
- if (usec > 1) {
- tmo = usec * CONFIG_SYS_HZ;
- tmo /= (1000*1000);
- } else {
- tmo = 1;
- }
- }
-
- endtime = get_timer_masked () + tmo;
-
- do {
- ulong now = get_timer_masked ();
- diff = endtime - now;
- } while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
- return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
- ulong tbclk;
-
- tbclk = timer_load_val * 100;
-
- return tbclk;
-}
#include <errno.h>
#include <linux/compiler.h>
-#define CPU_MASK_PXA_REVID 0x00f
+#define CPU_MASK_PXA_PRODID 0x000003f0
+#define CPU_MASK_PXA_REVID 0x0000000f
+
+#define CPU_MASK_PRODREV (CPU_MASK_PXA_PRODID | CPU_MASK_PXA_REVID)
-#define CPU_MASK_PXA_PRODID 0x3f0
#define CPU_VALUE_PXA25X 0x100
#define CPU_VALUE_PXA27X 0x110
return id == CPU_VALUE_PXA27X;
}
+uint32_t pxa_get_cpu_revision(void)
+{
+ return pxa_get_cpuid() & CPU_MASK_PRODREV;
+}
+
#ifdef CONFIG_DISPLAY_CPUINFO
static const char *pxa25x_get_revision(void)
{
#
-# (C) Copyright 2004-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2010,2011 Nvidia Corporation.
#
-# (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
-# Added support for Wind River SBC8560 board
+# (C) Copyright 2000-2008
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).o
+LIB = $(obj)libcputegra-common.o
-COBJS-y += $(BOARD).o
-COBJS-y += law.o
-COBJS-y += tlb.o
-COBJS-$(CONFIG_FSL_DDR1) += ddr.o
+SOBJS += lowlevel_init.o
+COBJS-y += ap.o board.o sys_info.o timer.o
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS-y))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
+$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
+#include <common.h>
#include <asm/io.h>
-#include <asm/arch/ap20.h>
-#include <asm/arch/fuse.h>
#include <asm/arch/gp_padctrl.h>
-#include <asm/arch/pmc.h>
-#include <asm/arch/scu.h>
-#include <asm/arch/warmboot.h>
-#include <common.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/fuse.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/scu.h>
+#include <asm/arch-tegra/warmboot.h>
int tegra_get_chip_type(void)
{
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
-#include <asm/arch/pmc.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/warmboot.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/board.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/sys_proto.h>
+#include <asm/arch-tegra/warmboot.h>
DECLARE_GLOBAL_DATA_PTR;
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/timer.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/timer.h>
DECLARE_GLOBAL_DATA_PTR;
LIB = $(obj)lib$(SOC)-common.o
-SOBJS += lowlevel_init.o
-COBJS-y += ap20.o board.o clock.o funcmux.o pinmux.o sys_info.o timer.o
+COBJS-y += clock.o funcmux.o pinmux.o
COBJS-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o
COBJS-$(CONFIG_TEGRA_CLOCK_SCALING) += emc.o
COBJS-$(CONFIG_TEGRA_PMU) += pmu.o
/* Tegra20 Clock control functions */
+#include <common.h>
#include <asm/io.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
-#include <asm/arch/timer.h>
-#include <asm/arch/tegra20.h>
-#include <common.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/timer.h>
#include <div64.h>
#include <fdtdec.h>
NONE(CRAM2),
};
+/* number of clock outputs of a PLL */
+static const u8 pll_num_clkouts[] = {
+ 1, /* PLLC */
+ 1, /* PLLM */
+ 4, /* PLLP */
+ 1, /* PLLA */
+ 0, /* PLLU */
+ 0, /* PLLD */
+};
+
/*
* Get the oscillator frequency, from the corresponding hardware configuration
* field.
case PERIPH_ID_RESERVED81:
case PERIPH_ID_RESERVED82:
case PERIPH_ID_RESERVED83:
+ case PERIPH_ID_RESERVED91:
printf("Peripheral id %d is reserved\n", id);
break;
default:
(readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT);
}
+int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
+{
+ struct clk_pll *pll = get_pll(clkid);
+ int data = 0, div = 0, offset = 0;
+
+ if (!clock_id_is_pll(clkid))
+ return -1;
+
+ if (pllout + 1 > pll_num_clkouts[clkid])
+ return -1;
+
+ div = clk_get_divider(8, pll_rate[clkid], rate);
+
+ if (div < 0)
+ return -1;
+
+ /* out2 and out4 are in the high part of the register */
+ if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
+ offset = 16;
+
+ data = (div << PLL_OUT_RATIO_SHIFT) |
+ PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
+ clrsetbits_le32(&pll->pll_out[pllout >> 1],
+ PLL_OUT_RATIO_MASK << offset, data << offset);
+
+ return 0;
+}
+
/**
* Find the best available 7.1 format divisor given a parent clock rate and
* required child clock rate. This function assumes that a second-stage
#include <common.h>
#include <fdtdec.h>
#include <asm/io.h>
-#include <asm/arch/ap20.h>
+#include <asm/arch-tegra/ap.h>
#include <asm/arch/apb_misc.h>
#include <asm/arch/clock.h>
#include <asm/arch/emc.h>
-#include <asm/arch/tegra20.h>
+#include <asm/arch/tegra.h>
/*
* The EMC registers have shadow registers. When the EMC clock is updated
break;
case PERIPH_ID_NDFLASH:
- if (config == FUNCMUX_NDFLASH_ATC) {
+ switch (config) {
+ case FUNCMUX_NDFLASH_ATC:
pinmux_set_func(PINGRP_ATC, PMUX_FUNC_NAND);
pinmux_tristate_disable(PINGRP_ATC);
+ break;
+ case FUNCMUX_NDFLASH_KBC_8_BIT:
+ pinmux_set_func(PINGRP_KBCA, PMUX_FUNC_NAND);
+ pinmux_set_func(PINGRP_KBCC, PMUX_FUNC_NAND);
+ pinmux_set_func(PINGRP_KBCD, PMUX_FUNC_NAND);
+ pinmux_set_func(PINGRP_KBCE, PMUX_FUNC_NAND);
+ pinmux_set_func(PINGRP_KBCF, PMUX_FUNC_NAND);
+
+ pinmux_tristate_disable(PINGRP_KBCA);
+ pinmux_tristate_disable(PINGRP_KBCC);
+ pinmux_tristate_disable(PINGRP_KBCD);
+ pinmux_tristate_disable(PINGRP_KBCE);
+ pinmux_tristate_disable(PINGRP_KBCF);
+
+ bad_config = 0;
+ break;
}
break;
/* Tegra20 pin multiplexing functions */
+#include <common.h>
#include <asm/io.h>
-#include <asm/arch/tegra20.h>
+#include <asm/arch/tegra.h>
#include <asm/arch/pinmux.h>
-#include <common.h>
/*
#include <common.h>
#include <tps6586x.h>
#include <asm/io.h>
-#include <asm/arch/ap20.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/tegra_i2c.h>
-#include <asm/arch/sys_proto.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/tegra_i2c.h>
+#include <asm/arch-tegra/sys_proto.h>
#define VDD_CORE_NOMINAL_T25 0x17 /* 1.3v */
#define VDD_CPU_NOMINAL_T25 0x10 /* 1.125v */
#include <common.h>
#include <asm/io.h>
#include <asm/errno.h>
-#include <asm/arch/ap20.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
-#include <asm/arch/pmc.h>
-#include <asm/arch/pinmux.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/fuse.h>
#include <asm/arch/emc.h>
#include <asm/arch/gp_padctrl.h>
-#include <asm/arch/warmboot.h>
+#include <asm/arch/pinmux.h>
#include <asm/arch/sdram_param.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/fuse.h>
+#include <asm/arch-tegra/warmboot.h>
DECLARE_GLOBAL_DATA_PTR;
/* Populate the header. */
dst_header->length_insecure = length + sizeof(struct wb_header);
dst_header->length_secure = length + sizeof(struct wb_header);
- dst_header->destination = AP20_WB_RUN_ADDRESS;
- dst_header->entry_point = AP20_WB_RUN_ADDRESS;
+ dst_header->destination = NV_WB_RUN_ADDRESS;
+ dst_header->entry_point = NV_WB_RUN_ADDRESS;
dst_header->code_length = length;
if (is_encrypted) {
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/ap20.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/flow.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/pmc.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/warmboot.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/warmboot.h>
#include "warmboot_avp.h"
#define DEBUG_RESET_CORESIGHT
/* no input, no clobber list */
);
- if (reg != AP20_WB_RUN_ADDRESS)
+ if (reg != NV_WB_RUN_ADDRESS)
goto do_reset;
/* Are we running with AVP? */
reg = PLLM_OUT1_RSTN_RESET_DISABLE | PLLM_OUT1_CLKEN_ENABLE |
PLLM_OUT1_RATIO_VAL_8;
- writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out);
+ writel(reg, &clkrst->crc_pll[CLOCK_ID_MEMORY].pll_out[0]);
reg = SCLK_SWAKE_FIQ_SRC_PLLM_OUT1 | SCLK_SWAKE_IRQ_SRC_PLLM_OUT1 |
SCLK_SWAKE_RUN_SRC_PLLM_OUT1 | SCLK_SWAKE_IDLE_SRC_PLLM_OUT1 |
. = ALIGN(4);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
#include <asm/io.h>
#include <asm/imx-common/boot_mode.h>
#include <malloc.h>
+#include <command.h>
static const struct boot_mode *modes[2];
int size;
char *dest;
- if (__u_boot_cmd_bmode.usage) {
- free(__u_boot_cmd_bmode.usage);
- __u_boot_cmd_bmode.usage = NULL;
+ cmd_tbl_t *entry = ll_entry_get(cmd_tbl_t, bmode, cmd);
+
+ if (entry->usage) {
+ free(entry->usage);
+ entry->usage = NULL;
}
modes[0] = p;
dest = malloc(size);
if (dest) {
create_usage(dest);
- __u_boot_cmd_bmode.usage = dest;
+ entry->usage = dest;
}
}
{
#ifdef CONFIG_FSL_ESDHC
#ifdef CONFIG_FSL_USDHC
+#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
+ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
+ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
+ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
+#else
gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#endif
+#else
+#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
+ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
+ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
+#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
+ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
#else
- gd->sdhc_clk = mxc_get_clock(MXC_IPG_PERCLK);
+ gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#endif
#endif
#endif
return 0;
#include <asm/io.h>
#include <div64.h>
#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
/* General purpose timers registers */
struct mxc_gpt {
#define GPTCR_FRR (1 << 9) /* Freerun / restart */
#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */
#define GPTCR_TEN 1 /* Timer enable */
-#define CLK_32KHZ 32768 /* 32Khz input */
DECLARE_GLOBAL_DATA_PTR;
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
- do_div(tick, CLK_32KHZ);
+ do_div(tick, MXC_CLK32);
return tick;
}
static inline unsigned long long us_to_tick(unsigned long long usec)
{
- usec = usec * CLK_32KHZ + 999999;
+ usec = usec * MXC_CLK32 + 999999;
do_div(usec, 1000000);
return usec;
__raw_writel(i | GPTCR_CLKSOURCE_32 | GPTCR_TEN, &cur_gpt->control);
val = __raw_readl(&cur_gpt->counter);
- lastinc = val / (CLK_32KHZ / CONFIG_SYS_HZ);
+ lastinc = val / (MXC_CLK32 / CONFIG_SYS_HZ);
timestamp = 0;
return 0;
{
/*
* get_ticks() returns a long long (64 bit), it wraps in
- * 2^64 / CONFIG_MX25_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
+ * 2^64 / MXC_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~
* 5 * 10^9 days... and get_ticks() * CONFIG_SYS_HZ wraps in
* 5 * 10^6 days - long enough.
*/
*/
ulong get_tbclk(void)
{
- return CLK_32KHZ;
+ return MXC_CLK32;
}
#endif
enum mxc_clock {
+ /* PER clocks (do not change order) */
MXC_CSI_CLK,
MXC_EPIT_CLK,
MXC_ESAI_CLK,
MXC_SSI1_CLK,
MXC_SSI2_CLK,
MXC_UART_CLK,
+ /* Other clocks */
MXC_ARM_CLK,
+ MXC_AHB_CLK,
+ MXC_IPG_CLK,
+ MXC_CSPI_CLK,
MXC_FEC_CLK,
MXC_CLK_NUM
};
-ulong imx_get_perclk(int clk);
-ulong imx_get_ahbclk(void);
-
-#define imx_get_uartclk() imx_get_perclk(15)
-#define imx_get_fecclk() (imx_get_ahbclk()/2)
-
unsigned int mxc_get_clock(enum mxc_clock clk);
+#define imx_get_uartclk() mxc_get_clock(MXC_UART_CLK)
+#define imx_get_fecclk() mxc_get_clock(MXC_FEC_CLK)
+
#endif /* __ASM_ARCH_CLOCK_H */
#define CHIP_REV_1_0 0x10
#define CHIP_REV_1_1 0x11
+#define CHIP_REV_1_2 0x12
#endif /* _IMX_REGS_H */
#include <asm/arch/imx-regs.h>
#include <generated/asm-offsets.h>
+#include <asm/macro.h>
-.macro init_aips
- write32 IMX_AIPS1_BASE + AIPS_MPR_0_7, 0x77777777
- write32 IMX_AIPS1_BASE + AIPS_MPR_8_15, 0x77777777
- write32 IMX_AIPS2_BASE + AIPS_MPR_0_7, 0x77777777
- write32 IMX_AIPS2_BASE + AIPS_MPR_8_15, 0x77777777
+/*
+ * AIPS setup - Only setup MPROTx registers.
+ * The PACR default values are good.
+ *
+ * Default argument values:
+ * - MPR: Set all MPROTx to be non-bufferable, trusted for R/W, not forced to
+ * user-mode.
+ */
+.macro init_aips mpr=0x77777777
+ ldr r0, =IMX_AIPS1_BASE
+ ldr r1, =\mpr
+ str r1, [r0, #AIPS_MPR_0_7]
+ str r1, [r0, #AIPS_MPR_8_15]
+ ldr r2, =IMX_AIPS2_BASE
+ str r1, [r2, #AIPS_MPR_0_7]
+ str r1, [r2, #AIPS_MPR_8_15]
.endm
-.macro init_max
- write32 IMX_MAX_BASE + MAX_MPR0, 0x43210
- write32 IMX_MAX_BASE + MAX_MPR1, 0x43210
- write32 IMX_MAX_BASE + MAX_MPR2, 0x43210
- write32 IMX_MAX_BASE + MAX_MPR3, 0x43210
- write32 IMX_MAX_BASE + MAX_MPR4, 0x43210
-
- write32 IMX_MAX_BASE + MAX_SGPCR0, 0x10
- write32 IMX_MAX_BASE + MAX_SGPCR1, 0x10
- write32 IMX_MAX_BASE + MAX_SGPCR2, 0x10
- write32 IMX_MAX_BASE + MAX_SGPCR3, 0x10
- write32 IMX_MAX_BASE + MAX_SGPCR4, 0x10
+/*
+ * MAX (Multi-Layer AHB Crossbar Switch) setup
+ *
+ * Default argument values:
+ * - MPR: priority is IAHB > DAHB > USBOTG > RTIC > eSDHC2/SDMA
+ * - SGPCR: always park on last master
+ * - MGPCR: restore default values
+ */
+.macro init_max mpr=0x00043210, sgpcr=0x00000010, mgpcr=0x00000000
+ ldr r0, =IMX_MAX_BASE
+ ldr r1, =\mpr
+ str r1, [r0, #MAX_MPR0] /* for S0 */
+ str r1, [r0, #MAX_MPR1] /* for S1 */
+ str r1, [r0, #MAX_MPR2] /* for S2 */
+ str r1, [r0, #MAX_MPR3] /* for S3 */
+ str r1, [r0, #MAX_MPR4] /* for S4 */
+ ldr r1, =\sgpcr
+ str r1, [r0, #MAX_SGPCR0] /* for S0 */
+ str r1, [r0, #MAX_SGPCR1] /* for S1 */
+ str r1, [r0, #MAX_SGPCR2] /* for S2 */
+ str r1, [r0, #MAX_SGPCR3] /* for S3 */
+ str r1, [r0, #MAX_SGPCR4] /* for S4 */
+ ldr r1, =\mgpcr
+ str r1, [r0, #MAX_MGPCR0] /* for M0 */
+ str r1, [r0, #MAX_MGPCR1] /* for M1 */
+ str r1, [r0, #MAX_MGPCR2] /* for M2 */
+ str r1, [r0, #MAX_MGPCR3] /* for M3 */
+ str r1, [r0, #MAX_MGPCR4] /* for M4 */
+.endm
- write32 IMX_MAX_BASE + MAX_MGPCR0, 0x0
- write32 IMX_MAX_BASE + MAX_MGPCR1, 0x0
- write32 IMX_MAX_BASE + MAX_MGPCR2, 0x0
- write32 IMX_MAX_BASE + MAX_MGPCR3, 0x0
- write32 IMX_MAX_BASE + MAX_MGPCR4, 0x0
+/*
+ * M3IF setup
+ *
+ * Default argument values:
+ * - CTL:
+ * MRRP[0] = LCDC on priority list (1 << 0) = 0x00000001
+ * MRRP[1] = MAX1 not on priority list (0 << 1) = 0x00000000
+ * MRRP[2] = MAX0 not on priority list (0 << 2) = 0x00000000
+ * MRRP[3] = USBH not on priority list (0 << 3) = 0x00000000
+ * MRRP[4] = SDMA not on priority list (0 << 4) = 0x00000000
+ * MRRP[5] = eSDHC1/ATA/FEC not on priority list (0 << 5) = 0x00000000
+ * MRRP[6] = LCDC/SLCDC/MAX2 not on priority list (0 << 6) = 0x00000000
+ * MRRP[7] = CSI not on priority list (0 << 7) = 0x00000000
+ * ------------
+ * 0x00000001
+ */
+.macro init_m3if ctl=0x00000001
+ /* M3IF Control Register (M3IFCTL) */
+ write32 IMX_M3IF_CTRL_BASE, \ctl
.endm
#endif /* __ASSEMBLY__ */
MXC_UART_CLK,
MXC_IPU_CLK,
MXC_ESDHC_CLK,
+ MXC_I2C_CLK,
};
unsigned int mxc_get_clock(enum mxc_clock clk);
#define MX31_IIM_BASE_ADDR 0x5001C000
-#define PDR0_CSI_PODF(x) (((x) & 0x1ff) << 23)
+#define PDR0_CSI_PODF(x) (((x) & 0x3f) << 26)
+#define PDR0_CSI_PRDF(x) (((x) & 0x7) << 23)
#define PDR0_PER_PODF(x) (((x) & 0x1f) << 16)
#define PDR0_HSP_PODF(x) (((x) & 0x7) << 11)
#define PDR0_NFC_PODF(x) (((x) & 0x7) << 8)
#define PDR0_MAX_PODF(x) (((x) & 0x7) << 3)
#define PDR0_MCU_PODF(x) ((x) & 0x7)
+#define PDR1_USB_PRDF(x) (((x) & 0x3) << 30)
+#define PDR1_USB_PODF(x) (((x) & 0x7) << 27)
+#define PDR1_FIRI_PRDF(x) (((x) & 0x7) << 24)
+#define PDR1_FIRI_PODF(x) (((x) & 0x3f) << 18)
+#define PDR1_SSI2_PRDF(x) (((x) & 0x7) << 15)
+#define PDR1_SSI2_PODF(x) (((x) & 0x3f) << 9)
+#define PDR1_SSI1_PRDF(x) (((x) & 0x7) << 6)
+#define PDR1_SSI1_PODF(x) ((x) & 0x3f)
+
+#define PLL_BRMO(x) (((x) & 0x1) << 31)
#define PLL_PD(x) (((x) & 0xf) << 26)
#define PLL_MFD(x) (((x) & 0x3ff) << 16)
#define PLL_MFI(x) (((x) & 0xf) << 10)
#define PLL_MFN(x) (((x) & 0x3ff) << 0)
-#define GET_PDR0_CSI_PODF(x) (((x) >> 23) & 0x1ff)
+#define GET_PDR0_CSI_PODF(x) (((x) >> 26) & 0x3f)
+#define GET_PDR0_CSI_PRDF(x) (((x) >> 23) & 0x7)
#define GET_PDR0_PER_PODF(x) (((x) >> 16) & 0x1f)
#define GET_PDR0_HSP_PODF(x) (((x) >> 11) & 0x7)
#define GET_PDR0_NFC_PODF(x) (((x) >> 8) & 0x7)
MXC_USB_CLK,
MXC_CSPI_CLK,
MXC_FEC_CLK,
+ MXC_I2C_CLK,
};
enum mxc_main_clock {
#define ESDC_MISC_DDR_EN (1 << 8)
#define ESDC_MISC_DDR2_EN (1 << 9)
+/* Multi-Layer AHB Crossbar Switch (MAX) registers */
+struct max_regs {
+ u32 mpr0;
+ u32 pad00[3];
+ u32 sgpcr0;
+ u32 pad01[59];
+ u32 mpr1;
+ u32 pad02[3];
+ u32 sgpcr1;
+ u32 pad03[59];
+ u32 mpr2;
+ u32 pad04[3];
+ u32 sgpcr2;
+ u32 pad05[59];
+ u32 mpr3;
+ u32 pad06[3];
+ u32 sgpcr3;
+ u32 pad07[59];
+ u32 mpr4;
+ u32 pad08[3];
+ u32 sgpcr4;
+ u32 pad09[251];
+ u32 mgpcr0;
+ u32 pad10[63];
+ u32 mgpcr1;
+ u32 pad11[63];
+ u32 mgpcr2;
+ u32 pad12[63];
+ u32 mgpcr3;
+ u32 pad13[63];
+ u32 mgpcr4;
+ u32 pad14[63];
+ u32 mgpcr5;
+};
+
+/* AHB <-> IP-Bus Interface (AIPS) */
+struct aips_regs {
+ u32 mpr_0_7;
+ u32 mpr_8_15;
+ u32 pad0[6];
+ u32 pacr_0_7;
+ u32 pacr_8_15;
+ u32 pacr_16_23;
+ u32 pacr_24_31;
+ u32 pad1[4];
+ u32 opacr_0_7;
+ u32 opacr_8_15;
+ u32 opacr_16_23;
+ u32 opacr_24_31;
+ u32 opacr_32_39;
+};
+
/*
* NFMS bit in RCSR register for pagesize of nandflash
*/
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
+#include <common.h>
+
+#ifdef CONFIG_SYS_MX5_HCLK
+#define MXC_HCLK CONFIG_SYS_MX5_HCLK
+#else
+#define MXC_HCLK 24000000
+#endif
+
+#ifdef CONFIG_SYS_MX5_CLK32
+#define MXC_CLK32 CONFIG_SYS_MX5_CLK32
+#else
+#define MXC_CLK32 32768
+#endif
+
enum mxc_clock {
MXC_ARM_CLK = 0,
MXC_AHB_CLK,
MXC_IPG_PERCLK,
MXC_UART_CLK,
MXC_CSPI_CLK,
+ MXC_ESDHC_CLK,
+ MXC_ESDHC2_CLK,
+ MXC_ESDHC3_CLK,
+ MXC_ESDHC4_CLK,
MXC_FEC_CLK,
MXC_SATA_CLK,
MXC_DDR_CLK,
MXC_NFC_CLK,
MXC_PERIPH_CLK,
+ MXC_I2C_CLK,
};
u32 imx_get_uartclk(void);
u32 imx_get_fecclk(void);
unsigned int mxc_get_clock(enum mxc_clock clk);
int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
-void set_usb_phy2_clk(void);
+void set_usb_phy_clk(void);
+void enable_usb_phy1_clk(unsigned char enable);
void enable_usb_phy2_clk(unsigned char enable);
void set_usboh3_clk(void);
void enable_usboh3_clk(unsigned char enable);
u32 cmeor;
};
+/* Define the bits in register CCR */
+#define MXC_CCM_CCR_COSC_EN (0x1 << 12)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCR_FPM_MULT (0x1 << 11)
+#endif
+#define MXC_CCM_CCR_CAMP2_EN (0x1 << 10)
+#define MXC_CCM_CCR_CAMP1_EN (0x1 << 9)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCR_FPM_EN (0x1 << 8)
+#endif
+#define MXC_CCM_CCR_OSCNT_OFFSET 0
+#define MXC_CCM_CCR_OSCNT_MASK 0xFF
+#define MXC_CCM_CCR_OSCNT(v) ((v) & 0xFF)
+#define MXC_CCM_CCR_OSCNT_RD(r) ((r) & 0xFF)
+
+/* Define the bits in register CCSR */
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCSR_LP_APM (0x1 << 9)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCSR_LP_APM (0x1 << 10)
+#define MXC_CCM_CCSR_PLL4_SW_CLK_SEL (0x1 << 9)
+#endif
+#define MXC_CCM_CCSR_STEP_SEL_OFFSET 7
+#define MXC_CCM_CCSR_STEP_SEL_MASK (0x3 << 7)
+#define MXC_CCM_CCSR_STEP_SEL(v) (((v) & 0x3) << 7)
+#define MXC_CCM_CCSR_STEP_SEL_RD(r) (((r) >> 7) & 0x3)
+#define MXC_CCM_CCSR_PLL2_DIV_PODF_OFFSET 5
+#define MXC_CCM_CCSR_PLL2_DIV_PODF_MASK (0x3 << 5)
+#define MXC_CCM_CCSR_PLL2_DIV_PODF(v) (((v) & 0x3) << 5)
+#define MXC_CCM_CCSR_PLL2_DIV_PODF_RD(r) (((r) >> 5) & 0x3)
+#define MXC_CCM_CCSR_PLL3_DIV_PODF_OFFSET 3
+#define MXC_CCM_CCSR_PLL3_DIV_PODF_MASK (0x3 << 3)
+#define MXC_CCM_CCSR_PLL3_DIV_PODF(v) (((v) & 0x3) << 3)
+#define MXC_CCM_CCSR_PLL3_DIV_PODF_RD(r) (((r) >> 3) & 0x3)
+#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (0x1 << 2)
+#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (0x1 << 1)
+#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL 0x1
+
/* Define the bits in register CACRR */
#define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
+#define MXC_CCM_CACRR_ARM_PODF(v) ((v) & 0x7)
+#define MXC_CCM_CACRR_ARM_PODF_RD(r) ((r) & 0x7)
/* Define the bits in register CBCDR */
#define MXC_CCM_CBCDR_DDR_HIFREQ_SEL (0x1 << 30)
-#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
#define MXC_CCM_CBCDR_DDR_PODF_OFFSET 27
+#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27)
+#define MXC_CCM_CBCDR_DDR_PODF(v) (((v) & 0x7) << 27)
+#define MXC_CCM_CBCDR_DDR_PODF_RD(r) (((r) >> 27) & 0x7)
#define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26)
#define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25)
#define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22
#define MXC_CCM_CBCDR_EMI_PODF_MASK (0x7 << 22)
+#define MXC_CCM_CBCDR_EMI_PODF(v) (((v) & 0x7) << 22)
+#define MXC_CCM_CBCDR_EMI_PODF_RD(r) (((r) >> 22) & 0x7)
#define MXC_CCM_CBCDR_AXI_B_PODF_OFFSET 19
#define MXC_CCM_CBCDR_AXI_B_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CBCDR_AXI_B_PODF(v) (((v) & 0x7) << 19)
+#define MXC_CCM_CBCDR_AXI_B_PODF_RD(r) (((r) >> 19) & 0x7)
#define MXC_CCM_CBCDR_AXI_A_PODF_OFFSET 16
#define MXC_CCM_CBCDR_AXI_A_PODF_MASK (0x7 << 16)
+#define MXC_CCM_CBCDR_AXI_A_PODF(v) (((v) & 0x7) << 16)
+#define MXC_CCM_CBCDR_AXI_A_PODF_RD(r) (((r) >> 16) & 0x7)
#define MXC_CCM_CBCDR_NFC_PODF_OFFSET 13
#define MXC_CCM_CBCDR_NFC_PODF_MASK (0x7 << 13)
+#define MXC_CCM_CBCDR_NFC_PODF(v) (((v) & 0x7) << 13)
+#define MXC_CCM_CBCDR_NFC_PODF_RD(r) (((r) >> 13) & 0x7)
#define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
+#define MXC_CCM_CBCDR_AHB_PODF(v) (((v) & 0x7) << 10)
+#define MXC_CCM_CBCDR_AHB_PODF_RD(r) (((r) >> 10) & 0x7)
#define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
+#define MXC_CCM_CBCDR_IPG_PODF(v) (((v) & 0x3) << 8)
+#define MXC_CCM_CBCDR_IPG_PODF_RD(r) (((r) >> 8) & 0x3)
#define MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET 6
#define MXC_CCM_CBCDR_PERCLK_PRED1_MASK (0x3 << 6)
+#define MXC_CCM_CBCDR_PERCLK_PRED1(v) (((v) & 0x3) << 6)
+#define MXC_CCM_CBCDR_PERCLK_PRED1_RD(r) (((r) >> 6) & 0x3)
#define MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET 3
#define MXC_CCM_CBCDR_PERCLK_PRED2_MASK (0x7 << 3)
+#define MXC_CCM_CBCDR_PERCLK_PRED2(v) (((v) & 0x7) << 3)
+#define MXC_CCM_CBCDR_PERCLK_PRED2_RD(r) (((r) >> 3) & 0x7)
#define MXC_CCM_CBCDR_PERCLK_PODF_OFFSET 0
#define MXC_CCM_CBCDR_PERCLK_PODF_MASK 0x7
+#define MXC_CCM_CBCDR_PERCLK_PODF(v) ((v) & 0x7)
+#define MXC_CCM_CBCDR_PERCLK_PODF_RD(r) ((r) & 0x7)
/* Define the bits in register CSCMR1 */
#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_OFFSET 30
#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_MASK (0x3 << 30)
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL(v) (((v) & 0x3) << 30)
+#define MXC_CCM_CSCMR1_SSI_EXT2_CLK_SEL_RD(r) (((r) >> 30) & 0x3)
#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_OFFSET 28
#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_MASK (0x3 << 28)
-#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET 26
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL(v) (((v) & 0x3) << 28)
+#define MXC_CCM_CSCMR1_SSI_EXT1_CLK_SEL_RD(r) (((r) >> 28) & 0x3)
#define MXC_CCM_CSCMR1_USB_PHY_CLK_SEL (0x1 << 26)
#define MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET 24
#define MXC_CCM_CSCMR1_UART_CLK_SEL_MASK (0x3 << 24)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL(v) (((v) & 0x3) << 24)
+#define MXC_CCM_CSCMR1_UART_CLK_SEL_RD(r) (((r) >> 24) & 0x3)
#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_OFFSET 22
#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_MASK (0x3 << 22)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL(v) (((v) & 0x3) << 22)
+#define MXC_CCM_CSCMR1_USBOH3_CLK_SEL_RD(r) (((r) >> 22) & 0x3)
#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_OFFSET 20
#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_MASK (0x3 << 20)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL(v) (((v) & 0x3) << 20)
+#define MXC_CCM_CSCMR1_ESDHC1_MSHC1_CLK_SEL_RD(r) (((r) >> 20) & 0x3)
#define MXC_CCM_CSCMR1_ESDHC3_CLK_SEL (0x1 << 19)
#define MXC_CCM_CSCMR1_ESDHC4_CLK_SEL (0x1 << 18)
#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_OFFSET 16
#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_MASK (0x3 << 16)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL(v) (((v) & 0x3) << 16)
+#define MXC_CCM_CSCMR1_ESDHC2_MSHC2_CLK_SEL_RD(r) (((r) >> 16) & 0x3)
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 14
#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL(v) (((v) & 0x3) << 14)
+#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_RD(r) (((r) >> 14) & 0x3)
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL(v) (((v) & 0x3) << 12)
+#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_RD(r) (((r) >> 12) & 0x3)
#define MXC_CCM_CSCMR1_SSI3_CLK_SEL (0x1 << 11)
#define MXC_CCM_CSCMR1_VPU_RCLK_SEL (0x1 << 10)
#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_OFFSET 8
#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_MASK (0x3 << 8)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL(v) (((v) & 0x3) << 8)
+#define MXC_CCM_CSCMR1_SSI_APM_CLK_SEL_RD(r) (((r) >> 8) & 0x3)
#define MXC_CCM_CSCMR1_TVE_CLK_SEL (0x1 << 7)
#define MXC_CCM_CSCMR1_TVE_EXT_CLK_SEL (0x1 << 6)
#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET 4
#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK (0x3 << 4)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL(v) (((v) & 0x3) << 4)
+#define MXC_CCM_CSCMR1_CSPI_CLK_SEL_RD(r) (((r) >> 4) & 0x3)
#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_OFFSET 2
#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_MASK (0x3 << 2)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL(v) (((v) & 0x3) << 2)
+#define MXC_CCM_CSCMR1_SPDIF_CLK_SEL_RD(r) (((r) >> 2) & 0x3)
#define MXC_CCM_CSCMR1_SSI_EXT2_COM_CLK_SEL (0x1 << 1)
#define MXC_CCM_CSCMR1_SSI_EXT1_COM_CLK_SEL 0x1
/* Define the bits in register CSCDR2 */
#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET 25
#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK (0x7 << 25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED(v) (((v) & 0x7) << 25)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PRED_RD(r) (((r) >> 25) & 0x7)
#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET 19
#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK (0x3F << 19)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF(v) (((v) & 0x3F) << 19)
+#define MXC_CCM_CSCDR2_CSPI_CLK_PODF_RD(r) (((r) >> 19) & 0x3F)
#define MXC_CCM_CSCDR2_SIM_CLK_PRED_OFFSET 16
#define MXC_CCM_CSCDR2_SIM_CLK_PRED_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED(v) (((v) & 0x7) << 16)
+#define MXC_CCM_CSCDR2_SIM_CLK_PRED_RD(r) (((r) >> 16) & 0x7)
#define MXC_CCM_CSCDR2_SIM_CLK_PODF_OFFSET 9
#define MXC_CCM_CSCDR2_SIM_CLK_PODF_MASK (0x3F << 9)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF(v) (((v) & 0x3F) << 9)
+#define MXC_CCM_CSCDR2_SIM_CLK_PODF_RD(r) (((r) >> 9) & 0x3F)
#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_OFFSET 6
-#define MXC_CCM_CSCDR2_SLIMBUS_PRED_MASK (0x7 << 6)
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_OFFSET 0
-#define MXC_CCM_CSCDR2_SLIMBUS_PODF_MASK 0x3F
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_MASK (0x7 << 6)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED(v) (((v) & 0x7) << 6)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PRED_RD(r) (((r) >> 6) & 0x7)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_OFFSET 0
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_MASK 0x3F
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF(v) ((v) & 0x3F)
+#define MXC_CCM_CSCDR2_SLIMBUS_CLK_PODF_RD(r) ((r) & 0x3F)
/* Define the bits in register CBCMR */
#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL(v) (((v) & 0x3) << 14)
+#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_RD(r) (((r) >> 14) & 0x3)
#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET 12
#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK (0x3 << 12)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL(v) (((v) & 0x3) << 12)
+#define MXC_CCM_CBCMR_PERIPH_CLK_SEL_RD(r) (((r) >> 12) & 0x3)
#define MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET 10
#define MXC_CCM_CBCMR_DDR_CLK_SEL_MASK (0x3 << 10)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL(v) (((v) & 0x3) << 10)
+#define MXC_CCM_CBCMR_DDR_CLK_SEL_RD(r) (((r) >> 10) & 0x3)
#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_OFFSET 8
#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_MASK (0x3 << 8)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL(v) (((v) & 0x3) << 8)
+#define MXC_CCM_CBCMR_ARM_AXI_CLK_SEL_RD(r) (((r) >> 8) & 0x3)
#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_OFFSET 6
#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK (0x3 << 6)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(v) (((v) & 0x3) << 6)
+#define MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_RD(r) (((r) >> 6) & 0x3)
#define MXC_CCM_CBCMR_GPU_CLK_SEL_OFFSET 4
#define MXC_CCM_CBCMR_GPU_CLK_SEL_MASK (0x3 << 4)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL(v) (((v) & 0x3) << 4)
+#define MXC_CCM_CBCMR_GPU_CLK_SEL_RD(r) (((r) >> 4) & 0x3)
#define MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL (0x1 << 1)
#define MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL (0x1 << 0)
/* Define the bits in register CSCDR1 */
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_OFFSET 22
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_MASK (0x7 << 22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED(v) (((v) & 0x7) << 22)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PRED_RD(r) (((r) >> 22) & 0x7)
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_OFFSET 19
#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_MASK (0x7 << 19)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF(v) (((v) & 0x7) << 19)
+#define MXC_CCM_CSCDR1_ESDHC2_MSHC2_CLK_PODF_RD(r) (((r) >> 19) & 0x7)
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_OFFSET 16
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_MASK (0x7 << 16)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED(v) (((v) & 0x7) << 16)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PRED_RD(r) (((r) >> 16) & 0x7)
#define MXC_CCM_CSCDR1_PGC_CLK_PODF_OFFSET 14
#define MXC_CCM_CSCDR1_PGC_CLK_PODF_MASK (0x3 << 14)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF(v) (((v) & 0x3) << 14)
+#define MXC_CCM_CSCDR1_PGC_CLK_PODF_RD(r) (((r) >> 14) & 0x3)
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_OFFSET 11
#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_MASK (0x7 << 11)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF(v) (((v) & 0x7) << 11)
+#define MXC_CCM_CSCDR1_ESDHC1_MSHC1_CLK_PODF_RD(r) (((r) >> 11) & 0x7)
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED(v) (((v) & 0x7) << 8)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_RD(r) (((r) >> 8) & 0x7)
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF(v) (((v) & 0x3) << 6)
+#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_RD(r) (((r) >> 6) & 0x3)
#define MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET 3
#define MXC_CCM_CSCDR1_UART_CLK_PRED_MASK (0x7 << 3)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED(v) (((v) & 0x7) << 3)
+#define MXC_CCM_CSCDR1_UART_CLK_PRED_RD(r) (((r) >> 3) & 0x7)
#define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x7
+#define MXC_CCM_CSCDR1_UART_CLK_PODF(v) ((v) & 0x7)
+#define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r) ((r) & 0x7)
/* Define the bits in register CCDR */
#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17)
/* Define the bits in register CCGRx */
#define MXC_CCM_CCGR_CG_MASK 0x3
+#define MXC_CCM_CCGR_CG_OFF 0x0
+#define MXC_CCM_CCGR_CG_RUN_ON 0x1
+#define MXC_CCM_CCGR_CG_ON 0x3
+
+#define MXC_CCM_CCGR0_ARM_BUS_OFFSET 0
+#define MXC_CCM_CCGR0_ARM_BUS(v) (((v) & 0x3) << 0)
+#define MXC_CCM_CCGR0_ARM_AXI_OFFSET 2
+#define MXC_CCM_CCGR0_ARM_AXI(v) (((v) & 0x3) << 2)
+#define MXC_CCM_CCGR0_ARM_DEBUG_OFFSET 4
+#define MXC_CCM_CCGR0_ARM_DEBUG(v) (((v) & 0x3) << 4)
+#define MXC_CCM_CCGR0_TZIC_OFFSET 6
+#define MXC_CCM_CCGR0_TZIC(v) (((v) & 0x3) << 6)
+#define MXC_CCM_CCGR0_DAP_OFFSET 8
+#define MXC_CCM_CCGR0_DAP(v) (((v) & 0x3) << 8)
+#define MXC_CCM_CCGR0_TPIU_OFFSET 10
+#define MXC_CCM_CCGR0_TPIU(v) (((v) & 0x3) << 10)
+#define MXC_CCM_CCGR0_CTI2_OFFSET 12
+#define MXC_CCM_CCGR0_CTI2(v) (((v) & 0x3) << 12)
+#define MXC_CCM_CCGR0_CTI3_OFFSET 14
+#define MXC_CCM_CCGR0_CTI3(v) (((v) & 0x3) << 14)
+#define MXC_CCM_CCGR0_AHBMUX1_OFFSET 16
+#define MXC_CCM_CCGR0_AHBMUX1(v) (((v) & 0x3) << 16)
+#define MXC_CCM_CCGR0_AHBMUX2_OFFSET 18
+#define MXC_CCM_CCGR0_AHBMUX2(v) (((v) & 0x3) << 18)
+#define MXC_CCM_CCGR0_ROMCP_OFFSET 20
+#define MXC_CCM_CCGR0_ROMCP(v) (((v) & 0x3) << 20)
+#define MXC_CCM_CCGR0_ROM_OFFSET 22
+#define MXC_CCM_CCGR0_ROM(v) (((v) & 0x3) << 22)
+#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 24
+#define MXC_CCM_CCGR0_AIPS_TZ1(v) (((v) & 0x3) << 24)
+#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 26
+#define MXC_CCM_CCGR0_AIPS_TZ2(v) (((v) & 0x3) << 26)
+#define MXC_CCM_CCGR0_AHB_MAX_OFFSET 28
+#define MXC_CCM_CCGR0_AHB_MAX(v) (((v) & 0x3) << 28)
+#define MXC_CCM_CCGR0_IIM_OFFSET 30
+#define MXC_CCM_CCGR0_IIM(v) (((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR1_TMAX1_OFFSET 0
+#define MXC_CCM_CCGR1_TMAX1(v) (((v) & 0x3) << 0)
+#define MXC_CCM_CCGR1_TMAX2_OFFSET 2
+#define MXC_CCM_CCGR1_TMAX2(v) (((v) & 0x3) << 2)
+#define MXC_CCM_CCGR1_TMAX3_OFFSET 4
+#define MXC_CCM_CCGR1_TMAX3(v) (((v) & 0x3) << 4)
+#define MXC_CCM_CCGR1_UART1_IPG_OFFSET 6
+#define MXC_CCM_CCGR1_UART1_IPG(v) (((v) & 0x3) << 6)
+#define MXC_CCM_CCGR1_UART1_PER_OFFSET 8
+#define MXC_CCM_CCGR1_UART1_PER(v) (((v) & 0x3) << 8)
+#define MXC_CCM_CCGR1_UART2_IPG_OFFSET 10
+#define MXC_CCM_CCGR1_UART2_IPG(v) (((v) & 0x3) << 10)
+#define MXC_CCM_CCGR1_UART2_PER_OFFSET 12
+#define MXC_CCM_CCGR1_UART2_PER(v) (((v) & 0x3) << 12)
+#define MXC_CCM_CCGR1_UART3_IPG_OFFSET 14
+#define MXC_CCM_CCGR1_UART3_IPG(v) (((v) & 0x3) << 14)
+#define MXC_CCM_CCGR1_UART3_PER_OFFSET 16
+#define MXC_CCM_CCGR1_UART3_PER(v) (((v) & 0x3) << 16)
+#define MXC_CCM_CCGR1_I2C1_OFFSET 18
+#define MXC_CCM_CCGR1_I2C1(v) (((v) & 0x3) << 18)
+#define MXC_CCM_CCGR1_I2C2_OFFSET 20
+#define MXC_CCM_CCGR1_I2C2(v) (((v) & 0x3) << 20)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET 22
+#define MXC_CCM_CCGR1_HSI2C_IPG(v) (((v) & 0x3) << 22)
+#define MXC_CCM_CCGR1_HSI2C_SERIAL_OFFSET 24
+#define MXC_CCM_CCGR1_HSI2C_SERIAL(v) (((v) & 0x3) << 24)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR1_I2C3_OFFSET 22
+#define MXC_CCM_CCGR1_I2C3(v) (((v) & 0x3) << 22)
+#endif
+#define MXC_CCM_CCGR1_FIRI_IPG_OFFSET 26
+#define MXC_CCM_CCGR1_FIRI_IPG(v) (((v) & 0x3) << 26)
+#define MXC_CCM_CCGR1_FIRI_SERIAL_OFFSET 28
+#define MXC_CCM_CCGR1_FIRI_SERIAL(v) (((v) & 0x3) << 28)
+#define MXC_CCM_CCGR1_SCC_OFFSET 30
+#define MXC_CCM_CCGR1_SCC(v) (((v) & 0x3) << 30)
+
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR2_USB_PHY_OFFSET 0
+#define MXC_CCM_CCGR2_USB_PHY(v) (((v) & 0x3) << 0)
+#endif
+#define MXC_CCM_CCGR2_EPIT1_IPG_OFFSET 2
+#define MXC_CCM_CCGR2_EPIT1_IPG(v) (((v) & 0x3) << 2)
+#define MXC_CCM_CCGR2_EPIT1_HF_OFFSET 4
+#define MXC_CCM_CCGR2_EPIT1_HF(v) (((v) & 0x3) << 4)
+#define MXC_CCM_CCGR2_EPIT2_IPG_OFFSET 6
+#define MXC_CCM_CCGR2_EPIT2_IPG(v) (((v) & 0x3) << 6)
+#define MXC_CCM_CCGR2_EPIT2_HF_OFFSET 8
+#define MXC_CCM_CCGR2_EPIT2_HF(v) (((v) & 0x3) << 8)
+#define MXC_CCM_CCGR2_PWM1_IPG_OFFSET 10
+#define MXC_CCM_CCGR2_PWM1_IPG(v) (((v) & 0x3) << 10)
+#define MXC_CCM_CCGR2_PWM1_HF_OFFSET 12
+#define MXC_CCM_CCGR2_PWM1_HF(v) (((v) & 0x3) << 12)
+#define MXC_CCM_CCGR2_PWM2_IPG_OFFSET 14
+#define MXC_CCM_CCGR2_PWM2_IPG(v) (((v) & 0x3) << 14)
+#define MXC_CCM_CCGR2_PWM2_HF_OFFSET 16
+#define MXC_CCM_CCGR2_PWM2_HF(v) (((v) & 0x3) << 16)
+#define MXC_CCM_CCGR2_GPT_IPG_OFFSET 18
+#define MXC_CCM_CCGR2_GPT_IPG(v) (((v) & 0x3) << 18)
+#define MXC_CCM_CCGR2_GPT_HF_OFFSET 20
+#define MXC_CCM_CCGR2_GPT_HF(v) (((v) & 0x3) << 20)
+#define MXC_CCM_CCGR2_OWIRE_OFFSET 22
+#define MXC_CCM_CCGR2_OWIRE(v) (((v) & 0x3) << 22)
+#define MXC_CCM_CCGR2_FEC_OFFSET 24
+#define MXC_CCM_CCGR2_FEC(v) (((v) & 0x3) << 24)
+#define MXC_CCM_CCGR2_USBOH3_IPG_AHB_OFFSET 26
+#define MXC_CCM_CCGR2_USBOH3_IPG_AHB(v) (((v) & 0x3) << 26)
+#define MXC_CCM_CCGR2_USBOH3_60M_OFFSET 28
+#define MXC_CCM_CCGR2_USBOH3_60M(v) (((v) & 0x3) << 28)
+#define MXC_CCM_CCGR2_TVE_OFFSET 30
+#define MXC_CCM_CCGR2_TVE(v) (((v) & 0x3) << 30)
-#define MXC_CCM_CCGR4_CG5_OFFSET 10
-#define MXC_CCM_CCGR4_CG6_OFFSET 12
-#define MXC_CCM_CCGR5_CG5_OFFSET 10
-#define MXC_CCM_CCGR2_CG14_OFFSET 28
+#define MXC_CCM_CCGR3_ESDHC1_IPG_OFFSET 0
+#define MXC_CCM_CCGR3_ESDHC1_IPG(v) (((v) & 0x3) << 0)
+#define MXC_CCM_CCGR3_ESDHC1_PER_OFFSET 2
+#define MXC_CCM_CCGR3_ESDHC1_PER(v) (((v) & 0x3) << 2)
+#define MXC_CCM_CCGR3_ESDHC2_IPG_OFFSET 4
+#define MXC_CCM_CCGR3_ESDHC2_IPG(v) (((v) & 0x3) << 4)
+#define MXC_CCM_CCGR3_ESDHC2_PER_OFFSET 6
+#define MXC_CCM_CCGR3_ESDHC2_PER(v) (((v) & 0x3) << 6)
+#define MXC_CCM_CCGR3_ESDHC3_IPG_OFFSET 8
+#define MXC_CCM_CCGR3_ESDHC3_IPG(v) (((v) & 0x3) << 8)
+#define MXC_CCM_CCGR3_ESDHC3_PER_OFFSET 10
+#define MXC_CCM_CCGR3_ESDHC3_PER(v) (((v) & 0x3) << 10)
+#define MXC_CCM_CCGR3_ESDHC4_IPG_OFFSET 12
+#define MXC_CCM_CCGR3_ESDHC4_IPG(v) (((v) & 0x3) << 12)
+#define MXC_CCM_CCGR3_ESDHC4_PER_OFFSET 14
+#define MXC_CCM_CCGR3_ESDHC4_PER(v) (((v) & 0x3) << 14)
+#define MXC_CCM_CCGR3_SSI1_IPG_OFFSET 16
+#define MXC_CCM_CCGR3_SSI1_IPG(v) (((v) & 0x3) << 16)
+#define MXC_CCM_CCGR3_SSI1_SSI_OFFSET 18
+#define MXC_CCM_CCGR3_SSI1_SSI(v) (((v) & 0x3) << 18)
+#define MXC_CCM_CCGR3_SSI2_IPG_OFFSET 20
+#define MXC_CCM_CCGR3_SSI2_IPG(v) (((v) & 0x3) << 20)
+#define MXC_CCM_CCGR3_SSI2_SSI_OFFSET 22
+#define MXC_CCM_CCGR3_SSI2_SSI(v) (((v) & 0x3) << 22)
+#define MXC_CCM_CCGR3_SSI3_IPG_OFFSET 24
+#define MXC_CCM_CCGR3_SSI3_IPG(v) (((v) & 0x3) << 24)
+#define MXC_CCM_CCGR3_SSI3_SSI_OFFSET 26
+#define MXC_CCM_CCGR3_SSI3_SSI(v) (((v) & 0x3) << 26)
+#define MXC_CCM_CCGR3_SSI_EXT1_OFFSET 28
+#define MXC_CCM_CCGR3_SSI_EXT1(v) (((v) & 0x3) << 28)
+#define MXC_CCM_CCGR3_SSI_EXT2_OFFSET 30
+#define MXC_CCM_CCGR3_SSI_EXT2(v) (((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR4_PATA_OFFSET 0
+#define MXC_CCM_CCGR4_PATA(v) (((v) & 0x3) << 0)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR4_SIM_IPG_OFFSET 2
+#define MXC_CCM_CCGR4_SIM_IPG(v) (((v) & 0x3) << 2)
+#define MXC_CCM_CCGR4_SIM_SERIAL_OFFSET 4
+#define MXC_CCM_CCGR4_SIM_SERIAL(v) (((v) & 0x3) << 4)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR4_SATA_OFFSET 2
+#define MXC_CCM_CCGR4_SATA(v) (((v) & 0x3) << 2)
+#define MXC_CCM_CCGR4_CAN2_IPG_OFFSET 6
+#define MXC_CCM_CCGR4_CAN2_IPG(v) (((v) & 0x3) << 6)
+#define MXC_CCM_CCGR4_CAN2_SERIAL_OFFSET 8
+#define MXC_CCM_CCGR4_CAN2_SERIAL(v) (((v) & 0x3) << 8)
+#define MXC_CCM_CCGR4_USB_PHY1_OFFSET 10
+#define MXC_CCM_CCGR4_USB_PHY1(v) (((v) & 0x3) << 10)
+#define MXC_CCM_CCGR4_USB_PHY2_OFFSET 12
+#define MXC_CCM_CCGR4_USB_PHY2(v) (((v) & 0x3) << 12)
+#endif
+#define MXC_CCM_CCGR4_SAHARA_OFFSET 14
+#define MXC_CCM_CCGR4_SAHARA(v) (((v) & 0x3) << 14)
+#define MXC_CCM_CCGR4_RTIC_OFFSET 16
+#define MXC_CCM_CCGR4_RTIC(v) (((v) & 0x3) << 16)
+#define MXC_CCM_CCGR4_ECSPI1_IPG_OFFSET 18
+#define MXC_CCM_CCGR4_ECSPI1_IPG(v) (((v) & 0x3) << 18)
+#define MXC_CCM_CCGR4_ECSPI1_PER_OFFSET 20
+#define MXC_CCM_CCGR4_ECSPI1_PER(v) (((v) & 0x3) << 20)
+#define MXC_CCM_CCGR4_ECSPI2_IPG_OFFSET 22
+#define MXC_CCM_CCGR4_ECSPI2_IPG(v) (((v) & 0x3) << 22)
+#define MXC_CCM_CCGR4_ECSPI2_PER_OFFSET 24
+#define MXC_CCM_CCGR4_ECSPI2_PER(v) (((v) & 0x3) << 24)
+#define MXC_CCM_CCGR4_CSPI_IPG_OFFSET 26
+#define MXC_CCM_CCGR4_CSPI_IPG(v) (((v) & 0x3) << 26)
+#define MXC_CCM_CCGR4_SRTC_OFFSET 28
+#define MXC_CCM_CCGR4_SRTC(v) (((v) & 0x3) << 28)
+#define MXC_CCM_CCGR4_SDMA_OFFSET 30
+#define MXC_CCM_CCGR4_SDMA(v) (((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR5_SPBA_OFFSET 0
+#define MXC_CCM_CCGR5_SPBA(v) (((v) & 0x3) << 0)
+#define MXC_CCM_CCGR5_GPU_OFFSET 2
+#define MXC_CCM_CCGR5_GPU(v) (((v) & 0x3) << 2)
+#define MXC_CCM_CCGR5_GARB_OFFSET 4
+#define MXC_CCM_CCGR5_GARB(v) (((v) & 0x3) << 4)
+#define MXC_CCM_CCGR5_VPU_OFFSET 6
+#define MXC_CCM_CCGR5_VPU(v) (((v) & 0x3) << 6)
+#define MXC_CCM_CCGR5_VPU_REF_OFFSET 8
+#define MXC_CCM_CCGR5_VPU_REF(v) (((v) & 0x3) << 8)
+#define MXC_CCM_CCGR5_IPU_OFFSET 10
+#define MXC_CCM_CCGR5_IPU(v) (((v) & 0x3) << 10)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR5_IPUMUX12_OFFSET 12
+#define MXC_CCM_CCGR5_IPUMUX12(v) (((v) & 0x3) << 12)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR5_IPUMUX1_OFFSET 12
+#define MXC_CCM_CCGR5_IPUMUX1(v) (((v) & 0x3) << 12)
+#endif
+#define MXC_CCM_CCGR5_EMI_FAST_OFFSET 14
+#define MXC_CCM_CCGR5_EMI_FAST(v) (((v) & 0x3) << 14)
+#define MXC_CCM_CCGR5_EMI_SLOW_OFFSET 16
+#define MXC_CCM_CCGR5_EMI_SLOW(v) (((v) & 0x3) << 16)
+#define MXC_CCM_CCGR5_EMI_INT1_OFFSET 18
+#define MXC_CCM_CCGR5_EMI_INT1(v) (((v) & 0x3) << 18)
+#define MXC_CCM_CCGR5_EMI_ENFC_OFFSET 20
+#define MXC_CCM_CCGR5_EMI_ENFC(v) (((v) & 0x3) << 20)
+#define MXC_CCM_CCGR5_EMI_WRCK_OFFSET 22
+#define MXC_CCM_CCGR5_EMI_WRCK(v) (((v) & 0x3) << 22)
+#define MXC_CCM_CCGR5_GPC_IPG_OFFSET 24
+#define MXC_CCM_CCGR5_GPC_IPG(v) (((v) & 0x3) << 24)
+#define MXC_CCM_CCGR5_SPDIF0_OFFSET 26
+#define MXC_CCM_CCGR5_SPDIF0(v) (((v) & 0x3) << 26)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR5_SPDIF1_OFFSET 28
+#define MXC_CCM_CCGR5_SPDIF1(v) (((v) & 0x3) << 28)
+#endif
+#define MXC_CCM_CCGR5_SPDIF_IPG_OFFSET 30
+#define MXC_CCM_CCGR5_SPDIF_IPG(v) (((v) & 0x3) << 30)
+
+#if defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_IPUMUX2_OFFSET 0
+#define MXC_CCM_CCGR6_IPUMUX2(v) (((v) & 0x3) << 0)
+#define MXC_CCM_CCGR6_OCRAM_OFFSET 2
+#define MXC_CCM_CCGR6_OCRAM(v) (((v) & 0x3) << 2)
+#endif
+#define MXC_CCM_CCGR6_CSI_MCLK1_OFFSET 4
+#define MXC_CCM_CCGR6_CSI_MCLK1(v) (((v) & 0x3) << 4)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCGR6_CSI_MCLK2_OFFSET 6
+#define MXC_CCM_CCGR6_CSI_MCLK2(v) (((v) & 0x3) << 6)
+#define MXC_CCM_CCGR6_EMI_GARB_OFFSET 8
+#define MXC_CCM_CCGR6_EMI_GARB(v) (((v) & 0x3) << 8)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_EMI_INT2_OFFSET 8
+#define MXC_CCM_CCGR6_EMI_INT2(v) (((v) & 0x3) << 8)
+#endif
+#define MXC_CCM_CCGR6_IPU_DI0_OFFSET 10
+#define MXC_CCM_CCGR6_IPU_DI0(v) (((v) & 0x3) << 10)
+#define MXC_CCM_CCGR6_IPU_DI1_OFFSET 12
+#define MXC_CCM_CCGR6_IPU_DI1(v) (((v) & 0x3) << 12)
+#define MXC_CCM_CCGR6_GPU2D_OFFSET 14
+#define MXC_CCM_CCGR6_GPU2D(v) (((v) & 0x3) << 14)
+#if defined(CONFIG_MX53)
+#define MXC_CCM_CCGR6_ESAI_IPG_OFFSET 16
+#define MXC_CCM_CCGR6_ESAI_IPG(v) (((v) & 0x3) << 16)
+#define MXC_CCM_CCGR6_ESAI_ROOT_OFFSET 18
+#define MXC_CCM_CCGR6_ESAI_ROOT(v) (((v) & 0x3) << 18)
+#define MXC_CCM_CCGR6_CAN1_IPG_OFFSET 20
+#define MXC_CCM_CCGR6_CAN1_IPG(v) (((v) & 0x3) << 20)
+#define MXC_CCM_CCGR6_CAN1_SERIAL_OFFSET 22
+#define MXC_CCM_CCGR6_CAN1_SERIAL(v) (((v) & 0x3) << 22)
+#define MXC_CCM_CCGR6_PL301_4X1_OFFSET 24
+#define MXC_CCM_CCGR6_PL301_4X1(v) (((v) & 0x3) << 24)
+#define MXC_CCM_CCGR6_PL301_2X2_OFFSET 26
+#define MXC_CCM_CCGR6_PL301_2X2(v) (((v) & 0x3) << 26)
+#define MXC_CCM_CCGR6_LDB_DI0_OFFSET 28
+#define MXC_CCM_CCGR6_LDB_DI0(v) (((v) & 0x3) << 28)
+#define MXC_CCM_CCGR6_LDB_DI1_OFFSET 30
+#define MXC_CCM_CCGR6_LDB_DI1(v) (((v) & 0x3) << 30)
+
+#define MXC_CCM_CCGR7_ASRC_IPG_OFFSET 0
+#define MXC_CCM_CCGR7_ASRC_IPG(v) (((v) & 0x3) << 0)
+#define MXC_CCM_CCGR7_ASRC_ASRCK_OFFSET 2
+#define MXC_CCM_CCGR7_ASRC_ASRCK(v) (((v) & 0x3) << 2)
+#define MXC_CCM_CCGR7_MLB_OFFSET 4
+#define MXC_CCM_CCGR7_MLB(v) (((v) & 0x3) << 4)
+#define MXC_CCM_CCGR7_IEEE1588_OFFSET 6
+#define MXC_CCM_CCGR7_IEEE1588(v) (((v) & 0x3) << 6)
+#define MXC_CCM_CCGR7_UART4_IPG_OFFSET 8
+#define MXC_CCM_CCGR7_UART4_IPG(v) (((v) & 0x3) << 8)
+#define MXC_CCM_CCGR7_UART4_PER_OFFSET 10
+#define MXC_CCM_CCGR7_UART4_PER(v) (((v) & 0x3) << 10)
+#define MXC_CCM_CCGR7_UART5_IPG_OFFSET 12
+#define MXC_CCM_CCGR7_UART5_IPG(v) (((v) & 0x3) << 12)
+#define MXC_CCM_CCGR7_UART5_PER_OFFSET 14
+#define MXC_CCM_CCGR7_UART5_PER(v) (((v) & 0x3) << 14)
+#endif
/* Define the bits in register CLPCR */
#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
#define MXC_DPLLC_CTL_DPDCK0_2_EN (1 << 12)
#define MXC_DPLLC_OP_PDF_MASK 0xf
-#define MXC_DPLLC_OP_MFI_MASK (0xf << 4)
#define MXC_DPLLC_OP_MFI_OFFSET 4
+#define MXC_DPLLC_OP_MFI_MASK (0xf << 4)
+#define MXC_DPLLC_OP_MFI(v) (((v) & 0xf) << 4)
+#define MXC_DPLLC_OP_MFI_RD(r) (((r) >> 4) & 0xf)
#define MXC_DPLLC_MFD_MFD_MASK 0x7ffffff
#ifndef __ASM_ARCH_CLOCK_H
#define __ASM_ARCH_CLOCK_H
+#include <common.h>
+
+#ifdef CONFIG_SYS_MX6_HCLK
+#define MXC_HCLK CONFIG_SYS_MX6_HCLK
+#else
+#define MXC_HCLK 24000000
+#endif
+
+#ifdef CONFIG_SYS_MX6_CLK32
+#define MXC_CLK32 CONFIG_SYS_MX6_CLK32
+#else
+#define MXC_CLK32 32768
+#endif
+
enum mxc_clock {
MXC_ARM_CLK = 0,
MXC_PER_CLK,
MXC_ESDHC4_CLK,
MXC_SATA_CLK,
MXC_NFC_CLK,
+ MXC_I2C_CLK,
};
u32 imx_get_uartclk(void);
u32 cs1cdr;
u32 cs2cdr;
u32 cdcdr; /* 0x0030 */
- u32 chscdr;
+ u32 chsccdr;
u32 cscdr2;
u32 cscdr3;
u32 cscdr4; /* 0x0040 */
#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
+#define CHSCCDR_CLK_SEL_LDB_DI0 3
+#define CHSCCDR_PODF_DIVIDE_BY_3 2
+#define CHSCCDR_IPU_PRE_CLK_540M_PFD 5
+
/* Define the bits in register CSCDR2 */
#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
/* Define the bits in registers CCGRx */
#define MXC_CCM_CCGR_CG_MASK 3
-#define MXC_CCM_CCGR0_CG15_OFFSET 30
-#define MXC_CCM_CCGR0_CG15_MASK (0x3 << 30)
-#define MXC_CCM_CCGR0_CG14_OFFSET 28
-#define MXC_CCM_CCGR0_CG14_MASK (0x3 << 28)
-#define MXC_CCM_CCGR0_CG13_OFFSET 26
-#define MXC_CCM_CCGR0_CG13_MASK (0x3 << 26)
-#define MXC_CCM_CCGR0_CG12_OFFSET 24
-#define MXC_CCM_CCGR0_CG12_MASK (0x3 << 24)
-#define MXC_CCM_CCGR0_CG11_OFFSET 22
-#define MXC_CCM_CCGR0_CG11_MASK (0x3 << 22)
-#define MXC_CCM_CCGR0_CG10_OFFSET 20
-#define MXC_CCM_CCGR0_CG10_MASK (0x3 << 20)
-#define MXC_CCM_CCGR0_CG9_OFFSET 18
-#define MXC_CCM_CCGR0_CG9_MASK (0x3 << 18)
-#define MXC_CCM_CCGR0_CG8_OFFSET 16
-#define MXC_CCM_CCGR0_CG8_MASK (0x3 << 16)
-#define MXC_CCM_CCGR0_CG7_OFFSET 14
-#define MXC_CCM_CCGR0_CG6_OFFSET 12
-#define MXC_CCM_CCGR0_CG5_OFFSET 10
-#define MXC_CCM_CCGR0_CG5_MASK (0x3 << 10)
-#define MXC_CCM_CCGR0_CG4_OFFSET 8
-#define MXC_CCM_CCGR0_CG4_MASK (0x3 << 8)
-#define MXC_CCM_CCGR0_CG3_OFFSET 6
-#define MXC_CCM_CCGR0_CG3_MASK (0x3 << 6)
-#define MXC_CCM_CCGR0_CG2_OFFSET 4
-#define MXC_CCM_CCGR0_CG2_MASK (0x3 << 4)
-#define MXC_CCM_CCGR0_CG1_OFFSET 2
-#define MXC_CCM_CCGR0_CG1_MASK (0x3 << 2)
-#define MXC_CCM_CCGR0_CG0_OFFSET 0
-#define MXC_CCM_CCGR0_CG0_MASK 3
-
-#define MXC_CCM_CCGR1_CG15_OFFSET 30
-#define MXC_CCM_CCGR1_CG14_OFFSET 28
-#define MXC_CCM_CCGR1_CG13_OFFSET 26
-#define MXC_CCM_CCGR1_CG12_OFFSET 24
-#define MXC_CCM_CCGR1_CG11_OFFSET 22
-#define MXC_CCM_CCGR1_CG10_OFFSET 20
-#define MXC_CCM_CCGR1_CG9_OFFSET 18
-#define MXC_CCM_CCGR1_CG8_OFFSET 16
-#define MXC_CCM_CCGR1_CG7_OFFSET 14
-#define MXC_CCM_CCGR1_CG6_OFFSET 12
-#define MXC_CCM_CCGR1_CG5_OFFSET 10
-#define MXC_CCM_CCGR1_CG4_OFFSET 8
-#define MXC_CCM_CCGR1_CG3_OFFSET 6
-#define MXC_CCM_CCGR1_CG2_OFFSET 4
-#define MXC_CCM_CCGR1_CG1_OFFSET 2
-#define MXC_CCM_CCGR1_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR2_CG15_OFFSET 30
-#define MXC_CCM_CCGR2_CG14_OFFSET 28
-#define MXC_CCM_CCGR2_CG13_OFFSET 26
-#define MXC_CCM_CCGR2_CG12_OFFSET 24
-#define MXC_CCM_CCGR2_CG11_OFFSET 22
-#define MXC_CCM_CCGR2_CG10_OFFSET 20
-#define MXC_CCM_CCGR2_CG9_OFFSET 18
-#define MXC_CCM_CCGR2_CG8_OFFSET 16
-#define MXC_CCM_CCGR2_CG7_OFFSET 14
-#define MXC_CCM_CCGR2_CG6_OFFSET 12
-#define MXC_CCM_CCGR2_CG5_OFFSET 10
-#define MXC_CCM_CCGR2_CG4_OFFSET 8
-#define MXC_CCM_CCGR2_CG3_OFFSET 6
-#define MXC_CCM_CCGR2_CG2_OFFSET 4
-#define MXC_CCM_CCGR2_CG1_OFFSET 2
-#define MXC_CCM_CCGR2_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR3_CG15_OFFSET 30
-#define MXC_CCM_CCGR3_CG14_OFFSET 28
-#define MXC_CCM_CCGR3_CG13_OFFSET 26
-#define MXC_CCM_CCGR3_CG12_OFFSET 24
-#define MXC_CCM_CCGR3_CG11_OFFSET 22
-#define MXC_CCM_CCGR3_CG10_OFFSET 20
-#define MXC_CCM_CCGR3_CG9_OFFSET 18
-#define MXC_CCM_CCGR3_CG8_OFFSET 16
-#define MXC_CCM_CCGR3_CG7_OFFSET 14
-#define MXC_CCM_CCGR3_CG6_OFFSET 12
-#define MXC_CCM_CCGR3_CG5_OFFSET 10
-#define MXC_CCM_CCGR3_CG4_OFFSET 8
-#define MXC_CCM_CCGR3_CG3_OFFSET 6
-#define MXC_CCM_CCGR3_CG2_OFFSET 4
-#define MXC_CCM_CCGR3_CG1_OFFSET 2
-#define MXC_CCM_CCGR3_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR4_CG15_OFFSET 30
-#define MXC_CCM_CCGR4_CG14_OFFSET 28
-#define MXC_CCM_CCGR4_CG13_OFFSET 26
-#define MXC_CCM_CCGR4_CG12_OFFSET 24
-#define MXC_CCM_CCGR4_CG11_OFFSET 22
-#define MXC_CCM_CCGR4_CG10_OFFSET 20
-#define MXC_CCM_CCGR4_CG9_OFFSET 18
-#define MXC_CCM_CCGR4_CG8_OFFSET 16
-#define MXC_CCM_CCGR4_CG7_OFFSET 14
-#define MXC_CCM_CCGR4_CG6_OFFSET 12
-#define MXC_CCM_CCGR4_CG5_OFFSET 10
-#define MXC_CCM_CCGR4_CG4_OFFSET 8
-#define MXC_CCM_CCGR4_CG3_OFFSET 6
-#define MXC_CCM_CCGR4_CG2_OFFSET 4
-#define MXC_CCM_CCGR4_CG1_OFFSET 2
-#define MXC_CCM_CCGR4_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR5_CG15_OFFSET 30
-#define MXC_CCM_CCGR5_CG14_OFFSET 28
-#define MXC_CCM_CCGR5_CG14_MASK (0x3 << 28)
-#define MXC_CCM_CCGR5_CG13_OFFSET 26
-#define MXC_CCM_CCGR5_CG13_MASK (0x3 << 26)
-#define MXC_CCM_CCGR5_CG12_OFFSET 24
-#define MXC_CCM_CCGR5_CG12_MASK (0x3 << 24)
-#define MXC_CCM_CCGR5_CG11_OFFSET 22
-#define MXC_CCM_CCGR5_CG11_MASK (0x3 << 22)
-#define MXC_CCM_CCGR5_CG10_OFFSET 20
-#define MXC_CCM_CCGR5_CG10_MASK (0x3 << 20)
-#define MXC_CCM_CCGR5_CG9_OFFSET 18
-#define MXC_CCM_CCGR5_CG9_MASK (0x3 << 18)
-#define MXC_CCM_CCGR5_CG8_OFFSET 16
-#define MXC_CCM_CCGR5_CG8_MASK (0x3 << 16)
-#define MXC_CCM_CCGR5_CG7_OFFSET 14
-#define MXC_CCM_CCGR5_CG7_MASK (0x3 << 14)
-#define MXC_CCM_CCGR5_CG6_OFFSET 12
-#define MXC_CCM_CCGR5_CG6_MASK (0x3 << 12)
-#define MXC_CCM_CCGR5_CG5_OFFSET 10
-#define MXC_CCM_CCGR5_CG4_OFFSET 8
-#define MXC_CCM_CCGR5_CG3_OFFSET 6
-#define MXC_CCM_CCGR5_CG2_OFFSET 4
-#define MXC_CCM_CCGR5_CG2_MASK (0x3 << 4)
-#define MXC_CCM_CCGR5_CG1_OFFSET 2
-#define MXC_CCM_CCGR5_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR6_CG15_OFFSET 30
-#define MXC_CCM_CCGR6_CG14_OFFSET 28
-#define MXC_CCM_CCGR6_CG14_MASK (0x3 << 28)
-#define MXC_CCM_CCGR6_CG13_OFFSET 26
-#define MXC_CCM_CCGR6_CG13_MASK (0x3 << 26)
-#define MXC_CCM_CCGR6_CG12_OFFSET 24
-#define MXC_CCM_CCGR6_CG12_MASK (0x3 << 24)
-#define MXC_CCM_CCGR6_CG11_OFFSET 22
-#define MXC_CCM_CCGR6_CG11_MASK (0x3 << 22)
-#define MXC_CCM_CCGR6_CG10_OFFSET 20
-#define MXC_CCM_CCGR6_CG10_MASK (0x3 << 20)
-#define MXC_CCM_CCGR6_CG9_OFFSET 18
-#define MXC_CCM_CCGR6_CG9_MASK (0x3 << 18)
-#define MXC_CCM_CCGR6_CG8_OFFSET 16
-#define MXC_CCM_CCGR6_CG8_MASK (0x3 << 16)
-#define MXC_CCM_CCGR6_CG7_OFFSET 14
-#define MXC_CCM_CCGR6_CG7_MASK (0x3 << 14)
-#define MXC_CCM_CCGR6_CG6_OFFSET 12
-#define MXC_CCM_CCGR6_CG6_MASK (0x3 << 12)
-#define MXC_CCM_CCGR6_CG5_OFFSET 10
-#define MXC_CCM_CCGR6_CG4_OFFSET 8
-#define MXC_CCM_CCGR6_CG3_OFFSET 6
-#define MXC_CCM_CCGR6_CG2_OFFSET 4
-#define MXC_CCM_CCGR6_CG2_MASK (0x3 << 4)
-#define MXC_CCM_CCGR6_CG1_OFFSET 2
-#define MXC_CCM_CCGR6_CG0_OFFSET 0
-
-#define MXC_CCM_CCGR7_CG15_OFFSET 30
-#define MXC_CCM_CCGR7_CG14_OFFSET 28
-#define MXC_CCM_CCGR7_CG14_MASK (0x3 << 28)
-#define MXC_CCM_CCGR7_CG13_OFFSET 26
-#define MXC_CCM_CCGR7_CG13_MASK (0x3 << 26)
-#define MXC_CCM_CCGR7_CG12_OFFSET 24
-#define MXC_CCM_CCGR7_CG12_MASK (0x3 << 24)
-#define MXC_CCM_CCGR7_CG11_OFFSET 22
-#define MXC_CCM_CCGR7_CG11_MASK (0x3 << 22)
-#define MXC_CCM_CCGR7_CG10_OFFSET 20
-#define MXC_CCM_CCGR7_CG10_MASK (0x3 << 20)
-#define MXC_CCM_CCGR7_CG9_OFFSET 18
-#define MXC_CCM_CCGR7_CG9_MASK (0x3 << 18)
-#define MXC_CCM_CCGR7_CG8_OFFSET 16
-#define MXC_CCM_CCGR7_CG8_MASK (0x3 << 16)
-#define MXC_CCM_CCGR7_CG7_OFFSET 14
-#define MXC_CCM_CCGR7_CG7_MASK (0x3 << 14)
-#define MXC_CCM_CCGR7_CG6_OFFSET 12
-#define MXC_CCM_CCGR7_CG6_MASK (0x3 << 12)
-#define MXC_CCM_CCGR7_CG5_OFFSET 10
-#define MXC_CCM_CCGR7_CG4_OFFSET 8
-#define MXC_CCM_CCGR7_CG3_OFFSET 6
-#define MXC_CCM_CCGR7_CG2_OFFSET 4
-#define MXC_CCM_CCGR7_CG2_MASK (0x3 << 4)
-#define MXC_CCM_CCGR7_CG1_OFFSET 2
-#define MXC_CCM_CCGR7_CG0_OFFSET 0
+#define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
+#define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
+#define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
+#define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3<<MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
+#define MXC_CCM_CCGR0_APBHDMA HCLK_OFFSET 4
+#define MXC_CCM_CCGR0_AMASK (3<<MXC_CCM_CCGR0_APBHDMA)
+#define MXC_CCM_CCGR0_ASRC_OFFSET 6
+#define MXC_CCM_CCGR0_ASRC_MASK (3<<MXC_CCM_CCGR0_ASRC_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8
+#define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3<<MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12
+#define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3<<MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
+#define MXC_CCM_CCGR0_CAN1_OFFSET 14
+#define MXC_CCM_CCGR0_CAN1_MASK (3<<MXC_CCM_CCGR0_CAN1_OFFSET)
+#define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16
+#define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3<<MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
+#define MXC_CCM_CCGR0_CAN2_OFFSET 18
+#define MXC_CCM_CCGR0_CAN2_MASK (3<<MXC_CCM_CCGR0_CAN2_OFFSET)
+#define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20
+#define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3<<MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
+#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22
+#define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3<<MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
+#define MXC_CCM_CCGR0_DCIC1_OFFSET 24
+#define MXC_CCM_CCGR0_DCIC1_MASK (3<<MXC_CCM_CCGR0_DCIC1_OFFSET)
+#define MXC_CCM_CCGR0_DCIC2_OFFSET 26
+#define MXC_CCM_CCGR0_DCIC2_MASK (3<<MXC_CCM_CCGR0_DCIC2_OFFSET)
+#define MXC_CCM_CCGR0_DTCP_OFFSET 28
+#define MXC_CCM_CCGR0_DTCP_MASK (3<<MXC_CCM_CCGR0_DTCP_OFFSET)
+
+#define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
+#define MXC_CCM_CCGR1_ECSPI1S_MASK (3<<MXC_CCM_CCGR1_ECSPI1S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2
+#define MXC_CCM_CCGR1_ECSPI2S_MASK (3<<MXC_CCM_CCGR1_ECSPI2S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4
+#define MXC_CCM_CCGR1_ECSPI3S_MASK (3<<MXC_CCM_CCGR1_ECSPI3S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6
+#define MXC_CCM_CCGR1_ECSPI4S_MASK (3<<MXC_CCM_CCGR1_ECSPI4S_OFFSET)
+#define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
+#define MXC_CCM_CCGR1_ECSPI5S_MASK (3<<MXC_CCM_CCGR1_ECSPI5S_OFFSET)
+#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10
+#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3<<MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
+#define MXC_CCM_CCGR1_EPIT1S_MASK (3<<MXC_CCM_CCGR1_EPIT1S_OFFSET)
+#define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
+#define MXC_CCM_CCGR1_EPIT2S_MASK (3<<MXC_CCM_CCGR1_EPIT2S_OFFSET)
+#define MXC_CCM_CCGR1_ESAIS_OFFSET 16
+#define MXC_CCM_CCGR1_ESAIS_MASK (3<<MXC_CCM_CCGR1_ESAIS_OFFSET)
+#define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20
+#define MXC_CCM_CCGR1_GPT_BUS_MASK (3<<MXC_CCM_CCGR1_GPT_BUS_OFFSET)
+#define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22
+#define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3<<MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
+#define MXC_CCM_CCGR1_GPU2D_OFFSET 24
+#define MXC_CCM_CCGR1_GPU2D_MASK (3<<MXC_CCM_CCGR1_GPU2D_OFFSET)
+#define MXC_CCM_CCGR1_GPU3D_OFFSET 26
+#define MXC_CCM_CCGR1_GPU3D_MASK (3<<MXC_CCM_CCGR1_GPU3D_OFFSET)
+
+#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
+#define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3<<MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
+#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
+#define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3<<MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
+#define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6
+#define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8
+#define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10
+#define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3<<MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
+#define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12
+#define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3<<MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
+#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14
+#define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3<<MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX1_OFFSET 16
+#define MXC_CCM_CCGR2_IPMUX1_MASK (3<<MXC_CCM_CCGR2_IPMUX1_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX2_OFFSET 18
+#define MXC_CCM_CCGR2_IPMUX2_MASK (3<<MXC_CCM_CCGR2_IPMUX2_OFFSET)
+#define MXC_CCM_CCGR2_IPMUX3_OFFSET 20
+#define MXC_CCM_CCGR2_IPMUX3_MASK (3<<MXC_CCM_CCGR2_IPMUX3_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
+#define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3<<MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
+#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
+#define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3<<MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
+
+#define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
+#define MXC_CCM_CCGR3_IPU1_IPU_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
+#define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
+#define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
+#define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3<<MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
+#define MXC_CCM_CCGR3_IPU2_IPU_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
+#define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
+#define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10
+#define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3<<MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
+#define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
+#define MXC_CCM_CCGR3_LDB_DI0_MASK (3<<MXC_CCM_CCGR3_LDB_DI0_OFFSET)
+#define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
+#define MXC_CCM_CCGR3_LDB_DI1_MASK (3<<MXC_CCM_CCGR3_LDB_DI1_OFFSET)
+#define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
+#define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3<<MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
+#define MXC_CCM_CCGR3_MLB_OFFSET 18
+#define MXC_CCM_CCGR3_MLB_MASK (3<<MXC_CCM_CCGR3_MLB_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22
+#define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
+#define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3<<MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
+#define MXC_CCM_CCGR3_OCRAM_OFFSET 28
+#define MXC_CCM_CCGR3_OCRAM_MASK (3<<MXC_CCM_CCGR3_OCRAM_OFFSET)
+#define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
+#define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3<<MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
+
+#define MXC_CCM_CCGR4_PCIE_OFFSET 0
+#define MXC_CCM_CCGR4_PCIE_MASK (3<<MXC_CCM_CCGR4_PCIE_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
+#define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
+#define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
+#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
+#define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3<<MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
+#define MXC_CCM_CCGR4_PWM1_OFFSET 16
+#define MXC_CCM_CCGR4_PWM1_MASK (3<<MXC_CCM_CCGR4_PWM1_OFFSET)
+#define MXC_CCM_CCGR4_PWM2_OFFSET 18
+#define MXC_CCM_CCGR4_PWM2_MASK (3<<MXC_CCM_CCGR4_PWM2_OFFSET)
+#define MXC_CCM_CCGR4_PWM3_OFFSET 20
+#define MXC_CCM_CCGR4_PWM3_MASK (3<<MXC_CCM_CCGR4_PWM3_OFFSET)
+#define MXC_CCM_CCGR4_PWM4_OFFSET 22
+#define MXC_CCM_CCGR4_PWM4_MASK (3<<MXC_CCM_CCGR4_PWM4_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24
+#define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30
+#define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3<<MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
+
+#define MXC_CCM_CCGR5_ROM_OFFSET 0
+#define MXC_CCM_CCGR5_ROM_MASK (3<<MXC_CCM_CCGR5_ROM_OFFSET)
+#define MXC_CCM_CCGR5_SATA_OFFSET 4
+#define MXC_CCM_CCGR5_SATA_MASK (3<<MXC_CCM_CCGR5_SATA_OFFSET)
+#define MXC_CCM_CCGR5_SDMA_OFFSET 6
+#define MXC_CCM_CCGR5_SDMA_MASK (3<<MXC_CCM_CCGR5_SDMA_OFFSET)
+#define MXC_CCM_CCGR5_SPBA_OFFSET 12
+#define MXC_CCM_CCGR5_SPBA_MASK (3<<MXC_CCM_CCGR5_SPBA_OFFSET)
+#define MXC_CCM_CCGR5_SPDIF_OFFSET 14
+#define MXC_CCM_CCGR5_SPDIF_MASK (3<<MXC_CCM_CCGR5_SPDIF_OFFSET)
+#define MXC_CCM_CCGR5_SSI1_OFFSET 18
+#define MXC_CCM_CCGR5_SSI1_MASK (3<<MXC_CCM_CCGR5_SSI1_OFFSET)
+#define MXC_CCM_CCGR5_SSI2_OFFSET 20
+#define MXC_CCM_CCGR5_SSI2_MASK (3<<MXC_CCM_CCGR5_SSI2_OFFSET)
+#define MXC_CCM_CCGR5_SSI3_OFFSET 22
+#define MXC_CCM_CCGR5_SSI3_MASK (3<<MXC_CCM_CCGR5_SSI3_OFFSET)
+#define MXC_CCM_CCGR5_UART_OFFSET 24
+#define MXC_CCM_CCGR5_UART_MASK (3<<MXC_CCM_CCGR5_UART_OFFSET)
+#define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
+#define MXC_CCM_CCGR5_UART_SERIAL_MASK (3<<MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
+
+#define MXC_CCM_CCGR6_USBOH3_OFFSET 0
+#define MXC_CCM_CCGR6_USBOH3_MASK (3<<MXC_CCM_CCGR6_USBOH3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC1_OFFSET 2
+#define MXC_CCM_CCGR6_USDHC1_MASK (3<<MXC_CCM_CCGR6_USDHC1_OFFSET)
+#define MXC_CCM_CCGR6_USDHC2_OFFSET 4
+#define MXC_CCM_CCGR6_USDHC2_MASK (3<<MXC_CCM_CCGR6_USDHC2_OFFSET)
+#define MXC_CCM_CCGR6_USDHC3_OFFSET 6
+#define MXC_CCM_CCGR6_USDHC3_MASK (3<<MXC_CCM_CCGR6_USDHC3_OFFSET)
+#define MXC_CCM_CCGR6_USDHC4_OFFSET 8
+#define MXC_CCM_CCGR6_USDHC4_MASK (3<<MXC_CCM_CCGR6_USDHC4_OFFSET)
+#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
+#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3<<MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
+#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
+#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3<<MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
+
#define BM_ANADIG_PLL_SYS_LOCK 0x80000000
#define BP_ANADIG_PLL_SYS_RSVD0 20
#define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
u32 gpr10;
};
+/* GPR3 bitfields */
+#define IOMUXC_GPR3_GPU_DBG_OFFSET 29
+#define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
+#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28
+#define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27
+#define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26
+#define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25
+#define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
+#define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21
+#define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
+#define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17
+#define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
+#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16
+#define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15
+#define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14
+#define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13
+#define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
+#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12
+#define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
+#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11
+#define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
+#define IOMUXC_GPR3_IPU_DIAG_OFFSET 10
+#define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
+
+#define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0
+#define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1
+#define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2
+#define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3
+
+#define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8
+#define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
+
+#define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6
+#define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
+
+#define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4
+#define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
+
+#define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2
+#define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
+
+
+struct iomuxc {
+ u32 gpr[14];
+ u32 omux[5];
+ /* mux and pad registers */
+};
+
+#define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20
+#define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
+#define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16
+#define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
+
+#define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15
+#define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
+#define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
+#define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
+#define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0
+#define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1
+
+#define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10
+#define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
+
+#define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9
+#define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
+#define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
+
+#define IOMUXC_GPR2_BITMAP_SPWG 0
+#define IOMUXC_GPR2_BITMAP_JEIDA 1
+
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
+
+#define IOMUXC_GPR2_DATA_WIDTH_18 0
+#define IOMUXC_GPR2_DATA_WIDTH_24 1
+
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
+
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+#define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
+
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+#define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
+
+#define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4
+#define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
+
+#define IOMUXC_GPR2_MODE_DISABLED 0
+#define IOMUXC_GPR2_MODE_ENABLED_DI0 1
+#define IOMUXC_GPR2_MODE_ENABLED_DI1 2
+
+#define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2
+#define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
+
+#define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
+#define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+#define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
+
/* ECSPI registers */
struct cspi_regs {
u32 rxdata;
u32 digprog; /* 0x260 */
};
+#define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0
+#define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD0_FRAC_SHIFT)
+#define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6
+#define ANATOP_PFD_480_PFD0_STABLE_MASK (1<<ANATOP_PFD_480_PFD0_STABLE_SHIFT)
+#define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7
+#define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1<<ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
+#define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8
+#define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f<<ANATOP_PFD_480_PFD1_FRAC_SHIFT)
+#define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14
+#define ANATOP_PFD_480_PFD1_STABLE_MASK (1<<ANATOP_PFD_480_PFD1_STABLE_SHIFT)
+#define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15
+#define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
+#define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16
+#define ANATOP_PFD_480_PFD2_FRAC_MASK (1<<ANATOP_PFD_480_PFD2_FRAC_SHIFT)
+#define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22
+#define ANATOP_PFD_480_PFD2_STABLE_MASK (1<<ANATOP_PFD_480_PFD2_STABLE_SHIFT)
+#define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23
+#define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f<<ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
+#define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24
+#define ANATOP_PFD_480_PFD3_FRAC_MASK (1<<ANATOP_PFD_480_PFD3_FRAC_SHIFT)
+#define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30
+#define ANATOP_PFD_480_PFD3_STABLE_MASK (1<<ANATOP_PFD_480_PFD3_STABLE_SHIFT)
+#define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31
+
struct iomuxc_base_regs {
u32 gpr[14]; /* 0x000 */
u32 obsrv[5]; /* 0x038 */
u32 daisy[104]; /* 0x7b0..94c */
};
-struct src_regs {
- u32 scr; /* 0x00 */
- u32 sbmr1; /* 0x04 */
- u32 srsr; /* 0x08 */
- u32 reserved1; /* 0x0c */
- u32 reserved2; /* 0x10 */
- u32 sisr; /* 0x14 */
- u32 simr; /* 0x18 */
- u32 sbmr2; /* 0x1c */
- u32 gpr1; /* 0x20 */
- u32 gpr2; /* 0x24 */
- u32 gpr3; /* 0x28 */
- u32 gpr4; /* 0x2c */
- u32 gpr5; /* 0x30 */
- u32 gpr6; /* 0x34 */
- u32 gpr7; /* 0x38 */
- u32 gpr8; /* 0x3c */
- u32 gpr9; /* 0x40 */
- u32 gpr10; /* 0x44 */
-};
-
#endif /* __ASSEMBLER__*/
#endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */
#ifndef __PXA_H__
#define __PXA_H__
+#define PXA255_A0 0x00000106
+#define PXA250_C0 0x00000105
+#define PXA250_B2 0x00000104
+#define PXA250_B1 0x00000103
+#define PXA250_B0 0x00000102
+#define PXA250_A1 0x00000101
+#define PXA250_A0 0x00000100
+#define PXA210_C0 0x00000125
+#define PXA210_B2 0x00000124
+#define PXA210_B1 0x00000123
+#define PXA210_B0 0x00000122
+
int cpu_is_pxa25x(void);
int cpu_is_pxa27x(void);
+uint32_t pxa_get_cpu_revision(void);
void pxa2xx_dram_init(void);
#endif /* __PXA_H__ */
--- /dev/null
+/*
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA_BOARD_H_
+#define _TEGRA_BOARD_H_
+
+/* Set up pinmux to make UART usable */
+void gpio_config_uart(void); /* CONFIG_SPI_UART_SWITCH */
+void gpio_early_init_uart(void); /*!CONFIG_SPI_UART_SWITCH */
+
+/* Set up early UART output */
+void board_init_uart_f(void);
+
+/* Set up any early GPIOs the board might need for proper operation */
+void gpio_early_init(void); /* overrideable GPIO config */
+
+/*
+ * Hooks to allow boards to set up the pinmux for a specific function.
+ * Has to be implemented in the board files as we don't yet support pinmux
+ * setup from FTD. If a board file does not implement one of those functions
+ * an empty stub function will be called.
+ */
+
+void pin_mux_usb(void); /* overrideable USB pinmux setup */
+void pin_mux_spi(void); /* overrideable SPI pinmux setup */
+void pin_mux_nand(void); /* overrideable NAND pinmux setup */
+
+#endif
/* PLL registers - there are several PLLs in the clock controller */
struct clk_pll {
uint pll_base; /* the control register */
- uint pll_out; /* output control */
- uint reserved;
+ uint pll_out[2]; /* output control */
uint pll_misc; /* other misc things */
};
#define PLL_DIVM_SHIFT 0
#define PLL_DIVM_MASK (0x1f << PLL_DIVM_SHIFT)
+/* CLK_RST_CONTROLLER_PLLx_OUTx_0 */
+#define PLL_OUT_RSTN (1 << 0)
+#define PLL_OUT_CLKEN (1 << 1)
+#define PLL_OUT_OVRRIDE (1 << 2)
+
+#define PLL_OUT_RATIO_SHIFT 8
+#define PLL_OUT_RATIO_MASK (0xffU << PLL_OUT_RATIO_SHIFT)
+
/* CLK_RST_CONTROLLER_PLLx_MISC_0 */
#define PLL_CPCON_SHIFT 8
#define PLL_CPCON_MASK (15U << PLL_CPCON_SHIFT)
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Tegra clock control functions */
+
+#ifndef _CLOCK_H
+#define _CLOCK_H
+
+/* Set of oscillator frequencies supported in the internal API. */
+enum clock_osc_freq {
+ /* All in MHz, so 13_0 is 13.0MHz */
+ CLOCK_OSC_FREQ_13_0,
+ CLOCK_OSC_FREQ_19_2,
+ CLOCK_OSC_FREQ_12_0,
+ CLOCK_OSC_FREQ_26_0,
+
+ CLOCK_OSC_FREQ_COUNT,
+};
+
+#include <asm/arch/clock-tables.h>
+/* PLL stabilization delay in usec */
+#define CLOCK_PLL_STABLE_DELAY_US 300
+
+/* return the current oscillator clock frequency */
+enum clock_osc_freq clock_get_osc_freq(void);
+
+/**
+ * Start PLL using the provided configuration parameters.
+ *
+ * @param id clock id
+ * @param divm input divider
+ * @param divn feedback divider
+ * @param divp post divider 2^n
+ * @param cpcon charge pump setup control
+ * @param lfcon loop filter setup control
+ *
+ * @returns monotonic time in us that the PLL will be stable
+ */
+unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
+ u32 divp, u32 cpcon, u32 lfcon);
+
+/**
+ * Set PLL output frequency
+ *
+ * @param clkid clock id
+ * @param pllout pll output id
+ * @param rate desired output rate
+ *
+ * @return 0 if ok, -1 on error (invalid clock id or no suitable divider)
+ */
+int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout,
+ unsigned rate);
+
+/**
+ * Read low-level parameters of a PLL.
+ *
+ * @param id clock id to read (note: USB is not supported)
+ * @param divm returns input divider
+ * @param divn returns feedback divider
+ * @param divp returns post divider 2^n
+ * @param cpcon returns charge pump setup control
+ * @param lfcon returns loop filter setup control
+ *
+ * @returns 0 if ok, -1 on error (invalid clock id)
+ */
+int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
+ u32 *divp, u32 *cpcon, u32 *lfcon);
+
+/*
+ * Enable a clock
+ *
+ * @param id clock id
+ */
+void clock_enable(enum periph_id clkid);
+
+/*
+ * Disable a clock
+ *
+ * @param id clock id
+ */
+void clock_disable(enum periph_id clkid);
+
+/*
+ * Set whether a clock is enabled or disabled.
+ *
+ * @param id clock id
+ * @param enable 1 to enable, 0 to disable
+ */
+void clock_set_enable(enum periph_id clkid, int enable);
+
+/**
+ * Reset a peripheral. This puts it in reset, waits for a delay, then takes
+ * it out of reset and waits for th delay again.
+ *
+ * @param periph_id peripheral to reset
+ * @param us_delay time to delay in microseconds
+ */
+void reset_periph(enum periph_id periph_id, int us_delay);
+
+/**
+ * Put a peripheral into or out of reset.
+ *
+ * @param periph_id peripheral to reset
+ * @param enable 1 to put into reset, 0 to take out of reset
+ */
+void reset_set_enable(enum periph_id periph_id, int enable);
+
+
+/* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */
+enum crc_reset_id {
+ /* Things we can hold in reset for each CPU */
+ crc_rst_cpu = 1,
+ crc_rst_de = 1 << 2, /* What is de? */
+ crc_rst_watchdog = 1 << 3,
+ crc_rst_debug = 1 << 4,
+};
+
+/**
+ * Put parts of the CPU complex into or out of reset.\
+ *
+ * @param cpu cpu number (0 or 1 on Tegra2)
+ * @param which which parts of the complex to affect (OR of crc_reset_id)
+ * @param reset 1 to assert reset, 0 to de-assert
+ */
+void reset_cmplx_set_enable(int cpu, int which, int reset);
+
+/**
+ * Set the source for a peripheral clock. This plus the divisor sets the
+ * clock rate. You need to look up the datasheet to see the meaning of the
+ * source parameter as it changes for each peripheral.
+ *
+ * Warning: This function is only for use pre-relocation. Please use
+ * clock_start_periph_pll() instead.
+ *
+ * @param periph_id peripheral to adjust
+ * @param source source clock (0, 1, 2 or 3)
+ */
+void clock_ll_set_source(enum periph_id periph_id, unsigned source);
+
+/**
+ * Set the source and divisor for a peripheral clock. This sets the
+ * clock rate. You need to look up the datasheet to see the meaning of the
+ * source parameter as it changes for each peripheral.
+ *
+ * Warning: This function is only for use pre-relocation. Please use
+ * clock_start_periph_pll() instead.
+ *
+ * @param periph_id peripheral to adjust
+ * @param source source clock (0, 1, 2 or 3)
+ * @param divisor divisor value to use
+ */
+void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
+ unsigned divisor);
+
+/**
+ * Start a peripheral PLL clock at the given rate. This also resets the
+ * peripheral.
+ *
+ * @param periph_id peripheral to start
+ * @param parent PLL id of required parent clock
+ * @param rate Required clock rate in Hz
+ * @return rate selected in Hz, or -1U if something went wrong
+ */
+unsigned clock_start_periph_pll(enum periph_id periph_id,
+ enum clock_id parent, unsigned rate);
+
+/**
+ * Returns the rate of a peripheral clock in Hz. Since the caller almost
+ * certainly knows the parent clock (having just set it) we require that
+ * this be passed in so we don't need to work it out.
+ *
+ * @param periph_id peripheral to start
+ * @param parent PLL id of parent clock (used to calculate rate, you
+ * must know this!)
+ * @return clock rate of peripheral in Hz
+ */
+unsigned long clock_get_periph_rate(enum periph_id periph_id,
+ enum clock_id parent);
+
+/**
+ * Adjust peripheral PLL clock to the given rate. This does not reset the
+ * peripheral. If a second stage divisor is not available, pass NULL for
+ * extra_div. If it is available, then this parameter will return the
+ * divisor selected (which will be a power of 2 from 1 to 256).
+ *
+ * @param periph_id peripheral to start
+ * @param parent PLL id of required parent clock
+ * @param rate Required clock rate in Hz
+ * @param extra_div value for the second-stage divisor (NULL if one is
+ not available)
+ * @return rate selected in Hz, or -1U if something went wrong
+ */
+unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
+ enum clock_id parent, unsigned rate, int *extra_div);
+
+/**
+ * Returns the clock rate of a specified clock, in Hz.
+ *
+ * @param parent PLL id of clock to check
+ * @return rate of clock in Hz
+ */
+unsigned clock_get_rate(enum clock_id clkid);
+
+/**
+ * Start up a UART using low-level calls
+ *
+ * Prior to relocation clock_start_periph_pll() cannot be called. This
+ * function provides a way to set up a UART using low-level calls which
+ * do not require BSS.
+ *
+ * @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1)
+ */
+void clock_ll_start_uart(enum periph_id periph_id);
+
+/**
+ * Decode a peripheral ID from a device tree node.
+ *
+ * This works by looking up the peripheral's 'clocks' node and reading out
+ * the second cell, which is the clock number / peripheral ID.
+ *
+ * @param blob FDT blob to use
+ * @param node Node to look at
+ * @return peripheral ID, or PERIPH_ID_NONE if none
+ */
+enum periph_id clock_decode_periph_id(const void *blob, int node);
+
+/**
+ * Checks if the oscillator bypass is enabled (XOBP bit)
+ *
+ * @return 1 if bypass is enabled, 0 if not
+ */
+int clock_get_osc_bypass(void);
+
+/*
+ * Checks that clocks are valid and prints a warning if not
+ *
+ * @return 0 if ok, -1 on error
+ */
+int clock_verify(void);
+
+/* Initialize the clocks */
+void clock_init(void);
+
+/* Initialize the PLLs */
+void clock_early_init(void);
+
+#endif /* _CLOCK_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2011, Google Inc. All rights reserved.
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _TEGRA_GPIO_H_
+#define _TEGRA_GPIO_H_
+
+#define MAX_NUM_GPIOS (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8)
+#define GPIO_NAME_SIZE 20 /* gpio_request max label len */
+
+#define GPIO_BANK(x) ((x) >> 5)
+#define GPIO_PORT(x) (((x) >> 3) & 0x3)
+#define GPIO_FULLPORT(x) ((x) >> 3)
+#define GPIO_BIT(x) ((x) & 0x7)
+
+/*
+ * Tegra-specific GPIO API
+ */
+
+void gpio_info(void);
+
+#define gpio_status() gpio_info()
+#endif /* TEGRA_GPIO_H_ */
* MA 02111-1307 USA
*/
-#ifndef _TEGRA20_H_
-#define _TEGRA20_H_
+#ifndef _TEGRA_H_
+#define _TEGRA_H_
-#define NV_PA_SDRAM_BASE 0x00000000
#define NV_PA_ARM_PERIPHBASE 0x50040000
#define NV_PA_PG_UP_BASE 0x60000000
#define NV_PA_TMRUS_BASE 0x60005010
#define NV_PA_APB_UARTE_BASE (NV_PA_APB_MISC_BASE + 0x6400)
#define NV_PA_NAND_BASE (NV_PA_APB_MISC_BASE + 0x8000)
#define NV_PA_SPI_BASE (NV_PA_APB_MISC_BASE + 0xC380)
+#define TEGRA_DVC_BASE (NV_PA_APB_MISC_BASE + 0xD000)
#define NV_PA_PMC_BASE (NV_PA_APB_MISC_BASE + 0xE400)
+#define NV_PA_EMC_BASE (NV_PA_APB_MISC_BASE + 0xF400)
#define NV_PA_FUSE_BASE (NV_PA_APB_MISC_BASE + 0xF800)
#define NV_PA_CSITE_BASE 0x70040000
-#define TEGRA_USB1_BASE 0xC5000000
-#define TEGRA_USB3_BASE 0xC5008000
#define TEGRA_USB_ADDR_MASK 0xFFFFC000
#define NV_PA_SDRC_CS0 NV_PA_SDRAM_BASE
};
/* Address at which WB code runs, it must not overlap Bootrom's IRAM usage */
-#define AP20_WB_RUN_ADDRESS 0x40020000
+#define NV_WB_RUN_ADDRESS 0x40020000
#define NVBOOTINFOTABLE_BCTSIZE 0x38 /* BCT size in BIT in IRAM */
#define NVBOOTINFOTABLE_BCTPTR 0x3C /* BCT pointer in BIT in IRAM */
-#define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */
/* These are the available SKUs (product types) for Tegra */
enum {
#define PRM_RSTCTRL NV_PA_PMC_BASE
#endif
-#endif /* TEGRA20_H */
+#endif /* TEGRA_H */
/*
- * NVIDIA Tegra20 I2C controller
+ * NVIDIA Tegra I2C controller
*
* Copyright 2010-2011 NVIDIA Corporation
*
*/
int tegra_i2c_get_dvc_bus_num(void);
-#endif
+#endif /* _TEGRA_I2C_H_ */
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors.
+ * Copyright (c) 2010-2012 NVIDIA Corporation <www.nvidia.com>
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* Tegra20 clock PLL tables */
+
+#ifndef _CLOCK_TABLES_H_
+#define _CLOCK_TABLES_H_
+
+/* The PLLs supported by the hardware */
+enum clock_id {
+ CLOCK_ID_FIRST,
+ CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
+ CLOCK_ID_MEMORY,
+ CLOCK_ID_PERIPH,
+ CLOCK_ID_AUDIO,
+ CLOCK_ID_USB,
+ CLOCK_ID_DISPLAY,
+
+ /* now the simple ones */
+ CLOCK_ID_FIRST_SIMPLE,
+ CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
+ CLOCK_ID_EPCI,
+ CLOCK_ID_SFROM32KHZ,
+
+ /* These are the base clocks (inputs to the Tegra SOC) */
+ CLOCK_ID_32KHZ,
+ CLOCK_ID_OSC,
+
+ CLOCK_ID_COUNT, /* number of clocks */
+ CLOCK_ID_NONE = -1,
+};
+
+/* The clocks supported by the hardware */
+enum periph_id {
+ PERIPH_ID_FIRST,
+
+ /* Low word: 31:0 */
+ PERIPH_ID_CPU = PERIPH_ID_FIRST,
+ PERIPH_ID_RESERVED1,
+ PERIPH_ID_RESERVED2,
+ PERIPH_ID_AC97,
+ PERIPH_ID_RTC,
+ PERIPH_ID_TMR,
+ PERIPH_ID_UART1,
+ PERIPH_ID_UART2,
+
+ /* 8 */
+ PERIPH_ID_GPIO,
+ PERIPH_ID_SDMMC2,
+ PERIPH_ID_SPDIF,
+ PERIPH_ID_I2S1,
+ PERIPH_ID_I2C1,
+ PERIPH_ID_NDFLASH,
+ PERIPH_ID_SDMMC1,
+ PERIPH_ID_SDMMC4,
+
+ /* 16 */
+ PERIPH_ID_TWC,
+ PERIPH_ID_PWM,
+ PERIPH_ID_I2S2,
+ PERIPH_ID_EPP,
+ PERIPH_ID_VI,
+ PERIPH_ID_2D,
+ PERIPH_ID_USBD,
+ PERIPH_ID_ISP,
+
+ /* 24 */
+ PERIPH_ID_3D,
+ PERIPH_ID_IDE,
+ PERIPH_ID_DISP2,
+ PERIPH_ID_DISP1,
+ PERIPH_ID_HOST1X,
+ PERIPH_ID_VCP,
+ PERIPH_ID_RESERVED30,
+ PERIPH_ID_CACHE2,
+
+ /* Middle word: 63:32 */
+ PERIPH_ID_MEM,
+ PERIPH_ID_AHBDMA,
+ PERIPH_ID_APBDMA,
+ PERIPH_ID_RESERVED35,
+ PERIPH_ID_KBC,
+ PERIPH_ID_STAT_MON,
+ PERIPH_ID_PMC,
+ PERIPH_ID_FUSE,
+
+ /* 40 */
+ PERIPH_ID_KFUSE,
+ PERIPH_ID_SBC1,
+ PERIPH_ID_SNOR,
+ PERIPH_ID_SPI1,
+ PERIPH_ID_SBC2,
+ PERIPH_ID_XIO,
+ PERIPH_ID_SBC3,
+ PERIPH_ID_DVC_I2C,
+
+ /* 48 */
+ PERIPH_ID_DSI,
+ PERIPH_ID_TVO,
+ PERIPH_ID_MIPI,
+ PERIPH_ID_HDMI,
+ PERIPH_ID_CSI,
+ PERIPH_ID_TVDAC,
+ PERIPH_ID_I2C2,
+ PERIPH_ID_UART3,
+
+ /* 56 */
+ PERIPH_ID_RESERVED56,
+ PERIPH_ID_EMC,
+ PERIPH_ID_USB2,
+ PERIPH_ID_USB3,
+ PERIPH_ID_MPE,
+ PERIPH_ID_VDE,
+ PERIPH_ID_BSEA,
+ PERIPH_ID_BSEV,
+
+ /* Upper word 95:64 */
+ PERIPH_ID_SPEEDO,
+ PERIPH_ID_UART4,
+ PERIPH_ID_UART5,
+ PERIPH_ID_I2C3,
+ PERIPH_ID_SBC4,
+ PERIPH_ID_SDMMC3,
+ PERIPH_ID_PCIE,
+ PERIPH_ID_OWR,
+
+ /* 72 */
+ PERIPH_ID_AFI,
+ PERIPH_ID_CORESIGHT,
+ PERIPH_ID_RESERVED74,
+ PERIPH_ID_AVPUCQ,
+ PERIPH_ID_RESERVED76,
+ PERIPH_ID_RESERVED77,
+ PERIPH_ID_RESERVED78,
+ PERIPH_ID_RESERVED79,
+
+ /* 80 */
+ PERIPH_ID_RESERVED80,
+ PERIPH_ID_RESERVED81,
+ PERIPH_ID_RESERVED82,
+ PERIPH_ID_RESERVED83,
+ PERIPH_ID_IRAMA,
+ PERIPH_ID_IRAMB,
+ PERIPH_ID_IRAMC,
+ PERIPH_ID_IRAMD,
+
+ /* 88 */
+ PERIPH_ID_CRAM2,
+ PERIPH_ID_SYNC_CLK_DOUBLER,
+ PERIPH_ID_CLK_M_DOUBLER,
+ PERIPH_ID_RESERVED91,
+ PERIPH_ID_SUS_OUT,
+ PERIPH_ID_DEV2_OUT,
+ PERIPH_ID_DEV1_OUT,
+
+ PERIPH_ID_COUNT,
+ PERIPH_ID_NONE = -1,
+};
+
+enum pll_out_id {
+ PLL_OUT1,
+ PLL_OUT2,
+ PLL_OUT3,
+ PLL_OUT4
+};
+
+/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
+#define PERIPH_REG(id) ((id) >> 5)
+
+/* Mask value for a clock (within PERIPH_REG(id)) */
+#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
+
+/* return 1 if a PLL ID is in range, and not a simple PLL */
+#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \
+ (id) < CLOCK_ID_FIRST_SIMPLE)
+
+#endif /* _CLOCK_TABLES_H_ */
* MA 02111-1307 USA
*/
-/* Tegra2 clock control functions */
+/* Tegra20 clock control functions */
-#ifndef _CLOCK_H
-#define _CLOCK_H
+#ifndef _TEGRA20_CLOCK_H
+#define _TEGRA20_CLOCK_H
-/* Set of oscillator frequencies supported in the internal API. */
-enum clock_osc_freq {
- /* All in MHz, so 13_0 is 13.0MHz */
- CLOCK_OSC_FREQ_13_0,
- CLOCK_OSC_FREQ_19_2,
- CLOCK_OSC_FREQ_12_0,
- CLOCK_OSC_FREQ_26_0,
+#include <asm/arch-tegra/clock.h>
- CLOCK_OSC_FREQ_COUNT,
-};
-
-/* The PLLs supported by the hardware */
-enum clock_id {
- CLOCK_ID_FIRST,
- CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
- CLOCK_ID_MEMORY,
- CLOCK_ID_PERIPH,
- CLOCK_ID_AUDIO,
- CLOCK_ID_USB,
- CLOCK_ID_DISPLAY,
-
- /* now the simple ones */
- CLOCK_ID_FIRST_SIMPLE,
- CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
- CLOCK_ID_EPCI,
- CLOCK_ID_SFROM32KHZ,
-
- /* These are the base clocks (inputs to the Tegra SOC) */
- CLOCK_ID_32KHZ,
- CLOCK_ID_OSC,
-
- CLOCK_ID_COUNT, /* number of clocks */
- CLOCK_ID_NONE = -1,
-};
-
-/* The clocks supported by the hardware */
-enum periph_id {
- PERIPH_ID_FIRST,
-
- /* Low word: 31:0 */
- PERIPH_ID_CPU = PERIPH_ID_FIRST,
- PERIPH_ID_RESERVED1,
- PERIPH_ID_RESERVED2,
- PERIPH_ID_AC97,
- PERIPH_ID_RTC,
- PERIPH_ID_TMR,
- PERIPH_ID_UART1,
- PERIPH_ID_UART2,
-
- /* 8 */
- PERIPH_ID_GPIO,
- PERIPH_ID_SDMMC2,
- PERIPH_ID_SPDIF,
- PERIPH_ID_I2S1,
- PERIPH_ID_I2C1,
- PERIPH_ID_NDFLASH,
- PERIPH_ID_SDMMC1,
- PERIPH_ID_SDMMC4,
-
- /* 16 */
- PERIPH_ID_TWC,
- PERIPH_ID_PWM,
- PERIPH_ID_I2S2,
- PERIPH_ID_EPP,
- PERIPH_ID_VI,
- PERIPH_ID_2D,
- PERIPH_ID_USBD,
- PERIPH_ID_ISP,
-
- /* 24 */
- PERIPH_ID_3D,
- PERIPH_ID_IDE,
- PERIPH_ID_DISP2,
- PERIPH_ID_DISP1,
- PERIPH_ID_HOST1X,
- PERIPH_ID_VCP,
- PERIPH_ID_RESERVED30,
- PERIPH_ID_CACHE2,
-
- /* Middle word: 63:32 */
- PERIPH_ID_MEM,
- PERIPH_ID_AHBDMA,
- PERIPH_ID_APBDMA,
- PERIPH_ID_RESERVED35,
- PERIPH_ID_KBC,
- PERIPH_ID_STAT_MON,
- PERIPH_ID_PMC,
- PERIPH_ID_FUSE,
-
- /* 40 */
- PERIPH_ID_KFUSE,
- PERIPH_ID_SBC1,
- PERIPH_ID_SNOR,
- PERIPH_ID_SPI1,
- PERIPH_ID_SBC2,
- PERIPH_ID_XIO,
- PERIPH_ID_SBC3,
- PERIPH_ID_DVC_I2C,
-
- /* 48 */
- PERIPH_ID_DSI,
- PERIPH_ID_TVO,
- PERIPH_ID_MIPI,
- PERIPH_ID_HDMI,
- PERIPH_ID_CSI,
- PERIPH_ID_TVDAC,
- PERIPH_ID_I2C2,
- PERIPH_ID_UART3,
-
- /* 56 */
- PERIPH_ID_RESERVED56,
- PERIPH_ID_EMC,
- PERIPH_ID_USB2,
- PERIPH_ID_USB3,
- PERIPH_ID_MPE,
- PERIPH_ID_VDE,
- PERIPH_ID_BSEA,
- PERIPH_ID_BSEV,
-
- /* Upper word 95:64 */
- PERIPH_ID_SPEEDO,
- PERIPH_ID_UART4,
- PERIPH_ID_UART5,
- PERIPH_ID_I2C3,
- PERIPH_ID_SBC4,
- PERIPH_ID_SDMMC3,
- PERIPH_ID_PCIE,
- PERIPH_ID_OWR,
-
- /* 72 */
- PERIPH_ID_AFI,
- PERIPH_ID_CORESIGHT,
- PERIPH_ID_RESERVED74,
- PERIPH_ID_AVPUCQ,
- PERIPH_ID_RESERVED76,
- PERIPH_ID_RESERVED77,
- PERIPH_ID_RESERVED78,
- PERIPH_ID_RESERVED79,
-
- /* 80 */
- PERIPH_ID_RESERVED80,
- PERIPH_ID_RESERVED81,
- PERIPH_ID_RESERVED82,
- PERIPH_ID_RESERVED83,
- PERIPH_ID_IRAMA,
- PERIPH_ID_IRAMB,
- PERIPH_ID_IRAMC,
- PERIPH_ID_IRAMD,
-
- /* 88 */
- PERIPH_ID_CRAM2,
-
- PERIPH_ID_COUNT,
- PERIPH_ID_NONE = -1,
-};
-
-/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
-#define PERIPH_REG(id) ((id) >> 5)
-
-/* Mask value for a clock (within PERIPH_REG(id)) */
-#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
-
-/* return 1 if a PLL ID is in range, and not a simple PLL */
-#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \
- (id) < CLOCK_ID_FIRST_SIMPLE)
-
-/* PLL stabilization delay in usec */
-#define CLOCK_PLL_STABLE_DELAY_US 300
-
-/* return the current oscillator clock frequency */
-enum clock_osc_freq clock_get_osc_freq(void);
-
-/**
- * Start PLL using the provided configuration parameters.
- *
- * @param id clock id
- * @param divm input divider
- * @param divn feedback divider
- * @param divp post divider 2^n
- * @param cpcon charge pump setup control
- * @param lfcon loop filter setup control
- *
- * @returns monotonic time in us that the PLL will be stable
- */
-unsigned long clock_start_pll(enum clock_id id, u32 divm, u32 divn,
- u32 divp, u32 cpcon, u32 lfcon);
-
-/**
- * Read low-level parameters of a PLL.
- *
- * @param id clock id to read (note: USB is not supported)
- * @param divm returns input divider
- * @param divn returns feedback divider
- * @param divp returns post divider 2^n
- * @param cpcon returns charge pump setup control
- * @param lfcon returns loop filter setup control
- *
- * @returns 0 if ok, -1 on error (invalid clock id)
- */
-int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
- u32 *divp, u32 *cpcon, u32 *lfcon);
-
-/*
- * Enable a clock
- *
- * @param id clock id
- */
-void clock_enable(enum periph_id clkid);
-
-/*
- * Disable a clock
- *
- * @param id clock id
- */
-void clock_disable(enum periph_id clkid);
-
-/*
- * Set whether a clock is enabled or disabled.
- *
- * @param id clock id
- * @param enable 1 to enable, 0 to disable
- */
-void clock_set_enable(enum periph_id clkid, int enable);
-
-/**
- * Reset a peripheral. This puts it in reset, waits for a delay, then takes
- * it out of reset and waits for th delay again.
- *
- * @param periph_id peripheral to reset
- * @param us_delay time to delay in microseconds
- */
-void reset_periph(enum periph_id periph_id, int us_delay);
-
-/**
- * Put a peripheral into or out of reset.
- *
- * @param periph_id peripheral to reset
- * @param enable 1 to put into reset, 0 to take out of reset
- */
-void reset_set_enable(enum periph_id periph_id, int enable);
-
-
-/* CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET/CLR_0 */
-enum crc_reset_id {
- /* Things we can hold in reset for each CPU */
- crc_rst_cpu = 1,
- crc_rst_de = 1 << 2, /* What is de? */
- crc_rst_watchdog = 1 << 3,
- crc_rst_debug = 1 << 4,
-};
-
-/**
- * Put parts of the CPU complex into or out of reset.\
- *
- * @param cpu cpu number (0 or 1 on Tegra2)
- * @param which which parts of the complex to affect (OR of crc_reset_id)
- * @param reset 1 to assert reset, 0 to de-assert
- */
-void reset_cmplx_set_enable(int cpu, int which, int reset);
-
-/**
- * Set the source for a peripheral clock. This plus the divisor sets the
- * clock rate. You need to look up the datasheet to see the meaning of the
- * source parameter as it changes for each peripheral.
- *
- * Warning: This function is only for use pre-relocation. Please use
- * clock_start_periph_pll() instead.
- *
- * @param periph_id peripheral to adjust
- * @param source source clock (0, 1, 2 or 3)
- */
-void clock_ll_set_source(enum periph_id periph_id, unsigned source);
-
-/**
- * Set the source and divisor for a peripheral clock. This sets the
- * clock rate. You need to look up the datasheet to see the meaning of the
- * source parameter as it changes for each peripheral.
- *
- * Warning: This function is only for use pre-relocation. Please use
- * clock_start_periph_pll() instead.
- *
- * @param periph_id peripheral to adjust
- * @param source source clock (0, 1, 2 or 3)
- * @param divisor divisor value to use
- */
-void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
- unsigned divisor);
-
-/**
- * Start a peripheral PLL clock at the given rate. This also resets the
- * peripheral.
- *
- * @param periph_id peripheral to start
- * @param parent PLL id of required parent clock
- * @param rate Required clock rate in Hz
- * @return rate selected in Hz, or -1U if something went wrong
- */
-unsigned clock_start_periph_pll(enum periph_id periph_id,
- enum clock_id parent, unsigned rate);
-
-/**
- * Returns the rate of a peripheral clock in Hz. Since the caller almost
- * certainly knows the parent clock (having just set it) we require that
- * this be passed in so we don't need to work it out.
- *
- * @param periph_id peripheral to start
- * @param parent PLL id of parent clock (used to calculate rate, you
- * must know this!)
- * @return clock rate of peripheral in Hz
- */
-unsigned long clock_get_periph_rate(enum periph_id periph_id,
- enum clock_id parent);
-
-/**
- * Adjust peripheral PLL clock to the given rate. This does not reset the
- * peripheral. If a second stage divisor is not available, pass NULL for
- * extra_div. If it is available, then this parameter will return the
- * divisor selected (which will be a power of 2 from 1 to 256).
- *
- * @param periph_id peripheral to start
- * @param parent PLL id of required parent clock
- * @param rate Required clock rate in Hz
- * @param extra_div value for the second-stage divisor (NULL if one is
- not available)
- * @return rate selected in Hz, or -1U if something went wrong
- */
-unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
- enum clock_id parent, unsigned rate, int *extra_div);
-
-/**
- * Returns the clock rate of a specified clock, in Hz.
- *
- * @param parent PLL id of clock to check
- * @return rate of clock in Hz
- */
-unsigned clock_get_rate(enum clock_id clkid);
-
-/**
- * Start up a UART using low-level calls
- *
- * Prior to relocation clock_start_periph_pll() cannot be called. This
- * function provides a way to set up a UART using low-level calls which
- * do not require BSS.
- *
- * @param periph_id Peripheral ID of UART to enable (e,g, PERIPH_ID_UART1)
- */
-void clock_ll_start_uart(enum periph_id periph_id);
-
-/**
- * Decode a peripheral ID from a device tree node.
- *
- * This works by looking up the peripheral's 'clocks' node and reading out
- * the second cell, which is the clock number / peripheral ID.
- *
- * @param blob FDT blob to use
- * @param node Node to look at
- * @return peripheral ID, or PERIPH_ID_NONE if none
- */
-enum periph_id clock_decode_periph_id(const void *blob, int node);
-
-/**
- * Checks if the oscillator bypass is enabled (XOBP bit)
- *
- * @return 1 if bypass is enabled, 0 if not
- */
-int clock_get_osc_bypass(void);
-
-/*
- * Checks that clocks are valid and prints a warning if not
- *
- * @return 0 if ok, -1 on error
- */
-int clock_verify(void);
-
-/* Initialize the clocks */
-void clock_init(void);
-
-/* Initialize the PLLs */
-void clock_early_init(void);
-
-#endif
+#endif /* _TEGRA20_CLOCK_H */
/* NAND flags */
FUNCMUX_NDFLASH_ATC = 0,
+ FUNCMUX_NDFLASH_KBC_8_BIT,
};
/**
* MA 02111-1307 USA
*/
-#ifndef _TEGRA_GPIO_H_
-#define _TEGRA_GPIO_H_
+#ifndef _TEGRA20_GPIO_H_
+#define _TEGRA20_GPIO_H_
/*
* The Tegra 2x GPIO controller has 224 GPIOs arranged in 7 banks of 4 ports,
*/
#define TEGRA_GPIO_PORTS 4 /* number of ports per bank */
#define TEGRA_GPIO_BANKS 7 /* number of banks */
-#define MAX_NUM_GPIOS (TEGRA_GPIO_PORTS * TEGRA_GPIO_BANKS * 8)
-#define GPIO_NAME_SIZE 20 /* gpio_request max label len */
+
+#include <asm/arch-tegra/gpio.h>
/* GPIO Controller registers for a single bank */
struct gpio_ctlr_bank {
struct gpio_ctlr_bank gpio_bank[TEGRA_GPIO_BANKS];
};
-#define GPIO_BANK(x) ((x) >> 5)
-#define GPIO_PORT(x) (((x) >> 3) & 0x3)
-#define GPIO_FULLPORT(x) ((x) >> 3)
-#define GPIO_BIT(x) ((x) & 0x7)
-
enum gpio_pin {
GPIO_PA0 = 0, /* pin 0 */
GPIO_PA1,
GPIO_PBB7, /* pin 223 */
};
-/*
- * Tegra20-specific GPIO API
- */
-
-void gpio_info(void);
-
-#define gpio_status() gpio_info()
-#endif /* TEGRA_GPIO_H_ */
+#endif /* TEGRA20_GPIO_H_ */
/*
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
+ * (C) Copyright 2010,2011
+ * NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
* project.
* MA 02111-1307 USA
*/
-#ifndef _BOARD_H_
-#define _BOARD_H_
+#ifndef _TEGRA20_H_
+#define _TEGRA20_H_
-void gpio_config_uart(void);
-void gpio_early_init(void);
-void gpio_early_init_uart(void);
+#define NV_PA_SDRAM_BASE 0x00000000
-/*
- * Set up any pin muxing needed for USB (for now, since fdt doesn't support
- * it). Boards can overwrite the default fucction which does nothing.
- */
-void pin_mux_usb(void);
+#include <asm/arch-tegra/tegra.h>
+
+#define TEGRA_USB1_BASE 0xC5000000
+#define TEGRA_USB3_BASE 0xC5008000
+
+#define BCT_ODMDATA_OFFSET 4068 /* 12 bytes from end of BCT */
-#endif /* BOARD_H */
+#endif /* TEGRA20_H */
/* 0x410 */
uint usb1_legacy_ctrl;
- uint reserved12[3];
+ uint reserved12[4];
- /* 0x420 */
- uint reserved13[56];
+ /* 0x424 */
+ uint ulpi_timing_ctrl_0;
+ uint ulpi_timing_ctrl_1;
+ uint reserved13[53];
/* 0x500 */
uint reserved14[64 * 3];
#define VBUS_SENSE_CTL_AB_SESS_VLD 2
#define VBUS_SENSE_CTL_A_SESS_VLD 3
+/* USB2_IF_ULPI_TIMING_CTRL_0 */
+#define ULPI_OUTPUT_PINMUX_BYP (1 << 10)
+#define ULPI_CLKOUT_PINMUX_BYP (1 << 11)
+
+/* USB2_IF_ULPI_TIMING_CTRL_1 */
+#define ULPI_DATA_TRIMMER_LOAD (1 << 0)
+#define ULPI_DATA_TRIMMER_SEL(x) (((x) & 0x7) << 1)
+#define ULPI_STPDIRNXT_TRIMMER_LOAD (1 << 16)
+#define ULPI_STPDIRNXT_TRIMMER_SEL(x) (((x) & 0x7) << 17)
+#define ULPI_DIR_TRIMMER_LOAD (1 << 24)
+#define ULPI_DIR_TRIMMER_SEL(x) (((x) & 0x7) << 25)
+
/* USBx_IF_USB_SUSP_CTRL_0 */
+#define ULPI_PHY_ENB (1 << 13)
#define UTMIP_PHY_ENB (1 << 12)
#define UTMIP_RESET (1 << 11)
#define USB_PHY_CLK_VALID (1 << 7)
+#define USB_SUSP_CLR (1 << 5)
/* USBx_UTMIP_MISC_CFG1 */
#define UTMIP_PLLU_STABLE_COUNT_SHIFT 6
/* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
#define PTS_SHIFT 30
#define PTS_MASK (3U << PTS_SHIFT)
-#define PTS_UTMI 0
+#define PTS_UTMI 0
#define PTS_RESERVED 1
-#define PTS_ULP 2
+#define PTS_ULPI 2
#define PTS_ICUSB_SER 3
#define STS (1 << 29)
+#define WKOC (1 << 22)
+#define WKDS (1 << 21)
+#define WKCN (1 << 20)
/* USBx_UTMIP_XCVR_CFG0_0 */
#define UTMIP_FORCE_PD_POWERDOWN (1 << 14)
* @param hcor returns start address of EHCI HCOR registers
* @return 0 if ok, -1 on error (generally invalid port number)
*/
-int tegrausb_start_port(unsigned portnum, u32 *hccr, u32 *hcor);
+int tegrausb_start_port(int portnum, u32 *hccr, u32 *hcor);
/**
* Stop the current port
*
* @return 0 if ok, -1 if no port was active
*/
-int tegrausb_stop_port(void);
+int tegrausb_stop_port(int portnum);
#endif /* _TEGRA_USB_H_ */
u32 insreg08; /* 0xb0 */
};
-int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata);
+/*
+ * FIXME: forward declaration of this structs needed because omap got the
+ * ehci implementation backwards. move out ehci_hcd_x from board files
+ */
+struct ehci_hccr;
+struct ehci_hcor;
+
+int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor);
int omap_ehci_hcd_stop(void);
#endif /* _OMAP_COMMON_EHCI_H_ */
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
unsigned long precon_buf_idx; /* Pre-Console buffer index */
#define _U_BOOT_H_ 1
typedef struct bd_info {
- int bi_baudrate; /* serial console baudrate */
+ unsigned int bi_baudrate; /* serial console baudrate */
ulong bi_arch_number; /* unique id for this board */
ulong bi_boot_params; /* where this board expects params */
unsigned long bi_arm_freq; /* arm frequency */
#include <miiphy.h>
#endif
-#ifdef CONFIG_DRIVER_SMC91111
-#include "../drivers/net/smc91111.h"
-#endif
-#ifdef CONFIG_DRIVER_LAN91C96
-#include "../drivers/net/lan91c96.h"
-#endif
-
DECLARE_GLOBAL_DATA_PTR;
ulong monitor_flash_len;
#ifdef CONFIG_PRAM
ulong reg;
#endif
+ void *new_fdt = NULL;
+ size_t fdt_size = 0;
bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
debug("Reserving %zu Bytes for Global Data at: %08lx\n",
sizeof (gd_t), addr_sp);
+#if defined(CONFIG_OF_SEPARATE) && defined(CONFIG_OF_CONTROL)
+ /*
+ * If the device tree is sitting immediate above our image then we
+ * must relocate it. If it is embedded in the data section, then it
+ * will be relocated with other data.
+ */
+ if (gd->fdt_blob) {
+ fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
+
+ addr_sp -= fdt_size;
+ new_fdt = (void *)addr_sp;
+ debug("Reserving %zu Bytes for FDT at: %08lx\n",
+ fdt_size, addr_sp);
+ }
+#endif
+
/* setup stackpointer for exeptions */
gd->irq_sp = addr_sp;
#ifdef CONFIG_USE_IRQ
gd->start_addr_sp = addr_sp;
gd->reloc_off = addr - _TEXT_BASE;
debug("relocation Offset is: %08lx\n", gd->reloc_off);
+ if (new_fdt) {
+ memcpy(new_fdt, gd->fdt_blob, fdt_size);
+ gd->fdt_blob = new_fdt;
+ }
memcpy(id, (void *)gd, sizeof(gd_t));
relocate_code(addr_sp, id, addr);
#ifdef CONFIG_CLOCKS
set_cpu_clk_info(); /* Setup clock information */
#endif
-#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
-#endif
debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
/* enable exceptions */
enable_interrupts();
- /* Perform network card initialisation if necessary */
-#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96)
- /* XXX: this needs to be moved to board init */
- if (getenv("ethaddr")) {
- uchar enetaddr[6];
- eth_getenv_enetaddr("ethaddr", enetaddr);
- smc_set_mac_addr(enetaddr);
- }
-#endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */
-
/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);
{
printf("\nStarting kernel ...\n\n");
bootstage_mark_name(BOOTSTAGE_ID_BOOTM_HANDOFF, "start_kernel");
+#ifdef CONFIG_BOOTSTAGE_FDT
+ bootstage_fdt_add_report();
+#endif
#ifdef CONFIG_BOOTSTAGE_REPORT
bootstage_report();
#endif
void do_data_abort (struct pt_regs *pt_regs)
{
- printf ("data abort\n");
+ printf ("data abort\n\n MAYBE you should read doc/README.arm-unaligned-accesses\n\n");
show_regs (pt_regs);
bad_mode ();
}
}
. = ALIGN(4);
- __u_boot_cmd_start = .;
- .u_boot_cmd : {
- KEEP(*(.u_boot_cmd))
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
}
- __u_boot_cmd_end = .;
. = ALIGN(4);
_got = .;
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long stack_end; /* highest stack address */
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
#define __ASM_U_BOOT_H__ 1
typedef struct bd_info {
- unsigned long bi_baudrate;
+ unsigned int bi_baudrate;
unsigned char bi_phy_id[4];
unsigned long bi_board_number;
void *bi_boot_params;
/*
* We have to relocate the command table manually
*/
- fixup_cmdtable(&__u_boot_cmd_start,
- (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+ fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+ ll_entry_count(cmd_tbl_t, cmd));
#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
/* there are some other pointer constants we must deal with */
}
#ifdef CONFIG_UART_CONSOLE_IS_JTAG
+#include <serial.h>
/* Since the JTAG is always available (at power on), allow it to fake a UART */
-void serial_set_baud(uint32_t baud) {}
-void serial_setbrg(void) {}
-int serial_init(void) { return 0; }
-void serial_putc(const char c) __attribute__((alias("jtag_putc")));
-void serial_puts(const char *s) __attribute__((alias("jtag_puts")));
-int serial_tstc(void) __attribute__((alias("jtag_tstc")));
-int serial_getc(void) __attribute__((alias("jtag_getc")));
+void jtag_serial_setbrg(void)
+{
+}
+
+int jtag_serial_init(void)
+{
+ return 0;
+}
+
+static struct serial_device serial_jtag_drv = {
+ .name = "jtag",
+ .start = jtag_serial_init,
+ .stop = NULL,
+ .setbrg = jtag_serial_setbrg,
+ .putc = jtag_putc,
+ .puts = jtag_puts,
+ .tstc = jtag_tstc,
+ .getc = jtag_getc,
+};
+
+void bfin_jtag_initialize(void)
+{
+ serial_register(&serial_jtag_drv);
+}
+
+struct serial_device *default_serial_console(void)
+{
+ return &serial_jtag_drv;
+}
#endif
\
struct serial_device bfin_serial##n##_device = { \
.name = "bfin_uart"#n, \
- .init = uart##n##_init, \
- .uninit = uart##n##_uninit, \
+ .start = uart##n##_init, \
+ .stop = uart##n##_uninit, \
.setbrg = uart##n##_setbrg, \
.getc = uart##n##_getc, \
.tstc = uart##n##_tstc, \
#endif
}
-void serial_register_bfin_uart(void)
+void bfin_serial_initialize(void)
{
#ifdef UART0_DLL
serial_register(&bfin_serial0_device);
CONSTRUCTORS
} >ram_data
- .u_boot_cmd :
- {
- ___u_boot_cmd_start = .;
- *(.u_boot_cmd)
- ___u_boot_cmd_end = .;
+
+ .u_boot_list : {
+ #include <u-boot.lst>
} >ram_data
.text_l1 :
#define __ASM_BLACKFIN_CONFIG_PRE_H__
/* Misc helper functions */
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
/* Bootmode defines -- your config needs to select this via CONFIG_BFIN_BOOT_MODE.
bd_t *bd;
unsigned long flags;
unsigned long board_type;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
unsigned long precon_buf_idx; /* Pre-Console buffer index */
#define _U_BOOT_H_ 1
typedef struct bd_info {
- int bi_baudrate; /* serial console baudrate */
+ unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
phys_size_t bi_memsize; /* size of DRAM memory in bytes */
printf(" gd: %p\n", gd);
printf(" |-flags: %lx\n", gd->flags);
printf(" |-board_type: %lx\n", gd->board_type);
- printf(" |-baudrate: %lu\n", gd->baudrate);
+ printf(" |-baudrate: %u\n", gd->baudrate);
printf(" |-have_console: %lx\n", gd->have_console);
printf(" |-ram_size: %lx\n", gd->ram_size);
printf(" |-env_addr: %lx\n", gd->env_addr);
gd->bd = bd;
bd->bi_r_version = version_string;
- bd->bi_cpu = MK_STR(CONFIG_BFIN_CPU);
+ bd->bi_cpu = __stringify(CONFIG_BFIN_CPU);
bd->bi_board_name = BFIN_BOARD_NAME;
bd->bi_vco = get_vco();
bd->bi_cclk = get_cclk();
init_baudrate();
serial_early_puts("Serial init\n");
serial_init();
-#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
-#endif
serial_early_puts("Console init flash\n");
console_init_f();
serial_early_puts("End of early debugging\n");
/* exception code */
.globl _fault
_fault:
- jmp _fault
+ bra _fault
.globl _exc_handler
_exc_handler:
/* exception code */
.globl _fault
_fault:
- jmp _fault
+ bra _fault
.globl _exc_handler
_exc_handler:
/* exception code */
.globl _fault
_fault:
- jmp _fault
+ bra _fault
.globl _exc_handler
_exc_handler:
/* exception code */
.globl _fault
_fault:
- jmp _fault
+ bra _fault
.globl _exc_handler
_exc_handler:
#include <asm/processor.h>
#include <asm/rtc.h>
#include <asm/io.h>
+#include <linux/compiler.h>
#if defined(CONFIG_CMD_NET)
#include <config.h>
{
scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
- fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+ fbcs_t *fbcs __maybe_unused = (fbcs_t *) MMAP_FBCS;
out_be32(&scm1->mpr, 0x77777777);
out_be32(&scm1->pacra, 0);
pll_t *pll = (pll_t *)MMAP_PLL;
int pllmult_nopci[] = { 20, 10, 24, 18, 12, 6, 16, 8 };
int pllmult_pci[] = { 12, 6, 16, 8 };
- int vco = 0, bPci, temp, fbtemp, pcrvalue;
+ int vco = 0, temp, fbtemp, pcrvalue;
int *pPllmult = NULL;
u16 fbpll_mask;
+#ifdef CONFIG_PCI
+ int bPci;
+#endif
#ifdef CONFIG_M54455EVB
u8 *cpld = (u8 *)(CONFIG_SYS_CS2_BASE + 3);
((in_be16(&ccm->ccr) & CCM_CCR_360_FBCONFIG_MASK) == 0x0060)) {
pPllmult = &pllmult_pci[0];
fbpll_mask = 3; /* 11b */
+#ifdef CONFIG_PCI
bPci = 1;
+#endif
} else {
pPllmult = &pllmult_nopci[0];
fbpll_mask = 7; /* 111b */
#ifdef CONFIG_PCI
gd->pci_clk = 0;
-#endif
bPci = 0;
+#endif
}
#ifdef CONFIG_M54455EVB
move.l #__got_start, %a5 /* put relocation table address to a5 */
- bsr cpu_init_f /* run low-level CPU init code (from flash) */
- bsr board_init_f /* run low-level board init code (from flash) */
+ jbsr cpu_init_f /* run low-level CPU init code (from flash) */
+ jbsr board_init_f /* run low-level board init code (from flash) */
/* board_init_f() does not return */
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long bus_clk;
#ifdef CONFIG_PCI
unsigned long bi_vcofreq; /* vco Freq in MHz */
unsigned long bi_flbfreq; /* Flexbus Freq in MHz */
#endif
- unsigned long bi_baudrate; /* Console Baudrate */
+ unsigned int bi_baudrate; /* Console Baudrate */
} bd_t;
#endif /* __ASSEMBLY__ */
#include <command.h>
#include <malloc.h>
#include <stdio_dev.h>
+#include <linux/compiler.h>
#include <asm/immap.h>
*/
void board_init_r (gd_t *id, ulong dest_addr)
{
- char *s;
+ char *s __maybe_unused;
bd_t *bd;
#ifndef CONFIG_ENV_IS_NOWHERE
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
-#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
-#endif
debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
/*
* We have to relocate the command table manually
*/
- fixup_cmdtable(&__u_boot_cmd_start,
- (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+ fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+ ll_entry_count(cmd_tbl_t, cmd));
#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
/* there are some other pointer constants we must deal with */
__data_end = .;
}
- .u_boot_cmd ALIGN(0x4):
- {
- . = .;
- __u_boot_cmd_start = .;
- *(.u_boot_cmd)
- __u_boot_cmd_end = .;
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
}
.bss ALIGN(0x4):
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
unsigned long precon_buf_idx; /* Pre-Console buffer index */
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
- unsigned long bi_baudrate; /* Console Baudrate */
+ unsigned int bi_baudrate; /* Console Baudrate */
} bd_t;
/* For image.h:image_check_target_arch() */
*/
mem_malloc_init (CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
-#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
-#endif
for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
WATCHDOG_RESET ();
LIB = $(obj)lib$(SOC).o
-COBJS = au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o
+COBJS = au1x00_eth.o au1x00_serial.o au1x00_usb_ohci.o au1x00_ide.o
SRCS := $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
/*
- * (C) Copyright 2005
+ * (C) Copyright 2000-2011
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
+ *
*/
#include <common.h>
+#include <ide.h>
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * flash_init()
- *
- * sets up flash_info and returns size of FLASH (bytes)
- */
-unsigned long flash_init (void)
-{
- printf ("Skipping flash_init\n");
- return (0);
-}
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+/* AU1X00 swaps data in big-endian mode, enforce little-endian function */
+void ide_input_swap_data(int dev, ulong *sect_buf, int words)
{
- printf ("write_buff not implemented\n");
- return (-1);
+ ide_input_data(dev, sect_buf, words);
}
#include <config.h>
#include <common.h>
#include <asm/au1x00.h>
+#include <serial.h>
+#include <linux/compiler.h>
/******************************************************************************
*
* RETURNS: N/A
*/
-int serial_init (void)
+static int au1x00_serial_init(void)
{
volatile u32 *uart_fifoctl = (volatile u32*)(UART0_ADDR+UART_FCR);
volatile u32 *uart_enable = (volatile u32*)(UART0_ADDR+UART_ENABLE);
}
-void serial_setbrg (void)
+static void au1x00_serial_setbrg(void)
{
volatile u32 *uart_clk = (volatile u32*)(UART0_ADDR+UART_CLK);
volatile u32 *uart_lcr = (volatile u32*)(UART0_ADDR+UART_LCR);
*uart_lcr = UART_LCR_WLEN8;
}
-void serial_putc (const char c)
+static void au1x00_serial_putc(const char c)
{
volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
volatile u32 *uart_tx = (volatile u32*)(UART0_ADDR+UART_TX);
- if (c == '\n') serial_putc ('\r');
+ if (c == '\n')
+ au1x00_serial_putc('\r');
/* Wait for fifo to shift out some bytes */
while((*uart_lsr&UART_LSR_THRE)==0);
*uart_tx = (u32)c;
}
-void serial_puts (const char *s)
-{
- while (*s)
- {
- serial_putc (*s++);
- }
-}
-
-int serial_getc (void)
+static int au1x00_serial_getc(void)
{
volatile u32 *uart_rx = (volatile u32*)(UART0_ADDR+UART_RX);
char c;
return c;
}
-int serial_tstc (void)
+static int au1x00_serial_tstc(void)
{
volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR);
}
return 0;
}
+
+static struct serial_device au1x00_serial_drv = {
+ .name = "au1x00_serial",
+ .start = au1x00_serial_init,
+ .stop = NULL,
+ .setbrg = au1x00_serial_setbrg,
+ .putc = au1x00_serial_putc,
+ .puts = default_serial_puts,
+ .getc = au1x00_serial_getc,
+ .tstc = au1x00_serial_tstc,
+};
+
+void au1x00_serial_initialize(void)
+{
+ serial_register(&au1x00_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &au1x00_serial_drv;
+}
*/
static char ohci_inited = 0;
-int usb_lowlevel_init(void)
+int usb_lowlevel_init(int index, void **controller)
{
u32 pin_func;
u32 sys_freqctrl, sys_clksrc;
return -1;
}
-int usb_lowlevel_stop(void)
+int usb_lowlevel_stop(int index)
{
/* this gets called really early - before the controller has */
/* even been initialized! */
/* clear tag to invalidate */
PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, a1
-1: cache_op Index_Store_Tag_I t0
+1: cache_op INDEX_STORE_TAG_I t0
PTR_ADDU t0, a2
bne t0, t1, 1b
/* fill once, so data field parity is correct */
PTR_LI t0, INDEX_BASE
-2: cache_op Fill t0
+2: cache_op FILL t0
PTR_ADDU t0, a2
bne t0, t1, 2b
/* invalidate again - prudent but not strictly neccessary */
PTR_LI t0, INDEX_BASE
-1: cache_op Index_Store_Tag_I t0
+1: cache_op INDEX_STORE_TAG_I t0
PTR_ADDU t0, a2
bne t0, t1, 1b
9: jr ra
/* clear all tags */
PTR_LI t0, INDEX_BASE
PTR_ADDU t1, t0, a1
-1: cache_op Index_Store_Tag_D t0
+1: cache_op INDEX_STORE_TAG_D t0
PTR_ADDU t0, a2
bne t0, t1, 1b
/* load from each line (in cached space) */
bne t0, t1, 2b
/* clear all tags */
PTR_LI t0, INDEX_BASE
-1: cache_op Index_Store_Tag_D t0
+1: cache_op INDEX_STORE_TAG_D t0
PTR_ADDU t0, a2
bne t0, t1, 1b
9: jr ra
return;
while (1) {
- cache_op(Hit_Writeback_Inv_D, addr);
- cache_op(Hit_Invalidate_I, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
+ cache_op(HIT_INVALIDATE_I, addr);
if (addr == aend)
break;
addr += lsize;
unsigned long aend = (stop - 1) & ~(lsize - 1);
while (1) {
- cache_op(Hit_Writeback_Inv_D, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
if (addr == aend)
break;
addr += lsize;
unsigned long aend = (stop - 1) & ~(lsize - 1);
while (1) {
- cache_op(Hit_Invalidate_D, addr);
+ cache_op(HIT_INVALIDATE_D, addr);
if (addr == aend)
break;
addr += lsize;
#include <config.h>
#include <common.h>
#include <asm/inca-ip.h>
+#include <serial.h>
+#include <linux/compiler.h>
#include "asc_serial.h"
* RETURNS: N/A
*/
-int serial_init (void)
+static int asc_serial_init(void)
{
/* we have to set PMU.EN13 bit to enable an ASC device*/
INCAASC_PMU_ENABLE(13);
return 0;
}
-void serial_setbrg (void)
+static void asc_serial_setbrg(void)
{
ulong uiReloadValue, fdv;
ulong f_ASC;
return 0;
}
-void serial_putc (const char c)
+static void asc_serial_putc(const char c)
{
uint txFl = 0;
}
}
-void serial_puts (const char *s)
-{
- while (*s)
- {
- serial_putc (*s++);
- }
-}
-
-int serial_getc (void)
+static int asc_serial_getc(void)
{
ulong symbol_mask;
char c;
return c;
}
-int serial_tstc (void)
+static int asc_serial_tstc(void)
{
int res = 1;
return res;
}
+
+static struct serial_device asc_serial_drv = {
+ .name = "asc_serial",
+ .start = asc_serial_init,
+ .stop = NULL,
+ .setbrg = asc_serial_setbrg,
+ .putc = asc_serial_putc,
+ .puts = default_serial_puts,
+ .getc = asc_serial_getc,
+ .tstc = asc_serial_tstc,
+};
+
+void asc_serial_initialize(void)
+{
+ serial_register(&asc_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &asc_serial_drv;
+}
#
-# (C) Copyright 2000-2006
+# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
LIB = $(obj)lib$(CPU).o
START = start.o
-COBJS = cpu.o speed.o timer.o
+COBJS-y = cpu.o interrupts.o time.o cache.o
-SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
+SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
START := $(addprefix $(obj),$(START))
all: $(obj).depend $(START) $(LIB)
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
-
-#########################################################################
--- /dev/null
+/*
+ * Cache-handling routined for MIPS CPUs
+ *
+ * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/cacheops.h>
+
+#define RA t9
+
+/*
+ * 16kB is the maximum size of instruction and data caches on MIPS 4K,
+ * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience.
+ *
+ * Note that the above size is the maximum size of primary cache. U-Boot
+ * doesn't have L2 cache support for now.
+ */
+#define MIPS_MAX_CACHE_SIZE 0x10000
+
+#define INDEX_BASE CKSEG0
+
+ .macro cache_op op addr
+ .set push
+ .set noreorder
+ .set mips3
+ cache \op, 0(\addr)
+ .set pop
+ .endm
+
+ .macro f_fill64 dst, offset, val
+ LONG_S \val, (\offset + 0 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 1 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 2 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 3 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 4 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 5 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 6 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 7 * LONGSIZE)(\dst)
+#if LONGSIZE == 4
+ LONG_S \val, (\offset + 8 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 9 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 10 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 11 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 12 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 13 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 14 * LONGSIZE)(\dst)
+ LONG_S \val, (\offset + 15 * LONGSIZE)(\dst)
+#endif
+ .endm
+
+/*
+ * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz)
+ */
+LEAF(mips_init_icache)
+ blez a1, 9f
+ mtc0 zero, CP0_TAGLO
+ /* clear tag to invalidate */
+ PTR_LI t0, INDEX_BASE
+ PTR_ADDU t1, t0, a1
+1: cache_op INDEX_STORE_TAG_I t0
+ PTR_ADDU t0, a2
+ bne t0, t1, 1b
+ /* fill once, so data field parity is correct */
+ PTR_LI t0, INDEX_BASE
+2: cache_op FILL t0
+ PTR_ADDU t0, a2
+ bne t0, t1, 2b
+ /* invalidate again - prudent but not strictly neccessary */
+ PTR_LI t0, INDEX_BASE
+1: cache_op INDEX_STORE_TAG_I t0
+ PTR_ADDU t0, a2
+ bne t0, t1, 1b
+9: jr ra
+ END(mips_init_icache)
+
+/*
+ * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz)
+ */
+LEAF(mips_init_dcache)
+ blez a1, 9f
+ mtc0 zero, CP0_TAGLO
+ /* clear all tags */
+ PTR_LI t0, INDEX_BASE
+ PTR_ADDU t1, t0, a1
+1: cache_op INDEX_STORE_TAG_D t0
+ PTR_ADDU t0, a2
+ bne t0, t1, 1b
+ /* load from each line (in cached space) */
+ PTR_LI t0, INDEX_BASE
+2: LONG_L zero, 0(t0)
+ PTR_ADDU t0, a2
+ bne t0, t1, 2b
+ /* clear all tags */
+ PTR_LI t0, INDEX_BASE
+1: cache_op INDEX_STORE_TAG_D t0
+ PTR_ADDU t0, a2
+ bne t0, t1, 1b
+9: jr ra
+ END(mips_init_dcache)
+
+/*
+ * mips_cache_reset - low level initialisation of the primary caches
+ *
+ * This routine initialises the primary caches to ensure that they have good
+ * parity. It must be called by the ROM before any cached locations are used
+ * to prevent the possibility of data with bad parity being written to memory.
+ *
+ * To initialise the instruction cache it is essential that a source of data
+ * with good parity is available. This routine will initialise an area of
+ * memory starting at location zero to be used as a source of parity.
+ *
+ * RETURNS: N/A
+ *
+ */
+NESTED(mips_cache_reset, 0, ra)
+ move RA, ra
+ li t2, CONFIG_SYS_ICACHE_SIZE
+ li t3, CONFIG_SYS_DCACHE_SIZE
+ li t8, CONFIG_SYS_CACHELINE_SIZE
+
+ li v0, MIPS_MAX_CACHE_SIZE
+
+ /*
+ * Now clear that much memory starting from zero.
+ */
+ PTR_LI a0, CKSEG1
+ PTR_ADDU a1, a0, v0
+2: PTR_ADDIU a0, 64
+ f_fill64 a0, -64, zero
+ bne a0, a1, 2b
+
+ /*
+ * The caches are probably in an indeterminate state,
+ * so we force good parity into them by doing an
+ * invalidate, load/fill, invalidate for each line.
+ */
+
+ /*
+ * Assume bottom of RAM will generate good parity for the cache.
+ */
+
+ /*
+ * Initialize the I-cache first,
+ */
+ move a1, t2
+ move a2, t8
+ PTR_LA v1, mips_init_icache
+ jalr v1
+
+ /*
+ * then initialize D-cache.
+ */
+ move a1, t3
+ move a2, t8
+ PTR_LA v1, mips_init_dcache
+ jalr v1
+
+ jr RA
+ END(mips_cache_reset)
+
+/*
+ * dcache_status - get cache status
+ *
+ * RETURNS: 0 - cache disabled; 1 - cache enabled
+ *
+ */
+LEAF(dcache_status)
+ mfc0 t0, CP0_CONFIG
+ li t1, CONF_CM_UNCACHED
+ andi t0, t0, CONF_CM_CMASK
+ move v0, zero
+ beq t0, t1, 2f
+ li v0, 1
+2: jr ra
+ END(dcache_status)
+
+/*
+ * dcache_disable - disable cache
+ *
+ * RETURNS: N/A
+ *
+ */
+LEAF(dcache_disable)
+ mfc0 t0, CP0_CONFIG
+ li t1, -8
+ and t0, t0, t1
+ ori t0, t0, CONF_CM_UNCACHED
+ mtc0 t0, CP0_CONFIG
+ jr ra
+ END(dcache_disable)
+
+/*
+ * dcache_enable - enable cache
+ *
+ * RETURNS: N/A
+ *
+ */
+LEAF(dcache_enable)
+ mfc0 t0, CP0_CONFIG
+ ori t0, CONF_CM_CMASK
+ xori t0, CONF_CM_CMASK
+ ori t0, CONF_CM_CACHABLE_NONCOHERENT
+ mtc0 t0, CP0_CONFIG
+ jr ra
+ END(dcache_enable)
#
-# (C) Copyright 2004-2005
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+# (C) Copyright 2003
+# Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
#
# See file CREDITS for list of people who contributed to this
# project.
#
#
-# AMD Alchemy AU1000, MIPS32 core
+# Default optimization level for MIPS64
#
+# Note: Toolchains with binutils prior to v2.16
+# are no longer supported by U-Boot MIPS tree!
+#
+MIPSFLAGS = -march=mips64
-ifeq ($(TBASE),0)
-CONFIG_SYS_TEXT_BASE = 0
-else
-ifeq ($(TBASE),1)
-CONFIG_SYS_TEXT_BASE = 0xbfc10070
-else
-ifeq ($(TBASE),2)
-CONFIG_SYS_TEXT_BASE = 0xbfc30070
+PLATFORM_CPPFLAGS += $(MIPSFLAGS)
+PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT
+ifdef CONFIG_SYS_BIG_ENDIAN
+PLATFORM_LDFLAGS += -m elf64btsmip
else
-## Only to make ordinary make work
-CONFIG_SYS_TEXT_BASE = 0x90000000
-endif
-endif
+PLATFORM_LDFLAGS += -m elf64ltsmip
endif
+
+CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 -T mips64.lds
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <netdev.h>
+#include <asm/mipsregs.h>
+#include <asm/cacheops.h>
+#include <asm/reboot.h>
+
+#define cache_op(op, addr) \
+ __asm__ __volatile__( \
+ " .set push\n" \
+ " .set noreorder\n" \
+ " .set mips64\n" \
+ " cache %0, %1\n" \
+ " .set pop\n" \
+ : \
+ : "i" (op), "R" (*(unsigned char *)(addr)))
+
+void __attribute__((weak)) _machine_restart(void)
+{
+ fprintf(stderr, "*** reset failed ***\n");
+
+ while (1)
+ /* NOP */;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ _machine_restart();
+
+ return 0;
+}
+
+void flush_cache(ulong start_addr, ulong size)
+{
+ unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+ unsigned long addr = start_addr & ~(lsize - 1);
+ unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
+
+ /* aend will be miscalculated when size is zero, so we return here */
+ if (size == 0)
+ return;
+
+ while (1) {
+ cache_op(HIT_WRITEBACK_INV_D, addr);
+ cache_op(HIT_INVALIDATE_I, addr);
+ if (addr == aend)
+ break;
+ addr += lsize;
+ }
+}
+
+void flush_dcache_range(ulong start_addr, ulong stop)
+{
+ unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+ unsigned long addr = start_addr & ~(lsize - 1);
+ unsigned long aend = (stop - 1) & ~(lsize - 1);
+
+ while (1) {
+ cache_op(HIT_WRITEBACK_INV_D, addr);
+ if (addr == aend)
+ break;
+ addr += lsize;
+ }
+}
+
+void invalidate_dcache_range(ulong start_addr, ulong stop)
+{
+ unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+ unsigned long addr = start_addr & ~(lsize - 1);
+ unsigned long aend = (stop - 1) & ~(lsize - 1);
+
+ while (1) {
+ cache_op(HIT_INVALIDATE_D, addr);
+ if (addr == aend)
+ break;
+ addr += lsize;
+ }
+}
+
+void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
+{
+ write_c0_entrylo0(low0);
+ write_c0_pagemask(pagemask);
+ write_c0_entrylo1(low1);
+ write_c0_entryhi(hi);
+ write_c0_index(index);
+ tlb_write_indexed();
+}
/*
- * (C) Copyright 2010-2011
- * NVIDIA Corporation <www.nvidia.com>
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
* MA 02111-1307 USA
*/
-void board_init_uart_f(void);
-void gpio_config_uart(void);
+#include <common.h>
+#include <asm/mipsregs.h>
+
+void enable_interrupts(void)
+{
+}
+
+int disable_interrupts(void)
+{
+ return 0;
+}
--- /dev/null
+/*
+ * Startup Code for MIPS64 CPU-core
+ *
+ * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any dlater version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICUdlaR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Pdlace, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+
+#ifndef CONFIG_SYS_MIPS_CACHE_MODE
+#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
+#endif
+
+ /*
+ * For the moment disable interrupts, mark the kernel mode and
+ * set ST0_KX so that the CPU does not spit fire when using
+ * 64-bit addresses.
+ */
+ .macro setup_c0_status set clr
+ .set push
+ mfc0 t0, CP0_STATUS
+ or t0, ST0_CU0 | \set | 0x1f | \clr
+ xor t0, 0x1f | \clr
+ mtc0 t0, CP0_STATUS
+ .set noreorder
+ sll zero, 3 # ehb
+ .set pop
+ .endm
+
+ .set noreorder
+
+ .globl _start
+ .text
+_start:
+ .org 0x000
+ b reset
+ nop
+ .org 0x080
+ b romReserved
+ nop
+ .org 0x100
+ b romReserved
+ nop
+ .org 0x180
+ b romReserved
+ nop
+ .org 0x200
+ b romReserved
+ nop
+ .org 0x280
+ b romReserved
+ nop
+ .org 0x300
+ b romReserved
+ nop
+ .org 0x380
+ b romReserved
+ nop
+ .org 0x480
+ b romReserved
+ nop
+
+ /*
+ * We hope there are no more reserved vectors!
+ * 128 * 8 == 1024 == 0x400
+ * so this is address R_VEC+0x400 == 0xbfc00400
+ */
+ .org 0x500
+ .align 4
+reset:
+
+ /* Clear watch registers */
+ dmtc0 zero, CP0_WATCHLO
+ dmtc0 zero, CP0_WATCHHI
+
+ /* WP(Watch Pending), SW0/1 should be cleared */
+ mtc0 zero, CP0_CAUSE
+
+ setup_c0_status ST0_KX 0
+
+ /* Init Timer */
+ mtc0 zero, CP0_COUNT
+ mtc0 zero, CP0_COMPARE
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ /* CONFIG0 register */
+ dli t0, CONF_CM_UNCACHED
+ mtc0 t0, CP0_CONFIG
+#endif
+
+ /* Initialize $gp */
+ bal 1f
+ nop
+ .dword _gp
+1:
+ ld gp, 0(ra)
+
+#ifndef CONFIG_SKIP_LOWLEVEL_INIT
+ /* Initialize any external memory */
+ dla t9, lowlevel_init
+ jalr t9
+ nop
+
+ /* Initialize caches... */
+ dla t9, mips_cache_reset
+ jalr t9
+ nop
+
+ /* ... and enable them */
+ dli t0, CONFIG_SYS_MIPS_CACHE_MODE
+ mtc0 t0, CP0_CONFIG
+#endif
+
+ /* Set up temporary stack */
+ dli t0, CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_INIT_SP_OFFSET
+ dla sp, 0(t0)
+
+ dla t9, board_init_f
+ jr t9
+ nop
+
+/*
+ * void relocate_code (addr_sp, gd, addr_moni)
+ *
+ * This "function" does not return, instead it continues in RAM
+ * after relocating the monitor code.
+ *
+ * a0 = addr_sp
+ * a1 = gd
+ * a2 = destination address
+ */
+ .globl relocate_code
+ .ent relocate_code
+relocate_code:
+ move sp, a0 # set new stack pointer
+
+ dli t0, CONFIG_SYS_MONITOR_BASE
+ dla t3, in_ram
+ ld t2, -24(t3) # t2 <-- uboot_end_data
+ move t1, a2
+ move s2, a2 # s2 <-- destination address
+
+ /*
+ * Fix $gp:
+ *
+ * New $gp = (Old $gp - CONFIG_SYS_MONITOR_BASE) + Destination Address
+ */
+ move t8, gp
+ dsub gp, CONFIG_SYS_MONITOR_BASE
+ dadd gp, a2 # gp now adjusted
+ dsub s1, gp, t8 # s1 <-- relocation offset
+
+ /*
+ * t0 = source address
+ * t1 = target address
+ * t2 = source end address
+ */
+
+ /*
+ * Save destination address and size for dlater usage in flush_cache()
+ */
+ move s0, a1 # save gd in s0
+ move a0, t1 # a0 <-- destination addr
+ dsub a1, t2, t0 # a1 <-- size
+
+1:
+ lw t3, 0(t0)
+ sw t3, 0(t1)
+ daddu t0, 4
+ ble t0, t2, 1b
+ daddu t1, 4
+
+ /* If caches were enabled, we would have to flush them here. */
+
+ /* a0 & a1 are already set up for flush_cache(start, size) */
+ dla t9, flush_cache
+ jalr t9
+ nop
+
+ /* Jump to where we've relocated ourselves */
+ daddi t0, s2, in_ram - _start
+ jr t0
+ nop
+
+ .dword _gp
+ .dword _GLOBAL_OFFSET_TABLE_
+ .dword uboot_end_data
+ .dword uboot_end
+ .dword num_got_entries
+
+in_ram:
+ /*
+ * Now we want to update GOT.
+ *
+ * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
+ * generated by GNU ld. Skip these reserved entries from relocation.
+ */
+ ld t3, -8(t0) # t3 <-- num_got_entries
+ ld t8, -32(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
+ ld t9, -40(t0) # t9 <-- _gp
+ dsub t8, t9 # compute offset
+ dadd t8, t8, gp # t8 now holds relocated _G_O_T_
+ daddi t8, t8, 16 # skipping first two entries
+ dli t2, 2
+1:
+ ld t1, 0(t8)
+ beqz t1, 2f
+ dadd t1, s1
+ sd t1, 0(t8)
+2:
+ daddi t2, 1
+ blt t2, t3, 1b
+ daddi t8, 8
+
+ /* Clear BSS */
+ ld t1, -24(t0) # t1 <-- uboot_end_data
+ ld t2, -16(t0) # t2 <-- uboot_end
+ dadd t1, s1 # adjust pointers
+ dadd t2, s1
+
+ dsub t1, 8
+1:
+ daddi t1, 8
+ bltl t1, t2, 1b
+ sd zero, 0(t1)
+
+ move a0, s0 # a0 <-- gd
+ dla t9, board_init_r
+ jr t9
+ move a1, s2
+
+ .end relocate_code
+
+ /* Exception handlers */
+romReserved:
+ b romReserved
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mipsregs.h>
+
+static unsigned long timestamp;
+
+/* how many counter cycles in a jiffy */
+#define CYCLES_PER_JIFFY \
+ (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ
+
+/*
+ * timer without interrupts
+ */
+
+int timer_init(void)
+{
+ /* Set up the timer for the first expiration. */
+ timestamp = 0;
+ write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
+
+ return 0;
+}
+
+ulong get_timer(ulong base)
+{
+ unsigned int count;
+ unsigned int expirelo = read_c0_compare();
+
+ /* Check to see if we have missed any timestamps. */
+ count = read_c0_count();
+ while ((count - expirelo) < 0x7fffffff) {
+ expirelo += CYCLES_PER_JIFFY;
+ timestamp++;
+ }
+ write_c0_compare(expirelo);
+
+ return timestamp - base;
+}
+
+void __udelay(unsigned long usec)
+{
+ unsigned int tmo;
+
+ tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 1000000));
+ while ((tmo - read_c0_count()) < 0x7fffffff)
+ /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On MIPS it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On MIPS it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
unsigned long aend = (start_addr + size - 1) & ~(lsize - 1);
for (; addr <= aend; addr += lsize) {
- cache_op(Hit_Writeback_Inv_D, addr);
- cache_op(Hit_Invalidate_I, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
+ cache_op(HIT_INVALIDATE_I, addr);
}
}
unsigned long aend = (stop - 1) & ~(lsize - 1);
for (; addr <= aend; addr += lsize)
- cache_op(Hit_Writeback_Inv_D, addr);
+ cache_op(HIT_WRITEBACK_INV_D, addr);
}
void invalidate_dcache_range(ulong start_addr, ulong stop)
unsigned long aend = (stop - 1) & ~(lsize - 1);
for (; addr <= aend; addr += lsize)
- cache_op(Hit_Invalidate_D, addr);
+ cache_op(HIT_INVALIDATE_D, addr);
}
void flush_icache_all(void)
for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_ICACHE_SIZE;
addr += CONFIG_SYS_CACHELINE_SIZE) {
- cache_op(Index_Store_Tag_I, addr);
+ cache_op(INDEX_STORE_TAG_I, addr);
}
/* invalidate btb */
for (addr = CKSEG0; addr < CKSEG0 + CONFIG_SYS_DCACHE_SIZE;
addr += CONFIG_SYS_CACHELINE_SIZE) {
- cache_op(Index_Writeback_Inv_D, addr);
+ cache_op(INDEX_WRITEBACK_INV_D, addr);
}
__asm__ __volatile__("sync");
#include <common.h>
#include <asm/io.h>
#include <asm/jz4740.h>
+#include <serial.h>
+#include <linux/compiler.h>
/*
* serial_init - initialize a channel
*/
struct jz4740_uart *uart = (struct jz4740_uart *)CONFIG_SYS_UART_BASE;
-int serial_init(void)
+static int jz_serial_init(void)
{
/* Disable port interrupts while changing hardware */
writeb(0, &uart->dlhr_ier);
return 0;
}
-void serial_setbrg(void)
+static void jz_serial_setbrg(void)
{
u32 baud_div, tmp;
writeb(tmp, &uart->lcr);
}
-int serial_tstc(void)
+static int jz_serial_tstc(void)
{
if (readb(&uart->lsr) & UART_LSR_DR)
return 1;
return 0;
}
-void serial_putc(const char c)
+static void jz_serial_putc(const char c)
{
if (c == '\n')
serial_putc('\r');
writeb((u8)c, &uart->rbr_thr_dllr);
}
-int serial_getc(void)
+static int jz_serial_getc(void)
{
while (!serial_tstc())
;
return readb(&uart->rbr_thr_dllr);
}
-void serial_puts(const char *s)
+static struct serial_device jz_serial_drv = {
+ .name = "jz_serial",
+ .start = jz_serial_init,
+ .stop = NULL,
+ .setbrg = jz_serial_setbrg,
+ .putc = jz_serial_putc,
+ .puts = default_serial_puts,
+ .getc = jz_serial_getc,
+ .tstc = jz_serial_tstc,
+};
+
+void jz_serial_initialize(void)
{
- while (*s)
- serial_putc(*s++);
+ serial_register(&jz_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &jz_serial_drv;
}
li t0, KSEG0
addi t1, t0, CONFIG_SYS_DCACHE_SIZE
2:
- cache Index_Writeback_Inv_D, 0(t0)
+ cache INDEX_WRITEBACK_INV_D, 0(t0)
bne t0, t1, 2b
addi t0, CONFIG_SYS_CACHELINE_SIZE
li t0, KSEG0
addi t1, t0, CONFIG_SYS_ICACHE_SIZE
3:
- cache Index_Invalidate_I, 0(t0)
+ cache INDEX_INVALIDATE_I, 0(t0)
bne t0, t1, 3b
addi t0, CONFIG_SYS_CACHELINE_SIZE
cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
#else /* !CONFIG_SOC_AU1X00 */
-#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
+#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
#endif /* CONFIG_SOC_AU1X00 */
#endif /* __ASSEMBLY__ */
#ifdef CONFIG_SGI_IP28
/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
#include <asm/cacheops.h>
-#define R10KCBARRIER(addr) cache Cache_Barrier, addr;
+#define R10KCBARRIER(addr) cache CACHE_BARRIER, addr;
#else
#define R10KCBARRIER(addr)
#endif
/*
* Cache Operations available on all MIPS processors with R4000-style caches
*/
-#define Index_Invalidate_I 0x00
-#define Index_Writeback_Inv_D 0x01
-#define Index_Load_Tag_I 0x04
-#define Index_Load_Tag_D 0x05
-#define Index_Store_Tag_I 0x08
-#define Index_Store_Tag_D 0x09
+#define INDEX_INVALIDATE_I 0x00
+#define INDEX_WRITEBACK_INV_D 0x01
+#define INDEX_LOAD_TAG_I 0x04
+#define INDEX_LOAD_TAG_D 0x05
+#define INDEX_STORE_TAG_I 0x08
+#define INDEX_STORE_TAG_D 0x09
#if defined(CONFIG_CPU_LOONGSON2)
-#define Hit_Invalidate_I 0x00
+#define HIT_INVALIDATE_I 0x00
#else
-#define Hit_Invalidate_I 0x10
+#define HIT_INVALIDATE_I 0x10
#endif
-#define Hit_Invalidate_D 0x11
-#define Hit_Writeback_Inv_D 0x15
+#define HIT_INVALIDATE_D 0x11
+#define HIT_WRITEBACK_INV_D 0x15
/*
* R4000-specific cacheops
*/
-#define Create_Dirty_Excl_D 0x0d
-#define Fill 0x14
-#define Hit_Writeback_I 0x18
-#define Hit_Writeback_D 0x19
+#define CREATE_DIRTY_EXCL_D 0x0d
+#define FILL 0x14
+#define HIT_WRITEBACK_I 0x18
+#define HIT_WRITEBACK_D 0x19
/*
* R4000SC and R4400SC-specific cacheops
*/
-#define Index_Invalidate_SI 0x02
-#define Index_Writeback_Inv_SD 0x03
-#define Index_Load_Tag_SI 0x06
-#define Index_Load_Tag_SD 0x07
-#define Index_Store_Tag_SI 0x0A
-#define Index_Store_Tag_SD 0x0B
-#define Create_Dirty_Excl_SD 0x0f
-#define Hit_Invalidate_SI 0x12
-#define Hit_Invalidate_SD 0x13
-#define Hit_Writeback_Inv_SD 0x17
-#define Hit_Writeback_SD 0x1b
-#define Hit_Set_Virtual_SI 0x1e
-#define Hit_Set_Virtual_SD 0x1f
+#define INDEX_INVALIDATE_SI 0x02
+#define INDEX_WRITEBACK_INV_SD 0x03
+#define INDEX_LOAD_TAG_SI 0x06
+#define INDEX_LOAD_TAG_SD 0x07
+#define INDEX_STORE_TAG_SI 0x0A
+#define INDEX_STORE_TAG_SD 0x0B
+#define CREATE_DIRTY_EXCL_SD 0x0f
+#define HIT_INVALIDATE_SI 0x12
+#define HIT_INVALIDATE_SD 0x13
+#define HIT_WRITEBACK_INV_SD 0x17
+#define HIT_WRITEBACK_SD 0x1b
+#define HIT_SET_VIRTUAL_SI 0x1e
+#define HIT_SET_VIRTUAL_SD 0x1f
/*
* R5000-specific cacheops
*/
-#define R5K_Page_Invalidate_S 0x17
+#define R5K_PAGE_INVALIDATE_S 0x17
/*
* RM7000-specific cacheops
*/
-#define Page_Invalidate_T 0x16
+#define PAGE_INVALIDATE_T 0x16
/*
* R10000-specific cacheops
* Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
* Most of the _S cacheops are identical to the R4000SC _SD cacheops.
*/
-#define Index_Writeback_Inv_S 0x03
-#define Index_Load_Tag_S 0x07
-#define Index_Store_Tag_S 0x0B
-#define Hit_Invalidate_S 0x13
-#define Cache_Barrier 0x14
-#define Hit_Writeback_Inv_S 0x17
-#define Index_Load_Data_I 0x18
-#define Index_Load_Data_D 0x19
-#define Index_Load_Data_S 0x1b
-#define Index_Store_Data_I 0x1c
-#define Index_Store_Data_D 0x1d
-#define Index_Store_Data_S 0x1f
+#define INDEX_WRITEBACK_INV_S 0x03
+#define INDEX_LOAD_TAG_S 0x07
+#define INDEX_STORE_TAG_S 0x0B
+#define HIT_INVALIDATE_S 0x13
+#define CACHE_BARRIER 0x14
+#define HIT_WRITEBACK_INV_S 0x17
+#define INDEX_LOAD_DATA_I 0x18
+#define INDEX_LOAD_DATA_D 0x19
+#define INDEX_LOAD_DATA_S 0x1b
+#define INDEX_STORE_DATA_I 0x1c
+#define INDEX_STORE_DATA_D 0x1d
+#define INDEX_STORE_DATA_S 0x1f
#endif /* __ASM_CACHEOPS_H */
unsigned long tbl;
unsigned long lastinc;
#endif
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
unsigned long precon_buf_idx; /* Pre-Console buffer index */
*/
extern inline phys_addr_t virt_to_phys(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * phys_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
*/
extern inline unsigned long virt_to_bus(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * bus_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
typedef int __kernel_ipc_pid_t;
typedef int __kernel_uid_t;
typedef int __kernel_gid_t;
+#if _MIPS_SZLONG != 64
typedef unsigned int __kernel_size_t;
typedef int __kernel_ssize_t;
typedef int __kernel_ptrdiff_t;
+#else
+typedef unsigned long __kernel_size_t;
+typedef long __kernel_ssize_t;
+typedef long __kernel_ptrdiff_t;
+#endif
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
#define _U_BOOT_H_ 1
typedef struct bd_info {
- int bi_baudrate; /* serial console baudrate */
+ unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_arch_number; /* unique id for this board */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
/*
* We have to relocate the command table manually
*/
- fixup_cmdtable(&__u_boot_cmd_start,
- (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+ fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+ ll_entry_count(cmd_tbl_t, cmd));
#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
/* there are some other pointer constants we must deal with */
}
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long have_console; /* serial_init() was called */
unsigned long reloc_off; /* Relocation Offset */
#include <environment.h>
typedef struct bd_info {
- int bi_baudrate; /* serial console baudrate */
+ unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_arch_number; /* unique id for this board */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
/*
* We have to relocate the command table manually
*/
- fixup_cmdtable(&__u_boot_cmd_start,
- (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+ fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+ ll_entry_count(cmd_tbl_t, cmd));
#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
-#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
-#endif
debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
/* Initialize from environment */
load_addr = getenv_ulong("loadaddr", 16, load_addr);
-#ifdef BOARD_LATE_INIT
+#ifdef CONFIG_BOARD_LATE_INIT
board_late_init();
#endif
* the initialization code relocates the command table as
* well -- admittedly, this is just pure laziness ;-)
*/
- __u_boot_cmd_start = .;
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- }
+
. = ALIGN(4);
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
/* INIT DATA sections - "Small" data (see the gcc -G option)
* is always gp-relative. Here we make all init data sections
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
- unsigned long bi_baudrate; /* Console Baudrate */
+ unsigned int bi_baudrate; /* Console Baudrate */
} bd_t;
/* For image.h:image_check_target_arch() */
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long have_console; /* serial_init() was called */
phys_size_t ram_size; /* RAM size */
#define _U_BOOT_H_
typedef struct bd_info {
- unsigned long bi_baudrate; /* serial console baudrate */
+ unsigned int bi_baudrate; /* serial console baudrate */
unsigned long bi_arch_number; /* unique id for this board */
unsigned long bi_boot_params; /* where this board expects params */
unsigned long bi_memstart; /* start of DRAM memory */
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
DECLARE_GLOBAL_DATA_PTR;
-#if defined(CONFIG_PSC_CONSOLE) || defined(CONFIG_SERIAL_MULTI)
+#if defined(CONFIG_PSC_CONSOLE)
static void fifo_init (volatile psc512x_t *psc)
{
out_be32(&psc->rfintmask, 0);
out_be32(&psc->tfintmask, 0);
-#if defined(CONFIG_SERIAL_MULTI)
switch (((u32)psc & 0xf00) >> 8) {
case 0:
tfsize = FIFOC_PSC0_TX_SIZE | (FIFOC_PSC0_TX_ADDR << 16);
default:
return;
}
-#else
- tfsize = CONSOLE_FIFO_TX_SIZE | (CONSOLE_FIFO_TX_ADDR << 16);
- rfsize = CONSOLE_FIFO_RX_SIZE | (CONSOLE_FIFO_RX_ADDR << 16);
-#endif
+
out_be32(&psc->tfsize, tfsize);
out_be32(&psc->rfsize, rfsize);
{
volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
volatile psc512x_t *psc = (psc512x_t *) &im->psc[idx];
-#if defined(CONFIG_SERIAL_MULTI)
u32 reg;
reg = in_be32(&im->clk.sccr[0]);
out_be32(&im->clk.sccr[0], reg | CLOCK_SCCR1_PSC_EN(idx));
-#endif
fifo_init (psc);
return (in_8(&psc->ip) & 0x1) ? 0 : 1;
}
-#endif /* CONFIG_PSC_CONSOLE || CONFIG_SERIAL_MULTI */
-
-#if defined(CONFIG_SERIAL_MULTI)
+#endif /* CONFIG_PSC_CONSOLE */
#define DECLARE_PSC_SERIAL_FUNCTIONS(port) \
int serial##port##_init(void) \
serial_puts_dev(port, s); \
}
-#define INIT_PSC_SERIAL_STRUCTURE(port, name) { \
- name, \
- serial##port##_init, \
- serial##port##_uninit, \
- serial##port##_setbrg, \
- serial##port##_getc, \
- serial##port##_tstc, \
- serial##port##_putc, \
- serial##port##_puts, \
+#define INIT_PSC_SERIAL_STRUCTURE(port, __name) { \
+ .name = __name, \
+ .start = serial##port##_init, \
+ .stop = serial##port##_uninit, \
+ .setbrg = serial##port##_setbrg, \
+ .getc = serial##port##_getc, \
+ .tstc = serial##port##_tstc, \
+ .putc = serial##port##_putc, \
+ .puts = serial##port##_puts, \
}
#if defined(CONFIG_SYS_PSC1)
#endif
}
-#else
-
-void serial_setbrg(void)
-{
- serial_setbrg_dev(CONFIG_PSC_CONSOLE);
-}
-
-int serial_init(void)
+void mpc512x_serial_initialize(void)
{
- return serial_init_dev(CONFIG_PSC_CONSOLE);
-}
-
-void serial_putc(const char c)
-{
- serial_putc_dev(CONFIG_PSC_CONSOLE, c);
-}
-
-void serial_putc_raw(const char c)
-{
- serial_putc_raw_dev(CONFIG_PSC_CONSOLE, c);
-}
-
-void serial_puts(const char *s)
-{
- serial_puts_dev(CONFIG_PSC_CONSOLE, s);
-}
-
-int serial_getc(void)
-{
- return serial_getc_dev(CONFIG_PSC_CONSOLE);
-}
-
-int serial_tstc(void)
-{
- return serial_tstc_dev(CONFIG_PSC_CONSOLE);
-}
-
-void serial_setrts(int s)
-{
- return serial_setrts_dev(CONFIG_PSC_CONSOLE, s);
-}
-
-int serial_getcts(void)
-{
- return serial_getcts_dev(CONFIG_PSC_CONSOLE);
+#if defined(CONFIG_SYS_PSC1)
+ serial_register(&serial1_device);
+#endif
+#if defined(CONFIG_SYS_PSC3)
+ serial_register(&serial3_device);
+#endif
+#if defined(CONFIG_SYS_PSC4)
+ serial_register(&serial4_device);
+#endif
+#if defined(CONFIG_SYS_PSC6)
+ serial_register(&serial6_device);
+#endif
}
-#endif /* CONFIG_PSC_CONSOLE */
-#if defined(CONFIG_SERIAL_MULTI)
#include <stdio_dev.h>
/*
* Routines for communication with serial devices over PSC
return cnt;
}
-#endif /* CONFIG_SERIAL_MULTI */
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
#include <watchdog.h>
#include <command.h>
#include <mpc5xx.h>
+#include <serial.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
/*
- * Local function prototypes
+ * Local functions
*/
-static int ready_to_send(void);
+static int ready_to_send(void)
+{
+ volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
+ volatile short status;
+
+ do {
+#if defined(CONFIG_5xx_CONS_SCI1)
+ status = immr->im_qsmcm.qsmcm_sc1sr;
+#else
+ status = immr->im_qsmcm.qsmcm_sc2sr;
+#endif
+
+#if defined(CONFIG_WATCHDOG)
+ reset_5xx_watchdog (immr);
+#endif
+ } while ((status & SCI_TDRE) == 0);
+ return 1;
+
+}
/*
* Minimal global serial functions needed to use one of the SCI modules.
*/
-int serial_init (void)
+static int mpc5xx_serial_init(void)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
return 0;
}
-void serial_putc(const char c)
+static void mpc5xx_serial_putc(const char c)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
}
}
-int serial_getc(void)
+static int mpc5xx_serial_getc(void)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
volatile short status;
return tmp;
}
-int serial_tstc()
+static int mpc5xx_serial_tstc(void)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
short status;
return (status & SCI_RDRF);
}
-void serial_setbrg (void)
+static void mpc5xx_serial_setbrg(void)
{
volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
short scxbr;
#endif
}
-void serial_puts (const char *s)
+static struct serial_device mpc5xx_serial_drv = {
+ .name = "mpc5xx_serial",
+ .start = mpc5xx_serial_init,
+ .stop = NULL,
+ .setbrg = mpc5xx_serial_setbrg,
+ .putc = mpc5xx_serial_putc,
+ .puts = default_serial_puts,
+ .getc = mpc5xx_serial_getc,
+ .tstc = mpc5xx_serial_tstc,
+};
+
+void mpc5xx_serial_initialize(void)
{
- while (*s) {
- serial_putc(*s);
- ++s;
- }
+ serial_register(&mpc5xx_serial_drv);
}
-int ready_to_send(void)
+__weak struct serial_device *default_serial_console(void)
{
- volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
- volatile short status;
-
- do {
-#if defined(CONFIG_5xx_CONS_SCI1)
- status = immr->im_qsmcm.qsmcm_sc1sr;
-#else
- status = immr->im_qsmcm.qsmcm_sc2sr;
-#endif
-
-#if defined(CONFIG_WATCHDOG)
- reset_5xx_watchdog (immr);
-#endif
- } while ((status & SCI_TDRE) == 0);
- return 1;
-
+ return &mpc5xx_serial_drv;
}
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
* Linux/PPC sources (m8260_tty.c had no copyright info in it).
*
* Martin Krause, 8 Jun 2006
- * Added CONFIG_SERIAL_MULTI support
+ * Added SERIAL_MULTI support
*/
/*
#include <common.h>
#include <linux/compiler.h>
#include <mpc5xxx.h>
-
-#if defined (CONFIG_SERIAL_MULTI)
#include <serial.h>
-#endif
DECLARE_GLOBAL_DATA_PTR;
#error CONFIG_PSC_CONSOLE must be in 1 ... 6
#endif
-#if defined(CONFIG_SERIAL_MULTI) && !defined(CONFIG_PSC_CONSOLE2)
-#error you must define CONFIG_PSC_CONSOLE2 if CONFIG_SERIAL_MULTI is set
-#endif
+#if defined(CONFIG_PSC_CONSOLE2)
-#if defined(CONFIG_SERIAL_MULTI)
#if CONFIG_PSC_CONSOLE2 == 1
#define PSC_BASE2 MPC5XXX_PSC1
#elif CONFIG_PSC_CONSOLE2 == 2
#else
#error CONFIG_PSC_CONSOLE2 must be in 1 ... 6
#endif
-#endif /* CONFIG_SERIAL_MULTI */
-#if defined(CONFIG_SERIAL_MULTI)
-int serial_init_dev (unsigned long dev_base)
-#else
-int serial_init (void)
#endif
+
+int serial_init_dev (unsigned long dev_base)
{
-#if defined(CONFIG_SERIAL_MULTI)
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
-#else
- volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#endif
unsigned long baseclk;
int div;
return (0);
}
-#if defined(CONFIG_SERIAL_MULTI)
void serial_putc_dev (unsigned long dev_base, const char c)
-#else
-void serial_putc(const char c)
-#endif
{
-#if defined(CONFIG_SERIAL_MULTI)
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
-#else
- volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#endif
if (c == '\n')
-#if defined(CONFIG_SERIAL_MULTI)
serial_putc_dev (dev_base, '\r');
-#else
- serial_putc('\r');
-#endif
/* Wait for last character to go. */
while (!(psc->psc_status & PSC_SR_TXEMP))
psc->psc_buffer_8 = c;
}
-#if defined(CONFIG_SERIAL_MULTI)
void serial_putc_raw_dev(unsigned long dev_base, const char c)
-#else
-void serial_putc_raw(const char c)
-#endif
{
-#if defined(CONFIG_SERIAL_MULTI)
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
-#else
- volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#endif
/* Wait for last character to go. */
while (!(psc->psc_status & PSC_SR_TXEMP))
;
}
-#if defined(CONFIG_SERIAL_MULTI)
void serial_puts_dev (unsigned long dev_base, const char *s)
-#else
-void serial_puts (const char *s)
-#endif
{
while (*s) {
-#if defined(CONFIG_SERIAL_MULTI)
serial_putc_dev (dev_base, *s++);
-#else
- serial_putc (*s++);
-#endif
}
}
-#if defined(CONFIG_SERIAL_MULTI)
int serial_getc_dev (unsigned long dev_base)
-#else
-int serial_getc(void)
-#endif
{
-#if defined(CONFIG_SERIAL_MULTI)
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
-#else
- volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#endif
/* Wait for a character to arrive. */
while (!(psc->psc_status & PSC_SR_RXRDY))
return psc->psc_buffer_8;
}
-#if defined(CONFIG_SERIAL_MULTI)
int serial_tstc_dev (unsigned long dev_base)
-#else
-int serial_tstc(void)
-#endif
{
-#if defined(CONFIG_SERIAL_MULTI)
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
-#else
- volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#endif
return (psc->psc_status & PSC_SR_RXRDY);
}
-#if defined(CONFIG_SERIAL_MULTI)
void serial_setbrg_dev (unsigned long dev_base)
-#else
-void serial_setbrg(void)
-#endif
{
-#if defined(CONFIG_SERIAL_MULTI)
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
-#else
- volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#endif
unsigned long baseclk, div;
baseclk = (gd->ipb_clk + 16) / 32;
psc->ctlr = div & 0xff;
}
-#if defined(CONFIG_SERIAL_MULTI)
void serial_setrts_dev (unsigned long dev_base, int s)
-#else
-void serial_setrts(int s)
-#endif
{
-#if defined(CONFIG_SERIAL_MULTI)
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
-#else
- volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#endif
if (s) {
/* Assert RTS (become LOW) */
}
}
-#if defined(CONFIG_SERIAL_MULTI)
int serial_getcts_dev (unsigned long dev_base)
-#else
-int serial_getcts(void)
-#endif
{
-#if defined(CONFIG_SERIAL_MULTI)
volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)dev_base;
-#else
- volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE;
-#endif
return (psc->ip & 0x1) ? 0 : 1;
}
-#if defined(CONFIG_SERIAL_MULTI)
int serial0_init(void)
{
return (serial_init_dev(PSC_BASE));
}
-int serial1_init(void)
-{
- return (serial_init_dev(PSC_BASE2));
-}
void serial0_setbrg (void)
{
serial_setbrg_dev(PSC_BASE);
}
-void serial1_setbrg (void)
-{
- serial_setbrg_dev(PSC_BASE2);
-}
void serial0_putc(const char c)
{
serial_putc_dev(PSC_BASE,c);
}
-void serial1_putc(const char c)
-{
- serial_putc_dev(PSC_BASE2, c);
-}
void serial0_puts(const char *s)
{
serial_puts_dev(PSC_BASE, s);
}
-void serial1_puts(const char *s)
-{
- serial_puts_dev(PSC_BASE2, s);
-}
-
int serial0_getc(void)
{
return(serial_getc_dev(PSC_BASE));
}
-int serial1_getc(void)
-{
- return(serial_getc_dev(PSC_BASE2));
-}
int serial0_tstc(void)
{
return (serial_tstc_dev(PSC_BASE));
}
-int serial1_tstc(void)
-{
- return (serial_tstc_dev(PSC_BASE2));
-}
-
struct serial_device serial0_device =
{
- "serial0",
- serial0_init,
- NULL,
- serial0_setbrg,
- serial0_getc,
- serial0_tstc,
- serial0_putc,
- serial0_puts,
+ .name = "serial0",
+ .start = serial0_init,
+ .stop = NULL,
+ .setbrg = serial0_setbrg,
+ .getc = serial0_getc,
+ .tstc = serial0_tstc,
+ .putc = serial0_putc,
+ .puts = serial0_puts,
};
__weak struct serial_device *default_serial_console(void)
return &serial0_device;
}
+#ifdef CONFIG_PSC_CONSOLE2
+int serial1_init(void)
+{
+ return serial_init_dev(PSC_BASE2);
+}
+
+void serial1_setbrg(void)
+{
+ serial_setbrg_dev(PSC_BASE2);
+}
+
+void serial1_putc(const char c)
+{
+ serial_putc_dev(PSC_BASE2, c);
+}
+
+void serial1_puts(const char *s)
+{
+ serial_puts_dev(PSC_BASE2, s);
+}
+
+int serial1_getc(void)
+{
+ return serial_getc_dev(PSC_BASE2);
+}
+
+int serial1_tstc(void)
+{
+ return serial_tstc_dev(PSC_BASE2);
+}
+
struct serial_device serial1_device =
{
- "serial1",
- serial1_init,
- NULL,
- serial1_setbrg,
- serial1_getc,
- serial1_tstc,
- serial1_putc,
- serial1_puts,
+ .name = "serial1",
+ .start = serial1_init,
+ .stop = NULL,
+ .setbrg = serial1_setbrg,
+ .getc = serial1_getc,
+ .tstc = serial1_tstc,
+ .putc = serial1_putc,
+ .puts = serial1_puts,
};
-#endif /* CONFIG_SERIAL_MULTI */
+#endif /* CONFIG_PSC_CONSOLE2 */
#endif /* CONFIG_PSC_CONSOLE */
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
*/
static char ohci_inited = 0;
-int usb_lowlevel_init(void)
+int usb_lowlevel_init(int index, void **controller)
{
/* Set the USB Clock */
return 0;
}
-int usb_lowlevel_stop(void)
+int usb_lowlevel_stop(int index)
{
/* this gets called really early - before the controller has */
/* even been initialized! */
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
#include <common.h>
#include <mpc8220.h>
+#include <serial.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
#define PSC_BASE MMAP_PSC1
#if defined(CONFIG_PSC_CONSOLE)
-int serial_init (void)
+static int mpc8220_serial_init(void)
{
volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
u32 counter;
return (0);
}
-void serial_putc (const char c)
+static void mpc8220_serial_putc(const char c)
{
volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
psc->xmitbuf[0] = c;
}
-void serial_puts (const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
-int serial_getc (void)
+static int mpc8220_serial_getc(void)
{
volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
return psc->xmitbuf[2];
}
-int serial_tstc (void)
+static int mpc8220_serial_tstc(void)
{
volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
return (psc->sr_csr & PSC_SR_RXRDY);
}
-void serial_setbrg (void)
+static void mpc8220_serial_setbrg(void)
{
volatile psc8220_t *psc = (psc8220_t *) PSC_BASE;
u32 counter;
psc->cr = PSC_CR_RX_ENABLE | PSC_CR_TX_ENABLE;
}
+
+static struct serial_device mpc8220_serial_drv = {
+ .name = "mpc8220_serial",
+ .start = mpc8220_serial_init,
+ .stop = NULL,
+ .setbrg = mpc8220_serial_setbrg,
+ .putc = mpc8220_serial_putc,
+ .puts = default_serial_puts,
+ .getc = mpc8220_serial_getc,
+ .tstc = mpc8220_serial_tstc,
+};
+
+void mpc8220_serial_initialize(void)
+{
+ serial_register(&mpc8220_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &mpc8220_serial_drv;
+}
#endif /* CONFIG_PSC_CONSOLE */
cpu_init_f (void)
{
/* MOUSSE board is initialized in asm */
-#if !defined(CONFIG_MOUSSE) && !defined(CONFIG_BMW)
+#if !defined(CONFIG_MOUSSE)
register unsigned long val;
CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
/* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/
CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */
__asm__ __volatile__("eieio");
-#endif /* !CONFIG_MOUSSE && !CONFIG_BMW */
+#endif /* !CONFIG_MOUSSE */
}
in_flash:
-#if defined(CONFIG_BMW)
- bl early_init_f /* Must be ASM: no stack yet! */
-#endif
/*
* Setup BATs - cannot be done in C since we don't have a stack yet
*/
mfmsr r3
ori r3, r3, (MSR_IR | MSR_DR)
mtmsr r3
-#if !defined(CONFIG_BMW)
+
/* Enable and invalidate data cache.
*/
mfspr r3, HID0
ori r3, r3, 0x0080
sync
mtspr 1011, r3
-#endif /* !CONFIG_BMW */
+
/*
* Thisk the stack pointer *somewhere* sensible. Doesnt
* matter much where as we'll move it when we relocate
bdnz 3b
4:
-#if !defined(CONFIG_BMW)
/* Unlock the data cache and invalidate locked area */
xor r0, r0, r0
mtspr 1011, r0
dcbi r0, r4
addi r4, r4, 32
bdnz 41b
-#endif
/*
* Now flush the cache: note that we must start from a cache aligned
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
#include <common.h>
#include <mpc8260.h>
#include <asm/cpm_8260.h>
+#include <serial.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
-int serial_init (void)
+static int mpc8260_scc_serial_init(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile scc_t *sp;
return (0);
}
-void
-serial_setbrg (void)
+static void mpc8260_scc_serial_setbrg(void)
{
#if defined(CONFIG_CONS_USE_EXTC)
m8260_cpm_extcbrg(SCC_INDEX, gd->baudrate,
#endif
}
-void
-serial_putc(const char c)
+static void mpc8260_scc_serial_putc(const char c)
{
volatile scc_uart_t *up;
volatile cbd_t *tbdf;
tbdf->cbd_sc |= BD_SC_READY;
}
-void
-serial_puts (const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
-int
-serial_getc(void)
+static int mpc8260_scc_serial_getc(void)
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
return (c);
}
-int
-serial_tstc()
+static int mpc8260_scc_serial_tstc(void)
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0);
}
+static struct serial_device mpc8260_scc_serial_drv = {
+ .name = "mpc8260_scc_uart",
+ .start = mpc8260_scc_serial_init,
+ .stop = NULL,
+ .setbrg = mpc8260_scc_serial_setbrg,
+ .putc = mpc8260_scc_serial_putc,
+ .puts = default_serial_puts,
+ .getc = mpc8260_scc_serial_getc,
+ .tstc = mpc8260_scc_serial_tstc,
+};
+
+void mpc8260_scc_serial_initialize(void)
+{
+ serial_register(&mpc8260_scc_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &mpc8260_scc_serial_drv;
+}
#endif /* CONFIG_CONS_ON_SCC */
#if defined(CONFIG_KGDB_ON_SCC)
#include <common.h>
#include <mpc8260.h>
#include <asm/cpm_8260.h>
+#include <serial.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
3, /* BRG1 for SCC4 */
};
-int serial_init (void)
+static int mpc8260_smc_serial_init(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
volatile smc_t *sp;
return (0);
}
-void
-serial_setbrg (void)
+static void mpc8260_smc_serial_setbrg(void)
{
#if defined(CONFIG_CONS_USE_EXTC)
m8260_cpm_extcbrg(brg_map[SMC_INDEX], gd->baudrate,
#endif
}
-void
-serial_putc(const char c)
+static void mpc8260_smc_serial_putc(const char c)
{
volatile smc_uart_t *up;
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
rtx->txbd.cbd_sc |= BD_SC_READY;
}
-void
-serial_puts (const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
-int
-serial_getc(void)
+static int mpc8260_smc_serial_getc(void)
{
volatile smc_uart_t *up;
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
return(c);
}
-int
-serial_tstc()
+static int mpc8260_smc_serial_tstc(void)
{
volatile smc_uart_t *up;
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
return !(rtx->rxbd.cbd_sc & BD_SC_EMPTY);
}
+static struct serial_device mpc8260_smc_serial_drv = {
+ .name = "mpc8260_smc_uart",
+ .start = mpc8260_smc_serial_init,
+ .stop = NULL,
+ .setbrg = mpc8260_smc_serial_setbrg,
+ .putc = mpc8260_smc_serial_putc,
+ .puts = default_serial_puts,
+ .getc = mpc8260_smc_serial_getc,
+ .tstc = mpc8260_smc_serial_tstc,
+};
+
+void mpc8260_smc_serial_initialize(void)
+{
+ serial_register(&mpc8260_smc_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &mpc8260_smc_serial_drv;
+}
#endif /* CONFIG_CONS_ON_SMC */
#if defined(CONFIG_KGDB_ON_SMC)
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
#include <common.h>
#include <asm/cpm_85xx.h>
+#include <serial.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
#endif
-int serial_init (void)
+static int mpc85xx_serial_init(void)
{
volatile ccsr_cpm_t *cpm = (ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR;
volatile ccsr_cpm_scc_t *sp;
return (0);
}
-void
-serial_setbrg (void)
+static void mpc85xx_serial_setbrg(void)
{
#if defined(CONFIG_CONS_USE_EXTC)
m8560_cpm_extcbrg(SCC_INDEX, gd->baudrate,
#endif
}
-void
-serial_putc(const char c)
+static void mpc85xx_serial_putc(const char c)
{
volatile scc_uart_t *up;
volatile cbd_t *tbdf;
tbdf->cbd_sc |= BD_SC_READY;
}
-void
-serial_puts (const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
-int
-serial_getc(void)
+static int mpc85xx_serial_getc(void)
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
return (c);
}
-int
-serial_tstc()
+static int mpc85xx_serial_tstc(void)
{
volatile cbd_t *rbdf;
volatile scc_uart_t *up;
return ((rbdf->cbd_sc & BD_SC_EMPTY) == 0);
}
+static struct serial_device mpc85xx_serial_drv = {
+ .name = "mpc85xx_serial",
+ .start = mpc85xx_serial_init,
+ .stop = NULL,
+ .setbrg = mpc85xx_serial_setbrg,
+ .putc = mpc85xx_serial_putc,
+ .puts = default_serial_puts,
+ .getc = mpc85xx_serial_getc,
+ .tstc = mpc85xx_serial_tstc,
+};
+
+void mpc85xx_serial_initialize(void)
+{
+ serial_register(&mpc85xx_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &mpc85xx_serial_drv;
+}
#endif /* CONFIG_CONS_ON_SCC */
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
}
_edata = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
+
. = ALIGN(8);
__init_begin = .;
__init_end = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
struct serial_device serial_smc_device =
{
- "serial_smc",
- smc_init,
- NULL,
- smc_setbrg,
- smc_getc,
- smc_tstc,
- smc_putc,
- smc_puts,
+ .name = "serial_smc",
+ .start = smc_init,
+ .stop = NULL,
+ .setbrg = smc_setbrg,
+ .getc = smc_getc,
+ .tstc = smc_tstc,
+ .putc = smc_putc,
+ .puts = smc_puts,
};
#endif /* CONFIG_8xx_CONS_SMC1 || CONFIG_8xx_CONS_SMC2 */
struct serial_device serial_scc_device =
{
- "serial_scc",
- scc_init,
- NULL,
- scc_setbrg,
- scc_getc,
- scc_tstc,
- scc_putc,
- scc_puts,
+ .name = "serial_scc",
+ .start = scc_init,
+ .stop = NULL,
+ .setbrg = scc_setbrg,
+ .getc = scc_getc,
+ .tstc = scc_tstc,
+ .putc = scc_putc,
+ .puts = scc_puts,
};
#endif /* CONFIG_8xx_CONS_SCCx */
#endif
}
+void mpc8xx_serial_initialize(void)
+{
+#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
+ serial_register(&serial_smc_device);
+#endif
+#if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
+ defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
+ serial_register(&serial_scc_device);
+#endif
+}
+
#ifdef CONFIG_MODEM_SUPPORT
void disable_putc(void)
{
COBJS-$(CONFIG_CMD_ECCTEST) += cmd_ecctest.o
COBJS += fdt.o
COBJS += interrupts.o
-COBJS += iop480_uart.o
COBJS-$(CONFIG_CMD_REGINFO) += reginfo.o
COBJS += sdram.o
COBJS += speed.o
#endif
#endif /* CONFIG_PCI */
-#if defined(CONFIG_PCI) && !defined(CONFIG_IOP480) && \
+#if defined(CONFIG_PCI) && \
!defined(CONFIG_405) && !defined(CONFIG_405EX)
int pci_arbiter_enabled(void)
{
u32 reg;
#endif
-#if !defined(CONFIG_IOP480)
char addstr[64] = "";
sys_info_t sys_info;
int cpu_num;
printf (" 16 kB I-Cache %d kB D-Cache",
((pvr | 0x00000001) == PVR_405GPR_RB) ? 16 : 8);
#endif
-#endif /* !defined(CONFIG_IOP480) */
-
-#if defined(CONFIG_IOP480)
- printf ("PLX IOP480 (PVR=%08x)", pvr);
- printf (" at %s MHz:", strmhz(buf, clock));
- printf (" %u kB I-Cache", 4);
- printf (" %u kB D-Cache", 2);
-#endif
#endif /* !defined(CONFIG_405) */
*/
unsigned long get_tbclk (void)
{
-#if !defined(CONFIG_IOP480)
sys_info_t sys_info;
get_sys_info(&sys_info);
return (sys_info.freqProcessor);
-#else
- return (66000000);
-#endif
-
}
+++ /dev/null
-/*
- * (C) Copyright 2000-2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <commproc.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <watchdog.h>
-
-#ifdef CONFIG_SERIAL_MULTI
-#include <serial.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifdef CONFIG_IOP480
-
-#define SPU_BASE 0x40000000
-
-#define spu_LineStat_rc 0x00 /* Line Status Register (Read/Clear) */
-#define spu_LineStat_w 0x04 /* Line Status Register (Set) */
-#define spu_Handshk_rc 0x08 /* Handshake Status Register (Read/Clear) */
-#define spu_Handshk_w 0x0c /* Handshake Status Register (Set) */
-#define spu_BRateDivh 0x10 /* Baud rate divisor high */
-#define spu_BRateDivl 0x14 /* Baud rate divisor low */
-#define spu_CtlReg 0x18 /* Control Register */
-#define spu_RxCmd 0x1c /* Rx Command Register */
-#define spu_TxCmd 0x20 /* Tx Command Register */
-#define spu_RxBuff 0x24 /* Rx data buffer */
-#define spu_TxBuff 0x24 /* Tx data buffer */
-
-/*-----------------------------------------------------------------------------+
- | Line Status Register.
- +-----------------------------------------------------------------------------*/
-#define asyncLSRport1 0x40000000
-#define asyncLSRport1set 0x40000004
-#define asyncLSRDataReady 0x80
-#define asyncLSRFramingError 0x40
-#define asyncLSROverrunError 0x20
-#define asyncLSRParityError 0x10
-#define asyncLSRBreakInterrupt 0x08
-#define asyncLSRTxHoldEmpty 0x04
-#define asyncLSRTxShiftEmpty 0x02
-
-/*-----------------------------------------------------------------------------+
- | Handshake Status Register.
- +-----------------------------------------------------------------------------*/
-#define asyncHSRport1 0x40000008
-#define asyncHSRport1set 0x4000000c
-#define asyncHSRDsr 0x80
-#define asyncLSRCts 0x40
-
-/*-----------------------------------------------------------------------------+
- | Control Register.
- +-----------------------------------------------------------------------------*/
-#define asyncCRport1 0x40000018
-#define asyncCRNormal 0x00
-#define asyncCRLoopback 0x40
-#define asyncCRAutoEcho 0x80
-#define asyncCRDtr 0x20
-#define asyncCRRts 0x10
-#define asyncCRWordLength7 0x00
-#define asyncCRWordLength8 0x08
-#define asyncCRParityDisable 0x00
-#define asyncCRParityEnable 0x04
-#define asyncCREvenParity 0x00
-#define asyncCROddParity 0x02
-#define asyncCRStopBitsOne 0x00
-#define asyncCRStopBitsTwo 0x01
-#define asyncCRDisableDtrRts 0x00
-
-/*-----------------------------------------------------------------------------+
- | Receiver Command Register.
- +-----------------------------------------------------------------------------*/
-#define asyncRCRport1 0x4000001c
-#define asyncRCRDisable 0x00
-#define asyncRCREnable 0x80
-#define asyncRCRIntDisable 0x00
-#define asyncRCRIntEnabled 0x20
-#define asyncRCRDMACh2 0x40
-#define asyncRCRDMACh3 0x60
-#define asyncRCRErrorInt 0x10
-#define asyncRCRPauseEnable 0x08
-
-/*-----------------------------------------------------------------------------+
- | Transmitter Command Register.
- +-----------------------------------------------------------------------------*/
-#define asyncTCRport1 0x40000020
-#define asyncTCRDisable 0x00
-#define asyncTCREnable 0x80
-#define asyncTCRIntDisable 0x00
-#define asyncTCRIntEnabled 0x20
-#define asyncTCRDMACh2 0x40
-#define asyncTCRDMACh3 0x60
-#define asyncTCRTxEmpty 0x10
-#define asyncTCRErrorInt 0x08
-#define asyncTCRStopPause 0x04
-#define asyncTCRBreakGen 0x02
-
-/*-----------------------------------------------------------------------------+
- | Miscellanies defines.
- +-----------------------------------------------------------------------------*/
-#define asyncTxBufferport1 0x40000024
-#define asyncRxBufferport1 0x40000024
-#define asyncDLABLsbport1 0x40000014
-#define asyncDLABMsbport1 0x40000010
-#define asyncXOFFchar 0x13
-#define asyncXONchar 0x11
-
-/*
- * Minimal serial functions needed to use one of the SMC ports
- * as serial console interface.
- */
-
-int serial_init (void)
-{
- unsigned short br_reg;
-
- br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
-
- /*
- * Init onboard UART
- */
- out_8((u8 *)SPU_BASE + spu_LineStat_rc, 0x78); /* Clear all bits in Line Status Reg */
- out_8((u8 *)SPU_BASE + spu_BRateDivl, (br_reg & 0x00ff)); /* Set baud rate divisor... */
- out_8((u8 *)SPU_BASE + spu_BRateDivh, ((br_reg & 0xff00) >> 8)); /* ... */
- out_8((u8 *)SPU_BASE + spu_CtlReg, 0x08); /* Set 8 bits, no parity and 1 stop bit */
- out_8((u8 *)SPU_BASE + spu_RxCmd, 0xb0); /* Enable Rx */
- out_8((u8 *)SPU_BASE + spu_TxCmd, 0x9c); /* Enable Tx */
- out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
- in_8((u8 *)SPU_BASE + spu_RxBuff); /* Dummy read, to clear receiver */
-
- return (0);
-}
-
-void serial_setbrg (void)
-{
- unsigned short br_reg;
-
- br_reg = ((((CONFIG_CPUCLOCK * 1000000) / 16) / gd->baudrate) - 1);
-
- out_8((u8 *)SPU_BASE + spu_BRateDivl,
- (br_reg & 0x00ff)); /* Set baud rate divisor... */
- out_8((u8 *)SPU_BASE + spu_BRateDivh,
- ((br_reg & 0xff00) >> 8)); /* ... */
-}
-
-void serial_putc (const char c)
-{
- if (c == '\n')
- serial_putc ('\r');
-
- /* load status from handshake register */
- if (in_8((u8 *)SPU_BASE + spu_Handshk_rc) != 00)
- out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
-
- out_8((u8 *)SPU_BASE + spu_TxBuff, c); /* Put char */
-
- while ((in_8((u8 *)SPU_BASE + spu_LineStat_rc) & 04) != 04) {
- if (in_8((u8 *)SPU_BASE + spu_Handshk_rc) != 00)
- out_8((u8 *)SPU_BASE + spu_Handshk_rc, 0xff); /* Clear Handshake */
- }
-}
-
-void serial_puts (const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
-int serial_getc ()
-{
- unsigned char status = 0;
-
- while (1) {
- status = in_8((u8 *)asyncLSRport1);
- if ((status & asyncLSRDataReady) != 0x0) {
- break;
- }
- if ((status & ( asyncLSRFramingError |
- asyncLSROverrunError |
- asyncLSRParityError |
- asyncLSRBreakInterrupt )) != 0) {
- (void) out_8((u8 *)asyncLSRport1,
- asyncLSRFramingError |
- asyncLSROverrunError |
- asyncLSRParityError |
- asyncLSRBreakInterrupt );
- }
- }
- return (0x000000ff & (int) in_8((u8 *)asyncRxBufferport1));
-}
-
-int serial_tstc ()
-{
- unsigned char status;
-
- status = in_8((u8 *)asyncLSRport1);
- if ((status & asyncLSRDataReady) != 0x0) {
- return (1);
- }
- if ((status & ( asyncLSRFramingError |
- asyncLSROverrunError |
- asyncLSRParityError |
- asyncLSRBreakInterrupt )) != 0) {
- (void) out_8((u8 *)asyncLSRport1,
- asyncLSRFramingError |
- asyncLSROverrunError |
- asyncLSRParityError |
- asyncLSRBreakInterrupt);
- }
- return 0;
-}
-
-#endif /* CONFIG_IOP480 */
extern void get_sys_info (sys_info_t * sysInfo);
extern ulong get_PCI_freq (void);
-#elif defined(CONFIG_AP1000)
-void get_sys_info (sys_info_t * sysInfo)
-{
- sysInfo->freqProcessor = 240 * 1000 * 1000;
- sysInfo->freqPLB = 80 * 1000 * 1000;
- sysInfo->freqPCI = 33 * 1000 * 1000;
-}
-
#elif defined(CONFIG_405)
void get_sys_info (sys_info_t * sysInfo)
int get_clocks (void)
{
-#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
- defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
- defined(CONFIG_405EX) || defined(CONFIG_405) || \
- defined(CONFIG_440)
sys_info_t sys_info;
get_sys_info (&sys_info);
gd->cpu_clk = sys_info.freqProcessor;
gd->bus_clk = sys_info.freqPLB;
-#endif /* defined(CONFIG_405GP) || defined(CONFIG_405CR) */
-
-#ifdef CONFIG_IOP480
- gd->cpu_clk = 66000000;
- gd->bus_clk = 66000000;
-#endif
return (0);
}
get_sys_info (&sys_info);
val = sys_info.freqPLB;
-
-#elif defined(CONFIG_IOP480)
-
- val = 66;
-
#else
# error get_bus_freq() not implemented
#endif
return val;
}
-#if !defined(CONFIG_IOP480)
ulong get_OPB_freq (void)
{
PPC4xx_SYS_INFO sys_info;
return sys_info.freqOPB;
}
-#endif
#endif /* CONFIG_440 */
-/*****************************************************************************/
-#ifdef CONFIG_IOP480
- /*----------------------------------------------------------------------- */
- /* Set up some machine state registers. */
- /*----------------------------------------------------------------------- */
- addi r0,r0,0x0000 /* initialize r0 to zero */
- mtspr SPRN_ESR,r0 /* clear Exception Syndrome Reg */
- mttcr r0 /* timer control register */
- mtexier r0 /* disable all interrupts */
- addis r4,r0,0xFFFF /* set r4 to 0xFFFFFFFF (status in the */
- ori r4,r4,0xFFFF /* dbsr is cleared by setting bits to 1) */
- mtdbsr r4 /* clear/reset the dbsr */
- mtexisr r4 /* clear all pending interrupts */
- addis r4,r0,0x8000
- mtexier r4 /* enable critical exceptions */
- addis r4,r0,0x0000 /* assume 403GCX - enable core clk */
- ori r4,r4,0x4020 /* dbling (no harm done on GA and GC */
- mtiocr r4 /* since bit not used) & DRC to latch */
- /* data bus on rising edge of CAS */
- /*----------------------------------------------------------------------- */
- /* Clear XER. */
- /*----------------------------------------------------------------------- */
- mtxer r0
- /*----------------------------------------------------------------------- */
- /* Invalidate i-cache and d-cache TAG arrays. */
- /*----------------------------------------------------------------------- */
- addi r3,0,1024 /* 1/4 of I-cache size, half of D-cache */
- addi r4,0,1024 /* 1/4 of I-cache */
-..cloop:
- iccci 0,r3
- iccci r4,r3
- dccci 0,r3
- addic. r3,r3,-16 /* move back one cache line */
- bne ..cloop /* loop back to do rest until r3 = 0 */
-
- /* */
- /* initialize IOP480 so it can read 1 MB code area for SRAM spaces */
- /* this requires enabling MA[17..0], by default only MA[12..0] are enabled. */
- /* */
-
- /* first copy IOP480 register base address into r3 */
- addis r3,0,0x5000 /* IOP480 register base address hi */
-/* ori r3,r3,0x0000 / IOP480 register base address lo */
-
-#ifdef CONFIG_ADCIOP
- /* use r4 as the working variable */
- /* turn on CS3 (LOCCTL.7) */
- lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
- andi. r4,r4,0xff7f /* make bit 7 = 0 -- CS3 mode */
- stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
-#endif
-
-#ifdef CONFIG_DASA_SIM
- /* use r4 as the working variable */
- /* turn on MA17 (LOCCTL.7) */
- lwz r4,0x84(r3) /* LOCTL is at offset 0x84 */
- ori r4,r4,0x80 /* make bit 7 = 1 -- MA17 mode */
- stw r4,0x84(r3) /* LOCTL is at offset 0x84 */
-#endif
-
- /* turn on MA16..13 (LCS0BRD.12 = 0) */
- lwz r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
- andi. r4,r4,0xefff /* make bit 12 = 0 */
- stw r4,0x100(r3) /* LCS0BRD is at offset 0x100 */
-
- /* make sure above stores all comlete before going on */
- sync
-
- /* last thing, set local init status done bit (DEVINIT.31) */
- lwz r4,0x80(r3) /* DEVINIT is at offset 0x80 */
- oris r4,r4,0x8000 /* make bit 31 = 1 */
- stw r4,0x80(r3) /* DEVINIT is at offset 0x80 */
-
- /* clear all pending interrupts and disable all interrupts */
- li r4,-1 /* set p1 to 0xffffffff */
- stw r4,0x1b0(r3) /* clear all pending interrupts */
- stw r4,0x1b8(r3) /* clear all pending interrupts */
- li r4,0 /* set r4 to 0 */
- stw r4,0x1b4(r3) /* disable all interrupts */
- stw r4,0x1bc(r3) /* disable all interrupts */
-
- /* make sure above stores all comlete before going on */
- sync
-
- /* Set-up icache cacheability. */
- lis r1, CONFIG_SYS_ICACHE_SACR_VALUE@h
- ori r1, r1, CONFIG_SYS_ICACHE_SACR_VALUE@l
- mticcr r1
- isync
-
- /* Set-up dcache cacheability. */
- lis r1, CONFIG_SYS_DCACHE_SACR_VALUE@h
- ori r1, r1, CONFIG_SYS_DCACHE_SACR_VALUE@l
- mtdccr r1
-
- addis r1,r0,CONFIG_SYS_INIT_RAM_ADDR@h
- ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack to SDRAM */
- li r0, 0 /* Make room for stack frame header and */
- stwu r0, -4(r1) /* clear final stack frame so that */
- stwu r0, -4(r1) /* stack backtraces terminate cleanly */
-
- GET_GOT /* initialize GOT access */
-
- bl board_init_f /* run first part of init code (from Flash) */
- /* NOTREACHED - board_init_f() does not return */
-
-#endif /* CONFIG_IOP480 */
-
/*****************************************************************************/
#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \
defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
*/
static char ohci_inited = 0;
-int usb_lowlevel_init(void)
+int usb_lowlevel_init(int index, void **controller)
{
memset (&gohci, 0, sizeof (ohci_t));
memset (&urb_priv, 0, sizeof (urb_priv_t));
return 0;
}
-int usb_lowlevel_stop(void)
+int usb_lowlevel_stop(int index)
{
/* this gets called really early - before the controller has */
/* even been initialized! */
#include <asm/processor.h>
/* bytes per L1 cache line */
-#if defined(CONFIG_8xx) || defined(CONFIG_IOP480)
+#if defined(CONFIG_8xx)
#define L1_CACHE_SHIFT 4
#elif defined(CONFIG_PPC64BRIDGE)
#define L1_CACHE_SHIFT 7
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long bus_clk;
#if defined(CONFIG_8xx)
#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27)
#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
-#ifndef CONFIG_IOP480
#define CONFIG_SYS_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */
-#else
-#define CONFIG_SYS_DCACHE_SIZE (2 << 10) /* For PLX IOP480(403)*/
-#endif
/* DCR registers */
#define PLB0_ACR 0x0087
#include <asm/apm821xx.h>
#endif
-/*
- * Configure which SDRAM/DDR/DDR2 controller is equipped
- */
-#if defined(CONFIG_AP1000) || defined(CONFIG_ML2)
-#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */
-#endif
-
/*
* Common registers for all SoC's
*/
unsigned long bi_ipbfreq; /* IPB Bus Freq, in MHz */
unsigned long bi_pcifreq; /* PCI Bus Freq, in MHz */
#endif
- unsigned long bi_baudrate; /* Console Baudrate */
+ unsigned int bi_baudrate; /* Console Baudrate */
#if defined(CONFIG_405) || \
defined(CONFIG_405GP) || \
defined(CONFIG_405CR) || \
COBJS-y += extable.o
COBJS-y += interrupts.o
COBJS-$(CONFIG_CMD_KGDB) += kgdb.o
+COBJS-${CONFIG_CMD_IDE} += ide.o
COBJS-y += time.o
# Workaround for local bus unaligned access problems
gd->env_addr += dest_addr - CONFIG_SYS_MONITOR_BASE;
#endif
-#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
-#endif
debug("Now running in RAM - U-Boot at: %08lx\n", dest_addr);
--- /dev/null
+/*
+ * (C) Copyright 2000-2011
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* Code taken from cmd_ide.c */
+#include <common.h>
+#include <ata.h>
+#include "ide.h"
+
+#ifdef CONFIG_IDE_8xx_DIRECT
+#include <mpc8xx.h>
+#include <pcmcia.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Timings for IDE Interface
+ *
+ * SETUP / LENGTH / HOLD - cycles valid for 50 MHz clk
+ * 70 165 30 PIO-Mode 0, [ns]
+ * 4 9 2 [Cycles]
+ * 50 125 20 PIO-Mode 1, [ns]
+ * 3 7 2 [Cycles]
+ * 30 100 15 PIO-Mode 2, [ns]
+ * 2 6 1 [Cycles]
+ * 30 80 10 PIO-Mode 3, [ns]
+ * 2 5 1 [Cycles]
+ * 25 70 10 PIO-Mode 4, [ns]
+ * 2 4 1 [Cycles]
+ */
+
+static const pio_config_t pio_config_ns[IDE_MAX_PIO_MODE+1] = {
+ /* Setup Length Hold */
+ { 70, 165, 30 }, /* PIO-Mode 0, [ns] */
+ { 50, 125, 20 }, /* PIO-Mode 1, [ns] */
+ { 30, 101, 15 }, /* PIO-Mode 2, [ns] */
+ { 30, 80, 10 }, /* PIO-Mode 3, [ns] */
+ { 25, 70, 10 }, /* PIO-Mode 4, [ns] */
+};
+
+static pio_config_t pio_config_clk[IDE_MAX_PIO_MODE+1];
+
+#ifndef CONFIG_SYS_PIO_MODE
+#define CONFIG_SYS_PIO_MODE 0 /* use a relaxed default */
+#endif
+static int pio_mode = CONFIG_SYS_PIO_MODE;
+
+/* Make clock cycles and always round up */
+
+#define PCMCIA_MK_CLKS(t, T) (((t) * (T) + 999U) / 1000U)
+
+static void set_pcmcia_timing(int pmode)
+{
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia);
+ ulong timings;
+
+ debug("Set timing for PIO Mode %d\n", pmode);
+
+ timings = PCMCIA_SHT(pio_config_clk[pmode].t_hold)
+ | PCMCIA_SST(pio_config_clk[pmode].t_setup)
+ | PCMCIA_SL(pio_config_clk[pmode].t_length);
+
+ /*
+ * IDE 0
+ */
+ pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_PBR0;
+#if (CONFIG_SYS_PCMCIA_POR0 != 0)
+ pcmp->pcmc_por0 = CONFIG_SYS_PCMCIA_POR0 | timings;
+#else
+ pcmp->pcmc_por0 = CONFIG_SYS_PCMCIA_POR0;
+#endif
+ debug("PBR0: %08x POR0: %08x\n", pcmp->pcmc_pbr0, pcmp->pcmc_por0);
+
+ pcmp->pcmc_pbr1 = CONFIG_SYS_PCMCIA_PBR1;
+#if (CONFIG_SYS_PCMCIA_POR1 != 0)
+ pcmp->pcmc_por1 = CONFIG_SYS_PCMCIA_POR1 | timings;
+#else
+ pcmp->pcmc_por1 = CONFIG_SYS_PCMCIA_POR1;
+#endif
+ debug("PBR1: %08x POR1: %08x\n", pcmp->pcmc_pbr1, pcmp->pcmc_por1);
+
+ pcmp->pcmc_pbr2 = CONFIG_SYS_PCMCIA_PBR2;
+#if (CONFIG_SYS_PCMCIA_POR2 != 0)
+ pcmp->pcmc_por2 = CONFIG_SYS_PCMCIA_POR2 | timings;
+#else
+ pcmp->pcmc_por2 = CONFIG_SYS_PCMCIA_POR2;
+#endif
+ debug("PBR2: %08x POR2: %08x\n", pcmp->pcmc_pbr2, pcmp->pcmc_por2);
+
+ pcmp->pcmc_pbr3 = CONFIG_SYS_PCMCIA_PBR3;
+#if (CONFIG_SYS_PCMCIA_POR3 != 0)
+ pcmp->pcmc_por3 = CONFIG_SYS_PCMCIA_POR3 | timings;
+#else
+ pcmp->pcmc_por3 = CONFIG_SYS_PCMCIA_POR3;
+#endif
+ debug("PBR3: %08x POR3: %08x\n", pcmp->pcmc_pbr3, pcmp->pcmc_por3);
+
+ /*
+ * IDE 1
+ */
+ pcmp->pcmc_pbr4 = CONFIG_SYS_PCMCIA_PBR4;
+#if (CONFIG_SYS_PCMCIA_POR4 != 0)
+ pcmp->pcmc_por4 = CONFIG_SYS_PCMCIA_POR4 | timings;
+#else
+ pcmp->pcmc_por4 = CONFIG_SYS_PCMCIA_POR4;
+#endif
+ debug("PBR4: %08x POR4: %08x\n", pcmp->pcmc_pbr4, pcmp->pcmc_por4);
+
+ pcmp->pcmc_pbr5 = CONFIG_SYS_PCMCIA_PBR5;
+#if (CONFIG_SYS_PCMCIA_POR5 != 0)
+ pcmp->pcmc_por5 = CONFIG_SYS_PCMCIA_POR5 | timings;
+#else
+ pcmp->pcmc_por5 = CONFIG_SYS_PCMCIA_POR5;
+#endif
+ debug("PBR5: %08x POR5: %08x\n", pcmp->pcmc_pbr5, pcmp->pcmc_por5);
+
+ pcmp->pcmc_pbr6 = CONFIG_SYS_PCMCIA_PBR6;
+#if (CONFIG_SYS_PCMCIA_POR6 != 0)
+ pcmp->pcmc_por6 = CONFIG_SYS_PCMCIA_POR6 | timings;
+#else
+ pcmp->pcmc_por6 = CONFIG_SYS_PCMCIA_POR6;
+#endif
+ debug("PBR6: %08x POR6: %08x\n", pcmp->pcmc_pbr6, pcmp->pcmc_por6);
+
+ pcmp->pcmc_pbr7 = CONFIG_SYS_PCMCIA_PBR7;
+#if (CONFIG_SYS_PCMCIA_POR7 != 0)
+ pcmp->pcmc_por7 = CONFIG_SYS_PCMCIA_POR7 | timings;
+#else
+ pcmp->pcmc_por7 = CONFIG_SYS_PCMCIA_POR7;
+#endif
+ debug("PBR7: %08x POR7: %08x\n", pcmp->pcmc_pbr7, pcmp->pcmc_por7);
+
+}
+
+int ide_preinit(void)
+{
+ int i;
+ /* Initialize PIO timing tables */
+ for (i = 0; i <= IDE_MAX_PIO_MODE; ++i) {
+ pio_config_clk[i].t_setup =
+ PCMCIA_MK_CLKS(pio_config_ns[i].t_setup, gd->bus_clk);
+ pio_config_clk[i].t_length =
+ PCMCIA_MK_CLKS(pio_config_ns[i].t_length, gd->bus_clk);
+ pio_config_clk[i].t_hold =
+ PCMCIA_MK_CLKS(pio_config_ns[i].t_hold, gd->bus_clk);
+ debug("PIO Mode %d: setup=%2d ns/%d clk" " len=%3d ns/%d clk"
+ " hold=%2d ns/%d clk\n", i, pio_config_ns[i].t_setup,
+ pio_config_clk[i].t_setup, pio_config_ns[i].t_length,
+ pio_config_clk[i].t_length, pio_config_ns[i].t_hold,
+ pio_config_clk[i].t_hold);
+ }
+
+ return 0;
+}
+
+int ide_init_postreset(void)
+{
+ volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia);
+
+ /* PCMCIA / IDE initialization for common mem space */
+ pcmp->pcmc_pgcrb = 0;
+
+ /* start in PIO mode 0 - most relaxed timings */
+ pio_mode = 0;
+ set_pcmcia_timing(pio_mode);
+ return 0;
+}
+#endif /* CONFIG_IDE_8xx_DIRECT */
+
+#ifdef CONFIG_IDE_8xx_PCCARD
+int ide_preinit(void)
+{
+ ide_devices_found = 0;
+ /* initialize the PCMCIA IDE adapter card */
+ pcmcia_on();
+ if (!ide_devices_found)
+ return 1;
+ udelay(1000000);/* 1 s */
+ return 0;
+}
+#endif
/*
- * (C) Copyright 2010,2011
- * NVIDIA Corporation <www.nvidia.com>
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
*
* See file CREDITS for list of people who contributed to this
* project.
* MA 02111-1307 USA
*/
-#ifndef _TEGRA_BOARD_H_
-#define _TEGRA_BOARD_H_
-
-/* Setup UARTs for the board according to the selected config */
-void board_init_uart_f(void);
+#ifndef _MPC8XX_IDE_H_
+#define _MPC8XX_IDE_H_ 1
+#ifdef CONFIG_IDE_8xx_PCCARD
+int pcmcia_on(void);
+extern int ide_devices_found;
+#endif
#endif
SECTIONS
{
- __u_boot_cmd_start = .;
- _u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__u_boot_sandbox_option_start = .;
_u_boot_sandbox_getopt : { *(.u_boot_sandbox_getopt) }
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long have_console; /* serial_init() was called */
unsigned long env_addr; /* Address of Environment struct */
unsigned long env_valid; /* Checksum of Environment valid? */
gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */
-#ifdef CONFIG_SERIAL_MULTI
serial_initialize();
-#endif
#ifdef CONFIG_POST
post_output_backlog();
}
PROVIDE (_egot = .);
- PROVIDE (__u_boot_cmd_start = .);
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- . = ALIGN(4);
+
+ .u_boot_list : {
+ #include <u-boot.lst>
}
- PROVIDE (__u_boot_cmd_end = .);
PROVIDE (reloc_dst_end = .);
}
PROVIDE (_egot = .);
- PROVIDE (__u_boot_cmd_start = .);
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- . = ALIGN(4);
+
+ .u_boot_list : {
+ #include <u-boot.lst>
}
- PROVIDE (__u_boot_cmd_end = .);
PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
}
PROVIDE (_egot = .);
- PROVIDE (__u_boot_cmd_start = .);
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- . = ALIGN(4);
+
+ .u_boot_list : {
+ #include <u-boot.lst>
}
- PROVIDE (__u_boot_cmd_end = .);
PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
{
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
unsigned long bi_flashoffset; /* reserved area for startup monitor */
unsigned long bi_sramstart; /* start of SRAM memory */
unsigned long bi_sramsize; /* size of SRAM memory */
- unsigned long bi_baudrate; /* Console Baudrate */
+ unsigned int bi_baudrate; /* Console Baudrate */
unsigned long bi_boot_params; /* where this board expects params */
} bd_t;
#include <common.h>
#include <asm/processor.h>
#include <asm/leon.h>
+#include <serial.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
#define READ_DWORD(var) SPARC_NOCACHE_READ_DWORD((unsigned int)&(var))
#endif
-int serial_init(void)
+static int leon2_serial_init(void)
{
LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
LEON2_Uart_regs *regs;
return 0;
}
-void serial_putc(const char c)
-{
- if (c == '\n')
- serial_putc_raw('\r');
-
- serial_putc_raw(c);
-}
-
-void serial_putc_raw(const char c)
+static void leon2_serial_putc_raw(const char c)
{
LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
LEON2_Uart_regs *regs;
#endif
}
-void serial_puts(const char *s)
+static void leon2_serial_putc(const char c)
{
- while (*s) {
- serial_putc(*s++);
- }
+ if (c == '\n')
+ leon2_serial_putc_raw('\r');
+
+ leon2_serial_putc_raw(c);
}
-int serial_getc(void)
+static int leon2_serial_getc(void)
{
LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
LEON2_Uart_regs *regs;
return READ_WORD(regs->UART_Channel);
}
-int serial_tstc(void)
+static int leon2_serial_tstc(void)
{
LEON2_regs *leon2 = (LEON2_regs *) LEON2_PREGS;
LEON2_Uart_regs *regs;
}
/* set baud rate for uart */
-void serial_setbrg(void)
+static void leon2_serial_setbrg(void)
{
/* update baud rate settings, read it from gd->baudrate */
unsigned int scaler;
regs->UART_Scaler = scaler;
}
}
+
+static struct serial_device leon2_serial_drv = {
+ .name = "leon2_serial",
+ .start = leon2_serial_init,
+ .stop = NULL,
+ .setbrg = leon2_serial_setbrg,
+ .putc = leon2_serial_putc,
+ .puts = default_serial_puts,
+ .getc = leon2_serial_getc,
+ .tstc = leon2_serial_tstc,
+};
+
+void leon2_serial_initialize(void)
+{
+ serial_register(&leon2_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &leon2_serial_drv;
+}
#include <asm/processor.h>
#include <asm/leon.h>
#include <ambapp.h>
+#include <serial.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
ambapp_dev_apbuart *leon3_apbuart = NULL;
-int serial_init(void)
+static int leon3_serial_init(void)
{
ambapp_apbdev apbdev;
unsigned int tmp;
return -1; /* didn't find hardware */
}
-void serial_putc(const char c)
-{
- if (c == '\n')
- serial_putc_raw('\r');
-
- serial_putc_raw(c);
-}
-
-void serial_putc_raw(const char c)
+static void leon3_serial_putc_raw(const char c)
{
if (!leon3_apbuart)
return;
#endif
}
-void serial_puts(const char *s)
+static void leon3_serial_putc(const char c)
{
- while (*s) {
- serial_putc(*s++);
- }
+ if (c == '\n')
+ leon3_serial_putc_raw('\r');
+
+ leon3_serial_putc_raw(c);
}
-int serial_getc(void)
+static int leon3_serial_getc(void)
{
if (!leon3_apbuart)
return 0;
return READ_WORD(leon3_apbuart->data);
}
-int serial_tstc(void)
+static int leon3_serial_tstc(void)
{
if (leon3_apbuart)
return (READ_WORD(leon3_apbuart->status) &
}
/* set baud rate for uart */
-void serial_setbrg(void)
+static void leon3_serial_setbrg(void)
{
/* update baud rate settings, read it from gd->baudrate */
unsigned int scaler;
}
return;
}
+
+static struct serial_device leon3_serial_drv = {
+ .name = "leon3_serial",
+ .start = leon3_serial_init,
+ .stop = NULL,
+ .setbrg = leon3_serial_setbrg,
+ .putc = leon3_serial_putc,
+ .puts = default_serial_puts,
+ .getc = leon3_serial_getc,
+ .tstc = leon3_serial_tstc,
+};
+
+void leon3_serial_initialize(void)
+{
+ serial_register(&leon3_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &leon3_serial_drv;
+}
/* init uhci
*/
-int usb_lowlevel_init(void)
+int usb_lowlevel_init(int index, void **controller)
{
unsigned char temp;
ambapp_ahbdev ahbdev;
/* stop uhci
*/
-int usb_lowlevel_stop(void)
+int usb_lowlevel_stop(int index)
{
if (grusb_irq == -1)
return 1;
typedef struct global_data {
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long cpu_clk; /* CPU clock in Hz! */
unsigned long bus_clk;
unsigned short bi_ethspeed; /* Ethernet speed in Mbps */
unsigned long bi_intfreq; /* Internal Freq, in MHz */
unsigned long bi_busfreq; /* Bus Freq, in MHz */
- unsigned long bi_baudrate; /* Console Baudrate */
+ unsigned int bi_baudrate; /* Console Baudrate */
} bd_t;
#endif /* __ASSEMBLY__ */
/*
* We have to relocate the command table manually
*/
- fixup_cmdtable(&__u_boot_cmd_start,
- (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start));
+ fixup_cmdtable(ll_entry_start(cmd_tbl_t, cmd),
+ ll_entry_count(cmd_tbl_t, cmd));
#endif /* defined(CONFIG_NEEDS_MANUAL_RELOC) */
#if defined(CONFIG_CMD_AMBAPP) && defined(CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP)
extern void prepare_bootargs(char *bootargs);
#ifdef CONFIG_USB_UHCI
-extern int usb_lowlevel_stop(void);
+extern int usb_lowlevel_stop(int index);
#endif
/* sparc kernel argument (the ROM vector) */
.text : { *(.text*); }
. = ALIGN(4);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
+
. = ALIGN(4);
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
unsigned long gd_addr; /* Location of Global Data */
bd_t *bd;
unsigned long flags;
- unsigned long baudrate;
+ unsigned int baudrate;
unsigned long have_console; /* serial_init() was called */
#ifdef CONFIG_PRE_CONSOLE_BUFFER
unsigned long precon_buf_idx; /* Pre-Console buffer index */
timer_init,
display_banner,
display_dram_config,
-#ifdef CONFIG_SERIAL_MULTI
serial_initialize_r,
-#endif
#ifndef CONFIG_SYS_NO_FLASH
flash_init_r,
#endif
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
#include <common.h>
#include <command.h>
+#include <serial.h>
+#include <linux/compiler.h>
+
#include "../include/memory.h"
#include "serial.h"
DECLARE_GLOBAL_DATA_PTR;
#ifdef CONFIG_MPSC
-
-
-int serial_init (void)
+static int marvell_serial_init(void)
{
#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
int clock_divisor = 230400 / gd->baudrate;
return (0);
}
-void serial_putc (const char c)
+static void marvell_serial_putc(const char c)
{
if (c == '\n')
mpsc_putchar ('\r');
mpsc_putchar (c);
}
-int serial_getc (void)
+static int marvell_serial_getc(void)
{
return mpsc_getchar ();
}
-int serial_tstc (void)
+static int marvell_serial_tstc(void)
{
return mpsc_test_char ();
}
-void serial_setbrg (void)
+static void marvell_serial_setbrg(void)
{
galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
}
#else /* ! CONFIG_MPSC */
-int serial_init (void)
+static int marvell_serial_init(void)
{
int clock_divisor = 230400 / gd->baudrate;
return (0);
}
-void serial_putc (const char c)
+static void marvell_serial_putc(const char c)
{
if (c == '\n')
NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
}
-int serial_getc (void)
+static int marvell_serial_getc(void)
{
return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
}
-int serial_tstc (void)
+static int marvell_serial_tstc(void)
{
return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
}
-void serial_setbrg (void)
+static void marvell_serial_setbrg(void)
{
int clock_divisor = 230400 / gd->baudrate;
#endif /* CONFIG_MPSC */
-void serial_puts (const char *s)
+static struct serial_device marvell_serial_drv = {
+ .name = "marvell_serial",
+ .start = marvell_serial_init,
+ .stop = NULL,
+ .setbrg = marvell_serial_setbrg,
+ .putc = marvell_serial_putc,
+ .puts = default_serial_puts,
+ .getc = marvell_serial_getc,
+ .tstc = marvell_serial_tstc,
+};
+
+void marvell_serial_initialize(void)
+{
+ serial_register(&marvell_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
{
- while (*s) {
- serial_putc (*s++);
- }
+ return &marvell_serial_drv;
}
#if defined(CONFIG_CMD_KGDB)
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
net/libnet.o(.text*)
board/actux1/libactux1.o(.text*)
arch/arm/cpu/ixp/libixp.o(.text*)
- drivers/serial/libserial.o(.text*)
+ drivers/input/libinput.o(.text*)
. = env_offset;
common/env_embedded.o(.ppcenv)
*(.got)
}
. =.;
- __u_boot_cmd_start =.;
- .u_boot_cmd : {
- *(.u_boot_cmd)
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
}
- __u_boot_cmd_end =.;
. = ALIGN (4);
.rel.dyn : {
net/libnet.o(.text*)
board/actux2/libactux2.o(.text*)
arch/arm/cpu/ixp/libixp.o(.text*)
- drivers/serial/libserial.o(.text*)
+ drivers/input/libinput.o(.text*)
. = env_offset;
common/env_embedded.o(.ppcenv)
*(.got)
}
. =.;
- __u_boot_cmd_start =.;
- .u_boot_cmd : {
- *(.u_boot_cmd)
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
}
- __u_boot_cmd_end =.;
. = ALIGN (4);
.rel.dyn : {
net/libnet.o(.text*)
board/actux3/libactux3.o(.text*)
arch/arm/cpu/ixp/libixp.o(.text*)
- drivers/serial/libserial.o(.text*)
+ drivers/input/libinput.o(.text*)
. = env_offset;
common/env_embedded.o(.ppcenv)
*(.got)
}
. =.;
- __u_boot_cmd_start =.;
- .u_boot_cmd : {
- *(.u_boot_cmd)
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
}
- __u_boot_cmd_end =.;
. = ALIGN (4);
.rel.dyn : {
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
. = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ } >.sram
+ . = ALIGN(4);
.rel.dyn : {
__rel_dyn_start = .;
*(.rel*)
* the initialization code relocates the command table as
* well -- admittedly, this is just pure laziness ;-)
*/
- __u_boot_cmd_start = .;
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- }
+
. = ALIGN(4);
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
/* INIT DATA sections - "Small" data (see the gcc -G option)
* is always gp-relative. Here we make all init data sections
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
+++ /dev/null
-/*
- * amirix.c: ppcboot platform support for AMIRIX board
- *
- * Copyright 2002 Mind NV
- * Copyright 2003 AMIRIX Systems Inc.
- *
- * http://www.mind.be/
- * http://www.amirix.com/
- *
- * Author : Peter De Schrijver (p2@mind.be)
- * Frank Smith (smith@amirix.com)
- *
- * Derived from : Other platform support files in this tree, ml2
- *
- * This software may be used and distributed according to the terms of
- * the GNU General Public License (GPL) version 2, incorporated herein by
- * reference. Drivers based on or derived from this code fall under the GPL
- * and must retain the authorship, copyright and this license notice. This
- * file is not a complete program and may only be used when the entire
- * program is licensed under the GPL.
- *
- */
-
-#include <common.h>
-#include <command.h>
-#include <netdev.h>
-#include <asm/processor.h>
-
-#include "powerspan.h"
-#include "ap1000.h"
-
-int board_pre_init (void)
-{
- return 0;
-}
-
-/** serial number and platform display at startup */
-int checkboard (void)
-{
- char buf[64];
- int l = getenv_f("serial#", buf, sizeof(buf));
-
- /* After a loadace command, the SystemAce control register is left in a wonky state. */
- /* this code did not work in board_pre_init */
- unsigned char *p = (unsigned char *) AP1000_SYSACE_REGBASE;
- unsigned int *revision_reg_ptr = (unsigned int *) AP1xx_FPGA_REV_ADDR;
- unsigned int device = (*revision_reg_ptr & AP1xx_TARGET_MASK);
-
- p[SYSACE_CTRLREG0] = 0x0;
-
- /* add platform and device to banner */
- switch (device) {
- case AP1xx_AP107_TARGET:
- puts (AP1xx_AP107_TARGET_STR);
- break;
- case AP1xx_AP120_TARGET:
- puts (AP1xx_AP120_TARGET_STR);
- break;
- case AP1xx_AP130_TARGET:
- puts (AP1xx_AP130_TARGET_STR);
- break;
- case AP1xx_AP1070_TARGET:
- puts (AP1xx_AP1070_TARGET_STR);
- break;
- case AP1xx_AP1100_TARGET:
- puts (AP1xx_AP1100_TARGET_STR);
- break;
- default:
- puts (AP1xx_UNKNOWN_STR);
- break;
- }
- puts (AP1xx_TARGET_STR);
- puts (" with ");
-
- switch (get_platform ()) {
- case AP100_BASELINE_PLATFORM:
- case AP1000_BASELINE_PLATFORM:
- puts (AP1xx_BASELINE_PLATFORM_STR);
- break;
- case AP1xx_QUADGE_PLATFORM:
- puts (AP1xx_QUADGE_PLATFORM_STR);
- break;
- case AP1xx_MGT_REF_PLATFORM:
- puts (AP1xx_MGT_REF_PLATFORM_STR);
- break;
- case AP1xx_STANDARD_PLATFORM:
- puts (AP1xx_STANDARD_PLATFORM_STR);
- break;
- case AP1xx_DUAL_PLATFORM:
- puts (AP1xx_DUAL_PLATFORM_STR);
- break;
- case AP1xx_BASE_SRAM_PLATFORM:
- puts (AP1xx_BASE_SRAM_PLATFORM_STR);
- break;
- case AP1xx_PCI_PCB_TESTPLATFORM:
- case AP1000_PCI_PCB_TESTPLATFORM:
- puts (AP1xx_PCI_PCB_TESTPLATFORM_STR);
- break;
- case AP1xx_DUAL_GE_MEZZ_TESTPLATFORM:
- puts (AP1xx_DUAL_GE_MEZZ_TESTPLATFORM_STR);
- break;
- case AP1xx_SFP_MEZZ_TESTPLATFORM:
- puts (AP1xx_SFP_MEZZ_TESTPLATFORM_STR);
- break;
- default:
- puts (AP1xx_UNKNOWN_STR);
- break;
- }
-
- if ((get_platform () & AP1xx_TESTPLATFORM_MASK) != 0) {
- puts (AP1xx_TESTPLATFORM_STR);
- } else {
- puts (AP1xx_PLATFORM_STR);
- }
-
- putc ('\n');
-
- puts ("Serial#: ");
-
- if (l < 0) {
- printf ("### No HW ID - assuming AMIRIX");
- } else {
- int i;
-
- for (i = 0; i < l; ++i) {
- if (buf[i] == ' ') {
- buf[i] = '\0';
- break;
- }
- }
-
- puts(buf);
- }
-
- putc ('\n');
-
- return (0);
-}
-
-
-phys_size_t initdram (int board_type)
-{
- char buf[64];
- int i = getenv_f("dramsize", buf, sizeof(buf));
-
- if (i > 0) {
- char *s = buf;
- if ((s[0] == '0') && ((s[1] == 'x') || (s[1] == 'X'))) {
- s += 2;
- }
- return (long int)simple_strtoul (s, NULL, 16);
- } else {
- /* give all 64 MB */
- return 64 * 1024 * 1024;
- }
-}
-
-unsigned int get_platform (void)
-{
- unsigned int *revision_reg_ptr = (unsigned int *) AP1xx_FPGA_REV_ADDR;
-
- return (*revision_reg_ptr & AP1xx_PLATFORM_MASK);
-}
-
-#if 0 /* loadace is not working; it appears to be a hardware issue with the system ace. */
-/*
- This function loads FPGA configurations from the SystemACE CompactFlash
-*/
-int do_loadace (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned char *p = (unsigned char *) AP1000_SYSACE_REGBASE;
- int cfg;
-
- if ((p[SYSACE_STATREG0] & 0x10) == 0) {
- p[SYSACE_CTRLREG0] = 0x80;
- printf ("\nNo CompactFlash Detected\n\n");
- p[SYSACE_CTRLREG0] = 0x00;
- return 1;
- }
-
- /* reset configuration controller: | 0x80 */
- /* select cpflash & ~0x40 */
- /* cfg start | 0x20 */
- /* wait for cfgstart & ~0x10 */
- /* force cfgmode: | 0x08 */
- /* do no force cfgaddr: & ~0x04 */
- /* clear mpulock: & ~0x02 */
- /* do not force lock request & ~0x01 */
-
- p[SYSACE_CTRLREG0] = 0x80 | 0x20 | 0x08;
- p[SYSACE_CTRLREG1] = 0x00;
-
- /* force config address if arg2 exists */
- if (argc == 2) {
- cfg = simple_strtoul (argv[1], NULL, 10);
-
- if (cfg > 7) {
- printf ("\nInvalid Configuration\n\n");
- p[SYSACE_CTRLREG0] = 0x00;
- return 1;
- }
- /* Set config address */
- p[SYSACE_CTRLREG1] = (cfg << 5);
- /* force cfgaddr */
- p[SYSACE_CTRLREG0] |= 0x04;
-
- } else {
- cfg = (p[SYSACE_STATREG1] & 0xE0) >> 5;
- }
-
- /* release configuration controller */
- printf ("\nLoading V2PRO with config %d...\n", cfg);
- p[SYSACE_CTRLREG0] &= ~0x80;
-
-
- while ((p[SYSACE_STATREG1] & 0x01) == 0) {
-
- if (p[SYSACE_ERRREG0] & 0x80) {
- /* attempting to load an invalid configuration makes the cpflash */
- /* appear to be removed. Reset here to avoid that problem */
- p[SYSACE_CTRLREG0] = 0x80;
- printf ("\nConfiguration %d Read Error\n\n", cfg);
- p[SYSACE_CTRLREG0] = 0x00;
- return 1;
- }
- }
-
- p[SYSACE_CTRLREG0] |= 0x20;
-
- return 0;
-}
-#endif
-
-/** Console command to display and set the software reconfigure byte
- * <pre>
- * swconfig - display the current value of the software reconfigure byte
- * swconfig [#] - change the software reconfigure byte to #
- * </pre>
- * @param *cmdtp [IN] as passed by run_command (ignored)
- * @param flag [IN] as passed by run_command (ignored)
- * @param argc [IN] as passed by run_command if 1, display, if 2 change
- * @param *argv[] [IN] contains the parameters to use
- * @return
- * <pre>
- * 0 if passed
- * -1 if failed
- * </pre>
- */
-int do_swconfigbyte (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned char *sector_buffer = NULL;
- unsigned char input_char;
- int write_result;
- unsigned int input_uint;
-
- /* display value if no argument */
- if (argc < 2) {
- printf ("Software configuration byte is currently: 0x%02x\n",
- *((unsigned char *) (SW_BYTE_SECTOR_ADDR +
- SW_BYTE_SECTOR_OFFSET)));
- return 0;
- } else if (argc > 3) {
- printf ("Too many arguments\n");
- return -1;
- }
-
- /* if 3 arguments, 3rd argument is the address to use */
- if (argc == 3) {
- input_uint = simple_strtoul (argv[1], NULL, 16);
- sector_buffer = (unsigned char *) input_uint;
- } else {
- sector_buffer = (unsigned char *) DEFAULT_TEMP_ADDR;
- }
-
- input_char = simple_strtoul (argv[1], NULL, 0);
- if ((input_char & ~SW_BYTE_MASK) != 0) {
- printf ("Input of 0x%02x will be masked to 0x%02x\n",
- input_char, (input_char & SW_BYTE_MASK));
- input_char = input_char & SW_BYTE_MASK;
- }
-
- memcpy (sector_buffer, (void *) SW_BYTE_SECTOR_ADDR,
- SW_BYTE_SECTOR_SIZE);
- sector_buffer[SW_BYTE_SECTOR_OFFSET] = input_char;
-
-
- printf ("Erasing Flash...");
- if (flash_sect_erase
- (SW_BYTE_SECTOR_ADDR,
- (SW_BYTE_SECTOR_ADDR + SW_BYTE_SECTOR_OFFSET))) {
- return -1;
- }
-
- printf ("Writing to Flash... ");
- write_result =
- flash_write ((char *)sector_buffer, SW_BYTE_SECTOR_ADDR,
- SW_BYTE_SECTOR_SIZE);
- if (write_result != 0) {
- flash_perror (write_result);
- return -1;
- } else {
- printf ("done\n");
- printf ("Software configuration byte is now: 0x%02x\n",
- *((unsigned char *) (SW_BYTE_SECTOR_ADDR +
- SW_BYTE_SECTOR_OFFSET)));
- }
-
- return 0;
-}
-
-#define ONE_SECOND 1000000
-
-int do_pause (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- int pause_time;
- unsigned int delay_time;
- int break_loop = 0;
-
- /* display value if no argument */
- if (argc < 2) {
- pause_time = 1;
- }
-
- else if (argc > 2) {
- printf ("Too many arguments\n");
- return -1;
- } else {
- pause_time = simple_strtoul (argv[1], NULL, 0);
- }
-
- printf ("Pausing with a poll time of %d, press any key to reactivate\n", pause_time);
- delay_time = pause_time * ONE_SECOND;
- while (break_loop == 0) {
- udelay (delay_time);
- if (serial_tstc () != 0) {
- break_loop = 1;
- /* eat user key presses */
- while (serial_tstc () != 0) {
- serial_getc ();
- }
- }
- }
-
- return 0;
-}
-
-int do_swreconfig (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- printf ("Triggering software reconfigure (software config byte is 0x%02x)...\n",
- *((unsigned char *) (SW_BYTE_SECTOR_ADDR + SW_BYTE_SECTOR_OFFSET)));
- udelay (1000);
- *((unsigned char *) AP1000_CPLD_BASE) = 1;
-
- return 0;
-}
-
-#define GET_DECIMAL(low_byte) ((low_byte >> 5) * 125)
-#define TEMP_BUSY_BIT 0x80
-#define TEMP_LHIGH_BIT 0x40
-#define TEMP_LLOW_BIT 0x20
-#define TEMP_EHIGH_BIT 0x10
-#define TEMP_ELOW_BIT 0x08
-#define TEMP_OPEN_BIT 0x04
-#define TEMP_ETHERM_BIT 0x02
-#define TEMP_LTHERM_BIT 0x01
-
-int do_temp_sensor (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- char cmd;
- int ret_val = 0;
- unsigned char temp_byte;
- int temp;
- int temp_low;
- int low;
- int low_low;
- int high;
- int high_low;
- int therm;
- unsigned char user_data[4] = { 0 };
- int user_data_count = 0;
- int ii;
-
- if (argc > 1) {
- cmd = argv[1][0];
- } else {
- cmd = 's'; /* default to status */
- }
-
- user_data_count = argc - 2;
- for (ii = 0; ii < user_data_count; ii++) {
- user_data[ii] = simple_strtoul (argv[2 + ii], NULL, 0);
- }
- switch (cmd) {
- case 's':
- if (I2CAccess
- (0x2, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- printf ("Status : 0x%02x ", temp_byte);
- if (temp_byte & TEMP_BUSY_BIT)
- printf ("BUSY ");
-
- if (temp_byte & TEMP_LHIGH_BIT)
- printf ("LHIGH ");
-
- if (temp_byte & TEMP_LLOW_BIT)
- printf ("LLOW ");
-
- if (temp_byte & TEMP_EHIGH_BIT)
- printf ("EHIGH ");
-
- if (temp_byte & TEMP_ELOW_BIT)
- printf ("ELOW ");
-
- if (temp_byte & TEMP_OPEN_BIT)
- printf ("OPEN ");
-
- if (temp_byte & TEMP_ETHERM_BIT)
- printf ("ETHERM ");
-
- if (temp_byte & TEMP_LTHERM_BIT)
- printf ("LTHERM");
-
- printf ("\n");
-
- if (I2CAccess
- (0x3, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- printf ("Config : 0x%02x ", temp_byte);
-
- if (I2CAccess
- (0x4, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- printf ("\n");
- goto fail;
- }
- printf ("Conversion: 0x%02x\n", temp_byte);
- if (I2CAccess
- (0x22, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- printf ("Cons Alert: 0x%02x ", temp_byte);
-
- if (I2CAccess
- (0x21, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- printf ("\n");
- goto fail;
- }
- printf ("Therm Hyst: %d\n", temp_byte);
-
- if (I2CAccess
- (0x0, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- temp = temp_byte;
- if (I2CAccess
- (0x6, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- low = temp_byte;
- if (I2CAccess
- (0x5, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- high = temp_byte;
- if (I2CAccess
- (0x20, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- therm = temp_byte;
- printf ("Local Temp: %2d Low: %2d High: %2d THERM: %2d\n", temp, low, high, therm);
-
- if (I2CAccess
- (0x1, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- temp = temp_byte;
- if (I2CAccess
- (0x10, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- temp_low = temp_byte;
- if (I2CAccess
- (0x8, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- low = temp_byte;
- if (I2CAccess
- (0x14, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- low_low = temp_byte;
- if (I2CAccess
- (0x7, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- high = temp_byte;
- if (I2CAccess
- (0x13, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- high_low = temp_byte;
- if (I2CAccess
- (0x19, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- therm = temp_byte;
- if (I2CAccess
- (0x11, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &temp_byte, I2C_READ) != 0) {
- goto fail;
- }
- printf ("Ext Temp : %2d.%03d Low: %2d.%03d High: %2d.%03d THERM: %2d Offset: %2d\n", temp, GET_DECIMAL (temp_low), low, GET_DECIMAL (low_low), high, GET_DECIMAL (high_low), therm, temp_byte);
- break;
- case 'l': /* alter local limits : low, high, therm */
- if (argc < 3) {
- goto usage;
- }
-
- /* low */
- if (I2CAccess
- (0xC, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &user_data[0], I2C_WRITE) != 0) {
- goto fail;
- }
-
- if (user_data_count > 1) {
- /* high */
- if (I2CAccess
- (0xB, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &user_data[1], I2C_WRITE) != 0) {
- goto fail;
- }
- }
-
- if (user_data_count > 2) {
- /* therm */
- if (I2CAccess
- (0x20, I2C_SENSOR_DEV,
- I2C_SENSOR_CHIP_SEL, &user_data[2],
- I2C_WRITE) != 0) {
- goto fail;
- }
- }
- break;
- case 'e': /* alter external limits: low, high, therm, offset */
- if (argc < 3) {
- goto usage;
- }
-
- /* low */
- if (I2CAccess
- (0xE, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &user_data[0], I2C_WRITE) != 0) {
- goto fail;
- }
-
- if (user_data_count > 1) {
- /* high */
- if (I2CAccess
- (0xD, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &user_data[1], I2C_WRITE) != 0) {
- goto fail;
- }
- }
-
- if (user_data_count > 2) {
- /* therm */
- if (I2CAccess
- (0x19, I2C_SENSOR_DEV,
- I2C_SENSOR_CHIP_SEL, &user_data[2],
- I2C_WRITE) != 0) {
- goto fail;
- }
- }
-
- if (user_data_count > 3) {
- /* offset */
- if (I2CAccess
- (0x11, I2C_SENSOR_DEV,
- I2C_SENSOR_CHIP_SEL, &user_data[3],
- I2C_WRITE) != 0) {
- goto fail;
- }
- }
- break;
- case 'c': /* alter config settings: config, conv, cons alert, therm hyst */
- if (argc < 3) {
- goto usage;
- }
-
- /* config */
- if (I2CAccess
- (0x9, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &user_data[0], I2C_WRITE) != 0) {
- goto fail;
- }
-
- if (user_data_count > 1) {
- /* conversion */
- if (I2CAccess
- (0xA, I2C_SENSOR_DEV, I2C_SENSOR_CHIP_SEL,
- &user_data[1], I2C_WRITE) != 0) {
- goto fail;
- }
- }
-
- if (user_data_count > 2) {
- /* cons alert */
- if (I2CAccess
- (0x22, I2C_SENSOR_DEV,
- I2C_SENSOR_CHIP_SEL, &user_data[2],
- I2C_WRITE) != 0) {
- goto fail;
- }
- }
-
- if (user_data_count > 3) {
- /* therm hyst */
- if (I2CAccess
- (0x21, I2C_SENSOR_DEV,
- I2C_SENSOR_CHIP_SEL, &user_data[3],
- I2C_WRITE) != 0) {
- goto fail;
- }
- }
- break;
- default:
- goto usage;
- }
-
- goto done;
-fail:
- printf ("Access to sensor failed\n");
- ret_val = -1;
- goto done;
-usage:
- printf ("Usage:\n%s\n", cmdtp->help);
-
-done:
- return ret_val;
-}
-
-U_BOOT_CMD (temp, 6, 0, do_temp_sensor,
- "interact with the temperature sensor",
- "temp [s]\n"
- " - Show status.\n"
- "temp l LOW [HIGH] [THERM]\n"
- " - Set local limits.\n"
- "temp e LOW [HIGH] [THERM] [OFFSET]\n"
- " - Set external limits.\n"
- "temp c CONFIG [CONVERSION] [CONS. ALERT] [THERM HYST]\n"
- " - Set config options.\n"
- "\n"
- "All values can be decimal or hex (hex preceded with 0x).\n"
- "Only whole numbers are supported for external limits.");
-
-#if 0
-U_BOOT_CMD (loadace, 2, 0, do_loadace,
- "load fpga configuration from System ACE compact flash",
- "N\n"
- " - Load configuration N (0-7) from System ACE compact flash\n"
- "loadace\n" " - loads default configuration");
-#endif
-
-U_BOOT_CMD (swconfig, 2, 0, do_swconfigbyte,
- "display or modify the software configuration byte",
- "N [ADDRESS]\n"
- " - set software configuration byte to N, optionally use ADDRESS as\n"
- " location of buffer for flash copy\n"
- "swconfig\n" " - display software configuration byte");
-
-U_BOOT_CMD (pause, 2, 0, do_pause,
- "sleep processor until any key is pressed with poll time of N seconds",
- "N\n"
- " - sleep processor until any key is pressed with poll time of N seconds\n"
- "pause\n"
- " - sleep processor until any key is pressed with poll time of 1 second");
-
-U_BOOT_CMD (swrecon, 1, 0, do_swreconfig,
- "trigger a board reconfigure to the software selected configuration",
- "\n"
- " - trigger a board reconfigure to the software selected configuration");
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
+++ /dev/null
-/*
- * ap1000.h: AP1000 (e.g. AP1070, AP1100) board specific definitions and functions that are needed globally
- *
- * Author : James MacAulay
- *
- * This software may be used and distributed according to the terms of
- * the GNU General Public License (GPL) version 2, incorporated herein by
- * reference. Drivers based on or derived from this code fall under the GPL
- * and must retain the authorship, copyright and this license notice. This
- * file is not a complete program and may only be used when the entire
- * program is licensed under the GPL.
- *
- */
-
-#ifndef __AP1000_H
-#define __AP1000_H
-
-/*
- * Revision Register stuff
- */
-#define AP1xx_FPGA_REV_ADDR 0x29000000
-
-#define AP1xx_PLATFORM_MASK 0xFF000000
-#define AP100_BASELINE_PLATFORM 0x01000000
-#define AP1xx_QUADGE_PLATFORM 0x02000000
-#define AP1xx_MGT_REF_PLATFORM 0x03000000
-#define AP1xx_STANDARD_PLATFORM 0x04000000
-#define AP1xx_DUAL_PLATFORM 0x05000000
-#define AP1xx_BASE_SRAM_PLATFORM 0x06000000
-
-#define AP1000_BASELINE_PLATFORM 0x21000000
-
-#define AP1xx_TESTPLATFORM_MASK 0xC0000000
-#define AP1xx_PCI_PCB_TESTPLATFORM 0xC0000000
-#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM 0xC1000000
-#define AP1xx_SFP_MEZZ_TESTPLATFORM 0xC2000000
-
-#define AP1000_PCI_PCB_TESTPLATFORM 0xC3000000
-
-#define AP1xx_TARGET_MASK 0x00FF0000
-#define AP1xx_AP107_TARGET 0x00010000
-#define AP1xx_AP120_TARGET 0x00020000
-#define AP1xx_AP130_TARGET 0x00030000
-#define AP1xx_AP1070_TARGET 0x00040000
-#define AP1xx_AP1100_TARGET 0x00050000
-
-#define AP1xx_UNKNOWN_STR "Unknown"
-
-#define AP1xx_PLATFORM_STR " Platform"
-#define AP1xx_BASELINE_PLATFORM_STR "Baseline"
-#define AP1xx_QUADGE_PLATFORM_STR "Quad GE"
-#define AP1xx_MGT_REF_PLATFORM_STR "MGT Reference"
-#define AP1xx_STANDARD_PLATFORM_STR "Standard"
-#define AP1xx_DUAL_PLATFORM_STR "Dual"
-#define AP1xx_BASE_SRAM_PLATFORM_STR "Baseline with SRAM"
-
-#define AP1xx_TESTPLATFORM_STR " Test Platform"
-#define AP1xx_PCI_PCB_TESTPLATFORM_STR "Base"
-#define AP1xx_DUAL_GE_MEZZ_TESTPLATFORM_STR "Dual GE Mezzanine"
-#define AP1xx_SFP_MEZZ_TESTPLATFORM_STR "SFP Mezzanine"
-
-#define AP1xx_TARGET_STR " Board"
-#define AP1xx_AP107_TARGET_STR "AP107"
-#define AP1xx_AP120_TARGET_STR "AP120"
-#define AP1xx_AP130_TARGET_STR "AP130"
-
-#define AP1xx_AP1070_TARGET_STR "AP1070"
-#define AP1xx_AP1100_TARGET_STR "AP1100"
-
-/*
- * Flash Stuff
- */
-#define AP1xx_PROGRAM_FLASH_INDEX 0
-#define AP1xx_CONFIG_FLASH_INDEX 1
-
-/*
- * System Ace Stuff
- */
-#define AP1000_SYSACE_REGBASE 0x28000000
-
-#define SYSACE_STATREG0 0x04 /* 7:0 */
-#define SYSACE_STATREG1 0x05 /* 15:8 */
-#define SYSACE_STATREG2 0x06 /* 23:16 */
-#define SYSACE_STATREG3 0x07 /* 31:24 */
-
-#define SYSACE_ERRREG0 0x08 /* 7:0 */
-#define SYSACE_ERRREG1 0x09 /* 15:8 */
-#define SYSACE_ERRREG2 0x0a /* 23:16 */
-#define SYSACE_ERRREG3 0x0b /* 31:24 */
-
-#define SYSACE_CTRLREG0 0x18 /* 7:0 */
-#define SYSACE_CTRLREG1 0x19 /* 15:8 */
-#define SYSACE_CTRLREG2 0x1A /* 23:16 */
-#define SYSACE_CTRLREG3 0x1B /* 31:24 */
-
-/*
- * Software reconfig thing
- */
-#define SW_BYTE_SECTOR_ADDR 0x24FE0000
-#define SW_BYTE_SECTOR_OFFSET 0x0001FFFF
-#define SW_BYTE_SECTOR_SIZE 0x00020000
-#define SW_BYTE_MASK 0x00000003
-
-#define DEFAULT_TEMP_ADDR 0x00100000
-
-#define AP1000_CPLD_BASE 0x26000000
-
-/* PowerSpan II Stuff */
-#define PSII_SYNC() asm("eieio")
-#define PSPAN_BASEADDR 0x30000000
-#define EEPROM_DEFAULT { 0x01, /* Byte 0 - Long Load = 0x02, short = 01, use 0xff for try no load */ \
- 0x0,0x0,0x0, /* Bytes 1 - 3 Power span reserved */ \
- 0x0, /* Byte 4 - Powerspan reserved - start of short load */ \
- 0x0F, /* Byte 5 - Enable PCI 1 & 2 as Bus masters and Memory targets. */ \
- 0x0E, /* Byte 6 - PCI 1 Target image prefetch - on for image 0,1,2, off for i20 & 3. */ \
- 0x00, 0x00, /* Byte 7,8 - PCI-1 Subsystem ID - */ \
- 0x00, 0x00, /* Byte 9,10 - PCI-1 Subsystem Vendor Id - */ \
- 0x00, /* Byte 11 - No PCI interrupt generation on PCI-1 PCI-2 int A */ \
- 0x1F, /* Byte 12 - PCI-1 enable bridge registers, all target images */ \
- 0xBA, /* Byte 13 - Target 0 image 128 Meg(Ram), Target 1 image 64 Meg. (config Flash/CPLD )*/ \
- 0xA0, /* Byte 14 - Target 2 image 64 Meg(program Flash), target 3 64k. */ \
- 0x00, /* Byte 15 - Vital Product Data Disabled. */ \
- 0x88, /* Byte 16 - PCI arbiter config complete, all requests routed through PCI-1, Unlock PCI-1 */ \
- 0x40, /* Byte 17 - Interrupt direction control - PCI-1 Int A out, everything else in. */ \
- 0x00, /* Byte 18 - I2O disabled */ \
- 0x00, /* Byte 19 - PCI-2 Target image prefetch - off for all images. */ \
- 0x00,0x00, /* Bytes 20,21 - PCI 2 Subsystem Id */ \
- 0x00,0x00, /* Bytes 22,23 - PCI 2 Subsystem Vendor id */ \
- 0x0C, /* Byte 24 - PCI-2 BAR enables, target image 0, & 1 */ \
- 0xBB, /* Byte 25 - PCI-2 target 0 - 128 Meg(Ram), target 1 - 128 Meg (program/config flash) */ \
- 0x00, /* Byte 26 - PCI-2 target 2 & 3 unused. */ \
- 0x00,0x00,0x00,0x00,0x00, /* Bytes 27,28,29,30, 31 - Reserved */ \
- /* Long Load Information */ \
- 0x82,0x60, /* Bytes 32,33 - PCI-1 Device ID - Powerspan II */ \
- 0x10,0xE3, /* Bytes 24,35 - PCI-1 Vendor ID - Tundra */ \
- 0x06, /* Byte 36 - PCI-1 Class Base - Bridge device. */ \
- 0x80, /* Byte 37 - PCI-1 Class sub class - Other bridge. */ \
- 0x00, /* Byte 38 - PCI-1 Class programing interface - Other bridge */ \
- 0x01, /* Byte 39 - Power span revision 1. */ \
- 0x6E, /* Byte 40 - PB SI0 enabled, translation enabled, decode enabled, 64 Meg */ \
- 0x40, /* Byte 41 - PB SI0 memory command mode, PCI-1 dest */ \
- 0x22, /* Byte 42 - Prefetch discard after read, PCI-little endian conversion, 32 byte prefetch */ \
- 0x00,0x00, /* Bytes 43, 44 - Translation address for SI0, set to zero for now. */ \
- 0x0E, /* Byte 45 - Translation address (0) and PB bus master enables - all. */ \
- 0x2c,00,00, /* Bytes 46,47,48 - PB SI0 processor base address - 0x2C000000 */ \
- 0x30,00,00, /* Bytes 49,50,51 - PB Address for Powerspan registers - 0x30000000, big Endian */ \
- 0x82,0x60, /* Bytes 52, 53 - PCI-2 Device ID - Powerspan II */ \
- 0x10,0xE3, /* Bytes 54,55 - PCI 2 Vendor Id - Tundra */ \
- 0x06, /* Byte 56 - PCI-2 Class Base - Bridge device */ \
- 0x80, /* Byte 57 - PCI-2 Class sub class - Other Bridge. */ \
- 0x00, /* Byte 58 - PCI-2 class programming interface - Other bridge */ \
- 0x01, /* Byte 59 - PCI-2 class revision 1 */ \
- 0x00,0x00,0x00,0x00 }; /* Bytes 60,61, 62, 63 - Powerspan reserved */
-
-
-#define EEPROM_LENGTH 64 /* Long Load */
-
-#define I2C_SENSOR_DEV 0x9
-#define I2C_SENSOR_CHIP_SEL 0x4
-
-/*
- * Board Functions
- */
-void set_eat_machine_checks(int a_flag);
-int get_eat_machine_checks(void);
-unsigned int get_platform(void);
-void* memcpyb(void * dest,const void *src,size_t count);
-int process_bootflag(ulong bootflag);
-void user_led_on(void);
-void user_led_off(void);
-
-#endif /* __COMMON_H_ */
+++ /dev/null
-/**
- * @file flash.c
- */
-
-/*
- * (C) Copyright 2003
- * AMIRIX Systems Inc.
- *
- * Originated from ppcboot-2.0.0/board/esd/cpci440/strataflash.c
- *
- * (C) Copyright 2002
- * Brad Kemp, Seranoa Networks, Brad.Kemp@seranoa.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/processor.h>
-
-#undef DEBUG_FLASH
-/*
- * This file implements a Common Flash Interface (CFI) driver for ppcboot.
- * The width of the port and the width of the chips are determined at initialization.
- * These widths are used to calculate the address for access CFI data structures.
- * It has been tested on an Intel Strataflash implementation.
- *
- * References
- * JEDEC Standard JESD68 - Common Flash Interface (CFI)
- * JEDEC Standard JEP137-A Common Flash Interface (CFI) ID Codes
- * Intel Application Note 646 Common Flash Interface (CFI) and Command Sets
- * Intel 290667-008 3 Volt Intel StrataFlash Memory datasheet
- *
- * TODO
- * Use Primary Extended Query table (PRI) and Alternate Algorithm Query Table (ALT) to determine if protection is available
- * Add support for other command sets Use the PRI and ALT to determine command set
- * Verify erase and program timeouts.
- */
-
-#define FLASH_CMD_CFI 0x98
-#define FLASH_CMD_READ_ID 0x90
-#define FLASH_CMD_RESET 0xff
-#define FLASH_CMD_BLOCK_ERASE 0x20
-#define FLASH_CMD_ERASE_CONFIRM 0xD0
-#define FLASH_CMD_WRITE 0x40
-#define FLASH_CMD_PROTECT 0x60
-#define FLASH_CMD_PROTECT_SET 0x01
-#define FLASH_CMD_PROTECT_CLEAR 0xD0
-#define FLASH_CMD_CLEAR_STATUS 0x50
-#define FLASH_CMD_WRITE_TO_BUFFER 0xE8
-#define FLASH_CMD_WRITE_BUFFER_CONFIRM 0xD0
-
-#define FLASH_STATUS_DONE 0x80
-#define FLASH_STATUS_ESS 0x40
-#define FLASH_STATUS_ECLBS 0x20
-#define FLASH_STATUS_PSLBS 0x10
-#define FLASH_STATUS_VPENS 0x08
-#define FLASH_STATUS_PSS 0x04
-#define FLASH_STATUS_DPS 0x02
-#define FLASH_STATUS_R 0x01
-#define FLASH_STATUS_PROTECT 0x01
-
-#define FLASH_OFFSET_CFI 0x55
-#define FLASH_OFFSET_CFI_RESP 0x10
-#define FLASH_OFFSET_WTOUT 0x1F
-#define FLASH_OFFSET_WBTOUT 0x20
-#define FLASH_OFFSET_ETOUT 0x21
-#define FLASH_OFFSET_CETOUT 0x22
-#define FLASH_OFFSET_WMAX_TOUT 0x23
-#define FLASH_OFFSET_WBMAX_TOUT 0x24
-#define FLASH_OFFSET_EMAX_TOUT 0x25
-#define FLASH_OFFSET_CEMAX_TOUT 0x26
-#define FLASH_OFFSET_SIZE 0x27
-#define FLASH_OFFSET_INTERFACE 0x28
-#define FLASH_OFFSET_BUFFER_SIZE 0x2A
-#define FLASH_OFFSET_NUM_ERASE_REGIONS 0x2C
-#define FLASH_OFFSET_ERASE_REGIONS 0x2D
-#define FLASH_OFFSET_PROTECT 0x02
-#define FLASH_OFFSET_USER_PROTECTION 0x85
-#define FLASH_OFFSET_INTEL_PROTECTION 0x81
-
-#define FLASH_MAN_CFI 0x01000000
-
-typedef union {
- unsigned char c;
- unsigned short w;
- unsigned long l;
-} cfiword_t;
-
-typedef union {
- unsigned char *cp;
- unsigned short *wp;
- unsigned long *lp;
-} cfiptr_t;
-
-#define NUM_ERASE_REGIONS 4
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-
-static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c);
-static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf);
-static void flash_write_cmd (flash_info_t * info, int sect, uchar offset,
- uchar cmd);
-static int flash_isequal (flash_info_t * info, int sect, uchar offset,
- uchar cmd);
-static int flash_isset (flash_info_t * info, int sect, uchar offset,
- uchar cmd);
-static int flash_detect_cfi (flash_info_t * info);
-static ulong flash_get_size (ulong base, int banknum);
-static int flash_write_cfiword (flash_info_t * info, ulong dest,
- cfiword_t cword);
-static int flash_full_status_check (flash_info_t * info, ulong sector,
- ulong tout, char *prompt);
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
- int len);
-#endif
-/*-----------------------------------------------------------------------
- * create an address based on the offset and the port width
- */
-uchar *flash_make_addr (flash_info_t * info, int sect, int offset)
-{
- return ((uchar *) (info->start[sect] + (offset * info->chipwidth)));
-}
-
-/*-----------------------------------------------------------------------
- * read a character at a port width address
- */
-uchar flash_read_uchar (flash_info_t * info, uchar offset)
-{
- if (info->portwidth == FLASH_CFI_8BIT) {
- volatile uchar *cp;
- uchar c;
-
- cp = flash_make_addr (info, 0, offset);
- c = *cp;
-#ifdef DEBUG_FLASH
- printf ("flash_read_uchar offset=%04x ptr=%08x c=%02x\n",
- offset, (unsigned int) cp, c);
-#endif
- return (c);
-
- } else if (info->portwidth == FLASH_CFI_16BIT) {
- volatile ushort *sp;
- ushort s;
- uchar c;
-
- sp = (ushort *) flash_make_addr (info, 0, offset);
- s = *sp;
- c = (uchar) s;
-#ifdef DEBUG_FLASH
- printf ("flash_read_uchar offset=%04x ptr=%08x s=%04x c=%02x\n", offset, (unsigned int) sp, s, c);
-#endif
- return (c);
-
- }
-
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * read a short word by swapping for ppc format.
- */
-ushort flash_read_ushort (flash_info_t * info, int sect, uchar offset)
-{
- if (info->portwidth == FLASH_CFI_8BIT) {
- volatile uchar *cp;
- uchar c0, c1;
- ushort s;
-
- cp = flash_make_addr (info, 0, offset);
- c1 = cp[2];
- c0 = cp[0];
- s = c1 << 8 | c0;
-#ifdef DEBUG_FLASH
- printf ("flash_read_ushort offset=%04x ptr=%08x c1=%02x c0=%02x s=%04x\n", offset, (unsigned int) cp, c1, c0, s);
-#endif
- return (s);
-
- } else if (info->portwidth == FLASH_CFI_16BIT) {
- volatile ushort *sp;
- ushort s;
- uchar c0, c1;
-
- sp = (ushort *) flash_make_addr (info, 0, offset);
- s = *sp;
- c1 = (uchar) sp[1];
- c0 = (uchar) sp[0];
- s = c1 << 8 | c0;
-#ifdef DEBUG_FLASH
- printf ("flash_read_ushort offset=%04x ptr=%08x c1=%02x c0=%02x s=%04x\n", offset, (unsigned int) sp, c1, c0, s);
-#endif
- return (s);
-
- }
-
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * read a long word by picking the least significant byte of each maiximum
- * port size word. Swap for ppc format.
- */
-ulong flash_read_long (flash_info_t * info, int sect, uchar offset)
-{
- if (info->portwidth == FLASH_CFI_8BIT) {
- volatile uchar *cp;
- uchar c0, c1, c2, c3;
- ulong l;
-
- cp = flash_make_addr (info, 0, offset);
- c3 = cp[6];
- c2 = cp[4];
- c1 = cp[2];
- c0 = cp[0];
- l = c3 << 24 | c2 << 16 | c1 << 8 | c0;
-#ifdef DEBUG_FLASH
- printf ("flash_read_long offset=%04x ptr=%08x c3=%02x c2=%02x c1=%02x c0=%02x l=%08x\n", offset, (unsigned int) cp, c3, c2, c1, c0, l);
-#endif
- return (l);
-
- } else if (info->portwidth == FLASH_CFI_16BIT) {
- volatile ushort *sp;
- uchar c0, c1, c2, c3;
- ulong l;
-
- sp = (ushort *) flash_make_addr (info, 0, offset);
- c3 = (uchar) sp[3];
- c2 = (uchar) sp[2];
- c1 = (uchar) sp[1];
- c0 = (uchar) sp[0];
- l = c3 << 24 | c2 << 16 | c1 << 8 | c0;
-#ifdef DEBUG_FLASH
- printf ("flash_read_long offset=%04x ptr=%08x c3=%02x c2=%02x c1=%02x c0=%02x l=%08x\n", offset, (unsigned int) sp, c3, c2, c1, c0, l);
-#endif
- return (l);
-
- }
-
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- */
-unsigned long flash_init (void)
-{
- unsigned long size;
-
- size = 0;
-
- flash_info[0].flash_id = FLASH_UNKNOWN;
- flash_info[0].portwidth = FLASH_CFI_16BIT;
- flash_info[0].chipwidth = FLASH_CFI_16BIT;
- size += flash_info[0].size = flash_get_size (CONFIG_SYS_PROGFLASH_BASE, 0);
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 1, flash_info[0].size, flash_info[0].size << 20);
- };
-
- flash_info[1].flash_id = FLASH_UNKNOWN;
- flash_info[1].portwidth = FLASH_CFI_8BIT;
- flash_info[1].chipwidth = FLASH_CFI_16BIT;
- size += flash_info[1].size = flash_get_size (CONFIG_SYS_CONFFLASH_BASE, 1);
- if (flash_info[1].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 2, flash_info[1].size, flash_info[1].size << 20);
- };
-
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- int rcode = 0;
- int prot;
- int sect;
-
- if (info->flash_id != FLASH_MAN_CFI) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
- if ((s_first < 0) || (s_first > s_last)) {
- printf ("- no sectors to erase\n");
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- } else {
- printf ("\n");
- }
-
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- flash_write_cmd (info, sect, 0,
- FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd (info, sect, 0,
- FLASH_CMD_BLOCK_ERASE);
- flash_write_cmd (info, sect, 0,
- FLASH_CMD_ERASE_CONFIRM);
-
- if (flash_full_status_check
- (info, sect, info->erase_blk_tout, "erase")) {
- rcode = 1;
- } else
- printf (".");
- }
- }
- printf (" done\n");
- return rcode;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- int i;
-
- if (info->flash_id != FLASH_MAN_CFI) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- printf ("CFI conformant FLASH (x%d device in x%d mode)",
- (info->chipwidth << 3), (info->portwidth << 3));
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
- printf (" Erase timeout %ld ms, write timeout %ld ms, buffer write timeout %ld ms, buffer size %d\n", info->erase_blk_tout, info->write_tout, info->buffer_write_tout, info->buffer_size);
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n");
- printf (" %08lX%5s",
- info->start[i], info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
- return;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong wp;
- ulong cp;
- int aln;
- cfiword_t cword;
- int i, rc;
-
- /* get lower aligned address */
- wp = (addr & ~(info->portwidth - 1));
-
- /* handle unaligned start */
- if ((aln = addr - wp) != 0) {
- cword.l = 0;
- cp = wp;
- for (i = 0; i < aln; ++i, ++cp)
- flash_add_byte (info, &cword, (*(uchar *) cp));
-
- for (; (i < info->portwidth) && (cnt > 0); i++) {
- flash_add_byte (info, &cword, *src++);
- cnt--;
- cp++;
- }
- for (; (cnt == 0) && (i < info->portwidth); ++i, ++cp)
- flash_add_byte (info, &cword, (*(uchar *) cp));
- if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
- return rc;
- wp = cp;
- }
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
- while (cnt >= info->portwidth) {
- i = info->buffer_size > cnt ? cnt : info->buffer_size;
- if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
- return rc;
- wp += i;
- src += i;
- cnt -= i;
- }
-#else
- /* handle the aligned part */
- while (cnt >= info->portwidth) {
- cword.l = 0;
- for (i = 0; i < info->portwidth; i++) {
- flash_add_byte (info, &cword, *src++);
- }
- if ((rc = flash_write_cfiword (info, wp, cword)) != 0)
- return rc;
- wp += info->portwidth;
- cnt -= info->portwidth;
- }
-#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- cword.l = 0;
- for (i = 0, cp = wp; (i < info->portwidth) && (cnt > 0); ++i, ++cp) {
- flash_add_byte (info, &cword, *src++);
- --cnt;
- }
- for (; i < info->portwidth; ++i, ++cp) {
- flash_add_byte (info, &cword, (*(uchar *) cp));
- }
-
- return flash_write_cfiword (info, wp, cword);
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_real_protect (flash_info_t * info, long sector, int prot)
-{
- int retcode = 0;
-
- flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT);
- if (prot)
- flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET);
- else
- flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR);
-
- if ((retcode =
- flash_full_status_check (info, sector, info->erase_blk_tout,
- prot ? "protect" : "unprotect")) == 0) {
-
- info->protect[sector] = prot;
- /* Intel's unprotect unprotects all locking */
- if (prot == 0) {
- int i;
-
- for (i = 0; i < info->sector_count; i++) {
- if (info->protect[i])
- flash_real_protect (info, i, 1);
- }
- }
- }
-
- return retcode;
-}
-
-/*-----------------------------------------------------------------------
- * wait for XSR.7 to be set. Time out with an error if it does not.
- * This routine does not set the flash to read-array mode.
- */
-static int flash_status_check (flash_info_t * info, ulong sector, ulong tout,
- char *prompt)
-{
- ulong start;
-
- /* Wait for command completion */
- start = get_timer (0);
- while (!flash_isset (info, sector, 0, FLASH_STATUS_DONE)) {
- if (get_timer (start) > info->erase_blk_tout) {
- printf ("Flash %s timeout at address %lx\n", prompt,
- info->start[sector]);
- flash_write_cmd (info, sector, 0, FLASH_CMD_RESET);
- return ERR_TIMOUT;
- }
- }
- return ERR_OK;
-}
-
-/*-----------------------------------------------------------------------
- * Wait for XSR.7 to be set, if it times out print an error, otherwise do a full status check.
- * This routine sets the flash to read-array mode.
- */
-static int flash_full_status_check (flash_info_t * info, ulong sector,
- ulong tout, char *prompt)
-{
- int retcode;
-
- retcode = flash_status_check (info, sector, tout, prompt);
- if ((retcode == ERR_OK)
- && !flash_isequal (info, sector, 0, FLASH_STATUS_DONE)) {
- retcode = ERR_INVAL;
- printf ("Flash %s error at address %lx\n", prompt,
- info->start[sector]);
- if (flash_isset
- (info, sector, 0,
- FLASH_STATUS_ECLBS | FLASH_STATUS_PSLBS)) {
- printf ("Command Sequence Error.\n");
- } else if (flash_isset (info, sector, 0, FLASH_STATUS_ECLBS)) {
- printf ("Block Erase Error.\n");
- retcode = ERR_NOT_ERASED;
- } else if (flash_isset (info, sector, 0, FLASH_STATUS_PSLBS)) {
- printf ("Locking Error\n");
- }
- if (flash_isset (info, sector, 0, FLASH_STATUS_DPS)) {
- printf ("Block locked.\n");
- retcode = ERR_PROTECTED;
- }
- if (flash_isset (info, sector, 0, FLASH_STATUS_VPENS))
- printf ("Vpp Low Error.\n");
- }
- flash_write_cmd (info, sector, 0, FLASH_CMD_RESET);
- return retcode;
-}
-
-/*-----------------------------------------------------------------------
- */
-static void flash_add_byte (flash_info_t * info, cfiword_t * cword, uchar c)
-{
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- cword->c = c;
- break;
- case FLASH_CFI_16BIT:
- cword->w = (cword->w << 8) | c;
- break;
- case FLASH_CFI_32BIT:
- cword->l = (cword->l << 8) | c;
- }
-}
-
-/*-----------------------------------------------------------------------
- * make a proper sized command based on the port and chip widths
- */
-static void flash_make_cmd (flash_info_t * info, uchar cmd, void *cmdbuf)
-{
- /*int i; */
- uchar *cp = (uchar *) cmdbuf;
-
- /* for(i=0; i< info->portwidth; i++) */
- /* *cp++ = ((i+1) % info->chipwidth) ? '\0':cmd; */
- if (info->portwidth == FLASH_CFI_8BIT
- && info->chipwidth == FLASH_CFI_16BIT) {
- cp[0] = cmd;
- } else if (info->portwidth == FLASH_CFI_16BIT
- && info->chipwidth == FLASH_CFI_16BIT) {
- cp[0] = '\0';
- cp[1] = cmd;
- };
-}
-
-/*
- * Write a proper sized command to the correct address
- */
-static void flash_write_cmd (flash_info_t * info, int sect, uchar offset,
- uchar cmd)
-{
-
- volatile cfiptr_t addr;
- cfiword_t cword;
-
- addr.cp = flash_make_addr (info, sect, offset);
- flash_make_cmd (info, cmd, &cword);
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- *addr.cp = cword.c;
- break;
- case FLASH_CFI_16BIT:
- *addr.wp = cword.w;
- break;
- case FLASH_CFI_32BIT:
- *addr.lp = cword.l;
- break;
- }
-}
-
-/*-----------------------------------------------------------------------
- */
-static int flash_isequal (flash_info_t * info, int sect, uchar offset,
- uchar cmd)
-{
- cfiptr_t cptr;
- cfiword_t cword;
- int retval;
-
- cptr.cp = flash_make_addr (info, sect, offset);
- flash_make_cmd (info, cmd, &cword);
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- retval = (cptr.cp[0] == cword.c);
- break;
- case FLASH_CFI_16BIT:
- retval = (cptr.wp[0] == cword.w);
- break;
- case FLASH_CFI_32BIT:
- retval = (cptr.lp[0] == cword.l);
- break;
- default:
- retval = 0;
- break;
- }
- return retval;
-}
-
-/*-----------------------------------------------------------------------
- */
-static int flash_isset (flash_info_t * info, int sect, uchar offset,
- uchar cmd)
-{
- cfiptr_t cptr;
- cfiword_t cword;
- int retval;
-
- cptr.cp = flash_make_addr (info, sect, offset);
- flash_make_cmd (info, cmd, &cword);
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- retval = ((cptr.cp[0] & cword.c) == cword.c);
- break;
- case FLASH_CFI_16BIT:
- retval = ((cptr.wp[0] & cword.w) == cword.w);
- break;
- case FLASH_CFI_32BIT:
- retval = ((cptr.lp[0] & cword.l) == cword.l);
- break;
- default:
- retval = 0;
- break;
- }
- return retval;
-}
-
-/*-----------------------------------------------------------------------
- * detect if flash is compatible with the Common Flash Interface (CFI)
- * http://www.jedec.org/download/search/jesd68.pdf
- *
-*/
-static int flash_detect_cfi (flash_info_t * info)
-{
-
-#if 0
- for (info->portwidth = FLASH_CFI_8BIT;
- info->portwidth <= FLASH_CFI_32BIT; info->portwidth <<= 1) {
- for (info->chipwidth = FLASH_CFI_BY8;
- info->chipwidth <= info->portwidth;
- info->chipwidth <<= 1) {
- flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
- flash_write_cmd (info, 0, FLASH_OFFSET_CFI,
- FLASH_CMD_CFI);
- if (flash_isequal
- (info, 0, FLASH_OFFSET_CFI_RESP, 'Q')
- && flash_isequal (info, 0,
- FLASH_OFFSET_CFI_RESP + 1, 'R')
- && flash_isequal (info, 0,
- FLASH_OFFSET_CFI_RESP + 2, 'Y'))
- return 1;
- }
- }
-#endif
- flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
- flash_write_cmd (info, 0, FLASH_OFFSET_CFI, FLASH_CMD_CFI);
- if (flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP, 'Q') &&
- flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 1, 'R') &&
- flash_isequal (info, 0, FLASH_OFFSET_CFI_RESP + 2, 'Y')) {
- return 1;
- } else {
- return 0;
- };
-}
-
-/*
- * The following code cannot be run from FLASH!
- *
- */
-static ulong flash_get_size (ulong base, int banknum)
-{
- flash_info_t *info = &flash_info[banknum];
- int i, j;
- int sect_cnt;
- unsigned long sector;
- unsigned long tmp;
- int size_ratio;
- uchar num_erase_regions;
- int erase_region_size;
- int erase_region_count;
-
- info->start[0] = base;
-
- if (flash_detect_cfi (info)) {
-#ifdef DEBUG_FLASH
- printf ("portwidth=%d chipwidth=%d\n", info->portwidth, info->chipwidth); /* test-only */
-#endif
- size_ratio = 1; /* info->portwidth / info->chipwidth; */
- num_erase_regions =
- flash_read_uchar (info,
- FLASH_OFFSET_NUM_ERASE_REGIONS);
-#ifdef DEBUG_FLASH
- printf ("found %d erase regions\n", num_erase_regions);
-#endif
- sect_cnt = 0;
- sector = base;
- for (i = 0; i < num_erase_regions; i++) {
- if (i > NUM_ERASE_REGIONS) {
- printf ("%d erase regions found, only %d used\n", num_erase_regions, NUM_ERASE_REGIONS);
- break;
- }
- tmp = flash_read_long (info, 0,
- FLASH_OFFSET_ERASE_REGIONS);
- erase_region_count = (tmp & 0xffff) + 1;
- tmp >>= 16;
- erase_region_size =
- (tmp & 0xffff) ? ((tmp & 0xffff) * 256) : 128;
- for (j = 0; j < erase_region_count; j++) {
- info->start[sect_cnt] = sector;
- sector += (erase_region_size * size_ratio);
- info->protect[sect_cnt] =
- flash_isset (info, sect_cnt,
- FLASH_OFFSET_PROTECT,
- FLASH_STATUS_PROTECT);
- sect_cnt++;
- }
- }
-
- info->sector_count = sect_cnt;
- /* multiply the size by the number of chips */
- info->size =
- (1 << flash_read_uchar (info, FLASH_OFFSET_SIZE)) *
- size_ratio;
- info->buffer_size =
- (1 <<
- flash_read_ushort (info, 0,
- FLASH_OFFSET_BUFFER_SIZE));
- tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_ETOUT);
- info->erase_blk_tout =
- (tmp *
- (1 <<
- flash_read_uchar (info, FLASH_OFFSET_EMAX_TOUT)));
- tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WBTOUT);
- info->buffer_write_tout =
- (tmp *
- (1 <<
- flash_read_uchar (info, FLASH_OFFSET_WBMAX_TOUT)));
- tmp = 1 << flash_read_uchar (info, FLASH_OFFSET_WTOUT);
- info->write_tout =
- (tmp *
- (1 <<
- flash_read_uchar (info,
- FLASH_OFFSET_WMAX_TOUT))) / 1000;
- info->flash_id = FLASH_MAN_CFI;
- }
-
- flash_write_cmd (info, 0, 0, FLASH_CMD_RESET);
- return (info->size);
-}
-
-/*-----------------------------------------------------------------------
- */
-static int flash_write_cfiword (flash_info_t * info, ulong dest,
- cfiword_t cword)
-{
- cfiptr_t cptr;
- int flag;
-
- cptr.cp = (uchar *) dest;
-
- /* Check if Flash is (sufficiently) erased */
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- flag = ((cptr.cp[0] & cword.c) == cword.c);
- break;
- case FLASH_CFI_16BIT:
- flag = ((cptr.wp[0] & cword.w) == cword.w);
- break;
- case FLASH_CFI_32BIT:
- flag = ((cptr.lp[0] & cword.l) == cword.l);
- break;
- default:
- return 2;
- }
- if (!flag)
- return 2;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- flash_write_cmd (info, 0, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd (info, 0, 0, FLASH_CMD_WRITE);
-
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- cptr.cp[0] = cword.c;
- break;
- case FLASH_CFI_16BIT:
- cptr.wp[0] = cword.w;
- break;
- case FLASH_CFI_32BIT:
- cptr.lp[0] = cword.l;
- break;
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- return flash_full_status_check (info, 0, info->write_tout, "write");
-}
-
-#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-/* loop through the sectors from the highest address
- * when the passed address is greater or equal to the sector address
- * we have a match
- */
-static int find_sector (flash_info_t * info, ulong addr)
-{
- int sector;
-
- for (sector = info->sector_count - 1; sector >= 0; sector--) {
- if (addr >= info->start[sector])
- break;
- }
- return sector;
-}
-
-static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
- int len)
-{
-
- int sector;
- int cnt;
- int retcode;
- volatile cfiptr_t src;
- volatile cfiptr_t dst;
-
- src.cp = cp;
- dst.cp = (uchar *) dest;
- sector = find_sector (info, dest);
- flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- flash_write_cmd (info, sector, 0, FLASH_CMD_WRITE_TO_BUFFER);
- if ((retcode =
- flash_status_check (info, sector, info->buffer_write_tout,
- "write to buffer")) == ERR_OK) {
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- cnt = len;
- break;
- case FLASH_CFI_16BIT:
- cnt = len >> 1;
- break;
- case FLASH_CFI_32BIT:
- cnt = len >> 2;
- break;
- default:
- return ERR_INVAL;
- break;
- }
- flash_write_cmd (info, sector, 0, (uchar) cnt - 1);
- while (cnt-- > 0) {
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- *dst.cp++ = *src.cp++;
- break;
- case FLASH_CFI_16BIT:
- *dst.wp++ = *src.wp++;
- break;
- case FLASH_CFI_32BIT:
- *dst.lp++ = *src.lp++;
- break;
- default:
- return ERR_INVAL;
- break;
- }
- }
- flash_write_cmd (info, sector, 0,
- FLASH_CMD_WRITE_BUFFER_CONFIRM);
- retcode =
- flash_full_status_check (info, sector,
- info->buffer_write_tout,
- "buffer write");
- }
- flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
- return retcode;
-}
-#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
+++ /dev/null
-/*
- * init.S: Stubs for ppcboot initialization
- *
- * Copyright 2002 Mind NV
- *
- * http://www.mind.be/
- *
- * Author : Peter De Schrijver (p2@mind.be)
- *
- * This software may be used and distributed according to the terms of
- * the GNU General Public License (GPL) version 2, incorporated herein by
- * reference. Drivers based on or derived from this code fall under the GPL
- * and must retain the authorship, copyright and this license notice. This
- * file is not a complete program and may only be used when the entire
- * program is licensed under the GPL.
- *
- */
-
-#include <asm/ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-
- .globl ext_bus_cntlr_init
-ext_bus_cntlr_init:
- blr
+++ /dev/null
-/*
- * (C) Copyright 2003
- * AMIRIX Systems Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-#include <pci.h>
-
-#define PCI_MEM_82559ER_CSR_BASE 0x30200000
-#define PCI_IO_82559ER_CSR_BASE 0x40000200
-
-/** AP1100 specific values */
-#define PSII_BASE 0x30000000 /**< PowerSpan II dual bridge local bus register address */
-#define PSII_CONFIG_ADDR 0x30000290 /**< PowerSpan II Configuration Cycle Address configuration register */
-#define PSII_CONFIG_DATA 0x30000294 /**< PowerSpan II Configuration Cycle Data register. */
-#define PSII_CONFIG_DEST_PCI2 0x01000000 /**< PowerSpan II configuration cycle destination selection, set for PCI2 bus */
-#define PSII_PCI_MEM_BASE 0x30200000 /**< Local Bus address for start of PCI memory space on PCI2 bus. */
-#define PSII_PCI_MEM_SIZE 0x1BE00000 /**< PCI Memory space about 510 Meg. */
-#define AP1000_SYS_MEM_START 0x00000000 /**< System memory starts at 0. */
-#define AP1000_SYS_MEM_SIZE 0x08000000 /**< System memory is 128 Meg. */
-
-/* static int G_verbosity_level = 1; */
-#define G_verbosity_level 1
-
-void write1 (unsigned long addr, unsigned char val)
-{
- volatile unsigned char *p = (volatile unsigned char *) addr;
-
- if (G_verbosity_level > 1)
- printf ("write1: addr=%08x val=%02x\n", (unsigned int) addr,
- val);
- *p = val;
- asm ("eieio");
-}
-
-unsigned char read1 (unsigned long addr)
-{
- unsigned char val;
- volatile unsigned char *p = (volatile unsigned char *) addr;
-
- if (G_verbosity_level > 1)
- printf ("read1: addr=%08x ", (unsigned int) addr);
- val = *p;
- asm ("eieio");
- if (G_verbosity_level > 1)
- printf ("val=%08x\n", val);
- return val;
-}
-
-void write2 (unsigned long addr, unsigned short val)
-{
- volatile unsigned short *p = (volatile unsigned short *) addr;
-
- if (G_verbosity_level > 1)
- printf ("write2: addr=%08x val=%04x -> *p=%04x\n",
- (unsigned int) addr, val,
- ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8));
-
- *p = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
- asm ("eieio");
-}
-
-unsigned short read2 (unsigned long addr)
-{
- unsigned short val;
- volatile unsigned short *p = (volatile unsigned short *) addr;
-
- if (G_verbosity_level > 1)
- printf ("read2: addr=%08x ", (unsigned int) addr);
- val = *p;
- val = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
- asm ("eieio");
- if (G_verbosity_level > 1)
- printf ("*p=%04x -> val=%04x\n",
- ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8), val);
- return val;
-}
-
-void write4 (unsigned long addr, unsigned long val)
-{
- volatile unsigned long *p = (volatile unsigned long *) addr;
-
- if (G_verbosity_level > 1)
- printf ("write4: addr=%08x val=%08x -> *p=%08x\n",
- (unsigned int) addr, (unsigned int) val,
- (unsigned int) (((val & 0xFF000000) >> 24) |
- ((val & 0x000000FF) << 24) |
- ((val & 0x00FF0000) >> 8) |
- ((val & 0x0000FF00) << 8)));
-
- *p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
- ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
- asm ("eieio");
-}
-
-unsigned long read4 (unsigned long addr)
-{
- unsigned long val;
- volatile unsigned long *p = (volatile unsigned long *) addr;
-
- if (G_verbosity_level > 1)
- printf ("read4: addr=%08x", (unsigned int) addr);
-
- val = *p;
- val = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
- ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
- asm ("eieio");
-
- if (G_verbosity_level > 1)
- printf ("*p=%04x -> val=%04x\n",
- (unsigned int) (((val & 0xFF000000) >> 24) |
- ((val & 0x000000FF) << 24) |
- ((val & 0x00FF0000) >> 8) |
- ((val & 0x0000FF00) << 8)),
- (unsigned int) val);
- return val;
-}
-
-void write4be (unsigned long addr, unsigned long val)
-{
- volatile unsigned long *p = (volatile unsigned long *) addr;
-
- if (G_verbosity_level > 1)
- printf ("write4: addr=%08x val=%08x\n", (unsigned int) addr,
- (unsigned int) val);
- *p = val;
- asm ("eieio");
-}
-
-/** One byte configuration write on PSII.
- * Currently fixes destination PCI bus to PCI2, onboard
- * pci.
- * @param hose PCI Host controller information. Ignored.
- * @param dev Encoded PCI device/Bus and Function value.
- * @param reg PCI Configuration register number.
- * @param val Address of location for received byte.
- * @return Always Zero.
- */
-static int psII_read_config_byte (struct pci_controller *hose,
- pci_dev_t dev, int reg, u8 * val)
-{
- write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
- (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
-
- *val = read1 (PSII_CONFIG_DATA + (reg & 0x03));
- return (0);
-}
-
-/** One byte configuration write on PSII.
- * Currently fixes destination bus to PCI2, onboard
- * pci.
- * @param hose PCI Host controller information. Ignored.
- * @param dev Encoded PCI device/Bus and Function value.
- * @param reg PCI Configuration register number.
- * @param val Output byte.
- * @return Always Zero.
- */
-static int psII_write_config_byte (struct pci_controller *hose,
- pci_dev_t dev, int reg, u8 val)
-{
- write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
- (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
-
- write1 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned char) val);
-
- return (0);
-}
-
-/** One word (16 bit) configuration read on PSII.
- * Currently fixes destination PCI bus to PCI2, onboard
- * pci.
- * @param hose PCI Host controller information. Ignored.
- * @param dev Encoded PCI device/Bus and Function value.
- * @param reg PCI Configuration register number.
- * @param val Address of location for received word.
- * @return Always Zero.
- */
-static int psII_read_config_word (struct pci_controller *hose,
- pci_dev_t dev, int reg, u16 * val)
-{
- write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
- (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
-
- *val = read2 (PSII_CONFIG_DATA + (reg & 0x03));
- return (0);
-}
-
-/** One word (16 bit) configuration write on PSII.
- * Currently fixes destination bus to PCI2, onboard
- * pci.
- * @param hose PCI Host controller information. Ignored.
- * @param dev Encoded PCI device/Bus and Function value.
- * @param reg PCI Configuration register number.
- * @param val Output word.
- * @return Always Zero.
- */
-static int psII_write_config_word (struct pci_controller *hose,
- pci_dev_t dev, int reg, u16 val)
-{
- write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
- (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
-
- write2 (PSII_CONFIG_DATA + (reg & 0x03), (unsigned short) val);
-
- return (0);
-}
-
-/** One DWord (32 bit) configuration read on PSII.
- * Currently fixes destination PCI bus to PCI2, onboard
- * pci.
- * @param hose PCI Host controller information. Ignored.
- * @param dev Encoded PCI device/Bus and Function value.
- * @param reg PCI Configuration register number.
- * @param val Address of location for received byte.
- * @return Always Zero.
- */
-static int psII_read_config_dword (struct pci_controller *hose,
- pci_dev_t dev, int reg, u32 * val)
-{
- write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
- (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
-
- *val = read4 (PSII_CONFIG_DATA);
- return (0);
-}
-
-/** One DWord (32 bit) configuration write on PSII.
- * Currently fixes destination bus to PCI2, onboard
- * pci.
- * @param hose PCI Host controller information. Ignored.
- * @param dev Encoded PCI device/Bus and Function value.
- * @param reg PCI Configuration register number.
- * @param val Output Dword.
- * @return Always Zero.
- */
-static int psII_write_config_dword (struct pci_controller *hose,
- pci_dev_t dev, int reg, u32 val)
-{
- write4be (PSII_CONFIG_ADDR, PSII_CONFIG_DEST_PCI2 | /* Operate on PCI2 bus interface . */
- (PCI_BUS (dev) << 16) | (PCI_DEV (dev) << 11) | (PCI_FUNC (dev) << 8) | ((reg & 0xFF) & ~3)); /* Configuation cycle type 0 */
-
- write4 (PSII_CONFIG_DATA, (unsigned long) val);
-
- return (0);
-}
-
-static struct pci_config_table ap1000_config_table[] = {
-#ifdef CONFIG_AP1000
- {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
- PCI_BUS (CONFIG_SYS_ETH_DEV_FN), PCI_DEV (CONFIG_SYS_ETH_DEV_FN),
- PCI_FUNC (CONFIG_SYS_ETH_DEV_FN),
- pci_cfgfunc_config_device,
- {CONFIG_SYS_ETH_IOBASE, CONFIG_SYS_ETH_MEMBASE,
- PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
-#endif
- {}
-};
-
-static struct pci_controller psII_hose = {
- config_table:ap1000_config_table,
-};
-
-void pci_init_board (void)
-{
- struct pci_controller *hose = &psII_hose;
-
- /*
- * Register the hose
- */
- hose->first_busno = 0;
- hose->last_busno = 0xff;
-
- /* System memory space */
- pci_set_region (hose->regions + 0,
- AP1000_SYS_MEM_START, AP1000_SYS_MEM_START,
- AP1000_SYS_MEM_SIZE,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- /* PCI Memory space */
- pci_set_region (hose->regions + 1,
- PSII_PCI_MEM_BASE, PSII_PCI_MEM_BASE,
- PSII_PCI_MEM_SIZE, PCI_REGION_MEM);
-
- /* No IO Memory space - for now */
-
- pci_set_ops (hose,
- psII_read_config_byte,
- psII_read_config_word,
- psII_read_config_dword,
- psII_write_config_byte,
- psII_write_config_word, psII_write_config_dword);
-
- hose->region_count = 2;
-
- pci_register_hose (hose);
-
- hose->last_busno = pci_hose_scan (hose);
-}
+++ /dev/null
-/**
- * @file powerspan.c Source file for PowerSpan II code.
- */
-
-/*
- * (C) Copyright 2005
- * AMIRIX Systems Inc.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/processor.h>
-#include "powerspan.h"
-#define tolower(x) x
-#include "ap1000.h"
-
-#ifdef INCLUDE_PCI
-
-/** Write one byte with byte swapping.
- * @param addr [IN] the address to write to
- * @param val [IN] the value to write
- */
-void write1 (unsigned long addr, unsigned char val)
-{
- volatile unsigned char *p = (volatile unsigned char *) addr;
-
-#ifdef VERBOSITY
- if (gVerbosityLevel > 1) {
- printf ("write1: addr=%08x val=%02x\n", addr, val);
- }
-#endif
- *p = val;
- PSII_SYNC ();
-}
-
-/** Read one byte with byte swapping.
- * @param addr [IN] the address to read from
- * @return the value at addr
- */
-unsigned char read1 (unsigned long addr)
-{
- unsigned char val;
- volatile unsigned char *p = (volatile unsigned char *) addr;
-
- val = *p;
- PSII_SYNC ();
-#ifdef VERBOSITY
- if (gVerbosityLevel > 1) {
- printf ("read1: addr=%08x val=%02x\n", addr, val);
- }
-#endif
- return val;
-}
-
-/** Write one 2-byte word with byte swapping.
- * @param addr [IN] the address to write to
- * @param val [IN] the value to write
- */
-void write2 (unsigned long addr, unsigned short val)
-{
- volatile unsigned short *p = (volatile unsigned short *) addr;
-
-#ifdef VERBOSITY
- if (gVerbosityLevel > 1) {
- printf ("write2: addr=%08x val=%04x -> *p=%04x\n", addr, val,
- ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8));
- }
-#endif
- *p = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
- PSII_SYNC ();
-}
-
-/** Read one 2-byte word with byte swapping.
- * @param addr [IN] the address to read from
- * @return the value at addr
- */
-unsigned short read2 (unsigned long addr)
-{
- unsigned short val;
- volatile unsigned short *p = (volatile unsigned short *) addr;
-
- val = *p;
- val = ((val & 0xFF00) >> 8) | ((val & 0x00FF) << 8);
- PSII_SYNC ();
-#ifdef VERBOSITY
- if (gVerbosityLevel > 1) {
- printf ("read2: addr=%08x *p=%04x -> val=%04x\n", addr, *p,
- val);
- }
-#endif
- return val;
-}
-
-/** Write one 4-byte word with byte swapping.
- * @param addr [IN] the address to write to
- * @param val [IN] the value to write
- */
-void write4 (unsigned long addr, unsigned long val)
-{
- volatile unsigned long *p = (volatile unsigned long *) addr;
-
-#ifdef VERBOSITY
- if (gVerbosityLevel > 1) {
- printf ("write4: addr=%08x val=%08x -> *p=%08x\n", addr, val,
- ((val & 0xFF000000) >> 24) |
- ((val & 0x000000FF) << 24) |
- ((val & 0x00FF0000) >> 8) |
- ((val & 0x0000FF00) << 8));
- }
-#endif
- *p = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
- ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
- PSII_SYNC ();
-}
-
-/** Read one 4-byte word with byte swapping.
- * @param addr [IN] the address to read from
- * @return the value at addr
- */
-unsigned long read4 (unsigned long addr)
-{
- unsigned long val;
- volatile unsigned long *p = (volatile unsigned long *) addr;
-
- val = *p;
- val = ((val & 0xFF000000) >> 24) | ((val & 0x000000FF) << 24) |
- ((val & 0x00FF0000) >> 8) | ((val & 0x0000FF00) << 8);
- PSII_SYNC ();
-#ifdef VERBOSITY
- if (gVerbosityLevel > 1) {
- printf ("read4: addr=%08x *p=%08x -> val=%08x\n", addr, *p,
- val);
- }
-#endif
- return val;
-}
-
-int PCIReadConfig (int bus, int dev, int fn, int reg, int width,
- unsigned long *val)
-{
- unsigned int conAdrVal;
- unsigned int conDataReg = REG_CONFIG_DATA;
- unsigned int status;
- int ret_val = 0;
-
-
- /* DEST bit hardcoded to 1: local pci is PCI-2 */
- /* TYPE bit is hardcoded to 1: all config cycles are local */
- conAdrVal = (1 << 24)
- | ((bus & 0xFF) << 16)
- | ((dev & 0xFF) << 11)
- | ((fn & 0x07) << 8)
- | (reg & 0xFC);
-
- /* clear any pending master aborts */
- write4 (REG_P1_CSR, CLEAR_MASTER_ABORT);
-
- /* Load the conAdrVal value first, then read from pb_conf_data */
- write4 (REG_CONFIG_ADDRESS, conAdrVal);
- PSII_SYNC ();
-
-
- /* Note: documentation does not match the pspan library code */
- /* Note: *pData comes back as -1 if device is not present */
- switch (width) {
- case 4:
- *(unsigned int *) val = read4 (conDataReg);
- break;
- case 2:
- *(unsigned short *) val = read2 (conDataReg);
- break;
- case 1:
- *(unsigned char *) val = read1 (conDataReg);
- break;
- default:
- ret_val = ILLEGAL_REG_OFFSET;
- break;
- }
- PSII_SYNC ();
-
- /* clear any pending master aborts */
- status = read4 (REG_P1_CSR);
- if (status & CLEAR_MASTER_ABORT) {
- ret_val = NO_DEVICE_FOUND;
- write4 (REG_P1_CSR, CLEAR_MASTER_ABORT);
- }
-
- return ret_val;
-}
-
-
-int PCIWriteConfig (int bus, int dev, int fn, int reg, int width,
- unsigned long val)
-{
- unsigned int conAdrVal;
- unsigned int conDataReg = REG_CONFIG_DATA;
- unsigned int status;
- int ret_val = 0;
-
-
- /* DEST bit hardcoded to 1: local pci is PCI-2 */
- /* TYPE bit is hardcoded to 1: all config cycles are local */
- conAdrVal = (1 << 24)
- | ((bus & 0xFF) << 16)
- | ((dev & 0xFF) << 11)
- | ((fn & 0x07) << 8)
- | (reg & 0xFC);
-
- /* clear any pending master aborts */
- write4 (REG_P1_CSR, CLEAR_MASTER_ABORT);
-
- /* Load the conAdrVal value first, then read from pb_conf_data */
- write4 (REG_CONFIG_ADDRESS, conAdrVal);
- PSII_SYNC ();
-
-
- /* Note: documentation does not match the pspan library code */
- /* Note: *pData comes back as -1 if device is not present */
- switch (width) {
- case 4:
- write4 (conDataReg, val);
- break;
- case 2:
- write2 (conDataReg, val);
- break;
- case 1:
- write1 (conDataReg, val);
- break;
- default:
- ret_val = ILLEGAL_REG_OFFSET;
- break;
- }
- PSII_SYNC ();
-
- /* clear any pending master aborts */
- status = read4 (REG_P1_CSR);
- if (status & CLEAR_MASTER_ABORT) {
- ret_val = NO_DEVICE_FOUND;
- write4 (REG_P1_CSR, CLEAR_MASTER_ABORT);
- }
-
- return ret_val;
-}
-
-
-int pci_read_config_byte (int bus, int dev, int fn, int reg,
- unsigned char *val)
-{
- unsigned long read_val;
- int ret_val;
-
- ret_val = PCIReadConfig (bus, dev, fn, reg, 1, &read_val);
- *val = read_val & 0xFF;
-
- return ret_val;
-}
-
-int pci_write_config_byte (int bus, int dev, int fn, int reg,
- unsigned char val)
-{
- return PCIWriteConfig (bus, dev, fn, reg, 1, val);
-}
-
-int pci_read_config_word (int bus, int dev, int fn, int reg,
- unsigned short *val)
-{
- unsigned long read_val;
- int ret_val;
-
- ret_val = PCIReadConfig (bus, dev, fn, reg, 2, &read_val);
- *val = read_val & 0xFFFF;
-
- return ret_val;
-}
-
-int pci_write_config_word (int bus, int dev, int fn, int reg,
- unsigned short val)
-{
- return PCIWriteConfig (bus, dev, fn, reg, 2, val);
-}
-
-int pci_read_config_dword (int bus, int dev, int fn, int reg,
- unsigned long *val)
-{
- return PCIReadConfig (bus, dev, fn, reg, 4, val);
-}
-
-int pci_write_config_dword (int bus, int dev, int fn, int reg,
- unsigned long val)
-{
- return PCIWriteConfig (bus, dev, fn, reg, 4, val);
-}
-
-#endif /* INCLUDE_PCI */
-
-int I2CAccess (unsigned char theI2CAddress, unsigned char theDevCode,
- unsigned char theChipSel, unsigned char *theValue, int RWFlag)
-{
- int ret_val = 0;
- unsigned int reg_value;
-
- reg_value = PowerSpanRead (REG_I2C_CSR);
-
- if (reg_value & I2C_CSR_ACT) {
- printf ("Error: I2C busy\n");
- ret_val = I2C_BUSY;
- } else {
- reg_value = ((theI2CAddress & 0xFF) << 24)
- | ((theDevCode & 0x0F) << 12)
- | ((theChipSel & 0x07) << 9)
- | I2C_CSR_ERR;
- if (RWFlag == I2C_WRITE) {
- reg_value |= I2C_CSR_RW | ((*theValue & 0xFF) << 16);
- }
-
- PowerSpanWrite (REG_I2C_CSR, reg_value);
- udelay (1);
-
- do {
- reg_value = PowerSpanRead (REG_I2C_CSR);
-
- if ((reg_value & I2C_CSR_ACT) == 0) {
- if (reg_value & I2C_CSR_ERR) {
- ret_val = I2C_ERR;
- } else {
- *theValue =
- (reg_value & I2C_CSR_DATA) >>
- 16;
- }
- }
- } while (reg_value & I2C_CSR_ACT);
- }
-
- return ret_val;
-}
-
-int EEPROMRead (unsigned char theI2CAddress, unsigned char *theValue)
-{
- return I2CAccess (theI2CAddress, I2C_EEPROM_DEV, I2C_EEPROM_CHIP_SEL,
- theValue, I2C_READ);
-}
-
-int EEPROMWrite (unsigned char theI2CAddress, unsigned char theValue)
-{
- return I2CAccess (theI2CAddress, I2C_EEPROM_DEV, I2C_EEPROM_CHIP_SEL,
- &theValue, I2C_WRITE);
-}
-
-int do_eeprom (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- char cmd;
- int ret_val = 0;
- unsigned int address = 0;
- unsigned char value = 1;
- unsigned char read_value;
- int ii;
- int error = 0;
- unsigned char *mem_ptr;
- unsigned char default_eeprom[] = EEPROM_DEFAULT;
-
- if (argc < 2) {
- goto usage;
- }
-
- cmd = argv[1][0];
- if (argc > 2) {
- address = simple_strtoul (argv[2], NULL, 16);
- if (argc > 3) {
- value = simple_strtoul (argv[3], NULL, 16) & 0xFF;
- }
- }
-
- switch (cmd) {
- case 'r':
- if (address > 256) {
- printf ("Illegal Address\n");
- goto usage;
- }
- printf ("@0x%x: ", address);
- for (ii = 0; ii < value; ii++) {
- if (EEPROMRead (address + ii, &read_value) !=
- 0) {
- printf ("Read Error\n");
- } else {
- printf ("0x%02x ", read_value);
- }
-
- if (((ii + 1) % 16) == 0) {
- printf ("\n");
- }
- }
- printf ("\n");
- break;
- case 'w':
- if (address > 256) {
- printf ("Illegal Address\n");
- goto usage;
- }
- if (argc < 4) {
- goto usage;
- }
- if (EEPROMWrite (address, value) != 0) {
- printf ("Write Error\n");
- }
- break;
- case 'g':
- if (argc != 3) {
- goto usage;
- }
- mem_ptr = (unsigned char *) address;
- for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0));
- ii++) {
- if (EEPROMRead (ii, &read_value) != 0) {
- printf ("Read Error\n");
- error = 1;
- } else {
- *mem_ptr = read_value;
- mem_ptr++;
- }
- }
- break;
- case 'p':
- if (argc != 3) {
- goto usage;
- }
- mem_ptr = (unsigned char *) address;
- for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0));
- ii++) {
- if (EEPROMWrite (ii, *mem_ptr) != 0) {
- printf ("Write Error\n");
- error = 1;
- }
-
- mem_ptr++;
- }
- break;
- case 'd':
- if (argc != 2) {
- goto usage;
- }
- for (ii = 0; ((ii < EEPROM_LENGTH) && (error == 0));
- ii++) {
- if (EEPROMWrite (ii, default_eeprom[ii]) != 0) {
- printf ("Write Error\n");
- error = 1;
- }
- }
- break;
- default:
- goto usage;
- }
-
- goto done;
- usage:
- printf ("Usage:\n%s\n", cmdtp->help);
-
- done:
- return ret_val;
-
-}
-
-U_BOOT_CMD (eeprom, 4, 0, do_eeprom,
- "read/write/copy to/from the PowerSpan II eeprom",
- "eeprom r OFF [NUM]\n"
- " - read NUM words starting at OFF\n"
- "eeprom w OFF VAL\n"
- " - write word VAL at offset OFF\n"
- "eeprom g ADD\n"
- " - store contents of eeprom at address ADD\n"
- "eeprom p ADD\n"
- " - put data stored at address ADD into the eeprom\n"
- "eeprom d\n" " - return eeprom to default contents");
-
-unsigned int PowerSpanRead (unsigned int theOffset)
-{
- volatile unsigned int *ptr =
- (volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
- unsigned int ret_val;
-
-#ifdef VERBOSITY
- if (gVerbosityLevel > 1) {
- printf ("PowerSpanRead: offset=%08x ", theOffset);
- }
-#endif
- ret_val = *ptr;
- PSII_SYNC ();
-
-#ifdef VERBOSITY
- if (gVerbosityLevel > 1) {
- printf ("value=%08x\n", ret_val);
- }
-#endif
-
- return ret_val;
-}
-
-void PowerSpanWrite (unsigned int theOffset, unsigned int theValue)
-{
- volatile unsigned int *ptr =
- (volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
-#ifdef VERBOSITY
- if (gVerbosityLevel > 1) {
- printf ("PowerSpanWrite: offset=%08x val=%02x\n", theOffset,
- theValue);
- }
-#endif
- *ptr = theValue;
- PSII_SYNC ();
-}
-
-/**
- * Sets the indicated bits in the indicated register.
- * @param theOffset [IN] the register to access.
- * @param theMask [IN] bits set in theMask will be set in the register.
- */
-void PowerSpanSetBits (unsigned int theOffset, unsigned int theMask)
-{
- volatile unsigned int *ptr =
- (volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
- unsigned int register_value;
-
-#ifdef VERBOSITY
- if (gVerbosityLevel > 1) {
- printf ("PowerSpanSetBits: offset=%08x mask=%02x\n",
- theOffset, theMask);
- }
-#endif
- register_value = *ptr;
- PSII_SYNC ();
-
- register_value |= theMask;
- *ptr = register_value;
- PSII_SYNC ();
-}
-
-/**
- * Clears the indicated bits in the indicated register.
- * @param theOffset [IN] the register to access.
- * @param theMask [IN] bits set in theMask will be cleared in the register.
- */
-void PowerSpanClearBits (unsigned int theOffset, unsigned int theMask)
-{
- volatile unsigned int *ptr =
- (volatile unsigned int *) (PSPAN_BASEADDR + theOffset);
- unsigned int register_value;
-
-#ifdef VERBOSITY
- if (gVerbosityLevel > 1) {
- printf ("PowerSpanClearBits: offset=%08x mask=%02x\n",
- theOffset, theMask);
- }
-#endif
- register_value = *ptr;
- PSII_SYNC ();
-
- register_value &= ~theMask;
- *ptr = register_value;
- PSII_SYNC ();
-}
-
-/**
- * Configures a slave image on the local bus, based on the parameters and some hardcoded system values.
- * Slave Images are images that cause the PowerSpan II to be a master on the PCI bus. Thus, they
- * are outgoing from the standpoint of the local bus.
- * @param theImageIndex [IN] the PowerSpan II image to set (assumed to be 0-7).
- * @param theBlockSize [IN] the block size of the image (as used by PowerSpan II: PB_SIx_CTL[BS]).
- * @param theMemIOFlag [IN] if PX_TGT_USE_MEM_IO, this image will have the MEM_IO bit set.
- * @param theEndianness [IN] the endian bits for the image (already shifted, use defines).
- * @param theLocalBaseAddr [IN] the Local address for the image (assumed to be valid with provided block size).
- * @param thePCIBaseAddr [IN] the PCI address for the image (assumed to be valid with provided block size).
- */
-int SetSlaveImage (int theImageIndex, unsigned int theBlockSize,
- int theMemIOFlag, int theEndianness,
- unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr)
-{
- unsigned int reg_offset = theImageIndex * PB_SLAVE_IMAGE_OFF;
- unsigned int reg_value = 0;
-
- /* Make sure that the Slave Image is disabled */
- PowerSpanClearBits ((REGS_PB_SLAVE_CSR + reg_offset),
- PB_SLAVE_CSR_IMG_EN);
-
- /* Setup the mask required for requested PB Slave Image configuration */
- reg_value = PB_SLAVE_CSR_TA_EN | theEndianness | (theBlockSize << 24);
- if (theMemIOFlag == PB_SLAVE_USE_MEM_IO) {
- reg_value |= PB_SLAVE_CSR_MEM_IO;
- }
-
- /* hardcoding the following:
- TA_EN = 1
- MD_EN = 0
- MODE = 0
- PRKEEP = 0
- RD_AMT = 0
- */
- PowerSpanWrite ((REGS_PB_SLAVE_CSR + reg_offset), reg_value);
-
- /* these values are not checked by software */
- PowerSpanWrite ((REGS_PB_SLAVE_BADDR + reg_offset), theLocalBaseAddr);
- PowerSpanWrite ((REGS_PB_SLAVE_TADDR + reg_offset), thePCIBaseAddr);
-
- /* Enable the Slave Image */
- PowerSpanSetBits ((REGS_PB_SLAVE_CSR + reg_offset),
- PB_SLAVE_CSR_IMG_EN);
-
- return 0;
-}
-
-/**
- * Configures a target image on the local bus, based on the parameters and some hardcoded system values.
- * Target Images are used when the PowerSpan II is acting as a target for an access. Thus, they
- * are incoming from the standpoint of the local bus.
- * In order to behave better on the host PCI bus, if thePCIBaseAddr is NULL (0x00000000), then the PCI
- * base address will not be updated; makes sense given that the hosts own memory should be mapped to
- * PCI address 0x00000000.
- * @param theImageIndex [IN] the PowerSpan II image to set.
- * @param theBlockSize [IN] the block size of the image (as used by PowerSpan II: Px_TIx_CTL[BS]).
- * @param theMemIOFlag [IN] if PX_TGT_USE_MEM_IO, this image will have the MEM_IO bit set.
- * @param theEndianness [IN] the endian bits for the image (already shifted, use defines).
- * @param theLocalBaseAddr [IN] the Local address for the image (assumed to be valid with provided block size).
- * @param thePCIBaseAddr [IN] the PCI address for the image (assumed to be valid with provided block size).
- */
-int SetTargetImage (int theImageIndex, unsigned int theBlockSize,
- int theMemIOFlag, int theEndianness,
- unsigned int theLocalBaseAddr,
- unsigned int thePCIBaseAddr)
-{
- unsigned int csr_reg_offset = theImageIndex * P1_TGT_IMAGE_OFF;
- unsigned int pci_reg_offset = theImageIndex * P1_BST_OFF;
- unsigned int reg_value = 0;
-
- /* Make sure that the Slave Image is disabled */
- PowerSpanClearBits ((REGS_P1_TGT_CSR + csr_reg_offset),
- PB_SLAVE_CSR_IMG_EN);
-
- /* Setup the mask required for requested PB Slave Image configuration */
- reg_value =
- PX_TGT_CSR_TA_EN | PX_TGT_CSR_BAR_EN | (theBlockSize << 24) |
- PX_TGT_CSR_RTT_READ | PX_TGT_CSR_WTT_WFLUSH | theEndianness;
- if (theMemIOFlag == PX_TGT_USE_MEM_IO) {
- reg_value |= PX_TGT_MEM_IO;
- }
-
- /* hardcoding the following:
- TA_EN = 1
- BAR_EN = 1
- MD_EN = 0
- MODE = 0
- DEST = 0
- RTT = 01010
- GBL = 0
- CI = 0
- WTT = 00010
- PRKEEP = 0
- MRA = 0
- RD_AMT = 0
- */
- PowerSpanWrite ((REGS_P1_TGT_CSR + csr_reg_offset), reg_value);
-
- PowerSpanWrite ((REGS_P1_TGT_TADDR + csr_reg_offset),
- theLocalBaseAddr);
-
- if (thePCIBaseAddr != (unsigned int) NULL) {
- PowerSpanWrite ((REGS_P1_BST + pci_reg_offset),
- thePCIBaseAddr);
- }
-
- /* Enable the Slave Image */
- PowerSpanSetBits ((REGS_P1_TGT_CSR + csr_reg_offset),
- PB_SLAVE_CSR_IMG_EN);
-
- return 0;
-}
-
-int do_bridge (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- char cmd;
- int ret_val = 1;
- unsigned int image_index;
- unsigned int block_size;
- unsigned int mem_io;
- unsigned int local_addr;
- unsigned int pci_addr;
- int endianness;
-
- if (argc != 8) {
- goto usage;
- }
-
- cmd = argv[1][0];
- image_index = simple_strtoul (argv[2], NULL, 16);
- block_size = simple_strtoul (argv[3], NULL, 16);
- mem_io = simple_strtoul (argv[4], NULL, 16);
- endianness = argv[5][0];
- local_addr = simple_strtoul (argv[6], NULL, 16);
- pci_addr = simple_strtoul (argv[7], NULL, 16);
-
-
- switch (cmd) {
- case 'i':
- if (tolower (endianness) == 'b') {
- endianness = PX_TGT_CSR_BIG_END;
- } else if (tolower (endianness) == 'l') {
- endianness = PX_TGT_CSR_TRUE_LEND;
- } else {
- goto usage;
- }
- SetTargetImage (image_index, block_size, mem_io,
- endianness, local_addr, pci_addr);
- break;
- case 'o':
- if (tolower (endianness) == 'b') {
- endianness = PB_SLAVE_CSR_BIG_END;
- } else if (tolower (endianness) == 'l') {
- endianness = PB_SLAVE_CSR_TRUE_LEND;
- } else {
- goto usage;
- }
- SetSlaveImage (image_index, block_size, mem_io,
- endianness, local_addr, pci_addr);
- break;
- default:
- goto usage;
- }
-
- goto done;
-usage:
- printf ("Usage:\n%s\n", cmdtp->help);
-
-done:
- return ret_val;
-}
+++ /dev/null
-/**
- * @file powerspan.h Header file for PowerSpan II code.
- */
-
-/*
- * (C) Copyright 2005
- * AMIRIX Systems Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef POWERSPAN_H
-#define POWERSPAN_H
-
-#define CLEAR_MASTER_ABORT 0xdeadbeef
-#define NO_DEVICE_FOUND -1
-#define ILLEGAL_REG_OFFSET -2
-#define I2C_BUSY -3
-#define I2C_ERR -4
-
-#define REG_P1_CSR 0x004
-#define REGS_P1_BST 0x018
-#define REG_P1_ERR_CSR 0x150
-#define REG_P1_MISC_CSR 0x160
-#define REGS_P1_TGT_CSR 0x100
-#define REGS_P1_TGT_TADDR 0x104
-#define REGS_PB_SLAVE_CSR 0x200
-#define REGS_PB_SLAVE_TADDR 0x204
-#define REGS_PB_SLAVE_BADDR 0x208
-#define REG_CONFIG_ADDRESS 0x290
-#define REG_CONFIG_DATA 0x294
-#define REG_PB_ERR_CSR 0x2B0
-#define REG_PB_MISC_CSR 0x2C0
-#define REG_MISC_CSR 0x400
-#define REG_I2C_CSR 0x408
-#define REG_RESET_CSR 0x40C
-#define REG_ISR0 0x410
-#define REG_ISR1 0x414
-#define REG_IER0 0x418
-#define REG_MBOX_MAP 0x420
-#define REG_HW_MAP 0x42C
-#define REG_IDR 0x444
-
-#define CSR_MEMORY_SPACE_ENABLE 0x00000002
-#define CSR_PCI_MASTER_ENABLE 0x00000004
-
-#define P1_BST_OFF 0x04
-
-#define PX_ERR_ERR_STATUS 0x01000000
-
-#define PX_MISC_CSR_MAX_RETRY_MASK 0x00000F00
-#define PX_MISC_CSR_MAX_RETRY 0x00000F00
-#define PX_MISC_REG_BAR_ENABLE 0x00008000
-#define PB_MISC_TEA_ENABLE 0x00000010
-#define PB_MISC_MAC_TEA 0x00000040
-
-#define P1_TGT_IMAGE_OFF 0x010
-#define PX_TGT_CSR_IMG_EN 0x80000000
-#define PX_TGT_CSR_TA_EN 0x40000000
-#define PX_TGT_CSR_BAR_EN 0x20000000
-#define PX_TGT_CSR_MD_EN 0x10000000
-#define PX_TGT_CSR_MODE 0x00800000
-#define PX_TGT_CSR_DEST 0x00400000
-#define PX_TGT_CSR_MEM_IO 0x00200000
-#define PX_TGT_CSR_GBL 0x00080000
-#define PX_TGT_CSR_CL 0x00040000
-#define PX_TGT_CSR_PRKEEP 0x00000080
-
-#define PX_TGT_CSR_BS_MASK 0x0F000000
-#define PX_TGT_MEM_IO 0x00200000
-#define PX_TGT_CSR_RTT_MASK 0x001F0000
-#define PX_TGT_CSR_RTT_READ 0x000A0000
-#define PX_TGT_CSR_WTT_MASK 0x00001F00
-#define PX_TGT_CSR_WTT_WFLUSH 0x00000200
-#define PX_TGT_CSR_END_MASK 0x00000060
-#define PX_TGT_CSR_BIG_END 0x00000040
-#define PX_TGT_CSR_TRUE_LEND 0x00000060
-#define PX_TGT_CSR_RDAMT_MASK 0x00000007
-
-#define PX_TGT_CSR_BS_64MB 0xa
-#define PX_TGT_CSR_BS_16MB 0x8
-
-#define PX_TGT_USE_MEM_IO 1
-#define PX_TGT_NOT_MEM_IO 0
-
-#define PB_SLAVE_IMAGE_OFF 0x010
-#define PB_SLAVE_CSR_IMG_EN 0x80000000
-#define PB_SLAVE_CSR_TA_EN 0x40000000
-#define PB_SLAVE_CSR_MD_EN 0x20000000
-#define PB_SLAVE_CSR_MODE 0x00800000
-#define PB_SLAVE_CSR_DEST 0x00400000
-#define PB_SLAVE_CSR_MEM_IO 0x00200000
-#define PB_SLAVE_CSR_PRKEEP 0x00000080
-
-#define PB_SLAVE_CSR_BS_MASK 0x1F000000
-#define PB_SLAVE_CSR_END_MASK 0x00000060
-#define PB_SLAVE_CSR_BIG_END 0x00000040
-#define PB_SLAVE_CSR_TRUE_LEND 0x00000060
-#define PB_SLAVE_CSR_RDAMT_MASK 0x00000007
-
-#define PB_SLAVE_USE_MEM_IO 1
-#define PB_SLAVE_NOT_MEM_IO 0
-
-
-#define MISC_CSR_PCI1_LOCK 0x00000080
-
-#define I2C_CSR_ADDR 0xFF000000 /* Specifies I2C Device Address to be Accessed */
-#define I2C_CSR_DATA 0x00FF0000 /* Specifies the Required Data for a Write */
-#define I2C_CSR_DEV_CODE 0x0000F000 /* Device Select. I2C 4-bit Device Code */
-#define I2C_CSR_CS 0x00000E00 /* Chip Select */
-#define I2C_CSR_RW 0x00000100 /* Read/Write */
-#define I2C_CSR_ACT 0x00000080 /* I2C Interface Active */
-#define I2C_CSR_ERR 0x00000040 /* Error */
-
-#define I2C_EEPROM_DEV 0xa
-#define I2C_EEPROM_CHIP_SEL 0
-
-#define I2C_READ 0
-#define I2C_WRITE 1
-
-#define RESET_CSR_EEPROM_LOAD 0x00000010
-
-#define ISR_CLEAR_ALL 0xFFFFFFFF
-
-#define IER0_DMA_INTS_EN 0x0F000000
-#define IER0_PCI_1_EN 0x00400000
-#define IER0_HW_INTS_EN 0x003F0000
-#define IER0_MB_INTS_EN 0x000000FF
-#define IER0_DEFAULT (IER0_DMA_INTS_EN | IER0_PCI_1_EN | IER0_HW_INTS_EN | IER0_MB_INTS_EN)
-
-#define MBOX_MAP_TO_INT4 0xCCCCCCCC
-
-#define HW_MAP_HW4_TO_INT4 0x000C0000
-
-#define IDR_PCI_A_OUT 0x40000000
-#define IDR_MBOX_OUT 0x10000000
-
-
-int pci_read_config_byte(int bus, int dev, int fn, int reg, unsigned char* val);
-int pci_write_config_byte(int bus, int dev, int fn, int reg, unsigned char val);
-int pci_read_config_word(int bus, int dev, int fn, int reg, unsigned short* val);
-int pci_write_config_word(int bus, int dev, int fn, int reg, unsigned short val);
-int pci_read_config_dword(int bus, int dev, int fn, int reg, unsigned long* val);
-int pci_write_config_dword(int bus, int dev, int fn, int reg, unsigned long val);
-
-unsigned int PowerSpanRead(unsigned int theOffset);
-void PowerSpanWrite(unsigned int theOffset, unsigned int theValue);
-
-int I2CAccess(unsigned char theI2CAddress, unsigned char theDevCode, unsigned char theChipSel, unsigned char* theValue, int RWFlag);
-
-int PCIWriteConfig(int bus, int dev, int fn, int reg, int width, unsigned long val);
-int PCIReadConfig(int bus, int dev, int fn, int reg, int width, unsigned long* val);
-
-int SetSlaveImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag, int theEndianness, unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr);
-int SetTargetImage(int theImageIndex, unsigned int theBlockSize, int theMemIOFlag, int theEndianness, unsigned int theLocalBaseAddr, unsigned int thePCIBaseAddr);
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Peter De Schrijver (p2@mind.be), Mind Linux Solutions, NV.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <asm/u-boot.h>
-#include <asm/processor.h>
-#include <command.h>
-#include <config.h>
-
-#include <ns16550.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-const NS16550_t COM_PORTS[] =
- { (NS16550_t) CONFIG_SYS_NS16550_COM1, (NS16550_t) CONFIG_SYS_NS16550_COM2 };
-
-#undef CONFIG_SYS_DUART_CHAN
-#define CONFIG_SYS_DUART_CHAN gComPort
-static int gComPort = 0;
-
-int serial_init (void)
-{
- int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
-
- (void) NS16550_init (COM_PORTS[0], clock_divisor);
- gComPort = 0;
-
- return 0;
-}
-
-void serial_putc (const char c)
-{
- if (c == '\n') {
- NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
- }
-
- NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
-}
-
-int serial_getc (void)
-{
- return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
-}
-
-int serial_tstc (void)
-{
- return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
-}
-
-void serial_setbrg (void)
-{
- int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
-
-#ifdef CONFIG_SYS_INIT_CHAN1
- NS16550_reinit (COM_PORTS[0], clock_divisor);
-#endif
-#ifdef CONFIG_SYS_INIT_CHAN2
- NS16550_reinit (COM_PORTS[1], clock_divisor);
-#endif
-}
-
-void serial_puts (const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
-#if defined(CONFIG_CMD_KGDB)
-void kgdb_serial_init (void)
-{
-}
-
-void putDebugChar (int c)
-{
- serial_putc (c);
-}
-
-void putDebugStr (const char *str)
-{
- serial_puts (str);
-}
-
-int getDebugChar (void)
-{
- return serial_getc ();
-}
-
-void kgdb_interruptible (int yes)
-{
- return;
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/powerpc/cpu/ppc4xx/start.o (.text)
- board/amirix/ap1000/init.o (.text)
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end__ = . ;
- PROVIDE (end = .);
-}
*/
OUTPUT_ARCH(m68k)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
+
SECTIONS
{
/* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
.text :
{
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- arch/m68k/cpu/mcf532x/start.o (.text)
- arch/m68k/lib/traps.o (.text)
- arch/m68k/lib/interrupts.o (.text)
- common/dlmalloc.o (.text)
- lib/zlib.o (.text)
+ arch/m68k/cpu/mcf532x/start.o (.text*)
. = DEFINED(env_offset) ? env_offset : .;
- common/env_embedded.o (.text)
+ common/env_embedded.o (.text*)
- *(.text)
-/* *(.fixup)*/
- *(.got1)
+ *(.text*)
}
_etext = .;
PROVIDE (etext = .);
{
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
}
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
.reloc :
{
__got_start = .;
- *(.got)
+ KEEP(*(.got))
__got_end = .;
_GOT2_TABLE_ = .;
- *(.got2)
+ KEEP(*(.got2))
_FIXUP_TABLE_ = .;
- *(.fixup)
+ KEEP(*(.fixup))
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
+ *(.data*)
+ *(.sdata*)
}
_edata = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
.bss :
{
_sbss = .;
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
+ *(.sbss*)
+ *(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
#include <ns16550.h>
#include <asm/io.h>
#include <asm/gpio.h>
-#include <asm/arch/board.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/uart.h>
-#include <asm/arch/mmc.h>
-
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/board.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/mmc.h>
+#include <asm/arch-tegra/sys_proto.h>
+#include <asm/arch-tegra/uart.h>
#ifdef CONFIG_TEGRA_MMC
#include <mmc.h>
#endif
-/*
- * Routine: gpio_config_uart
- * Description: Does nothing on Tamonten - no conflict w/SPI.
- */
-void gpio_config_uart(void)
-{
-}
#ifdef CONFIG_BOARD_EARLY_INIT_F
void gpio_early_init(void)
/ {
model = "Avionic Design Medcom-Wide";
- compatible = "avionic-design,medcom", "nvidia,tegra20";
+ compatible = "ad,medcom-wide", "nvidia,tegra20";
aliases {
usb0 = "/usb@c5008000";
/ {
model = "Avionic Design Plutux";
- compatible = "avionic-design,plutux", "nvidia,tegra20";
+ compatible = "ad,plutux", "nvidia,tegra20";
aliases {
usb0 = "/usb@c5008000";
/ {
model = "Avionic Design Tamonten Evaluation Carrier";
- compatible = "avionic-design,tec", "nvidia,tegra20";
+ compatible = "ad,tec", "nvidia,tegra20";
aliases {
usb0 = "/usb@c5008000";
return 0;
}
-struct serial_device *default_serial_console(void)
-{
- return &serial_stuart_device;
-}
-
int dram_init(void)
{
pxa2xx_dram_init();
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# (C) Copyright 2002
-# James F. Dougherty, Broadcom Corporation, jfd@broadcom.com
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS = $(BOARD).o flash.o ns16550.o serial.o m48t59y.o
-
-SOBJS = early_init.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-Broadcom 95xx BMW CPCI Platform
-
-Overview
-=========
-BMW is an MPC8245 system controller featuring:
-* 3U CPCI Form Factor
-* BCM5703 Gigabit Ethernet
-* M48T59Y NVRAM
-* 16MB DOC
-* DIP Socket for Socketed DOC up to 1GB
-* 64MB SDRAM
-* LCD Display
-* Configurable Jumper options for 66,85, and 100Mhz memory bus
-
-
-BMW System Address Map
-======================
-BMW uses the MPC8245 CHRP Address MAP B found in the MPC8245 Users Manual
-(P.121, Section 3.1 Address Maps, Address Map B). Other I/O devices found
-onboard the processor module are listed briefly below:
-
-0x00000000 - 0x40000000 - 64MB SDRAM SIMM
- (Unregistered PC-100 SDRAM DIMM Module)
-
-0xFF000000 - 0xFF001FFF - M-Systems DiskOnChip (TM) 2000
- TSOP 16MB (MD2211-D16-V3)
-
-0x70000000 - 0x70001FFF - M-Systems DiskOnChip (TM) 2000
- DIP32 (Socketed 16MB - 1GB ) *
- NOTE: this is not populated on all systems.
-
-0x7c000000 - 0x7c000000 - Reset Register
- (Write 0 to reset)
-
-0x7c000001 - 0x7c000001 - System LED
- (Clear Bit 7 to turn on, set to shut off)
-
-0x7c000002 - 0x7c000002 - M48T59 Watchdog IRQ3
- (Clear bit 7 to reset, set to assert IRQ3)
-
-0x7c000003 - 0x7c000003 - M48T59 Write-Protect Register
- (Clear bit 7 to make R/W, set to make R/O)
-
-0x7c002000 - 0x7c002003 - Infineon OSRAM DLR2416 4 Character
- 5x7 Dot Matrix Alphanumeric Display
- (Each byte sets the appropriate character)
-
-0x7c004000 - 0x7c005FF0 - SGS-THOMSON M48T59Y 8K NVRAM/RTC
- NVRAM Memory Region
-
-0x7c005FF0 - 0x7c005FFF - SGS-THOMSON M48T59Y 8K NVRAM/RTC
- Realtime Clock Registers
-
-0xFFF00000 - 0xFFF80000 - 512K PLCC32 BootRom
- (AMD AM29F040, ST 29W040B)
-
-0xFFF00100 - System Reset Vector
-
-
-IO/MMU (BAT) Configuration
-======================
-The following Block-Address-Translation (BAT) configuration
-is recommended to access all I/O devices.
-
-#define CONFIG_SYS_IBAT0L (0x00000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (0x00000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-
-Interrupt Mappings
-======================
-BMW uses MPC8245 discrete mode interrupts. With the following
-hardwired mappings:
-
-BCM5701 10/100/1000 Ethernet IRQ1
-CompactPCI Interrupt A IRQ2
-RTC/Watchdog Interrupt IRQ3
-Internal NS16552 UART IRQ4
-
-
-Jumper Settings
-======================
-
-BMW has a jumper (JP600) for selecting 66, 85, or 100Mhz memory bus.
-A jumper (X) is a 0 bit.
-
-Hence 66= 10110
- 85= 11000
- 100= 10000
-
-Jumper Settings for various Speeds
-=======================
-J1 J2 J3 J4 J5
- X X 66Mhz
-=======================
-J1 J2 J3 J4 J5
- X X X 85Mhz
-=======================
-J1 J2 J3 J4 J5
- X X X X 100Mhz
-=======================
-
-Obviously, 100Mhz memory bus is recommended for optimum performance.
-
-
-U-Boot
-===============
-Broadcom BMW board is supported under config_BWM option.
-Supported features:
-
-- NVRAM setenv/getenv (used by Linux Kernel for configuration variables)
-- BCM570x TFTP file transfer support
-- LCD Display Support
-- DOC Support - (underway)
-
-
-U-Boot 1.2.0 (Aug 6 2002 - 17:44:48)
-
-CPU: MPC8245 Revision 16.20 at 264 MHz: 16 kB I-Cache 16 kB D-Cache
-Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)
-Built: Aug 6 2002 at 17:44:37
-Local Bus at 66 MHz
-DRAM: 64 MB
-FLASH: 4095 MB
-In: serial
-Out: serial
-Err: serial
-DOC: No DiskOnChip found
-Hit any key to stop autoboot: 0
-=>printenv
-bootdelay=5
-baudrate=9600
-clocks_in_mhz=1
-hostname=switch-2
-bootcmd=tftp 100000 vmlinux.img;bootm
-gateway=10.16.64.1
-ethaddr=00:00:10:18:10:10
-nfsroot=172.16.40.111:/boot/root-fs
-filesize=5ec8c
-netmask=255.255.240.0
-ipaddr=172.16.40.114
-serverip=172.16.40.111
-root=/dev/nfs
-stdin=serial
-stdout=serial
-stderr=serial
-
-Environment size: 315/8172 bytes
-=>boot
-
-
-DevTools
-========
-ELDK
- DENX Embedded Linux Development Kit
-
-ROM Emulator
- Grammar Engine PROMICE P1160-90-AI21E (2MBx8bit, 90ns access time)
- Grammar Engine PL32E 32Pin PLCC Emulation cables
- Grammar Engine 3VA8CON (3Volt adapter with Short cables)
- Grammar Engine FPNET PromICE Ethernet Adapters
-
-ICE
- WRS/EST VisionICE-II (PPC8240)
-
-
-=>reset
-
-
-U-Boot 1.2.0 (Aug 6 2002 - 17:44:48)
-
-CPU: MPC8245 Revision 16.20 at 264 MHz: 16 kB I-Cache 16 kB D-Cache
-Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)
-Built: Aug 6 2002 at 17:44:37
-Local Bus at 66 MHz
-DRAM: 64 MB
-FLASH: 4095 MB
-In: serial
-Out: serial
-Err: serial
-DOC: No DiskOnChip found
-Hit any key to stop autoboot: 0
-
-Broadcom BCM5701 1000Base-T: bus 0, device 13, function 0: MBAR=0x80100000
-BCM570x PCI Memory base address @0x80100000
-eth0:Broadcom BCM5701 1000Base-T: 100 Mbps half duplex link up, flow control OFF
-eth0: Broadcom BCM5701 1000Base-T @0x80100000,node addr 000010181010
-eth0: BCM5700 with Broadcom BCM5701 Integrated Copper transceiver found
-eth0: 32-bit PCI 33MHz, MTU: 1500,Rx Checksum ON
-ARP broadcast 1
-TFTP from server 172.16.40.111; our IP address is 172.16.40.114
-Filename 'vmlinux.img'.
-Load address: 0x100000
-Loading: #################################################################
- ####################################T #############################
- ######################
-done
-Bytes transferred = 777199 (bdbef hex)
-
-eth0:Broadcom BCM5701 1000Base-T,HALT,POWER DOWN,done - offline.
-## Booting image at 00100000 ...
- Image Name: vmlinux.bin.gz
- Created: 2002-08-06 6:30:13 UTC
- Image Type: PowerPC Linux Kernel Image (gzip compressed)
- Data Size: 777135 Bytes = 758 kB = 0 MB
- Load Address: 00000000
- Entry Point: 00000000
- Verifying Checksum ... OK
- Uncompressing Kernel Image ... OK
-Memory BAT mapping: BAT2=64Mb, BAT3=0Mb, residual: 0Mb
-Linux version 2.4.19-rc3 (jfd@que) (gcc version 2.95.3 20010111 (prerelease/franzo/20010111)) #168 Mon Aug 5 23:29:20 PDT 2002
-CPU:82xx: 32 I-Cache Block Size, 32 D-Cache Block Size PVR: 0x810000
-U-Boot Environment: 0xc01b08f0
-IP PNP: 802.3 Ethernet Address=<0:0:10:18:10:10>
-cpu0: MPC8245/KAHLUA-II : BMW Platform : 64MB RAM: BPLD Rev. 6e
-NOTICE: mounting root file system via NFS
-IP PNP: switch-2: eth0 IP 172.16.40.114/255.255.240.0 gateway 10.16.64.1 server 172.16.40.111
-On node 0 totalpages: 16384
-zone(0): 16384 pages.
-zone(1): 0 pages.
-zone(2): 0 pages.
-Kernel command line: console=ttyS0,9600 ip=172.16.40.114:172.16.40.111:10.16.64.1:255.255.240.0:switch-2:eth0 root=/dev/nfs rw nfsroot=172.16.40.111:/boot/root-fs,timeo=200,retrans=500 nfsaddrs=172.16.40.114:172.16.40.111
-root_dev_setup:/dev/nfs or 00:ff
-time_init: decrementer frequency = 16.501145 MHz
-Calibrating delay loop... 175.71 BogoMIPS
-Memory: 62572k available (1396k kernel code, 436k data, 100k init, 0k highmem)
-Dentry cache hash table entries: 8192 (order: 4, 65536 bytes)
-Inode cache hash table entries: 4096 (order: 3, 32768 bytes)
-Mount-cache hash table entries: 1024 (order: 1, 8192 bytes)
-Buffer-cache hash table entries: 4096 (order: 2, 16384 bytes)
-Page-cache hash table entries: 16384 (order: 4, 65536 bytes)
-POSIX conformance testing by UNIFIX
-PCI: Probing PCI hardware
-Linux NET4.0 for Linux 2.4
-Based upon Swansea University Computer Society NET3.039
-Initializing RT netlink socket
-Starting kswapd
-devfs: v1.12a (20020514) Richard Gooch (rgooch@atnf.csiro.au)
-devfs: devfs_debug: 0x0
-devfs: boot_options: 0x1
-Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
-pty: 256 Unix98 ptys configured
-Serial driver version 5.05c (2001-07-08) with MANY_PORTS SHARE_IRQ SERIAL_PCI enabled
-Testing ttyS0 (0xf7f51500, 0xf7f51500)...
-Testing ttyS1 (0xfc004600, 0xfc004600)...
-ttyS00 at 0xf7f51500 (irq = 24) is a ST16650
-ttyS01 at 0xfc004600 (irq = 25) is a 16550A
-Real Time Clock Driver v1.10e
-RAMDISK driver initialized: 16 RAM disks of 4096K size 1024 blocksize
-loop: loaded (max 8 devices)
-TFFS 5.1.1 Flash disk driver for DiskOnChip
-Copyright (C) 1998,2001 M-Systems Flash Disk Pioneers Ltd.
-DOC device(s) found: 1
-fl_init: registered device at major: 100
-fl_geninit: registered device at major: 100
-Partition check:
- fla: p1
-partition: /dev/fl/0: start_sect: 0,nr_sects: 32000 Fl_blk_size[]: 16000KB
-partition: /dev/fl/1: start_sect: 2,nr_sects: 31998 Fl_blk_size[]: 15999KB
-partition: /dev/fl/2: start_sect: 0,nr_sects: 0 Fl_blk_size[]: 0KB
-partition: /dev/fl/3: start_sect: 0,nr_sects: 0 Fl_blk_size[]: 0KB
-Broadcom Gigabit Ethernet Driver bcm5700 ver. 3.0.7 (07/17/02)
-eth0: Broadcom BCM5701 found at mem bfff0000, IRQ 1, node addr 000010181010
-eth0: Broadcom BCM5701 Integrated Copper transceiver found
-eth0: Scatter-gather ON, 64-bit DMA ON, Tx Checksum ON, Rx Checksum ON, 802.1Q VLAN ON
-bond0 registered without MII link monitoring, in bonding mode.
-rtc: unable to get misc minor
-NET4: Linux TCP/IP 1.0 for NET4.0
-IP Protocols: ICMP, UDP, TCP, IGMP
-IP: routing cache hash table of 512 buckets, 4Kbytes
-TCP: Hash tables configured (established 4096 bind 4096)
-bcm5700: eth0 NIC Link is UP, 100 Mbps half duplex
-IP-Config: Gateway not on directly connected network.
-NET4: Unix domain sockets 1.0/SMP for Linux NET4.0.
-802.1Q VLAN Support v1.7 Ben Greear <greearb@candelatech.com>
-All bugs added by David S. Miller <davem@redhat.com>
-Looking up port of RPC 100003/2 on 172.16.40.111
-Looking up port of RPC 100005/1 on 172.16.40.111
-VFS: Mounted root (nfs filesystem).
-Mounted devfs on /dev
-Freeing unused kernel memory: 100k init
-INIT: version 2.78 booting
-Mounting local filesystems...
-not mounted anything
-Setting up symlinks in /dev...done.
-Setting up extra devices in /dev...done.
-Starting devfsd...Started device management daemon for /dev
-INIT: Entering runlevel: 2
-Starting internet superserver: inetd.
-
-
-Welcome to Linux/PPC
-MPC8245/BMW
-
-
-switch-2 login: root
-Password:
-PAM_unix[49]: (login) session opened for user root by LOGIN(uid=0)
-Last login: Thu Nov 25 11:51:14 1920 on console
-
-
-Welcome to Linux/PPC
-MPC8245/BMW
-
-
-login[49]: ROOT LOGIN on `console'
-
-root@switch-2:~# cat /proc/cpuinfo
-cpu : 82xx
-revision : 16.20 (pvr 8081 1014)
-bogomips : 175.71
-vendor : Broadcom
-machine : BMW/MPC8245
-root@switch-2:~#
+++ /dev/null
-/*
- * (C) Copyright 2002
- * James F. Dougherty, Broadcom Corporation, jfd@broadcom.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <watchdog.h>
-#include <command.h>
-#include <malloc.h>
-#include <stdio_dev.h>
-#include <net.h>
-#include <timestamp.h>
-#include <dtt.h>
-#include <mpc824x.h>
-#include <asm/processor.h>
-#include <linux/mtd/doc2000.h>
-
-#include "bmw.h"
-#include "m48t59y.h"
-#include <pci.h>
-
-
-int checkboard(void)
-{
- ulong busfreq = get_bus_freq(0);
- char buf[32];
-
- puts ("Board: BMW MPC8245/KAHLUA2 - CHRP (MAP B)\n");
- printf("Built: %s at %s\n", U_BOOT_DATE, U_BOOT_TIME);
- /* printf("MPLD: Revision %d\n", SYS_REVID_GET()); */
- printf("Local Bus at %s MHz\n", strmhz(buf, busfreq));
- return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
- return 64*1024*1024;
-}
-
-
-void
-get_tod(void)
-{
- int year, month, day, hour, minute, second;
-
- m48_tod_get(&year,
- &month,
- &day,
- &hour,
- &minute,
- &second);
-
- printf(" Current date/time: %d/%d/%d %d:%d:%d \n",
- month, day, year, hour, minute, second);
-
-}
-
-/*
- * EPIC, PCI, and I/O devices.
- * Initialize Mousse Platform, probe for PCI devices,
- * Query configuration parameters if not set.
- */
-int misc_init_f (void)
-{
-#if 0
- m48_tod_init(); /* Init SGS M48T59Y TOD/NVRAM */
- printf("RTC: M48T589 TOD/NVRAM (%d) bytes\n",
- TOD_NVRAM_SIZE);
- get_tod();
-#endif
-
- sys_led_msg("BOOT");
- return 0;
-}
-
-
-/*
- * Initialize PCI Devices, report devices found.
- */
-struct pci_controller hose;
-
-void pci_init_board (void)
-{
- pci_mpc824x_init(&hose);
- /* pci_dev_init(0); */
-}
-
-/*
- * Write characters to LCD display.
- * Note that the bytes for the first character is the last address.
- */
-void
-sys_led_msg(char* msg)
-{
- LED_REG(0) = msg[3];
- LED_REG(1) = msg[2];
- LED_REG(2) = msg[1];
- LED_REG(3) = msg[0];
-}
-
-#ifdef CONFIG_CMD_DOC
-/*
- * Map onboard TSOP-16MB DOC FLASH chip.
- */
-void doc_init (void)
-{
- doc_probe(DOC_BASE_ADDR);
-}
-#endif
-
-#define NV_ADDR ((volatile unsigned char *) CONFIG_ENV_ADDR)
-
-/* Read from NVRAM */
-void*
-nvram_read(void *dest, const long src, size_t count)
-{
- int i;
- volatile unsigned char* d = (unsigned char*)dest;
- volatile unsigned char* s = (unsigned char*)src;
-
- for( i = 0; i < count;i++)
- d[i] = s[i];
-
- return dest;
-}
-
-/* Write to NVRAM */
-void
-nvram_write(long dest, const void *src, size_t count)
-{
- int i;
- volatile unsigned char* d = (unsigned char*)dest;
- volatile unsigned char* s = (unsigned char*)src;
-
- SYS_TOD_UNPROTECT();
-
- for( i = 0; i < count;i++)
- d[i] = s[i];
-
- SYS_TOD_PROTECT();
-}
+++ /dev/null
-/*
- * BMW/MPC8245 Board definitions.
- * For more info, see http://www.vooha.com/
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2002
- * James Dougherty (jfd@broadcom.com)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __BMW_H
-#define __BMW_H
-
-/* System addresses */
-
-#define PCI_SPECIAL_BASE 0xfe000000
-#define PCI_SPECIAL_SIZE 0x01000000
-
-#define EUMBBAR_VAL 0x80500000 /* Location of EUMB region */
-#define EUMBSIZE 0x00100000 /* Size of EUMB region */
-
-/* Extended ROM space devices */
-#define DOC_BASE_ADDR 0xff000000 /* Onboard DOC TSOP 16MB */
-#define DOC2_BASE_ADDR 0x70000000 /* DIP32 socket -> 1GB */
-#define XROM_BASE_ADDR 0x7c000000 /* RCS2 (PAL / Satellite IO) */
-#define PLD_REG_BASE XROM_BASE_ADDR
-#define LED_REG_BASE (XROM_BASE_ADDR | 0x2000)
-#define TOD_BASE (XROM_BASE_ADDR | 0x4000)
-#define LED_REG(x) (*(volatile unsigned char *) \
- (LED_REG_BASE + (x)))
-#define XROM_DEV_SIZE 0x00006000
-
-#define ENET_DEV_BASE 0x80000000
-
-#define PLD_REG(off) (*(volatile unsigned char *)\
- (PLD_REG_BASE + (off)))
-
-#define PLD_REVID_B1 0x7f /* Fix me */
-#define PLD_REVID_B2 0x01 /* Fix me */
-
-#define SYS_HARD_RESET() { for (;;) PLD_REG(0) = 0; } /* clr 0x80 bit */
-#define SYS_REVID_GET() ((int) PLD_REG(0) & 0x7f)
-#define SYS_LED_OFF() (PLD_REG(1) |= 0x80)
-#define SYS_LED_ON() (PLD_REG(1) &= ~0x80)
-#define SYS_WATCHDOG_IRQ3() (PLD_REG(2) |= 0x80)
-#define SYS_WATCHDOG_RESET() (PLD_REG(2) &= ~0x80)
-#define SYS_TOD_PROTECT() (PLD_REG(3) |= 0x80)
-#define SYS_TOD_UNPROTECT() (PLD_REG(3) &= ~0x80)
-
-#define TOD_REG_BASE (TOD_BASE | 0x1ff0)
-#define TOD_NVRAM_BASE TOD_BASE
-#define TOD_NVRAM_SIZE 0x1ff0
-#define TOD_NVRAM_LIMIT (TOD_NVRAM_BASE + TOD_NVRAM_SIZE)
-#define RTC(r) (TOD_BASE + r)
-
-/* Onboard BCM570x device */
-#define PCI_ENET_IOADDR 0x80000000
-#define PCI_ENET_MEMADDR 0x80000000
-
-
-#ifndef __ASSEMBLY__
-/* C Function prototypes */
-void sys_led_msg(char* msg);
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* __BMW_H */
+++ /dev/null
-#
-# (C) Copyright 2001
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-#
-# BMW board
-#
-
-# NOTE: The flags below affect how the BCM570x driver is compiled
-PLATFORM_CPPFLAGS += -DEMBEDDED -DBIG_ENDIAN_HOST -DINCLUDE_5701_AX_FIX=1\
- -DDBG=0 -DT3_JUMBO_RCV_RCB_ENTRY_COUNT=256
+++ /dev/null
-#include <ppc_asm.tmpl>
-#include <mpc824x.h>
-#include <ppc_defs.h>
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-#define USE_V2_INIT 1 /* Jimmy Blair's initialization. */
-
-
-/*
- * Initialize the MMU using BAT entries and hardwired TLB
- * This obviates the need for any code in cpu_init_f which
- * configures the BAT registers.
-*/
-#define MEMORY_MGMT_MSR_BITS (MSR_DR | MSR_IR) /* Data and Inst Relocate */
- .global iommu_setup
- /* Initialize IO/MMU mappings via BAT method Ch. 7,
- * PPC Programming Reference
- */
-iommu_setup:
-
-/* initialize the BAT registers (SPRs 528 - 543 */
-#define mtibat0u(x) mtspr 528,(x) /* SPR 528 (IBAT0U) */
-#define mtibat0l(x) mtspr 529,(x) /* SPR 529 (IBAT0L) */
-#define mtibat1u(x) mtspr 530,(x) /* SPR 530 (IBAT1U) */
-#define mtibat1l(x) mtspr 531,(x) /* SPR 531 (IBAT1L) */
-#define mtibat2u(x) mtspr 532,(x) /* SPR 532 (IBAT2U) */
-#define mtibat2l(x) mtspr 533,(x) /* SPR 533 (IBAT2L) */
-#define mtibat3u(x) mtspr 534,(x) /* SPR 534 (IBAT3U) */
-#define mtibat3l(x) mtspr 535,(x) /* SPR 535 (IBAT3L) */
-#define mtdbat0u(x) mtspr 536,(x) /* SPR 536 (DBAT0U) */
-#define mtdbat0l(x) mtspr 537,(x) /* SPR 537 (DBAT0L) */
-#define mtdbat1u(x) mtspr 538,(x) /* SPR 538 (DBAT1U) */
-#define mtdbat1l(x) mtspr 539,(x) /* SPR 539 (DBAT1L) */
-#define mtdbat2u(x) mtspr 540,(x) /* SPR 540 (DBAT2U) */
-#define mtdbat2l(x) mtspr 541,(x) /* SPR 541 (DBAT2L) */
-#define mtdbat3u(x) mtspr 542,(x) /* SPR 542 (DBAT3U) */
-#define mtdbat3l(x) mtspr 543,(x) /* SPR 543 (DBAT3L) */
-
-
-/* PowerPC processors do not necessarily initialize the BAT
- registers on power-up or reset. So they are in an unknown
- state. Before programming the BATs for the first time, all
- BAT registers MUST have their Vs and Vp bits cleared in the
- upper BAT half in order to avoid possibly having 2 BATs
- valid and mapping the same memory region.
-
- The reason for this is that, even with address translation
- disabled, multiple BAT hits for an address are treated as
- programming errors and can cause unpredictable results.
-
- It is up to the software to make sure it never has 2 IBAT
- mappings or 2 DBAT mappings that are valid for the same
- addresses. It is not necessary to perform this code
- sequence every time the BATs are programmed, only when
- there is a possibility that there may be overlapping BAT
- entries.
-
- When programming the BATs in non-reset scenarios, even if
- you are sure that your new mapping will not temporarily
- create overlapping regions, it is still a wise idea to
- invalidate a BAT entry by setting its upper BAT register to
- all 0's before programming it. This will avoid having a
- BAT marked valid that is in an unknown or transient state
-*/
-
- addis r5,0,0x0000
- mtibat0u(r5)
- mtibat0l(r5)
- mtibat1u(r5)
- mtibat1l(r5)
- mtibat2u(r5)
- mtibat2l(r5)
- mtibat3u(r5)
- mtibat3l(r5)
- mtdbat0u(r5)
- mtdbat0l(r5)
- mtdbat1u(r5)
- mtdbat1l(r5)
- mtdbat2u(r5)
- mtdbat2l(r5)
- mtdbat3u(r5)
- mtdbat3l(r5)
- isync
-
-/*
- * Set up I/D BAT0
- */
- lis r4, CONFIG_SYS_DBAT0L@h
- ori r4, r4, CONFIG_SYS_DBAT0L@l
- lis r3, CONFIG_SYS_DBAT0U@h
- ori r3, r3, CONFIG_SYS_DBAT0U@l
-
- mtdbat0l(r4)
- isync
- mtdbat0u(r3)
- isync
- sync
-
- lis r4, CONFIG_SYS_IBAT0L@h
- ori r4, r4, CONFIG_SYS_IBAT0L@l
- lis r3, CONFIG_SYS_IBAT0U@h
- ori r3, r3, CONFIG_SYS_IBAT0U@l
-
- isync
- mtibat0l(r4)
- isync
- mtibat0u(r3)
- isync
-
-/*
- * Set up I/D BAT1
- */
- lis r4, CONFIG_SYS_IBAT1L@h
- ori r4, r4, CONFIG_SYS_IBAT1L@l
- lis r3, CONFIG_SYS_IBAT1U@h
- ori r3, r3, CONFIG_SYS_IBAT1U@l
-
- isync
- mtibat1l(r4)
- isync
- mtibat1u(r3)
- isync
- mtdbat1l(r4)
- isync
- mtdbat1u(r3)
- isync
- sync
-
-/*
- * Set up I/D BAT2
- */
- lis r4, CONFIG_SYS_IBAT2L@h
- ori r4, r4, CONFIG_SYS_IBAT2L@l
- lis r3, CONFIG_SYS_IBAT2U@h
- ori r3, r3, CONFIG_SYS_IBAT2U@l
-
- isync
- mtibat2l(r4)
- isync
- mtibat2u(r3)
- isync
- mtdbat2l(r4)
- isync
- mtdbat2u(r3)
- isync
- sync
-
-/*
- * Setup I/D BAT3
- */
- lis r4, CONFIG_SYS_IBAT3L@h
- ori r4, r4, CONFIG_SYS_IBAT3L@l
- lis r3, CONFIG_SYS_IBAT3U@h
- ori r3, r3, CONFIG_SYS_IBAT3U@l
-
- isync
- mtibat3l(r4)
- isync
- mtibat3u(r3)
- isync
- mtdbat3l(r4)
- isync
- mtdbat3u(r3)
- isync
- sync
-
-
-/*
- * Invalidate all 64 TLB's
- */
- lis r3, 0
- mtctr r3
- lis r5, 4
-
-tlblp:
- tlbie r3
- sync
- addi r3, r3, 0x1000
- cmplw r3, r5
- blt tlblp
-
- sync
-
-/*
- * Enable Data Translation
- */
- lis r4, MEMORY_MGMT_MSR_BITS@h
- ori r4, r4, MEMORY_MGMT_MSR_BITS@l
- mfmsr r3
- or r3, r4, r3
- mtmsr r3
- isync
- sync
-
- blr
-
-
-#ifdef USE_V2_INIT
-/* #define USER_I_CACHE_ENABLE 1*/ /* Fast rom boots */
-/* Macro for hiadjust and lo */
-#define HIADJ(arg) arg@ha
-#define HI(arg) arg@h
-#define LO(arg) arg@l
-
-#undef LOADPTR
-#define LOADPTR(reg,const32) \
- addis reg,r0,HIADJ(const32); addi reg,reg,LO(const32)
-
-.globl early_init_f
-
-early_init_f:
-/* MPC8245/BMW CPCI System Init
- * Jimmy Blair, Broadcom Corp, 2002.
- */
- mflr r11
- /* Zero-out registers */
-
- addis r0,r0,0
- mtspr SPRG0,r0
- mtspr SPRG1,r0
- mtspr SPRG2,r0
- mtspr SPRG3,r0
-
- /* Set MPU/MSR to a known state. Turn on FP */
-
- LOADPTR (r3, MSR_FP)
- sync
- mtmsr r3
- isync
-
- /* Init the floating point control/status register */
-
- mtfsfi 7,0x0
- mtfsfi 6,0x0
- mtfsfi 5,0x0
- mtfsfi 4,0x0
- mtfsfi 3,0x0
- mtfsfi 2,0x0
- mtfsfi 1,0x0
- mtfsfi 0,0x0
- isync
-
- /* Set MPU/MSR to a known state. Turn off FP */
-
-#if 1 /* Turn off floating point (remove to keep FP on) */
- andi. r3, r3, 0
- sync
- mtmsr r3
- isync
-#endif
-
- /* Init the Segment registers */
-
- andi. r3, r3, 0
- isync
- mtsr 0,r3
- isync
- mtsr 1,r3
- isync
- mtsr 2,r3
- isync
- mtsr 3,r3
- isync
- mtsr 4,r3
- isync
- mtsr 5,r3
- isync
- mtsr 6,r3
- isync
- mtsr 7,r3
- isync
- mtsr 8,r3
- isync
- mtsr 9,r3
- isync
- mtsr 10,r3
- isync
- mtsr 11,r3
- isync
- mtsr 12,r3
- isync
- mtsr 13,r3
- isync
- mtsr 14,r3
- isync
- mtsr 15,r3
- isync
-
- /* Turn off data and instruction cache control bits */
-
- mfspr r3, HID0
- isync
- rlwinm r4, r3, 0, 18, 15 /* r4 has ICE and DCE bits cleared */
- sync
- isync
- mtspr HID0, r4 /* HID0 = r4 */
- isync
-
- /* Get cpu type */
-
- mfspr r28, PVR
- rlwinm r28, r28, 16, 16, 31
-
- /* invalidate the MPU's data/instruction caches */
-
- lis r3, 0x0
- cmpli 0, 0, r28, CPU_TYPE_603
- beq cpuIs603
- cmpli 0, 0, r28, CPU_TYPE_603E
- beq cpuIs603
- cmpli 0, 0, r28, CPU_TYPE_603P
- beq cpuIs603
- cmpli 0, 0, r28, CPU_TYPE_604R
- bne cpuNot604R
-
-cpuIs604R:
- lis r3, 0x0
- mtspr HID0, r3 /* disable the caches */
- isync
- ori r4, r4, 0x0002 /* disable BTAC by setting bit 30 */
-
-cpuNot604R:
- ori r3, r3, (HID0_ICFI |HID0_DCI)
-
-cpuIs603:
- ori r3, r3, (HID0_ICE | HID0_DCE)
- or r4, r4, r3 /* set bits */
- sync
- isync
- mtspr HID0, r4 /* HID0 = r4 */
- andc r4, r4, r3 /* clear bits */
- isync
- cmpli 0, 0, r28, CPU_TYPE_604
- beq cpuIs604
- cmpli 0, 0, r28, CPU_TYPE_604E
- beq cpuIs604
- cmpli 0, 0, r28, CPU_TYPE_604R
- beq cpuIs604
- mtspr HID0, r4
- isync
-
-#ifdef USER_I_CACHE_ENABLE
- b instCacheOn603
-#else
- b cacheEnableDone
-#endif
-
-cpuIs604:
- LOADPTR (r5, 0x1000) /* loop count, 0x1000 */
- mtspr CTR, r5
-loopDelay:
- nop
- bdnz loopDelay
- isync
- mtspr HID0, r4
- isync
-
- /* turn the Instruction cache ON for faster FLASH ROM boots */
-
-#ifdef USER_I_CACHE_ENABLE
-
- ori r4, r4, (HID0_ICE | HID0_ICFI)
- isync /* Synchronize for ICE enable */
- b writeReg4
-instCacheOn603:
- ori r4, r4, (HID0_ICE | HID0_ICFI)
- rlwinm r3, r4, 0, 21, 19 /* clear the ICFI bit */
-
- /*
- * The setting of the instruction cache enable (ICE) bit must be
- * preceded by an isync instruction to prevent the cache from being
- * enabled or disabled while an instruction access is in progress.
- */
- isync
-writeReg4:
- mtspr HID0, r4 /* Enable Instr Cache & Inval cache */
- cmpli 0, 0, r28, CPU_TYPE_604
- beq cacheEnableDone
- cmpli 0, 0, r28, CPU_TYPE_604E
- beq cacheEnableDone
-
- mtspr HID0, r3 /* using 2 consec instructions */
- /* PPC603 recommendation */
-#endif
-cacheEnableDone:
-
- /* Detect map A or B */
-
- addis r5,r0, HI(CHRP_REG_ADDR)
- addis r6,r0, HI(CHRP_REG_DATA)
- LOADPTR (r7, KAHLUA_ID) /* Kahlua PCI controller ID */
- LOADPTR (r8, BMC_BASE)
-
- stwbrx r8,0,(r5)
- lwbrx r3,0,(r6) /* Store read value to r3 */
- cmp 0,0,r3,r7
- beq cr0, X4_KAHLUA_START
-
- /* It's not an 8240, is it an 8245? */
-
- LOADPTR (r7, KAHLUA2_ID) /* Kahlua PCI controller ID */
- cmp 0,0,r3,r7
- beq cr0, X4_KAHLUA_START
-
- /* Save the PCI controller type in r7 */
- mr r7, r3
-
- LOADPTR (r5, PREP_REG_ADDR)
- LOADPTR (r6, PREP_REG_DATA)
-
-X4_KAHLUA_START:
- /* MPC8245 changes begin here */
- LOADPTR (r3, MPC107_PCI_CMD) /* PCI command reg */
- stwbrx r3,0,r5
- li r4, 6 /* Command register value */
- sthbrx r4, 0, r6
-
- LOADPTR (r3, MPC107_PCI_STAT) /* PCI status reg */
- stwbrx r3,0,r5
- li r4, -1 /* Write-to-clear all bits */
- li r3, 2 /* PCI_STATUS is at +2 offset */
- sthbrx r4, r3, r6
-
- /*-------PROC_INT1_ADR */
-
- LOADPTR (r3, PROC_INT1_ADR) /* Processor I/F Config 1 reg. */
- stwbrx r3,0,r5
- LOADPTR (r4, 0xff141b98)
- stwbrx r4,0,r6
-
- /*-------PROC_INT2_ADR */
-
- LOADPTR (r3, PROC_INT2_ADR) /* Processor I/F Config 2 reg. */
- stwbrx r3,0,r5
- lis r4, 0x2000 /* Flush PCI config writes */
- stwbrx r4,0,r6
-
- LOADPTR (r9, KAHLUA2_ID)
- cmpl 0, 0, r7, r9
- bne L1not8245
-
- /* MIOCR1 -- turn on bit for DLL delay */
-
- LOADPTR (r3, MIOCR1_ADR_X)
- stwbrx r3,0,r5
- li r4, 0x04
- stb r4, MIOCR1_SHIFT(r6)
-
- /* For the MPC8245, set register 77 to %00100000 (see Errata #15) */
- /* SDRAM_CLK_DEL (0x77)*/
-
- LOADPTR (r3, MIOCR2_ADR_X)
- stwbrx r3,0,r5
- li r4, 0x10
- stb r4, MIOCR2_SHIFT(r6)
-
- /* PMCR2 -- set PCI hold delay to <10>b for 33 MHz */
-
- LOADPTR (r3, PMCR2_ADR_X)
- stwbrx r3,0,r5
- li r4, 0x20
- stb r4, PMCR2_SHIFT(r6)
-
- /* Initialize EUMBBAR early since 8245 has internal UART in EUMB */
-
- LOADPTR (r3, EUMBBAR)
- stwbrx r3,0,r5
- LOADPTR (r4, CONFIG_SYS_EUMB_ADDR)
- stwbrx r4,0,r6
-
-L1not8245:
-
- /* Toggle the DLL reset bit in AMBOR */
-
- LOADPTR (r3, AMBOR)
- stwbrx r3,0,r5
- lbz r4, 0(r6)
-
- andi. r4, r4, 0xdf
- stb r4, 0(r6) /* Clear DLL_RESET */
- sync
-
- ori r4, r4, 0x20 /* Set DLL_RESET */
- stb r4, 0(r6)
- sync
-
- andi. r4, r4, 0xdf
- stb r4, 0(r6) /* Clear DLL_RESET */
-
-
- /* Enable RCS2, use supplied timings */
- LOADPTR (r3, ERCR1)
- stwbrx r3,0,r5
- LOADPTR (r4, 0x80408000)
- stwbrx r4,0,r6
-
- /* Disable RCS3 parameters */
- LOADPTR (r3, ERCR2)
- stwbrx r3,0,r5
- LOADPTR (r4, 0x00000000)
- stwbrx r4,0,r6
-
- /* RCS3 at 0x70000000, 64KBytes */
- LOADPTR (r3, ERCR2)
- stwbrx r3,0,r5
- LOADPTR (r4, 0x00000004)
- stwbrx r4,0,r6
-
- /*-------MCCR1 */
-
-#ifdef INCLUDE_ECC
-#define MC_ECC 1
-#else /* INCLUDE_ECC */
-#define MC_ECC 0
-#endif /* INCLUDE_ECC */
-
-#define MC1_ROMNAL 8 /* 0-15 */
-#define MC1_ROMFAL 11 /* 0-31 */
-#define MC1_DBUS_SIZE 0 /* 0-3, read only */
-#define MC1_BURST 0 /* 0-1 */
-#define MC1_MEMGO 0 /* 0-1 */
-#define MC1_SREN 1 /* 0-1 */
-#define MC1_RAM_TYPE 0 /* 0-1 */
-#define MC1_PCKEN MC_ECC /* 0-1 */
-#define MC1_BANKBITS 0x5555 /* 2 bits/bank 7-0 */
-
- LOADPTR (r3, MEM_CONT1_ADR) /* Set MCCR1 (F0) */
- stwbrx r3,0,r5
- LOADPTR(r4, \
- MC1_ROMNAL << 28 | MC1_ROMFAL << 23 | \
- MC1_DBUS_SIZE << 21 | MC1_BURST << 20 | \
- MC1_MEMGO << 19 | MC1_SREN << 18 | \
- MC1_RAM_TYPE << 17 | MC1_PCKEN << 16 )
- li r3, MC1_BANKBITS
- cmpl 0, 0, r7, r9 /* Check for Kahlua2 */
- bne BankBitsAdd
- cmpli 0, 0, r3, 0x5555
- beq K2BankBitsHack /* On 8245, 5555 ==> 0 */
-BankBitsAdd:
- ori r4, r3, 0
-K2BankBitsHack:
- stwbrx r4, 0, r6
-
- /*------- MCCR2 */
-
-#define MC2_TS_WAIT_TIMER 0 /* 0-7 */
-#define MC2_ASRISE 8 /* 0-15 */
-#define MC2_ASFALL 4 /* 0-15 */
-#define MC2_INLINE_PAR_NOT_ECC 0 /* 0-1 */
-#define MC2_WRITE_PARITY_CHK_EN MC_ECC /* 0-1 */
-#define MC2_INLRD_PARECC_CHK_EN MC_ECC /* 0-1 */
-#define MC2_ECC_EN 0 /* 0-1 */
-#define MC2_EDO 0 /* 0-1 */
-/*
-* N.B. This refresh interval looks good up to 85 MHz with Hynix SDRAM.
-* May need to be decreased for 100 MHz
-*/
-#define MC2_REFINT 0x3a5 /* 0-0x3fff */
-#define MC2_RSV_PG 0 /* 0-1 */
-#define MC2_RMW_PAR MC_ECC /* 0-1 */
-
- LOADPTR (r3, MEM_CONT2_ADR) /* Set MCCR2 (F4) */
- stwbrx r3,0,r5
- LOADPTR(r4, \
- MC2_TS_WAIT_TIMER << 29 | MC2_ASRISE << 25 | \
- MC2_ASFALL << 21 | MC2_INLINE_PAR_NOT_ECC << 20 | \
- MC2_WRITE_PARITY_CHK_EN << 19 | \
- MC2_INLRD_PARECC_CHK_EN << 18 | \
- MC2_ECC_EN << 17 | MC2_EDO << 16 | \
- MC2_REFINT << 2 | MC2_RSV_PG << 1 | MC2_RMW_PAR)
- cmpl 0, 0, r7, r9 /* Check for Kahlua2 */
- bne notK2
- /* clear Kahlua2 reserved bits */
- LOADPTR (r3, 0xfffcffff)
- and r4, r4, r3
-notK2:
- stwbrx r4,0,r6
-
- /*------- MCCR3 */
-
-#define MC_BSTOPRE 0x079 /* 0-0x7ff */
-
-#define MC3_BSTOPRE_U (MC_BSTOPRE >> 4 & 0xf)
-#define MC3_REFREC 8 /* 0-15 */
-#define MC3_RDLAT (4+MC_ECC) /* 0-15 */
-#define MC3_CPX 0 /* 0-1 */
-#define MC3_RAS6P 0 /* 0-15 */
-#define MC3_CAS5 0 /* 0-7 */
-#define MC3_CP4 0 /* 0-7 */
-#define MC3_CAS3 0 /* 0-7 */
-#define MC3_RCD2 0 /* 0-7 */
-#define MC3_RP1 0 /* 0-7 */
-
- LOADPTR (r3, MEM_CONT3_ADR) /* Set MCCR3 (F8) */
- stwbrx r3,0,r5
- LOADPTR(r4, \
- MC3_BSTOPRE_U << 28 | MC3_REFREC << 24 | \
- MC3_RDLAT << 20 | MC3_CPX << 19 | \
- MC3_RAS6P << 15 | MC3_CAS5 << 12 | MC3_CP4 << 9 | \
- MC3_CAS3 << 6 | MC3_RCD2 << 3 | MC3_RP1)
- cmpl 0, 0, r7, r9 /* Check for Kahlua2 */
- bne notK2b
- /* clear Kahlua2 reserved bits */
- LOADPTR (r3, 0xff000000)
- and r4, r4, r3
-notK2b:
- stwbrx r4,0,r6
-
- /*------- MCCR4 */
-
-#define MC4_PRETOACT 3 /* 0-15 */
-#define MC4_ACTOPRE 5 /* 0-15 */
-#define MC4_WMODE 0 /* 0-1 */
-#define MC4_INLINE MC_ECC /* 0-1 */
-#define MC4_REGISTERED (1-MC_ECC) /* 0-1 */
-#define MC4_BSTOPRE_UU (MC_BSTOPRE >> 8 & 3)
-#define MC4_REGDIMM 0 /* 0-1 */
-#define MC4_SDMODE_CAS 2 /* 0-7 */
-#define MC4_DBUS_RCS1 1 /* 0-1, 8-bit */
-#define MC4_SDMODE_WRAP 0 /* 0-1 */
-#define MC4_SDMODE_BURST 2 /* 0-7 */
-#define MC4_ACTORW 3 /* 0-15 */
-#define MC4_BSTOPRE_L (MC_BSTOPRE & 0xf)
-
- LOADPTR (r3, MEM_CONT4_ADR) /* Set MCCR4 (FC) */
- stwbrx r3,0,r5
- LOADPTR(r4, \
- MC4_PRETOACT << 28 | MC4_ACTOPRE << 24 | \
- MC4_WMODE << 23 | MC4_INLINE << 22 | \
- MC4_REGISTERED << 20 | MC4_BSTOPRE_UU << 18 | \
- MC4_DBUS_RCS1 << 17 | \
- MC4_REGDIMM << 15 | MC4_SDMODE_CAS << 12 | \
- MC4_SDMODE_WRAP << 11 | MC4_SDMODE_BURST << 8 | \
- MC4_ACTORW << 4 | MC4_BSTOPRE_L)
- cmpl 0, 0, r7, r9 /* Check for Kahlua 2 */
- bne notK2c
- /* Turn on Kahlua2 extended ROM space */
- LOADPTR (r3, 0x00200000)
- or r4, r4, r3
-notK2c:
- stwbrx r4,0,r6
-
-#ifdef INCLUDE_ECC
- /*------- MEM_ERREN1 */
-
- LOADPTR (r3, MEM_ERREN1_ADR) /* Set MEM_ERREN1 (c0) */
- stwbrx r3,0,r5
- lwbrx r4,0,r6
- ori r4,r4,4 /* Set MEM_PERR_EN */
- stwbrx r4,0,r6
-#endif /* INCLUDE_ECC */
-
- /*------- MSAR/MEAR */
-
- LOADPTR (r3, MEM_START1_ADR) /* Set MSAR1 (80) */
- stwbrx r3,0,r5
- LOADPTR (r4, 0xc0804000)
- stwbrx r4,0,r6
-
- LOADPTR (r3, MEM_START2_ADR) /* Set MSAR2 (84) */
- stwbrx r3,0,r5
- LOADPTR (r4, 0xc0804000)
- stwbrx r4,0,r6
-
- LOADPTR (r3, XMEM_START1_ADR) /* Set MESAR1 (88) */
- stwbrx r3,0,r5
- LOADPTR (r4, 0x00000000)
- stwbrx r4,0,r6
-
- LOADPTR (r3, XMEM_START2_ADR) /* Set MESAR2 (8c) */
- stwbrx r3,0,r5
- LOADPTR (r4, 0x01010101)
- stwbrx r4,0,r6
-
- LOADPTR (r3, MEM_END1_ADR) /* Set MEAR1 (90) */
- stwbrx r3,0,r5
- LOADPTR (r4, 0xffbf7f3f)
- stwbrx r4,0,r6
-
- LOADPTR (r3, MEM_END2_ADR) /* Set MEAR2 (94) */
- stwbrx r3,0,r5
- LOADPTR (r4, 0xffbf7f3f)
- stwbrx r4,0,r6
-
- LOADPTR (r3, XMEM_END1_ADR) /* MEEAR1 (98) */
- stwbrx r3,0,r5
- LOADPTR (r4, 0x00000000)
- stwbrx r4,0,r6
-
- LOADPTR (r3, XMEM_END2_ADR) /* MEEAR2 (9c) */
- stwbrx r3,0,r5
- LOADPTR (r4, 0x01010101)
- stwbrx r4,0,r6
-
- /*-------ODCR */
-
- LOADPTR (r3, ODCR_ADR_X) /* Set ODCR */
- stwbrx r3,0,r5
-
- li r4, 0x7f
- stb r4, ODCR_SHIFT(r6) /* ODCR is at +3 offset */
-
- /*-------MBEN */
-
- LOADPTR (r3, MEM_EN_ADR) /* Set MBEN (a0) */
- stwbrx r3,0,r5
- li r4, 0x01 /* Enable bank 0 */
- stb r4, 0(r6) /* MBEN is at +0 offset */
-
-#if 0 /* Jimmy: I think page made is broken */
- /*-------PGMAX */
-
- LOADPTR (r3, MPM_ADR_X)
- stwbrx r3,0,r5
- li r4, 0x32
- stb r4, MPM_SHIFT(r6) /* PAGE_MODE is at +3 offset */
-#endif
-
- /* Wait before initializing other registers */
-
- lis r4,0x0001
- mtctr r4
-
-KahluaX4wait200us:
- bdnz KahluaX4wait200us
-
- /* Set MEMGO bit */
-
- LOADPTR (r3, MEM_CONT1_ADR) /* MCCR1 (F0) |= PGMAX */
- stwbrx r3,0,r5
- lwbrx r4,0,r6 /* old MCCR1 */
- oris r4,r4,0x0008 /* MEMGO=1 */
- stwbrx r4, 0, r6
-
- /* Wait again */
-
- addis r4,r0,0x0002
- ori r4,r4,0xffff
-
- mtctr r4
-
-KahluaX4wait8ref:
- bdnz KahluaX4wait8ref
-
- sync
- eieio
- mtlr r11
- blr
-
-#else /* USE_V2_INIT */
-
-
-/* U-Boot works, but memory will not run reliably for all address ranges.
- * Early U-Boot Working init, but 2.4.19 kernel will crash since memory is not
- * initialized correctly. Could work if debugged.
- */
-/* PCI Support routines */
-
- .globl __pci_config_read_32
-__pci_config_read_32:
- lis r4, 0xfec0
- stwbrx r3, r0, r4
- sync
- lis r4, 0xfee0
- lwbrx r3, 0, r4
- blr
- .globl __pci_config_read_16
-__pci_config_read_16:
- lis r4, 0xfec0
- andi. r5, r3, 2
- stwbrx r3, r0, r4
- sync
- oris r4, r5, 0xfee0
- lhbrx r3, r0, r4
- blr
- .globl __pci_config_read_8
-__pci_config_read_8:
- lis r4, 0xfec0
- andi. r5, r3, 3
- stwbrx r3, r0, r4
- sync
- oris r4, r5, 0xfee0
- lbz r3, 0(4)
- blr
- .globl __pci_config_write_32
-__pci_config_write_32:
- lis r5, 0xfec0
- stwbrx r3, r0, r5
- sync
- lis r5, 0xfee0
- stwbrx r4, r0, r5
- sync
- blr
- .globl __pci_config_write_16
-__pci_config_write_16:
- lis r5, 0xfec0
- andi. r6, r3, 2
- stwbrx r3, r0, 5
- sync
- oris r5, r6, 0xfee0
- sthbrx r4, r0, r5
- sync
- blr
- .globl __pci_config_write_8
-__pci_config_write_8:
- lis r5, 0xfec0
- andi. r6, r3, 3
- stwbrx r3, r0, r5
- sync
- oris r5, r6, 0xfee0
- stb r4, 0(r5)
- sync
- blr
- .globl in_8
-in_8:
- oris r3, r3, 0xfe00
- lbz r3,0(r3)
- blr
- .globl in_16
-in_16:
- oris r3, r3, 0xfe00
- lhbrx r3, 0, r3
- blr
- .globl in_16_ne
-in_16_ne:
- oris r3, r3, 0xfe00
- lhzx r3, 0, r3
- blr
- .globl in_32
-in_32:
- oris r3, r3, 0xfe00
- lwbrx r3, 0, r3
- blr
- .globl out_8
-out_8:
- oris r3, r3, 0xfe00
- stb r4, 0(r3)
- eieio
- blr
- .globl out_16
-out_16:
- oris r3, r3, 0xfe00
- sthbrx r4, 0, r3
- eieio
- blr
- .globl out_16_ne
-out_16_ne:
- oris r3, r3, 0xfe00
- sth r4, 0(r3)
- eieio
- blr
- .globl out_32
-out_32:
- oris r3, r3, 0xfe00
- stwbrx r4, 0, r3
- eieio
- blr
- .globl read_8
-read_8:
- lbz r3,0(r3)
- blr
- .globl read_16
-read_16:
- lhbrx r3, 0, r3
- blr
- .globl read_32
-read_32:
- lwbrx r3, 0, r3
- blr
- .globl read_32_ne
-read_32_ne:
- lwz r3, 0(r3)
- blr
- .globl write_8
-write_8:
- stb r4, 0(r3)
- eieio
- blr
- .globl write_16
-write_16:
- sthbrx r4, 0, r3
- eieio
- blr
- .globl write_32
-write_32:
- stwbrx r4, 0, r3
- eieio
- blr
- .globl write_32_ne
-write_32_ne:
- stw r4, 0(r3)
- eieio
- blr
-
-
-.globl early_init_f
-
-early_init_f:
- mflr r11
- lis r10, 0x8000
-
- /* PCI Latency Timer */
- li r4, 0x0d
- ori r3, r10, PLTR@l
- bl __pci_config_write_8
-
- /* Cache Line Size */
- li r4, 0x08
- ori r3, r10, PCLSR@l
- bl __pci_config_write_8
-
- /* PCI Cmd */
- li r4, 6
- ori r3, r10, PCICR@l
- bl __pci_config_write_16
-
-#if 1
- /* PCI Stat */
- ori r3, r10, PCISR@l
- bl __pci_config_read_16
- ori r4, r4, 0xffff
- ori r3, r10, PCISR@l
- bl __pci_config_write_16
-#endif
-
- /* PICR1 */
- lis r4, 0xff14
- ori r4, r4, 0x1b98
- ori r3, r10, PICR1@l
- bl __pci_config_write_32
-
-
- /* PICR2 */
- lis r4, 0x0404
- ori r4, r4, 0x0004
- ori r3, r10, PICR2@l
- bl __pci_config_write_32
-
- /* MIOCR1 */
- li r4, 0x04
- ori r3, r10, MIOCR1@l
- bl __pci_config_write_8
-
- /* For the MPC8245, set register 77 to %00100000 (see Errata #15) */
- /* SDRAM_CLK_DEL (0x77)*/
- li r4, 0x10
- ori r3, r10, MIOCR2@l
- bl __pci_config_write_8
-
- /* EUMBBAR */
- lis r4, 0xfc00
- ori r3, r10, EUMBBAR@l
- bl __pci_config_write_32
-
- /* AMBOR */
-
- /* Even if Address Map B is not being used (though it should),
- * the memory DLL needs to be cleared/set/cleared before using memory.
- */
-
- ori r3, r10, AMBOR@l
- bl __pci_config_read_8 /* get Current bits */
-
- andi. r4, r4, 0xffdf
- ori r3, r10, AMBOR@l
- bl __pci_config_write_16 /* Clear DLL_RESET */
-
- ori r4, r4, 0x0020
- ori r3, r10, AMBOR@l
- bl __pci_config_write_16 /* Set DLL_RESET */
-
- andi. r4, r4, 0xffdf
- ori r3, r10, AMBOR@l
- bl __pci_config_write_16 /* Clear DLL_RESET */
-
- /* ERCR1 */
- lis r4, 0x8040 /* Enable RCS2, use supplied timings */
- ori r4, r4, 0x8000
- ori r3, r10, ERCR1@l
- bl __pci_config_write_32
-
- /* ERCR2 */
- lis r4, 0x0000 /* Disable RCS3 parms */
- ori r4, r4, 0x0000
- ori r3, r10, ERCR2@l
- bl __pci_config_write_32
-
- /* ERCR3 */
- lis r4, 0x0000 /* RCS3 at 0x70000000, 64K bytes */
- ori r4, r4, 0x0004
- ori r3, r10, ERCR2@l
- bl __pci_config_write_32
-
- /* Preserve memgo bit */
- /* MCCR1 */
-
-/* lis r4, 0x75a8 / Safe Local ROM = 11+3 clocks */
- lis r4, 0x75a0 /* Safe Local ROM = 11+3 clocks */
-/* lis r4, 0x73a0 / Fast Local ROM = 7+3 clocks */
-/* oris r4, r4, 0x0010 / Burst ROM/Flash enable */
-/* oris r4, r4, 0x0004 / Self-refresh enable */
-
-/* ori r4,r4,0xFFFF / 16Mbit 2bank SDRAM */
-/* ori r4,r4,0xAAAA / 256Mbit 4bank SDRAM (8245 only) */
-/* ori r4,r4,0x5555 / 64Mbit 2bank SDRAM */
- ori r4,r4,0x0000 /* 64Mbit 4bank SDRAM */
-
- ori r3, r10, MCCR1@l
- bl __pci_config_write_32
-
- /* MCCR2 */
-
- lis r4,0x0000
-/* oris r4,r4,0x4000 / TS_WAIT_TIMER = 3 clocks */
- oris r4,r4,0x1000 /* ASRISE = 8 clocks */
- oris r4,r4,0x0080 /* ASFALL = 8 clocks */
-/* oris r4,r4,0x0010 / SDRAM Parity (else ECC) */
-/* oris r4,r4,0x0008 / Write parity check */
-/* oris r4,r4,0x0004 / SDRAM inline reads */
-
-
-/* Select a refresh rate; it needs to match the bus speed; if too */
-/* slow, data may be lost; if too fast, performance is lost. We */
-/* use the fastest value so we run at all speeds. */
-/* Refresh = (15600ns/busclk) - (213 (see UM)). */
-
-/* ori r4,r4,0x1d2c / 133 MHz mem bus = 1867 */
-/* ori r4,r4,0x150c / 100 MHz mem bus = 1347 */
-/* ori r4,r4,0x10fc / 83 MHz mem bus = 1087 */
-/* ori r4,r4,0x0cc4 / 66 MHz mem bus = 817 */
- ori r4,r4,0x04cc /* 33 MHz mem bus (SAFE) = 307 */
-/* ori r4,r4,0x0002 / Reserve a page */
-/* ori r4,r4,0x0001 / RWM parity */
-
- ori r3, r10, MCCR2@l
- bl __pci_config_write_32
-
-
- /* MCCR3 */
- lis r4,0x0000 /* BSTOPRE_M = 7 (see A/N) */
- oris r4,r4,0x0500 /* REFREC = 8 clocks */
- ori r3, r10, MCCR3@l
- bl __pci_config_write_32
-
- /* MCCR4 */ /* Turn on registered buffer mode */
- lis r4, 0x2000 /* PRETOACT = 3 clocks */
- oris r4,r4,0x0400 /* ACTOPRE = 5 clocks */
-/* oris r4,r4,0x0080 / Enable 8-beat burst (32-bit bus) */
-/* oris r4,r4,0x0040 / Enable Inline ECC/Parity */
- oris r4,r4,0x0020 /* EXTROM enabled */
- oris r4,r4,0x0010 /* Registered buffers */
-/* oris r4,r4,0x0000 / BSTOPRE_U = 0 (see A/N) */
- oris r4,r4,0x0002 /* DBUS_SIZ[2] (8 bit on RCS1) */
-
-/* ori r4,r4,0x8000 / Registered DIMMs */
- ori r4,r4,0x2000 /*CAS Latency (CL=3) (see RDLAT) */
-/* ori r4,r4,0x2000 / CAS Latency (CL=2) (see RDLAT) */
-/* ori r4,r4,0x0300 / Sequential wrap/8-beat burst */
- ori r4,r4,0x0200 /* Sequential wrap/4-beat burst */
- ori r4,r4,0x0030 /* ACTORW = 3 clocks */
- ori r4,r4,0x0009 /* BSTOPRE_L = 9 (see A/N) */
-
- ori r3, r10, MCCR4@l
- bl __pci_config_write_32
-
- /* MSAR1 */
- lis r4, 0xc0804000@h
- ori r4, r4, 0xc0804000@l
- ori r3, r10, MSAR1@l
- bl __pci_config_write_32
-
- /* MSAR2 */
- lis r4, 0xc0804000@h
- ori r4, r4, 0xc0804000@l
- ori r3, r10, MSAR2@l
- bl __pci_config_write_32
-
- /* MESAR1 */
- lis r4, 0x00000000@h
- ori r4, r4, 0x00000000@l
- ori r3, r10, EMSAR1@l
- bl __pci_config_write_32
-
- /* MESAR2 */
- lis r4, 0x01010101@h
- ori r4, r4, 0x01010101@l
- ori r3, r10, EMSAR2@l
- bl __pci_config_write_32
-
- /* MEAR1 */
- lis r4, 0xffbf7f3f@h
- ori r4, r4, 0xffbf7f3f@l
- ori r3, r10, MEAR1@l
- bl __pci_config_write_32
-
- /* MEAR2 */
- lis r4, 0xffbf7f3f@h
- ori r4, r4, 0xffbf7f3f@l
- ori r3, r10, MEAR2@l
- bl __pci_config_write_32
-
- /* MEEAR1 */
- lis r4, 0x00000000@h
- ori r4, r4, 0x00000000@l
- ori r3, r10, EMEAR1@l
- bl __pci_config_write_32
-
- /* MEEAR2 */
- lis r4, 0x01010101@h
- ori r4, r4, 0x01010101@l
- ori r3, r10, EMEAR2@l
- bl __pci_config_write_32
-
- /* ODCR */
- li r4, 0x7f
- ori r3, r10, ODCR@l
- bl __pci_config_write_8
-
- /* MBER */
- li r4, 0x01
- ori r3, r10, MBER@l
- bl __pci_config_write_8
-
- /* Page CTR aka PGMAX */
- li r4, 0x32
- ori r3, r10, 0x70
- bl __pci_config_write_8
-
-#if 0
- /* CLK Drive */
- ori r4, r10, 0xfc01 /* Top bit will be ignored */
- ori r3, r10, 0x74
- bl __pci_config_write_16
-#endif
-
- /* delay */
- lis r7, 1
- mtctr r7
-label1: bdnz label1
-
- /* Set memgo bit */
- /* MCCR1 */
- ori r3, r10, MCCR1@l
- bl __pci_config_read_32
- lis r7, 0x0008
- or r4, r3, r7
- ori r3, r10, MCCR1@l
- bl __pci_config_write_32
-
- /* delay again */
- lis r7, 1
- mtctr r7
-label2: bdnz label2
-#if 0
-/* DEBUG: Infinite loop, write then read */
-loop:
- lis r7, 0xffff
- mtctr r7
- li r3, 0x5004
- lis r4, 0xa0a0
- ori r4, r4, 0x5050
- bl write_32_ne
- li r3, 0x5004
- bl read_32_ne
- bdnz loop
-#endif
- mtlr r11
- blr
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <asm/processor.h>
-#include <asm/pci_io.h>
-
-#define ROM_CS0_START 0xFF800000
-#define ROM_CS1_START 0xFF000000
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static int write_word (flash_info_t * info, ulong dest, ulong data);
-
-#if 0
-static void flash_get_offsets (ulong base, flash_info_t * info);
-#endif /* 0 */
-
-/*flash command address offsets*/
-
-#if 0
-#define ADDR0 (0x555)
-#define ADDR1 (0x2AA)
-#define ADDR3 (0x001)
-#else
-#define ADDR0 (0xAAA)
-#define ADDR1 (0x555)
-#define ADDR3 (0x001)
-#endif
-
-#define FLASH_WORD_SIZE unsigned char
-
-/*-----------------------------------------------------------------------
- */
-
-#if 0
-static int byte_parity_odd (unsigned char x) __attribute__ ((const));
-#endif /* 0 */
-static unsigned long flash_id (unsigned char mfct, unsigned char chip)
- __attribute__ ((const));
-
-typedef struct {
- FLASH_WORD_SIZE extval;
- unsigned short intval;
-} map_entry;
-
-#if 0
-static int byte_parity_odd (unsigned char x)
-{
- x ^= x >> 4;
- x ^= x >> 2;
- x ^= x >> 1;
- return (x & 0x1) != 0;
-}
-#endif /* 0 */
-
-
-static unsigned long flash_id (unsigned char mfct, unsigned char chip)
-{
- static const map_entry mfct_map[] = {
- {(FLASH_WORD_SIZE) AMD_MANUFACT,
- (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)},
- {(FLASH_WORD_SIZE) FUJ_MANUFACT,
- (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)},
- {(FLASH_WORD_SIZE) STM_MANUFACT,
- (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)},
- {(FLASH_WORD_SIZE) MT_MANUFACT,
- (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)},
- {(FLASH_WORD_SIZE) INTEL_MANUFACT,
- (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)},
- {(FLASH_WORD_SIZE) INTEL_ALT_MANU,
- (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}
- };
-
- static const map_entry chip_map[] = {
- {AMD_ID_F040B, FLASH_AM040},
- {(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB}
- };
-
- const map_entry *p;
- unsigned long result = FLASH_UNKNOWN;
-
- /* find chip id */
- for (p = &chip_map[0];
- p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++)
- if (p->extval == chip) {
- result = FLASH_VENDMASK | p->intval;
- break;
- }
-
- /* find vendor id */
- for (p = &mfct_map[0];
- p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++)
- if (p->extval == mfct) {
- result &= ~FLASH_VENDMASK;
- result |= (unsigned long) p->intval << 16;
- break;
- }
-
- return result;
-}
-
-
-unsigned long flash_init (void)
-{
- unsigned long i;
- unsigned char j;
- static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- flash_info_t *const pflinfo = &flash_info[i];
-
- pflinfo->flash_id = FLASH_UNKNOWN;
- pflinfo->size = 0;
- pflinfo->sector_count = 0;
- }
-
- for (i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) {
- flash_info_t *const pflinfo = &flash_info[i];
- const unsigned long base_address = flash_banks[i];
- volatile FLASH_WORD_SIZE *const flash =
- (FLASH_WORD_SIZE *) base_address;
-#if 0
- volatile FLASH_WORD_SIZE *addr2;
-#endif
-#if 0
- /* write autoselect sequence */
- flash[0x5555] = 0xaa;
- flash[0x2aaa] = 0x55;
- flash[0x5555] = 0x90;
-#else
- flash[0xAAA << (3 * i)] = 0xaa;
- flash[0x555 << (3 * i)] = 0x55;
- flash[0xAAA << (3 * i)] = 0x90;
-#endif
- __asm__ __volatile__ ("sync");
-
-#if 0
- pflinfo->flash_id = flash_id (flash[0x0], flash[0x1]);
-#else
- pflinfo->flash_id =
- flash_id (flash[0x0], flash[0x2 + 14 * i]);
-#endif
-
- switch (pflinfo->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- pflinfo->size = 0x00080000;
- pflinfo->sector_count = 8;
- for (j = 0; j < 8; j++) {
- pflinfo->start[j] =
- base_address + 0x00010000 * j;
- pflinfo->protect[j] = flash[(j << 16) | 0x2];
- }
- break;
- case FLASH_STM800AB:
- pflinfo->size = 0x00100000;
- pflinfo->sector_count = 19;
- pflinfo->start[0] = base_address;
- pflinfo->start[1] = base_address + 0x4000;
- pflinfo->start[2] = base_address + 0x6000;
- pflinfo->start[3] = base_address + 0x8000;
- for (j = 1; j < 16; j++) {
- pflinfo->start[j + 3] =
- base_address + 0x00010000 * j;
- }
-#if 0
- /* check for protected sectors */
- for (j = 0; j < pflinfo->sector_count; j++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr2 = (volatile FLASH_WORD_SIZE
- *) (pflinfo->start[j]);
- if (pflinfo->flash_id & FLASH_MAN_SST)
- pflinfo->protect[j] = 0;
- else
- pflinfo->protect[j] = addr2[2] & 1;
- }
-#endif
- break;
- }
- /* Protect monitor and environment sectors
- */
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- &flash_info[0]);
-#endif
-
- /* reset device to read mode */
- flash[0x0000] = 0xf0;
- __asm__ __volatile__ ("sync");
- }
-
- return flash_info[0].size + flash_info[1].size;
-}
-
-#if 0
-static void flash_get_offsets (ulong base, flash_info_t * info)
-{
- int i;
-
- /* set up sector start address table */
- if (info->flash_id & FLASH_MAN_SST) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
-
-}
-#endif /* 0 */
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- static const char unk[] = "Unknown";
- const char *mfct = unk, *type = unk;
- unsigned int i;
-
- if (info->flash_id != FLASH_UNKNOWN) {
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- mfct = "AMD";
- break;
- case FLASH_MAN_FUJ:
- mfct = "FUJITSU";
- break;
- case FLASH_MAN_STM:
- mfct = "STM";
- break;
- case FLASH_MAN_SST:
- mfct = "SST";
- break;
- case FLASH_MAN_BM:
- mfct = "Bright Microelectonics";
- break;
- case FLASH_MAN_INTEL:
- mfct = "Intel";
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- type = "AM29F040B (512K * 8, uniform sector size)";
- break;
- case FLASH_AM400B:
- type = "AM29LV400B (4 Mbit, bottom boot sect)";
- break;
- case FLASH_AM400T:
- type = "AM29LV400T (4 Mbit, top boot sector)";
- break;
- case FLASH_AM800B:
- type = "AM29LV800B (8 Mbit, bottom boot sect)";
- break;
- case FLASH_AM800T:
- type = "AM29LV800T (8 Mbit, top boot sector)";
- break;
- case FLASH_AM160T:
- type = "AM29LV160T (16 Mbit, top boot sector)";
- break;
- case FLASH_AM320B:
- type = "AM29LV320B (32 Mbit, bottom boot sect)";
- break;
- case FLASH_AM320T:
- type = "AM29LV320T (32 Mbit, top boot sector)";
- break;
- case FLASH_STM800AB:
- type = "M29W800AB (8 Mbit, bottom boot sect)";
- break;
- case FLASH_SST800A:
- type = "SST39LF/VF800 (8 Mbit, uniform sector size)";
- break;
- case FLASH_SST160A:
- type = "SST39LF/VF160 (16 Mbit, uniform sector size)";
- break;
- }
- }
-
- printf ("\n Brand: %s Type: %s\n"
- " Size: %lu KB in %d Sectors\n",
- mfct, type, info->size >> 10, info->sector_count);
-
- printf (" Sector Start Addresses:");
-
- for (i = 0; i < info->sector_count; i++) {
- unsigned long size;
- unsigned int erased;
- unsigned long *flash = (unsigned long *) info->start[i];
-
- /*
- * Check if whole sector is erased
- */
- size = (i != (info->sector_count - 1)) ?
- (info->start[i + 1] - info->start[i]) >> 2 :
- (info->start[0] + info->size - info->start[i]) >> 2;
-
- for (flash = (unsigned long *) info->start[i], erased = 1;
- (flash != (unsigned long *) info->start[i] + size)
- && erased; flash++)
- erased = *flash == ~0x0UL;
-
- printf ("%s %08lX %s %s",
- (i % 5) ? "" : "\n ",
- info->start[i],
- erased ? "E" : " ", info->protect[i] ? "RO" : " ");
- }
-
- puts ("\n");
- return;
-}
-
-#if 0
-
-/*
- * The following code cannot be run from FLASH!
- */
-ulong flash_get_size (vu_long * addr, flash_info_t * info)
-{
- short i;
- FLASH_WORD_SIZE value;
- ulong base = (ulong) addr;
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr;
-
- printf ("flash_get_size: \n");
- /* Write auto select command: read Manufacturer ID */
- eieio ();
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAA;
- addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55;
- addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90;
- value = addr2[0];
-
- switch (value) {
- case (FLASH_WORD_SIZE) AMD_MANUFACT:
- info->flash_id = FLASH_MAN_AMD;
- break;
- case (FLASH_WORD_SIZE) FUJ_MANUFACT:
- info->flash_id = FLASH_MAN_FUJ;
- break;
- case (FLASH_WORD_SIZE) SST_MANUFACT:
- info->flash_id = FLASH_MAN_SST;
- break;
- default:
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
- printf ("recognised manufacturer");
-
- value = addr2[ADDR3]; /* device ID */
- debug ("\ndev_code=%x\n", value);
-
- switch (value) {
- case (FLASH_WORD_SIZE) AMD_ID_LV400T:
- info->flash_id += FLASH_AM400T;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (FLASH_WORD_SIZE) AMD_ID_LV400B:
- info->flash_id += FLASH_AM400B;
- info->sector_count = 11;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- case (FLASH_WORD_SIZE) AMD_ID_LV800T:
- info->flash_id += FLASH_AM800T;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE) AMD_ID_LV800B:
- info->flash_id += FLASH_AM800B;
- info->sector_count = 19;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE) AMD_ID_LV160T:
- info->flash_id += FLASH_AM160T;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (FLASH_WORD_SIZE) AMD_ID_LV160B:
- info->flash_id += FLASH_AM160B;
- info->sector_count = 35;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (FLASH_WORD_SIZE) SST_ID_xF800A:
- info->flash_id += FLASH_SST800A;
- info->sector_count = 16;
- info->size = 0x00100000;
- break; /* => 1 MB */
-
- case (FLASH_WORD_SIZE) SST_ID_xF160A:
- info->flash_id += FLASH_SST160A;
- info->sector_count = 32;
- info->size = 0x00200000;
- break; /* => 2 MB */
-
- case (FLASH_WORD_SIZE) AMD_ID_F040B:
- info->flash_id += FLASH_AM040;
- info->sector_count = 8;
- info->size = 0x00080000;
- break; /* => 0.5 MB */
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- printf ("flash id %lx; sector count %x, size %lx\n", info->flash_id,
- info->sector_count, info->size);
- /* set up sector start address table */
- if (info->flash_id & FLASH_MAN_SST) {
- for (i = 0; i < info->sector_count; i++)
- info->start[i] = base + (i * 0x00010000);
- } else if (info->flash_id & FLASH_BTYPE) {
- /* set sector offsets for bottom boot block type */
- info->start[0] = base + 0x00000000;
- info->start[1] = base + 0x00004000;
- info->start[2] = base + 0x00006000;
- info->start[3] = base + 0x00008000;
- for (i = 4; i < info->sector_count; i++) {
- info->start[i] = base + (i * 0x00010000) - 0x00030000;
- }
- } else {
- /* set sector offsets for top boot block type */
- i = info->sector_count - 1;
- info->start[i--] = base + info->size - 0x00004000;
- info->start[i--] = base + info->size - 0x00006000;
- info->start[i--] = base + info->size - 0x00008000;
- for (; i >= 0; i--) {
- info->start[i] = base + i * 0x00010000;
- }
- }
-
- /* check for protected sectors */
- for (i = 0; i < info->sector_count; i++) {
- /* read sector protection at sector address, (A7 .. A0) = 0x02 */
- /* D0 = 1 if protected */
- addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]);
- if (info->flash_id & FLASH_MAN_SST)
- info->protect[i] = 0;
- else
- info->protect[i] = addr2[2] & 1;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr2 = (FLASH_WORD_SIZE *) info->start[0];
- *addr2 = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
- }
-
- return (info->size);
-}
-
-#endif
-
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
- unsigned char sh8b;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Check the ROM CS */
- if ((info->start[0] >= ROM_CS1_START)
- && (info->start[0] < ROM_CS0_START))
- sh8b = 3;
- else
- sh8b = 0;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080;
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->
- start
- [sect]
- -
- info->
- start
- [0]) <<
- sh8b));
- if (info->flash_id & FLASH_MAN_SST) {
- addr[ADDR0 << sh8b] =
- (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1 << sh8b] =
- (FLASH_WORD_SIZE) 0x00550055;
- addr[ADDR0 << sh8b] =
- (FLASH_WORD_SIZE) 0x00800080;
- addr[ADDR0 << sh8b] =
- (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1 << sh8b] =
- (FLASH_WORD_SIZE) 0x00550055;
- addr[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */
- udelay (30000); /* wait 30 ms */
- } else
- addr[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] -
- info->
- start[0]) << sh8b));
- while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
- (FLASH_WORD_SIZE) 0x00800080) {
- if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- serial_putc ('.');
- last = now;
- }
- }
-
- DONE:
- /* reset to read mode */
- addr = (FLASH_WORD_SIZE *) info->start[0];
- addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < 4 && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i = 0; i < 4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_word (info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0];
- volatile FLASH_WORD_SIZE *dest2;
- volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
- ulong start;
- int flag;
- int i;
- unsigned char sh8b;
-
- /* Check the ROM CS */
- if ((info->start[0] >= ROM_CS1_START)
- && (info->start[0] < ROM_CS0_START))
- sh8b = 3;
- else
- sh8b = 0;
-
- dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) +
- info->start[0]);
-
- /* Check if Flash is (sufficiently) erased */
- if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
- addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0;
-
- dest2[i << sh8b] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) !=
- (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
-
- return (0);
-}
-
-/*-----------------------------------------------------------------------
- */
+++ /dev/null
-/*
- * SGS M48-T59Y TOD/NVRAM Driver
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp.
- *
- * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * SGS M48-T59Y TOD/NVRAM Driver
- *
- * The SGS M48 an 8K NVRAM starting at offset M48_BASE_ADDR and
- * continuing for 8176 bytes. After that starts the Time-Of-Day (TOD)
- * registers which are used to set/get the internal date/time functions.
- *
- * This module implements Y2K compliance by taking full year numbers
- * and translating back and forth from the TOD 2-digit year.
- *
- * NOTE: for proper interaction with an operating system, the TOD should
- * be used to store Universal Coordinated Time (GMT) and timezone
- * conversions should be used.
- *
- * Here is a diagram of the memory layout:
- *
- * +---------------------------------------------+ 0xffe0a000
- * | Non-volatile memory | .
- * | | .
- * | (8176 bytes of Non-volatile memory) | .
- * | | .
- * +---------------------------------------------+ 0xffe0bff0
- * | Flags |
- * +---------------------------------------------+ 0xffe0bff1
- * | Unused |
- * +---------------------------------------------+ 0xffe0bff2
- * | Alarm Seconds |
- * +---------------------------------------------+ 0xffe0bff3
- * | Alarm Minutes |
- * +---------------------------------------------+ 0xffe0bff4
- * | Alarm Date |
- * +---------------------------------------------+ 0xffe0bff5
- * | Interrupts |
- * +---------------------------------------------+ 0xffe0bff6
- * | WatchDog |
- * +---------------------------------------------+ 0xffe0bff7
- * | Calibration |
- * +---------------------------------------------+ 0xffe0bff8
- * | Seconds |
- * +---------------------------------------------+ 0xffe0bff9
- * | Minutes |
- * +---------------------------------------------+ 0xffe0bffa
- * | Hours |
- * +---------------------------------------------+ 0xffe0bffb
- * | Day |
- * +---------------------------------------------+ 0xffe0bffc
- * | Date |
- * +---------------------------------------------+ 0xffe0bffd
- * | Month |
- * +---------------------------------------------+ 0xffe0bffe
- * | Year (2 digits only) |
- * +---------------------------------------------+ 0xffe0bfff
- */
-#include <common.h>
-#include <rtc.h>
-#include "bmw.h"
-
-/*
- * Imported from mousse.h:
- *
- * TOD_REG_BASE Base of m48t59y TOD registers
- * SYS_TOD_UNPROTECT() Disable NVRAM write protect
- * SYS_TOD_PROTECT() Re-enable NVRAM write protect
- */
-
-#define YEAR 0xf
-#define MONTH 0xe
-#define DAY 0xd
-#define DAY_OF_WEEK 0xc
-#define HOUR 0xb
-#define MINUTE 0xa
-#define SECOND 0x9
-#define CONTROL 0x8
-#define WATCH 0x7
-#define INTCTL 0x6
-#define WD_DATE 0x5
-#define WD_HOUR 0x4
-#define WD_MIN 0x3
-#define WD_SEC 0x2
-#define _UNUSED 0x1
-#define FLAGS 0x0
-
-#define M48_ADDR ((volatile unsigned char *) TOD_REG_BASE)
-
-int m48_tod_init(void)
-{
- SYS_TOD_UNPROTECT();
-
- M48_ADDR[CONTROL] = 0;
- M48_ADDR[WATCH] = 0;
- M48_ADDR[INTCTL] = 0;
-
- /*
- * If the oscillator is currently stopped (as on a new part shipped
- * from the factory), start it running.
- *
- * Here is an example of the TOD bytes on a brand new M48T59Y part:
- * 00 00 00 00 00 00 00 00 00 88 8c c3 bf c8 f5 01
- */
-
- if (M48_ADDR[SECOND] & 0x80)
- M48_ADDR[SECOND] = 0;
-
- /* Is battery low */
- if ( M48_ADDR[FLAGS] & 0x10) {
- printf("NOTICE: Battery low on Real-Time Clock (replace SNAPHAT).\n");
- }
-
- SYS_TOD_PROTECT();
-
- return 0;
-}
-
-/*
- * m48_tod_set
- */
-
-static int to_bcd(int value)
-{
- return value / 10 * 16 + value % 10;
-}
-
-static int from_bcd(int value)
-{
- return value / 16 * 10 + value % 16;
-}
-
-static int day_of_week(int y, int m, int d) /* 0-6 ==> Sun-Sat */
-{
- static int t[] = {0, 3, 2, 5, 0, 3, 5, 1, 4, 6, 2, 4};
- y -= m < 3;
- return (y + y/4 - y/100 + y/400 + t[m-1] + d) % 7;
-}
-
-/*
- * Note: the TOD should store the current GMT
- */
-
-int m48_tod_set(int year, /* 1980-2079 */
- int month, /* 01-12 */
- int day, /* 01-31 */
- int hour, /* 00-23 */
- int minute, /* 00-59 */
- int second) /* 00-59 */
-
-{
- SYS_TOD_UNPROTECT();
-
- M48_ADDR[CONTROL] |= 0x80; /* Set WRITE bit */
-
- M48_ADDR[YEAR] = to_bcd(year % 100);
- M48_ADDR[MONTH] = to_bcd(month);
- M48_ADDR[DAY] = to_bcd(day);
- M48_ADDR[DAY_OF_WEEK] = day_of_week(year, month, day) + 1;
- M48_ADDR[HOUR] = to_bcd(hour);
- M48_ADDR[MINUTE] = to_bcd(minute);
- M48_ADDR[SECOND] = to_bcd(second);
-
- M48_ADDR[CONTROL] &= ~0x80; /* Clear WRITE bit */
-
- SYS_TOD_PROTECT();
-
- return 0;
-}
-
-/*
- * Note: the TOD should store the current GMT
- */
-
-int m48_tod_get(int *year, /* 1980-2079 */
- int *month, /* 01-12 */
- int *day, /* 01-31 */
- int *hour, /* 00-23 */
- int *minute, /* 00-59 */
- int *second) /* 00-59 */
-{
- int y;
-
- SYS_TOD_UNPROTECT();
-
- M48_ADDR[CONTROL] |= 0x40; /* Set READ bit */
-
- y = from_bcd(M48_ADDR[YEAR]);
- *year = y < 80 ? 2000 + y : 1900 + y;
- *month = from_bcd(M48_ADDR[MONTH]);
- *day = from_bcd(M48_ADDR[DAY]);
- /* day_of_week = M48_ADDR[DAY_OF_WEEK] & 0xf; */
- *hour = from_bcd(M48_ADDR[HOUR]);
- *minute = from_bcd(M48_ADDR[MINUTE]);
- *second = from_bcd(M48_ADDR[SECOND] & 0x7f);
-
- M48_ADDR[CONTROL] &= ~0x40; /* Clear READ bit */
-
- SYS_TOD_PROTECT();
-
- return 0;
-}
-
-int m48_tod_get_second(void)
-{
- return from_bcd(M48_ADDR[SECOND] & 0x7f);
-}
-
-/*
- * Watchdog function
- *
- * If usec is 0, the watchdog timer is disarmed.
- *
- * If usec is non-zero, the watchdog timer is armed (or re-armed) for
- * approximately usec microseconds (if the exact requested usec is
- * not supported by the chip, the next higher available value is used).
- *
- * Minimum watchdog timeout = 62500 usec
- * Maximum watchdog timeout = 124 sec (124000000 usec)
- */
-
-void m48_watchdog_arm(int usec)
-{
- int mpy, res;
-
- SYS_TOD_UNPROTECT();
-
- if (usec == 0) {
- res = 0;
- mpy = 0;
- } else if (usec < 2000000) { /* Resolution: 1/16s if below 2s */
- res = 0;
- mpy = (usec + 62499) / 62500;
- } else if (usec < 8000000) { /* Resolution: 1/4s if below 8s */
- res = 1;
- mpy = (usec + 249999) / 250000;
- } else if (usec < 32000000) { /* Resolution: 1s if below 32s */
- res = 2;
- mpy = (usec + 999999) / 1000000;
- } else { /* Resolution: 4s up to 124s */
- res = 3;
- mpy = (usec + 3999999) / 4000000;
- if (mpy > 31)
- mpy = 31;
- }
-
- M48_ADDR[WATCH] = (0x80 | /* Steer to RST signal (IRQ = N/C) */
- mpy << 2 |
- res);
-
- SYS_TOD_PROTECT();
-}
-
-/*
- * U-Boot RTC support.
- */
-int
-rtc_get( struct rtc_time *tmp )
-{
- m48_tod_get(&tmp->tm_year,
- &tmp->tm_mon,
- &tmp->tm_mday,
- &tmp->tm_hour,
- &tmp->tm_min,
- &tmp->tm_sec);
- tmp->tm_yday = 0;
- tmp->tm_isdst= 0;
-
-#ifdef RTC_DEBUG
- printf( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
- tmp->tm_hour, tmp->tm_min, tmp->tm_sec );
-#endif
-
- return 0;
-}
-
-int rtc_set( struct rtc_time *tmp )
-{
- m48_tod_set(tmp->tm_year, /* 1980-2079 */
- tmp->tm_mon, /* 01-12 */
- tmp->tm_mday, /* 01-31 */
- tmp->tm_hour, /* 00-23 */
- tmp->tm_min, /* 00-59 */
- tmp->tm_sec); /* 00-59 */
-
-#ifdef RTC_DEBUG
- printf( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
- tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
-#endif
-
- return 0;
-}
-
-void
-rtc_reset (void)
-{
- m48_tod_init();
-}
+++ /dev/null
-/*
- * SGS M48-T59Y TOD/NVRAM Driver
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 1999, by Curt McDowell, 08-06-99, Broadcom Corp.
- *
- * (C) Copyright 2001, James Dougherty, 07/18/01, Broadcom Corp.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef __M48_T59_Y_H
-#define __M48_T59_Y_H
-
-/*
- * M48 T59Y -Timekeeping Battery backed SRAM.
- */
-
-int m48_tod_init(void);
-
-int m48_tod_set(int year,
- int month,
- int day,
- int hour,
- int minute,
- int second);
-
-int m48_tod_get(int *year,
- int *month,
- int *day,
- int *hour,
- int *minute,
- int *second);
-
-int m48_tod_get_second(void);
-
-void m48_watchdog_arm(int usec);
-
-#endif /*!__M48_T59_Y_H */
+++ /dev/null
-/*
- * COM1 NS16550 support
- * originally from linux source (arch/powerpc/boot/ns16550.c)
- * modified to use CONFIG_SYS_ISA_MEM and new defines
- */
-
-#include <config.h>
-#include "ns16550.h"
-
-typedef struct NS16550 *NS16550_t;
-
-const NS16550_t COM_PORTS[] =
- { (NS16550_t) ((CONFIG_SYS_EUMB_ADDR) + 0x4500),
-(NS16550_t) ((CONFIG_SYS_EUMB_ADDR) + 0x4600) };
-
-volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)
-{
- volatile struct NS16550 *com_port;
-
- com_port = (struct NS16550 *) COM_PORTS[chan];
- com_port->ier = 0x00;
- com_port->lcr = LCR_BKSE; /* Access baud rate */
- com_port->dll = baud_divisor & 0xff; /* 9600 baud */
- com_port->dlm = (baud_divisor >> 8) & 0xff;
- com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */
- com_port->mcr = MCR_RTS; /* RTS/DTR */
- com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */
- return (com_port);
-}
-
-void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor)
-{
- com_port->ier = 0x00;
- com_port->lcr = LCR_BKSE; /* Access baud rate */
- com_port->dll = baud_divisor & 0xff; /* 9600 baud */
- com_port->dlm = (baud_divisor >> 8) & 0xff;
- com_port->lcr = LCR_8N1; /* 8 data, 1 stop, no parity */
- com_port->mcr = MCR_RTS; /* RTS/DTR */
- com_port->fcr = FCR_FIFO_EN | FCR_RXSR | FCR_TXSR; /* Clear & enable FIFOs */
-}
-
-void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c)
-{
- while ((com_port->lsr & LSR_THRE) == 0);
- com_port->thr = c;
-}
-
-unsigned char NS16550_getc (volatile struct NS16550 *com_port)
-{
- while ((com_port->lsr & LSR_DR) == 0);
- return (com_port->rbr);
-}
-
-int NS16550_tstc (volatile struct NS16550 *com_port)
-{
- return ((com_port->lsr & LSR_DR) != 0);
-}
+++ /dev/null
-/*
- * NS16550 Serial Port
- * originally from linux source (arch/powerpc/boot/ns16550.h)
- * modified slightly to
- * have addresses as offsets from CONFIG_SYS_ISA_BASE
- * added a few more definitions
- * added prototypes for ns16550.c
- * reduced no of com ports to 2
- * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
- * further modified to support the 8245 duart
- * modifications (c) Paul Jimenez, Musenki, Inc. 2001.
- */
-
-
-struct NS16550 {
- unsigned char rbrthrdlb; /* 0 */
- unsigned char ierdmb; /* 1 */
- unsigned char iirfcrafr; /* 2 */
- unsigned char lcr; /* 3 */
- unsigned char mcr; /* 4 */
- unsigned char lsr; /* 5 */
- unsigned char msr; /* 6 */
- unsigned char scr; /* 7 */
- unsigned char reserved[2]; /* 8 & 9 */
- unsigned char dsr; /* 10 */
- unsigned char dcr; /* 11 */
-};
-
-
-#define rbr rbrthrdlb
-#define thr rbrthrdlb
-#define dll rbrthrdlb
-#define ier ierdmb
-#define dlm ierdmb
-#define iir iirfcrafr
-#define fcr iirfcrafr
-#define afr iirfcrafr
-
-#define FCR_FIFO_EN 0x01 /*fifo enable */
-#define FCR_RXSR 0x02 /*receiver soft reset */
-#define FCR_TXSR 0x04 /*transmitter soft reset */
-#define FCR_DMS 0x08 /* DMA Mode Select */
-
-#define MCR_RTS 0x02 /* Readyu to Send */
-#define MCR_LOOP 0x10 /* Local loopback mode enable */
-/* #define MCR_DTR 0x01 noton 8245 duart */
-/* #define MCR_DMA_EN 0x04 noton 8245 duart */
-/* #define MCR_TX_DFR 0x08 noton 8245 duart */
-
-#define LCR_WLS_MSK 0x03 /* character length slect mask */
-#define LCR_WLS_5 0x00 /* 5 bit character length */
-#define LCR_WLS_6 0x01 /* 6 bit character length */
-#define LCR_WLS_7 0x02 /* 7 bit character length */
-#define LCR_WLS_8 0x03 /* 8 bit character length */
-#define LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
-#define LCR_PEN 0x08 /* Parity eneble */
-#define LCR_EPS 0x10 /* Even Parity Select */
-#define LCR_STKP 0x20 /* Stick Parity */
-#define LCR_SBRK 0x40 /* Set Break */
-#define LCR_BKSE 0x80 /* Bank select enable - aka DLAB on 8245 */
-
-#define LSR_DR 0x01 /* Data ready */
-#define LSR_OE 0x02 /* Overrun */
-#define LSR_PE 0x04 /* Parity error */
-#define LSR_FE 0x08 /* Framing error */
-#define LSR_BI 0x10 /* Break */
-#define LSR_THRE 0x20 /* Xmit holding register empty */
-#define LSR_TEMT 0x40 /* Xmitter empty */
-#define LSR_ERR 0x80 /* Error */
-
-/* useful defaults for LCR*/
-#define LCR_8N1 0x03
-
-
-volatile struct NS16550 *NS16550_init (int chan, int baud_divisor);
-void NS16550_putc (volatile struct NS16550 *com_port, unsigned char c);
-unsigned char NS16550_getc (volatile struct NS16550 *com_port);
-int NS16550_tstc (volatile struct NS16550 *com_port);
-void NS16550_reinit (volatile struct NS16550 *com_port, int baud_divisor);
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include "ns16550.h"
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if CONFIG_CONS_INDEX == 1
-static struct NS16550 *console =
- (struct NS16550 *) (CONFIG_SYS_EUMB_ADDR + 0x4500);
-#elif CONFIG_CONS_INDEX == 2
-static struct NS16550 *console =
- (struct NS16550 *) (CONFIG_SYS_EUMB_ADDR + 0x4500);
-#else
-#error no valid console defined
-#endif
-
-extern ulong get_bus_freq (ulong);
-
-int serial_init (void)
-{
- int clock_divisor = gd->bus_clk / 16 / gd->baudrate;
-
- NS16550_init (CONFIG_CONS_INDEX - 1, clock_divisor);
-
- return (0);
-}
-
-void serial_putc (const char c)
-{
- if (c == '\n') {
- serial_putc ('\r');
- }
- NS16550_putc (console, c);
-}
-
-void serial_puts (const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
-
-int serial_getc (void)
-{
- return NS16550_getc (console);
-}
-
-int serial_tstc (void)
-{
- return NS16550_tstc (console);
-}
-
-void serial_setbrg (void)
-{
- int clock_divisor = get_bus_freq (0) / 16 / gd->baudrate;
-
- NS16550_reinit (console, clock_divisor);
-}
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
#include <common.h>
#include <board/cogent/serial.h>
+#include <serial.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
#error CONFIG_CONS_INDEX must be configured for Cogent motherboard serial
#endif
-int serial_init (void)
+static int cogent_serial_init(void)
{
cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
return (0);
}
-void serial_setbrg (void)
+static void cogent_serial_setbrg(void)
{
cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
unsigned int divisor;
cma_mb_reg_write (&mbsp->ser_lcr, lcr); /* unset DLAB */
}
-void serial_putc (const char c)
+static void cogent_serial_putc(const char c)
{
cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
cma_mb_reg_write (&mbsp->ser_thr, c);
}
-void serial_puts (const char *s)
-{
- while (*s != '\0')
- serial_putc (*s++);
-}
-
-int serial_getc (void)
+static int cogent_serial_getc(void)
{
cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
return ((int) cma_mb_reg_read (&mbsp->ser_rhr) & 0x7f);
}
-int serial_tstc (void)
+static int cogent_serial_tstc(void)
{
cma_mb_serial *mbsp = (cma_mb_serial *) CMA_MB_SERIAL_BASE;
return ((cma_mb_reg_read (&mbsp->ser_lsr) & LSR_DR) != 0);
}
+static struct serial_device cogent_serial_drv = {
+ .name = "cogent_serial",
+ .start = cogent_serial_init,
+ .stop = NULL,
+ .setbrg = cogent_serial_setbrg,
+ .putc = cogent_serial_putc,
+ .puts = default_serial_puts,
+ .getc = cogent_serial_getc,
+ .tstc = cogent_serial_tstc,
+};
+
+void cogent_serial_initialize(void)
+{
+ serial_register(&cogent_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &cogent_serial_drv;
+}
#endif /* CONS_NONE */
#if defined(CONFIG_CMD_KGDB) && \
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/tegra20.h>
+#include <asm/arch/tegra.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/mmc.h>
+#include <asm/arch-tegra/mmc.h>
#include <asm/gpio.h>
#ifdef CONFIG_TEGRA_MMC
#include <mmc.h>
#endif
-/*
- * Routine: gpio_config_uart
- * Description: Does nothing on Paz00 - no conflict w/SPI.
- */
-void gpio_config_uart(void)
-{
-}
#ifdef CONFIG_TEGRA_MMC
/*
*/
#include <common.h>
-#include <i2c.h>
#include <asm/io.h>
-#include <asm/arch/tegra20.h>
+#include <asm/arch/tegra.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/mmc.h>
+#include <asm/arch-tegra/mmc.h>
#include <asm/gpio.h>
+#include <i2c.h>
#ifdef CONFIG_TEGRA_MMC
#include <mmc.h>
#endif
-/*
- * Routine: gpio_config_uart
- * Description: Does nothing on TrimSlice - no UART-related GPIOs.
- */
-void gpio_config_uart(void)
-{
-}
void pin_mux_spi(void)
{
LIB = $(obj)lib$(BOARD).o
-COBJS = $(BOARD).o flash.o plx9030.o pd67290.o
+COBJS = $(BOARD).o flash.o plx9030.o pd67290.o ide.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
#endif
-# ifdef CONFIG_IDE_LED
-void ide_led (uchar led, uchar status)
-{
- u_char val;
- /* We have one PCMCIA slot and use LED H4 for the IDE Interface */
- val = readb(BCSR_BASE + 0x04);
- if (status) { /* led on */
- val |= B_CTRL_LED0;
- } else {
- val &= ~B_CTRL_LED0;
- }
- writeb(val, BCSR_BASE + 0x04);
-}
-# endif
-
int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
--- /dev/null
+/*
+ * (C) Copyright 2001
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * (C) Copyright 2000-2011
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <ide.h>
+#include <ata.h>
+#include <asm/io.h>
+
+#define EIEIO __asm__ volatile ("eieio")
+#define SYNC __asm__ volatile ("sync")
+
+void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+{
+ uchar i;
+ volatile uchar *pbuf_even =
+ (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
+ volatile uchar *pbuf_odd =
+ (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
+ ushort *dbuf = (ushort *) sect_buf;
+
+ while (words--) {
+ for (i = 0; i < 2; i++) {
+ *(((uchar *) (dbuf)) + 1) = *pbuf_even;
+ *(uchar *) dbuf = *pbuf_odd;
+ dbuf += 1;
+ }
+ }
+}
+
+void ide_input_data(int dev, ulong *sect_buf, int words)
+{
+ uchar *dbuf;
+ volatile uchar *pbuf_even;
+ volatile uchar *pbuf_odd;
+
+ pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
+ pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
+ dbuf = (uchar *) sect_buf;
+ while (words--) {
+ *dbuf++ = *pbuf_even;
+ EIEIO;
+ SYNC;
+ *dbuf++ = *pbuf_odd;
+ EIEIO;
+ SYNC;
+ *dbuf++ = *pbuf_even;
+ EIEIO;
+ SYNC;
+ *dbuf++ = *pbuf_odd;
+ EIEIO;
+ SYNC;
+ }
+}
+
+void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+ uchar *dbuf;
+ volatile uchar *pbuf_even;
+ volatile uchar *pbuf_odd;
+
+ pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
+ pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
+ dbuf = (uchar *) sect_buf;
+ while (shorts--) {
+ EIEIO;
+ *dbuf++ = *pbuf_even;
+ EIEIO;
+ *dbuf++ = *pbuf_odd;
+ }
+}
+
+void ide_output_data(int dev, const ulong *sect_buf, int words)
+{
+ uchar *dbuf;
+ volatile uchar *pbuf_even;
+ volatile uchar *pbuf_odd;
+
+ pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
+ pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
+ dbuf = (uchar *) sect_buf;
+ while (words--) {
+ EIEIO;
+ *pbuf_even = *dbuf++;
+ EIEIO;
+ *pbuf_odd = *dbuf++;
+ EIEIO;
+ *pbuf_even = *dbuf++;
+ EIEIO;
+ *pbuf_odd = *dbuf++;
+ }
+}
+
+void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
+{
+ uchar *dbuf;
+ volatile uchar *pbuf_even;
+ volatile uchar *pbuf_odd;
+
+ pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
+ pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
+ dbuf = (uchar *) sect_buf;
+ while (shorts--) {
+ EIEIO;
+ *pbuf_even = *dbuf++;
+ EIEIO;
+ *pbuf_odd = *dbuf++;
+ }
+}
+
+void ide_led(uchar led, uchar status)
+{
+ u_char val;
+ /* We have one PCMCIA slot and use LED H4 for the IDE Interface */
+ val = readb(BCSR_BASE + 0x04);
+ if (status) /* led on */
+ val |= B_CTRL_LED0;
+ else
+ val &= ~B_CTRL_LED0;
+
+ writeb(val, BCSR_BASE + 0x04);
+}
+
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
. = ALIGN(4);
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ } >.sram
+
. = ALIGN(4);
.rel.dyn : {
__rel_dyn_start = .;
*(.data.rel.ro)
}
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
+
. = ALIGN(4);
__rel_dyn_start = .;
__rel_dyn_end = .;
.sdata : { *(.sdata*) }
- .u_boot_cmd : {
- __u_boot_cmd_start = .;
- *(.u_boot_cmd)
- __u_boot_cmd_end = .;
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
}
uboot_end_data = .;
*(.got)
}
. =.;
- __u_boot_cmd_start =.;
- .u_boot_cmd : {
- *(.u_boot_cmd)
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
}
- __u_boot_cmd_end =.;
. = ALIGN (4);
.rel.dyn : {
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
#include <ide.h>
#include <pci.h>
-extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
int cpci_hd_type;
int ata_device(int dev)
#include <common.h>
#include <command.h>
+#include <serial.h>
+#include <linux/compiler.h>
+
#include "../../Marvell/include/memory.h"
#include "serial.h"
DECLARE_GLOBAL_DATA_PTR;
-int serial_init (void)
+static int cpci750_serial_init(void)
{
mpsc_init (gd->baudrate);
return (0);
}
-void serial_putc (const char c)
+static void cpci750_serial_putc(const char c)
{
if (c == '\n')
mpsc_putchar ('\r');
mpsc_putchar (c);
}
-int serial_getc (void)
+static int cpci750_serial_getc(void)
{
return mpsc_getchar ();
}
-int serial_tstc (void)
+static int cpci750_serial_tstc(void)
{
return mpsc_test_char ();
}
-void serial_setbrg (void)
+static void cpci750_serial_setbrg(void)
{
galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
}
+static struct serial_device cpci750_serial_drv = {
+ .name = "cpci750_serial",
+ .start = cpci750_serial_init,
+ .stop = NULL,
+ .setbrg = cpci750_serial_setbrg,
+ .putc = cpci750_serial_putc,
+ .puts = default_serial_puts,
+ .getc = cpci750_serial_getc,
+ .tstc = cpci750_serial_tstc,
+};
+
+void cpci750_serial_initialize(void)
+{
+ serial_register(&cpci750_serial_drv);
+}
-void serial_puts (const char *s)
+__weak struct serial_device *default_serial_console(void)
{
- while (*s) {
- serial_putc (*s++);
- }
+ return &cpci750_serial_drv;
}
#if defined(CONFIG_CMD_KGDB)
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
#if defined(CONFIG_PRAM)
#include <environment.h>
-extern env_t *env_ptr;
int do_painit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
#include <common.h>
#include <command.h>
#include <galileo/memory.h>
+#include <serial.h>
+#include <linux/compiler.h>
#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
#include <ns16550.h>
#ifdef CONFIG_MPSC
-int serial_init (void)
+static int evb64260_serial_init(void)
{
#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
return (0);
}
-void
-serial_putc(const char c)
+static void evb64260_serial_putc(const char c)
{
if (c == '\n')
mpsc_putchar('\r');
mpsc_putchar(c);
}
-int
-serial_getc(void)
+static int evb64260_serial_getc(void)
{
return mpsc_getchar();
}
-int
-serial_tstc(void)
+static int evb64260_serial_tstc(void)
{
return mpsc_test_char();
}
-void
-serial_setbrg (void)
+static void evb64260_serial_setbrg(void)
{
galbrg_set_baudrate(CONFIG_MPSC_PORT, gd->baudrate);
}
#else /* ! CONFIG_MPSC */
-int serial_init (void)
+static int evb64260_serial_init(void)
{
int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
return (0);
}
-void
-serial_putc(const char c)
+static void evb64260_serial_putc(const char c)
{
if (c == '\n')
NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
}
-int
-serial_getc(void)
+static int evb64260_serial_getc(void)
{
return NS16550_getc(COM_PORTS[CONFIG_SYS_DUART_CHAN]);
}
-int
-serial_tstc(void)
+static int evb64260_serial_tstc(void)
{
return NS16550_tstc(COM_PORTS[CONFIG_SYS_DUART_CHAN]);
}
-void
-serial_setbrg (void)
+static void evb64260_serial_setbrg(void)
{
int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
#endif /* CONFIG_MPSC */
-void
-serial_puts (const char *s)
+static struct serial_device evb64260_serial_drv = {
+ .name = "evb64260_serial",
+ .start = evb64260_serial_init,
+ .stop = NULL,
+ .setbrg = evb64260_serial_setbrg,
+ .putc = evb64260_serial_putc,
+ .puts = default_serial_puts,
+ .getc = evb64260_serial_getc,
+ .tstc = evb64260_serial_tstc,
+};
+
+void evb64260_serial_initialize(void)
+{
+ serial_register(&evb64260_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
{
- while (*s) {
- serial_putc (*s++);
- }
+ return &evb64260_serial_drv;
}
#if defined(CONFIG_CMD_KGDB)
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
{
arch/m68k/cpu/mcf52x2/start.o (.text*)
+ . = DEFINED(env_offset) ? env_offset : .;
+ common/env_embedded.o (.text*)
+
*(.text*)
}
_etext = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
/* COSR */
str r1, [r0, #0x1c]
- /* RedBoot sets 0x1ff, 7, 3, 5, 1, 3, 0 */
-/* REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/
+ /* RedBoot sets 0x3f, 7, 7, 3, 5, 1, 3, 0 */
+/* REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/
/* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */
/* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/
}
. = ALIGN(4);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
static void clock_1GHz(void)
{
int ret;
- u32 ref_clk = CONFIG_SYS_MX5_HCLK;
+ u32 ref_clk = MXC_HCLK;
/*
* After increasing voltage to 1.25V, we can switch
* CPU clock to 1GHz and DDR to 400MHz safely
--- /dev/null
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := mx6qsabreauto.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+# Copyright (C) 2012 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not write to the Free Software
+# Foundation Inc. 51 Franklin Street Fifth Floor Boston,
+# MA 02110-1301 USA
+#
+# Refer docs/README.imxmage for more details about how-to configure
+# and create imximage boot image
+#
+# The syntax is taken as close as possible with the kwbimage
+
+# image version
+
+IMAGE_VERSION 2
+
+# Boot Device : one of
+# spi, sd (the board has no nand neither onenand)
+
+BOOT_FROM sd
+
+# Device Configuration Data (DCD)
+#
+# Each entry must have the format:
+# Addr-type Address Value
+#
+# where:
+# Addr-type register length (1,2 or 4 bytes)
+# Address absolute address of the register
+# value value to be stored in the register
+DATA 4 0x020e05a8 0x00000028
+DATA 4 0x020e05b0 0x00000028
+DATA 4 0x020e0524 0x00000028
+DATA 4 0x020e051c 0x00000028
+
+DATA 4 0x020e0518 0x00000028
+DATA 4 0x020e050c 0x00000028
+DATA 4 0x020e05b8 0x00000028
+DATA 4 0x020e05c0 0x00000028
+
+DATA 4 0x020e05ac 0x00000028
+DATA 4 0x020e05b4 0x00000028
+DATA 4 0x020e0528 0x00000028
+DATA 4 0x020e0520 0x00000028
+
+DATA 4 0x020e0514 0x00000028
+DATA 4 0x020e0510 0x00000028
+DATA 4 0x020e05bc 0x00000028
+DATA 4 0x020e05c4 0x00000028
+
+DATA 4 0x020e056c 0x00000030
+DATA 4 0x020e0578 0x00000030
+DATA 4 0x020e0588 0x00000030
+DATA 4 0x020e0594 0x00000030
+
+DATA 4 0x020e057c 0x00000030
+DATA 4 0x020e0590 0x00000030
+DATA 4 0x020e0598 0x00000030
+DATA 4 0x020e058c 0x00000000
+
+DATA 4 0x020e059c 0x00003030
+DATA 4 0x020e05a0 0x00003030
+DATA 4 0x020e0784 0x00000028
+DATA 4 0x020e0788 0x00000028
+
+DATA 4 0x020e0794 0x00000028
+DATA 4 0x020e079c 0x00000028
+DATA 4 0x020e07a0 0x00000028
+DATA 4 0x020e07a4 0x00000028
+
+DATA 4 0x020e07a8 0x00000028
+DATA 4 0x020e0748 0x00000028
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e0750 0x00020000
+
+DATA 4 0x020e0758 0x00000000
+DATA 4 0x020e0774 0x00020000
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0798 0x000C0000
+
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+
+DATA 4 0x021b0018 0x00001740
+
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b000c 0x8A8F7975
+DATA 4 0x021b0010 0xFF538E64
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b002c 0x000026D2
+
+DATA 4 0x021b0030 0x008F0E21
+DATA 4 0x021b0008 0x09444040
+DATA 4 0x021b0004 0x00020036
+DATA 4 0x021b0040 0x00000047
+DATA 4 0x021b0000 0x841A0000
+
+DATA 4 0x021b001c 0x04088032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00428031
+DATA 4 0x021b001c 0x09408030
+
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0800 0xA1380003
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00000007
+DATA 4 0x021b4818 0x00000007
+
+# Calibration values based on ARD and 528MHz
+DATA 4 0x021b083c 0x434B0358
+DATA 4 0x021b0840 0x033D033C
+DATA 4 0x021b483c 0x03520362
+DATA 4 0x021b4840 0x03480318
+DATA 4 0x021b0848 0x41383A3C
+DATA 4 0x021b4848 0x3F3C374A
+DATA 4 0x021b0850 0x42434444
+DATA 4 0x021b4850 0x4932473A
+
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+
+DATA 4 0x021b480c 0x001F001F
+DATA 4 0x021b4810 0x001F001F
+
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b0004 0x00025576
+
+DATA 4 0x021b001c 0x00000000
+
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC00
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
--- /dev/null
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6x_pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+iomux_v3_cfg_t uart4_pads[] = {
+ MX6Q_PAD_KEY_COL0__UART4_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6Q_PAD_KEY_ROW0__UART4_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t enet_pads[] = {
+ MX6Q_PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+}
+
+iomux_v3_cfg_t usdhc3_pads[] = {
+ MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC3_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ gpio_direction_input(IMX_GPIO_NR(6, 15));
+ return !gpio_get_value(IMX_GPIO_NR(6, 15));
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+ unsigned short val;
+
+ /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+ val &= 0xffe3;
+ val |= 0x18;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+ /* introduce tx clock delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+ val |= 0x0100;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ mx6_rgmii_rework(phydev);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+
+ setup_iomux_enet();
+
+ ret = cpu_eth_init(bis);
+ if (ret)
+ printf("FEC MXC: %s:failed\n", __func__);
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ return 0x63000;
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: MX6Q-Sabreauto\n");
+
+ return 0;
+}
--- /dev/null
+#
+# Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
+#
+# (C) Copyright 2011 Freescale Semiconductor, Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := mx6qsabresd.o
+
+SRCS := $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6x_pins.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+#include <miiphy.h>
+#include <netdev.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
+ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
+ PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
+ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
+
+ return 0;
+}
+
+iomux_v3_cfg_t uart1_pads[] = {
+ MX6Q_PAD_CSI0_DAT10__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+ MX6Q_PAD_CSI0_DAT11__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t enet_pads[] = {
+ MX6Q_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ /* AR8031 PHY Reset */
+ MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+static void setup_iomux_enet(void)
+{
+ imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+
+ /* Reset AR8031 PHY */
+ gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
+ udelay(500);
+ gpio_set_value(IMX_GPIO_NR(1, 25), 1);
+}
+
+iomux_v3_cfg_t usdhc3_pads[] = {
+ MX6Q_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+ MX6Q_PAD_NANDF_D0__GPIO_2_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+static void setup_iomux_uart(void)
+{
+ imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
+}
+
+#ifdef CONFIG_FSL_ESDHC
+struct fsl_esdhc_cfg usdhc_cfg[1] = {
+ {USDHC3_BASE_ADDR},
+};
+
+int board_mmc_getcd(struct mmc *mmc)
+{
+ gpio_direction_input(IMX_GPIO_NR(2, 0));
+ return !gpio_get_value(IMX_GPIO_NR(2, 0));
+}
+
+int board_mmc_init(bd_t *bis)
+{
+ imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+
+ return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
+}
+#endif
+
+int mx6_rgmii_rework(struct phy_device *phydev)
+{
+ unsigned short val;
+
+ /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
+
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
+ val &= 0xffe3;
+ val |= 0x18;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
+
+ /* introduce tx clock delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
+ val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
+ val |= 0x0100;
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
+
+ return 0;
+}
+
+int board_phy_config(struct phy_device *phydev)
+{
+ mx6_rgmii_rework(phydev);
+
+ if (phydev->drv->config)
+ phydev->drv->config(phydev);
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bis)
+{
+ int ret;
+
+ setup_iomux_enet();
+
+ ret = cpu_eth_init(bis);
+ if (ret)
+ printf("FEC MXC: %s:failed\n", __func__);
+
+ return 0;
+}
+
+u32 get_board_rev(void)
+{
+ return 0x63000;
+}
+
+int board_early_init_f(void)
+{
+ setup_iomux_uart();
+
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+
+ return 0;
+}
+
+int checkboard(void)
+{
+ puts("Board: MX6Q-SabreSD\n");
+
+ return 0;
+}
/* CMD Table */
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
+
. = ALIGN(4);
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
.data :
{
/* CMD Table */
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
+
. = ALIGN(4);
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
.data :
{
/* CMD Table */
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
+
. = ALIGN(4);
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
.data :
{
/* CMD Table */
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
+
. = ALIGN(4);
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
.data :
{
/* CMD Table */
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
+
. = ALIGN(4);
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
.data :
{
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
+++ /dev/null
-/* Module for handling DALLAS DS2438, smart battery monitor
- Chip can store up to 40 bytes of user data in EEPROM,
- perform temp, voltage and current measurements.
- Chip also contains a unique serial number.
-
- Always read/write LSb first
-
- For documentaion, see data sheet for DS2438, 2438.pdf
-
- By Thomas.Lange@corelatus.com 001025
-
- Copyright (C) 2000-2005 Corelatus AB */
-
-/* This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/au1x00.h>
-#include <asm/io.h>
-#include "ee_dev.h"
-#include "ee_access.h"
-
-/* static int Debug = 1; */
-#undef E_DEBUG
-#define E_DEBUG(fmt,args...) /* */
-/* #define E_DEBUG(fmt,args...) printk("EEA:"fmt,##args); */
-
-/* We dont have kernel functions */
-#define printk printf
-#define KERN_DEBUG
-#define KERN_ERR
-#define EIO 1
-
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-
-/* lookup table ripped from DS app note 17, understanding and using cyclic redundancy checks... */
-
-static u8 crc_lookup[256] = {
- 0, 94, 188, 226, 97, 63, 221, 131,
- 194, 156, 126, 32, 163, 253, 31, 65,
- 157, 195, 33, 127, 252, 162, 64, 30,
- 95, 1, 227, 189, 62, 96, 130, 220,
- 35, 125, 159, 193, 66, 28, 254, 160,
- 225, 191, 93, 3, 128, 222, 60, 98,
- 190, 224, 2, 92, 223, 129, 99, 61,
- 124, 34, 192, 158, 29, 67, 161, 255,
- 70, 24, 250, 164, 39, 121, 155, 197,
- 132, 218, 56, 102, 229, 187, 89, 7,
- 219, 133, 103, 57, 186, 228, 6, 88,
- 25, 71, 165, 251, 120, 38, 196, 154,
- 101, 59, 217, 135, 4, 90, 184, 230,
- 167, 249, 27, 69, 198, 152, 122, 36,
- 248, 166, 68, 26, 153, 199, 37, 123,
- 58, 100, 134, 216, 91, 5, 231, 185,
- 140, 210, 48, 110, 237, 179, 81, 15,
- 78, 16, 242, 172, 47, 113, 147, 205,
- 17, 79, 173, 243, 112, 46, 204, 146,
- 211, 141, 111, 49, 178, 236, 14, 80,
- 175, 241, 19, 77, 206, 144, 114, 44,
- 109, 51, 209, 143, 12, 82, 176, 238,
- 50, 108, 142, 208, 83, 13, 239, 177,
- 240, 174, 76, 18, 145, 207, 45, 115,
- 202, 148, 118, 40, 171, 245, 23, 73,
- 8, 86, 180, 234, 105, 55, 213, 139,
- 87, 9, 235, 181, 54, 104, 138, 212,
- 149, 203, 41, 119, 244, 170, 72, 22,
- 233, 183, 85, 11, 136, 214, 52, 106,
- 43, 117, 151, 201, 74, 20, 246, 168,
- 116, 42, 200, 150, 21, 75, 169, 247,
- 182, 232, 10, 84, 215, 137, 107, 53
-};
-
-static void
-write_gpio_data(int value ){
- if(value){
- /* Tristate */
- gpio_tristate(GPIO_EEDQ);
- }
- else{
- /* Drive 0 */
- gpio_clear(GPIO_EEDQ);
- }
-}
-
-static u8 make_new_crc( u8 Old_crc, u8 New_value ){
- /* Compute a new checksum with new byte, using previous checksum as input
- See DS app note 17, understanding and using cyclic redundancy checks...
- Also see DS2438, page 11 */
- return( crc_lookup[Old_crc ^ New_value ]);
-}
-
-int ee_crc_ok( u8 *Buffer, int Len, u8 Crc ){
- /* Check if the checksum for this buffer is correct */
- u8 Curr_crc=0;
- int i;
- u8 *Curr_byte = Buffer;
-
- for(i=0;i<Len;i++){
- Curr_crc = make_new_crc( Curr_crc, *Curr_byte);
- Curr_byte++;
- }
- E_DEBUG("Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
-
- if(Curr_crc == Crc){
- /* Good */
- return(TRUE);
- }
- printk(KERN_ERR"EE checksum error, Calculated CRC = 0x%x, read = 0x%x\n", Curr_crc, Crc);
- return(FALSE);
-}
-
-static void
-set_idle(void){
- /* Send idle and keep start time
- Continous 1 is idle */
- WRITE_PORT(1);
-}
-
-
-static int
-do_cpu_reset(void){
- /* Release reset and verify that chip responds with presence pulse */
- int Retries=0;
- while(Retries<15){
- udelay(RESET_LOW_TIME);
-
- /* Send reset */
- WRITE_PORT(0);
- udelay(RESET_LOW_TIME);
-
- /* Release reset */
- WRITE_PORT(1);
-
- /* Wait for EEPROM to drive output */
- udelay(PRESENCE_TIMEOUT);
- if(!READ_PORT){
- /* Ok, EEPROM is driving a 0 */
- E_DEBUG("Presence detected\n");
- if(Retries){
- E_DEBUG("Retries %d\n",Retries);
- }
- /* Make sure chip releases pin */
- udelay(PRESENCE_LOW_TIME);
- return 0;
- }
- Retries++;
- }
-
- printk(KERN_ERR"eeprom did not respond when releasing reset\n");
-
- /* Make sure chip releases pin */
- udelay(PRESENCE_LOW_TIME);
-
- /* Set to idle again */
- set_idle();
-
- return(-EIO);
-}
-
-static u8
-read_cpu_byte(void){
- /* Read a single byte from EEPROM
- Read LSb first */
- int i;
- int Value;
- u8 Result=0;
- u32 Flags;
-
- E_DEBUG("Reading byte\n");
-
- for(i=0;i<8;i++){
- /* Small delay between pulses */
- udelay(1);
-
-#ifdef __KERNEL__
- /* Disable irq */
- save_flags(Flags);
- cli();
-#endif
-
- /* Pull down pin short time to start read
- See page 26 in data sheet */
-
- WRITE_PORT(0);
- udelay(READ_LOW);
- WRITE_PORT(1);
-
- /* Wait for chip to drive pin */
- udelay(READ_TIMEOUT);
-
- Value = READ_PORT;
- if(Value)
- Value=1;
-
-#ifdef __KERNEL__
- /* Enable irq */
- restore_flags(Flags);
-#endif
-
- /* Wait for chip to release pin */
- udelay(TOTAL_READ_LOW-READ_TIMEOUT);
-
- /* LSb first */
- Result|=Value<<i;
- /* E_DEBUG("Read %d\n",Value); */
-
- }
-
- E_DEBUG("Read byte 0x%x\n",Result);
-
- return(Result);
-}
-
-static void
-write_cpu_byte(u8 Byte){
- /* Write a single byte to EEPROM
- Write LSb first */
- int i;
- int Value;
- u32 Flags;
-
- E_DEBUG("Writing byte 0x%x\n",Byte);
-
- for(i=0;i<8;i++){
- /* Small delay between pulses */
- udelay(1);
- Value = Byte&1;
-
-#ifdef __KERNEL__
- /* Disable irq */
- save_flags(Flags);
- cli();
-#endif
-
- /* Pull down pin short time for a 1, long time for a 0
- See page 26 in data sheet */
-
- WRITE_PORT(0);
- if(Value){
- /* Write a 1 */
- udelay(WRITE_1_LOW);
- }
- else{
- /* Write a 0 */
- udelay(WRITE_0_LOW);
- }
-
- WRITE_PORT(1);
-
-#ifdef __KERNEL__
- /* Enable irq */
- restore_flags(Flags);
-#endif
-
- if(Value)
- /* Wait for chip to read the 1 */
- udelay(TOTAL_WRITE_LOW-WRITE_1_LOW);
-
- /* E_DEBUG("Wrote %d\n",Value); */
- Byte>>=1;
- }
-}
-
-int ee_do_cpu_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip ){
- /* Execute this command string, including
- giving reset and setting to idle after command
- if Rx_len is set, we read out data from EEPROM */
- int i;
-
- E_DEBUG("Command, Tx_len %d, Rx_len %d\n", Tx_len, Rx_len );
-
- if(do_cpu_reset()){
- /* Failed! */
- return(-EIO);
- }
-
- if(Send_skip)
- /* Always send SKIP_ROM first to tell chip we are sending a command,
- except when we read out rom data for chip */
- write_cpu_byte(SKIP_ROM);
-
- /* Always have Tx data */
- for(i=0;i<Tx_len;i++){
- write_cpu_byte(Tx[i]);
- }
-
- if(Rx_len){
- for(i=0;i<Rx_len;i++){
- Rx[i]=read_cpu_byte();
- }
- }
-
- set_idle();
-
- E_DEBUG("Command done\n");
-
- return(0);
-}
-
-int ee_init_cpu_data(void){
- int i;
- u8 Tx[10];
-
- /* Leave it floting since altera is driving the same pin */
- set_idle();
-
- /* Copy all User EEPROM data to scratchpad */
- for(i=0;i<USER_PAGES;i++){
- Tx[0]=RECALL_MEMORY;
- Tx[1]=EE_USER_PAGE_0+i;
- if(ee_do_cpu_command(Tx,2,NULL,0,TRUE)) return(-EIO);
- }
-
- /* Make sure chip doesnt store measurements in NVRAM */
- Tx[0]=WRITE_SCRATCHPAD;
- Tx[1]=0; /* Page */
- Tx[2]=9;
- if(ee_do_cpu_command(Tx,3,NULL,0,TRUE)) return(-EIO);
-
- Tx[0]=COPY_SCRATCHPAD;
- if(ee_do_cpu_command(Tx,2,NULL,0,TRUE)) return(-EIO);
-
- for(i=0;i<10;i++){
- udelay(1000);
- }
-
- return(0);
-}
+++ /dev/null
-/* By Thomas.Lange@Corelatus.com 001025 */
-
-/* Definitions for EEPROM/VOLT METER DS2438 */
-/* Copyright (C) 2000-2005 Corelatus AB */
-
-#ifndef INCeeaccessh
-#define INCeeaccessh
-
-#include <asm/types.h>
-#include "ee_dev.h"
-
-int ee_do_cpu_command( u8 *Tx, int Tx_len, u8 *Rx, int Rx_len, int Send_skip );
-int ee_init_cpu_data(void);
-
-int ee_crc_ok( u8 *Buffer, int Len, u8 Crc );
-
-/* Defs for altera reg */
-#define EE_WRITE_SHIFT 8 /* bits to shift left */
-#define EE_READ_SHIFT 16 /* bits to shift left */
-#define EE_DONE 0x80000000
-#define EE_BUSY 0x40000000
-#define EE_ERROR 0x20000000
-
-/* Commands */
-#define EE_CMD_NOP 0
-#define EE_CMD_INIT_RES 1
-#define EE_CMD_WR_BYTE 2
-#define EE_CMD_RD_BYTE 3
-
-#endif /* INCeeaccessh */
+++ /dev/null
-/* By Thomas.Lange@Corelatus.com 001025 */
-/* Definitions for EEPROM/VOLT METER DS2438 */
-/* Copyright (C) 2000-2005 Corelatus AB */
-
-/* This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef INCeedevh
-#define INCeedevh
-
-#define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args)
-
-/* MIPS */
-#define WRITE_PORT(Value) write_gpio_data(Value)
-
-#define READ_PORT (gpio_read()&GPIO_EEDQ)
-
-/* 64 bytes chip */
-#define EE_CHIP_SIZE 64
-
-/* Board with new current resistor */
-#define EE_GTH_0304 1
-
-/* new dsp and 64 MB SDRAM */
-#define EE_DSP_64 0x10
-
-/* microsecs */
-/* Pull line down at least this long for reset pulse */
-#define RESET_LOW_TIME 490
-
-/* Read presence pulse after we release reset pulse */
-#define PRESENCE_TIMEOUT 100
-#define PRESENCE_LOW_TIME 200
-
-#define WRITE_0_LOW 60
-#define WRITE_1_LOW 1
-#define TOTAL_WRITE_LOW 60
-
-#define READ_LOW 1
-#define READ_TIMEOUT 10
-#define TOTAL_READ_LOW 70
-
-/* Rom function commands */
-#define READ_ROM 0x33
-#define MATCH_ROM 0x55
-#define SKIP_ROM 0xCC
-#define SEARCH_ROM 0xF0
-
-
-/* Memory_command_function */
-#define WRITE_SCRATCHPAD 0x4E
-#define READ_SCRATCHPAD 0xBE
-#define COPY_SCRATCHPAD 0x48
-#define RECALL_MEMORY 0xB8
-#define CONVERT_TEMP 0x44
-#define CONVERT_VOLTAGE 0xB4
-
-/* Chip is divided in 8 pages, 8 bytes each */
-
-#define EE_PAGE_SIZE 8
-
-/* All chip data we want are in page 0 */
-
-/* Bytes in page 0 */
-#define EE_P0_STATUS 0
-#define EE_P0_TEMP_LSB 1
-#define EE_P0_TEMP_MSB 2
-#define EE_P0_VOLT_LSB 3
-#define EE_P0_VOLT_MSB 4
-#define EE_P0_CURRENT_LSB 5
-#define EE_P0_CURRENT_MSB 6
-
-
-/* 40 byte user data is located at page 3-7 */
-#define EE_USER_PAGE_0 3
-#define USER_PAGES 5
-
-/* Layout of gth user pages usage */
-/* Bytes 0-16 ethernet addr in ascii ( len 17 ) */
-
-#define EE_ETHERNET_OFFSET 0
-
-#endif /* INCeedevh */
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Thomas.Lange@corelatus.se
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/au1x00.h>
-#include <asm/addrspace.h>
-#include <asm/mipsregs.h>
-#include <asm/io.h>
-#include <watchdog.h>
-
-#include "ee_access.h"
-
-static int wdi_status = 0;
-
-#define SDRAM_SIZE ((64*1024*1024)-(12*4096))
-
-
-#define SERIAL_LOG_BUFFER CKSEG1ADDR(SDRAM_SIZE + (8*4096))
-
-void inline log_serial_char(char c){
- char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER;
- int serial_log_offset;
- u32 *serial_log_offsetp = (u32*)SERIAL_LOG_BUFFER;
-
- serial_log_offset = *serial_log_offsetp;
-
- *(serial_log_buffer + serial_log_offset) = c;
-
- serial_log_offset++;
-
- if(serial_log_offset >= 4096){
- serial_log_offset = 4;
- }
- *serial_log_offsetp = serial_log_offset;
-}
-
-void init_log_serial(void){
- char *serial_log_buffer = (char*)SERIAL_LOG_BUFFER;
- u32 *serial_log_offsetp = (u32*)SERIAL_LOG_BUFFER;
-
- /* Copy buffer from last run */
- memcpy(serial_log_buffer + 4096,
- serial_log_buffer,
- 4096);
-
- memset(serial_log_buffer, 0, 4096);
-
- *serial_log_offsetp = 4;
-}
-
-
-void hw_watchdog_reset(void){
- volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET;
- volatile u32 *sys_outputclear = (volatile u32*)SYS_OUTPUTCLR;
- if(wdi_status){
- *sys_outputset = GPIO_CPU_LED|GPIO_WDI;
- wdi_status = 0;
- }
- else{
- *sys_outputclear = GPIO_CPU_LED|GPIO_WDI;
- wdi_status = 1;
- }
-}
-
-phys_size_t initdram(int board_type)
-{
- /* Sdram is setup by assembler code */
- /* If memory could be changed, we should return the true value here */
-
- WATCHDOG_RESET();
-
- return (SDRAM_SIZE);
-}
-
-/* In arch/mips/cpu/cpu.c */
-void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 );
-
-void set_ledcard(u32 value){
- /* Clock 24 bits to led card */
- int i;
- volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET;
- volatile u32 *sys_outputclr = (volatile u32*)SYS_OUTPUTCLR;
-
- /* Start with known values */
- *sys_outputclr = GPIO_LEDCLK|GPIO_LEDD;
-
- for(i=0;i<24;i++){
- if(value&0x00800000){
- *sys_outputset = GPIO_LEDD;
- }
- else{
- *sys_outputclr = GPIO_LEDD;
- }
- udelay(1);
- *sys_outputset = GPIO_LEDCLK;
- udelay(1);
- *sys_outputclr = GPIO_LEDCLK;
- udelay(1);
-
- value<<=1;
- }
- /* Data is enable output */
- *sys_outputset = GPIO_LEDD;
-}
-
-int checkboard (void)
-{
- volatile u32 *sys_counter = (volatile u32*)SYS_COUNTER_CNTRL;
- volatile u32 *sys_outputset = (volatile u32*)SYS_OUTPUTSET;
- volatile u32 *sys_outputclr = (volatile u32*)SYS_OUTPUTCLR;
- u32 proc_id;
-
- WATCHDOG_RESET();
-
- *sys_counter = 0x100; /* Enable 32 kHz oscillator for RTC/TOY */
-
- proc_id = read_c0_prid();
-
- switch (proc_id >> 24) {
- case 0:
- puts ("Board: GTH2\n");
- printf ("CPU: Au1000 500 MHz, id: 0x%02x, rev: 0x%02x\n",
- (proc_id >> 8) & 0xFF, proc_id & 0xFF);
- break;
- default:
- printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id);
- }
-
- set_io_port_base(0);
-
-#ifdef CONFIG_IDE_PCMCIA
- /* PCMCIA is on a 36 bit physical address.
- We need to map it into a 32 bit addresses */
- write_one_tlb(20, /* index */
- 0x01ffe000, /* Pagemask, 16 MB pages */
- CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
- 0x3C000017, /* Lo0 */
- 0x3C200017); /* Lo1 */
-
- write_one_tlb(21, /* index */
- 0x01ffe000, /* Pagemask, 16 MB pages */
- CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
- 0x3D000017, /* Lo0 */
- 0x3D200017); /* Lo1 */
-
- write_one_tlb(22, /* index */
- 0x01ffe000, /* Pagemask, 16 MB pages */
- CONFIG_SYS_PCMCIA_MEM_ADDR, /* Hi */
- 0x3E000017, /* Lo0 */
- 0x3E200017); /* Lo1 */
-
-#endif /* CONFIG_IDE_PCMCIA */
-
- /* Wait for GPIO ports to become stable */
- udelay(5000); /* FIXME */
-
- /* Release reset of ethernet PHY chips */
- /* Always do this, because linux does not know about it */
- *sys_outputset = GPIO_ERESET;
-
- /* Kill FPGA:s */
- *sys_outputclr = GPIO_CACONFIG|GPIO_DPACONFIG;
- udelay(2);
- *sys_outputset = GPIO_CACONFIG|GPIO_DPACONFIG;
-
- /* Turn front led yellow */
- set_ledcard(0x00100000);
-
- return 0;
-}
-
-#define POWER_OFFSET 0xF0000
-#define SW_WATCHDOG_REASON 13
-
-#define BOOTDATA_OFFSET 0xF8000
-#define MAX_ATTEMPTS 5
-
-#define FAILSAFE_BOOT 1
-#define SYSTEM_BOOT 2
-#define SYSTEM2_BOOT 3
-
-#define WRITE_FLASH16(a, d) \
-do \
-{ \
- *((volatile u16 *) (a)) = (d);\
- } while(0)
-
-static void write_bootdata (volatile u16 * addr, u8 System, u8 Count)
-{
- u16 data;
- volatile u16 *flash = (u16 *) (CONFIG_SYS_FLASH_BASE);
-
- switch(System){
- case FAILSAFE_BOOT:
- printf ("Setting failsafe boot in flash\n");
- break;
- case SYSTEM_BOOT:
- printf ("Setting system boot in flash\n");
- break;
- case SYSTEM2_BOOT:
- printf ("Setting system2 boot in flash\n");
- break;
- default:
- printf ("Invalid system data %u, setting failsafe\n", System);
- System = FAILSAFE_BOOT;
- }
-
- if ((Count < 1) | (Count > MAX_ATTEMPTS)) {
- printf ("Invalid boot count %u, setting 1\n", Count);
- Count = 1;
- }
-
- printf ("Boot attempt %d\n", Count);
-
- data = (System << 8) | Count;
- /* AMD 16 bit */
- WRITE_FLASH16 (&flash[0x555], 0xAAAA);
- WRITE_FLASH16 (&flash[0x2AA], 0x5555);
- WRITE_FLASH16 (&flash[0x555], 0xA0A0);
-
- WRITE_FLASH16 (addr, data);
-}
-
-static int random_system(void){
- /* EEPROM read failed. Just try to choose one
- system release and hope it works */
-
- /* FIXME */
- return(SYSTEM_BOOT);
-}
-
-static int switch_system(int old_system){
- u8 Rx[10];
- u8 Tx[5];
- int valid_release;
-
- if(old_system==FAILSAFE_BOOT){
- /* Find out which system release to use */
-
- /* Copy from nvram to scratchpad */
- Tx[0] = RECALL_MEMORY;
- Tx[1] = 7; /* Page */
- if (ee_do_cpu_command (Tx, 2, NULL, 0, 1)) {
- printf ("EE user page 7 recall failed\n");
- return (random_system());
- }
-
- Tx[0] = READ_SCRATCHPAD;
- if (ee_do_cpu_command (Tx, 2, Rx, 9, 1)) {
- printf ("EE user page 7 read failed\n");
- return (random_system());
- }
- /* Crc in 9:th byte */
- if (!ee_crc_ok (Rx, 8, *(Rx + 8))) {
- printf ("EE read failed, page 7. CRC error\n");
- return (random_system());
- }
-
- valid_release = Rx[7];
- if((valid_release==0xFF)|
- ((valid_release&1) == 0)){
- return(SYSTEM_BOOT);
- }
- else{
- return(SYSTEM2_BOOT);
- }
- }
- else{
- return(FAILSAFE_BOOT);
- }
-}
-
-static void check_boot_tries (void)
-{
- /* Count the number of boot attemps
- switch system if too many */
-
- int i;
- volatile u16 *addr;
- volatile u16 data;
- u8 system = FAILSAFE_BOOT;
- u8 count;
-
- addr = (u16 *) (CONFIG_SYS_FLASH_BASE + BOOTDATA_OFFSET);
-
- if (*addr == 0xFFFF) {
- printf ("*** No bootdata exists. ***\n");
- write_bootdata (addr, FAILSAFE_BOOT, 1);
- } else {
- /* Search for latest written bootdata */
- i = 0;
- while ((*(addr + 1) != 0xFFFF) & (i < 8000)) {
- addr++;
- i++;
- }
- if (i >= 8000) {
- /* Whoa, dont write any more */
- printf ("*** No bootdata found. Not updating flash***\n");
- } else {
- /* See how many times we have tried to boot real system */
- data = *addr;
- system = data >> 8;
- count = data & 0xFF;
- if ((system != SYSTEM_BOOT) &
- (system != SYSTEM2_BOOT) &
- (system != FAILSAFE_BOOT)) {
- printf ("*** Wrong system %d\n", system);
- system = FAILSAFE_BOOT;
- count = 1;
- } else {
- switch (count) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- /* Try same system again if needed */
- count++;
- break;
-
- case 5:
- /* Switch system and reset tries */
- count = 1;
- system = switch_system(system);
- printf ("***Too many boot attempts, switching system***\n");
- break;
- default:
- /* Switch system, start over and hope it works */
- printf ("***Unexpected data on addr 0x%x, %u***\n",
- (u32) addr, data);
- count = 1;
- system = switch_system(system);
- }
- }
- write_bootdata (addr + 1, system, count);
- }
- }
- switch(system){
- case FAILSAFE_BOOT:
- printf ("Booting failsafe system\n");
- setenv ("bootargs", "panic=1 root=/dev/hda7");
- setenv ("bootcmd", "ide reset;disk 0x81000000 0:5;run addmisc;bootm");
- break;
-
- case SYSTEM_BOOT:
- printf ("Using normal system\n");
- setenv ("bootargs", "panic=1 root=/dev/hda4");
- setenv ("bootcmd", "ide reset;disk 0x81000000 0:2;run addmisc;bootm");
- break;
-
- case SYSTEM2_BOOT:
- printf ("Using normal system2\n");
- setenv ("bootargs", "panic=1 root=/dev/hda9");
- setenv ("bootcmd", "ide reset;disk 0x81000000 0:8;run addmisc;bootm");
- break;
- default:
- printf ("Invalid system %d\n", system);
- printf ("Hanging\n");
- while(1);
- }
-}
-
-int misc_init_r(void){
- u8 Rx[80];
- u8 Tx[5];
- int page;
- int read = 0;
-
- WATCHDOG_RESET();
-
- if (ee_init_cpu_data ()) {
- printf ("EEPROM init failed\n");
- return (0);
- }
-
- /* Check which release to boot */
- check_boot_tries ();
-
- /* Read the pages where ethernet address is stored */
-
- for (page = EE_USER_PAGE_0; page <= EE_USER_PAGE_0 + 2; page++) {
- /* Copy from nvram to scratchpad */
- Tx[0] = RECALL_MEMORY;
- Tx[1] = page;
- if (ee_do_cpu_command (Tx, 2, NULL, 0, 1)) {
- printf ("EE user page %d recall failed\n", page);
- return (0);
- }
-
- Tx[0] = READ_SCRATCHPAD;
- if (ee_do_cpu_command (Tx, 2, Rx + read, 9, 1)) {
- printf ("EE user page %d read failed\n", page);
- return (0);
- }
- /* Crc in 9:th byte */
- if (!ee_crc_ok (Rx + read, 8, *(Rx + read + 8))) {
- printf ("EE read failed, page %d. CRC error\n", page);
- return (0);
- }
- read += 8;
- }
-
- /* Add eos after eth addr */
- Rx[17] = 0;
-
- printf ("Ethernet addr read from eeprom: %s\n\n", Rx);
-
- if ((Rx[2] != ':') |
- (Rx[5] != ':') |
- (Rx[8] != ':') | (Rx[11] != ':') | (Rx[14] != ':')) {
- printf ("*** ethernet addr invalid, using default ***\n");
- } else {
- setenv ("ethaddr", (char *)Rx);
- }
- return (0);
-}
+++ /dev/null
-/* Memory sub-system initialization code */
-
-#include <config.h>
-#include <asm/regdef.h>
-#include <asm/au1x00.h>
-#include <asm/mipsregs.h>
-
-#define CP0_Config0 $16
-#define MEM_1MS ((CONFIG_SYS_MHZ) * 1000)
-#define GPIO_RJ1LY (1<<22)
-#define GPIO_CFRESET (1<<10)
-
- .text
- .set noreorder
- .set mips32
-
- .globl lowlevel_init
-lowlevel_init:
- /*
- * Step 2) Establish Status Register
- * (set BEV, clear ERL, clear EXL, clear IE)
- */
- li t1, 0x00400000
- mtc0 t1, CP0_STATUS
-
- /*
- * Step 3) Establish CP0 Config0
- * (set OD, set K0=3)
- */
- li t1, 0x00080003
- mtc0 t1, CP0_CONFIG
-
- /*
- * Step 4) Disable Watchpoint facilities
- */
- li t1, 0x00000000
- mtc0 t1, CP0_WATCHLO
- mtc0 t1, CP0_IWATCHLO
- /*
- * Step 5) Disable the performance counters
- */
- mtc0 zero, CP0_PERFORMANCE
- nop
-
- /*
- * Step 6) Establish EJTAG Debug register
- */
- mtc0 zero, CP0_DEBUG
- nop
-
- /*
- * Step 7) Establish Cause
- * (set IV bit)
- */
- li t1, 0x00800000
- mtc0 t1, CP0_CAUSE
-
- /* Establish Wired (and Random) */
- mtc0 zero, CP0_WIRED
- nop
-
- /* No workaround if running from ram */
- lui t0, 0xffc0
- lui t3, 0xbfc0
- and t1, ra, t0
- bne t1, t3, noCacheJump
- nop
-
- /*** From AMD YAMON ***/
- /*
- * Step 8) Initialize the caches
- */
- li t0, (16*1024)
- li t1, 32
- li t2, 0x80000000
- addu t3, t0, t2
-cacheloop:
- cache 0, 0(t2)
- cache 1, 0(t2)
- addu t2, t1
- bne t2, t3, cacheloop
- nop
-
- /* Save return address */
- move t3, ra
-
- /* Run from cacheable space now */
- bal cachehere
- nop
-cachehere:
- li t1, ~0x20000000 /* convert to KSEG0 */
- and t0, ra, t1
- addi t0, 5*4 /* 5 insns beyond cachehere */
- jr t0
- nop
-
- /* Restore return address */
- move ra, t3
-
- /*
- * Step 9) Initialize the TLB
- */
- li t0, 0 # index value
- li t1, 0x00000000 # entryhi value
- li t2, 32 # 32 entries
-
-tlbloop:
- /* Probe TLB for matching EntryHi */
- mtc0 t1, CP0_ENTRYHI
- tlbp
- nop
-
- /* Examine Index[P], 1=no matching entry */
- mfc0 t3, CP0_INDEX
- li t4, 0x80000000
- and t3, t4, t3
- addiu t1, t1, 1 # increment t1 (asid)
- beq zero, t3, tlbloop
- nop
-
- /* Initialize the TLB entry */
- mtc0 t0, CP0_INDEX
- mtc0 zero, CP0_ENTRYLO0
- mtc0 zero, CP0_ENTRYLO1
- mtc0 zero, CP0_PAGEMASK
- tlbwi
-
- /* Do it again */
- addiu t0, t0, 1
- bne t0, t2, tlbloop
- nop
-
- /* First setup pll:s to make serial work ok */
- /* We have a 12.5 MHz crystal */
- li t0, SYS_CPUPLL
- li t1, 0x28 /* CPU clock, 500 MHz */
- sw t1, 0(t0)
- sync
- nop
- nop
-
- /* wait 1mS for clocks to settle */
- li t1, MEM_1MS
-1: add t1, -1
- bne t1, zero, 1b
- nop
- /* Setup AUX PLL */
- li t0, SYS_AUXPLL
- li t1, 0
- sw t1, 0(t0) /* aux pll */
- sync
-
- /* Static memory controller */
- /* RCE0 - can not change while fetching, do so from icache */
- move t2, ra /* Store return address */
- bal getAddr
- nop
-
-getAddr:
- move t1, ra
- move ra, t2 /* Move return addess back */
-
- cache 0x14,0(t1)
- cache 0x14,32(t1)
- /*** /From YAMON ***/
-
-noCacheJump:
-
- /* Static memory controller */
-
- /* RCE0 AMD 29LV800 Flash */
- li t0, MEM_STCFG0
- li t1, 0x00000243
- sw t1, 0(t0)
-
- li t0, MEM_STTIME0
- li t1, 0x040181D7 /* FIXME */
- sw t1, 0(t0)
-
- li t0, MEM_STADDR0
- li t1, 0x11E03F80
- sw t1, 0(t0)
-
- /* RCE1 PCMCIA 250ns */
- li t0, MEM_STCFG1
- li t1, 0x00000002
- sw t1, 0(t0)
-
- li t0, MEM_STTIME1
- li t1, 0x280E3E07
- sw t1, 0(t0)
-
- li t0, MEM_STADDR1
- li t1, 0x10000000
- sw t1, 0(t0)
-
- /* RCE2 CP Altera */
- li t0, MEM_STCFG2
- li t1, 0x00000280 /* BE, EW */
- sw t1, 0(t0)
-
- li t0, MEM_STTIME2
- li t1, 0x0303000c
- sw t1, 0(t0)
-
- li t0, MEM_STADDR2
- li t1, 0x10c03f80 /* 1 MB */
- sw t1, 0(t0)
-
- /* RCE3 DP Altera */
- li t0, MEM_STCFG3
- li t1, 0x00000280 /* BE, EW */
- sw t1, 0(t0)
-
- li t0, MEM_STTIME3
- li t1, 0x0303000c
- sw t1, 0(t0)
-
- li t0, MEM_STADDR3
- li t1, 0x10e03f80 /* 1 MB */
- sw t1, 0(t0)
-
- sync
-
- /* Set peripherals to a known state */
- li t0, IC0_CFG0CLR
- li t1, 0xFFFFFFFF
- sw t1, 0(t0)
-
- li t0, IC0_CFG0CLR
- sw t1, 0(t0)
-
- li t0, IC0_CFG1CLR
- sw t1, 0(t0)
-
- li t0, IC0_CFG2CLR
- sw t1, 0(t0)
-
- li t0, IC0_SRCSET
- sw t1, 0(t0)
-
- li t0, IC0_ASSIGNSET
- sw t1, 0(t0)
-
- li t0, IC0_WAKECLR
- sw t1, 0(t0)
-
- li t0, IC0_RISINGCLR
- sw t1, 0(t0)
-
- li t0, IC0_FALLINGCLR
- sw t1, 0(t0)
-
- li t0, IC0_TESTBIT
- li t1, 0x00000000
- sw t1, 0(t0)
- sync
-
- li t0, IC1_CFG0CLR
- li t1, 0xFFFFFFFF
- sw t1, 0(t0)
-
- li t0, IC1_CFG0CLR
- sw t1, 0(t0)
-
- li t0, IC1_CFG1CLR
- sw t1, 0(t0)
-
- li t0, IC1_CFG2CLR
- sw t1, 0(t0)
-
- li t0, IC1_SRCSET
- sw t1, 0(t0)
-
- li t0, IC1_ASSIGNSET
- sw t1, 0(t0)
-
- li t0, IC1_WAKECLR
- sw t1, 0(t0)
-
- li t0, IC1_RISINGCLR
- sw t1, 0(t0)
-
- li t0, IC1_FALLINGCLR
- sw t1, 0(t0)
-
- li t0, IC1_TESTBIT
- li t1, 0x00000000
- sw t1, 0(t0)
- sync
-
- li t0, SYS_FREQCTRL0
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_FREQCTRL1
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_CLKSRC
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_PININPUTEN
- li t1, 0x00000000
- sw t1, 0(t0)
- sync
-
- li t0, 0xB1100100
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, 0xB1400100
- li t1, 0x00000000
- sw t1, 0(t0)
-
-
- li t0, SYS_WAKEMSK
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, SYS_WAKESRC
- li t1, 0x00000000
- sw t1, 0(t0)
-
- /* wait 1mS before setup */
- li t1, MEM_1MS
-1: add t1, -1
- bne t1, zero, 1b
- nop
-
-
-/* SDCS 0 SDRAM */
- li t0, MEM_SDMODE0
- li t1, 0x592CD1
- sw t1, 0(t0)
-
- li t0, MEM_SDMODE1
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, MEM_SDMODE2
- li t1, 0x00000000
- sw t1, 0(t0)
-
-/* 64 MB SDRAM at addr 0 */
- li t0, MEM_SDADDR0
- li t1, 0x001003F0
- sw t1, 0(t0)
-
-
- li t0, MEM_SDADDR1
- li t1, 0x00000000
- sw t1, 0(t0)
-
- li t0, MEM_SDADDR2
- li t1, 0x00000000
- sw t1, 0(t0)
-
- sync
-
- li t0, MEM_SDREFCFG
- li t1, 0x880007A1 /* Disable */
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDPRECMD
- sw zero, 0(t0)
- sync
-
- li t0, MEM_SDAUTOREF
- sw zero, 0(t0)
- sync
- sw zero, 0(t0)
- sync
-
- li t0, MEM_SDREFCFG
- li t1, 0x8A0007A1 /* Enable */
- sw t1, 0(t0)
- sync
-
- li t0, MEM_SDWRMD0
- li t1, 0x00000023
- sw t1, 0(t0)
- sync
-
- /* wait 1mS after setup */
- li t1, MEM_1MS
-1: add t1, -1
- bne t1, zero, 1b
- nop
-
- /* Setup GPIO pins */
-
- li t0, SYS_PINFUNC
- li t1, 0x00007025 /* 0x8080 */
- sw t1, 0(t0)
-
- li t0, SYS_TRIOUTCLR
- li t1, 0xFFFFFFFF /* 0x1FFF */
- sw t1, 0(t0)
-
- /* Turn yellow front led on */
- /* Release reset on CF */
- li t0, SYS_OUTPUTCLR
- li t1, GPIO_RJ1LG
- sw t1, 0(t0)
- li t0, SYS_OUTPUTSET
- li t1, GPIO_RJ1LY|GPIO_CFRESET
- sw t1, 0(t0)
- sync
- j clearmem
- nop
-
-#if 0
- .globl memtest
-#endif
-memtest:
- /* Fill memory with address */
- li t0, 0x80000000
- li t1, 0xFFF000 /* 64 MB */
-mt0: sw t0, 0(t0)
- add t1, -1
- add t0, 4
- bne t1, zero, mt0
- nop
- nop
- /* Verify addr */
- li t0, 0x80000000
- li t1, 0xFFF000 /* 64 MB */
-mt1: lw t2, 0(t0)
- bne t0, t2, memhang
- add t1, -1
- add t0, 4
- bne t1, zero, mt1
- nop
- nop
-#if 0
- .globl clearmem
-#endif
-clearmem:
- /* Clear memory */
- li t0, 0x80000000
- li t1, 0xFFF000 /* 64 MB */
-mtc: sw zero, 0(t0)
- add t1, -1
- add t0, 4
- bne t1, zero, mtc
- nop
- nop
-memtestend:
- jr ra
- nop
-
-memhang:
- b memhang
- nop
--- /dev/null
+#
+# h2200 Support
+#
+# Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := h2200.o
+
+SRCS := $(COBJS:.o=.c) h2200-header.S
+OBJS := $(addprefix $(obj),$(COBJS))
+
+all: $(LIB) $(obj)h2200-header.bin
+
+$(obj)h2200-header.o: h2200-header.S
+ $(CC) $(CFLAGS) -c -o $@ $<
+
+$(obj)h2200-header.bin: $(obj)h2200-header.o
+ $(OBJCOPY) -O binary $< $@
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * iPAQ h2200 header
+ *
+ * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+ .word 0xea0003fe /* b 0x1000 */
+
+ .org 0x40
+ .ascii "ECEC"
+
+ .org 0x1000 - 1
+ .byte 0x0
--- /dev/null
+/*
+ * iPAQ h2200 board configuration
+ *
+ * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/pxa.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ /* We have RAM, disable cache */
+ dcache_disable();
+ icache_disable();
+
+ gd->bd->bi_arch_number = MACH_TYPE_H2200;
+
+ /* adress of boot parameters */
+ gd->bd->bi_boot_params = 0xa0000100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ /*
+ * Everything except MSC0 was already set up by
+ * 1st stage bootloader.
+ *
+ * This setting enables access to companion chip.
+ */
+ clrsetbits_le32(MSC0, 0xffffffff, CONFIG_SYS_MSC0_VAL);
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ return 0;
+}
writel((CCM_CCMR_SETUP | CCMR_MPE) & ~CCMR_MDS, &ccm->ccmr);
/* Set up clock to 532MHz */
- writel(PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) |
+ writel(PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) |
PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |
PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |
PDR0_MCU_PODF(0), &ccm->pdr0);
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
- return omap_ehci_hcd_init(&usbhs_bdata);
+ return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
}
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return omap_ehci_hcd_stop();
}
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
- REG CCM_PDR0, PDR0_CSI_PODF(0xff1) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
+ REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0)
REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0xe) | PLL_MFI(9) | PLL_MFN(0xd)
.sdata : { *(.sdata*) }
- .u_boot_cmd : {
- __u_boot_cmd_start = .;
- *(.u_boot_cmd)
- __u_boot_cmd_end = .;
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
}
uboot_end_data = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
void ide_set_reset (int on)
{
volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
+ int i;
/*
* Configure PC for IDE Reset Pin
*/
if (on) { /* assert RESET */
immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET);
+
+#ifdef CONFIG_SYS_PB_12V_ENABLE
+ /* 12V Enable output OFF */
+ immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_12V_ENABLE);
+
+ immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_12V_ENABLE);
+ immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_12V_ENABLE);
+ immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_12V_ENABLE;
+
+ /* wait 500 ms for the voltage to stabilize */
+ for (i = 0; i < 500; ++i)
+ udelay(1000);
+#endif /* CONFIG_SYS_PB_12V_ENABLE */
} else { /* release RESET */
+#ifdef CONFIG_SYS_PB_12V_ENABLE
+ /* 12V Enable output ON */
+ immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_12V_ENABLE;
+#endif /* CONFIG_SYS_PB_12V_ENABLE */
+
+#ifdef CONFIG_SYS_PB_IDE_MOTOR
+ /* configure IDE Motor voltage monitor pin as input */
+ immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_IDE_MOTOR);
+ immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_IDE_MOTOR);
+ immr->im_cpm.cp_pbdir &= ~(CONFIG_SYS_PB_IDE_MOTOR);
+
+/* wait up to 1 s for the motor voltage to stabilize */
+ for (i = 0; i < 1000; ++i) {
+ if ((immr->im_cpm.cp_pbdat
+ & CONFIG_SYS_PB_IDE_MOTOR) != 0)
+ break;
+ udelay(1000);
+ }
+
+ if (i == 1000) { /* Timeout */
+ printf("\nWarning: 5V for IDE Motor missing\n");
+#ifdef CONFIG_STATUS_LED
+#ifdef STATUS_LED_YELLOW
+ status_led_set(STATUS_LED_YELLOW, STATUS_LED_ON);
+#endif
+#ifdef STATUS_LED_GREEN
+ status_led_set(STATUS_LED_GREEN, STATUS_LED_OFF);
+#endif
+#endif /* CONFIG_STATUS_LED */
+ }
+#endif /* CONFIG_SYS_PB_IDE_MOTOR */
+
immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET;
}
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
*/
#include <asm/macro.h>
-
-.macro init_aips
- write32 0x43f00000, 0x77777777
- write32 0x43f00004, 0x77777777
- write32 0x43f00000, 0x77777777
- write32 0x53f00004, 0x77777777
-.endm
-
-.macro init_max
- write32 0x43f04000, 0x43210
- write32 0x43f04100, 0x43210
- write32 0x43f04200, 0x43210
- write32 0x43f04300, 0x43210
- write32 0x43f04400, 0x43210
-
- write32 0x43f04010, 0x10
- write32 0x43f04110, 0x10
- write32 0x43f04210, 0x10
- write32 0x43f04310, 0x10
- write32 0x43f04410, 0x10
-
- write32 0x43f04800, 0x0
- write32 0x43f04900, 0x0
- write32 0x43f04a00, 0x0
- write32 0x43f04b00, 0x0
- write32 0x43f04c00, 0x0
-.endm
-
-.macro init_m3if
- write32 0xb8003000, 0x1
-.endm
+#include <asm/arch/macro.h>
.macro init_clocks
/*
* 0x00600000 makes CLKO parent clk the USB clk
*/
write32 0x53f80064, 0x45600000
+
+ /* CCTL: ARM = 399 MHz, AHB = 133 MHz */
write32 0x53f80008, 0x20034000
/*
#define SMSTPCR1_CMT0 (1 << 24)
#define SMSTPCR1_I2C0 (1 << 16)
#define SMSTPCR3_USB (1 << 22)
+#define SMSTPCR3_I2C1 (1 << 23)
#define PORT32CR (0xE6051020)
#define PORT33CR (0xE6051021)
clrbits_le32(&cpg->smstpcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
clrbits_le32(&cpg_srcr->srcr1, (SMSTPCR1_CMT0|SMSTPCR1_I2C0));
- clrbits_le32(&cpg->smstpcr3, SMSTPCR3_USB);
- clrbits_le32(&cpg_srcr->srcr3, SMSTPCR3_USB);
+ clrbits_le32(&cpg->smstpcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1));
+ clrbits_le32(&cpg_srcr->srcr3, (SMSTPCR3_USB|SMSTPCR3_I2C1));
writel(VCLKCR1_D, &cpg->vclkcr1);
/* Setup SCIF4 / workaround */
gpio_direction_output(GPIO_PORT15, 1);
/* I2C */
+ gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL);
+ gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL);
gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
#define IT8212_PCI_IdeBusSkewCONTROL 0x4c
#define IT8212_PCI_IdeDrivingCURRENT 0x42
-extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
extern struct pci_controller hose;
int ide_preinit (void)
REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE
REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS
- REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)
+ REG CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)
REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)
REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
struct serial_device *default_serial_console(void)
{
- return ZOOM2_DEFAULT_SERIAL_DEVICE;
+ switch (ZOOM2_DEFAULT_SERIAL_DEVICE) {
+ case 0: return &zoom2_serial_device0;
+ case 1: return &zoom2_serial_device1;
+ case 2: return &zoom2_serial_device2;
+ case 3: return &zoom2_serial_device3;
+ }
}
#ifndef ZOOM2_SERIAL_H
#define ZOOM2_SERIAL_H
+#include <linux/stringify.h>
+
extern int zoom2_debug_board_connected (void);
#define SERIAL_TL16CP754C_BASE 0x10000000 /* Zoom2 Serial chip address */
#define QUAD_BASE_2 (SERIAL_TL16CP754C_BASE + 0x200)
#define QUAD_BASE_3 (SERIAL_TL16CP754C_BASE + 0x300)
-#define S(a) #a
-#define N(a) S(quad##a)
-
#define QUAD_INIT(n) \
int quad_init_##n(void) \
{ \
} \
struct serial_device zoom2_serial_device##n = \
{ \
- N(n), \
- quad_init_##n, \
- NULL, \
- quad_setbrg_##n, \
- quad_getc_##n, \
- quad_tstc_##n, \
- quad_putc_##n, \
- quad_puts_##n, \
+ .name = __stringify(n), \
+ .start = quad_init_##n, \
+ .stop = NULL, \
+ .setbrg = quad_setbrg_##n, \
+ .getc = quad_getc_##n, \
+ .tstc = quad_tstc_##n, \
+ .putc = quad_putc_##n, \
+ .puts = quad_puts_##n, \
};
#endif /* ZOOM2_SERIAL_H */
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
.sdata : { *(.sdata*) }
. = ALIGN(4);
- .u_boot_cmd : {
- __u_boot_cmd_start = .;
- *(.u_boot_cmd)
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include <u-boot.lst>
}
. = ALIGN(4);
+++ /dev/null
-/*
- * flash.c: Support code for the flash chips on the Xilinx ML2 board
- *
- * Copyright 2002 Mind NV
- *
- * http://www.mind.be/
- *
- * Author : Peter De Schrijver (p2@mind.be)
- *
- * This software may be used and distributed according to the terms of
- * the GNU General Public License (GPL) version 2, incorporated herein by
- * reference. Drivers based on or derived from this code fall under the GPL
- * and must retain the authorship, copyright and this license notice. This
- * file is not a complete program and may only be used when the entire program
- * is licensed under the GPL.
- *
- */
-
-#include <common.h>
-#include <asm/u-boot.h>
-#include <configs/ML2.h>
-
-#define FLASH_BANK_SIZE (64*1024*1024)
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
-
-#define SECT_SIZE (512*1024)
-
-#define CMD_READ_ARRAY 0x00FF00FF00FF00FULL
-#define CMD_IDENTIFY 0x0090009000900090ULL
-#define CMD_ERASE_SETUP 0x0020002000200020ULL
-#define CMD_ERASE_CONFIRM 0x00D000D000D000D0ULL
-#define CMD_PROGRAM 0x0040004000400040ULL
-#define CMD_RESUME 0x00D000D000D000D0ULL
-#define CMD_SUSPEND 0x00B000B000B000B0ULL
-#define CMD_STATUS_READ 0x0070007000700070ULL
-#define CMD_STATUS_RESET 0x0050005000500050ULL
-
-#define BIT_BUSY 0x0080008000800080ULL
-#define BIT_ERASE_SUSPEND 0x004000400400040ULL
-#define BIT_ERASE_ERROR 0x0020002000200020ULL
-#define BIT_PROGRAM_ERROR 0x0010001000100010ULL
-#define BIT_VPP_RANGE_ERROR 0x0008000800080008ULL
-#define BIT_PROGRAM_SUSPEND 0x0004000400040004ULL
-#define BIT_PROTECT_ERROR 0x0002000200020002ULL
-#define BIT_UNDEFINED 0x0001000100010001ULL
-
-#define BIT_SEQUENCE_ERROR 0x0030003000300030ULL
-
-#define BIT_TIMEOUT 0x80000000
-
-
-inline void eieio(void) {
-
- __asm__ __volatile__ ("eieio" : : : "memory");
-
-}
-
-ulong flash_init(void) {
-
- int i, j;
- ulong size = 0;
-
- for(i=0;i<CONFIG_SYS_MAX_FLASH_BANKS;i++) {
- ulong flashbase = 0;
-
- flash_info[i].flash_id = (INTEL_MANUFACT & FLASH_VENDMASK) |
- (INTEL_ID_28F128J3A & FLASH_TYPEMASK);
- flash_info[i].size = FLASH_BANK_SIZE;
- flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
- memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
- if (i==0)
- flashbase = CONFIG_SYS_FLASH_BASE;
- else
- panic("configured too many flash banks!\n");
- for (j = 0; j < flash_info[i].sector_count; j++)
- flash_info[i].start[j]=flashbase + j * SECT_SIZE;
-
- size += flash_info[i].size;
- }
-
- return size;
-}
-
-void flash_print_info (flash_info_t *info) {
-
- int i;
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case (INTEL_MANUFACT & FLASH_VENDMASK):
- printf("Intel: ");
- break;
- default:
- printf("Unknown Vendor ");
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case (INTEL_ID_28F128J3A & FLASH_TYPEMASK):
- printf("4x 28F128J3A (128Mbit)\n");
- break;
- default:
- printf("Unknown Chip Type\n");
- break;
- }
-
- printf(" Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
- printf(" Sector Start Addresses:");
- for (i = 0; i < info->sector_count; i++) {
- if ((i % 5) == 0)
- printf("\n ");
- printf (" %08lX%s", info->start[i],
- info->protect[i] ? " (RO)" : " ");
- }
- printf ("\n");
-}
-
-int flash_error (unsigned long long code) {
-
- if (code & BIT_TIMEOUT) {
- printf ("Timeout\n");
- return ERR_TIMOUT;
- }
-
- if (~code & BIT_BUSY) {
- printf ("Busy\n");
- return ERR_PROG_ERROR;
- }
-
- if (code & BIT_VPP_RANGE_ERROR) {
- printf ("Vpp range error\n");
- return ERR_PROG_ERROR;
- }
-
- if (code & BIT_PROTECT_ERROR) {
- printf ("Device protect error\n");
- return ERR_PROG_ERROR;
- }
-
- if (code & BIT_SEQUENCE_ERROR) {
- printf ("Command seqence error\n");
- return ERR_PROG_ERROR;
- }
-
- if (code & BIT_ERASE_ERROR) {
- printf ("Block erase error\n");
- return ERR_PROG_ERROR;
- }
-
- if (code & BIT_PROGRAM_ERROR) {
- printf ("Program error\n");
- return ERR_PROG_ERROR;
- }
-
- if (code & BIT_ERASE_SUSPEND) {
- printf ("Block erase suspended\n");
- return ERR_PROG_ERROR;
- }
-
- if (code & BIT_PROGRAM_SUSPEND) {
- printf ("Program suspended\n");
- return ERR_PROG_ERROR;
- }
-
- return ERR_OK;
-
-}
-
-int flash_erase (flash_info_t *info, int s_first, int s_last) {
-
- int rc = ERR_OK;
- int sect;
- unsigned long long result;
-
- if (info->flash_id == FLASH_UNKNOWN)
- return ERR_UNKNOWN_FLASH_TYPE;
-
- if ((s_first < 0) || (s_first > s_last))
- return ERR_INVAL;
-
- if ((info->flash_id & FLASH_VENDMASK) != (INTEL_MANUFACT & FLASH_VENDMASK))
- return ERR_UNKNOWN_FLASH_VENDOR;
-
- for (sect=s_first; sect<=s_last; ++sect)
- if (info->protect[sect])
- return ERR_PROTECTED;
-
- for (sect = s_first; sect<=s_last && !ctrlc(); sect++) {
- volatile unsigned long long *addr=
- (unsigned long long *)(info->start[sect]);
-
- printf("Erasing sector %2d ... ", sect);
-
- *addr=CMD_STATUS_RESET;
- eieio();
- *addr=CMD_ERASE_SETUP;
- eieio();
- *addr=CMD_ERASE_CONFIRM;
- eieio();
-
- do {
- result = *addr;
- } while(~result & BIT_BUSY);
-
- *addr=CMD_READ_ARRAY;
-
- if ((rc = flash_error(result)) == ERR_OK)
- printf("ok.\n");
- else
- break;
- }
-
- if (ctrlc())
- printf("User Interrupt!\n");
-
- return rc;
-}
-
-static int write_word (flash_info_t *info, ulong dest, unsigned long long data) {
-
- volatile unsigned long long *addr=(unsigned long long *)dest;
- unsigned long long result;
- int rc = ERR_OK;
-
- result = *addr;
- if ((result & data) != data)
- return ERR_NOT_ERASED;
-
- *addr=CMD_STATUS_RESET;
- eieio();
- *addr=CMD_PROGRAM;
- eieio();
- *addr=data;
- eieio();
-
- do {
- result = *addr;
- } while(~result & BIT_BUSY);
-
- *addr=CMD_READ_ARRAY;
-
- rc = flash_error(result);
-
- return rc;
-
-}
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) {
-
- ulong cp, wp;
- unsigned long long data;
- int l;
- int i,rc;
-
- wp=(addr & ~7);
-
- if((l=addr-wp) != 0) {
- data=0;
- for(i=0,cp=wp;i<l;++i,++cp)
- data = (data >> 8) | (*(uchar *)cp << 24);
-
- for (; i<8 && cnt>0; ++i) {
- data = (data >> 8) | (*src++ << 24);
- --cnt;
- ++cp;
- }
-
- for (; i<8; ++i, ++cp)
- data = (data >> 8) | (*(uchar *)cp << 24);
-
- if ((rc = write_word(info, wp, data)) != 0)
- return rc;
-
- wp+=8;
- }
-
- while(cnt>=8) {
- data = *((unsigned long long *)src);
- if ((rc = write_word(info, wp, data)) != 0)
- return rc;
- src+=8;
- wp+=8;
- cnt-=8;
- }
-
- if(cnt == 0)
- return ERR_OK;
-
- data = 0;
- for (i=0, cp=wp; i<8 && cnt>0; ++i, ++cp) {
- data = (data >> 8) | (*src++ << 24);
- --cnt;
- }
- for (; i<8; ++i, ++cp) {
- data = (data >> 8) | (*(uchar *)cp << 24);
- }
-
- return write_word(info, wp, data);
-
-}
+++ /dev/null
-/*
- * init.S: Stubs for U-Boot initialization
- *
- * Copyright 2002 Mind NV
- *
- * http://www.mind.be/
- *
- * Author : Peter De Schrijver (p2@mind.be)
- *
- * This software may be used and distributed according to the terms of
- * the GNU General Public License (GPL) version 2, incorporated herein by
- * reference. Drivers based on or derived from this code fall under the GPL
- * and must retain the authorship, copyright and this license notice. This
- * file is not a complete program and may only be used when the entire
- * program is licensed under the GPL.
- *
- */
-
-#include <asm/ppc4xx.h>
-
-#include <ppc_asm.tmpl>
-#include <ppc_defs.h>
-
-#include <asm/cache.h>
-#include <asm/mmu.h>
-
-
- .globl ext_bus_cntlr_init
-ext_bus_cntlr_init:
- blr
+++ /dev/null
-/*
- * ml2.c: U-Boot platform support for Xilinx ML2 board
- *
- * Copyright 2002 Mind NV
- *
- * http://www.mind.be/
- *
- * Author : Peter De Schrijver (p2@mind.be)
- *
- * Derived from : Other platform support files in this tree
- *
- * This software may be used and distributed according to the terms of
- * the GNU General Public License (GPL) version 2, incorporated herein by
- * reference. Drivers based on or derived from this code fall under the GPL
- * and must retain the authorship, copyright and this license notice. This
- * file is not a complete program and may only be used when the entire
- * program is licensed under the GPL.
- *
- */
-
-#include <common.h>
-#include <asm/processor.h>
-
-
-int board_early_init_f (void)
-{
- return 0;
-}
-
-
-int checkboard (void)
-{
- char buf[64];
- int i;
- int l = getenv_f("serial#", buf, sizeof(buf));
-
- if (l < 0 || strncmp(buf, "ML2", 9)) {
- printf ("### No HW ID - assuming ML2");
- } else {
- for (i = 0; i < l; i++) {
- if (buf[i] == ' ')
- break;
- putc(buf[i]);
- }
- }
- putc ('\n');
-
- return (0);
-}
-
-
-phys_size_t initdram (int board_type)
-{
- return 32 * 1024 * 1024;
-}
-
-int testdram (void)
-{
- printf ("test: xxx MB - ok\n");
-
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Peter De Schrijver (p2@mind.be), Mind Linux Solutions, NV.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <asm/u-boot.h>
-#include <asm/processor.h>
-#include <command.h>
-#include <configs/ML2.h>
-
-#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
-#include <ns16550.h>
-#endif
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
-const NS16550_t COM_PORTS[] = { (NS16550_t) CONFIG_SYS_NS16550_COM1,
- (NS16550_t) CONFIG_SYS_NS16550_COM2
-};
-#endif
-
-int serial_init (void)
-{
- int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
-
-#ifdef CONFIG_SYS_INIT_CHAN1
- (void) NS16550_init (COM_PORTS[0], clock_divisor);
-#endif
-#ifdef CONFIG_SYS_INIT_CHAN2
- (void) NS16550_init (COM_PORTS[1], clock_divisor);
-#endif
- return 0;
-
-}
-
-void serial_putc (const char c)
-{
- if (c == '\n')
- NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
-
- NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
-}
-
-int serial_getc (void)
-{
- return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
-}
-
-int serial_tstc (void)
-{
- return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
-}
-
-void serial_setbrg (void)
-{
- int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
-
-#ifdef CONFIG_SYS_INIT_CHAN1
- NS16550_reinit (COM_PORTS[0], clock_divisor);
-#endif
-#ifdef CONFIG_SYS_INIT_CHAN2
- NS16550_reinit (COM_PORTS[1], clock_divisor);
-#endif
-}
-
-void serial_puts (const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
-#if defined(CONFIG_CMD_KGDB)
-void kgdb_serial_init (void)
-{
-}
-
-void putDebugChar (int c)
-{
- serial_putc (c);
-}
-
-void putDebugStr (const char *str)
-{
- serial_puts (str);
-}
-
-int getDebugChar (void)
-{
- return serial_getc ();
-}
-
-void kgdb_interruptible (int yes)
-{
- return;
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- *(.text*)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x00FF) & 0xFFFFFF00;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(256);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(256);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end__ = . ;
- PROVIDE (end = .);
-}
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-OUTPUT_ARCH(powerpc)
-/* Do we need any of these for elf?
- __DYNAMIC = 0; */
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .interp : { *(.interp) }
- .hash : { *(.hash) }
- .dynsym : { *(.dynsym) }
- .dynstr : { *(.dynstr) }
- .rel.text : { *(.rel.text) }
- .rela.text : { *(.rela.text) }
- .rel.data : { *(.rel.data) }
- .rela.data : { *(.rela.data) }
- .rel.rodata : { *(.rel.rodata) }
- .rela.rodata : { *(.rela.rodata) }
- .rel.got : { *(.rel.got) }
- .rela.got : { *(.rela.got) }
- .rel.ctors : { *(.rel.ctors) }
- .rela.ctors : { *(.rela.ctors) }
- .rel.dtors : { *(.rel.dtors) }
- .rela.dtors : { *(.rela.dtors) }
- .rel.bss : { *(.rel.bss) }
- .rela.bss : { *(.rela.bss) }
- .rel.plt : { *(.rel.plt) }
- .rela.plt : { *(.rela.plt) }
- .init : { *(.init) }
- .plt : { *(.plt) }
- .text :
- {
- /* WARNING - the following is hand-optimized to fit within */
- /* the sector layout of our flash chips! XXX FIXME XXX */
-
- mpc8xx/start.o (.text)
- common/dlmalloc.o (.text)
- lib/vsprintf.o (.text)
- lib/crc32.o (.text)
- arch/powerpc/lib/extable.o (.text)
-
- common/env_embedded.o(.text)
-
- *(.text)
- *(.got1)
- }
- _etext = .;
- PROVIDE (etext = .);
- .rodata :
- {
- *(.rodata)
- *(.rodata1)
- *(.rodata.str1.4)
- *(.eh_frame)
- }
- .fini : { *(.fini) } =0
- .ctors : { *(.ctors) }
- .dtors : { *(.dtors) }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- *(.got)
- _GOT2_TABLE_ = .;
- *(.got2)
- _FIXUP_TABLE_ = .;
- *(.fixup)
- }
- __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
- __fixup_entries = (. - _FIXUP_TABLE_)>>2;
-
- .data :
- {
- *(.data)
- *(.data1)
- *(.sdata)
- *(.sdata2)
- *(.dynamic)
- CONSTRUCTORS
- }
- _edata = .;
- PROVIDE (edata = .);
-
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
-
-
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss :
- {
- *(.sbss) *(.scommon)
- *(.dynbss)
- *(.bss)
- *(COMMON)
- }
- __bss_end__ = . ;
- PROVIDE (end = .);
-}
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
} > ram
*/
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) } > ram
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
/* init uhci
*/
-int usb_lowlevel_init(void)
+int usb_lowlevel_init(int index, void **controller)
{
unsigned char temp;
int busdevfunc;
/* stop uhci
*/
-int usb_lowlevel_stop(void)
+int usb_lowlevel_stop(int index)
{
if(irqvec==-1)
return 1;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
#include <ns16550.h>
#include <linux/compiler.h>
#include <asm/io.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/sys_proto.h>
-
-#include <asm/arch/board.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/emc.h>
+#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/pmc.h>
#include <asm/arch/pmu.h>
-#include <asm/arch/uart.h>
-#include <asm/arch/warmboot.h>
-#include <spi.h>
+#include <asm/arch/tegra.h>
#include <asm/arch/usb.h>
+#include <asm/arch-tegra/board.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/pmc.h>
+#include <asm/arch-tegra/sys_proto.h>
+#include <asm/arch-tegra/uart.h>
+#include <asm/arch-tegra/warmboot.h>
+#include <spi.h>
#include <i2c.h>
-#include "board.h"
#include "emc.h"
DECLARE_GLOBAL_DATA_PTR;
void pin_mux_spi(void) __attribute__((weak, alias("__pin_mux_spi")));
+void __gpio_early_init_uart(void)
+{
+}
+
+void gpio_early_init_uart(void)
+__attribute__((weak, alias("__gpio_early_init_uart")));
+
+void __pin_mux_nand(void)
+{
+ funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
+}
+
+void pin_mux_nand(void) __attribute__((weak, alias("__pin_mux_nand")));
+
/*
* Routine: power_det_init
* Description: turn off power detects
board_usb_init(gd->fdt_blob);
#endif
+#ifdef CONFIG_TEGRA_NAND
+ pin_mux_nand();
+#endif
+
#ifdef CONFIG_TEGRA_LP0
/* save Sdram params to PMC 2, 4, and 24 for WB0 */
warmboot_save_sdram_params();
/* Initialize periph GPIOs */
gpio_early_init();
-#ifdef CONFIG_SPI_UART_SWITCH
gpio_early_init_uart();
-#else
- gpio_config_uart();
-#endif
+
return 0;
}
#endif /* EARLY_INIT */
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/ap20.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/emc.h>
#include <asm/arch/pmu.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/tegra20.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/sys_proto.h>
DECLARE_GLOBAL_DATA_PTR;
#include <asm/gpio.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/uart-spi-switch.h>
-#include <asm/arch/tegra20.h>
-#include <asm/arch/tegra_spi.h>
-
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/tegra_spi.h>
+#include <asm/arch-tegra/board.h>
/* position of the UART/SPI select switch */
enum spi_uart_switch {
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/tegra20.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/mmc.h>
+#include <asm/arch/tegra.h>
+#include <asm/arch-tegra/mmc.h>
#include <asm/gpio.h>
#ifdef CONFIG_TEGRA_MMC
#include <mmc.h>
#endif
-/*
- * Routine: gpio_config_uart
- * Description: Does nothing on Harmony - no conflict w/SPI.
- */
-void gpio_config_uart(void)
-{
-}
#ifdef CONFIG_TEGRA_MMC
/*
#include <common.h>
#include <asm/io.h>
-#include <asm/arch/tegra20.h>
+#include <asm/arch/tegra.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/mmc.h>
+#include <asm/arch-tegra/mmc.h>
#include <asm/gpio.h>
#ifdef CONFIG_TEGRA_MMC
#include <mmc.h>
gpio_direction_output(GPIO_PI3, 0);
}
-void gpio_config_uart(void)
+void gpio_early_init_uart(void)
{
if (machine_is_ventana())
return;
*/
#include <common.h>
-#include <i2c.h>
#include <asm/io.h>
-#include <asm/arch/tegra20.h>
+#include <asm/arch/tegra.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/mmc.h>
+#include <asm/arch-tegra/mmc.h>
#include <asm/gpio.h>
+#include <i2c.h>
#ifdef CONFIG_TEGRA_MMC
#include <mmc.h>
#endif
-/*
- * Routine: gpio_config_uart
- * Description: Does nothing on Whistler - no UART-related GPIOs.
- */
-void gpio_config_uart(void)
-{
-}
/*
* Routine: pin_mux_mmc
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
_endtext = .;
} > ram
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) } > ram
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
.rodata : {
*(.rodata);
return 0;
}
-struct serial_device *default_serial_console(void)
-{
- return &serial_ffuart_device;
-}
-
int dram_init(void)
{
pxa2xx_dram_init();
return 0;
}
-struct serial_device *default_serial_console(void)
-{
- return &serial_ffuart_device;
-}
-
int dram_init(void)
{
pxa2xx_dram_init();
.sdata : { *(.sdata*) }
- .u_boot_cmd : {
- __u_boot_cmd_start = .;
- *(.u_boot_cmd)
- __u_boot_cmd_end = .;
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
}
uboot_end_data = .;
}
}
-void fpga_serial_puts (const char *s)
-{
- while (*s) {
- fpga_serial_print (*s++);
- }
-}
-
int fpga_serial_getc (void)
{
while ((in8 (UART (LSR)) & 0x01) == 0);
extern void fpga_serial_init (int);
extern void fpga_serial_putc (char);
-extern void fpga_serial_puts (const char *);
extern int fpga_serial_getc (void);
extern int fpga_serial_tstc (void);
extern void fpga_serial_setbrg (void);
#include <watchdog.h>
#include <pci.h>
#include <netdev.h>
+#include <serial.h>
#include "hardware.h"
#include "pcippc2.h"
fpga_serial_init (sconsole_get_baudrate ());
sconsole_putc = fpga_serial_putc;
- sconsole_puts = fpga_serial_puts;
+ sconsole_puts = default_serial_puts;
sconsole_getc = fpga_serial_getc;
sconsole_tstc = fpga_serial_tstc;
sconsole_setbrg = fpga_serial_setbrg;
#include <config.h>
#include <common.h>
+#include <serial.h>
+#include <linux/compiler.h>
#include "sconsole.h"
int (*sconsole_tstc) (void) = 0;
void (*sconsole_setbrg) (void) = 0;
-int serial_init (void)
+static int sconsole_serial_init(void)
{
sconsole_buffer_t *sb = SCONSOLE_BUFFER;
return (0);
}
-void serial_putc (char c)
+static void sconsole_serial_putc(char c)
{
if (sconsole_putc) {
(*sconsole_putc) (c);
}
}
-void serial_puts (const char *s)
+static void sconsole_serial_puts(const char *s)
{
if (sconsole_puts) {
(*sconsole_puts) (s);
}
}
-int serial_getc (void)
+static int sconsole_serial_getc(void)
{
if (sconsole_getc) {
return (*sconsole_getc) ();
}
}
-int serial_tstc (void)
+static int sconsole_serial_tstc(void)
{
if (sconsole_tstc) {
return (*sconsole_tstc) ();
}
}
-void serial_setbrg (void)
+static void sconsole_serial_setbrg(void)
{
if (sconsole_setbrg) {
(*sconsole_setbrg) ();
}
}
+static struct serial_device sconsole_serial_drv = {
+ .name = "sconsole_serial",
+ .start = sconsole_serial_init,
+ .stop = NULL,
+ .setbrg = sconsole_serial_setbrg,
+ .putc = sconsole_serial_putc,
+ .puts = sconsole_serial_puts,
+ .getc = sconsole_serial_getc,
+ .tstc = sconsole_serial_tstc,
+};
+
+void sconsole_serial_initialize(void)
+{
+ serial_register(&sconsole_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &sconsole_serial_drv;
+}
+
int sconsole_get_baudrate (void)
{
sconsole_buffer_t *sb = SCONSOLE_BUFFER;
#include <sha1.h>
#include <asm/io.h>
#include <net.h>
+#include <ata.h>
DECLARE_GLOBAL_DATA_PTR;
* ( bus per_addr 20 -30 is connectsd on CF bus A10-A0)
* These values are shifted
*/
-extern ulong *ide_bus_offset;
void inline ide_outb(int dev, int port, unsigned char val)
{
debug ("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
udelay (10000);
}
#endif /* defined (CONFIG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
+
+
+/* this is motly the same as it should, causing a little code duplication */
+#if defined(CONFIG_CMD_IDE)
+#define EIEIO __asm__ volatile ("eieio")
+
+void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+{
+ volatile ushort *pbuf =
+ (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
+ ushort *dbuf = (ushort *) sect_buf;
+
+ debug("in input swap data base for read is %lx\n",
+ (unsigned long) pbuf);
+
+ while (words--) {
+ *dbuf++ = *pbuf;
+ *dbuf++ = *pbuf;
+ }
+}
+
+void ide_output_data(int dev, const ulong *sect_buf, int words)
+{
+ ushort *dbuf;
+ volatile ushort *pbuf;
+
+ pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
+ dbuf = (ushort *) sect_buf;
+ while (words--) {
+ EIEIO;
+ *pbuf = ld_le16(dbuf++);
+ EIEIO;
+ *pbuf = ld_le16(dbuf++);
+ }
+}
+
+void ide_input_data(int dev, ulong *sect_buf, int words)
+{
+ ushort *dbuf;
+ volatile ushort *pbuf;
+
+ pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
+ dbuf = (ushort *) sect_buf;
+
+ debug("in input data base for read is %lx\n", (unsigned long) pbuf);
+
+ while (words--) {
+ EIEIO;
+ *dbuf++ = ld_le16(pbuf);
+ EIEIO;
+ *dbuf++ = ld_le16(pbuf);
+ }
+}
+
+#endif
return msize;
}
-#if defined(CONFIG_SERIAL_MULTI)
static int set_lcd_brightness(char *);
-#endif
int misc_init_r(void)
{
#endif
#ifdef CONFIG_FSL_DIU_FB
-#if defined(CONFIG_SERIAL_MULTI)
set_lcd_brightness(0);
-#endif
/* Switch LCD-Backlight and LVDS-Interface on */
setbits_be32(&im->gpio.gpdir, 0x01040000);
clrsetbits_be32(&im->gpio.gpdat, 0x01000000, 0x00040000);
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
-#if defined(CONFIG_SERIAL_MULTI)
/*
* If argument is NULL, set the LCD brightness to the
* value from "brightness" environment variable. Set
"set LCD brightness",
"<brightness> - set LCD backlight level to <brightness>.\n"
);
-#endif /* CONFIG_SERIAL_MULTI */
#include <common.h>
#include <command.h>
+#include <serial.h>
+#include <linux/compiler.h>
+
#include "../../Marvell/include/memory.h"
#include "serial.h"
DECLARE_GLOBAL_DATA_PTR;
-int serial_init (void)
+static int p3mx_serial_init(void)
{
mpsc_init (gd->baudrate);
return (0);
}
-void serial_putc (const char c)
+static void p3mx_serial_putc(const char c)
{
if (c == '\n')
mpsc_putchar ('\r');
mpsc_putchar (c);
}
-int serial_getc (void)
+static int p3mx_serial_getc(void)
{
return mpsc_getchar ();
}
-int serial_tstc (void)
+static int p3mx_serial_tstc(void)
{
return mpsc_test_char ();
}
-void serial_setbrg (void)
+static void p3mx_serial_setbrg(void)
{
galbrg_set_baudrate (CONFIG_MPSC_PORT, gd->baudrate);
}
+static struct serial_device p3mx_serial_drv = {
+ .name = "p3mx_serial",
+ .start = p3mx_serial_init,
+ .stop = NULL,
+ .setbrg = p3mx_serial_setbrg,
+ .putc = p3mx_serial_putc,
+ .puts = default_serial_puts,
+ .getc = p3mx_serial_getc,
+ .tstc = p3mx_serial_tstc,
+};
+
+void p3mx_serial_initialize(void)
+{
+ serial_register(&p3mx_serial_drv);
+}
-void serial_puts (const char *s)
+__weak struct serial_device *default_serial_console(void)
{
- while (*s) {
- serial_putc (*s++);
- }
+ return &p3mx_serial_drv;
}
#if defined(CONFIG_CMD_KGDB)
+++ /dev/null
-#
-# Qemu -M mips system emulator
-# See http://fabrice.bellard.free.fr/qemu
-#
-
-# ROM version
-CONFIG_SYS_TEXT_BASE = 0xbfc00000
-
-# RAM version
-#CONFIG_SYS_TEXT_BASE = 0x80001000
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
+#if defined(CONFIG_64BIT)
+OUTPUT_FORMAT("elf64-tradbigmips", "elf64-tradbigmips", "elf64-tradlittlemips")
+#else
OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
+#endif
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
. = ALIGN(4);
.sdata : { *(.sdata*) }
- . = .;
- .u_boot_cmd : {
- __u_boot_cmd_start = .;
- *(.u_boot_cmd)
- __u_boot_cmd_end = .;
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
}
uboot_end_data = .;
+#if defined(CONFIG_64BIT)
+ num_got_entries = (__got_end - __got_start) >> 3;
+#else
num_got_entries = (__got_end - __got_start) >> 2;
+#endif
. = ALIGN(4);
.sbss : { *(.sbss*) }
.sdata : { *(.sdata*) }
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
uboot_end_data = .;
num_got_entries = (__got_end - __got_start) >> 2;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
__start___ex_table = .;
}
PROVIDE (_egot = .);
- PROVIDE (__u_boot_cmd_start = .);
- .u_boot_cmd :
- {
- *(.u_boot_cmd)
- . = ALIGN(4);
+
+ .u_boot_list : {
+ #include <u-boot.lst>
}
- PROVIDE (__u_boot_cmd_end = .);
PROVIDE (reloc_dst_end = .);
/* _reloc_dst_end = .; */
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
.data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram
. = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ } >.sram
+ . = ALIGN(4);
+
/* Align .machine_param on 256 byte boundary for easier searching */
.machine_param ALIGN(0x100) : { *(.machine_param) } >.sram
. = ALIGN(4);
. = ALIGN(4);
.got : { *(.got) }
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
- . = ALIGN(4);
+ . = align(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
+
+ . = align(4);
.mmudata : { *(.mmudata) }
. = ALIGN(4);
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
+++ /dev/null
-The port was tested on Wind River System Sbc8560 board
-<www.windriver.com>. U-Boot was installed on the flash memory of the
-CPU card (no the SODIMM).
-
-NOTE: Please configure uboot compile to the proper PCI frequency and
-setup the appropriate DIP switch settings.
-
-SBC8560 board:
-
-Make sure boards switches are set to their appropriate conditions.
-Refer to the Engineering Reference Guide ERG-00300-002. Of particular
-importance are: 1) the settings for JP4 (JP4 1-3 and 2-4), which
-select the on-board FLASH device (Intel 28F128Jx); 2) The settings
-for the Clock SW9 (33 MHz or 66 MHz).
-
- Note: SW9 Settings: 66 MHz
- 4:1 ratio CCB clocks:SYSCLK
- 3:1 ration e500 Core:CCB
- pos1 - on, pos2 - on, pos3 - off, pos4 - on, pos5 - off, pos6 - on
- Note: SW9 Settings: 33 MHz
- 8:1 ratio CCB clocks:SYSCLK
- 3:1 ration e500 Core:CCB
- pos1 - on, pos2 - on, pos3 - on, pos4 - off, pos5 - off, pos6 - on
-
-
-Flashing the FLASH device with the "Wind River ICE":
-
-1) Properly connect and configure the Wind River ICE to the target
- JTAG port. This includes running the SBC8560 register script. Make
- sure target memory can be read and written.
-
-2) Build the u-boot image:
- make distclean
- make SBC8560_66_config or SBC8560_33_config
- make CROSS_COMPILE=.../ELDK3.0/ppc_8xx-/ all
-
- Note: reference is made to the ELDK3.0 compiler. Further, it seems
- the ppc_8xx compiler is required for the 85xx (no 85xx
- designated compiler in ELDK3.0)
-
-3) Convert the uboot (.elf) file to a uboot.bin file (using
- visionClick converter). The bin file should be converted from
- fffc0000 to ffffffff
-
-4) Setup the Flash Utility (tools menu) for:
-
- Do a "dc clr" [visionClick] to load the default register settings
- Determine the clock speed of the PCI bus and set SW9 accordingly
- Note: the speed of the PCI bus defaults to the slowest PCI card
- PlayBack the "default" register file for the SBC8560
- Select the uboot.bin file with zero bias
- Select the initialize Target prior to programming
- Select the V28F640Jx (8192 x 8) 1 device FLASH Algorithm
- Select the erase base address from FFFC0000 to FFFFFFFF
- Select the start address from 0 with size of 4000
-
-5) Erase and Program
+++ /dev/null
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- /*
- * Factors to consider for CPO:
- * - frequency
- * - ddr1 vs. ddr2
- */
- popts->cpo_override = 0;
-
- /*
- * Factors to consider for write data delay:
- * - number of DIMMs
- *
- * 1 = 1/4 clock delay
- * 2 = 1/2 clock delay
- * 3 = 3/4 clock delay
- * 4 = 1 clock delay
- * 5 = 5/4 clock delay
- * 6 = 3/2 clock delay
- */
- popts->write_data_delay = 3;
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-}
+++ /dev/null
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/* LAW(Local Access Window) configuration:
- * 0000_0000-0800_0000: DDR(512M) -or- larger
- * c000_0000-cfff_ffff: PCI(256M)
- * d000_0000-dfff_ffff: RapidIO(256M)
- * e000_0000-ffff_ffff: localbus(512M)
- * e000_0000-e3ff_ffff: LBC 64M, 32-bit flash on CS6
- * e400_0000-e7ff_ffff: LBC 64M, 32-bit flash on CS1
- * e800_0000-efff_ffff: LBC 128M, nothing here
- * f000_0000-f3ff_ffff: LBC 64M, SDRAM on CS3
- * f400_0000-f7ff_ffff: LBC 64M, SDRAM on CS4
- * f800_0000-fdff_ffff: LBC 64M, nothing here
- * fc00_0000-fcff_ffff: LBC 16M, CSR,RTC,UART,etc on CS5
- * fd00_0000-fdff_ffff: LBC 16M, nothing here
- * fe00_0000-feff_ffff: LBC 16M, nothing here
- * ff00_0000-ff6f_ffff: LBC 7M, nothing here
- * ff70_0000-ff7f_ffff: CCSRBAR 1M
- * ff80_0000-ffff_ffff: LBC 8M, 8-bit flash on CS0
- * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
- * Window.
- * Note: If flash is 8M at default position(last 8M),no LAW needed.
- */
-
-struct law_entry law_table[] = {
-#ifndef CONFIG_SPD_EEPROM
- SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
-#endif
- SET_LAW(CONFIG_SYS_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
- SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_LBC),
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
+++ /dev/null
-/*
- * (C) Copyright 2003,Motorola Inc.
- * Xianghua Xiao, (X.Xiao@motorola.com)
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
- * Added support for Wind River SBC8560 board
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <ioports.h>
-#include <spd_sdram.h>
-#include <miiphy.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
- /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
- /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
- /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
- /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
- /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
- /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
- /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
- /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
- /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
- /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
- /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
- /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
- /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
- /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
- /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
- /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
- /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
- /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
- /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
- /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
- /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
- /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
- /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
- /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
- /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
- /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
- /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
- /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
- /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
- /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
- /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
- /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
- /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
- /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
- /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
- /* PC15 */ { 1, 1, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
- /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
- /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
- /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
- /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
- /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
- /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
- /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
- /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 RTS */
- /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
- /* PD27 */ { 1, 1, 1, 1, 0, 0 }, /* SCC2 TxD */
- /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 RTS */
- /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
- /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
- /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-int board_early_init_f (void)
-{
-#if defined(CONFIG_PCI)
- volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
-
- pci->peer &= 0xfffffffdf; /* disable master abort */
-#endif
- return 0;
-}
-
-void reset_phy (void)
-{
-#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
- volatile unsigned char *bcsr = (unsigned char *) CONFIG_SYS_BCSR;
-#endif
- /* reset Giga bit Ethernet port if needed here */
-
- /* reset the CPM FEC port */
-#if (CONFIG_ETHER_INDEX == 2)
- bcsr[0] &= ~0x20;
- udelay(2);
- bcsr[0] |= 0x20;
- udelay(1000);
-#elif (CONFIG_ETHER_INDEX == 3)
- bcsr[0] &= ~0x10;
- udelay(2);
- bcsr[0] |= 0x10;
- udelay(1000);
-#endif
-#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
- /* reset PHY */
- miiphy_reset("FCC1", 0x0);
-
- /* change PHY address to 0x02 */
- bb_miiphy_write(NULL, 0, MII_MIPSCR, 0xf028);
-
- bb_miiphy_write(NULL, 0x02, MII_BMCR,
- BMCR_ANENABLE | BMCR_ANRESTART);
-#endif /* CONFIG_MII */
-}
-
-int checkboard (void)
-{
- sys_info_t sysinfo;
- char buf[32];
-
- get_sys_info (&sysinfo);
-
-#ifdef CONFIG_SBC8560
- printf ("Board: Wind River SBC8560 Board\n");
-#else
- printf ("Board: Wind River SBC8540 Board\n");
-#endif
- printf ("\tCPU: %s MHz\n", strmhz(buf, sysinfo.freqProcessor[0]));
- printf ("\tCCB: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus));
- printf ("\tDDR: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus/2));
- if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
- || (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) {
- printf ("\tLBC: %s MHz\n",
- strmhz(buf, sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f)));
- } else {
- printf("\tLBC: unknown\n");
- }
- printf("\tCPM: %s MHz\n", strmhz(buf, sysinfo.freqSystemBus));
- printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
- return (0);
-}
-
-
-#if defined(CONFIG_SYS_DRAM_TEST)
-int testdram (void)
-{
- uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
- uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
- uint *p;
-
- printf("SDRAM test phase 1:\n");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("SDRAM test phase 2:\n");
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("SDRAM test passed.\n");
- return 0;
-}
-#endif
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-phys_size_t fixed_sdram(void)
-{
-
-#define CONFIG_SYS_DDR_CONTROL 0xc2000000
-
- #ifndef CONFIG_SYS_RAMBOOT
- volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
-
-#if (CONFIG_SYS_SDRAM_SIZE == 512)
- ddr->cs0_bnds = 0x0000000f;
-#else
- ddr->cs0_bnds = 0x00000007;
-#endif
- ddr->cs1_bnds = 0x0010001f;
- ddr->cs2_bnds = 0x00000000;
- ddr->cs3_bnds = 0x00000000;
- ddr->cs0_config = 0x80000102;
- ddr->cs1_config = 0x80000102;
- ddr->cs2_config = 0x00000000;
- ddr->cs3_config = 0x00000000;
- ddr->timing_cfg_1 = 0x37334321;
- ddr->timing_cfg_2 = 0x00000800;
- ddr->sdram_cfg = 0x42000000;
- ddr->sdram_mode = 0x00000022;
- ddr->sdram_interval = 0x05200100;
- ddr->err_sbe = 0x00ff0000;
- #if defined (CONFIG_DDR_ECC)
- ddr->err_disable = 0x0000000D;
- #endif
- asm("sync;isync;msync");
- udelay(500);
- #if defined (CONFIG_DDR_ECC)
- /* Enable ECC checking */
- ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
- #else
- ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
- #endif
- asm("sync; isync; msync");
- udelay(500);
- #endif
- return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
-}
-#endif /* !defined(CONFIG_SPD_EEPROM) */
-
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
-{
- int node;
-#ifdef CONFIG_PCI
- const char *path;
-#endif
-
- ft_cpu_setup(blob, bd);
-
- node = fdt_path_offset(blob, "/aliases");
- if (node >= 0) {
-#ifdef CONFIG_PCI
- path = fdt_getprop(blob, node, "pci0", NULL);
- if (path) {
- tmp[1] = hose.last_busno - hose.first_busno;
- do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
- }
-#endif
- }
-}
-#endif
+++ /dev/null
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-/* TLB for CCSRBAR (IMMR) */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
-/* TLB for Local Bus stuff, just map the whole 512M */
-/* note that the LBC SDRAM is cache-inhibit and guarded, like everything else */
-
- SET_TLB_ENTRY(1, 0xe0000000, 0xe0000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY(1, 0xf0000000, 0xf0000000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_256M, 1),
-
-#if !defined(CONFIG_SPD_EEPROM)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 4, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 5, BOOKE_PAGESZ_256M, 1),
-#endif
-
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 6, BOOKE_PAGESZ_16K, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_256M, 1),
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
- return omap_ehci_hcd_init(&usbhs_bdata);
+ return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
}
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return omap_ehci_hcd_stop();
}
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
- return omap_ehci_hcd_init(&usbhs_bdata);
+ return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
}
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return omap_ehci_hcd_stop();
}
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED
};
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
- return omap_ehci_hcd_init(&usbhs_bdata);
+ return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
}
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return omap_ehci_hcd_stop();
}
******************************************************************/
void ether_init (void)
{
-#ifdef CONFIG_DRIVER_LAN91C96
+#ifdef CONFIG_LAN91C96
int cnt = 20;
__raw_writeb(0x3,OMAP2420_CTRL_BASE+0x10a); /*protect->gpio95 */
*********************************************************************/
void display_board_info(u32 btype)
{
- char cpu_2420[] = "2420"; /* cpu type */
- char cpu_2422[] = "2422";
- char cpu_2423[] = "2423";
- char db_men[] = "Menelaus"; /* board type */
- char db_ip[] = "IP";
- char mem_sdr[] = "mSDR"; /* memory type */
- char mem_ddr[] = "mDDR";
- char t_tst[] = "TST"; /* security level */
- char t_emu[] = "EMU";
- char t_hs[] = "HS";
- char t_gp[] = "GP";
- char unk[] = "?";
-
- char *cpu_s, *db_s, *mem_s, *sec_s;
+ static const char cpu_2420 [] = "2420"; /* cpu type */
+ static const char cpu_2422 [] = "2422";
+ static const char cpu_2423 [] = "2423";
+ static const char db_men [] = "Menelaus"; /* board type */
+ static const char db_ip [] = "IP";
+ static const char mem_sdr [] = "mSDR"; /* memory type */
+ static const char mem_ddr [] = "mDDR";
+ static const char t_tst [] = "TST"; /* security level */
+ static const char t_emu [] = "EMU";
+ static const char t_hs [] = "HS";
+ static const char t_gp [] = "GP";
+ static const char unk [] = "?";
+
+ const char *cpu_s, *db_s, *mem_s, *sec_s;
u32 cpu, rev, sec;
rev = get_cpu_rev();
.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
};
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
int ret;
unsigned int utmi_clk;
utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
sr32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, 0, 32, utmi_clk);
- ret = omap_ehci_hcd_init(&usbhs_bdata);
+ ret = omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor);
if (ret < 0)
return ret;
return 0;
}
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return omap_ehci_hcd_stop();
}
DECLARE_GLOBAL_DATA_PTR;
-struct serial_device *default_serial_console(void)
-{
- return &serial_ffuart_device;
-}
-
int board_init(void)
{
/* We have RAM, disable cache */
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
int board_late_init(void)
{
-#if defined(CONFIG_SERIAL_MULTI)
char *console=getenv("boot_console");
if ((console == NULL) || (strcmp(console,"serial_btuart") &&
setenv("stdout",console);
setenv("stdin", console);
setenv("stderr",console);
-#endif
return 0;
}
-struct serial_device *default_serial_console (void)
-{
- return &serial_ffuart_device;
-}
-
int dram_init(void)
{
pxa2xx_dram_init();
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
*(.data)
}
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
+
. = ALIGN(4);
.rel.dyn : {
return 0;
}
-struct serial_device *default_serial_console(void)
-{
- return &serial_ffuart_device;
-}
-
int dram_init(void)
{
#ifndef CONFIG_ONENAND
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
unsigned long get_dram_size (void);
void sdram_init(void);
-/*
- * Macros to transform values
- * into environment strings.
- */
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
/* ------------------------------------------------------------------------- */
int board_early_init_f (void)
/* Set 'ethaddr' envvar if 'ethaddr' envvar is the default */
eth = (char *)(vpd->ethAddrs[0]);
if (ethaddr
- && (strcmp (ethaddr, MK_STR (CONFIG_ETHADDR)) == 0)) {
+ && (strcmp(ethaddr, __stringify(CONFIG_ETHADDR)) == 0)) {
/* Now setup ethaddr */
sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
eth[0], eth[1], eth[2], eth[3], eth[4],
PROVIDE (edata = .);
. = .;
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
_edata = .;
PROVIDE (edata = .);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
__start___ex_table = .;
#define REBOOT_DO_POST 0x00000001
extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-extern env_t *env_ptr;
ulong flash_get_size(ulong base, int banknum);
void env_crc_update(void);
return 0;
}
-struct serial_device *default_serial_console (void)
-{
- return &serial_stuart_device;
-}
-
int dram_init(void)
{
pxa2xx_dram_init();
ima3-mx53 arm armv7 ima3-mx53 esg mx5 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg
vision2 arm armv7 vision2 ttcontrol mx5 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg
mx6qarm2 arm armv7 mx6qarm2 freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg
-mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/mx6qsabrelite/imximage.cfg
+mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg
+mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+mx6qsabresd arm armv7 mx6qsabresd freescale mx6 mx6qsabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
cm_t35 arm armv7 cm_t35 - omap3
omap3_overo arm armv7 overo - omap3
omap3_pandora arm armv7 pandora - omap3
pdnb3 arm ixp pdnb3 prodrive
scpu arm ixp pdnb3 prodrive - pdnb3:SCPU
balloon3 arm pxa
+h2200 arm pxa
lubbock arm pxa
palmld arm pxa
palmtc arm pxa
colibri_pxa270 arm pxa - toradex
jornada arm sa1100
plutux arm armv7:arm720t plutux avionic-design tegra20
-medcom arm armv7:arm720t medcom avionic-design tegra20
+medcom-wide arm armv7:arm720t medcom-wide avionic-design tegra20
tec arm armv7:arm720t tec avionic-design tegra20
paz00 arm armv7:arm720t paz00 compal tegra20
trimslice arm armv7:arm720t trimslice compulab tegra20
microblaze-generic microblaze microblaze microblaze-generic xilinx
qemu_mips mips mips32 qemu-mips - - qemu-mips:SYS_BIG_ENDIAN
qemu_mipsel mips mips32 qemu-mips - - qemu-mips:SYS_LITTLE_ENDIAN
+qemu_mips64 mips mips64 qemu-mips - - qemu-mips64:SYS_BIG_ENDIAN
+qemu_mips64el mips mips64 qemu-mips - - qemu-mips64:SYS_LITTLE_ENDIAN
vct_platinum mips mips32 vct micronas - vct:VCT_PLATINUM
vct_platinumavc mips mips32 vct micronas - vct:VCT_PLATINUMAVC
vct_platinumavc_onenand mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND
dbau1500 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1500
dbau1550 mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1550
dbau1550_el mips mips32 dbau1x00 - au1x00 dbau1x00:DBAU1550,SYS_LITTLE_ENDIAN
-gth2 mips mips32 - - au1x00
pb1000 mips mips32 pb1x00 - au1x00 pb1x00:PB1000
incaip mips mips32 incaip - incaip
incaip_100MHz mips mips32 incaip - incaip incaip:CPU_CLOCK_RATE=100000000
sorcery powerpc mpc8220
Yukon8220 powerpc mpc8220 alaska
A3000 powerpc mpc824x a3000
-BMW powerpc mpc824x bmw
CPC45 powerpc mpc824x cpc45 - - CPC45
CPC45_ROMBOOT powerpc mpc824x cpc45 - - CPC45:BOOT_ROM
CU824 powerpc mpc824x cu824
tuge1 powerpc mpc83xx km83xx keymile - tuxx1:KM_DISABLE_APP2,TUGE1
tuxx1 powerpc mpc83xx km83xx keymile
kmsupx5 powerpc mpc83xx km83xx keymile - tuxx1:KM_DISABLE_APP2,KMSUPX5
-sbc8540 powerpc mpc85xx sbc8560 - - SBC8540
-sbc8540_33 powerpc mpc85xx sbc8560 - - SBC8540
-sbc8540_66 powerpc mpc85xx sbc8560 - - SBC8540
sbc8548 powerpc mpc85xx sbc8548 - - sbc8548
sbc8548_PCI_33 powerpc mpc85xx sbc8548 - - sbc8548:PCI,33
sbc8548_PCI_33_PCIE powerpc mpc85xx sbc8548 - - sbc8548:PCI,33,PCIE
sbc8548_PCI_66 powerpc mpc85xx sbc8548 - - sbc8548:PCI,66
sbc8548_PCI_66_PCIE powerpc mpc85xx sbc8548 - - sbc8548:PCI,66,PCIE
-sbc8560 powerpc mpc85xx sbc8560 - - sbc8560
-sbc8560_33 powerpc mpc85xx sbc8560 - - sbc8560
-sbc8560_66 powerpc mpc85xx sbc8560 - - sbc8560
socrates powerpc mpc85xx socrates
HWW1U1A powerpc mpc85xx hww1u1a exmeritus
MPC8536DS powerpc mpc85xx mpc8536ds freescale - MPC8536DS
korat powerpc ppc4xx
korat_perm powerpc ppc4xx korat - - korat:KORAT_PERMANENT
lwmon5 powerpc ppc4xx
-ML2 powerpc ppc4xx ml2
pcs440ep powerpc ppc4xx
quad100hd powerpc ppc4xx
sbc405 powerpc ppc4xx
yellowstone powerpc ppc4xx yosemite amcc - yosemite:YELLOWSTONE
yosemite powerpc ppc4xx yosemite amcc - yosemite:YOSEMITE
yucca powerpc ppc4xx - amcc
-AP1000 powerpc ppc4xx ap1000 amirix
fx12mm powerpc ppc4xx fx12mm avnet - fx12mm:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,INIT_TLB=board/xilinx/ppc405-generic/init.o
fx12mm_flash powerpc ppc4xx fx12mm avnet - fx12mm:SYS_TEXT_BASE=0xF7F60000,RESET_VECTOR_ADDRESS=0xF7FFFFFC,INIT_TLB=board/xilinx/ppc405-generic/init.o
v5fx30teval powerpc ppc4xx v5fx30teval avnet - v5fx30teval:SYS_TEXT_BASE=0x04000000,RESET_VECTOR_ADDRESS=0x04100000,BOOT_FROM_XMD=1,INIT_TLB=board/xilinx/ppc440-generic/init.o
PPChameleonEVB_HI_33 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=2,PPCHAMELEON_CLK_33
PPChameleonEVB_ME_25 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_25
PPChameleonEVB_ME_33 powerpc ppc4xx PPChameleonEVB dave - PPChameleonEVB:PPCHAMELEON_MODULE_MODEL=1,PPCHAMELEON_CLK_33
-ADCIOP powerpc ppc4xx adciop esd
APC405 powerpc ppc4xx apc405 esd
AR405 powerpc ppc4xx ar405 esd
ASH405 powerpc ppc4xx ash405 esd
CPCI405AB powerpc ppc4xx cpci405 esd
CPCI405DT powerpc ppc4xx cpci405 esd
CPCIISER4 powerpc ppc4xx cpciiser4 esd
-DASA_SIM powerpc ppc4xx dasa_sim esd
DP405 powerpc ppc4xx dp405 esd
DU405 powerpc ppc4xx du405 esd
DU440 powerpc ppc4xx du440 esd
COBJS-y += exports.o
COBJS-$(CONFIG_SYS_HUSH_PARSER) += hush.o
COBJS-y += s_record.o
-COBJS-$(CONFIG_SERIAL_MULTI) += serial.o
COBJS-y += xyzModem.o
COBJS-y += cmd_disk.o
COBJS-$(CONFIG_CMD_BEDBUG) += bedbug.o cmd_bedbug.o
COBJS-$(CONFIG_CMD_BMP) += cmd_bmp.o
COBJS-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o
+COBJS-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o
COBJS-$(CONFIG_CMD_CACHE) += cmd_cache.o
+COBJS-$(CONFIG_CMD_CBFS) += cmd_cbfs.o
COBJS-$(CONFIG_CMD_CONSOLE) += cmd_console.o
COBJS-$(CONFIG_CMD_CPLBINFO) += cmd_cplbinfo.o
COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += cmd_dataflash_mmc_mux.o
$(obj)../tools/envcrc:
$(MAKE) -C ../tools
+# SEE README.arm-unaligned-accesses
+$(obj)hush.o: CFLAGS += $(PLATFORM_NO_UNALIGNED)
+$(obj)fdt_support.o: CFLAGS += $(PLATFORM_NO_UNALIGNED)
+
#########################################################################
# defines $(obj).depend target
DECLARE_GLOBAL_DATA_PTR;
-enum bootstage_flags {
- BOOTSTAGEF_ERROR = 1 << 0, /* Error record */
- BOOTSTAGEF_ALLOC = 1 << 1, /* Allocate an id */
-};
-
struct bootstage_record {
ulong time_us;
+ uint32_t start_us;
const char *name;
int flags; /* see enum bootstage_flags */
enum bootstage_id id;
static struct bootstage_record record[BOOTSTAGE_ID_COUNT] = { {1} };
static int next_id = BOOTSTAGE_ID_USER;
+enum {
+ BOOTSTAGE_VERSION = 0,
+ BOOTSTAGE_MAGIC = 0xb00757a3,
+};
+
+struct bootstage_hdr {
+ uint32_t version; /* BOOTSTAGE_VERSION */
+ uint32_t count; /* Number of records */
+ uint32_t size; /* Total data size (non-zero if valid) */
+ uint32_t magic; /* Unused */
+};
+
ulong bootstage_add_record(enum bootstage_id id, const char *name,
- int flags)
+ int flags, ulong mark)
{
struct bootstage_record *rec;
- ulong mark = timer_get_boot_us();
if (flags & BOOTSTAGEF_ALLOC)
id = next_id++;
ulong bootstage_mark(enum bootstage_id id)
{
- return bootstage_add_record(id, NULL, 0);
+ return bootstage_add_record(id, NULL, 0, timer_get_boot_us());
}
ulong bootstage_error(enum bootstage_id id)
{
- return bootstage_add_record(id, NULL, BOOTSTAGEF_ERROR);
+ return bootstage_add_record(id, NULL, BOOTSTAGEF_ERROR,
+ timer_get_boot_us());
}
ulong bootstage_mark_name(enum bootstage_id id, const char *name)
if (id == BOOTSTAGE_ID_ALLOC)
flags = BOOTSTAGEF_ALLOC;
- return bootstage_add_record(id, name, flags);
+ return bootstage_add_record(id, name, flags, timer_get_boot_us());
+}
+
+uint32_t bootstage_start(enum bootstage_id id, const char *name)
+{
+ struct bootstage_record *rec = &record[id];
+
+ rec->start_us = timer_get_boot_us();
+ rec->name = name;
+ return rec->start_us;
+}
+
+uint32_t bootstage_accum(enum bootstage_id id)
+{
+ struct bootstage_record *rec = &record[id];
+ uint32_t duration;
+
+ duration = (uint32_t)timer_get_boot_us() - rec->start_us;
+ rec->time_us += duration;
+ return duration;
}
static void print_time(unsigned long us_time)
}
}
-static uint32_t print_time_record(enum bootstage_id id,
- struct bootstage_record *rec, uint32_t prev)
+/**
+ * Get a record name as a printable string
+ *
+ * @param buf Buffer to put name if needed
+ * @param len Length of buffer
+ * @param rec Boot stage record to get the name from
+ * @return pointer to name, either from the record or pointing to buf.
+ */
+static const char *get_record_name(char *buf, int len,
+ struct bootstage_record *rec)
{
- print_time(rec->time_us);
- print_time(rec->time_us - prev);
if (rec->name)
- printf(" %s\n", rec->name);
- else if (id >= BOOTSTAGE_ID_USER)
- printf(" user_%d\n", id - BOOTSTAGE_ID_USER);
+ return rec->name;
+ else if (rec->id >= BOOTSTAGE_ID_USER)
+ snprintf(buf, len, "user_%d", rec->id - BOOTSTAGE_ID_USER);
else
- printf(" id=%d\n", id);
+ snprintf(buf, len, "id=%d", rec->id);
+
+ return buf;
+}
+
+static uint32_t print_time_record(enum bootstage_id id,
+ struct bootstage_record *rec, uint32_t prev)
+{
+ char buf[20];
+
+ if (prev == -1U) {
+ printf("%11s", "");
+ print_time(rec->time_us);
+ } else {
+ print_time(rec->time_us);
+ print_time(rec->time_us - prev);
+ }
+ printf(" %s\n", get_record_name(buf, sizeof(buf), rec));
+
return rec->time_us;
}
return rec1->time_us > rec2->time_us ? 1 : -1;
}
+#ifdef CONFIG_OF_LIBFDT
+/**
+ * Add all bootstage timings to a device tree.
+ *
+ * @param blob Device tree blob
+ * @return 0 on success, != 0 on failure.
+ */
+static int add_bootstages_devicetree(struct fdt_header *blob)
+{
+ int bootstage;
+ char buf[20];
+ int id;
+ int i;
+
+ if (!blob)
+ return 0;
+
+ /*
+ * Create the node for bootstage.
+ * The address of flat device tree is set up by the command bootm.
+ */
+ bootstage = fdt_add_subnode(blob, 0, "bootstage");
+ if (bootstage < 0)
+ return -1;
+
+ /*
+ * Insert the timings to the device tree in the reverse order so
+ * that they can be printed in the Linux kernel in the right order.
+ */
+ for (id = BOOTSTAGE_ID_COUNT - 1, i = 0; id >= 0; id--, i++) {
+ struct bootstage_record *rec = &record[id];
+ int node;
+
+ if (id != BOOTSTAGE_ID_AWAKE && rec->time_us == 0)
+ continue;
+
+ node = fdt_add_subnode(blob, bootstage, simple_itoa(i));
+ if (node < 0)
+ break;
+
+ /* add properties to the node. */
+ if (fdt_setprop_string(blob, node, "name",
+ get_record_name(buf, sizeof(buf), rec)))
+ return -1;
+
+ /* Check if this is a 'mark' or 'accum' record */
+ if (fdt_setprop_cell(blob, node,
+ rec->start_us ? "accum" : "mark",
+ rec->time_us))
+ return -1;
+ }
+
+ return 0;
+}
+
+int bootstage_fdt_add_report(void)
+{
+ if (add_bootstages_devicetree(working_fdt))
+ puts("bootstage: Failed to add to device tree\n");
+
+ return 0;
+}
+#endif
+
void bootstage_report(void)
{
struct bootstage_record *rec = record;
qsort(record, ARRAY_SIZE(record), sizeof(*rec), h_compare_record);
for (id = 0; id < BOOTSTAGE_ID_COUNT; id++, rec++) {
- if (rec->time_us != 0)
+ if (rec->time_us != 0 && !rec->start_us)
prev = print_time_record(rec->id, rec, prev);
}
if (next_id > BOOTSTAGE_ID_COUNT)
printf("(Overflowed internal boot id table by %d entries\n"
"- please increase CONFIG_BOOTSTAGE_USER_COUNT\n",
next_id - BOOTSTAGE_ID_COUNT);
+
+ puts("\nAccumulated time:\n");
+ for (id = 0, rec = record; id < BOOTSTAGE_ID_COUNT; id++, rec++) {
+ if (rec->start_us)
+ prev = print_time_record(id, rec, -1);
+ }
}
ulong __timer_get_boot_us(void)
ulong timer_get_boot_us(void)
__attribute__((weak, alias("__timer_get_boot_us")));
+
+/**
+ * Append data to a memory buffer
+ *
+ * Write data to the buffer if there is space. Whether there is space or not,
+ * the buffer pointer is incremented.
+ *
+ * @param ptrp Pointer to buffer, updated by this function
+ * @param end Pointer to end of buffer
+ * @param data Data to write to buffer
+ * @param size Size of data
+ */
+static void append_data(char **ptrp, char *end, const void *data, int size)
+{
+ char *ptr = *ptrp;
+
+ *ptrp += size;
+ if (*ptrp > end)
+ return;
+
+ memcpy(ptr, data, size);
+}
+
+int bootstage_stash(void *base, int size)
+{
+ struct bootstage_hdr *hdr = (struct bootstage_hdr *)base;
+ struct bootstage_record *rec;
+ char buf[20];
+ char *ptr = base, *end = ptr + size;
+ uint32_t count;
+ int id;
+
+ if (hdr + 1 > (struct bootstage_hdr *)end) {
+ debug("%s: Not enough space for bootstage hdr\n", __func__);
+ return -1;
+ }
+
+ /* Write an arbitrary version number */
+ hdr->version = BOOTSTAGE_VERSION;
+
+ /* Count the number of records, and write that value first */
+ for (rec = record, id = count = 0; id < BOOTSTAGE_ID_COUNT;
+ id++, rec++) {
+ if (rec->time_us != 0)
+ count++;
+ }
+ hdr->count = count;
+ hdr->size = 0;
+ hdr->magic = BOOTSTAGE_MAGIC;
+ ptr += sizeof(*hdr);
+
+ /* Write the records, silently stopping when we run out of space */
+ for (rec = record, id = 0; id < BOOTSTAGE_ID_COUNT; id++, rec++) {
+ if (rec->time_us != 0)
+ append_data(&ptr, end, rec, sizeof(*rec));
+ }
+
+ /* Write the name strings */
+ for (rec = record, id = 0; id < BOOTSTAGE_ID_COUNT; id++, rec++) {
+ if (rec->time_us != 0) {
+ const char *name;
+
+ name = get_record_name(buf, sizeof(buf), rec);
+ append_data(&ptr, end, name, strlen(name) + 1);
+ }
+ }
+
+ /* Check for buffer overflow */
+ if (ptr > end) {
+ debug("%s: Not enough space for bootstage stash\n", __func__);
+ return -1;
+ }
+
+ /* Update total data size */
+ hdr->size = ptr - (char *)base;
+ printf("Stashed %d records\n", hdr->count);
+
+ return 0;
+}
+
+int bootstage_unstash(void *base, int size)
+{
+ struct bootstage_hdr *hdr = (struct bootstage_hdr *)base;
+ struct bootstage_record *rec;
+ char *ptr = base, *end = ptr + size;
+ uint rec_size;
+ int id;
+
+ if (size == -1)
+ end = (char *)(~(uintptr_t)0);
+
+ if (hdr + 1 > (struct bootstage_hdr *)end) {
+ debug("%s: Not enough space for bootstage hdr\n", __func__);
+ return -1;
+ }
+
+ if (hdr->magic != BOOTSTAGE_MAGIC) {
+ debug("%s: Invalid bootstage magic\n", __func__);
+ return -1;
+ }
+
+ if (ptr + hdr->size > end) {
+ debug("%s: Bootstage data runs past buffer end\n", __func__);
+ return -1;
+ }
+
+ if (hdr->count * sizeof(*rec) > hdr->size) {
+ debug("%s: Bootstage has %d records needing %d bytes, but "
+ "only %d bytes is available\n", __func__, hdr->count,
+ hdr->count * sizeof(*rec), hdr->size);
+ return -1;
+ }
+
+ if (hdr->version != BOOTSTAGE_VERSION) {
+ debug("%s: Bootstage data version %#0x unrecognised\n",
+ __func__, hdr->version);
+ return -1;
+ }
+
+ if (next_id + hdr->count > BOOTSTAGE_ID_COUNT) {
+ debug("%s: Bootstage has %d records, we have space for %d\n"
+ "- please increase CONFIG_BOOTSTAGE_USER_COUNT\n",
+ __func__, hdr->count, BOOTSTAGE_ID_COUNT - next_id);
+ return -1;
+ }
+
+ ptr += sizeof(*hdr);
+
+ /* Read the records */
+ rec_size = hdr->count * sizeof(*record);
+ memcpy(record + next_id, ptr, rec_size);
+
+ /* Read the name strings */
+ ptr += rec_size;
+ for (rec = record + next_id, id = 0; id < hdr->count; id++, rec++) {
+ rec->name = ptr;
+
+ /* Assume no data corruption here */
+ ptr += strlen(ptr) + 1;
+ }
+
+ /* Mark the records as read */
+ next_id += hdr->count;
+ printf("Unstashed %d records\n", hdr->count);
+
+ return 0;
+}
}
__maybe_unused
-static void print_lnum(const char *name, u64 value)
+static void print_lnum(const char *name, unsigned long long value)
{
printf("%-12s= 0x%.8llX\n", name, value);
}
print_mhz("ethspeed", bd->bi_ethspeed);
#endif
printf("IP addr = %s\n", getenv("ipaddr"));
- printf("baudrate = %6ld bps\n", bd->bi_baudrate);
+ printf("baudrate = %6u bps\n", bd->bi_baudrate);
print_num("relocaddr", gd->relocaddr);
return 0;
}
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %ld bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", bd->bi_baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %ld bps\n", (ulong)bd->bi_baudrate);
+ printf("baudrate = %u bps\n", (ulong)bd->bi_baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %6ld bps\n", bd->bi_baudrate);
+ printf("baudrate = %6u bps\n", bd->bi_baudrate);
return 0;
}
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %ld bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", bd->bi_baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
- printf("baudrate = %d bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", bd->bi_baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
- printf("baudrate = %d bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", bd->bi_baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
- printf("baudrate = %lu bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", bd->bi_baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %d bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", bd->bi_baudrate);
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
print_num("TLB addr", gd->tlb_addr);
#endif
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %ld bps\n", (ulong)bd->bi_baudrate);
+ printf("baudrate = %u bps\n", bd->bi_baudrate);
return 0;
}
printf("ip_addr = %s\n", getenv("ipaddr"));
print_mhz("ethspeed", bd->bi_ethspeed);
#endif
- printf("baudrate = %d bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", bd->bi_baudrate);
return 0;
}
print_eth(0);
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %d bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", bd->bi_baudrate);
return 0;
}
printf("ip_addr = %s\n", getenv("ipaddr"));
#endif
- printf("baudrate = %ld bps\n", bd->bi_baudrate);
+ printf("baudrate = %u bps\n", bd->bi_baudrate);
return 0;
}
--- /dev/null
+/*
+ * Copyright (c) 2012, Google Inc. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+
+#ifndef CONFIG_BOOTSTAGE_STASH
+#define CONFIG_BOOTSTAGE_STASH -1UL
+#define CONFIG_BOOTSTAGE_STASH_SIZE -1
+#endif
+
+static int do_bootstage_report(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ bootstage_report();
+
+ return 0;
+}
+
+static int get_base_size(int argc, char * const argv[], ulong *basep,
+ ulong *sizep)
+{
+ char *endp;
+
+ *basep = CONFIG_BOOTSTAGE_STASH;
+ *sizep = CONFIG_BOOTSTAGE_STASH_SIZE;
+ if (argc < 2)
+ return 0;
+ *basep = simple_strtoul(argv[1], &endp, 16);
+ if (*argv[1] == 0 || *endp != 0)
+ return -1;
+ if (argc == 2)
+ return 0;
+ *sizep = simple_strtoul(argv[2], &endp, 16);
+ if (*argv[2] == 0 || *endp != 0)
+ return -1;
+
+ return 0;
+}
+
+static int do_bootstage_stash(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ ulong base, size;
+ int ret;
+
+ if (get_base_size(argc, argv, &base, &size))
+ return CMD_RET_USAGE;
+ if (base == -1UL) {
+ printf("No bootstage stash area defined\n");
+ return 1;
+ }
+
+ if (0 == strcmp(argv[0], "stash"))
+ ret = bootstage_stash((void *)base, size);
+ else
+ ret = bootstage_unstash((void *)base, size);
+ if (ret)
+ return 1;
+
+ return 0;
+}
+
+static cmd_tbl_t cmd_bootstage_sub[] = {
+ U_BOOT_CMD_MKENT(report, 2, 1, do_bootstage_report, "", ""),
+ U_BOOT_CMD_MKENT(stash, 4, 0, do_bootstage_stash, "", ""),
+ U_BOOT_CMD_MKENT(unstash, 4, 0, do_bootstage_stash, "", ""),
+};
+
+/*
+ * Process a bootstage sub-command
+ */
+static int do_boostage(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ cmd_tbl_t *c;
+
+ /* Strip off leading 'bootstage' command argument */
+ argc--;
+ argv++;
+
+ c = find_cmd_tbl(argv[0], cmd_bootstage_sub,
+ ARRAY_SIZE(cmd_bootstage_sub));
+
+ if (c)
+ return c->cmd(cmdtp, flag, argc, argv);
+ else
+ return CMD_RET_USAGE;
+}
+
+
+U_BOOT_CMD(bootstage, 4, 1, do_boostage,
+ "Boot stage command",
+ " - check boot progress and timing\n"
+ "report - Print a report\n"
+ "stash [<start> [<size>]] - Stash data into memory\n"
+ "unstash [<start> [<size>]] - Unstash data from memory"
+);
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * CBFS commands
+ */
+#include <common.h>
+#include <command.h>
+#include <cbfs.h>
+
+int do_cbfs_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ uintptr_t end_of_rom = 0xffffffff;
+ char *ep;
+
+ if (argc > 2) {
+ printf("usage: cbfsls [end of rom]>\n");
+ return 0;
+ }
+ if (argc == 2) {
+ end_of_rom = (int)simple_strtoul(argv[1], &ep, 16);
+ if (*ep) {
+ puts("\n** Invalid end of ROM **\n");
+ return 1;
+ }
+ }
+ file_cbfs_init(end_of_rom);
+ if (file_cbfs_result != CBFS_SUCCESS) {
+ printf("%s.\n", file_cbfs_error());
+ return 1;
+ }
+ return 0;
+}
+
+U_BOOT_CMD(
+ cbfsinit, 2, 0, do_cbfs_init,
+ "initialize the cbfs driver",
+ "[end of rom]\n"
+ " - Initialize the cbfs driver. The optional 'end of rom'\n"
+ " parameter specifies where the end of the ROM is that the\n"
+ " CBFS is in. It defaults to 0xFFFFFFFF\n"
+);
+
+int do_cbfs_fsload(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ const struct cbfs_cachenode *file;
+ unsigned long offset;
+ unsigned long count;
+ char buf[12];
+ long size;
+
+ if (argc < 3) {
+ printf("usage: cbfsload <addr> <filename> [bytes]\n");
+ return 1;
+ }
+
+ /* parse offset and count */
+ offset = simple_strtoul(argv[1], NULL, 16);
+ if (argc == 4)
+ count = simple_strtoul(argv[3], NULL, 16);
+ else
+ count = 0;
+
+ file = file_cbfs_find(argv[2]);
+ if (!file) {
+ if (file_cbfs_result == CBFS_FILE_NOT_FOUND)
+ printf("%s: %s\n", file_cbfs_error(), argv[2]);
+ else
+ printf("%s.\n", file_cbfs_error());
+ return 1;
+ }
+
+ printf("reading %s\n", file_cbfs_name(file));
+
+ size = file_cbfs_read(file, (void *)offset, count);
+
+ printf("\n%ld bytes read\n", size);
+
+ sprintf(buf, "%lX", size);
+ setenv("filesize", buf);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ cbfsload, 4, 0, do_cbfs_fsload,
+ "load binary file from a cbfs filesystem",
+ "<addr> <filename> [bytes]\n"
+ " - load binary file 'filename' from the cbfs to address 'addr'\n"
+);
+
+int do_cbfs_ls(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ const struct cbfs_cachenode *file = file_cbfs_get_first();
+ int files = 0;
+
+ if (!file) {
+ printf("%s.\n", file_cbfs_error());
+ return 1;
+ }
+
+ printf(" size type name\n");
+ printf("------------------------------------------\n");
+ while (file) {
+ u32 type = file_cbfs_type(file);
+ char *type_name = NULL;
+ const char *filename = file_cbfs_name(file);
+
+ printf(" %8d", file_cbfs_size(file));
+
+ switch (type) {
+ case CBFS_TYPE_STAGE:
+ type_name = "stage";
+ break;
+ case CBFS_TYPE_PAYLOAD:
+ type_name = "payload";
+ break;
+ case CBFS_TYPE_OPTIONROM:
+ type_name = "option rom";
+ break;
+ case CBFS_TYPE_BOOTSPLASH:
+ type_name = "boot splash";
+ break;
+ case CBFS_TYPE_RAW:
+ type_name = "raw";
+ break;
+ case CBFS_TYPE_VSA:
+ type_name = "vsa";
+ break;
+ case CBFS_TYPE_MBI:
+ type_name = "mbi";
+ break;
+ case CBFS_TYPE_MICROCODE:
+ type_name = "microcode";
+ break;
+ case CBFS_COMPONENT_CMOS_DEFAULT:
+ type_name = "cmos default";
+ break;
+ case CBFS_COMPONENT_CMOS_LAYOUT:
+ type_name = "cmos layout";
+ break;
+ case -1UL:
+ type_name = "null";
+ break;
+ }
+ if (type_name)
+ printf(" %16s", type_name);
+ else
+ printf(" %16d", type);
+
+ if (filename[0])
+ printf(" %s\n", filename);
+ else
+ printf(" %s\n", "(empty)");
+ file_cbfs_get_next(&file);
+ files++;
+ }
+
+ printf("\n%d file(s)\n\n", files);
+ return 0;
+}
+
+U_BOOT_CMD(
+ cbfsls, 1, 1, do_cbfs_ls,
+ "list files",
+ " - list the files in the cbfs\n"
+);
+
+int do_cbfs_fsinfo(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ const struct cbfs_header *header = file_cbfs_get_header();
+
+ if (!header) {
+ printf("%s.\n", file_cbfs_error());
+ return 1;
+ }
+
+ printf("\n");
+ printf("CBFS version: %#x\n", header->version);
+ printf("ROM size: %#x\n", header->rom_size);
+ printf("Boot block size: %#x\n", header->boot_block_size);
+ printf("CBFS size: %#x\n",
+ header->rom_size - header->boot_block_size - header->offset);
+ printf("Alignment: %d\n", header->align);
+ printf("Offset: %#x\n", header->offset);
+ printf("\n");
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ cbfsinfo, 1, 1, do_cbfs_fsinfo,
+ "print information about filesystem",
+ " - print information about the cbfs filesystem\n"
+);
static int do_dfu(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
const char *str_env;
- char s[] = "dfu";
+ char *s = "dfu";
char *env_bkp;
int ret;
DECLARE_GLOBAL_DATA_PTR;
#endif
-int valid_elf_image (unsigned long addr);
static unsigned long load_elf_image_phdr(unsigned long addr);
static unsigned long load_elf_image_shdr(unsigned long addr);
/* Allow ports to override the default behavior */
__attribute__((weak))
-unsigned long do_bootelf_exec (ulong (*entry)(int, char * const[]),
+unsigned long do_bootelf_exec(ulong (*entry)(int, char * const[]),
int argc, char * const argv[])
{
unsigned long ret;
* QNX images require the data cache is disabled.
* Data cache is already flushed, so just turn it off.
*/
- int dcache = dcache_status ();
+ int dcache = dcache_status();
if (dcache)
- dcache_disable ();
+ dcache_disable();
/*
* pass address parameter as argv[0] (aka command name),
* and all remaining args
*/
- ret = entry (argc, argv);
+ ret = entry(argc, argv);
if (dcache)
- dcache_enable ();
+ dcache_enable();
return ret;
}
+/* ======================================================================
+ * Determine if a valid ELF image exists at the given memory location.
+ * First looks at the ELF header magic field, the makes sure that it is
+ * executable and makes sure that it is for a PowerPC.
+ * ====================================================================== */
+int valid_elf_image(unsigned long addr)
+{
+ Elf32_Ehdr *ehdr; /* Elf header structure pointer */
+
+ /* -------------------------------------------------- */
+
+ ehdr = (Elf32_Ehdr *) addr;
+
+ if (!IS_ELF(*ehdr)) {
+ printf("## No elf image at address 0x%08lx\n", addr);
+ return 0;
+ }
+
+ if (ehdr->e_type != ET_EXEC) {
+ printf("## Not a 32-bit elf image at address 0x%08lx\n", addr);
+ return 0;
+ }
+
+#if 0
+ if (ehdr->e_machine != EM_PPC) {
+ printf("## Not a PowerPC elf image at address 0x%08lx\n", addr);
+ return 0;
+ }
+#endif
+
+ return 1;
+}
+
/* ======================================================================
* Interpreter command to boot an arbitrary ELF image from memory.
* ====================================================================== */
-int do_bootelf (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_bootelf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned long addr; /* Address of the ELF image */
unsigned long rc; /* Return value from user code */
else
addr = load_addr;
- if (!valid_elf_image (addr))
+ if (!valid_elf_image(addr))
return 1;
if (sload && sload[1] == 'p')
else
addr = load_elf_image_shdr(addr);
- printf ("## Starting application at 0x%08lx ...\n", addr);
+ printf("## Starting application at 0x%08lx ...\n", addr);
/*
* pass address parameter as argv[0] (aka command name),
* and all remaining args
*/
- rc = do_bootelf_exec ((void *)addr, argc - 1, argv + 1);
+ rc = do_bootelf_exec((void *)addr, argc - 1, argv + 1);
if (rc != 0)
rcode = 1;
- printf ("## Application terminated, rc = 0x%lx\n", rc);
+ printf("## Application terminated, rc = 0x%lx\n", rc);
return rcode;
}
* be either an ELF image or a raw binary. Will attempt to setup the
* bootline and other parameters correctly.
* ====================================================================== */
-int do_bootvx (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned long addr; /* Address of image */
- unsigned long bootaddr; /* Address to put the bootline */
+ unsigned long bootaddr; /* Address to put the bootline */
char *bootline; /* Text of the bootline */
char *tmp; /* Temporary char pointer */
char build_buf[128]; /* Buffer for building the bootline */
if (argc < 2)
addr = load_addr;
else
- addr = simple_strtoul (argv[1], NULL, 16);
+ addr = simple_strtoul(argv[1], NULL, 16);
#if defined(CONFIG_CMD_NET)
- /* Check to see if we need to tftp the image ourselves before starting */
-
- if ((argc == 2) && (strcmp (argv[1], "tftp") == 0)) {
+ /*
+ * Check to see if we need to tftp the image ourselves before starting
+ */
+ if ((argc == 2) && (strcmp(argv[1], "tftp") == 0)) {
if (NetLoop(TFTPGET) <= 0)
return 1;
- printf("Automatic boot of VxWorks image at address 0x%08lx "
- "...\n", addr);
+ printf("Automatic boot of VxWorks image at address 0x%08lx ...\n",
+ addr);
}
#endif
eth_getenv_enetaddr("ethaddr", (uchar *)build_buf);
memcpy(tmp, build_buf, 6);
#else
- puts ("## Ethernet MAC address not copied to NV RAM\n");
+ puts("## Ethernet MAC address not copied to NV RAM\n");
#endif
/*
* PowerPC is LOCAL_MEM_LOCAL_ADRS + BOOT_LINE_OFFSET which
* defaults to 0x4200
*/
-
- if ((tmp = getenv ("bootaddr")) == NULL)
+ tmp = getenv("bootaddr");
+ if (tmp)
bootaddr = CONFIG_SYS_VXWORKS_BOOT_ADDR;
else
- bootaddr = simple_strtoul (tmp, NULL, 16);
+ bootaddr = simple_strtoul(tmp, NULL, 16);
/*
* Check to see if the bootline is defined in the 'bootargs'
* parameter. If it is not defined, we may be able to
* construct the info
*/
-
- if ((bootline = getenv ("bootargs")) != NULL) {
- memcpy ((void *) bootaddr, bootline,
- max (strlen (bootline), 255));
- flush_cache (bootaddr, max (strlen (bootline), 255));
+ bootline = getenv("bootargs");
+ if (bootline) {
+ memcpy((void *) bootaddr, bootline,
+ max(strlen(bootline), 255));
+ flush_cache(bootaddr, max(strlen(bootline), 255));
} else {
-
-
- sprintf (build_buf, CONFIG_SYS_VXWORKS_BOOT_DEVICE);
- if ((tmp = getenv ("bootfile")) != NULL) {
- sprintf (&build_buf[strlen (build_buf)],
+ sprintf(build_buf, CONFIG_SYS_VXWORKS_BOOT_DEVICE);
+ tmp = getenv("bootfile");
+ if (tmp)
+ sprintf(&build_buf[strlen(build_buf)],
"%s:%s ", CONFIG_SYS_VXWORKS_SERVERNAME, tmp);
- } else {
- sprintf (&build_buf[strlen (build_buf)],
+ else
+ sprintf(&build_buf[strlen(build_buf)],
"%s:file ", CONFIG_SYS_VXWORKS_SERVERNAME);
- }
- if ((tmp = getenv ("ipaddr")) != NULL) {
- sprintf (&build_buf[strlen (build_buf)], "e=%s ", tmp);
- }
+ tmp = getenv("ipaddr");
+ if (tmp)
+ sprintf(&build_buf[strlen(build_buf)], "e=%s ", tmp);
- if ((tmp = getenv ("serverip")) != NULL) {
- sprintf (&build_buf[strlen (build_buf)], "h=%s ", tmp);
- }
+ tmp = getenv("serverip");
+ if (tmp)
+ sprintf(&build_buf[strlen(build_buf)], "h=%s ", tmp);
+
+ tmp = getenv("hostname");
+ if (tmp)
+ sprintf(&build_buf[strlen(build_buf)], "tn=%s ", tmp);
- if ((tmp = getenv ("hostname")) != NULL) {
- sprintf (&build_buf[strlen (build_buf)], "tn=%s ", tmp);
- }
#ifdef CONFIG_SYS_VXWORKS_ADD_PARAMS
- sprintf (&build_buf[strlen (build_buf)],
+ sprintf(&build_buf[strlen(build_buf)],
CONFIG_SYS_VXWORKS_ADD_PARAMS);
#endif
- memcpy ((void *) bootaddr, build_buf,
- max (strlen (build_buf), 255));
- flush_cache (bootaddr, max (strlen (build_buf), 255));
+ memcpy((void *) bootaddr, build_buf,
+ max(strlen(build_buf), 255));
+ flush_cache(bootaddr, max(strlen(build_buf), 255));
}
/*
* binary image
*/
- if (valid_elf_image (addr)) {
- addr = load_elf_image_shdr (addr);
+ if (valid_elf_image(addr)) {
+ addr = load_elf_image_shdr(addr);
} else {
- puts ("## Not an ELF image, assuming binary\n");
+ puts("## Not an ELF image, assuming binary\n");
/* leave addr as load_addr */
}
- printf ("## Using bootline (@ 0x%lx): %s\n", bootaddr,
+ printf("## Using bootline (@ 0x%lx): %s\n", bootaddr,
(char *) bootaddr);
- printf ("## Starting vxWorks at 0x%08lx ...\n", addr);
+ printf("## Starting vxWorks at 0x%08lx ...\n", addr);
dcache_disable();
((void (*)(int)) addr) (0);
- puts ("## vxWorks terminated\n");
- return 1;
-}
-
-/* ======================================================================
- * Determine if a valid ELF image exists at the given memory location.
- * First looks at the ELF header magic field, the makes sure that it is
- * executable and makes sure that it is for a PowerPC.
- * ====================================================================== */
-int valid_elf_image (unsigned long addr)
-{
- Elf32_Ehdr *ehdr; /* Elf header structure pointer */
-
- /* -------------------------------------------------- */
-
- ehdr = (Elf32_Ehdr *) addr;
-
- if (!IS_ELF (*ehdr)) {
- printf ("## No elf image at address 0x%08lx\n", addr);
- return 0;
- }
-
- if (ehdr->e_type != ET_EXEC) {
- printf ("## Not a 32-bit elf image at address 0x%08lx\n", addr);
- return 0;
- }
-
-#if 0
- if (ehdr->e_machine != EM_PPC) {
- printf ("## Not a PowerPC elf image at address 0x%08lx\n",
- addr);
- return 0;
- }
-#endif
-
+ puts("## vxWorks terminated\n");
return 1;
}
/* Load each program header */
for (i = 0; i < ehdr->e_phnum; ++i) {
- void *dst = (void *) phdr->p_paddr;
+ void *dst = (void *)(uintptr_t) phdr->p_paddr;
void *src = (void *) addr + phdr->p_offset;
debug("Loading phdr %i to 0x%p (%i bytes)\n",
i, dst, phdr->p_filesz);
if (phdr->p_filesz)
memcpy(dst, src, phdr->p_filesz);
if (phdr->p_filesz != phdr->p_memsz)
- memset(dst + phdr->p_filesz, 0x00, phdr->p_memsz - phdr->p_filesz);
+ memset(dst + phdr->p_filesz, 0x00,
+ phdr->p_memsz - phdr->p_filesz);
flush_cache((unsigned long)dst, phdr->p_filesz);
++phdr;
}
/* Find the section header string table for output info */
shdr = (Elf32_Shdr *) (addr + ehdr->e_shoff +
- (ehdr->e_shstrndx * sizeof (Elf32_Shdr)));
+ (ehdr->e_shstrndx * sizeof(Elf32_Shdr)));
if (shdr->sh_type == SHT_STRTAB)
strtab = (unsigned char *) (addr + shdr->sh_offset);
/* Load each appropriate section */
for (i = 0; i < ehdr->e_shnum; ++i) {
shdr = (Elf32_Shdr *) (addr + ehdr->e_shoff +
- (i * sizeof (Elf32_Shdr)));
+ (i * sizeof(Elf32_Shdr)));
if (!(shdr->sh_flags & SHF_ALLOC)
|| shdr->sh_addr == 0 || shdr->sh_size == 0) {
}
if (shdr->sh_type == SHT_NOBITS) {
- memset ((void *)shdr->sh_addr, 0, shdr->sh_size);
+ memset((void *)(uintptr_t) shdr->sh_addr, 0,
+ shdr->sh_size);
} else {
image = (unsigned char *) addr + shdr->sh_offset;
- memcpy ((void *) shdr->sh_addr,
+ memcpy((void *)(uintptr_t) shdr->sh_addr,
(const void *) image,
shdr->sh_size);
}
- flush_cache (shdr->sh_addr, shdr->sh_size);
+ flush_cache(shdr->sh_addr, shdr->sh_size);
}
return ehdr->e_entry;
int do_help(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
- return _do_help(&__u_boot_cmd_start,
- &__u_boot_cmd_end - &__u_boot_cmd_start,
- cmdtp, flag, argc, argv);
+ cmd_tbl_t *start = ll_entry_start(cmd_tbl_t, cmd);
+ const int len = ll_entry_count(cmd_tbl_t, cmd);
+ return _do_help(start, len, cmdtp, flag, argc, argv);
}
U_BOOT_CMD(
);
/* This does not use the U_BOOT_CMD macro as ? can't be used in symbol names */
-cmd_tbl_t __u_boot_cmd_question_mark Struct_Section = {
+ll_entry_declare(cmd_tbl_t, question_mark, cmd, cmd) = {
"?", CONFIG_SYS_MAXARGS, 1, do_help,
"alias for 'help'",
#ifdef CONFIG_SYS_LONGHELP
return 0;
}
+static int do_i2c_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ u_char chip;
+ uint devaddr, alen, length;
+ u_char *memaddr;
+
+ if (argc != 5)
+ return cmd_usage(cmdtp);
+
+ /*
+ * memaddr is the address where to store things in memory
+ */
+ memaddr = (u_char *)simple_strtoul(argv[1], NULL, 16);
+
+ /*
+ * I2C chip address
+ */
+ chip = simple_strtoul(argv[2], NULL, 16);
+
+ /*
+ * I2C data address within the chip. This can be 1 or
+ * 2 bytes long. Some day it might be 3 bytes long :-).
+ */
+ devaddr = simple_strtoul(argv[3], NULL, 16);
+ alen = get_alen(argv[3]);
+ if (alen > 3)
+ return cmd_usage(cmdtp);
+
+ /*
+ * Length is the number of objects, not number of bytes.
+ */
+ length = simple_strtoul(argv[4], NULL, 16);
+
+ while (length-- > 0) {
+ if (i2c_write(chip, devaddr++, alen, memaddr++, 1) != 0) {
+ puts("Error writing to the chip.\n");
+ return 1;
+ }
+/*
+ * No write delay with FRAM devices.
+ */
+#if !defined(CONFIG_SYS_I2C_FRAM)
+ udelay(11000);
+#endif
+ }
+ return 0;
+}
+
/*
* Syntax:
* i2c md {i2c_chip} {addr}{.0, .1, .2} {len}
/*
* Syntax:
- * i2c probe {addr}{.0, .1, .2}
+ * i2c probe {addr}
+ *
+ * Returns zero (success) if one or more I2C devices was found
*/
static int do_i2c_probe (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int j;
+ int addr = -1;
+ int found = 0;
#if defined(CONFIG_SYS_I2C_NOPROBES)
int k, skip;
uchar bus = GET_BUS_NUM;
#endif /* NOPROBES */
+ if (argc == 2)
+ addr = simple_strtol(argv[1], 0, 16);
+
puts ("Valid chip addresses:");
for (j = 0; j < 128; j++) {
+ if ((0 <= addr) && (j != addr))
+ continue;
+
#if defined(CONFIG_SYS_I2C_NOPROBES)
skip = 0;
for (k=0; k < NUM_ELEMENTS_NOPROBE; k++) {
if (skip)
continue;
#endif
- if (i2c_probe(j) == 0)
+ if (i2c_probe(j) == 0) {
printf(" %02X", j);
+ found++;
+ }
}
putc ('\n');
putc ('\n');
#endif
- return 0;
+ return (0 == found);
}
/*
U_BOOT_CMD_MKENT(nm, 2, 1, do_i2c_nm, "", ""),
U_BOOT_CMD_MKENT(probe, 0, 1, do_i2c_probe, "", ""),
U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""),
+ U_BOOT_CMD_MKENT(write, 5, 0, do_i2c_write, "", ""),
U_BOOT_CMD_MKENT(reset, 0, 1, do_i2c_reset, "", ""),
#if defined(CONFIG_CMD_SDRAM)
U_BOOT_CMD_MKENT(sdram, 1, 1, do_sdram, "", ""),
"i2c mm chip address[.0, .1, .2] - write to I2C device (auto-incrementing)\n"
"i2c mw chip address[.0, .1, .2] value [count] - write to I2C device (fill)\n"
"i2c nm chip address[.0, .1, .2] - write to I2C device (constant address)\n"
- "i2c probe - show devices on the I2C bus\n"
+ "i2c probe [address] - test for and show device(s) on the I2C bus\n"
"i2c read chip address[.0, .1, .2] length memaddress - read to memory \n"
+ "i2c write memaddress chip address[.0, .1, .2] length - write memory to i2c\n"
"i2c reset - re-init the I2C Controller\n"
#if defined(CONFIG_CMD_SDRAM)
"i2c sdram chip - print SDRAM configuration information\n"
# include <pcmcia.h>
#endif
-#ifdef CONFIG_8xx
-# include <mpc8xx.h>
-#endif
-
-#ifdef CONFIG_MPC5xxx
-#include <mpc5xxx.h>
-#endif
-
#include <ide.h>
#include <ata.h>
# include <status_led.h>
#endif
-#ifdef CONFIG_IDE_8xx_DIRECT
-DECLARE_GLOBAL_DATA_PTR;
-#endif
-
#ifdef __PPC__
# define EIEIO __asm__ volatile ("eieio")
# define SYNC __asm__ volatile ("sync")
# define SYNC /* nothing */
#endif
-#ifdef CONFIG_IDE_8xx_DIRECT
-/* Timings for IDE Interface
- *
- * SETUP / LENGTH / HOLD - cycles valid for 50 MHz clk
- * 70 165 30 PIO-Mode 0, [ns]
- * 4 9 2 [Cycles]
- * 50 125 20 PIO-Mode 1, [ns]
- * 3 7 2 [Cycles]
- * 30 100 15 PIO-Mode 2, [ns]
- * 2 6 1 [Cycles]
- * 30 80 10 PIO-Mode 3, [ns]
- * 2 5 1 [Cycles]
- * 25 70 10 PIO-Mode 4, [ns]
- * 2 4 1 [Cycles]
- */
-
-const static pio_config_t pio_config_ns [IDE_MAX_PIO_MODE+1] =
-{
- /* Setup Length Hold */
- { 70, 165, 30 }, /* PIO-Mode 0, [ns] */
- { 50, 125, 20 }, /* PIO-Mode 1, [ns] */
- { 30, 101, 15 }, /* PIO-Mode 2, [ns] */
- { 30, 80, 10 }, /* PIO-Mode 3, [ns] */
- { 25, 70, 10 }, /* PIO-Mode 4, [ns] */
-};
-
-static pio_config_t pio_config_clk [IDE_MAX_PIO_MODE+1];
-
-#ifndef CONFIG_SYS_PIO_MODE
-#define CONFIG_SYS_PIO_MODE 0 /* use a relaxed default */
-#endif
-static int pio_mode = CONFIG_SYS_PIO_MODE;
-
-/* Make clock cycles and always round up */
-
-#define PCMCIA_MK_CLKS( t, T ) (( (t) * (T) + 999U ) / 1000U )
-
-#endif /* CONFIG_IDE_8xx_DIRECT */
-
/* ------------------------------------------------------------------------- */
/* Current I/O Device */
block_dev_desc_t ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
/* ------------------------------------------------------------------------- */
-#ifdef CONFIG_IDE_LED
-# if !defined(CONFIG_BMS2003) && \
- !defined(CONFIG_CPC45) && \
- !defined(CONFIG_KUP4K) && \
- !defined(CONFIG_KUP4X)
-static void ide_led (uchar led, uchar status);
-#else
-extern void ide_led (uchar led, uchar status);
-#endif
-#else
-#define ide_led(a,b) /* dummy */
-#endif
-
#ifdef CONFIG_IDE_RESET
static void ide_reset (void);
#else
#define IDE_SPIN_UP_TIME_OUT 5000 /* 5 sec spin-up timeout */
-static void input_data(int dev, ulong *sect_buf, int words);
-static void output_data(int dev, const ulong *sect_buf, int words);
static void ident_cpy (unsigned char *dest, unsigned char *src, unsigned int len);
#ifndef CONFIG_SYS_ATA_PORT_ADDR
#endif
-#ifdef CONFIG_IDE_8xx_DIRECT
-static void set_pcmcia_timing (int pmode);
-#endif
-
/* ------------------------------------------------------------------------- */
int do_ide(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
/* ------------------------------------------------------------------------- */
+void __ide_led(uchar led, uchar status)
+{
+#if defined(CONFIG_IDE_LED) && defined(PER8_BASE) /* required by LED_PORT */
+ static uchar led_buffer; /* Buffer for current LED status */
+
+ uchar *led_port = LED_PORT;
+
+ if (status) /* switch LED on */
+ led_buffer |= led;
+ else /* switch LED off */
+ led_buffer &= ~led;
+
+ *led_port = led_buffer;
+#endif
+}
+
+void ide_led(uchar led, uchar status)
+ __attribute__ ((weak, alias("__ide_led")));
+
+#ifndef CONFIG_IDE_LED /* define LED macros, they are not used anyways */
+# define DEVICE_LED(x) 0
+# define LED_IDE1 1
+# define LED_IDE2 2
+#endif
+
+/* ------------------------------------------------------------------------- */
+
inline void __ide_outb(int dev, int port, unsigned char val)
{
debug("ide_outb (dev= %d, port= 0x%x, val= 0x%02x) : @ 0x%08lx\n",
void ide_init(void)
{
-
-#ifdef CONFIG_IDE_8xx_DIRECT
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia);
-#endif
unsigned char c;
int i, bus;
-#if defined(CONFIG_SC3)
- unsigned int ata_reset_time = ATA_RESET_TIME;
-#endif
#ifdef CONFIG_IDE_8xx_PCCARD
- extern int pcmcia_on(void);
extern int ide_devices_found; /* Initialized in check_ide_device() */
#endif /* CONFIG_IDE_8xx_PCCARD */
#ifdef CONFIG_IDE_PREINIT
- extern int ide_preinit(void);
-
WATCHDOG_RESET();
if (ide_preinit()) {
}
#endif /* CONFIG_IDE_PREINIT */
-#ifdef CONFIG_IDE_8xx_PCCARD
- extern int pcmcia_on(void);
- extern int ide_devices_found; /* Initialized in check_ide_device() */
-
- WATCHDOG_RESET();
-
- ide_devices_found = 0;
- /* initialize the PCMCIA IDE adapter card */
- pcmcia_on();
- if (!ide_devices_found)
- return;
- udelay(1000000); /* 1 s */
-#endif /* CONFIG_IDE_8xx_PCCARD */
-
WATCHDOG_RESET();
-#ifdef CONFIG_IDE_8xx_DIRECT
- /* Initialize PIO timing tables */
- for (i = 0; i <= IDE_MAX_PIO_MODE; ++i) {
- pio_config_clk[i].t_setup =
- PCMCIA_MK_CLKS(pio_config_ns[i].t_setup, gd->bus_clk);
- pio_config_clk[i].t_length =
- PCMCIA_MK_CLKS(pio_config_ns[i].t_length,
- gd->bus_clk);
- pio_config_clk[i].t_hold =
- PCMCIA_MK_CLKS(pio_config_ns[i].t_hold, gd->bus_clk);
- debug("PIO Mode %d: setup=%2d ns/%d clk" " len=%3d ns/%d clk"
- " hold=%2d ns/%d clk\n", i, pio_config_ns[i].t_setup,
- pio_config_clk[i].t_setup, pio_config_ns[i].t_length,
- pio_config_clk[i].t_length, pio_config_ns[i].t_hold,
- pio_config_clk[i].t_hold);
- }
-#endif /* CONFIG_IDE_8xx_DIRECT */
-
/*
* Reset the IDE just to be sure.
* Light LED's to show
/* ATAPI Drives seems to need a proper IDE Reset */
ide_reset();
-#ifdef CONFIG_IDE_8xx_DIRECT
- /* PCMCIA / IDE initialization for common mem space */
- pcmp->pcmc_pgcrb = 0;
+#ifdef CONFIG_IDE_INIT_POSTRESET
+ WATCHDOG_RESET();
- /* start in PIO mode 0 - most relaxed timings */
- pio_mode = 0;
- set_pcmcia_timing(pio_mode);
-#endif /* CONFIG_IDE_8xx_DIRECT */
+ if (ide_init_postreset()) {
+ puts("ide_preinit_postreset failed\n");
+ return;
+ }
+#endif /* CONFIG_IDE_INIT_POSTRESET */
/*
* Wait for IDE to get ready.
c = ide_inb(dev, ATA_STATUS);
i++;
-#if defined(CONFIG_SC3)
- if (i > (ata_reset_time * 100)) {
-#else
if (i > (ATA_RESET_TIME * 100)) {
-#endif
puts("** Timeout **\n");
/* LED's off */
ide_led((LED_IDE1 | LED_IDE2), 0);
curr_device = -1;
for (i = 0; i < CONFIG_SYS_IDE_MAXDEVICE; ++i) {
-#ifdef CONFIG_IDE_LED
int led = (IDE_BUS(i) == 0) ? LED_IDE1 : LED_IDE2;
-#endif
ide_dev_desc[i].type = DEV_TYPE_UNKNOWN;
ide_dev_desc[i].if_type = IF_TYPE_IDE;
ide_dev_desc[i].dev = i;
}
#endif
+/* ------------------------------------------------------------------------- */
-#ifdef CONFIG_IDE_8xx_DIRECT
-
-static void set_pcmcia_timing(int pmode)
-{
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
- volatile pcmconf8xx_t *pcmp = &(immr->im_pcmcia);
- ulong timings;
-
- debug("Set timing for PIO Mode %d\n", pmode);
-
- timings = PCMCIA_SHT(pio_config_clk[pmode].t_hold)
- | PCMCIA_SST(pio_config_clk[pmode].t_setup)
- | PCMCIA_SL(pio_config_clk[pmode].t_length);
-
- /*
- * IDE 0
- */
- pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_PBR0;
- pcmp->pcmc_por0 = CONFIG_SYS_PCMCIA_POR0
-#if (CONFIG_SYS_PCMCIA_POR0 != 0)
- | timings
-#endif
- ;
- debug("PBR0: %08x POR0: %08x\n", pcmp->pcmc_pbr0, pcmp->pcmc_por0);
-
- pcmp->pcmc_pbr1 = CONFIG_SYS_PCMCIA_PBR1;
- pcmp->pcmc_por1 = CONFIG_SYS_PCMCIA_POR1
-#if (CONFIG_SYS_PCMCIA_POR1 != 0)
- | timings
-#endif
- ;
- debug("PBR1: %08x POR1: %08x\n", pcmp->pcmc_pbr1, pcmp->pcmc_por1);
-
- pcmp->pcmc_pbr2 = CONFIG_SYS_PCMCIA_PBR2;
- pcmp->pcmc_por2 = CONFIG_SYS_PCMCIA_POR2
-#if (CONFIG_SYS_PCMCIA_POR2 != 0)
- | timings
-#endif
- ;
- debug("PBR2: %08x POR2: %08x\n", pcmp->pcmc_pbr2, pcmp->pcmc_por2);
-
- pcmp->pcmc_pbr3 = CONFIG_SYS_PCMCIA_PBR3;
- pcmp->pcmc_por3 = CONFIG_SYS_PCMCIA_POR3
-#if (CONFIG_SYS_PCMCIA_POR3 != 0)
- | timings
-#endif
- ;
- debug("PBR3: %08x POR3: %08x\n", pcmp->pcmc_pbr3, pcmp->pcmc_por3);
-
- /*
- * IDE 1
- */
- pcmp->pcmc_pbr4 = CONFIG_SYS_PCMCIA_PBR4;
- pcmp->pcmc_por4 = CONFIG_SYS_PCMCIA_POR4
-#if (CONFIG_SYS_PCMCIA_POR4 != 0)
- | timings
-#endif
- ;
- debug("PBR4: %08x POR4: %08x\n", pcmp->pcmc_pbr4, pcmp->pcmc_por4);
-
- pcmp->pcmc_pbr5 = CONFIG_SYS_PCMCIA_PBR5;
- pcmp->pcmc_por5 = CONFIG_SYS_PCMCIA_POR5
-#if (CONFIG_SYS_PCMCIA_POR5 != 0)
- | timings
-#endif
- ;
- debug("PBR5: %08x POR5: %08x\n", pcmp->pcmc_pbr5, pcmp->pcmc_por5);
-
- pcmp->pcmc_pbr6 = CONFIG_SYS_PCMCIA_PBR6;
- pcmp->pcmc_por6 = CONFIG_SYS_PCMCIA_POR6
-#if (CONFIG_SYS_PCMCIA_POR6 != 0)
- | timings
-#endif
- ;
- debug("PBR6: %08x POR6: %08x\n", pcmp->pcmc_pbr6, pcmp->pcmc_por6);
-
- pcmp->pcmc_pbr7 = CONFIG_SYS_PCMCIA_PBR7;
- pcmp->pcmc_por7 = CONFIG_SYS_PCMCIA_POR7
-#if (CONFIG_SYS_PCMCIA_POR7 != 0)
- | timings
-#endif
- ;
- debug("PBR7: %08x POR7: %08x\n", pcmp->pcmc_pbr7, pcmp->pcmc_por7);
-
-}
+void ide_input_swap_data(int dev, ulong *sect_buf, int words)
+ __attribute__ ((weak, alias("__ide_input_swap_data")));
-#endif /* CONFIG_IDE_8xx_DIRECT */
+void ide_input_data(int dev, ulong *sect_buf, int words)
+ __attribute__ ((weak, alias("__ide_input_data")));
-/* ------------------------------------------------------------------------- */
+void ide_output_data(int dev, const ulong *sect_buf, int words)
+ __attribute__ ((weak, alias("__ide_output_data")));
/* We only need to swap data if we are running on a big endian cpu. */
-/* But Au1x00 cpu:s already swaps data in big endian mode! */
-#if defined(__LITTLE_ENDIAN) || \
- (defined(CONFIG_SOC_AU1X00) && !defined(CONFIG_GTH2))
-#define input_swap_data(x,y,z) input_data(x,y,z)
-#else
-static void input_swap_data(int dev, ulong *sect_buf, int words)
+#if defined(__LITTLE_ENDIAN)
+void __ide_input_swap_data(int dev, ulong *sect_buf, int words)
{
-#if defined(CONFIG_CPC45)
- uchar i;
- volatile uchar *pbuf_even =
- (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
- volatile uchar *pbuf_odd =
- (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
- ushort *dbuf = (ushort *) sect_buf;
-
- while (words--) {
- for (i = 0; i < 2; i++) {
- *(((uchar *) (dbuf)) + 1) = *pbuf_even;
- *(uchar *) dbuf = *pbuf_odd;
- dbuf += 1;
- }
- }
+ ide_input_data(dev, sect_buf, words);
+}
#else
+void __ide_input_swap_data(int dev, ulong *sect_buf, int words)
+{
volatile ushort *pbuf =
(ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
ushort *dbuf = (ushort *) sect_buf;
#ifdef __MIPS__
*dbuf++ = swab16p((u16 *) pbuf);
*dbuf++ = swab16p((u16 *) pbuf);
-#elif defined(CONFIG_PCS440EP)
- *dbuf++ = *pbuf;
- *dbuf++ = *pbuf;
#else
*dbuf++ = ld_le16(pbuf);
*dbuf++ = ld_le16(pbuf);
#endif /* !MIPS */
}
-#endif
}
-#endif /* __LITTLE_ENDIAN || CONFIG_AU1X00 */
+#endif /* __LITTLE_ENDIAN */
#if defined(CONFIG_IDE_SWAP_IO)
-static void output_data(int dev, const ulong *sect_buf, int words)
+void __ide_output_data(int dev, const ulong *sect_buf, int words)
{
-#if defined(CONFIG_CPC45)
- uchar *dbuf;
- volatile uchar *pbuf_even;
- volatile uchar *pbuf_odd;
-
- pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
- pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
- dbuf = (uchar *) sect_buf;
- while (words--) {
- EIEIO;
- *pbuf_even = *dbuf++;
- EIEIO;
- *pbuf_odd = *dbuf++;
- EIEIO;
- *pbuf_even = *dbuf++;
- EIEIO;
- *pbuf_odd = *dbuf++;
- }
-#else
ushort *dbuf;
volatile ushort *pbuf;
pbuf = (ushort *) (ATA_CURR_BASE(dev) + ATA_DATA_REG);
dbuf = (ushort *) sect_buf;
while (words--) {
-#if defined(CONFIG_PCS440EP)
- /* not tested, because CF was write protected */
- EIEIO;
- *pbuf = ld_le16(dbuf++);
- EIEIO;
- *pbuf = ld_le16(dbuf++);
-#else
EIEIO;
*pbuf = *dbuf++;
EIEIO;
*pbuf = *dbuf++;
-#endif
}
-#endif
}
#else /* ! CONFIG_IDE_SWAP_IO */
-static void output_data(int dev, const ulong *sect_buf, int words)
+void __ide_output_data(int dev, const ulong *sect_buf, int words)
{
#if defined(CONFIG_IDE_AHB)
ide_write_data(dev, sect_buf, words);
#endif /* CONFIG_IDE_SWAP_IO */
#if defined(CONFIG_IDE_SWAP_IO)
-static void input_data(int dev, ulong *sect_buf, int words)
+void __ide_input_data(int dev, ulong *sect_buf, int words)
{
-#if defined(CONFIG_CPC45)
- uchar *dbuf;
- volatile uchar *pbuf_even;
- volatile uchar *pbuf_odd;
-
- pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
- pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
- dbuf = (uchar *) sect_buf;
- while (words--) {
- *dbuf++ = *pbuf_even;
- EIEIO;
- SYNC;
- *dbuf++ = *pbuf_odd;
- EIEIO;
- SYNC;
- *dbuf++ = *pbuf_even;
- EIEIO;
- SYNC;
- *dbuf++ = *pbuf_odd;
- EIEIO;
- SYNC;
- }
-#else
ushort *dbuf;
volatile ushort *pbuf;
debug("in input data base for read is %lx\n", (unsigned long) pbuf);
while (words--) {
-#if defined(CONFIG_PCS440EP)
- EIEIO;
- *dbuf++ = ld_le16(pbuf);
- EIEIO;
- *dbuf++ = ld_le16(pbuf);
-#else
EIEIO;
*dbuf++ = *pbuf;
EIEIO;
*dbuf++ = *pbuf;
-#endif
}
-#endif
}
#else /* ! CONFIG_IDE_SWAP_IO */
-static void input_data(int dev, ulong *sect_buf, int words)
+void __ide_input_data(int dev, ulong *sect_buf, int words)
{
#if defined(CONFIG_IDE_AHB)
ide_read_data(dev, sect_buf, words);
return;
#endif
- input_swap_data(device, (ulong *)&iop, ATA_SECTORWORDS);
+ ide_input_swap_data(device, (ulong *)&iop, ATA_SECTORWORDS);
ident_cpy((unsigned char *) dev_desc->revision, iop.fw_rev,
sizeof(dev_desc->revision));
break;
}
- input_data(device, buffer, ATA_SECTORWORDS);
+ ide_input_data(device, buffer, ATA_SECTORWORDS);
(void) ide_inb(device, ATA_STATUS); /* clear IRQ */
++n;
goto WR_OUT;
}
- output_data(device, buffer, ATA_SECTORWORDS);
+ ide_output_data(device, buffer, ATA_SECTORWORDS);
c = ide_inb(device, ATA_STATUS); /* clear IRQ */
++n;
++blknr;
static void ide_reset(void)
{
-#if defined(CONFIG_SYS_PB_12V_ENABLE) || defined(CONFIG_SYS_PB_IDE_MOTOR)
- volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
-#endif
int i;
curr_device = -1;
WATCHDOG_RESET();
-#ifdef CONFIG_SYS_PB_12V_ENABLE
- /* 12V Enable output OFF */
- immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_12V_ENABLE);
-
- immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_12V_ENABLE);
- immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_12V_ENABLE);
- immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_12V_ENABLE;
-
- /* wait 500 ms for the voltage to stabilize */
- for (i = 0; i < 500; ++i)
- udelay(1000);
-
- /* 12V Enable output ON */
- immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_12V_ENABLE;
-#endif /* CONFIG_SYS_PB_12V_ENABLE */
-
-#ifdef CONFIG_SYS_PB_IDE_MOTOR
- /* configure IDE Motor voltage monitor pin as input */
- immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_IDE_MOTOR);
- immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_IDE_MOTOR);
- immr->im_cpm.cp_pbdir &= ~(CONFIG_SYS_PB_IDE_MOTOR);
-
- /* wait up to 1 s for the motor voltage to stabilize */
- for (i = 0; i < 1000; ++i) {
- if ((immr->im_cpm.cp_pbdat & CONFIG_SYS_PB_IDE_MOTOR) != 0) {
- break;
- }
- udelay(1000);
- }
-
- if (i == 1000) { /* Timeout */
- printf("\nWarning: 5V for IDE Motor missing\n");
-#ifdef CONFIG_STATUS_LED
-#ifdef STATUS_LED_YELLOW
- status_led_set(STATUS_LED_YELLOW, STATUS_LED_ON);
-#endif
-#ifdef STATUS_LED_GREEN
- status_led_set(STATUS_LED_GREEN, STATUS_LED_OFF);
-#endif
-#endif /* CONFIG_STATUS_LED */
- }
-#endif /* CONFIG_SYS_PB_IDE_MOTOR */
-
- WATCHDOG_RESET();
-
/* de-assert RESET signal */
ide_set_reset(0);
/* ------------------------------------------------------------------------- */
-#if defined(CONFIG_IDE_LED) && \
- !defined(CONFIG_CPC45) && \
- !defined(CONFIG_KUP4K) && \
- !defined(CONFIG_KUP4X)
-
-static uchar led_buffer; /* Buffer for current LED status */
-
-static void ide_led(uchar led, uchar status)
-{
- uchar *led_port = LED_PORT;
-
- if (status) /* switch LED on */
- led_buffer |= led;
- else /* switch LED off */
- led_buffer &= ~led;
-
- *led_port = led_buffer;
-}
-
-#endif /* CONFIG_IDE_LED */
-
#if defined(CONFIG_OF_IDE_FIXUP)
int ide_device_present(int dev)
{
* ATAPI Support
*/
+void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
+ __attribute__ ((weak, alias("__ide_input_data_shorts")));
+
+void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
+ __attribute__ ((weak, alias("__ide_output_data_shorts")));
+
+
#if defined(CONFIG_IDE_SWAP_IO)
/* since ATAPI may use commands with not 4 bytes alligned length
* we have our own transfer functions, 2 bytes alligned */
-static void output_data_shorts(int dev, ushort *sect_buf, int shorts)
+void __ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
{
-#if defined(CONFIG_CPC45)
- uchar *dbuf;
- volatile uchar *pbuf_even;
- volatile uchar *pbuf_odd;
-
- pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
- pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
- while (shorts--) {
- EIEIO;
- *pbuf_even = *dbuf++;
- EIEIO;
- *pbuf_odd = *dbuf++;
- }
-#else
ushort *dbuf;
volatile ushort *pbuf;
EIEIO;
*pbuf = *dbuf++;
}
-#endif
}
-static void input_data_shorts(int dev, ushort *sect_buf, int shorts)
+void __ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
{
-#if defined(CONFIG_CPC45)
- uchar *dbuf;
- volatile uchar *pbuf_even;
- volatile uchar *pbuf_odd;
-
- pbuf_even = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_EVEN);
- pbuf_odd = (uchar *) (ATA_CURR_BASE(dev) + ATA_DATA_ODD);
- while (shorts--) {
- EIEIO;
- *dbuf++ = *pbuf_even;
- EIEIO;
- *dbuf++ = *pbuf_odd;
- }
-#else
ushort *dbuf;
volatile ushort *pbuf;
EIEIO;
*dbuf++ = *pbuf;
}
-#endif
}
#else /* ! CONFIG_IDE_SWAP_IO */
-static void output_data_shorts(int dev, ushort *sect_buf, int shorts)
+void __ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
{
outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
}
-static void input_data_shorts(int dev, ushort *sect_buf, int shorts)
+void __ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
{
insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
}
}
/* write command block */
- output_data_shorts(device, (unsigned short *) ccb, ccblen / 2);
+ ide_output_data_shorts(device, (unsigned short *) ccb, ccblen / 2);
/* ATAPI Command written wait for completition */
udelay(5000); /* device must set bsy */
/* ok now decide if it is an in or output */
if ((ide_inb(device, ATA_SECT_CNT) & 0x02) == 0) {
debug("Write to device\n");
- output_data_shorts(device, (unsigned short *) buffer,
- n);
+ ide_output_data_shorts(device,
+ (unsigned short *) buffer, n);
} else {
debug("Read from device @ %p shorts %d\n", buffer, n);
- input_data_shorts(device, (unsigned short *) buffer,
- n);
+ ide_input_data_shorts(device,
+ (unsigned short *) buffer, n);
}
}
udelay(5000); /* seems that some CD ROMs need this... */
SPI_FLASH|NVRAM|MMC|FAT|REMOTE} or CONFIG_ENV_IS_NOWHERE
#endif
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
/*
* Maximum expected input data size for import command
*/
if (console_assign(console, newval) < 0)
return 1;
-#ifdef CONFIG_SERIAL_MULTI
if (serial_assign(newval) < 0)
return 1;
-#endif
#endif /* CONFIG_CONSOLE_MUX */
}
if (strcmp(name, "serial#") == 0 ||
(strcmp(name, "ethaddr") == 0
#if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR)
- && strcmp(oldval, MK_STR(CONFIG_ETHADDR)) != 0
+ && strcmp(oldval, __stringify(CONFIG_ETHADDR)) != 0
#endif /* CONFIG_OVERWRITE_ETHADDR_ONCE && CONFIG_ETHADDR */
)) {
printf("Can't overwrite \"%s\"\n", name);
*/
int envmatch(uchar *s1, int i2)
{
+ if (s1 == NULL)
+ return -1;
+
while (*s1 == env_get_char(i2++))
if (*s1++ == '=')
return i2;
bootstage_mark_name(BOOTSTAGE_ID_USB_START, "usb_start");
usb_stop();
printf("(Re)start USB...\n");
- i = usb_init();
- if (i >= 0) {
+ if (usb_init() >= 0) {
#ifdef CONFIG_USB_STORAGE
/* try to recognize storage devices immediately */
usb_stor_curr_dev = usb_stor_scan(1);
#ifdef CONFIG_USB_HOST_ETHER
/* try to recognize ethernet devices immediately */
usb_ether_curr_dev = usb_host_eth_scan(1);
+#endif
+#ifdef CONFIG_USB_KEYBOARD
+ drv_usb_kbd_init();
#endif
}
return 0;
return 1;
}
if (strncmp(argv[1], "tree", 4) == 0) {
- printf("\nDevice Tree:\n");
- usb_show_tree(usb_get_dev_index(0));
+ puts("USB device tree:\n");
+ for (i = 0; i < USB_MAX_DEVICE; i++) {
+ dev = usb_get_dev_index(i);
+ if (dev == NULL)
+ break;
+ if (dev->parent == NULL)
+ usb_show_tree(dev);
+ }
return 0;
}
if (strncmp(argv[1], "inf", 3) == 0) {
cmd_tbl_t *find_cmd (const char *cmd)
{
- int len = &__u_boot_cmd_end - &__u_boot_cmd_start;
- return find_cmd_tbl(cmd, &__u_boot_cmd_start, len);
+ cmd_tbl_t *start = ll_entry_start(cmd_tbl_t, cmd);
+ const int len = ll_entry_count(cmd_tbl_t, cmd);
+ return find_cmd_tbl(cmd, start, len);
}
int cmd_usage(const cmd_tbl_t *cmdtp)
static int complete_cmdv(int argc, char * const argv[], char last_char, int maxv, char *cmdv[])
{
- cmd_tbl_t *cmdtp;
+ cmd_tbl_t *cmdtp = ll_entry_start(cmd_tbl_t, cmd);
+ const int count = ll_entry_count(cmd_tbl_t, cmd);
+ const cmd_tbl_t *cmdend = cmdtp + count;
const char *p;
int len, clen;
int n_found = 0;
if (argc == 0) {
/* output full list of commands */
- for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) {
+ for (; cmdtp != cmdend; cmdtp++) {
if (n_found >= maxv - 2) {
- cmdv[n_found++] = "...";
+ cmdv[n_found] = "...";
break;
}
- cmdv[n_found++] = cmdtp->name;
+ cmdv[n_found] = cmdtp->name;
}
cmdv[n_found] = NULL;
return n_found;
len = p - cmd;
/* return the partial matches */
- for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) {
+ for (; cmdtp != cmdend; cmdtp++) {
clen = strlen(cmdtp->name);
if (clen < len)
/************************************************************************
* Default settings to be used when no valid environment is found
*/
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
-const uchar default_environment[] = {
-#ifdef CONFIG_BOOTARGS
- "bootargs=" CONFIG_BOOTARGS "\0"
-#endif
-#ifdef CONFIG_BOOTCOMMAND
- "bootcmd=" CONFIG_BOOTCOMMAND "\0"
-#endif
-#ifdef CONFIG_RAMBOOTCOMMAND
- "ramboot=" CONFIG_RAMBOOTCOMMAND "\0"
-#endif
-#ifdef CONFIG_NFSBOOTCOMMAND
- "nfsboot=" CONFIG_NFSBOOTCOMMAND "\0"
-#endif
-#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
- "bootdelay=" MK_STR(CONFIG_BOOTDELAY) "\0"
-#endif
-#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0)
- "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0"
-#endif
-#ifdef CONFIG_LOADS_ECHO
- "loads_echo=" MK_STR(CONFIG_LOADS_ECHO) "\0"
-#endif
-#ifdef CONFIG_ETHADDR
- "ethaddr=" MK_STR(CONFIG_ETHADDR) "\0"
-#endif
-#ifdef CONFIG_ETH1ADDR
- "eth1addr=" MK_STR(CONFIG_ETH1ADDR) "\0"
-#endif
-#ifdef CONFIG_ETH2ADDR
- "eth2addr=" MK_STR(CONFIG_ETH2ADDR) "\0"
-#endif
-#ifdef CONFIG_ETH3ADDR
- "eth3addr=" MK_STR(CONFIG_ETH3ADDR) "\0"
-#endif
-#ifdef CONFIG_ETH4ADDR
- "eth4addr=" MK_STR(CONFIG_ETH4ADDR) "\0"
-#endif
-#ifdef CONFIG_ETH5ADDR
- "eth5addr=" MK_STR(CONFIG_ETH5ADDR) "\0"
-#endif
-#ifdef CONFIG_ETHPRIME
- "ethprime=" CONFIG_ETHPRIME "\0"
-#endif
-#ifdef CONFIG_IPADDR
- "ipaddr=" MK_STR(CONFIG_IPADDR) "\0"
-#endif
-#ifdef CONFIG_SERVERIP
- "serverip=" MK_STR(CONFIG_SERVERIP) "\0"
-#endif
-#ifdef CONFIG_SYS_AUTOLOAD
- "autoload=" CONFIG_SYS_AUTOLOAD "\0"
-#endif
-#ifdef CONFIG_PREBOOT
- "preboot=" CONFIG_PREBOOT "\0"
-#endif
-#ifdef CONFIG_ROOTPATH
- "rootpath=" CONFIG_ROOTPATH "\0"
-#endif
-#ifdef CONFIG_GATEWAYIP
- "gatewayip=" MK_STR(CONFIG_GATEWAYIP) "\0"
-#endif
-#ifdef CONFIG_NETMASK
- "netmask=" MK_STR(CONFIG_NETMASK) "\0"
-#endif
-#ifdef CONFIG_HOSTNAME
- "hostname=" MK_STR(CONFIG_HOSTNAME) "\0"
-#endif
-#ifdef CONFIG_BOOTFILE
- "bootfile=" CONFIG_BOOTFILE "\0"
-#endif
-#ifdef CONFIG_LOADADDR
- "loadaddr=" MK_STR(CONFIG_LOADADDR) "\0"
-#endif
-#ifdef CONFIG_CLOCKS_IN_MHZ
- "clocks_in_mhz=1\0"
-#endif
-#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
- "pcidelay=" MK_STR(CONFIG_PCI_BOOTDELAY) "\0"
-#endif
-#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG
- "arch=" CONFIG_SYS_ARCH "\0"
- "cpu=" CONFIG_SYS_CPU "\0"
- "board=" CONFIG_SYS_BOARD "\0"
-#ifdef CONFIG_SYS_VENDOR
- "vendor=" CONFIG_SYS_VENDOR "\0"
-#endif
-#ifdef CONFIG_SYS_SOC
- "soc=" CONFIG_SYS_SOC "\0"
-#endif
-#endif
-#ifdef CONFIG_EXTRA_ENV_SETTINGS
- CONFIG_EXTRA_ENV_SETTINGS
-#endif
- "\0"
-};
+#include <env_default.h>
struct hsearch_data env_htab = {
.apply = env_check_apply,
#include <config.h>
#undef __ASSEMBLY__
#include <environment.h>
+#include <linux/stringify.h>
/* Handle HOSTS that have prepended crap on symbol names, not TARGETS. */
#if defined(__APPLE__)
asm(".globl " GEN_SYMNAME(name)); \
GEN_SET_VALUE(name, value)
-/*
- * Macros to transform values
- * into environment strings.
- */
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
/*
* Check to see if we are building with a
* computed CRC. Otherwise define it as ~0.
# define ENV_CRC (~0)
#endif
-env_t environment __PPCENV__ = {
- ENV_CRC, /* CRC Sum */
-#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
- 1, /* Flags: valid */
-#endif
- {
-#if defined(CONFIG_BOOTARGS)
- "bootargs=" CONFIG_BOOTARGS "\0"
-#endif
-#if defined(CONFIG_BOOTCOMMAND)
- "bootcmd=" CONFIG_BOOTCOMMAND "\0"
-#endif
-#if defined(CONFIG_RAMBOOTCOMMAND)
- "ramboot=" CONFIG_RAMBOOTCOMMAND "\0"
-#endif
-#if defined(CONFIG_NFSBOOTCOMMAND)
- "nfsboot=" CONFIG_NFSBOOTCOMMAND "\0"
-#endif
-#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
- "bootdelay=" MK_STR(CONFIG_BOOTDELAY) "\0"
-#endif
-#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0)
- "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0"
-#endif
-#ifdef CONFIG_LOADS_ECHO
- "loads_echo=" MK_STR(CONFIG_LOADS_ECHO) "\0"
-#endif
-#ifdef CONFIG_ETHADDR
- "ethaddr=" MK_STR(CONFIG_ETHADDR) "\0"
-#endif
-#ifdef CONFIG_ETH1ADDR
- "eth1addr=" MK_STR(CONFIG_ETH1ADDR) "\0"
-#endif
-#ifdef CONFIG_ETH2ADDR
- "eth2addr=" MK_STR(CONFIG_ETH2ADDR) "\0"
-#endif
-#ifdef CONFIG_ETH3ADDR
- "eth3addr=" MK_STR(CONFIG_ETH3ADDR) "\0"
-#endif
-#ifdef CONFIG_ETH4ADDR
- "eth4addr=" MK_STR(CONFIG_ETH4ADDR) "\0"
-#endif
-#ifdef CONFIG_ETH5ADDR
- "eth5addr=" MK_STR(CONFIG_ETH5ADDR) "\0"
-#endif
-#ifdef CONFIG_ETHPRIME
- "ethprime=" CONFIG_ETHPRIME "\0"
-#endif
-#ifdef CONFIG_IPADDR
- "ipaddr=" MK_STR(CONFIG_IPADDR) "\0"
-#endif
-#ifdef CONFIG_SERVERIP
- "serverip=" MK_STR(CONFIG_SERVERIP) "\0"
-#endif
-#ifdef CONFIG_SYS_AUTOLOAD
- "autoload=" CONFIG_SYS_AUTOLOAD "\0"
-#endif
-#ifdef CONFIG_ROOTPATH
- "rootpath=" CONFIG_ROOTPATH "\0"
-#endif
-#ifdef CONFIG_GATEWAYIP
- "gatewayip=" MK_STR(CONFIG_GATEWAYIP) "\0"
-#endif
-#ifdef CONFIG_NETMASK
- "netmask=" MK_STR(CONFIG_NETMASK) "\0"
-#endif
-#ifdef CONFIG_HOSTNAME
- "hostname=" MK_STR(CONFIG_HOSTNAME) "\0"
-#endif
-#ifdef CONFIG_BOOTFILE
- "bootfile=" CONFIG_BOOTFILE "\0"
-#endif
-#ifdef CONFIG_LOADADDR
- "loadaddr=" MK_STR(CONFIG_LOADADDR) "\0"
-#endif
-#ifdef CONFIG_PREBOOT
- "preboot=" CONFIG_PREBOOT "\0"
-#endif
-#ifdef CONFIG_CLOCKS_IN_MHZ
- "clocks_in_mhz=" "1" "\0"
-#endif
-#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
- "pcidelay=" MK_STR(CONFIG_PCI_BOOTDELAY) "\0"
-#endif
-#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG
- "arch=" CONFIG_SYS_ARCH "\0"
- "cpu=" CONFIG_SYS_CPU "\0"
- "board=" CONFIG_SYS_BOARD "\0"
-#ifdef CONFIG_SYS_VENDOR
- "vendor=" CONFIG_SYS_VENDOR "\0"
-#endif
-#ifdef CONFIG_SYS_SOC
- "soc=" CONFIG_SYS_SOC "\0"
-#endif
-#endif
-#ifdef CONFIG_EXTRA_ENV_SETTINGS
- CONFIG_EXTRA_ENV_SETTINGS
-#endif
- "\0" /* Term. env_t.data with 2 NULs */
- }
-};
+#define DEFAULT_ENV_INSTANCE_EMBEDDED
+#include <env_default.h>
+
#ifdef CONFIG_ENV_ADDR_REDUND
env_t redundand_environment __PPCENV__ = {
0, /* CRC Sum: invalid */
#ifdef CONFIG_OF_STDOUT_VIA_ALIAS
-#ifdef CONFIG_SERIAL_MULTI
+#ifdef CONFIG_CONS_INDEX
static void fdt_fill_multisername(char *sername, size_t maxlen)
{
const char *outname = stdio_devices[stdout]->name;
if (strcmp(outname + 1, "serial") > 0)
strncpy(sername, outname + 1, maxlen);
}
-#else
-static inline void fdt_fill_multisername(char *sername, size_t maxlen) {}
-#endif /* CONFIG_SERIAL_MULTI */
+#endif
static int fdt_fixup_stdout(void *fdt, int chosenoff)
{
*/
if (console_assign(console, start[j]) < 0)
continue;
-#ifdef CONFIG_SERIAL_MULTI
/*
* This was taken from common/cmd_nvedit.c.
* This will never work because serial_assign() returns
*/
if (serial_assign(start[j]) < 0)
continue;
-#endif
cons_set[cs_idx++] = dev;
}
free(console_args);
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <serial.h>
-#include <stdio_dev.h>
-#include <post.h>
-#include <linux/compiler.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static struct serial_device *serial_devices;
-static struct serial_device *serial_current;
-
-void serial_register(struct serial_device *dev)
-{
-#ifdef CONFIG_NEEDS_MANUAL_RELOC
- dev->init += gd->reloc_off;
- dev->setbrg += gd->reloc_off;
- dev->getc += gd->reloc_off;
- dev->tstc += gd->reloc_off;
- dev->putc += gd->reloc_off;
- dev->puts += gd->reloc_off;
-#endif
-
- dev->next = serial_devices;
- serial_devices = dev;
-}
-
-void serial_initialize(void)
-{
-#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2)
- serial_register(&serial_smc_device);
-#endif
-#if defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) || \
- defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
- serial_register(&serial_scc_device);
-#endif
-
-#if defined(CONFIG_SYS_NS16550_SERIAL)
-#if defined(CONFIG_SYS_NS16550_COM1)
- serial_register(&eserial1_device);
-#endif
-#if defined(CONFIG_SYS_NS16550_COM2)
- serial_register(&eserial2_device);
-#endif
-#if defined(CONFIG_SYS_NS16550_COM3)
- serial_register(&eserial3_device);
-#endif
-#if defined(CONFIG_SYS_NS16550_COM4)
- serial_register(&eserial4_device);
-#endif
-#endif /* CONFIG_SYS_NS16550_SERIAL */
-#if defined(CONFIG_FFUART)
- serial_register(&serial_ffuart_device);
-#endif
-#if defined(CONFIG_BTUART)
- serial_register(&serial_btuart_device);
-#endif
-#if defined(CONFIG_STUART)
- serial_register(&serial_stuart_device);
-#endif
-#if defined(CONFIG_S3C2410)
- serial_register(&s3c24xx_serial0_device);
- serial_register(&s3c24xx_serial1_device);
- serial_register(&s3c24xx_serial2_device);
-#endif
-#if defined(CONFIG_S5P)
- serial_register(&s5p_serial0_device);
- serial_register(&s5p_serial1_device);
- serial_register(&s5p_serial2_device);
- serial_register(&s5p_serial3_device);
-#endif
-#if defined(CONFIG_MPC512X)
-#if defined(CONFIG_SYS_PSC1)
- serial_register(&serial1_device);
-#endif
-#if defined(CONFIG_SYS_PSC3)
- serial_register(&serial3_device);
-#endif
-#if defined(CONFIG_SYS_PSC4)
- serial_register(&serial4_device);
-#endif
-#if defined(CONFIG_SYS_PSC6)
- serial_register(&serial6_device);
-#endif
-#endif
-#if defined(CONFIG_SYS_BFIN_UART)
- serial_register_bfin_uart();
-#endif
-#if defined(CONFIG_XILINX_UARTLITE)
-# ifdef XILINX_UARTLITE_BASEADDR
- serial_register(&uartlite_serial0_device);
-# endif /* XILINX_UARTLITE_BASEADDR */
-# ifdef XILINX_UARTLITE_BASEADDR1
- serial_register(&uartlite_serial1_device);
-# endif /* XILINX_UARTLITE_BASEADDR1 */
-# ifdef XILINX_UARTLITE_BASEADDR2
- serial_register(&uartlite_serial2_device);
-# endif /* XILINX_UARTLITE_BASEADDR2 */
-# ifdef XILINX_UARTLITE_BASEADDR3
- serial_register(&uartlite_serial3_device);
-# endif /* XILINX_UARTLITE_BASEADDR3 */
-#endif /* CONFIG_XILINX_UARTLITE */
-#if defined(CONFIG_ZYNQ_SERIAL)
-# ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0
- serial_register(&uart_zynq_serial0_device);
-# endif
-# ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1
- serial_register(&uart_zynq_serial1_device);
-# endif
-#endif
- serial_assign(default_serial_console()->name);
-}
-
-void serial_stdio_init(void)
-{
- struct stdio_dev dev;
- struct serial_device *s = serial_devices;
-
- while (s) {
- memset(&dev, 0, sizeof(dev));
-
- strcpy(dev.name, s->name);
- dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT;
-
- dev.start = s->init;
- dev.stop = s->uninit;
- dev.putc = s->putc;
- dev.puts = s->puts;
- dev.getc = s->getc;
- dev.tstc = s->tstc;
-
- stdio_register(&dev);
-
- s = s->next;
- }
-}
-
-int serial_assign(const char *name)
-{
- struct serial_device *s;
-
- for (s = serial_devices; s; s = s->next) {
- if (strcmp(s->name, name) == 0) {
- serial_current = s;
- return 0;
- }
- }
-
- return 1;
-}
-
-void serial_reinit_all(void)
-{
- struct serial_device *s;
-
- for (s = serial_devices; s; s = s->next)
- s->init();
-}
-
-static struct serial_device *get_current(void)
-{
- struct serial_device *dev;
-
- if (!(gd->flags & GD_FLG_RELOC) || !serial_current) {
- dev = default_serial_console();
-
- /* We must have a console device */
- if (!dev)
- panic("Cannot find console");
- } else
- dev = serial_current;
- return dev;
-}
-
-int serial_init(void)
-{
- return get_current()->init();
-}
-
-void serial_setbrg(void)
-{
- get_current()->setbrg();
-}
-
-int serial_getc(void)
-{
- return get_current()->getc();
-}
-
-int serial_tstc(void)
-{
- return get_current()->tstc();
-}
-
-void serial_putc(const char c)
-{
- get_current()->putc(c);
-}
-
-void serial_puts(const char *s)
-{
- get_current()->puts(s);
-}
-
-#if CONFIG_POST & CONFIG_SYS_POST_UART
-static const int bauds[] = CONFIG_SYS_BAUDRATE_TABLE;
-
-/* Mark weak until post/cpu/.../uart.c migrate over */
-__weak
-int uart_post_test(int flags)
-{
- unsigned char c;
- int ret, saved_baud, b;
- struct serial_device *saved_dev, *s;
- bd_t *bd = gd->bd;
-
- /* Save current serial state */
- ret = 0;
- saved_dev = serial_current;
- saved_baud = bd->bi_baudrate;
-
- for (s = serial_devices; s; s = s->next) {
- /* If this driver doesn't support loop back, skip it */
- if (!s->loop)
- continue;
-
- /* Test the next device */
- serial_current = s;
-
- ret = serial_init();
- if (ret)
- goto done;
-
- /* Consume anything that happens to be queued */
- while (serial_tstc())
- serial_getc();
-
- /* Enable loop back */
- s->loop(1);
-
- /* Test every available baud rate */
- for (b = 0; b < ARRAY_SIZE(bauds); ++b) {
- bd->bi_baudrate = bauds[b];
- serial_setbrg();
-
- /*
- * Stick to printable chars to avoid issues:
- * - terminal corruption
- * - serial program reacting to sequences and sending
- * back random extra data
- * - most serial drivers add in extra chars (like \r\n)
- */
- for (c = 0x20; c < 0x7f; ++c) {
- /* Send it out */
- serial_putc(c);
-
- /* Make sure it's the same one */
- ret = (c != serial_getc());
- if (ret) {
- s->loop(0);
- goto done;
- }
-
- /* Clean up the output in case it was sent */
- serial_putc('\b');
- ret = ('\b' != serial_getc());
- if (ret) {
- s->loop(0);
- goto done;
- }
- }
- }
-
- /* Disable loop back */
- s->loop(0);
-
- /* XXX: There is no serial_uninit() !? */
- if (s->uninit)
- s->uninit();
- }
-
- done:
- /* Restore previous serial state */
- serial_current = saved_dev;
- bd->bi_baudrate = saved_baud;
- serial_reinit_all();
- serial_setbrg();
-
- return ret;
-}
-#endif
void preloader_console_init(void)
{
gd->bd = &bdata;
- gd->flags |= GD_FLG_RELOC;
gd->baudrate = CONFIG_BAUDRATE;
serial_init(); /* serial communications setup */
drv_logbuff_init ();
#endif
drv_system_init ();
-#ifdef CONFIG_SERIAL_MULTI
serial_stdio_init ();
-#endif
#ifdef CONFIG_USB_TTY
drv_usbtty_init ();
#endif
static struct usb_device usb_dev[USB_MAX_DEVICE];
static int dev_index;
-static int running;
static int asynch_allowed;
char usb_started; /* flag for the started/stopped USB status */
-/**********************************************************************
- * some forward declerations...
- */
-static void usb_scan_devices(void);
+#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
/***************************************************************************
* Init USB Device
*/
-
int usb_init(void)
{
- int result;
+ void *ctrl;
+ struct usb_device *dev;
+ int i, start_index = 0;
- running = 0;
dev_index = 0;
asynch_allowed = 1;
usb_hub_reset();
+
+ /* first make all devices unknown */
+ for (i = 0; i < USB_MAX_DEVICE; i++) {
+ memset(&usb_dev[i], 0, sizeof(struct usb_device));
+ usb_dev[i].devnum = -1;
+ }
+
/* init low_level USB */
- printf("USB: ");
- result = usb_lowlevel_init();
- /* if lowlevel init is OK, scan the bus for devices
- * i.e. search HUBs and configure them */
- if (result == 0) {
- printf("scanning bus for devices... ");
- running = 1;
- usb_scan_devices();
+ for (i = 0; i < CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
+ /* init low_level USB */
+ printf("USB%d: ", i);
+ if (usb_lowlevel_init(i, &ctrl)) {
+ puts("lowlevel init failed\n");
+ continue;
+ }
+ /*
+ * lowlevel init is OK, now scan the bus for devices
+ * i.e. search HUBs and configure them
+ */
+ start_index = dev_index;
+ printf("scanning bus %d for devices... ", i);
+ dev = usb_alloc_new_device(ctrl);
+ /*
+ * device 0 is always present
+ * (root hub, so let it analyze)
+ */
+ if (dev)
+ usb_new_device(dev);
+
+ if (start_index == dev_index)
+ puts("No USB Device found\n");
+ else
+ printf("%d USB Device(s) found\n",
+ dev_index - start_index);
+
usb_started = 1;
- return 0;
- } else {
- printf("Error, couldn't init Lowlevel part\n");
- usb_started = 0;
+ }
+
+ USB_PRINTF("scan end\n");
+ /* if we were not able to find at least one working bus, bail out */
+ if (!usb_started) {
+ puts("USB error: all controllers failed lowlevel init\n");
return -1;
}
+
+ return 0;
}
/******************************************************************************
*/
int usb_stop(void)
{
- int res = 0;
+ int i;
if (usb_started) {
asynch_allowed = 1;
usb_started = 0;
usb_hub_reset();
- res = usb_lowlevel_stop();
+
+ for (i = 0; i < CONFIG_USB_MAX_CONTROLLER_COUNT; i++) {
+ if (usb_lowlevel_stop(i))
+ printf("failed to stop USB controller %d\n", i);
+ }
}
- return res;
+
+ return 0;
}
/*
tmp = le16_to_cpu(config->wTotalLength);
if (tmp > USB_BUFSIZ) {
- USB_PRINTF("usb_get_configuration_no: failed to get " \
- "descriptor - too long: %d\n", tmp);
+ printf("usb_get_configuration_no: failed to get " \
+ "descriptor - too long: %d\n", tmp);
return -1;
}
return &usb_dev[index];
}
-
/* returns a pointer of a new device structure or NULL, if
* no device struct is available
*/
-struct usb_device *usb_alloc_new_device(void)
+struct usb_device *usb_alloc_new_device(void *controller)
{
int i;
USB_PRINTF("New Device %d\n", dev_index);
for (i = 0; i < USB_MAXCHILDREN; i++)
usb_dev[dev_index].children[i] = NULL;
usb_dev[dev_index].parent = NULL;
+ usb_dev[dev_index].controller = controller;
dev_index++;
return &usb_dev[dev_index - 1];
}
le16_to_cpus(&dev->descriptor.idProduct);
le16_to_cpus(&dev->descriptor.bcdDevice);
/* only support for one config for now */
- usb_get_configuration_no(dev, tmpbuf, 0);
+ err = usb_get_configuration_no(dev, tmpbuf, 0);
+ if (err < 0) {
+ printf("usb_new_device: Cannot read configuration, " \
+ "skipping device %04x:%04x\n",
+ dev->descriptor.idVendor, dev->descriptor.idProduct);
+ return -1;
+ }
usb_parse_config(dev, tmpbuf, 0);
usb_set_maxpacket(dev);
/* we set the default configuration here */
return 0;
}
-/* build device Tree */
-static void usb_scan_devices(void)
-{
- int i;
- struct usb_device *dev;
-
- /* first make all devices unknown */
- for (i = 0; i < USB_MAX_DEVICE; i++) {
- memset(&usb_dev[i], 0, sizeof(struct usb_device));
- usb_dev[i].devnum = -1;
- }
- dev_index = 0;
- /* device 0 is always present (root hub, so let it analyze) */
- dev = usb_alloc_new_device();
- if (usb_new_device(dev))
- printf("No USB Device found\n");
- else
- printf("%d USB Device(s) found\n", dev_index);
- /* insert "driver" if possible */
-#ifdef CONFIG_USB_KEYBOARD
- drv_usb_kbd_init();
-#endif
- USB_PRINTF("scan end\n");
-}
-
/* EOF */
mdelay(200);
/* Allocate a new device struct for it */
- usb = usb_alloc_new_device();
+ usb = usb_alloc_new_device(dev->controller);
if (portstatus & USB_PORT_STAT_HIGH_SPEED)
usb->speed = USB_SPEED_HIGH;
int usb_storage_probe(struct usb_device *dev, unsigned int ifnum,
struct us_data *ss);
unsigned long usb_stor_read(int device, unsigned long blknr,
- unsigned long blkcnt, void *buffer);
+ lbaint_t blkcnt, void *buffer);
unsigned long usb_stor_write(int device, unsigned long blknr,
- unsigned long blkcnt, const void *buffer);
+ lbaint_t blkcnt, const void *buffer);
struct usb_device * usb_get_dev_index(int index);
void uhci_show_temp_int_td(void);
struct usb_device *dev;
if (mode == 1)
- printf(" scanning bus for storage devices... ");
+ printf(" scanning usb for storage devices... ");
usb_disable_asynch(1); /* asynch transfer not allowed */
#endif /* CONFIG_USB_BIN_FIXUP */
unsigned long usb_stor_read(int device, unsigned long blknr,
- unsigned long blkcnt, void *buffer)
+ lbaint_t blkcnt, void *buffer)
{
- unsigned long start, blks, buf_addr;
+ lbaint_t start, blks;
+ uintptr_t buf_addr;
unsigned short smallblks;
struct usb_device *dev;
struct us_data *ss;
start = blknr;
blks = blkcnt;
- USB_STOR_PRINTF("\nusb_read: dev %d startblk %lx, blccnt %lx"
+ USB_STOR_PRINTF("\nusb_read: dev %d startblk " LBAF ", blccnt " LBAF
" buffer %lx\n", device, start, blks, buf_addr);
do {
} while (blks != 0);
ss->flags &= ~USB_READY;
- USB_STOR_PRINTF("usb_read: end startblk %lx, blccnt %x buffer %lx\n",
+ USB_STOR_PRINTF("usb_read: end startblk " LBAF
+ ", blccnt %x buffer %lx\n",
start, smallblks, buf_addr);
usb_disable_asynch(0); /* asynch transfer allowed */
}
unsigned long usb_stor_write(int device, unsigned long blknr,
- unsigned long blkcnt, const void *buffer)
+ lbaint_t blkcnt, const void *buffer)
{
- unsigned long start, blks, buf_addr;
+ lbaint_t start, blks;
+ uintptr_t buf_addr;
unsigned short smallblks;
struct usb_device *dev;
struct us_data *ss;
start = blknr;
blks = blkcnt;
- USB_STOR_PRINTF("\nusb_write: dev %d startblk %lx, blccnt %lx"
+ USB_STOR_PRINTF("\nusb_write: dev %d startblk " LBAF ", blccnt " LBAF
" buffer %lx\n", device, start, blks, buf_addr);
do {
} while (blks != 0);
ss->flags &= ~USB_READY;
- USB_STOR_PRINTF("usb_write: end startblk %lx, blccnt %x buffer %lx\n",
+ USB_STOR_PRINTF("usb_write: end startblk " LBAF
+ ", blccnt %x buffer %lx\n",
start, smallblks, buf_addr);
usb_disable_asynch(0); /* asynch transfer allowed */
#########################################################################
+include $(TOPDIR)/helper.mk
+
ifeq ($(CURDIR),$(SRCTREE))
dir :=
else
OBJDUMP = $(CROSS_COMPILE)objdump
RANLIB = $(CROSS_COMPILE)RANLIB
DTC = dtc
+CHECK = sparse
#########################################################################
LDFLAGS_u-boot-spl += -Ttext $(CONFIG_SPL_TEXT_BASE)
endif
+# Linus' kernel sanity checking tool
+CHECKFLAGS := -D__linux__ -Dlinux -D__STDC__ -Dunix -D__unix__ \
+ -Wbitwise -Wno-return-void -D__CHECK_ENDIAN__ $(CF)
+
# Location of a usable BFD library, where we define "usable" as
# "built for ${HOST}, supports ${TARGET}". Sensible values are
# - When cross-compiling: the root of the cross-environment
$(obj)%.o: %.S
$(CC) $(ALL_AFLAGS) -o $@ $< -c
$(obj)%.o: %.c
+ifneq ($(CHECKSRC),0)
+ $(CHECK) $(CHECKFLAGS) $(ALL_CFLAGS) $<
+endif
$(CC) $(ALL_CFLAGS) -o $@ $< -c
$(obj)%.i: %.c
$(CPP) $(ALL_CFLAGS) -o $@ $< -c
#define PRINTF(fmt,args...)
#endif
+/* Rather than repeat this expression each time, add a define for it */
#if (defined(CONFIG_CMD_IDE) || \
defined(CONFIG_CMD_SATA) || \
defined(CONFIG_CMD_SCSI) || \
defined(CONFIG_CMD_USB) || \
defined(CONFIG_MMC) || \
defined(CONFIG_SYSTEMACE) )
+#define HAVE_BLOCK_DEVICE
+#endif
struct block_drvr {
char *name;
DECLARE_GLOBAL_DATA_PTR;
+#ifdef HAVE_BLOCK_DEVICE
block_dev_desc_t *get_dev(const char *ifname, int dev)
{
const struct block_drvr *drvr = block_drvr;
}
#endif
-#if (defined(CONFIG_CMD_IDE) || \
- defined(CONFIG_CMD_SATA) || \
- defined(CONFIG_CMD_SCSI) || \
- defined(CONFIG_CMD_USB) || \
- defined(CONFIG_MMC) || \
- defined(CONFIG_SYSTEMACE) )
+#ifdef HAVE_BLOCK_DEVICE
/* ------------------------------------------------------------------------- */
/*
}
#endif
-#if (defined(CONFIG_CMD_IDE) || \
- defined(CONFIG_CMD_SATA) || \
- defined(CONFIG_CMD_SCSI) || \
- defined(CONFIG_CMD_USB) || \
- defined(CONFIG_MMC) || \
- defined(CONFIG_SYSTEMACE) )
-
-#if defined(CONFIG_MAC_PARTITION) || \
- defined(CONFIG_DOS_PARTITION) || \
- defined(CONFIG_ISO_PARTITION) || \
- defined(CONFIG_AMIGA_PARTITION) || \
- defined(CONFIG_EFI_PARTITION)
+#ifdef HAVE_BLOCK_DEVICE
void init_part (block_dev_desc_t * dev_desc)
{
}
+#if defined(CONFIG_MAC_PARTITION) || \
+ defined(CONFIG_DOS_PARTITION) || \
+ defined(CONFIG_ISO_PARTITION) || \
+ defined(CONFIG_AMIGA_PARTITION) || \
+ defined(CONFIG_EFI_PARTITION)
+
static void print_part_header (const char *type, block_dev_desc_t * dev_desc)
{
puts ("\nPartition Map for ");
dev_desc->dev, type);
}
+#endif /* any CONFIG_..._PARTITION */
+
void print_part (block_dev_desc_t * dev_desc)
{
puts ("## Unknown partition table\n");
}
-
-#else /* neither MAC nor DOS nor ISO nor AMIGA nor EFI partition configured */
-# error neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION
-# error nor CONFIG_ISO_PARTITION nor CONFIG_AMIGA_PARTITION
-# error nor CONFIG_EFI_PARTITION configured!
-#endif
-
-#endif
+#endif /* HAVE_BLOCK_DEVICE */
int get_partition_info(block_dev_desc_t *dev_desc, int part
, disk_partition_t *info)
{
-#if defined(CONFIG_CMD_IDE) || \
- defined(CONFIG_CMD_SATA) || \
- defined(CONFIG_CMD_SCSI) || \
- defined(CONFIG_CMD_USB) || \
- defined(CONFIG_MMC) || \
- defined(CONFIG_SYSTEMACE)
+#ifdef HAVE_BLOCK_DEVICE
#ifdef CONFIG_PARTITION_UUIDS
/* The common case is no UUID support */
default:
break;
}
-#endif
+#endif /* HAVE_BLOCK_DEVICE */
return -1;
}
info->size = (*dev_desc)->lba;
info->blksz = (*dev_desc)->blksz;
info->bootable = 0;
+ strcpy((char *)info->type, BOOT_PART_TYPE);
+ strcpy((char *)info->name, "Whole Disk");
#ifdef CONFIG_PARTITION_UUIDS
info->uuid[0] = 0;
#endif
*/
if (p == MAX_SEARCH_PARTITIONS + 1)
*info = tmpinfo;
- ret = 0;
} else {
printf("** No valid partitions found **\n");
+ ret = -1;
goto cleanup;
}
}
return p->boot_ind == 0x80;
}
-static void print_one_part (dos_partition_t *p, int ext_part_sector, int part_num)
+static void print_one_part(dos_partition_t *p, int ext_part_sector,
+ int part_num, unsigned int disksig)
{
int lba_start = ext_part_sector + le32_to_int (p->start4);
int lba_size = le32_to_int (p->size4);
- printf("%5d\t\t%10d\t%10d\t%2x%s%s\n",
- part_num, lba_start, lba_size, p->sys_ind,
+ printf("%3d\t%-10d\t%-10d\t%08x-%02x\t%02x%s%s\n",
+ part_num, lba_start, lba_size, disksig, part_num, p->sys_ind,
(is_extended(p->sys_ind) ? " Extd" : ""),
(is_bootable(p) ? " Boot" : ""));
}
/* Print a partition that is relative to its Extended partition table
*/
-static void print_partition_extended (block_dev_desc_t *dev_desc, int ext_part_sector, int relative,
- int part_num)
+static void print_partition_extended(block_dev_desc_t *dev_desc,
+ int ext_part_sector, int relative,
+ int part_num, unsigned int disksig)
{
ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
dos_partition_t *pt;
return;
}
+ if (!ext_part_sector)
+ disksig = le32_to_int(&buffer[DOS_PART_DISKSIG_OFFSET]);
+
/* Print all primary/logical partitions */
pt = (dos_partition_t *) (buffer + DOS_PART_TBL_OFFSET);
for (i = 0; i < 4; i++, pt++) {
if ((pt->sys_ind != 0) &&
(ext_part_sector == 0 || !is_extended (pt->sys_ind)) ) {
- print_one_part (pt, ext_part_sector, part_num);
+ print_one_part(pt, ext_part_sector, part_num, disksig);
}
/* Reverse engr the fdisk part# assignment rule! */
if (is_extended (pt->sys_ind)) {
int lba_start = le32_to_int (pt->start4) + relative;
- print_partition_extended (dev_desc, lba_start,
- ext_part_sector == 0 ? lba_start
- : relative,
- part_num);
+ print_partition_extended(dev_desc, lba_start,
+ ext_part_sector == 0 ? lba_start : relative,
+ part_num, disksig);
}
}
void print_part_dos (block_dev_desc_t *dev_desc)
{
- printf ("Partition Start Sector Num Sectors Type\n");
- print_partition_extended (dev_desc, 0, 0, 1);
+ printf("Part\tStart Sector\tNum Sectors\tUUID\t\tType\n");
+ print_partition_extended(dev_desc, 0, 0, 1, 0);
}
int get_partition_info_dos (block_dev_desc_t *dev_desc, int part, disk_partition_t * info)
return name;
}
+static void uuid_string(unsigned char *uuid, char *str)
+{
+ static const u8 le[16] = {3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11,
+ 12, 13, 14, 15};
+ int i;
+
+ for (i = 0; i < 16; i++) {
+ sprintf(str, "%02x", uuid[le[i]]);
+ str += 2;
+ switch (i) {
+ case 3:
+ case 5:
+ case 7:
+ case 9:
+ *str++ = '-';
+ break;
+ }
+ }
+}
+
+static efi_guid_t system_guid = PARTITION_SYSTEM_GUID;
+
+static inline int is_bootable(gpt_entry *p)
+{
+ return p->attributes.fields.legacy_bios_bootable ||
+ !memcmp(&(p->partition_type_guid), &system_guid,
+ sizeof(efi_guid_t));
+}
+
/*
* Public Functions (include/part.h)
*/
ALLOC_CACHE_ALIGN_BUFFER(gpt_header, gpt_head, 1);
gpt_entry *gpt_pte = NULL;
int i = 0;
+ char uuid[37];
if (!dev_desc) {
printf("%s: Invalid Argument(s)\n", __func__);
debug("%s: gpt-entry at %p\n", __func__, gpt_pte);
- printf("Part\tName\t\t\tStart LBA\tEnd LBA\n");
+ printf("Part\tStart LBA\tEnd LBA\t\tName\n");
+ printf("\tAttributes\n");
+ printf("\tType UUID\n");
+ printf("\tPartition UUID\n");
+
for (i = 0; i < le32_to_int(gpt_head->num_partition_entries); i++) {
+ /* Stop at the first non valid PTE */
+ if (!is_pte_valid(&gpt_pte[i]))
+ break;
- if (is_pte_valid(&gpt_pte[i])) {
- printf("%3d\t%-18s\t0x%08llX\t0x%08llX\n", (i + 1),
- print_efiname(&gpt_pte[i]),
- le64_to_int(gpt_pte[i].starting_lba),
- le64_to_int(gpt_pte[i].ending_lba));
- } else {
- break; /* Stop at the first non valid PTE */
- }
+ printf("%3d\t0x%08llx\t0x%08llx\t\"%s\"\n", (i + 1),
+ le64_to_int(gpt_pte[i].starting_lba),
+ le64_to_int(gpt_pte[i].ending_lba),
+ print_efiname(&gpt_pte[i]));
+ printf("\tattrs:\t0x%016llx\n", gpt_pte[i].attributes.raw);
+ uuid_string(gpt_pte[i].partition_type_guid.b, uuid);
+ printf("\ttype:\t%s\n", uuid);
+ uuid_string(gpt_pte[i].unique_partition_guid.b, uuid);
+ printf("\tuuid:\t%s\n", uuid);
}
/* Remember to free pte */
return;
}
-#ifdef CONFIG_PARTITION_UUIDS
-static void uuid_string(unsigned char *uuid, char *str)
-{
- static const u8 le[16] = {3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11,
- 12, 13, 14, 15};
- int i;
-
- for (i = 0; i < 16; i++) {
- sprintf(str, "%02x", uuid[le[i]]);
- str += 2;
- switch (i) {
- case 3:
- case 5:
- case 7:
- case 9:
- *str++ = '-';
- break;
- }
- }
-}
-#endif
-
int get_partition_info_efi(block_dev_desc_t * dev_desc, int part,
disk_partition_t * info)
{
sprintf((char *)info->name, "%s",
print_efiname(&gpt_pte[part - 1]));
sprintf((char *)info->type, "U-Boot");
+ info->bootable = is_bootable(&gpt_pte[part - 1]);
#ifdef CONFIG_PARTITION_UUIDS
uuid_string(gpt_pte[part - 1].unique_partition_guid.b, info->uuid);
#endif
count = le32_to_int(pgpt_head->num_partition_entries) *
le32_to_int(pgpt_head->sizeof_partition_entry);
- debug("%s: count = %lu * %lu = %u\n", __func__,
+ debug("%s: count = %lu * %lu = %zu\n", __func__,
le32_to_int(pgpt_head->num_partition_entries),
le32_to_int(pgpt_head->sizeof_partition_entry), count);
}
if (count == 0 || pte == NULL) {
- printf("%s: ERROR: Can't allocate 0x%X bytes for GPT Entries\n",
+ printf("%s: ERROR: Can't allocate 0x%zX "
+ "bytes for GPT Entries\n",
__func__, count);
return NULL;
}
sizeof(unused_guid.b)) == 0) {
debug("%s: Found an unused PTE GUID at 0x%08X\n", __func__,
- (unsigned int)pte);
+ (unsigned int)(uintptr_t)pte);
return 0;
} else {
unsigned char reserved2[GPT_BLOCK_SIZE - 92];
} __attribute__ ((packed)) gpt_header;
-typedef struct _gpt_entry_attributes {
- unsigned long long required_to_function:1;
- unsigned long long reserved:47;
- unsigned long long type_guid_specific:16;
+typedef union _gpt_entry_attributes {
+ struct {
+ unsigned long long required_to_function:1;
+ unsigned long long no_block_io_protocol:1;
+ unsigned long long legacy_bios_bootable:1;
+ unsigned long long reserved:45;
+ unsigned long long type_guid_specific:16;
+ } fields;
+ unsigned long long raw;
} __attribute__ ((packed)) gpt_entry_attributes;
#define PARTNAME_SZ (72 / sizeof(efi_char16_t))
--- /dev/null
+*/
+*.xml
+*.ps
+*.pdf
+*.html
+*.9.gz
+*.9
+*.aux
+*.dvi
+*.log
+*.out
+*.png
+*.gif
+media-indices.tmpl
+media-entities.tmpl
--- /dev/null
+###
+# This makefile is used to generate the kernel documentation,
+# primarily based on in-line comments in various source files.
+# See doc/kernel-doc-nano-HOWTO.txt for instruction in how
+# to document the SRC - and how to read it.
+# To add a new book the only step required is to add the book to the
+# list of DOCBOOKS.
+
+include $(TOPDIR)/config.mk
+
+DOCBOOKS := linker_lists.xml stdio.xml
+
+###
+# The build process is as follows (targets):
+# (xmldocs) [by docproc]
+# file.tmpl --> file.xml +--> file.ps (psdocs) [by db2ps or xmlto]
+# +--> file.pdf (pdfdocs) [by db2pdf or xmlto]
+# +--> DIR=file (htmldocs) [by xmlto]
+# +--> man/ (mandocs) [by xmlto]
+
+
+# for PDF and PS output you can choose between xmlto and docbook-utils tools
+PDF_METHOD = $(prefer-db2x)
+PS_METHOD = $(prefer-db2x)
+
+
+###
+# The targets that may be used.
+PHONY += $(obj).depend xmldocs sgmldocs psdocs pdfdocs htmldocs mandocs installmandocs cleandocs
+
+BOOKS := $(addprefix $(OBJTREE)/doc/DocBook/,$(DOCBOOKS))
+xmldocs: $(BOOKS)
+sgmldocs: xmldocs
+
+PS := $(patsubst %.xml, %.ps, $(BOOKS))
+psdocs: $(PS)
+
+PDF := $(patsubst %.xml, %.pdf, $(BOOKS))
+pdfdocs: $(PDF)
+
+HTML := $(sort $(patsubst %.xml, %.html, $(BOOKS)))
+htmldocs: $(HTML)
+ $(call build_main_index)
+ $(call build_images)
+ $(call install_media_images)
+
+MAN := $(patsubst %.xml, %.9, $(BOOKS))
+mandocs: $(MAN)
+
+installmandocs: mandocs
+ mkdir -p /usr/local/man/man9/
+ install doc/DocBook/man/*.9.gz /usr/local/man/man9/
+
+###
+#External programs used
+KERNELDOC = $(SRCTREE)/tools/kernel-doc/kernel-doc
+DOCPROC = $(OBJTREE)/tools/kernel-doc/docproc
+
+XMLTOFLAGS = -m $(SRCTREE)/doc/DocBook/stylesheet.xsl
+XMLTOFLAGS += --skip-validation
+
+###
+# DOCPROC is used for two purposes:
+# 1) To generate a dependency list for a .tmpl file
+# 2) To preprocess a .tmpl file and call kernel-doc with
+# appropriate parameters.
+# The following rules are used to generate the .xml documentation
+# required to generate the final targets. (ps, pdf, html).
+%.xml: %.tmpl
+ $(DOCPROC) doc $< >$@
+
+ifeq ($@, "cleandocs")
+sinclude $(obj).depend
+$(obj).depend: $(patsubst %.xml, %.tmpl, $(DOCBOOKS))
+ rm -f $(obj).depend ; \
+ touch $(obj).depend ; \
+ for file in $^ ; do \
+ xmlfile=`echo "$${file}" | \
+ sed "s/tmpl$$/xml/"` ; \
+ echo -n "$${xmlfile}: ">> $(obj).depend ; \
+ $(DOCPROC) depend $$file >> $(obj).depend ; \
+ echo -e "\n\t$(DOCPROC) doc $< >$${xmlfile} " >> \
+ $(obj).depend ; \
+ done
+endif
+
+###
+# Changes in kernel-doc force a rebuild of all documentation
+$(BOOKS): $(KERNELDOC)
+
+notfoundtemplate = echo "*** You have to install docbook-utils or xmlto ***"; \
+ exit 1
+db2xtemplate = db2TYPE -o $(dir $@) $<
+xmltotemplate = xmlto TYPE $(XMLTOFLAGS) -o $(dir $@) $<
+
+# determine which methods are available
+ifeq ($(shell which db2ps >/dev/null 2>&1 && echo found),found)
+ use-db2x = db2x
+ prefer-db2x = db2x
+else
+ use-db2x = notfound
+ prefer-db2x = $(use-xmlto)
+endif
+ifeq ($(shell which xmlto >/dev/null 2>&1 && echo found),found)
+ use-xmlto = xmlto
+ prefer-xmlto = xmlto
+else
+ use-xmlto = notfound
+ prefer-xmlto = $(use-db2x)
+endif
+
+# the commands, generated from the chosen template
+quiet_cmd_db2ps = PS $@
+ cmd_db2ps = $(subst TYPE,ps, $($(PS_METHOD)template))
+%.ps : %.xml
+ $(call cmd_db2ps)
+
+quiet_cmd_db2pdf = PDF $@
+ cmd_db2pdf = $(subst TYPE,pdf, $($(PDF_METHOD)template))
+%.pdf : %.xml
+ $(call cmd_db2pdf)
+
+
+index = index.html
+main_idx = $(index)
+build_main_index = rm -rf $(main_idx); \
+ echo '<h1>U-Boot Bootloader HTML Documentation</h1>' >> $(main_idx) && \
+ echo '<h2>U-Boot Version: $(U_BOOT_VERSION)</h2>' >> $(main_idx) && \
+ cat $(HTML) >> $(main_idx)
+
+# To work around bug [1] in docbook-xsl-stylesheets 1.76.1 , generate only html
+# docs instead of xhtml with xmlto.
+# [1] http://bugs.debian.org/cgi-bin/bugreport.cgi?bug=654338
+quiet_cmd_db2html = HTML $@
+ cmd_db2html = xmlto html $(XMLTOFLAGS) -o $(patsubst %.html,%,$@) $< && \
+ echo '<a HREF="$(patsubst %.html,%,$(notdir $@))/index.html"> \
+ $(patsubst %.html,%,$(notdir $@))</a><p>' > $@
+
+%.html: %.xml
+ @(which xmlto > /dev/null 2>&1) || \
+ (echo "*** You need to install xmlto ***"; \
+ exit 1)
+ @rm -rf $@ $(patsubst %.html,%,$@)
+ $(call cmd_db2html)
+ @if [ ! -z "$(PNG-$(basename $(notdir $@)))" ]; then \
+ cp $(PNG-$(basename $(notdir $@))) $(patsubst %.html,%,$@); fi
+
+quiet_cmd_db2man = MAN $@
+ cmd_db2man = if grep -q refentry $<; then xmlto man $(XMLTOFLAGS) -o $(obj)/man $< ; gzip -f $(obj)/man/*.9; fi
+%.9 : %.xml
+ @(which xmlto > /dev/null 2>&1) || \
+ (echo "*** You need to install xmlto ***"; \
+ exit 1)
+ $(Q)mkdir -p $(obj)man
+ $(call cmd_db2man)
+ @touch $@
+
+###
+# Rules to generate postscripts and PNG images from .fig format files
+quiet_cmd_fig2eps = FIG2EPS $@
+ cmd_fig2eps = fig2dev -Leps $< $@
+
+%.eps: %.fig
+ @(which fig2dev > /dev/null 2>&1) || \
+ (echo "*** You need to install transfig ***"; \
+ exit 1)
+ $(call cmd_fig2eps)
+
+quiet_cmd_fig2png = FIG2PNG $@
+ cmd_fig2png = fig2dev -Lpng $< $@
+
+%.png: %.fig
+ @(which fig2dev > /dev/null 2>&1) || \
+ (echo "*** You need to install transfig ***"; \
+ exit 1)
+ $(call cmd_fig2png)
+
+###
+# Rule to convert a .c file to inline XML documentation
+ gen_xml = :
+ quiet_gen_xml = echo ' GEN $@'
+silent_gen_xml = :
+%.xml: %.c
+ @$($(quiet)gen_xml)
+ @( \
+ echo "<programlisting>"; \
+ expand --tabs=8 < $< | \
+ sed -e "s/&/\\&/g" \
+ -e "s/</\\</g" \
+ -e "s/>/\\>/g"; \
+ echo "</programlisting>") > $@
+
+###
+# Help targets as used by the top-level makefile
+dochelp:
+ @echo ' U-Boot bootloader internal documentation in different formats:'
+ @echo ' htmldocs - HTML'
+ @echo ' pdfdocs - PDF'
+ @echo ' psdocs - Postscript'
+ @echo ' xmldocs - XML DocBook'
+ @echo ' mandocs - man pages'
+ @echo ' installmandocs - install man pages generated by mandocs'
+ @echo ' cleandocs - clean all generated DocBook files'
+
+###
+# Temporary files left by various tools
+clean-files := $(DOCBOOKS) \
+ $(patsubst %.xml, %.dvi, $(DOCBOOKS)) \
+ $(patsubst %.xml, %.aux, $(DOCBOOKS)) \
+ $(patsubst %.xml, %.tex, $(DOCBOOKS)) \
+ $(patsubst %.xml, %.log, $(DOCBOOKS)) \
+ $(patsubst %.xml, %.out, $(DOCBOOKS)) \
+ $(patsubst %.xml, %.ps, $(DOCBOOKS)) \
+ $(patsubst %.xml, %.pdf, $(DOCBOOKS)) \
+ $(patsubst %.xml, %.html, $(DOCBOOKS)) \
+ $(patsubst %.xml, %.9, $(DOCBOOKS)) \
+ $(index)
+
+clean-dirs := $(patsubst %.xml,%,$(DOCBOOKS)) man
+
+cleandocs:
+ @rm -f $(obj).depend
+ @$(Q)rm -f $(call objectify, $(clean-files))
+ @$(Q)rm -rf $(call objectify, $(clean-dirs))
+
+# Declare the contents of the .PHONY variable as phony. We keep that
+# information in a variable se we can use it in if_changed and friends.
+
+.PHONY: $(PHONY)
--- /dev/null
+body {
+ font-family: sans-serif;
+}
+
+.programlisting {
+ font-family: monospace;
+ font-size: 1em;
+ display: block;
+ padding: 10px;
+ border: 1px solid #aaa;
+ color: #000;
+ background-color: #eee;
+ overflow: auto;
+ margin: 1em 0em;
+ border-radius: 6px;
+}
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE book PUBLIC "-//OASIS//DTD DocBook XML V4.1.2//EN"
+ "http://www.oasis-open.org/docbook/xml/4.1.2/docbookx.dtd" []>
+
+<book id="UBootLGArrays">
+ <bookinfo>
+ <title>The U-Boot Linker-Generated Arrays</title>
+
+ <legalnotice>
+ <para>
+ This documentation is free software; you can redistribute
+ it and/or modify it under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either
+ version 2 of the License, or (at your option) any later
+ version.
+ </para>
+
+ <para>
+ This program is distributed in the hope that it will be
+ useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU General Public License for more details.
+ </para>
+
+ <para>
+ You should have received a copy of the GNU General Public
+ License along with this program; if not, write to the Free
+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ MA 02111-1307 USA
+ </para>
+
+ <para>
+ For more details see the file COPYING in the source
+ distribution of U-Boot Bootloader.
+ </para>
+ </legalnotice>
+ </bookinfo>
+
+<toc></toc>
+
+ <chapter id="adt">
+ <title>Linker-Generated Arrays</title>
+!Iinclude/linker_lists.h
+ </chapter>
+
+</book>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<!DOCTYPE book PUBLIC "-//OASIS//DTD DocBook XML V4.1.2//EN"
+ "http://www.oasis-open.org/docbook/xml/4.1.2/docbookx.dtd" []>
+
+<book id="UBootSTDIO">
+ <bookinfo>
+ <title>The U-Boot STDIO subsystem</title>
+
+ <legalnotice>
+ <para>
+ This documentation is free software; you can redistribute
+ it and/or modify it under the terms of the GNU General Public
+ License as published by the Free Software Foundation; either
+ version 2 of the License, or (at your option) any later
+ version.
+ </para>
+
+ <para>
+ This program is distributed in the hope that it will be
+ useful, but WITHOUT ANY WARRANTY; without even the implied
+ warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ See the GNU General Public License for more details.
+ </para>
+
+ <para>
+ You should have received a copy of the GNU General Public
+ License along with this program; if not, write to the Free
+ Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ MA 02111-1307 USA
+ </para>
+
+ <para>
+ For more details see the file COPYING in the source
+ distribution of U-Boot Bootloader.
+ </para>
+ </legalnotice>
+ </bookinfo>
+
+<toc></toc>
+
+ <chapter id="adt">
+ <title>U-Boot Serial subsystem</title>
+!Idrivers/serial/serial.c
+ </chapter>
+
+</book>
--- /dev/null
+<?xml version="1.0" encoding="UTF-8"?>
+<stylesheet xmlns="http://www.w3.org/1999/XSL/Transform" version="1.0">
+<param name="chunk.quietly">1</param>
+<param name="funcsynopsis.style">ansi</param>
+<param name="funcsynopsis.tabular.threshold">80</param>
+<param name="callout.graphics">0</param>
+<!-- <param name="paper.type">A4</param> -->
+<param name="generate.section.toc.level">2</param>
+<param name="use.id.as.filename">1</param>
+<param name="html.stylesheet">../docbook.css</param>
+</stylesheet>
--- /dev/null
+If you are reading this because of a data abort: the following MIGHT
+be relevant to your abort, if it was caused by an alignment violation.
+In order to determine this, use the PC from the abort dump along with
+an objdump -s -S of the u-boot ELF binary to locate the function where
+the abort happened; then compare this function with the examples below.
+If they match, then you've been hit with a compiler generated unaligned
+access, and you should rewrite your code or add -mno-unaligned-access
+to the command line of the offending file.
+
+Note that the PC shown in the abort message is relocated. In order to
+be able to match it to an address in the ELF binary dump, you will need
+to know the relocation offset. If your target defines CONFIG_CMD_BDI
+and if you can get to the prompt and enter commands before the abort
+happens, then command "bdinfo" will give you the offset. Otherwise you
+will need to try a build with DEBUG set, which will display the offset,
+or use a debugger and set a breakpoint at relocate_code() to see the
+offset (passed as an argument).
+
+*
+
+Since U-Boot runs on a variety of hardware, some only able to perform
+unaligned accesses with a strong penalty, some unable to perform them
+at all, the policy regarding unaligned accesses is to not perform any,
+unless absolutely necessary because of hardware or standards.
+
+Also, on hardware which permits it, the core is configured to throw
+data abort exceptions on unaligned accesses in order to catch these
+unallowed accesses as early as possible.
+
+Until version 4.7, the gcc default for performing unaligned accesses
+(-mno-unaligned-access) is to emulate unaligned accesses using aligned
+loads and stores plus shifts and masks. Emulated unaligned accesses
+will not be caught by hardware. These accesses may be costly and may
+be actually unnecessary. In order to catch these accesses and remove
+or optimize them, option -munaligned-access is explicitly set for all
+versions of gcc which support it.
+
+From gcc 4.7 onward starting at armv7 architectures, the default for
+performing unaligned accesses is to use unaligned native loads and
+stores (-munaligned-access), because the cost of unaligned accesses
+has dropped on armv7 and beyond. This should not affect U-Boot's
+policy of controlling unaligned accesses, however the compiler may
+generate uncontrolled unaligned accesses on its own in at least one
+known case: when declaring a local initialized char array, e.g.
+
+function foo()
+{
+ char buffer[] = "initial value";
+/* or */
+ char buffer[] = { 'i', 'n', 'i', 't', 0 };
+ ...
+}
+
+Under -munaligned-accesses with optimizations on, this declaration
+causes the compiler to generate native loads from the literal string
+and native stores to the buffer, and the literal string alignment
+cannot be controlled. If it is misaligned, then the core will throw
+a data abort exception.
+
+Quite probably the same might happen for 16-bit array initializations
+where the constant is aligned on a boundary which is a multiple of 2
+but not of 4:
+
+function foo()
+{
+ u16 buffer[] = { 1, 2, 3 };
+ ...
+}
+
+The long term solution to this issue is to add an option to gcc to
+allow controlling the general alignment of data, including constant
+initialization values.
+
+However this will only apply to the version of gcc which will have such
+an option. For other versions, there are four workarounds:
+
+a) Enforce as a rule that array initializations as described above
+ are forbidden. This is generally not acceptable as they are valid,
+ and usual, C constructs. The only case where they could be rejected
+ is when they actually equate to a const char* declaration, i.e. the
+ array is initialized and never modified in the function's scope.
+
+b) Drop the requirement on unaligned accesses at least for ARMv7,
+ i.e. do not throw a data abort exception upon unaligned accesses.
+ But that will allow adding badly aligned code to U-Boot, only for
+ it to fail when re-used with a stricter target, possibly once the
+ bad code is already in mainline.
+
+c) Relax the -munaligned-access rule globally. This will prevent native
+ unaligned accesses of course, but that will also hide any bug caused
+ by a bad unaligned access, making it much harder to diagnose it. It
+ is actually what already happens when building ARM targets with a
+ pre-4.7 gcc, and it may actually already hide some bugs yet unseen
+ until the target gets compiled with -munaligned-access.
+
+d) Relax the -munaligned-access rule only for for files susceptible to
+ the local initialized array issue and for armv7 architectures and
+ beyond. This minimizes the quantity of code which can hide unwanted
+ misaligned accesses.
+
+The option retained is d).
+
+Considering that actual occurrences of the issue are rare (as of this
+writing, 5 files out of 7840 in U-Boot, or .3%, contain an initialized
+local char array which cannot actually be replaced with a const char*),
+contributors should not be required to systematically try and detect
+the issue in their patches.
+
+Detecting files susceptible to the issue can be automated through a
+filter installed as a hook in .git which recognizes local char array
+initializations. Automation should err on the false positive side, for
+instance flagging non-local arrays as if they were local if they cannot
+be told apart.
+
+In any case, detection shall not prevent committing the patch, but
+shall pre-populate the commit message with a note to the effect that
+this patch contains an initialized local char or 16-bit array and thus
+should be protected from the gcc 4.7 issue.
+
+Upon a positive detection, either $(PLATFORM_NO_UNALIGNED) should be
+added to CFLAGS for the affected file(s), or if the array is a pseudo
+const char*, it should be replaced by an actual one.
**** Behind the scene ******
-The structure created is named with a special prefix (__u_boot_cmd_)
+The structure created is named with a special prefix (__u_boot_list_cmd_)
and placed by the linker in a special section.
This makes it possible for the final link to extract all commands
compiled into any object code and construct a static array so the
-command can be found in an array starting at __u_boot_cmd_start.
+command can be found in an array starting at _u_boot_list_cmd__start.
To ensure that the linker does not discard these symbols when linking
full U-Boot we generate a list of all the commands we have built (based
by writing in u-boot.lds ($(TOPDIR)/board/boardname/u-boot.lds) these
3 lines:
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+ .u_boot_list : {
+ #include "u-boot.lst";
+ }
-------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 17) serial_lh7a40x.c
+ 17) serial_lpc2292.c
--------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 18) serial_lpc2292.c
+ 18) serial_max3100.c
--------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 19) serial_max3100.c
- --------------------
- No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
-
- 20) serial_mxc.c
+ 19) serial_mxc.c
----------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 21) serial_netarm.c
+ 20) serial_netarm.c
-------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 22) serial_pl01x.c
+ 21) serial_pl01x.c
------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible, though this
driver in fact contains two drivers in total.
- 23) serial_pxa.c
+ 22) serial_pxa.c
----------------
This driver is a bit complicated, but due to clean support for
CONFIG_SERIAL_MULTI, there are no expected obstructions throughout the
conversion process.
- 24) serial_s3c24x0.c
+ 23) serial_s3c24x0.c
--------------------
This driver, being quite ad-hoc might need some work to bring back to shape.
- 25) serial_s3c44b0.c
+ 24) serial_s3c44b0.c
--------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 26) serial_s5p.c
+ 25) serial_s5p.c
----------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 27) serial_sa1100.c
+ 26) serial_sa1100.c
-------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 28) serial_sh.c
+ 27) serial_sh.c
---------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 29) serial_xuartlite.c
+ 28) serial_xuartlite.c
----------------------
No support for CONFIG_SERIAL_MULTI. Simple conversion possible.
- 30) usbtty.c
+ 29) usbtty.c
------------
This driver seems very complicated and entangled with USB framework. The
conversion might be complicated here.
- 31) arch/powerpc/cpu/mpc512x/serial.c
+ 30) arch/powerpc/cpu/mpc512x/serial.c
-------------------------------------
This driver supports CONFIG_SERIAL_MULTI. This driver will need to be moved to
proper place.
# Subsystem aliases
alias cfi uboot, stroese
+alias kerneldoc uboot, marex
alias fdt uboot, Jerry Van Baren <vanbaren@cideas.com>
alias i2c uboot, hs
alias mmc uboot, afleming
#include <part.h>
#include <ide.h>
#include <ata.h>
+#include <sata.h>
-extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
-extern int sata_curr_device;
-
-#define DEBUG_SATA 0 /*For debug prints set DEBUG_SATA to 1 */
+#define DEBUG_SATA 0 /* For debug prints set DEBUG_SATA to 1 */
#define SATA_DECL
-#define DRV_DECL /*For file specific declarations */
+#define DRV_DECL /* For file specific declarations */
#include "ata_piix.h"
-/*Macros realted to PCI*/
+/* Macros realted to PCI */
#define PCI_SATA_BUS 0x00
#define PCI_SATA_DEV 0x1f
#define PCI_SATA_FUNC 0x02
#define PORT_ENABLED (1<<4)
u32 bdf;
-u32 iobase1 = 0; /*Primary cmd block */
-u32 iobase2 = 0; /*Primary ctl block */
-u32 iobase3 = 0; /*Sec cmd block */
-u32 iobase4 = 0; /*sec ctl block */
-u32 iobase5 = 0; /*BMDMA*/
-int
-pci_sata_init (void)
+u32 iobase1; /* Primary cmd block */
+u32 iobase2; /* Primary ctl block */
+u32 iobase3; /* Sec cmd block */
+u32 iobase4; /* sec ctl block */
+u32 iobase5; /* BMDMA*/
+
+int pci_sata_init(void)
{
u32 bus = PCI_SATA_BUS;
u32 dev = PCI_SATA_DEV;
u32 fun = PCI_SATA_FUNC;
u16 cmd = 0;
u8 lat = 0, pcibios_max_latency = 0xff;
- u8 pmr; /*Port mapping reg */
- u8 pi; /*Prgming Interface reg */
+ u8 pmr; /* Port mapping reg */
+ u8 pi; /* Prgming Interface reg */
- bdf = PCI_BDF (bus, dev, fun);
- pci_read_config_dword (bdf, PCI_SATA_BASE1, &iobase1);
- pci_read_config_dword (bdf, PCI_SATA_BASE2, &iobase2);
- pci_read_config_dword (bdf, PCI_SATA_BASE3, &iobase3);
- pci_read_config_dword (bdf, PCI_SATA_BASE4, &iobase4);
- pci_read_config_dword (bdf, PCI_SATA_BASE5, &iobase5);
+ bdf = PCI_BDF(bus, dev, fun);
+ pci_read_config_dword(bdf, PCI_SATA_BASE1, &iobase1);
+ pci_read_config_dword(bdf, PCI_SATA_BASE2, &iobase2);
+ pci_read_config_dword(bdf, PCI_SATA_BASE3, &iobase3);
+ pci_read_config_dword(bdf, PCI_SATA_BASE4, &iobase4);
+ pci_read_config_dword(bdf, PCI_SATA_BASE5, &iobase5);
if ((iobase1 == 0xFFFFFFFF) || (iobase2 == 0xFFFFFFFF) ||
(iobase3 == 0xFFFFFFFF) || (iobase4 == 0xFFFFFFFF) ||
(iobase5 == 0xFFFFFFFF)) {
- printf ("error no base addr for SATA controller\n");
+ /* ERROR */
+ printf("error no base addr for SATA controller\n");
return 1;
- /*ERROR*/}
+ }
iobase1 &= 0xFFFFFFFE;
iobase2 &= 0xFFFFFFFE;
iobase4 &= 0xFFFFFFFE;
iobase5 &= 0xFFFFFFFE;
- /*check for mode */
- pci_read_config_byte (bdf, PCI_PMR, &pmr);
+ /* check for mode */
+ pci_read_config_byte(bdf, PCI_PMR, &pmr);
if (pmr > 1) {
- printf ("combined mode not supported\n");
+ puts("combined mode not supported\n");
return 1;
}
- pci_read_config_byte (bdf, PCI_PI, &pi);
+ pci_read_config_byte(bdf, PCI_PI, &pi);
if ((pi & 0x05) != 0x05) {
- printf ("Sata is in Legacy mode\n");
+ puts("Sata is in Legacy mode\n");
return 1;
- } else {
- printf ("sata is in Native mode\n");
- }
+ } else
+ puts("sata is in Native mode\n");
- /*MASTER CFG AND IO CFG */
- pci_read_config_word (bdf, PCI_COMMAND, &cmd);
+ /* MASTER CFG AND IO CFG */
+ pci_read_config_word(bdf, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
- pci_write_config_word (bdf, PCI_COMMAND, cmd);
- pci_read_config_byte (dev, PCI_LATENCY_TIMER, &lat);
+ pci_write_config_word(bdf, PCI_COMMAND, cmd);
+ pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
if (lat < 16)
lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
else if (lat > pcibios_max_latency)
lat = pcibios_max_latency;
- pci_write_config_byte (dev, PCI_LATENCY_TIMER, lat);
+ pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
return 0;
}
-int
-sata_bus_probe (int port_no)
+int sata_bus_probe(int port_no)
{
int orig_mask, mask;
u16 pcs;
mask = (PORT_PRESENT << port_no);
- pci_read_config_word (bdf, PCI_PCS, &pcs);
+ pci_read_config_word(bdf, PCI_PCS, &pcs);
orig_mask = (int) pcs & 0xff;
if ((orig_mask & mask) != mask)
return 0;
return 1;
}
-int
-init_sata (int dev)
+int init_sata(int dev)
{
- static int done = 0;
+ static int done;
u8 i, rv = 0;
if (!done)
else
return 0;
- rv = pci_sata_init ();
+ rv = pci_sata_init();
if (rv == 1) {
- printf ("pci initialization failed\n");
+ puts("pci initialization failed\n");
return 1;
}
port[1].ioaddr.bmdma_addr = iobase5 + 0x8;
for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++)
- sata_port (&port[i].ioaddr);
+ sata_port(&port[i].ioaddr);
for (i = 0; i < CONFIG_SYS_SATA_MAXBUS; i++) {
- if (!(sata_bus_probe (i))) {
+ if (!(sata_bus_probe(i))) {
port[i].port_state = 0;
- printf ("SATA#%d port is not present \n", i);
+ printf("SATA#%d port is not present\n", i);
} else {
- printf ("SATA#%d port is present\n", i);
- if (sata_bus_softreset (i)) {
+ printf("SATA#%d port is present\n", i);
+ if (sata_bus_softreset(i))
port[i].port_state = 0;
- } else {
+ else
port[i].port_state = 1;
- }
}
}
if (port[i].port_state == 0)
continue;
for (j = 0; j < CONFIG_SYS_SATA_DEVS_PER_BUS; j++) {
- sata_identify (i, j);
- set_Feature_cmd (i, j);
+ sata_identify(i, j);
+ set_Feature_cmd(i, j);
devno = i * CONFIG_SYS_SATA_DEVS_PER_BUS + j;
if ((sata_dev_desc[devno].lba > 0) &&
(sata_dev_desc[devno].blksz > 0)) {
- dev_print (&sata_dev_desc[devno]);
+ dev_print(&sata_dev_desc[devno]);
/* initialize partition type */
- init_part (&sata_dev_desc[devno]);
+ init_part(&sata_dev_desc[devno]);
}
}
}
return 0;
}
-static u8 __inline__
-sata_inb (unsigned long ioaddr)
+static inline u8 sata_inb(unsigned long ioaddr)
{
- return inb (ioaddr);
+ return inb(ioaddr);
}
-static void __inline__
-sata_outb (unsigned char val, unsigned long ioaddr)
+static inline void sata_outb(unsigned char val, unsigned long ioaddr)
{
- outb (val, ioaddr);
+ outb(val, ioaddr);
}
-static void
-output_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words)
+static void output_data(struct sata_ioports *ioaddr, ulong * sect_buf,
+ int words)
{
- outsw (ioaddr->data_addr, sect_buf, words << 1);
+ outsw(ioaddr->data_addr, sect_buf, words << 1);
}
-static int
-input_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words)
+static int input_data(struct sata_ioports *ioaddr, ulong * sect_buf, int words)
{
- insw (ioaddr->data_addr, sect_buf, words << 1);
+ insw(ioaddr->data_addr, sect_buf, words << 1);
return 0;
}
-static void
-sata_cpy (unsigned char *dst, unsigned char *src, unsigned int len)
+static void sata_cpy(unsigned char *dst, unsigned char *src, unsigned int len)
{
unsigned char *end, *last;
if (*src++ != ' ')
last = dst;
}
- OUT:
+OUT:
*last = '\0';
}
-int
-sata_bus_softreset (int num)
+int sata_bus_softreset(int num)
{
u8 dev = 0, status = 0, i;
port[num].dev_mask = 0;
for (i = 0; i < CONFIG_SYS_SATA_DEVS_PER_BUS; i++) {
- if (!(sata_devchk (&port[num].ioaddr, i))) {
- PRINTF ("dev_chk failed for dev#%d\n", i);
+ if (!(sata_devchk(&port[num].ioaddr, i))) {
+ debug("dev_chk failed for dev#%d\n", i);
} else {
port[num].dev_mask |= (1 << i);
- PRINTF ("dev_chk passed for dev#%d\n", i);
+ debug("dev_chk passed for dev#%d\n", i);
}
}
if (!(port[num].dev_mask)) {
- printf ("no devices on port%d\n", num);
+ printf("no devices on port%d\n", num);
return 1;
}
- dev_select (&port[num].ioaddr, dev);
+ dev_select(&port[num].ioaddr, dev);
- port[num].ctl_reg = 0x08; /*Default value of control reg */
- sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
- udelay (10);
- sata_outb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
- udelay (10);
- sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
+ port[num].ctl_reg = 0x08; /* Default value of control reg */
+ sata_outb(port[num].ctl_reg, port[num].ioaddr.ctl_addr);
+ udelay(10);
+ sata_outb(port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
+ udelay(10);
+ sata_outb(port[num].ctl_reg, port[num].ioaddr.ctl_addr);
- /* spec mandates ">= 2ms" before checking status.
+ /*
+ * spec mandates ">= 2ms" before checking status.
* We wait 150ms, because that was the magic delay used for
* ATAPI devices in Hale Landis's ATADRVR, for the period of time
* between when the ATA command register is written, and then
* checking status is fine, post SRST, we perform this magic
* delay here as well.
*/
- msleep (150);
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300);
+ mdelay(150);
+ status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 300);
while ((status & ATA_BUSY)) {
- msleep (100);
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3);
+ mdelay(100);
+ status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 3);
}
if (status & ATA_BUSY)
- printf ("ata%u is slow to respond,plz be patient\n", num);
+ printf("ata%u is slow to respond,plz be patient\n", num);
while ((status & ATA_BUSY)) {
- msleep (100);
- status = sata_chk_status (&port[num].ioaddr);
+ mdelay(100);
+ status = sata_chk_status(&port[num].ioaddr);
}
if (status & ATA_BUSY) {
- printf ("ata%u failed to respond : ", num);
- printf ("bus reset failed\n");
+ printf("ata%u failed to respond : bus reset failed\n", num);
return 1;
}
return 0;
}
-void
-sata_identify (int num, int dev)
+void sata_identify(int num, int dev)
{
- u8 cmd = 0, status = 0, devno = num * CONFIG_SYS_SATA_DEVS_PER_BUS + dev;
+ u8 cmd = 0, status = 0;
+ u8 devno = num * CONFIG_SYS_SATA_DEVS_PER_BUS + dev;
u16 iobuf[ATA_SECT_SIZE];
u64 n_sectors = 0;
u8 mask = 0;
- memset (iobuf, 0, sizeof (iobuf));
+ memset(iobuf, 0, sizeof(iobuf));
hd_driveid_t *iop = (hd_driveid_t *) iobuf;
if (dev == 0)
mask = 0x02;
if (!(port[num].dev_mask & mask)) {
- printf ("dev%d is not present on port#%d\n", dev, num);
+ printf("dev%d is not present on port#%d\n", dev, num);
return;
}
- printf ("port=%d dev=%d\n", num, dev);
+ printf("port=%d dev=%d\n", num, dev);
- dev_select (&port[num].ioaddr, dev);
+ dev_select(&port[num].ioaddr, dev);
status = 0;
- cmd = ATA_CMD_IDENT; /*Device Identify Command */
- sata_outb (cmd, port[num].ioaddr.command_addr);
- sata_inb (port[num].ioaddr.altstatus_addr);
- udelay (10);
+ cmd = ATA_CMD_IDENT; /* Device Identify Command */
+ sata_outb(cmd, port[num].ioaddr.command_addr);
+ sata_inb(port[num].ioaddr.altstatus_addr);
+ udelay(10);
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000);
+ status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 1000);
if (status & ATA_ERR) {
- printf ("\ndevice not responding\n");
+ puts("\ndevice not responding\n");
port[num].dev_mask &= ~mask;
return;
}
- input_data (&port[num].ioaddr, (ulong *) iobuf, ATA_SECTORWORDS);
+ input_data(&port[num].ioaddr, (ulong *) iobuf, ATA_SECTORWORDS);
- PRINTF ("\nata%u: dev %u cfg 49:%04x 82:%04x 83:%04x 84:%04x85:%04x"
+ debug("\nata%u: dev %u cfg 49:%04x 82:%04x 83:%04x 84:%04x85:%04x"
"86:%04x" "87:%04x 88:%04x\n", num, dev, iobuf[49],
iobuf[82], iobuf[83], iobuf[84], iobuf[85], iobuf[86],
iobuf[87], iobuf[88]);
/* we require LBA and DMA support (bits 8 & 9 of word 49) */
- if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) {
- PRINTF ("ata%u: no dma/lba\n", num);
- }
- ata_dump_id (iobuf);
+ if (!ata_id_has_dma(iobuf) || !ata_id_has_lba(iobuf))
+ debug("ata%u: no dma/lba\n", num);
+ ata_dump_id(iobuf);
- if (ata_id_has_lba48 (iobuf)) {
- n_sectors = ata_id_u64 (iobuf, 100);
- } else {
- n_sectors = ata_id_u32 (iobuf, 60);
- }
- PRINTF ("no. of sectors %u\n", ata_id_u64 (iobuf, 100));
- PRINTF ("no. of sectors %u\n", ata_id_u32 (iobuf, 60));
+ if (ata_id_has_lba48(iobuf))
+ n_sectors = ata_id_u64(iobuf, 100);
+ else
+ n_sectors = ata_id_u32(iobuf, 60);
+ debug("no. of sectors %u\n", ata_id_u64(iobuf, 100));
+ debug("no. of sectors %u\n", ata_id_u32(iobuf, 60));
if (n_sectors == 0) {
port[num].dev_mask &= ~mask;
return;
}
- sata_cpy ((unsigned char *)sata_dev_desc[devno].revision, iop->fw_rev,
- sizeof (sata_dev_desc[devno].revision));
- sata_cpy ((unsigned char *)sata_dev_desc[devno].vendor, iop->model,
- sizeof (sata_dev_desc[devno].vendor));
- sata_cpy ((unsigned char *)sata_dev_desc[devno].product, iop->serial_no,
- sizeof (sata_dev_desc[devno].product));
- strswab (sata_dev_desc[devno].revision);
- strswab (sata_dev_desc[devno].vendor);
+ sata_cpy((unsigned char *)sata_dev_desc[devno].revision, iop->fw_rev,
+ sizeof(sata_dev_desc[devno].revision));
+ sata_cpy((unsigned char *)sata_dev_desc[devno].vendor, iop->model,
+ sizeof(sata_dev_desc[devno].vendor));
+ sata_cpy((unsigned char *)sata_dev_desc[devno].product, iop->serial_no,
+ sizeof(sata_dev_desc[devno].product));
+ strswab(sata_dev_desc[devno].revision);
+ strswab(sata_dev_desc[devno].vendor);
- if ((iop->config & 0x0080) == 0x0080) {
+ if ((iop->config & 0x0080) == 0x0080)
sata_dev_desc[devno].removable = 1;
- } else {
+ else
sata_dev_desc[devno].removable = 0;
- }
sata_dev_desc[devno].lba = iop->lba_capacity;
- PRINTF ("lba=0x%x", sata_dev_desc[devno].lba);
+ debug("lba=0x%x", sata_dev_desc[devno].lba);
#ifdef CONFIG_LBA48
if (iop->command_set_2 & 0x0400) {
sata_dev_desc[devno].lun = 0; /* just to fill something in... */
}
-void
-set_Feature_cmd (int num, int dev)
+void set_Feature_cmd(int num, int dev)
{
u8 mask = 0x00, status = 0;
mask = 0x02;
if (!(port[num].dev_mask & mask)) {
- PRINTF ("dev%d is not present on port#%d\n", dev, num);
+ debug("dev%d is not present on port#%d\n", dev, num);
return;
}
- dev_select (&port[num].ioaddr, dev);
+ dev_select(&port[num].ioaddr, dev);
- sata_outb (SETFEATURES_XFER, port[num].ioaddr.feature_addr);
- sata_outb (XFER_PIO_4, port[num].ioaddr.nsect_addr);
- sata_outb (0, port[num].ioaddr.lbal_addr);
- sata_outb (0, port[num].ioaddr.lbam_addr);
- sata_outb (0, port[num].ioaddr.lbah_addr);
+ sata_outb(SETFEATURES_XFER, port[num].ioaddr.feature_addr);
+ sata_outb(XFER_PIO_4, port[num].ioaddr.nsect_addr);
+ sata_outb(0, port[num].ioaddr.lbal_addr);
+ sata_outb(0, port[num].ioaddr.lbam_addr);
+ sata_outb(0, port[num].ioaddr.lbah_addr);
- sata_outb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
- sata_outb (ATA_CMD_SETF, port[num].ioaddr.command_addr);
+ sata_outb(ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
+ sata_outb(ATA_CMD_SETF, port[num].ioaddr.command_addr);
- udelay (50);
- msleep (150);
+ udelay(50);
+ mdelay(150);
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000);
+ status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 5000);
if ((status & (ATA_STAT_BUSY | ATA_STAT_ERR))) {
- printf ("Error : status 0x%02x\n", status);
+ printf("Error : status 0x%02x\n", status);
port[num].dev_mask &= ~mask;
}
}
-void
-sata_port (struct sata_ioports *ioport)
+void sata_port(struct sata_ioports *ioport)
{
ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
}
-int
-sata_devchk (struct sata_ioports *ioaddr, int dev)
+int sata_devchk(struct sata_ioports *ioaddr, int dev)
{
u8 nsect, lbal;
- dev_select (ioaddr, dev);
+ dev_select(ioaddr, dev);
- sata_outb (0x55, ioaddr->nsect_addr);
- sata_outb (0xaa, ioaddr->lbal_addr);
+ sata_outb(0x55, ioaddr->nsect_addr);
+ sata_outb(0xaa, ioaddr->lbal_addr);
- sata_outb (0xaa, ioaddr->nsect_addr);
- sata_outb (0x55, ioaddr->lbal_addr);
+ sata_outb(0xaa, ioaddr->nsect_addr);
+ sata_outb(0x55, ioaddr->lbal_addr);
- sata_outb (0x55, ioaddr->nsect_addr);
- sata_outb (0xaa, ioaddr->lbal_addr);
+ sata_outb(0x55, ioaddr->nsect_addr);
+ sata_outb(0xaa, ioaddr->lbal_addr);
- nsect = sata_inb (ioaddr->nsect_addr);
- lbal = sata_inb (ioaddr->lbal_addr);
+ nsect = sata_inb(ioaddr->nsect_addr);
+ lbal = sata_inb(ioaddr->lbal_addr);
if ((nsect == 0x55) && (lbal == 0xaa))
return 1; /* we found a device */
return 0; /* nothing found */
}
-void
-dev_select (struct sata_ioports *ioaddr, int dev)
+void dev_select(struct sata_ioports *ioaddr, int dev)
{
u8 tmp = 0;
else
tmp = ATA_DEVICE_OBS | ATA_DEV1;
- sata_outb (tmp, ioaddr->device_addr);
- sata_inb (ioaddr->altstatus_addr);
- udelay (5);
+ sata_outb(tmp, ioaddr->device_addr);
+ sata_inb(ioaddr->altstatus_addr);
+ udelay(5);
}
-u8
-sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max)
+u8 sata_busy_wait(struct sata_ioports *ioaddr, int bits, unsigned int max)
{
u8 status;
do {
- udelay (1000);
- status = sata_chk_status (ioaddr);
+ udelay(1000);
+ status = sata_chk_status(ioaddr);
max--;
} while ((status & bits) && (max > 0));
return status;
}
-u8
-sata_chk_status (struct sata_ioports * ioaddr)
+u8 sata_chk_status(struct sata_ioports *ioaddr)
{
- return sata_inb (ioaddr->status_addr);
+ return sata_inb(ioaddr->status_addr);
}
-void
-msleep (int count)
-{
- int i;
- for (i = 0; i < count; i++)
- udelay (1000);
-}
-
-ulong
-sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buff)
+ulong sata_read(int device, ulong blknr, lbaint_t blkcnt, void *buff)
{
ulong n = 0, *buffer = (ulong *)buff;
u8 dev = 0, num = 0, mask = 0, status = 0;
if (blknr & 0x0000fffff0000000) {
if (!sata_dev_desc[devno].lba48) {
- printf ("Drive doesn't support 48-bit addressing\n");
+ printf("Drive doesn't support 48-bit addressing\n");
return 0;
}
/* more than 28 bits used, use 48bit mode */
lba48 = 1;
}
#endif
- /*Port Number */
+ /* Port Number */
num = device / CONFIG_SYS_SATA_DEVS_PER_BUS;
- /*dev on the port */
+ /* dev on the port */
if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS)
dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS;
else
mask = 0x02;
if (!(port[num].dev_mask & mask)) {
- printf ("dev%d is not present on port#%d\n", dev, num);
+ printf("dev%d is not present on port#%d\n", dev, num);
return 0;
}
/* Select device */
- dev_select (&port[num].ioaddr, dev);
+ dev_select(&port[num].ioaddr, dev);
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
+ status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
if (status & ATA_BUSY) {
- printf ("ata%u failed to respond\n", port[num].port_no);
+ printf("ata%u failed to respond\n", port[num].port_no);
return n;
}
while (blkcnt-- > 0) {
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
+ status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
if (status & ATA_BUSY) {
- printf ("ata%u failed to respond\n", 0);
+ printf("ata%u failed to respond\n", 0);
return n;
}
#ifdef CONFIG_LBA48
if (lba48) {
/* write high bits */
- sata_outb (0, port[num].ioaddr.nsect_addr);
- sata_outb ((blknr >> 24) & 0xFF,
+ sata_outb(0, port[num].ioaddr.nsect_addr);
+ sata_outb((blknr >> 24) & 0xFF,
port[num].ioaddr.lbal_addr);
- sata_outb ((blknr >> 32) & 0xFF,
+ sata_outb((blknr >> 32) & 0xFF,
port[num].ioaddr.lbam_addr);
- sata_outb ((blknr >> 40) & 0xFF,
+ sata_outb((blknr >> 40) & 0xFF,
port[num].ioaddr.lbah_addr);
}
#endif
- sata_outb (1, port[num].ioaddr.nsect_addr);
- sata_outb (((blknr) >> 0) & 0xFF,
+ sata_outb(1, port[num].ioaddr.nsect_addr);
+ sata_outb(((blknr) >> 0) & 0xFF,
port[num].ioaddr.lbal_addr);
- sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
- sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
+ sata_outb((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
+ sata_outb((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
#ifdef CONFIG_LBA48
if (lba48) {
- sata_outb (ATA_LBA, port[num].ioaddr.device_addr);
- sata_outb (ATA_CMD_READ_EXT,
+ sata_outb(ATA_LBA, port[num].ioaddr.device_addr);
+ sata_outb(ATA_CMD_READ_EXT,
port[num].ioaddr.command_addr);
} else
#endif
{
- sata_outb (ATA_LBA | ((blknr >> 24) & 0xF),
+ sata_outb(ATA_LBA | ((blknr >> 24) & 0xF),
port[num].ioaddr.device_addr);
- sata_outb (ATA_CMD_READ,
+ sata_outb(ATA_CMD_READ,
port[num].ioaddr.command_addr);
}
- msleep (50);
- /*may take up to 4 sec */
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000);
+ mdelay(50);
+ /* may take up to 4 sec */
+ status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 4000);
if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
!= ATA_STAT_DRQ) {
u8 err = 0;
- printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
+ printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
device, (ulong) blknr, status);
- err = sata_inb (port[num].ioaddr.error_addr);
- printf ("Error reg = 0x%x\n", err);
- return (n);
+ err = sata_inb(port[num].ioaddr.error_addr);
+ printf("Error reg = 0x%x\n", err);
+ return n;
}
- input_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS);
- sata_inb (port[num].ioaddr.altstatus_addr);
- udelay (50);
+ input_data(&port[num].ioaddr, buffer, ATA_SECTORWORDS);
+ sata_inb(port[num].ioaddr.altstatus_addr);
+ udelay(50);
++n;
++blknr;
return n;
}
-ulong
-sata_write (int device, ulong blknr,lbaint_t blkcnt, void * buff)
+ulong sata_write(int device, ulong blknr, lbaint_t blkcnt, const void *buff)
{
ulong n = 0, *buffer = (ulong *)buff;
unsigned char status = 0, num = 0, dev = 0, mask = 0;
if (blknr & 0x0000fffff0000000) {
if (!sata_dev_desc[devno].lba48) {
- printf ("Drive doesn't support 48-bit addressing\n");
+ printf("Drive doesn't support 48-bit addressing\n");
return 0;
}
/* more than 28 bits used, use 48bit mode */
lba48 = 1;
}
#endif
- /*Port Number */
+ /* Port Number */
num = device / CONFIG_SYS_SATA_DEVS_PER_BUS;
- /*dev on the Port */
+ /* dev on the Port */
if (device >= CONFIG_SYS_SATA_DEVS_PER_BUS)
dev = device - CONFIG_SYS_SATA_DEVS_PER_BUS;
else
mask = 0x02;
/* Select device */
- dev_select (&port[num].ioaddr, dev);
+ dev_select(&port[num].ioaddr, dev);
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
+ status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
if (status & ATA_BUSY) {
- printf ("ata%u failed to respond\n", port[num].port_no);
+ printf("ata%u failed to respond\n", port[num].port_no);
return n;
}
while (blkcnt-- > 0) {
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
+ status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 500);
if (status & ATA_BUSY) {
- printf ("ata%u failed to respond\n",
+ printf("ata%u failed to respond\n",
port[num].port_no);
return n;
}
#ifdef CONFIG_LBA48
if (lba48) {
/* write high bits */
- sata_outb (0, port[num].ioaddr.nsect_addr);
- sata_outb ((blknr >> 24) & 0xFF,
+ sata_outb(0, port[num].ioaddr.nsect_addr);
+ sata_outb((blknr >> 24) & 0xFF,
port[num].ioaddr.lbal_addr);
- sata_outb ((blknr >> 32) & 0xFF,
+ sata_outb((blknr >> 32) & 0xFF,
port[num].ioaddr.lbam_addr);
- sata_outb ((blknr >> 40) & 0xFF,
+ sata_outb((blknr >> 40) & 0xFF,
port[num].ioaddr.lbah_addr);
}
#endif
- sata_outb (1, port[num].ioaddr.nsect_addr);
- sata_outb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
- sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
- sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
+ sata_outb(1, port[num].ioaddr.nsect_addr);
+ sata_outb((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
+ sata_outb((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
+ sata_outb((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
#ifdef CONFIG_LBA48
if (lba48) {
- sata_outb (ATA_LBA, port[num].ioaddr.device_addr);
- sata_outb (ATA_CMD_WRITE_EXT,
+ sata_outb(ATA_LBA, port[num].ioaddr.device_addr);
+ sata_outb(ATA_CMD_WRITE_EXT,
port[num].ioaddr.command_addr);
} else
#endif
{
- sata_outb (ATA_LBA | ((blknr >> 24) & 0xF),
+ sata_outb(ATA_LBA | ((blknr >> 24) & 0xF),
port[num].ioaddr.device_addr);
- sata_outb (ATA_CMD_WRITE,
+ sata_outb(ATA_CMD_WRITE,
port[num].ioaddr.command_addr);
}
- msleep (50);
- /*may take up to 4 sec */
- status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000);
+ mdelay(50);
+ /* may take up to 4 sec */
+ status = sata_busy_wait(&port[num].ioaddr, ATA_BUSY, 4000);
if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
!= ATA_STAT_DRQ) {
- printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
+ printf("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
device, (ulong) blknr, status);
- return (n);
+ return n;
}
- output_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS);
- sata_inb (port[num].ioaddr.altstatus_addr);
- udelay (50);
+ output_data(&port[num].ioaddr, buffer, ATA_SECTORWORDS);
+ sata_inb(port[num].ioaddr.altstatus_addr);
+ udelay(50);
++n;
++blknr;
#ifndef __ATA_PIIX_H__
#define __ATA_PIIX_H__
-#if (DEBUG_SATA)
-#define PRINTF(fmt,args...) printf (fmt ,##args)
-#else
-#define PRINTF(fmt,args...)
-#endif
-
struct sata_ioports {
unsigned long cmd_addr;
unsigned long data_addr;
};
/***********SATA LIBRARY SPECIFIC DEFINITIONS AND DECLARATIONS**************/
-#ifdef SATA_DECL /*SATA library specific declarations */
-inline void
-ata_dump_id (u16 * id)
+#ifdef SATA_DECL /* SATA library specific declarations */
+inline void ata_dump_id(u16 *id)
{
- PRINTF ("49 = 0x%04x "
+ debug("49 = 0x%04x "
"53 = 0x%04x "
"63 = 0x%04x "
"64 = 0x%04x "
- "75 = 0x%04x \n", id[49], id[53], id[63], id[64], id[75]);
- PRINTF ("80 = 0x%04x "
+ "75 = 0x%04x\n", id[49], id[53], id[63], id[64], id[75]);
+ debug("80 = 0x%04x "
"81 = 0x%04x "
"82 = 0x%04x "
"83 = 0x%04x "
- "84 = 0x%04x \n", id[80], id[81], id[82], id[83], id[84]);
- PRINTF ("88 = 0x%04x " "93 = 0x%04x\n", id[88], id[93]);
+ "84 = 0x%04x\n", id[80], id[81], id[82], id[83], id[84]);
+ debug("88 = 0x%04x " "93 = 0x%04x\n", id[88], id[93]);
}
#endif
#ifdef SATA_DECL /*SATA library specific declarations */
-int sata_bus_softreset (int num);
-void sata_identify (int num, int dev);
-void sata_port (struct sata_ioports *ioport);
-void set_Feature_cmd (int num, int dev);
-int sata_devchk (struct sata_ioports *ioaddr, int dev);
-void dev_select (struct sata_ioports *ioaddr, int dev);
-u8 sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max);
-u8 sata_chk_status (struct sata_ioports *ioaddr);
-ulong sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buffer);
-ulong sata_write (int device,ulong blknr, lbaint_t blkcnt, void * buffer);
-void msleep (int count);
+int sata_bus_softreset(int num);
+void sata_identify(int num, int dev);
+void sata_port(struct sata_ioports *ioport);
+void set_Feature_cmd(int num, int dev);
+int sata_devchk(struct sata_ioports *ioaddr, int dev);
+void dev_select(struct sata_ioports *ioaddr, int dev);
+u8 sata_busy_wait(struct sata_ioports *ioaddr, int bits, unsigned int max);
+u8 sata_chk_status(struct sata_ioports *ioaddr);
#endif
/************DRIVER SPECIFIC DEFINITIONS AND DECLARATIONS**************/
-#ifdef DRV_DECL /*Driver specific declaration */
-int init_sata (int dev);
+#ifdef DRV_DECL /* Driver specific declaration */
+int init_sata(int dev);
#endif
-#ifdef DRV_DECL /*Defines Driver Specific variables */
+#ifdef DRV_DECL /* Defines Driver Specific variables */
struct sata_port port[CONFIG_SYS_SATA_MAXBUS];
#endif
#include <libata.h>
#include <ahci.h>
#include <fis.h>
+#include <sata.h>
#include <common.h>
#include <malloc.h>
}
u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt,
- void *buffer, int is_write)
+ const void *buffer, int is_write)
{
u32 start, blks;
u8 *addr;
}
u32 ata_low_level_rw_lba28(int dev, u32 blknr, lbaint_t blkcnt,
- void *buffer, int is_write)
+ const void *buffer, int is_write)
{
u32 start, blks;
u8 *addr;
/*
* SATA interface between low level driver and command layer
*/
-ulong sata_read(int dev, unsigned long blknr, lbaint_t blkcnt, void *buffer)
+ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
{
u32 rc;
return rc;
}
-ulong sata_write(int dev, unsigned long blknr, lbaint_t blkcnt, void *buffer)
+ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
{
u32 rc;
struct ahci_probe_ent *probe_ent =
#define READ_CMD 0
#define WRITE_CMD 1
-extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
-
#endif /* __FSL_SATA_H__ */
#include <malloc.h>
#include <libata.h>
#include <fis.h>
+#include <sata.h>
#include "fsl_sata.h"
-extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
-
#ifndef CONFIG_SYS_SATA1_FLAGS
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
#endif
return sata->flush_ext;
}
-u32 ata_low_level_rw_lba48(int dev, u32 blknr, u32 blkcnt, void *buffer, int is_write)
+u32 ata_low_level_rw_lba48(int dev, u32 blknr, lbaint_t blkcnt,
+ const void *buffer, int is_write)
{
u32 start, blks;
u8 *addr;
return blkcnt;
}
-u32 ata_low_level_rw_lba28(int dev, u32 blknr, u32 blkcnt, void *buffer, int is_write)
+u32 ata_low_level_rw_lba28(int dev, u32 blknr, u32 blkcnt, const void *buffer,
+ int is_write)
{
u32 start, blks;
u8 *addr;
/*
* SATA interface between low level driver and command layer
*/
-ulong sata_read(int dev, u32 blknr, u32 blkcnt, void *buffer)
+ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
{
u32 rc;
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
return rc;
}
-ulong sata_write(int dev, u32 blknr, u32 blkcnt, void *buffer)
+ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
{
u32 rc;
fsl_sata_t *sata = (fsl_sata_t *)sata_dev_desc[dev].priv;
#include <asm/portmux.h>
#include <asm/mach-common/bits/pata.h>
#include <ata.h>
+#include <sata.h>
#include <libata.h>
#include "pata_bfin.h"
return sr;
}
-ulong sata_read(int dev, ulong block, ulong blkcnt, void *buff)
+ulong sata_read(int dev, ulong block, lbaint_t blkcnt, void *buff)
{
struct ata_port *ap = &port[dev];
ulong n = 0, sread;
return n;
}
-ulong sata_write(int dev, ulong block, ulong blkcnt, const void *buff)
+ulong sata_write(int dev, ulong block, lbaint_t blkcnt, const void *buff)
{
struct ata_port *ap = &port[dev];
void __iomem *base = (void __iomem *)ap->ioaddr.ctl_addr;
unsigned char dev_mask;
};
-extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
-
#define DRV_NAME "pata-bfin"
#define DRV_VERSION "0.9"
#define __iomem
#include <asm/io.h>
#include <malloc.h>
#include <ata.h>
+#include <sata.h>
#include <linux/ctype.h>
#include "sata_dwc.h"
unsigned int flags, u16 *id);
static int check_sata_dev_state(void);
-extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
-
static const struct ata_port_info sata_dwc_port_info[] = {
{
.flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
#define SATA_MAX_WRITE_BLK 0xFFFF
#endif
-ulong sata_write(int device, ulong blknr, lbaint_t blkcnt, void *buffer)
+ulong sata_write(int device, ulong blknr, lbaint_t blkcnt, const void *buffer)
{
ulong start,blks, buf_addr;
unsigned short smallblks;
#include <malloc.h>
#include <asm/io.h>
#include <fis.h>
+#include <sata.h>
#include <libata.h>
#include "sata_sil.h"
}
ulong sil_sata_rw_lba28(int dev, ulong blknr, lbaint_t blkcnt,
- void *buffer, int is_write)
+ const void *buffer, int is_write)
{
ulong start, blks, max_blks;
u8 *addr;
}
ulong sil_sata_rw_lba48(int dev, ulong blknr, lbaint_t blkcnt,
- void *buffer, int is_write)
+ const void *buffer, int is_write)
{
ulong start, blks, max_blks;
u8 *addr;
/*
* SATA interface between low level driver and command layer
*/
-ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
+ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
{
struct sil_sata *sata = sata_dev_desc[dev].priv;
ulong rc;
#define READ_CMD 0
#define WRITE_CMD 1
-extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
-
/*
* SATA device driver struct for each dev
*/
#include <asm/byteorder.h>
#include <asm/io.h>
#include <ide.h>
+#include <sata.h>
#include <libata.h>
#include "sata_sil3114.h"
static void msleep (int count);
static u32 iobase[6] = { 0, 0, 0, 0, 0, 0}; /* PCI BAR registers for device */
-extern block_dev_desc_t sata_dev_desc[CONFIG_SYS_SATA_MAX_DEVICE];
static struct sata_port port[CONFIG_SYS_SATA_MAX_DEVICE];
#include <common.h>
#include <asm/io.h>
#include <asm/bitops.h>
-#include <asm/arch/tegra20.h>
+#include <asm/arch/tegra.h>
#include <asm/gpio.h>
enum {
#endif
/* Divider value calculation */
- i2c_clk_rate = mxc_get_clock(MXC_IPG_PERCLK);
+ i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK);
div = (i2c_clk_rate + rate - 1) / rate;
if (div < i2c_clk_div[0][0])
clk_div = 0;
for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++)
;
- return mxc_get_clock(MXC_IPG_PERCLK) / i2c_clk_div[clk_div][0];
+ return mxc_get_clock(MXC_I2C_CLK) / i2c_clk_div[clk_div][0];
}
#define ST_BUS_IDLE (0 | (I2SR_IBB << 8))
#define SH_I2C_ICCR_SCP (1 << 0)
/* ICSR / ICIC */
-#define SH_IC_BUSY (1 << 3)
+#define SH_IC_BUSY (1 << 4)
#define SH_IC_TACK (1 << 2)
#define SH_IC_WAIT (1 << 1)
#define SH_IC_DTE (1 << 0)
-static u8 iccl, icch;
+#ifdef CONFIG_SH_I2C_8BIT
+/* store 8th bit of iccl and icch in ICIC register */
+#define SH_I2C_ICIC_ICCLB8 (1 << 7)
+#define SH_I2C_ICIC_ICCHB8 (1 << 6)
+#endif
+
+static u16 iccl, icch;
#define IRQ_WAIT 1000
}
}
+static int irq_dte_with_tack(struct sh_i2c *base)
+{
+ int i;
+
+ for (i = 0 ; i < IRQ_WAIT ; i++) {
+ if (SH_IC_DTE & readb(&base->icsr))
+ break;
+ if (SH_IC_TACK & readb(&base->icsr))
+ return -1;
+ udelay(10);
+ }
+ return 0;
+}
+
static void irq_busy(struct sh_i2c *base)
{
int i;
}
}
-static void i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop)
+static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop)
{
- writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr);
- writeb(readb(&base->iccr) | SH_I2C_ICCR_ICE, &base->iccr);
-
- writeb(iccl, &base->iccl);
- writeb(icch, &base->icch);
- writeb(0, &base->icic);
+ u8 icic = SH_IC_TACK;
+
+ clrbits_8(&base->iccr, SH_I2C_ICCR_ICE);
+ setbits_8(&base->iccr, SH_I2C_ICCR_ICE);
+
+ writeb(iccl & 0xff, &base->iccl);
+ writeb(icch & 0xff, &base->icch);
+#ifdef CONFIG_SH_I2C_8BIT
+ if (iccl > 0xff)
+ icic |= SH_I2C_ICIC_ICCLB8;
+ if (icch > 0xff)
+ icic |= SH_I2C_ICIC_ICCHB8;
+#endif
+ writeb(icic, &base->icic);
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr);
irq_dte(base);
+ clrbits_8(&base->icsr, SH_IC_TACK);
writeb(id << 1, &base->icdr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ return -1;
writeb(reg, &base->icdr);
if (stop)
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &base->iccr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ return -1;
+ return 0;
}
static void i2c_finish(struct sh_i2c *base)
{
writeb(0, &base->icsr);
- writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr);
+ clrbits_8(&base->iccr, SH_I2C_ICCR_ICE);
}
-static void i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val)
+static int i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val)
{
- i2c_set_addr(base, id, reg, 0);
+ int ret = -1;
+ if (i2c_set_addr(base, id, reg, 0) != 0)
+ goto exit0;
udelay(10);
writeb(val, &base->icdr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ goto exit0;
writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &base->iccr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ goto exit0;
irq_busy(base);
-
+ ret = 0;
+exit0:
i2c_finish(base);
+ return ret;
}
-static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
+static int i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg)
{
- u8 ret;
-
- i2c_set_addr(base, id, reg, 1);
+ int ret = -1;
+
+#if defined(CONFIG_SH73A0)
+ if (i2c_set_addr(base, id, reg, 0) != 0)
+ goto exit0;
+#else
+ if (i2c_set_addr(base, id, reg, 1) != 0)
+ goto exit0;
udelay(100);
+#endif
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr);
irq_dte(base);
writeb(id << 1 | 0x01, &base->icdr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ goto exit0;
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &base->iccr);
- irq_dte(base);
+ if (irq_dte_with_tack(base) != 0)
+ goto exit0;
- ret = readb(&base->icdr);
+ ret = readb(&base->icdr) & 0xff;
writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &base->iccr);
readb(&base->icdr); /* Dummy read */
irq_busy(base);
-
+exit0:
i2c_finish(base);
return ret;
case 1:
base = (void *)CONFIG_SH_I2C_BASE1;
break;
+#ifdef CONFIG_SH_I2C_BASE2
+ case 2:
+ base = (void *)CONFIG_SH_I2C_BASE2;
+ break;
+#endif
+#ifdef CONFIG_SH_I2C_BASE3
+ case 3:
+ base = (void *)CONFIG_SH_I2C_BASE3;
+ break;
+#endif
+#ifdef CONFIG_SH_I2C_BASE4
+ case 4:
+ base = (void *)CONFIG_SH_I2C_BASE4;
+ break;
+#endif
default:
return -1;
}
denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW);
tmp = num * 10 / denom;
if (tmp % 10 >= 5)
- iccl = (u8)((num/denom) + 1);
+ iccl = (u16)((num/denom) + 1);
else
- iccl = (u8)(num/denom);
+ iccl = (u16)(num/denom);
/* Calculate the value for icch. From the data sheet:
icch = (p clock / transfer rate) * (H / (L + H)) */
num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH;
tmp = num * 10 / denom;
if (tmp % 10 >= 5)
- icch = (u8)((num/denom) + 1);
+ icch = (u16)((num/denom) + 1);
else
- icch = (u8)(num/denom);
+ icch = (u16)(num/denom);
}
/*
*/
int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len)
{
+ int ret;
int i = 0;
- for (i = 0 ; i < len ; i++)
- buffer[i] = i2c_raw_read(base, chip, addr + i);
-
+ for (i = 0 ; i < len ; i++) {
+ ret = i2c_raw_read(base, chip, addr + i);
+ if (ret < 0)
+ return -1;
+ buffer[i] = ret & 0xff;
+ }
return 0;
}
{
int i = 0;
for (i = 0; i < len ; i++)
- i2c_raw_write(base, chip, addr + i, buffer[i]);
-
+ if (i2c_raw_write(base, chip, addr + i, buffer[i]) != 0)
+ return -1;
return 0;
}
*/
int i2c_probe(u8 chip)
{
- return 0;
+ int ret;
+
+ ret = i2c_set_addr(base, chip, 0, 1);
+ i2c_finish(base);
+ return ret;
}
#include <fdtdec.h>
#include <i2c.h>
#include <asm/io.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
#include <asm/arch/gpio.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/tegra_i2c.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/tegra_i2c.h>
DECLARE_GLOBAL_DATA_PTR;
/* includes */
#include <common.h>
+#include <linux/compiler.h>
#ifdef CONFIG_USE_CPCIDVI
extern u8 gt_cpcidvi_in8(u32 offset);
return in8(I8042_STATUS_REG) != 0xff;
}
+/*
+ * Implement a weak default function for boards that optionally
+ * need to skip the i8042 initialization.
+ */
+int __weak board_i8042_skip(void)
+{
+ /* As default, don't skip */
+ return 0;
+}
+
+void i8042_flush(void)
+{
+ int timeout;
+
+ /*
+ * The delay is to give the keyboard controller some time to fill the
+ * next byte.
+ */
+ while (1) {
+ timeout = 100; /* wait for no longer than 100us */
+ while (timeout > 0 && !(in8(I8042_STATUS_REG) & 0x01)) {
+ udelay(1);
+ timeout--;
+ }
+
+ /* Try to pull next byte if not timeout. */
+ if (in8(I8042_STATUS_REG) & 0x01)
+ in8(I8042_DATA_REG);
+ else
+ break;
+ }
+}
+
+int i8042_disable(void)
+{
+ if (kbd_input_empty() == 0)
+ return -1;
+
+ /* Disable keyboard */
+ out8(I8042_COMMAND_REG, 0xad);
+
+ if (kbd_input_empty() == 0)
+ return -1;
+
+ return 0;
+}
+
+
/*******************************************************************************
*
* i8042_kbd_init - reset keyboard and init state flags
int keymap, try;
char *penv;
- if (!kbd_controller_present())
+ if (!kbd_controller_present() || board_i8042_skip())
return -1;
#ifdef CONFIG_USE_CPCIDVI
static int kbd_input_empty(void)
{
- int kbdTimeout = KBD_TIMEOUT;
+ int kbdTimeout = KBD_TIMEOUT * 1000;
+
+ while ((in8(I8042_STATUS_REG) & I8042_STATUS_IN_DATA) && kbdTimeout--)
+ udelay(1);
+
+ return kbdTimeout != -1;
+}
+
+/******************************************************************************/
+
+static int wait_until_kbd_output_full(void)
+{
+ int kbdTimeout = KBD_TIMEOUT * 1000;
- /* wait for input buf empty */
- while ((in8(I8042_STATUS_REG) & 0x02) && kbdTimeout--)
- udelay(1000);
+ while (((in8(I8042_STATUS_REG) & 0x01) == 0) && kbdTimeout--)
+ udelay(1);
return kbdTimeout != -1;
}
static int kbd_reset(void)
{
+ /* KB Reset */
if (kbd_input_empty() == 0)
return -1;
out8(I8042_DATA_REG, 0xff);
- udelay(250000);
+ if (wait_until_kbd_output_full() == 0)
+ return -1;
+
+ if (in8(I8042_DATA_REG) != 0xfa) /* ACK */
+ return -1;
+
+ if (wait_until_kbd_output_full() == 0)
+ return -1;
+
+ if (in8(I8042_DATA_REG) != 0xaa) /* Test Pass*/
+ return -1;
if (kbd_input_empty() == 0)
return -1;
-#ifdef CONFIG_USE_CPCIDVI
+ /* Set KBC mode */
out8(I8042_COMMAND_REG, 0x60);
-#else
- out8(I8042_DATA_REG, 0x60);
-#endif
if (kbd_input_empty() == 0)
return -1;
out8(I8042_DATA_REG, 0x45);
-
if (kbd_input_empty() == 0)
return -1;
+ /* Enable Keyboard */
out8(I8042_COMMAND_REG, 0xae);
if (kbd_input_empty() == 0)
'\r', 0xff, 0xff
};
+/*
+ * Scan key code to ANSI 3.64 escape sequence table. This table is
+ * incomplete in that it does not include all possible extra keys.
+ */
+static struct {
+ int kbd_scan_code;
+ char *escape;
+} kbd_to_ansi364[] = {
+ { KEY_UP, "\033[A"},
+ { KEY_DOWN, "\033[B"},
+ { KEY_RIGHT, "\033[C"},
+ { KEY_LEFT, "\033[D"},
+};
+
+/* Maximum number of output characters that an ANSI sequence expands to */
+#define ANSI_CHAR_MAX 3
int input_queue_ascii(struct input_config *config, int ch)
{
}
/**
+ * Checks and converts a special key code into ANSI 3.64 escape sequence.
+ *
+ * @param config Input state
+ * @param keycode Key code to examine
+ * @param output_ch Buffer to place output characters into. It should
+ * be at least ANSI_CHAR_MAX bytes long, to allow for
+ * an ANSI sequence.
+ * @param max_chars Maximum number of characters to add to output_ch
+ * @return number of characters output, if the key was converted, otherwise 0.
+ * This may be larger than max_chars, in which case the overflow
+ * characters are not output.
+ */
+static int input_keycode_to_ansi364(struct input_config *config,
+ int keycode, char output_ch[], int max_chars)
+{
+ const char *escape;
+ int ch_count;
+ int i;
+
+ for (i = ch_count = 0; i < ARRAY_SIZE(kbd_to_ansi364); i++) {
+ if (keycode != kbd_to_ansi364[i].kbd_scan_code)
+ continue;
+ for (escape = kbd_to_ansi364[i].escape; *escape; escape++) {
+ if (ch_count < max_chars)
+ output_ch[ch_count] = *escape;
+ ch_count++;
+ }
+ return ch_count;
+ }
+
+ return 0;
+}
+
+/**
+ * Converts and queues a list of key codes in escaped ASCII string form
* Convert a list of key codes into ASCII
*
* You must call input_check_keycodes() before this. It turns the keycode
- * list into a list of ASCII characters which are ready to send to the
- * input layer.
+ * list into a list of ASCII characters and sends them to the input layer.
*
* Characters which were seen last time do not generate fresh ASCII output.
+ * The output (calls to queue_ascii) may be longer than num_keycodes, if the
+ * keycode contains special keys that was encoded to longer escaped sequence.
*
* @param config Input state
* @param keycode List of key codes to examine
* @param num_keycodes Number of key codes
+ * @param output_ch Buffer to place output characters into. It should
+ * be at last ANSI_CHAR_MAX * num_keycodes, to allow for
+ * ANSI sequences.
+ * @param max_chars Maximum number of characters to add to output_ch
* @param same Number of key codes which are the same
+ * @return number of characters written into output_ch, or -1 if we would
+ * exceed max_chars chars.
*/
static int input_keycodes_to_ascii(struct input_config *config,
- int keycode[], int num_keycodes, char output_ch[], int same)
+ int keycode[], int num_keycodes, char output_ch[],
+ int max_chars, int same)
{
struct input_key_xlate *table;
- int ch_count;
+ int ch_count = 0;
int i;
table = &config->table[0];
}
}
- /* now find normal keys */
- for (i = ch_count = 0; i < num_keycodes; i++) {
+ /* Start conversion by looking for the first new keycode (by same). */
+ for (i = same; i < num_keycodes; i++) {
int key = keycode[i];
+ int ch = (key < table->num_entries) ? table->xlate[key] : 0xff;
- if (key < table->num_entries && i >= same) {
- int ch = table->xlate[key];
-
- /* If a normal key with an ASCII value, add it! */
- if (ch != 0xff)
- output_ch[ch_count++] = (uchar)ch;
+ /*
+ * For a normal key (with an ASCII value), add it; otherwise
+ * translate special key to escape sequence if possible.
+ */
+ if (ch != 0xff) {
+ if (ch_count < max_chars)
+ output_ch[ch_count] = (uchar)ch;
+ ch_count++;
+ } else {
+ ch_count += input_keycode_to_ansi364(config, key,
+ output_ch, max_chars);
}
}
+ if (ch_count > max_chars) {
+ debug("%s: Output char buffer overflow size=%d, need=%d\n",
+ __func__, max_chars, ch_count);
+ return -1;
+ }
+
/* ok, so return keys */
return ch_count;
}
int input_send_keycodes(struct input_config *config,
int keycode[], int num_keycodes)
{
- char ch[num_keycodes];
+ char ch[num_keycodes * ANSI_CHAR_MAX];
int count, i, same = 0;
int is_repeat = 0;
unsigned delay_ms;
* insert another character if we later realise that we
* have missed a repeat slot.
*/
- is_repeat = (int)get_timer(config->next_repeat_ms) >= 0;
+ is_repeat = config->repeat_rate_ms &&
+ (int)get_timer(config->next_repeat_ms) >= 0;
if (!is_repeat)
return 0;
}
count = input_keycodes_to_ascii(config, keycode, num_keycodes,
- ch, is_repeat ? 0 : same);
+ ch, sizeof(ch), is_repeat ? 0 : same);
for (i = 0; i < count; i++)
input_queue_ascii(config, ch[i]);
delay_ms = is_repeat ?
config->repeat_delay_ms;
config->next_repeat_ms = get_timer(0) + delay_ms;
- return 0;
+
+ return count;
}
int input_add_table(struct input_config *config, int left_keycode,
return 0;
}
-int input_init(struct input_config *config, int leds, int repeat_delay_ms,
+void input_set_delays(struct input_config *config, int repeat_delay_ms,
int repeat_rate_ms)
{
- memset(config, '\0', sizeof(*config));
- config->leds = leds;
config->repeat_delay_ms = repeat_delay_ms;
config->repeat_rate_ms = repeat_rate_ms;
+}
+
+int input_init(struct input_config *config, int leds)
+{
+ memset(config, '\0', sizeof(*config));
+ config->leds = leds;
if (input_add_table(config, -1, -1,
kbd_plain_xlate, ARRAY_SIZE(kbd_plain_xlate)) ||
input_add_table(config, KEY_LEFTSHIFT, KEY_RIGHTSHIFT,
int key_in_same_col = 0, key_in_same_row = 0;
int i, j;
+ if (!config->ghost_filter || valid < 3)
+ return 0;
+
for (i = 0; i < valid; i++) {
/*
* Find 2 keys such that one key is in the same row
}
/* For a ghost key config, ignore the keypresses for this iteration. */
- if (valid >= 3 && has_ghosting(config, keys, valid)) {
+ if (has_ghosting(config, keys, valid)) {
valid = 0;
debug(" ghosting detected!\n");
}
key_code = tmp & 0xffff;
entry = row * config->num_cols + col;
map[entry] = key_code;
+ debug(" map %d, %d: pos=%d, keycode=%d\n", row, col,
+ entry, key_code);
if (pos && map_keycode == key_code)
*pos = entry;
}
int node)
{
const struct fdt_property *prop;
+ const char prefix[] = "linux,";
+ int plen = sizeof(prefix) - 1;
int offset;
/* Check each property name for ones that we understand */
/* Name needs to match "1,<type>keymap" */
debug("%s: property '%s'\n", __func__, name);
- if (strncmp(name, "1,", 2) || len < 8 ||
- strcmp(name + len - 6, "keymap"))
+ if (strncmp(name, prefix, plen) ||
+ len < plen + 6 ||
+ strcmp(name + len - 6, "keymap"))
continue;
- len -= 8;
+ len -= plen + 6;
if (len == 0) {
config->plain_keycode = create_keymap(config,
(u32 *)prop->data, fdt32_to_cpu(prop->len),
KEY_FN, &config->fn_pos);
- } else if (0 == strncmp(name + 2, "fn-", len)) {
+ } else if (0 == strncmp(name + plen, "fn-", len)) {
config->fn_keycode = create_keymap(config,
(u32 *)prop->data, fdt32_to_cpu(prop->len),
-1, NULL);
return 0;
}
-int key_matrix_init(struct key_matrix *config, int rows, int cols)
+int key_matrix_init(struct key_matrix *config, int rows, int cols,
+ int ghost_filter)
{
memset(config, '\0', sizeof(*config));
config->num_rows = rows;
config->num_cols = cols;
config->key_count = rows * cols;
+ config->ghost_filter = ghost_filter;
assert(config->key_count > 0);
return 0;
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
-#include <asm/arch/timer.h>
+#include <asm/arch-tegra/timer.h>
#include <linux/input.h>
DECLARE_GLOBAL_DATA_PTR;
debug("%s: No keyboard register found\n", __func__);
return -1;
}
+ input_set_delays(&config.input, KBC_REPEAT_DELAY_MS,
+ KBC_REPEAT_RATE_MS);
/* Decode the keyboard matrix information (16 rows, 8 columns) */
- if (key_matrix_init(&config.matrix, 16, 8)) {
+ if (key_matrix_init(&config.matrix, 16, 8, 1)) {
debug("%s: Could not init key matrix\n", __func__);
return -1;
}
{
struct stdio_dev dev;
- if (input_init(&config.input, 0, KBC_REPEAT_DELAY_MS,
- KBC_REPEAT_RATE_MS)) {
+ if (input_init(&config.input, 0)) {
debug("%s: Cannot set up input\n", __func__);
return -1;
}
*/
#include <common.h>
-#include <mmc.h>
#include <asm/gpio.h>
#include <asm/io.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
-#include <asm/arch/tegra_mmc.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/tegra_mmc.h>
+#include <mmc.h>
/* support 4 mmc hosts */
struct mmc mmc_dev[4];
#include <common.h>
#include <asm/io.h>
#include <nand.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/funcmux.h>
-#include <asm/arch/gpio.h>
+#include <asm/arch-tegra/clk_rst.h>
#include <asm/errno.h>
-#include <asm-generic/gpio.h>
+#include <asm/gpio.h>
#include <fdtdec.h>
#include "tegra_nand.h"
/* Adjust timing for NAND device */
setup_timing(config->timing, info->reg);
- funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
fdtdec_setup_gpio(&config->wp_gpio);
gpio_direction_output(config->wp_gpio.gpio, 1);
static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);
-#ifndef CONFIG_AP1000 /* remove for warnings */
static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
uint16_t words,
uint16_t *data);
return E1000_SUCCESS;
}
-#endif /* #ifndef CONFIG_AP1000 */
/***************************************************************************
*
static int
e1000_read_mac_addr(struct eth_device *nic)
{
-#ifndef CONFIG_AP1000
struct e1000_hw *hw = nic->priv;
uint16_t offset;
uint16_t eeprom_data;
memcpy (nic->enetaddr, fb_mac, NODE_ADDRESS_SIZE);
}
-#endif
-#else
- /*
- * The AP1000's e1000 has no eeprom; the MAC address is stored in the
- * environment variables. Currently this does not support the addition
- * of a PMC e1000 card, which is certainly a possibility, so this should
- * be updated to properly use the env variable only for the onboard e1000
- */
-
- int ii;
- char *s, *e;
-
- DEBUGFUNC();
-
- s = getenv ("ethaddr");
- if (s == NULL) {
- return -E1000_ERR_EEPROM;
- } else {
- for(ii = 0; ii < 6; ii++) {
- nic->enetaddr[ii] = s ? simple_strtoul (s, &e, 16) : 0;
- if (s){
- s = (*e) ? e + 1 : e;
- }
- }
- }
#endif
return 0;
}
if (e1000_check_phy_reset_block(hw))
return E1000_SUCCESS;
-#ifndef CONFIG_AP1000
/* Read and store word 0x0F of the EEPROM. This word contains bits
* that determine the hardware's default PAUSE (flow control) mode,
* a bit that determines whether the HW defaults to enabling or
DEBUGOUT("EEPROM Read Error\n");
return -E1000_ERR_EEPROM;
}
-#else
- /* we have to hardcode the proper value for our hardware. */
- /* this value is for the 82540EM pci card used for prototyping, and it works. */
- eeprom_data = 0xb220;
-#endif
if (hw->fc == e1000_fc_default) {
switch (hw->mac_type) {
hw->fc = e1000_fc_full;
break;
default:
-#ifndef CONFIG_AP1000
ret_val = e1000_read_eeprom(hw,
EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data);
if (ret_val) {
DEBUGOUT("EEPROM Read Error\n");
return -E1000_ERR_EEPROM;
}
-#else
- eeprom_data = 0xb220;
-#endif
if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
hw->fc = e1000_fc_none;
else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
}
DEBUGOUT("Phy ID = %x \n", hw->phy_id);
-#ifndef CONFIG_AP1000
/* Set PHY to class A mode (if necessary) */
ret_val = e1000_set_phy_mode(hw);
if (ret_val)
return ret_val;
-#endif
if ((hw->mac_type == e1000_82545_rev_3) ||
(hw->mac_type == e1000_82546_rev_3)) {
ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
list_add_tail(&hw->list_node, &e1000_hw_list);
/* Validate the EEPROM and get chipset information */
-#if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G))
+#if !defined(CONFIG_MVBC_1G)
if (e1000_init_eeprom_params(hw)) {
E1000_ERR(nic, "EEPROM is invalid!\n");
continue;
int mcffec_miiphy_write(const char *devname, unsigned char addr, unsigned char reg,
unsigned short value)
{
- short rdreg; /* register working value */
-
#ifdef MII_DEBUG
printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr);
#endif
- rdreg = mii_send(mk_mii_write(addr, reg, value));
+ mii_send(mk_mii_write(addr, reg, value));
#ifdef MII_DEBUG
printf("0x%04x\n", value);
LIB := $(obj)libserial.o
+COBJS-y += serial.o
+
COBJS-$(CONFIG_ALTERA_UART) += altera_uart.o
COBJS-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
COBJS-$(CONFIG_ARM_DCC) += arm_dcc.o
COBJS-$(CONFIG_DRIVER_S3C4510_UART) += s3c4510b_uart.o
COBJS-$(CONFIG_S3C64XX) += s3c64xx.o
COBJS-$(CONFIG_S5P) += serial_s5p.o
-COBJS-$(CONFIG_SYS_NS16550_SERIAL) += serial.o
+COBJS-$(CONFIG_SYS_NS16550_SERIAL) += serial_ns16550.o
COBJS-$(CONFIG_CLPS7111_SERIAL) += serial_clps7111.o
COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o
COBJS-$(CONFIG_IXP_SERIAL) += serial_ixp.o
COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o
COBJS-$(CONFIG_LPC2292_SERIAL) += serial_lpc2292.o
-COBJS-$(CONFIG_LH7A40X_SERIAL) += serial_lh7a40x.o
COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
COBJS-$(CONFIG_MXC_UART) += serial_mxc.o
COBJS-$(CONFIG_NETARM_SERIAL) += serial_netarm.o
#include <watchdog.h>
#include <asm/io.h>
#include <nios2-io.h>
+#include <linux/compiler.h>
+#include <serial.h>
DECLARE_GLOBAL_DATA_PTR;
*-----------------------------------------------------------------*/
static nios_jtag_t *jtag = (nios_jtag_t *)CONFIG_SYS_NIOS_CONSOLE;
-void serial_setbrg( void ){ return; }
-int serial_init( void ) { return(0);}
+static void altera_jtag_serial_setbrg(void)
+{
+}
+
+static int altera_jtag_serial_init(void)
+{
+ return 0;
+}
-void serial_putc (char c)
+static void altera_jtag_serial_putc(char c)
{
while (1) {
unsigned st = readl(&jtag->control);
writel ((unsigned char)c, &jtag->data);
}
-void serial_puts (const char *s)
-{
- while (*s != 0)
- serial_putc (*s++);
-}
-
-int serial_tstc (void)
+static int altera_jtag_serial_tstc(void)
{
return ( readl (&jtag->control) & NIOS_JTAG_RRDY);
}
-int serial_getc (void)
+static int altera_jtag_serial_getc(void)
{
int c;
unsigned val;
c = val & 0x0ff;
return (c);
}
+
+static struct serial_device altera_jtag_serial_drv = {
+ .name = "altera_jtag_uart",
+ .start = altera_jtag_serial_init,
+ .stop = NULL,
+ .setbrg = altera_jtag_serial_setbrg,
+ .putc = altera_jtag_serial_putc,
+ .puts = default_serial_puts,
+ .getc = altera_jtag_serial_getc,
+ .tstc = altera_jtag_serial_tstc,
+};
+
+void altera_jtag_serial_initialize(void)
+{
+ serial_register(&altera_jtag_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &altera_jtag_serial_drv;
+}
#include <watchdog.h>
#include <asm/io.h>
#include <nios2-io.h>
+#include <linux/compiler.h>
+#include <serial.h>
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_SYS_NIOS_FIXEDBAUD)
-/* Everything's already setup for fixed-baud PTF
+/*
+ * Everything's already setup for fixed-baud PTF
* assignment
*/
-void serial_setbrg (void){ return; }
-int serial_init (void) { return (0);}
+static void altera_serial_setbrg(void)
+{
+}
+
+static int altera_serial_init(void)
+{
+ return 0;
+}
#else
-void serial_setbrg (void)
+static void altera_serial_setbrg(void)
{
unsigned div;
div = (CONFIG_SYS_CLK_FREQ/gd->baudrate)-1;
writel (div, &uart->divisor);
- return;
}
-int serial_init (void)
+static int altera_serial_init(void)
{
- serial_setbrg ();
- return (0);
+ serial_setbrg();
+ return 0;
}
#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */
/*-----------------------------------------------------------------------
* UART CONSOLE
*---------------------------------------------------------------------*/
-void serial_putc (char c)
+static void altera_serial_putc(char c)
{
if (c == '\n')
serial_putc ('\r');
writel ((unsigned char)c, &uart->txdata);
}
-void serial_puts (const char *s)
-{
- while (*s != 0) {
- serial_putc (*s++);
- }
-}
-
-int serial_tstc (void)
+static int altera_serial_tstc(void)
{
return (readl (&uart->status) & NIOS_UART_RRDY);
}
-int serial_getc (void)
+static int altera_serial_getc(void)
{
while (serial_tstc () == 0)
WATCHDOG_RESET ();
return (readl (&uart->rxdata) & 0x00ff );
}
+
+static struct serial_device altera_serial_drv = {
+ .name = "altera_serial",
+ .start = altera_serial_init,
+ .stop = NULL,
+ .setbrg = altera_serial_setbrg,
+ .putc = altera_serial_putc,
+ .puts = default_serial_puts,
+ .getc = altera_serial_getc,
+ .tstc = altera_serial_tstc,
+};
+
+void altera_serial_initialize(void)
+{
+ serial_register(&altera_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &altera_serial_drv;
+}
*/
#include <common.h>
#include <watchdog.h>
+#include <serial.h>
+#include <linux/compiler.h>
#include <asm/io.h>
#include <asm/arch/clk.h>
DECLARE_GLOBAL_DATA_PTR;
-void serial_setbrg(void)
+static void atmel_serial_setbrg(void)
{
atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
unsigned long divisor;
writel(USART3_BF(CD, divisor), &usart->brgr);
}
-int serial_init(void)
+static int atmel_serial_init(void)
{
atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
return 0;
}
-void serial_putc(char c)
+static void atmel_serial_putc(char c)
{
atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
writel(c, &usart->thr);
}
-void serial_puts(const char *s)
-{
- while (*s)
- serial_putc(*s++);
-}
-
-int serial_getc(void)
+static int atmel_serial_getc(void)
{
atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
return readl(&usart->rhr);
}
-int serial_tstc(void)
+static int atmel_serial_tstc(void)
{
atmel_usart3_t *usart = (atmel_usart3_t *)CONFIG_USART_BASE;
return (readl(&usart->csr) & USART3_BIT(RXRDY)) != 0;
}
+
+static struct serial_device atmel_serial_drv = {
+ .name = "atmel_serial",
+ .start = atmel_serial_init,
+ .stop = NULL,
+ .setbrg = atmel_serial_setbrg,
+ .putc = atmel_serial_putc,
+ .puts = default_serial_puts,
+ .getc = atmel_serial_getc,
+ .tstc = atmel_serial_tstc,
+};
+
+void atmel_serial_initialize(void)
+{
+ serial_register(&atmel_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &atmel_serial_drv;
+}
#include <asm/arch/clk.h>
#include <asm/arch/uart.h>
#include <asm/io.h>
+#include <serial.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
static struct hsuart_regs *hsuart = (struct hsuart_regs *)HS_UART_BASE;
-static void lpc32xx_hsuart_set_baudrate(void)
+static void lpc32xx_serial_setbrg(void)
{
u32 div;
writel(div, &hsuart->rate);
}
-static int lpc32xx_hsuart_getc(void)
+static int lpc32xx_serial_getc(void)
{
while (!(readl(&hsuart->level) & HSUART_LEVEL_RX))
/* NOP */;
return readl(&hsuart->rx) & HSUART_RX_DATA;
}
-static void lpc32xx_hsuart_putc(const char c)
+static void lpc32xx_serial_putc(const char c)
{
writel(c, &hsuart->tx);
/* NOP */;
}
-static int lpc32xx_hsuart_tstc(void)
+static int lpc32xx_serial_tstc(void)
{
if (readl(&hsuart->level) & HSUART_LEVEL_RX)
return 1;
return 0;
}
-static void lpc32xx_hsuart_init(void)
+static int lpc32xx_serial_init(void)
{
- lpc32xx_hsuart_set_baudrate();
+ lpc32xx_serial_setbrg();
/* Disable hardware RTS and CTS flow control, set up RX and TX FIFO */
writel(HSUART_CTRL_TMO_16 | HSUART_CTRL_HSU_OFFSET(20) |
HSUART_CTRL_HSU_RX_TRIG_32 | HSUART_CTRL_HSU_TX_TRIG_0,
&hsuart->ctrl);
+ return 0;
}
-void serial_setbrg(void)
-{
- return lpc32xx_hsuart_set_baudrate();
-}
-
-void serial_putc(const char c)
-{
- lpc32xx_hsuart_putc(c);
-
- /* If \n, also do \r */
- if (c == '\n')
- lpc32xx_hsuart_putc('\r');
-}
-
-int serial_getc(void)
-{
- return lpc32xx_hsuart_getc();
-}
-
-void serial_puts(const char *s)
-{
- while (*s)
- serial_putc(*s++);
-}
-
-int serial_tstc(void)
+static struct serial_device lpc32xx_serial_drv = {
+ .name = "lpc32xx_serial",
+ .start = lpc32xx_serial_init,
+ .stop = NULL,
+ .setbrg = lpc32xx_serial_setbrg,
+ .putc = lpc32xx_serial_putc,
+ .puts = default_serial_puts,
+ .getc = lpc32xx_serial_getc,
+ .tstc = lpc32xx_serial_tstc,
+};
+
+void lpc32xx_serial_initialize(void)
{
- return lpc32xx_hsuart_tstc();
+ serial_register(&lpc32xx_serial_drv);
}
-int serial_init(void)
+__weak struct serial_device *default_serial_console(void)
{
- lpc32xx_hsuart_init();
-
- return 0;
+ return &lpc32xx_serial_drv;
}
*/
#include <common.h>
+#include <serial.h>
+#include <linux/compiler.h>
#include <asm/immap.h>
#include <asm/uart.h>
extern void uart_port_conf(int port);
-int serial_init(void)
+static int mcf_serial_init(void)
{
volatile uart_t *uart;
u32 counter;
return (0);
}
-void serial_putc(const char c)
+static void mcf_serial_putc(const char c)
{
volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
uart->utb = c;
}
-void serial_puts(const char *s)
-{
- while (*s) {
- serial_putc(*s++);
- }
-}
-
-int serial_getc(void)
+static int mcf_serial_getc(void)
{
volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
return uart->urb;
}
-int serial_tstc(void)
+static int mcf_serial_tstc(void)
{
volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
return (uart->usr & UART_USR_RXRDY);
}
-void serial_setbrg(void)
+static void mcf_serial_setbrg(void)
{
volatile uart_t *uart = (volatile uart_t *)(CONFIG_SYS_UART_BASE);
u32 counter;
uart->ucr = UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED;
}
+
+static struct serial_device mcf_serial_drv = {
+ .name = "mcf_serial",
+ .start = mcf_serial_init,
+ .stop = NULL,
+ .setbrg = mcf_serial_setbrg,
+ .putc = mcf_serial_putc,
+ .puts = default_serial_puts,
+ .getc = mcf_serial_getc,
+ .tstc = mcf_serial_tstc,
+};
+
+void mcf_serial_initialize(void)
+{
+ serial_register(&mcf_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &mcf_serial_drv;
+}
char NS16550_getc(NS16550_t com_port)
{
while ((serial_in(&com_port->lsr) & UART_LSR_DR) == 0) {
-#ifdef CONFIG_USB_TTY
+#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_USB_TTY)
extern void usbtty_poll(void);
usbtty_poll();
#endif
* @Descr: configures GPIOs and UART. Requires BBUS Master Reset turned off
***********************************************************************/
-int serial_init( void )
+static int ns9750_serial_init(void)
{
unsigned int aunGPIOTxD[] = { 0, 8, 40, 44 };
unsigned int aunGPIORxD[] = { 1, 9, 41, 45 };
* @Descr: writes one character to the FIFO. Blocks until FIFO is not full
***********************************************************************/
-void serial_putc( const char c )
+static void ns9750_serial_putc(const char c)
{
if (c == '\n')
serial_putc( '\r' );
CONSOLE) = c;
}
-/***********************************************************************
- * @Function: serial_puts
- * @Return: n/a
- * @Descr: writes non-zero string to the FIFO.
- ***********************************************************************/
-
-void serial_puts( const char *s )
-{
- while (*s) {
- serial_putc( *s++ );
- }
-}
-
/***********************************************************************
* @Function: serial_getc
* @Return: the character read
* @Descr: performs only 8bit accesses to the FIFO. No error handling
***********************************************************************/
-int serial_getc( void )
+static int ns9750_serial_getc(void)
{
int i;
* unCharCache and the numbers of characters in cCharsAvailable
***********************************************************************/
-int serial_tstc( void )
+static int ns9750_serial_tstc(void)
{
unsigned int unRegCache;
return 0;
}
-void serial_setbrg( void )
+static void ns9750_serial_setbrg(void)
{
*get_ser_reg_addr_channel( NS9750_SER_BITRATE, CONSOLE ) =
calcBitrateRegister();
{
return NS9750_SER_RX_CHAR_TIMER_TRUN;
}
+
+static struct serial_device ns9750_serial_drv = {
+ .name = "ns9750_serial",
+ .start = ns9750_serial_init,
+ .stop = NULL,
+ .setbrg = ns9750_serial_setbrg,
+ .putc = ns9750_serial_putc,
+ .puts = default_serial_puts,
+ .getc = ns9750_serial_getc,
+ .tstc = ns9750_serial_tstc,
+};
+
+void ns9750_serial_initialize(void)
+{
+ serial_register(&ns9750_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &ns9750_serial_drv;
+}
/* Everything's already setup for fixed-baud PTF assignment*/
-void serial_setbrg (void)
+static void oc_serial_setbrg(void)
{
int n, k;
const unsigned max_uns = 0xFFFFFFFF;
#else
-void serial_setbrg (void)
+static void oc_serial_setbrg(void)
{
int n, k;
const unsigned max_uns = 0xFFFFFFFF;
#endif /* CONFIG_SYS_NIOS_FIXEDBAUD */
-int serial_init (void)
+static int oc_serial_init(void)
{
unsigned action,control;
/*-----------------------------------------------------------------------
* YANU CONSOLE
*---------------------------------------------------------------------*/
-void serial_putc (char c)
+static void oc_serial_putc(char c)
{
int tx_chars;
unsigned status;
writel((unsigned char)c, &uart->data);
}
-void serial_puts (const char *s)
-{
- while (*s != 0) {
- serial_putc (*s++);
- }
-}
-
-
-int serial_tstc(void)
+static int oc_serial_tstc(void)
{
unsigned status ;
((1 << YANU_RFIFO_CHARS_N) - 1)) > 0);
}
-int serial_getc (void)
+statoc int oc_serial_getc(void)
{
while (serial_tstc() == 0)
WATCHDOG_RESET ();
return(readl(&uart->data) & YANU_DATA_CHAR_MASK);
}
+
+static struct serial_device oc_serial_drv = {
+ .name = "oc_serial",
+ .start = oc_serial_init,
+ .stop = NULL,
+ .setbrg = oc_serial_setbrg,
+ .putc = oc_serial_putc,
+ .puts = default_serial_puts,
+ .getc = oc_serial_getc,
+ .tstc = oc_serial_tstc,
+};
+
+void oc_serial_initialize(void)
+{
+ serial_register(&oc_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &oc_serial_drv;
+}
}
-void serial_setbrg (void)
+static void s3c4510b_serial_setbrg(void)
{
UART_LINE_CTRL ulctrl;
UART_CTRL uctrl;
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
-int serial_init (void)
+static int s3c4510b_serial_init(void)
{
#if CONFIG_SERIAL1 == 1
/*
* Output a single byte to the serial port.
*/
-void serial_putc (const char c)
+static void s3c4510_serial_putc(const char c)
{
/* wait for room in the transmit FIFO */
while( !uart->m_stat.bf.txBufEmpty);
* Test if an input byte is ready from the serial port. Returns non-zero on
* success, 0 otherwise.
*/
-int serial_tstc (void)
+static int s3c4510b_serial_tstc(void)
{
return uart->m_stat.bf.rxReady;
}
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_getc (void)
+static int s3c4510b_serial_getc(void)
{
int rv;
}
}
-void serial_puts (const char *s)
+static void s3c4510b_serial_puts(const char *s)
{
- while (*s) {
- serial_putc (*s++);
- }
+ default_serial_puts(s);
/* busy wait for tx complete */
- while ( !uart->m_stat.bf.txComplete);
+ while (!uart->m_stat.bf.txComplete);
/* clear break */
uart->m_ctrl.bf.sendBreak = 0;
}
+
+static struct serial_device s3c4510b_serial_drv = {
+ .name = "s3c4510b_serial",
+ .start = s3c4510b_serial_init,
+ .stop = NULL,
+ .setbrg = s3c4510b_serial_setbrg,
+ .putc = s3c4510b_serial_putc,
+ .puts = s3c4510b_serial_puts,
+ .getc = s3c4510b_serial_getc,
+ .tstc = s3c4510b_serial_tstc,
+};
+
+void s3c4510b_serial_initialize(void)
+{
+ serial_register(&s3c4510b_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &s3c4510b_serial_drv;
+}
0xffdf,
};
-void serial_setbrg(void)
+static void s3c64xx_serial_setbrg(void)
{
s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
u32 pclk = get_PCLK();
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*/
-int serial_init(void)
+static int s3c64xx_serial_init(void)
{
s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_getc(void)
+static int s3c64xx_serial_getc(void)
{
s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
/*
* Output a single byte to the serial port.
*/
-void serial_putc(const char c)
+static void s3c64xx_serial_putc(const char c)
{
s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
/*
* Test whether a character is in the RX buffer
*/
-int serial_tstc(void)
+static int s3c64xx_serial_tstc(void)
{
s3c64xx_uart *const uart = s3c64xx_get_base_uart(UART_NR);
return uart->UTRSTAT & 0x1;
}
-void serial_puts(const char *s)
+static struct serial_device s3c64xx_serial_drv = {
+ .name = "s3c64xx_serial",
+ .start = s3c64xx_serial_init,
+ .stop = NULL,
+ .setbrg = s3c64xx_serial_setbrg,
+ .putc = s3c64xx_serial_putc,
+ .puts = default_serial_puts,
+ .getc = s3c64xx_serial_getc,
+ .tstc = s3c64xx_serial_tstc,
+};
+
+void s3c64xx_serial_initialize(void)
+{
+ serial_register(&s3c64xx_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
{
- while (*s)
- serial_putc(*s++);
+ return &s3c64xx_serial_drv;
}
#include <common.h>
#include <os.h>
+#include <serial.h>
+#include <linux/compiler.h>
-int serial_init(void)
+static int sandbox_serial_init(void)
{
os_tty_raw(0);
return 0;
}
-void serial_setbrg(void)
+static void sandbox_serial_setbrg(void)
{
}
-void serial_putc(const char ch)
+static void sandbox_serial_putc(const char ch)
{
os_write(1, &ch, 1);
}
-void serial_puts(const char *str)
+static void sandbox_serial_puts(const char *str)
{
os_write(1, str, strlen(str));
}
-int serial_getc(void)
+static int sandbox_serial_getc(void)
{
char buf;
ssize_t count;
return count == 1 ? buf : 0;
}
-int serial_tstc(void)
+static int sandbox_serial_tstc(void)
{
return 0;
}
+
+static struct serial_device sandbox_serial_drv = {
+ .name = "sandbox_serial",
+ .start = sandbox_serial_init,
+ .stop = NULL,
+ .setbrg = sandbox_serial_setbrg,
+ .putc = sandbox_serial_putc,
+ .puts = sandbox_serial_puts,
+ .getc = sandbox_serial_getc,
+ .tstc = sandbox_serial_tstc,
+};
+
+void sandbox_serial_initialize(void)
+{
+ serial_register(&sandbox_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &sandbox_serial_drv;
+}
/*
- * (C) Copyright 2000
- * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ * (C) Copyright 2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*/
#include <common.h>
-#include <linux/compiler.h>
-
-#include <ns16550.h>
-#ifdef CONFIG_NS87308
-#include <ns87308.h>
-#endif
-
-#if defined (CONFIG_SERIAL_MULTI)
#include <serial.h>
-#endif
+#include <stdio_dev.h>
+#include <post.h>
+#include <linux/compiler.h>
+#include <errno.h>
DECLARE_GLOBAL_DATA_PTR;
-#if !defined(CONFIG_CONS_INDEX)
-#if defined (CONFIG_SERIAL_MULTI)
-/* with CONFIG_SERIAL_MULTI we might have no console
- * on these devices
- */
-#else
-#error "No console index specified."
-#endif /* CONFIG_SERIAL_MULTI */
-#elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 4)
-#error "Invalid console index value."
-#endif
+static struct serial_device *serial_devices;
+static struct serial_device *serial_current;
-#if CONFIG_CONS_INDEX == 1 && !defined(CONFIG_SYS_NS16550_COM1)
-#error "Console port 1 defined but not configured."
-#elif CONFIG_CONS_INDEX == 2 && !defined(CONFIG_SYS_NS16550_COM2)
-#error "Console port 2 defined but not configured."
-#elif CONFIG_CONS_INDEX == 3 && !defined(CONFIG_SYS_NS16550_COM3)
-#error "Console port 3 defined but not configured."
-#elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4)
-#error "Console port 4 defined but not configured."
-#endif
+/**
+ * serial_null() - Void registration routine of a serial driver
+ *
+ * This routine implements a void registration routine of a serial
+ * driver. The registration routine of a particular driver is aliased
+ * to this empty function in case the driver is not compiled into
+ * U-Boot.
+ */
+static void serial_null(void)
+{
+}
-/* Note: The port number specified in the functions is 1 based.
- * the array is 0 based.
+/**
+ * serial_initfunc() - Forward declare of driver registration routine
+ * @name: Name of the real driver registration routine.
+ *
+ * This macro expands onto forward declaration of a driver registration
+ * routine, which is then used below in serial_initialize() function.
+ * The declaration is made weak and aliases to serial_null() so in case
+ * the driver is not compiled in, the function is still declared and can
+ * be used, but aliases to serial_null() and thus is optimized away.
*/
-static NS16550_t serial_ports[4] = {
-#ifdef CONFIG_SYS_NS16550_COM1
- (NS16550_t)CONFIG_SYS_NS16550_COM1,
-#else
- NULL,
-#endif
-#ifdef CONFIG_SYS_NS16550_COM2
- (NS16550_t)CONFIG_SYS_NS16550_COM2,
-#else
- NULL,
-#endif
-#ifdef CONFIG_SYS_NS16550_COM3
- (NS16550_t)CONFIG_SYS_NS16550_COM3,
-#else
- NULL,
-#endif
-#ifdef CONFIG_SYS_NS16550_COM4
- (NS16550_t)CONFIG_SYS_NS16550_COM4
-#else
- NULL
-#endif
-};
-
-#define PORT serial_ports[port-1]
-
-#if defined(CONFIG_SERIAL_MULTI)
-
-/* Multi serial device functions */
-#define DECLARE_ESERIAL_FUNCTIONS(port) \
- int eserial##port##_init (void) {\
- int clock_divisor; \
- clock_divisor = calc_divisor(serial_ports[port-1]); \
- NS16550_init(serial_ports[port-1], clock_divisor); \
- return(0);}\
- void eserial##port##_setbrg (void) {\
- serial_setbrg_dev(port);}\
- int eserial##port##_getc (void) {\
- return serial_getc_dev(port);}\
- int eserial##port##_tstc (void) {\
- return serial_tstc_dev(port);}\
- void eserial##port##_putc (const char c) {\
- serial_putc_dev(port, c);}\
- void eserial##port##_puts (const char *s) {\
- serial_puts_dev(port, s);}
-
-/* Serial device descriptor */
-#define INIT_ESERIAL_STRUCTURE(port, name) {\
- name,\
- eserial##port##_init,\
- NULL,\
- eserial##port##_setbrg,\
- eserial##port##_getc,\
- eserial##port##_tstc,\
- eserial##port##_putc,\
- eserial##port##_puts, }
-
-#endif /* CONFIG_SERIAL_MULTI */
-
-static int calc_divisor (NS16550_t port)
+#define serial_initfunc(name) \
+ void name(void) \
+ __attribute__((weak, alias("serial_null")));
+
+serial_initfunc(mpc8xx_serial_initialize);
+serial_initfunc(ns16550_serial_initialize);
+serial_initfunc(pxa_serial_initialize);
+serial_initfunc(s3c24xx_serial_initialize);
+serial_initfunc(s5p_serial_initialize);
+serial_initfunc(zynq_serial_initalize);
+serial_initfunc(bfin_serial_initialize);
+serial_initfunc(bfin_jtag_initialize);
+serial_initfunc(mpc512x_serial_initialize);
+serial_initfunc(uartlite_serial_initialize);
+serial_initfunc(au1x00_serial_initialize);
+serial_initfunc(asc_serial_initialize);
+serial_initfunc(jz_serial_initialize);
+serial_initfunc(mpc5xx_serial_initialize);
+serial_initfunc(mpc8220_serial_initialize);
+serial_initfunc(mpc8260_scc_serial_initialize);
+serial_initfunc(mpc8260_smc_serial_initialize);
+serial_initfunc(mpc85xx_serial_initialize);
+serial_initfunc(iop480_serial_initialize);
+serial_initfunc(leon2_serial_initialize);
+serial_initfunc(leon3_serial_initialize);
+serial_initfunc(marvell_serial_initialize);
+serial_initfunc(amirix_serial_initialize);
+serial_initfunc(bmw_serial_initialize);
+serial_initfunc(cogent_serial_initialize);
+serial_initfunc(cpci750_serial_initialize);
+serial_initfunc(evb64260_serial_initialize);
+serial_initfunc(ml2_serial_initialize);
+serial_initfunc(sconsole_serial_initialize);
+serial_initfunc(p3mx_serial_initialize);
+serial_initfunc(altera_jtag_serial_initialize);
+serial_initfunc(altera_serial_initialize);
+serial_initfunc(atmel_serial_initialize);
+serial_initfunc(lpc32xx_serial_initialize);
+serial_initfunc(mcf_serial_initialize);
+serial_initfunc(ns9750_serial_initialize);
+serial_initfunc(oc_serial_initialize);
+serial_initfunc(s3c4510b_serial_initialize);
+serial_initfunc(s3c64xx_serial_initialize);
+serial_initfunc(sandbox_serial_initialize);
+serial_initfunc(clps7111_serial_initialize);
+serial_initfunc(imx_serial_initialize);
+serial_initfunc(ixp_serial_initialize);
+serial_initfunc(ks8695_serial_initialize);
+serial_initfunc(lh7a40x_serial_initialize);
+serial_initfunc(lpc2292_serial_initialize);
+serial_initfunc(max3100_serial_initialize);
+serial_initfunc(mxc_serial_initialize);
+serial_initfunc(netarm_serial_initialize);
+serial_initfunc(pl01x_serial_initialize);
+serial_initfunc(s3c44b0_serial_initialize);
+serial_initfunc(sa1100_serial_initialize);
+serial_initfunc(sh_serial_initialize);
+
+/**
+ * serial_register() - Register serial driver with serial driver core
+ * @dev: Pointer to the serial driver structure
+ *
+ * This function registers the serial driver supplied via @dev with
+ * serial driver core, thus making U-Boot aware of it and making it
+ * available for U-Boot to use. On platforms that still require manual
+ * relocation of constant variables, relocation of the supplied structure
+ * is performed.
+ */
+void serial_register(struct serial_device *dev)
{
-#ifdef CONFIG_OMAP1510
- /* If can't cleanly clock 115200 set div to 1 */
- if ((CONFIG_SYS_NS16550_CLK == 12000000) && (gd->baudrate == 115200)) {
- port->osc_12m_sel = OSC_12M_SEL; /* enable 6.5 * divisor */
- return (1); /* return 1 for base divisor */
- }
- port->osc_12m_sel = 0; /* clear if previsouly set */
-#endif
-#ifdef CONFIG_OMAP1610
- /* If can't cleanly clock 115200 set div to 1 */
- if ((CONFIG_SYS_NS16550_CLK == 48000000) && (gd->baudrate == 115200)) {
- return (26); /* return 26 for base divisor */
- }
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
+ if (dev->start)
+ dev->start += gd->reloc_off;
+ if (dev->stop)
+ dev->stop += gd->reloc_off;
+ if (dev->setbrg)
+ dev->setbrg += gd->reloc_off;
+ if (dev->getc)
+ dev->getc += gd->reloc_off;
+ if (dev->tstc)
+ dev->tstc += gd->reloc_off;
+ if (dev->putc)
+ dev->putc += gd->reloc_off;
+ if (dev->puts)
+ dev->puts += gd->reloc_off;
#endif
-#ifdef CONFIG_APTIX
-#define MODE_X_DIV 13
-#else
-#define MODE_X_DIV 16
-#endif
+ dev->next = serial_devices;
+ serial_devices = dev;
+}
- /* Compute divisor value. Normally, we should simply return:
- * CONFIG_SYS_NS16550_CLK) / MODE_X_DIV / gd->baudrate
- * but we need to round that value by adding 0.5.
- * Rounding is especially important at high baud rates.
- */
- return (CONFIG_SYS_NS16550_CLK + (gd->baudrate * (MODE_X_DIV / 2))) /
- (MODE_X_DIV * gd->baudrate);
+/**
+ * serial_initialize() - Register all compiled-in serial port drivers
+ *
+ * This function registers all serial port drivers that are compiled
+ * into the U-Boot binary with the serial core, thus making them
+ * available to U-Boot to use. Lastly, this function assigns a default
+ * serial port to the serial core. That serial port is then used as a
+ * default output.
+ */
+void serial_initialize(void)
+{
+ mpc8xx_serial_initialize();
+ ns16550_serial_initialize();
+ pxa_serial_initialize();
+ s3c24xx_serial_initialize();
+ s5p_serial_initialize();
+ mpc512x_serial_initialize();
+ bfin_serial_initialize();
+ bfin_jtag_initialize();
+ uartlite_serial_initialize();
+ zynq_serial_initalize();
+ au1x00_serial_initialize();
+ asc_serial_initialize();
+ jz_serial_initialize();
+ mpc5xx_serial_initialize();
+ mpc8220_serial_initialize();
+ mpc8260_scc_serial_initialize();
+ mpc8260_smc_serial_initialize();
+ mpc85xx_serial_initialize();
+ iop480_serial_initialize();
+ leon2_serial_initialize();
+ leon3_serial_initialize();
+ marvell_serial_initialize();
+ amirix_serial_initialize();
+ bmw_serial_initialize();
+ cogent_serial_initialize();
+ cpci750_serial_initialize();
+ evb64260_serial_initialize();
+ ml2_serial_initialize();
+ sconsole_serial_initialize();
+ p3mx_serial_initialize();
+ altera_jtag_serial_initialize();
+ altera_serial_initialize();
+ atmel_serial_initialize();
+ lpc32xx_serial_initialize();
+ mcf_serial_initialize();
+ ns9750_serial_initialize();
+ oc_serial_initialize();
+ s3c4510b_serial_initialize();
+ s3c64xx_serial_initialize();
+ sandbox_serial_initialize();
+ clps7111_serial_initialize();
+ imx_serial_initialize();
+ ixp_serial_initialize();
+ ks8695_serial_initialize();
+ lh7a40x_serial_initialize();
+ lpc2292_serial_initialize();
+ max3100_serial_initialize();
+ mxc_serial_initialize();
+ netarm_serial_initialize();
+ pl01x_serial_initialize();
+ s3c44b0_serial_initialize();
+ sa1100_serial_initialize();
+ sh_serial_initialize();
+
+ serial_assign(default_serial_console()->name);
}
-#if !defined(CONFIG_SERIAL_MULTI)
-int serial_init (void)
+/**
+ * serial_stdio_init() - Register serial ports with STDIO core
+ *
+ * This function generates a proxy driver for each serial port driver.
+ * These proxy drivers then register with the STDIO core, making the
+ * serial drivers available as STDIO devices.
+ */
+void serial_stdio_init(void)
{
- int clock_divisor;
+ struct stdio_dev dev;
+ struct serial_device *s = serial_devices;
-#ifdef CONFIG_NS87308
- initialise_ns87308();
-#endif
+ while (s) {
+ memset(&dev, 0, sizeof(dev));
-#ifdef CONFIG_SYS_NS16550_COM1
- clock_divisor = calc_divisor(serial_ports[0]);
- NS16550_init(serial_ports[0], clock_divisor);
-#endif
-#ifdef CONFIG_SYS_NS16550_COM2
- clock_divisor = calc_divisor(serial_ports[1]);
- NS16550_init(serial_ports[1], clock_divisor);
-#endif
-#ifdef CONFIG_SYS_NS16550_COM3
- clock_divisor = calc_divisor(serial_ports[2]);
- NS16550_init(serial_ports[2], clock_divisor);
-#endif
-#ifdef CONFIG_SYS_NS16550_COM4
- clock_divisor = calc_divisor(serial_ports[3]);
- NS16550_init(serial_ports[3], clock_divisor);
-#endif
+ strcpy(dev.name, s->name);
+ dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT;
- return (0);
-}
-#endif
+ dev.start = s->start;
+ dev.stop = s->stop;
+ dev.putc = s->putc;
+ dev.puts = s->puts;
+ dev.getc = s->getc;
+ dev.tstc = s->tstc;
-void
-_serial_putc(const char c,const int port)
-{
- if (c == '\n')
- NS16550_putc(PORT, '\r');
+ stdio_register(&dev);
- NS16550_putc(PORT, c);
+ s = s->next;
+ }
}
-void
-_serial_putc_raw(const char c,const int port)
+/**
+ * serial_assign() - Select the serial output device by name
+ * @name: Name of the serial driver to be used as default output
+ *
+ * This function configures the serial output multiplexing by
+ * selecting which serial device will be used as default. In case
+ * the STDIO "serial" device is selected as stdin/stdout/stderr,
+ * the serial device previously configured by this function will be
+ * used for the particular operation.
+ *
+ * Returns 0 on success, negative on error.
+ */
+int serial_assign(const char *name)
{
- NS16550_putc(PORT, c);
-}
+ struct serial_device *s;
-void
-_serial_puts (const char *s,const int port)
-{
- while (*s) {
- _serial_putc (*s++,port);
+ for (s = serial_devices; s; s = s->next) {
+ if (strcmp(s->name, name))
+ continue;
+ serial_current = s;
+ return 0;
}
-}
-
-int
-_serial_getc(const int port)
-{
- return NS16550_getc(PORT);
+ return -EINVAL;
}
-int
-_serial_tstc(const int port)
-{
- return NS16550_tstc(PORT);
-}
-
-void
-_serial_setbrg (const int port)
+/**
+ * serial_reinit_all() - Reinitialize all compiled-in serial ports
+ *
+ * This function reinitializes all serial ports that are compiled
+ * into U-Boot by calling their serial_start() functions.
+ */
+void serial_reinit_all(void)
{
- int clock_divisor;
+ struct serial_device *s;
- clock_divisor = calc_divisor(PORT);
- NS16550_reinit(PORT, clock_divisor);
+ for (s = serial_devices; s; s = s->next)
+ s->start();
}
-#if defined(CONFIG_SERIAL_MULTI)
-static inline void
-serial_putc_dev(unsigned int dev_index,const char c)
+/**
+ * get_current() - Return pointer to currently selected serial port
+ *
+ * This function returns a pointer to currently selected serial port.
+ * The currently selected serial port is altered by serial_assign()
+ * function.
+ *
+ * In case this function is called before relocation or before any serial
+ * port is configured, this function calls default_serial_console() to
+ * determine the serial port. Otherwise, the configured serial port is
+ * returned.
+ *
+ * Returns pointer to the currently selected serial port on success,
+ * NULL on error.
+ */
+static struct serial_device *get_current(void)
{
- _serial_putc(c,dev_index);
-}
+ struct serial_device *dev;
+
+ if (!(gd->flags & GD_FLG_RELOC))
+ dev = default_serial_console();
+ else if (!serial_current)
+ dev = default_serial_console();
+ else
+ dev = serial_current;
+
+ /* We must have a console device */
+ if (!dev) {
+#ifdef CONFIG_SPL_BUILD
+ puts("Cannot find console\n");
+ hang();
#else
-void
-serial_putc(const char c)
-{
- _serial_putc(c,CONFIG_CONS_INDEX);
-}
+ panic("Cannot find console\n");
#endif
+ }
-#if defined(CONFIG_SERIAL_MULTI)
-static inline void
-serial_putc_raw_dev(unsigned int dev_index,const char c)
-{
- _serial_putc_raw(c,dev_index);
+ return dev;
}
-#else
-void
-serial_putc_raw(const char c)
-{
- _serial_putc_raw(c,CONFIG_CONS_INDEX);
-}
-#endif
-#if defined(CONFIG_SERIAL_MULTI)
-static inline void
-serial_puts_dev(unsigned int dev_index,const char *s)
-{
- _serial_puts(s,dev_index);
-}
-#else
-void
-serial_puts(const char *s)
+/**
+ * serial_init() - Initialize currently selected serial port
+ *
+ * This function initializes the currently selected serial port. This
+ * usually involves setting up the registers of that particular port,
+ * enabling clock and such. This function uses the get_current() call
+ * to determine which port is selected.
+ *
+ * Returns 0 on success, negative on error.
+ */
+int serial_init(void)
{
- _serial_puts(s,CONFIG_CONS_INDEX);
+ return get_current()->start();
}
-#endif
-#if defined(CONFIG_SERIAL_MULTI)
-static inline int
-serial_getc_dev(unsigned int dev_index)
+/**
+ * serial_setbrg() - Configure baud-rate of currently selected serial port
+ *
+ * This function configures the baud-rate of the currently selected
+ * serial port. The baud-rate is retrieved from global data within
+ * the serial port driver. This function uses the get_current() call
+ * to determine which port is selected.
+ *
+ * Returns 0 on success, negative on error.
+ */
+void serial_setbrg(void)
{
- return _serial_getc(dev_index);
+ get_current()->setbrg();
}
-#else
-int
-serial_getc(void)
+
+/**
+ * serial_getc() - Read character from currently selected serial port
+ *
+ * This function retrieves a character from currently selected serial
+ * port. In case there is no character waiting on the serial port,
+ * this function will block and wait for the character to appear. This
+ * function uses the get_current() call to determine which port is
+ * selected.
+ *
+ * Returns the character on success, negative on error.
+ */
+int serial_getc(void)
{
- return _serial_getc(CONFIG_CONS_INDEX);
+ return get_current()->getc();
}
-#endif
-#if defined(CONFIG_SERIAL_MULTI)
-static inline int
-serial_tstc_dev(unsigned int dev_index)
+/**
+ * serial_tstc() - Test if data is available on currently selected serial port
+ *
+ * This function tests if one or more characters are available on
+ * currently selected serial port. This function never blocks. This
+ * function uses the get_current() call to determine which port is
+ * selected.
+ *
+ * Returns positive if character is available, zero otherwise.
+ */
+int serial_tstc(void)
{
- return _serial_tstc(dev_index);
+ return get_current()->tstc();
}
-#else
-int
-serial_tstc(void)
+
+/**
+ * serial_putc() - Output character via currently selected serial port
+ * @c: Single character to be output from the serial port.
+ *
+ * This function outputs a character via currently selected serial
+ * port. This character is passed to the serial port driver responsible
+ * for controlling the hardware. The hardware may still be in process
+ * of transmitting another character, therefore this function may block
+ * for a short amount of time. This function uses the get_current()
+ * call to determine which port is selected.
+ */
+void serial_putc(const char c)
{
- return _serial_tstc(CONFIG_CONS_INDEX);
+ get_current()->putc(c);
}
-#endif
-#if defined(CONFIG_SERIAL_MULTI)
-static inline void
-serial_setbrg_dev(unsigned int dev_index)
+/**
+ * serial_puts() - Output string via currently selected serial port
+ * @s: Zero-terminated string to be output from the serial port.
+ *
+ * This function outputs a zero-terminated string via currently
+ * selected serial port. This function behaves as an accelerator
+ * in case the hardware can queue multiple characters for transfer.
+ * The whole string that is to be output is available to the function
+ * implementing the hardware manipulation. Transmitting the whole
+ * string may take some time, thus this function may block for some
+ * amount of time. This function uses the get_current() call to
+ * determine which port is selected.
+ */
+void serial_puts(const char *s)
{
- _serial_setbrg(dev_index);
+ get_current()->puts(s);
}
-#else
-void
-serial_setbrg(void)
+
+/**
+ * default_serial_puts() - Output string by calling serial_putc() in loop
+ * @s: Zero-terminated string to be output from the serial port.
+ *
+ * This function outputs a zero-terminated string by calling serial_putc()
+ * in a loop. Most drivers do not support queueing more than one byte for
+ * transfer, thus this function precisely implements their serial_puts().
+ *
+ * To optimize the number of get_current() calls, this function only
+ * calls get_current() once and then directly accesses the putc() call
+ * of the &struct serial_device .
+ */
+void default_serial_puts(const char *s)
{
- _serial_setbrg(CONFIG_CONS_INDEX);
+ struct serial_device *dev = get_current();
+ while (*s)
+ dev->putc(*s++);
}
-#endif
-#if defined(CONFIG_SERIAL_MULTI)
-
-DECLARE_ESERIAL_FUNCTIONS(1);
-struct serial_device eserial1_device =
- INIT_ESERIAL_STRUCTURE(1, "eserial0");
-DECLARE_ESERIAL_FUNCTIONS(2);
-struct serial_device eserial2_device =
- INIT_ESERIAL_STRUCTURE(2, "eserial1");
-DECLARE_ESERIAL_FUNCTIONS(3);
-struct serial_device eserial3_device =
- INIT_ESERIAL_STRUCTURE(3, "eserial2");
-DECLARE_ESERIAL_FUNCTIONS(4);
-struct serial_device eserial4_device =
- INIT_ESERIAL_STRUCTURE(4, "eserial3");
-
-__weak struct serial_device *default_serial_console(void)
+#if CONFIG_POST & CONFIG_SYS_POST_UART
+static const int bauds[] = CONFIG_SYS_BAUDRATE_TABLE;
+
+/**
+ * uart_post_test() - Test the currently selected serial port using POST
+ * @flags: POST framework flags
+ *
+ * Do a loopback test of the currently selected serial port. This
+ * function is only useful in the context of the POST testing framwork.
+ * The serial port is firstly configured into loopback mode and then
+ * characters are sent through it.
+ *
+ * Returns 0 on success, value otherwise.
+ */
+/* Mark weak until post/cpu/.../uart.c migrate over */
+__weak
+int uart_post_test(int flags)
{
-#if CONFIG_CONS_INDEX == 1
- return &eserial1_device;
-#elif CONFIG_CONS_INDEX == 2
- return &eserial2_device;
-#elif CONFIG_CONS_INDEX == 3
- return &eserial3_device;
-#elif CONFIG_CONS_INDEX == 4
- return &eserial4_device;
-#else
-#error "Bad CONFIG_CONS_INDEX."
-#endif
-}
+ unsigned char c;
+ int ret, saved_baud, b;
+ struct serial_device *saved_dev, *s;
+ bd_t *bd = gd->bd;
+
+ /* Save current serial state */
+ ret = 0;
+ saved_dev = serial_current;
+ saved_baud = bd->bi_baudrate;
+
+ for (s = serial_devices; s; s = s->next) {
+ /* If this driver doesn't support loop back, skip it */
+ if (!s->loop)
+ continue;
+
+ /* Test the next device */
+ serial_current = s;
+
+ ret = serial_init();
+ if (ret)
+ goto done;
+
+ /* Consume anything that happens to be queued */
+ while (serial_tstc())
+ serial_getc();
+
+ /* Enable loop back */
+ s->loop(1);
+
+ /* Test every available baud rate */
+ for (b = 0; b < ARRAY_SIZE(bauds); ++b) {
+ bd->bi_baudrate = bauds[b];
+ serial_setbrg();
+
+ /*
+ * Stick to printable chars to avoid issues:
+ * - terminal corruption
+ * - serial program reacting to sequences and sending
+ * back random extra data
+ * - most serial drivers add in extra chars (like \r\n)
+ */
+ for (c = 0x20; c < 0x7f; ++c) {
+ /* Send it out */
+ serial_putc(c);
+
+ /* Make sure it's the same one */
+ ret = (c != serial_getc());
+ if (ret) {
+ s->loop(0);
+ goto done;
+ }
+
+ /* Clean up the output in case it was sent */
+ serial_putc('\b');
+ ret = ('\b' != serial_getc());
+ if (ret) {
+ s->loop(0);
+ goto done;
+ }
+ }
+ }
+
+ /* Disable loop back */
+ s->loop(0);
+
+ /* XXX: There is no serial_stop() !? */
+ if (s->stop)
+ s->stop();
+ }
-#endif /* CONFIG_SERIAL_MULTI */
+ done:
+ /* Restore previous serial state */
+ serial_current = saved_dev;
+ bd->bi_baudrate = saved_baud;
+ serial_reinit_all();
+ serial_setbrg();
+
+ return ret;
+}
+#endif
DECLARE_GLOBAL_DATA_PTR;
-void serial_setbrg (void)
+static void clps7111_serial_setbrg(void)
{
unsigned int reg = 0;
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
-int serial_init (void)
+static int clps7111_serial_init(void)
{
serial_setbrg ();
/*
* Output a single byte to the serial port.
*/
-void serial_putc (const char c)
+static void clps7111_serial_putc(const char c)
{
int tmo;
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_tstc (void)
+static int clps7111_serial_tstc(void)
{
return !(IO_SYSFLG1 & SYSFLG1_URXFE);
}
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_getc (void)
+static int clps7111_serial_getc(void)
{
while (IO_SYSFLG1 & SYSFLG1_URXFE);
return IO_UARTDR1 & 0xff;
}
-void
-serial_puts (const char *s)
+static struct serial_device clps7111_serial_drv = {
+ .name = "clps7111_serial",
+ .start = clps7111_serial_init,
+ .stop = NULL,
+ .setbrg = clps7111_serial_setbrg,
+ .putc = clps7111_serial_putc,
+ .puts = default_serial_puts,
+ .getc = clps7111_serial_getc,
+ .tstc = clps7111_serial_tstc,
+};
+
+void clps7111_serial_initialize(void)
{
- while (*s) {
- serial_putc (*s++);
- }
+ serial_register(&clps7111_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &clps7111_serial_drv;
}
#include <common.h>
#include <asm/arch/imx-regs.h>
+#include <serial.h>
+#include <linux/compiler.h>
#if defined CONFIG_IMX_SERIAL1
#define UART_BASE IMX_UART1_BASE
DECLARE_GLOBAL_DATA_PTR;
-void serial_setbrg (void)
+static void imx_serial_setbrg(void)
{
serial_init();
}
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
-int serial_init (void)
+static int imx_serial_init(void)
{
volatile struct imx_serial* base = (struct imx_serial *)UART_BASE;
unsigned int ufcr_rfdiv;
* otherwise. When the function is successful, the character read is
* written into its argument c.
*/
-int serial_getc (void)
+static int imx_serial_getc(void)
{
volatile struct imx_serial* base = (struct imx_serial *)UART_BASE;
unsigned char ch;
/*
* Output a single byte to the serial port.
*/
-void serial_putc (const char c)
+static void imx_serial_putc(const char c)
{
volatile struct imx_serial* base = (struct imx_serial *)UART_BASE;
/*
* Test whether a character is in the RX buffer
*/
-int serial_tstc (void)
+static int imx_serial_tstc(void)
{
volatile struct imx_serial* base = (struct imx_serial *)UART_BASE;
return 1;
}
-void
-serial_puts (const char *s)
+static struct serial_device imx_serial_drv = {
+ .name = "imx_serial",
+ .start = imx_serial_init,
+ .stop = NULL,
+ .setbrg = imx_serial_setbrg,
+ .putc = imx_serial_putc,
+ .puts = default_serial_puts,
+ .getc = imx_serial_getc,
+ .tstc = imx_serial_tstc,
+};
+
+void imx_serial_initialize(void)
+{
+ serial_register(&imx_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
{
- while (*s) {
- serial_putc (*s++);
- }
+ return &imx_serial_drv;
}
#include <common.h>
#include <asm/arch/ixp425.h>
#include <watchdog.h>
+#include <serial.h>
+#include <linux/compiler.h>
/*
* 14.7456 MHz
DECLARE_GLOBAL_DATA_PTR;
-void serial_setbrg (void)
+static void ixp_serial_setbrg(void)
{
unsigned int quot = 0;
int uart = CONFIG_SYS_IXP425_CONSOLE;
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
-int serial_init (void)
+static int ixp_serial_init(void)
{
serial_setbrg ();
/*
* Output a single byte to the serial port.
*/
-void serial_putc (const char c)
+static void ixp_serial_putc(const char c)
{
/* wait for room in the tx FIFO on UART */
while ((LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_TEMT) == 0)
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_tstc (void)
+static int ixp_serial_tstc(void)
{
return LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR;
}
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_getc (void)
+static int ixp_serial_getc(void)
{
while (!(LSR(CONFIG_SYS_IXP425_CONSOLE) & LSR_DR))
WATCHDOG_RESET(); /* Reset HW Watchdog, if needed */
return (char) RBR(CONFIG_SYS_IXP425_CONSOLE) & 0xff;
}
-void
-serial_puts (const char *s)
+static struct serial_device ixp_serial_drv = {
+ .name = "ixp_serial",
+ .start = ixp_serial_init,
+ .stop = NULL,
+ .setbrg = ixp_serial_setbrg,
+ .putc = ixp_serial_putc,
+ .puts = default_serial_puts,
+ .getc = ixp_serial_getc,
+ .tstc = ixp_serial_tstc,
+};
+
+void ixp_serial_initialize(void)
{
- while (*s) {
- serial_putc (*s++);
- }
+ serial_register(&ixp_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &ixp_serial_drv;
}
#include <common.h>
#include <asm/arch/platform.h>
+#include <serial.h>
+#include <linux/compiler.h>
#ifndef CONFIG_SERIAL1
#error "Bad: you didn't configure serial ..."
int serial_console = 1;
-void serial_setbrg(void)
+static void ks8695_serial_setbrg(void)
{
volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
uartp->LCR = KS8695_UART_LINEC_WLEN8;
}
-int serial_init(void)
+static int ks8695_serial_init(void)
{
serial_console = 1;
serial_setbrg();
return 0;
}
-void serial_raw_putc(const char c)
+static void ks8695_serial_raw_putc(const char c)
{
volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
int i;
uartp->TX = c;
}
-void serial_putc(const char c)
+static void ks8695_serial_putc(const char c)
{
if (serial_console) {
- serial_raw_putc(c);
+ ks8695_serial_raw_putc(c);
if (c == '\n')
- serial_raw_putc('\r');
+ ks8695_serial_raw_putc('\r');
}
}
-int serial_tstc(void)
+static int ks8695_serial_tstc(void)
{
volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
if (serial_console)
return 0;
}
-void serial_puts(const char *s)
-{
- char c;
- while ((c = *s++) != 0)
- serial_putc(c);
-}
-
-int serial_getc(void)
+static int ks8695_serial_getc(void)
{
volatile struct ks8695uart *uartp = KS8695_UART_ADDR;
;
return (uartp->RX);
}
+
+static struct serial_device ks8695_serial_drv = {
+ .name = "ks8695_serial",
+ .start = ks8695_serial_init,
+ .stop = NULL,
+ .setbrg = ks8695_serial_setbrg,
+ .putc = ks8695_serial_putc,
+ .puts = default_serial_puts,
+ .getc = ks8695_serial_getc,
+ .tstc = ks8695_serial_tstc,
+};
+
+void ks8695_serial_initialize(void)
+{
+ serial_register(&ks8695_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &ks8695_serial_drv;
+}
+++ /dev/null
-/*
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- *
- */
-
-#include <common.h>
-#include <lh7a40x.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CONSOLE_UART1)
-# define UART_CONSOLE 1
-#elif defined(CONFIG_CONSOLE_UART2)
-# define UART_CONSOLE 2
-#elif defined(CONFIG_CONSOLE_UART3)
-# define UART_CONSOLE 3
-#else
-# error "No console configured ... "
-#endif
-
-void serial_setbrg (void)
-{
- lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
- int i;
- unsigned int reg = 0;
-
- /*
- * userguide 15.1.2.4
- *
- * BAUDDIV is (UART_REF_FREQ/(16 X BAUD))-1
- *
- * UART_REF_FREQ = external system clock input / 2 (Hz)
- * BAUD is desired baudrate (bits/s)
- *
- * NOTE: we add (divisor/2) to numerator to round for
- * more precision
- */
- reg = (((get_PLLCLK()/2) + ((16*gd->baudrate)/2)) / (16 * gd->baudrate)) - 1;
- uart->brcon = reg;
-
- for (i = 0; i < 100; i++);
-}
-
-/*
- * Initialise the serial port with the given baudrate. The settings
- * are always 8 data bits, no parity, 1 stop bit, no start bits.
- *
- */
-int serial_init (void)
-{
- lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
-
- /* UART must be enabled before writing to any config registers */
- uart->con |= (UART_EN);
-
-#ifdef CONFIG_CONSOLE_UART1
- /* infrared disabled */
- uart->con |= UART_SIRD;
-#endif
- /* loopback disabled */
- uart->con &= ~(UART_LBE);
-
- /* modem lines and tx/rx polarities */
- uart->con &= ~(UART_MXP | UART_TXP | UART_RXP);
-
- /* FIFO enable, N81 */
- uart->fcon = (UART_WLEN_8 | UART_FEN | UART_STP2_1);
-
- /* set baudrate */
- serial_setbrg ();
-
- /* enable rx interrupt */
- uart->inten |= UART_RI;
-
- return (0);
-}
-
-/*
- * Read a single byte from the serial port. Returns 1 on success, 0
- * otherwise. When the function is succesfull, the character read is
- * written into its argument c.
- */
-int serial_getc (void)
-{
- lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
-
- /* wait for character to arrive */
- while (uart->status & UART_RXFE);
-
- return(uart->data & 0xff);
-}
-
-#ifdef CONFIG_HWFLOW
-static int hwflow = 0; /* turned off by default */
-int hwflow_onoff(int on)
-{
- switch(on) {
- case 0:
- default:
- break; /* return current */
- case 1:
- hwflow = 1; /* turn on */
- break;
- case -1:
- hwflow = 0; /* turn off */
- break;
- }
- return hwflow;
-}
-#endif
-
-#ifdef CONFIG_MODEM_SUPPORT
-static int be_quiet = 0;
-void disable_putc(void)
-{
- be_quiet = 1;
-}
-
-void enable_putc(void)
-{
- be_quiet = 0;
-}
-#endif
-
-
-/*
- * Output a single byte to the serial port.
- */
-void serial_putc (const char c)
-{
- lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
-
-#ifdef CONFIG_MODEM_SUPPORT
- if (be_quiet)
- return;
-#endif
-
- /* wait for room in the tx FIFO */
- while (!(uart->status & UART_TXFE));
-
-#ifdef CONFIG_HWFLOW
- /* Wait for CTS up */
- while(hwflow && !(uart->status & UART_CTS));
-#endif
-
- uart->data = c;
-
- /* If \n, also do \r */
- if (c == '\n')
- serial_putc ('\r');
-}
-
-/*
- * Test whether a character is in the RX buffer
- */
-int serial_tstc (void)
-{
- lh7a40x_uart_t* uart = LH7A40X_UART_PTR(UART_CONSOLE);
-
- return(!(uart->status & UART_RXFE));
-}
-
-void
-serial_puts (const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
DECLARE_GLOBAL_DATA_PTR;
-void serial_setbrg (void)
+static void lpc2292_serial_setbrg(void)
{
unsigned short divisor = 0;
PUT8(U0FCR, 1); /* Enable RX and TX FIFOs */
}
-int serial_init (void)
+static int lpc2292_serial_init(void)
{
unsigned long pinsel0;
return (0);
}
-void serial_putc (const char c)
+static void lpc2292_serial_putc(const char c)
{
if (c == '\n')
{
PUT8(U0THR, c);
}
-int serial_getc (void)
+static int lpc2292_serial_getc(void)
{
while((GET8(U0LSR) & 1) == 0);
return GET8(U0RBR);
}
-void
-serial_puts (const char *s)
+/* Test if there is a byte to read */
+static int lpc2292_serial_tstc(void)
{
- while (*s) {
- serial_putc (*s++);
- }
+ return (GET8(U0LSR) & 1);
}
-/* Test if there is a byte to read */
-int serial_tstc (void)
+static struct serial_device lpc2292_serial_drv = {
+ .name = "lpc2292_serial",
+ .start = lpc2292_serial_init,
+ .stop = NULL,
+ .setbrg = lpc2292_serial_setbrg,
+ .putc = lpc2292_serial_putc,
+ .puts = default_serial_puts,
+ .getc = lpc2292_serial_getc,
+ .tstc = lpc2292_serial_tstc,
+};
+
+void lpc2292_serial_initialize(void)
{
- return (GET8(U0LSR) & 1);
+ serial_register(&lpc2292_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &lpc2292_serial_drv;
}
#include <common.h>
#include <watchdog.h>
+#include <serial.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
static int rxfifo_out;
static unsigned char rxfifo_buf[16];
-static void max3100_putc(int c)
+static void max3100_serial_putc_raw(int c)
{
unsigned int rx;
}
}
-static int max3100_getc(void)
+static int max3100_serial_getc(void)
{
int c;
unsigned int rx;
return c;
}
-static int max3100_tstc(void)
+static int max3100_serial_tstc(void)
{
unsigned int rx;
return 1;
}
-int serial_init(void)
+static int max3100_serial_init(void)
{
unsigned int wconf, rconf;
int i;
return (0);
}
-void serial_putc(const char c)
+static void max3100_serial_putc(const char c)
{
if (c == '\n')
- max3100_putc('\r');
+ max3100_serial_putc_raw('\r');
- max3100_putc(c);
+ max3100_serial_putc_raw(c);
}
-void serial_puts(const char *s)
+static void max3100_serial_puts(const char *s)
{
while (*s)
- serial_putc (*s++);
+ max3100_serial_putc_raw(*s++);
}
-int serial_getc(void)
+static void max3100_serial_setbrg(void)
{
- return max3100_getc();
}
-int serial_tstc(void)
+static struct serial_device max3100_serial_drv = {
+ .name = "max3100_serial",
+ .start = max3100_serial_init,
+ .stop = NULL,
+ .setbrg = max3100_serial_setbrg,
+ .putc = max3100_serial_putc,
+ .puts = max3100_serial_puts,
+ .getc = max3100_serial_getc,
+ .tstc = max3100_serial_tstc,
+};
+
+void max3100_serial_initialize(void)
{
- return max3100_tstc();
+ serial_register(&max3100_serial_drv);
}
-/* XXX WTF? */
-void serial_setbrg(void)
+__weak struct serial_device *default_serial_console(void)
{
+ return &max3100_serial_drv;
}
#include <watchdog.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
+#include <serial.h>
+#include <linux/compiler.h>
#define __REG(x) (*((volatile u32 *)(x)))
#define UART_PHYS CONFIG_MXC_UART_BASE
-#ifdef CONFIG_SERIAL_MULTI
-#warning "MXC driver does not support MULTI serials."
-#endif
-
/* Register definitions */
#define URXD 0x0 /* Receiver Register */
#define UTXD 0x40 /* Transmitter Register */
DECLARE_GLOBAL_DATA_PTR;
-void serial_setbrg (void)
+static void mxc_serial_setbrg(void)
{
u32 clk = imx_get_uartclk();
}
-int serial_getc (void)
+static int mxc_serial_getc(void)
{
while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
WATCHDOG_RESET();
return (__REG(UART_PHYS + URXD) & URXD_RX_DATA); /* mask out status from upper word */
}
-void serial_putc (const char c)
+static void mxc_serial_putc(const char c)
{
__REG(UART_PHYS + UTXD) = c;
/*
* Test whether a character is in the RX buffer
*/
-int serial_tstc (void)
+static int mxc_serial_tstc(void)
{
/* If receive fifo is empty, return false */
if (__REG(UART_PHYS + UTS) & UTS_RXEMPTY)
return 1;
}
-void
-serial_puts (const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
/*
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
-int serial_init (void)
+static int mxc_serial_init(void)
{
__REG(UART_PHYS + UCR1) = 0x0;
__REG(UART_PHYS + UCR2) = 0x0;
return 0;
}
+
+static struct serial_device mxc_serial_drv = {
+ .name = "mxc_serial",
+ .start = mxc_serial_init,
+ .stop = NULL,
+ .setbrg = mxc_serial_setbrg,
+ .putc = mxc_serial_putc,
+ .puts = default_serial_puts,
+ .getc = mxc_serial_getc,
+ .tstc = mxc_serial_tstc,
+};
+
+void mxc_serial_initialize(void)
+{
+ serial_register(&mxc_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &mxc_serial_drv;
+}
/*
* Setup both serial i/f with given baudrate
*/
-void serial_setbrg (void)
+static void netarm_serial_setbrg(void)
{
/* set 0 ... make sure pins are configured for serial */
#if !defined(CONFIG_NETARM_NS7520)
* Initialise the serial port with the given baudrate. The settings
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*/
-int serial_init (void)
+static int netarm_serial_init(void)
{
serial_setbrg ();
return 0;
/*
* Output a single byte to the serial port.
*/
-void serial_putc (const char c)
+static void netarm_serial_putc(const char c)
{
volatile unsigned char *fifo;
* Test of a single byte from the serial port. Returns 1 on success, 0
* otherwise.
*/
-int serial_tstc(void)
+static int netarm_serial_tstc(void)
{
return serial_reg_ch1->status_a & NETARM_SER_STATA_RX_RDY;
}
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise.
*/
-int serial_getc (void)
+static int netarm_serial_getc(void)
{
unsigned int ch_uint;
volatile unsigned int *fifo;
return ch_uint & 0xff;
}
-void serial_puts (const char *s)
+static struct serial_device netarm_serial_drv = {
+ .name = "netarm_serial",
+ .start = netarm_serial_init,
+ .stop = NULL,
+ .setbrg = netarm_serial_setbrg,
+ .putc = netarm_serial_putc,
+ .puts = default_serial_puts,
+ .getc = netarm_serial_getc,
+ .tstc = netarm_serial_tstc,
+};
+
+void netarm_serial_initialize(void)
{
- while (*s) {
- serial_putc (*s++);
- }
+ serial_register(&netarm_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &netarm_serial_drv;
}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/compiler.h>
+
+#include <ns16550.h>
+#ifdef CONFIG_NS87308
+#include <ns87308.h>
+#endif
+
+#include <serial.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !defined(CONFIG_CONS_INDEX)
+#elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 4)
+#error "Invalid console index value."
+#endif
+
+#if CONFIG_CONS_INDEX == 1 && !defined(CONFIG_SYS_NS16550_COM1)
+#error "Console port 1 defined but not configured."
+#elif CONFIG_CONS_INDEX == 2 && !defined(CONFIG_SYS_NS16550_COM2)
+#error "Console port 2 defined but not configured."
+#elif CONFIG_CONS_INDEX == 3 && !defined(CONFIG_SYS_NS16550_COM3)
+#error "Console port 3 defined but not configured."
+#elif CONFIG_CONS_INDEX == 4 && !defined(CONFIG_SYS_NS16550_COM4)
+#error "Console port 4 defined but not configured."
+#endif
+
+/* Note: The port number specified in the functions is 1 based.
+ * the array is 0 based.
+ */
+static NS16550_t serial_ports[4] = {
+#ifdef CONFIG_SYS_NS16550_COM1
+ (NS16550_t)CONFIG_SYS_NS16550_COM1,
+#else
+ NULL,
+#endif
+#ifdef CONFIG_SYS_NS16550_COM2
+ (NS16550_t)CONFIG_SYS_NS16550_COM2,
+#else
+ NULL,
+#endif
+#ifdef CONFIG_SYS_NS16550_COM3
+ (NS16550_t)CONFIG_SYS_NS16550_COM3,
+#else
+ NULL,
+#endif
+#ifdef CONFIG_SYS_NS16550_COM4
+ (NS16550_t)CONFIG_SYS_NS16550_COM4
+#else
+ NULL
+#endif
+};
+
+#define PORT serial_ports[port-1]
+
+/* Multi serial device functions */
+#define DECLARE_ESERIAL_FUNCTIONS(port) \
+ int eserial##port##_init (void) {\
+ int clock_divisor; \
+ clock_divisor = calc_divisor(serial_ports[port-1]); \
+ NS16550_init(serial_ports[port-1], clock_divisor); \
+ return(0);}\
+ void eserial##port##_setbrg (void) {\
+ serial_setbrg_dev(port);}\
+ int eserial##port##_getc (void) {\
+ return serial_getc_dev(port);}\
+ int eserial##port##_tstc (void) {\
+ return serial_tstc_dev(port);}\
+ void eserial##port##_putc (const char c) {\
+ serial_putc_dev(port, c);}\
+ void eserial##port##_puts (const char *s) {\
+ serial_puts_dev(port, s);}
+
+/* Serial device descriptor */
+#define INIT_ESERIAL_STRUCTURE(port, __name) { \
+ .name = __name, \
+ .start = eserial##port##_init, \
+ .stop = NULL, \
+ .setbrg = eserial##port##_setbrg, \
+ .getc = eserial##port##_getc, \
+ .tstc = eserial##port##_tstc, \
+ .putc = eserial##port##_putc, \
+ .puts = eserial##port##_puts, \
+}
+
+static int calc_divisor (NS16550_t port)
+{
+#ifdef CONFIG_OMAP1510
+ /* If can't cleanly clock 115200 set div to 1 */
+ if ((CONFIG_SYS_NS16550_CLK == 12000000) && (gd->baudrate == 115200)) {
+ port->osc_12m_sel = OSC_12M_SEL; /* enable 6.5 * divisor */
+ return (1); /* return 1 for base divisor */
+ }
+ port->osc_12m_sel = 0; /* clear if previsouly set */
+#endif
+#ifdef CONFIG_OMAP1610
+ /* If can't cleanly clock 115200 set div to 1 */
+ if ((CONFIG_SYS_NS16550_CLK == 48000000) && (gd->baudrate == 115200)) {
+ return (26); /* return 26 for base divisor */
+ }
+#endif
+
+#ifdef CONFIG_APTIX
+#define MODE_X_DIV 13
+#else
+#define MODE_X_DIV 16
+#endif
+
+ /* Compute divisor value. Normally, we should simply return:
+ * CONFIG_SYS_NS16550_CLK) / MODE_X_DIV / gd->baudrate
+ * but we need to round that value by adding 0.5.
+ * Rounding is especially important at high baud rates.
+ */
+ return (CONFIG_SYS_NS16550_CLK + (gd->baudrate * (MODE_X_DIV / 2))) /
+ (MODE_X_DIV * gd->baudrate);
+}
+
+void
+_serial_putc(const char c,const int port)
+{
+ if (c == '\n')
+ NS16550_putc(PORT, '\r');
+
+ NS16550_putc(PORT, c);
+}
+
+void
+_serial_putc_raw(const char c,const int port)
+{
+ NS16550_putc(PORT, c);
+}
+
+void
+_serial_puts (const char *s,const int port)
+{
+ while (*s) {
+ _serial_putc (*s++,port);
+ }
+}
+
+
+int
+_serial_getc(const int port)
+{
+ return NS16550_getc(PORT);
+}
+
+int
+_serial_tstc(const int port)
+{
+ return NS16550_tstc(PORT);
+}
+
+void
+_serial_setbrg (const int port)
+{
+ int clock_divisor;
+
+ clock_divisor = calc_divisor(PORT);
+ NS16550_reinit(PORT, clock_divisor);
+}
+
+static inline void
+serial_putc_dev(unsigned int dev_index,const char c)
+{
+ _serial_putc(c,dev_index);
+}
+
+static inline void
+serial_putc_raw_dev(unsigned int dev_index,const char c)
+{
+ _serial_putc_raw(c,dev_index);
+}
+
+static inline void
+serial_puts_dev(unsigned int dev_index,const char *s)
+{
+ _serial_puts(s,dev_index);
+}
+
+static inline int
+serial_getc_dev(unsigned int dev_index)
+{
+ return _serial_getc(dev_index);
+}
+
+static inline int
+serial_tstc_dev(unsigned int dev_index)
+{
+ return _serial_tstc(dev_index);
+}
+
+static inline void
+serial_setbrg_dev(unsigned int dev_index)
+{
+ _serial_setbrg(dev_index);
+}
+
+DECLARE_ESERIAL_FUNCTIONS(1);
+struct serial_device eserial1_device =
+ INIT_ESERIAL_STRUCTURE(1, "eserial0");
+DECLARE_ESERIAL_FUNCTIONS(2);
+struct serial_device eserial2_device =
+ INIT_ESERIAL_STRUCTURE(2, "eserial1");
+DECLARE_ESERIAL_FUNCTIONS(3);
+struct serial_device eserial3_device =
+ INIT_ESERIAL_STRUCTURE(3, "eserial2");
+DECLARE_ESERIAL_FUNCTIONS(4);
+struct serial_device eserial4_device =
+ INIT_ESERIAL_STRUCTURE(4, "eserial3");
+
+__weak struct serial_device *default_serial_console(void)
+{
+#if CONFIG_CONS_INDEX == 1
+ return &eserial1_device;
+#elif CONFIG_CONS_INDEX == 2
+ return &eserial2_device;
+#elif CONFIG_CONS_INDEX == 3
+ return &eserial3_device;
+#elif CONFIG_CONS_INDEX == 4
+ return &eserial4_device;
+#else
+#error "Bad CONFIG_CONS_INDEX."
+#endif
+}
+
+void ns16550_serial_initialize(void)
+{
+#if defined(CONFIG_SYS_NS16550_COM1)
+ serial_register(&eserial1_device);
+#endif
+#if defined(CONFIG_SYS_NS16550_COM2)
+ serial_register(&eserial2_device);
+#endif
+#if defined(CONFIG_SYS_NS16550_COM3)
+ serial_register(&eserial3_device);
+#endif
+#if defined(CONFIG_SYS_NS16550_COM4)
+ serial_register(&eserial4_device);
+#endif
+}
#include <common.h>
#include <watchdog.h>
#include <asm/io.h>
+#include <serial.h>
+#include <linux/compiler.h>
#include "serial_pl01x.h"
/*
#ifdef CONFIG_PL010_SERIAL
-int serial_init (void)
+static int pl01x_serial_init(void)
{
struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
unsigned int divisor;
#ifdef CONFIG_PL011_SERIAL
-int serial_init (void)
+static int pl01x_serial_init(void)
{
struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
unsigned int temp;
#endif /* CONFIG_PL011_SERIAL */
-void serial_putc (const char c)
+static void pl01x_serial_putc(const char c)
{
if (c == '\n')
pl01x_putc (CONSOLE_PORT, '\r');
pl01x_putc (CONSOLE_PORT, c);
}
-void serial_puts (const char *s)
-{
- while (*s) {
- serial_putc (*s++);
- }
-}
-
-int serial_getc (void)
+static int pl01x_serial_getc(void)
{
return pl01x_getc (CONSOLE_PORT);
}
-int serial_tstc (void)
+static int pl01x_serial_tstc(void)
{
return pl01x_tstc (CONSOLE_PORT);
}
-void serial_setbrg (void)
+static void pl01x_serial_setbrg(void)
{
struct pl01x_regs *regs = pl01x_get_regs(CONSOLE_PORT);
WATCHDOG_RESET();
return !(readl(®s->fr) & UART_PL01x_FR_RXFE);
}
+
+static struct serial_device pl01x_serial_drv = {
+ .name = "pl01x_serial",
+ .start = pl01x_serial_init,
+ .stop = NULL,
+ .setbrg = pl01x_serial_setbrg,
+ .putc = pl01x_serial_putc,
+ .puts = default_serial_puts,
+ .getc = pl01x_serial_getc,
+ .tstc = pl01x_serial_tstc,
+};
+
+void pl01x_serial_initialize(void)
+{
+ serial_register(&pl01x_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &pl01x_serial_drv;
+}
#include <asm/arch/pxa-regs.h>
#include <asm/arch/regs-uart.h>
#include <asm/io.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
#define HWUART_INDEX 0xff
#endif
-#ifndef CONFIG_SERIAL_MULTI
-#if defined(CONFIG_FFUART)
-#define UART_INDEX FFUART_INDEX
-#elif defined(CONFIG_BTUART)
-#define UART_INDEX BTUART_INDEX
-#elif defined(CONFIG_STUART)
-#define UART_INDEX STUART_INDEX
-#elif defined(CONFIG_HWUART)
-#define UART_INDEX HWUART_INDEX
-#else
-#error "Please select CONFIG_(FF|BT|ST|HW)UART in board config file."
-#endif
-#endif
-
-uint32_t pxa_uart_get_baud_divider(void)
+static uint32_t pxa_uart_get_baud_divider(void)
{
if (gd->baudrate == 1200)
return 768;
return 0;
}
-struct pxa_uart_regs *pxa_uart_index_to_regs(uint32_t uart_index)
+static struct pxa_uart_regs *pxa_uart_index_to_regs(uint32_t uart_index)
{
switch (uart_index) {
case FFUART_INDEX: return (struct pxa_uart_regs *)FFUART_BASE;
}
}
-void pxa_uart_toggle_clock(uint32_t uart_index, int enable)
+static void pxa_uart_toggle_clock(uint32_t uart_index, int enable)
{
uint32_t clk_reg, clk_offset, reg;
#define pxa_uart_desc(uart) \
struct serial_device serial_##uart##_device = \
{ \
- "serial_"#uart, \
- uart##_init, \
- NULL, \
- uart##_setbrg, \
- uart##_getc, \
- uart##_tstc, \
- uart##_putc, \
- uart##_puts, \
+ .name = "serial_"#uart, \
+ .start = uart##_init, \
+ .stop = NULL, \
+ .setbrg = uart##_setbrg, \
+ .getc = uart##_getc, \
+ .tstc = uart##_tstc, \
+ .putc = uart##_putc, \
+ .puts = uart##_puts, \
};
#define pxa_uart_multi(uart, UART) \
pxa_uart_multi(btuart, BTUART)
#endif
-#ifndef CONFIG_SERIAL_MULTI
- pxa_uart(serial, UART)
+__weak struct serial_device *default_serial_console(void)
+{
+#if CONFIG_CONS_INDEX == 1
+ return &serial_hwuart_device;
+#elif CONFIG_CONS_INDEX == 2
+ return &serial_stuart_device;
+#elif CONFIG_CONS_INDEX == 3
+ return &serial_ffuart_device;
+#elif CONFIG_CONS_INDEX == 4
+ return &serial_btuart_device;
+#else
+#error "Bad CONFIG_CONS_INDEX."
#endif
+}
+
+void pxa_serial_initialize(void)
+{
+#if defined(CONFIG_FFUART)
+ serial_register(&serial_ffuart_device);
+#endif
+#if defined(CONFIG_BTUART)
+ serial_register(&serial_btuart_device);
+#endif
+#if defined(CONFIG_STUART)
+ serial_register(&serial_stuart_device);
+#endif
+}
#endif
#include <asm/io.h>
-
-#if defined(CONFIG_SERIAL_MULTI)
#include <serial.h>
/* Multi serial device functions */
serial_puts_dev(port, s); \
}
-#define INIT_S3C_SERIAL_STRUCTURE(port, name) { \
- name, \
- s3serial##port##_init, \
- NULL,\
- s3serial##port##_setbrg, \
- s3serial##port##_getc, \
- s3serial##port##_tstc, \
- s3serial##port##_putc, \
- s3serial##port##_puts, \
+#define INIT_S3C_SERIAL_STRUCTURE(port, __name) { \
+ .name = __name, \
+ .start = s3serial##port##_init, \
+ .stop = NULL, \
+ .setbrg = s3serial##port##_setbrg, \
+ .getc = s3serial##port##_getc, \
+ .tstc = s3serial##port##_tstc, \
+ .putc = s3serial##port##_putc, \
+ .puts = s3serial##port##_puts, \
}
-#endif /* CONFIG_SERIAL_MULTI */
-
#ifdef CONFIG_HWFLOW
static int hwflow;
#endif
/* Delay */ ;
}
-#if defined(CONFIG_SERIAL_MULTI)
static inline void serial_setbrg_dev(unsigned int dev_index)
{
_serial_setbrg(dev_index);
}
-#else
-void serial_setbrg(void)
-{
- _serial_setbrg(UART_NR);
-}
-#endif
-
/* Initialise the serial port. The settings are always 8 data bits, no parity,
* 1 stop bit, no start bits.
return (0);
}
-#if !defined(CONFIG_SERIAL_MULTI)
-/* Initialise the serial port. The settings are always 8 data bits, no parity,
- * 1 stop bit, no start bits.
- */
-int serial_init(void)
-{
- return serial_init_dev(UART_NR);
-}
-#endif
-
/*
* Read a single byte from the serial port. Returns 1 on success, 0
* otherwise. When the function is succesfull, the character read is
return readb(&uart->urxh) & 0xff;
}
-#if defined(CONFIG_SERIAL_MULTI)
static inline int serial_getc_dev(unsigned int dev_index)
{
return _serial_getc(dev_index);
}
-#else
-int serial_getc(void)
-{
- return _serial_getc(UART_NR);
-}
-#endif
#ifdef CONFIG_HWFLOW
int hwflow_onoff(int on)
serial_putc('\r');
}
-#if defined(CONFIG_SERIAL_MULTI)
static inline void serial_putc_dev(unsigned int dev_index, const char c)
{
_serial_putc(c, dev_index);
}
-#else
-void serial_putc(const char c)
-{
- _serial_putc(c, UART_NR);
-}
-#endif
-
/*
* Test whether a character is in the RX buffer
return readl(&uart->utrstat) & 0x1;
}
-#if defined(CONFIG_SERIAL_MULTI)
static inline int serial_tstc_dev(unsigned int dev_index)
{
return _serial_tstc(dev_index);
}
-#else
-int serial_tstc(void)
-{
- return _serial_tstc(UART_NR);
-}
-#endif
void _serial_puts(const char *s, const int dev_index)
{
}
}
-#if defined(CONFIG_SERIAL_MULTI)
static inline void serial_puts_dev(int dev_index, const char *s)
{
_serial_puts(s, dev_index);
}
-#else
-void serial_puts(const char *s)
-{
- _serial_puts(s, UART_NR);
-}
-#endif
-#if defined(CONFIG_SERIAL_MULTI)
DECLARE_S3C_SERIAL_FUNCTIONS(0);
struct serial_device s3c24xx_serial0_device =
INIT_S3C_SERIAL_STRUCTURE(0, "s3ser0");
#error "CONFIG_SERIAL? missing."
#endif
}
-#endif /* CONFIG_SERIAL_MULTI */
+
+void s3c24xx_serial_initialize(void)
+{
+ serial_register(&s3c24xx_serial0_device);
+ serial_register(&s3c24xx_serial1_device);
+ serial_register(&s3c24xx_serial2_device);
+}
}
-void serial_setbrg (void)
+static void s3c44b0_serial_setbrg(void)
{
u32 divisor = 0;
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
-int serial_init (void)
+static int s3c44b0_serial_init(void)
{
serial_setbrg ();
/*
* Output a single byte to the serial port.
*/
-void serial_putc (const char c)
+static void s3c44b0_serial_putc(const char c)
{
/* wait for room in the transmit FIFO */
while(!(UTRSTAT0 & 0x02));
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_tstc (void)
+static int s3c44b0_serial_tstc(void)
{
return (UTRSTAT0 & 0x01);
}
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_getc (void)
+static int s3c44b0_serial_getc(void)
{
int rv;
for(;;) {
- rv = serial_tstc();
+ rv = s3c44b0_serial_tstc();
if(rv > 0)
return URXH0;
}
}
-void
-serial_puts (const char *s)
+static struct serial_device s3c44b0_serial_drv = {
+ .name = "s3c44b0_serial",
+ .start = s3c44b0_serial_init,
+ .stop = NULL,
+ .setbrg = s3c44b0_serial_setbrg,
+ .putc = s3c44b0_serial_putc,
+ .puts = default_serial_puts,
+ .getc = s3c44b0_serial_getc,
+ .tstc = s3c44b0_serial_tstc,
+};
+
+void s3c44b0_serial_initialize(void)
{
- while (*s) {
- serial_putc (*s++);
- }
+ serial_register(&s3c44b0_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &s3c44b0_serial_drv;
}
void s5p_serial##port##_putc(const char c) { serial_putc_dev(c, port); } \
void s5p_serial##port##_puts(const char *s) { serial_puts_dev(s, port); }
-#define INIT_S5P_SERIAL_STRUCTURE(port, name) { \
- name, \
- s5p_serial##port##_init, \
- NULL, \
- s5p_serial##port##_setbrg, \
- s5p_serial##port##_getc, \
- s5p_serial##port##_tstc, \
- s5p_serial##port##_putc, \
- s5p_serial##port##_puts, }
+#define INIT_S5P_SERIAL_STRUCTURE(port, __name) { \
+ .name = __name, \
+ .start = s5p_serial##port##_init, \
+ .stop = NULL, \
+ .setbrg = s5p_serial##port##_setbrg, \
+ .getc = s5p_serial##port##_getc, \
+ .tstc = s5p_serial##port##_tstc, \
+ .putc = s5p_serial##port##_putc, \
+ .puts = s5p_serial##port##_puts, \
+}
DECLARE_S5P_SERIAL_FUNCTIONS(0);
struct serial_device s5p_serial0_device =
#error "CONFIG_SERIAL? missing."
#endif
}
+
+void s5p_serial_initialize(void)
+{
+ serial_register(&s5p_serial0_device);
+ serial_register(&s5p_serial1_device);
+ serial_register(&s5p_serial2_device);
+ serial_register(&s5p_serial3_device);
+}
#include <common.h>
#include <SA-1100.h>
+#include <serial.h>
+#include <linux/compiler.h>
DECLARE_GLOBAL_DATA_PTR;
-void serial_setbrg (void)
+static void sa1100_serial_setbrg(void)
{
unsigned int reg = 0;
* are always 8 data bits, no parity, 1 stop bit, no start bits.
*
*/
-int serial_init (void)
+static int sa1100_serial_init(void)
{
serial_setbrg ();
/*
* Output a single byte to the serial port.
*/
-void serial_putc (const char c)
+static void sa1100_serial_putc(const char c)
{
#ifdef CONFIG_SERIAL1
/* wait for room in the tx FIFO on SERIAL1 */
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_tstc (void)
+static int sa1100_serial_tstc(void)
{
#ifdef CONFIG_SERIAL1
return Ser1UTSR1 & UTSR1_RNE;
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int serial_getc (void)
+static int sa1100_serial_getc(void)
{
#ifdef CONFIG_SERIAL1
while (!(Ser1UTSR1 & UTSR1_RNE));
#endif
}
-void
-serial_puts (const char *s)
+static struct serial_device sa1100_serial_drv = {
+ .name = "sa1100_serial",
+ .start = sa1100_serial_init,
+ .stop = NULL,
+ .setbrg = sa1100_serial_setbrg,
+ .putc = sa1100_serial_putc,
+ .puts = default_serial_puts,
+ .getc = sa1100_serial_getc,
+ .tstc = sa1100_serial_tstc,
+};
+
+void sa1100_serial_initialize(void)
{
- while (*s) {
- serial_putc (*s++);
- }
+ serial_register(&sa1100_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &sa1100_serial_drv;
}
#include <asm/io.h>
#include <asm/processor.h>
#include "serial_sh.h"
+#include <serial.h>
+#include <linux/compiler.h>
#if defined(CONFIG_CONS_SCIF0)
# define SCIF_BASE SCIF0_BASE
.type = SCIF_BASE_PORT,
};
-void serial_setbrg(void)
+static void sh_serial_setbrg(void)
{
DECLARE_GLOBAL_DATA_PTR;
sci_out(&sh_sci, SCBRR, SCBRR_VALUE(gd->baudrate, CONFIG_SYS_CLK_FREQ));
}
-int serial_init(void)
+static int sh_serial_init(void)
{
sci_out(&sh_sci, SCSCR , SCSCR_INIT(&sh_sci));
sci_out(&sh_sci, SCSCR , SCSCR_INIT(&sh_sci));
sci_out(&sh_sci, SCxSR, sci_in(&sh_sci, SCxSR) & ~SCxSR_TEND(&sh_sci));
}
-void serial_putc(const char c)
+static void sh_serial_putc(const char c)
{
if (c == '\n')
serial_raw_putc('\r');
serial_raw_putc(c);
}
-void serial_puts(const char *s)
-{
- char c;
- while ((c = *s++) != 0)
- serial_putc(c);
-}
-
-int serial_tstc(void)
+static int sh_serial_tstc(void)
{
return serial_rx_fifo_level() ? 1 : 0;
}
return status & (SCIF_DR | SCxSR_RDxF(&sh_sci));
}
-int serial_getc(void)
+static int sh_serial_getc(void)
{
unsigned short status;
char ch;
handle_error();
return ch;
}
+
+static struct serial_device sh_serial_drv = {
+ .name = "sh_serial",
+ .start = sh_serial_init,
+ .stop = NULL,
+ .setbrg = sh_serial_setbrg,
+ .putc = sh_serial_putc,
+ .puts = default_serial_puts,
+ .getc = sh_serial_getc,
+ .tstc = sh_serial_tstc,
+};
+
+void sh_serial_initialize(void)
+{
+ serial_register(&sh_serial_drv);
+}
+
+__weak struct serial_device *default_serial_console(void)
+{
+ return &sh_serial_drv;
+}
return -1;
}
-#if !defined(CONFIG_SERIAL_MULTI)
-int serial_init(void)
-{
- return uartlite_serial_init(0);
-}
-
-void serial_setbrg(void)
-{
- /* FIXME: what's this for? */
-}
-
-void serial_putc(const char c)
-{
- uartlite_serial_putc(c, 0);
-}
-
-void serial_puts(const char *s)
-{
- uartlite_serial_puts(s, 0);
-}
-
-int serial_getc(void)
-{
- return uartlite_serial_getc(0);
-}
-
-int serial_tstc(void)
-{
- return uartlite_serial_tstc(0);
-}
-#endif
-
-#if defined(CONFIG_SERIAL_MULTI)
/* Multi serial device functions */
#define DECLARE_ESERIAL_FUNCTIONS(port) \
int userial##port##_init(void) \
{ uartlite_serial_puts(s, port); }
/* Serial device descriptor */
-#define INIT_ESERIAL_STRUCTURE(port, name) {\
- name,\
- userial##port##_init,\
- NULL,\
- userial##port##_setbrg,\
- userial##port##_getc,\
- userial##port##_tstc,\
- userial##port##_putc,\
- userial##port##_puts, }
+#define INIT_ESERIAL_STRUCTURE(port, __name) { \
+ .name = __name, \
+ .start = userial##port##_init, \
+ .stop = NULL, \
+ .setbrg = userial##port##_setbrg, \
+ .getc = userial##port##_getc, \
+ .tstc = userial##port##_tstc, \
+ .putc = userial##port##_putc, \
+ .puts = userial##port##_puts, \
+}
DECLARE_ESERIAL_FUNCTIONS(0);
struct serial_device uartlite_serial0_device =
return NULL;
}
-#endif /* CONFIG_SERIAL_MULTI */
+
+void uartlite_serial_initialize(void)
+{
+#ifdef XILINX_UARTLITE_BASEADDR
+ serial_register(&uartlite_serial0_device);
+#endif /* XILINX_UARTLITE_BASEADDR */
+#ifdef XILINX_UARTLITE_BASEADDR1
+ serial_register(&uartlite_serial1_device);
+#endif /* XILINX_UARTLITE_BASEADDR1 */
+#ifdef XILINX_UARTLITE_BASEADDR2
+ serial_register(&uartlite_serial2_device);
+#endif /* XILINX_UARTLITE_BASEADDR2 */
+#ifdef XILINX_UARTLITE_BASEADDR3
+ serial_register(&uartlite_serial3_device);
+#endif /* XILINX_UARTLITE_BASEADDR3 */
+}
return readl(®s->tx_rx_fifo);
}
-#if !defined(CONFIG_SERIAL_MULTI)
-int serial_init(void)
-{
- return uart_zynq_serial_init(0);
-}
-
-void serial_setbrg(void)
-{
- uart_zynq_serial_setbrg(0);
-}
-
-void serial_putc(const char c)
-{
- uart_zynq_serial_putc(c, 0);
-}
-
-void serial_puts(const char *s)
-{
- uart_zynq_serial_puts(s, 0);
-}
-
-int serial_getc(void)
-{
- return uart_zynq_serial_getc(0);
-}
-
-int serial_tstc(void)
-{
- return uart_zynq_serial_tstc(0);
-}
-#else
/* Multi serial device functions */
#define DECLARE_PSSERIAL_FUNCTIONS(port) \
int uart_zynq##port##_init(void) \
/* Serial device descriptor */
#define INIT_PSSERIAL_STRUCTURE(port, __name) { \
.name = __name, \
- .init = uart_zynq##port##_init, \
- .uninit = NULL, \
+ .start = uart_zynq##port##_init, \
+ .stop = NULL, \
.setbrg = uart_zynq##port##_setbrg, \
.getc = uart_zynq##port##_getc, \
.tstc = uart_zynq##port##_tstc, \
return NULL;
}
+
+void zynq_serial_initalize(void)
+{
+#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR0
+ serial_register(&uart_zynq_serial0_device);
#endif
+#ifdef CONFIG_ZYNQ_SERIAL_BASEADDR1
+ serial_register(&uart_zynq_serial1_device);
+#endif
+}
*/
#include <common.h>
-
#include <malloc.h>
-#include <spi.h>
#include <asm/io.h>
#include <asm/gpio.h>
-#include <asm/arch/clk_rst.h>
#include <asm/arch/clock.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/uart-spi-switch.h>
-#include <asm/arch/tegra_spi.h>
+#include <asm/arch-tegra/clk_rst.h>
+#include <asm/arch-tegra/tegra_spi.h>
+#include <spi.h>
#if defined(CONFIG_SPI_CORRUPTS_UART)
#define corrupt_delay() udelay(CONFIG_SPI_CORRUPTS_UART_DLY);
if (mode == 1)
- printf(" scanning bus for ethernet devices... ");
+ printf(" scanning usb for ethernet devices... ");
old_async = usb_disable_asynch(1); /* asynch transfer not allowed */
COBJS-y += ether.o epautoconf.o config.o usbstring.o
COBJS-$(CONFIG_USB_ETH_RNDIS) += rndis.o
COBJS-$(CONFIG_MV_UDC) += mv_udc.o
+COBJS-$(CONFIG_CPU_PXA25X) += pxa25x_udc.o
else
# Devices not related to the new gadget layer depend on CONFIG_USB_DEVICE
ifdef CONFIG_USB_DEVICE
unsigned packet_received, packet_sent;
-#define DEV_CONFIG_CDC 1
#define GFP_ATOMIC ((gfp_t) 0)
#define GFP_KERNEL ((gfp_t) 0)
/* "main" config is either CDC, or its simple subset */
static inline int is_cdc(struct eth_dev *dev)
{
-#if !defined(DEV_CONFIG_SUBSET)
+#if !defined(CONFIG_USB_ETH_SUBSET)
return 1; /* only cdc possible */
-#elif !defined(DEV_CONFIG_CDC)
+#elif !defined(CONFIG_USB_ETH_CDC)
return 0; /* only subset possible */
#else
return dev->cdc; /* depends on what hardware we found */
* get those drivers from MCCI, or bundled with various products.
*/
-#ifdef DEV_CONFIG_CDC
+#ifdef CONFIG_USB_ETH_CDC
static struct usb_interface_descriptor
control_intf = {
.bLength = sizeof control_intf,
.bcdCDC = __constant_cpu_to_le16(0x0110),
};
-#if defined(DEV_CONFIG_CDC) || defined(CONFIG_USB_ETH_RNDIS)
+#if defined(CONFIG_USB_ETH_CDC) || defined(CONFIG_USB_ETH_RNDIS)
static const struct usb_cdc_union_desc union_desc = {
.bLength = sizeof union_desc,
#endif
-#ifndef DEV_CONFIG_CDC
+#ifndef CONFIG_USB_ETH_CDC
/*
* "SAFE" loosely follows CDC WMC MDLM, violating the spec in various
.bNumberPowerFilters = 0,
};
-#if defined(DEV_CONFIG_CDC) || defined(CONFIG_USB_ETH_RNDIS)
+#if defined(CONFIG_USB_ETH_CDC) || defined(CONFIG_USB_ETH_RNDIS)
/*
* include the status endpoint if we can, even where it's optional.
};
#endif
-#ifdef DEV_CONFIG_CDC
+#ifdef CONFIG_USB_ETH_CDC
/* the default data interface has no endpoints ... */
#endif
-#ifdef DEV_CONFIG_SUBSET
+#ifdef CONFIG_USB_ETH_SUBSET
/*
* "Simple" CDC-subset option is a simple vendor-neutral model that most
static const struct usb_descriptor_header *fs_eth_function[11] = {
(struct usb_descriptor_header *) &otg_descriptor,
-#ifdef DEV_CONFIG_CDC
+#ifdef CONFIG_USB_ETH_CDC
/* "cdc" mode descriptors */
(struct usb_descriptor_header *) &control_intf,
(struct usb_descriptor_header *) &header_desc,
(struct usb_descriptor_header *) &fs_source_desc,
(struct usb_descriptor_header *) &fs_sink_desc,
NULL,
-#endif /* DEV_CONFIG_CDC */
+#endif /* CONFIG_USB_ETH_CDC */
};
static inline void fs_subset_descriptors(void)
{
-#ifdef DEV_CONFIG_SUBSET
+#ifdef CONFIG_USB_ETH_SUBSET
/* behavior is "CDC Subset"; extra descriptors say "SAFE" */
fs_eth_function[1] = (struct usb_descriptor_header *) &subset_data_intf;
fs_eth_function[2] = (struct usb_descriptor_header *) &header_desc;
* descriptors, unless they only run at full speed.
*/
-#if defined(DEV_CONFIG_CDC) || defined(CONFIG_USB_ETH_RNDIS)
+#if defined(CONFIG_USB_ETH_CDC) || defined(CONFIG_USB_ETH_RNDIS)
static struct usb_endpoint_descriptor
hs_status_desc = {
.bLength = USB_DT_ENDPOINT_SIZE,
.wMaxPacketSize = __constant_cpu_to_le16(STATUS_BYTECOUNT),
.bInterval = LOG2_STATUS_INTERVAL_MSEC + 4,
};
-#endif /* DEV_CONFIG_CDC */
+#endif /* CONFIG_USB_ETH_CDC */
static struct usb_endpoint_descriptor
hs_source_desc = {
static const struct usb_descriptor_header *hs_eth_function[11] = {
(struct usb_descriptor_header *) &otg_descriptor,
-#ifdef DEV_CONFIG_CDC
+#ifdef CONFIG_USB_ETH_CDC
/* "cdc" mode descriptors */
(struct usb_descriptor_header *) &control_intf,
(struct usb_descriptor_header *) &header_desc,
(struct usb_descriptor_header *) &hs_source_desc,
(struct usb_descriptor_header *) &hs_sink_desc,
NULL,
-#endif /* DEV_CONFIG_CDC */
+#endif /* CONFIG_USB_ETH_CDC */
};
static inline void hs_subset_descriptors(void)
{
-#ifdef DEV_CONFIG_SUBSET
+#ifdef CONFIG_USB_ETH_SUBSET
/* behavior is "CDC Subset"; extra descriptors say "SAFE" */
hs_eth_function[1] = (struct usb_descriptor_header *) &subset_data_intf;
hs_eth_function[2] = (struct usb_descriptor_header *) &header_desc;
{ STRING_SERIALNUMBER, serial_number, },
{ STRING_DATA, "Ethernet Data", },
{ STRING_ETHADDR, ethaddr, },
-#ifdef DEV_CONFIG_CDC
+#ifdef CONFIG_USB_ETH_CDC
{ STRING_CDC, "CDC Ethernet", },
{ STRING_CONTROL, "CDC Communications Control", },
#endif
-#ifdef DEV_CONFIG_SUBSET
+#ifdef CONFIG_USB_ETH_SUBSET
{ STRING_SUBSET, "CDC Ethernet Subset", },
#endif
#ifdef CONFIG_USB_ETH_RNDIS
/*============================================================================*/
static u8 control_req[USB_BUFSIZ];
+#if defined(CONFIG_USB_ETH_CDC) || defined(CONFIG_USB_ETH_RNDIS)
static u8 status_req[STATUS_BYTECOUNT] __attribute__ ((aligned(4)));
+#endif
/**
int result = 0;
struct usb_gadget *gadget = dev->gadget;
-#if defined(DEV_CONFIG_CDC) || defined(CONFIG_USB_ETH_RNDIS)
+#if defined(CONFIG_USB_ETH_CDC) || defined(CONFIG_USB_ETH_RNDIS)
/* status endpoint used for RNDIS and (optionally) CDC */
if (!subset_active(dev) && dev->status_ep) {
dev->status = ep_desc(gadget, &hs_status_desc,
/*-------------------------------------------------------------------------*/
-#ifdef DEV_CONFIG_CDC
+#ifdef CONFIG_USB_ETH_CDC
/*
* The interrupt endpoint is used in CDC networking models (Ethernet, ATM)
if (gadget_is_pxa(gadget)) {
value = eth_set_config(dev, DEV_CONFIG_VALUE,
GFP_ATOMIC);
+ /*
+ * PXA25x driver use non-CDC ethernet gadget.
+ * But only _CDC and _RNDIS code can signalize
+ * that network is working. So we signalize it
+ * here.
+ */
+ l_ethdev.network_started = 1;
+ debug("USB network up!\n");
goto done_set_intf;
}
-#ifdef DEV_CONFIG_CDC
+#ifdef CONFIG_USB_ETH_CDC
switch (wIndex) {
case 0: /* control/master intf */
if (wValue != 0)
* all non-PXA hardware talks real CDC ...
*/
debug("set_interface ignored!\n");
-#endif /* DEV_CONFIG_CDC */
+#endif /* CONFIG_USB_ETH_CDC */
done_set_intf:
break;
value = min(wLength, (u16) 1);
break;
-#ifdef DEV_CONFIG_CDC
+#ifdef CONFIG_USB_ETH_CDC
case USB_CDC_SET_ETHERNET_PACKET_FILTER:
/*
* see 6.2.30: no data, wIndex = interface,
* case USB_CDC_GET_ETHERNET_STATISTIC:
*/
-#endif /* DEV_CONFIG_CDC */
+#endif /* CONFIG_USB_ETH_CDC */
#ifdef CONFIG_USB_ETH_RNDIS
/*
u8 tmp[7];
/* these flags are only ever cleared; compiler take note */
-#ifndef DEV_CONFIG_CDC
+#ifndef CONFIG_USB_ETH_CDC
cdc = 0;
#endif
#ifndef CONFIG_USB_ETH_RNDIS
goto autoconf_fail;
out_ep->driver_data = out_ep; /* claim */
-#if defined(DEV_CONFIG_CDC) || defined(CONFIG_USB_ETH_RNDIS)
+#if defined(CONFIG_USB_ETH_CDC) || defined(CONFIG_USB_ETH_RNDIS)
/*
* CDC Ethernet control interface doesn't require a status endpoint.
* Since some hosts expect one, try to allocate one anyway.
} else if (rndis) {
error("can't run RNDIS on %s", gadget->name);
return -ENODEV;
-#ifdef DEV_CONFIG_CDC
+#ifdef CONFIG_USB_ETH_CDC
} else if (cdc) {
control_intf.bNumEndpoints = 0;
/* FIXME remove endpoint from descriptor list */
fs_source_desc.bEndpointAddress;
hs_sink_desc.bEndpointAddress =
fs_sink_desc.bEndpointAddress;
-#if defined(DEV_CONFIG_CDC) || defined(CONFIG_USB_ETH_RNDIS)
+#if defined(CONFIG_USB_ETH_CDC) || defined(CONFIG_USB_ETH_RNDIS)
if (status_ep)
hs_status_desc.bEndpointAddress =
fs_status_desc.bEndpointAddress;
dev->req->complete = eth_setup_complete;
/* ... and maybe likewise for status transfer */
-#if defined(DEV_CONFIG_CDC) || defined(CONFIG_USB_ETH_RNDIS)
+#if defined(CONFIG_USB_ETH_CDC) || defined(CONFIG_USB_ETH_RNDIS)
if (dev->status_ep) {
dev->stat_req = usb_ep_alloc_request(dev->status_ep,
GFP_KERNEL);
#define gadget_is_sa1100(g) 0
#endif
-#ifdef CONFIG_USB_GADGET_LH7A40X
-#define gadget_is_lh7a40x(g) (!strcmp("lh7a40x_udc", (g)->name))
-#else
-#define gadget_is_lh7a40x(g) 0
-#endif
-
/* handhelds.org tree (?) */
#ifdef CONFIG_USB_GADGET_MQ11XX
#define gadget_is_mq11xx(g) (!strcmp("mq11xx_udc", (g)->name))
return 0x07;
else if (gadget_is_omap(gadget))
return 0x08;
- else if (gadget_is_lh7a40x(gadget))
- return 0x09;
else if (gadget_is_n9604(gadget))
- return 0x10;
+ return 0x09;
else if (gadget_is_pxa27x(gadget))
- return 0x11;
+ return 0x10;
else if (gadget_is_s3c2410(gadget))
- return 0x12;
+ return 0x11;
else if (gadget_is_at91(gadget))
- return 0x13;
+ return 0x12;
else if (gadget_is_imx(gadget))
- return 0x14;
+ return 0x13;
else if (gadget_is_musbhsfc(gadget))
- return 0x15;
+ return 0x14;
else if (gadget_is_musbhdrc(gadget))
- return 0x16;
+ return 0x15;
else if (gadget_is_mpc8272(gadget))
- return 0x17;
+ return 0x16;
else if (gadget_is_atmel_usba(gadget))
- return 0x18;
+ return 0x17;
else if (gadget_is_fsl_usb2(gadget))
- return 0x19;
+ return 0x18;
else if (gadget_is_amd5536udc(gadget))
- return 0x20;
+ return 0x19;
else if (gadget_is_m66592(gadget))
- return 0x21;
+ return 0x20;
else if (gadget_is_mv(gadget))
- return 0x22;
+ return 0x21;
return -ENOENT;
}
--- /dev/null
+/*
+ * Intel PXA25x and IXP4xx on-chip full speed USB device controllers
+ *
+ * Copyright (C) 2002 Intrinsyc, Inc. (Frank Becker)
+ * Copyright (C) 2003 Robert Schwebel, Pengutronix
+ * Copyright (C) 2003 Benedikt Spranger, Pengutronix
+ * Copyright (C) 2003 David Brownell
+ * Copyright (C) 2003 Joshua Wise
+ * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * MODULE_AUTHOR("Frank Becker, Robert Schwebel, David Brownell");
+ */
+
+#define CONFIG_USB_PXA25X_SMALL
+#define DRIVER_NAME "pxa25x_udc_linux"
+#define ARCH_HAS_PREFETCH
+
+#include <common.h>
+#include <errno.h>
+#include <asm/byteorder.h>
+#include <asm/system.h>
+#include <asm/mach-types.h>
+#include <asm/unaligned.h>
+#include <linux/compat.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/arch/pxa.h>
+
+#include <usbdescriptors.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <usb/lin_gadget_compat.h>
+#include <asm/arch/pxa-regs.h>
+
+#include "pxa25x_udc.h"
+
+/*
+ * This driver handles the USB Device Controller (UDC) in Intel's PXA 25x
+ * series processors. The UDC for the IXP 4xx series is very similar.
+ * There are fifteen endpoints, in addition to ep0.
+ *
+ * Such controller drivers work with a gadget driver. The gadget driver
+ * returns descriptors, implements configuration and data protocols used
+ * by the host to interact with this device, and allocates endpoints to
+ * the different protocol interfaces. The controller driver virtualizes
+ * usb hardware so that the gadget drivers will be more portable.
+ *
+ * This UDC hardware wants to implement a bit too much USB protocol, so
+ * it constrains the sorts of USB configuration change events that work.
+ * The errata for these chips are misleading; some "fixed" bugs from
+ * pxa250 a0/a1 b0/b1/b2 sure act like they're still there.
+ *
+ * Note that the UDC hardware supports DMA (except on IXP) but that's
+ * not used here. IN-DMA (to host) is simple enough, when the data is
+ * suitably aligned (16 bytes) ... the network stack doesn't do that,
+ * other software can. OUT-DMA is buggy in most chip versions, as well
+ * as poorly designed (data toggle not automatic). So this driver won't
+ * bother using DMA. (Mostly-working IN-DMA support was available in
+ * kernels before 2.6.23, but was never enabled or well tested.)
+ */
+
+#define DRIVER_VERSION "18-August-2012"
+#define DRIVER_DESC "PXA 25x USB Device Controller driver"
+
+static const char driver_name[] = "pxa25x_udc";
+static const char ep0name[] = "ep0";
+
+/* Watchdog */
+static inline void start_watchdog(struct pxa25x_udc *udc)
+{
+ debug("Started watchdog\n");
+ udc->watchdog.base = get_timer(0);
+ udc->watchdog.running = 1;
+}
+
+static inline void stop_watchdog(struct pxa25x_udc *udc)
+{
+ udc->watchdog.running = 0;
+ debug("Stopped watchdog\n");
+}
+
+static inline void test_watchdog(struct pxa25x_udc *udc)
+{
+ if (!udc->watchdog.running)
+ return;
+
+ debug("watchdog %ld %ld\n", get_timer(udc->watchdog.base),
+ udc->watchdog.period);
+
+ if (get_timer(udc->watchdog.base) >= udc->watchdog.period) {
+ stop_watchdog(udc);
+ udc->watchdog.function(udc);
+ }
+}
+
+static void udc_watchdog(struct pxa25x_udc *dev)
+{
+ uint32_t udccs0 = readl(&dev->regs->udccs[0]);
+
+ debug("Fired up udc_watchdog\n");
+
+ local_irq_disable();
+ if (dev->ep0state == EP0_STALL
+ && (udccs0 & UDCCS0_FST) == 0
+ && (udccs0 & UDCCS0_SST) == 0) {
+ writel(UDCCS0_FST|UDCCS0_FTF, &dev->regs->udccs[0]);
+ debug("ep0 re-stall\n");
+ start_watchdog(dev);
+ }
+ local_irq_enable();
+}
+
+#ifdef DEBUG
+
+static const char * const state_name[] = {
+ "EP0_IDLE",
+ "EP0_IN_DATA_PHASE", "EP0_OUT_DATA_PHASE",
+ "EP0_END_XFER", "EP0_STALL"
+};
+
+static void
+dump_udccr(const char *label)
+{
+ u32 udccr = readl(&UDC_REGS->udccr);
+ debug("%s %02X =%s%s%s%s%s%s%s%s\n",
+ label, udccr,
+ (udccr & UDCCR_REM) ? " rem" : "",
+ (udccr & UDCCR_RSTIR) ? " rstir" : "",
+ (udccr & UDCCR_SRM) ? " srm" : "",
+ (udccr & UDCCR_SUSIR) ? " susir" : "",
+ (udccr & UDCCR_RESIR) ? " resir" : "",
+ (udccr & UDCCR_RSM) ? " rsm" : "",
+ (udccr & UDCCR_UDA) ? " uda" : "",
+ (udccr & UDCCR_UDE) ? " ude" : "");
+}
+
+static void
+dump_udccs0(const char *label)
+{
+ u32 udccs0 = readl(&UDC_REGS->udccs[0]);
+
+ debug("%s %s %02X =%s%s%s%s%s%s%s%s\n",
+ label, state_name[the_controller->ep0state], udccs0,
+ (udccs0 & UDCCS0_SA) ? " sa" : "",
+ (udccs0 & UDCCS0_RNE) ? " rne" : "",
+ (udccs0 & UDCCS0_FST) ? " fst" : "",
+ (udccs0 & UDCCS0_SST) ? " sst" : "",
+ (udccs0 & UDCCS0_DRWF) ? " dwrf" : "",
+ (udccs0 & UDCCS0_FTF) ? " ftf" : "",
+ (udccs0 & UDCCS0_IPR) ? " ipr" : "",
+ (udccs0 & UDCCS0_OPR) ? " opr" : "");
+}
+
+static void
+dump_state(struct pxa25x_udc *dev)
+{
+ u32 tmp;
+ unsigned i;
+
+ debug("%s, uicr %02X.%02X, usir %02X.%02x, ufnr %02X.%02X\n",
+ state_name[dev->ep0state],
+ readl(&UDC_REGS->uicr1), readl(&UDC_REGS->uicr0),
+ readl(&UDC_REGS->usir1), readl(&UDC_REGS->usir0),
+ readl(&UDC_REGS->ufnrh), readl(&UDC_REGS->ufnrl));
+ dump_udccr("udccr");
+ if (dev->has_cfr) {
+ tmp = readl(&UDC_REGS->udccfr);
+ debug("udccfr %02X =%s%s\n", tmp,
+ (tmp & UDCCFR_AREN) ? " aren" : "",
+ (tmp & UDCCFR_ACM) ? " acm" : "");
+ }
+
+ if (!dev->driver) {
+ debug("no gadget driver bound\n");
+ return;
+ } else
+ debug("ep0 driver '%s'\n", "ether");
+
+ dump_udccs0("udccs0");
+ debug("ep0 IN %lu/%lu, OUT %lu/%lu\n",
+ dev->stats.write.bytes, dev->stats.write.ops,
+ dev->stats.read.bytes, dev->stats.read.ops);
+
+ for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++) {
+ if (dev->ep[i].desc == NULL)
+ continue;
+ debug("udccs%d = %02x\n", i, *dev->ep->reg_udccs);
+ }
+}
+
+#else /* DEBUG */
+
+static inline void dump_udccr(const char *label) { }
+static inline void dump_udccs0(const char *label) { }
+static inline void dump_state(struct pxa25x_udc *dev) { }
+
+#endif /* DEBUG */
+
+/*
+ * ---------------------------------------------------------------------------
+ * endpoint related parts of the api to the usb controller hardware,
+ * used by gadget driver; and the inner talker-to-hardware core.
+ * ---------------------------------------------------------------------------
+ */
+
+static void pxa25x_ep_fifo_flush(struct usb_ep *ep);
+static void nuke(struct pxa25x_ep *, int status);
+
+/* one GPIO should control a D+ pullup, so host sees this device (or not) */
+static void pullup_off(void)
+{
+ struct pxa2xx_udc_mach_info *mach = the_controller->mach;
+
+ if (mach->udc_command)
+ mach->udc_command(PXA2XX_UDC_CMD_DISCONNECT);
+}
+
+static void pullup_on(void)
+{
+ struct pxa2xx_udc_mach_info *mach = the_controller->mach;
+
+ if (mach->udc_command)
+ mach->udc_command(PXA2XX_UDC_CMD_CONNECT);
+}
+
+static void pio_irq_enable(int bEndpointAddress)
+{
+ bEndpointAddress &= 0xf;
+ if (bEndpointAddress < 8) {
+ clrbits_le32(&the_controller->regs->uicr0,
+ 1 << bEndpointAddress);
+ } else {
+ bEndpointAddress -= 8;
+ clrbits_le32(&the_controller->regs->uicr1,
+ 1 << bEndpointAddress);
+ }
+}
+
+static void pio_irq_disable(int bEndpointAddress)
+{
+ bEndpointAddress &= 0xf;
+ if (bEndpointAddress < 8) {
+ setbits_le32(&the_controller->regs->uicr0,
+ 1 << bEndpointAddress);
+ } else {
+ bEndpointAddress -= 8;
+ setbits_le32(&the_controller->regs->uicr1,
+ 1 << bEndpointAddress);
+ }
+}
+
+static inline void udc_set_mask_UDCCR(int mask)
+{
+ /*
+ * The UDCCR reg contains mask and interrupt status bits,
+ * so using '|=' isn't safe as it may ack an interrupt.
+ */
+ const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
+
+ mask &= mask_bits;
+ clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask);
+}
+
+static inline void udc_clear_mask_UDCCR(int mask)
+{
+ const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
+
+ mask = ~mask & mask_bits;
+ clrbits_le32(&the_controller->regs->udccr, ~mask);
+}
+
+static inline void udc_ack_int_UDCCR(int mask)
+{
+ const uint32_t mask_bits = UDCCR_REM | UDCCR_SRM | UDCCR_UDE;
+
+ mask &= ~mask_bits;
+ clrsetbits_le32(&the_controller->regs->udccr, ~mask_bits, mask);
+}
+
+/*
+ * endpoint enable/disable
+ *
+ * we need to verify the descriptors used to enable endpoints. since pxa25x
+ * endpoint configurations are fixed, and are pretty much always enabled,
+ * there's not a lot to manage here.
+ *
+ * because pxa25x can't selectively initialize bulk (or interrupt) endpoints,
+ * (resetting endpoint halt and toggle), SET_INTERFACE is unusable except
+ * for a single interface (with only the default altsetting) and for gadget
+ * drivers that don't halt endpoints (not reset by set_interface). that also
+ * means that if you use ISO, you must violate the USB spec rule that all
+ * iso endpoints must be in non-default altsettings.
+ */
+static int pxa25x_ep_enable(struct usb_ep *_ep,
+ const struct usb_endpoint_descriptor *desc)
+{
+ struct pxa25x_ep *ep;
+ struct pxa25x_udc *dev;
+
+ ep = container_of(_ep, struct pxa25x_ep, ep);
+ if (!_ep || !desc || ep->desc || _ep->name == ep0name
+ || desc->bDescriptorType != USB_DT_ENDPOINT
+ || ep->bEndpointAddress != desc->bEndpointAddress
+ || ep->fifo_size < le16_to_cpu(desc->wMaxPacketSize)) {
+ printf("%s, bad ep or descriptor\n", __func__);
+ return -EINVAL;
+ }
+
+ /* xfer types must match, except that interrupt ~= bulk */
+ if (ep->bmAttributes != desc->bmAttributes
+ && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
+ && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
+ printf("%s, %s type mismatch\n", __func__, _ep->name);
+ return -EINVAL;
+ }
+
+ /* hardware _could_ do smaller, but driver doesn't */
+ if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
+ && le16_to_cpu(desc->wMaxPacketSize)
+ != BULK_FIFO_SIZE)
+ || !desc->wMaxPacketSize) {
+ printf("%s, bad %s maxpacket\n", __func__, _ep->name);
+ return -ERANGE;
+ }
+
+ dev = ep->dev;
+ if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
+ printf("%s, bogus device state\n", __func__);
+ return -ESHUTDOWN;
+ }
+
+ ep->desc = desc;
+ ep->stopped = 0;
+ ep->pio_irqs = 0;
+ ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
+
+ /* flush fifo (mostly for OUT buffers) */
+ pxa25x_ep_fifo_flush(_ep);
+
+ /* ... reset halt state too, if we could ... */
+
+ debug("enabled %s\n", _ep->name);
+ return 0;
+}
+
+static int pxa25x_ep_disable(struct usb_ep *_ep)
+{
+ struct pxa25x_ep *ep;
+ unsigned long flags;
+
+ ep = container_of(_ep, struct pxa25x_ep, ep);
+ if (!_ep || !ep->desc) {
+ printf("%s, %s not enabled\n", __func__,
+ _ep ? ep->ep.name : NULL);
+ return -EINVAL;
+ }
+ local_irq_save(flags);
+
+ nuke(ep, -ESHUTDOWN);
+
+ /* flush fifo (mostly for IN buffers) */
+ pxa25x_ep_fifo_flush(_ep);
+
+ ep->desc = NULL;
+ ep->stopped = 1;
+
+ local_irq_restore(flags);
+ debug("%s disabled\n", _ep->name);
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * for the pxa25x, these can just wrap kmalloc/kfree. gadget drivers
+ * must still pass correctly initialized endpoints, since other controller
+ * drivers may care about how it's currently set up (dma issues etc).
+ */
+
+/*
+ * pxa25x_ep_alloc_request - allocate a request data structure
+ */
+static struct usb_request *
+pxa25x_ep_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
+{
+ struct pxa25x_request *req;
+
+ req = kzalloc(sizeof(*req), gfp_flags);
+ if (!req)
+ return NULL;
+
+ INIT_LIST_HEAD(&req->queue);
+ return &req->req;
+}
+
+
+/*
+ * pxa25x_ep_free_request - deallocate a request data structure
+ */
+static void
+pxa25x_ep_free_request(struct usb_ep *_ep, struct usb_request *_req)
+{
+ struct pxa25x_request *req;
+
+ req = container_of(_req, struct pxa25x_request, req);
+ WARN_ON(!list_empty(&req->queue));
+ kfree(req);
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * done - retire a request; caller blocked irqs
+ */
+static void done(struct pxa25x_ep *ep, struct pxa25x_request *req, int status)
+{
+ unsigned stopped = ep->stopped;
+
+ list_del_init(&req->queue);
+
+ if (likely(req->req.status == -EINPROGRESS))
+ req->req.status = status;
+ else
+ status = req->req.status;
+
+ if (status && status != -ESHUTDOWN)
+ debug("complete %s req %p stat %d len %u/%u\n",
+ ep->ep.name, &req->req, status,
+ req->req.actual, req->req.length);
+
+ /* don't modify queue heads during completion callback */
+ ep->stopped = 1;
+ req->req.complete(&ep->ep, &req->req);
+ ep->stopped = stopped;
+}
+
+
+static inline void ep0_idle(struct pxa25x_udc *dev)
+{
+ dev->ep0state = EP0_IDLE;
+}
+
+static int
+write_packet(u32 *uddr, struct pxa25x_request *req, unsigned max)
+{
+ u8 *buf;
+ unsigned length, count;
+
+ debug("%s(): uddr %p\n", __func__, uddr);
+
+ buf = req->req.buf + req->req.actual;
+ prefetch(buf);
+
+ /* how big will this packet be? */
+ length = min(req->req.length - req->req.actual, max);
+ req->req.actual += length;
+
+ count = length;
+ while (likely(count--))
+ writeb(*buf++, uddr);
+
+ return length;
+}
+
+/*
+ * write to an IN endpoint fifo, as many packets as possible.
+ * irqs will use this to write the rest later.
+ * caller guarantees at least one packet buffer is ready (or a zlp).
+ */
+static int
+write_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
+{
+ unsigned max;
+
+ max = le16_to_cpu(ep->desc->wMaxPacketSize);
+ do {
+ unsigned count;
+ int is_last, is_short;
+
+ count = write_packet(ep->reg_uddr, req, max);
+
+ /* last packet is usually short (or a zlp) */
+ if (unlikely(count != max))
+ is_last = is_short = 1;
+ else {
+ if (likely(req->req.length != req->req.actual)
+ || req->req.zero)
+ is_last = 0;
+ else
+ is_last = 1;
+ /* interrupt/iso maxpacket may not fill the fifo */
+ is_short = unlikely(max < ep->fifo_size);
+ }
+
+ debug_cond(NOISY, "wrote %s %d bytes%s%s %d left %p\n",
+ ep->ep.name, count,
+ is_last ? "/L" : "", is_short ? "/S" : "",
+ req->req.length - req->req.actual, req);
+
+ /*
+ * let loose that packet. maybe try writing another one,
+ * double buffering might work. TSP, TPC, and TFS
+ * bit values are the same for all normal IN endpoints.
+ */
+ writel(UDCCS_BI_TPC, ep->reg_udccs);
+ if (is_short)
+ writel(UDCCS_BI_TSP, ep->reg_udccs);
+
+ /* requests complete when all IN data is in the FIFO */
+ if (is_last) {
+ done(ep, req, 0);
+ if (list_empty(&ep->queue))
+ pio_irq_disable(ep->bEndpointAddress);
+ return 1;
+ }
+
+ /*
+ * TODO experiment: how robust can fifo mode tweaking be?
+ * double buffering is off in the default fifo mode, which
+ * prevents TFS from being set here.
+ */
+
+ } while (readl(ep->reg_udccs) & UDCCS_BI_TFS);
+ return 0;
+}
+
+/*
+ * caller asserts req->pending (ep0 irq status nyet cleared); starts
+ * ep0 data stage. these chips want very simple state transitions.
+ */
+static inline
+void ep0start(struct pxa25x_udc *dev, u32 flags, const char *tag)
+{
+ writel(flags|UDCCS0_SA|UDCCS0_OPR, &dev->regs->udccs[0]);
+ writel(USIR0_IR0, &dev->regs->usir0);
+ dev->req_pending = 0;
+ debug_cond(NOISY, "%s() %s, udccs0: %02x/%02x usir: %X.%X\n",
+ __func__, tag, readl(&dev->regs->udccs[0]), flags,
+ readl(&dev->regs->usir1), readl(&dev->regs->usir0));
+}
+
+static int
+write_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
+{
+ unsigned count;
+ int is_short;
+
+ count = write_packet(&ep->dev->regs->uddr0, req, EP0_FIFO_SIZE);
+ ep->dev->stats.write.bytes += count;
+
+ /* last packet "must be" short (or a zlp) */
+ is_short = (count != EP0_FIFO_SIZE);
+
+ debug_cond(NOISY, "ep0in %d bytes %d left %p\n", count,
+ req->req.length - req->req.actual, req);
+
+ if (unlikely(is_short)) {
+ if (ep->dev->req_pending)
+ ep0start(ep->dev, UDCCS0_IPR, "short IN");
+ else
+ writel(UDCCS0_IPR, &ep->dev->regs->udccs[0]);
+
+ count = req->req.length;
+ done(ep, req, 0);
+ ep0_idle(ep->dev);
+
+ /*
+ * This seems to get rid of lost status irqs in some cases:
+ * host responds quickly, or next request involves config
+ * change automagic, or should have been hidden, or ...
+ *
+ * FIXME get rid of all udelays possible...
+ */
+ if (count >= EP0_FIFO_SIZE) {
+ count = 100;
+ do {
+ if ((readl(&ep->dev->regs->udccs[0]) &
+ UDCCS0_OPR) != 0) {
+ /* clear OPR, generate ack */
+ writel(UDCCS0_OPR,
+ &ep->dev->regs->udccs[0]);
+ break;
+ }
+ count--;
+ udelay(1);
+ } while (count);
+ }
+ } else if (ep->dev->req_pending)
+ ep0start(ep->dev, 0, "IN");
+
+ return is_short;
+}
+
+
+/*
+ * read_fifo - unload packet(s) from the fifo we use for usb OUT
+ * transfers and put them into the request. caller should have made
+ * sure there's at least one packet ready.
+ *
+ * returns true if the request completed because of short packet or the
+ * request buffer having filled (and maybe overran till end-of-packet).
+ */
+static int
+read_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
+{
+ u32 udccs;
+ u8 *buf;
+ unsigned bufferspace, count, is_short;
+
+ for (;;) {
+ /*
+ * make sure there's a packet in the FIFO.
+ * UDCCS_{BO,IO}_RPC are all the same bit value.
+ * UDCCS_{BO,IO}_RNE are all the same bit value.
+ */
+ udccs = readl(ep->reg_udccs);
+ if (unlikely((udccs & UDCCS_BO_RPC) == 0))
+ break;
+ buf = req->req.buf + req->req.actual;
+ prefetchw(buf);
+ bufferspace = req->req.length - req->req.actual;
+
+ /* read all bytes from this packet */
+ if (likely(udccs & UDCCS_BO_RNE)) {
+ count = 1 + (0x0ff & readl(ep->reg_ubcr));
+ req->req.actual += min(count, bufferspace);
+ } else /* zlp */
+ count = 0;
+ is_short = (count < ep->ep.maxpacket);
+ debug_cond(NOISY, "read %s %02x, %d bytes%s req %p %d/%d\n",
+ ep->ep.name, udccs, count,
+ is_short ? "/S" : "",
+ req, req->req.actual, req->req.length);
+ while (likely(count-- != 0)) {
+ u8 byte = readb(ep->reg_uddr);
+
+ if (unlikely(bufferspace == 0)) {
+ /*
+ * this happens when the driver's buffer
+ * is smaller than what the host sent.
+ * discard the extra data.
+ */
+ if (req->req.status != -EOVERFLOW)
+ printf("%s overflow %d\n",
+ ep->ep.name, count);
+ req->req.status = -EOVERFLOW;
+ } else {
+ *buf++ = byte;
+ bufferspace--;
+ }
+ }
+ writel(UDCCS_BO_RPC, ep->reg_udccs);
+ /* RPC/RSP/RNE could now reflect the other packet buffer */
+
+ /* iso is one request per packet */
+ if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
+ if (udccs & UDCCS_IO_ROF)
+ req->req.status = -EHOSTUNREACH;
+ /* more like "is_done" */
+ is_short = 1;
+ }
+
+ /* completion */
+ if (is_short || req->req.actual == req->req.length) {
+ done(ep, req, 0);
+ if (list_empty(&ep->queue))
+ pio_irq_disable(ep->bEndpointAddress);
+ return 1;
+ }
+
+ /* finished that packet. the next one may be waiting... */
+ }
+ return 0;
+}
+
+/*
+ * special ep0 version of the above. no UBCR0 or double buffering; status
+ * handshaking is magic. most device protocols don't need control-OUT.
+ * CDC vendor commands (and RNDIS), mass storage CB/CBI, and some other
+ * protocols do use them.
+ */
+static int
+read_ep0_fifo(struct pxa25x_ep *ep, struct pxa25x_request *req)
+{
+ u8 *buf, byte;
+ unsigned bufferspace;
+
+ buf = req->req.buf + req->req.actual;
+ bufferspace = req->req.length - req->req.actual;
+
+ while (readl(&ep->dev->regs->udccs[0]) & UDCCS0_RNE) {
+ byte = (u8)readb(&ep->dev->regs->uddr0);
+
+ if (unlikely(bufferspace == 0)) {
+ /*
+ * this happens when the driver's buffer
+ * is smaller than what the host sent.
+ * discard the extra data.
+ */
+ if (req->req.status != -EOVERFLOW)
+ printf("%s overflow\n", ep->ep.name);
+ req->req.status = -EOVERFLOW;
+ } else {
+ *buf++ = byte;
+ req->req.actual++;
+ bufferspace--;
+ }
+ }
+
+ writel(UDCCS0_OPR | UDCCS0_IPR, &ep->dev->regs->udccs[0]);
+
+ /* completion */
+ if (req->req.actual >= req->req.length)
+ return 1;
+
+ /* finished that packet. the next one may be waiting... */
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static int
+pxa25x_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
+{
+ struct pxa25x_request *req;
+ struct pxa25x_ep *ep;
+ struct pxa25x_udc *dev;
+ unsigned long flags;
+
+ req = container_of(_req, struct pxa25x_request, req);
+ if (unlikely(!_req || !_req->complete || !_req->buf
+ || !list_empty(&req->queue))) {
+ printf("%s, bad params\n", __func__);
+ return -EINVAL;
+ }
+
+ ep = container_of(_ep, struct pxa25x_ep, ep);
+ if (unlikely(!_ep || (!ep->desc && ep->ep.name != ep0name))) {
+ printf("%s, bad ep\n", __func__);
+ return -EINVAL;
+ }
+
+ dev = ep->dev;
+ if (unlikely(!dev->driver
+ || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
+ printf("%s, bogus device state\n", __func__);
+ return -ESHUTDOWN;
+ }
+
+ /*
+ * iso is always one packet per request, that's the only way
+ * we can report per-packet status. that also helps with dma.
+ */
+ if (unlikely(ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
+ && req->req.length >
+ le16_to_cpu(ep->desc->wMaxPacketSize)))
+ return -EMSGSIZE;
+
+ debug_cond(NOISY, "%s queue req %p, len %d buf %p\n",
+ _ep->name, _req, _req->length, _req->buf);
+
+ local_irq_save(flags);
+
+ _req->status = -EINPROGRESS;
+ _req->actual = 0;
+
+ /* kickstart this i/o queue? */
+ if (list_empty(&ep->queue) && !ep->stopped) {
+ if (ep->desc == NULL/* ep0 */) {
+ unsigned length = _req->length;
+
+ switch (dev->ep0state) {
+ case EP0_IN_DATA_PHASE:
+ dev->stats.write.ops++;
+ if (write_ep0_fifo(ep, req))
+ req = NULL;
+ break;
+
+ case EP0_OUT_DATA_PHASE:
+ dev->stats.read.ops++;
+ /* messy ... */
+ if (dev->req_config) {
+ debug("ep0 config ack%s\n",
+ dev->has_cfr ? "" : " raced");
+ if (dev->has_cfr)
+ writel(UDCCFR_AREN|UDCCFR_ACM
+ |UDCCFR_MB1,
+ &ep->dev->regs->udccfr);
+ done(ep, req, 0);
+ dev->ep0state = EP0_END_XFER;
+ local_irq_restore(flags);
+ return 0;
+ }
+ if (dev->req_pending)
+ ep0start(dev, UDCCS0_IPR, "OUT");
+ if (length == 0 ||
+ ((readl(
+ &ep->dev->regs->udccs[0])
+ & UDCCS0_RNE) != 0
+ && read_ep0_fifo(ep, req))) {
+ ep0_idle(dev);
+ done(ep, req, 0);
+ req = NULL;
+ }
+ break;
+
+ default:
+ printf("ep0 i/o, odd state %d\n",
+ dev->ep0state);
+ local_irq_restore(flags);
+ return -EL2HLT;
+ }
+ /* can the FIFO can satisfy the request immediately? */
+ } else if ((ep->bEndpointAddress & USB_DIR_IN) != 0) {
+ if ((readl(ep->reg_udccs) & UDCCS_BI_TFS) != 0
+ && write_fifo(ep, req))
+ req = NULL;
+ } else if ((readl(ep->reg_udccs) & UDCCS_BO_RFS) != 0
+ && read_fifo(ep, req)) {
+ req = NULL;
+ }
+
+ if (likely(req && ep->desc))
+ pio_irq_enable(ep->bEndpointAddress);
+ }
+
+ /* pio or dma irq handler advances the queue. */
+ if (likely(req != NULL))
+ list_add_tail(&req->queue, &ep->queue);
+ local_irq_restore(flags);
+
+ return 0;
+}
+
+
+/*
+ * nuke - dequeue ALL requests
+ */
+static void nuke(struct pxa25x_ep *ep, int status)
+{
+ struct pxa25x_request *req;
+
+ /* called with irqs blocked */
+ while (!list_empty(&ep->queue)) {
+ req = list_entry(ep->queue.next,
+ struct pxa25x_request,
+ queue);
+ done(ep, req, status);
+ }
+ if (ep->desc)
+ pio_irq_disable(ep->bEndpointAddress);
+}
+
+
+/* dequeue JUST ONE request */
+static int pxa25x_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
+{
+ struct pxa25x_ep *ep;
+ struct pxa25x_request *req;
+ unsigned long flags;
+
+ ep = container_of(_ep, struct pxa25x_ep, ep);
+ if (!_ep || ep->ep.name == ep0name)
+ return -EINVAL;
+
+ local_irq_save(flags);
+
+ /* make sure it's actually queued on this endpoint */
+ list_for_each_entry(req, &ep->queue, queue) {
+ if (&req->req == _req)
+ break;
+ }
+ if (&req->req != _req) {
+ local_irq_restore(flags);
+ return -EINVAL;
+ }
+
+ done(ep, req, -ECONNRESET);
+
+ local_irq_restore(flags);
+ return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+static int pxa25x_ep_set_halt(struct usb_ep *_ep, int value)
+{
+ struct pxa25x_ep *ep;
+ unsigned long flags;
+
+ ep = container_of(_ep, struct pxa25x_ep, ep);
+ if (unlikely(!_ep
+ || (!ep->desc && ep->ep.name != ep0name))
+ || ep->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
+ printf("%s, bad ep\n", __func__);
+ return -EINVAL;
+ }
+ if (value == 0) {
+ /*
+ * this path (reset toggle+halt) is needed to implement
+ * SET_INTERFACE on normal hardware. but it can't be
+ * done from software on the PXA UDC, and the hardware
+ * forgets to do it as part of SET_INTERFACE automagic.
+ */
+ printf("only host can clear %s halt\n", _ep->name);
+ return -EROFS;
+ }
+
+ local_irq_save(flags);
+
+ if ((ep->bEndpointAddress & USB_DIR_IN) != 0
+ && ((readl(ep->reg_udccs) & UDCCS_BI_TFS) == 0
+ || !list_empty(&ep->queue))) {
+ local_irq_restore(flags);
+ return -EAGAIN;
+ }
+
+ /* FST bit is the same for control, bulk in, bulk out, interrupt in */
+ writel(UDCCS_BI_FST|UDCCS_BI_FTF, ep->reg_udccs);
+
+ /* ep0 needs special care */
+ if (!ep->desc) {
+ start_watchdog(ep->dev);
+ ep->dev->req_pending = 0;
+ ep->dev->ep0state = EP0_STALL;
+
+ /* and bulk/intr endpoints like dropping stalls too */
+ } else {
+ unsigned i;
+ for (i = 0; i < 1000; i += 20) {
+ if (readl(ep->reg_udccs) & UDCCS_BI_SST)
+ break;
+ udelay(20);
+ }
+ }
+ local_irq_restore(flags);
+
+ debug("%s halt\n", _ep->name);
+ return 0;
+}
+
+static int pxa25x_ep_fifo_status(struct usb_ep *_ep)
+{
+ struct pxa25x_ep *ep;
+
+ ep = container_of(_ep, struct pxa25x_ep, ep);
+ if (!_ep) {
+ printf("%s, bad ep\n", __func__);
+ return -ENODEV;
+ }
+ /* pxa can't report unclaimed bytes from IN fifos */
+ if ((ep->bEndpointAddress & USB_DIR_IN) != 0)
+ return -EOPNOTSUPP;
+ if (ep->dev->gadget.speed == USB_SPEED_UNKNOWN
+ || (readl(ep->reg_udccs) & UDCCS_BO_RFS) == 0)
+ return 0;
+ else
+ return (readl(ep->reg_ubcr) & 0xfff) + 1;
+}
+
+static void pxa25x_ep_fifo_flush(struct usb_ep *_ep)
+{
+ struct pxa25x_ep *ep;
+
+ ep = container_of(_ep, struct pxa25x_ep, ep);
+ if (!_ep || ep->ep.name == ep0name || !list_empty(&ep->queue)) {
+ printf("%s, bad ep\n", __func__);
+ return;
+ }
+
+ /* toggle and halt bits stay unchanged */
+
+ /* for OUT, just read and discard the FIFO contents. */
+ if ((ep->bEndpointAddress & USB_DIR_IN) == 0) {
+ while (((readl(ep->reg_udccs)) & UDCCS_BO_RNE) != 0)
+ (void)readb(ep->reg_uddr);
+ return;
+ }
+
+ /* most IN status is the same, but ISO can't stall */
+ writel(UDCCS_BI_TPC|UDCCS_BI_FTF|UDCCS_BI_TUR
+ | (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC
+ ? 0 : UDCCS_BI_SST), ep->reg_udccs);
+}
+
+
+static struct usb_ep_ops pxa25x_ep_ops = {
+ .enable = pxa25x_ep_enable,
+ .disable = pxa25x_ep_disable,
+
+ .alloc_request = pxa25x_ep_alloc_request,
+ .free_request = pxa25x_ep_free_request,
+
+ .queue = pxa25x_ep_queue,
+ .dequeue = pxa25x_ep_dequeue,
+
+ .set_halt = pxa25x_ep_set_halt,
+ .fifo_status = pxa25x_ep_fifo_status,
+ .fifo_flush = pxa25x_ep_fifo_flush,
+};
+
+
+/* ---------------------------------------------------------------------------
+ * device-scoped parts of the api to the usb controller hardware
+ * ---------------------------------------------------------------------------
+ */
+
+static int pxa25x_udc_get_frame(struct usb_gadget *_gadget)
+{
+ return ((readl(&the_controller->regs->ufnrh) & 0x07) << 8) |
+ (readl(&the_controller->regs->ufnrl) & 0xff);
+}
+
+static int pxa25x_udc_wakeup(struct usb_gadget *_gadget)
+{
+ /* host may not have enabled remote wakeup */
+ if ((readl(&the_controller->regs->udccs[0]) & UDCCS0_DRWF) == 0)
+ return -EHOSTUNREACH;
+ udc_set_mask_UDCCR(UDCCR_RSM);
+ return 0;
+}
+
+static void stop_activity(struct pxa25x_udc *, struct usb_gadget_driver *);
+static void udc_enable(struct pxa25x_udc *);
+static void udc_disable(struct pxa25x_udc *);
+
+/*
+ * We disable the UDC -- and its 48 MHz clock -- whenever it's not
+ * in active use.
+ */
+static int pullup(struct pxa25x_udc *udc)
+{
+ if (udc->pullup)
+ pullup_on();
+ else
+ pullup_off();
+
+
+ int is_active = udc->pullup;
+ if (is_active) {
+ if (!udc->active) {
+ udc->active = 1;
+ udc_enable(udc);
+ }
+ } else {
+ if (udc->active) {
+ if (udc->gadget.speed != USB_SPEED_UNKNOWN)
+ stop_activity(udc, udc->driver);
+ udc_disable(udc);
+ udc->active = 0;
+ }
+
+ }
+ return 0;
+}
+
+/* VBUS reporting logically comes from a transceiver */
+static int pxa25x_udc_vbus_session(struct usb_gadget *_gadget, int is_active)
+{
+ struct pxa25x_udc *udc;
+
+ udc = container_of(_gadget, struct pxa25x_udc, gadget);
+ printf("vbus %s\n", is_active ? "supplied" : "inactive");
+ pullup(udc);
+ return 0;
+}
+
+/* drivers may have software control over D+ pullup */
+static int pxa25x_udc_pullup(struct usb_gadget *_gadget, int is_active)
+{
+ struct pxa25x_udc *udc;
+
+ udc = container_of(_gadget, struct pxa25x_udc, gadget);
+
+ /* not all boards support pullup control */
+ if (!udc->mach->udc_command)
+ return -EOPNOTSUPP;
+
+ udc->pullup = (is_active != 0);
+ pullup(udc);
+ return 0;
+}
+
+/*
+ * boards may consume current from VBUS, up to 100-500mA based on config.
+ * the 500uA suspend ceiling means that exclusively vbus-powered PXA designs
+ * violate USB specs.
+ */
+static int pxa25x_udc_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
+{
+ return -EOPNOTSUPP;
+}
+
+static const struct usb_gadget_ops pxa25x_udc_ops = {
+ .get_frame = pxa25x_udc_get_frame,
+ .wakeup = pxa25x_udc_wakeup,
+ .vbus_session = pxa25x_udc_vbus_session,
+ .pullup = pxa25x_udc_pullup,
+ .vbus_draw = pxa25x_udc_vbus_draw,
+};
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * udc_disable - disable USB device controller
+ */
+static void udc_disable(struct pxa25x_udc *dev)
+{
+ /* block all irqs */
+ udc_set_mask_UDCCR(UDCCR_SRM|UDCCR_REM);
+ writel(0xff, &dev->regs->uicr0);
+ writel(0xff, &dev->regs->uicr1);
+ writel(UFNRH_SIM, &dev->regs->ufnrh);
+
+ /* if hardware supports it, disconnect from usb */
+ pullup_off();
+
+ udc_clear_mask_UDCCR(UDCCR_UDE);
+
+ ep0_idle(dev);
+ dev->gadget.speed = USB_SPEED_UNKNOWN;
+}
+
+/*
+ * udc_reinit - initialize software state
+ */
+static void udc_reinit(struct pxa25x_udc *dev)
+{
+ u32 i;
+
+ /* device/ep0 records init */
+ INIT_LIST_HEAD(&dev->gadget.ep_list);
+ INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
+ dev->ep0state = EP0_IDLE;
+
+ /* basic endpoint records init */
+ for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
+ struct pxa25x_ep *ep = &dev->ep[i];
+
+ if (i != 0)
+ list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
+
+ ep->desc = NULL;
+ ep->stopped = 0;
+ INIT_LIST_HEAD(&ep->queue);
+ ep->pio_irqs = 0;
+ }
+
+ /* the rest was statically initialized, and is read-only */
+}
+
+/*
+ * until it's enabled, this UDC should be completely invisible
+ * to any USB host.
+ */
+static void udc_enable(struct pxa25x_udc *dev)
+{
+ debug("udc: enabling udc\n");
+
+ udc_clear_mask_UDCCR(UDCCR_UDE);
+
+ /*
+ * Try to clear these bits before we enable the udc.
+ * Do not touch reset ack bit, we would take care of it in
+ * interrupt handle routine
+ */
+ udc_ack_int_UDCCR(UDCCR_SUSIR|UDCCR_RESIR);
+
+ ep0_idle(dev);
+ dev->gadget.speed = USB_SPEED_UNKNOWN;
+ dev->stats.irqs = 0;
+
+ /*
+ * sequence taken from chapter 12.5.10, PXA250 AppProcDevManual:
+ * - enable UDC
+ * - if RESET is already in progress, ack interrupt
+ * - unmask reset interrupt
+ */
+ udc_set_mask_UDCCR(UDCCR_UDE);
+ if (!(readl(&dev->regs->udccr) & UDCCR_UDA))
+ udc_ack_int_UDCCR(UDCCR_RSTIR);
+
+ if (dev->has_cfr /* UDC_RES2 is defined */) {
+ /*
+ * pxa255 (a0+) can avoid a set_config race that could
+ * prevent gadget drivers from configuring correctly
+ */
+ writel(UDCCFR_ACM | UDCCFR_MB1, &dev->regs->udccfr);
+ }
+
+ /* enable suspend/resume and reset irqs */
+ udc_clear_mask_UDCCR(UDCCR_SRM | UDCCR_REM);
+
+ /* enable ep0 irqs */
+ clrbits_le32(&dev->regs->uicr0, UICR0_IM0);
+
+ /* if hardware supports it, pullup D+ and wait for reset */
+ pullup_on();
+}
+
+static inline void clear_ep_state(struct pxa25x_udc *dev)
+{
+ unsigned i;
+
+ /*
+ * hardware SET_{CONFIGURATION,INTERFACE} automagic resets endpoint
+ * fifos, and pending transactions mustn't be continued in any case.
+ */
+ for (i = 1; i < PXA_UDC_NUM_ENDPOINTS; i++)
+ nuke(&dev->ep[i], -ECONNABORTED);
+}
+
+static void handle_ep0(struct pxa25x_udc *dev)
+{
+ u32 udccs0 = readl(&dev->regs->udccs[0]);
+ struct pxa25x_ep *ep = &dev->ep[0];
+ struct pxa25x_request *req;
+ union {
+ struct usb_ctrlrequest r;
+ u8 raw[8];
+ u32 word[2];
+ } u;
+
+ if (list_empty(&ep->queue))
+ req = NULL;
+ else
+ req = list_entry(ep->queue.next, struct pxa25x_request, queue);
+
+ /* clear stall status */
+ if (udccs0 & UDCCS0_SST) {
+ nuke(ep, -EPIPE);
+ writel(UDCCS0_SST, &dev->regs->udccs[0]);
+ stop_watchdog(dev);
+ ep0_idle(dev);
+ }
+
+ /* previous request unfinished? non-error iff back-to-back ... */
+ if ((udccs0 & UDCCS0_SA) != 0 && dev->ep0state != EP0_IDLE) {
+ nuke(ep, 0);
+ stop_watchdog(dev);
+ ep0_idle(dev);
+ }
+
+ switch (dev->ep0state) {
+ case EP0_IDLE:
+ /* late-breaking status? */
+ udccs0 = readl(&dev->regs->udccs[0]);
+
+ /* start control request? */
+ if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))
+ == (UDCCS0_OPR|UDCCS0_SA|UDCCS0_RNE))) {
+ int i;
+
+ nuke(ep, -EPROTO);
+
+ /* read SETUP packet */
+ for (i = 0; i < 8; i++) {
+ if (unlikely(!(readl(&dev->regs->udccs[0]) &
+ UDCCS0_RNE))) {
+bad_setup:
+ debug("SETUP %d!\n", i);
+ goto stall;
+ }
+ u.raw[i] = (u8)readb(&dev->regs->uddr0);
+ }
+ if (unlikely((readl(&dev->regs->udccs[0]) &
+ UDCCS0_RNE) != 0))
+ goto bad_setup;
+
+got_setup:
+ debug("SETUP %02x.%02x v%04x i%04x l%04x\n",
+ u.r.bRequestType, u.r.bRequest,
+ le16_to_cpu(u.r.wValue),
+ le16_to_cpu(u.r.wIndex),
+ le16_to_cpu(u.r.wLength));
+
+ /* cope with automagic for some standard requests. */
+ dev->req_std = (u.r.bRequestType & USB_TYPE_MASK)
+ == USB_TYPE_STANDARD;
+ dev->req_config = 0;
+ dev->req_pending = 1;
+ switch (u.r.bRequest) {
+ /* hardware restricts gadget drivers here! */
+ case USB_REQ_SET_CONFIGURATION:
+ debug("GOT SET_CONFIGURATION\n");
+ if (u.r.bRequestType == USB_RECIP_DEVICE) {
+ /*
+ * reflect hardware's automagic
+ * up to the gadget driver.
+ */
+config_change:
+ dev->req_config = 1;
+ clear_ep_state(dev);
+ /*
+ * if !has_cfr, there's no synch
+ * else use AREN (later) not SA|OPR
+ * USIR0_IR0 acts edge sensitive
+ */
+ }
+ break;
+ /* ... and here, even more ... */
+ case USB_REQ_SET_INTERFACE:
+ if (u.r.bRequestType == USB_RECIP_INTERFACE) {
+ /*
+ * udc hardware is broken by design:
+ * - altsetting may only be zero;
+ * - hw resets all interfaces' eps;
+ * - ep reset doesn't include halt(?).
+ */
+ printf("broken set_interface (%d/%d)\n",
+ le16_to_cpu(u.r.wIndex),
+ le16_to_cpu(u.r.wValue));
+ goto config_change;
+ }
+ break;
+ /* hardware was supposed to hide this */
+ case USB_REQ_SET_ADDRESS:
+ debug("GOT SET ADDRESS\n");
+ if (u.r.bRequestType == USB_RECIP_DEVICE) {
+ ep0start(dev, 0, "address");
+ return;
+ }
+ break;
+ }
+
+ if (u.r.bRequestType & USB_DIR_IN)
+ dev->ep0state = EP0_IN_DATA_PHASE;
+ else
+ dev->ep0state = EP0_OUT_DATA_PHASE;
+
+ i = dev->driver->setup(&dev->gadget, &u.r);
+ if (i < 0) {
+ /* hardware automagic preventing STALL... */
+ if (dev->req_config) {
+ /*
+ * hardware sometimes neglects to tell
+ * tell us about config change events,
+ * so later ones may fail...
+ */
+ printf("config change %02x fail %d?\n",
+ u.r.bRequest, i);
+ return;
+ /*
+ * TODO experiment: if has_cfr,
+ * hardware didn't ACK; maybe we
+ * could actually STALL!
+ */
+ }
+ if (0) {
+stall:
+ /* uninitialized when goto stall */
+ i = 0;
+ }
+ debug("protocol STALL, "
+ "%02x err %d\n",
+ readl(&dev->regs->udccs[0]), i);
+
+ /*
+ * the watchdog timer helps deal with cases
+ * where udc seems to clear FST wrongly, and
+ * then NAKs instead of STALLing.
+ */
+ ep0start(dev, UDCCS0_FST|UDCCS0_FTF, "stall");
+ start_watchdog(dev);
+ dev->ep0state = EP0_STALL;
+
+ /* deferred i/o == no response yet */
+ } else if (dev->req_pending) {
+ if (likely(dev->ep0state == EP0_IN_DATA_PHASE
+ || dev->req_std || u.r.wLength))
+ ep0start(dev, 0, "defer");
+ else
+ ep0start(dev, UDCCS0_IPR, "defer/IPR");
+ }
+
+ /* expect at least one data or status stage irq */
+ return;
+
+ } else if (likely((udccs0 & (UDCCS0_OPR|UDCCS0_SA))
+ == (UDCCS0_OPR|UDCCS0_SA))) {
+ unsigned i;
+
+ /*
+ * pxa210/250 erratum 131 for B0/B1 says RNE lies.
+ * still observed on a pxa255 a0.
+ */
+ debug("e131\n");
+ nuke(ep, -EPROTO);
+
+ /* read SETUP data, but don't trust it too much */
+ for (i = 0; i < 8; i++)
+ u.raw[i] = (u8)readb(&dev->regs->uddr0);
+ if ((u.r.bRequestType & USB_RECIP_MASK)
+ > USB_RECIP_OTHER)
+ goto stall;
+ if (u.word[0] == 0 && u.word[1] == 0)
+ goto stall;
+ goto got_setup;
+ } else {
+ /*
+ * some random early IRQ:
+ * - we acked FST
+ * - IPR cleared
+ * - OPR got set, without SA (likely status stage)
+ */
+ debug("random IRQ %X %X\n", udccs0,
+ readl(&dev->regs->udccs[0]));
+ writel(udccs0 & (UDCCS0_SA|UDCCS0_OPR),
+ &dev->regs->udccs[0]);
+ }
+ break;
+ case EP0_IN_DATA_PHASE: /* GET_DESCRIPTOR etc */
+ if (udccs0 & UDCCS0_OPR) {
+ debug("ep0in premature status\n");
+ if (req)
+ done(ep, req, 0);
+ ep0_idle(dev);
+ } else /* irq was IPR clearing */ {
+ if (req) {
+ debug("next ep0 in packet\n");
+ /* this IN packet might finish the request */
+ (void) write_ep0_fifo(ep, req);
+ } /* else IN token before response was written */
+ }
+ break;
+ case EP0_OUT_DATA_PHASE: /* SET_DESCRIPTOR etc */
+ if (udccs0 & UDCCS0_OPR) {
+ if (req) {
+ /* this OUT packet might finish the request */
+ if (read_ep0_fifo(ep, req))
+ done(ep, req, 0);
+ /* else more OUT packets expected */
+ } /* else OUT token before read was issued */
+ } else /* irq was IPR clearing */ {
+ debug("ep0out premature status\n");
+ if (req)
+ done(ep, req, 0);
+ ep0_idle(dev);
+ }
+ break;
+ case EP0_END_XFER:
+ if (req)
+ done(ep, req, 0);
+ /*
+ * ack control-IN status (maybe in-zlp was skipped)
+ * also appears after some config change events.
+ */
+ if (udccs0 & UDCCS0_OPR)
+ writel(UDCCS0_OPR, &dev->regs->udccs[0]);
+ ep0_idle(dev);
+ break;
+ case EP0_STALL:
+ writel(UDCCS0_FST, &dev->regs->udccs[0]);
+ break;
+ }
+
+ writel(USIR0_IR0, &dev->regs->usir0);
+}
+
+static void handle_ep(struct pxa25x_ep *ep)
+{
+ struct pxa25x_request *req;
+ int is_in = ep->bEndpointAddress & USB_DIR_IN;
+ int completed;
+ u32 udccs, tmp;
+
+ do {
+ completed = 0;
+ if (likely(!list_empty(&ep->queue)))
+ req = list_entry(ep->queue.next,
+ struct pxa25x_request, queue);
+ else
+ req = NULL;
+
+ /* TODO check FST handling */
+
+ udccs = readl(ep->reg_udccs);
+ if (unlikely(is_in)) { /* irq from TPC, SST, or (ISO) TUR */
+ tmp = UDCCS_BI_TUR;
+ if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
+ tmp |= UDCCS_BI_SST;
+ tmp &= udccs;
+ if (likely(tmp))
+ writel(tmp, ep->reg_udccs);
+ if (req && likely((udccs & UDCCS_BI_TFS) != 0))
+ completed = write_fifo(ep, req);
+
+ } else { /* irq from RPC (or for ISO, ROF) */
+ if (likely(ep->bmAttributes == USB_ENDPOINT_XFER_BULK))
+ tmp = UDCCS_BO_SST | UDCCS_BO_DME;
+ else
+ tmp = UDCCS_IO_ROF | UDCCS_IO_DME;
+ tmp &= udccs;
+ if (likely(tmp))
+ writel(tmp, ep->reg_udccs);
+
+ /* fifos can hold packets, ready for reading... */
+ if (likely(req))
+ completed = read_fifo(ep, req);
+ else
+ pio_irq_disable(ep->bEndpointAddress);
+ }
+ ep->pio_irqs++;
+ } while (completed);
+}
+
+/*
+ * pxa25x_udc_irq - interrupt handler
+ *
+ * avoid delays in ep0 processing. the control handshaking isn't always
+ * under software control (pxa250c0 and the pxa255 are better), and delays
+ * could cause usb protocol errors.
+ */
+static struct pxa25x_udc memory;
+static int
+pxa25x_udc_irq(void)
+{
+ struct pxa25x_udc *dev = &memory;
+ int handled;
+
+ test_watchdog(dev);
+
+ dev->stats.irqs++;
+ do {
+ u32 udccr = readl(&dev->regs->udccr);
+
+ handled = 0;
+
+ /* SUSpend Interrupt Request */
+ if (unlikely(udccr & UDCCR_SUSIR)) {
+ udc_ack_int_UDCCR(UDCCR_SUSIR);
+ handled = 1;
+ debug("USB suspend\n");
+
+ if (dev->gadget.speed != USB_SPEED_UNKNOWN
+ && dev->driver
+ && dev->driver->suspend)
+ dev->driver->suspend(&dev->gadget);
+ ep0_idle(dev);
+ }
+
+ /* RESume Interrupt Request */
+ if (unlikely(udccr & UDCCR_RESIR)) {
+ udc_ack_int_UDCCR(UDCCR_RESIR);
+ handled = 1;
+ debug("USB resume\n");
+
+ if (dev->gadget.speed != USB_SPEED_UNKNOWN
+ && dev->driver
+ && dev->driver->resume)
+ dev->driver->resume(&dev->gadget);
+ }
+
+ /* ReSeT Interrupt Request - USB reset */
+ if (unlikely(udccr & UDCCR_RSTIR)) {
+ udc_ack_int_UDCCR(UDCCR_RSTIR);
+ handled = 1;
+
+ if ((readl(&dev->regs->udccr) & UDCCR_UDA) == 0) {
+ debug("USB reset start\n");
+
+ /*
+ * reset driver and endpoints,
+ * in case that's not yet done
+ */
+ stop_activity(dev, dev->driver);
+
+ } else {
+ debug("USB reset end\n");
+ dev->gadget.speed = USB_SPEED_FULL;
+ memset(&dev->stats, 0, sizeof dev->stats);
+ /* driver and endpoints are still reset */
+ }
+
+ } else {
+ u32 uicr0 = readl(&dev->regs->uicr0);
+ u32 uicr1 = readl(&dev->regs->uicr1);
+ u32 usir0 = readl(&dev->regs->usir0);
+ u32 usir1 = readl(&dev->regs->usir1);
+
+ usir0 = usir0 & ~uicr0;
+ usir1 = usir1 & ~uicr1;
+ int i;
+
+ if (unlikely(!usir0 && !usir1))
+ continue;
+
+ debug_cond(NOISY, "irq %02x.%02x\n", usir1, usir0);
+
+ /* control traffic */
+ if (usir0 & USIR0_IR0) {
+ dev->ep[0].pio_irqs++;
+ handle_ep0(dev);
+ handled = 1;
+ }
+
+ /* endpoint data transfers */
+ for (i = 0; i < 8; i++) {
+ u32 tmp = 1 << i;
+
+ if (i && (usir0 & tmp)) {
+ handle_ep(&dev->ep[i]);
+ setbits_le32(&dev->regs->usir0, tmp);
+ handled = 1;
+ }
+#ifndef CONFIG_USB_PXA25X_SMALL
+ if (usir1 & tmp) {
+ handle_ep(&dev->ep[i+8]);
+ setbits_le32(&dev->regs->usir1, tmp);
+ handled = 1;
+ }
+#endif
+ }
+ }
+
+ /* we could also ask for 1 msec SOF (SIR) interrupts */
+
+ } while (handled);
+ return IRQ_HANDLED;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * this uses load-time allocation and initialization (instead of
+ * doing it at run-time) to save code, eliminate fault paths, and
+ * be more obviously correct.
+ */
+static struct pxa25x_udc memory = {
+ .regs = UDC_REGS,
+
+ .gadget = {
+ .ops = &pxa25x_udc_ops,
+ .ep0 = &memory.ep[0].ep,
+ .name = driver_name,
+ },
+
+ /* control endpoint */
+ .ep[0] = {
+ .ep = {
+ .name = ep0name,
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = EP0_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .reg_udccs = &UDC_REGS->udccs[0],
+ .reg_uddr = &UDC_REGS->uddr0,
+ },
+
+ /* first group of endpoints */
+ .ep[1] = {
+ .ep = {
+ .name = "ep1in-bulk",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = BULK_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = BULK_FIFO_SIZE,
+ .bEndpointAddress = USB_DIR_IN | 1,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .reg_udccs = &UDC_REGS->udccs[1],
+ .reg_uddr = &UDC_REGS->uddr1,
+ },
+ .ep[2] = {
+ .ep = {
+ .name = "ep2out-bulk",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = BULK_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = BULK_FIFO_SIZE,
+ .bEndpointAddress = 2,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .reg_udccs = &UDC_REGS->udccs[2],
+ .reg_ubcr = &UDC_REGS->ubcr2,
+ .reg_uddr = &UDC_REGS->uddr2,
+ },
+#ifndef CONFIG_USB_PXA25X_SMALL
+ .ep[3] = {
+ .ep = {
+ .name = "ep3in-iso",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = ISO_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = ISO_FIFO_SIZE,
+ .bEndpointAddress = USB_DIR_IN | 3,
+ .bmAttributes = USB_ENDPOINT_XFER_ISOC,
+ .reg_udccs = &UDC_REGS->udccs[3],
+ .reg_uddr = &UDC_REGS->uddr3,
+ },
+ .ep[4] = {
+ .ep = {
+ .name = "ep4out-iso",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = ISO_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = ISO_FIFO_SIZE,
+ .bEndpointAddress = 4,
+ .bmAttributes = USB_ENDPOINT_XFER_ISOC,
+ .reg_udccs = &UDC_REGS->udccs[4],
+ .reg_ubcr = &UDC_REGS->ubcr4,
+ .reg_uddr = &UDC_REGS->uddr4,
+ },
+ .ep[5] = {
+ .ep = {
+ .name = "ep5in-int",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = INT_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = INT_FIFO_SIZE,
+ .bEndpointAddress = USB_DIR_IN | 5,
+ .bmAttributes = USB_ENDPOINT_XFER_INT,
+ .reg_udccs = &UDC_REGS->udccs[5],
+ .reg_uddr = &UDC_REGS->uddr5,
+ },
+
+ /* second group of endpoints */
+ .ep[6] = {
+ .ep = {
+ .name = "ep6in-bulk",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = BULK_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = BULK_FIFO_SIZE,
+ .bEndpointAddress = USB_DIR_IN | 6,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .reg_udccs = &UDC_REGS->udccs[6],
+ .reg_uddr = &UDC_REGS->uddr6,
+ },
+ .ep[7] = {
+ .ep = {
+ .name = "ep7out-bulk",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = BULK_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = BULK_FIFO_SIZE,
+ .bEndpointAddress = 7,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .reg_udccs = &UDC_REGS->udccs[7],
+ .reg_ubcr = &UDC_REGS->ubcr7,
+ .reg_uddr = &UDC_REGS->uddr7,
+ },
+ .ep[8] = {
+ .ep = {
+ .name = "ep8in-iso",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = ISO_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = ISO_FIFO_SIZE,
+ .bEndpointAddress = USB_DIR_IN | 8,
+ .bmAttributes = USB_ENDPOINT_XFER_ISOC,
+ .reg_udccs = &UDC_REGS->udccs[8],
+ .reg_uddr = &UDC_REGS->uddr8,
+ },
+ .ep[9] = {
+ .ep = {
+ .name = "ep9out-iso",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = ISO_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = ISO_FIFO_SIZE,
+ .bEndpointAddress = 9,
+ .bmAttributes = USB_ENDPOINT_XFER_ISOC,
+ .reg_udccs = &UDC_REGS->udccs[9],
+ .reg_ubcr = &UDC_REGS->ubcr9,
+ .reg_uddr = &UDC_REGS->uddr9,
+ },
+ .ep[10] = {
+ .ep = {
+ .name = "ep10in-int",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = INT_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = INT_FIFO_SIZE,
+ .bEndpointAddress = USB_DIR_IN | 10,
+ .bmAttributes = USB_ENDPOINT_XFER_INT,
+ .reg_udccs = &UDC_REGS->udccs[10],
+ .reg_uddr = &UDC_REGS->uddr10,
+ },
+
+ /* third group of endpoints */
+ .ep[11] = {
+ .ep = {
+ .name = "ep11in-bulk",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = BULK_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = BULK_FIFO_SIZE,
+ .bEndpointAddress = USB_DIR_IN | 11,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .reg_udccs = &UDC_REGS->udccs[11],
+ .reg_uddr = &UDC_REGS->uddr11,
+ },
+ .ep[12] = {
+ .ep = {
+ .name = "ep12out-bulk",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = BULK_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = BULK_FIFO_SIZE,
+ .bEndpointAddress = 12,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .reg_udccs = &UDC_REGS->udccs[12],
+ .reg_ubcr = &UDC_REGS->ubcr12,
+ .reg_uddr = &UDC_REGS->uddr12,
+ },
+ .ep[13] = {
+ .ep = {
+ .name = "ep13in-iso",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = ISO_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = ISO_FIFO_SIZE,
+ .bEndpointAddress = USB_DIR_IN | 13,
+ .bmAttributes = USB_ENDPOINT_XFER_ISOC,
+ .reg_udccs = &UDC_REGS->udccs[13],
+ .reg_uddr = &UDC_REGS->uddr13,
+ },
+ .ep[14] = {
+ .ep = {
+ .name = "ep14out-iso",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = ISO_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = ISO_FIFO_SIZE,
+ .bEndpointAddress = 14,
+ .bmAttributes = USB_ENDPOINT_XFER_ISOC,
+ .reg_udccs = &UDC_REGS->udccs[14],
+ .reg_ubcr = &UDC_REGS->ubcr14,
+ .reg_uddr = &UDC_REGS->uddr14,
+ },
+ .ep[15] = {
+ .ep = {
+ .name = "ep15in-int",
+ .ops = &pxa25x_ep_ops,
+ .maxpacket = INT_FIFO_SIZE,
+ },
+ .dev = &memory,
+ .fifo_size = INT_FIFO_SIZE,
+ .bEndpointAddress = USB_DIR_IN | 15,
+ .bmAttributes = USB_ENDPOINT_XFER_INT,
+ .reg_udccs = &UDC_REGS->udccs[15],
+ .reg_uddr = &UDC_REGS->uddr15,
+ },
+#endif /* !CONFIG_USB_PXA25X_SMALL */
+};
+
+static void udc_command(int cmd)
+{
+ switch (cmd) {
+ case PXA2XX_UDC_CMD_CONNECT:
+ setbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO),
+ GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO));
+
+ /* enable pullup */
+ writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO),
+ GPCR(CONFIG_USB_DEV_PULLUP_GPIO));
+
+ debug("Connected to USB\n");
+ break;
+
+ case PXA2XX_UDC_CMD_DISCONNECT:
+ /* disable pullup resistor */
+ writel(GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO),
+ GPSR(CONFIG_USB_DEV_PULLUP_GPIO));
+
+ /* setup pin as input, line will float */
+ clrbits_le32(GPDR(CONFIG_USB_DEV_PULLUP_GPIO),
+ GPIO_bit(CONFIG_USB_DEV_PULLUP_GPIO));
+
+ debug("Disconnected from USB\n");
+ break;
+ }
+}
+
+static struct pxa2xx_udc_mach_info mach_info = {
+ .udc_command = udc_command,
+};
+
+/*
+ * when a driver is successfully registered, it will receive
+ * control requests including set_configuration(), which enables
+ * non-control requests. then usb traffic follows until a
+ * disconnect is reported. then a host may connect again, or
+ * the driver might get unbound.
+ */
+int usb_gadget_register_driver(struct usb_gadget_driver *driver)
+{
+ struct pxa25x_udc *dev = &memory;
+ int retval;
+ uint32_t chiprev;
+
+ if (!driver
+ || driver->speed < USB_SPEED_FULL
+ || !driver->disconnect
+ || !driver->setup)
+ return -EINVAL;
+ if (!dev)
+ return -ENODEV;
+ if (dev->driver)
+ return -EBUSY;
+
+ /* Enable clock for usb controller */
+ setbits_le32(CKEN, CKEN11_USB);
+
+ /* first hook up the driver ... */
+ dev->driver = driver;
+ dev->pullup = 1;
+
+ /* trigger chiprev-specific logic */
+ switch ((chiprev = pxa_get_cpu_revision())) {
+ case PXA255_A0:
+ dev->has_cfr = 1;
+ break;
+ case PXA250_A0:
+ case PXA250_A1:
+ /* A0/A1 "not released"; ep 13, 15 unusable */
+ /* fall through */
+ case PXA250_B2: case PXA210_B2:
+ case PXA250_B1: case PXA210_B1:
+ case PXA250_B0: case PXA210_B0:
+ /* OUT-DMA is broken ... */
+ /* fall through */
+ case PXA250_C0: case PXA210_C0:
+ break;
+ default:
+ printf("%s: unrecognized processor: %08x\n",
+ DRIVER_NAME, chiprev);
+ return -ENODEV;
+ }
+
+ the_controller = dev;
+
+ /* prepare watchdog timer */
+ dev->watchdog.running = 0;
+ dev->watchdog.period = 5000 * CONFIG_SYS_HZ / 1000000; /* 5 ms */
+ dev->watchdog.function = udc_watchdog;
+
+ udc_disable(dev);
+ udc_reinit(dev);
+
+ dev->mach = &mach_info;
+
+ dev->gadget.name = "pxa2xx_udc";
+ retval = driver->bind(&dev->gadget);
+ if (retval) {
+ printf("bind to driver %s --> error %d\n",
+ DRIVER_NAME, retval);
+ dev->driver = NULL;
+ return retval;
+ }
+
+ /*
+ * ... then enable host detection and ep0; and we're ready
+ * for set_configuration as well as eventual disconnect.
+ */
+ printf("registered gadget driver '%s'\n", DRIVER_NAME);
+
+ pullup(dev);
+ dump_state(dev);
+ return 0;
+}
+
+static void
+stop_activity(struct pxa25x_udc *dev, struct usb_gadget_driver *driver)
+{
+ int i;
+
+ /* don't disconnect drivers more than once */
+ if (dev->gadget.speed == USB_SPEED_UNKNOWN)
+ driver = NULL;
+ dev->gadget.speed = USB_SPEED_UNKNOWN;
+
+ /* prevent new request submissions, kill any outstanding requests */
+ for (i = 0; i < PXA_UDC_NUM_ENDPOINTS; i++) {
+ struct pxa25x_ep *ep = &dev->ep[i];
+
+ ep->stopped = 1;
+ nuke(ep, -ESHUTDOWN);
+ }
+ stop_watchdog(dev);
+
+ /* report disconnect; the driver is already quiesced */
+ if (driver)
+ driver->disconnect(&dev->gadget);
+
+ /* re-init driver-visible data structures */
+ udc_reinit(dev);
+}
+
+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+{
+ struct pxa25x_udc *dev = the_controller;
+
+ if (!dev)
+ return -ENODEV;
+ if (!driver || driver != dev->driver || !driver->unbind)
+ return -EINVAL;
+
+ local_irq_disable();
+ dev->pullup = 0;
+ pullup(dev);
+ stop_activity(dev, driver);
+ local_irq_enable();
+
+ driver->unbind(&dev->gadget);
+ dev->driver = NULL;
+
+ printf("unregistered gadget driver '%s'\n", DRIVER_NAME);
+ dump_state(dev);
+
+ the_controller = NULL;
+
+ clrbits_le32(CKEN, CKEN11_USB);
+
+ return 0;
+}
+
+extern void udc_disconnect(void)
+{
+ setbits_le32(CKEN, CKEN11_USB);
+ udc_clear_mask_UDCCR(UDCCR_UDE);
+ udc_command(PXA2XX_UDC_CMD_DISCONNECT);
+ clrbits_le32(CKEN, CKEN11_USB);
+}
+
+/*-------------------------------------------------------------------------*/
+
+extern int
+usb_gadget_handle_interrupts(void)
+{
+ return pxa25x_udc_irq();
+}
--- /dev/null
+/*
+ * Intel PXA25x on-chip full speed USB device controller
+ *
+ * Copyright (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
+ * Copyright (C) 2003 David Brownell
+ * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __LINUX_USB_GADGET_PXA25X_H
+#define __LINUX_USB_GADGET_PXA25X_H
+
+#include <linux/types.h>
+#include <asm/arch/regs-usb.h>
+
+/*
+ * Prefetching support - only ARMv5.
+ */
+
+#ifdef ARCH_HAS_PREFETCH
+static inline void prefetch(const void *ptr)
+{
+ __asm__ __volatile__(
+ "pld\t%a0"
+ :
+ : "p" (ptr)
+ : "cc");
+}
+
+#define prefetchw(ptr) prefetch(ptr)
+#endif /* ARCH_HAS_PREFETCH */
+
+/*-------------------------------------------------------------------------*/
+
+#define UDC_REGS ((struct pxa25x_udc_regs *)PXA25X_UDC_BASE)
+
+/*-------------------------------------------------------------------------*/
+
+struct pxa2xx_udc_mach_info {
+ int (*udc_is_connected)(void); /* do we see host? */
+ void (*udc_command)(int cmd);
+#define PXA2XX_UDC_CMD_CONNECT 0 /* let host see us */
+#define PXA2XX_UDC_CMD_DISCONNECT 1 /* so host won't see us */
+};
+
+struct pxa25x_udc;
+
+struct pxa25x_ep {
+ struct usb_ep ep;
+ struct pxa25x_udc *dev;
+
+ const struct usb_endpoint_descriptor *desc;
+ struct list_head queue;
+ unsigned long pio_irqs;
+
+ unsigned short fifo_size;
+ u8 bEndpointAddress;
+ u8 bmAttributes;
+
+ unsigned stopped:1;
+
+ /* UDCCS = UDC Control/Status for this EP
+ * UBCR = UDC Byte Count Remaining (contents of OUT fifo)
+ * UDDR = UDC Endpoint Data Register (the fifo)
+ * DRCM = DMA Request Channel Map
+ */
+ u32 *reg_udccs;
+ u32 *reg_ubcr;
+ u32 *reg_uddr;
+};
+
+struct pxa25x_request {
+ struct usb_request req;
+ struct list_head queue;
+};
+
+enum ep0_state {
+ EP0_IDLE,
+ EP0_IN_DATA_PHASE,
+ EP0_OUT_DATA_PHASE,
+ EP0_END_XFER,
+ EP0_STALL,
+};
+
+#define EP0_FIFO_SIZE 16U
+#define BULK_FIFO_SIZE 64U
+#define ISO_FIFO_SIZE 256U
+#define INT_FIFO_SIZE 8U
+
+struct udc_stats {
+ struct ep0stats {
+ unsigned long ops;
+ unsigned long bytes;
+ } read, write;
+ unsigned long irqs;
+};
+
+#ifdef CONFIG_USB_PXA25X_SMALL
+/* when memory's tight, SMALL config saves code+data. */
+#define PXA_UDC_NUM_ENDPOINTS 3
+#endif
+
+#ifndef PXA_UDC_NUM_ENDPOINTS
+#define PXA_UDC_NUM_ENDPOINTS 16
+#endif
+
+struct pxa25x_watchdog {
+ unsigned running:1;
+ ulong period;
+ ulong base;
+ struct pxa25x_udc *udc;
+
+ void (*function)(struct pxa25x_udc *udc);
+};
+
+struct pxa25x_udc {
+ struct usb_gadget gadget;
+ struct usb_gadget_driver *driver;
+ struct pxa25x_udc_regs *regs;
+
+ enum ep0_state ep0state;
+ struct udc_stats stats;
+ unsigned got_irq:1,
+ pullup:1,
+ has_cfr:1,
+ req_pending:1,
+ req_std:1,
+ req_config:1,
+ active:1;
+
+ struct clk *clk;
+ struct pxa2xx_udc_mach_info *mach;
+ u64 dma_mask;
+ struct pxa25x_ep ep[PXA_UDC_NUM_ENDPOINTS];
+
+ struct pxa25x_watchdog watchdog;
+};
+
+/*-------------------------------------------------------------------------*/
+
+static struct pxa25x_udc *the_controller;
+
+/*-------------------------------------------------------------------------*/
+
+#ifndef DEBUG
+# define NOISY 0
+#endif
+
+#endif /* __LINUX_USB_GADGET_PXA25X_H */
COBJS-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o
COBJS-$(CONFIG_USB_S3C64XX) += s3c64xx-hcd.o
COBJS-$(CONFIG_USB_SL811HS) += sl811-hcd.o
+COBJS-$(CONFIG_USB_OHCI_S3C24XX) += ohci-s3c24xx.o
# echi
COBJS-$(CONFIG_USB_EHCI) += ehci-hcd.o
#include <asm/io.h>
#include <usb.h>
#include "ehci.h"
-#include "ehci-core.h"
#include <asm/arch/cpu.h>
#include <asm/arch/armada100.h>
#include <asm/arch/utmi-armada100.h>
/*
* EHCI host controller init
*/
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
if (utmi_init() < 0)
return -1;
- hccr = (struct ehci_hccr *)(ARMD1_USB_HOST_BASE + 0x100);
- hcor = (struct ehci_hcor *)((uint32_t) hccr
- + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ *hccr = (struct ehci_hccr *)(ARMD1_USB_HOST_BASE + 0x100);
+ *hcor = (struct ehci_hcor *)((uint32_t) *hccr
+ + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
debug("armada100-ehci: init hccr %x and hcor %x hc_length %d\n",
- (uint32_t)hccr, (uint32_t)hcor,
- (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
return 0;
}
/*
* EHCI host controller stop
*/
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return 0;
}
#include <asm/arch/clk.h>
#include "ehci.h"
-#include "ehci-core.h"
/* Enable UTMI PLL time out 500us
* 10 times as datasheet specified
*/
#define EN_UPLL_TIMEOUT 500UL
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
ulong start_time, tmp_time;
/* Enable USB Host clock */
writel(1 << ATMEL_ID_UHPHS, &pmc->pcer);
- hccr = (struct ehci_hccr *)ATMEL_BASE_EHCI;
- hcor = (struct ehci_hcor *)((uint32_t)hccr +
- HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ *hccr = (struct ehci_hccr *)ATMEL_BASE_EHCI;
+ *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
return 0;
}
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
ulong start_time, tmp_time;
+++ /dev/null
-/*-
- * Copyright (c) 2007-2008, Juniper Networks, Inc.
- * Copyright (c) 2008, Excito Elektronik i Skåne AB
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef USB_EHCI_CORE_H
-#define USB_EHCI_CORE_H
-
-extern int rootdev;
-extern struct ehci_hccr *hccr;
-extern volatile struct ehci_hcor *hcor;
-
-#endif
#include <asm/arch/system.h>
#include <asm/arch/power.h>
#include "ehci.h"
-#include "ehci-core.h"
/* Setup the EHCI host controller. */
static void setup_usb_phy(struct exynos_usb_phy *usb)
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct exynos_usb_phy *usb;
usb = (struct exynos_usb_phy *)samsung_get_base_usb_phy();
setup_usb_phy(usb);
- hccr = (struct ehci_hccr *)samsung_get_base_usb_ehci();
- hcor = (struct ehci_hcor *)((uint32_t) hccr
- + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ *hccr = (struct ehci_hccr *)samsung_get_base_usb_ehci();
+ *hcor = (struct ehci_hcor *)((uint32_t) *hccr
+ + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
debug("Exynos5-ehci: init hccr %x and hcor %x hc_length %d\n",
- (uint32_t)hccr, (uint32_t)hcor,
- (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
return 0;
}
* Destroy the appropriate control structures corresponding
* the EHCI host controller.
*/
-int ehci_hcd_stop()
+int ehci_hcd_stop(int index)
{
struct exynos_usb_phy *usb;
#include <hwconfig.h>
#include "ehci.h"
-#include "ehci-core.h"
+
+/* Check USB PHY clock valid */
+static int usb_phy_clk_valid(struct usb_ehci *ehci)
+{
+ if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
+ in_be32(&ehci->prictrl))) {
+ printf("USB PHY clock invalid!\n");
+ return 0;
+ } else {
+ return 1;
+ }
+}
/*
* Create the appropriate control structures to manage
*
* Excerpts from linux ehci fsl driver.
*/
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci;
const char *phy_type = NULL;
#endif
ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
- hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
- hcor = (struct ehci_hcor *)((uint32_t) hccr +
- HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+ *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
/* Set to Host mode */
setbits_le32(&ehci->usbmode, CM_HOST);
setbits_be32(&ehci->control, UTMI_PHY_EN);
udelay(1000); /* delay required for PHY Clk to appear */
#endif
- out_le32(&(hcor->or_portsc[0]), PORT_PTS_UTMI);
+ out_le32(&(*hcor)->or_portsc[0], PORT_PTS_UTMI);
+ setbits_be32(&ehci->control, USB_EN);
} else {
-#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
- clrbits_be32(&ehci->control, UTMI_PHY_EN);
setbits_be32(&ehci->control, PHY_CLK_SEL_ULPI);
+ clrsetbits_be32(&ehci->control, UTMI_PHY_EN, USB_EN);
udelay(1000); /* delay required for PHY Clk to appear */
-#endif
- out_le32(&(hcor->or_portsc[0]), PORT_PTS_ULPI);
+ if (!usb_phy_clk_valid(ehci))
+ return -EINVAL;
+ out_le32(&(*hcor)->or_portsc[0], PORT_PTS_ULPI);
}
- /* Enable interface. */
- setbits_be32(&ehci->control, USB_EN);
-
out_be32(&ehci->prictrl, 0x0000000c);
out_be32(&ehci->age_cnt_limit, 0x00000040);
out_be32(&ehci->sictrl, 0x00000001);
* Destroy the appropriate control structures corresponding
* the the EHCI host controller.
*/
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return 0;
}
#include "ehci.h"
-int rootdev;
-struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
-volatile struct ehci_hcor *hcor;
+#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
+#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+#endif
-static uint16_t portreset;
-DEFINE_ALIGN_BUFFER(struct QH, qh_list, 1, USB_DMA_MINALIGN);
+static struct ehci_ctrl {
+ struct ehci_hccr *hccr; /* R/O registers, not need for volatile */
+ struct ehci_hcor *hcor;
+ int rootdev;
+ uint16_t portreset;
+ struct QH qh_list __attribute__((aligned(USB_DMA_MINALIGN)));
+} ehcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
#define ALIGN_END_ADDR(type, ptr, size) \
((uint32_t)(ptr) + roundup((size) * sizeof(type), USB_DMA_MINALIGN))
return -1;
}
-static int ehci_reset(void)
+static int ehci_reset(int index)
{
uint32_t cmd;
uint32_t tmp;
uint32_t *reg_ptr;
int ret = 0;
- cmd = ehci_readl(&hcor->or_usbcmd);
+ cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
cmd = (cmd & ~CMD_RUN) | CMD_RESET;
- ehci_writel(&hcor->or_usbcmd, cmd);
- ret = handshake((uint32_t *)&hcor->or_usbcmd, CMD_RESET, 0, 250 * 1000);
+ ehci_writel(&ehcic[index].hcor->or_usbcmd, cmd);
+ ret = handshake((uint32_t *)&ehcic[index].hcor->or_usbcmd,
+ CMD_RESET, 0, 250 * 1000);
if (ret < 0) {
printf("EHCI fail to reset\n");
goto out;
}
if (ehci_is_TDI()) {
- reg_ptr = (uint32_t *)((u8 *)hcor + USBMODE);
+ reg_ptr = (uint32_t *)((u8 *)ehcic[index].hcor + USBMODE);
tmp = ehci_readl(reg_ptr);
tmp |= USBMODE_CM_HC;
#if defined(CONFIG_EHCI_MMIO_BIG_ENDIAN)
}
#ifdef CONFIG_USB_EHCI_TXFIFO_THRESH
- cmd = ehci_readl(&hcor->or_txfilltuning);
+ cmd = ehci_readl(&ehcic[index].hcor->or_txfilltuning);
cmd &= ~TXFIFO_THRESH_MASK;
cmd |= TXFIFO_THRESH(CONFIG_USB_EHCI_TXFIFO_THRESH);
- ehci_writel(&hcor->or_txfilltuning, cmd);
+ ehci_writel(&ehcic[index].hcor->or_txfilltuning, cmd);
#endif
out:
return ret;
struct qTD *qtd;
int qtd_count = 0;
int qtd_counter = 0;
-
volatile struct qTD *vtd;
unsigned long ts;
uint32_t *tdp;
uint32_t cmd;
int timeout;
int ret = 0;
+ struct ehci_ctrl *ctrl = dev->controller;
debug("dev=%p, pipe=%lx, buffer=%p, length=%d, req=%p\n", dev, pipe,
buffer, length, req);
* qh_overlay.qt_next ...... 13-10 H
* - qh_overlay.qt_altnext
*/
- qh->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
+ qh->qh_link = cpu_to_hc32((uint32_t)&ctrl->qh_list | QH_LINK_TYPE_QH);
c = usb_pipespeed(pipe) != USB_SPEED_HIGH && !usb_pipeendpoint(pipe);
maxpacket = usb_maxpacket(dev, pipe);
endpt = QH_ENDPT1_RL(8) | QH_ENDPT1_C(c) |
tdp = &qtd[qtd_counter++].qt_next;
}
- qh_list->qh_link = cpu_to_hc32((uint32_t)qh | QH_LINK_TYPE_QH);
+ ctrl->qh_list.qh_link = cpu_to_hc32((uint32_t)qh | QH_LINK_TYPE_QH);
/* Flush dcache */
- flush_dcache_range((uint32_t)qh_list,
- ALIGN_END_ADDR(struct QH, qh_list, 1));
+ flush_dcache_range((uint32_t)&ctrl->qh_list,
+ ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
flush_dcache_range((uint32_t)qh, ALIGN_END_ADDR(struct QH, qh, 1));
flush_dcache_range((uint32_t)qtd,
ALIGN_END_ADDR(struct qTD, qtd, qtd_count));
/* Set async. queue head pointer. */
- ehci_writel(&hcor->or_asynclistaddr, (uint32_t)qh_list);
+ ehci_writel(&ctrl->hcor->or_asynclistaddr, (uint32_t)&ctrl->qh_list);
- usbsts = ehci_readl(&hcor->or_usbsts);
- ehci_writel(&hcor->or_usbsts, (usbsts & 0x3f));
+ usbsts = ehci_readl(&ctrl->hcor->or_usbsts);
+ ehci_writel(&ctrl->hcor->or_usbsts, (usbsts & 0x3f));
/* Enable async. schedule. */
- cmd = ehci_readl(&hcor->or_usbcmd);
+ cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
cmd |= CMD_ASE;
- ehci_writel(&hcor->or_usbcmd, cmd);
+ ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
- ret = handshake((uint32_t *)&hcor->or_usbsts, STS_ASS, STS_ASS,
+ ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, STS_ASS,
100 * 1000);
if (ret < 0) {
printf("EHCI fail timeout STS_ASS set\n");
timeout = USB_TIMEOUT_MS(pipe);
do {
/* Invalidate dcache */
- invalidate_dcache_range((uint32_t)qh_list,
- ALIGN_END_ADDR(struct QH, qh_list, 1));
+ invalidate_dcache_range((uint32_t)&ctrl->qh_list,
+ ALIGN_END_ADDR(struct QH, &ctrl->qh_list, 1));
invalidate_dcache_range((uint32_t)qh,
ALIGN_END_ADDR(struct QH, qh, 1));
invalidate_dcache_range((uint32_t)qtd,
printf("EHCI timed out on TD - token=%#x\n", token);
/* Disable async schedule. */
- cmd = ehci_readl(&hcor->or_usbcmd);
+ cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
cmd &= ~CMD_ASE;
- ehci_writel(&hcor->or_usbcmd, cmd);
+ ehci_writel(&ctrl->hcor->or_usbcmd, cmd);
- ret = handshake((uint32_t *)&hcor->or_usbsts, STS_ASS, 0,
+ ret = handshake((uint32_t *)&ctrl->hcor->or_usbsts, STS_ASS, 0,
100 * 1000);
if (ret < 0) {
printf("EHCI fail timeout STS_ASS reset\n");
} else {
dev->act_len = 0;
debug("dev=%u, usbsts=%#x, p[1]=%#x, p[2]=%#x\n",
- dev->devnum, ehci_readl(&hcor->or_usbsts),
- ehci_readl(&hcor->or_portsc[0]),
- ehci_readl(&hcor->or_portsc[1]));
+ dev->devnum, ehci_readl(&ctrl->hcor->or_usbsts),
+ ehci_readl(&ctrl->hcor->or_portsc[0]),
+ ehci_readl(&ctrl->hcor->or_portsc[1]));
}
free(qtd);
int len, srclen;
uint32_t reg;
uint32_t *status_reg;
+ struct ehci_ctrl *ctrl = dev->controller;
if (le16_to_cpu(req->index) > CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS) {
printf("The request port(%d) is not configured\n",
le16_to_cpu(req->index) - 1);
return -1;
}
- status_reg = (uint32_t *)&hcor->or_portsc[
+ status_reg = (uint32_t *)&ctrl->hcor->or_portsc[
le16_to_cpu(req->index) - 1];
srclen = 0;
break;
case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
debug("USB_REQ_SET_ADDRESS\n");
- rootdev = le16_to_cpu(req->value);
+ ctrl->rootdev = le16_to_cpu(req->value);
break;
case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
debug("USB_REQ_SET_CONFIGURATION\n");
tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
if (reg & EHCI_PS_OCC)
tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
- if (portreset & (1 << le16_to_cpu(req->index)))
+ if (ctrl->portreset & (1 << le16_to_cpu(req->index)))
tmpbuf[2] |= USB_PORT_STAT_C_RESET;
srcptr = tmpbuf;
ehci_writel(status_reg, reg);
break;
case USB_PORT_FEAT_POWER:
- if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams))) {
+ if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams))) {
reg |= EHCI_PS_PP;
ehci_writel(status_reg, reg);
}
ret = handshake(status_reg, EHCI_PS_PR, 0,
2 * 1000);
if (!ret)
- portreset |=
+ ctrl->portreset |=
1 << le16_to_cpu(req->index);
else
printf("port(%d) reset error\n",
goto unknown;
}
/* unblock posted writes */
- (void) ehci_readl(&hcor->or_usbcmd);
+ (void) ehci_readl(&ctrl->hcor->or_usbcmd);
break;
case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
reg = ehci_readl(status_reg);
reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_PE;
break;
case USB_PORT_FEAT_POWER:
- if (HCS_PPC(ehci_readl(&hccr->cr_hcsparams)))
+ if (HCS_PPC(ehci_readl(&ctrl->hccr->cr_hcsparams)))
reg = reg & ~(EHCI_PS_CLEAR | EHCI_PS_PP);
case USB_PORT_FEAT_C_CONNECTION:
reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_CSC;
reg = (reg & ~EHCI_PS_CLEAR) | EHCI_PS_OCC;
break;
case USB_PORT_FEAT_C_RESET:
- portreset &= ~(1 << le16_to_cpu(req->index));
+ ctrl->portreset &= ~(1 << le16_to_cpu(req->index));
break;
default:
debug("unknown feature %x\n", le16_to_cpu(req->value));
}
ehci_writel(status_reg, reg);
/* unblock posted write */
- (void) ehci_readl(&hcor->or_usbcmd);
+ (void) ehci_readl(&ctrl->hcor->or_usbcmd);
break;
default:
debug("Unknown request\n");
return -1;
}
-int usb_lowlevel_stop(void)
+int usb_lowlevel_stop(int index)
{
- return ehci_hcd_stop();
+ return ehci_hcd_stop(index);
}
-int usb_lowlevel_init(void)
+int usb_lowlevel_init(int index, void **controller)
{
uint32_t reg;
uint32_t cmd;
+ struct QH *qh_list;
- if (ehci_hcd_init())
+ if (ehci_hcd_init(index, &ehcic[index].hccr, &ehcic[index].hcor))
return -1;
/* EHCI spec section 4.1 */
- if (ehci_reset())
+ if (ehci_reset(index))
return -1;
#if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET)
- if (ehci_hcd_init())
+ if (ehci_hcd_init(index, &ehcic[index].hccr, &ehcic[index].hcor))
return -1;
#endif
+ qh_list = &ehcic[index].qh_list;
+
/* Set head of reclaim list */
memset(qh_list, 0, sizeof(*qh_list));
qh_list->qh_link = cpu_to_hc32((uint32_t)qh_list | QH_LINK_TYPE_QH);
qh_list->qh_overlay.qt_token =
cpu_to_hc32(QT_TOKEN_STATUS(QT_TOKEN_STATUS_HALTED));
- reg = ehci_readl(&hccr->cr_hcsparams);
+ reg = ehci_readl(&ehcic[index].hccr->cr_hcsparams);
descriptor.hub.bNbrPorts = HCS_N_PORTS(reg);
- printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
+ debug("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
/* Port Indicators */
if (HCS_INDICATOR(reg))
put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
| 0x01, &descriptor.hub.wHubCharacteristics);
/* Start the host controller. */
- cmd = ehci_readl(&hcor->or_usbcmd);
+ cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
/*
* Philips, Intel, and maybe others need CMD_RUN before the
* root hub will detect new devices (why?); NEC doesn't
*/
cmd &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
cmd |= CMD_RUN;
- ehci_writel(&hcor->or_usbcmd, cmd);
+ ehci_writel(&ehcic[index].hcor->or_usbcmd, cmd);
/* take control over the ports */
- cmd = ehci_readl(&hcor->or_configflag);
+ cmd = ehci_readl(&ehcic[index].hcor->or_configflag);
cmd |= FLAG_CF;
- ehci_writel(&hcor->or_configflag, cmd);
+ ehci_writel(&ehcic[index].hcor->or_configflag, cmd);
/* unblock posted write */
- cmd = ehci_readl(&hcor->or_usbcmd);
+ cmd = ehci_readl(&ehcic[index].hcor->or_usbcmd);
mdelay(5);
- reg = HC_VERSION(ehci_readl(&hccr->cr_capbase));
+ reg = HC_VERSION(ehci_readl(&ehcic[index].hccr->cr_capbase));
printf("USB EHCI %x.%02x\n", reg >> 8, reg & 0xff);
- rootdev = 0;
+ ehcic[index].rootdev = 0;
+ *controller = &ehcic[index];
return 0;
}
submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
int length, struct devrequest *setup)
{
+ struct ehci_ctrl *ctrl = dev->controller;
if (usb_pipetype(pipe) != PIPE_CONTROL) {
debug("non-control pipe (type=%lu)", usb_pipetype(pipe));
return -1;
}
- if (usb_pipedevice(pipe) == rootdev) {
- if (!rootdev)
+ if (usb_pipedevice(pipe) == ctrl->rootdev) {
+ if (!ctrl->rootdev)
dev->speed = USB_SPEED_HIGH;
return ehci_submit_root(dev, pipe, buffer, length, setup);
}
#include <usb.h>
#include "ehci.h"
-#include "ehci-core.h"
/*
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
- hccr = (struct ehci_hccr *)(0xcd000100);
- hcor = (struct ehci_hcor *)((uint32_t) hccr
- + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ *hccr = (struct ehci_hccr *)(0xcd000100);
+ *hcor = (struct ehci_hcor *)((uint32_t) *hccr
+ + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
printf("IXP4XX init hccr %x and hcor %x hc_length %d\n",
- (uint32_t)hccr, (uint32_t)hcor,
- (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
return 0;
}
* Destroy the appropriate control structures corresponding
* the the EHCI host controller.
*/
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return 0;
}
#include <asm/io.h>
#include <usb.h>
#include "ehci.h"
-#include "ehci-core.h"
#include <asm/arch/cpu.h>
#if defined(CONFIG_KIRKWOOD)
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
usb_brg_adrdec_setup();
- hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100);
- hcor = (struct ehci_hcor *)((uint32_t) hccr
- + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ *hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100);
+ *hcor = (struct ehci_hcor *)((uint32_t) *hccr
+ + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
debug("ehci-marvell: init hccr %x and hcor %x hc_length %d\n",
- (uint32_t)hccr, (uint32_t)hcor,
- (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
return 0;
}
* Destroy the appropriate control structures corresponding
* the the EHCI host controller.
*/
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return 0;
}
#include <usb/ehci-fsl.h>
#include "ehci.h"
-#include "ehci-core.h"
static void fsl_setup_phy(volatile struct ehci_hcor *);
static void fsl_platform_set_host_mode(volatile struct usb_ehci *ehci);
* This code is derived from EHCI FSL USB Linux driver for MPC5121
*
*/
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
volatile struct usb_ehci *ehci;
/* Hook the memory mapped registers for EHCI-Controller */
ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
- hccr = (struct ehci_hccr *)((uint32_t)&(ehci->caplength));
- hcor = (struct ehci_hcor *)((uint32_t) hccr +
- HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ *hccr = (struct ehci_hccr *)((uint32_t)&(ehci->caplength));
+ *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
/* configure interface for UTMI_WIDE */
usb_platform_dr_init(ehci);
/* Init Phy USB0 to UTMI+ */
- fsl_setup_phy(hcor);
+ fsl_setup_phy(*hcor);
/* Set to host mode */
fsl_platform_set_host_mode(ehci);
* Destroy the appropriate control structures corresponding
* the the EHCI host controller.
*/
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
volatile struct usb_ehci *ehci;
int exit_status = 0;
- if (hcor) {
- /* Unhook struct */
- hccr = NULL;
- hcor = NULL;
-
- /* Reset the USB controller */
- ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
- exit_status = reset_usb_controller(ehci);
- }
+ /* Reset the USB controller */
+ ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB_ADDR;
+ exit_status = reset_usb_controller(ehci);
return exit_status;
}
#include <asm/arch/iomux.h>
#include "ehci.h"
-#include "ehci-core.h"
#define MX5_USBOTHER_REGS_OFFSET 0x800
void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
__attribute((weak, alias("__board_ehci_hcd_postinit")));
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci;
#ifdef CONFIG_MX53
set_usboh3_clk();
enable_usboh3_clk(1);
- set_usb_phy2_clk();
+ set_usb_phy_clk();
+ enable_usb_phy1_clk(1);
enable_usb_phy2_clk(1);
mdelay(1);
ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
(0x200 * CONFIG_MXC_USB_PORT));
- hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
- hcor = (struct ehci_hcor *)((uint32_t)hccr +
- HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+ *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
setbits_le32(&ehci->usbmode, CM_HOST);
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
return 0;
}
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return 0;
}
#include <asm/imx-common/iomux-v3.h>
#include "ehci.h"
-#include "ehci-core.h"
#define USB_OTGREGS_OFFSET 0x000
#define USB_H1REGS_OFFSET 0x200
__raw_writel(val, usbother_base + USB_H1_CTRL_OFFSET);
}
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci;
ehci = (struct usb_ehci *)(USBOH3_USB_BASE_ADDR +
(0x200 * CONFIG_MXC_USB_PORT));
- hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
- hcor = (struct ehci_hcor *)((uint32_t)hccr +
- HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+ *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
setbits_le32(&ehci->usbmode, CM_HOST);
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
return 0;
}
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return 0;
}
#include <errno.h>
#include "ehci.h"
-#include "ehci-core.h"
#define USBCTRL_OTGBASE_OFFSET 0x600
return 0;
}
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
struct usb_ehci *ehci;
#ifdef CONFIG_MX31
ehci = (struct usb_ehci *)(IMX_USB_BASE +
(0x200 * CONFIG_MXC_USB_PORT));
- hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
- hcor = (struct ehci_hcor *)((uint32_t) hccr +
- HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
+ *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
setbits_le32(&ehci->usbmode, CM_HOST);
__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
* Destroy the appropriate control structures corresponding
* the the EHCI host controller.
*/
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return 0;
}
#include <asm/arch/regs-usb.h>
#include <asm/arch/regs-usbphy.h>
-#include "ehci-core.h"
#include "ehci.h"
#if (CONFIG_EHCI_MXS_PORT != 0) && (CONFIG_EHCI_MXS_PORT != 1)
#define HW_DIGCTL_CTRL_USB0_CLKGATE (1 << 2)
#define HW_DIGCTL_CTRL_USB1_CLKGATE (1 << 16)
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
int ret;
&ehci_mxs.phy_regs->hw_usbphy_ctrl_set);
usb_base = ((uint32_t)ehci_mxs.usb_regs) + 0x100;
- hccr = (struct ehci_hccr *)usb_base;
+ *hccr = (struct ehci_hccr *)usb_base;
- cap_base = ehci_readl(&hccr->cr_capbase);
- hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
+ cap_base = ehci_readl(&(*hccr)->cr_capbase);
+ *hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
return 0;
}
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
int ret;
- uint32_t tmp;
+ uint32_t usb_base, cap_base, tmp;
struct mxs_register_32 *digctl_ctrl =
(struct mxs_register_32 *)HW_DIGCTL_CTRL;
struct mxs_clkctrl_regs *clkctrl_regs =
(struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
+ struct ehci_hccr *hccr;
+ struct ehci_hcor *hcor;
ret = mxs_ehci_get_port(&ehci_mxs, CONFIG_EHCI_MXS_PORT);
if (ret)
return ret;
/* Stop the USB port */
+ usb_base = ((uint32_t)ehci_mxs.usb_regs) + 0x100;
+ hccr = (struct ehci_hccr *)usb_base;
+ cap_base = ehci_readl(&hccr->cr_capbase);
+ hcor = (struct ehci_hcor *)(usb_base + HC_LENGTH(cap_base));
+
tmp = ehci_readl(&hcor->or_usbcmd);
tmp &= ~CMD_RUN;
ehci_writel(tmp, &hcor->or_usbcmd);
#include <asm/gpio.h>
#include <asm/arch/ehci.h>
#include <asm/ehci-omap.h>
-#include "ehci-core.h"
+
+#include "ehci.h"
static struct omap_uhh *const uhh = (struct omap_uhh *)OMAP_UHH_BASE;
static struct omap_usbtll *const usbtll = (struct omap_usbtll *)OMAP_USBTLL_BASE;
* Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1
* See there for additional Copyrights.
*/
-int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata)
+int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
int ret;
unsigned int i, reg = 0, rev = 0;
if (is_ehci_phy_mode(usbhs_pdata->port_mode[i]))
omap_ehci_soft_phy_reset(i);
- hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE);
- hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10);
+ *hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE);
+ *hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10);
debug("OMAP EHCI init done\n");
return 0;
#include <usb.h>
#include "ehci.h"
-#include "ehci-core.h"
#ifdef CONFIG_PCI_EHCI_DEVICE
static struct pci_device_id ehci_pci_ids[] = {
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
pci_dev_t pdev;
return -1;
}
- hccr = (struct ehci_hccr *)pci_map_bar(pdev,
+ *hccr = (struct ehci_hccr *)pci_map_bar(pdev,
PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
- hcor = (struct ehci_hcor *)((uint32_t) hccr +
- HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
debug("EHCI-PCI init hccr 0x%x and hcor 0x%x hc_length %d\n",
- (uint32_t)hccr, (uint32_t)hcor,
- (uint32_t)HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ (uint32_t)*hccr, (uint32_t)*hcor,
+ (uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
return 0;
}
* Destroy the appropriate control structures corresponding
* the the EHCI host controller.
*/
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return 0;
}
#include <usb.h>
#include "ehci.h"
-#include "ehci-core.h"
/*
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
- hccr = (struct ehci_hccr *)(CONFIG_SYS_PPC4XX_USB_ADDR);
- hcor = (struct ehci_hcor *)((uint32_t) hccr +
- HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
+ *hccr = (struct ehci_hccr *)(CONFIG_SYS_PPC4XX_USB_ADDR);
+ *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
return 0;
}
* Destroy the appropriate control structures corresponding
* the the EHCI host controller.
*/
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return 0;
}
#include <usb.h>
#include "ehci.h"
-#include "ehci-core.h"
#include <asm/errno.h>
#include <asm/arch/usb.h>
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
u32 our_hccr, our_hcor;
* Select the first port, as we don't have a way of selecting others
* yet
*/
- if (tegrausb_start_port(0, &our_hccr, &our_hcor))
+ if (tegrausb_start_port(index, &our_hccr, &our_hcor))
return -1;
- hccr = (struct ehci_hccr *)our_hccr;
- hcor = (struct ehci_hcor *)our_hcor;
+ *hccr = (struct ehci_hccr *)our_hccr;
+ *hcor = (struct ehci_hcor *)our_hcor;
return 0;
}
* Destroy the appropriate control structures corresponding
* the the EHCI host controller.
*/
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
- tegrausb_stop_port();
- return 0;
+ return tegrausb_stop_port(index);
}
#include <usb.h>
#include "ehci.h"
-#include "ehci-core.h"
int vct_ehci_hcd_init(u32 *hccr, u32 *hcor);
* Create the appropriate control structures to manage
* a new EHCI host controller.
*/
-int ehci_hcd_init(void)
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
int ret;
u32 vct_hccr;
if (ret)
return ret;
- hccr = (struct ehci_hccr *)vct_hccr;
- hcor = (struct ehci_hcor *)vct_hcor;
+ *hccr = (struct ehci_hccr *)vct_hccr;
+ *hcor = (struct ehci_hcor *)vct_hcor;
return 0;
}
* Destroy the appropriate control structures corresponding
* the the EHCI host controller.
*/
-int ehci_hcd_stop(void)
+int ehci_hcd_stop(int index)
{
return 0;
}
};
/* Low level init functions */
-int ehci_hcd_init(void);
-int ehci_hcd_stop(void);
+int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor);
+int ehci_hcd_stop(int index);
#endif /* USB_EHCI_H */
return 0;
}
-int usb_lowlevel_init(void)
+int usb_lowlevel_init(int index, void **controller))
{
struct isp116x *isp116x = &isp116x_dev;
return 0;
}
-int usb_lowlevel_stop(void)
+int usb_lowlevel_stop(int index)
{
struct isp116x *isp116x = &isp116x_dev;
*/
static char ohci_inited = 0;
-int usb_lowlevel_init(void)
+int usb_lowlevel_init(int index, void **controller)
{
#ifdef CONFIG_PCI_OHCI
pci_dev_t pdev;
return 0;
}
-int usb_lowlevel_stop(void)
+int usb_lowlevel_stop(int index)
{
/* this gets called really early - before the controller has */
/* even been initialized! */
#include <asm/io.h>
#include <malloc.h>
#include <usb.h>
-#include "usb_ohci.h"
+#include "ohci-s3c24xx.h"
#define OHCI_USE_NPS /* force NoPowerSwitching mode */
#undef OHCI_VERBOSE_DEBUG /* not always helpful */
*/
static char ohci_inited = 0;
-int usb_lowlevel_init(void)
+int usb_lowlevel_init(int index, void **controller)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
return 0;
}
-int usb_lowlevel_stop(void)
+int usb_lowlevel_stop(int index)
{
struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
}
#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_S3C24X0) */
+
+#if defined(CONFIG_USB_OHCI_NEW) && \
+ defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
+ defined(CONFIG_S3C24X0)
+
+int usb_cpu_init(void)
+{
+ struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+ struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
+
+ /*
+ * Set the 48 MHz UPLL clocking. Values are taken from
+ * "PLL value selection guide", 6-23, s3c2400_UM.pdf.
+ */
+ writel((40 << 12) + (1 << 4) + 2, &clk_power->upllcon);
+ /* 1 = use pads related USB for USB host */
+ writel(readl(&gpio->misccr) | 0x8, &gpio->misccr);
+
+ /*
+ * Enable USB host clock.
+ */
+ writel(readl(&clk_power->clkcon) | (1 << 4), &clk_power->clkcon);
+
+ return 0;
+}
+
+int usb_cpu_stop(void)
+{
+ struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+ /* may not want to do this */
+ writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
+ return 0;
+}
+
+int usb_cpu_init_fail(void)
+{
+ struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+ writel(readl(&clk_power->clkcon) & ~(1 << 4), &clk_power->clkcon);
+ return 0;
+}
+
+#endif /* defined(CONFIG_USB_OHCI_NEW) && \
+ defined(CONFIG_SYS_USB_OHCI_CPU_INIT) && \
+ defined(CONFIG_S3C24X0) */
return 0;
}
-int usb_lowlevel_init(void)
+int usb_lowlevel_init(int index, void **controller))
{
struct r8a66597 *r8a66597 = &gr8a66597;
return 0;
}
-int usb_lowlevel_stop(void)
+int usb_lowlevel_stop(int index)
{
disable_controller(&gr8a66597);
return 1;
}
-int usb_lowlevel_init(void)
+int usb_lowlevel_init(int index, void **controller)
{
root_hub_devnum = 0;
sl811_hc_reset();
return 0;
}
-int usb_lowlevel_stop(void)
+int usb_lowlevel_stop(int index)
{
sl811_hc_reset();
return 0;
/*
* This function initializes the usb controller module.
*/
-int usb_lowlevel_init(void)
+int usb_lowlevel_init(int index, void **controller)
{
u8 power;
u32 timeout;
/*
* This function stops the operation of the davinci usb module.
*/
-int usb_lowlevel_stop(void)
+int usb_lowlevel_stop(int index)
{
/* Reset the USB module */
musb_platform_deinit();
return ulpi_write(ulpi_vp, &ulpi->function_ctrl, val);
}
-int ulpi_set_vbus(struct ulpi_viewport *ulpi_vp, int on, int ext_power,
- int ext_ind)
+int ulpi_set_vbus(struct ulpi_viewport *ulpi_vp, int on, int ext_power)
{
u32 flags = ULPI_OTG_DRVVBUS;
u8 *reg = on ? &ulpi->otg_ctrl_set : &ulpi->otg_ctrl_clear;
if (ext_power)
flags |= ULPI_OTG_DRVVBUS_EXT;
- if (ext_ind)
- flags |= ULPI_OTG_EXTVBUSIND;
return ulpi_write(ulpi_vp, reg, flags);
}
+int ulpi_set_vbus_indicator(struct ulpi_viewport *ulpi_vp, int external,
+ int passthu, int complement)
+{
+ u32 flags, val;
+ u8 *reg;
+
+ reg = external ? &ulpi->otg_ctrl_set : &ulpi->otg_ctrl_clear;
+ val = ulpi_write(ulpi_vp, reg, ULPI_OTG_EXTVBUSIND);
+ if (val)
+ return val;
+
+ flags = passthu ? ULPI_IFACE_PASSTHRU : 0;
+ flags |= complement ? ULPI_IFACE_EXTVBUS_COMPLEMENT : 0;
+
+ val = ulpi_read(ulpi_vp, &ulpi->iface_ctrl);
+ if (val == ULPI_ERROR)
+ return val;
+
+ val = val & ~(ULPI_IFACE_PASSTHRU & ULPI_IFACE_EXTVBUS_COMPLEMENT);
+ val |= flags;
+ val = ulpi_write(ulpi_vp, &ulpi->iface_ctrl, val);
+ if (val)
+ return val;
+
+ return 0;
+}
+
int ulpi_set_pd(struct ulpi_viewport *ulpi_vp, int enable)
{
u32 val = ULPI_OTG_DP_PULLDOWN | ULPI_OTG_DM_PULLDOWN;
static int clk_ipu_enable(struct clk *clk)
{
-#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
u32 reg;
reg = __raw_readl(clk->enable_reg);
reg |= MXC_CCM_CCGR_CG_MASK << clk->enable_shift;
__raw_writel(reg, clk->enable_reg);
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
/* Handshake with IPU when certain clock rates are changed. */
reg = __raw_readl(&mxc_ccm->ccdr);
reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
static void clk_ipu_disable(struct clk *clk)
{
-#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
u32 reg;
reg = __raw_readl(clk->enable_reg);
reg &= ~(MXC_CCM_CCGR_CG_MASK << clk->enable_shift);
__raw_writel(reg, clk->enable_reg);
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
/*
* No handshake with IPU whe dividers are changed
* as its not enabled.
static struct clk ipu_clk = {
.name = "ipu_clk",
.rate = CONFIG_IPUV3_CLK,
+#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
.enable_reg = (u32 *)(CCM_BASE_ADDR +
offsetof(struct mxc_ccm_reg, CCGR5)),
- .enable_shift = MXC_CCM_CCGR5_CG5_OFFSET,
+ .enable_shift = MXC_CCM_CCGR5_IPU_OFFSET,
+#else
+ .enable_reg = (u32 *)(CCM_BASE_ADDR +
+ offsetof(struct mxc_ccm_reg, CCGR3)),
+ .enable_shift = MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET,
+#endif
.enable = clk_ipu_enable,
.disable = clk_ipu_disable,
.usecount = 0,
COBJS-$(CONFIG_AT91SAM9_WATCHDOG) += at91sam9_wdt.o
COBJS-$(CONFIG_FTWDT010_WATCHDOG) += ftwdt010_wdt.o
+COBJS-$(CONFIG_TNETV107X_WATCHDOG) += tnetv107x_wdt.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
/*
- * (C) Copyright 2003-2005
+ * (C) Copyright 2003
* Wolfgang Denk Engineering, <wd@denx.de>
*
* See file CREDITS for list of people who contributed to this
/*
OUTPUT_FORMAT("elf32-bigmips", "elf32-bigmips", "elf32-bigmips")
*/
-OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
+OUTPUT_FORMAT("elf64-tradbigmips", "elf64-tradbigmips", "elf64-tradlittlemips")
OUTPUT_ARCH(mips)
-ENTRY(_start)
SECTIONS
{
- . = 0x00000000;
-
- . = ALIGN(4);
.text :
{
*(.text*)
.sdata : { *(.sdata*) }
- .u_boot_cmd : {
- __u_boot_cmd_start = .;
- *(.u_boot_cmd)
- __u_boot_cmd_end = .;
- }
-
- uboot_end_data = .;
- num_got_entries = (__got_end - __got_start) >> 2;
-
. = ALIGN(4);
- .sbss (NOLOAD) : { *(.sbss*) }
+ __bss_start = .;
+ .sbss (NOLOAD) : { *(.sbss*) }
.bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
- uboot_end = .;
+
+ _end = .;
}
{
*(.data)
}
+
. = ALIGN(4);
__data_end = .;
#
#
+subdirs-$(CONFIG_CMD_CBFS) += cbfs
subdirs-$(CONFIG_CMD_CRAMFS) := cramfs
subdirs-$(CONFIG_CMD_EXT4) += ext4
ifndef CONFIG_CMD_EXT4
#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
# See file CREDITS for list of people who contributed to this
# project.
#
include $(TOPDIR)/config.mk
-LIB = $(obj)lib$(BOARD).o
+LIB = $(obj)libcbfs.o
+
+COBJS-$(CONFIG_CMD_CBFS) := cbfs.o
+
+SRCS := $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
-COBJS = $(BOARD).o flash.o serial.o
-SOBJS = init.o
+all: $(LIB)
-SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS))
-SOBJS := $(addprefix $(obj),$(SOBJS))
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
-$(LIB): $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <cbfs.h>
+#include <malloc.h>
+#include <asm/byteorder.h>
+
+enum cbfs_result file_cbfs_result;
+
+const char *file_cbfs_error(void)
+{
+ switch (file_cbfs_result) {
+ case CBFS_SUCCESS:
+ return "Success";
+ case CBFS_NOT_INITIALIZED:
+ return "CBFS not initialized";
+ case CBFS_BAD_HEADER:
+ return "Bad CBFS header";
+ case CBFS_BAD_FILE:
+ return "Bad CBFS file";
+ case CBFS_FILE_NOT_FOUND:
+ return "File not found";
+ default:
+ return "Unknown";
+ }
+}
+
+
+static const u32 good_magic = 0x4f524243;
+static const u8 good_file_magic[] = "LARCHIVE";
+
+
+static int initialized;
+static struct cbfs_header cbfs_header;
+static struct cbfs_cachenode *file_cache;
+
+/* Do endian conversion on the CBFS header structure. */
+static void swap_header(struct cbfs_header *dest, struct cbfs_header *src)
+{
+ dest->magic = be32_to_cpu(src->magic);
+ dest->version = be32_to_cpu(src->version);
+ dest->rom_size = be32_to_cpu(src->rom_size);
+ dest->boot_block_size = be32_to_cpu(src->boot_block_size);
+ dest->align = be32_to_cpu(src->align);
+ dest->offset = be32_to_cpu(src->offset);
+}
+
+/* Do endian conversion on a CBFS file header. */
+static void swap_file_header(struct cbfs_fileheader *dest,
+ const struct cbfs_fileheader *src)
+{
+ memcpy(&dest->magic, &src->magic, sizeof(dest->magic));
+ dest->len = be32_to_cpu(src->len);
+ dest->type = be32_to_cpu(src->type);
+ dest->checksum = be32_to_cpu(src->checksum);
+ dest->offset = be32_to_cpu(src->offset);
+}
+
+/*
+ * Given a starting position in memory, scan forward, bounded by a size, and
+ * find the next valid CBFS file. No memory is allocated by this function. The
+ * caller is responsible for allocating space for the new file structure.
+ *
+ * @param start The location in memory to start from.
+ * @param size The size of the memory region to search.
+ * @param align The alignment boundaries to check on.
+ * @param newNode A pointer to the file structure to load.
+ * @param used A pointer to the count of of bytes scanned through,
+ * including the file if one is found.
+ *
+ * @return 1 if a file is found, 0 if one isn't.
+ */
+static int file_cbfs_next_file(u8 *start, u32 size, u32 align,
+ struct cbfs_cachenode *newNode, u32 *used)
+{
+ struct cbfs_fileheader header;
+
+ *used = 0;
+
+ while (size >= align) {
+ const struct cbfs_fileheader *fileHeader =
+ (const struct cbfs_fileheader *)start;
+ u32 name_len;
+ u32 step;
+
+ /* Check if there's a file here. */
+ if (memcmp(good_file_magic, &(fileHeader->magic),
+ sizeof(fileHeader->magic))) {
+ *used += align;
+ size -= align;
+ start += align;
+ continue;
+ }
+
+ swap_file_header(&header, fileHeader);
+ if (header.offset < sizeof(const struct cbfs_cachenode *) ||
+ header.offset > header.len) {
+ file_cbfs_result = CBFS_BAD_FILE;
+ return -1;
+ }
+ newNode->next = NULL;
+ newNode->type = header.type;
+ newNode->data = start + header.offset;
+ newNode->data_length = header.len;
+ name_len = header.offset - sizeof(struct cbfs_cachenode *);
+ newNode->name = (char *)fileHeader +
+ sizeof(struct cbfs_cachenode *);
+ newNode->name_length = name_len;
+ newNode->checksum = header.checksum;
+
+ step = header.len;
+ if (step % align)
+ step = step + align - step % align;
+
+ *used += step;
+ return 1;
+ }
+ return 0;
+}
+
+/* Look through a CBFS instance and copy file metadata into regular memory. */
+static void file_cbfs_fill_cache(u8 *start, u32 size, u32 align)
+{
+ struct cbfs_cachenode *cache_node;
+ struct cbfs_cachenode *newNode;
+ struct cbfs_cachenode **cache_tail = &file_cache;
+
+ /* Clear out old information. */
+ cache_node = file_cache;
+ while (cache_node) {
+ struct cbfs_cachenode *oldNode = cache_node;
+ cache_node = cache_node->next;
+ free(oldNode);
+ }
+ file_cache = NULL;
+
+ while (size >= align) {
+ int result;
+ u32 used;
+
+ newNode = (struct cbfs_cachenode *)
+ malloc(sizeof(struct cbfs_cachenode));
+ result = file_cbfs_next_file(start, size, align,
+ newNode, &used);
+
+ if (result < 0) {
+ free(newNode);
+ return;
+ } else if (result == 0) {
+ free(newNode);
+ break;
+ }
+ *cache_tail = newNode;
+ cache_tail = &newNode->next;
+
+ size -= used;
+ start += used;
+ }
+ file_cbfs_result = CBFS_SUCCESS;
+}
+
+/* Get the CBFS header out of the ROM and do endian conversion. */
+static int file_cbfs_load_header(uintptr_t end_of_rom,
+ struct cbfs_header *header)
+{
+ struct cbfs_header *header_in_rom;
+
+ header_in_rom = (struct cbfs_header *)(uintptr_t)
+ *(u32 *)(end_of_rom - 3);
+ swap_header(header, header_in_rom);
+
+ if (header->magic != good_magic || header->offset >
+ header->rom_size - header->boot_block_size) {
+ file_cbfs_result = CBFS_BAD_HEADER;
+ return 1;
+ }
+ return 0;
+}
+
+void file_cbfs_init(uintptr_t end_of_rom)
+{
+ u8 *start_of_rom;
+ initialized = 0;
+
+ if (file_cbfs_load_header(end_of_rom, &cbfs_header))
+ return;
+
+ start_of_rom = (u8 *)(end_of_rom + 1 - cbfs_header.rom_size);
+
+ file_cbfs_fill_cache(start_of_rom + cbfs_header.offset,
+ cbfs_header.rom_size, cbfs_header.align);
+ if (file_cbfs_result == CBFS_SUCCESS)
+ initialized = 1;
+}
+
+const struct cbfs_header *file_cbfs_get_header(void)
+{
+ if (initialized) {
+ file_cbfs_result = CBFS_SUCCESS;
+ return &cbfs_header;
+ } else {
+ file_cbfs_result = CBFS_NOT_INITIALIZED;
+ return NULL;
+ }
+}
+
+const struct cbfs_cachenode *file_cbfs_get_first(void)
+{
+ if (!initialized) {
+ file_cbfs_result = CBFS_NOT_INITIALIZED;
+ return NULL;
+ } else {
+ file_cbfs_result = CBFS_SUCCESS;
+ return file_cache;
+ }
+}
+
+void file_cbfs_get_next(const struct cbfs_cachenode **file)
+{
+ if (!initialized) {
+ file_cbfs_result = CBFS_NOT_INITIALIZED;
+ file = NULL;
+ return;
+ }
+
+ if (*file)
+ *file = (*file)->next;
+ file_cbfs_result = CBFS_SUCCESS;
+}
+
+const struct cbfs_cachenode *file_cbfs_find(const char *name)
+{
+ struct cbfs_cachenode *cache_node = file_cache;
+
+ if (!initialized) {
+ file_cbfs_result = CBFS_NOT_INITIALIZED;
+ return NULL;
+ }
+
+ while (cache_node) {
+ if (!strcmp(name, cache_node->name))
+ break;
+ cache_node = cache_node->next;
+ }
+ if (!cache_node)
+ file_cbfs_result = CBFS_FILE_NOT_FOUND;
+ else
+ file_cbfs_result = CBFS_SUCCESS;
+
+ return cache_node;
+}
+
+const struct cbfs_cachenode *file_cbfs_find_uncached(uintptr_t end_of_rom,
+ const char *name)
+{
+ u8 *start;
+ u32 size;
+ u32 align;
+ static struct cbfs_cachenode node;
+
+ if (file_cbfs_load_header(end_of_rom, &cbfs_header))
+ return NULL;
+
+ start = (u8 *)(end_of_rom + 1 - cbfs_header.rom_size);
+ size = cbfs_header.rom_size;
+ align = cbfs_header.align;
+
+ while (size >= align) {
+ int result;
+ u32 used;
+
+ result = file_cbfs_next_file(start, size, align, &node, &used);
+
+ if (result < 0)
+ return NULL;
+ else if (result == 0)
+ break;
+
+ if (!strcmp(name, node.name))
+ return &node;
+
+ size -= used;
+ start += used;
+ }
+ file_cbfs_result = CBFS_FILE_NOT_FOUND;
+ return NULL;
+}
+
+const char *file_cbfs_name(const struct cbfs_cachenode *file)
+{
+ file_cbfs_result = CBFS_SUCCESS;
+ return file->name;
+}
+
+u32 file_cbfs_size(const struct cbfs_cachenode *file)
+{
+ file_cbfs_result = CBFS_SUCCESS;
+ return file->data_length;
+}
+
+u32 file_cbfs_type(const struct cbfs_cachenode *file)
+{
+ file_cbfs_result = CBFS_SUCCESS;
+ return file->type;
+}
+
+long file_cbfs_read(const struct cbfs_cachenode *file, void *buffer,
+ unsigned long maxsize)
+{
+ u32 size;
+
+ size = file->data_length;
+ if (maxsize && size > maxsize)
+ size = maxsize;
+
+ memcpy(buffer, file->data, size);
+
+ file_cbfs_result = CBFS_SUCCESS;
+ return size;
+}
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
+# SEE README.arm-unaligned-accesses
+$(obj)file.o: CFLAGS += $(PLATFORM_NO_UNALIGNED)
#########################################################################
}
/* Calculate short name checksum */
-static __u8 mkcksum(const char *str)
+static __u8 mkcksum(const char name[8], const char ext[3])
{
int i;
__u8 ret = 0;
- for (i = 0; i < 11; i++) {
- ret = (((ret & 1) << 7) | ((ret & 0xfe) >> 1)) + str[i];
- }
+ for (i = 0; i < sizeof(name); i++)
+ ret = (((ret & 1) << 7) | ((ret & 0xfe) >> 1)) + name[i];
+ for (i = 0; i < sizeof(ext); i++)
+ ret = (((ret & 1) << 7) | ((ret & 0xfe) >> 1)) + ext[i];
return ret;
}
return NULL;
}
#ifdef CONFIG_SUPPORT_VFAT
- if (dols && mkcksum(dentptr->name) == prevcksum) {
+ __u8 csum = mkcksum(dentptr->name, dentptr->ext);
+ if (dols && csum == prevcksum) {
prevcksum = 0xffff;
dentptr++;
continue;
for (i = 0; i < DIRENTSPERBLOCK; i++) {
char s_name[14], l_name[VFAT_MAXLEN_BYTES];
+ __u8 csum;
l_name[0] = '\0';
if (dentptr->name[0] == DELETED_FLAG) {
dentptr++;
continue;
}
- if ((dentptr->attr & ATTR_VOLUME)) {
+
+ csum = mkcksum(dentptr->name, dentptr->ext);
+ if (dentptr->attr & ATTR_VOLUME) {
#ifdef CONFIG_SUPPORT_VFAT
if ((dentptr->attr & ATTR_VFAT) == ATTR_VFAT &&
(dentptr->name[0] & LAST_LONG_ENTRY_MASK)) {
goto exit;
}
#ifdef CONFIG_SUPPORT_VFAT
- else if (dols == LS_ROOT &&
- mkcksum(dentptr->name) == prevcksum) {
+ else if (dols == LS_ROOT && csum == prevcksum) {
prevcksum = 0xffff;
dentptr++;
continue;
/* Get short file name and checksum value */
strncpy(s_name, (*dentptr)->name, 16);
- checksum = mkcksum(s_name);
+ checksum = mkcksum((*dentptr)->name, (*dentptr)->ext);
do {
memset(slotptr, 0x00, sizeof(dir_slot));
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
+# SEE README.arm-unaligned-accesses
+$(obj)super.o: CFLAGS += $(PLATFORM_NO_UNALIGNED)
+
#########################################################################
# defines $(obj).depend target
--- /dev/null
+#
+# Copyright (C) 2012 Marek Vasut <marex@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+#########################################################################
+
+##
+# make_u_boot_list - Generate contents of u_boot_list section
+# 1: The name of the resulting file (usually u-boot.lst)
+# 2: Files to analyze for possible u_boot_list entries
+#
+# This function generates the contents of the u_boot_list section,
+# including all the border symbols for it's subsections. The operation
+# of this function is as follows, numbering goes per lines:
+#
+# 1) Dump the ELF header sections from all files supplied via $(2)
+# 2) Filter out all other stuff that does not belong into .u_boot_list
+# section.
+# 3) Fix up the lines so that the resulting output is is in format
+# ".u_boot_list.*".
+# 4) Remove the last .something$, since that only contains the name
+# of the variable to be put into a subsection. This name is irelevant
+# for generation of border symbols, thus of no interest, remove it.
+# 5) Take each line and for every dot "." in that line, print the whole
+# line until that dot "." . This is important so that we have all
+# parent border symbols generated as well.
+# 6) Load every line and firstly append "\a" at the end and print the
+# line. Next, append "@" at the end and print the line. Finally,
+# append "~" at the end of line. This will make sense in conjunction
+# with 6) and 7).
+# 7) Sort the lines. It is imperative to use LC_COLLATE=C here because
+# with this, the "\a" symbol is first and "~" symbol is last. Any
+# other symbols fall inbetween. Symbols like "@", which marks the
+# end of current line (representing current section) and ".", which
+# means the line continues and thus represents subsection.
+# 8) With such ordering, all lines ending with "\a" will float at the
+# begining of all lines with the same prefix. Thus it is easy to
+# replace "\a" with __start and make it the __start border symbol.
+# Very similarly for "~", which will be always at the bottom and so
+# can be replaced by "__end" and made into the __end border symbol.
+# Finally, every line ending with "@" symbol will be transformed
+# into " *(SORT(${line}*)); " format, which in the linker parlance
+# will allow it to trap all symbols relevant to the subsection.
+#
+define make_u_boot_list
+$(1): $(2)
+ $(OBJDUMP) -h $(2) | \
+ sed -n -e '/.*\.u_boot_list[^ ]\+/ ! {d;n}' \
+ -e 's/.*\(\.u_boot_list[^ ]\+\).*$$$$/\1/' \
+ -e 's/\.[^\.]\+$$$$//' \
+ -e ':s /^.\+$$$$/ { p;s/^\(.*\)\.[^\.]*$$$$/\1/;b s }' | \
+ sed -n -e 'h;s/$$$$/\a/p;g;s/$$$$/@/p;g;s/$$$$/~/p;' | \
+ LC_COLLATE=C sort -u | \
+ sed -n -e '/\a$$$$/ { s/\./_/g;s/\a$$$$/__start = .;/p; }'\
+ -e '/~$$$$/ { s/\./_/g;s/~$$$$/__end = .;/p; }'\
+ -e '/@$$$$/ { s/\(.*\)@$$$$/*(SORT(\1.*));/p }' > $(1)
+endef
#define CONFIG_BOOTSTAGE_USER_COUNT 20
#endif
+/* Flags for each bootstage record */
+enum bootstage_flags {
+ BOOTSTAGEF_ERROR = 1 << 0, /* Error record */
+ BOOTSTAGEF_ALLOC = 1 << 1, /* Allocate an id */
+};
+
/*
* A list of boot stages that we know about. Each of these indicates the
* state that we are at, and the action that we are about to perform. For
* rough boot timing information.
*/
BOOTSTAGE_ID_AWAKE,
+ BOOTSTAGE_ID_START_SPL,
BOOTSTAGE_ID_START_UBOOT_F,
BOOTSTAGE_ID_START_UBOOT_R,
BOOTSTAGE_ID_USB_START,
BOOTSTAGE_ID_MAIN_LOOP,
BOOTSTAGE_KERNELREAD_START,
BOOTSTAGE_KERNELREAD_STOP,
+ BOOTSTAGE_ID_BOARD_INIT,
+ BOOTSTAGE_ID_BOARD_INIT_DONE,
BOOTSTAGE_ID_CPU_AWAKE,
BOOTSTAGE_ID_MAIN_CPU_AWAKE,
BOOTSTAGE_ID_MAIN_CPU_READY,
+ BOOTSTAGE_ID_ACCUM_LCD,
+
/* a few spare for the user, from here */
BOOTSTAGE_ID_USER,
BOOTSTAGE_ID_COUNT = BOOTSTAGE_ID_USER + CONFIG_BOOTSTAGE_USER_COUNT,
#if defined(CONFIG_BOOTSTAGE) && !defined(CONFIG_SPL_BUILD)
/* This is the full bootstage implementation */
+/**
+ * Add a new bootstage record
+ *
+ * @param id Bootstage ID to use (ignored if flags & BOOTSTAGEF_ALLOC)
+ * @param name Name of record, or NULL for none
+ * @param flags Flags (BOOTSTAGEF_...)
+ * @param mark Time to record in this record, in microseconds
+ */
+ulong bootstage_add_record(enum bootstage_id id, const char *name,
+ int flags, ulong mark);
+
/*
* Mark a time stamp for the current boot stage.
*/
ulong bootstage_mark_name(enum bootstage_id id, const char *name);
+/**
+ * Mark the start of a bootstage activity. The end will be marked later with
+ * bootstage_accum() and at that point we accumulate the time taken. Calling
+ * this function turns the given id into a accumulator rather than and
+ * absolute mark in time. Accumulators record the total amount of time spent
+ * in an activty during boot.
+ *
+ * @param id Bootstage id to record this timestamp against
+ * @param name Textual name to display for this id in the report (maybe NULL)
+ * @return start timestamp in microseconds
+ */
+uint32_t bootstage_start(enum bootstage_id id, const char *name);
+
+/**
+ * Mark the end of a bootstage activity
+ *
+ * After previously marking the start of an activity with bootstage_start(),
+ * call this function to mark the end. You can call these functions in pairs
+ * as many times as you like.
+ *
+ * @param id Bootstage id to record this timestamp against
+ * @return time spent in this iteration of the activity (i.e. the time now
+ * less the start time recorded in the last bootstage_start() call
+ * with this id.
+ */
+uint32_t bootstage_accum(enum bootstage_id id);
+
/* Print a report about boot time */
void bootstage_report(void);
+/**
+ * Add bootstage information to the device tree
+ *
+ * @return 0 if ok, -ve on error
+ */
+int bootstage_fdt_add_report(void);
+
+/*
+ * Stash bootstage data into memory
+ *
+ * @param base Base address of memory buffer
+ * @param size Size of memory buffer
+ * @return 0 if stashed ok, -1 if out of space
+ */
+int bootstage_stash(void *base, int size);
+
+/**
+ * Read bootstage data from memory
+ *
+ * Bootstage data is read from memory and placed in the bootstage table
+ * in the user records.
+ *
+ * @param base Base address of memory buffer
+ * @param size Size of memory buffer (-1 if unknown)
+ * @return 0 if unstashed ok, -1 if bootstage info not found, or out of space
+ */
+int bootstage_unstash(void *base, int size);
+
#else
/*
* This is a dummy implementation which just calls show_boot_progress(),
return 0;
}
+static inline int bootstage_stash(void *base, int size)
+{
+ return 0; /* Pretend to succeed */
+}
+static inline int bootstage_unstash(void *base, int size)
+{
+ return 0; /* Pretend to succeed */
+}
#endif /* CONFIG_BOOTSTAGE */
#endif
--- /dev/null
+/*
+ * Copyright (c) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CBFS_H
+#define __CBFS_H
+
+#include <compiler.h>
+#include <linux/compiler.h>
+
+enum cbfs_result {
+ CBFS_SUCCESS = 0,
+ CBFS_NOT_INITIALIZED,
+ CBFS_BAD_HEADER,
+ CBFS_BAD_FILE,
+ CBFS_FILE_NOT_FOUND
+};
+
+enum cbfs_filetype {
+ CBFS_TYPE_STAGE = 0x10,
+ CBFS_TYPE_PAYLOAD = 0x20,
+ CBFS_TYPE_OPTIONROM = 0x30,
+ CBFS_TYPE_BOOTSPLASH = 0x40,
+ CBFS_TYPE_RAW = 0x50,
+ CBFS_TYPE_VSA = 0x51,
+ CBFS_TYPE_MBI = 0x52,
+ CBFS_TYPE_MICROCODE = 0x53,
+ CBFS_COMPONENT_CMOS_DEFAULT = 0xaa,
+ CBFS_COMPONENT_CMOS_LAYOUT = 0x01aa
+};
+
+struct cbfs_header {
+ u32 magic;
+ u32 version;
+ u32 rom_size;
+ u32 boot_block_size;
+ u32 align;
+ u32 offset;
+ u32 pad[2];
+} __packed;
+
+struct cbfs_fileheader {
+ u8 magic[8];
+ u32 len;
+ u32 type;
+ u32 checksum;
+ u32 offset;
+} __packed;
+
+struct cbfs_cachenode {
+ struct cbfs_cachenode *next;
+ u32 type;
+ void *data;
+ u32 data_length;
+ char *name;
+ u32 name_length;
+ u32 checksum;
+} __packed;
+
+extern enum cbfs_result file_cbfs_result;
+
+/*
+ * Return a string describing the most recent error condition.
+ *
+ * @return A pointer to the constant string.
+ */
+const char *file_cbfs_error(void);
+
+/*
+ * Initialize the CBFS driver and load metadata into RAM.
+ *
+ * @param end_of_rom Points to the end of the ROM the CBFS should be read
+ * from.
+ */
+void file_cbfs_init(uintptr_t end_of_rom);
+
+/*
+ * Get the header structure for the current CBFS.
+ *
+ * @return A pointer to the constant structure, or NULL if there is none.
+ */
+const struct cbfs_header *file_cbfs_get_header(void);
+
+/*
+ * Get a handle for the first file in CBFS.
+ *
+ * @return A handle for the first file in CBFS, NULL on error.
+ */
+const struct cbfs_cachenode *file_cbfs_get_first(void);
+
+/*
+ * Get a handle to the file after this one in CBFS.
+ *
+ * @param file A pointer to the handle to advance.
+ */
+void file_cbfs_get_next(const struct cbfs_cachenode **file);
+
+/*
+ * Find a file with a particular name in CBFS.
+ *
+ * @param name The name to search for.
+ *
+ * @return A handle to the file, or NULL on error.
+ */
+const struct cbfs_cachenode *file_cbfs_find(const char *name);
+
+
+/***************************************************************************/
+/* All of the functions below can be used without first initializing CBFS. */
+/***************************************************************************/
+
+/*
+ * Find a file with a particular name in CBFS without using the heap.
+ *
+ * @param end_of_rom Points to the end of the ROM the CBFS should be read
+ * from.
+ * @param name The name to search for.
+ *
+ * @return A handle to the file, or NULL on error.
+ */
+const struct cbfs_cachenode *file_cbfs_find_uncached(uintptr_t end_of_rom,
+ const char *name);
+
+/*
+ * Get the name of a file in CBFS.
+ *
+ * @param file The handle to the file.
+ *
+ * @return The name of the file, NULL on error.
+ */
+const char *file_cbfs_name(const struct cbfs_cachenode *file);
+
+/*
+ * Get the size of a file in CBFS.
+ *
+ * @param file The handle to the file.
+ *
+ * @return The size of the file, zero on error.
+ */
+u32 file_cbfs_size(const struct cbfs_cachenode *file);
+
+/*
+ * Get the type of a file in CBFS.
+ *
+ * @param file The handle to the file.
+ *
+ * @return The type of the file, zero on error.
+ */
+u32 file_cbfs_type(const struct cbfs_cachenode *file);
+
+/*
+ * Read a file from CBFS into RAM
+ *
+ * @param file A handle to the file to read.
+ * @param buffer Where to read it into memory.
+ *
+ * @return If positive or zero, the number of characters read. If negative, an
+ * error occurred.
+ */
+long file_cbfs_read(const struct cbfs_cachenode *file, void *buffer,
+ unsigned long maxsize);
+
+#endif /* __CBFS_H */
#define __COMMAND_H
#include <config.h>
+#include <linker_lists.h>
#ifndef NULL
#define NULL 0
typedef struct cmd_tbl_s cmd_tbl_t;
-extern cmd_tbl_t __u_boot_cmd_start;
-extern cmd_tbl_t __u_boot_cmd_end;
#if defined(CONFIG_CMD_RUN)
extern int do_run(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
#define CMD_FLAG_REPEAT 0x0001 /* repeat last command */
#define CMD_FLAG_BOOTD 0x0002 /* command is from bootd */
-#define Struct_Section __attribute__((unused, section(".u_boot_cmd"), \
- aligned(4)))
-
#ifdef CONFIG_AUTO_COMPLETE
# define _CMD_COMPLETE(x) x,
#else
# define _CMD_HELP(x)
#endif
-#define U_BOOT_CMD_MKENT_COMPLETE(name,maxargs,rep,cmd,usage,help,comp) \
- {#name, maxargs, rep, cmd, usage, _CMD_HELP(help) _CMD_COMPLETE(comp)}
+#define U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, \
+ _usage, _help, _comp) \
+ { #_name, _maxargs, _rep, _cmd, _usage, \
+ _CMD_HELP(_help) _CMD_COMPLETE(_comp) }
-#define U_BOOT_CMD_MKENT(name,maxargs,rep,cmd,usage,help) \
- U_BOOT_CMD_MKENT_COMPLETE(name,maxargs,rep,cmd,usage,help,NULL)
+#define U_BOOT_CMD_MKENT(_name, _maxargs, _rep, _cmd, _usage, _help) \
+ U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, \
+ _usage, _help, NULL)
-#define U_BOOT_CMD_COMPLETE(name,maxargs,rep,cmd,usage,help,comp) \
- cmd_tbl_t __u_boot_cmd_##name Struct_Section = \
- U_BOOT_CMD_MKENT_COMPLETE(name,maxargs,rep,cmd,usage,help,comp)
+#define U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, _comp) \
+ ll_entry_declare(cmd_tbl_t, _name, cmd, cmd) = \
+ U_BOOT_CMD_MKENT_COMPLETE(_name, _maxargs, _rep, _cmd, \
+ _usage, _help, _comp);
-#define U_BOOT_CMD(name,maxargs,rep,cmd,usage,help) \
- U_BOOT_CMD_COMPLETE(name,maxargs,rep,cmd,usage,help,NULL)
+#define U_BOOT_CMD(_name, _maxargs, _rep, _cmd, _usage, _help) \
+ U_BOOT_CMD_COMPLETE(_name, _maxargs, _rep, _cmd, _usage, _help, NULL)
#if defined(CONFIG_NEEDS_MANUAL_RELOC)
void fixup_cmdtable(cmd_tbl_t *cmdtp, int size);
#include <linux/bitops.h>
#include <linux/types.h>
#include <linux/string.h>
+#include <linux/stringify.h>
#include <asm/ptrace.h>
#include <stdarg.h>
-#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000))
+#if defined(CONFIG_PCI) && defined(CONFIG_4xx)
#include <pci.h>
#endif
#if defined(CONFIG_8xx)
# endif
#endif
-#ifndef CONFIG_SERIAL_MULTI
-
-#if defined(CONFIG_8xx_CONS_SMC1) || defined(CONFIG_8xx_CONS_SMC2) \
- || defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) \
- || defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4)
-
-#define CONFIG_SERIAL_MULTI 1
-
-#endif
-
-#endif /* CONFIG_SERIAL_MULTI */
-
/*
* General Purpose Utilities
*/
void pci_init_board(void);
void pciinfo (int, int);
-#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000))
+#if defined(CONFIG_PCI) && defined(CONFIG_4xx)
int pci_pre_init (struct pci_controller *);
int is_pci_host (struct pci_controller *);
#endif
}
#endif
-#if defined(CONFIG_4xx) || defined(CONFIG_IOP480)
+#if defined(CONFIG_4xx)
# if defined(CONFIG_440)
# if defined(CONFIG_440SPE)
unsigned long determine_sysper(void);
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_IOP480 1 /* This is a IOP480 CPU */
-#define CONFIG_ADCIOP 1 /* ...on a ADCIOP board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFD0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#define CONFIG_CPUCLOCK 66
-#define CONFIG_BUSCLOCK (CONFIG_CPUCLOCK)
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-#define CONFIG_BOOTCOMMAND "bootm ffc00000" /* autoboot command */
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-
-#define CONFIG_IPADDR 10.0.18.222
-#define CONFIG_SERVERIP 10.0.18.190
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_ASKENV
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x0f00 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFD0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x0AA9 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x0556 /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0002 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0000 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0004 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#if 1 /* Use NVRAM for environment variables */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0x10000000 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
-#define CONFIG_ENV_SIZE 0x0400 /* Size of Environment vars */
-#define CONFIG_ENV_ADDR \
- (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
-#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x7800) /* VxWorks eth-addr*/
-
-#else /* Use FLASH for environment variables */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-
-#define CONFIG_ENV_SECT_SIZE 0x8000 /* see README - env sector total size */
-
-#endif
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- */
-#define CONFIG_PCI /* include pci support */
-#undef CONFIG_PCI_PNP
-
-
-#define CONFIG_TULIP
-
-#define CONFIG_SYS_ETH_DEV_FN 0x0000
-#define CONFIG_SYS_ETH_IOBASE 0x0fff0000
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0xFFE00000 /* FLASH bank #1 */
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * AMIRIX.h: AMIRIX specific config options
- *
- * Author : Frank Smith (smith at amirix dot com)
- *
- * Derived from : other configuration header files in this tree
- *
- * This software may be used and distributed according to the terms of
- * the GNU General Public License (GPL) version 2, incorporated herein by
- * reference. Drivers based on or derived from this code fall under the GPL
- * and must retain the authorship, copyright and this license notice. This
- * file is not a complete program and may only be used when the entire
- * program is licensed under the GPL.
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
-
-#define CONFIG_AP1000 1 /* ...on an AP1000 board */
-
-/*
- * Start at bottom of RAM, but at an aliased address so that it looks
- * like it's not in RAM. This is a bit of voodoo to allow it to be
- * run from RAM instead of Flash.
- */
-#define CONFIG_SYS_TEXT_BASE 0x08000000
-#define CONFIG_SYS_LDSCRIPT "board/amirix/ap1000/u-boot.lds"
-
-#define CONFIG_PCI 1
-
-#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */
-#define CONFIG_SYS_PROMPT "0> "
-
-#define CONFIG_COMMAND_EDIT 1
-#define CONFIG_COMPLETE_ADDRESSES 1
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-
-#ifdef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#else
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_NVRAM
-#endif
-#endif
-
-#define CONFIG_BAUDRATE 57600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#define CONFIG_BOOTCOMMAND "" /* autoboot command */
-
-#define CONFIG_BOOTARGS "console=ttyS0,57600"
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_MVENV
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SYS_CLK_FREQ 30000000
-
-#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
-
-/*
- * I2C
- */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_SPEED 400000
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-/* usually: (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+4+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_ALT_MEMTEST 1
-#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 4 ... 16 MB in DRAM */
-
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- * baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
-#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
-
-#define CONFIG_SYS_NS16550_CLK 40000000
-#define CONFIG_SYS_DUART_CHAN 0
-#define CONFIG_SYS_NS16550_COM1 (0x4C000000 + 0x1000)
-#define CONFIG_SYS_NS16550_COM2 (0x4C800000 + 0x1000)
-#define CONFIG_SYS_NS16550_REG_SIZE 4
-#define CONFIG_SYS_NS16550 1
-#define CONFIG_SYS_INIT_CHAN1 1
-#define CONFIG_SYS_INIT_CHAN2 0
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CONFIG_SYS_LOAD_ADDR 0x00200000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x20000000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_CFI 1
-#define CONFIG_SYS_PROGFLASH_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_CONFFLASH_BASE 0x24000000
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware protection */
-
-/* BEG ENVIRONNEMENT FLASH */
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE 0x20000 /* see README - env sector total size */
-#endif
-/* END ENVIRONNEMENT FLASH */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */
-
-#ifdef CONFIG_ENV_IS_IN_NVRAM
-#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
-#define CONFIG_ENV_ADDR \
- (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
-
-/* Configuration Port location */
-#define CONFIG_PORT_ADDR 0xF0000500
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x400000 /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS 0x50
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/* JFFS2 stuff */
-
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 1
-
-#define CONFIG_E1000
-
-#define CONFIG_SYS_ETH_DEV_FN 0x0800
-#define CONFIG_SYS_ETH_IOBASE 0x31000000
-#define CONFIG_SYS_ETH_MEMBASE 0x32000000
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- *
- * Configuration settings for the CU824 board.
- *
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC824X 1
-#define CONFIG_MPC8245 1
-#define CONFIG_BMW 1
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 9600
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#define CONFIG_BOOTCOMMAND "bootm FF820000" /* autoboot command */
-#define CONFIG_BOOTDELAY 5
-
-#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Only use Onboard TSOP-16MB device */
-#define DOC_PASSIVE_PROBE 1
-#define CONFIG_SYS_DOC_SUPPORT_2000 1
-#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM 1
-#define CONFIG_SYS_DOC_SHORT_TIMEOUT 1
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_ELF
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-
-
-#if 0
-#define CONFIG_PCI 1
-#define CONFIG_PCI_PNP 1 /* PCI plug-and-play */
-#endif
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-
-/* Print Buffer Size
- */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-
-#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-
-#define CONFIG_SYS_FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank on RCS#0 */
-#define CONFIG_SYS_FLASH_BASE1_PRELIM 0xFF800000 /* FLASH bank on RCS#1 */
-#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
-#define CONFIG_SYS_FLASH_BANKS { CONFIG_SYS_FLASH_BASE0_PRELIM , CONFIG_SYS_FLASH_BASE1_PRELIM }
-
-/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
- * reset vector is actually located at FFB00100, but the 8245
- * takes care of us.
- */
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-
-#define CONFIG_SYS_EUMB_ADDR 0xFC000000
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (2048 << 10) /* Reserve 2MB for malloc() */
-
-#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
-
- /* Maximum amount of RAM.
- */
-#define CONFIG_SYS_MAX_RAM_SIZE 0x04000000 /* 0 .. 64 MB of (S)DRAM */
-
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
-#undef CONFIG_SYS_RAMBOOT
-#else
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- * For the detail description refer to the MPC8240 user's manual.
- */
-
-#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
-#define CONFIG_SYS_HZ 1000
-
-#define CONFIG_SYS_ETH_DEV_FN 0x7800
-#define CONFIG_SYS_ETH_IOBASE 0x00104000
-
- /* Bit-field values for MCCR1.
- */
-#define CONFIG_SYS_ROMNAL 0xf
-#define CONFIG_SYS_ROMFAL 0x1f
-#define CONFIG_SYS_DBUS_SIZE 0x3
-
- /* Bit-field values for MCCR2.
- */
-#define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */
-#define CONFIG_SYS_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */
-
- /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
- */
-#define CONFIG_SYS_BSTOPRE 0 /* FIXME: was 192 */
-
- /* Bit-field values for MCCR3.
- */
-#define CONFIG_SYS_REFREC 2 /* Refresh to activate interval */
-
- /* Bit-field values for MCCR4.
- */
-#define CONFIG_SYS_PRETOACT 2 /* Precharge to activate interval FIXME: was 2 */
-#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */
-#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
-#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
-#define CONFIG_SYS_SDMODE_BURSTLEN 3 /* SDMODE Burst length */
-#define CONFIG_SYS_ACTORW 0xa /* FIXME was 2 */
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-
-#define CONFIG_SYS_PGMAX 0x0 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
-
-#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
-
-/* Memory bank settings.
- * Only bits 20-29 are actually used from these vales to set the
- * start/end addresses. The upper two bits will always be 0, and the lower
- * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
- * address. Refer to the MPC8240 book.
- */
-
-#define CONFIG_SYS_BANK0_START 0x00000000
-#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK0_ENABLE 1
-#define CONFIG_SYS_BANK1_START 0x3ff00000
-#define CONFIG_SYS_BANK1_END 0x3fffffff
-#define CONFIG_SYS_BANK1_ENABLE 0
-#define CONFIG_SYS_BANK2_START 0x3ff00000
-#define CONFIG_SYS_BANK2_END 0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE 0
-#define CONFIG_SYS_BANK3_START 0x3ff00000
-#define CONFIG_SYS_BANK3_END 0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE 0
-#define CONFIG_SYS_BANK4_START 0x3ff00000
-#define CONFIG_SYS_BANK4_END 0x3fffffff
-#define CONFIG_SYS_BANK4_ENABLE 0
-#define CONFIG_SYS_BANK5_START 0x3ff00000
-#define CONFIG_SYS_BANK5_END 0x3fffffff
-#define CONFIG_SYS_BANK5_ENABLE 0
-#define CONFIG_SYS_BANK6_START 0x3ff00000
-#define CONFIG_SYS_BANK6_END 0x3fffffff
-#define CONFIG_SYS_BANK6_ENABLE 0
-#define CONFIG_SYS_BANK7_START 0x3ff00000
-#define CONFIG_SYS_BANK7_END 0x3fffffff
-#define CONFIG_SYS_BANK7_ENABLE 0
-
-#define CONFIG_SYS_ODCR 0xff
-
-#define CONFIG_PCI 1 /* Include PCI support */
-#undef CONFIG_PCI_PNP
-
-/* PCI Memory space(s) */
-#define PCI_MEM_SPACE1_START 0x80000000
-#define PCI_MEM_SPACE2_START 0xfd000000
-
-/* ROM Spaces */
-#include "../board/bmw/bmw.h"
-
-/* BAT configuration */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT1L (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT1U (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 0 /* Max number of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/*
- * Warining: environment is not EMBEDDED in the U-Boot code.
- * It's stored in flash separately.
- */
-#define CONFIG_ENV_IS_IN_NVRAM 1
-#define CONFIG_ENV_OVERWRITE 1
-#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1
-#define CONFIG_ENV_ADDR 0x7c004000 /* right at the start of NVRAM */
-#define CONFIG_ENV_SIZE 0x1ff0 /* Size of the Environment - 8K */
-#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
-
-/*
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-#endif /* __CONFIG_H */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_IOP480 1 /* This is a IOP480 CPU */
-#define CONFIG_DASA_SIM 1 /* ...on a DASA_SIM board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-#define CONFIG_SYS_LDSCRIPT "board/esd/dasa_sim/u-boot.lds"
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-
-#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
-
-#define CONFIG_CPUCLOCK 66
-#define CONFIG_BUSCLOCK (CONFIG_CPUCLOCK)
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
-#define CONFIG_BOOTCOMMAND "bootm ffe00000" /* autoboot command */
-
-#undef CONFIG_BOOTARGS
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_IPADDR 10.0.18.222
-#define CONFIG_SERVERIP 10.0.18.190
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_BSP
-
-
-#if 0 /* Does not appear to be used?! If it is used, needs to be fixed */
-#define CONFIG_SOFT_I2C /* Software I2C support enabled */
-#endif
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x0f00 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 128 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x0AA9 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x0556 /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0002 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0000 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0004 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x00010000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
-
-#if 0
-#define CONFIG_ENV_SECT_SIZE 0x8000 /* see README - env sector total size */
-#else
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
-#endif
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- */
-#define CONFIG_PCI /* include pci support */
-#undef CONFIG_PCI_PNP
-
-
-#define CONFIG_TULIP
-
-#define CONFIG_SYS_ETH_DEV_FN 0x0000
-#define CONFIG_SYS_ETH_IOBASE 0x0fff0000
-#define CONFIG_SYS_PCI9054_DEV_FN 0x0800
-#define CONFIG_SYS_PCI9054_IOBASE 0x0eff0000
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
-
-#endif /* __CONFIG_H */
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
* IDE/ATA stuff
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
+#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */
#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
#define CONFIG_IDE_RESET 1 /* reset for ide supported */
* IDE/ATA stuff
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
+#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */
#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
#define CONFIG_IDE_RESET 1 /* reset for ide supported */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_BAUDRATE 9600
#define CONFIG_SYS_BAUDRATE_TABLE \
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#ifdef CONFIG_SYS_STMICRO_BOOT
/* ST Micro serial flash */
#define CONFIG_EXTRA_ENV_SETTINGS \
- "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
+ "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
"loadaddr=0x40010000\0" \
"uboot=u-boot.bin\0" \
"load=loadb ${loadaddr} ${baudrate};" \
- "loadb " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
+ "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
"upd=run load; run prog\0" \
"prog=sf probe 0:2 10000 1;" \
"sf erase 0 30000;" \
#endif
#ifdef CONFIG_SYS_SPANSION_BOOT
#define CONFIG_EXTRA_ENV_SETTINGS \
- "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
+ "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
"loadaddr=0x40010000\0" \
"uboot=u-boot.bin\0" \
"load=loadb ${loadaddr} ${baudrate}\0" \
"upd=run load; run prog\0" \
- "prog=prot off " MK_STR(CONFIG_SYS_FLASH_BASE) \
- " " MK_STR(CONFIG_SYS_UBOOT_END) ";" \
- "era " MK_STR(CONFIG_SYS_FLASH_BASE) " " \
- MK_STR(CONFIG_SYS_UBOOT_END) ";" \
- "cp.b ${loadaddr} " MK_STR(CONFIG_SYS_FLASH_BASE) \
+ "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
+ " " __stringify(CONFIG_SYS_UBOOT_END) ";" \
+ "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
+ __stringify(CONFIG_SYS_UBOOT_END) ";" \
+ "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
" ${filesize}; save\0" \
"updsbf=run loadsbf; run progsbf\0" \
"loadsbf=loadb ${loadaddr} ${baudrate};" \
- "loadb " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
+ "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
"progsbf=sf probe 0:2 10000 1;" \
"sf erase 0 30000;" \
"sf write ${loadaddr} 0 30000;" \
# define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
+ "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
"loadaddr=10000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
#define CONFIG_HOSTNAME M5373EVB
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
#define CONFIG_SYS_LOAD_ADDR2 0x40010007
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
+ "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
"loadaddr=0x40010000\0" \
"sbfhdr=sbfhdr.bin\0" \
"uboot=u-boot.bin\0" \
"load=tftp ${loadaddr} ${sbfhdr};" \
- "tftp " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
+ "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
"upd=run load; run prog\0" \
"prog=sf probe 0:1 1000000 3;" \
"sf erase 0 30000;" \
#define CONFIG_SYS_UBOOT_END 0x3FFFF
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
+ "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
"loadaddr=40010000\0" \
"u-boot=u-boot.bin\0" \
"load=tftp ${loadaddr) ${u-boot}\0" \
"upd=run load; run prog\0" \
- "prog=prot off 0 " MK_STR(CONFIG_SYS_UBOOT_END) \
- "; era 0 " MK_STR(CONFIG_SYS_UBOOT_END) " ;" \
+ "prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \
+ "; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \
"cp.b ${loadaddr} 0 ${filesize};" \
"save\0" \
""
#define CONFIG_SYS_LOAD_ADDR2 0x40010013
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
+ "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
"loadaddr=0x40010000\0" \
"sbfhdr=sbfhdr.bin\0" \
"uboot=u-boot.bin\0" \
"load=tftp ${loadaddr} ${sbfhdr};" \
- "tftp " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
+ "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
"upd=run load; run prog\0" \
"prog=sf probe 0:1 1000000 3;" \
"sf erase 0 30000;" \
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
+ "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
"loadaddr=0x40010000\0" \
"uboot=u-boot.bin\0" \
"load=tftp ${loadaddr} ${uboot}\0" \
"upd=run load; run prog\0" \
- "prog=prot off " MK_STR(CONFIG_SYS_FLASH_BASE) \
- " " MK_STR(CONFIG_SYS_UBOOT_END) ";" \
- "era " MK_STR(CONFIG_SYS_FLASH_BASE) " " \
- MK_STR(CONFIG_SYS_UBOOT_END) ";" \
- "cp.b ${loadaddr} " MK_STR(CONFIG_SYS_FLASH_BASE) \
+ "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
+ " " __stringify(CONFIG_SYS_UBOOT_END) ";" \
+ "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
+ __stringify(CONFIG_SYS_UBOOT_END) ";" \
+ "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
" ${filesize}; save\0" \
""
#endif
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
"then; run fitboot;else;run ubiboot;fi;"
#define CONFIG_BOOTARGS "console=ttyS0,115200n8"
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"console_nr=0\0"\
"stdin=serial\0"\
"boot_sqfs=1\0"\
"usb_dr_mode=host\0"\
"bootfile=MergerBox.fit\0"\
- "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0"\
+ "baudrate=" __stringify(CONFIG_BAUDRATE) "\0"\
"fpga=0\0"\
- "fpgadata=" MK_STR(MV_FPGA_DATA) "\0"\
- "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0"\
- "mv_kernel_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0"\
- "mv_initrd_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0"\
- "mv_dtb_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0"\
- "uboota=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0"\
- "fitaddr=" MK_STR(MV_FITADDR) "\0"\
+ "fpgadata=" __stringify(MV_FPGA_DATA) "\0"\
+ "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"\
+ "mv_kernel_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"\
+ "mv_initrd_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"\
+ "mv_dtb_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"\
+ "uboota=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"\
+ "fitaddr=" __stringify(MV_FITADDR) "\0"\
"mv_version=" U_BOOT_VERSION "\0"\
"mtdids=" MTDIDS_DEFAULT "\0"\
"mtdparts=" MTDPARTS_DEFAULT "\0"\
"i2c_speed=i2c dev 0;i2c speed 300000;i2c dev 1;i2c speed 120000\0"\
"init_sdi_tx=i2c mw 21 6 0;i2c mw 21 2 0;i2c mw 21 3 0;sleep 1;"\
"i2c mw 21 2 ff;i2c mw 21 3 3c\0"\
- "splashimage=" MK_STR(MV_SPLAH_ADDR) "\0"\
+ "splashimage=" __stringify(MV_SPLAH_ADDR) "\0"\
""
-#undef MK_STR
-#undef XMK_STR
-
/*
* FPGA
*/
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_BAUDRATE 9600
#define CONFIG_SYS_BAUDRATE_TABLE \
+++ /dev/null
-/*
- * ML2.h: ML2 specific config options
- *
- * Copyright 2002 Mind NV
- *
- * http://www.mind.be/
- *
- * Author : Peter De Schrijver (p2@mind.be)
- *
- * Derived from : other configuration header files in this tree
- *
- * This software may be used and distributed according to the terms of
- * the GNU General Public License (GPL) version 2, incorporated herein by
- * reference. Drivers based on or derived from this code fall under the GPL
- * and must retain the authorship, copyright and this license notice. This
- * file is not a complete program and may only be used when the entire
- * program is licensed under the GPL.
- *
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405 1 /* This is a PPC405 CPU */
-#define CONFIG_4xx 1 /* ...member of PPC4xx family */
-#define CONFIG_ML2 1 /* ...on a ML2 board */
-
-#define CONFIG_SYS_TEXT_BASE 0x18000000
-#define CONFIG_SYS_LDSCRIPT "board/ml2/u-boot.lds"
-
-#define CONFIG_ENV_IS_IN_FLASH 1
-
-#ifdef CONFIG_ENV_IS_IN_NVRAM
-#undef CONFIG_ENV_IS_IN_FLASH
-#else
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#undef CONFIG_ENV_IS_IN_NVRAM
-#endif
-#endif
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#if 1
-#define CONFIG_BOOTCOMMAND "bootm" /* autoboot command */
-#else
-#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
-#endif
-
-#define CONFIG_PREBOOT "fsload 0x00100000 /boot/image"
-
-#if 0
-#define CONFIG_BOOTARGS "root=/dev/nfs " \
- "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \
- "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
-#else
-#define CONFIG_BOOTARGS "root=/dev/mtdblock2 " \
- "console=ttyS0 console=tty"
-
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_KGDB
-#define CONFIG_CMD_BEDBUG
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_JFFS2
-
-#undef CONFIG_CMD_NET
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_RTC
-#undef CONFIG_CMD_PCI
-#undef CONFIG_CMD_I2C
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SYS_CLK_FREQ 50000000
-
-#define CONFIG_SPD_EEPROM 1 /* use SPD EEPROM for setup */
-
-/*
- * I2C
- */
-#define CONFIG_HARD_I2C /* I2C with hardware support */
-#define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_SPEED 400000
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-/*
- * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
- * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
- * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
- * The Linux BASE_BAUD define should match this configuration.
- * baseBaud = cpuClock/(uartDivisor*16)
- * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
- * set Linux BASE_BAUD to 403200.
- */
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
-#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
-
-#define CONFIG_SYS_BASE_BAUD (3125000*16)
-#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_BASE_BAUD
-#define CONFIG_SYS_DUART_CHAN 0
-#define CONFIG_SYS_NS16550_COM1 0xa0001003
-#define CONFIG_SYS_NS16550_COM2 0xa0011003
-#define CONFIG_SYS_NS16550_REG_SIZE -4
-#define CONFIG_SYS_NS16550 1
-#define CONFIG_SYS_INIT_CHAN1 1
-#define CONFIG_SYS_INIT_CHAN2 1
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x18000000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 196 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/* BEG ENVIRONNEMENT FLASH */
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_OFFSET 0x00050000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
-#endif
-/* END ENVIRONNEMENT FLASH */
-/*-----------------------------------------------------------------------
- * NVRAM organization
- */
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */
-
-#ifdef CONFIG_ENV_IS_IN_NVRAM
-#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
-#define CONFIG_ENV_ADDR \
- (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */
-#endif
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
-#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
-
-
-/* Configuration Port location */
-#define CONFIG_PORT_ADDR 0xF0000500
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x800000 /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for Serial Presence Detect EEPROM address
- * (to get SDRAM settings)
- */
-#define SPD_EEPROM_ADDRESS 0x50
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00080000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor0=ml2-0"
-#define MTDPARTS_DEFAULT "mtdparts=ml2-0:-@512k(jffs2)"
-*/
-
-#endif /* __CONFIG_H */
#define CONFIG_NETDEV eth0
#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
+ "netdev=" __stringify(CONFIG_NETDEV) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
"fdtaddr=400000\0" \
"console=ttyCPM0\0" \
"setbootargs=setenv bootargs " \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#undef MK_STR
-#undef XMK_STR
-
#endif /* __CONFIG_H */
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
-#define xstr(s) str(s)
-#define str(s) #s
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
"bootcmd=run flash_self\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
- "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
- " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
+ "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
" +${filesize};cp.b ${fileaddr} " \
- xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
+ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
"upd=run load update\0" \
#endif /* __CONFIG_H */
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=" CONFIG_NETDEV "\0" \
"ethprime=TSEC1\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
"fdtaddr=780000\0" \
"fdtfile=" CONFIG_FDTFILE "\0" \
"console=ttyS0\0" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#undef MK_STR
-#undef XMK_STR
-
#endif /* __CONFIG_H */
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=" CONFIG_NETDEV "\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftp $loadaddr $uboot;" \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
"fdtaddr=780000\0" \
"fdtfile=" CONFIG_FDTFILE "\0" \
"ramdiskaddr=1000000\0" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#undef MK_STR
-#undef XMK_STR
-
#endif /* __CONFIG_H */
#define CONFIG_BOOTDELAY 6
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
#define CONFIG_BOOTARGS \
"root=/dev/nfs rw" \
- " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \
- " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \
- MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \
+ " nfsroot=" __stringify(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \
+ " ip=" __stringify(CONFIG_IPADDR) ":" \
+ __stringify(CONFIG_SERVERIP) ":" \
+ __stringify(CONFIG_GATEWAYIP) ":" \
+ __stringify(CONFIG_NETMASK) ":" \
CONFIG_HOSTNAME ":" CONFIG_NETDEV ":off" \
- " console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE)
+ " console=" __stringify(CONFIG_CONSOLE) "," __stringify(CONFIG_BAUDRATE)
#define CONFIG_EXTRA_ENV_SETTINGS \
- "console=" MK_STR(CONFIG_CONSOLE) "\0" \
+ "console=" __stringify(CONFIG_CONSOLE) "\0" \
"netdev=" CONFIG_NETDEV "\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "\
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "\
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
"fdtaddr=780000\0" \
"fdtfile=" CONFIG_FDTFILE "\0"
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#undef MK_STR
-#undef XMK_STR
-
#endif
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=" CONFIG_NETDEV "\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftp $loadaddr $uboot;" \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
"fdtaddr=780000\0" \
"fdtfile=" CONFIG_FDTFILE "\0" \
"ramdiskaddr=1000000\0" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#undef MK_STR
-#undef XMK_STR
-
#endif /* __CONFIG_H */
#define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=8536ds/ramdisk.uboot\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=8536ds/mpc8536ds.dtb\0" \
- "bdev=sda3\0" \
- "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
+"netdev=eth0\0" \
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+"tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
+"consoledev=ttyS0\0" \
+"ramdiskaddr=2000000\0" \
+"ramdiskfile=8536ds/ramdisk.uboot\0" \
+"fdtaddr=c00000\0" \
+"fdtfile=8536ds/mpc8536ds.dtb\0" \
+"bdev=sda3\0" \
+"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
#define CONFIG_HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
#define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=8544ds/ramdisk.uboot\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=8544ds/mpc8544ds.dtb\0" \
- "bdev=sda3\0"
+"netdev=eth0\0" \
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+"tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
+"consoledev=ttyS0\0" \
+"ramdiskaddr=2000000\0" \
+"ramdiskfile=8544ds/ramdisk.uboot\0" \
+"fdtaddr=c00000\0" \
+"fdtfile=8544ds/mpc8544ds.dtb\0" \
+"bdev=sda3\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:ecc=off\0" \
"netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"\
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
"consoledev=ttyS1\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=ramdisk.uboot\0" \
/* Serial Port */
#define CONFIG_CONS_INDEX 1
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=fsl_ddr:ctlr_intlv=bank,ecc=off\0" \
- "netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=8572ds/ramdisk.uboot\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=8572ds/mpc8572ds.dtb\0" \
- "bdev=sda3\0"
+"hwconfig=fsl_ddr:ctlr_intlv=bank,ecc=off\0" \
+"netdev=eth0\0" \
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+"tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
+"consoledev=ttyS0\0" \
+"ramdiskaddr=2000000\0" \
+"ramdiskfile=8572ds/ramdisk.uboot\0" \
+"fdtaddr=c00000\0" \
+"fdtfile=8572ds/mpc8572ds.dtb\0" \
+"bdev=sda3\0"
#define CONFIG_HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
#ifdef ENV_DEBUG
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
- "bdev=sda3\0" \
- "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
- "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
- "maxcpus=1" \
- "eoi=mw e00400b0 0\0" \
- "iack=md e00400a0 1\0" \
- "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
+"netdev=eth0\0" \
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+"tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
+"consoledev=ttyS0\0" \
+"ramdiskaddr=2000000\0" \
+"ramdiskfile=8610hpcd/ramdisk.uboot\0" \
+"fdtaddr=c00000\0" \
+"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
+"bdev=sda3\0" \
+"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
+"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
+"maxcpus=1" \
+"eoi=mw e00400b0 0\0" \
+"iack=md e00400a0 1\0" \
+"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
"md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
"md ${a}f00 5\0" \
- "ddr1regs=setenv a e0002; run ddrreg\0" \
- "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
+"ddr1regs=setenv a e0002; run ddrreg\0" \
+"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
"md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
"md ${a}e60 1; md ${a}ef0 1d\0" \
- "guregs=setenv a e00e0; run gureg\0" \
- "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
- "mcmregs=setenv a e0001; run mcmreg\0" \
- "diuregs=md e002c000 1d\0" \
- "dium=mw e002c01c\0" \
- "diuerr=md e002c014 1\0" \
- "pmregs=md e00e1000 2b\0" \
- "lawregs=md e0000c08 4b\0" \
- "lbcregs=md e0005000 36\0" \
- "dma0regs=md e0021100 12\0" \
- "dma1regs=md e0021180 12\0" \
- "dma2regs=md e0021200 12\0" \
- "dma3regs=md e0021280 12\0" \
+"guregs=setenv a e00e0; run gureg\0" \
+"mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
+"mcmregs=setenv a e0001; run mcmreg\0" \
+"diuregs=md e002c000 1d\0" \
+"dium=mw e002c01c\0" \
+"diuerr=md e002c014 1\0" \
+"pmregs=md e00e1000 2b\0" \
+"lawregs=md e0000c08 4b\0" \
+"lbcregs=md e0005000 36\0" \
+"dma0regs=md e0021100 12\0" \
+"dma1regs=md e0021180 12\0" \
+"dma2regs=md e0021200 12\0" \
+"dma3regs=md e0021280 12\0" \
PCI_ENV \
PCIE_ENV \
DMA_ENV
#else
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
- "bdev=sda3\0"
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "netdev=eth0\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "consoledev=ttyS0\0" \
+ "ramdiskaddr=2000000\0" \
+ "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
+ "fdtaddr=c00000\0" \
+ "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
+ "bdev=sda3\0"
#endif
#define CONFIG_NFSBOOTCOMMAND \
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=your.ramdisk.u-boot\0" \
#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs"
#define CONFIG_ENV_OVERWRITE
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"console_nr=0\0" \
"console=yes\0" \
"stdout=serial\0" \
"stderr=serial\0" \
"fpga=0\0" \
- "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
- "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
- "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \
- "script_addr2=" MK_STR(MV_SCRIPT_ADDR2) "\0" \
- "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
- "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
- "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
- "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
- "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
- "mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0" \
- "mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \
- "dtb_name=" MK_STR(MV_DTB_NAME) "\0" \
- "mv_scratch_addr=" MK_STR(MV_SCRATCH_ADDR) "\0" \
- "mv_scratch_length=" MK_STR(MV_SCRATCH_LENGTH) "\0" \
+ "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \
+ "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \
+ "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \
+ "script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0" \
+ "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \
+ "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \
+ "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \
+ "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \
+ "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \
+ "mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0" \
+ "mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0" \
+ "dtb_name=" __stringify(MV_DTB_NAME) "\0" \
+ "mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0" \
+ "mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0" \
"mv_version=" U_BOOT_VERSION "\0" \
- "dhcp_client_id=" MK_STR(MV_CI) "\0" \
- "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \
+ "dhcp_client_id=" __stringify(MV_CI) "\0" \
+ "dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0" \
"netretry=no\0" \
"use_static_ipaddr=no\0" \
"static_ipaddr=192.168.90.10\0" \
"sensor_cnt=1\0" \
""
-#undef XMK_STR
-#undef MK_STR
-
/*
* IPB Bus clocking configuration.
*/
#define CONFIG_EXTRA_ENV_SETTINGS \
"console_nr=0\0" \
- "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" \
+ "baudrate=" __stringify(CONFIG_BAUDRATE) "\0" \
"stdin=serial\0" \
"stdout=serial\0" \
"stderr=serial\0" \
"fpga=0\0" \
- "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
- "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
- "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \
- "script_addr2=" MK_STR(MV_SCRIPT_ADDR2) "\0" \
- "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
- "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
- "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
- "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
- "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
- "mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0" \
- "mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \
- "dtb_name=" MK_STR(MV_DTB_NAME) "\0" \
+ "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \
+ "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \
+ "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \
+ "script_addr2=" __stringify(MV_SCRIPT_ADDR2) "\0" \
+ "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \
+ "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \
+ "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \
+ "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \
+ "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \
+ "mv_dtb_addr=" __stringify(MV_DTB_ADDR) "\0" \
+ "mv_dtb_addr_ram=" __stringify(MV_DTB_ADDR_RAM) "\0" \
+ "dtb_name=" __stringify(MV_DTB_NAME) "\0" \
"mv_version=" U_BOOT_VERSION "\0" \
"dhcp_client_id=" MV_CI "\0" \
"dhcp_vendor-class-identifier=" MV_VCI "\0" \
#define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" \
" allocate=6M"
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"console_nr=0\0" \
"console=no\0" \
"stdout=serial\0" \
"stderr=serial\0" \
"fpga=0\0" \
- "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \
- "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \
- "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \
- "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \
- "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \
- "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \
- "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \
- "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \
- "mv_scratch_addr=" MK_STR(MV_SCRATCH_ADDR) "\0" \
- "mv_scratch_length=" MK_STR(MV_SCRATCH_LENGTH) "\0" \
+ "fpgadata=" __stringify(MV_FPGA_DATA) "\0" \
+ "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0" \
+ "mv_kernel_addr=" __stringify(MV_KERNEL_ADDR) "\0" \
+ "mv_kernel_addr_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0" \
+ "script_addr=" __stringify(MV_SCRIPT_ADDR) "\0" \
+ "mv_initrd_addr=" __stringify(MV_INITRD_ADDR) "\0" \
+ "mv_initrd_addr_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0" \
+ "mv_initrd_length=" __stringify(MV_INITRD_LENGTH) "\0" \
+ "mv_scratch_addr=" __stringify(MV_SCRATCH_ADDR) "\0" \
+ "mv_scratch_length=" __stringify(MV_SCRATCH_LENGTH) "\0" \
"mv_version=" U_BOOT_VERSION "\0" \
- "dhcp_client_id=" MK_STR(MV_CI) "\0" \
- "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \
+ "dhcp_client_id=" __stringify(MV_CI) "\0" \
+ "dhcp_vendor-class-identifier=" __stringify(MV_VCI) "\0" \
"netretry=no\0" \
"use_static_ipaddr=no\0" \
"static_ipaddr=192.168.0.101\0" \
"netboot=no\0" \
""
-#undef XMK_STR
-#undef MK_STR
-
/*
* IPB Bus clocking configuration.
*/
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
-#define CONFIG_SERIAL_MULTI /* Enable both serial ports */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
#define CONFIG_SYS_BAUDRATE_TABLE \
#define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \
- "hwconfig=" MK_STR(CONFIG_DEF_HWCONFIG) "\0" \
+ "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \
"netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"loadaddr=1000000\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
"tftpflash=tftpboot $loadaddr $uboot && " \
"protect off $ubootaddr +$filesize && " \
"erase $ubootaddr +$filesize && " \
#define CONFIG_NS16550_MIN_FUNCTIONS
#endif
-#define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
#define CONFIG_SYS_BAUDRATE_TABLE \
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "loadaddr=1000000\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "loadaddr=1000000\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=rootfs.ext2.gz.uboot\0" \
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#define CONFIG_SERIAL_MULTI 1 /* Enable both serial ports */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */
#define CONFIG_SYS_BAUDRATE_TABLE \
#define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \
- "perf_mode=performance\0" \
+"perf_mode=performance\0" \
"hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \
"usb1:dr_mode=host,phy_type=ulpi\0" \
- "netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
- "satabootcmd=setenv bootargs root=/dev/$bdev rw " \
+"netdev=eth0\0" \
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+"tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+"satabootcmd=setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=p2020ds/ramdisk.uboot\0" \
- "fdtaddr=c00000\0" \
- "othbootargs=cache-sram-size=0x10000\0" \
- "fdtfile=p2020ds/p2020ds.dtb\0" \
- "bdev=sda3\0" \
- "partition=scsi 0:0\0"
+"consoledev=ttyS0\0" \
+"ramdiskaddr=2000000\0" \
+"ramdiskfile=p2020ds/ramdisk.uboot\0" \
+"fdtaddr=c00000\0" \
+"othbootargs=cache-sram-size=0x10000\0" \
+"fdtfile=p2020ds/p2020ds.dtb\0" \
+"bdev=sda3\0" \
+"partition=scsi 0:0\0"
#define CONFIG_HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
"bank_intlv=cs0_cs1\0" \
"netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
"tftpflash=tftpboot $loadaddr $uboot && " \
"protect off $ubootaddr +$filesize && " \
"erase $ubootaddr +$filesize && " \
"protect on $ubootaddr +$filesize && " \
"cmp.b $loadaddr $ubootaddr $filesize\0" \
"consoledev=ttyS0\0" \
- "usb_phy_type=" MK_STR(__USB_PHY_TYPE) "\0" \
+ "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
"usb_dr_mode=host\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=p2041rdb/ramdisk.uboot\0" \
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
*/
#if 1
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
+++ /dev/null
-/*
- * (C) Copyright 2002,2003 Motorola,Inc.
- * Xianghua Xiao <X.Xiao@motorola.com>
- *
- * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
- * Added support for Wind River SBC8540 board
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * sbc8540 board configuration file.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Top level Makefile configuration choices
- */
-#ifdef CONFIG_66
-#define CONFIG_PCI_66
-#endif
-
-#define TSEC_DEBUG
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
-#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
-
-#define CONFIG_SYS_TEXT_BASE 0xfffc0000
-
-
-#define CONFIG_CPM2 1 /* has CPM2 */
-
-#define CONFIG_SBC8540 1 /* configuration for SBC8560 board */
-#define CONFIG_MPC8540 1
-
-#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific (supplement) */
-
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
-#undef CONFIG_PCI /* pci ethernet support */
-#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
-
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-
-#define CONFIG_ENV_OVERWRITE
-
-/* Using Localbus SDRAM to emulate flash before we can program the flash,
- * normally you need a flash-boot image(u-boot.bin), if so undef this.
- */
-#undef CONFIG_RAM_AS_FLASH
-
-#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */
- #define CONFIG_SYS_CLK_FREQ 66000000 /* sysclk for MPC85xx */
-#else
- #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
-#endif
-
-/* below can be toggled for performance analysis. otherwise use default */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#undef CONFIG_BTB /* toggle branch predition */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
-
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
-#define CONFIG_SYS_MEMTEST_END 0x00400000
-
-#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
- defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
- defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
-#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
-#endif
-
-#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
-
-/* DDR Setup */
-#define CONFIG_FSL_DDR1
-#undef CONFIG_FSL_DDR_INTERACTIVE
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#undef CONFIG_DDR_SPD
-
-#if defined(CONFIG_MPC85xx_REV1)
-#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
-#endif
-
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 2
-
-/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS 0x55 /* CTLR 0 DIMM 0 */
-
-#undef CONFIG_CLOCKS_IN_MHZ
-
-#if defined(CONFIG_RAM_AS_FLASH)
- #define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
- #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
- #define CONFIG_SYS_BR0_PRELIM 0xf8000801 /* port size 8bit */
- #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */
-#else /* Boot from real Flash */
- #define CONFIG_SYS_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
- #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
- #define CONFIG_SYS_BR0_PRELIM 0xff800801 /* port size 8bit */
- #define CONFIG_SYS_OR0_PRELIM 0xff800ff7 /* 8MB Flash */
-#endif
-#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
-
-/* local bus definitions */
-#define CONFIG_SYS_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */
-#define CONFIG_SYS_OR1_PRELIM 0xfc000ff7
-
-#define CONFIG_SYS_BR2_PRELIM 0x00000000 /* CS2 not used */
-#define CONFIG_SYS_OR2_PRELIM 0x00000000
-
-#define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
-#define CONFIG_SYS_OR3_PRELIM 0xfc000cc1
-
-#if defined(CONFIG_RAM_AS_FLASH)
- #define CONFIG_SYS_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */
-#else
- #define CONFIG_SYS_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */
-#endif
-#define CONFIG_SYS_OR4_PRELIM 0xfc000cc1
-
-#define CONFIG_SYS_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */
-#if 1
- #define CONFIG_SYS_OR5_PRELIM 0xff000ff7
-#else
- #define CONFIG_SYS_OR5_PRELIM 0xff0000f0
-#endif
-
-#define CONFIG_SYS_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */
-#define CONFIG_SYS_OR6_PRELIM 0xfc000ff7
-#define CONFIG_SYS_LBC_LCRR 0x00030002 /* local bus freq */
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-#define CONFIG_SYS_LBC_LSRT 0x20000000
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
-#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
-#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
-#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
-#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
-
-/* just hijack the MOT BCSR def for SBC8560 misc devices */
-#define CONFIG_SYS_BCSR ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000)
-/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
-
-/* Serial Port */
-#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else */
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#if 0
-#define CONFIG_SYS_NS16550_CLK 1843200 /* get_bus_freq(0) */
-#else
-#define CONFIG_SYS_NS16550_CLK 264000000 /* get_bus_freq(0) */
-#endif
-
-#define CONFIG_BAUDRATE 9600
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#if 0
-#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000)
-#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000)
-#else
-/* SBC8540 uses internal COMM controller */
-#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004500)
-#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_CCSRBAR & 0xfff00000)+0x00004600)
-#endif
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/*
- * I2C
- */
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-
-#define CONFIG_SYS_PCI_MEM_BASE 0xC0000000
-#define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000
-#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
-
-#if defined(CONFIG_TSEC_ENET) /* TSEC Ethernet port */
-
-# define CONFIG_MPC85xx_TSEC1
-# define CONFIG_MPC85xx_TSEC1_NAME "TSEC0"
-# define CONFIG_MII 1 /* MII PHY management */
-# define TSEC1_PHY_ADDR 25
-# define TSEC1_PHYIDX 0
-/* Options are: TSEC0 */
-# define CONFIG_ETHPRIME "TSEC0"
-
-
-#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
-
- #undef CONFIG_ETHER_NONE /* define if ether on something else */
- #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */
- #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
-
- #if (CONFIG_ETHER_INDEX == 2)
- /*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - Select bus for bd/buffers
- * - Full duplex
- */
- #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
- #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
- #define CONFIG_SYS_CPMFCR_RAMTYPE 0
- #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
-
- #elif (CONFIG_ETHER_INDEX == 3)
- /* need more definitions here for FE3 */
- #endif /* CONFIG_ETHER_INDEX */
-
- #define CONFIG_MII /* MII PHY management */
- #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
- /*
- * GPIO pins used for bit-banged MII communications
- */
- #define MDIO_PORT 2 /* Port C */
- #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
- #define MDC_DECLARE MDIO_DECLARE
-
- #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
- #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
- #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
-
- #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
- else iop->pdat &= ~0x00400000
-
- #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
- else iop->pdat &= ~0x00200000
-
- #define MIIDELAY udelay(1)
-
-#endif
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#if 0
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */
-#endif
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if 0
-/* XXX This doesn't work and I don't want to fix it */
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
- #define CONFIG_SYS_RAMBOOT
-#else
- #undef CONFIG_SYS_RAMBOOT
-#endif
-#endif
-
-/* Environment */
-#if !defined(CONFIG_SYS_RAMBOOT)
- #if defined(CONFIG_RAM_AS_FLASH)
- #define CONFIG_ENV_IS_NOWHERE
- #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000)
- #define CONFIG_ENV_SIZE 0x2000
- #else
- #define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
- #define CONFIG_ENV_SIZE 0x2000 /* CONFIG_ENV_SECT_SIZE */
- #endif
-#else
- #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
- #define CONFIG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=192.168.0.251:/tftpboot ip=192.168.0.105:192.168.0.251::255.255.255.0:sbc8560:eth0:off console=ttyS0,9600"
-/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
-#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
-#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_REGINFO
-
-#if defined(CONFIG_PCI)
- #define CONFIG_CMD_PCI
-#endif
-
-#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
- #define CONFIG_CMD_MII
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#endif
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "SBC8540=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
- #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
- #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/*Note: change below for your network setting!!! */
-#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
-# define CONFIG_ETHADDR 00:vv:ww:xx:yy:8a
-# define CONFIG_HAS_ETH1
-# define CONFIG_ETH1ADDR 00:vv:ww:xx:yy:8b
-# define CONFIG_HAS_ETH2
-# define CONFIG_ETH2ADDR 00:vv:ww:xx:yy:8c
-#endif
-
-#define CONFIG_SERVERIP YourServerIP
-#define CONFIG_IPADDR YourTargetIP
-#define CONFIG_GATEWAYIP YourGatewayIP
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_HOSTNAME SBC8560
-#define CONFIG_ROOTPATH "YourRootPath"
-#define CONFIG_BOOTFILE "YourImageName"
-
-#endif /* __CONFIG_H */
#define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;" \
"bootm $loadaddr - $fdtaddr"
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=" CONFIG_NETDEV "\0" \
"ethprime=TSEC1\0" \
"uboot=" CONFIG_UBOOTPATH "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
+ " $filesize\0" \
"fdtaddr=ae0000\0" \
"fdtfile=" CONFIG_FDTFILE "\0" \
"console=ttyS0\0" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr $ramdiskaddr $fdtaddr"
-#undef MK_STR
-#undef XMK_STR
-
#endif /* __CONFIG_H */
* IDE/ATA stuff
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
+#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */
#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
#define CONFIG_IDE_LED 1 /* LED for ide supported */
#define CONFIG_IDE_RESET 1 /* reset for ide supported */
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 1 /* default console is on PSC1 */
-#define CONFIG_SERIAL_MULTI 1 /* support multiple consoles */
#define CONFIG_PSC_CONSOLE2 6 /* second console is on PSC6 */
#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
/* USB support (currently only works with D-cache off) */
#define CONFIG_USB_OHCI
+#define CONFIG_USB_OHCI_S3C24XX
#define CONFIG_USB_KEYBOARD
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
/*
* UART
*/
-#define CONFIG_SERIAL_MULTI
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_ADDMISC "addmisc=setenv bootargs ${bootargs}\0"
#endif
-#define xstr(s) str(s)
-#define str(s) #s
-
/*
* General common environment variables shared on all AMCC eval boards
*/
#define CONFIG_AMCC_DEF_ENV \
- "netdev=" xstr(CONFIG_USE_NETDEV) "\0" \
+ "netdev=" __stringify(CONFIG_USE_NETDEV) "\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/ram rw\0" \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"addtty=setenv bootargs ${bootargs}" \
- " console=" xstr(CONFIG_USE_TTY) ",${baudrate}\0" \
+ " console=" __stringify(CONFIG_USE_TTY) ",${baudrate}\0" \
CONFIG_ADDMISC \
"initrd_high=30000000\0" \
"kernel_addr_r=1000000\0" \
"fdt_addr_r=1800000\0" \
"ramdisk_addr_r=1900000\0" \
- "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
- "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
- "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \
CONFIG_AMCC_DEF_ENV_ROOTPATH
/*
"net_self=run net_self_load;" \
"run ramargs addip addtty addmisc;" \
"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0" \
- "fdt_file=" xstr(CONFIG_HOSTNAME) "/" xstr(CONFIG_HOSTNAME) ".dtb\0"
+ "fdt_file=" __stringify(CONFIG_HOSTNAME) "/" __stringify(CONFIG_HOSTNAME) ".dtb\0"
/*
* Default environment for arch/ppc booting,
"bootm ${kernel_addr_r}\0"
#define CONFIG_AMCC_DEF_ENV_NOR_UPD \
- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
"load=tftp 200000 ${u-boot}\0" \
- "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \
- "era " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \
- "cp.b ${fileaddr} " xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
+ "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \
+ "era " __stringify(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \
+ "cp.b ${fileaddr} " __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
"upd=run load update\0" \
#define CONFIG_AMCC_DEF_ENV_NAND_UPD \
- "u-boot-nand=" xstr(CONFIG_HOSTNAME) "/u-boot-nand.bin\0" \
+ "u-boot-nand=" __stringify(CONFIG_HOSTNAME) "/u-boot-nand.bin\0"\
"nload=tftp 200000 ${u-boot-nand}\0" \
"nupdate=nand erase 0 100000;nand write 200000 0 100000\0" \
"nupd=run nload nupdate\0"
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */
+#define CONFIG_SYS_PSC3
#if CONFIG_PSC_CONSOLE != 3
#error CONFIG_PSC_CONSOLE must be 3
#endif
#ifndef _CONFIG_ASTRO_MCF5373L_H
#define _CONFIG_ASTRO_MCF5373L_H
+#include <linux/stringify.h>
+
/*
* set the card type to actually compile for; either of
* the possibilities listed below has to be used!
* u-boot: 'set' command
*/
-#define _QUOTEME(x) #x
-#define QUOTEME(x) _QUOTEME(x)
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"loaderversion=11\0" \
- "card_id="QUOTEME(ASTRO_ID)"\0" \
+ "card_id="__stringify(ASTRO_ID)"\0" \
"alterafile=0\0" \
"xilinxfile=0\0" \
"xilinxload=imxtract 0x540000 $xilinxfile 0x41000000&&"\
/* Address and size of Primary Environment Sector */
#define CONFIG_ENV_SIZE 0x10000
-#define xstr(s) str(s)
-#define str(s) #s
-
#define CONFIG_EXTRA_ENV_SETTINGS \
- "monitor_base=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
+ "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
"update=" \
"protect off ${monitor_base} +${filesize};" \
"erase ${monitor_base} +${filesize};" \
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
*/
#define CONFIG_PXA_SERIAL
#define CONFIG_STUART 1
+#define CONFIG_CONS_INDEX 2
#define CONFIG_BAUDRATE 115200
/*
#define BOOT_ENV_SETTINGS \
"update=tftpboot $(loadaddr) u-boot.ldr;" \
- "sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \
+ "sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
"sf erase 0 0x30000;" \
"sf write $(loadaddr) 0 $(filesize)" \
"flashboot=sf read 0x1000000 0x30000 0x320000;" \
#define BOOT_ENV_SETTINGS \
"update=tftpboot $(loadaddr) u-boot.ldr;" \
- "sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \
+ "sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
"sf erase 0 0x30000;" \
"sf write $(loadaddr) 0 $(filesize)" \
"flashboot=sf read 0x1000000 0x30000 0x320000;" \
# define CONFIG_BAUDRATE 57600
#endif
#ifndef CONFIG_DEBUG_EARLY_SERIAL
-# define CONFIG_SERIAL_MULTI
# define CONFIG_SYS_BFIN_UART
#endif
#endif
#define CONFIG_BOOTARGS \
"root=" CONFIG_BOOTARGS_ROOT " " \
- "clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \
+ "clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \
"earlyprintk=" \
"serial," \
- "uart" MK_STR(CONFIG_UART_CONSOLE) "," \
- MK_STR(CONFIG_BAUDRATE) " " \
+ "uart" __stringify(CONFIG_UART_CONSOLE) "," \
+ __stringify(CONFIG_BAUDRATE) " " \
CONFIG_BOOTARGS_VIDEO \
- "console=ttyBF" MK_STR(CONFIG_UART_CONSOLE) "," MK_STR(CONFIG_BAUDRATE)
+ "console=ttyBF" __stringify(CONFIG_UART_CONSOLE) "," \
+ __stringify(CONFIG_BAUDRATE)
#if defined(CONFIG_CMD_NAND)
# define NAND_ENV_SETTINGS \
"nandargs=set bootargs " CONFIG_BOOTARGS "\0" \
# define CONFIG_BFIN_SPI_IMG_SIZE 0x40000
# endif
# define UBOOT_ENV_UPDATE \
- "sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \
- "sf erase 0 " MK_STR(CONFIG_BFIN_SPI_IMG_SIZE) ";" \
+ "sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
+ "sf erase 0 " __stringify(CONFIG_BFIN_SPI_IMG_SIZE) ";" \
"sf write $(loadaddr) 0 $(filesize)"
# endif
# elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
#define CONFIG_BOOTCOMMAND "run ramboot"
#define CONFIG_BOOTARGS \
"root=/dev/mtdblock0 rw " \
- "clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \
+ "clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \
"earlyprintk=" \
"serial," \
- "uart" MK_STR(CONFIG_UART_CONSOLE) "," \
- MK_STR(CONFIG_BAUDRATE) " " \
- "console=ttyBF0," MK_STR(CONFIG_BAUDRATE)
+ "uart" __stringify(CONFIG_UART_CONSOLE) "," \
+ __stringify(CONFIG_BAUDRATE) " " \
+ "console=ttyBF0," __stringify(CONFIG_BAUDRATE)
#if defined(CONFIG_CMD_NET)
# if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
"eeprom write $(loadaddr) 0x0 $(filesize)"
# else
# define UBOOT_ENV_UPDATE \
- "sf probe " MK_STR(BFIN_BOOT_SPI_SSEL) ";" \
+ "sf probe " __stringify(BFIN_BOOT_SPI_SSEL) ";" \
"sf erase 0 0x40000;" \
"sf write $(loadaddr) 0 $(filesize)"
# endif
*/
#define CONFIG_BOOTARGS \
"root=/dev/mtdblock0 rw " \
- "clkin_hz=" MK_STR(CONFIG_CLKIN_HZ) " " \
+ "clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \
"earlyprintk=serial,uart0," \
- MK_STR(CONFIG_BAUDRATE) " " \
- "console=ttyBF0," MK_STR(CONFIG_BAUDRATE) " "
+ __stringify(CONFIG_BAUDRATE) " " \
+ "console=ttyBF0," __stringify(CONFIG_BAUDRATE) " "
/* Convenience env variables & commands.
* Reserve kernstart = 0x20000 = 128 kB for U-Boot.
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
/* Room required on the stack for the environment data */
#define CONFIG_ENV_SIZE FLASH_MAX_SECTOR_SIZE
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
+
/*
* Amount of flash used for environment:
* We don't know which end has the small erase blocks so we use the penultimate
/*
* Default environment settings
*/
-#define xstr(s) str(s)
-#define str(s) #s
#define DVN4XX_UBOOT_ADDR_R_RAM 0x80000000
/* (DVN4XX_UBOOT_ADDR_R_RAM + CONFIG_SYS_NAND_PAGE_SIZE) */
#define DVN4XX_UBOOT_ADDR_R_UBOOT 0x80003800
#define CONFIG_EXTRA_ENV_SETTINGS \
- "u_boot_addr_r=" xstr(DVN4XX_UBOOT_ADDR_R_RAM) "\0" \
- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.ubl\0" \
+ "u_boot_addr_r=" __stringify(DVN4XX_UBOOT_ADDR_R_RAM) "\0" \
+ "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.ubl\0" \
"load=tftp ${u_boot_addr_r} ${u-boot}\0" \
- "pagesz=" xstr(CONFIG_SYS_NAND_PAGE_SIZE) "\0" \
+ "pagesz=" __stringify(CONFIG_SYS_NAND_PAGE_SIZE) "\0" \
"writeheader=nandrbl rbl;nand erase 20000 ${pagesz};" \
"nand write ${u_boot_addr_r} 20000 ${pagesz};" \
"nandrbl uboot\0" \
"writenand_spl=nandrbl rbl;nand erase 0 3000;" \
- "nand write " xstr(DVN4XX_UBOOT_ADDR_R_NAND_SPL) \
+ "nand write " __stringify(DVN4XX_UBOOT_ADDR_R_NAND_SPL) \
" 0 3000;nandrbl uboot\0" \
"writeuboot=nandrbl uboot;" \
- "nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
- xstr(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE) \
- ";nand write " xstr(DVN4XX_UBOOT_ADDR_R_UBOOT) \
- " " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
- xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
+ "nand erase " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " "\
+ __stringify(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE) \
+ ";nand write " __stringify(DVN4XX_UBOOT_ADDR_R_UBOOT) \
+ " " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
+ __stringify(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
"update=run load writenand_spl writeuboot\0" \
"bootcmd=run net_nfs\0" \
"rootpath=/opt/eldk-arm/arm\0" \
"rootpath=/opt/eldk-arm/arm\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
- "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage \0" \
+ "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage \0" \
"kernel_addr_r=80600000\0" \
"load_kernel=tftp ${kernel_addr_r} ${bootfile}\0" \
"ubi_load_kernel=ubi part ubi 2048;ubifsmount ${img_volume};" \
"ubifsload ${kernel_addr_r} boot/uImage\0" \
- "fit_addr_r=" xstr(CONFIG_BOARD_IMG_ADDR_R) "\0" \
- "img_addr_r=" xstr(CONFIG_BOARD_IMG_ADDR_R) "\0" \
- "img_file=" xstr(CONFIG_HOSTNAME) "/ait.itb\0" \
+ "fit_addr_r=" __stringify(CONFIG_BOARD_IMG_ADDR_R) "\0" \
+ "img_addr_r=" __stringify(CONFIG_BOARD_IMG_ADDR_R) "\0" \
+ "img_file=" __stringify(CONFIG_HOSTNAME) "/ait.itb\0" \
"header_addr=20000\0" \
"img_writeheader=nandrbl rbl;" \
"nand erase ${header_addr} ${pagesz};" \
"img_writespl=nandrbl rbl;nand erase 0 3000;" \
"nand write ${img_addr_r} 0 3000;nandrbl uboot\0" \
"img_writeuboot=nandrbl uboot;" \
- "nand erase " xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
- xstr(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE) \
+ "nand erase " __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " "\
+ __stringify(CONFIG_SYS_NAND_U_BOOT_ERA_SIZE) \
";nand write ${img_addr_r} " \
- xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
- xstr(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
+ __stringify(CONFIG_SYS_NAND_U_BOOT_OFFS) " " \
+ __stringify(CONFIG_SYS_NAND_U_BOOT_SIZE) "\0" \
"img_writedfenv=ubi part ubi 2048;" \
"ubi write ${img_addr_r} default ${filesize}\0" \
"img_volume=rootfs1\0" \
*/
#define CONFIG_PXA_SERIAL
#define CONFIG_FFUART 1
+#define CONFIG_CONS_INDEX 3
#define CONFIG_BAUDRATE 115200
/*
/*-----------------------------------------------------------------------
* Serial Configuration
*/
-#define CONFIG_SERIAL_MULTI
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION /* Experimental */
+#define CONFIG_CMD_CBFS
+#define CONFIG_CMD_EXT4
+#define CONFIG_CMD_EXT4_WRITE
/*-----------------------------------------------------------------------
* Video Configuration
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
"bank_intlv=cs0_cs1;" \
- "usb1:dr_mode=host,phy_type=" MK_STR(__USB_PHY_TYPE) "\0"\
+ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
"netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \
+ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+ "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
"tftpflash=tftpboot $loadaddr $uboot && " \
"protect off $ubootaddr +$filesize && " \
"erase $ubootaddr +$filesize && " \
/*-----------------------------------------------------------------------
* Serial Configuration
*/
-#define CONFIG_SERIAL_MULTI
#define CONFIG_CONS_INDEX 1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
* Default environment and default scripts
* to update uboot and load kernel
*/
-#define xstr(s) str(s)
-#define str(s) #s
#define CONFIG_HOSTNAME ea20
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=c0000014\0" \
"memory=32M\0" \
"kernel_addr_r=c0700000\0" \
- "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
- "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
- "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/image.ext2\0" \
+ "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/image.ext2\0" \
"flash_self=run ramargs addip addtty addmtd addmisc addmem;" \
"bootm ${kernel_addr_r}\0" \
"flash_nfs=run nfsargs addip addtty addmtd addmisc addmem;" \
"net_nandrw=tftp ${kernel_addr_r} ${bootfile}; run nandrwargs" \
" addip addtty addmtd addmisc addmem;" \
"clrlogo;bootm ${kernel_addr_r}\0" \
- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
"load_magic=if sf probe 0;then sf " \
"read c0000000 0x10000 0x60000;fi\0" \
"load_nand=ubi part nand0,${as};ubifsmount rootfs;" \
#define CONFIG_DEFAULT_SETTINGS_ADDR (CONFIG_ENV_ADDR_REDUND + \
CONFIG_ENV_SECT_SIZE)
-#define xstr(s) str(s)
-#define str(s) #s
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"u-boot_addr_r=c0000000\0" \
- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
"load=tftp ${u-boot_addr_r} ${u-boot}\0" \
- "update=protect off " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize};"\
- "erase " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
- "cp.b ${u-boot_addr_r} " xstr(CONFIG_SYS_FLASH_BASE) \
+ "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};"\
+ "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
+ "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \
" ${filesize};" \
- "protect on " xstr(CONFIG_SYS_FLASH_BASE) " +${filesize}\0"\
+ "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0"\
"netdev=eth0\0" \
"rootpath=/opt/eldk-arm/arm\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"kernel_addr_r=c0700000\0" \
"fdt_addr_r=c0600000\0" \
"ramdisk_addr_r=c0b00000\0" \
- "fdt_file=" xstr(CONFIG_HOSTNAME) "/" \
- xstr(CONFIG_HOSTNAME) ".dtb\0" \
- "kernel_file=" xstr(CONFIG_HOSTNAME) "/uImage \0" \
+ "fdt_file=" __stringify(CONFIG_HOSTNAME) "/" \
+ __stringify(CONFIG_HOSTNAME) ".dtb\0" \
+ "kernel_file=" __stringify(CONFIG_HOSTNAME) "/uImage \0" \
"nand_ld_ramdsk=nand read ${ramdisk_addr_r} 320000 400000\0" \
"nand_ld_kernel=nand read ${kernel_addr_r} 20000 300000\0" \
"nand_ld_fdt=nand read ${fdt_addr_r} 0 2000\0" \
* Default environment and default scripts
* to update uboot and load kernel
*/
-#define xstr(s) str(s)
-#define str(s) #s
#define CONFIG_HOSTNAME flea3
#define CONFIG_EXTRA_ENV_SETTINGS \
":${hostname}:${netdev}:off panic=1\0" \
"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
"addip=if test -n ${ipdyn};then run addip_dyn;" \
- "else run addip_sta;fi\0" \
+ "else run addip_sta;fi\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"addtty=setenv bootargs ${bootargs}" \
" console=ttymxc2,${baudrate}\0" \
"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
"loadaddr=80800000\0" \
"kernel_addr_r=80800000\0" \
- "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
- "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
- "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \
"flash_self=run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
"run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
"else echo Images not loades;fi\0" \
- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
- "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
+ "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
"update=protect off ${uboot_addr} +40000;" \
"erase ${uboot_addr} +40000;" \
"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Thomas.Lange@corelatus.se
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * This file contains the configuration parameters for the gth2 board.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
-#define CONFIG_GTH2 1
-#define CONFIG_SOC_AU1X00 1 /* alchemy series cpu */
-
-#define CONFIG_SOC_AU1000 1
-
-#define CONFIG_MISC_INIT_R 1
-
-#define CONFIG_ETHADDR DE:AD:BE:EF:01:02 /* Ethernet address */
-
-#define CONFIG_BOOTDELAY 1 /* autoboot after 1 seconds */
-
-#define CONFIG_ENV_OVERWRITE 1 /* Allow change of ethernet address */
-
-#define CONFIG_BOOT_RETRY_TIME 5 /* Retry boot in 5 secs */
-
-#define CONFIG_RESET_TO_RETRY 1 /* If timeout waiting for command, perform a reset */
-
-#define CONFIG_BAUDRATE 115200
-
-/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
-
-/* Only interrupt boot if space is pressed */
-/* If a long serial cable is connected but */
-/* other end is dead, garbage will be read */
-#define CONFIG_AUTOBOOT_KEYED 1
-#define CONFIG_AUTOBOOT_PROMPT \
- "Press space to abort autoboot in %d second\n", bootdelay
-#define CONFIG_AUTOBOOT_DELAY_STR "d"
-#define CONFIG_AUTOBOOT_STOP_STR " "
-
-#define CONFIG_TIMESTAMP /* Print image info with timestamp */
-#define CONFIG_BOOTARGS "panic=1"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "addmisc=setenv bootargs $(bootargs) " \
- "ethaddr=$(ethaddr) \0" \
- "netboot=bootp;run addmisc;bootm\0" \
- ""
-
-/* Boot from Compact flash partition 2 as default */
-#define CONFIG_BOOTCOMMAND "ide reset;disk 0x81000000 0:2;run addmisc;bootm"
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_IDE
-#define CONFIG_CMD_DHCP
-
-#undef CONFIG_CMD_BDI
-#undef CONFIG_CMD_BEDBUG
-#undef CONFIG_CMD_ELF
-#undef CONFIG_CMD_FAT
-#undef CONFIG_CMD_FLASH
-#undef CONFIG_CMD_FPGA
-#undef CONFIG_CMD_LOADB
-#undef CONFIG_CMD_LOADS
-#undef CONFIG_CMD_MII
-#undef CONFIG_CMD_NFS
-#undef CONFIG_CMD_SAVEENV
-#undef CONFIG_CMD_SOURCE
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "GTH2 # " /* Monitor Command Prompt */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args*/
-
-#define CONFIG_SYS_MALLOC_LEN 128*1024
-
-#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
-
-#define CONFIG_SYS_MHZ 500
-
-#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
-
-#define CONFIG_SYS_HZ 1000
-
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
-
-#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
-
-#define CONFIG_SYS_MEMTEST_START 0x80100000
-#define CONFIG_SYS_MEMTEST_END 0x83000000
-
-#define CONFIG_HW_WATCHDOG 1
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */
-
-#define PHYS_FLASH 0xbfc00000 /* Flash Bank #1 */
-
-/* The following #defines are needed to get flash environment right */
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (192 << 10)
-
-#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
-
-/* We boot from this flash, selected with dip switch */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH
-
-/* timeout values are in ticks */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */
-
-#define CONFIG_ENV_IS_NOWHERE 1
-
-/* Address and size of Primary Environment Sector */
-#define CONFIG_ENV_ADDR 0xB0030000
-#define CONFIG_ENV_SIZE 0x10000
-
-#define CONFIG_FLASH_16BIT
-
-#define CONFIG_NR_DRAM_BANKS 2
-
-
-#define CONFIG_MEMSIZE_IN_BYTES
-
-/*---ATA PCMCIA ------------------------------------*/
-#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x4000000 /* Offset to slot 1 FIXME!!! */
-
-#define CONFIG_SYS_PCMCIA_MEM_ADDR 0x20000000
-#define CONFIG_SYS_PCMCIA_IO_BASE 0x28000000
-#define CONFIG_SYS_PCMCIA_ATTR_BASE 0x30000000
-
-#define CONFIG_PCMCIA_SLOT_A
-
-#define CONFIG_ATAPI 1
-#define CONFIG_MAC_PARTITION 1
-
-/* We run CF in "true ide" mode or a harddrive via pcmcia */
-#define CONFIG_IDE_PCMCIA 1
-
-/* We only support one slot for now */
-#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
-#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
-
-#undef CONFIG_IDE_LED /* LED for ide not supported */
-#undef CONFIG_IDE_RESET /* reset for ide not supported */
-
-#define CONFIG_SYS_ATA_IDE0_OFFSET 0
-
-#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_IO_BASE
-
-/* Offset for data I/O */
-#define CONFIG_SYS_ATA_DATA_OFFSET 0
-
-/* Offset for normal register accesses */
-#define CONFIG_SYS_ATA_REG_OFFSET 0
-
-/* Offset for alternate registers */
-#define CONFIG_SYS_ATA_ALT_OFFSET 0x0200
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_DCACHE_SIZE 16384
-#define CONFIG_SYS_ICACHE_SIZE 16384
-#define CONFIG_SYS_CACHELINE_SIZE 32
-
-#define GPIO_CACONFIG (1<<0)
-#define GPIO_DPACONFIG (1<<6)
-#define GPIO_ERESET (1<<11)
-#define GPIO_EEDQ (1<<17)
-#define GPIO_WDI (1<<18)
-#define GPIO_RJ1LY (1<<22)
-#define GPIO_RJ1LG (1<<23)
-#define GPIO_LEDCLK (1<<29)
-#define GPIO_LEDD (1<<30)
-#define GPIO_CPU_LED (1<<31)
-
-#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * iPAQ h2200 board configuration
+ *
+ * Copyright (C) 2012 Lukasz Dalek <luk0104@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define MACH_TYPE_H2200 341
+#define CONFIG_MACH_TYPE MACH_TYPE_H2200
+
+#define CONFIG_CPU_PXA25X 1
+#define CONFIG_BOARD_H2200
+
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
+#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE
+
+#define CONFIG_SYS_INIT_SP_ADDR 0xfffff800
+
+#define CONFIG_ENV_SIZE 0x00040000
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024)
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */
+
+/*
+ * iPAQ 1st stage bootloader loads 2nd stage bootloader
+ * at address 0xa0040000 but bootloader requires header
+ * which is 0x1000 long.
+ *
+ * --- Header begin ---
+ * .word 0xea0003fe ; b 0x1000
+ *
+ * .org 0x40
+ * .ascii "ECEC"
+ *
+ * .org 0x1000
+ * --- Header end ---
+ */
+
+#define CONFIG_SYS_TEXT_BASE 0xa0041000
+
+/*
+ * Static chips
+ */
+
+#define CONFIG_SYS_MSC0_VAL 0x246c7ffc
+#define CONFIG_SYS_MSC1_VAL 0x7ff07ff0
+#define CONFIG_SYS_MSC2_VAL 0x7ff07ff0
+
+/*
+ * PCMCIA and CF Interfaces
+ */
+
+#define CONFIG_SYS_MECR_VAL 0x00000000
+#define CONFIG_SYS_MCMEM0_VAL 0x00000000
+#define CONFIG_SYS_MCMEM1_VAL 0x00000000
+#define CONFIG_SYS_MCATT0_VAL 0x00000000
+#define CONFIG_SYS_MCATT1_VAL 0x00000000
+#define CONFIG_SYS_MCIO0_VAL 0x00000000
+#define CONFIG_SYS_MCIO1_VAL 0x00000000
+
+#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
+#define CONFIG_SYS_SXCNFG_VAL 0x00040004
+
+#define CONFIG_SYS_MDREFR_VAL 0x0099E018
+#define CONFIG_SYS_MDCNFG_VAL 0x01C801CB
+#define CONFIG_SYS_MDMRS_VAL 0x00220022
+
+#define CONFIG_SYS_PSSR_VAL 0x00000000
+#define CONFIG_SYS_CKEN 0x00004840
+#define CONFIG_SYS_CCCR 0x00000161
+
+/*
+ * GPIOs
+ */
+
+#define CONFIG_SYS_GPSR0_VAL 0x01000000
+#define CONFIG_SYS_GPSR1_VAL 0x00000000
+#define CONFIG_SYS_GPSR2_VAL 0x00010000
+
+#define CONFIG_SYS_GPCR0_VAL 0x00000000
+#define CONFIG_SYS_GPCR1_VAL 0x00000000
+#define CONFIG_SYS_GPCR2_VAL 0x00000000
+
+#define CONFIG_SYS_GPDR0_VAL 0xF7E38C00
+#define CONFIG_SYS_GPDR1_VAL 0xBCFFBF83
+#define CONFIG_SYS_GPDR2_VAL 0x000157FF
+
+#define CONFIG_SYS_GAFR0_L_VAL 0x80401000
+#define CONFIG_SYS_GAFR0_U_VAL 0x00000112
+#define CONFIG_SYS_GAFR1_L_VAL 0x600A9550
+#define CONFIG_SYS_GAFR1_U_VAL 0x0005AAAA
+#define CONFIG_SYS_GAFR2_L_VAL 0x20000000
+#define CONFIG_SYS_GAFR2_U_VAL 0x00000000
+
+/*
+ * Serial port
+ */
+
+#define CONFIG_PXA_SERIAL
+#define CONFIG_FFUART
+#define CONFIG_CONS_INDEX 3
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 38400, 115200 }
+
+#define CONFIG_CMD_IMPORTENV 1
+#define CONFIG_CMD_LOADB
+#define CONFIG_CMD_SOURCE
+#define CONFIG_CMD_RUN
+#define CONFIG_CMD_IMI
+
+#define CONFIG_FIT
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+
+/* Monitor Command Prompt */
+#define CONFIG_SYS_PROMPT "> "
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "$ "
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#define CONFIG_BOOTARGS "root=/dev/ram0 ro console=ttyS0,115200n8"
+
+#endif /* __CONFIG_H */
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Harmony"
/* Board-specific serial config */
-#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTD
/* UARTD: keyboard satellite board UART, default */
#include <asm/arch/imx-regs.h>
#include <asm/arch/mx5x_pins.h>
-#define CONFIG_SYS_MX5_HCLK 24000000
-#define CONFIG_SYS_MX5_CLK32 32768
-
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
*/
#define HOSTNAME ima3-mx53
-#define xstr(s) str(s)
-#define str(s) #s
#define CONFIG_HOSTNAME ima3-mx53
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=70800000\0" \
"kernel_addr_r=70800000\0" \
"ramdisk_addr_r=71000000\0" \
- "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
- "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
- "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \
"mmcargs=setenv bootargs root=${mmcroot} " \
"rootfstype=${mmcrootfstype}\0" \
"mmcroot=/dev/mmcblk0p3 rw\0" \
"run satargs addip addtty addmtd addmisc;" \
"sata init;ext2load sata 0:1 ${kernel_addr_r} " \
"${satafile};bootm\0" \
- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.imx\0" \
+ "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.imx\0" \
"uimage=uImage\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
"uboot_addr=0xf0001000\0" \
#define CONFIG_LOADADDR 0xa0800000 /* loadaddr env var */
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define xstr(s) str(s)
-#define str(s) #s
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
" console=ttymxc0,${baudrate}\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"addmisc=setenv bootargs ${bootargs}\0" \
- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
"kernel_addr_r=a0800000\0" \
- "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
"rootpath=/opt/eldk-4.2-arm/arm\0" \
"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
"run nfsargs addip addtty addmtd addmisc;" \
"bootm\0" \
- "bootcmd=run net_nfs\0" \
+ "bootcmd=run net_nfs\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
- "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
- " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
+ "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
" +${filesize};cp.b ${fileaddr} " \
- xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
+ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
"upd=run load update\0" \
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
/*
* Serial
*/
-#define CONFIG_SERIAL_MULTI
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
"ubi part " CONFIG_KM_UBI_PARTITION_NAME_APP "; fi\0"
#endif /* CONFIG_KM_UBI_PARTITION_NAME_APP */
-#define xstr(s) str(s)
-#define str(s) #s
-
/*
* boottargets
* - set 'subbootcmds'
":${hostname}:${netdev}:off3" \
" console=" CONFIG_KM_CONSOLE_TTY ",${baudrate}" \
" mem=${kernelmem} init=${init}" \
- " phram.phram=phvar,${varaddr}," xstr(CONFIG_KM_PHRAM) \
+ " phram.phram=phvar,${varaddr}," __stringify(CONFIG_KM_PHRAM)\
" " CONFIG_KM_UBI_LINUX_MTD " " \
CONFIG_KM_DEF_BOOT_ARGS_CPU \
"\0" \
* - 'cramfsloadfdt': copy fdt from a cramfs to ram
*/
#define CONFIG_KM_DEF_ENV_FLASH_BOOT \
- "cramfsaddr=" xstr(CONFIG_KM_CRAMFS_ADDR) "\0" \
+ "cramfsaddr=" __stringify(CONFIG_KM_CRAMFS_ADDR) "\0" \
"cramfsloadkernel=cramfsload ${load_addr_r} uImage\0" \
- "ubicopy=ubi read "xstr(CONFIG_KM_CRAMFS_ADDR) \
+ "ubicopy=ubi read "__stringify(CONFIG_KM_CRAMFS_ADDR) \
" bootfs${boot_bank}\0" \
CONFIG_KM_DEV_ENV_FLASH_BOOT_UBI
#define CONFIG_KM_DEF_ENV_CONSTANTS \
"backup_bank=0\0" \
"release=run newenv; reset\0" \
- "pnvramsize=" xstr(CONFIG_KM_PNVRAM) "\0" \
+ "pnvramsize=" __stringify(CONFIG_KM_PNVRAM) "\0" \
"testbootcmd=setenv boot_bank ${test_bank}; " \
"run ${subbootcmds}; reset\0" \
""
"saveenv && saveenv && boot\0" \
"bootlimit=3\0" \
"init=/sbin/init-overlay.sh\0" \
- "load_addr_r="xstr(CONFIG_KM_KERNEL_ADDR) "\0" \
+ "load_addr_r="__stringify(CONFIG_KM_KERNEL_ADDR) "\0" \
"load=tftpboot ${load_addr_r} ${u-boot}\0" \
"mtdids=" MTDIDS_DEFAULT "\0" \
"mtdparts=" MTDPARTS_DEFAULT "\0" \
"cramfsloadfdt=" \
"cramfsload ${fdt_addr_r} " \
"fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0" \
- "fdt_addr_r=" xstr(CONFIG_KM_FDT_ADDR) "\0" \
- "u-boot="xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0" \
+ "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
"update=" \
- "protect off " xstr(BOOTFLASH_START) " +${filesize} && "\
- "erase " xstr(BOOTFLASH_START) " +${filesize} && " \
- "cp.b ${load_addr_r} " xstr(BOOTFLASH_START) \
+ "protect off " __stringify(BOOTFLASH_START) " +${filesize} && "\
+ "erase " __stringify(BOOTFLASH_START) " +${filesize} && "\
+ "cp.b ${load_addr_r} " __stringify(BOOTFLASH_START) \
" ${filesize} && " \
- "protect on " xstr(BOOTFLASH_START) " +${filesize}\0" \
+ "protect on " __stringify(BOOTFLASH_START) " +${filesize}\0"\
""
#endif /* __CONFIG_KEYMILE_POWERPC_H */
#define CONFIG_KM_DEF_ENV_CPU \
"boot=bootm ${load_addr_r} - -\0" \
"cramfsloadfdt=true\0" \
- "u-boot="xstr(CONFIG_HOSTNAME) "/u-boot.kwb\0" \
+ "u-boot="__stringify(CONFIG_HOSTNAME) "/u-boot.kwb\0" \
CONFIG_KM_UPDATE_UBOOT \
""
#if defined CONFIG_KM_ENV_IS_IN_SPI_NOR
#define CONFIG_KM_NEW_ENV \
"newenv=sf probe 0;" \
- "sf erase " xstr(CONFIG_ENV_OFFSET) " " \
- xstr(CONFIG_ENV_TOTAL_SIZE)"\0"
+ "sf erase " __stringify(CONFIG_ENV_OFFSET) " " \
+ __stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
#else
#define CONFIG_KM_NEW_ENV \
"newenv=setenv addr 0x100000 && " \
"i2c dev 1; mw.b ${addr} 0 4 && " \
- "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
- " ${addr} " xstr(CONFIG_ENV_OFFSET) " 4 && " \
- "eeprom write " xstr(CONFIG_SYS_DEF_EEPROM_ADDR) \
- " ${addr} " xstr(CONFIG_ENV_OFFSET_REDUND) " 4\0"
+ "eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \
+ " ${addr} " __stringify(CONFIG_ENV_OFFSET) " 4 && " \
+ "eeprom write " __stringify(CONFIG_SYS_DEF_EEPROM_ADDR) \
+ " ${addr} " __stringify(CONFIG_ENV_OFFSET_REDUND) " 4\0"
#endif
/*
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/* I2C */
#define CONFIG_CMD_I2C
#define CONFIG_SH_I2C 1
+#define CONFIG_SH_I2C_8BIT
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MULTI_BUS
-#define CONFIG_SYS_MAX_I2C_BUS (2)
+#define CONFIG_SYS_MAX_I2C_BUS (5)
#define CONFIG_SYS_I2C_MODULE
#define CONFIG_SYS_I2C_SPEED (100000) /* 100 kHz */
#define CONFIG_SYS_I2C_SLAVE (0x7F)
#define CONFIG_SH_I2C_DATA_HIGH (4)
#define CONFIG_SH_I2C_DATA_LOW (5)
-#define CONFIG_SH_I2C_CLOCK (41666666)
+#define CONFIG_SH_I2C_CLOCK (104000000) /* 104 MHz */
#define CONFIG_SH_I2C_BASE0 (0xE6820000)
#define CONFIG_SH_I2C_BASE1 (0xE6822000)
+#define CONFIG_SH_I2C_BASE2 (0xE6824000)
+#define CONFIG_SH_I2C_BASE3 (0xE6826000)
+#define CONFIG_SH_I2C_BASE4 (0xE6828000)
#endif /* __KZM9G_H */
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
#if defined(CONFIG_HLAN) || defined(CONFIG_LAN)
#define UBFILE "share/u-boot/u-boot-hd.flash.bin"
#elif defined(CONFIG_HGLAN)
"stdin=nc\0" \
"stdout=nc\0" \
"stderr=nc\0" \
- "ipaddr="MK_STR(CONFIG_IPADDR_LS)"\0" \
+ "ipaddr="__stringify(CONFIG_IPADDR_LS)"\0" \
"netmask=255.255.255.0\0" \
- "serverip="MK_STR(CONFIG_SERVERIP_LS)"\0" \
- "ncip="MK_STR(CONFIG_NCIP_LS)"\0" \
+ "serverip="__stringify(CONFIG_SERVERIP_LS)"\0" \
+ "ncip="__stringify(CONFIG_NCIP_LS)"\0" \
"netretry=no\0" \
"nc=setenv stdin nc;setenv stdout nc;setenv stderr nc\0" \
"ser=setenv stdin serial;setenv stdout serial;setenv stderr serial\0" \
"&& bootm 0x00100000 0x00800000\0" \
"bootcmd_rescue=run config_nc_dhcp; run nc\0" \
"eraseenv=sf probe 0 " \
- "&& sf erase " MK_STR(CONFIG_ENV_OFFSET) \
- " +" MK_STR(CONFIG_ENV_SIZE) "\0" \
+ "&& sf erase " __stringify(CONFIG_ENV_OFFSET) \
+ " +" __stringify(CONFIG_ENV_SIZE) "\0" \
"config_nc_dhcp=setenv autoload_old ${autoload}; " \
"setenv autoload no " \
"&& bootp " \
*/
#define CONFIG_PXA_SERIAL
#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
+#define CONFIG_CONS_INDEX 3
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_LCD_INFO 1 /* ... and some board info */
#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
#define CONFIG_8xx_CONS_SCC2 1 /* Console is on SCC2 */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
#undef CONFIG_BOOTARGS
-#define xstr(s) str(s)
-#define str(s) #s
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
":${hostname}:${netdev}:off panic=1\0" \
"kernel_addr=ff810000\0" \
- "fdt_addr="xstr(CONFIG_SYS_FLASH_BASE)"\0" \
+ "fdt_addr="__stringify(CONFIG_SYS_FLASH_BASE)"\0" \
"flash_nfs=run nfsargs addip addcon addwdt addlog;" \
"bootm ${kernel_addr} - ${fdt_addr}\0" \
"rootpath=/opt/eldk/ppc_82xx\0" \
"kernel_addr_r=300000\0" \
"fdt_addr_r=200000\0" \
- "fdt_file=" xstr(CONFIG_HOSTNAME) "/" \
- xstr(CONFIG_HOSTNAME) ".dtb\0" \
- "kernel_file=" xstr(CONFIG_HOSTNAME) "/uImage \0" \
+ "fdt_file=" __stringify(CONFIG_HOSTNAME) "/" \
+ __stringify(CONFIG_HOSTNAME) ".dtb\0" \
+ "kernel_file=" __stringify(CONFIG_HOSTNAME) "/uImage \0" \
"load_fdt=tftp ${fdt_addr_r} ${fdt_file};\0" \
"load_kernel=tftp ${kernel_addr_r} ${kernel_file};\0" \
"addcon=setenv bootargs ${bootargs} console=ttyPSC0,${baudrate}\0"\
"net_nfs=run load_fdt load_kernel; " \
"run nfsargs addip addcon addwdt addlog;" \
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin \0" \
+ "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin \0" \
"u-boot_addr_r=200000\0" \
"load=tftp ${u-boot_addr_r} ${u-boot}\0" \
- "update=protect off " xstr(CONFIG_SYS_TEXT_BASE) " +${filesize};" \
- "erase " xstr(CONFIG_SYS_TEXT_BASE) " +${filesize};" \
- "cp.b ${u-boot_addr_r} " xstr(CONFIG_SYS_TEXT_BASE) \
+ "update=protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +${filesize};"\
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +${filesize};"\
+ "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_TEXT_BASE) \
" ${filesize};" \
- "protect on " xstr(CONFIG_SYS_TEXT_BASE) " +${filesize}\0" \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +${filesize}\0"\
""
#define CONFIG_BOOTCOMMAND "run net_nfs"
*/
#if !defined(CONFIG_PRS200)
/* MCC200 configuration: */
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_PSC_CONSOLE 1 /* PSC1 may be COM */
#define CONFIG_PSC_CONSOLE2 2 /* PSC2 is PSoC */
#else
/* PRS200 configuration: */
#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
#endif
-#if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE) && \
- !defined(CONFIG_SERIAL_MULTI)
-#error "Select only one console device!"
-#endif
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
#undef CONFIG_BOOTARGS
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
#ifdef CONFIG_PRS200
# define CONFIG_SYS__BOARDNAME "prs200"
# define CONFIG_SYS__LINUX_CONSOLE "ttyS0"
#define CONFIG_EXTRA_ENV_SETTINGS \
"ubootver=" U_BOOT_VERSION "\0" \
"netdev=eth0\0" \
- "hostname=" CONFIG_SYS__BOARDNAME "\0" \
+ "hostname=" CONFIG_SYS__BOARDNAME "\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"nfsroot=${serverip}:${rootpath}\0" \
"ramargs=setenv bootargs root=/dev/mtdblock2 " \
"rootpath=/opt/eldk/ppc_6xx\0" \
"bootfile=/tftpboot/" CONFIG_SYS__BOARDNAME "/uImage\0" \
"load=tftp 200000 /tftpboot/" CONFIG_SYS__BOARDNAME "/u-boot.bin\0" \
- "text_base=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \
+ "text_base=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
"kernel_addr=0xFC0C0000\0" \
"update=protect off ${text_base} +${filesize};" \
"era ${text_base} +${filesize};" \
"cp.b 200000 ${text_base} ${filesize}\0" \
"unlock=yes\0" \
""
-#undef MK_STR
-#undef XMK_STR
#define CONFIG_BOOTCOMMAND "run flash_self"
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
+#define CONFIG_SYS_PSC3
#if CONFIG_PSC_CONSOLE != 3
#error CONFIG_PSC_CONSOLE must be 3
#endif
#include "tegra20-common.h"
-/* Enable fdt support for Medcom. Flash the image in u-boot-dtb.bin */
-#define CONFIG_DEFAULT_DEVICE_TREE tegra20-medcom
+/* Enable fdt support for Medcom-Wide. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE tegra20-medcom-wide
#define CONFIG_OF_CONTROL
#define CONFIG_OF_SEPARATE
/* High-level configuration options */
-#define V_PROMPT "Tegra20 (Medcom) # "
-#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Medcom"
+#define V_PROMPT "Tegra20 (Medcom-Wide) # "
+#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Medcom-Wide"
/* Board-specific serial config */
-#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
* Serial console configuration
*/
#define CONFIG_PSC_CONSOLE 3 /* console is on PSC3 */
+#define CONFIG_SYS_PSC3
#if CONFIG_PSC_CONSOLE != 3
#error CONFIG_PSC_CONSOLE must be 3
#endif
#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
-#define xstr(s) str(s)
-#define str(s) #s
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"consoledev=ttyS0\0" \
"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
"bootcmd=run flash_self\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
- "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
- " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
+ "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
" +${filesize};cp.b ${fileaddr} " \
- xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
+ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
"upd=run load update\0" \
#endif /* __CONFIG_H */
/* Configuration of lowlevel_init.S (clocks and SDRAM) */
#define CCM_CCMR_SETUP 0x074B0BF5
-#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \
- PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) | \
- PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) | \
- PDR0_MCU_PODF(0))
-#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
+#define CCM_PDR0_SETUP_532MHZ (PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | \
+ PDR0_PER_PODF(7) | PDR0_HSP_PODF(3) | \
+ PDR0_NFC_PODF(5) | PDR0_IPG_PODF(1) | \
+ PDR0_MAX_PODF(3) | PDR0_MCU_PODF(0))
+#define CCM_MPCTL_SETUP_532MHZ (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) | \
PLL_MFN(12))
#define ESDMISC_MDDR_SETUP 0x00000004
* Default environment and default scripts
* to update uboot and load kernel
*/
-#define xstr(s) str(s)
-#define str(s) #s
#define CONFIG_HOSTNAME "mx35pdk"
#define CONFIG_EXTRA_ENV_SETTINGS \
":${hostname}:${netdev}:off panic=1\0" \
"addip_dyn=setenv bootargs ${bootargs} ip=dhcp\0" \
"addip=if test -n ${ipdyn};then run addip_dyn;" \
- "else run addip_sta;fi\0" \
+ "else run addip_sta;fi\0" \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"addtty=setenv bootargs ${bootargs}" \
" console=ttymxc0,${baudrate}\0" \
"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
"loadaddr=80800000\0" \
"kernel_addr_r=80800000\0" \
- "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
- "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
- "ramdisk_file=" xstr(CONFIG_HOSTNAME) "/uRamdisk\0" \
+ "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
+ "ramdisk_file=" __stringify(CONFIG_HOSTNAME) "/uRamdisk\0" \
"flash_self=run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr_r}\0" \
"net_self_load=tftp ${kernel_addr_r} ${bootfile};" \
"tftp ${ramdisk_addr_r} ${ramdisk_file};\0" \
- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \
+ "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.bin\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
- "uboot_addr=" xstr(CONFIG_SYS_MONITOR_BASE) "\0" \
+ "uboot_addr=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \
"update=protect off ${uboot_addr} +80000;" \
"erase ${uboot_addr} +80000;" \
"cp.b ${loadaddr} ${uboot_addr} ${filesize}\0" \
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MX5_HCLK 24000000
-#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MX51 /* in a mx51 */
-#define CONFIG_SYS_MX5_HCLK 24000000
-#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MX53
-#define CONFIG_SYS_MX5_HCLK 24000000
-#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MX53
-#define CONFIG_SYS_MX5_HCLK 24000000
-#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MX53
-#define CONFIG_SYS_MX5_HCLK 24000000
-#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO
#define CONFIG_MX53
-#define CONFIG_SYS_MX5_HCLK 24000000
-#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
#define __CONFIG_H
#define CONFIG_MX6Q
-#define CONFIG_SYS_MX6_HCLK 24000000
-#define CONFIG_SYS_MX6_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
--- /dev/null
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6Q SabreSD board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MX6QSABRE_COMMON_CONFIG_H
+#define __MX6QSABRE_COMMON_CONFIG_H
+
+#define CONFIG_MX6Q
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+#define CONFIG_REVISION_TAG
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_MXC_GPIO
+
+#define CONFIG_MXC_UART
+
+/* MMC Configs */
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+
+#define CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_EXT2
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NET
+#define CONFIG_FEC_MXC
+#define CONFIG_MII
+#define IMX_FEC_BASE ENET_BASE_ADDR
+#define CONFIG_FEC_XCV_TYPE RGMII
+#define CONFIG_ETHPRIME "FEC"
+#define CONFIG_FEC_MXC_PHYADDR 1
+
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_ATHEROS
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_BAUDRATE 115200
+
+/* Command definition */
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_IMLS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_LOADADDR 0x10800000
+#define CONFIG_SYS_TEXT_BASE 0x17800000
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "uimage=uImage\0" \
+ "console=" CONFIG_CONSOLE_DEV "\0" \
+ "fdt_high=0xffffffff\0" \
+ "initrd_high=0xffffffff\0" \
+ "mmcdev=0\0" \
+ "mmcpart=1\0" \
+ "mmcroot=/dev/mmcblk1p2 rootwait rw\0" \
+ "mmcargs=setenv bootargs console=${console},${baudrate} " \
+ "root=${mmcroot}\0" \
+ "loadbootscript=" \
+ "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "bootm\0" \
+ "netargs=setenv bootargs console=${console},${baudrate} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "dhcp ${uimage}; bootm\0" \
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev};" \
+ "if mmc rescan ${mmcdev}; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loaduimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else run netboot; fi"
+
+#define CONFIG_ARP_TIMEOUT 200UL
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "U-Boot > "
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_CBSIZE 256
+
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x10000000
+#define CONFIG_SYS_MEMTEST_END 0x10010000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_STACKSIZE (128 * 1024)
+
+/* Physical Memory Map */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
+
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
+#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
+#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
+
+#define CONFIG_SYS_INIT_SP_OFFSET \
+ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+
+/* FLASH and environment organization */
+#define CONFIG_SYS_NO_FLASH
+
+#define CONFIG_ENV_SIZE (8 * 1024)
+
+#define CONFIG_ENV_IS_IN_MMC
+
+#if defined(CONFIG_ENV_IS_IN_MMC)
+#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#endif
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_SYS_DCACHE_OFF
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#endif
+
+#endif /* __MX6QSABRE_COMMON_CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6Q SabreSD board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __MX6QSABREAUTO_CONFIG_H
+#define __MX6QSABREAUTO_CONFIG_H
+
+#define CONFIG_MACH_TYPE 3529
+#define CONFIG_MXC_UART_BASE UART4_BASE
+#define CONFIG_CONSOLE_DEV "ttymxc3"
+#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
+
+#include "mx6qsabre_common.h"
+
+#endif /* __MX6QSABREAUTO_CONFIG_H */
#define __CONFIG_H
#define CONFIG_MX6Q
-#define CONFIG_SYS_MX6_HCLK 24000000
-#define CONFIG_SYS_MX6_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
--- /dev/null
+/*
+ * Copyright (C) 2012 Freescale Semiconductor, Inc.
+ *
+ * Configuration settings for the Freescale i.MX6Q SabreSD board.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MX6QSABRESD_CONFIG_H
+#define __MX6QSABRESD_CONFIG_H
+
+#define CONFIG_MACH_TYPE 3980
+#define CONFIG_MXC_UART_BASE UART1_BASE
+#define CONFIG_CONSOLE_DEV "ttymxc0"
+#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
+
+#include "mx6qsabre_common.h"
+
+#endif /* __MX6QSABRESD_CONFIG_H */
* NS16550 Configuration
* Zoom2 uses the TL16CP754C on the debug board
*/
-#define CONFIG_SERIAL_MULTI 1
/*
* 0 - 1 : first USB with respect to the left edge of the debug board
* 2 - 3 : second USB with respect to the left edge of the debug board
*/
-#define ZOOM2_DEFAULT_SERIAL_DEVICE (&zoom2_serial_device0)
+#define ZOOM2_DEFAULT_SERIAL_DEVICE 0
#define V_NS16550_CLK (1843200) /* 1.8432 Mhz */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
/* select serial console configuration */
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_SERIAL2 1 /* use SERIAL 2 */
#define CONFIG_BAUDRATE 115200
#define EXYNOS4_DEFAULT_UART_OFFSET 0x020000
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
-"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"loadaddr=1000000\0" \
"bootfile=uImage\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdisk_size=120000\0" \
"map_lowernorbank=i2c dev 1; i2c mw 18 1 02 1; i2c mw 18 3 fd 1\0" \
"map_uppernorbank=i2c dev 1; i2c mw 18 1 00 1; i2c mw 18 3 fd 1\0" \
-MK_STR(__NOR_RST_CMD)"\0" \
-MK_STR(__SPI_RST_CMD)"\0" \
-MK_STR(__SD_RST_CMD)"\0" \
-MK_STR(__NAND_RST_CMD)"\0" \
-MK_STR(__PCIE_RST_CMD)"\0"
+__stringify(__NOR_RST_CMD)"\0" \
+__stringify(__SPI_RST_CMD)"\0" \
+__stringify(__SD_RST_CMD)"\0" \
+__stringify(__NAND_RST_CMD)"\0" \
+__stringify(__PCIE_RST_CMD)"\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
*/
#define CONFIG_PXA_SERIAL
#define CONFIG_FFUART 1
+#define CONFIG_CONS_INDEX 3
#define CONFIG_BAUDRATE 9600
/*
*/
#define CONFIG_PXA_SERIAL
#define CONFIG_FFUART 1
+#define CONFIG_CONS_INDEX 3
#define CONFIG_BAUDRATE 115200
/*
#define CONFIG_TEGRA_BOARD_STRING "Compal Paz00"
/* Board-specific serial config */
-#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clk used */
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
/*
* Used PSC UART devices
*/
-#define CONFIG_SERIAL_MULTI
#define CONFIG_SYS_PSC1
#define CONFIG_SYS_PSC4
#define CONFIG_SYS_PSC6
#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
#endif
-#ifdef CONFIG_SERIAL_MULTI
/* POST support */
#define CONFIG_POST (CONFIG_SYS_POST_COPROC)
-#endif
/*
* Environment Configuration
#define CONFIG_TEGRA_BOARD_STRING "Avionic Design Plutux"
/* Board-specific serial config */
-#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
*/
#define CONFIG_PXA_SERIAL
#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */
+#define CONFIG_CONS_INDEX 3
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#ifndef __CONFIG_H
#define __CONFIG_H
-#define CONFIG_MIPS32 1 /* MIPS32 CPU core */
-#define CONFIG_QEMU_MIPS 1
+#define CONFIG_MIPS32 /* MIPS32 CPU core */
+#define CONFIG_QEMU_MIPS
#define CONFIG_MISC_INIT_R
-/*IP address is default used by Qemu*/
-#define CONFIG_IPADDR 10.0.2.15 /* Our IP address */
-#define CONFIG_SERVERIP 10.0.2.2 /* Server IP address */
-
#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
#define CONFIG_BAUDRATE 115200
#define CONFIG_CMD_DHCP
#define CONFIG_DRIVER_NE2000
-#define CONFIG_DRIVER_NE2000_BASE (0xb4000300)
+#define CONFIG_DRIVER_NE2000_BASE 0xb4000300
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK 115200
-#define CONFIG_SYS_NS16550_COM1 (0xb40003f8)
-#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550_COM1 0xb40003f8
+#define CONFIG_CONS_INDEX 1
#define CONFIG_CMD_IDE
#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_IDE_MAXBUS 2
-#define CONFIG_SYS_ATA_IDE0_OFFSET (0x1f0)
-#define CONFIG_SYS_ATA_IDE1_OFFSET (0x170)
-#define CONFIG_SYS_ATA_DATA_OFFSET (0)
-#define CONFIG_SYS_ATA_REG_OFFSET (0)
-#define CONFIG_SYS_ATA_BASE_ADDR (0xb4000000)
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
+#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
+#define CONFIG_SYS_ATA_DATA_OFFSET 0
+#define CONFIG_SYS_ATA_REG_OFFSET 0
+#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
-#define CONFIG_SYS_IDE_MAXDEVICE (4)
+#define CONFIG_SYS_IDE_MAXDEVICE 4
/*
* Miscellaneous configurable options
*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
/* Monitor Command Prompt */
#if defined(CONFIG_SYS_LITTLE_ENDIAN)
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
#define CONFIG_SYS_MALLOC_LEN 128*1024
#define CONFIG_SYS_HZ 1000
-#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* Cached addr */
+/* Cached addr */
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
-#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* default load address */
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR 0x81000000
#define CONFIG_SYS_MEMTEST_START 0x80100000
#define CONFIG_SYS_MEMTEST_END 0x80800000
/*-----------------------------------------------------------------------
* FLASH and environment organization
*/
-
/* The following #defines are needed to get flash environment right */
+#define CONFIG_SYS_TEXT_BASE 0xbfc00000 /* Rom version */
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN (192 << 10)
#define CONFIG_SYS_FLASH_BASE 0xbfc00000
#define CONFIG_SYS_MAX_FLASH_BANKS 1
#define CONFIG_SYS_MAX_FLASH_SECT 128
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */
-#define CONFIG_FLASH_CFI_DRIVER 1
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_ENV_IS_IN_FLASH 1
+#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
/* Address and size of Primary Environment Sector */
#define MEM_SIZE 128
-#undef CONFIG_MEMSIZE_IN_BYTES
-
#define CONFIG_LZMA
/*-----------------------------------------------------------------------
--- /dev/null
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for qemu-mips64 target.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MIPS64 /* MIPS64 CPU core */
+#define CONFIG_QEMU_MIPS
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
+
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "addmisc=setenv bootargs ${bootargs} " \
+ "console=ttyS0,${baudrate} " \
+ "panic=1\0" \
+ "bootfile=/tftpboot/vmlinux\0" \
+ "load=tftp ffffffff80500000 ${u-boot}\0" \
+ ""
+
+#define CONFIG_BOOTCOMMAND "bootp;bootelf"
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#define CONFIG_CMD_DHCP
+
+#define CONFIG_DRIVER_NE2000
+#define CONFIG_DRIVER_NE2000_BASE 0xffffffffb4000300
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK 115200
+#define CONFIG_SYS_NS16550_COM1 0xffffffffb40003f8
+#define CONFIG_CONS_INDEX 1
+
+#define CONFIG_CMD_IDE
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SYS_IDE_MAXBUS 2
+#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1f0
+#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170
+#define CONFIG_SYS_ATA_DATA_OFFSET 0
+#define CONFIG_SYS_ATA_REG_OFFSET 0
+#define CONFIG_SYS_ATA_BASE_ADDR 0xffffffffb4000000
+
+#define CONFIG_SYS_IDE_MAXDEVICE 4
+
+#define CONFIG_CMD_RARP
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+
+/* Monitor Command Prompt */
+#if defined(CONFIG_SYS_LITTLE_ENDIAN)
+#define CONFIG_SYS_PROMPT "qemu-mips64el # "
+#else
+#define CONFIG_SYS_PROMPT "qemu-mips64 # "
+#endif
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256
+/* Print Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+/* max number of command args */
+#define CONFIG_SYS_MAXARGS 16
+
+#define CONFIG_SYS_MALLOC_LEN 128*1024
+
+#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
+
+#define CONFIG_SYS_MHZ 132
+
+#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
+
+#define CONFIG_SYS_HZ 1000
+
+/* Cached addr */
+#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
+
+/* default load address */
+#define CONFIG_SYS_LOAD_ADDR 0xffffffff81000000
+
+#define CONFIG_SYS_MEMTEST_START 0xffffffff80100000
+#define CONFIG_SYS_MEMTEST_END 0xffffffff80800000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+/* The following #defines are needed to get flash environment right */
+#define CONFIG_SYS_TEXT_BASE 0xffffffffbfc00000 /* Rom version */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_MONITOR_LEN (192 << 10)
+
+#define CONFIG_SYS_INIT_SP_OFFSET 0x400000
+
+/* We boot from this flash, selected with dip switch */
+#define CONFIG_SYS_FLASH_BASE 0xffffffffbfc00000
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 128
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
+
+/* Address and size of Primary Environment Sector */
+#define CONFIG_ENV_SIZE 0x8000
+
+#define CONFIG_ENV_OVERWRITE 1
+
+#define MEM_SIZE 128
+
+#define CONFIG_LZMA
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CONFIG_SYS_DCACHE_SIZE 16384
+#define CONFIG_SYS_ICACHE_SIZE 16384
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+#endif /* __CONFIG_H */
#define CONFIG_LOADADDR 0x80800000 /* loadaddr env var */
-#define xstr(s) str(s)
-#define str(s) #s
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"bootm\0" \
"bootcmd=run flash_self\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
- "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
- " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
+ "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE) \
+ " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
" +${filesize};cp.b ${fileaddr} " \
- xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
+ __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
"upd=run load update\0" \
"videomode=video=ctfb:x:640,y:480,depth:16,mode:0,pclk:40000," \
"le:120,ri:40,up:35,lo:10,hs:30,vs:3,sync:100663296," \
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
#define CONFIG_SYS_BASE_BAUD 691200
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI
/* The following table includes the supported baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE \
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
* select serial console configuration
*/
#define CONFIG_SERIAL2 1 /* use SERIAL2 */
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_BAUDRATE 115200
/* MMC */
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
/* select serial console configuration */
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_SERIAL2 1 /* use SERIAL 2 */
#define CONFIG_BAUDRATE 115200
#define CONFIG_BAUDRATE 115200
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
- "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=uRamdisk\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=sbc8548.dtb\0"
+"netdev=eth0\0" \
+"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
+"tftpflash=tftpboot $loadaddr $uboot; " \
+ "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
+ "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
+ "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
+"consoledev=ttyS0\0" \
+"ramdiskaddr=2000000\0" \
+"ramdiskfile=uRamdisk\0" \
+"fdtaddr=c00000\0" \
+"fdtfile=sbc8548.dtb\0"
#define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \
+++ /dev/null
-/*
- * (C) Copyright 2002,2003 Motorola,Inc.
- * Xianghua Xiao <X.Xiao@motorola.com>
- *
- * (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>.
- * Added support for Wind River SBC8560 board
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * sbc8560 board configuration file.
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * Top level Makefile configuration choices
- */
-#ifdef CONFIG_66
-#define CONFIG_PCI_66
-#endif
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
-#define CONFIG_MPC85xx_REV1 1 /* MPC85xx Rev 1.0 chip */
-
-#define CONFIG_SYS_TEXT_BASE 0xfffc0000
-
-
-#define CONFIG_CPM2 1 /* has CPM2 */
-#define CONFIG_SBC8560 1 /* configuration for SBC8560 board */
-#define CONFIG_MPC8560 1
-
-/* XXX flagging this as something I might want to delete */
-#define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
-
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
-#undef CONFIG_PCI /* pci ethernet support */
-#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
-
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-
-#define CONFIG_ENV_OVERWRITE
-
-/* Using Localbus SDRAM to emulate flash before we can program the flash,
- * normally you need a flash-boot image(u-boot.bin), if so undef this.
- */
-#undef CONFIG_RAM_AS_FLASH
-
-#if defined(CONFIG_PCI_66) /* some PCI card is 33Mhz only */
- #define CONFIG_SYS_CLK_FREQ 66000000/* sysclk for MPC85xx */
-#else
- #define CONFIG_SYS_CLK_FREQ 33000000/* most pci cards are 33Mhz */
-#endif
-
-/* below can be toggled for performance analysis. otherwise use default */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#undef CONFIG_BTB /* toggle branch predition */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
-
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
-#define CONFIG_SYS_MEMTEST_END 0x00400000
-
-#if (defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET) || \
- defined(CONFIG_PCI) && defined(CONFIG_ETHER_ON_FCC) || \
- defined(CONFIG_TSEC_ENET) && defined(CONFIG_ETHER_ON_FCC))
-#error "You can only use ONE of PCI Ethernet Card or TSEC Ethernet or CPM FCC."
-#endif
-
-#define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */
-
-/* DDR Setup */
-#define CONFIG_FSL_DDR1
-#undef CONFIG_FSL_DDR_INTERACTIVE
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#undef CONFIG_DDR_SPD
-
-#if defined(CONFIG_MPC85xx_REV1)
-#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
-#endif
-
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 2
-
-/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS 0x55 /* CTLR 0 DIMM 0 */
-
-#undef CONFIG_CLOCKS_IN_MHZ
-
-#if defined(CONFIG_RAM_AS_FLASH)
- #define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
- #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
- #define CONFIG_SYS_BR0_PRELIM 0xf8000801 /* port size 8bit */
- #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 /* 8MB Flash */
-#else /* Boot from real Flash */
- #define CONFIG_SYS_LBC_SDRAM_BASE 0xf8000000 /* Localbus SDRAM */
- #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
- #define CONFIG_SYS_BR0_PRELIM 0xff800801 /* port size 8bit */
- #define CONFIG_SYS_OR0_PRELIM 0xff800ff7 /* 8MB Flash */
-#endif
-#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
-
-/* local bus definitions */
-#define CONFIG_SYS_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */
-#define CONFIG_SYS_OR1_PRELIM 0xfc000ff7
-
-#define CONFIG_SYS_BR2_PRELIM 0x00000000 /* CS2 not used */
-#define CONFIG_SYS_OR2_PRELIM 0x00000000
-
-#define CONFIG_SYS_BR3_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
-#define CONFIG_SYS_OR3_PRELIM 0xfc000cc1
-
-#if defined(CONFIG_RAM_AS_FLASH)
- #define CONFIG_SYS_BR4_PRELIM 0xf4001861 /* 64M localbus SDRAM */
-#else
- #define CONFIG_SYS_BR4_PRELIM 0xf8001861 /* 64M localbus SDRAM */
-#endif
-#define CONFIG_SYS_OR4_PRELIM 0xfc000cc1
-
-#define CONFIG_SYS_BR5_PRELIM 0xfc000801 /* 16M CS5 misc devices */
-#if 1
- #define CONFIG_SYS_OR5_PRELIM 0xff000ff7
-#else
- #define CONFIG_SYS_OR5_PRELIM 0xff0000f0
-#endif
-
-#define CONFIG_SYS_BR6_PRELIM 0xe0001801 /* 64M, 32-bit flash */
-#define CONFIG_SYS_OR6_PRELIM 0xfc000ff7
-#define CONFIG_SYS_LBC_LCRR 0x00030002 /* local bus freq */
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-#define CONFIG_SYS_LBC_LSRT 0x20000000
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
-#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
-#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
-#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
-#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
-
-/* just hijack the MOT BCSR def for SBC8560 misc devices */
-#define CONFIG_SYS_BCSR ((CONFIG_SYS_BR5_PRELIM & 0xff000000)|0x00400000)
-/* the size of CS5 needs to be >= 16M for TLB and LAW setups */
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
-
-/* Serial Port */
-#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else */
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK 1843200 /* get_bus_freq(0) */
-#define CONFIG_BAUDRATE 9600
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00700000)
-#define CONFIG_SYS_NS16550_COM2 ((CONFIG_SYS_BR5_PRELIM & 0xff000000)+0x00800000)
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/*
- * I2C
- */
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-
-#define CONFIG_SYS_PCI_MEM_BASE 0xC0000000
-#define CONFIG_SYS_PCI_MEM_PHYS 0xC0000000
-#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
-
-#ifdef CONFIG_TSEC_ENET
-
-#ifndef CONFIG_MII
-#define CONFIG_MII 1 /* MII PHY management */
-#endif
-#define CONFIG_TSEC1 1
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_TSEC2 1
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define TSEC1_PHY_ADDR 0x19
-#define TSEC2_PHY_ADDR 0x1a
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME "TSEC0"
-
-#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
-
- #undef CONFIG_ETHER_NONE /* define if ether on something else */
- #define CONFIG_ETHER_ON_FCC2 /* cpm FCC ethernet support */
- #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
-
- #if (CONFIG_ETHER_INDEX == 2)
- /*
- * - Rx-CLK is CLK13
- * - Tx-CLK is CLK14
- * - Select bus for bd/buffers
- * - Full duplex
- */
- #define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
- #define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
- #define CONFIG_SYS_CPMFCR_RAMTYPE 0
- #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
-
- #elif (CONFIG_ETHER_INDEX == 3)
- /* need more definitions here for FE3 */
- #endif /* CONFIG_ETHER_INDEX */
-
- #define CONFIG_MII /* MII PHY management */
- #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
- /*
- * GPIO pins used for bit-banged MII communications
- */
- #define MDIO_PORT 2 /* Port C */
- #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
- #define MDC_DECLARE MDIO_DECLARE
-
- #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
- #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
- #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
-
- #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
- else iop->pdat &= ~0x00400000
-
- #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
- else iop->pdat &= ~0x00200000
-
- #define MIIDELAY udelay(1)
-
-#endif
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-
-#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
-#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
-#if 0
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_PROTECTION /* use hardware protection */
-#endif
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 200000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 50000 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if 0
-/* XXX This doesn't work and I don't want to fix it */
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
- #define CONFIG_SYS_RAMBOOT
-#else
- #undef CONFIG_SYS_RAMBOOT
-#endif
-#endif
-
-/* Environment */
-#if !defined(CONFIG_SYS_RAMBOOT)
- #if defined(CONFIG_RAM_AS_FLASH)
- #define CONFIG_ENV_IS_NOWHERE
- #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000)
- #define CONFIG_ENV_SIZE 0x2000
- #else
- #define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
- #define CONFIG_ENV_SIZE 0x2000 /* CONFIG_ENV_SECT_SIZE */
- #endif
-#else
- #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
- #define CONFIG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=dhcp console=ttyS0,9600"
-/*#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"*/
-#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_REGINFO
-
-#if defined(CONFIG_PCI)
- #define CONFIG_CMD_PCI
-#endif
-
-#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
- #define CONFIG_CMD_MII
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#endif
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_PROMPT "SBC8560=> " /* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
- #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
- #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#endif
-
-/* You can compile in a MAC address and your custom net settings by using
- * the following syntax. Your board should be marked with the assigned
- * MAC addresses directly on it.
- *
- * #define CONFIG_ETHADDR de:ad:be:ef:00:00
- * #define CONFIG_ETH1ADDR fa:ke:ad:dr:es:s!
- * #define CONFIG_SERVERIP <server ip>
- * #define CONFIG_IPADDR <board ip>
- * #define CONFIG_GATEWAYIP <gateway ip>
- * #define CONFIG_NETMASK <your netmask>
- */
-
-#define CONFIG_HOSTNAME SBC8560
-#define CONFIG_ROOTPATH "/home/ppc"
-#define CONFIG_BOOTFILE "uImage"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=eth0\0" \
- "consoledev=ttyS0\0" \
- "ramdiskaddr=2000000\0" \
- "ramdiskfile=ramdisk.uboot\0" \
- "fdtaddr=c00000\0" \
- "fdtfile=sbc8560.dtb\0"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv bootargs root=/dev/nfs rw " \
- "nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv bootargs root=/dev/ram rw " \
- "console=$consoledev,$baudrate $othbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
-
-#endif /* __CONFIG_H */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE 1
#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#define CONFIG_SERIAL_MULTI
/*
* define CONFIG_SYS_CLK_FREQ to your base crystal clock in Hz
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Seaboard"
/* Board-specific serial config */
-#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
* USB support (currently only works with D-cache off)
************************************************************/
#define CONFIG_USB_OHCI
+#define CONFIG_USB_OHCI_S3C24XX
#define CONFIG_USB_KEYBOARD
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
/* select serial console configuration */
-#define CONFIG_SERIAL_MULTI
#define CONFIG_SERIAL3 /* use SERIAL 3 */
#define CONFIG_BAUDRATE 115200
#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000
* select serial console configuration
*/
#define CONFIG_SERIAL0 1 /* use SERIAL 0 on SMDKC100 */
-#define CONFIG_SERIAL_MULTI 1
/* PWM */
#define CONFIG_PWM 1
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
/* select serial console configuration */
-#define CONFIG_SERIAL_MULTI 1
#define CONFIG_SERIAL1 1 /* use SERIAL 1 */
#define CONFIG_BAUDRATE 115200
#define EXYNOS4_DEFAULT_UART_OFFSET 0x010000
#define CONFIG_EXTRA_ENV_SETTINGS \
"verify=n\0" \
- "loadaddr= " MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
"bootm ${loadaddr} - ${fdt_addr}\0" \
"bootimage=uImage\0" \
#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
+#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */
#define CONFIG_IDE_8xx_DIRECT 1 /* Direct IDE not supported */
#undef CONFIG_IDE_LED /* LED for ide not supported */
#undef CONFIG_IDE_RESET /* reset for ide not supported */
"1m(u-boot),256k(env1)," \
"256k(env2),6m(kernel),-(rootfs)"
-#define xstr(s) str(s)
-#define str(s) #s
-
#define CONFIG_TAM3517_SETTINGS \
"netdev=eth0\0" \
"nandargs=setenv bootargs root=${nandroot} " \
"addmisc=setenv bootargs ${bootargs} ${misc}\0" \
"loadaddr=82000000\0" \
"kernel_addr_r=82000000\0" \
- "hostname=" xstr(CONFIG_HOSTNAME) "\0" \
- "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \
+ "hostname=" __stringify(CONFIG_HOSTNAME) "\0" \
+ "bootfile=" __stringify(CONFIG_HOSTNAME) "/uImage\0" \
"flash_self=run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr} ${ramdisk_addr}\0" \
"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
"run ramargs addip addtty addmtd addmisc;" \
"bootm ${kernel_addr_r} ${ramdisk_addr_r};" \
"else echo Images not loades;fi\0" \
- "u-boot=" xstr(CONFIG_HOSTNAME) "/u-boot.img\0" \
+ "u-boot=" __stringify(CONFIG_HOSTNAME) "/u-boot.img\0" \
"load=tftp ${loadaddr} ${u-boot}\0" \
"loadmlo=tftp ${loadaddr} ${mlo}\0" \
- "mlo=" xstr(CONFIG_HOSTNAME) "/MLO\0" \
+ "mlo=" __stringify(CONFIG_HOSTNAME) "/MLO\0" \
"uboot_addr=0x80000\0" \
"update=nandecc sw;nand erase ${uboot_addr} 100000;" \
"nand write ${loadaddr} ${uboot_addr} 80000\0" \
#define CONFIG_SYS_BOARD_ODMDATA 0x2b0d8011
/* Board-specific serial config */
-#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTD /* UARTD: debug UART */
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#undef CONFIG_OF_CONTROL
#endif
-/* remove SERIAL_MULTI */
-#ifdef CONFIG_SERIAL_MULTI
-#undef CONFIG_SERIAL_MULTI
-#endif
-
/* remove I2C support */
#ifdef CONFIG_TEGRA_I2C
#undef CONFIG_TEGRA_I2C
#undef CONFIG_CMD_USB
#endif
+/* remove part command support */
+#ifdef CONFIG_PARTITION_UUIDS
+#undef CONFIG_PARTITION_UUIDS
+#endif
+
+#ifdef CONFIG_CMD_PART
+#undef CONFIG_CMD_PART
+#endif
+
#endif /* CONFIG_SPL_BUILD */
#endif /* __TEGRA_COMMON_POST_H */
#ifndef __TEGRA20_COMMON_H
#define __TEGRA20_COMMON_H
#include <asm/sizes.h>
-
-/*
- * QUOTE(m) will evaluate to a string version of the value of the macro m
- * passed in. The extra level of indirection here is to first evaluate the
- * macro m before applying the quoting operator.
- */
-#define QUOTE_(m) #m
-#define QUOTE(m) QUOTE_(m)
+#include <linux/stringify.h>
/*
* High Level Configuration Options
#define CONFIG_SYS_CACHELINE_SIZE 32
-#include <asm/arch/tegra20.h> /* get chip and board defs */
+#include <asm/arch/tegra.h> /* get chip and board defs */
/*
* Display CPU and Board information
#define TEGRA_LP0_ADDR 0x1C406000
#define TEGRA_LP0_SIZE 0x2000
#define TEGRA_LP0_VEC \
- "lp0_vec=" QUOTE(TEGRA_LP0_SIZE) "@" QUOTE(TEGRA_LP0_ADDR) " "
+ "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
+ "@" __stringify(TEGRA_LP0_ADDR) " "
#else
#define TEGRA_LP0_VEC
#endif
/* include default commands */
#include <config_cmd_default.h>
+#define CONFIG_PARTITION_UUIDS
+#define CONFIG_CMD_PART
/* remove unused commands */
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
#define CONFIG_ARM1176
#define CONFIG_TNETV107X
#define CONFIG_TNETV107X_EVM
+#define CONFIG_TNETV107X_WATCHDOG
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
#define CONFIG_DISABLE_TCM
#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
/* select serial console configuration */
-#define CONFIG_SERIAL_MULTI
#define CONFIG_SERIAL2 /* use SERIAL 2 */
#define CONFIG_BAUDRATE 115200
#define CONFIG_TEGRA_BOARD_STRING "Compulab Trimslice"
/* Board-specific serial config */
-#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_TEGRA_UARTA_GPU
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
* select serial console configuration
*/
#define CONFIG_PXA_SERIAL
-#define CONFIG_SERIAL_MULTI
#define CONFIG_FFUART 1 /* we use FFUART on Conxs */
#define CONFIG_BTUART 1 /* we use BTUART on Conxs */
#define CONFIG_STUART 1 /* we use STUART on Conxs */
+#define CONFIG_CONS_INDEX 3
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#define xstr(s) str(s)
-#define str(s) #s
-
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"nfsargs=setenv bootargs root=/dev/nfs rw " \
"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
"addmisc=setenv bootargs ${bootargs}\0" \
"u-boot=tx25/u-boot.bin\0" \
- "kernel_addr_r=" xstr(CONFIG_LOADADDR) "\0" \
+ "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
"hostname=tx25\0" \
"bootfile=tx25/uImage\0" \
"rootpath=/opt/eldk/arm\0" \
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
- "ethprime=" MK_STR(CONFIG_TSEC1_NAME) "\0" \
- "u-boot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
+ "netdev=" __stringify(CONFIG_NETDEV) "\0" \
+ "ethprime=" __stringify(CONFIG_TSEC1_NAME) "\0" \
+ "u-boot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"u-boot_addr_r=100000\0" \
"load=tftp ${u-boot_addr_r} ${u-boot}\0" \
- "update=protect off " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
- "erase " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
- "cp.b ${u-boot_addr_r} " MK_STR(CONFIG_SYS_FLASH_BASE) \
+ "update=protect off " __stringify(CONFIG_SYS_FLASH_BASE) \
+ " +${filesize};" \
+ "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize};" \
+ "cp.b ${u-boot_addr_r} " __stringify(CONFIG_SYS_FLASH_BASE) \
" ${filesize};" \
- "protect on " MK_STR(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
-
-#undef MK_STR
-#undef XMK_STR
+ "protect on " __stringify(CONFIG_SYS_FLASH_BASE) " +${filesize}\0" \
#endif /* __CONFIG_H */
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Ventana"
/* Board-specific serial config */
-#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTD
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
#define CONFIG_SYS_FLASH_PROTECTION /* The devices have real protection */
#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes */
#endif
#endif /* __CONFIG_H */
*-----------------------------------------------------------------------
*/
+#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
#include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MX5_HCLK 24000000
-#define CONFIG_SYS_MX5_CLK32 32768
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO
*/
#define CONFIG_PXA_SERIAL
#define CONFIG_FFUART 1
+#define CONFIG_CONS_INDEX 3
#define CONFIG_BAUDRATE 115200
/*
#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Whistler"
/* Board-specific serial config */
-#define CONFIG_SERIAL_MULTI
#define CONFIG_TEGRA_ENABLE_UARTA
#define CONFIG_TEGRA_UARTA_UAA_UAB
#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
*/
#define CONFIG_PXA_SERIAL
#define CONFIG_BTUART 1 /* we use BTUART on XAENIAX */
-
+#define CONFIG_CONS_INDEX 4
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
* ff000000 - ffbfffff OS Use/Filesystem (12MB)
*/
-#define CONFIG_UBOOT_ENV_ADDR MK_STR(CONFIG_SYS_TEXT_BASE)
-#define CONFIG_FDT_ENV_ADDR MK_STR(0xfff00000)
-#define CONFIG_OS_ENV_ADDR MK_STR(0xffc00000)
+#define CONFIG_UBOOT_ENV_ADDR __stringify(CONFIG_SYS_TEXT_BASE)
+#define CONFIG_FDT_ENV_ADDR __stringify(0xfff00000)
+#define CONFIG_OS_ENV_ADDR __stringify(0xffc00000)
#define CONFIG_PROG_UBOOT \
"$download_cmd $loadaddr $ubootfile; " \
* f6f00000 - f7efffff Sec OS image (16MB)
* f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
*/
-#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff00000)
-#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f00000)
-#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfffc0000)
-#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7fc0000)
-#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
-#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000)
+#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff00000)
+#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f00000)
+#define CONFIG_FDT1_ENV_ADDR __stringify(0xfffc0000)
+#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7fc0000)
+#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
#define CONFIG_PROG_UBOOT1 \
"$download_cmd $loadaddr $ubootfile; " \
* faf00000 - fbefffff Sec OS image (16MB)
* f8000000 - faefffff Sec OS Use/Filesystem (47MB)
*/
-#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
-#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xfbf80000)
-#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
-#define CONFIG_FDT2_ENV_ADDR MK_STR(0xfbf00000)
-#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
-#define CONFIG_OS2_ENV_ADDR MK_STR(0xfaf00000)
+#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
+#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xfbf80000)
+#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
+#define CONFIG_FDT2_ENV_ADDR __stringify(0xfbf00000)
+#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR __stringify(0xfaf00000)
#define CONFIG_PROG_UBOOT1 \
"$download_cmd $loadaddr $ubootfile; " \
* f6f00000 - f7efffff Sec OS image (16MB)
* f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
*/
-#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
-#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f80000)
-#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
-#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7f00000)
-#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
-#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000)
+#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
+#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
+#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
+#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
+#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
#define CONFIG_PROG_UBOOT1 \
"$download_cmd $loadaddr $ubootfile; " \
* f6f00000 - f7efffff Sec OS image (16MB)
* f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
*/
-#define CONFIG_UBOOT1_ENV_ADDR MK_STR(0xfff80000)
-#define CONFIG_UBOOT2_ENV_ADDR MK_STR(0xf7f80000)
-#define CONFIG_FDT1_ENV_ADDR MK_STR(0xfff00000)
-#define CONFIG_FDT2_ENV_ADDR MK_STR(0xf7f00000)
-#define CONFIG_OS1_ENV_ADDR MK_STR(0xfef00000)
-#define CONFIG_OS2_ENV_ADDR MK_STR(0xf6f00000)
+#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
+#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
+#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
+#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
+#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
+#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
#define CONFIG_PROG_UBOOT1 \
"$download_cmd $loadaddr $ubootfile; " \
#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
#define CONFIG_SYS_BASE_BAUD 691200
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SERIAL_MULTI
#define CONFIG_SYS_BAUDRATE_TABLE \
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
*/
#define CONFIG_PXA_SERIAL
#define CONFIG_STUART 1
+#define CONFIG_CONS_INDEX 2
#define CONFIG_BAUDRATE 115200
/*
#define CONFIG_BAUDRATE 115200
/* XPSS Serial driver */
-#define CONFIG_SERIAL_MULTI
#define CONFIG_ZYNQ_SERIAL
#define CONFIG_ZYNQ_SERIAL_BASEADDR0 0xE0001000
#define CONFIG_ZYNQ_SERIAL_BAUDRATE0 CONFIG_BAUDRATE
--- /dev/null
+/*
+ * (C) Copyright 2000-2010
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifdef DEFAULT_ENV_INSTANCE_EMBEDDED
+env_t environment __PPCENV__ = {
+ ENV_CRC, /* CRC Sum */
+#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
+ 1, /* Flags: valid */
+#endif
+ {
+#elif defined(DEFAULT_ENV_INSTANCE_STATIC)
+static char default_environment[] = {
+#else
+const uchar default_environment[] = {
+#endif
+#ifdef CONFIG_BOOTARGS
+ "bootargs=" CONFIG_BOOTARGS "\0"
+#endif
+#ifdef CONFIG_BOOTCOMMAND
+ "bootcmd=" CONFIG_BOOTCOMMAND "\0"
+#endif
+#ifdef CONFIG_RAMBOOTCOMMAND
+ "ramboot=" CONFIG_RAMBOOTCOMMAND "\0"
+#endif
+#ifdef CONFIG_NFSBOOTCOMMAND
+ "nfsboot=" CONFIG_NFSBOOTCOMMAND "\0"
+#endif
+#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
+ "bootdelay=" __stringify(CONFIG_BOOTDELAY) "\0"
+#endif
+#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0)
+ "baudrate=" __stringify(CONFIG_BAUDRATE) "\0"
+#endif
+#ifdef CONFIG_LOADS_ECHO
+ "loads_echo=" __stringify(CONFIG_LOADS_ECHO) "\0"
+#endif
+#ifdef CONFIG_ETHADDR
+ "ethaddr=" __stringify(CONFIG_ETHADDR) "\0"
+#endif
+#ifdef CONFIG_ETH1ADDR
+ "eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0"
+#endif
+#ifdef CONFIG_ETH2ADDR
+ "eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0"
+#endif
+#ifdef CONFIG_ETH3ADDR
+ "eth3addr=" __stringify(CONFIG_ETH3ADDR) "\0"
+#endif
+#ifdef CONFIG_ETH4ADDR
+ "eth4addr=" __stringify(CONFIG_ETH4ADDR) "\0"
+#endif
+#ifdef CONFIG_ETH5ADDR
+ "eth5addr=" __stringify(CONFIG_ETH5ADDR) "\0"
+#endif
+#ifdef CONFIG_ETHPRIME
+ "ethprime=" CONFIG_ETHPRIME "\0"
+#endif
+#ifdef CONFIG_IPADDR
+ "ipaddr=" __stringify(CONFIG_IPADDR) "\0"
+#endif
+#ifdef CONFIG_SERVERIP
+ "serverip=" __stringify(CONFIG_SERVERIP) "\0"
+#endif
+#ifdef CONFIG_SYS_AUTOLOAD
+ "autoload=" CONFIG_SYS_AUTOLOAD "\0"
+#endif
+#ifdef CONFIG_PREBOOT
+ "preboot=" CONFIG_PREBOOT "\0"
+#endif
+#ifdef CONFIG_ROOTPATH
+ "rootpath=" CONFIG_ROOTPATH "\0"
+#endif
+#ifdef CONFIG_GATEWAYIP
+ "gatewayip=" __stringify(CONFIG_GATEWAYIP) "\0"
+#endif
+#ifdef CONFIG_NETMASK
+ "netmask=" __stringify(CONFIG_NETMASK) "\0"
+#endif
+#ifdef CONFIG_HOSTNAME
+ "hostname=" __stringify(CONFIG_HOSTNAME) "\0"
+#endif
+#ifdef CONFIG_BOOTFILE
+ "bootfile=" CONFIG_BOOTFILE "\0"
+#endif
+#ifdef CONFIG_LOADADDR
+ "loadaddr=" __stringify(CONFIG_LOADADDR) "\0"
+#endif
+#ifdef CONFIG_CLOCKS_IN_MHZ
+ "clocks_in_mhz=1\0"
+#endif
+#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
+ "pcidelay=" __stringify(CONFIG_PCI_BOOTDELAY)"\0"
+#endif
+#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG
+ "arch=" CONFIG_SYS_ARCH "\0"
+ "cpu=" CONFIG_SYS_CPU "\0"
+ "board=" CONFIG_SYS_BOARD "\0"
+#ifdef CONFIG_SYS_VENDOR
+ "vendor=" CONFIG_SYS_VENDOR "\0"
+#endif
+#ifdef CONFIG_SYS_SOC
+ "soc=" CONFIG_SYS_SOC "\0"
+#endif
+#endif
+#ifdef CONFIG_EXTRA_ENV_SETTINGS
+ CONFIG_EXTRA_ENV_SETTINGS
+#endif
+ "\0"
+#ifdef DEFAULT_ENV_INSTANCE_EMBEDDED
+ }
+#endif
+};
#define I8042_STATUS_REG (CONFIG_SYS_ISA_IO + 0x0064) /* keyboard status read */
#define I8042_COMMAND_REG (CONFIG_SYS_ISA_IO + 0x0064) /* keyboard ctrl write */
+enum {
+ /* Output register (I8042_DATA_REG) has data for system */
+ I8042_STATUS_OUT_DATA = 1 << 0,
+ I8042_STATUS_IN_DATA = 1 << 1,
+};
+
#define KBD_US 0 /* default US layout */
#define KBD_GER 1 /* german layout */
/* exports */
+/**
+ * Flush all buffer from keyboard controller to host.
+ */
+void i8042_flush(void);
+
+/**
+ * Disables the keyboard so that key strokes no longer generate scancodes to
+ * the host.
+ *
+ * @return 0 if ok, -1 if keyboard input was found while disabling
+ */
+int i8042_disable(void);
+
int i8042_kbd_init(void);
int i8042_tstc(void);
int i8042_getc(void);
#define IDE_BUS(dev) (dev / (CONFIG_SYS_IDE_MAXDEVICE / CONFIG_SYS_IDE_MAXBUS))
#define ATA_CURR_BASE(dev) (CONFIG_SYS_ATA_BASE_ADDR+ide_bus_offset[IDE_BUS(dev)])
+extern ulong ide_bus_offset[];
#ifdef CONFIG_IDE_LED
#ifdef CONFIG_SYS_64BIT_LBA
typedef uint64_t lbaint_t;
+#define LBAF "%llx"
#else
typedef ulong lbaint_t;
+#define LBAF "%lx"
#endif
/*
*/
void ide_init(void);
-ulong ide_read(int device, lbaint_t blknr, ulong blkcnt, void *buffer);
-ulong ide_write(int device, lbaint_t blknr, ulong blkcnt, const void *buffer);
+ulong ide_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer);
+ulong ide_write(int device, ulong blknr, lbaint_t blkcnt, const void *buffer);
+
+#ifdef CONFIG_IDE_PREINIT
+int ide_preinit(void);
+#endif
+
+#ifdef CONFIG_IDE_INIT_POSTRESET
+int ide_init_postreset(void);
+#endif
#if defined(CONFIG_OF_IDE_FIXUP)
int ide_device_present(int dev);
void ide_read_data(int dev, ulong *sect_buf, int words);
void ide_write_data(int dev, ulong *sect_buf, int words);
#endif
+
+/*
+ * I/O function overrides
+ */
+void ide_input_swap_data(int dev, ulong *sect_buf, int words);
+void ide_input_data(int dev, ulong *sect_buf, int words);
+void ide_output_data(int dev, const ulong *sect_buf, int words);
+void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts);
+void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts);
+
#endif /* _IDE_H */
* @param config Input state
* @param keycode List of key codes to examine
* @param num_keycodes Number of key codes
+ * @return number of ascii characters sent, or 0 if none, or -1 for an
+ * internal error
*/
int input_send_keycodes(struct input_config *config, int keycode[], int count);
*/
int input_stdio_register(struct stdio_dev *dev);
+/**
+ * Set up the keyboard autorepeat delays
+ *
+ * @param repeat_delay_ms Delay before key auto-repeat starts (in ms)
+ * @param repeat_rate_ms Delay between successive key repeats (in ms)
+ */
+void input_set_delays(struct input_config *config, int repeat_delay_ms,
+ int repeat_rate_ms);
+
/**
* Set up the input handler with basic key maps.
*
* @param config Input state
* @param leds Initial LED value (INPUT_LED_ mask), 0 suggested
- * @param repeat_delay_ms Delay before key auto-repeat starts (in ms)
- * @param repeat_rate_ms Delay between successive key repeats (in ms)
* @return 0 if ok, -1 on error
*/
-int input_init(struct input_config *config, int leds, int repeat_delay_ms,
- int repeat_rate_ms);
+int input_init(struct input_config *config, int leds);
#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
extern int overwrite_console(void);
const u8 *plain_keycode; /* key code for each row / column */
const u8 *fn_keycode; /* ...when Fn held down */
int fn_pos; /* position of Fn key in key (or -1) */
+ int ghost_filter; /* non-zero to enable ghost filter */
};
/* Information about a particular key (row, column pair) in the matrix */
* @param config Keyboard matrix config
* @param rows Number of rows in key matrix
* @param cols Number of columns in key matrix
+ * @param ghost_filter Non-zero to enable ghost filtering
* @return 0 if ok, -1 on error
*/
-int key_matrix_init(struct key_matrix *config, int rows, int cols);
+int key_matrix_init(struct key_matrix *config, int rows, int cols,
+ int ghost_filter);
#endif
+++ /dev/null
-/*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * lh7a400 SoC interface
- */
-
-#ifndef __LH7A400_H__
-#define __LH7A400_H__
-
-#include "lh7a40x.h"
-
-/* Interrupt Controller (userguide 8.2.1) */
-typedef struct {
- volatile u32 intsr;
- volatile u32 intrsr;
- volatile u32 intens;
- volatile u32 intenc;
- volatile u32 rsvd1;
- volatile u32 rsvd2;
- volatile u32 rsvd3;
-} /*__attribute__((__packed__))*/ lh7a400_interrupt_t;
-#define LH7A400_INTERRUPT_BASE (0x80000500)
-#define LH7A400_INTERRUPT_PTR ((lh7a400_interrupt_t*) LH7A400_INTERRUPT_BASE)
-
-/* (DMA) Direct Memory Access Controller (userguide 9.2.1) */
-typedef struct {
- lh7a40x_dmachan_t chan[15];
- volatile u32 glblint;
- volatile u32 rsvd1;
- volatile u32 rsvd2;
- volatile u32 rsvd3;
-} /*__attribute__((__packed__))*/ lh7a400_dma_t;
-
-#define LH7A400_DMA_BASE (0x80002800)
-#define DMA_USBTX_OFFSET (0x000)
-#define DMA_USBRX_OFFSET (0x040)
-#define DMA_MMCTX_OFFSET (0x080)
-#define DMA_MMCRX_OFFSET (0x0C0)
-#define DMA_AC97_BASE (0x80002A00)
-
-#define LH7A400_DMA_PTR ((lh7a400_dma_t*) LH7A400_DMA_BASE)
-#define LH7A400_DMA_USBTX \
- ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_USBTX_OFFSET))
-#define LH7A400_DMA_USBRX \
- ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_USBRX_OFFSET))
-#define LH7A400_DMA_MMCTX \
- ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_MMCTX_OFFSET))
-#define LH7A400_DMA_MMCRX \
- ((lh7a400_dmachan_t*) (LH7A400_DMA_BASE + DMA_MMCRX_OFFSET))
-#define LH7A400_AC97RX(n) \
- ((lh7a400_dmachan_t*) (LH7A400_AC97_BASE + \
- ((2*n) * sizeof(lh7a400_dmachan_t))))
-#define LH7A400_AC97TX(n) \
- ((lh7a400_dmachan_t*) (LH7A400_AC97_BASE + \
- (((2*n)+1) * sizeof(lh7a400_dmachan_t))))
-
-#endif /* __LH7A400_H__ */
+++ /dev/null
-/*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * lh7a404 SoC interface
- */
-
-#ifndef __LH7A404_H__
-#define __LH7A404_H__
-
-#include "lh7a40x.h"
-
-/* Interrupt Controller (userguide 8.2.1) */
-typedef struct {
- volatile u32 irqstatus;
- volatile u32 fiqstatus;
- volatile u32 rawintr;
- volatile u32 intsel;
- volatile u32 inten;
- volatile u32 intenclr;
- volatile u32 softint;
- volatile u32 softintclr;
- volatile u32 protect;
- volatile u32 unused1;
- volatile u32 unused2;
- volatile u32 vectaddr;
- volatile u32 nvaddr;
- volatile u32 unused3[32];
- volatile u32 vad[16];
- volatile u32 unused4[44];
- volatile u32 vectcntl[16];
- volatile u32 unused5[44];
- volatile u32 itcr;
- volatile u32 itip1;
- volatile u32 itip2;
- volatile u32 itop1;
- volatile u32 itop2;
- volatile u32 unused6[333];
- volatile u32 periphid[4];
- volatile u32 pcellid[4];
-} /*__attribute__((__packed__))*/ lh7a404_vic_t;
-#define LH7A404_VIC_BASE (0x80008000)
-#define LH7A400_VIC_PTR(x) ((lh7a404_vic_t*)(LH7A400_VIC_BASE + (x*0x2000)))
-
-
-typedef struct {
- lh7a40x_dmachan_t m2p0_tx;
- lh7a40x_dmachan_t m2p1_rx;
- lh7a40x_dmachan_t m2p2_tx;
- lh7a40x_dmachan_t m2p3_rx;
- lh7a40x_dmachan_t m2m0;
- lh7a40x_dmachan_t m2m1;
- lh7a40x_dmachan_t unused1;
- lh7a40x_dmachan_t unused2;
- lh7a40x_dmachan_t m2p5_rx;
- lh7a40x_dmachan_t m2p4_tx;
- lh7a40x_dmachan_t m2p7_rx;
- lh7a40x_dmachan_t m2p6_tx;
- lh7a40x_dmachan_t m2p9_rx;
- lh7a40x_dmachan_t m2p8_tx;
- volatile u32 chanarb;
- volatile u32 glblint;
-} /*__attribute__((__packed__))*/ lh7a400_dma_t;
-
-
-#endif /* __LH7A404_H__ */
+++ /dev/null
-/*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * lh7a40x SoC series common interface
- */
-
-#ifndef __LH7A40X_H__
-#define __LH7A40X_H__
-
-/* (SMC) Static Memory Controller (usersguide 4.2.1) */
-typedef struct {
- volatile u32 attib;
- volatile u32 com;
- volatile u32 io;
- volatile u32 rsvd1;
-} /*__attribute__((__packed__))*/ lh7a40x_pccard_t;
-
-typedef struct {
- volatile u32 bcr[8];
- lh7a40x_pccard_t pccard[2];
- volatile u32 pcmciacon;
-} /*__attribute__((__packed__))*/ lh7a40x_smc_t;
-#define LH7A40X_SMC_BASE (0x80002000)
-#define LH7A40X_SMC_PTR ((lh7a40x_smc_t*) LH7A40X_SMC_BASE)
-
-/* (SDMC) Synchronous Dynamic Ram Controller (usersguide 5.3.1) */
-typedef struct {
- volatile u32 rsvd1;
- volatile u32 gblcnfg;
- volatile u32 rfshtmr;
- volatile u32 bootstat;
- volatile u32 sdcsc[4];
-} /*__attribute__((__packed__))*/ lh7a40x_sdmc_t;
-#define LH7A40X_SDMC_BASE (0x80002400)
-#define LH7A40X_SDMC_PTR ((lh7a40x_sdmc_t*) LH7A40X_SDMC_BASE)
-
-/* (CSC) Clock and State Controller (userguide 6.2.1) */
-typedef struct {
- volatile u32 pwrsr;
- volatile u32 pwrcnt;
- volatile u32 halt;
- volatile u32 stby;
- volatile u32 bleoi;
- volatile u32 mceoi;
- volatile u32 teoi;
- volatile u32 stfclr;
- volatile u32 clkset;
- volatile u32 scrreg[2];
- volatile u32 rsvd1;
- volatile u32 usbreset;
-} /*__attribute__((__packed__))*/ lh7a40x_csc_t;
-#define LH7A40X_STPWR_BASE (0x80000400)
-#define LH7A40X_CSC_PTR ((lh7a40x_csc_t*) LH7A40X_STPWR_BASE)
-
-#define CLKSET_SMCROM (0x01000000)
-#define CLKSET_PS (0x000C0000)
-#define CLKSET_PS_0 (0x00000000)
-#define CLKSET_PS_1 (0x00040000)
-#define CLKSET_PS_2 (0x00080000)
-#define CLKSET_PS_3 (0x000C0000)
-#define CLKSET_PCLKDIV (0x00030000)
-#define CLKSET_PCLKDIV_2 (0x00000000)
-#define CLKSET_PCLKDIV_4 (0x00010000)
-#define CLKSET_PCLKDIV_8 (0x00020000)
-#define CLKSET_MAINDIV2 (0x0000f800)
-#define CLKSET_MAINDIV1 (0x00000780)
-#define CLKSET_PREDIV (0x0000007C)
-#define CLKSET_HCLKDIV (0x00000003)
-
-/* (DMA) Direct Memory Access Controller (userguide 9.2.1) */
-typedef struct {
- volatile u32 maxcnt;
- volatile u32 base;
- volatile u32 current;
- volatile u32 rsvd1;
-} lh7a40x_dmabuf_t;
-
-typedef struct {
- volatile u32 control;
- volatile u32 interrupt;
- volatile u32 rsvd1;
- volatile u32 status;
- volatile u32 rsvd2;
- volatile u32 remain;
- volatile u32 rsvd3;
- volatile u32 rsvd4;
- lh7a40x_dmabuf_t buf[2];
-} /*__attribute__((__packed__))*/ lh7a40x_dmachan_t;
-
-
-/* (WDT) Watchdog Timer (userguide 11.2.1) */
-typedef struct {
- volatile u32 ctl;
- volatile u32 rst;
- volatile u32 status;
- volatile u32 count[4];
-} /*__attribute__((__packed__))*/ lh7a40x_wdt_t;
-#define LH7A40X_WDT_BASE (0x80001400)
-#define LH7A40X_WDT_PTR ((lh7a40x_wdt_t*) LH7A40X_WDT_BASE)
-
-/* (RTC) Real Time Clock (lh7a400 userguide 12.2.1, lh7a404 userguide 13.2.1) */
-typedef struct {
- volatile u32 rtcdr;
- volatile u32 rtclr;
- volatile u32 rtcmr;
- volatile u32 unk1;
- volatile u32 rtcstat_eoi;
- volatile u32 rtccr;
- volatile u32 rsvd1[58];
-} /*__attribute__((__packed__))*/ lh7a40x_rtc_t;
-#define LH7A40X_RTC_BASE (0x80000D00)
-#define LH7A40X_RTC_PTR ((lh7a40x_rtc_t*) LH7A40X_RTC_BASE)
-
-/* Timers (lh7a400 userguide 13.2.1, lh7a404 userguide 11.2.1) */
-typedef struct {
- volatile u32 load;
- volatile u32 value;
- volatile u32 control;
- volatile u32 tceoi;
-} /*__attribute__((__packed__))*/ lh7a40x_timer_t;
-
-typedef struct {
- lh7a40x_timer_t timer1;
- volatile u32 rsvd1[4];
- lh7a40x_timer_t timer2;
- volatile u32 unk1[4];
- volatile u32 bzcon;
- volatile u32 unk2[15];
- lh7a40x_timer_t timer3;
- /*volatile u32 rsvd2;*/
-} /*__attribute__((__packed__))*/ lh7a40x_timers_t;
-#define LH7A40X_TIMERS_BASE (0x80000C00)
-#define LH7A40X_TIMERS_PTR ((lh7a40x_timers_t*) LH7A40X_TIMERS_BASE)
-
-#define TIMER_EN (0x00000080)
-#define TIMER_PER (0x00000040)
-#define TIMER_FREE (0x00000000)
-#define TIMER_CLK508K (0x00000008)
-#define TIMER_CLK2K (0x00000000)
-
-/* (SSP) Sychronous Serial Ports (lh7a400 userguide 14.2.1, lh7a404 userguide 14.2.1) */
-typedef struct {
- volatile u32 cr0;
- volatile u32 cr1;
- volatile u32 irr_roeoi;
- volatile u32 dr;
- volatile u32 cpr;
- volatile u32 sr;
- /*volatile u32 rsvd1[58];*/
-} /*__attribute__((__packed__))*/ lh7a40x_ssp_t;
-#define LH7A40X_SSP_BASE (0x80000B00)
-#define LH7A40X_SSP_PTR ((lh7a40x_ssp_t*) LH7A40X_SSP_BASE)
-
-/* (UART) Universal Asychronous Receiver/Transmitter (lh7a400 userguide 15.2.1, lh7a404 userguide 15.2.1) */
-typedef struct {
- volatile u32 data;
- volatile u32 fcon;
- volatile u32 brcon;
- volatile u32 con;
- volatile u32 status;
- volatile u32 rawisr;
- volatile u32 inten;
- volatile u32 isr;
- volatile u32 rsvd1[56];
-} /*__attribute__((__packed__))*/ lh7a40x_uart_t;
-#define LH7A40X_UART_BASE (0x80000600)
-#define LH7A40X_UART_PTR(n) \
- ((lh7a40x_uart_t*) (LH7A40X_UART_BASE + ((n-1) * sizeof(lh7a40x_uart_t))))
-
-#define UART_BE (0x00000800) /* the rx error bits */
-#define UART_OE (0x00000400)
-#define UART_PE (0x00000200)
-#define UART_FE (0x00000100)
-
-#define UART_WLEN (0x00000060) /* fcon bits */
-#define UART_WLEN_8 (0x00000060)
-#define UART_WLEN_7 (0x00000040)
-#define UART_WLEN_6 (0x00000020)
-#define UART_WLEN_5 (0x00000000)
-#define UART_FEN (0x00000010)
-#define UART_STP2 (0x00000008)
-#define UART_STP2_2 (0x00000008)
-#define UART_STP2_1 (0x00000000)
-#define UART_EPS (0x00000004)
-#define UART_EPS_EVEN (0x00000004)
-#define UART_EPS_ODD (0x00000000)
-#define UART_PEN (0x00000002)
-#define UART_BRK (0x00000001)
-
-#define UART_BAUDDIV (0x0000ffff) /* brcon bits */
-
-#define UART_SIRBD (0x00000080) /* con bits */
-#define UART_LBE (0x00000040)
-#define UART_MXP (0x00000020)
-#define UART_TXP (0x00000010)
-#define UART_RXP (0x00000008)
-#define UART_SIRLP (0x00000004)
-#define UART_SIRD (0x00000002)
-#define UART_EN (0x00000001)
-
-#define UART_TXFE (0x00000080) /* status bits */
-#define UART_RXFF (0x00000040)
-#define UART_TXFF (0x00000020)
-#define UART_RXFE (0x00000010)
-#define UART_BUSY (0x00000008)
-#define UART_DCD (0x00000004)
-#define UART_DSR (0x00000002)
-#define UART_CTS (0x00000001)
-
-#define UART_MSEOI (0xfffffff0) /* rawisr interrupt bits */
-
-#define UART_RTI (0x00000008) /* generic interrupt bits */
-#define UART_MI (0x00000004)
-#define UART_TI (0x00000002)
-#define UART_RI (0x00000001)
-
-/* (GPIO) General Purpose IO and External Interrupts (userguide 16.2.1) */
-typedef struct {
- volatile u32 pad;
- volatile u32 pbd;
- volatile u32 pcd;
- volatile u32 pdd;
- volatile u32 padd;
- volatile u32 pbdd;
- volatile u32 pcdd;
- volatile u32 pddd;
- volatile u32 ped;
- volatile u32 pedd;
- volatile u32 kbdctl;
- volatile u32 pinmux;
- volatile u32 pfd;
- volatile u32 pfdd;
- volatile u32 pgd;
- volatile u32 pgdd;
- volatile u32 phd;
- volatile u32 phdd;
- volatile u32 rsvd1;
- volatile u32 inttype1;
- volatile u32 inttype2;
- volatile u32 gpiofeoi;
- volatile u32 gpiointen;
- volatile u32 intstatus;
- volatile u32 rawintstatus;
- volatile u32 gpiodb;
- volatile u32 papd;
- volatile u32 pbpd;
- volatile u32 pcpd;
- volatile u32 pdpd;
- volatile u32 pepd;
- volatile u32 pfpd;
- volatile u32 pgpd;
- volatile u32 phpd;
-} /*__attribute__((__packed__))*/ lh7a40x_gpioint_t;
-#define LH7A40X_GPIOINT_BASE (0x80000E00)
-#define LH7A40X_GPIOINT_PTR ((lh7a40x_gpioint_t*) LH7A40X_GPIOINT_BASE)
-
-/* Embedded SRAM */
-#define CONFIG_SYS_SRAM_BASE (0xB0000000)
-#define CONFIG_SYS_SRAM_SIZE (80*1024) /* 80kB */
-
-#endif /* __LH7A40X_H__ */
--- /dev/null
+/*
+ * include/linker_lists.h
+ *
+ * Implementation of linker-generated arrays
+ *
+ * Copyright (C) 2012 Marek Vasut <marex@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+#ifndef __LINKER_LISTS_H__
+#define __LINKER_LISTS_H__
+
+/**
+ * ll_entry_declare() - Declare linker-generated array entry
+ * @_type: Data type of the entry
+ * @_name: Name of the entry
+ * @_section_u: Subsection of u_boot_list in which this entry is placed
+ * (with underscores instead of dots, for name concatenation)
+ * @_section_d: Subsection of u_boot_list in which this entry is placed
+ * (with dots, for section concatenation)
+ *
+ * This macro declares a variable that is placed into a linker-generated
+ * array. This is a basic building block for more advanced use of linker-
+ * generated arrays. The user is expected to build their own macro wrapper
+ * around this one.
+ *
+ * A variable declared using this macro must be compile-time initialized
+ * and is as such placed into subsection of special section, .u_boot_list.
+ * The subsection is specified by the _section_[u,d] parameter, see below.
+ * The base name of the variable is _name, yet the actual variable is
+ * declared as concatenation of
+ *
+ * %_u_boot_list_ + @_section_u + _ + @_name
+ *
+ * which ensures name uniqueness. This variable shall never be refered
+ * directly though.
+ *
+ * Special precaution must be made when using this macro:
+ * 1) The _type must not contain the "static" keyword, otherwise the entry
+ * is not generated.
+ *
+ * 2) The @_section_u and @_section_d variables must match, the only difference
+ * is that in @_section_u is every dot "." character present in @_section_d
+ * replaced by a single underscore "_" character in @_section_u. The actual
+ * purpose of these parameters is to select proper subsection in the global
+ * .u_boot_list section.
+ *
+ * 3) In case a section is declared that contains some array elements AND a
+ * subsection of this section is declared and contains some elements, it is
+ * imperative that the elements are of the same type.
+ *
+ * 4) In case an outer section is declared that contains some array elements
+ * AND am inner subsection of this section is declared and contains some
+ * elements, then when traversing the outer section, even the elements of
+ * the inner sections are present in the array.
+ *
+ * Example:
+ * ll_entry_declare(struct my_sub_cmd, my_sub_cmd, cmd_sub, cmd.sub) = {
+ * .x = 3,
+ * .y = 4,
+ * };
+ */
+#define ll_entry_declare(_type, _name, _section_u, _section_d) \
+ _type _u_boot_list_##_section_u##_##_name __attribute__(( \
+ unused, aligned(4), \
+ section(".u_boot_list."#_section_d"."#_name)))
+
+/**
+ * ll_entry_start() - Point to first entry of linker-generated array
+ * @_type: Data type of the entry
+ * @_section_u: Subsection of u_boot_list in which this entry is placed
+ * (with underscores instead of dots)
+ *
+ * This function returns (_type *) pointer to the very first entry of a
+ * linker-generated array placed into subsection of .u_boot_list section
+ * specified by _section_u argument.
+ *
+ * Example:
+ * struct my_sub_cmd *msc = ll_entry_start(struct my_sub_cmd, cmd_sub);
+ */
+#define ll_entry_start(_type, _section_u) \
+ ({ \
+ extern _type _u_boot_list_##_section_u##__start; \
+ _type *_ll_result = &_u_boot_list_##_section_u##__start;\
+ _ll_result; \
+ })
+
+/**
+ * ll_entry_count() - Return the number of elements in linker-generated array
+ * @_type: Data type of the entry
+ * @_section_u: Subsection of u_boot_list in which this entry is placed
+ * (with underscores instead of dots)
+ *
+ * This function returns the number of elements of a linker-generated array
+ * placed into subsection of .u_boot_list section specified by _section_u
+ * argument. The result is of an unsigned int type.
+ *
+ * Example:
+ * int i;
+ * const unsigned int count = ll_entry_count(struct my_sub_cmd, cmd_sub);
+ * struct my_sub_cmd *msc = ll_entry_start(struct my_sub_cmd, cmd_sub);
+ * for (i = 0; i < count; i++, msc++)
+ * printf("Entry %i, x=%i y=%i\n", i, msc->x, msc->y);
+ */
+#define ll_entry_count(_type, _section_u) \
+ ({ \
+ extern _type _u_boot_list_##_section_u##__start; \
+ extern _type _u_boot_list_##_section_u##__end; \
+ unsigned int _ll_result = \
+ &_u_boot_list_##_section_u##__end - \
+ &_u_boot_list_##_section_u##__start; \
+ _ll_result; \
+ })
+
+
+/**
+ * ll_entry_get() - Retrieve entry from linker-generated array by name
+ * @_type: Data type of the entry
+ * @_name: Name of the entry
+ * @_section_u: Subsection of u_boot_list in which this entry is placed
+ * (with underscores instead of dots)
+ *
+ * This function returns a pointer to a particular entry in LG-array
+ * identified by the subsection of u_boot_list where the entry resides
+ * and it's name.
+ *
+ * Example:
+ * ll_entry_declare(struct my_sub_cmd, my_sub_cmd, cmd_sub, cmd.sub) = {
+ * .x = 3,
+ * .y = 4,
+ * };
+ * ...
+ * struct my_sub_cmd *c = ll_entry_get(struct my_sub_cmd, my_sub_cmd, cmd_sub);
+ */
+#define ll_entry_get(_type, _name, _section_u) \
+ ({ \
+ extern _type _u_boot_list_##_section_u##_##_name; \
+ _type *_ll_result = &_u_boot_list_##_section_u##_##_name;\
+ _ll_result; \
+ })
+
+#endif /* __LINKER_LISTS_H__ */
--- /dev/null
+#ifndef __LINUX_STRINGIFY_H
+#define __LINUX_STRINGIFY_H
+
+/* Indirect stringification. Doing two levels allows the parameter to be a
+ * macro itself. For example, compile with -DFOO=bar, __stringify(FOO)
+ * converts to "bar".
+ */
+
+#define __stringify_1(x...) #x
+#define __stringify(x...) __stringify_1(x)
+
+#endif /* !__LINUX_STRINGIFY_H */
+++ /dev/null
-/*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Logic lh7a400-10 Card Engine CPLD interface
- */
-
-#ifndef __LPD7A400_CPLD_H_
-#define __LPD7A400_CPLD_H_
-
-
-/*
- * IO Controller Address and Register Definitions
- * - using LH7A400-10 Card Engine IO Controller Specification
- * (logic PN: 70000079)
- */
-
-/*------------------------------------------------------------------
- * Slow Peripherals (nCS6)
- */
-#define LPD7A400_CPLD_CF (0x60200000)
-#define LPD7A400_CPLD_ISA (0x60400000)
-
-/*------------------------------------------------------------------
- * Fast Peripherals (nCS7)
- *
- * The CPLD directs access to 0x70000000-0x701fffff to the onboard
- * ethernet controller
- */
-#define LPD7A400_CPLD_WLAN_BASE (0x70000000)
-
-/* All registers are 8 bit */
-#define LPD7A400_CPLD_CECTL_REG (0x70200000)
-#define LPD7A400_CPLD_SPIDATA_REG (0x70600000)
-#define LPD7A400_CPLD_SPICTL_REG (0x70800000)
-#define LPD7A400_CPLD_EEPSPI_REG (0x70a00000)
-#define LPD7A400_CPLD_INTMASK_REG (0x70c00000)
-#define LPD7A400_CPLD_MODE_REG (0x70e00000)
-#define LPD7A400_CPLD_FLASH_REG (0x71000000)
-#define LPD7A400_CPLD_PWRMG_REG (0x71200000)
-#define LPD7A400_CPLD_REV_REG (0x71400000)
-#define LPD7A400_CPLD_EXTGPIO_REG (0x71600000)
-#define LPD7A400_CPLD_GPIODATA_REG (0x71800000)
-#define LPD7A400_CPLD_GPIODIR_REG (0x71a00000)
-
-#define LPD7A400_CPLD_REGPTR (volatile u8*)
-
-/* Card Engine Control Register (section 3.1.2) */
-#define CECTL_SWINT (0x80) /* Software settable interrupt source
- (routed to uP PF3)
- 0 = generate interrupt, 1 = do not */
-#define CECTL_OCMSK (0x40) /* USB1 connection interrupt mask
- 0 = not masked, 1 = masked */
-#define CECTL_PDRV (0x20) /* PCC_nDRV output
- 0 = active, 1 = inactive */
-#define CECTL_USB1C (0x10) /* USB1 connection interrupt
- 0 = active, 1 = inactive */
-#define CECTL_USB1P (0x08) /* USB1 Power enable
- 0 = enabled, 1 = disabled */
-#define CECTL_AWKP (0x04) /* Auto-Wakeup enable
- 0 = enabled, 1 = disabled */
-#define CECTL_LCDV (0x02) /* LCD VEE enable
- 0 = disabled, 1 = enabled */
-#define CECTL_WLPE (0x01) /* Wired LAN power enable
- 0 = enabled, 1 = disabled */
-
-/* SPI Control Register (section 3.1.5) */
-#define SPICTL_SPLD (0x20) /* SPI load (R)
- 0 = data reg. has not been loaded, shift
- count has not been reset
- 1 = data reg. loaded, shift count reset */
-#define SPICTL_SPST (0x10) /* SPI start (RW)
- 0 = don't load data reg. and reset shift count
- 1 = ready to load data reg and reset shift count */
-#define SPICTL_SPDN (0x08) /* SPI done (R)
- 0 = not done
- 1 = access done */
-#define SPICTL_SPRW (0x04) /* SPI read/write (RW)
- 0 = SPI write access
- 1 = SPI read access */
-#define SPICTL_STCS (0x02) /* SPI touch chip select (RW)
- 0 = not selected
- 1 = selected */
-#define SPICTL_SCCS (0x01) /* SPI CODEC chip select (RW) {not used}
- 0 = not selected
- 1 = selected */
-
-/* EEPROM SPI Interface Register (section 3.1.6) */
-#define EEPSPI_EECS (0x08) /* EEPROM chip select (RW)
- 0 = not selected
- 1 = selected */
-#define EEPSPI_EECK (0x04) /* EEPROM SPI clock (RW) */
-#define EEPSPI_EETX (0x02) /* EEPROM SPI tx data (RW) */
-#define EEPSPI_EERX (0x01) /* EEPROM SPI rx data (R) */
-
-/* Interrupt/Mask Register (section 3.1.7) */
-#define INTMASK_CMSK (0x80) /* CPLD_nIRQD interrupt mask (RW)
- 0 = not masked
- 1 = masked */
-#define INTMASK_CIRQ (0x40) /* interrupt signal to CPLD (R)
- 0 = interrupt active
- 1 = no interrupt */
-#define INTMASK_PIRQ (0x10) /* legacy, no effect */
-#define INTMASK_TMSK (0x08) /* Touch chip interrupt mask (RW)
- 0 = not masked
- 1 = masked */
-#define INTMASK_WMSK (0x04) /* Wired LAN interrupt mask (RW)
- 0 = not masked
- 1 = masked */
-#define INTMASK_TIRQ (0x02) /* Touch chip interrupt request (R)
- 0 = interrupt active
- 1 = no interrupt */
-#define INTMASK_WIRQ (0x01) /* Wired LAN interrupt request (R)
- 0 = interrupt active
- 1 = no interrupt */
-
-/* Mode Register (section 3.1.8) */
-#define MODE_VS1 (0x80) /* PCMCIA Voltage Sense 1 input (PCC_VS1) (R)
- 0 = active slot VS1 pin is low
- 1 = active slot VS1 pin is high */
-#define MODE_CD2 (0x40) /* PCMCIA Card Detect 2 input (PCC_nCD2) (R)
- 0 = active slot CD2 is low
- 1 = active slot CD2 is high */
-#define MODE_IOIS16 (0x20) /* PCMCIA IOIS16 input (PCC_nIOIS16) (R)
- 0 = 16 bit access area
- 1 = 8 bit access area */
-#define MODE_CD1 (0x10) /* PCMCIA Card Detect 1 input (PCC_nCD1) (R)
- 0 = active slot CD1 is low
- 1 = active slot CD1 is high */
-#define MODE_upMODE3 (0x08) /* Mode Pin 3 (R)
- 0 = off-board boot device
- 1 = on-board boot device (flash) */
-#define MODE_upMODE2 (0x04) /* Mode Pin 2 (R) (LH7A400 Little Endian only)
- 0 = big endian
- 1 = little endian */
-#define MODE_upMODE1 (0x02) /* Mode Pin 1 and Mode Pin 2 (R) */
-#define MODE_upMODE0 (0x01) /* - bus width at boot */
-
-
-/* Flash Register (section 3.1.9) */
-#define FLASH_FPOP (0x08) /* Flash populated (RW)
- 0 = populated, 1 = not */
-#define FLASH_FST2 (0x04) /* Flash status (R) (RY/BY# pin for upper 16 bit chip
- 0 = busy, 1 = ready */
-#define FLASH_FST1 (0x02) /* Flash status (R) (RY/BY# pin for lower 16 bit chip
- 0 = busy, 1 = ready */
-#define FLASH_FPEN (0x01) /* Flash program enable (RW)
- 0 = flash write protected
- 1 = programming enabled */
-
-/* Power Management Register (section 3.1.10)
- * - when either of these is low an unmaskable interrupt to cpu
- * is generated
- */
-#define PWRMG_STBY (0x10) /* state of nSTANDBY signal to CPLD (R)
- 0 = low, 1 = high */
-#define PWRMG_SPND (0x04) /* state of nSUSPEND signal to CPLD (R)
- 0 = low, 1 = high */
-
-
-/* Extended GPIO Register (section 3.1.12) */
-#define EXTGPIO_STATUS1 (0x04) /* Status 1 output (RW) (uP_STATUS_1)
- 0 = set pin low, 1 = set pin high */
-#define EXTGPIO_STATUS2 (0x02) /* Status 2 output (RW) (uP_STATUS_2)
- 0 = set pin low, 1 = set pin high */
-#define EXTGPIO_GPIO1 (0x01) /* General purpose output (RW) (CPLD_GPIO_1)
- 0 = set pin low, 1 = set pin high */
-
-/* GPIO Data Register (section 3.1.13) */
-#define GPIODATA_GPIO2 (0x01) /* General purpose input/output (RW) (CPLD_GPIO_2)
- 0 = set low (output) / read low (input)
- 1 = set high (output) / read high (input) */
-
-/* GPIO Direction Register (section 3.1.14) */
-#define GPIODIR_GPDR0 (0x01) /* GPIO2 direction (RW)
- 0 = output, 1 = input */
-
-#endif /* __LH7A400_H__ */
#ifndef __NIOS2_H__
#define __NIOS2_H__
+#include <linux/stringify.h>
+
/*------------------------------------------------------------------------
* Control registers -- use with wrctl() & rdctl()
*----------------------------------------------------------------------*/
/*------------------------------------------------------------------------
* Access to control regs
*----------------------------------------------------------------------*/
-#define _str_(x) #x
#define rdctl(reg)\
({unsigned int val;\
- asm volatile( "rdctl %0, ctl" _str_(reg)\
+ asm volatile("rdctl %0, ctl" __stringify(reg) \
: "=r" (val) ); val;})
#define wrctl(reg,val)\
#ifndef __SATA_H__
#define __SATA_H__
+#include <part.h>
int init_sata(int dev);
int scan_sata(int dev);
-ulong sata_read(int dev, ulong blknr, ulong blkcnt, void *buffer);
-ulong sata_write(int dev, ulong blknr, ulong blkcnt, const void *buffer);
+ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer);
+ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer);
int sata_initialize(void);
int __sata_initialize(void);
+extern block_dev_desc_t sata_dev_desc[];
+
#endif
struct serial_device {
/* enough bytes to match alignment of following func pointer */
- char name[16];
-
- int (*init) (void);
- int (*uninit) (void);
- void (*setbrg) (void);
- int (*getc) (void);
- int (*tstc) (void);
- void (*putc) (const char c);
- void (*puts) (const char *s);
+ char name[16];
+
+ int (*start)(void);
+ int (*stop)(void);
+ void (*setbrg)(void);
+ int (*getc)(void);
+ int (*tstc)(void);
+ void (*putc)(const char c);
+ void (*puts)(const char *s);
#if CONFIG_POST & CONFIG_SYS_POST_UART
- void (*loop) (int);
+ void (*loop)(int);
#endif
-
- struct serial_device *next;
+ struct serial_device *next;
};
+void default_serial_puts(const char *s);
+
extern struct serial_device serial_smc_device;
extern struct serial_device serial_scc_device;
extern struct serial_device *default_serial_console(void);
defined(CONFIG_MICROBLAZE)
extern struct serial_device serial0_device;
extern struct serial_device serial1_device;
-#if defined(CONFIG_SYS_NS16550_SERIAL)
-extern struct serial_device eserial1_device;
-extern struct serial_device eserial2_device;
-extern struct serial_device eserial3_device;
-extern struct serial_device eserial4_device;
-#endif /* CONFIG_SYS_NS16550_SERIAL */
-
#endif
-#if defined(CONFIG_MPC512X)
-extern struct serial_device serial1_device;
-extern struct serial_device serial3_device;
-extern struct serial_device serial4_device;
-extern struct serial_device serial6_device;
-#endif
-
-#if defined(CONFIG_XILINX_UARTLITE)
-extern struct serial_device uartlite_serial0_device;
-extern struct serial_device uartlite_serial1_device;
-extern struct serial_device uartlite_serial2_device;
-extern struct serial_device uartlite_serial3_device;
-#endif
-
-#if defined(CONFIG_S3C2410)
-extern struct serial_device s3c24xx_serial0_device;
-extern struct serial_device s3c24xx_serial1_device;
-extern struct serial_device s3c24xx_serial2_device;
-#endif
-
-#if defined(CONFIG_S5P)
-extern struct serial_device s5p_serial0_device;
-extern struct serial_device s5p_serial1_device;
-extern struct serial_device s5p_serial2_device;
-extern struct serial_device s5p_serial3_device;
-#endif
-
-#if defined(CONFIG_OMAP3_ZOOM2)
-extern struct serial_device zoom2_serial_device0;
-extern struct serial_device zoom2_serial_device1;
-extern struct serial_device zoom2_serial_device2;
-extern struct serial_device zoom2_serial_device3;
-#endif
-
-extern struct serial_device serial_ffuart_device;
-extern struct serial_device serial_btuart_device;
-extern struct serial_device serial_stuart_device;
-
-#if defined(CONFIG_SYS_BFIN_UART)
-extern void serial_register_bfin_uart(void);
-extern struct serial_device bfin_serial0_device;
-extern struct serial_device bfin_serial1_device;
-extern struct serial_device bfin_serial2_device;
-extern struct serial_device bfin_serial3_device;
-#endif
-
-#if defined(CONFIG_ZYNQ_SERIAL)
-extern struct serial_device uart_zynq_serial0_device;
-extern struct serial_device uart_zynq_serial1_device;
-#endif
+extern struct serial_device eserial1_device;
+extern struct serial_device eserial2_device;
extern void serial_register(struct serial_device *);
extern void serial_initialize(void);
#endif /* CONFIG_USB_TTY */
-#if defined(CONFIG_MPC512X) && defined(CONFIG_SERIAL_MULTI)
+#if defined(CONFIG_MPC512X)
extern struct stdio_dev *open_port(int num, int baudrate);
extern int close_port(int num);
extern int write_port(struct stdio_dev *port, char *buf);
int portnr;
struct usb_device *parent;
struct usb_device *children[USB_MAXCHILDREN];
+
+ void *controller; /* hardware controller private data */
};
/**********************************************************************
defined(CONFIG_USB_OMAP3) || defined(CONFIG_USB_DA8XX) || \
defined(CONFIG_USB_BLACKFIN) || defined(CONFIG_USB_AM35X)
-int usb_lowlevel_init(void);
-int usb_lowlevel_stop(void);
+int usb_lowlevel_init(int index, void **controller);
+int usb_lowlevel_stop(int index);
+
int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
void *buffer, int transfer_len);
int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
#define USB_UHCI_VEND_ID 0x8086
#define USB_UHCI_DEV_ID 0x7112
+/*
+ * PXA25x can only act as USB device. There are drivers
+ * which works with USB CDC gadgets implementations.
+ * Some of them have common routines which can be used
+ * in boards init functions e.g. udc_disconnect() used for
+ * forced device disconnection from host.
+ */
+#elif defined(CONFIG_USB_GADGET_PXA2XX)
+
+extern void udc_disconnect(void);
+
#else
#error USB Lowlevel not defined
#endif
int hub_port_reset(struct usb_device *dev, int port,
unsigned short *portstat);
-struct usb_device *usb_alloc_new_device(void);
+struct usb_device *usb_alloc_new_device(void *controller);
+
int usb_new_device(struct usb_device *dev);
#endif /*_USB_H_ */
#define INFO_BUFFER_ERROR (1 << 5)
#define INFO_TX_ERROR (1 << 3)
-extern int usb_lowlevel_init(void);
+extern int usb_lowlevel_init(int index, void **controller);
#endif /* __MV_UDC_H__ */
*
* returns 0 on success, ULPI_ERROR on failure.
*/
-int ulpi_set_vbus(struct ulpi_viewport *ulpi_vp,
- int on, int ext_power, int ext_ind);
+int ulpi_set_vbus(struct ulpi_viewport *ulpi_vp, int on, int ext_power);
+
+/*
+ * Configure VBUS indicator
+ * @external - external VBUS over-current indicator is used
+ * @passthru - disables ANDing of internal VBUS comparator
+ * with external VBUS input
+ * @complement - inverts the external VBUS input
+ */
+int ulpi_set_vbus_indicator(struct ulpi_viewport *ulpi_vp, int external,
+ int passthru, int complement);
/*
* Enable/disable pull-down resistors on D+ and D- USB lines.
#ifndef CONFIG_SYS_VXWORKS_BOOT_DEVICE
#if defined(CONFIG_4xx)
#define CONFIG_SYS_VXWORKS_BOOT_DEVICE "emac(0,0)"
-#elif defined(CONFIG_IOP480)
-#define CONFIG_SYS_VXWORKS_BOOT_DEVICE "dc(0,0)"
#else
#define CONFIG_SYS_VXWORKS_BOOT_DEVICE "eth(0,0)"
#endif
$(LIB): $(obj).depend $(OBJS)
$(call cmd_link_o_target, $(OBJS))
+# SEE README.arm-unaligned-accesses
+$(obj)bzlib.o: CFLAGS += $(PLATFORM_NO_UNALIGNED)
+
#########################################################################
# defines $(obj).depend target
#include <errno.h>
#include <common.h>
-#if !defined (CONFIG_PANIC_HANG)
+#if !defined(CONFIG_PANIC_HANG)
#include <command.h>
#endif
#include <div64.h>
-# define NUM_TYPE long long
#define noinline __attribute__((noinline))
/* some reluctance to put this into a new limits.h, so it is here */
return buf;
}
-unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base)
+unsigned long simple_strtoul(const char *cp, char **endp,
+ unsigned int base)
{
- unsigned long result = 0,value;
+ unsigned long result = 0;
+ unsigned long value;
if (*cp == '0') {
cp++;
base = 16;
cp++;
}
- if (!base) {
+
+ if (!base)
base = 8;
- }
}
- if (!base) {
+
+ if (!base)
base = 10;
- }
+
while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp)
? toupper(*cp) : *cp)-'A'+10) < base) {
result = result*base + value;
cp++;
}
+
if (endp)
*endp = (char *)cp;
+
return result;
}
return -EINVAL;
}
-long simple_strtol(const char *cp,char **endp,unsigned int base)
+long simple_strtol(const char *cp, char **endp, unsigned int base)
{
- if(*cp=='-')
- return -simple_strtoul(cp+1,endp,base);
- return simple_strtoul(cp,endp,base);
+ if (*cp == '-')
+ return -simple_strtoul(cp + 1, endp, base);
+
+ return simple_strtoul(cp, endp, base);
}
int ustrtoul(const char *cp, char **endp, unsigned int base)
{
unsigned long result = simple_strtoul(cp, endp, base);
switch (**endp) {
- case 'G' :
+ case 'G':
result *= 1024;
/* fall through */
case 'M':
return result;
}
-unsigned long long simple_strtoull (const char *cp, char **endp, unsigned int base)
+unsigned long long simple_strtoull(const char *cp, char **endp,
+ unsigned int base)
{
unsigned long long result = 0, value;
if (*cp == '0') {
cp++;
- if ((*cp == 'x') && isxdigit (cp[1])) {
+ if ((*cp == 'x') && isxdigit(cp[1])) {
base = 16;
cp++;
}
- if (!base) {
+
+ if (!base)
base = 8;
- }
}
- if (!base) {
+
+ if (!base)
base = 10;
- }
- while (isxdigit (*cp) && (value = isdigit (*cp)
- ? *cp - '0'
- : (islower (*cp) ? toupper (*cp) : *cp) - 'A' + 10) < base) {
+
+ while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp - '0'
+ : (islower(*cp) ? toupper(*cp) : *cp) - 'A' + 10) < base) {
result = result * base + value;
cp++;
}
+
if (endp)
*endp = (char *) cp;
+
return result;
}
static int skip_atoi(const char **s)
{
- int i=0;
+ int i = 0;
while (is_digit(**s))
- i = i*10 + *((*s)++) - '0';
+ i = i * 10 + *((*s)++) - '0';
+
return i;
}
/* Formats correctly any integer in [0,99999].
* Outputs from one to five digits depending on input.
* On i386 gcc 4.1.2 -O2: ~250 bytes of code. */
-static char* put_dec_trunc(char *buf, unsigned q)
+static char *put_dec_trunc(char *buf, unsigned q)
{
unsigned d3, d2, d1, d0;
d1 = (q>>4) & 0xf;
d3 = d3 - 10*q;
*buf++ = d3 + '0'; /* next digit */
if (q != 0)
- *buf++ = q + '0'; /* most sign. digit */
+ *buf++ = q + '0'; /* most sign. digit */
}
}
}
return buf;
}
/* Same with if's removed. Always emits five digits */
-static char* put_dec_full(char *buf, unsigned q)
+static char *put_dec_full(char *buf, unsigned q)
{
/* BTW, if q is in [0,9999], 8-bit ints will be enough, */
/* but anyway, gcc produces better code with full-sized ints */
return buf;
}
/* No inlining helps gcc to use registers better */
-static noinline char* put_dec(char *buf, unsigned NUM_TYPE num)
+static noinline char *put_dec(char *buf, u64 num)
{
while (1) {
unsigned rem;
#define ADDCH(str, ch) (*(str)++ = (ch))
#endif
-static char *number(char *buf, char *end, unsigned NUM_TYPE num,
+static char *number(char *buf, char *end, u64 num,
int base, int size, int precision, int type)
{
/* we are called with base 8, 10 or 16, only, thus don't need "G..." */
- static const char digits[16] = "0123456789ABCDEF"; /* "GHIJKLMNOPQRSTUVWXYZ"; */
+ static const char digits[16] = "0123456789ABCDEF";
char tmp[66];
char sign;
type &= ~ZEROPAD;
sign = 0;
if (type & SIGN) {
- if ((signed NUM_TYPE) num < 0) {
+ if ((s64) num < 0) {
sign = '-';
- num = - (signed NUM_TYPE) num;
+ num = -(s64) num;
size--;
} else if (type & PLUS) {
sign = '+';
else if (base != 10) { /* 8 or 16 */
int mask = base - 1;
int shift = 3;
- if (base == 16) shift = 4;
+
+ if (base == 16)
+ shift = 4;
+
do {
- tmp[i++] = (digits[((unsigned char)num) & mask] | locase);
+ tmp[i++] = (digits[((unsigned char)num) & mask]
+ | locase);
num >>= shift;
} while (num);
} else { /* base 10 */
static char *mac_address_string(char *buf, char *end, u8 *addr, int field_width,
int precision, int flags)
{
- char mac_addr[6 * 3]; /* (6 * 2 hex digits), 5 colons and trailing zero */
+ /* (6 * 2 hex digits), 5 colons and trailing zero */
+ char mac_addr[6 * 3];
char *p = mac_addr;
int i;
static char *ip6_addr_string(char *buf, char *end, u8 *addr, int field_width,
int precision, int flags)
{
- char ip6_addr[8 * 5]; /* (8 * 4 hex digits), 7 colons and trailing zero */
+ /* (8 * 4 hex digits), 7 colons and trailing zero */
+ char ip6_addr[8 * 5];
char *p = ip6_addr;
int i;
static char *ip4_addr_string(char *buf, char *end, u8 *addr, int field_width,
int precision, int flags)
{
- char ip4_addr[4 * 4]; /* (4 * 3 decimal digits), 3 dots and trailing zero */
+ /* (4 * 3 decimal digits), 3 dots and trailing zero */
+ char ip4_addr[4 * 4];
char temp[3]; /* hold each IP quad in reverse order */
char *p = ip4_addr;
int i, digits;
static int vsnprintf_internal(char *buf, size_t size, const char *fmt,
va_list args)
{
- unsigned NUM_TYPE num;
+ u64 num;
int base;
char *str;
/* process flags */
flags = 0;
- repeat:
+repeat:
++fmt; /* this also skips first '%' */
switch (*fmt) {
- case '-': flags |= LEFT; goto repeat;
- case '+': flags |= PLUS; goto repeat;
- case ' ': flags |= SPACE; goto repeat;
- case '#': flags |= SPECIAL; goto repeat;
- case '0': flags |= ZEROPAD; goto repeat;
+ case '-':
+ flags |= LEFT;
+ goto repeat;
+ case '+':
+ flags |= PLUS;
+ goto repeat;
+ case ' ':
+ flags |= SPACE;
+ goto repeat;
+ case '#':
+ flags |= SPECIAL;
+ goto repeat;
+ case '0':
+ flags |= ZEROPAD;
+ goto repeat;
}
/* get field width */
continue;
case 'p':
- str = pointer(fmt+1, str, end,
+ str = pointer(fmt + 1, str, end,
va_arg(args, void *),
field_width, precision, flags);
/* Skip all alphanumeric pointer suffixes */
case 'n':
if (qualifier == 'l') {
- long * ip = va_arg(args, long *);
+ long *ip = va_arg(args, long *);
*ip = (str - buf);
} else {
- int * ip = va_arg(args, int *);
+ int *ip = va_arg(args, int *);
*ip = (str - buf);
}
continue;
*str = '\0';
#endif
/* the trailing null byte doesn't count towards the total */
- return str-buf;
+ return str - buf;
}
#ifdef CONFIG_SYS_VSNPRINTF
return vsnprintf_internal(buf, INT_MAX, fmt, args);
}
-int sprintf(char * buf, const char *fmt, ...)
+int sprintf(char *buf, const char *fmt, ...)
{
va_list args;
int i;
va_start(args, fmt);
- i=vsprintf(buf,fmt,args);
+ i = vsprintf(buf, fmt, args);
va_end(args);
return i;
}
void panic(const char *fmt, ...)
{
- va_list args;
+ va_list args;
va_start(args, fmt);
vprintf(fmt, args);
putc('\n');
va_end(args);
-#if defined (CONFIG_PANIC_HANG)
+#if defined(CONFIG_PANIC_HANG)
hang();
#else
- udelay (100000); /* allow messages to go out */
- do_reset (NULL, 0, 0, NULL);
+ udelay(100000); /* allow messages to go out */
+ do_reset(NULL, 0, 0, NULL);
#endif
while (1)
;
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+# The following line expands into whole rule which generates $(LSTSCRIPT),
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
+$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@
# create symbolic links for common files
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+# The following line expands into whole rule which generates $(LSTSCRIPT),
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
+$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@
# create symbolic links for common files
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+# The following line expands into whole rule which generates $(LSTSCRIPT),
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
+$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@
# create symbolic links for common files
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
$(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $@
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+# The following line expands into whole rule which generates $(LSTSCRIPT),
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
+$(nandobj)u-boot.lds: $(LDSCRIPT) $(LSTSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@
#########################################################################
}
. = ALIGN(4);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) $(LDFLAGS) \
$(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+# The following line expands into whole rule which generates $(LSTSCRIPT),
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
+$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@
# create symbolic links for common files
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+# The following line expands into whole rule which generates $(LSTSCRIPT),
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
+$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@
# create symbolic links for common files
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+# The following line expands into whole rule which generates $(LSTSCRIPT),
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
+$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@
# create symbolic links for common files
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/$(CPUDIR)/u-boot-nand_spl.lds
+LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
$(LDFLAGS) $(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $(nandobj)u-boot-spl
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+# The following line expands into whole rule which generates $(LSTSCRIPT),
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
+$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT) $(LSTSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@
# create symbolic links for common files
nandobj := $(OBJTREE)/nand_spl/
LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
+LSTSCRIPT= $(nandobj)/board/$(BOARDDIR)/u-boot.lst
LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE) $(LDFLAGS) \
$(LDFLAGS_FINAL)
AFLAGS += -DCONFIG_SPL_BUILD -DCONFIG_NAND_SPL
-Map $(nandobj)u-boot-spl.map \
-o $@
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
+# The following line expands into whole rule which generates $(LSTSCRIPT),
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(LSTSCRIPT), $(OBJS)))
+$(nandobj)u-boot.lds: $(LDSCRIPT) $(LSTSCRIPT)
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj) -ansi -D__ASSEMBLY__ -P - <$< >$@
#########################################################################
}
. = ALIGN(4);
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
. = ALIGN(4);
.got : { *(.got) }
- __u_boot_cmd_start = .;
- .u_boot_cmd : { *(.u_boot_cmd) }
- __u_boot_cmd_end = .;
+
+ . = ALIGN(4);
+ .u_boot_list : {
+ #include <u-boot.lst>
+ }
. = ALIGN(4);
#include <post.h>
#include <serial.h>
-#if defined(CONFIG_SERIAL_MULTI)
-
/*
* Actually the termination sequence of the coprocessor
* commands is "\r\n" (CR LF), but here we use a side effect of
return 0;
}
-#endif /* CONFIG_SERIAL_MULTI */
u-boot-spl.bin
u-boot-spl.lds
u-boot-spl.map
+u-boot.lst
ifeq ($(SOC),tegra20)
LIBS-y += arch/$(ARCH)/cpu/$(SOC)-common/lib$(SOC)-common.o
+LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o
+LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o
endif
# Add GCC lib
$(LIBS): depend
$(MAKE) -C $(SRCTREE)$(dir $(subst $(SPLTREE),,$@))
-$(obj)u-boot-spl.lds: $(LDSCRIPT) depend
- $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - < $< > $@
+# The following line expands into whole rule which generates u-boot.lst,
+# the file containing u-boots LG-array linker section. This is included into
+# $(LDSCRIPT). The function make_u_boot_list is defined in helper.mk file.
+$(eval $(call make_u_boot_list, $(obj)u-boot.lst, $(LIBS)))
+$(obj)u-boot-spl.lds: $(LDSCRIPT) $(obj)u-boot.lst depend
+ $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -I$(obj). -ansi -D__ASSEMBLY__ -P - < $< > $@
depend: $(obj).depend
.PHONY: depend
/env/fw_printenv
/gdb/gdbcont
/gdb/gdbsend
+/kernel-doc/docproc
# MA 02111-1307 USA
#
-TOOLSUBDIRS =
+TOOLSUBDIRS = kernel-doc
#
# Include this after HOSTOS HOSTARCH check
--- /dev/null
+#!/usr/bin/perl -w
+#
+# Clean a patch file -- or directory of patch files -- of stealth whitespace.
+# WARNING: this can be a highly destructive operation. Use with caution.
+#
+
+use bytes;
+use File::Basename;
+
+# Default options
+$max_width = 79;
+
+# Clean up space-tab sequences, either by removing spaces or
+# replacing them with tabs.
+sub clean_space_tabs($)
+{
+ no bytes; # Tab alignment depends on characters
+
+ my($li) = @_;
+ my($lo) = '';
+ my $pos = 0;
+ my $nsp = 0;
+ my($i, $c);
+
+ for ($i = 0; $i < length($li); $i++) {
+ $c = substr($li, $i, 1);
+ if ($c eq "\t") {
+ my $npos = ($pos+$nsp+8) & ~7;
+ my $ntab = ($npos >> 3) - ($pos >> 3);
+ $lo .= "\t" x $ntab;
+ $pos = $npos;
+ $nsp = 0;
+ } elsif ($c eq "\n" || $c eq "\r") {
+ $lo .= " " x $nsp;
+ $pos += $nsp;
+ $nsp = 0;
+ $lo .= $c;
+ $pos = 0;
+ } elsif ($c eq " ") {
+ $nsp++;
+ } else {
+ $lo .= " " x $nsp;
+ $pos += $nsp;
+ $nsp = 0;
+ $lo .= $c;
+ $pos++;
+ }
+ }
+ $lo .= " " x $nsp;
+ return $lo;
+}
+
+# Compute the visual width of a string
+sub strwidth($) {
+ no bytes; # Tab alignment depends on characters
+
+ my($li) = @_;
+ my($c, $i);
+ my $pos = 0;
+ my $mlen = 0;
+
+ for ($i = 0; $i < length($li); $i++) {
+ $c = substr($li,$i,1);
+ if ($c eq "\t") {
+ $pos = ($pos+8) & ~7;
+ } elsif ($c eq "\n") {
+ $mlen = $pos if ($pos > $mlen);
+ $pos = 0;
+ } else {
+ $pos++;
+ }
+ }
+
+ $mlen = $pos if ($pos > $mlen);
+ return $mlen;
+}
+
+$name = basename($0);
+
+@files = ();
+
+while (defined($a = shift(@ARGV))) {
+ if ($a =~ /^-/) {
+ if ($a eq '-width' || $a eq '-w') {
+ $max_width = shift(@ARGV)+0;
+ } else {
+ print STDERR "Usage: $name [-width #] files...\n";
+ exit 1;
+ }
+ } else {
+ push(@files, $a);
+ }
+}
+
+foreach $f ( @files ) {
+ print STDERR "$name: $f\n";
+
+ if (! -f $f) {
+ print STDERR "$f: not a file\n";
+ next;
+ }
+
+ if (!open(FILE, '+<', $f)) {
+ print STDERR "$name: Cannot open file: $f: $!\n";
+ next;
+ }
+
+ binmode FILE;
+
+ # First, verify that it is not a binary file; consider any file
+ # with a zero byte to be a binary file. Is there any better, or
+ # additional, heuristic that should be applied?
+ $is_binary = 0;
+
+ while (read(FILE, $data, 65536) > 0) {
+ if ($data =~ /\0/) {
+ $is_binary = 1;
+ last;
+ }
+ }
+
+ if ($is_binary) {
+ print STDERR "$name: $f: binary file\n";
+ next;
+ }
+
+ seek(FILE, 0, 0);
+
+ $in_bytes = 0;
+ $out_bytes = 0;
+ $lineno = 0;
+
+ @lines = ();
+
+ $in_hunk = 0;
+ $err = 0;
+
+ while ( defined($line = <FILE>) ) {
+ $lineno++;
+ $in_bytes += length($line);
+
+ if (!$in_hunk) {
+ if ($line =~
+ /^\@\@\s+\-([0-9]+),([0-9]+)\s+\+([0-9]+),([0-9]+)\s\@\@/) {
+ $minus_lines = $2;
+ $plus_lines = $4;
+ if ($minus_lines || $plus_lines) {
+ $in_hunk = 1;
+ @hunk_lines = ($line);
+ }
+ } else {
+ push(@lines, $line);
+ $out_bytes += length($line);
+ }
+ } else {
+ # We're in a hunk
+
+ if ($line =~ /^\+/) {
+ $plus_lines--;
+
+ $text = substr($line, 1);
+ $text =~ s/[ \t\r]*$//; # Remove trailing spaces
+ $text = clean_space_tabs($text);
+
+ $l_width = strwidth($text);
+ if ($max_width && $l_width > $max_width) {
+ print STDERR
+ "$f:$lineno: adds line exceeds $max_width ",
+ "characters ($l_width)\n";
+ }
+
+ push(@hunk_lines, '+'.$text);
+ } elsif ($line =~ /^\-/) {
+ $minus_lines--;
+ push(@hunk_lines, $line);
+ } elsif ($line =~ /^ /) {
+ $plus_lines--;
+ $minus_lines--;
+ push(@hunk_lines, $line);
+ } else {
+ print STDERR "$name: $f: malformed patch\n";
+ $err = 1;
+ last;
+ }
+
+ if ($plus_lines < 0 || $minus_lines < 0) {
+ print STDERR "$name: $f: malformed patch\n";
+ $err = 1;
+ last;
+ } elsif ($plus_lines == 0 && $minus_lines == 0) {
+ # End of a hunk. Process this hunk.
+ my $i;
+ my $l;
+ my @h = ();
+ my $adj = 0;
+ my $done = 0;
+
+ for ($i = scalar(@hunk_lines)-1; $i > 0; $i--) {
+ $l = $hunk_lines[$i];
+ if (!$done && $l eq "+\n") {
+ $adj++; # Skip this line
+ } elsif ($l =~ /^[ +]/) {
+ $done = 1;
+ unshift(@h, $l);
+ } else {
+ unshift(@h, $l);
+ }
+ }
+
+ $l = $hunk_lines[0]; # Hunk header
+ undef @hunk_lines; # Free memory
+
+ if ($adj) {
+ die unless
+ ($l =~ /^\@\@\s+\-([0-9]+),([0-9]+)\s+\+([0-9]+),([0-9]+)\s\@\@(.*)$/);
+ my $mstart = $1;
+ my $mlin = $2;
+ my $pstart = $3;
+ my $plin = $4;
+ my $tail = $5; # doesn't include the final newline
+
+ $l = sprintf("@@ -%d,%d +%d,%d @@%s\n",
+ $mstart, $mlin, $pstart, $plin-$adj,
+ $tail);
+ }
+ unshift(@h, $l);
+
+ # Transfer to the output array
+ foreach $l (@h) {
+ $out_bytes += length($l);
+ push(@lines, $l);
+ }
+
+ $in_hunk = 0;
+ }
+ }
+ }
+
+ if ($in_hunk) {
+ print STDERR "$name: $f: malformed patch\n";
+ $err = 1;
+ }
+
+ if (!$err) {
+ if ($in_bytes != $out_bytes) {
+ # Only write to the file if changed
+ seek(FILE, 0, 0);
+ print FILE @lines;
+
+ if ( !defined($where = tell(FILE)) ||
+ !truncate(FILE, $where) ) {
+ die "$name: Failed to truncate modified file: $f: $!\n";
+ }
+ }
+ }
+
+ close(FILE);
+}
include $(TOPDIR)/config.mk
HOSTSRCS := $(SRCTREE)/lib/crc32.c fw_env.c fw_env_main.c
-HEADERS := fw_env.h
+HEADERS := fw_env.h $(OBJTREE)/include/config.h
# Compile for a hosted environment on the target
HOSTCPPFLAGS = -idirafter $(SRCTREE)/include \
-idirafter $(OBJTREE)/include2 \
-idirafter $(OBJTREE)/include \
- -DUSE_HOSTCC
+ -DUSE_HOSTCC \
+ -DTEXT_BASE=$(TEXT_BASE)
ifeq ($(MTD_VERSION),old)
HOSTCPPFLAGS += -DMTD_OLD
DEVICEx_ENVSECTORS defines the number of sectors that may be used for
this environment instance. On NAND this is used to limit the range
within which bad blocks are skipped, on NOR it is not used.
+
+To prevent losing changes to the environment and to prevent confusing the MTD
+drivers, a lock file at /var/lock/fw_printenv.lock is used to serialize access
+to the environment.
#include <errno.h>
#include <fcntl.h>
+#include <linux/stringify.h>
#include <stdio.h>
#include <stdlib.h>
#include <stddef.h>
#include "fw_env.h"
-#include <config.h>
-
#define WHITESPACE(c) ((c == '\t') || (c == ' '))
#define min(x, y) ({ \
#define ENVSECTORS(i) envdevices[(i)].env_sectors
#define DEVTYPE(i) envdevices[(i)].mtd_type
-#define CONFIG_ENV_SIZE ENVSIZE(dev_current)
+#define CUR_ENVSIZE ENVSIZE(dev_current)
#define ENV_SIZE getenvsize()
/* obsolete_flag must be 0 to efficiently set it on NOR flash without erasing */
static unsigned char obsolete_flag = 0;
-
-#define XMK_STR(x) #x
-#define MK_STR(x) XMK_STR(x)
-
-static char default_environment[] = {
-#if defined(CONFIG_BOOTARGS)
- "bootargs=" CONFIG_BOOTARGS "\0"
-#endif
-#if defined(CONFIG_BOOTCOMMAND)
- "bootcmd=" CONFIG_BOOTCOMMAND "\0"
-#endif
-#if defined(CONFIG_RAMBOOTCOMMAND)
- "ramboot=" CONFIG_RAMBOOTCOMMAND "\0"
-#endif
-#if defined(CONFIG_NFSBOOTCOMMAND)
- "nfsboot=" CONFIG_NFSBOOTCOMMAND "\0"
-#endif
-#if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
- "bootdelay=" MK_STR (CONFIG_BOOTDELAY) "\0"
-#endif
-#if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0)
- "baudrate=" MK_STR (CONFIG_BAUDRATE) "\0"
-#endif
-#ifdef CONFIG_LOADS_ECHO
- "loads_echo=" MK_STR (CONFIG_LOADS_ECHO) "\0"
-#endif
-#ifdef CONFIG_ETHADDR
- "ethaddr=" MK_STR (CONFIG_ETHADDR) "\0"
-#endif
-#ifdef CONFIG_ETH1ADDR
- "eth1addr=" MK_STR (CONFIG_ETH1ADDR) "\0"
-#endif
-#ifdef CONFIG_ETH2ADDR
- "eth2addr=" MK_STR (CONFIG_ETH2ADDR) "\0"
-#endif
-#ifdef CONFIG_ETH3ADDR
- "eth3addr=" MK_STR (CONFIG_ETH3ADDR) "\0"
-#endif
-#ifdef CONFIG_ETH4ADDR
- "eth4addr=" MK_STR (CONFIG_ETH4ADDR) "\0"
-#endif
-#ifdef CONFIG_ETH5ADDR
- "eth5addr=" MK_STR (CONFIG_ETH5ADDR) "\0"
-#endif
-#ifdef CONFIG_ETHPRIME
- "ethprime=" CONFIG_ETHPRIME "\0"
-#endif
-#ifdef CONFIG_IPADDR
- "ipaddr=" MK_STR (CONFIG_IPADDR) "\0"
-#endif
-#ifdef CONFIG_SERVERIP
- "serverip=" MK_STR (CONFIG_SERVERIP) "\0"
-#endif
-#ifdef CONFIG_SYS_AUTOLOAD
- "autoload=" CONFIG_SYS_AUTOLOAD "\0"
-#endif
-#ifdef CONFIG_ROOTPATH
- "rootpath=" CONFIG_ROOTPATH "\0"
-#endif
-#ifdef CONFIG_GATEWAYIP
- "gatewayip=" MK_STR (CONFIG_GATEWAYIP) "\0"
-#endif
-#ifdef CONFIG_NETMASK
- "netmask=" MK_STR (CONFIG_NETMASK) "\0"
-#endif
-#ifdef CONFIG_HOSTNAME
- "hostname=" MK_STR (CONFIG_HOSTNAME) "\0"
-#endif
-#ifdef CONFIG_BOOTFILE
- "bootfile=" CONFIG_BOOTFILE "\0"
-#endif
-#ifdef CONFIG_LOADADDR
- "loadaddr=" MK_STR (CONFIG_LOADADDR) "\0"
-#endif
-#ifdef CONFIG_PREBOOT
- "preboot=" CONFIG_PREBOOT "\0"
-#endif
-#ifdef CONFIG_CLOCKS_IN_MHZ
- "clocks_in_mhz=" "1" "\0"
-#endif
-#if defined(CONFIG_PCI_BOOTDELAY) && (CONFIG_PCI_BOOTDELAY > 0)
- "pcidelay=" MK_STR (CONFIG_PCI_BOOTDELAY) "\0"
-#endif
-#ifdef CONFIG_ENV_VARS_UBOOT_CONFIG
- "arch=" CONFIG_SYS_ARCH "\0"
- "cpu=" CONFIG_SYS_CPU "\0"
- "board=" CONFIG_SYS_BOARD "\0"
-#ifdef CONFIG_SYS_VENDOR
- "vendor=" CONFIG_SYS_VENDOR "\0"
-#endif
-#ifdef CONFIG_SYS_SOC
- "soc=" CONFIG_SYS_SOC "\0"
-#endif
-#endif
-#ifdef CONFIG_EXTRA_ENV_SETTINGS
- CONFIG_EXTRA_ENV_SETTINGS
-#endif
- "\0" /* Termimate struct environment data with 2 NULs */
-};
+#define DEFAULT_ENV_INSTANCE_STATIC
+#include <env_default.h>
static int flash_io (int mode);
static char *envmatch (char * s1, char * s2);
#endif
static inline ulong getenvsize (void)
{
- ulong rc = CONFIG_ENV_SIZE - sizeof (long);
+ ulong rc = CUR_ENVSIZE - sizeof(long);
if (HaveRedundEnv)
rc -= sizeof (char);
{
char *env, *nxt;
- if (fw_env_open())
- return NULL;
-
for (env = environment.data; *env; env = nxt + 1) {
char *val;
(strcmp(name, "serial#") == 0) ||
((strcmp(name, "ethaddr") == 0)
#if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR)
- && (strcmp(oldval, MK_STR(CONFIG_ETHADDR)) != 0)
+ && (strcmp(oldval, __stringify(CONFIG_ETHADDR)) != 0)
#endif /* CONFIG_OVERWRITE_ETHADDR_ONCE && CONFIG_ETHADDR */
) ) {
fprintf (stderr, "Can't overwrite \"%s\"\n", name);
++env;
/*
* Overflow when:
- * "name" + "=" + "val" +"\0\0" > CONFIG_ENV_SIZE - (env-environment)
+ * "name" + "=" + "val" +"\0\0" > CUR_ENVSIZE - (env-environment)
*/
len = strlen (name) + 2;
/* add '=' for first arg, ' ' for all others */
int i, len;
char *name;
char *value = NULL;
- char *tmpval = NULL;
if (argc < 2) {
errno = EINVAL;
name = argv[1];
- len = strlen(name) + 2;
- for (i = 2; i < argc; ++i)
- len += strlen(argv[i]) + 1;
-
- /* Allocate enough place to the data string */
+ len = 0;
for (i = 2; i < argc; ++i) {
char *val = argv[i];
+ size_t val_len = strlen(val);
+
+ if (value)
+ value[len - 1] = ' ';
+ value = realloc(value, len + val_len + 1);
if (!value) {
- value = (char *)malloc(len - strlen(name));
- if (!value) {
- fprintf(stderr,
+ fprintf(stderr,
"Cannot malloc %zu bytes: %s\n",
- len - strlen(name), strerror(errno));
- return -1;
- }
- memset(value, 0, len - strlen(name));
- tmpval = value;
+ len, strerror(errno));
+ return -1;
}
- if (i != 2)
- *tmpval++ = ' ';
- while (*val != '\0')
- *tmpval++ = *val++;
+
+ memcpy(value + len, val, val_len);
+ len += val_len;
+ value[len++] = '\0';
}
fw_env_write(name, value);
- if (value)
- free(value);
+ free(value);
return fw_env_close();
}
return -1;
}
#ifdef DEBUG
- fprintf (stderr, "Read 0x%x bytes at 0x%llx\n",
- rc, blockstart + block_seek);
+ fprintf(stderr, "Read 0x%x bytes at 0x%llx on %s\n",
+ rc, blockstart + block_seek, DEVNAME(dev));
#endif
processed += readlen;
readlen = min (blocklen, count - processed);
if (write_total != rc)
return -1;
+#ifdef DEBUG
+ fprintf(stderr, "Preserving data ");
+ if (block_seek != 0)
+ fprintf(stderr, "0x%x - 0x%lx", 0, block_seek - 1);
+ if (block_seek + count != write_total) {
+ if (block_seek != 0)
+ fprintf(stderr, " and ");
+ fprintf(stderr, "0x%lx - 0x%x",
+ block_seek + count, write_total - 1);
+ }
+ fprintf(stderr, "\n");
+#endif
/* Overwrite the old environment */
memcpy (data + block_seek, buf, count);
} else {
}
#ifdef DEBUG
- printf ("Write 0x%x bytes at 0x%llx\n", erasesize, blockstart);
+ fprintf(stderr, "Write 0x%x bytes at 0x%llx\n", erasesize,
+ blockstart);
#endif
if (write (fd, data + processed, erasesize) != erasesize) {
fprintf (stderr, "Write error on %s: %s\n",
}
#ifdef DEBUG
- printf ("Writing new environment at 0x%lx on %s\n",
+ fprintf(stderr, "Writing new environment at 0x%lx on %s\n",
DEVOFFSET (dev_target), DEVNAME (dev_target));
#endif
- rc = flash_write_buf (dev_target, fd_target, environment.image,
- CONFIG_ENV_SIZE, DEVOFFSET (dev_target),
+ rc = flash_write_buf(dev_target, fd_target, environment.image,
+ CUR_ENVSIZE, DEVOFFSET(dev_target),
DEVTYPE(dev_target));
if (rc < 0)
return rc;
off_t offset = DEVOFFSET (dev_current) +
offsetof (struct env_image_redundant, flags);
#ifdef DEBUG
- printf ("Setting obsolete flag in environment at 0x%lx on %s\n",
+ fprintf(stderr,
+ "Setting obsolete flag in environment at 0x%lx on %s\n",
DEVOFFSET (dev_current), DEVNAME (dev_current));
#endif
flash_flag_obsolete (dev_current, fd_current, offset);
DEVTYPE(dev_current) = mtdinfo.type;
- rc = flash_read_buf (dev_current, fd, environment.image, CONFIG_ENV_SIZE,
+ rc = flash_read_buf(dev_current, fd, environment.image, CUR_ENVSIZE,
DEVOFFSET (dev_current), mtdinfo.type);
- return (rc != CONFIG_ENV_SIZE) ? -1 : 0;
+ return (rc != CUR_ENVSIZE) ? -1 : 0;
}
static int flash_io (int mode)
static char *envmatch (char * s1, char * s2)
{
+ if (s1 == NULL || s2 == NULL)
+ return NULL;
while (*s1 == *s2++)
if (*s1++ == '=')
if (parse_config ()) /* should fill envdevices */
return -1;
- addr0 = calloc (1, CONFIG_ENV_SIZE);
+ addr0 = calloc(1, CUR_ENVSIZE);
if (addr0 == NULL) {
- fprintf (stderr,
+ fprintf(stderr,
"Not enough memory for environment (%ld bytes)\n",
- CONFIG_ENV_SIZE);
+ CUR_ENVSIZE);
return -1;
}
flag0 = *environment.flags;
dev_current = 1;
- addr1 = calloc (1, CONFIG_ENV_SIZE);
+ addr1 = calloc(1, CUR_ENVSIZE);
if (addr1 == NULL) {
- fprintf (stderr,
+ fprintf(stderr,
"Not enough memory for environment (%ld bytes)\n",
- CONFIG_ENV_SIZE);
+ CUR_ENVSIZE);
return -1;
}
redundant = addr1;
/* Other pointers are already set */
free (addr1);
}
+#ifdef DEBUG
+ fprintf(stderr, "Selected env in %s\n", DEVNAME(dev_current));
+#endif
}
return 0;
}
* MA 02111-1307 USA
*/
+/* Pull in the current config to define the default environment */
+#ifndef __ASSEMBLY__
+#define __ASSEMBLY__ /* get only #defines from config.h */
+#include <config.h>
+#undef __ASSEMBLY__
+#else
+#include <config.h>
+#endif
+
/*
* To build the utility with the static configuration
* comment out the next line.
*/
#define CONFIG_FILE "/etc/fw_env.config"
+#ifndef CONFIG_FILE
#define HAVE_REDUND /* For systems with 2 env sectors */
#define DEVICE1_NAME "/dev/mtd1"
#define DEVICE2_NAME "/dev/mtd2"
#define ENV2_SIZE 0x4000
#define DEVICE2_ESIZE 0x4000
#define DEVICE2_ENVSECTORS 2
+#endif
+#ifndef CONFIG_BAUDRATE
#define CONFIG_BAUDRATE 115200
+#endif
+
+#ifndef CONFIG_BOOTDELAY
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
+#endif
+
+#ifndef CONFIG_BOOTCOMMAND
#define CONFIG_BOOTCOMMAND \
"bootp; " \
"setenv bootargs root=/dev/nfs nfsroot=${serverip}:${rootpath} " \
"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
"bootm"
+#endif
extern int fw_printenv(int argc, char *argv[]);
extern char *fw_getenv (char *name);
* variable "name"
*/
+#include <fcntl.h>
+#include <getopt.h>
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
-#include <getopt.h>
+#include <sys/file.h>
+#include <unistd.h>
#include "fw_env.h"
#define CMD_PRINTENV "fw_printenv"
);
}
-int
-main(int argc, char *argv[])
+int main(int argc, char *argv[])
{
char *p;
char *cmdname = *argv;
char *script_file = NULL;
int c;
+ const char *lockname = "/var/lock/" CMD_PRINTENV ".lock";
+ int lockfd = -1;
+ int retval = EXIT_SUCCESS;
+
+ lockfd = open(lockname, O_WRONLY | O_CREAT | O_TRUNC);
+ if (-1 == lockfd) {
+ fprintf(stderr, "Error opening lock file %s\n", lockname);
+ return EXIT_FAILURE;
+ }
+
+ if (-1 == flock(lockfd, LOCK_EX)) {
+ fprintf(stderr, "Error locking file %s\n", lockname);
+ close(lockfd);
+ return EXIT_FAILURE;
+ }
if ((p = strrchr (cmdname, '/')) != NULL) {
cmdname = p + 1;
break;
case 'h':
usage();
- return EXIT_SUCCESS;
+ goto exit;
default: /* '?' */
fprintf(stderr, "Try `%s --help' for more information."
"\n", cmdname);
- return EXIT_FAILURE;
+ retval = EXIT_FAILURE;
+ goto exit;
}
}
-
if (strcmp(cmdname, CMD_PRINTENV) == 0) {
-
- if (fw_printenv (argc, argv) != 0)
- return EXIT_FAILURE;
-
- return EXIT_SUCCESS;
-
+ if (fw_printenv(argc, argv) != 0)
+ retval = EXIT_FAILURE;
} else if (strcmp(cmdname, CMD_SETENV) == 0) {
if (!script_file) {
if (fw_setenv(argc, argv) != 0)
- return EXIT_FAILURE;
+ retval = EXIT_FAILURE;
} else {
if (fw_parse_script(script_file) != 0)
- return EXIT_FAILURE;
+ retval = EXIT_FAILURE;
}
-
- return EXIT_SUCCESS;
-
+ } else {
+ fprintf(stderr,
+ "Identity crisis - may be called as `" CMD_PRINTENV
+ "' or as `" CMD_SETENV "' but not as `%s'\n",
+ cmdname);
+ retval = EXIT_FAILURE;
}
- fprintf (stderr,
- "Identity crisis - may be called as `" CMD_PRINTENV
- "' or as `" CMD_SETENV "' but not as `%s'\n",
- cmdname);
- return EXIT_FAILURE;
+exit:
+ flock(lockfd, LOCK_UN);
+ close(lockfd);
+ return retval;
}
--- /dev/null
+#
+# Copyright (C) 2012 Marek Vasut <marex@denx.de>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+all: $(obj)docproc
+
+$(obj)docproc: docproc.c
+ $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
+ $(HOSTSTRIP) $@
+
+clean:
+ rm -rf docproc
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * docproc is a simple preprocessor for the template files
+ * used as placeholders for the kernel internal documentation.
+ * docproc is used for documentation-frontend and
+ * dependency-generator.
+ * The two usages have in common that they require
+ * some knowledge of the .tmpl syntax, therefore they
+ * are kept together.
+ *
+ * documentation-frontend
+ * Scans the template file and call kernel-doc for
+ * all occurrences of ![EIF]file
+ * Beforehand each referenced file is scanned for
+ * any symbols that are exported via these macros:
+ * EXPORT_SYMBOL(), EXPORT_SYMBOL_GPL(), &
+ * EXPORT_SYMBOL_GPL_FUTURE()
+ * This is used to create proper -function and
+ * -nofunction arguments in calls to kernel-doc.
+ * Usage: docproc doc file.tmpl
+ *
+ * dependency-generator:
+ * Scans the template file and list all files
+ * referenced in a format recognized by make.
+ * Usage: docproc depend file.tmpl
+ * Writes dependency information to stdout
+ * in the following format:
+ * file.tmpl src.c src2.c
+ * The filenames are obtained from the following constructs:
+ * !Efilename
+ * !Ifilename
+ * !Dfilename
+ * !Ffilename
+ * !Pfilename
+ *
+ */
+
+#define _GNU_SOURCE
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <ctype.h>
+#include <unistd.h>
+#include <limits.h>
+#include <errno.h>
+#include <sys/types.h>
+#include <sys/wait.h>
+
+/* exitstatus is used to keep track of any failing calls to kernel-doc,
+ * but execution continues. */
+int exitstatus = 0;
+
+typedef void DFL(char *);
+DFL *defaultline;
+
+typedef void FILEONLY(char * file);
+FILEONLY *internalfunctions;
+FILEONLY *externalfunctions;
+FILEONLY *symbolsonly;
+FILEONLY *findall;
+
+typedef void FILELINE(char * file, char * line);
+FILELINE * singlefunctions;
+FILELINE * entity_system;
+FILELINE * docsection;
+
+#define MAXLINESZ 2048
+#define MAXFILES 250
+#define KERNELDOCPATH "tools/kernel-doc/"
+#define KERNELDOC "kernel-doc"
+#define DOCBOOK "-docbook"
+#define LIST "-list"
+#define FUNCTION "-function"
+#define NOFUNCTION "-nofunction"
+#define NODOCSECTIONS "-no-doc-sections"
+
+static char *srctree, *kernsrctree;
+
+static char **all_list = NULL;
+static int all_list_len = 0;
+
+static void consume_symbol(const char *sym)
+{
+ int i;
+
+ for (i = 0; i < all_list_len; i++) {
+ if (!all_list[i])
+ continue;
+ if (strcmp(sym, all_list[i]))
+ continue;
+ all_list[i] = NULL;
+ break;
+ }
+}
+
+static void usage (void)
+{
+ fprintf(stderr, "Usage: docproc {doc|depend} file\n");
+ fprintf(stderr, "Input is read from file.tmpl. Output is sent to stdout\n");
+ fprintf(stderr, "doc: frontend when generating kernel documentation\n");
+ fprintf(stderr, "depend: generate list of files referenced within file\n");
+ fprintf(stderr, "Environment variable SRCTREE: absolute path to sources.\n");
+ fprintf(stderr, " KBUILD_SRC: absolute path to kernel source tree.\n");
+}
+
+/*
+ * Execute kernel-doc with parameters given in svec
+ */
+static void exec_kernel_doc(char **svec)
+{
+ pid_t pid;
+ int ret;
+ char real_filename[PATH_MAX + 1];
+ /* Make sure output generated so far are flushed */
+ fflush(stdout);
+ switch (pid=fork()) {
+ case -1:
+ perror("fork");
+ exit(1);
+ case 0:
+ memset(real_filename, 0, sizeof(real_filename));
+ strncat(real_filename, kernsrctree, PATH_MAX);
+ strncat(real_filename, "/" KERNELDOCPATH KERNELDOC,
+ PATH_MAX - strlen(real_filename));
+ execvp(real_filename, svec);
+ fprintf(stderr, "exec ");
+ perror(real_filename);
+ exit(1);
+ default:
+ waitpid(pid, &ret ,0);
+ }
+ if (WIFEXITED(ret))
+ exitstatus |= WEXITSTATUS(ret);
+ else
+ exitstatus = 0xff;
+}
+
+/* Types used to create list of all exported symbols in a number of files */
+struct symbols
+{
+ char *name;
+};
+
+struct symfile
+{
+ char *filename;
+ struct symbols *symbollist;
+ int symbolcnt;
+};
+
+struct symfile symfilelist[MAXFILES];
+int symfilecnt = 0;
+
+static void add_new_symbol(struct symfile *sym, char * symname)
+{
+ sym->symbollist =
+ realloc(sym->symbollist, (sym->symbolcnt + 1) * sizeof(char *));
+ sym->symbollist[sym->symbolcnt++].name = strdup(symname);
+}
+
+/* Add a filename to the list */
+static struct symfile * add_new_file(char * filename)
+{
+ symfilelist[symfilecnt++].filename = strdup(filename);
+ return &symfilelist[symfilecnt - 1];
+}
+
+/* Check if file already are present in the list */
+static struct symfile * filename_exist(char * filename)
+{
+ int i;
+ for (i=0; i < symfilecnt; i++)
+ if (strcmp(symfilelist[i].filename, filename) == 0)
+ return &symfilelist[i];
+ return NULL;
+}
+
+/*
+ * List all files referenced within the template file.
+ * Files are separated by tabs.
+ */
+static void adddep(char * file) { printf("\t%s", file); }
+static void adddep2(char * file, char * line) { line = line; adddep(file); }
+static void noaction(char * line) { line = line; }
+static void noaction2(char * file, char * line) { file = file; line = line; }
+
+/* Echo the line without further action */
+static void printline(char * line) { printf("%s", line); }
+
+/*
+ * Find all symbols in filename that are exported with EXPORT_SYMBOL &
+ * EXPORT_SYMBOL_GPL (& EXPORT_SYMBOL_GPL_FUTURE implicitly).
+ * All symbols located are stored in symfilelist.
+ */
+static void find_export_symbols(char * filename)
+{
+ FILE * fp;
+ struct symfile *sym;
+ char line[MAXLINESZ];
+ if (filename_exist(filename) == NULL) {
+ char real_filename[PATH_MAX + 1];
+ memset(real_filename, 0, sizeof(real_filename));
+ strncat(real_filename, srctree, PATH_MAX);
+ strncat(real_filename, "/", PATH_MAX - strlen(real_filename));
+ strncat(real_filename, filename,
+ PATH_MAX - strlen(real_filename));
+ sym = add_new_file(filename);
+ fp = fopen(real_filename, "r");
+ if (fp == NULL) {
+ fprintf(stderr, "docproc: ");
+ perror(real_filename);
+ exit(1);
+ }
+ while (fgets(line, MAXLINESZ, fp)) {
+ char *p;
+ char *e;
+ if (((p = strstr(line, "EXPORT_SYMBOL_GPL")) != NULL) ||
+ ((p = strstr(line, "EXPORT_SYMBOL")) != NULL)) {
+ /* Skip EXPORT_SYMBOL{_GPL} */
+ while (isalnum(*p) || *p == '_')
+ p++;
+ /* Remove parentheses & additional whitespace */
+ while (isspace(*p))
+ p++;
+ if (*p != '(')
+ continue; /* Syntax error? */
+ else
+ p++;
+ while (isspace(*p))
+ p++;
+ e = p;
+ while (isalnum(*e) || *e == '_')
+ e++;
+ *e = '\0';
+ add_new_symbol(sym, p);
+ }
+ }
+ fclose(fp);
+ }
+}
+
+/*
+ * Document all external or internal functions in a file.
+ * Call kernel-doc with following parameters:
+ * kernel-doc -docbook -nofunction function_name1 filename
+ * Function names are obtained from all the src files
+ * by find_export_symbols.
+ * intfunc uses -nofunction
+ * extfunc uses -function
+ */
+static void docfunctions(char * filename, char * type)
+{
+ int i,j;
+ int symcnt = 0;
+ int idx = 0;
+ char **vec;
+
+ for (i=0; i <= symfilecnt; i++)
+ symcnt += symfilelist[i].symbolcnt;
+ vec = malloc((2 + 2 * symcnt + 3) * sizeof(char *));
+ if (vec == NULL) {
+ perror("docproc: ");
+ exit(1);
+ }
+ vec[idx++] = KERNELDOC;
+ vec[idx++] = DOCBOOK;
+ vec[idx++] = NODOCSECTIONS;
+ for (i=0; i < symfilecnt; i++) {
+ struct symfile * sym = &symfilelist[i];
+ for (j=0; j < sym->symbolcnt; j++) {
+ vec[idx++] = type;
+ consume_symbol(sym->symbollist[j].name);
+ vec[idx++] = sym->symbollist[j].name;
+ }
+ }
+ vec[idx++] = filename;
+ vec[idx] = NULL;
+ printf("<!-- %s -->\n", filename);
+ exec_kernel_doc(vec);
+ fflush(stdout);
+ free(vec);
+}
+static void intfunc(char * filename) { docfunctions(filename, NOFUNCTION); }
+static void extfunc(char * filename) { docfunctions(filename, FUNCTION); }
+
+/*
+ * Document specific function(s) in a file.
+ * Call kernel-doc with the following parameters:
+ * kernel-doc -docbook -function function1 [-function function2]
+ */
+static void singfunc(char * filename, char * line)
+{
+ char *vec[200]; /* Enough for specific functions */
+ int i, idx = 0;
+ int startofsym = 1;
+ vec[idx++] = KERNELDOC;
+ vec[idx++] = DOCBOOK;
+
+ /* Split line up in individual parameters preceded by FUNCTION */
+ for (i=0; line[i]; i++) {
+ if (isspace(line[i])) {
+ line[i] = '\0';
+ startofsym = 1;
+ continue;
+ }
+ if (startofsym) {
+ startofsym = 0;
+ vec[idx++] = FUNCTION;
+ vec[idx++] = &line[i];
+ }
+ }
+ for (i = 0; i < idx; i++) {
+ if (strcmp(vec[i], FUNCTION))
+ continue;
+ consume_symbol(vec[i + 1]);
+ }
+ vec[idx++] = filename;
+ vec[idx] = NULL;
+ exec_kernel_doc(vec);
+}
+
+/*
+ * Insert specific documentation section from a file.
+ * Call kernel-doc with the following parameters:
+ * kernel-doc -docbook -function "doc section" filename
+ */
+static void docsect(char *filename, char *line)
+{
+ char *vec[6]; /* kerneldoc -docbook -function "section" file NULL */
+ char *s;
+
+ for (s = line; *s; s++)
+ if (*s == '\n')
+ *s = '\0';
+
+ if (asprintf(&s, "DOC: %s", line) < 0) {
+ perror("asprintf");
+ exit(1);
+ }
+ consume_symbol(s);
+ free(s);
+
+ vec[0] = KERNELDOC;
+ vec[1] = DOCBOOK;
+ vec[2] = FUNCTION;
+ vec[3] = line;
+ vec[4] = filename;
+ vec[5] = NULL;
+ exec_kernel_doc(vec);
+}
+
+static void find_all_symbols(char *filename)
+{
+ char *vec[4]; /* kerneldoc -list file NULL */
+ pid_t pid;
+ int ret, i, count, start;
+ char real_filename[PATH_MAX + 1];
+ int pipefd[2];
+ char *data, *str;
+ size_t data_len = 0;
+
+ vec[0] = KERNELDOC;
+ vec[1] = LIST;
+ vec[2] = filename;
+ vec[3] = NULL;
+
+ if (pipe(pipefd)) {
+ perror("pipe");
+ exit(1);
+ }
+
+ switch (pid=fork()) {
+ case -1:
+ perror("fork");
+ exit(1);
+ case 0:
+ close(pipefd[0]);
+ dup2(pipefd[1], 1);
+ memset(real_filename, 0, sizeof(real_filename));
+ strncat(real_filename, kernsrctree, PATH_MAX);
+ strncat(real_filename, "/" KERNELDOCPATH KERNELDOC,
+ PATH_MAX - strlen(real_filename));
+ execvp(real_filename, vec);
+ fprintf(stderr, "exec ");
+ perror(real_filename);
+ exit(1);
+ default:
+ close(pipefd[1]);
+ data = malloc(4096);
+ do {
+ while ((ret = read(pipefd[0],
+ data + data_len,
+ 4096)) > 0) {
+ data_len += ret;
+ data = realloc(data, data_len + 4096);
+ }
+ } while (ret == -EAGAIN);
+ if (ret != 0) {
+ perror("read");
+ exit(1);
+ }
+ waitpid(pid, &ret ,0);
+ }
+ if (WIFEXITED(ret))
+ exitstatus |= WEXITSTATUS(ret);
+ else
+ exitstatus = 0xff;
+
+ count = 0;
+ /* poor man's strtok, but with counting */
+ for (i = 0; i < data_len; i++) {
+ if (data[i] == '\n') {
+ count++;
+ data[i] = '\0';
+ }
+ }
+ start = all_list_len;
+ all_list_len += count;
+ all_list = realloc(all_list, sizeof(char *) * all_list_len);
+ str = data;
+ for (i = 0; i < data_len && start != all_list_len; i++) {
+ if (data[i] == '\0') {
+ all_list[start] = str;
+ str = data + i + 1;
+ start++;
+ }
+ }
+}
+
+/*
+ * Parse file, calling action specific functions for:
+ * 1) Lines containing !E
+ * 2) Lines containing !I
+ * 3) Lines containing !D
+ * 4) Lines containing !F
+ * 5) Lines containing !P
+ * 6) Lines containing !C
+ * 7) Default lines - lines not matching the above
+ */
+static void parse_file(FILE *infile)
+{
+ char line[MAXLINESZ];
+ char * s;
+ while (fgets(line, MAXLINESZ, infile)) {
+ if (line[0] == '!') {
+ s = line + 2;
+ switch (line[1]) {
+ case 'E':
+ while (*s && !isspace(*s)) s++;
+ *s = '\0';
+ externalfunctions(line+2);
+ break;
+ case 'I':
+ while (*s && !isspace(*s)) s++;
+ *s = '\0';
+ internalfunctions(line+2);
+ break;
+ case 'D':
+ while (*s && !isspace(*s)) s++;
+ *s = '\0';
+ symbolsonly(line+2);
+ break;
+ case 'F':
+ /* filename */
+ while (*s && !isspace(*s)) s++;
+ *s++ = '\0';
+ /* function names */
+ while (isspace(*s))
+ s++;
+ singlefunctions(line +2, s);
+ break;
+ case 'P':
+ /* filename */
+ while (*s && !isspace(*s)) s++;
+ *s++ = '\0';
+ /* DOC: section name */
+ while (isspace(*s))
+ s++;
+ docsection(line + 2, s);
+ break;
+ case 'C':
+ while (*s && !isspace(*s)) s++;
+ *s = '\0';
+ if (findall)
+ findall(line+2);
+ break;
+ default:
+ defaultline(line);
+ }
+ } else {
+ defaultline(line);
+ }
+ }
+ fflush(stdout);
+}
+
+
+int main(int argc, char *argv[])
+{
+ FILE * infile;
+ int i;
+
+ srctree = getenv("SRCTREE");
+ if (!srctree)
+ srctree = getcwd(NULL, 0);
+ kernsrctree = getenv("KBUILD_SRC");
+ if (!kernsrctree || !*kernsrctree)
+ kernsrctree = srctree;
+ if (argc != 3) {
+ usage();
+ exit(1);
+ }
+ /* Open file, exit on error */
+ infile = fopen(argv[2], "r");
+ if (infile == NULL) {
+ fprintf(stderr, "docproc: ");
+ perror(argv[2]);
+ exit(2);
+ }
+
+ if (strcmp("doc", argv[1]) == 0) {
+ /* Need to do this in two passes.
+ * First pass is used to collect all symbols exported
+ * in the various files;
+ * Second pass generate the documentation.
+ * This is required because some functions are declared
+ * and exported in different files :-((
+ */
+ /* Collect symbols */
+ defaultline = noaction;
+ internalfunctions = find_export_symbols;
+ externalfunctions = find_export_symbols;
+ symbolsonly = find_export_symbols;
+ singlefunctions = noaction2;
+ docsection = noaction2;
+ findall = find_all_symbols;
+ parse_file(infile);
+
+ /* Rewind to start from beginning of file again */
+ fseek(infile, 0, SEEK_SET);
+ defaultline = printline;
+ internalfunctions = intfunc;
+ externalfunctions = extfunc;
+ symbolsonly = printline;
+ singlefunctions = singfunc;
+ docsection = docsect;
+ findall = NULL;
+
+ parse_file(infile);
+
+ for (i = 0; i < all_list_len; i++) {
+ if (!all_list[i])
+ continue;
+ fprintf(stderr, "Warning: didn't use docs for %s\n",
+ all_list[i]);
+ }
+ } else if (strcmp("depend", argv[1]) == 0) {
+ /* Create first part of dependency chain
+ * file.tmpl */
+ printf("%s\t", argv[2]);
+ defaultline = noaction;
+ internalfunctions = adddep;
+ externalfunctions = adddep;
+ symbolsonly = adddep;
+ singlefunctions = adddep2;
+ docsection = adddep2;
+ findall = adddep;
+ parse_file(infile);
+ printf("\n");
+ } else {
+ fprintf(stderr, "Unknown option: %s\n", argv[1]);
+ exit(1);
+ }
+ fclose(infile);
+ fflush(stdout);
+ return exitstatus;
+}
--- /dev/null
+#!/usr/bin/perl -w
+
+use strict;
+
+## Copyright (c) 1998 Michael Zucchi, All Rights Reserved ##
+## Copyright (C) 2000, 1 Tim Waugh <twaugh@redhat.com> ##
+## Copyright (C) 2001 Simon Huggins ##
+## Copyright (C) 2005-2012 Randy Dunlap ##
+## Copyright (C) 2012 Dan Luedtke ##
+## ##
+## #define enhancements by Armin Kuster <akuster@mvista.com> ##
+## Copyright (c) 2000 MontaVista Software, Inc. ##
+## ##
+## This software falls under the GNU General Public License. ##
+## Please read the COPYING file for more information ##
+
+# 18/01/2001 - Cleanups
+# Functions prototyped as foo(void) same as foo()
+# Stop eval'ing where we don't need to.
+# -- huggie@earth.li
+
+# 27/06/2001 - Allowed whitespace after initial "/**" and
+# allowed comments before function declarations.
+# -- Christian Kreibich <ck@whoop.org>
+
+# Still to do:
+# - add perldoc documentation
+# - Look more closely at some of the scarier bits :)
+
+# 26/05/2001 - Support for separate source and object trees.
+# Return error code.
+# Keith Owens <kaos@ocs.com.au>
+
+# 23/09/2001 - Added support for typedefs, structs, enums and unions
+# Support for Context section; can be terminated using empty line
+# Small fixes (like spaces vs. \s in regex)
+# -- Tim Jansen <tim@tjansen.de>
+
+# 25/07/2012 - Added support for HTML5
+# -- Dan Luedtke <mail@danrl.de>
+
+#
+# This will read a 'c' file and scan for embedded comments in the
+# style of gnome comments (+minor extensions - see below).
+#
+
+# Note: This only supports 'c'.
+
+# usage:
+# kernel-doc [ -docbook | -html | -html5 | -text | -man | -list ]
+# [ -no-doc-sections ]
+# [ -function funcname [ -function funcname ...] ]
+# c file(s)s > outputfile
+# or
+# [ -nofunction funcname [ -function funcname ...] ]
+# c file(s)s > outputfile
+#
+# Set output format using one of -docbook -html -html5 -text or -man.
+# Default is man.
+# The -list format is for internal use by docproc.
+#
+# -no-doc-sections
+# Do not output DOC: sections
+#
+# -function funcname
+# If set, then only generate documentation for the given function(s) or
+# DOC: section titles. All other functions and DOC: sections are ignored.
+#
+# -nofunction funcname
+# If set, then only generate documentation for the other function(s)/DOC:
+# sections. Cannot be used together with -function (yes, that's a bug --
+# perl hackers can fix it 8))
+#
+# c files - list of 'c' files to process
+#
+# All output goes to stdout, with errors to stderr.
+
+#
+# format of comments.
+# In the following table, (...)? signifies optional structure.
+# (...)* signifies 0 or more structure elements
+# /**
+# * function_name(:)? (- short description)?
+# (* @parameterx: (description of parameter x)?)*
+# (* a blank line)?
+# * (Description:)? (Description of function)?
+# * (section header: (section description)? )*
+# (*)?*/
+#
+# So .. the trivial example would be:
+#
+# /**
+# * my_function
+# */
+#
+# If the Description: header tag is omitted, then there must be a blank line
+# after the last parameter specification.
+# e.g.
+# /**
+# * my_function - does my stuff
+# * @my_arg: its mine damnit
+# *
+# * Does my stuff explained.
+# */
+#
+# or, could also use:
+# /**
+# * my_function - does my stuff
+# * @my_arg: its mine damnit
+# * Description: Does my stuff explained.
+# */
+# etc.
+#
+# Besides functions you can also write documentation for structs, unions,
+# enums and typedefs. Instead of the function name you must write the name
+# of the declaration; the struct/union/enum/typedef must always precede
+# the name. Nesting of declarations is not supported.
+# Use the argument mechanism to document members or constants.
+# e.g.
+# /**
+# * struct my_struct - short description
+# * @a: first member
+# * @b: second member
+# *
+# * Longer description
+# */
+# struct my_struct {
+# int a;
+# int b;
+# /* private: */
+# int c;
+# };
+#
+# All descriptions can be multiline, except the short function description.
+#
+# You can also add additional sections. When documenting kernel functions you
+# should document the "Context:" of the function, e.g. whether the functions
+# can be called form interrupts. Unlike other sections you can end it with an
+# empty line.
+# Example-sections should contain the string EXAMPLE so that they are marked
+# appropriately in DocBook.
+#
+# Example:
+# /**
+# * user_function - function that can only be called in user context
+# * @a: some argument
+# * Context: !in_interrupt()
+# *
+# * Some description
+# * Example:
+# * user_function(22);
+# */
+# ...
+#
+#
+# All descriptive text is further processed, scanning for the following special
+# patterns, which are highlighted appropriately.
+#
+# 'funcname()' - function
+# '$ENVVAR' - environmental variable
+# '&struct_name' - name of a structure (up to two words including 'struct')
+# '@parameter' - name of a parameter
+# '%CONST' - name of a constant.
+
+## init lots of data
+
+my $errors = 0;
+my $warnings = 0;
+my $anon_struct_union = 0;
+
+# match expressions used to find embedded type information
+my $type_constant = '\%([-_\w]+)';
+my $type_func = '(\w+)\(\)';
+my $type_param = '\@(\w+)';
+my $type_struct = '\&((struct\s*)*[_\w]+)';
+my $type_struct_xml = '\\&((struct\s*)*[_\w]+)';
+my $type_env = '(\$\w+)';
+
+# Output conversion substitutions.
+# One for each output format
+
+# these work fairly well
+my %highlights_html = ( $type_constant, "<i>\$1</i>",
+ $type_func, "<b>\$1</b>",
+ $type_struct_xml, "<i>\$1</i>",
+ $type_env, "<b><i>\$1</i></b>",
+ $type_param, "<tt><b>\$1</b></tt>" );
+my $local_lt = "\\\\\\\\lt:";
+my $local_gt = "\\\\\\\\gt:";
+my $blankline_html = $local_lt . "p" . $local_gt; # was "<p>"
+
+# html version 5
+my %highlights_html5 = ( $type_constant, "<span class=\"const\">\$1</span>",
+ $type_func, "<span class=\"func\">\$1</span>",
+ $type_struct_xml, "<span class=\"struct\">\$1</span>",
+ $type_env, "<span class=\"env\">\$1</span>",
+ $type_param, "<span class=\"param\">\$1</span>" );
+my $blankline_html5 = $local_lt . "br /" . $local_gt;
+
+# XML, docbook format
+my %highlights_xml = ( "([^=])\\\"([^\\\"<]+)\\\"", "\$1<quote>\$2</quote>",
+ $type_constant, "<constant>\$1</constant>",
+ $type_func, "<function>\$1</function>",
+ $type_struct_xml, "<structname>\$1</structname>",
+ $type_env, "<envar>\$1</envar>",
+ $type_param, "<parameter>\$1</parameter>" );
+my $blankline_xml = $local_lt . "/para" . $local_gt . $local_lt . "para" . $local_gt . "\n";
+
+# gnome, docbook format
+my %highlights_gnome = ( $type_constant, "<replaceable class=\"option\">\$1</replaceable>",
+ $type_func, "<function>\$1</function>",
+ $type_struct, "<structname>\$1</structname>",
+ $type_env, "<envar>\$1</envar>",
+ $type_param, "<parameter>\$1</parameter>" );
+my $blankline_gnome = "</para><para>\n";
+
+# these are pretty rough
+my %highlights_man = ( $type_constant, "\$1",
+ $type_func, "\\\\fB\$1\\\\fP",
+ $type_struct, "\\\\fI\$1\\\\fP",
+ $type_param, "\\\\fI\$1\\\\fP" );
+my $blankline_man = "";
+
+# text-mode
+my %highlights_text = ( $type_constant, "\$1",
+ $type_func, "\$1",
+ $type_struct, "\$1",
+ $type_param, "\$1" );
+my $blankline_text = "";
+
+# list mode
+my %highlights_list = ( $type_constant, "\$1",
+ $type_func, "\$1",
+ $type_struct, "\$1",
+ $type_param, "\$1" );
+my $blankline_list = "";
+
+# read arguments
+if ($#ARGV == -1) {
+ usage();
+}
+
+my $kernelversion;
+my $dohighlight = "";
+
+my $verbose = 0;
+my $output_mode = "man";
+my $no_doc_sections = 0;
+my %highlights = %highlights_man;
+my $blankline = $blankline_man;
+my $modulename = "Bootloader API";
+my $function_only = 0;
+my $man_date = ('January', 'February', 'March', 'April', 'May', 'June',
+ 'July', 'August', 'September', 'October',
+ 'November', 'December')[(localtime)[4]] .
+ " " . ((localtime)[5]+1900);
+
+# Essentially these are globals.
+# They probably want to be tidied up, made more localised or something.
+# CAVEAT EMPTOR! Some of the others I localised may not want to be, which
+# could cause "use of undefined value" or other bugs.
+my ($function, %function_table, %parametertypes, $declaration_purpose);
+my ($type, $declaration_name, $return_type);
+my ($newsection, $newcontents, $prototype, $brcount, %source_map);
+
+if (defined($ENV{'KBUILD_VERBOSE'})) {
+ $verbose = "$ENV{'KBUILD_VERBOSE'}";
+}
+
+# Generated docbook code is inserted in a template at a point where
+# docbook v3.1 requires a non-zero sequence of RefEntry's; see:
+# http://www.oasis-open.org/docbook/documentation/reference/html/refentry.html
+# We keep track of number of generated entries and generate a dummy
+# if needs be to ensure the expanded template can be postprocessed
+# into html.
+my $section_counter = 0;
+
+my $lineprefix="";
+
+# states
+# 0 - normal code
+# 1 - looking for function name
+# 2 - scanning field start.
+# 3 - scanning prototype.
+# 4 - documentation block
+my $state;
+my $in_doc_sect;
+
+#declaration types: can be
+# 'function', 'struct', 'union', 'enum', 'typedef'
+my $decl_type;
+
+my $doc_special = "\@\%\$\&";
+
+my $doc_start = '^/\*\*\s*$'; # Allow whitespace at end of comment start.
+my $doc_end = '\*/';
+my $doc_com = '\s*\*\s*';
+my $doc_decl = $doc_com . '(\w+)';
+my $doc_sect = $doc_com . '([' . $doc_special . ']?[\w\s]+):(.*)';
+my $doc_content = $doc_com . '(.*)';
+my $doc_block = $doc_com . 'DOC:\s*(.*)?';
+
+my %constants;
+my %parameterdescs;
+my @parameterlist;
+my %sections;
+my @sectionlist;
+my $sectcheck;
+my $struct_actual;
+
+my $contents = "";
+my $section_default = "Description"; # default section
+my $section_intro = "Introduction";
+my $section = $section_default;
+my $section_context = "Context";
+
+my $undescribed = "-- undescribed --";
+
+reset_state();
+
+while ($ARGV[0] =~ m/^-(.*)/) {
+ my $cmd = shift @ARGV;
+ if ($cmd eq "-html") {
+ $output_mode = "html";
+ %highlights = %highlights_html;
+ $blankline = $blankline_html;
+ } elsif ($cmd eq "-html5") {
+ $output_mode = "html5";
+ %highlights = %highlights_html5;
+ $blankline = $blankline_html5;
+ } elsif ($cmd eq "-man") {
+ $output_mode = "man";
+ %highlights = %highlights_man;
+ $blankline = $blankline_man;
+ } elsif ($cmd eq "-text") {
+ $output_mode = "text";
+ %highlights = %highlights_text;
+ $blankline = $blankline_text;
+ } elsif ($cmd eq "-docbook") {
+ $output_mode = "xml";
+ %highlights = %highlights_xml;
+ $blankline = $blankline_xml;
+ } elsif ($cmd eq "-list") {
+ $output_mode = "list";
+ %highlights = %highlights_list;
+ $blankline = $blankline_list;
+ } elsif ($cmd eq "-gnome") {
+ $output_mode = "gnome";
+ %highlights = %highlights_gnome;
+ $blankline = $blankline_gnome;
+ } elsif ($cmd eq "-module") { # not needed for XML, inherits from calling document
+ $modulename = shift @ARGV;
+ } elsif ($cmd eq "-function") { # to only output specific functions
+ $function_only = 1;
+ $function = shift @ARGV;
+ $function_table{$function} = 1;
+ } elsif ($cmd eq "-nofunction") { # to only output specific functions
+ $function_only = 2;
+ $function = shift @ARGV;
+ $function_table{$function} = 1;
+ } elsif ($cmd eq "-v") {
+ $verbose = 1;
+ } elsif (($cmd eq "-h") || ($cmd eq "--help")) {
+ usage();
+ } elsif ($cmd eq '-no-doc-sections') {
+ $no_doc_sections = 1;
+ }
+}
+
+# continue execution near EOF;
+
+sub usage {
+ print "Usage: $0 [ -docbook | -html | -html5 | -text | -man | -list ]\n";
+ print " [ -no-doc-sections ]\n";
+ print " [ -function funcname [ -function funcname ...] ]\n";
+ print " [ -nofunction funcname [ -nofunction funcname ...] ]\n";
+ print " [ -v ]\n";
+ print " c source file(s) > outputfile\n";
+ print " -v : verbose output, more warnings & other info listed\n";
+ exit 1;
+}
+
+# get kernel version from env
+sub get_kernel_version() {
+ my $version = 'unknown kernel version';
+
+ if (defined($ENV{'U_BOOT_VERSION'})) {
+ $version = $ENV{'U_BOOT_VERSION'};
+ }
+ return $version;
+}
+
+##
+# dumps section contents to arrays/hashes intended for that purpose.
+#
+sub dump_section {
+ my $file = shift;
+ my $name = shift;
+ my $contents = join "\n", @_;
+
+ if ($name =~ m/$type_constant/) {
+ $name = $1;
+# print STDERR "constant section '$1' = '$contents'\n";
+ $constants{$name} = $contents;
+ } elsif ($name =~ m/$type_param/) {
+# print STDERR "parameter def '$1' = '$contents'\n";
+ $name = $1;
+ $parameterdescs{$name} = $contents;
+ $sectcheck = $sectcheck . $name . " ";
+ } elsif ($name eq "@\.\.\.") {
+# print STDERR "parameter def '...' = '$contents'\n";
+ $name = "...";
+ $parameterdescs{$name} = $contents;
+ $sectcheck = $sectcheck . $name . " ";
+ } else {
+# print STDERR "other section '$name' = '$contents'\n";
+ if (defined($sections{$name}) && ($sections{$name} ne "")) {
+ print STDERR "Error(${file}:$.): duplicate section name '$name'\n";
+ ++$errors;
+ }
+ $sections{$name} = $contents;
+ push @sectionlist, $name;
+ }
+}
+
+##
+# dump DOC: section after checking that it should go out
+#
+sub dump_doc_section {
+ my $file = shift;
+ my $name = shift;
+ my $contents = join "\n", @_;
+
+ if ($no_doc_sections) {
+ return;
+ }
+
+ if (($function_only == 0) ||
+ ( $function_only == 1 && defined($function_table{$name})) ||
+ ( $function_only == 2 && !defined($function_table{$name})))
+ {
+ dump_section($file, $name, $contents);
+ output_blockhead({'sectionlist' => \@sectionlist,
+ 'sections' => \%sections,
+ 'module' => $modulename,
+ 'content-only' => ($function_only != 0), });
+ }
+}
+
+##
+# output function
+#
+# parameterdescs, a hash.
+# function => "function name"
+# parameterlist => @list of parameters
+# parameterdescs => %parameter descriptions
+# sectionlist => @list of sections
+# sections => %section descriptions
+#
+
+sub output_highlight {
+ my $contents = join "\n",@_;
+ my $line;
+
+# DEBUG
+# if (!defined $contents) {
+# use Carp;
+# confess "output_highlight got called with no args?\n";
+# }
+
+ if ($output_mode eq "html" || $output_mode eq "html5" ||
+ $output_mode eq "xml") {
+ $contents = local_unescape($contents);
+ # convert data read & converted thru xml_escape() into &xyz; format:
+ $contents =~ s/\\\\\\/\&/g;
+ }
+# print STDERR "contents b4:$contents\n";
+ eval $dohighlight;
+ die $@ if $@;
+# print STDERR "contents af:$contents\n";
+
+# strip whitespaces when generating html5
+ if ($output_mode eq "html5") {
+ $contents =~ s/^\s+//;
+ $contents =~ s/\s+$//;
+ }
+ foreach $line (split "\n", $contents) {
+ if ($line eq ""){
+ print $lineprefix, local_unescape($blankline);
+ } else {
+ $line =~ s/\\\\\\/\&/g;
+ if ($output_mode eq "man" && substr($line, 0, 1) eq ".") {
+ print "\\&$line";
+ } else {
+ print $lineprefix, $line;
+ }
+ }
+ print "\n";
+ }
+}
+
+# output sections in html
+sub output_section_html(%) {
+ my %args = %{$_[0]};
+ my $section;
+
+ foreach $section (@{$args{'sectionlist'}}) {
+ print "<h3>$section</h3>\n";
+ print "<blockquote>\n";
+ output_highlight($args{'sections'}{$section});
+ print "</blockquote>\n";
+ }
+}
+
+# output enum in html
+sub output_enum_html(%) {
+ my %args = %{$_[0]};
+ my ($parameter);
+ my $count;
+ print "<h2>enum " . $args{'enum'} . "</h2>\n";
+
+ print "<b>enum " . $args{'enum'} . "</b> {<br>\n";
+ $count = 0;
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ print " <b>" . $parameter . "</b>";
+ if ($count != $#{$args{'parameterlist'}}) {
+ $count++;
+ print ",\n";
+ }
+ print "<br>";
+ }
+ print "};<br>\n";
+
+ print "<h3>Constants</h3>\n";
+ print "<dl>\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ print "<dt><b>" . $parameter . "</b>\n";
+ print "<dd>";
+ output_highlight($args{'parameterdescs'}{$parameter});
+ }
+ print "</dl>\n";
+ output_section_html(@_);
+ print "<hr>\n";
+}
+
+# output typedef in html
+sub output_typedef_html(%) {
+ my %args = %{$_[0]};
+ my ($parameter);
+ my $count;
+ print "<h2>typedef " . $args{'typedef'} . "</h2>\n";
+
+ print "<b>typedef " . $args{'typedef'} . "</b>\n";
+ output_section_html(@_);
+ print "<hr>\n";
+}
+
+# output struct in html
+sub output_struct_html(%) {
+ my %args = %{$_[0]};
+ my ($parameter);
+
+ print "<h2>" . $args{'type'} . " " . $args{'struct'} . " - " . $args{'purpose'} . "</h2>\n";
+ print "<b>" . $args{'type'} . " " . $args{'struct'} . "</b> {<br>\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ if ($parameter =~ /^#/) {
+ print "$parameter<br>\n";
+ next;
+ }
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+ $type = $args{'parametertypes'}{$parameter};
+ if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+ # pointer-to-function
+ print " <i>$1</i><b>$parameter</b>) <i>($2)</i>;<br>\n";
+ } elsif ($type =~ m/^(.*?)\s*(:.*)/) {
+ # bitfield
+ print " <i>$1</i> <b>$parameter</b>$2;<br>\n";
+ } else {
+ print " <i>$type</i> <b>$parameter</b>;<br>\n";
+ }
+ }
+ print "};<br>\n";
+
+ print "<h3>Members</h3>\n";
+ print "<dl>\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ ($parameter =~ /^#/) && next;
+
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+ print "<dt><b>" . $parameter . "</b>\n";
+ print "<dd>";
+ output_highlight($args{'parameterdescs'}{$parameter_name});
+ }
+ print "</dl>\n";
+ output_section_html(@_);
+ print "<hr>\n";
+}
+
+# output function in html
+sub output_function_html(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $count;
+
+ print "<h2>" . $args{'function'} . " - " . $args{'purpose'} . "</h2>\n";
+ print "<i>" . $args{'functiontype'} . "</i>\n";
+ print "<b>" . $args{'function'} . "</b>\n";
+ print "(";
+ $count = 0;
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ $type = $args{'parametertypes'}{$parameter};
+ if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+ # pointer-to-function
+ print "<i>$1</i><b>$parameter</b>) <i>($2)</i>";
+ } else {
+ print "<i>" . $type . "</i> <b>" . $parameter . "</b>";
+ }
+ if ($count != $#{$args{'parameterlist'}}) {
+ $count++;
+ print ",\n";
+ }
+ }
+ print ")\n";
+
+ print "<h3>Arguments</h3>\n";
+ print "<dl>\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+ print "<dt><b>" . $parameter . "</b>\n";
+ print "<dd>";
+ output_highlight($args{'parameterdescs'}{$parameter_name});
+ }
+ print "</dl>\n";
+ output_section_html(@_);
+ print "<hr>\n";
+}
+
+# output DOC: block header in html
+sub output_blockhead_html(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $count;
+
+ foreach $section (@{$args{'sectionlist'}}) {
+ print "<h3>$section</h3>\n";
+ print "<ul>\n";
+ output_highlight($args{'sections'}{$section});
+ print "</ul>\n";
+ }
+ print "<hr>\n";
+}
+
+# output sections in html5
+sub output_section_html5(%) {
+ my %args = %{$_[0]};
+ my $section;
+
+ foreach $section (@{$args{'sectionlist'}}) {
+ print "<section>\n";
+ print "<h1>$section</h1>\n";
+ print "<p>\n";
+ output_highlight($args{'sections'}{$section});
+ print "</p>\n";
+ print "</section>\n";
+ }
+}
+
+# output enum in html5
+sub output_enum_html5(%) {
+ my %args = %{$_[0]};
+ my ($parameter);
+ my $count;
+ my $html5id;
+
+ $html5id = $args{'enum'};
+ $html5id =~ s/[^a-zA-Z0-9\-]+/_/g;
+ print "<article class=\"enum\" id=\"enum:". $html5id . "\">";
+ print "<h1>enum " . $args{'enum'} . "</h1>\n";
+ print "<ol class=\"code\">\n";
+ print "<li>";
+ print "<span class=\"keyword\">enum</span> ";
+ print "<span class=\"identifier\">" . $args{'enum'} . "</span> {";
+ print "</li>\n";
+ $count = 0;
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ print "<li class=\"indent\">";
+ print "<span class=\"param\">" . $parameter . "</span>";
+ if ($count != $#{$args{'parameterlist'}}) {
+ $count++;
+ print ",";
+ }
+ print "</li>\n";
+ }
+ print "<li>};</li>\n";
+ print "</ol>\n";
+
+ print "<section>\n";
+ print "<h1>Constants</h1>\n";
+ print "<dl>\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ print "<dt>" . $parameter . "</dt>\n";
+ print "<dd>";
+ output_highlight($args{'parameterdescs'}{$parameter});
+ print "</dd>\n";
+ }
+ print "</dl>\n";
+ print "</section>\n";
+ output_section_html5(@_);
+ print "</article>\n";
+}
+
+# output typedef in html5
+sub output_typedef_html5(%) {
+ my %args = %{$_[0]};
+ my ($parameter);
+ my $count;
+ my $html5id;
+
+ $html5id = $args{'typedef'};
+ $html5id =~ s/[^a-zA-Z0-9\-]+/_/g;
+ print "<article class=\"typedef\" id=\"typedef:" . $html5id . "\">\n";
+ print "<h1>typedef " . $args{'typedef'} . "</h1>\n";
+
+ print "<ol class=\"code\">\n";
+ print "<li>";
+ print "<span class=\"keyword\">typedef</span> ";
+ print "<span class=\"identifier\">" . $args{'typedef'} . "</span>";
+ print "</li>\n";
+ print "</ol>\n";
+ output_section_html5(@_);
+ print "</article>\n";
+}
+
+# output struct in html5
+sub output_struct_html5(%) {
+ my %args = %{$_[0]};
+ my ($parameter);
+ my $html5id;
+
+ $html5id = $args{'struct'};
+ $html5id =~ s/[^a-zA-Z0-9\-]+/_/g;
+ print "<article class=\"struct\" id=\"struct:" . $html5id . "\">\n";
+ print "<hgroup>\n";
+ print "<h1>" . $args{'type'} . " " . $args{'struct'} . "</h1>";
+ print "<h2>". $args{'purpose'} . "</h2>\n";
+ print "</hgroup>\n";
+ print "<ol class=\"code\">\n";
+ print "<li>";
+ print "<span class=\"type\">" . $args{'type'} . "</span> ";
+ print "<span class=\"identifier\">" . $args{'struct'} . "</span> {";
+ print "</li>\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ print "<li class=\"indent\">";
+ if ($parameter =~ /^#/) {
+ print "<span class=\"param\">" . $parameter ."</span>\n";
+ print "</li>\n";
+ next;
+ }
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+ $type = $args{'parametertypes'}{$parameter};
+ if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+ # pointer-to-function
+ print "<span class=\"type\">$1</span> ";
+ print "<span class=\"param\">$parameter</span>";
+ print "<span class=\"type\">)</span> ";
+ print "(<span class=\"args\">$2</span>);";
+ } elsif ($type =~ m/^(.*?)\s*(:.*)/) {
+ # bitfield
+ print "<span class=\"type\">$1</span> ";
+ print "<span class=\"param\">$parameter</span>";
+ print "<span class=\"bits\">$2</span>;";
+ } else {
+ print "<span class=\"type\">$type</span> ";
+ print "<span class=\"param\">$parameter</span>;";
+ }
+ print "</li>\n";
+ }
+ print "<li>};</li>\n";
+ print "</ol>\n";
+
+ print "<section>\n";
+ print "<h1>Members</h1>\n";
+ print "<dl>\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ ($parameter =~ /^#/) && next;
+
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+ print "<dt>" . $parameter . "</dt>\n";
+ print "<dd>";
+ output_highlight($args{'parameterdescs'}{$parameter_name});
+ print "</dd>\n";
+ }
+ print "</dl>\n";
+ print "</section>\n";
+ output_section_html5(@_);
+ print "</article>\n";
+}
+
+# output function in html5
+sub output_function_html5(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $count;
+ my $html5id;
+
+ $html5id = $args{'function'};
+ $html5id =~ s/[^a-zA-Z0-9\-]+/_/g;
+ print "<article class=\"function\" id=\"func:". $html5id . "\">\n";
+ print "<hgroup>\n";
+ print "<h1>" . $args{'function'} . "</h1>";
+ print "<h2>" . $args{'purpose'} . "</h2>\n";
+ print "</hgroup>\n";
+ print "<ol class=\"code\">\n";
+ print "<li>";
+ print "<span class=\"type\">" . $args{'functiontype'} . "</span> ";
+ print "<span class=\"identifier\">" . $args{'function'} . "</span> (";
+ print "</li>";
+ $count = 0;
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ print "<li class=\"indent\">";
+ $type = $args{'parametertypes'}{$parameter};
+ if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+ # pointer-to-function
+ print "<span class=\"type\">$1</span> ";
+ print "<span class=\"param\">$parameter</span>";
+ print "<span class=\"type\">)</span> ";
+ print "(<span class=\"args\">$2</span>)";
+ } else {
+ print "<span class=\"type\">$type</span> ";
+ print "<span class=\"param\">$parameter</span>";
+ }
+ if ($count != $#{$args{'parameterlist'}}) {
+ $count++;
+ print ",";
+ }
+ print "</li>\n";
+ }
+ print "<li>)</li>\n";
+ print "</ol>\n";
+
+ print "<section>\n";
+ print "<h1>Arguments</h1>\n";
+ print "<p>\n";
+ print "<dl>\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+ print "<dt>" . $parameter . "</dt>\n";
+ print "<dd>";
+ output_highlight($args{'parameterdescs'}{$parameter_name});
+ print "</dd>\n";
+ }
+ print "</dl>\n";
+ print "</section>\n";
+ output_section_html5(@_);
+ print "</article>\n";
+}
+
+# output DOC: block header in html5
+sub output_blockhead_html5(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $count;
+ my $html5id;
+
+ foreach $section (@{$args{'sectionlist'}}) {
+ $html5id = $section;
+ $html5id =~ s/[^a-zA-Z0-9\-]+/_/g;
+ print "<article class=\"doc\" id=\"doc:". $html5id . "\">\n";
+ print "<h1>$section</h1>\n";
+ print "<p>\n";
+ output_highlight($args{'sections'}{$section});
+ print "</p>\n";
+ }
+ print "</article>\n";
+}
+
+sub output_section_xml(%) {
+ my %args = %{$_[0]};
+ my $section;
+ # print out each section
+ $lineprefix=" ";
+ foreach $section (@{$args{'sectionlist'}}) {
+ print "<refsect1>\n";
+ print "<title>$section</title>\n";
+ if ($section =~ m/EXAMPLE/i) {
+ print "<informalexample><programlisting>\n";
+ } else {
+ print "<para>\n";
+ }
+ output_highlight($args{'sections'}{$section});
+ if ($section =~ m/EXAMPLE/i) {
+ print "</programlisting></informalexample>\n";
+ } else {
+ print "</para>\n";
+ }
+ print "</refsect1>\n";
+ }
+}
+
+# output function in XML DocBook
+sub output_function_xml(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $count;
+ my $id;
+
+ $id = "API-" . $args{'function'};
+ $id =~ s/[^A-Za-z0-9]/-/g;
+
+ print "<refentry id=\"$id\">\n";
+ print "<refentryinfo>\n";
+ print " <title>U-BOOT</title>\n";
+ print " <productname>Bootloader Hackers Manual</productname>\n";
+ print " <date>$man_date</date>\n";
+ print "</refentryinfo>\n";
+ print "<refmeta>\n";
+ print " <refentrytitle><phrase>" . $args{'function'} . "</phrase></refentrytitle>\n";
+ print " <manvolnum>9</manvolnum>\n";
+ print " <refmiscinfo class=\"version\">" . $kernelversion . "</refmiscinfo>\n";
+ print "</refmeta>\n";
+ print "<refnamediv>\n";
+ print " <refname>" . $args{'function'} . "</refname>\n";
+ print " <refpurpose>\n";
+ print " ";
+ output_highlight ($args{'purpose'});
+ print " </refpurpose>\n";
+ print "</refnamediv>\n";
+
+ print "<refsynopsisdiv>\n";
+ print " <title>Synopsis</title>\n";
+ print " <funcsynopsis><funcprototype>\n";
+ print " <funcdef>" . $args{'functiontype'} . " ";
+ print "<function>" . $args{'function'} . " </function></funcdef>\n";
+
+ $count = 0;
+ if ($#{$args{'parameterlist'}} >= 0) {
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ $type = $args{'parametertypes'}{$parameter};
+ if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+ # pointer-to-function
+ print " <paramdef>$1<parameter>$parameter</parameter>)\n";
+ print " <funcparams>$2</funcparams></paramdef>\n";
+ } else {
+ print " <paramdef>" . $type;
+ print " <parameter>$parameter</parameter></paramdef>\n";
+ }
+ }
+ } else {
+ print " <void/>\n";
+ }
+ print " </funcprototype></funcsynopsis>\n";
+ print "</refsynopsisdiv>\n";
+
+ # print parameters
+ print "<refsect1>\n <title>Arguments</title>\n";
+ if ($#{$args{'parameterlist'}} >= 0) {
+ print " <variablelist>\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ print " <varlistentry>\n <term><parameter>$parameter</parameter></term>\n";
+ print " <listitem>\n <para>\n";
+ $lineprefix=" ";
+ output_highlight($args{'parameterdescs'}{$parameter_name});
+ print " </para>\n </listitem>\n </varlistentry>\n";
+ }
+ print " </variablelist>\n";
+ } else {
+ print " <para>\n None\n </para>\n";
+ }
+ print "</refsect1>\n";
+
+ output_section_xml(@_);
+ print "</refentry>\n\n";
+}
+
+# output struct in XML DocBook
+sub output_struct_xml(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $id;
+
+ $id = "API-struct-" . $args{'struct'};
+ $id =~ s/[^A-Za-z0-9]/-/g;
+
+ print "<refentry id=\"$id\">\n";
+ print "<refentryinfo>\n";
+ print " <title>U-BOOT</title>\n";
+ print " <productname>Bootloader Hackers Manual</productname>\n";
+ print " <date>$man_date</date>\n";
+ print "</refentryinfo>\n";
+ print "<refmeta>\n";
+ print " <refentrytitle><phrase>" . $args{'type'} . " " . $args{'struct'} . "</phrase></refentrytitle>\n";
+ print " <manvolnum>9</manvolnum>\n";
+ print " <refmiscinfo class=\"version\">" . $kernelversion . "</refmiscinfo>\n";
+ print "</refmeta>\n";
+ print "<refnamediv>\n";
+ print " <refname>" . $args{'type'} . " " . $args{'struct'} . "</refname>\n";
+ print " <refpurpose>\n";
+ print " ";
+ output_highlight ($args{'purpose'});
+ print " </refpurpose>\n";
+ print "</refnamediv>\n";
+
+ print "<refsynopsisdiv>\n";
+ print " <title>Synopsis</title>\n";
+ print " <programlisting>\n";
+ print $args{'type'} . " " . $args{'struct'} . " {\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ if ($parameter =~ /^#/) {
+ my $prm = $parameter;
+ # convert data read & converted thru xml_escape() into &xyz; format:
+ # This allows us to have #define macros interspersed in a struct.
+ $prm =~ s/\\\\\\/\&/g;
+ print "$prm\n";
+ next;
+ }
+
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ defined($args{'parameterdescs'}{$parameter_name}) || next;
+ ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+ $type = $args{'parametertypes'}{$parameter};
+ if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+ # pointer-to-function
+ print " $1 $parameter) ($2);\n";
+ } elsif ($type =~ m/^(.*?)\s*(:.*)/) {
+ # bitfield
+ print " $1 $parameter$2;\n";
+ } else {
+ print " " . $type . " " . $parameter . ";\n";
+ }
+ }
+ print "};";
+ print " </programlisting>\n";
+ print "</refsynopsisdiv>\n";
+
+ print " <refsect1>\n";
+ print " <title>Members</title>\n";
+
+ if ($#{$args{'parameterlist'}} >= 0) {
+ print " <variablelist>\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ ($parameter =~ /^#/) && next;
+
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ defined($args{'parameterdescs'}{$parameter_name}) || next;
+ ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+ print " <varlistentry>";
+ print " <term>$parameter</term>\n";
+ print " <listitem><para>\n";
+ output_highlight($args{'parameterdescs'}{$parameter_name});
+ print " </para></listitem>\n";
+ print " </varlistentry>\n";
+ }
+ print " </variablelist>\n";
+ } else {
+ print " <para>\n None\n </para>\n";
+ }
+ print " </refsect1>\n";
+
+ output_section_xml(@_);
+
+ print "</refentry>\n\n";
+}
+
+# output enum in XML DocBook
+sub output_enum_xml(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $count;
+ my $id;
+
+ $id = "API-enum-" . $args{'enum'};
+ $id =~ s/[^A-Za-z0-9]/-/g;
+
+ print "<refentry id=\"$id\">\n";
+ print "<refentryinfo>\n";
+ print " <title>U-BOOT</title>\n";
+ print " <productname>Bootloader Hackers Manual</productname>\n";
+ print " <date>$man_date</date>\n";
+ print "</refentryinfo>\n";
+ print "<refmeta>\n";
+ print " <refentrytitle><phrase>enum " . $args{'enum'} . "</phrase></refentrytitle>\n";
+ print " <manvolnum>9</manvolnum>\n";
+ print " <refmiscinfo class=\"version\">" . $kernelversion . "</refmiscinfo>\n";
+ print "</refmeta>\n";
+ print "<refnamediv>\n";
+ print " <refname>enum " . $args{'enum'} . "</refname>\n";
+ print " <refpurpose>\n";
+ print " ";
+ output_highlight ($args{'purpose'});
+ print " </refpurpose>\n";
+ print "</refnamediv>\n";
+
+ print "<refsynopsisdiv>\n";
+ print " <title>Synopsis</title>\n";
+ print " <programlisting>\n";
+ print "enum " . $args{'enum'} . " {\n";
+ $count = 0;
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ print " $parameter";
+ if ($count != $#{$args{'parameterlist'}}) {
+ $count++;
+ print ",";
+ }
+ print "\n";
+ }
+ print "};";
+ print " </programlisting>\n";
+ print "</refsynopsisdiv>\n";
+
+ print "<refsect1>\n";
+ print " <title>Constants</title>\n";
+ print " <variablelist>\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ print " <varlistentry>";
+ print " <term>$parameter</term>\n";
+ print " <listitem><para>\n";
+ output_highlight($args{'parameterdescs'}{$parameter_name});
+ print " </para></listitem>\n";
+ print " </varlistentry>\n";
+ }
+ print " </variablelist>\n";
+ print "</refsect1>\n";
+
+ output_section_xml(@_);
+
+ print "</refentry>\n\n";
+}
+
+# output typedef in XML DocBook
+sub output_typedef_xml(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $id;
+
+ $id = "API-typedef-" . $args{'typedef'};
+ $id =~ s/[^A-Za-z0-9]/-/g;
+
+ print "<refentry id=\"$id\">\n";
+ print "<refentryinfo>\n";
+ print " <title>U-BOOT</title>\n";
+ print " <productname>Bootloader Hackers Manual</productname>\n";
+ print " <date>$man_date</date>\n";
+ print "</refentryinfo>\n";
+ print "<refmeta>\n";
+ print " <refentrytitle><phrase>typedef " . $args{'typedef'} . "</phrase></refentrytitle>\n";
+ print " <manvolnum>9</manvolnum>\n";
+ print "</refmeta>\n";
+ print "<refnamediv>\n";
+ print " <refname>typedef " . $args{'typedef'} . "</refname>\n";
+ print " <refpurpose>\n";
+ print " ";
+ output_highlight ($args{'purpose'});
+ print " </refpurpose>\n";
+ print "</refnamediv>\n";
+
+ print "<refsynopsisdiv>\n";
+ print " <title>Synopsis</title>\n";
+ print " <synopsis>typedef " . $args{'typedef'} . ";</synopsis>\n";
+ print "</refsynopsisdiv>\n";
+
+ output_section_xml(@_);
+
+ print "</refentry>\n\n";
+}
+
+# output in XML DocBook
+sub output_blockhead_xml(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $count;
+
+ my $id = $args{'module'};
+ $id =~ s/[^A-Za-z0-9]/-/g;
+
+ # print out each section
+ $lineprefix=" ";
+ foreach $section (@{$args{'sectionlist'}}) {
+ if (!$args{'content-only'}) {
+ print "<refsect1>\n <title>$section</title>\n";
+ }
+ if ($section =~ m/EXAMPLE/i) {
+ print "<example><para>\n";
+ } else {
+ print "<para>\n";
+ }
+ output_highlight($args{'sections'}{$section});
+ if ($section =~ m/EXAMPLE/i) {
+ print "</para></example>\n";
+ } else {
+ print "</para>";
+ }
+ if (!$args{'content-only'}) {
+ print "\n</refsect1>\n";
+ }
+ }
+
+ print "\n\n";
+}
+
+# output in XML DocBook
+sub output_function_gnome {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $count;
+ my $id;
+
+ $id = $args{'module'} . "-" . $args{'function'};
+ $id =~ s/[^A-Za-z0-9]/-/g;
+
+ print "<sect2>\n";
+ print " <title id=\"$id\">" . $args{'function'} . "</title>\n";
+
+ print " <funcsynopsis>\n";
+ print " <funcdef>" . $args{'functiontype'} . " ";
+ print "<function>" . $args{'function'} . " ";
+ print "</function></funcdef>\n";
+
+ $count = 0;
+ if ($#{$args{'parameterlist'}} >= 0) {
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ $type = $args{'parametertypes'}{$parameter};
+ if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+ # pointer-to-function
+ print " <paramdef>$1 <parameter>$parameter</parameter>)\n";
+ print " <funcparams>$2</funcparams></paramdef>\n";
+ } else {
+ print " <paramdef>" . $type;
+ print " <parameter>$parameter</parameter></paramdef>\n";
+ }
+ }
+ } else {
+ print " <void>\n";
+ }
+ print " </funcsynopsis>\n";
+ if ($#{$args{'parameterlist'}} >= 0) {
+ print " <informaltable pgwide=\"1\" frame=\"none\" role=\"params\">\n";
+ print "<tgroup cols=\"2\">\n";
+ print "<colspec colwidth=\"2*\">\n";
+ print "<colspec colwidth=\"8*\">\n";
+ print "<tbody>\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ print " <row><entry align=\"right\"><parameter>$parameter</parameter></entry>\n";
+ print " <entry>\n";
+ $lineprefix=" ";
+ output_highlight($args{'parameterdescs'}{$parameter_name});
+ print " </entry></row>\n";
+ }
+ print " </tbody></tgroup></informaltable>\n";
+ } else {
+ print " <para>\n None\n </para>\n";
+ }
+
+ # print out each section
+ $lineprefix=" ";
+ foreach $section (@{$args{'sectionlist'}}) {
+ print "<simplesect>\n <title>$section</title>\n";
+ if ($section =~ m/EXAMPLE/i) {
+ print "<example><programlisting>\n";
+ } else {
+ }
+ print "<para>\n";
+ output_highlight($args{'sections'}{$section});
+ print "</para>\n";
+ if ($section =~ m/EXAMPLE/i) {
+ print "</programlisting></example>\n";
+ } else {
+ }
+ print " </simplesect>\n";
+ }
+
+ print "</sect2>\n\n";
+}
+
+##
+# output function in man
+sub output_function_man(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $count;
+
+ print ".TH \"$args{'function'}\" 9 \"$args{'function'}\" \"$man_date\" \"Bootloader Hacker's Manual\" U-BOOT\n";
+
+ print ".SH NAME\n";
+ print $args{'function'} . " \\- " . $args{'purpose'} . "\n";
+
+ print ".SH SYNOPSIS\n";
+ if ($args{'functiontype'} ne "") {
+ print ".B \"" . $args{'functiontype'} . "\" " . $args{'function'} . "\n";
+ } else {
+ print ".B \"" . $args{'function'} . "\n";
+ }
+ $count = 0;
+ my $parenth = "(";
+ my $post = ",";
+ foreach my $parameter (@{$args{'parameterlist'}}) {
+ if ($count == $#{$args{'parameterlist'}}) {
+ $post = ");";
+ }
+ $type = $args{'parametertypes'}{$parameter};
+ if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+ # pointer-to-function
+ print ".BI \"" . $parenth . $1 . "\" " . $parameter . " \") (" . $2 . ")" . $post . "\"\n";
+ } else {
+ $type =~ s/([^\*])$/$1 /;
+ print ".BI \"" . $parenth . $type . "\" " . $parameter . " \"" . $post . "\"\n";
+ }
+ $count++;
+ $parenth = "";
+ }
+
+ print ".SH ARGUMENTS\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ print ".IP \"" . $parameter . "\" 12\n";
+ output_highlight($args{'parameterdescs'}{$parameter_name});
+ }
+ foreach $section (@{$args{'sectionlist'}}) {
+ print ".SH \"", uc $section, "\"\n";
+ output_highlight($args{'sections'}{$section});
+ }
+}
+
+##
+# output enum in man
+sub output_enum_man(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $count;
+
+ print ".TH \"$args{'module'}\" 9 \"enum $args{'enum'}\" \"$man_date\" \"API Manual\" U-BOOT\n";
+
+ print ".SH NAME\n";
+ print "enum " . $args{'enum'} . " \\- " . $args{'purpose'} . "\n";
+
+ print ".SH SYNOPSIS\n";
+ print "enum " . $args{'enum'} . " {\n";
+ $count = 0;
+ foreach my $parameter (@{$args{'parameterlist'}}) {
+ print ".br\n.BI \" $parameter\"\n";
+ if ($count == $#{$args{'parameterlist'}}) {
+ print "\n};\n";
+ last;
+ }
+ else {
+ print ", \n.br\n";
+ }
+ $count++;
+ }
+
+ print ".SH Constants\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ print ".IP \"" . $parameter . "\" 12\n";
+ output_highlight($args{'parameterdescs'}{$parameter_name});
+ }
+ foreach $section (@{$args{'sectionlist'}}) {
+ print ".SH \"$section\"\n";
+ output_highlight($args{'sections'}{$section});
+ }
+}
+
+##
+# output struct in man
+sub output_struct_man(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+
+ print ".TH \"$args{'module'}\" 9 \"" . $args{'type'} . " " . $args{'struct'} . "\" \"$man_date\" \"API Manual\" U-BOOT\n";
+
+ print ".SH NAME\n";
+ print $args{'type'} . " " . $args{'struct'} . " \\- " . $args{'purpose'} . "\n";
+
+ print ".SH SYNOPSIS\n";
+ print $args{'type'} . " " . $args{'struct'} . " {\n.br\n";
+
+ foreach my $parameter (@{$args{'parameterlist'}}) {
+ if ($parameter =~ /^#/) {
+ print ".BI \"$parameter\"\n.br\n";
+ next;
+ }
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+ $type = $args{'parametertypes'}{$parameter};
+ if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+ # pointer-to-function
+ print ".BI \" " . $1 . "\" " . $parameter . " \") (" . $2 . ")" . "\"\n;\n";
+ } elsif ($type =~ m/^(.*?)\s*(:.*)/) {
+ # bitfield
+ print ".BI \" " . $1 . "\ \" " . $parameter . $2 . " \"" . "\"\n;\n";
+ } else {
+ $type =~ s/([^\*])$/$1 /;
+ print ".BI \" " . $type . "\" " . $parameter . " \"" . "\"\n;\n";
+ }
+ print "\n.br\n";
+ }
+ print "};\n.br\n";
+
+ print ".SH Members\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ ($parameter =~ /^#/) && next;
+
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+ print ".IP \"" . $parameter . "\" 12\n";
+ output_highlight($args{'parameterdescs'}{$parameter_name});
+ }
+ foreach $section (@{$args{'sectionlist'}}) {
+ print ".SH \"$section\"\n";
+ output_highlight($args{'sections'}{$section});
+ }
+}
+
+##
+# output typedef in man
+sub output_typedef_man(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+
+ print ".TH \"$args{'module'}\" 9 \"$args{'typedef'}\" \"$man_date\" \"API Manual\" U-BOOT\n";
+
+ print ".SH NAME\n";
+ print "typedef " . $args{'typedef'} . " \\- " . $args{'purpose'} . "\n";
+
+ foreach $section (@{$args{'sectionlist'}}) {
+ print ".SH \"$section\"\n";
+ output_highlight($args{'sections'}{$section});
+ }
+}
+
+sub output_blockhead_man(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $count;
+
+ print ".TH \"$args{'module'}\" 9 \"$args{'module'}\" \"$man_date\" \"API Manual\" U-BOOT\n";
+
+ foreach $section (@{$args{'sectionlist'}}) {
+ print ".SH \"$section\"\n";
+ output_highlight($args{'sections'}{$section});
+ }
+}
+
+##
+# output in text
+sub output_function_text(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+ my $start;
+
+ print "Name:\n\n";
+ print $args{'function'} . " - " . $args{'purpose'} . "\n";
+
+ print "\nSynopsis:\n\n";
+ if ($args{'functiontype'} ne "") {
+ $start = $args{'functiontype'} . " " . $args{'function'} . " (";
+ } else {
+ $start = $args{'function'} . " (";
+ }
+ print $start;
+
+ my $count = 0;
+ foreach my $parameter (@{$args{'parameterlist'}}) {
+ $type = $args{'parametertypes'}{$parameter};
+ if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+ # pointer-to-function
+ print $1 . $parameter . ") (" . $2;
+ } else {
+ print $type . " " . $parameter;
+ }
+ if ($count != $#{$args{'parameterlist'}}) {
+ $count++;
+ print ",\n";
+ print " " x length($start);
+ } else {
+ print ");\n\n";
+ }
+ }
+
+ print "Arguments:\n\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ print $parameter . "\n\t" . $args{'parameterdescs'}{$parameter_name} . "\n";
+ }
+ output_section_text(@_);
+}
+
+#output sections in text
+sub output_section_text(%) {
+ my %args = %{$_[0]};
+ my $section;
+
+ print "\n";
+ foreach $section (@{$args{'sectionlist'}}) {
+ print "$section:\n\n";
+ output_highlight($args{'sections'}{$section});
+ }
+ print "\n\n";
+}
+
+# output enum in text
+sub output_enum_text(%) {
+ my %args = %{$_[0]};
+ my ($parameter);
+ my $count;
+ print "Enum:\n\n";
+
+ print "enum " . $args{'enum'} . " - " . $args{'purpose'} . "\n\n";
+ print "enum " . $args{'enum'} . " {\n";
+ $count = 0;
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ print "\t$parameter";
+ if ($count != $#{$args{'parameterlist'}}) {
+ $count++;
+ print ",";
+ }
+ print "\n";
+ }
+ print "};\n\n";
+
+ print "Constants:\n\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ print "$parameter\n\t";
+ print $args{'parameterdescs'}{$parameter} . "\n";
+ }
+
+ output_section_text(@_);
+}
+
+# output typedef in text
+sub output_typedef_text(%) {
+ my %args = %{$_[0]};
+ my ($parameter);
+ my $count;
+ print "Typedef:\n\n";
+
+ print "typedef " . $args{'typedef'} . " - " . $args{'purpose'} . "\n";
+ output_section_text(@_);
+}
+
+# output struct as text
+sub output_struct_text(%) {
+ my %args = %{$_[0]};
+ my ($parameter);
+
+ print $args{'type'} . " " . $args{'struct'} . " - " . $args{'purpose'} . "\n\n";
+ print $args{'type'} . " " . $args{'struct'} . " {\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ if ($parameter =~ /^#/) {
+ print "$parameter\n";
+ next;
+ }
+
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+ $type = $args{'parametertypes'}{$parameter};
+ if ($type =~ m/([^\(]*\(\*)\s*\)\s*\(([^\)]*)\)/) {
+ # pointer-to-function
+ print "\t$1 $parameter) ($2);\n";
+ } elsif ($type =~ m/^(.*?)\s*(:.*)/) {
+ # bitfield
+ print "\t$1 $parameter$2;\n";
+ } else {
+ print "\t" . $type . " " . $parameter . ";\n";
+ }
+ }
+ print "};\n\n";
+
+ print "Members:\n\n";
+ foreach $parameter (@{$args{'parameterlist'}}) {
+ ($parameter =~ /^#/) && next;
+
+ my $parameter_name = $parameter;
+ $parameter_name =~ s/\[.*//;
+
+ ($args{'parameterdescs'}{$parameter_name} ne $undescribed) || next;
+ print "$parameter\n\t";
+ print $args{'parameterdescs'}{$parameter_name} . "\n";
+ }
+ print "\n";
+ output_section_text(@_);
+}
+
+sub output_blockhead_text(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+
+ foreach $section (@{$args{'sectionlist'}}) {
+ print " $section:\n";
+ print " -> ";
+ output_highlight($args{'sections'}{$section});
+ }
+}
+
+## list mode output functions
+
+sub output_function_list(%) {
+ my %args = %{$_[0]};
+
+ print $args{'function'} . "\n";
+}
+
+# output enum in list
+sub output_enum_list(%) {
+ my %args = %{$_[0]};
+ print $args{'enum'} . "\n";
+}
+
+# output typedef in list
+sub output_typedef_list(%) {
+ my %args = %{$_[0]};
+ print $args{'typedef'} . "\n";
+}
+
+# output struct as list
+sub output_struct_list(%) {
+ my %args = %{$_[0]};
+
+ print $args{'struct'} . "\n";
+}
+
+sub output_blockhead_list(%) {
+ my %args = %{$_[0]};
+ my ($parameter, $section);
+
+ foreach $section (@{$args{'sectionlist'}}) {
+ print "DOC: $section\n";
+ }
+}
+
+##
+# generic output function for all types (function, struct/union, typedef, enum);
+# calls the generated, variable output_ function name based on
+# functype and output_mode
+sub output_declaration {
+ no strict 'refs';
+ my $name = shift;
+ my $functype = shift;
+ my $func = "output_${functype}_$output_mode";
+ if (($function_only==0) ||
+ ( $function_only == 1 && defined($function_table{$name})) ||
+ ( $function_only == 2 && !defined($function_table{$name})))
+ {
+ &$func(@_);
+ $section_counter++;
+ }
+}
+
+##
+# generic output function - calls the right one based on current output mode.
+sub output_blockhead {
+ no strict 'refs';
+ my $func = "output_blockhead_" . $output_mode;
+ &$func(@_);
+ $section_counter++;
+}
+
+##
+# takes a declaration (struct, union, enum, typedef) and
+# invokes the right handler. NOT called for functions.
+sub dump_declaration($$) {
+ no strict 'refs';
+ my ($prototype, $file) = @_;
+ my $func = "dump_" . $decl_type;
+ &$func(@_);
+}
+
+sub dump_union($$) {
+ dump_struct(@_);
+}
+
+sub dump_struct($$) {
+ my $x = shift;
+ my $file = shift;
+ my $nested;
+
+ if ($x =~ /(struct|union)\s+(\w+)\s*{(.*)}/) {
+ #my $decl_type = $1;
+ $declaration_name = $2;
+ my $members = $3;
+
+ # ignore embedded structs or unions
+ $members =~ s/({.*})//g;
+ $nested = $1;
+
+ # ignore members marked private:
+ $members =~ s/\/\*\s*private:.*?\/\*\s*public:.*?\*\///gos;
+ $members =~ s/\/\*\s*private:.*//gos;
+ # strip comments:
+ $members =~ s/\/\*.*?\*\///gos;
+ $nested =~ s/\/\*.*?\*\///gos;
+ # strip kmemcheck_bitfield_{begin,end}.*;
+ $members =~ s/kmemcheck_bitfield_.*?;//gos;
+ # strip attributes
+ $members =~ s/__aligned\s*\(\d+\)//gos;
+
+ create_parameterlist($members, ';', $file);
+ check_sections($file, $declaration_name, "struct", $sectcheck, $struct_actual, $nested);
+
+ output_declaration($declaration_name,
+ 'struct',
+ {'struct' => $declaration_name,
+ 'module' => $modulename,
+ 'parameterlist' => \@parameterlist,
+ 'parameterdescs' => \%parameterdescs,
+ 'parametertypes' => \%parametertypes,
+ 'sectionlist' => \@sectionlist,
+ 'sections' => \%sections,
+ 'purpose' => $declaration_purpose,
+ 'type' => $decl_type
+ });
+ }
+ else {
+ print STDERR "Error(${file}:$.): Cannot parse struct or union!\n";
+ ++$errors;
+ }
+}
+
+sub dump_enum($$) {
+ my $x = shift;
+ my $file = shift;
+
+ $x =~ s@/\*.*?\*/@@gos; # strip comments.
+ $x =~ s/^#\s*define\s+.*$//; # strip #define macros inside enums
+
+ if ($x =~ /enum\s+(\w+)\s*{(.*)}/) {
+ $declaration_name = $1;
+ my $members = $2;
+
+ foreach my $arg (split ',', $members) {
+ $arg =~ s/^\s*(\w+).*/$1/;
+ push @parameterlist, $arg;
+ if (!$parameterdescs{$arg}) {
+ $parameterdescs{$arg} = $undescribed;
+ print STDERR "Warning(${file}:$.): Enum value '$arg' ".
+ "not described in enum '$declaration_name'\n";
+ }
+
+ }
+
+ output_declaration($declaration_name,
+ 'enum',
+ {'enum' => $declaration_name,
+ 'module' => $modulename,
+ 'parameterlist' => \@parameterlist,
+ 'parameterdescs' => \%parameterdescs,
+ 'sectionlist' => \@sectionlist,
+ 'sections' => \%sections,
+ 'purpose' => $declaration_purpose
+ });
+ }
+ else {
+ print STDERR "Error(${file}:$.): Cannot parse enum!\n";
+ ++$errors;
+ }
+}
+
+sub dump_typedef($$) {
+ my $x = shift;
+ my $file = shift;
+
+ $x =~ s@/\*.*?\*/@@gos; # strip comments.
+ while (($x =~ /\(*.\)\s*;$/) || ($x =~ /\[*.\]\s*;$/)) {
+ $x =~ s/\(*.\)\s*;$/;/;
+ $x =~ s/\[*.\]\s*;$/;/;
+ }
+
+ if ($x =~ /typedef.*\s+(\w+)\s*;/) {
+ $declaration_name = $1;
+
+ output_declaration($declaration_name,
+ 'typedef',
+ {'typedef' => $declaration_name,
+ 'module' => $modulename,
+ 'sectionlist' => \@sectionlist,
+ 'sections' => \%sections,
+ 'purpose' => $declaration_purpose
+ });
+ }
+ else {
+ print STDERR "Error(${file}:$.): Cannot parse typedef!\n";
+ ++$errors;
+ }
+}
+
+sub save_struct_actual($) {
+ my $actual = shift;
+
+ # strip all spaces from the actual param so that it looks like one string item
+ $actual =~ s/\s*//g;
+ $struct_actual = $struct_actual . $actual . " ";
+}
+
+sub create_parameterlist($$$) {
+ my $args = shift;
+ my $splitter = shift;
+ my $file = shift;
+ my $type;
+ my $param;
+
+ # temporarily replace commas inside function pointer definition
+ while ($args =~ /(\([^\),]+),/) {
+ $args =~ s/(\([^\),]+),/$1#/g;
+ }
+
+ foreach my $arg (split($splitter, $args)) {
+ # strip comments
+ $arg =~ s/\/\*.*\*\///;
+ # strip leading/trailing spaces
+ $arg =~ s/^\s*//;
+ $arg =~ s/\s*$//;
+ $arg =~ s/\s+/ /;
+
+ if ($arg =~ /^#/) {
+ # Treat preprocessor directive as a typeless variable just to fill
+ # corresponding data structures "correctly". Catch it later in
+ # output_* subs.
+ push_parameter($arg, "", $file);
+ } elsif ($arg =~ m/\(.+\)\s*\(/) {
+ # pointer-to-function
+ $arg =~ tr/#/,/;
+ $arg =~ m/[^\(]+\(\*?\s*(\w*)\s*\)/;
+ $param = $1;
+ $type = $arg;
+ $type =~ s/([^\(]+\(\*?)\s*$param/$1/;
+ save_struct_actual($param);
+ push_parameter($param, $type, $file);
+ } elsif ($arg) {
+ $arg =~ s/\s*:\s*/:/g;
+ $arg =~ s/\s*\[/\[/g;
+
+ my @args = split('\s*,\s*', $arg);
+ if ($args[0] =~ m/\*/) {
+ $args[0] =~ s/(\*+)\s*/ $1/;
+ }
+
+ my @first_arg;
+ if ($args[0] =~ /^(.*\s+)(.*?\[.*\].*)$/) {
+ shift @args;
+ push(@first_arg, split('\s+', $1));
+ push(@first_arg, $2);
+ } else {
+ @first_arg = split('\s+', shift @args);
+ }
+
+ unshift(@args, pop @first_arg);
+ $type = join " ", @first_arg;
+
+ foreach $param (@args) {
+ if ($param =~ m/^(\*+)\s*(.*)/) {
+ save_struct_actual($2);
+ push_parameter($2, "$type $1", $file);
+ }
+ elsif ($param =~ m/(.*?):(\d+)/) {
+ if ($type ne "") { # skip unnamed bit-fields
+ save_struct_actual($1);
+ push_parameter($1, "$type:$2", $file)
+ }
+ }
+ else {
+ save_struct_actual($param);
+ push_parameter($param, $type, $file);
+ }
+ }
+ }
+ }
+}
+
+sub push_parameter($$$) {
+ my $param = shift;
+ my $type = shift;
+ my $file = shift;
+
+ if (($anon_struct_union == 1) && ($type eq "") &&
+ ($param eq "}")) {
+ return; # ignore the ending }; from anon. struct/union
+ }
+
+ $anon_struct_union = 0;
+ my $param_name = $param;
+ $param_name =~ s/\[.*//;
+
+ if ($type eq "" && $param =~ /\.\.\.$/)
+ {
+ if (!defined $parameterdescs{$param} || $parameterdescs{$param} eq "") {
+ $parameterdescs{$param} = "variable arguments";
+ }
+ }
+ elsif ($type eq "" && ($param eq "" or $param eq "void"))
+ {
+ $param="void";
+ $parameterdescs{void} = "no arguments";
+ }
+ elsif ($type eq "" && ($param eq "struct" or $param eq "union"))
+ # handle unnamed (anonymous) union or struct:
+ {
+ $type = $param;
+ $param = "{unnamed_" . $param . "}";
+ $parameterdescs{$param} = "anonymous\n";
+ $anon_struct_union = 1;
+ }
+
+ # warn if parameter has no description
+ # (but ignore ones starting with # as these are not parameters
+ # but inline preprocessor statements);
+ # also ignore unnamed structs/unions;
+ if (!$anon_struct_union) {
+ if (!defined $parameterdescs{$param_name} && $param_name !~ /^#/) {
+
+ $parameterdescs{$param_name} = $undescribed;
+
+ if (($type eq 'function') || ($type eq 'enum')) {
+ print STDERR "Warning(${file}:$.): Function parameter ".
+ "or member '$param' not " .
+ "described in '$declaration_name'\n";
+ }
+ print STDERR "Warning(${file}:$.):" .
+ " No description found for parameter '$param'\n";
+ ++$warnings;
+ }
+ }
+
+ $param = xml_escape($param);
+
+ # strip spaces from $param so that it is one continuous string
+ # on @parameterlist;
+ # this fixes a problem where check_sections() cannot find
+ # a parameter like "addr[6 + 2]" because it actually appears
+ # as "addr[6", "+", "2]" on the parameter list;
+ # but it's better to maintain the param string unchanged for output,
+ # so just weaken the string compare in check_sections() to ignore
+ # "[blah" in a parameter string;
+ ###$param =~ s/\s*//g;
+ push @parameterlist, $param;
+ $parametertypes{$param} = $type;
+}
+
+sub check_sections($$$$$$) {
+ my ($file, $decl_name, $decl_type, $sectcheck, $prmscheck, $nested) = @_;
+ my @sects = split ' ', $sectcheck;
+ my @prms = split ' ', $prmscheck;
+ my $err;
+ my ($px, $sx);
+ my $prm_clean; # strip trailing "[array size]" and/or beginning "*"
+
+ foreach $sx (0 .. $#sects) {
+ $err = 1;
+ foreach $px (0 .. $#prms) {
+ $prm_clean = $prms[$px];
+ $prm_clean =~ s/\[.*\]//;
+ $prm_clean =~ s/__attribute__\s*\(\([a-z,_\*\s\(\)]*\)\)//i;
+ # ignore array size in a parameter string;
+ # however, the original param string may contain
+ # spaces, e.g.: addr[6 + 2]
+ # and this appears in @prms as "addr[6" since the
+ # parameter list is split at spaces;
+ # hence just ignore "[..." for the sections check;
+ $prm_clean =~ s/\[.*//;
+
+ ##$prm_clean =~ s/^\**//;
+ if ($prm_clean eq $sects[$sx]) {
+ $err = 0;
+ last;
+ }
+ }
+ if ($err) {
+ if ($decl_type eq "function") {
+ print STDERR "Warning(${file}:$.): " .
+ "Excess function parameter " .
+ "'$sects[$sx]' " .
+ "description in '$decl_name'\n";
+ ++$warnings;
+ } else {
+ if ($nested !~ m/\Q$sects[$sx]\E/) {
+ print STDERR "Warning(${file}:$.): " .
+ "Excess struct/union/enum/typedef member " .
+ "'$sects[$sx]' " .
+ "description in '$decl_name'\n";
+ ++$warnings;
+ }
+ }
+ }
+ }
+}
+
+##
+# takes a function prototype and the name of the current file being
+# processed and spits out all the details stored in the global
+# arrays/hashes.
+sub dump_function($$) {
+ my $prototype = shift;
+ my $file = shift;
+
+ $prototype =~ s/^static +//;
+ $prototype =~ s/^extern +//;
+ $prototype =~ s/^asmlinkage +//;
+ $prototype =~ s/^inline +//;
+ $prototype =~ s/^__inline__ +//;
+ $prototype =~ s/^__inline +//;
+ $prototype =~ s/^__always_inline +//;
+ $prototype =~ s/^noinline +//;
+ $prototype =~ s/__devinit +//;
+ $prototype =~ s/__init +//;
+ $prototype =~ s/__init_or_module +//;
+ $prototype =~ s/__must_check +//;
+ $prototype =~ s/__weak +//;
+ $prototype =~ s/^#\s*define\s+//; #ak added
+ $prototype =~ s/__attribute__\s*\(\([a-z,]*\)\)//;
+
+ # Yes, this truly is vile. We are looking for:
+ # 1. Return type (may be nothing if we're looking at a macro)
+ # 2. Function name
+ # 3. Function parameters.
+ #
+ # All the while we have to watch out for function pointer parameters
+ # (which IIRC is what the two sections are for), C types (these
+ # regexps don't even start to express all the possibilities), and
+ # so on.
+ #
+ # If you mess with these regexps, it's a good idea to check that
+ # the following functions' documentation still comes out right:
+ # - parport_register_device (function pointer parameters)
+ # - atomic_set (macro)
+ # - pci_match_device, __copy_to_user (long return type)
+
+ if ($prototype =~ m/^()([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
+ $prototype =~ m/^(\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
+ $prototype =~ m/^(\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
+ $prototype =~ m/^(\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
+ $prototype =~ m/^(\w+\s+\w+\s*\*+)\s*([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
+ $prototype =~ m/^(\w+\s+\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
+ $prototype =~ m/^(\w+\s+\w+\s+\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\(]*)\)/ ||
+ $prototype =~ m/^()([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+ $prototype =~ m/^(\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+ $prototype =~ m/^(\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+ $prototype =~ m/^(\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+ $prototype =~ m/^(\w+\s+\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+ $prototype =~ m/^(\w+\s+\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+ $prototype =~ m/^(\w+\s+\w+\s+\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+ $prototype =~ m/^(\w+\s+\w+\s+\w+\s+\w+)\s+([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+ $prototype =~ m/^(\w+\s+\w+\s+\w+\s+\w+\s*\*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/ ||
+ $prototype =~ m/^(\w+\s+\w+\s*\*\s*\w+\s*\*\s*)\s*([a-zA-Z0-9_~:]+)\s*\(([^\{]*)\)/) {
+ $return_type = $1;
+ $declaration_name = $2;
+ my $args = $3;
+
+ create_parameterlist($args, ',', $file);
+ } else {
+ print STDERR "Error(${file}:$.): cannot understand prototype: '$prototype'\n";
+ ++$errors;
+ return;
+ }
+
+ my $prms = join " ", @parameterlist;
+ check_sections($file, $declaration_name, "function", $sectcheck, $prms, "");
+
+ output_declaration($declaration_name,
+ 'function',
+ {'function' => $declaration_name,
+ 'module' => $modulename,
+ 'functiontype' => $return_type,
+ 'parameterlist' => \@parameterlist,
+ 'parameterdescs' => \%parameterdescs,
+ 'parametertypes' => \%parametertypes,
+ 'sectionlist' => \@sectionlist,
+ 'sections' => \%sections,
+ 'purpose' => $declaration_purpose
+ });
+}
+
+sub reset_state {
+ $function = "";
+ %constants = ();
+ %parameterdescs = ();
+ %parametertypes = ();
+ @parameterlist = ();
+ %sections = ();
+ @sectionlist = ();
+ $sectcheck = "";
+ $struct_actual = "";
+ $prototype = "";
+
+ $state = 0;
+}
+
+sub tracepoint_munge($) {
+ my $file = shift;
+ my $tracepointname = 0;
+ my $tracepointargs = 0;
+
+ if ($prototype =~ m/TRACE_EVENT\((.*?),/) {
+ $tracepointname = $1;
+ }
+ if ($prototype =~ m/DEFINE_SINGLE_EVENT\((.*?),/) {
+ $tracepointname = $1;
+ }
+ if ($prototype =~ m/DEFINE_EVENT\((.*?),(.*?),/) {
+ $tracepointname = $2;
+ }
+ $tracepointname =~ s/^\s+//; #strip leading whitespace
+ if ($prototype =~ m/TP_PROTO\((.*?)\)/) {
+ $tracepointargs = $1;
+ }
+ if (($tracepointname eq 0) || ($tracepointargs eq 0)) {
+ print STDERR "Warning(${file}:$.): Unrecognized tracepoint format: \n".
+ "$prototype\n";
+ } else {
+ $prototype = "static inline void trace_$tracepointname($tracepointargs)";
+ }
+}
+
+sub syscall_munge() {
+ my $void = 0;
+
+ $prototype =~ s@[\r\n\t]+@ @gos; # strip newlines/CR's/tabs
+## if ($prototype =~ m/SYSCALL_DEFINE0\s*\(\s*(a-zA-Z0-9_)*\s*\)/) {
+ if ($prototype =~ m/SYSCALL_DEFINE0/) {
+ $void = 1;
+## $prototype = "long sys_$1(void)";
+ }
+
+ $prototype =~ s/SYSCALL_DEFINE.*\(/long sys_/; # fix return type & func name
+ if ($prototype =~ m/long (sys_.*?),/) {
+ $prototype =~ s/,/\(/;
+ } elsif ($void) {
+ $prototype =~ s/\)/\(void\)/;
+ }
+
+ # now delete all of the odd-number commas in $prototype
+ # so that arg types & arg names don't have a comma between them
+ my $count = 0;
+ my $len = length($prototype);
+ if ($void) {
+ $len = 0; # skip the for-loop
+ }
+ for (my $ix = 0; $ix < $len; $ix++) {
+ if (substr($prototype, $ix, 1) eq ',') {
+ $count++;
+ if ($count % 2 == 1) {
+ substr($prototype, $ix, 1) = ' ';
+ }
+ }
+ }
+}
+
+sub process_state3_function($$) {
+ my $x = shift;
+ my $file = shift;
+
+ $x =~ s@\/\/.*$@@gos; # strip C99-style comments to end of line
+
+ if ($x =~ m#\s*/\*\s+MACDOC\s*#io || ($x =~ /^#/ && $x !~ /^#\s*define/)) {
+ # do nothing
+ }
+ elsif ($x =~ /([^\{]*)/) {
+ $prototype .= $1;
+ }
+
+ if (($x =~ /\{/) || ($x =~ /\#\s*define/) || ($x =~ /;/)) {
+ $prototype =~ s@/\*.*?\*/@@gos; # strip comments.
+ $prototype =~ s@[\r\n]+@ @gos; # strip newlines/cr's.
+ $prototype =~ s@^\s+@@gos; # strip leading spaces
+ if ($prototype =~ /SYSCALL_DEFINE/) {
+ syscall_munge();
+ }
+ if ($prototype =~ /TRACE_EVENT/ || $prototype =~ /DEFINE_EVENT/ ||
+ $prototype =~ /DEFINE_SINGLE_EVENT/)
+ {
+ tracepoint_munge($file);
+ }
+ dump_function($prototype, $file);
+ reset_state();
+ }
+}
+
+sub process_state3_type($$) {
+ my $x = shift;
+ my $file = shift;
+
+ $x =~ s@[\r\n]+@ @gos; # strip newlines/cr's.
+ $x =~ s@^\s+@@gos; # strip leading spaces
+ $x =~ s@\s+$@@gos; # strip trailing spaces
+ $x =~ s@\/\/.*$@@gos; # strip C99-style comments to end of line
+
+ if ($x =~ /^#/) {
+ # To distinguish preprocessor directive from regular declaration later.
+ $x .= ";";
+ }
+
+ while (1) {
+ if ( $x =~ /([^{};]*)([{};])(.*)/ ) {
+ $prototype .= $1 . $2;
+ ($2 eq '{') && $brcount++;
+ ($2 eq '}') && $brcount--;
+ if (($2 eq ';') && ($brcount == 0)) {
+ dump_declaration($prototype, $file);
+ reset_state();
+ last;
+ }
+ $x = $3;
+ } else {
+ $prototype .= $x;
+ last;
+ }
+ }
+}
+
+# xml_escape: replace <, >, and & in the text stream;
+#
+# however, formatting controls that are generated internally/locally in the
+# kernel-doc script are not escaped here; instead, they begin life like
+# $blankline_html (4 of '\' followed by a mnemonic + ':'), then these strings
+# are converted to their mnemonic-expected output, without the 4 * '\' & ':',
+# just before actual output; (this is done by local_unescape())
+sub xml_escape($) {
+ my $text = shift;
+ if (($output_mode eq "text") || ($output_mode eq "man")) {
+ return $text;
+ }
+ $text =~ s/\&/\\\\\\amp;/g;
+ $text =~ s/\</\\\\\\lt;/g;
+ $text =~ s/\>/\\\\\\gt;/g;
+ return $text;
+}
+
+# convert local escape strings to html
+# local escape strings look like: '\\\\menmonic:' (that's 4 backslashes)
+sub local_unescape($) {
+ my $text = shift;
+ if (($output_mode eq "text") || ($output_mode eq "man")) {
+ return $text;
+ }
+ $text =~ s/\\\\\\\\lt:/</g;
+ $text =~ s/\\\\\\\\gt:/>/g;
+ return $text;
+}
+
+sub process_file($) {
+ my $file;
+ my $identifier;
+ my $func;
+ my $descr;
+ my $in_purpose = 0;
+ my $initial_section_counter = $section_counter;
+
+ if (defined($ENV{'SRCTREE'})) {
+ $file = "$ENV{'SRCTREE'}" . "/" . "@_";
+ }
+ else {
+ $file = "@_";
+ }
+ if (defined($source_map{$file})) {
+ $file = $source_map{$file};
+ }
+
+ if (!open(IN,"<$file")) {
+ print STDERR "Error: Cannot open file $file\n";
+ ++$errors;
+ return;
+ }
+
+ $. = 1;
+
+ $section_counter = 0;
+ while (<IN>) {
+ if ($state == 0) {
+ if (/$doc_start/o) {
+ $state = 1; # next line is always the function name
+ $in_doc_sect = 0;
+ }
+ } elsif ($state == 1) { # this line is the function name (always)
+ if (/$doc_block/o) {
+ $state = 4;
+ $contents = "";
+ if ( $1 eq "" ) {
+ $section = $section_intro;
+ } else {
+ $section = $1;
+ }
+ }
+ elsif (/$doc_decl/o) {
+ $identifier = $1;
+ if (/\s*([\w\s]+?)\s*-/) {
+ $identifier = $1;
+ }
+
+ $state = 2;
+ if (/-(.*)/) {
+ # strip leading/trailing/multiple spaces
+ $descr= $1;
+ $descr =~ s/^\s*//;
+ $descr =~ s/\s*$//;
+ $descr =~ s/\s+/ /;
+ $declaration_purpose = xml_escape($descr);
+ $in_purpose = 1;
+ } else {
+ $declaration_purpose = "";
+ }
+
+ if (($declaration_purpose eq "") && $verbose) {
+ print STDERR "Warning(${file}:$.): missing initial short description on line:\n";
+ print STDERR $_;
+ ++$warnings;
+ }
+
+ if ($identifier =~ m/^struct/) {
+ $decl_type = 'struct';
+ } elsif ($identifier =~ m/^union/) {
+ $decl_type = 'union';
+ } elsif ($identifier =~ m/^enum/) {
+ $decl_type = 'enum';
+ } elsif ($identifier =~ m/^typedef/) {
+ $decl_type = 'typedef';
+ } else {
+ $decl_type = 'function';
+ }
+
+ if ($verbose) {
+ print STDERR "Info(${file}:$.): Scanning doc for $identifier\n";
+ }
+ } else {
+ print STDERR "Warning(${file}:$.): Cannot understand $_ on line $.",
+ " - I thought it was a doc line\n";
+ ++$warnings;
+ $state = 0;
+ }
+ } elsif ($state == 2) { # look for head: lines, and include content
+ if (/$doc_sect/o) {
+ $newsection = $1;
+ $newcontents = $2;
+
+ if (($contents ne "") && ($contents ne "\n")) {
+ if (!$in_doc_sect && $verbose) {
+ print STDERR "Warning(${file}:$.): contents before sections\n";
+ ++$warnings;
+ }
+ dump_section($file, $section, xml_escape($contents));
+ $section = $section_default;
+ }
+
+ $in_doc_sect = 1;
+ $in_purpose = 0;
+ $contents = $newcontents;
+ if ($contents ne "") {
+ while ((substr($contents, 0, 1) eq " ") ||
+ substr($contents, 0, 1) eq "\t") {
+ $contents = substr($contents, 1);
+ }
+ $contents .= "\n";
+ }
+ $section = $newsection;
+ } elsif (/$doc_end/) {
+
+ if (($contents ne "") && ($contents ne "\n")) {
+ dump_section($file, $section, xml_escape($contents));
+ $section = $section_default;
+ $contents = "";
+ }
+ # look for doc_com + <text> + doc_end:
+ if ($_ =~ m'\s*\*\s*[a-zA-Z_0-9:\.]+\*/') {
+ print STDERR "Warning(${file}:$.): suspicious ending line: $_";
+ ++$warnings;
+ }
+
+ $prototype = "";
+ $state = 3;
+ $brcount = 0;
+# print STDERR "end of doc comment, looking for prototype\n";
+ } elsif (/$doc_content/) {
+ # miguel-style comment kludge, look for blank lines after
+ # @parameter line to signify start of description
+ if ($1 eq "") {
+ if ($section =~ m/^@/ || $section eq $section_context) {
+ dump_section($file, $section, xml_escape($contents));
+ $section = $section_default;
+ $contents = "";
+ } else {
+ $contents .= "\n";
+ }
+ $in_purpose = 0;
+ } elsif ($in_purpose == 1) {
+ # Continued declaration purpose
+ chomp($declaration_purpose);
+ $declaration_purpose .= " " . xml_escape($1);
+ } elsif ($section =~ m/^Example/) {
+ $_ =~ s/^\s*\*//;
+ $contents .= $_;
+ } else {
+ $contents .= $1 . "\n";
+ }
+ } else {
+ # i dont know - bad line? ignore.
+ print STDERR "Warning(${file}:$.): bad line: $_";
+ ++$warnings;
+ }
+ } elsif ($state == 3) { # scanning for function '{' (end of prototype)
+ if ($decl_type eq 'function') {
+ process_state3_function($_, $file);
+ } else {
+ process_state3_type($_, $file);
+ }
+ } elsif ($state == 4) {
+ # Documentation block
+ if (/$doc_block/) {
+ dump_doc_section($file, $section, xml_escape($contents));
+ $contents = "";
+ $function = "";
+ %constants = ();
+ %parameterdescs = ();
+ %parametertypes = ();
+ @parameterlist = ();
+ %sections = ();
+ @sectionlist = ();
+ $prototype = "";
+ if ( $1 eq "" ) {
+ $section = $section_intro;
+ } else {
+ $section = $1;
+ }
+ }
+ elsif (/$doc_end/)
+ {
+ dump_doc_section($file, $section, xml_escape($contents));
+ $contents = "";
+ $function = "";
+ %constants = ();
+ %parameterdescs = ();
+ %parametertypes = ();
+ @parameterlist = ();
+ %sections = ();
+ @sectionlist = ();
+ $prototype = "";
+ $state = 0;
+ }
+ elsif (/$doc_content/)
+ {
+ if ( $1 eq "" )
+ {
+ $contents .= $blankline;
+ }
+ else
+ {
+ $contents .= $1 . "\n";
+ }
+ }
+ }
+ }
+ if ($initial_section_counter == $section_counter) {
+ print STDERR "Warning(${file}): no structured comments found\n";
+ if ($output_mode eq "xml") {
+ # The template wants at least one RefEntry here; make one.
+ print "<refentry>\n";
+ print " <refnamediv>\n";
+ print " <refname>\n";
+ print " ${file}\n";
+ print " </refname>\n";
+ print " <refpurpose>\n";
+ print " Document generation inconsistency\n";
+ print " </refpurpose>\n";
+ print " </refnamediv>\n";
+ print " <refsect1>\n";
+ print " <title>\n";
+ print " Oops\n";
+ print " </title>\n";
+ print " <warning>\n";
+ print " <para>\n";
+ print " The template for this document tried to insert\n";
+ print " the structured comment from the file\n";
+ print " <filename>${file}</filename> at this point,\n";
+ print " but none was found.\n";
+ print " This dummy section is inserted to allow\n";
+ print " generation to continue.\n";
+ print " </para>\n";
+ print " </warning>\n";
+ print " </refsect1>\n";
+ print "</refentry>\n";
+ }
+ }
+}
+
+
+$kernelversion = get_kernel_version();
+
+# generate a sequence of code that will splice in highlighting information
+# using the s// operator.
+foreach my $pattern (keys %highlights) {
+# print STDERR "scanning pattern:$pattern, highlight:($highlights{$pattern})\n";
+ $dohighlight .= "\$contents =~ s:$pattern:$highlights{$pattern}:gs;\n";
+}
+
+# Read the file that maps relative names to absolute names for
+# separate source and object directories and for shadow trees.
+if (open(SOURCE_MAP, "<.tmp_filelist.txt")) {
+ my ($relname, $absname);
+ while(<SOURCE_MAP>) {
+ chop();
+ ($relname, $absname) = (split())[0..1];
+ $relname =~ s:^/+::;
+ $source_map{$relname} = $absname;
+ }
+ close(SOURCE_MAP);
+}
+
+foreach (@ARGV) {
+ chomp;
+ process_file($_);
+}
+if ($verbose && $errors) {
+ print STDERR "$errors errors\n";
+}
+if ($verbose && $warnings) {
+ print STDERR "$warnings warnings\n";
+}
+
+exit($errors);
Sets the subject prefix. Normally empty but it can be RFC for
RFC patches, or RESEND if you are being ignored.
+Series-name: name
+ Sets the name of the series. You don't need to have a name, and
+ patman does not yet use it, but it is convenient to put the branch
+ name here to help you keep track of multiple upstreaming efforts.
+
Cover-letter:
This is the patch set title
blah blah
if len(problems) != error_count + warning_count:
print "Internal error: some problems lost"
for item in problems:
- print GetWarningMsg(col, item['type'], item['file'],
- item['line'], item['msg'])
+ print GetWarningMsg(col, item['type'],
+ item.get('file', '<unknown>'),
+ item.get('line', 0), item['msg'])
#print stdout
if error_count != 0 or warning_count != 0:
str = 'checkpatch.pl found %d error(s), %d warning(s)' % (
Return:
Number of patches that exist on top of the branch
"""
- pipe = [['git', 'log', '--oneline', '@{upstream}..'],
+ pipe = [['git', 'log', '--no-color', '--oneline', '@{upstream}..'],
['wc', '-l']]
stdout = command.RunPipe(pipe, capture=True, oneline=True)
patch_count = int(stdout)
start: Commit to start from: 0=HEAD, 1=next one, etc.
count: Number of commits to list
"""
- pipe = [['git', 'log', '--reverse', 'HEAD~%d' % start, '-n%d' % count]]
+ pipe = [['git', 'log', '--no-color', '--reverse', 'HEAD~%d' % start,
+ '-n%d' % count]]
stdout = command.RunPipe(pipe, capture=True)
series = Series()
ps = PatchStream(series, is_log=True)
import terminal
# Series-xxx tags that we understand
-valid_series = ['to', 'cc', 'version', 'changes', 'prefix', 'notes'];
+valid_series = ['to', 'cc', 'version', 'changes', 'prefix', 'notes', 'name'];
class Series(dict):
"""Holds information about a patch series, including all tags.
self[name] = value
else:
raise ValueError("In %s: line '%s': Unknown 'Series-%s': valid "
- "options are %s" % (self.commit.hash, line, name,
+ "options are %s" % (commit.hash, line, name,
', '.join(valid_series)))
def AddCommit(self, commit):
projects / karo-tx-uboot.git / commitdiff