ARM: remove obsolete at91rm9200

The big "ARM: remove broken boards" series deletes all boards using
obsolete arm920t/at91rm9200 arch code. Therefore we can safely remove
this code now.

Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>

diff --git a/arch/arm/cpu/arm920t/at91rm9200/Makefile b/arch/arm/cpu/arm920t/at91rm9200/Makefile
deleted file mode 100644 (file)
index 7530e6a..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/Makefile
+++ /dev/null
@@ -1,56 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB    = $(obj)lib$(SOC).o
-
-SOBJS  += lowlevel_init.o
-
-COBJS  += bcm5221.o
-COBJS  += dm9161.o
-COBJS  += ether.o
-COBJS  += i2c.o
-COBJS-$(CONFIG_KS8721_PHY)     += ks8721.o
-COBJS  += lxt972.o
-COBJS  += reset.o
-COBJS  += spi.o
-COBJS  += timer.o
-COBJS  += usb.o
-
-SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c) $(COBJS-y:.o=.c)
-OBJS   := $(addprefix $(obj),$(SOBJS) $(COBJS) $(COBJS-y))
-
-all:   $(obj).depend $(LIB)
-
-$(LIB):        $(OBJS)
-       $(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################

diff --git a/arch/arm/cpu/arm920t/at91rm9200/bcm5221.c b/arch/arm/cpu/arm920t/at91rm9200/bcm5221.c
deleted file mode 100644 (file)
index 8de3cba..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/bcm5221.c
+++ /dev/null
@@ -1,232 +0,0 @@
-/*
- * Broadcom BCM5221 Ethernet PHY
- *
- * (C) Copyright 2005 REA Elektronik GmbH <www.rea.de>
- * Anders Larsen <alarsen@rea.de>
- *
- * (C) Copyright 2003
- * Author : Hamid Ikdoumi (Atmel)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <at91rm9200_net.h>
-#include <net.h>
-#ifdef CONFIG_DRIVER_ETHER
-
-#include <bcm5221.h>
-
-#if defined(CONFIG_CMD_NET)
-
-/*
- * Name:
- *     bcm5221_IsPhyConnected
- * Description:
- *     Reads the 2 PHY ID registers
- * Arguments:
- *     p_mac - pointer to AT91S_EMAC struct
- * Return value:
- *     TRUE - if id read successfully
- *     FALSE- if error
- */
-unsigned int bcm5221_IsPhyConnected (AT91PS_EMAC p_mac)
-{
-       unsigned short Id1, Id2;
-
-       at91rm9200_EmacEnableMDIO (p_mac);
-       at91rm9200_EmacReadPhy (p_mac, BCM5221_PHYID1, &Id1);
-       at91rm9200_EmacReadPhy (p_mac, BCM5221_PHYID2, &Id2);
-       at91rm9200_EmacDisableMDIO (p_mac);
-
-       if ((Id1 == (BCM5221_PHYID1_OUI >> 6)) &&
-               ((Id2 >> 10) == (BCM5221_PHYID1_OUI & BCM5221_LSB_MASK)))
-               return TRUE;
-
-       return FALSE;
-}
-
-/*
- * Name:
- *     bcm5221_GetLinkSpeed
- * Description:
- *     Link parallel detection status of MAC is checked and set in the
- *     MAC configuration registers
- * Arguments:
- *     p_mac - pointer to MAC
- * Return value:
- *     TRUE - if link status set succesfully
- *     FALSE - if link status not set
- */
-unsigned char bcm5221_GetLinkSpeed (AT91PS_EMAC p_mac)
-{
-       unsigned short stat1, stat2;
-
-       if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMSR, &stat1))
-               return FALSE;
-
-       if (!(stat1 & BCM5221_LINK_STATUS))     /* link status up? */
-               return FALSE;
-
-       if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_ACSR, &stat2))
-               return FALSE;
-
-       if ((stat1 & BCM5221_100BASE_TX_FD) && (stat2 & BCM5221_100) && (stat2 & BCM5221_FDX)) {
-               /*set Emac for 100BaseTX and Full Duplex  */
-               p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
-               return TRUE;
-       }
-
-       if ((stat1 & BCM5221_10BASE_T_FD) && !(stat2 & BCM5221_100) && (stat2 & BCM5221_FDX)) {
-               /*set MII for 10BaseT and Full Duplex  */
-               p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-                               ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-                               | AT91C_EMAC_FD;
-               return TRUE;
-       }
-
-       if ((stat1 & BCM5221_100BASE_TX_HD) && (stat2 & BCM5221_100) && !(stat2 & BCM5221_FDX)) {
-               /*set MII for 100BaseTX and Half Duplex  */
-               p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-                               ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-                               | AT91C_EMAC_SPD;
-               return TRUE;
-       }
-
-       if ((stat1 & BCM5221_10BASE_T_HD) && !(stat2 & BCM5221_100) && !(stat2 & BCM5221_FDX)) {
-               /*set MII for 10BaseT and Half Duplex  */
-               p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
-               return TRUE;
-       }
-       return FALSE;
-}
-
-
-/*
- * Name:
- *     bcm5221_InitPhy
- * Description:
- *     MAC starts checking its link by using parallel detection and
- *     Autonegotiation and the same is set in the MAC configuration registers
- * Arguments:
- *     p_mac - pointer to struct AT91S_EMAC
- * Return value:
- *     TRUE - if link status set succesfully
- *     FALSE - if link status not set
- */
-unsigned char bcm5221_InitPhy (AT91PS_EMAC p_mac)
-{
-       unsigned char ret = TRUE;
-       unsigned short IntValue;
-
-       at91rm9200_EmacEnableMDIO (p_mac);
-
-       if (!bcm5221_GetLinkSpeed (p_mac)) {
-               /* Try another time */
-               ret = bcm5221_GetLinkSpeed (p_mac);
-       }
-
-       /* Disable PHY Interrupts */
-       at91rm9200_EmacReadPhy (p_mac, BCM5221_INTR, &IntValue);
-       /* clear FDX LED and INTR Enable */
-       IntValue &= ~(BCM5221_FDX_LED | BCM5221_INTR_ENABLE);
-       /* set FDX, SPD, Link, INTR masks */
-       IntValue |= (BCM5221_FDX_MASK  | BCM5221_SPD_MASK |
-                    BCM5221_LINK_MASK | BCM5221_INTR_MASK);
-       at91rm9200_EmacWritePhy (p_mac, BCM5221_INTR, &IntValue);
-       at91rm9200_EmacDisableMDIO (p_mac);
-
-       return (ret);
-}
-
-
-/*
- * Name:
- *     bcm5221_AutoNegotiate
- * Description:
- *     MAC Autonegotiates with the partner status of same is set in the
- *     MAC configuration registers
- * Arguments:
- *     dev - pointer to struct net_device
- * Return value:
- *     TRUE - if link status set successfully
- *     FALSE - if link status not set
- */
-unsigned char bcm5221_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
-{
-       unsigned short value;
-       unsigned short PhyAnar;
-       unsigned short PhyAnalpar;
-
-       /* Set bcm5221 control register */
-       if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMCR, &value))
-               return FALSE;
-       value &= ~BCM5221_AUTONEG;      /* remove autonegotiation enable */
-       value |=  BCM5221_ISOLATE;      /* Electrically isolate PHY */
-       if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value))
-               return FALSE;
-
-       /* Set the Auto_negotiation Advertisement Register */
-       /* MII advertising for 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3 */
-       PhyAnar = BCM5221_TX_FDX | BCM5221_TX_HDX |
-                 BCM5221_10_FDX | BCM5221_10_HDX | BCM5221_AN_IEEE_802_3;
-       if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_ANAR, &PhyAnar))
-               return FALSE;
-
-       /* Read the Control Register     */
-       if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_BMCR, &value))
-               return FALSE;
-
-       value |= BCM5221_SPEED_SELECT | BCM5221_AUTONEG | BCM5221_DUPLEX_MODE;
-       if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value))
-               return FALSE;
-       /* Restart Auto_negotiation  */
-       value |= BCM5221_RESTART_AUTONEG;
-       value &= ~BCM5221_ISOLATE;
-       if (!at91rm9200_EmacWritePhy (p_mac, BCM5221_BMCR, &value))
-               return FALSE;
-
-       /*check AutoNegotiate complete */
-       udelay (10000);
-       at91rm9200_EmacReadPhy (p_mac, BCM5221_BMSR, &value);
-       if (!(value & BCM5221_AUTONEG_COMP))
-               return FALSE;
-
-       /* Get the AutoNeg Link partner base page */
-       if (!at91rm9200_EmacReadPhy (p_mac, BCM5221_ANLPAR, &PhyAnalpar))
-               return FALSE;
-
-       if ((PhyAnar & BCM5221_TX_FDX) && (PhyAnalpar & BCM5221_TX_FDX)) {
-               /*set MII for 100BaseTX and Full Duplex  */
-               p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
-               return TRUE;
-       }
-
-       if ((PhyAnar & BCM5221_10_FDX) && (PhyAnalpar & BCM5221_10_FDX)) {
-               /*set MII for 10BaseT and Full Duplex  */
-               p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-                               ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-                               | AT91C_EMAC_FD;
-               return TRUE;
-       }
-       return FALSE;
-}
-
-#endif
-
-#endif /* CONFIG_DRIVER_ETHER */

diff --git a/arch/arm/cpu/arm920t/at91rm9200/dm9161.c b/arch/arm/cpu/arm920t/at91rm9200/dm9161.c
deleted file mode 100644 (file)
index 6d4384f..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/dm9161.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * (C) Copyright 2003
- * Author : Hamid Ikdoumi (Atmel)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <at91rm9200_net.h>
-#include <net.h>
-#ifdef CONFIG_DRIVER_ETHER
-#include <dm9161.h>
-
-#if defined(CONFIG_CMD_NET)
-
-/*
- * Name:
- *     dm9161_IsPhyConnected
- * Description:
- *     Reads the 2 PHY ID registers
- * Arguments:
- *     p_mac - pointer to AT91S_EMAC struct
- * Return value:
- *     TRUE - if id read successfully
- *     FALSE- if error
- */
-unsigned int dm9161_IsPhyConnected (AT91PS_EMAC p_mac)
-{
-       unsigned short Id1, Id2;
-
-       at91rm9200_EmacEnableMDIO (p_mac);
-       at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID1, &Id1);
-       at91rm9200_EmacReadPhy (p_mac, DM9161_PHYID2, &Id2);
-       at91rm9200_EmacDisableMDIO (p_mac);
-
-       if ((Id1 == (DM9161_PHYID1_OUI >> 6)) &&
-               ((Id2 >> 10) == (DM9161_PHYID1_OUI & DM9161_LSB_MASK)))
-               return TRUE;
-
-       return FALSE;
-}
-
-/*
- * Name:
- *     dm9161_GetLinkSpeed
- * Description:
- *     Link parallel detection status of MAC is checked and set in the
- *     MAC configuration registers
- * Arguments:
- *     p_mac - pointer to MAC
- * Return value:
- *     TRUE - if link status set succesfully
- *     FALSE - if link status not set
- */
-UCHAR dm9161_GetLinkSpeed (AT91PS_EMAC p_mac)
-{
-       unsigned short stat1, stat2;
-
-       if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &stat1))
-               return FALSE;
-
-       if (!(stat1 & DM9161_LINK_STATUS))      /* link status up? */
-               return FALSE;
-
-       if (!at91rm9200_EmacReadPhy (p_mac, DM9161_DSCSR, &stat2))
-               return FALSE;
-
-       if ((stat1 & DM9161_100BASE_TX_FD) && (stat2 & DM9161_100FDX)) {
-               /*set Emac for 100BaseTX and Full Duplex  */
-               p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
-               return TRUE;
-       }
-
-       if ((stat1 & DM9161_10BASE_T_FD) && (stat2 & DM9161_10FDX)) {
-               /*set MII for 10BaseT and Full Duplex  */
-               p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-                               ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-                               | AT91C_EMAC_FD;
-               return TRUE;
-       }
-
-       if ((stat1 & DM9161_100BASE_TX_HD) && (stat2 & DM9161_100HDX)) {
-               /*set MII for 100BaseTX and Half Duplex  */
-               p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-                               ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-                               | AT91C_EMAC_SPD;
-               return TRUE;
-       }
-
-       if ((stat1 & DM9161_10BASE_T_HD) && (stat2 & DM9161_10HDX)) {
-               /*set MII for 10BaseT and Half Duplex  */
-               p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
-               return TRUE;
-       }
-       return FALSE;
-}
-
-
-/*
- * Name:
- *     dm9161_InitPhy
- * Description:
- *     MAC starts checking its link by using parallel detection and
- *     Autonegotiation and the same is set in the MAC configuration registers
- * Arguments:
- *     p_mac - pointer to struct AT91S_EMAC
- * Return value:
- *     TRUE - if link status set succesfully
- *     FALSE - if link status not set
- */
-UCHAR dm9161_InitPhy (AT91PS_EMAC p_mac)
-{
-       UCHAR ret = TRUE;
-       unsigned short IntValue;
-
-       at91rm9200_EmacEnableMDIO (p_mac);
-
-       if (!dm9161_GetLinkSpeed (p_mac)) {
-               /* Try another time */
-               ret = dm9161_GetLinkSpeed (p_mac);
-       }
-
-       /* Disable PHY Interrupts */
-       at91rm9200_EmacReadPhy (p_mac, DM9161_MDINTR, &IntValue);
-       /* set FDX, SPD, Link, INTR masks */
-       IntValue |= (DM9161_FDX_MASK | DM9161_SPD_MASK |
-                       DM9161_LINK_MASK | DM9161_INTR_MASK);
-       at91rm9200_EmacWritePhy (p_mac, DM9161_MDINTR, &IntValue);
-       at91rm9200_EmacDisableMDIO (p_mac);
-
-       return (ret);
-}
-
-
-/*
- * Name:
- *     dm9161_AutoNegotiate
- * Description:
- *     MAC Autonegotiates with the partner status of same is set in the
- *     MAC configuration registers
- * Arguments:
- *     dev - pointer to struct net_device
- * Return value:
- *     TRUE - if link status set successfully
- *     FALSE - if link status not set
- */
-UCHAR dm9161_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
-{
-       unsigned short value;
-       unsigned short PhyAnar;
-       unsigned short PhyAnalpar;
-
-       /* Set dm9161 control register */
-       if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
-               return FALSE;
-       value &= ~DM9161_AUTONEG;       /* remove autonegotiation enable */
-       value |= DM9161_ISOLATE;        /* Electrically isolate PHY */
-       if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
-               return FALSE;
-
-       /* Set the Auto_negotiation Advertisement Register      */
-       /* MII advertising for Next page, 100BaseTxFD and HD,   */
-       /* 10BaseTFD and HD, IEEE 802.3 */
-       PhyAnar = DM9161_NP | DM9161_TX_FDX | DM9161_TX_HDX |
-                       DM9161_10_FDX | DM9161_10_HDX | DM9161_AN_IEEE_802_3;
-       if (!at91rm9200_EmacWritePhy (p_mac, DM9161_ANAR, &PhyAnar))
-               return FALSE;
-
-       /* Read the Control Register     */
-       if (!at91rm9200_EmacReadPhy (p_mac, DM9161_BMCR, &value))
-               return FALSE;
-
-       value |= DM9161_SPEED_SELECT | DM9161_AUTONEG | DM9161_DUPLEX_MODE;
-       if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
-               return FALSE;
-       /* Restart Auto_negotiation  */
-       value |= DM9161_RESTART_AUTONEG;
-       value &= ~DM9161_ISOLATE;
-       if (!at91rm9200_EmacWritePhy (p_mac, DM9161_BMCR, &value))
-               return FALSE;
-
-       /*check AutoNegotiate complete */
-       udelay (10000);
-       at91rm9200_EmacReadPhy (p_mac, DM9161_BMSR, &value);
-       if (!(value & DM9161_AUTONEG_COMP))
-               return FALSE;
-
-       /* Get the AutoNeg Link partner base page */
-       if (!at91rm9200_EmacReadPhy (p_mac, DM9161_ANLPAR, &PhyAnalpar))
-               return FALSE;
-
-       if ((PhyAnar & DM9161_TX_FDX) && (PhyAnalpar & DM9161_TX_FDX)) {
-               /*set MII for 100BaseTX and Full Duplex  */
-               p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
-               return TRUE;
-       }
-
-       if ((PhyAnar & DM9161_10_FDX) && (PhyAnalpar & DM9161_10_FDX)) {
-               /*set MII for 10BaseT and Full Duplex  */
-               p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-                               ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-                               | AT91C_EMAC_FD;
-               return TRUE;
-       }
-       return FALSE;
-}
-
-#endif
-
-#endif /* CONFIG_DRIVER_ETHER */

diff --git a/arch/arm/cpu/arm920t/at91rm9200/ether.c b/arch/arm/cpu/arm920t/at91rm9200/ether.c
deleted file mode 100644 (file)
index d7135c5..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/ether.c
+++ /dev/null
@@ -1,316 +0,0 @@
-/*
- * (C) Copyright 2003
- * Author : Hamid Ikdoumi (Atmel)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <at91rm9200_net.h>
-#include <net.h>
-#include <miiphy.h>
-#include <asm/mach-types.h>
-
-/* ----- Ethernet Buffer definitions ----- */
-
-typedef struct {
-       unsigned long addr, size;
-} rbf_t;
-
-#define RBF_ADDR      0xfffffffc
-#define RBF_OWNER     (1<<0)
-#define RBF_WRAP      (1<<1)
-#define RBF_BROADCAST (1<<31)
-#define RBF_MULTICAST (1<<30)
-#define RBF_UNICAST   (1<<29)
-#define RBF_EXTERNAL  (1<<28)
-#define RBF_UNKNOWN   (1<<27)
-#define RBF_SIZE      0x07ff
-#define RBF_LOCAL4    (1<<26)
-#define RBF_LOCAL3    (1<<25)
-#define RBF_LOCAL2    (1<<24)
-#define RBF_LOCAL1    (1<<23)
-
-#define RBF_FRAMEMAX 64
-#define RBF_FRAMELEN 0x600
-
-#ifdef CONFIG_DRIVER_ETHER
-
-#if defined(CONFIG_CMD_NET)
-
-/* alignment as per Errata #11 (64 bytes) is insufficient! */
-rbf_t rbfdt[RBF_FRAMEMAX] __attribute__((aligned(512)));
-rbf_t *rbfp;
-
-unsigned char rbf_framebuf[RBF_FRAMEMAX][RBF_FRAMELEN]
-       __attribute__((aligned(4)));
-
-/* structure to interface the PHY */
-AT91S_PhyOps PhyOps;
-
-AT91PS_EMAC p_mac;
-
-/*********** EMAC Phy layer Management functions *************************/
-/*
- * Name:
- *     at91rm9200_EmacEnableMDIO
- * Description:
- *     Enables the MDIO bit in MAC control register
- * Arguments:
- *     p_mac - pointer to struct AT91S_EMAC
- * Return value:
- *     none
- */
-void at91rm9200_EmacEnableMDIO (AT91PS_EMAC p_mac)
-{
-       /* Mac CTRL reg set for MDIO enable */
-       p_mac->EMAC_CTL |= AT91C_EMAC_MPE;      /* Management port enable */
-}
-
-/*
- * Name:
- *     at91rm9200_EmacDisableMDIO
- * Description:
- *     Disables the MDIO bit in MAC control register
- * Arguments:
- *     p_mac - pointer to struct AT91S_EMAC
- * Return value:
- *     none
- */
-void at91rm9200_EmacDisableMDIO (AT91PS_EMAC p_mac)
-{
-       /* Mac CTRL reg set for MDIO disable */
-       p_mac->EMAC_CTL &= ~AT91C_EMAC_MPE;     /* Management port disable */
-}
-
-
-/*
- * Name:
- *     at91rm9200_EmacReadPhy
- * Description:
- *     Reads data from the PHY register
- * Arguments:
- *     dev - pointer to struct net_device
- *     RegisterAddress - unsigned char
- *     pInput - pointer to value read from register
- * Return value:
- *     TRUE - if data read successfully
- */
-UCHAR at91rm9200_EmacReadPhy (AT91PS_EMAC p_mac,
-                                    unsigned char RegisterAddress,
-                                    unsigned short *pInput)
-{
-       p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
-                         (AT91C_EMAC_RW_R) |
-                         (RegisterAddress << 18) |
-                         (AT91C_EMAC_CODE_802_3);
-
-       udelay (10000);
-
-       *pInput = (unsigned short) p_mac->EMAC_MAN;
-
-       return TRUE;
-}
-
-
-/*
- * Name:
- *     at91rm9200_EmacWritePhy
- * Description:
- *     Writes data to the PHY register
- * Arguments:
- *     dev - pointer to struct net_device
- *     RegisterAddress - unsigned char
- *     pOutput - pointer to value to be written in the register
- * Return value:
- *     TRUE - if data read successfully
- */
-UCHAR at91rm9200_EmacWritePhy (AT91PS_EMAC p_mac,
-                                     unsigned char RegisterAddress,
-                                     unsigned short *pOutput)
-{
-       p_mac->EMAC_MAN = (AT91C_EMAC_HIGH & ~AT91C_EMAC_LOW) |
-                       AT91C_EMAC_CODE_802_3 | AT91C_EMAC_RW_W |
-                       (RegisterAddress << 18) | *pOutput;
-
-       udelay (10000);
-
-       return TRUE;
-}
-
-int eth_init (bd_t * bd)
-{
-       int ret;
-       int i;
-       uchar enetaddr[6];
-
-       p_mac = AT91C_BASE_EMAC;
-
-       /* PIO Disable Register */
-       *AT91C_PIOA_PDR = AT91C_PA16_EMDIO | AT91C_PA15_EMDC | AT91C_PA14_ERXER |
-                         AT91C_PA13_ERX1 | AT91C_PA12_ERX0 | AT91C_PA11_ECRS_ECRSDV |
-                         AT91C_PA10_ETX1 | AT91C_PA9_ETX0 | AT91C_PA8_ETXEN |
-                         AT91C_PA7_ETXCK_EREFCK;
-
-#ifdef CONFIG_AT91C_USE_RMII
-       *AT91C_PIOB_PDR = AT91C_PB19_ERXCK;
-       *AT91C_PIOB_BSR = AT91C_PB19_ERXCK;
-#else
-       *AT91C_PIOB_PDR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL | AT91C_PB17_ERXDV |
-                         AT91C_PB16_ERX3 | AT91C_PB15_ERX2 | AT91C_PB14_ETXER |
-                         AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
-
-       /* Select B Register */
-       *AT91C_PIOB_BSR = AT91C_PB19_ERXCK | AT91C_PB18_ECOL |
-                         AT91C_PB17_ERXDV | AT91C_PB16_ERX3 | AT91C_PB15_ERX2 |
-                         AT91C_PB14_ETXER | AT91C_PB13_ETX3 | AT91C_PB12_ETX2;
-#endif
-
-       *AT91C_PMC_PCER = 1 << AT91C_ID_EMAC;   /* Peripheral Clock Enable Register */
-
-       p_mac->EMAC_CFG |= AT91C_EMAC_CSR;      /* Clear statistics */
-
-       /* Init Ethernet buffers */
-       for (i = 0; i < RBF_FRAMEMAX; i++) {
-               rbfdt[i].addr = (unsigned long)rbf_framebuf[i];
-               rbfdt[i].size = 0;
-       }
-       rbfdt[RBF_FRAMEMAX - 1].addr |= RBF_WRAP;
-       rbfp = &rbfdt[0];
-
-       eth_getenv_enetaddr("ethaddr", enetaddr);
-
-       /* The CSB337 originally used a version of the MicroMonitor bootloader
-        * which saved Ethernet addresses in the "wrong" order.  Operating
-        * systems (like Linux) know this, and apply a workaround.  Replicate
-        * that MicroMonitor behavior so we avoid needing to make such OS code
-        * care about which bootloader was used.
-        */
-       if (machine_is_csb337()) {
-               p_mac->EMAC_SA2H = (enetaddr[0] <<  8) | (enetaddr[1]);
-               p_mac->EMAC_SA2L = (enetaddr[2] << 24) | (enetaddr[3] << 16)
-                                | (enetaddr[4] <<  8) | (enetaddr[5]);
-       } else {
-               p_mac->EMAC_SA2L = (enetaddr[3] << 24) | (enetaddr[2] << 16)
-                                | (enetaddr[1] <<  8) | (enetaddr[0]);
-               p_mac->EMAC_SA2H = (enetaddr[5] <<  8) | (enetaddr[4]);
-       }
-
-       p_mac->EMAC_RBQP = (long) (&rbfdt[0]);
-       p_mac->EMAC_RSR &= ~(AT91C_EMAC_RSR_OVR | AT91C_EMAC_REC | AT91C_EMAC_BNA);
-
-       p_mac->EMAC_CFG = (p_mac->EMAC_CFG | AT91C_EMAC_CAF | AT91C_EMAC_NBC)
-                       & ~AT91C_EMAC_CLK;
-
-#ifdef CONFIG_AT91C_USE_RMII
-       p_mac->EMAC_CFG |= AT91C_EMAC_RMII;
-#endif
-
-#if (AT91C_MASTER_CLOCK > 40000000)
-       /* MDIO clock must not exceed 2.5 MHz, so enable MCK divider */
-       p_mac->EMAC_CFG |= AT91C_EMAC_CLK_HCLK_64;
-#endif
-
-       p_mac->EMAC_CTL |= AT91C_EMAC_TE | AT91C_EMAC_RE;
-
-       at91rm9200_GetPhyInterface (& PhyOps);
-
-       if (!PhyOps.IsPhyConnected (p_mac))
-               printf ("PHY not connected!!\n\r");
-
-       /* MII management start from here */
-       if (!(p_mac->EMAC_SR & AT91C_EMAC_LINK)) {
-               if (!(ret = PhyOps.Init (p_mac))) {
-                       printf ("MAC: error during MII initialization\n");
-                       return 0;
-               }
-       } else {
-               printf ("No link\n\r");
-               return 0;
-       }
-
-       return 0;
-}
-
-int eth_send (volatile void *packet, int length)
-{
-       while (!(p_mac->EMAC_TSR & AT91C_EMAC_BNQ));
-       p_mac->EMAC_TAR = (long) packet;
-       p_mac->EMAC_TCR = length;
-       while (p_mac->EMAC_TCR & 0x7ff);
-       p_mac->EMAC_TSR |= AT91C_EMAC_COMP;
-       return 0;
-}
-
-int eth_rx (void)
-{
-       int size;
-
-       if (!(rbfp->addr & RBF_OWNER))
-               return 0;
-
-       size = rbfp->size & RBF_SIZE;
-       NetReceive ((volatile uchar *) (rbfp->addr & RBF_ADDR), size);
-
-       rbfp->addr &= ~RBF_OWNER;
-       if (rbfp->addr & RBF_WRAP)
-               rbfp = &rbfdt[0];
-       else
-               rbfp++;
-
-       p_mac->EMAC_RSR |= AT91C_EMAC_REC;
-
-       return size;
-}
-
-void eth_halt (void)
-{
-};
-
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-int  at91rm9200_miiphy_read(const char *devname, unsigned char addr,
-               unsigned char reg, unsigned short * value)
-{
-       at91rm9200_EmacEnableMDIO (p_mac);
-       at91rm9200_EmacReadPhy (p_mac, reg, value);
-       at91rm9200_EmacDisableMDIO (p_mac);
-       return 0;
-}
-
-int  at91rm9200_miiphy_write(const char *devname, unsigned char addr,
-               unsigned char reg, unsigned short value)
-{
-       at91rm9200_EmacEnableMDIO (p_mac);
-       at91rm9200_EmacWritePhy (p_mac, reg, &value);
-       at91rm9200_EmacDisableMDIO (p_mac);
-       return 0;
-}
-
-#endif
-
-int at91rm9200_miiphy_initialize(bd_t *bis)
-{
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
-       miiphy_register("at91rm9200phy", at91rm9200_miiphy_read, at91rm9200_miiphy_write);
-#endif
-       return 0;
-}
-
-#endif
-
-#endif /* CONFIG_DRIVER_ETHER */

diff --git a/arch/arm/cpu/arm920t/at91rm9200/i2c.c b/arch/arm/cpu/arm920t/at91rm9200/i2c.c
deleted file mode 100644 (file)
index 1711088..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/i2c.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- *  i2c Support for Atmel's AT91RM9200 Two-Wire Interface
- *
- *  (c) Rick Bronson
- *
- *  Borrowed heavily from original work by:
- *  Copyright (c) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
- *
- *  Modified to work with u-boot by (C) 2004 Gary Jennejohn garyj@denx.de
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- *
-*/
-#include <common.h>
-
-#ifdef CONFIG_HARD_I2C
-
-#include <i2c.h>
-#include <asm/io.h>
-#include <asm/arch/hardware.h>
-
-#include <at91rm9200_i2c.h>
-
-/* define DEBUG */
-
-/*
- * Poll the i2c status register until the specified bit is set.
- * Returns 0 if timed out (100 msec)
- */
-static short at91_poll_status(AT91PS_TWI twi, unsigned long bit) {
-       int loop_cntr = 10000;
-       do {
-               udelay(10);
-       } while (!(twi->TWI_SR & bit) && (--loop_cntr > 0));
-
-       return (loop_cntr > 0);
-}
-
-/*
- * Generic i2c master transfer entrypoint
- *
- * rw == 1 means that this is a read
- */
-static int
-at91_xfer(unsigned char chip, unsigned int addr, int alen,
-                                               unsigned char *buffer, int len, int rw)
-{
-       AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE;
-       int length;
-       unsigned char *buf;
-       /* Set the TWI Master Mode Register */
-       twi->TWI_MMR = (chip << 16) | (alen << 8)
-               | ((rw == 1) ? AT91C_TWI_MREAD : 0);
-
-       /* Set TWI Internal Address Register with first messages data field */
-       if (alen > 0)
-               twi->TWI_IADR = addr;
-
-       length = len;
-       buf = buffer;
-       if (length && buf) {    /* sanity check */
-               if (rw) {
-                       twi->TWI_CR = AT91C_TWI_START;
-                       while (length--) {
-                               if (!length)
-                                       twi->TWI_CR = AT91C_TWI_STOP;
-                               /* Wait until transfer is finished */
-                               if (!at91_poll_status(twi, AT91C_TWI_RXRDY)) {
-                                       debug ("at91_i2c: timeout 1\n");
-                                       return 1;
-                               }
-                               *buf++ = twi->TWI_RHR;
-                       }
-                       if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) {
-                               debug ("at91_i2c: timeout 2\n");
-                               return 1;
-                       }
-               } else {
-                       twi->TWI_CR = AT91C_TWI_START;
-                       while (length--) {
-                               twi->TWI_THR = *buf++;
-                               if (!length)
-                                       twi->TWI_CR = AT91C_TWI_STOP;
-                               if (!at91_poll_status(twi, AT91C_TWI_TXRDY)) {
-                                       debug ("at91_i2c: timeout 3\n");
-                                       return 1;
-                               }
-                       }
-                       /* Wait until transfer is finished */
-                       if (!at91_poll_status(twi, AT91C_TWI_TXCOMP)) {
-                               debug ("at91_i2c: timeout 4\n");
-                               return 1;
-                       }
-               }
-       }
-       return 0;
-}
-
-int
-i2c_probe(unsigned char chip)
-{
-       unsigned char buffer[1];
-
-       return at91_xfer(chip, 0, 0, buffer, 1, 1);
-}
-
-int
-i2c_read (unsigned char chip, unsigned int addr, int alen,
-         unsigned char *buffer, int len)
-{
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
-       /* we only allow one address byte */
-       if (alen > 1)
-               return 1;
-       /* XXX assume an ATMEL AT24C16 */
-       if (alen == 1) {
-#if 0 /* EEPROM code already sets this correctly */
-               chip |= (addr >> 8) & 0xff;
-#endif
-               addr = addr & 0xff;
-       }
-#endif
-       return at91_xfer(chip, addr, alen, buffer, len, 1);
-}
-
-int
-i2c_write(unsigned char chip, unsigned int addr, int alen,
-         unsigned char *buffer, int len)
-{
-#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
-       int i;
-       unsigned char *buf;
-
-       /* we only allow one address byte */
-       if (alen > 1)
-               return 1;
-       /* XXX assume an ATMEL AT24C16 */
-       if (alen == 1) {
-               buf = buffer;
-               /* do single byte writes */
-               for (i = 0; i < len; i++) {
-#if 0 /* EEPROM code already sets this correctly */
-                       chip |= (addr >> 8) & 0xff;
-#endif
-                       addr = addr & 0xff;
-                       if (at91_xfer(chip, addr, alen, buf++, 1, 0))
-                               return 1;
-                       addr++;
-               }
-               return 0;
-       }
-#endif
-       return at91_xfer(chip, addr, alen, buffer, len, 0);
-}
-
-/*
- * Main initialization routine
- */
-void
-i2c_init(int speed, int slaveaddr)
-{
-       AT91PS_TWI twi = (AT91PS_TWI) AT91_TWI_BASE;
-
-       *AT91C_PIOA_PDR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
-       *AT91C_PIOA_ASR = AT91C_PA25_TWD | AT91C_PA26_TWCK;
-       *AT91C_PIOA_MDER = AT91C_PA25_TWD | AT91C_PA26_TWCK;
-       *AT91C_PMC_PCER = 1 << AT91C_ID_TWI;            /* enable peripheral clock */
-
-       twi->TWI_IDR = 0x3ff;                           /* Disable all interrupts */
-       twi->TWI_CR = AT91C_TWI_SWRST;                  /* Reset peripheral */
-       twi->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS; /* Set Master mode */
-
-       /* Here, CKDIV = 1 and CHDIV=CLDIV  ==> CLDIV = CHDIV = 1/4*((Fmclk/FTWI) -6) */
-       twi->TWI_CWGR = AT91C_TWI_CKDIV1 | AT91C_TWI_CLDIV3 | (AT91C_TWI_CLDIV3 << 8);
-
-       debug ("Found AT91 i2c\n");
-       return;
-}
-
-#endif /* CONFIG_HARD_I2C */

diff --git a/arch/arm/cpu/arm920t/at91rm9200/ks8721.c b/arch/arm/cpu/arm920t/at91rm9200/ks8721.c
deleted file mode 100644 (file)
index 9fe3793..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/ks8721.c
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * (C) Copyright 2006
- * Author : Eric Benard (Eukrea Electromatique)
- * based on dm9161.c which is :
- * (C) Copyright 2003
- * Author : Hamid Ikdoumi (Atmel)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <at91rm9200_net.h>
-#include <net.h>
-#include <ks8721.h>
-
-#ifdef CONFIG_DRIVER_ETHER
-
-#if defined(CONFIG_CMD_NET)
-
-/*
- * Name:
- *     ks8721_isphyconnected
- * Description:
- *     Reads the 2 PHY ID registers
- * Arguments:
- *     p_mac - pointer to AT91S_EMAC struct
- * Return value:
- *     1 - if id read successfully
- *     0 - if error
- */
-unsigned int ks8721_isphyconnected(AT91PS_EMAC p_mac)
-{
-       unsigned short id1, id2;
-
-       at91rm9200_EmacEnableMDIO(p_mac);
-       at91rm9200_EmacReadPhy(p_mac,
-               CONFIG_PHY_ADDRESS | KS8721_PHYID1, &id1);
-       at91rm9200_EmacReadPhy(p_mac,
-               CONFIG_PHY_ADDRESS | KS8721_PHYID2, &id2);
-       at91rm9200_EmacDisableMDIO(p_mac);
-
-       if ((id1 == (KS8721_PHYID_OUI >> 6)) &&
-               ((id2 >> 10) == (KS8721_PHYID_OUI & KS8721_LSB_MASK))) {
-               if ((id2 & KS8721_MODELMASK) == KS8721BL_MODEL)
-                       printf("Micrel KS8721bL PHY detected : ");
-               else
-                       printf("Unknown Micrel PHY detected : ");
-               return 1;
-       }
-       return 0;
-}
-
-/*
- * Name:
- *     ks8721_getlinkspeed
- * Description:
- *     Link parallel detection status of MAC is checked and set in the
- *     MAC configuration registers
- * Arguments:
- *     p_mac - pointer to MAC
- * Return value:
- *     1 - if link status set succesfully
- *     0 - if link status not set
- */
-unsigned char ks8721_getlinkspeed(AT91PS_EMAC p_mac)
-{
-       unsigned short stat1;
-
-       if (!at91rm9200_EmacReadPhy(p_mac, KS8721_BMSR, &stat1))
-               return 0;
-
-       if (!(stat1 & KS8721_LINK_STATUS)) {
-               /* link status up? */
-               printf("Link Down !\n");
-               return 0;
-       }
-
-       if (stat1 & KS8721_100BASE_TX_FD) {
-               /* set Emac for 100BaseTX and Full Duplex */
-               printf("100BT FD\n");
-               p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
-               return 1;
-       }
-
-       if (stat1 & KS8721_10BASE_T_FD) {
-               /* set MII for 10BaseT and Full Duplex */
-               printf("10BT FD\n");
-               p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-                               ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-                               | AT91C_EMAC_FD;
-               return 1;
-       }
-
-       if (stat1 & KS8721_100BASE_T4_HD) {
-               /* set MII for 100BaseTX and Half Duplex */
-               printf("100BT HD\n");
-               p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-                               ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-                               | AT91C_EMAC_SPD;
-               return 1;
-       }
-
-       if (stat1 & KS8721_10BASE_T_HD) {
-               /* set MII for 10BaseT and Half Duplex */
-               printf("10BT HD\n");
-               p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
-               return 1;
-       }
-       return 0;
-}
-
-/*
- * Name:
- *     ks8721_initphy
- * Description:
- *     MAC starts checking its link by using parallel detection and
- *     Autonegotiation and the same is set in the MAC configuration registers
- * Arguments:
- *     p_mac - pointer to struct AT91S_EMAC
- * Return value:
- *     1 - if link status set succesfully
- *     0 - if link status not set
- */
-unsigned char ks8721_initphy(AT91PS_EMAC p_mac)
-{
-       unsigned char ret = 1;
-       unsigned short intvalue;
-
-       at91rm9200_EmacEnableMDIO(p_mac);
-
-       /* Try another time */
-       if (!ks8721_getlinkspeed(p_mac))
-               ret = ks8721_getlinkspeed(p_mac);
-
-       /* Disable PHY Interrupts */
-       intvalue = 0;
-       at91rm9200_EmacWritePhy(p_mac,
-               CONFIG_PHY_ADDRESS | KS8721_MDINTR, &intvalue);
-       at91rm9200_EmacDisableMDIO(p_mac);
-
-       return ret;
-}
-
-/*
- * Name:
- *     ks8721_autonegotiate
- * Description:
- *     MAC Autonegotiates with the partner status of same is set in the
- *     MAC configuration registers
- * Arguments:
- *     dev - pointer to struct net_device
- * Return value:
- *     1 - if link status set successfully
- *     0 - if link status not set
- */
-unsigned char ks8721_autonegotiate(AT91PS_EMAC p_mac, int *status)
-{
-       unsigned short value;
-       unsigned short phyanar;
-       unsigned short phyanalpar;
-
-       /* Set ks8721 control register */
-       if (!at91rm9200_EmacReadPhy(p_mac,
-               CONFIG_PHY_ADDRESS | KS8721_BMCR, &value))
-               return 0;
-
-       /* remove autonegotiation enable */
-       value &= ~KS8721_AUTONEG;
-       /* Electrically isolate PHY */
-       value |= KS8721_ISOLATE;
-       if (!at91rm9200_EmacWritePhy(p_mac,
-               CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) {
-               return 0;
-       }
-       /*
-        * Set the Auto_negotiation Advertisement Register
-        * MII advertising for Next page, 100BaseTxFD and HD,
-        * 10BaseTFD and HD, IEEE 802.3
-        */
-       phyanar = KS8721_NP | KS8721_TX_FDX | KS8721_TX_HDX |
-                 KS8721_10_FDX | KS8721_10_HDX | KS8721_AN_IEEE_802_3;
-       if (!at91rm9200_EmacWritePhy(p_mac,
-               CONFIG_PHY_ADDRESS | KS8721_ANAR, &phyanar)) {
-               return 0;
-       }
-       /* Read the Control Register */
-       if (!at91rm9200_EmacReadPhy(p_mac,
-               CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) {
-               return 0;
-       }
-       value |= KS8721_SPEED_SELECT | KS8721_AUTONEG | KS8721_DUPLEX_MODE;
-       if (!at91rm9200_EmacWritePhy(p_mac,
-               CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) {
-               return 0;
-       }
-       /* Restart Auto_negotiation */
-       value |= KS8721_RESTART_AUTONEG;
-       value &= ~KS8721_ISOLATE;
-       if (!at91rm9200_EmacWritePhy(p_mac,
-               CONFIG_PHY_ADDRESS | KS8721_BMCR, &value)) {
-               return 0;
-       }
-       /* Check AutoNegotiate complete */
-       udelay(10000);
-       at91rm9200_EmacReadPhy(p_mac,
-               CONFIG_PHY_ADDRESS | KS8721_BMSR, &value);
-       if (!(value & KS8721_AUTONEG_COMP))
-               return 0;
-
-       /* Get the AutoNeg Link partner base page */
-       if (!at91rm9200_EmacReadPhy(p_mac,
-               CONFIG_PHY_ADDRESS | KS8721_ANLPAR, &phyanalpar)) {
-               return 0;
-       }
-
-       if ((phyanar & KS8721_TX_FDX) && (phyanalpar & KS8721_TX_FDX)) {
-               /* Set MII for 100BaseTX and Full Duplex */
-               p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
-               return 1;
-       }
-
-       if ((phyanar & KS8721_10_FDX) && (phyanalpar & KS8721_10_FDX)) {
-               /* Set MII for 10BaseT and Full Duplex */
-               p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-                               ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-                               | AT91C_EMAC_FD;
-               return 1;
-       }
-       return 0;
-}
-
-#endif /* CONFIG_CMD_NET */
-
-#endif /* CONFIG_DRIVER_ETHER */

diff --git a/arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S b/arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S
deleted file mode 100644 (file)
index 2e7160f..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/lowlevel_init.S
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * Memory Setup stuff - taken from blob memsetup.S
- *
- * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
- *                    Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- *
- * Modified for the at91rm9200dk board by
- * (C) Copyright 2004
- * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <config.h>
-#include <version.h>
-
-#ifndef CONFIG_SKIP_LOWLEVEL_INIT
-/*
- * some parameters for the board
- *
- * This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
- * turn is based on the boot.bin code from ATMEL
- *
- */
-#include <asm/arch/AT91RM9200.h>
-
-_MTEXT_BASE:
-#undef START_FROM_MEM
-#ifdef START_FROM_MEM
-       .word   CONFIG_SYS_TEXT_BASE-PHYS_FLASH_1
-#else
-       .word   CONFIG_SYS_TEXT_BASE
-#endif
-
-.globl lowlevel_init
-lowlevel_init:
-       /* Get the CKGR Base Address */
-       ldr     r1, =AT91C_BASE_CKGR
-       /* Main oscillator Enable register */
-#ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
-       ldr     r0, =0x0000FF01         /* Enable main oscillator,  OSCOUNT = 0xFF */
-#else
-       ldr     r0, =0x0000FF00         /* Disable main oscillator, OSCOUNT = 0xFF */
-#endif
-       str     r0, [r1, #AT91C_CKGR_MOR]
-       /* Add loop to compensate Main Oscillator startup time */
-       ldr     r0, =0x00000010
-LoopOsc:
-       subs    r0, r0, #1
-       bhi     LoopOsc
-
-       /* memory control configuration */
-       /* this isn't very elegant, but  what the heck */
-       ldr     r0, =SMRDATA
-       ldr     r1, _MTEXT_BASE
-       sub     r0, r0, r1
-       add     r2, r0, #80
-0:
-       /* the address */
-       ldr     r1, [r0], #4
-       /* the value */
-       ldr     r3, [r0], #4
-       str     r3, [r1]
-       cmp     r2, r0
-       bne     0b
-       /* delay - this is all done by guess */
-       ldr     r0, =0x00010000
-       /* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
-1:
-       subs    r0, r0, #1
-       bhi     1b
-       ldr     r0, =SMRDATA1
-       ldr     r1, _MTEXT_BASE
-       sub     r0, r0, r1
-       add     r2, r0, #176
-2:
-       /* the address */
-       ldr     r1, [r0], #4
-       /* the value */
-       ldr     r3, [r0], #4
-       str     r3, [r1]
-       cmp     r2, r0
-       bne     2b
-
-       /* switch from FastBus to Asynchronous clock mode */
-       mrc     p15, 0, r0, c1, c0, 0
-       orr     r0, r0, #0xC0000000     @ set bit 31 (iA) and 30 (nF)
-       mcr     p15, 0, r0, c1, c0, 0
-
-       /* everything is fine now */
-       mov     pc, lr
-
-       .ltorg
-
-SMRDATA:
-       .word AT91C_EBI_CFGR
-       .word CONFIG_SYS_EBI_CFGR_VAL
-       .word AT91C_SMC_CSR0
-       .word CONFIG_SYS_SMC_CSR0_VAL
-       .word AT91C_PLLAR
-       .word CONFIG_SYS_PLLAR_VAL
-       .word AT91C_PLLBR
-       .word CONFIG_SYS_PLLBR_VAL
-       .word AT91C_MCKR
-       .word CONFIG_SYS_MCKR_VAL
-       /* here there's a delay */
-SMRDATA1:
-       .word AT91C_PIOC_ASR
-       .word CONFIG_SYS_PIOC_ASR_VAL
-       .word AT91C_PIOC_BSR
-       .word CONFIG_SYS_PIOC_BSR_VAL
-       .word AT91C_PIOC_PDR
-       .word CONFIG_SYS_PIOC_PDR_VAL
-       .word AT91C_EBI_CSA
-       .word CONFIG_SYS_EBI_CSA_VAL
-       .word AT91C_SDRC_CR
-       .word CONFIG_SYS_SDRC_CR_VAL
-       .word AT91C_SDRC_MR
-       .word CONFIG_SYS_SDRC_MR_VAL
-       .word CONFIG_SYS_SDRAM
-       .word CONFIG_SYS_SDRAM_VAL
-       .word AT91C_SDRC_MR
-       .word CONFIG_SYS_SDRC_MR_VAL1
-       .word CONFIG_SYS_SDRAM
-       .word CONFIG_SYS_SDRAM_VAL
-       .word CONFIG_SYS_SDRAM
-       .word CONFIG_SYS_SDRAM_VAL
-       .word CONFIG_SYS_SDRAM
-       .word CONFIG_SYS_SDRAM_VAL
-       .word CONFIG_SYS_SDRAM
-       .word CONFIG_SYS_SDRAM_VAL
-       .word CONFIG_SYS_SDRAM
-       .word CONFIG_SYS_SDRAM_VAL
-       .word CONFIG_SYS_SDRAM
-       .word CONFIG_SYS_SDRAM_VAL
-       .word CONFIG_SYS_SDRAM
-       .word CONFIG_SYS_SDRAM_VAL
-       .word CONFIG_SYS_SDRAM
-       .word CONFIG_SYS_SDRAM_VAL
-       .word AT91C_SDRC_MR
-       .word CONFIG_SYS_SDRC_MR_VAL2
-       .word CONFIG_SYS_SDRAM1
-       .word CONFIG_SYS_SDRAM_VAL
-       .word AT91C_SDRC_TR
-       .word CONFIG_SYS_SDRC_TR_VAL
-       .word CONFIG_SYS_SDRAM
-       .word CONFIG_SYS_SDRAM_VAL
-       .word AT91C_SDRC_MR
-       .word CONFIG_SYS_SDRC_MR_VAL3
-       .word CONFIG_SYS_SDRAM
-       .word CONFIG_SYS_SDRAM_VAL
-       /* SMRDATA1 is 176 bytes long */
-#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

diff --git a/arch/arm/cpu/arm920t/at91rm9200/lxt972.c b/arch/arm/cpu/arm920t/at91rm9200/lxt972.c
deleted file mode 100644 (file)
index f02cfdd..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/lxt972.c
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- *
- * (C) Copyright 2003
- * Author : Hamid Ikdoumi (Atmel)
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * Adapted for KwikByte KB920x board: 22APR2005
- */
-
-#include <common.h>
-#include <at91rm9200_net.h>
-#include <net.h>
-#include <miiphy.h>
-#include <lxt971a.h>
-
-#ifdef CONFIG_DRIVER_ETHER
-
-#if defined(CONFIG_CMD_NET)
-
-/*
- * Name:
- *     lxt972_IsPhyConnected
- * Description:
- *     Reads the 2 PHY ID registers
- * Arguments:
- *     p_mac - pointer to AT91S_EMAC struct
- * Return value:
- *     TRUE - if id read successfully
- *     FALSE- if error
- */
-unsigned int lxt972_IsPhyConnected (AT91PS_EMAC p_mac)
-{
-       unsigned short Id1, Id2;
-
-       at91rm9200_EmacEnableMDIO (p_mac);
-       at91rm9200_EmacReadPhy(p_mac, MII_PHYSID1, &Id1);
-       at91rm9200_EmacReadPhy(p_mac, MII_PHYSID2, &Id2);
-       at91rm9200_EmacDisableMDIO (p_mac);
-
-       if ((Id1 == (0x0013)) && ((Id2  & 0xFFF0) == 0x78E0))
-               return TRUE;
-
-       return FALSE;
-}
-
-/*
- * Name:
- *     lxt972_GetLinkSpeed
- * Description:
- *     Link parallel detection status of MAC is checked and set in the
- *     MAC configuration registers
- * Arguments:
- *     p_mac - pointer to MAC
- * Return value:
- *     TRUE - if link status set succesfully
- *     FALSE - if link status not set
- */
-UCHAR lxt972_GetLinkSpeed (AT91PS_EMAC p_mac)
-{
-       unsigned short stat1;
-
-       if (!at91rm9200_EmacReadPhy (p_mac, PHY_LXT971_STAT2, &stat1))
-               return FALSE;
-
-       if (!(stat1 & PHY_LXT971_STAT2_LINK))   /* link status up? */
-               return FALSE;
-
-       if (stat1 & PHY_LXT971_STAT2_100BTX) {
-
-               if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
-
-                       /*set Emac for 100BaseTX and Full Duplex  */
-                       p_mac->EMAC_CFG |= AT91C_EMAC_SPD | AT91C_EMAC_FD;
-               } else {
-
-                       /*set Emac for 100BaseTX and Half Duplex  */
-                       p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-                                       ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-                                       | AT91C_EMAC_SPD;
-               }
-
-               return TRUE;
-
-       } else {
-
-               if (stat1 & PHY_LXT971_STAT2_DUPLEX_MODE) {
-
-                       /*set MII for 10BaseT and Full Duplex  */
-                       p_mac->EMAC_CFG = (p_mac->EMAC_CFG &
-                                       ~(AT91C_EMAC_SPD | AT91C_EMAC_FD))
-                                       | AT91C_EMAC_FD;
-               } else {
-
-                       /*set MII for 10BaseT and Half Duplex  */
-                       p_mac->EMAC_CFG &= ~(AT91C_EMAC_SPD | AT91C_EMAC_FD);
-               }
-
-               return TRUE;
-       }
-
-       return FALSE;
-}
-
-
-/*
- * Name:
- *     lxt972_InitPhy
- * Description:
- *     MAC starts checking its link by using parallel detection and
- *     Autonegotiation and the same is set in the MAC configuration registers
- * Arguments:
- *     p_mac - pointer to struct AT91S_EMAC
- * Return value:
- *     TRUE - if link status set succesfully
- *     FALSE - if link status not set
- */
-UCHAR lxt972_InitPhy (AT91PS_EMAC p_mac)
-{
-       UCHAR ret = TRUE;
-
-       at91rm9200_EmacEnableMDIO (p_mac);
-
-       if (!lxt972_GetLinkSpeed (p_mac)) {
-               /* Try another time */
-               ret = lxt972_GetLinkSpeed (p_mac);
-       }
-
-       /* Disable PHY Interrupts */
-       at91rm9200_EmacWritePhy (p_mac, PHY_LXT971_INT_ENABLE, 0);
-
-       at91rm9200_EmacDisableMDIO (p_mac);
-
-       return (ret);
-}
-
-
-/*
- * Name:
- *     lxt972_AutoNegotiate
- * Description:
- *     MAC Autonegotiates with the partner status of same is set in the
- *     MAC configuration registers
- * Arguments:
- *     dev - pointer to struct net_device
- * Return value:
- *     TRUE - if link status set successfully
- *     FALSE - if link status not set
- */
-UCHAR lxt972_AutoNegotiate (AT91PS_EMAC p_mac, int *status)
-{
-       unsigned short value;
-
-       /* Set lxt972 control register */
-       if (!at91rm9200_EmacReadPhy (p_mac, MII_BMCR, &value))
-               return FALSE;
-
-       /* Restart Auto_negotiation  */
-       value |= BMCR_ANRESTART;
-       if (!at91rm9200_EmacWritePhy (p_mac, MII_BMCR, &value))
-               return FALSE;
-
-       /*check AutoNegotiate complete */
-       udelay (10000);
-       at91rm9200_EmacReadPhy(p_mac, MII_BMSR, &value);
-       if (!(value & BMSR_ANEGCOMPLETE))
-               return FALSE;
-
-       return (lxt972_GetLinkSpeed (p_mac));
-}
-
-#endif
-
-#endif /* CONFIG_DRIVER_ETHER */

diff --git a/arch/arm/cpu/arm920t/at91rm9200/reset.c b/arch/arm/cpu/arm920t/at91rm9200/reset.c
deleted file mode 100644 (file)
index 945ea2c..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/reset.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * (C) Copyright 2002
- * Lineo, Inc. <www.lineo.com>
- * Bernhard Kuhn <bkuhn@lineo.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/arch/hardware.h>
-
-void board_reset(void) __attribute__((__weak__));
-
-/*
- * Reset the cpu by setting up the watchdog timer and let him time out
- * or toggle a GPIO pin on the AT91RM9200DK board
- */
-void reset_cpu (ulong ignored)
-{
-
-#if defined(CONFIG_AT91RM9200_USART)
-       /*shutdown the console to avoid strange chars during reset */
-       serial_exit();
-#endif
-
-       if (board_reset)
-               board_reset();
-
-       /* this is the way Linux does it */
-
-       /* FIXME:
-        * These defines should be moved into
-        * include/asm-arm/arch-at91rm9200/AT91RM9200.h
-        * as soon as the whitespace fix gets applied.
-        */
-       #define AT91C_ST_RSTEN (0x1 << 16)
-       #define AT91C_ST_EXTEN (0x1 << 17)
-       #define AT91C_ST_WDRST (0x1 <<  0)
-       #define ST_WDMR *((unsigned long *)0xfffffd08)  /* watchdog mode register */
-       #define ST_CR *((unsigned long *)0xfffffd00)    /* system clock control register */
-
-       ST_WDMR = AT91C_ST_RSTEN | AT91C_ST_EXTEN | 1 ;
-       ST_CR = AT91C_ST_WDRST;
-
-       while (1);
-       /* Never reached */
-}

diff --git a/arch/arm/cpu/arm920t/at91rm9200/spi.c b/arch/arm/cpu/arm920t/at91rm9200/spi.c
deleted file mode 100644 (file)
index c70efc6..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/spi.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/* Driver for ATMEL DataFlash support
- * Author : Hamid Ikdoumi (Atmel)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- *
- */
-
-#include <config.h>
-#include <common.h>
-#include <asm/hardware.h>
-
-#ifdef CONFIG_HAS_DATAFLASH
-#include <dataflash.h>
-
-#define AT91C_SPI_CLK  10000000        /* Max Value = 10MHz to be compliant to
-                                       the Continuous Array Read function */
-
-/* AC Characteristics */
-/* DLYBS = tCSS = 250ns min and DLYBCT = tCSH = 250ns */
-#define DATAFLASH_TCSS (0xC << 16)
-#define DATAFLASH_TCHS (0x1 << 24)
-
-#define AT91C_TIMEOUT_WRDY             200000
-#define AT91C_SPI_PCS0_SERIAL_DATAFLASH        0xE     /* Chip Select 0: NPCS0%1110 */
-#define AT91C_SPI_PCS3_DATAFLASH_CARD  0x7     /* Chip Select 3: NPCS3%0111 */
-
-/*-------------------------------------------------------------------*/
-/*     SPI DataFlash Init                                           */
-/*-------------------------------------------------------------------*/
-void AT91F_SpiInit(void)
-{
-       /* Configure PIOs */
-       AT91C_BASE_PIOA->PIO_ASR =
-               AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI |
-               AT91C_PA5_NPCS2 | AT91C_PA6_NPCS3 | AT91C_PA0_MISO |
-               AT91C_PA2_SPCK;
-       AT91C_BASE_PIOA->PIO_PDR =
-               AT91C_PA3_NPCS0 | AT91C_PA4_NPCS1 | AT91C_PA1_MOSI |
-               AT91C_PA5_NPCS2 | AT91C_PA6_NPCS3 | AT91C_PA0_MISO |
-               AT91C_PA2_SPCK;
-       /* Enable CLock */
-       AT91C_BASE_PMC->PMC_PCER = 1 << AT91C_ID_SPI;
-
-       /* Reset the SPI */
-       AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SWRST;
-
-       /* Configure SPI in Master Mode with No CS selected !!! */
-       AT91C_BASE_SPI->SPI_MR =
-               AT91C_SPI_MSTR | AT91C_SPI_MODFDIS | AT91C_SPI_PCS;
-
-       /* Configure CS0 and CS3 */
-       *(AT91C_SPI_CSR + 0) =
-               AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) |
-               (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) |
-               ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
-
-       *(AT91C_SPI_CSR + 3) =
-               AT91C_SPI_CPOL | (AT91C_SPI_DLYBS & DATAFLASH_TCSS) |
-               (AT91C_SPI_DLYBCT & DATAFLASH_TCHS) |
-               ((AT91C_MASTER_CLOCK / (2*AT91C_SPI_CLK)) << 8);
-}
-
-void AT91F_SpiEnable(int cs)
-{
-       switch(cs) {
-       case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
-               AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
-               AT91C_BASE_SPI->SPI_MR |=
-                       ((AT91C_SPI_PCS0_SERIAL_DATAFLASH<<16) &
-                               AT91C_SPI_PCS);
-               break;
-       case 3: /* Configure SPI CS3 for Serial DataFlash Card */
-               /* Set up PIO SDC_TYPE to switch on DataFlash Card */
-               /* and not MMC/SDCard */
-               AT91C_BASE_PIOB->PIO_PER =
-                       AT91C_PIO_PB7;  /* Set in PIO mode */
-               AT91C_BASE_PIOB->PIO_OER =
-                       AT91C_PIO_PB7;  /* Configure in output */
-               /* Clear Output */
-               AT91C_BASE_PIOB->PIO_CODR = AT91C_PIO_PB7;
-               /* Configure PCS */
-               AT91C_BASE_SPI->SPI_MR &= 0xFFF0FFFF;
-               AT91C_BASE_SPI->SPI_MR |=
-                       ((AT91C_SPI_PCS3_DATAFLASH_CARD<<16) & AT91C_SPI_PCS);
-               break;
-       }
-
-       /* SPI_Enable */
-       AT91C_BASE_SPI->SPI_CR = AT91C_SPI_SPIEN; }
-
-/*---------------------------------------------------------------------------*/
-/* \fn    AT91F_SpiWrite                                                    */
-/* \brief Set the PDC registers for a transfert                                     */
-/*---------------------------------------------------------------------------*/
-unsigned int AT91F_SpiWrite ( AT91PS_DataflashDesc pDesc )
-{
-       unsigned int timeout;
-       unsigned long start;
-
-       pDesc->state = BUSY;
-
-       AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
-
-       /* Initialize the Transmit and Receive Pointer */
-       AT91C_BASE_SPI->SPI_RPR = (unsigned int)pDesc->rx_cmd_pt ;
-       AT91C_BASE_SPI->SPI_TPR = (unsigned int)pDesc->tx_cmd_pt ;
-
-       /* Intialize the Transmit and Receive Counters */
-       AT91C_BASE_SPI->SPI_RCR = pDesc->rx_cmd_size;
-       AT91C_BASE_SPI->SPI_TCR = pDesc->tx_cmd_size;
-
-       if ( pDesc->tx_data_size != 0 ) {
-               /* Initialize the Next Transmit and Next Receive Pointer */
-               AT91C_BASE_SPI->SPI_RNPR = (unsigned int)pDesc->rx_data_pt ;
-               AT91C_BASE_SPI->SPI_TNPR = (unsigned int)pDesc->tx_data_pt ;
-
-               /* Intialize the Next Transmit and Next Receive Counters */
-               AT91C_BASE_SPI->SPI_RNCR = pDesc->rx_data_size ;
-               AT91C_BASE_SPI->SPI_TNCR = pDesc->tx_data_size ;
-       }
-
-       /* arm simple, non interrupt dependent timer */
-       start = get_timer(0);
-       timeout = 0;
-
-       AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTEN + AT91C_PDC_RXTEN;
-       while(!(AT91C_BASE_SPI->SPI_SR & AT91C_SPI_RXBUFF) &&
-               ((timeout = get_timer(start) ) < CONFIG_SYS_SPI_WRITE_TOUT));
-       AT91C_BASE_SPI->SPI_PTCR = AT91C_PDC_TXTDIS + AT91C_PDC_RXTDIS;
-       pDesc->state = IDLE;
-
-       if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT){
-               printf("Error Timeout\n\r");
-               return DATAFLASH_ERROR;
-       }
-
-       return DATAFLASH_OK;
-}
-#endif

diff --git a/arch/arm/cpu/arm920t/at91rm9200/timer.c b/arch/arm/cpu/arm920t/at91rm9200/timer.c
deleted file mode 100644 (file)
index fbe74b6..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/timer.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * (C) Copyright 2002
- * Lineo, Inc. <www.lineo.com>
- * Bernhard Kuhn <bkuhn@lineo.com>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Marius Groeger <mgroeger@sysgo.de>
- *
- * (C) Copyright 2002
- * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
- * Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-/*#include <asm/io.h>*/
-#include <asm/arch/hardware.h>
-/*#include <asm/proc/ptrace.h>*/
-
-/* the number of clocks per CONFIG_SYS_HZ */
-#define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
-
-/* macro to read the 16 bit timer */
-#define READ_TIMER (tmr->TC_CV & 0x0000ffff)
-AT91PS_TC tmr;
-
-static ulong timestamp;
-static ulong lastinc;
-
-int timer_init (void)
-{
-       tmr = AT91C_BASE_TC0;
-
-       /* enables TC1.0 clock */
-       *AT91C_PMC_PCER = 1 << AT91C_ID_TC0;  /* enable clock */
-
-       *AT91C_TCB0_BCR = 0;
-       *AT91C_TCB0_BMR = AT91C_TCB_TC0XC0S_NONE | AT91C_TCB_TC1XC1S_NONE | AT91C_TCB_TC2XC2S_NONE;
-       tmr->TC_CCR = AT91C_TC_CLKDIS;
-#define AT91C_TC_CMR_CPCTRG (1 << 14)
-       /* set to MCLK/2 and restart the timer when the vlaue in TC_RC is reached */
-       tmr->TC_CMR = AT91C_TC_TIMER_DIV1_CLOCK | AT91C_TC_CMR_CPCTRG;
-
-       tmr->TC_IDR = ~0ul;
-       tmr->TC_RC = TIMER_LOAD_VAL;
-       lastinc = 0;
-       tmr->TC_CCR = AT91C_TC_SWTRG | AT91C_TC_CLKEN;
-       timestamp = 0;
-
-       return (0);
-}
-
-/*
- * timer without interrupts
- */
-ulong get_timer (ulong base)
-{
-       return get_timer_masked () - base;
-}
-
-void __udelay (unsigned long usec)
-{
-       udelay_masked(usec);
-}
-
-ulong get_timer_raw (void)
-{
-       ulong now = READ_TIMER;
-
-       if (now >= lastinc) {
-               /* normal mode */
-               timestamp += now - lastinc;
-       } else {
-               /* we have an overflow ... */
-               timestamp += now + TIMER_LOAD_VAL - lastinc;
-       }
-       lastinc = now;
-
-       return timestamp;
-}
-
-ulong get_timer_masked (void)
-{
-       return get_timer_raw()/TIMER_LOAD_VAL;
-}
-
-void udelay_masked (unsigned long usec)
-{
-       ulong tmo;
-       ulong endtime;
-       signed long diff;
-
-       tmo = CONFIG_SYS_HZ_CLOCK / 1000;
-       tmo *= usec;
-       tmo /= 1000;
-
-       endtime = get_timer_raw () + tmo;
-
-       do {
-               ulong now = get_timer_raw ();
-               diff = endtime - now;
-       } while (diff >= 0);
-}
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On ARM it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-       return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On ARM it returns the number of timer ticks per second.
- */
-ulong get_tbclk (void)
-{
-       ulong tbclk;
-
-       tbclk = CONFIG_SYS_HZ;
-       return tbclk;
-}

diff --git a/arch/arm/cpu/arm920t/at91rm9200/usb.c b/arch/arm/cpu/arm920t/at91rm9200/usb.c
deleted file mode 100644 (file)
index 72355dc..0000000
--- a/arch/arm/cpu/arm920t/at91rm9200/usb.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * (C) Copyright 2006
- * DENX Software Engineering <mk@denx.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
-# ifdef CONFIG_AT91RM9200
-
-#include <asm/arch/hardware.h>
-
-int usb_cpu_init(void)
-{
-       /* Enable USB host clock. */
-       *AT91C_PMC_SCER = AT91C_PMC_UHP;        /* 48MHz clock enabled for UHP */
-       *AT91C_PMC_PCER = 1 << AT91C_ID_UHP;    /* Peripheral Clock Enable Register */
-       return 0;
-}
-
-int usb_cpu_stop(void)
-{
-       /* Initialization failed */
-       *AT91C_PMC_PCDR = 1 << AT91C_ID_UHP;    /* Peripheral Clock Disable Register */
-       *AT91C_PMC_SCDR = AT91C_PMC_UHP;        /* 48MHz clock disabled for UHP */
-       return 0;
-}
-
-int usb_cpu_init_fail(void)
-{
-       return usb_cpu_stop();
-}
-
-# endif /* CONFIG_AT91RM9200 */
-#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */

diff --git a/arch/arm/include/asm/arch-at91rm9200/AT91RM9200.h b/arch/arm/include/asm/arch-at91rm9200/AT91RM9200.h
deleted file mode 100644 (file)
index 00bae1c..0000000
--- a/arch/arm/include/asm/arch-at91rm9200/AT91RM9200.h
+++ /dev/null
@@ -1,812 +0,0 @@
-/*
- * (C) Copyright 2003
- * AT91RM9200 definitions
- * Author : ATMEL AT91 application group
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef AT91RM9200_H
-#define AT91RM9200_H
-
-#ifndef __ASSEMBLY__
-typedef volatile unsigned int AT91_REG;                /* Hardware register definition */
-
-/*****************************************************************************/
-/*        SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface       */
-/*****************************************************************************/
-typedef struct _AT91S_TC
-{
-       AT91_REG         TC_CCR;        /* Channel Control Register */
-       AT91_REG         TC_CMR;        /* Channel Mode Register */
-       AT91_REG         Reserved0[2];  /*  */
-       AT91_REG         TC_CV;         /* Counter Value */
-       AT91_REG         TC_RA;         /* Register A */
-       AT91_REG         TC_RB;         /* Register B */
-       AT91_REG         TC_RC;         /* Register C */
-       AT91_REG         TC_SR;         /* Status Register */
-       AT91_REG         TC_IER;        /* Interrupt Enable Register */
-       AT91_REG         TC_IDR;        /* Interrupt Disable Register */
-       AT91_REG         TC_IMR;        /* Interrupt Mask Register */
-} AT91S_TC, *AT91PS_TC;
-
-#define AT91C_TC_TIMER_DIV1_CLOCK ((unsigned int) 0x0 <<  0) /* (TC) MCK/2 */
-#define AT91C_TC_TIMER_DIV2_CLOCK ((unsigned int) 0x1 <<  0) /* (TC) MCK/8 */
-#define AT91C_TC_TIMER_DIV3_CLOCK ((unsigned int) 0x2 <<  0) /* (TC) MCK/32 */
-#define AT91C_TC_TIMER_DIV4_CLOCK ((unsigned int) 0x3 <<  0) /* (TC) MCK/128 */
-#define AT91C_TC_SLOW_CLOCK      ((unsigned int) 0x4 <<  0) /* (TC) SLOW CLK*/
-#define AT91C_TC_XC0_CLOCK       ((unsigned int) 0x5 <<  0) /* (TC) XC0 */
-#define AT91C_TC_XC1_CLOCK       ((unsigned int) 0x6 <<  0) /* (TC) XC1 */
-#define AT91C_TC_XC2_CLOCK       ((unsigned int) 0x7 <<  0) /* (TC) XC2 */
-#define AT91C_TCB_TC0XC0S_NONE   ((unsigned int) 0x1)       /* (TCB) None signal connected to XC0 */
-#define AT91C_TCB_TC1XC1S_NONE   ((unsigned int) 0x1 <<  2) /* (TCB) None signal connected to XC1 */
-#define AT91C_TCB_TC2XC2S_NONE   ((unsigned int) 0x1 <<  4) /* (TCB) None signal connected to XC2 */
-#define AT91C_TC_CLKDIS                  ((unsigned int) 0x1 <<  1) /* (TC) Counter Clock Disable Command */
-#define AT91C_TC_SWTRG           ((unsigned int) 0x1 <<  2) /* (TC) Software Trigger Command */
-#define AT91C_TC_CLKEN           ((unsigned int) 0x1 <<  0) /* (TC) Counter Clock Enable Command */
-
-/*****************************************************************************/
-/*                  SOFTWARE API DEFINITION  FOR Usart                       */
-/*****************************************************************************/
-typedef struct _AT91S_USART
-{
-       AT91_REG         US_CR;         /* Control Register */
-       AT91_REG         US_MR;         /* Mode Register */
-       AT91_REG         US_IER;        /* Interrupt Enable Register */
-       AT91_REG         US_IDR;        /* Interrupt Disable Register */
-       AT91_REG         US_IMR;        /* Interrupt Mask Register */
-       AT91_REG         US_CSR;        /* Channel Status Register */
-       AT91_REG         US_RHR;        /* Receiver Holding Register */
-       AT91_REG         US_THR;        /* Transmitter Holding Register */
-       AT91_REG         US_BRGR;       /* Baud Rate Generator Register */
-       AT91_REG         US_RTOR;       /* Receiver Time-out Register */
-       AT91_REG         US_TTGR;       /* Transmitter Time-guard Register */
-       AT91_REG         Reserved0[5];  /*  */
-       AT91_REG         US_FIDI;       /* FI_DI_Ratio Register */
-       AT91_REG         US_NER;        /* Nb Errors Register */
-       AT91_REG         US_XXR;        /* XON_XOFF Register */
-       AT91_REG         US_IF;         /* IRDA_FILTER Register */
-       AT91_REG         Reserved1[44]; /*  */
-       AT91_REG         US_RPR;        /* Receive Pointer Register */
-       AT91_REG         US_RCR;        /* Receive Counter Register */
-       AT91_REG         US_TPR;        /* Transmit Pointer Register */
-       AT91_REG         US_TCR;        /* Transmit Counter Register */
-       AT91_REG         US_RNPR;       /* Receive Next Pointer Register */
-       AT91_REG         US_RNCR;       /* Receive Next Counter Register */
-       AT91_REG         US_TNPR;       /* Transmit Next Pointer Register */
-       AT91_REG         US_TNCR;       /* Transmit Next Counter Register */
-       AT91_REG         US_PTCR;       /* PDC Transfer Control Register */
-       AT91_REG         US_PTSR;       /* PDC Transfer Status Register */
-} AT91S_USART, *AT91PS_USART;
-
-/*****************************************************************************/
-/*          SOFTWARE API DEFINITION  FOR Clock Generator Controler           */
-/*****************************************************************************/
-typedef struct _AT91S_CKGR
-{
-       AT91_REG         CKGR_MOR;      /* Main Oscillator Register */
-       AT91_REG         CKGR_MCFR;     /* Main Clock  Frequency Register */
-       AT91_REG         CKGR_PLLAR;    /* PLL A Register */
-       AT91_REG         CKGR_PLLBR;    /* PLL B Register */
-} AT91S_CKGR, *AT91PS_CKGR;
-
-/* -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- */
-#define AT91C_CKGR_MOSCEN      ((unsigned int) 0x1  <<  0)     /* (CKGR) Main Oscillator Enable */
-#define AT91C_CKGR_OSCTEST     ((unsigned int) 0x1  <<  1)     /* (CKGR) Oscillator Test */
-#define AT91C_CKGR_OSCOUNT     ((unsigned int) 0xFF <<  8)     /* (CKGR) Main Oscillator Start-up Time */
-
-/* -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- */
-#define AT91C_CKGR_MAINF       ((unsigned int) 0xFFFF <<  0)   /* (CKGR) Main Clock Frequency */
-#define AT91C_CKGR_MAINRDY     ((unsigned int) 0x1 << 16)      /* (CKGR) Main Clock Ready */
-
-/* -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register -------- */
-#define AT91C_CKGR_DIVA                ((unsigned int) 0xFF  <<  0)    /* (CKGR) Divider Selected */
-#define AT91C_CKGR_DIVA_0      ((unsigned int) 0x0)            /* (CKGR) Divider output is 0 */
-#define AT91C_CKGR_DIVA_BYPASS ((unsigned int) 0x1)            /* (CKGR) Divider is bypassed */
-#define AT91C_CKGR_PLLACOUNT   ((unsigned int) 0x3F  <<  8)    /* (CKGR) PLL A Counter */
-#define AT91C_CKGR_OUTA                ((unsigned int) 0x3   << 14)    /* (CKGR) PLL A Output Frequency Range */
-#define AT91C_CKGR_OUTA_0      ((unsigned int) 0x0   << 14)    /* (CKGR) Please refer to the PLLA datasheet */
-#define AT91C_CKGR_OUTA_1      ((unsigned int) 0x1   << 14)    /* (CKGR) Please refer to the PLLA datasheet */
-#define AT91C_CKGR_OUTA_2      ((unsigned int) 0x2   << 14)    /* (CKGR) Please refer to the PLLA datasheet */
-#define AT91C_CKGR_OUTA_3      ((unsigned int) 0x3   << 14)    /* (CKGR) Please refer to the PLLA datasheet */
-#define AT91C_CKGR_MULA                ((unsigned int) 0x7FF << 16)    /* (CKGR) PLL A Multiplier */
-#define AT91C_CKGR_SRCA                ((unsigned int) 0x1   << 29)    /* (CKGR) PLL A Source */
-
-/* -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register -------- */
-#define AT91C_CKGR_DIVB                ((unsigned int) 0xFF  <<  0)    /* (CKGR) Divider Selected */
-#define AT91C_CKGR_DIVB_0      ((unsigned int) 0x0)            /* (CKGR) Divider output is 0 */
-#define AT91C_CKGR_DIVB_BYPASS ((unsigned int) 0x1)            /* (CKGR) Divider is bypassed */
-#define AT91C_CKGR_PLLBCOUNT   ((unsigned int) 0x3F  <<  8)    /* (CKGR) PLL B Counter */
-#define AT91C_CKGR_OUTB                ((unsigned int) 0x3   << 14)    /* (CKGR) PLL B Output Frequency Range */
-#define AT91C_CKGR_OUTB_0      ((unsigned int) 0x0   << 14)    /* (CKGR) Please refer to the PLLB datasheet */
-#define AT91C_CKGR_OUTB_1      ((unsigned int) 0x1   << 14)    /* (CKGR) Please refer to the PLLB datasheet */
-#define AT91C_CKGR_OUTB_2      ((unsigned int) 0x2   << 14)    /* (CKGR) Please refer to the PLLB datasheet */
-#define AT91C_CKGR_OUTB_3      ((unsigned int) 0x3   << 14)    /* (CKGR) Please refer to the PLLB datasheet */
-#define AT91C_CKGR_MULB                ((unsigned int) 0x7FF << 16)    /* (CKGR) PLL B Multiplier */
-#define AT91C_CKGR_USB_96M     ((unsigned int) 0x1   << 28)    /* (CKGR) Divider for USB Ports */
-#define AT91C_CKGR_USB_PLL     ((unsigned int) 0x1   << 29)    /* (CKGR) PLL Use */
-
-/*****************************************************************************/
-/*        SOFTWARE API DEFINITION  FOR Parallel Input Output Controler       */
-/*****************************************************************************/
-typedef struct _AT91S_PIO
-{
-       AT91_REG         PIO_PER;       /* PIO Enable Register */
-       AT91_REG         PIO_PDR;       /* PIO Disable Register */
-       AT91_REG         PIO_PSR;       /* PIO Status Register */
-       AT91_REG         Reserved0[1];  /*  */
-       AT91_REG         PIO_OER;       /* Output Enable Register */
-       AT91_REG         PIO_ODR;       /* Output Disable Registerr */
-       AT91_REG         PIO_OSR;       /* Output Status Register */
-       AT91_REG         Reserved1[1];  /*  */
-       AT91_REG         PIO_IFER;      /* Input Filter Enable Register */
-       AT91_REG         PIO_IFDR;      /* Input Filter Disable Register */
-       AT91_REG         PIO_IFSR;      /* Input Filter Status Register */
-       AT91_REG         Reserved2[1];  /*  */
-       AT91_REG         PIO_SODR;      /* Set Output Data Register */
-       AT91_REG         PIO_CODR;      /* Clear Output Data Register */
-       AT91_REG         PIO_ODSR;      /* Output Data Status Register */
-       AT91_REG         PIO_PDSR;      /* Pin Data Status Register */
-       AT91_REG         PIO_IER;       /* Interrupt Enable Register */
-       AT91_REG         PIO_IDR;       /* Interrupt Disable Register */
-       AT91_REG         PIO_IMR;       /* Interrupt Mask Register */
-       AT91_REG         PIO_ISR;       /* Interrupt Status Register */
-       AT91_REG         PIO_MDER;      /* Multi-driver Enable Register */
-       AT91_REG         PIO_MDDR;      /* Multi-driver Disable Register */
-       AT91_REG         PIO_MDSR;      /* Multi-driver Status Register */
-       AT91_REG         Reserved3[1];  /*  */
-       AT91_REG         PIO_PPUDR;     /* Pull-up Disable Register */
-       AT91_REG         PIO_PPUER;     /* Pull-up Enable Register */
-       AT91_REG         PIO_PPUSR;     /* Pad Pull-up Status Register */
-       AT91_REG         Reserved4[1];  /*  */
-       AT91_REG         PIO_ASR;       /* Select A Register */
-       AT91_REG         PIO_BSR;       /* Select B Register */
-       AT91_REG         PIO_ABSR;      /* AB Select Status Register */
-       AT91_REG         Reserved5[9];  /*  */
-       AT91_REG         PIO_OWER;      /* Output Write Enable Register */
-       AT91_REG         PIO_OWDR;      /* Output Write Disable Register */
-       AT91_REG         PIO_OWSR;      /* Output Write Status Register */
-} AT91S_PIO, *AT91PS_PIO;
-
-
-/*****************************************************************************/
-/*              SOFTWARE API DEFINITION  FOR Debug Unit                      */
-/*****************************************************************************/
-typedef struct _AT91S_DBGU
-{
-       AT91_REG         DBGU_CR;       /* Control Register */
-       AT91_REG         DBGU_MR;       /* Mode Register */
-       AT91_REG         DBGU_IER;      /* Interrupt Enable Register */
-       AT91_REG         DBGU_IDR;      /* Interrupt Disable Register */
-       AT91_REG         DBGU_IMR;      /* Interrupt Mask Register */
-       AT91_REG         DBGU_CSR;      /* Channel Status Register */
-       AT91_REG         DBGU_RHR;      /* Receiver Holding Register */
-       AT91_REG         DBGU_THR;      /* Transmitter Holding Register */
-       AT91_REG         DBGU_BRGR;     /* Baud Rate Generator Register */
-       AT91_REG         Reserved0[7];  /*  */
-       AT91_REG         DBGU_C1R;      /* Chip ID1 Register */
-       AT91_REG         DBGU_C2R;      /* Chip ID2 Register */
-       AT91_REG         DBGU_FNTR;     /* Force NTRST Register */
-       AT91_REG         Reserved1[45]; /*  */
-       AT91_REG         DBGU_RPR;      /* Receive Pointer Register */
-       AT91_REG         DBGU_RCR;      /* Receive Counter Register */
-       AT91_REG         DBGU_TPR;      /* Transmit Pointer Register */
-       AT91_REG         DBGU_TCR;      /* Transmit Counter Register */
-       AT91_REG         DBGU_RNPR;     /* Receive Next Pointer Register */
-       AT91_REG         DBGU_RNCR;     /* Receive Next Counter Register */
-       AT91_REG         DBGU_TNPR;     /* Transmit Next Pointer Register */
-       AT91_REG         DBGU_TNCR;     /* Transmit Next Counter Register */
-       AT91_REG         DBGU_PTCR;     /* PDC Transfer Control Register */
-       AT91_REG         DBGU_PTSR;     /* PDC Transfer Status Register */
-} AT91S_DBGU, *AT91PS_DBGU;
-
-/* -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------  */
-#define AT91C_US_RXRDY         ((unsigned int) 0x1 <<  0) /* (DBGU) RXRDY Interrupt */
-#define AT91C_US_TXRDY         ((unsigned int) 0x1 <<  1) /* (DBGU) TXRDY Interrupt */
-#define AT91C_US_ENDRX         ((unsigned int) 0x1 <<  3) /* (DBGU) End of Receive Transfer Interrupt */
-#define AT91C_US_ENDTX         ((unsigned int) 0x1 <<  4) /* (DBGU) End of Transmit Interrupt */
-#define AT91C_US_OVRE          ((unsigned int) 0x1 <<  5) /* (DBGU) Overrun Interrupt */
-#define AT91C_US_FRAME         ((unsigned int) 0x1 <<  6) /* (DBGU) Framing Error Interrupt */
-#define AT91C_US_PARE          ((unsigned int) 0x1 <<  7) /* (DBGU) Parity Error Interrupt */
-#define AT91C_US_TXEMPTY       ((unsigned int) 0x1 <<  9) /* (DBGU) TXEMPTY Interrupt */
-#define AT91C_US_TXBUFE                ((unsigned int) 0x1 << 11) /* (DBGU) TXBUFE Interrupt */
-#define AT91C_US_RXBUFF                ((unsigned int) 0x1 << 12) /* (DBGU) RXBUFF Interrupt */
-#define AT91C_US_COMM_TX       ((unsigned int) 0x1 << 30) /* (DBGU) COMM_TX Interrupt */
-#define AT91C_US_COMM_RX       ((unsigned int) 0x1 << 31) /* (DBGU) COMM_RX Interrupt */
-
-/* -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------  */
-#define AT91C_US_RSTRX         ((unsigned int) 0x1 <<  2) /* (DBGU) Reset Receiver */
-#define AT91C_US_RSTTX         ((unsigned int) 0x1 <<  3) /* (DBGU) Reset Transmitter */
-#define AT91C_US_RXEN          ((unsigned int) 0x1 <<  4) /* (DBGU) Receiver Enable */
-#define AT91C_US_RXDIS         ((unsigned int) 0x1 <<  5) /* (DBGU) Receiver Disable */
-#define AT91C_US_TXEN          ((unsigned int) 0x1 <<  6) /* (DBGU) Transmitter Enable */
-#define AT91C_US_TXDIS         ((unsigned int) 0x1 <<  7) /* (DBGU) Transmitter Disable */
-
-#define AT91C_US_CLKS_CLOCK    ((unsigned int) 0x0 <<  4) /* (USART) Clock */
-#define AT91C_US_CHRL_8_BITS   ((unsigned int) 0x3 <<  6) /* (USART) Character Length: 8 bits */
-#define AT91C_US_PAR_NONE      ((unsigned int) 0x4 <<  9) /* (DBGU) No Parity */
-#define AT91C_US_NBSTOP_1_BIT  ((unsigned int) 0x0 << 12) /* (USART) 1 stop bit */
-
-/*****************************************************************************/
-/*      SOFTWARE API DEFINITION  FOR Static Memory Controller 2 Interface    */
-/*****************************************************************************/
-typedef struct _AT91S_SMC2
-{
-       AT91_REG         SMC2_CSR[8];   /* SMC2 Chip Select Register */
-} AT91S_SMC2, *AT91PS_SMC2;
-
-/* -------- SMC2_CSR : (SMC2 Offset: 0x0) SMC2 Chip Select Register --------  */
-#define AT91C_SMC2_NWS                 ((unsigned int) 0x7F << 0) /* (SMC2) Number of Wait States */
-#define AT91C_SMC2_WSEN                        ((unsigned int) 0x1 <<  7) /* (SMC2) Wait State Enable */
-#define AT91C_SMC2_TDF                 ((unsigned int) 0xF <<  8) /* (SMC2) Data Float Time */
-#define AT91C_SMC2_BAT                 ((unsigned int) 0x1 << 12) /* (SMC2) Byte Access Type */
-#define AT91C_SMC2_DBW                 ((unsigned int) 0x1 << 13) /* (SMC2) Data Bus Width */
-#define AT91C_SMC2_DBW_16              ((unsigned int) 0x1 << 13) /* (SMC2) 16-bit. */
-#define AT91C_SMC2_DBW_8               ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */
-#define AT91C_SMC2_DRP                 ((unsigned int) 0x1 << 15) /* (SMC2) Data Read Protocol */
-#define AT91C_SMC2_ACSS                        ((unsigned int) 0x3 << 16) /* (SMC2) Address to Chip Select Setup */
-#define AT91C_SMC2_ACSS_STANDARD       ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */
-#define AT91C_SMC2_ACSS_1_CYCLE                ((unsigned int) 0x1 << 16) /* (SMC2) One cycle less at the beginning and the end of the access. */
-#define AT91C_SMC2_ACSS_2_CYCLES       ((unsigned int) 0x2 << 16) /* (SMC2) Two cycles less at the beginning and the end of the access. */
-#define AT91C_SMC2_ACSS_3_CYCLES       ((unsigned int) 0x3 << 16) /* (SMC2) Three cycles less at the beginning and the end of the access. */
-#define AT91C_SMC2_RWSETUP             ((unsigned int) 0x7 << 24) /* (SMC2) Read and Write Signal Setup Time */
-#define AT91C_SMC2_RWHOLD              ((unsigned int) 0x7 << 29) /* (SMC2) Read and Write Signal Hold Time */
-
-/*****************************************************************************/
-/*           SOFTWARE API DEFINITION  FOR Power Management Controler         */
-/*****************************************************************************/
-typedef struct _AT91S_PMC
-{
-       AT91_REG         PMC_SCER;      /* System Clock Enable Register */
-       AT91_REG         PMC_SCDR;      /* System Clock Disable Register */
-       AT91_REG         PMC_SCSR;      /* System Clock Status Register */
-       AT91_REG         Reserved0[1];  /* */
-       AT91_REG         PMC_PCER;      /* Peripheral Clock Enable Register */
-       AT91_REG         PMC_PCDR;      /* Peripheral Clock Disable Register */
-       AT91_REG         PMC_PCSR;      /* Peripheral Clock Status Register */
-       AT91_REG         Reserved1[5];  /* */
-       AT91_REG         PMC_MCKR;      /* Master Clock Register */
-       AT91_REG         Reserved2[3];  /* */
-       AT91_REG         PMC_PCKR[8];   /* Programmable Clock Register */
-       AT91_REG         PMC_IER;       /* Interrupt Enable Register */
-       AT91_REG         PMC_IDR;       /* Interrupt Disable Register */
-       AT91_REG         PMC_SR;        /* Status Register */
-       AT91_REG         PMC_IMR;       /* Interrupt Mask Register */
-} AT91S_PMC, *AT91PS_PMC;
-
-/*------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------*/
-#define AT91C_PMC_PCK          ((unsigned int) 0x1 <<  0) /* (PMC) Processor Clock */
-#define AT91C_PMC_UDP          ((unsigned int) 0x1 <<  1) /* (PMC) USB Device Port Clock */
-#define AT91C_PMC_MCKUDP       ((unsigned int) 0x1 <<  2) /* (PMC) USB Device Port Master Clock Automatic Disable on Suspend */
-#define AT91C_PMC_UHP          ((unsigned int) 0x1 <<  4) /* (PMC) USB Host Port Clock */
-#define AT91C_PMC_PCK0         ((unsigned int) 0x1 <<  8) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK1         ((unsigned int) 0x1 <<  9) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK2         ((unsigned int) 0x1 << 10) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK3         ((unsigned int) 0x1 << 11) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK4         ((unsigned int) 0x1 << 12) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK5         ((unsigned int) 0x1 << 13) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK6         ((unsigned int) 0x1 << 14) /* (PMC) Programmable Clock Output */
-#define AT91C_PMC_PCK7         ((unsigned int) 0x1 << 15) /* (PMC) Programmable Clock Output */
-/*-------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register ------*/
-/*-------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------*/
-/*-------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------*/
-#define AT91C_PMC_CSS          ((unsigned int) 0x3 <<  0) /* (PMC) Programmable Clock Selection */
-#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0)       /* (PMC) Slow Clock is selected */
-#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1)       /* (PMC) Main Clock is selected */
-#define AT91C_PMC_CSS_PLLA_CLK ((unsigned int) 0x2)       /* (PMC) Clock from PLL A is selected */
-#define AT91C_PMC_CSS_PLLB_CLK ((unsigned int) 0x3)       /* (PMC) Clock from PLL B is selected */
-#define AT91C_PMC_PRES         ((unsigned int) 0x7 <<  2) /* (PMC) Programmable Clock Prescaler */
-#define AT91C_PMC_PRES_CLK     ((unsigned int) 0x0 <<  2) /* (PMC) Selected clock */
-#define AT91C_PMC_PRES_CLK_2   ((unsigned int) 0x1 <<  2) /* (PMC) Selected clock divided by 2 */
-#define AT91C_PMC_PRES_CLK_4   ((unsigned int) 0x2 <<  2) /* (PMC) Selected clock divided by 4 */
-#define AT91C_PMC_PRES_CLK_8   ((unsigned int) 0x3 <<  2) /* (PMC) Selected clock divided by 8 */
-#define AT91C_PMC_PRES_CLK_16  ((unsigned int) 0x4 <<  2) /* (PMC) Selected clock divided by 16 */
-#define AT91C_PMC_PRES_CLK_32  ((unsigned int) 0x5 <<  2) /* (PMC) Selected clock divided by 32 */
-#define AT91C_PMC_PRES_CLK_64  ((unsigned int) 0x6 <<  2) /* (PMC) Selected clock divided by 64 */
-#define AT91C_PMC_MDIV         ((unsigned int) 0x3 <<  8) /* (PMC) Master Clock Division */
-#define AT91C_PMC_MDIV_1       ((unsigned int) 0x0 <<  8) /* (PMC) The master clock and the processor clock are the same */
-#define AT91C_PMC_MDIV_2       ((unsigned int) 0x1 <<  8) /* (PMC) The processor clock is twice as fast as the master clock */
-#define AT91C_PMC_MDIV_3       ((unsigned int) 0x2 <<  8) /* (PMC) The processor clock is three times faster than the master clock */
-#define AT91C_PMC_MDIV_4       ((unsigned int) 0x3 <<  8) /* (PMC) The processor clock is four times faster than the master clock */
-/*------ PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------*/
-/*------ PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------*/
-#define AT91C_PMC_MOSCS                ((unsigned int) 0x1 <<  0) /* (PMC) MOSC Status/Enable/Disable/Mask */
-#define AT91C_PMC_LOCKA                ((unsigned int) 0x1 <<  1) /* (PMC) PLL A Status/Enable/Disable/Mask */
-#define AT91C_PMC_LOCKB                ((unsigned int) 0x1 <<  2) /* (PMC) PLL B Status/Enable/Disable/Mask */
-#define AT91C_PMC_MCKRDY       ((unsigned int) 0x1 <<  3) /* (PMC) MCK_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK0RDY      ((unsigned int) 0x1 <<  8) /* (PMC) PCK0_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK1RDY      ((unsigned int) 0x1 <<  9) /* (PMC) PCK1_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK2RDY      ((unsigned int) 0x1 << 10) /* (PMC) PCK2_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK3RDY      ((unsigned int) 0x1 << 11) /* (PMC) PCK3_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK4RDY      ((unsigned int) 0x1 << 12) /* (PMC) PCK4_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK5RDY      ((unsigned int) 0x1 << 13) /* (PMC) PCK5_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK6RDY      ((unsigned int) 0x1 << 14) /* (PMC) PCK6_RDY Status/Enable/Disable/Mask */
-#define AT91C_PMC_PCK7RDY      ((unsigned int) 0x1 << 15) /* (PMC) PCK7_RDY Status/Enable/Disable/Mask */
-/*---- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------*/
-/*-------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------*/
-/*-------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------*/
-
-/*****************************************************************************/
-/*              SOFTWARE API DEFINITION  FOR Ethernet MAC                    */
-/*****************************************************************************/
-typedef struct _AT91S_EMAC
-{
-       AT91_REG         EMAC_CTL;      /* Network Control Register */
-       AT91_REG         EMAC_CFG;      /* Network Configuration Register */
-       AT91_REG         EMAC_SR;       /* Network Status Register */
-       AT91_REG         EMAC_TAR;      /* Transmit Address Register */
-       AT91_REG         EMAC_TCR;      /* Transmit Control Register */
-       AT91_REG         EMAC_TSR;      /* Transmit Status Register */
-       AT91_REG         EMAC_RBQP;     /* Receive Buffer Queue Pointer */
-       AT91_REG         Reserved0[1];  /*  */
-       AT91_REG         EMAC_RSR;      /* Receive Status Register */
-       AT91_REG         EMAC_ISR;      /* Interrupt Status Register */
-       AT91_REG         EMAC_IER;      /* Interrupt Enable Register */
-       AT91_REG         EMAC_IDR;      /* Interrupt Disable Register */
-       AT91_REG         EMAC_IMR;      /* Interrupt Mask Register */
-       AT91_REG         EMAC_MAN;      /* PHY Maintenance Register */
-       AT91_REG         Reserved1[2];  /*  */
-       AT91_REG         EMAC_FRA;      /* Frames Transmitted OK Register */
-       AT91_REG         EMAC_SCOL;     /* Single Collision Frame Register */
-       AT91_REG         EMAC_MCOL;     /* Multiple Collision Frame Register */
-       AT91_REG         EMAC_OK;       /* Frames Received OK Register */
-       AT91_REG         EMAC_SEQE;     /* Frame Check Sequence Error Register */
-       AT91_REG         EMAC_ALE;      /* Alignment Error Register */
-       AT91_REG         EMAC_DTE;      /* Deferred Transmission Frame Register */
-       AT91_REG         EMAC_LCOL;     /* Late Collision Register */
-       AT91_REG         EMAC_ECOL;     /* Excessive Collision Register */
-       AT91_REG         EMAC_CSE;      /* Carrier Sense Error Register */
-       AT91_REG         EMAC_TUE;      /* Transmit Underrun Error Register */
-       AT91_REG         EMAC_CDE;      /* Code Error Register */
-       AT91_REG         EMAC_ELR;      /* Excessive Length Error Register */
-       AT91_REG         EMAC_RJB;      /* Receive Jabber Register */
-       AT91_REG         EMAC_USF;      /* Undersize Frame Register */
-       AT91_REG         EMAC_SQEE;     /* SQE Test Error Register */
-       AT91_REG         EMAC_DRFC;     /* Discarded RX Frame Register */
-       AT91_REG         Reserved2[3];  /*  */
-       AT91_REG         EMAC_HSH;      /* Hash Address High[63:32] */
-       AT91_REG         EMAC_HSL;      /* Hash Address Low[31:0] */
-       AT91_REG         EMAC_SA1L;     /* Specific Address 1 Low, First 4 bytes */
-       AT91_REG         EMAC_SA1H;     /* Specific Address 1 High, Last 2 bytes */
-       AT91_REG         EMAC_SA2L;     /* Specific Address 2 Low, First 4 bytes */
-       AT91_REG         EMAC_SA2H;     /* Specific Address 2 High, Last 2 bytes */
-       AT91_REG         EMAC_SA3L;     /* Specific Address 3 Low, First 4 bytes */
-       AT91_REG         EMAC_SA3H;     /* Specific Address 3 High, Last 2 bytes */
-       AT91_REG         EMAC_SA4L;     /* Specific Address 4 Low, First 4 bytes */
-       AT91_REG         EMAC_SA4H;     /* Specific Address 4 High, Last 2 bytesr */
-} AT91S_EMAC, *AT91PS_EMAC;
-
-/* -------- EMAC_CTL : (EMAC Offset: 0x0)  --------  */
-#define AT91C_EMAC_LB          ((unsigned int) 0x1 <<  0) /* (EMAC) Loopback. Optional. When set, loopback signal is at high level. */
-#define AT91C_EMAC_LBL         ((unsigned int) 0x1 <<  1) /* (EMAC) Loopback local. */
-#define AT91C_EMAC_RE          ((unsigned int) 0x1 <<  2) /* (EMAC) Receive enable. */
-#define AT91C_EMAC_TE          ((unsigned int) 0x1 <<  3) /* (EMAC) Transmit enable. */
-#define AT91C_EMAC_MPE         ((unsigned int) 0x1 <<  4) /* (EMAC) Management port enable. */
-#define AT91C_EMAC_CSR         ((unsigned int) 0x1 <<  5) /* (EMAC) Clear statistics registers. */
-#define AT91C_EMAC_ISR         ((unsigned int) 0x1 <<  6) /* (EMAC) Increment statistics registers. */
-#define AT91C_EMAC_WES         ((unsigned int) 0x1 <<  7) /* (EMAC) Write enable for statistics registers. */
-#define AT91C_EMAC_BP          ((unsigned int) 0x1 <<  8) /* (EMAC) Back pressure. */
-
-/* -------- EMAC_CFG : (EMAC Offset: 0x4) Network Configuration Register --------  */
-#define AT91C_EMAC_SPD         ((unsigned int) 0x1 <<  0) /* (EMAC) Speed. */
-#define AT91C_EMAC_FD          ((unsigned int) 0x1 <<  1) /* (EMAC) Full duplex. */
-#define AT91C_EMAC_BR          ((unsigned int) 0x1 <<  2) /* (EMAC) Bit rate. */
-#define AT91C_EMAC_CAF         ((unsigned int) 0x1 <<  4) /* (EMAC) Copy all frames. */
-#define AT91C_EMAC_NBC         ((unsigned int) 0x1 <<  5) /* (EMAC) No broadcast. */
-#define AT91C_EMAC_MTI         ((unsigned int) 0x1 <<  6) /* (EMAC) Multicast hash enable */
-#define AT91C_EMAC_UNI         ((unsigned int) 0x1 <<  7) /* (EMAC) Unicast hash enable. */
-#define AT91C_EMAC_BIG         ((unsigned int) 0x1 <<  8) /* (EMAC) Receive 1522 bytes. */
-#define AT91C_EMAC_EAE         ((unsigned int) 0x1 <<  9) /* (EMAC) External address match enable. */
-#define AT91C_EMAC_CLK         ((unsigned int) 0x3 << 10) /* (EMAC) */
-#define AT91C_EMAC_CLK_HCLK_8  ((unsigned int) 0x0 << 10) /* (EMAC) HCLK divided by 8 */
-#define AT91C_EMAC_CLK_HCLK_16 ((unsigned int) 0x1 << 10) /* (EMAC) HCLK divided by 16 */
-#define AT91C_EMAC_CLK_HCLK_32 ((unsigned int) 0x2 << 10) /* (EMAC) HCLK divided by 32 */
-#define AT91C_EMAC_CLK_HCLK_64 ((unsigned int) 0x3 << 10) /* (EMAC) HCLK divided by 64 */
-#define AT91C_EMAC_RTY         ((unsigned int) 0x1 << 12) /* (EMAC) */
-#define AT91C_EMAC_RMII                ((unsigned int) 0x1 << 13) /* (EMAC) */
-
-/* -------- EMAC_SR : (EMAC Offset: 0x8) Network Status Register --------  */
-#define AT91C_EMAC_MDIO                ((unsigned int) 0x1 <<  1) /* (EMAC) */
-#define AT91C_EMAC_IDLE                ((unsigned int) 0x1 <<  2) /* (EMAC) */
-
-/* -------- EMAC_TCR : (EMAC Offset: 0x10) Transmit Control Register ------- */
-#define AT91C_EMAC_LEN         ((unsigned int) 0x7FF <<  0) /* (EMAC) */
-#define AT91C_EMAC_NCRC                ((unsigned int) 0x1 << 15) /* (EMAC) */
-
-/* -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Control Register ------- */
-#define AT91C_EMAC_OVR         ((unsigned int) 0x1 <<  0) /* (EMAC) */
-#define AT91C_EMAC_COL         ((unsigned int) 0x1 <<  1) /* (EMAC) */
-#define AT91C_EMAC_RLE         ((unsigned int) 0x1 <<  2) /* (EMAC) */
-#define AT91C_EMAC_TXIDLE      ((unsigned int) 0x1 <<  3) /* (EMAC) */
-#define AT91C_EMAC_BNQ         ((unsigned int) 0x1 <<  4) /* (EMAC) */
-#define AT91C_EMAC_COMP                ((unsigned int) 0x1 <<  5) /* (EMAC) */
-#define AT91C_EMAC_UND         ((unsigned int) 0x1 <<  6) /* (EMAC) */
-
-/* -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- */
-#define AT91C_EMAC_BNA         ((unsigned int) 0x1 <<  0) /* (EMAC) */
-#define AT91C_EMAC_REC         ((unsigned int) 0x1 <<  1) /* (EMAC) */
-#define AT91C_EMAC_RSR_OVR     ((unsigned int) 0x1 <<  2) /* (EMAC) */
-
-/* -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register ------- */
-#define AT91C_EMAC_DONE                ((unsigned int) 0x1 <<  0) /* (EMAC) */
-#define AT91C_EMAC_RCOM                ((unsigned int) 0x1 <<  1) /* (EMAC) */
-#define AT91C_EMAC_RBNA                ((unsigned int) 0x1 <<  2) /* (EMAC) */
-#define AT91C_EMAC_TOVR                ((unsigned int) 0x1 <<  3) /* (EMAC) */
-#define AT91C_EMAC_TUND                ((unsigned int) 0x1 <<  4) /* (EMAC) */
-#define AT91C_EMAC_RTRY                ((unsigned int) 0x1 <<  5) /* (EMAC) */
-#define AT91C_EMAC_TBRE                ((unsigned int) 0x1 <<  6) /* (EMAC) */
-#define AT91C_EMAC_TCOM                ((unsigned int) 0x1 <<  7) /* (EMAC) */
-#define AT91C_EMAC_TIDLE       ((unsigned int) 0x1 <<  8) /* (EMAC) */
-#define AT91C_EMAC_LINK                ((unsigned int) 0x1 <<  9) /* (EMAC) */
-#define AT91C_EMAC_ROVR                ((unsigned int) 0x1 << 10) /* (EMAC) */
-#define AT91C_EMAC_HRESP       ((unsigned int) 0x1 << 11) /* (EMAC) */
-
-/* -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register ------- */
-/* -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register ------ */
-/* -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- */
-/* -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- */
-#define AT91C_EMAC_DATA                ((unsigned int) 0xFFFF <<  0) /* (EMAC) */
-#define AT91C_EMAC_CODE                ((unsigned int) 0x3  << 16) /* (EMAC) */
-#define AT91C_EMAC_CODE_802_3  ((unsigned int) 0x2  << 16) /* (EMAC) Write Operation */
-#define AT91C_EMAC_REGA                ((unsigned int) 0x1F << 18) /* (EMAC) */
-#define AT91C_EMAC_PHYA                ((unsigned int) 0x1F << 23) /* (EMAC) */
-#define AT91C_EMAC_RW          ((unsigned int) 0x3  << 28) /* (EMAC) */
-#define AT91C_EMAC_RW_R                ((unsigned int) 0x2  << 28) /* (EMAC) Read Operation */
-#define AT91C_EMAC_RW_W                ((unsigned int) 0x1  << 28) /* (EMAC) Write Operation */
-#define AT91C_EMAC_HIGH                ((unsigned int) 0x1  << 30) /* (EMAC) */
-#define AT91C_EMAC_LOW         ((unsigned int) 0x1  << 31) /* (EMAC) */
-
-/*****************************************************************************/
-/*           SOFTWARE API DEFINITION  FOR Serial Parallel Interface          */
-/*****************************************************************************/
-typedef struct _AT91S_SPI
-{
-       AT91_REG         SPI_CR;        /* Control Register */
-       AT91_REG         SPI_MR;        /* Mode Register */
-       AT91_REG         SPI_RDR;       /* Receive Data Register */
-       AT91_REG         SPI_TDR;       /* Transmit Data Register */
-       AT91_REG         SPI_SR;        /* Status Register */
-       AT91_REG         SPI_IER;       /* Interrupt Enable Register */
-       AT91_REG         SPI_IDR;       /* Interrupt Disable Register */
-       AT91_REG         SPI_IMR;       /* Interrupt Mask Register */
-       AT91_REG         Reserved0[4];  /* */
-       AT91_REG         SPI_CSR[4];    /* Chip Select Register */
-       AT91_REG         Reserved1[48]; /* */
-       AT91_REG         SPI_RPR;       /* Receive Pointer Register */
-       AT91_REG         SPI_RCR;       /* Receive Counter Register */
-       AT91_REG         SPI_TPR;       /* Transmit Pointer Register */
-       AT91_REG         SPI_TCR;       /* Transmit Counter Register */
-       AT91_REG         SPI_RNPR;      /* Receive Next Pointer Register */
-       AT91_REG         SPI_RNCR;      /* Receive Next Counter Register */
-       AT91_REG         SPI_TNPR;      /* Transmit Next Pointer Register */
-       AT91_REG         SPI_TNCR;      /* Transmit Next Counter Register */
-       AT91_REG         SPI_PTCR;      /* PDC Transfer Control Register */
-       AT91_REG         SPI_PTSR;      /* PDC Transfer Status Register */
-} AT91S_SPI, *AT91PS_SPI;
-
-/* -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- */
-#define AT91C_SPI_SPIEN                ((unsigned int) 0x1 <<  0) /* (SPI) SPI Enable */
-#define AT91C_SPI_SPIDIS       ((unsigned int) 0x1 <<  1) /* (SPI) SPI Disable */
-#define AT91C_SPI_SWRST                ((unsigned int) 0x1 <<  7) /* (SPI) SPI Software reset */
-
-/* -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- */
-#define AT91C_SPI_MSTR         ((unsigned int) 0x1 <<  0) /* (SPI) Master/Slave Mode */
-#define AT91C_SPI_PS           ((unsigned int) 0x1 <<  1) /* (SPI) Peripheral Select */
-#define AT91C_SPI_PS_FIXED     ((unsigned int) 0x0 <<  1) /* (SPI) Fixed Peripheral Select */
-#define AT91C_SPI_PS_VARIABLE  ((unsigned int) 0x1 <<  1) /* (SPI) Variable Peripheral Select */
-#define AT91C_SPI_PCSDEC       ((unsigned int) 0x1 <<  2) /* (SPI) Chip Select Decode */
-#define AT91C_SPI_DIV32                ((unsigned int) 0x1 <<  3) /* (SPI) Clock Selection */
-#define AT91C_SPI_MODFDIS      ((unsigned int) 0x1 <<  4) /* (SPI) Mode Fault Detection */
-#define AT91C_SPI_LLB          ((unsigned int) 0x1 <<  7) /* (SPI) Clock Selection */
-#define AT91C_SPI_PCS          ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select */
-#define AT91C_SPI_DLYBCS       ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Chip Selects */
-
-/* -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- */
-#define AT91C_SPI_RD           ((unsigned int) 0xFFFF <<  0) /* (SPI) Receive Data */
-#define AT91C_SPI_RPCS         ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */
-
-/* -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- */
-#define AT91C_SPI_TD           ((unsigned int) 0xFFFF <<  0) /* (SPI) Transmit Data */
-#define AT91C_SPI_TPCS         ((unsigned int) 0xF << 16) /* (SPI) Peripheral Chip Select Status */
-
-/* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */
-#define AT91C_SPI_RDRF         ((unsigned int) 0x1 <<  0) /* (SPI) Receive Data Register Full */
-#define AT91C_SPI_TDRE         ((unsigned int) 0x1 <<  1) /* (SPI) Transmit Data Register Empty */
-#define AT91C_SPI_MODF         ((unsigned int) 0x1 <<  2) /* (SPI) Mode Fault Error */
-#define AT91C_SPI_OVRES                ((unsigned int) 0x1 <<  3) /* (SPI) Overrun Error Status */
-#define AT91C_SPI_SPENDRX      ((unsigned int) 0x1 <<  4) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_SPENDTX      ((unsigned int) 0x1 <<  5) /* (SPI) End of Receiver Transfer */
-#define AT91C_SPI_RXBUFF       ((unsigned int) 0x1 <<  6) /* (SPI) RXBUFF Interrupt */
-#define AT91C_SPI_TXBUFE       ((unsigned int) 0x1 <<  7) /* (SPI) TXBUFE Interrupt */
-#define AT91C_SPI_SPIENS       ((unsigned int) 0x1 << 16) /* (SPI) Enable Status */
-
-/* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */
-/* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register ------- */
-/* -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- */
-/* -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- */
-#define AT91C_SPI_CPOL         ((unsigned int) 0x1  <<  0) /* (SPI) Clock Polarity */
-#define AT91C_SPI_NCPHA                ((unsigned int) 0x1  <<  1) /* (SPI) Clock Phase */
-#define AT91C_SPI_BITS         ((unsigned int) 0xF  <<  4) /* (SPI) Bits Per Transfer */
-#define AT91C_SPI_BITS_8       ((unsigned int) 0x0  <<  4) /* (SPI) 8 Bits Per transfer */
-#define AT91C_SPI_BITS_9       ((unsigned int) 0x1  <<  4) /* (SPI) 9 Bits Per transfer */
-#define AT91C_SPI_BITS_10      ((unsigned int) 0x2  <<  4) /* (SPI) 10 Bits Per transfer */
-#define AT91C_SPI_BITS_11      ((unsigned int) 0x3  <<  4) /* (SPI) 11 Bits Per transfer */
-#define AT91C_SPI_BITS_12      ((unsigned int) 0x4  <<  4) /* (SPI) 12 Bits Per transfer */
-#define AT91C_SPI_BITS_13      ((unsigned int) 0x5  <<  4) /* (SPI) 13 Bits Per transfer */
-#define AT91C_SPI_BITS_14      ((unsigned int) 0x6  <<  4) /* (SPI) 14 Bits Per transfer */
-#define AT91C_SPI_BITS_15      ((unsigned int) 0x7  <<  4) /* (SPI) 15 Bits Per transfer */
-#define AT91C_SPI_BITS_16      ((unsigned int) 0x8  <<  4) /* (SPI) 16 Bits Per transfer */
-#define AT91C_SPI_SCBR         ((unsigned int) 0xFF <<  8) /* (SPI) Serial Clock Baud Rate */
-#define AT91C_SPI_DLYBS                ((unsigned int) 0xFF << 16) /* (SPI) Serial Clock Baud Rate */
-#define AT91C_SPI_DLYBCT       ((unsigned int) 0xFF << 24) /* (SPI) Delay Between Consecutive Transfers */
-
-/*****************************************************************************/
-/*           SOFTWARE API DEFINITION  FOR Peripheral Data Controller         */
-/*****************************************************************************/
-typedef struct _AT91S_PDC
-{
-       AT91_REG         PDC_RPR;       /* Receive Pointer Register */
-       AT91_REG         PDC_RCR;       /* Receive Counter Register */
-       AT91_REG         PDC_TPR;       /* Transmit Pointer Register */
-       AT91_REG         PDC_TCR;       /* Transmit Counter Register */
-       AT91_REG         PDC_RNPR;      /* Receive Next Pointer Register */
-       AT91_REG         PDC_RNCR;      /* Receive Next Counter Register */
-       AT91_REG         PDC_TNPR;      /* Transmit Next Pointer Register */
-       AT91_REG         PDC_TNCR;      /* Transmit Next Counter Register */
-       AT91_REG         PDC_PTCR;      /* PDC Transfer Control Register */
-       AT91_REG         PDC_PTSR;      /* PDC Transfer Status Register */
-} AT91S_PDC, *AT91PS_PDC;
-
-/* -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- */
-#define AT91C_PDC_RXTEN                ((unsigned int) 0x1 <<  0) /* (PDC) Receiver Transfer Enable */
-#define AT91C_PDC_RXTDIS       ((unsigned int) 0x1 <<  1) /* (PDC) Receiver Transfer Disable */
-#define AT91C_PDC_TXTEN                ((unsigned int) 0x1 <<  8) /* (PDC) Transmitter Transfer Enable */
-#define AT91C_PDC_TXTDIS       ((unsigned int) 0x1 <<  9) /* (PDC) Transmitter Transfer Disable */
-/* -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------  */
-
-/* ========== Register definition ==================================== */
-#define AT91C_SPI_CSR          ((AT91_REG *)   0xFFFE0030) /* (SPI) Chip Select Register */
-#define AT91C_PMC_PCER         ((AT91_REG *)   0xFFFFFC10) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PMC_PCDR         ((AT91_REG *)   0xFFFFFC14) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PMC_SCER         ((AT91_REG *)   0xFFFFFC00) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PMC_SCDR         ((AT91_REG *)   0xFFFFFC04) /* (PMC) Peripheral Clock Enable Register */
-#define AT91C_PIOA_PER         ((AT91_REG *)   0xFFFFF400) /* (PIOA) PIO Enable Register */
-#define AT91C_PIOA_PDR         ((AT91_REG *)   0xFFFFF404) /* (PIOA) PIO Disable Register */
-#define AT91C_PIOA_PSR         ((AT91_REG *)   0xFFFFF408) /* (PIOA) PIO Status Register */
-#define AT91C_PIOA_OER         ((AT91_REG *)   0xFFFFF410) /* (PIOA) PIO Output Enable Register */
-#define AT91C_PIOA_ODR         ((AT91_REG *)   0xFFFFF414) /* (PIOA) PIO Output Disable Register */
-#define AT91C_PIOA_OSR         ((AT91_REG *)   0xFFFFF418) /* (PIOA) PIO Output Status Register */
-#define AT91C_PIOA_IFER                ((AT91_REG *)   0xFFFFF420) /* (PIOA) PIO Glitch Input Filter Enable Register */
-#define AT91C_PIOA_IFDR                ((AT91_REG *)   0xFFFFF424) /* (PIOA) PIO Glitch Input Filter Disable Register */
-#define AT91C_PIOA_IFSR                ((AT91_REG *)   0xFFFFF428) /* (PIOA) PIO Glitch Input Filter Status Register */
-#define AT91C_PIOA_SODR                ((AT91_REG *)   0xFFFFF430) /* (PIOA) PIO Set Output Data Register */
-#define AT91C_PIOA_CODR                ((AT91_REG *)   0xFFFFF434) /* (PIOA) PIO Clear Output Data Register */
-#define AT91C_PIOA_ODSR                ((AT91_REG *)   0xFFFFF438) /* (PIOA) PIO Output Data Status Register */
-#define AT91C_PIOA_PDSR                ((AT91_REG *)   0xFFFFF43C) /* (PIOA) PIO Pin Data Status Register */
-#define AT91C_PIOA_IER         ((AT91_REG *)   0xFFFFF440) /* (PIOA) PIO Interrupt Enable Register */
-#define AT91C_PIOA_IDR         ((AT91_REG *)   0xFFFFF444) /* (PIOA) PIO Interrupt Disable Register */
-#define AT91C_PIOA_IMR         ((AT91_REG *)   0xFFFFF448) /* (PIOA) PIO Interrupt Mask Register */
-#define AT91C_PIOA_ISR         ((AT91_REG *)   0xFFFFF44C) /* (PIOA) PIO Interrupt Status Register */
-#define AT91C_PIOA_MDER                ((AT91_REG *)   0xFFFFF450) /* (PIOA) PIO Multi-drive Enable Register */
-#define AT91C_PIOA_MDDR                ((AT91_REG *)   0xFFFFF454) /* (PIOA) PIO Multi-drive Disable Register */
-#define AT91C_PIOA_MDSR                ((AT91_REG *)   0xFFFFF458) /* (PIOA) PIO Multi-drive Status Register */
-#define AT91C_PIOA_PUDR                ((AT91_REG *)   0xFFFFF460) /* (PIOA) PIO Pull-up Disable Register */
-#define AT91C_PIOA_PUER                ((AT91_REG *)   0xFFFFF464) /* (PIOA) PIO Pull-up Enable Register */
-#define AT91C_PIOA_PUSR                ((AT91_REG *)   0xFFFFF468) /* (PIOA) PIO Pull-up Status Register */
-#define AT91C_PIOA_ASR         ((AT91_REG *)   0xFFFFF470) /* (PIOA) PIO Peripheral A Select Register */
-#define AT91C_PIOA_BSR         ((AT91_REG *)   0xFFFFF474) /* (PIOA) PIO Peripheral B Select Register */
-#define AT91C_PIOA_ABSR                ((AT91_REG *)   0xFFFFF478) /* (PIOA) PIO Peripheral AB Select Register */
-#define AT91C_PIOA_OWER                ((AT91_REG *)   0xFFFFF4A0) /* (PIOA) PIO Output Write Enable Register */
-#define AT91C_PIOA_OWDR                ((AT91_REG *)   0xFFFFF4A4) /* (PIOA) PIO Output Write Disable Register */
-#define AT91C_PIOA_OWSR                ((AT91_REG *)   0xFFFFF4A8) /* (PIOA) PIO Output Write Status Register */
-#define AT91C_PIOB_PDR         ((AT91_REG *)   0xFFFFF604) /* (PIOB) PIO Disable Register */
-
-#define AT91C_PIO_PA30         ((unsigned int) 1 << 30)        /* Pin Controlled by PA30 */
-#define AT91C_PIO_PC0          ((unsigned int) 1 <<  0)        /* Pin Controlled by PC0 */
-#define AT91C_PC0_BFCK         ((unsigned int) AT91C_PIO_PC0)  /* Burst Flash Clock */
-#define AT91C_PA30_DRXD                ((unsigned int) AT91C_PIO_PA30) /* DBGU Debug Receive Data */
-#define AT91C_PIO_PA31         ((unsigned int) 1 << 31)        /* Pin Controlled by PA31 */
-#define AT91C_PA25_TWD         ((unsigned int) 1 << 25)
-#define AT91C_PA26_TWCK                ((unsigned int) 1 << 26)
-#define AT91C_PA31_DTXD                ((unsigned int) AT91C_PIO_PA31) /* DBGU Debug Transmit Data */
-#define AT91C_PIO_PA17         ((unsigned int) 1 << 17)        /* Pin Controlled by PA17 */
-#define AT91C_PA17_TXD0                AT91C_PIO_PA17                  /* USART0 Transmit Data */
-#define AT91C_PIO_PA18         ((unsigned int) 1 << 18)        /* Pin Controlled by PA18 */
-#define AT91C_PA18_RXD0                AT91C_PIO_PA18                  /* USART0 Receive Data */
-#define AT91C_PIO_PB20         ((unsigned int) 1 << 20)        /* Pin Controlled by PB20 */
-#define AT91C_PB20_RXD1                AT91C_PIO_PB20                  /* USART1 Receive Data */
-#define AT91C_PIO_PB21         ((unsigned int) 1 << 21)        /* Pin Controlled by PB21 */
-#define AT91C_PB21_TXD1                AT91C_PIO_PB21                  /* USART1 Transmit Data */
-
-#define AT91C_ID_SYS           ((unsigned int)  1) /* System Peripheral */
-#define AT91C_ID_PIOA          ((unsigned int)  2) /* PIO port A */
-#define AT91C_ID_PIOB          ((unsigned int)  3) /* PIO port B */
-#define AT91C_ID_PIOC          ((unsigned int)  4) /* PIO port C */
-#define AT91C_ID_USART0                ((unsigned int)  6) /* USART 0 */
-#define AT91C_ID_USART1                ((unsigned int)  7) /* USART 1 */
-#define AT91C_ID_TWI           ((unsigned int) 12) /* Two Wire Interface */
-#define AT91C_ID_SPI           ((unsigned int) 13) /* Serial Peripheral Interface */
-#define AT91C_ID_TC0           ((unsigned int) 17) /* Timer Counter 0 */
-#define AT91C_ID_UHP           ((unsigned int) 23) /* OHCI USB Host Port */
-#define AT91C_ID_EMAC          ((unsigned int) 24) /* Ethernet MAC */
-
-#define AT91C_PIO_PC1          ((unsigned int) 1 <<  1)        /* Pin Controlled by PC1 */
-#define AT91C_PC1_BFRDY_SMOE   ((unsigned int) AT91C_PIO_PC1)  /*  Burst Flash Ready */
-#define AT91C_PIO_PC3          ((unsigned int) 1 <<  3)        /* Pin Controlled by PC3 */
-#define AT91C_PC3_BFBAA_SMWE   ((unsigned int) AT91C_PIO_PC3)  /*  Burst Flash Address Advance / SmartMedia Write Enable */
-#define AT91C_PIO_PC2          ((unsigned int) 1 <<  2)        /* Pin Controlled by PC2 */
-#define AT91C_PC2_BFAVD                ((unsigned int) AT91C_PIO_PC2)  /*  Burst Flash Address Valid */
-#define AT91C_PIO_PB1          ((unsigned int) 1 <<  1)        /* Pin Controlled by PB1 */
-
-#define AT91C_PIO_PA23         ((unsigned int) 1 << 23)        /* Pin Controlled by PA23 */
-#define AT91C_PA23_TXD2                ((unsigned int) AT91C_PIO_PA23) /* USART 2 Transmit Data */
-
-#define AT91C_PIO_PA0          ((unsigned int) 1 <<  0)        /* Pin Controlled by PA0 */
-#define AT91C_PA0_MISO         ((unsigned int) AT91C_PIO_PA0)  /* SPI Master In Slave */
-#define AT91C_PIO_PA1          ((unsigned int) 1 <<  1)        /* Pin Controlled by PA1 */
-#define AT91C_PA1_MOSI         ((unsigned int) AT91C_PIO_PA1)  /* SPI Master Out Slave */
-#define AT91C_PIO_PA2          ((unsigned int) 1 <<  2)        /* Pin Controlled by PA2 */
-#define AT91C_PA2_SPCK         ((unsigned int) AT91C_PIO_PA2)  /* SPI Serial Clock */
-#define AT91C_PIO_PA3          ((unsigned int) 1 <<  3)        /* Pin Controlled by PA3 */
-#define AT91C_PA3_NPCS0                ((unsigned int) AT91C_PIO_PA3)  /* SPI Peripheral Chip Select 0 */
-#define AT91C_PIO_PA4          ((unsigned int) 1 <<  4)        /* Pin Controlled by PA4 */
-#define AT91C_PA4_NPCS1                ((unsigned int) AT91C_PIO_PA4)  /* SPI Peripheral Chip Select 1 */
-#define AT91C_PIO_PA5          ((unsigned int) 1 <<  5)        /* Pin Controlled by PA5 */
-#define AT91C_PA5_NPCS2                ((unsigned int) AT91C_PIO_PA5)  /* SPI Peripheral Chip Select 2 */
-#define AT91C_PIO_PA6          ((unsigned int) 1 <<  6)        /* Pin Controlled by PA6 */
-#define AT91C_PA6_NPCS3                ((unsigned int) AT91C_PIO_PA6)  /* SPI Peripheral Chip Select 3 */
-
-#define AT91C_PIO_PA16         ((unsigned int) 1 << 16)        /* Pin Controlled by PA16 */
-#define AT91C_PA16_EMDIO       ((unsigned int) AT91C_PIO_PA16) /* Ethernet MAC Management Data Input/Output */
-#define AT91C_PIO_PA15         ((unsigned int) 1 << 15)        /* Pin Controlled by PA15 */
-#define AT91C_PA15_EMDC                ((unsigned int) AT91C_PIO_PA15) /* Ethernet MAC Management Data Clock */
-#define AT91C_PIO_PA14         ((unsigned int) 1 << 14)        /* Pin Controlled by PA14 */
-#define AT91C_PA14_ERXER       ((unsigned int) AT91C_PIO_PA14) /* Ethernet MAC Receive Error */
-#define AT91C_PIO_PA13         ((unsigned int) 1 << 13)        /* Pin Controlled by PA13 */
-#define AT91C_PA13_ERX1                ((unsigned int) AT91C_PIO_PA13) /* Ethernet MAC Receive Data 1 */
-#define AT91C_PIO_PA12         ((unsigned int) 1 << 12)        /* Pin Controlled by PA12 */
-#define AT91C_PA12_ERX0                ((unsigned int) AT91C_PIO_PA12) /* Ethernet MAC Receive Data 0 */
-#define AT91C_PIO_PA11         ((unsigned int) 1 << 11)        /* Pin Controlled by PA11 */
-#define AT91C_PA11_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PA11) /* Ethernet MAC Carrier Sense/Carrier Sense and Data Valid */
-#define AT91C_PIO_PA10         ((unsigned int) 1 << 10)        /* Pin Controlled by PA10 */
-#define AT91C_PA10_ETX1                ((unsigned int) AT91C_PIO_PA10) /* Ethernet MAC Transmit Data 1 */
-#define AT91C_PIO_PA9          ((unsigned int) 1 <<  9)        /* Pin Controlled by PA9 */
-#define AT91C_PA9_ETX0         ((unsigned int) AT91C_PIO_PA9)  /* Ethernet MAC Transmit Data 0 */
-#define AT91C_PIO_PA8          ((unsigned int) 1 <<  8)        /* Pin Controlled by PA8 */
-#define AT91C_PA8_ETXEN                ((unsigned int) AT91C_PIO_PA8)  /* Ethernet MAC Transmit Enable */
-#define AT91C_PIO_PA7          ((unsigned int) 1 <<  7)        /* Pin Controlled by PA7 */
-#define AT91C_PA7_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PA7)  /* Ethernet MAC Transmit Clock/Reference Clock */
-
-#define AT91C_PIO_PB0          ((unsigned int) 1 <<  0)        /* Pin Controlled by PB3 */
-#define AT91C_PIO_PB1          ((unsigned int) 1 <<  1)        /* Pin Controlled by PB3 */
-#define AT91C_PIO_PB2          ((unsigned int) 1 <<  2)        /* Pin Controlled by PB3 */
-#define AT91C_PIO_PB3          ((unsigned int) 1 <<  3)        /* Pin Controlled by PB3 */
-#define AT91C_PIO_PB4          ((unsigned int) 1 <<  4)        /* Pin Controlled by PB4 */
-#define AT91C_PIO_PB5          ((unsigned int) 1 <<  5)        /* Pin Controlled by PB5 */
-#define AT91C_PIO_PB6          ((unsigned int) 1 <<  6)        /* Pin Controlled by PB6 */
-#define AT91C_PIO_PB7          ((unsigned int) 1 <<  7)        /* Pin Controlled by PB7 */
-#define AT91C_PIO_PB22         ((unsigned int) 1 << 22)        /* Pin Controlled by PB22 */
-#define AT91C_PIO_PB25         ((unsigned int) 1 << 25)        /* Pin Controlled by PB25 */
-#define AT91C_PB25_DSR1                ((unsigned int) AT91C_PIO_PB25) /* USART 1 Data Set ready */
-#define AT91C_PB25_EF100       ((unsigned int) AT91C_PIO_PB25) /* Ethernet MAC Force 100 Mbits */
-#define AT91C_PIO_PB19         ((unsigned int) 1 << 19)        /* Pin Controlled by PB19 */
-#define AT91C_PB19_DTR1                ((unsigned int) AT91C_PIO_PB19) /* USART 1 Data Terminal ready */
-#define AT91C_PB19_ERXCK       ((unsigned int) AT91C_PIO_PB19) /* Ethernet MAC Receive Clock */
-#define AT91C_PIO_PB18         ((unsigned int) 1 << 18)        /* Pin Controlled by PB18 */
-#define AT91C_PB18_RI1         ((unsigned int) AT91C_PIO_PB18) /* USART 1 Ring Indicator */
-#define AT91C_PB18_ECOL                ((unsigned int) AT91C_PIO_PB18) /* Ethernet MAC Collision Detected */
-#define AT91C_PIO_PB17         ((unsigned int) 1 << 17)        /* Pin Controlled by PB17 */
-#define AT91C_PB17_RF2         ((unsigned int) AT91C_PIO_PB17) /* SSC Receive Frame Sync 2 */
-#define AT91C_PB17_ERXDV       ((unsigned int) AT91C_PIO_PB17) /* Ethernet MAC Receive Data Valid */
-#define AT91C_PIO_PB16         ((unsigned int) 1 << 16)        /* Pin Controlled by PB16 */
-#define AT91C_PB16_RK2         ((unsigned int) AT91C_PIO_PB16) /* SSC Receive Clock 2 */
-#define AT91C_PB16_ERX3                ((unsigned int) AT91C_PIO_PB16) /* Ethernet MAC Receive Data 3 */
-#define AT91C_PIO_PB15         ((unsigned int) 1 << 15)        /* Pin Controlled by PB15 */
-#define AT91C_PB15_RD2         ((unsigned int) AT91C_PIO_PB15) /* SSC Receive Data 2 */
-#define AT91C_PB15_ERX2                ((unsigned int) AT91C_PIO_PB15) /* Ethernet MAC Receive Data 2 */
-#define AT91C_PIO_PB14         ((unsigned int) 1 << 14)        /* Pin Controlled by PB14 */
-#define AT91C_PB14_TD2         ((unsigned int) AT91C_PIO_PB14) /* SSC Transmit Data 2 */
-#define AT91C_PB14_ETXER       ((unsigned int) AT91C_PIO_PB14) /* Ethernet MAC Transmikt Coding Error */
-#define AT91C_PIO_PB13         ((unsigned int) 1 << 13)        /* Pin Controlled by PB13 */
-#define AT91C_PB13_TK2         ((unsigned int) AT91C_PIO_PB13) /* SSC Transmit Clock 2 */
-#define AT91C_PB13_ETX3                ((unsigned int) AT91C_PIO_PB13) /* Ethernet MAC Transmit Data 3 */
-#define AT91C_PIO_PB12         ((unsigned int) 1 << 12)        /* Pin Controlled by PB12 */
-#define AT91C_PB12_TF2         ((unsigned int) AT91C_PIO_PB12) /* SSC Transmit Frame Sync 2 */
-#define AT91C_PB12_ETX2                ((unsigned int) AT91C_PIO_PB12) /* Ethernet MAC Transmit Data 2 */
-
-#define AT91C_PIOB_BSR         ((AT91_REG *)   0xFFFFF674)     /* (PIOB) Select B Register */
-#define AT91C_PIOB_PDR         ((AT91_REG *)   0xFFFFF604)     /* (PIOB) PIO Disable Register */
-
-#define AT91C_EBI_CS3A_SMC_SmartMedia  ((unsigned int) 0x1 <<  3) /* (EBI) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated. */
-#define AT91C_SMC2_ACSS_STANDARD       ((unsigned int) 0x0 << 16) /* (SMC2) Standard, asserted at the beginning of the access and deasserted at the end. */
-#define AT91C_SMC2_DBW_8       ((unsigned int) 0x2 << 13) /* (SMC2) 8-bit. */
-#define AT91C_SMC2_WSEN                ((unsigned int) 0x1 <<  7) /* (SMC2) Wait State Enable */
-#define AT91C_PIOC_ASR         ((AT91_REG *)   0xFFFFF870) /* (PIOC) Select A Register */
-#define AT91C_PIOC_SODR                ((AT91_REG *)   0xFFFFF830) /* (PIOC) Set Output Data Register */
-#define AT91C_PIOC_CODR                ((AT91_REG *)   0xFFFFF834) /* (PIOC) Clear Output Data Register */
-#define AT91C_PIOC_PDSR                ((AT91_REG *)   0xFFFFF83C) /* (PIOC) Pin Data Status Register */
-
-#define AT91C_BASE_AIC         ((AT91PS_AIC)   0xFFFFF000) /* (AIC) Base Address */
-#define AT91C_BASE_DBGU                ((AT91PS_DBGU)  0xFFFFF200) /* (DBGU) Base Address */
-#define AT91C_BASE_PIOA                ((AT91PS_PIO)   0xFFFFF400) /* (PIOA) Base Address */
-#define AT91C_BASE_PIOB                ((AT91PS_PIO)   0xFFFFF600) /* (PIOB) Base Address */
-#define AT91C_BASE_PIOC                ((AT91PS_PIO)   0xFFFFF800) /* (PIOC) Base Address */
-#define AT91C_BASE_PIOD                ((AT91PS_PIO)   0xFFFFFA00) /* (PIOC) Base Address */
-#define AT91C_BASE_PMC         ((AT91PS_PMC)   0xFFFFFC00) /* (PMC) Base Address */
-#if    0
-#define AT91C_BASE_ST          ((AT91PS_ST)    0xFFFFFD00) /* (PMC) Base Address */
-#define AT91C_BASE_RTC         ((AT91PS_RTC)   0xFFFFFE00) /* (PMC) Base Address */
-#define AT91C_BASE_MC          ((AT91PS_MC)    0xFFFFFF00) /* (PMC) Base Address */
-#endif
-
-#define AT91C_BASE_TC0         ((AT91PS_TC)    0xFFFA0000) /* (TC0) Base Address */
-#define AT91C_BASE_TC1         ((AT91PS_TC)    0xFFFA4000) /* (TC0) Base Address */
-#if    0
-#define AT91C_BASE_UDP         ((AT91PS_UDP)   0xFFFB0000) /* (TC0) Base Address */
-#define AT91C_BASE_MCI         ((AT91PS_MCI)   0xFFFB4000) /* (TC0) Base Address */
-#define AT91C_BASE_TWI         ((AT91PS_TWI)   0xFFFB8000) /* (TC0) Base Address */
-#endif
-#define AT91C_BASE_EMAC                ((AT91PS_EMAC)  0xFFFBC000) /* (EMAC) Base Address */
-#define AT91C_BASE_US0         ((AT91PS_USART) 0xFFFC0000) /* (US0) Base Address */
-#define AT91C_BASE_US1         ((AT91PS_USART) 0xFFFC4000) /* (US1) Base Address */
-#define AT91C_BASE_US2         ((AT91PS_USART) 0xFFFC8000) /* (US1) Base Address */
-#define AT91C_BASE_US3         ((AT91PS_USART) 0xFFFCC000) /* (US1) Base Address */
-#define AT91C_BASE_SPI         ((AT91PS_SPI)   0xFFFE0000) /* (SPI) Base Address */
-
-#define AT91C_BASE_CKGR                ((AT91PS_CKGR)  0xFFFFFC20) /* (CKGR) Base Address */
-#define AT91C_EBI_CSA          ((AT91_REG *)   0xFFFFFF60) /* (EBI) Chip Select Assignment Register */
-#define AT91C_BASE_SMC2                ((AT91PS_SMC2)  0xFFFFFF70) /* (SMC2) Base Address */
-#define AT91C_TCB0_BMR         ((AT91_REG *)   0xFFFA00C4) /* (TCB0) TC Block Mode Register */
-#define AT91C_TCB0_BCR         ((AT91_REG *)   0xFFFA00C0) /* (TCB0) TC Block Control Register */
-#define AT91C_PIOC_PDR         ((AT91_REG *)   0xFFFFF804) /* (PIOC) PIO Disable Register */
-#define AT91C_PIOC_PER         ((AT91_REG *)   0xFFFFF800) /* (PIOC) PIO Enable Register */
-#define AT91C_PIOC_ODR         ((AT91_REG *)   0xFFFFF814) /* (PIOC) Output Disable Registerr */
-#define AT91C_PIOB_PER         ((AT91_REG *)   0xFFFFF600) /* (PIOB) PIO Enable Register */
-#define AT91C_PIOB_ODR         ((AT91_REG *)   0xFFFFF614) /* (PIOB) Output Disable Registerr */
-#define AT91C_PIOB_PDSR                ((AT91_REG *)   0xFFFFF63C) /* (PIOB) Pin Data Status Register */
-
-#else
-/* flash */
-#define AT91C_MC_PUIA          0xFFFFFF10
-#define AT91C_MC_PUP           0xFFFFFF50
-#define AT91C_MC_PUER          0xFFFFFF54
-#define AT91C_MC_ASR           0xFFFFFF04
-#define AT91C_MC_AASR          0xFFFFFF08
-#define AT91C_EBI_CFGR         0xFFFFFF64
-#define AT91C_SMC_CSR0         0xFFFFFF70
-
-/* clocks */
-#define AT91C_PLLAR            0xFFFFFC28
-#define AT91C_PLLBR            0xFFFFFC2C
-#define AT91C_MCKR             0xFFFFFC30
-
-#define AT91C_BASE_CKGR                0xFFFFFC20
-#define AT91C_CKGR_MOR         0
-
-/* sdram */
-#define AT91C_PIOC_ASR         0xFFFFF870
-#define AT91C_PIOC_BSR         0xFFFFF874
-#define AT91C_PIOC_PDR         0xFFFFF804
-#define AT91C_EBI_CSA          0xFFFFFF60
-#define AT91C_SDRC_CR          0xFFFFFF98
-#define AT91C_SDRC_MR          0xFFFFFF90
-#define AT91C_SDRC_TR          0xFFFFFF94
-
-#endif /* __ASSEMBLY__ */
-#endif /* AT91RM9200_H */

diff --git a/arch/arm/include/asm/arch-at91rm9200/hardware.h b/arch/arm/include/asm/arch-at91rm9200/hardware.h
deleted file mode 100644 (file)
index b868e38..0000000
--- a/arch/arm/include/asm/arch-at91rm9200/hardware.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * linux/include/asm-arm/arch-at91/hardware.h
- *
- *  Copyright (C) 2003 SAN People
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#include <asm/sizes.h>
-
-#ifndef __ASSEMBLY__
-#include "AT91RM9200.h"
-#endif
-
-/* Virtual and Physical base address for system peripherals */
-#define AT91_SYS_BASE          0xFFFFF000 /*4K */
-
-/* Virtual and Physical base addresses of user peripherals */
-#define AT91_SPI_BASE          0xFFFE0000 /*16K */
-#define AT91_SSC2_BASE         0xFFFD8000 /*16K */
-#define AT91_SSC1_BASE         0xFFFD4000 /*16K */
-#define AT91_SSC0_BASE         0xFFFD0000 /*16K */
-#define AT91_USART3_BASE       0xFFFCC000 /*16K */
-#define AT91_USART2_BASE       0xFFFC8000 /*16K */
-#define AT91_USART1_BASE       0xFFFC4000 /*16K */
-#define AT91_USART0_BASE       0xFFFC0000 /*16K */
-#define AT91_EMAC_BASE         0xFFFBC000 /*16K */
-#define AT91_TWI_BASE          0xFFFB8000 /*16K */
-#define AT91_MCI_BASE          0xFFFB4000 /*16K */
-#define AT91_UDP_BASE          0xFFFB0000 /*16K */
-#define AT91_TCB1_BASE         0xFFFA4000 /*16K */
-#define AT91_TCB0_BASE         0xFFFA0000 /*16K */
-
-#define AT91_USB_HOST_BASE     0x00300000
-
-/*
- * Where in virtual memory the IO devices (timers, system controllers
- * and so on)
- */
-#define AT91_IO_BASE           0xF0000000      /* Virt/Phys Address of IO */
-
-/* FLASH */
-#define AT91_FLASH_BASE                0x10000000      /* NCS0 */
-
-/* SDRAM */
-#define AT91_SDRAM_BASE                0x20000000      /* NCS1 */
-
-/* SmartMedia */
-#define AT91_SMARTMEDIA_BASE   0x40000000      /* NCS3 */
-
-/* Definition of interrupt priority levels */
-#define AT91C_AIC_PRIOR_0 AT91C_AIC_PRIOR_LOWEST
-#define AT91C_AIC_PRIOR_1 ((unsigned int) 0x1)
-#define AT91C_AIC_PRIOR_2 ((unsigned int) 0x2)
-#define AT91C_AIC_PRIOR_3 ((unsigned int) 0x3)
-#define AT91C_AIC_PRIOR_4 ((unsigned int) 0x4)
-#define AT91C_AIC_PRIOR_5 ((unsigned int) 0x5)
-#define AT91C_AIC_PRIOR_6 ((unsigned int) 0x6)
-#define AT91C_AIC_PRIOR_7 AT91C_AIC_PRIOR_HIGEST
-
-#endif