lart SA1100
dnp1110 SA1110
+Minkyu Kang <mk7.kang@samsung.com>
+
+ SMDKC100 ARM CORTEX-A8 (S5PC100 SoC)
+
-------------------------------------------------------------------------
Unknown / orphaned boards:
omap3_pandora \
omap3_zoom1 \
omap3_zoom2 \
+ smdkc100 \
"
#########################################################################
omap3_zoom2_config : unconfig
@$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom2 logicpd omap3
+smdkc100_config: unconfig
+ @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 smdkc100 samsung s5pc1xx
+
#########################################################################
## XScale Systems
#########################################################################
int board_init(void)
{
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_clock_power * const clk_power =
+ s3c24x0_get_base_clock_power();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* to reduce PLL lock time, adjust the LOCKTIME register */
clk_power->LOCKTIME = 0xFFFFFF;
void
nand_init(void)
{
- S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+ struct s3c2410_nand * const nand = s3c2410_get_base_nand();
NF_Init();
#ifdef DEBUG
static u8 Get_PLD_ID(void)
{
- VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
+ VCMA9_PLD * const pld = VCMA9_get_base_PLD();
return(pld->ID);
}
static u8 Get_PLD_BOARD(void)
{
- VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
+ VCMA9_PLD * const pld = VCMA9_get_base_PLD();
return(pld->BOARD);
}
static u8 Get_PLD_SDRAM(void)
{
- VCMA9_PLD * const pld = VCMA9_GetBase_PLD();
+ VCMA9_PLD * const pld = VCMA9_get_base_PLD();
return(pld->SDRAM);
}
static inline void NF_Conf(u16 conf)
{
- S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+ struct s3c2410_nand * const nand = s3c2410_get_base_nand();
nand->NFCONF = conf;
}
static inline void NF_Cmd(u8 cmd)
{
- S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+ struct s3c2410_nand * const nand = s3c2410_get_base_nand();
nand->NFCMD = cmd;
}
static inline void NF_Addr(u8 addr)
{
- S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+ struct s3c2410_nand * const nand = s3c2410_get_base_nand();
nand->NFADDR = addr;
}
static inline void NF_SetCE(NFCE_STATE s)
{
- S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+ struct s3c2410_nand * const nand = s3c2410_get_base_nand();
switch (s) {
case NFCE_LOW:
static inline void NF_WaitRB(void)
{
- S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+ struct s3c2410_nand * const nand = s3c2410_get_base_nand();
while (!(nand->NFSTAT & (1<<0)));
}
static inline void NF_Write(u8 data)
{
- S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+ struct s3c2410_nand * const nand = s3c2410_get_base_nand();
nand->NFDATA = data;
}
static inline u8 NF_Read(void)
{
- S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+ struct s3c2410_nand * const nand = s3c2410_get_base_nand();
return(nand->NFDATA);
}
static inline void NF_Init_ECC(void)
{
- S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+ struct s3c2410_nand * const nand = s3c2410_get_base_nand();
nand->NFCONF |= (1<<12);
}
static inline u32 NF_Read_ECC(void)
{
- S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+ struct s3c2410_nand * const nand = s3c2410_get_base_nand();
return(nand->NFECC);
}
} /*__attribute__((__packed__))*/ VCMA9_PLD;
#define VCMA9_PLD_BASE 0x2C000100
-static inline VCMA9_PLD * VCMA9_GetBase_PLD(void)
+static inline VCMA9_PLD *VCMA9_get_base_PLD(void)
{
return (VCMA9_PLD * const)VCMA9_PLD_BASE;
}
int board_init (void)
{
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_clock_power * const clk_power =
+ s3c24x0_get_base_clock_power();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* memory and cpu-speed are setup before relocation */
/* change the clock to be 50 MHz 1:1:1 */
int board_init (void)
{
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_clock_power * const clk_power =
+ s3c24x0_get_base_clock_power();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* to reduce PLL lock time, adjust the LOCKTIME register */
clk_power->LOCKTIME = 0xFFFFFF;
--- /dev/null
+#
+# (C) Copyright 2000, 2001, 2002
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).a
+
+COBJS-y := smdkc100.o
+COBJS-$(CONFIG_SAMSUNG_ONENAND) += onenand.o
+SOBJS := lowlevel_init.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS-y))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(SOBJS) $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(SOBJS) $(OBJS)
+
+clean:
+ rm -f $(SOBJS) $(OBJS)
+
+distclean: clean
+ rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+#
+# Copyright (C) 2008 # Samsung Elecgtronics
+# Kyungmin Park <kyungmin.park@samsung.com>
+#
+
+# On S5PC100 we use the 128 MiB OneDRAM bank at
+#
+# 0x30000000 to 0x35000000 (80MiB)
+# 0x38000000 to 0x40000000 (128MiB)
+#
+# On S5PC110 we use the 128 MiB OneDRAM bank at
+#
+# 0x30000000 to 0x35000000 (80MiB)
+# 0x40000000 to 0x48000000 (128MiB)
+#
+TEXT_BASE = 0x34800000
--- /dev/null
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/power.h>
+
+/*
+ * Register usages:
+ *
+ * r5 has zero always
+ */
+
+_TEXT_BASE:
+ .word TEXT_BASE
+
+ .globl lowlevel_init
+lowlevel_init:
+ mov r9, lr
+
+ /* r5 has always zero */
+ mov r5, #0
+
+ ldr r8, =S5PC100_GPIO_BASE
+
+ /* Disable Watchdog */
+ ldr r0, =S5PC100_WATCHDOG_BASE @0xEA200000
+ orr r0, r0, #0x0
+ str r5, [r0]
+
+#ifndef CONFIG_ONENAND_IPL
+ /* setting SRAM */
+ ldr r0, =S5PC100_SROMC_BASE
+ ldr r1, =0x9
+ str r1, [r0]
+#endif
+
+ /* S5PC100 has 3 groups of interrupt sources */
+ ldr r0, =S5PC100_VIC0_BASE @0xE4000000
+ ldr r1, =S5PC100_VIC1_BASE @0xE4000000
+ ldr r2, =S5PC100_VIC2_BASE @0xE4000000
+
+ /* Disable all interrupts (VIC0, VIC1 and VIC2) */
+ mvn r3, #0x0
+ str r3, [r0, #0x14] @INTENCLEAR
+ str r3, [r1, #0x14] @INTENCLEAR
+ str r3, [r2, #0x14] @INTENCLEAR
+
+#ifndef CONFIG_ONENAND_IPL
+ /* Set all interrupts as IRQ */
+ str r5, [r0, #0xc] @INTSELECT
+ str r5, [r1, #0xc] @INTSELECT
+ str r5, [r2, #0xc] @INTSELECT
+
+ /* Pending Interrupt Clear */
+ str r5, [r0, #0xf00] @INTADDRESS
+ str r5, [r1, #0xf00] @INTADDRESS
+ str r5, [r2, #0xf00] @INTADDRESS
+#endif
+
+#ifndef CONFIG_ONENAND_IPL
+ /* for UART */
+ bl uart_asm_init
+
+ /* for TZPC */
+ bl tzpc_asm_init
+#endif
+
+#ifdef CONFIG_ONENAND_IPL
+ /* init system clock */
+ bl system_clock_init
+
+ bl mem_ctrl_asm_init
+
+ /* Wakeup support. Don't know if it's going to be used, untested. */
+ ldr r0, =S5PC100_RST_STAT
+ ldr r1, [r0]
+ bic r1, r1, #0xfffffff7
+ cmp r1, #0x8
+ beq wakeup_reset
+#endif
+
+1:
+ mov lr, r9
+ mov pc, lr
+
+#ifdef CONFIG_ONENAND_IPL
+wakeup_reset:
+
+ /* Clear wakeup status register */
+ ldr r0, =S5PC100_WAKEUP_STAT
+ ldr r1, [r0]
+ str r1, [r0]
+
+ /* Load return address and jump to kernel */
+ ldr r0, =S5PC100_INFORM0
+
+ /* r1 = physical address of s5pc100_cpu_resume function */
+ ldr r1, [r0]
+
+ /* Jump to kernel (sleep.S) */
+ mov pc, r1
+ nop
+ nop
+#endif
+
+/*
+ * system_clock_init: Initialize core clock and bus clock.
+ * void system_clock_init(void)
+ */
+system_clock_init:
+ ldr r8, =S5PC1XX_CLOCK_BASE @ 0xE0100000
+
+ /* Set Clock divider */
+ ldr r1, =0x00011110
+ str r1, [r8, #0x304]
+ ldr r1, =0x1
+ str r1, [r8, #0x308]
+ ldr r1, =0x00011301
+ str r1, [r8, #0x300]
+
+ /* Set Lock Time */
+ ldr r1, =0xe10 @ Locktime : 0xe10 = 3600
+ str r1, [r8, #0x000] @ APLL_LOCK
+ str r1, [r8, #0x004] @ MPLL_LOCK
+ str r1, [r8, #0x008] @ EPLL_LOCK
+ str r1, [r8, #0x00C] @ HPLL_LOCK
+
+ /* APLL_CON */
+ ldr r1, =0x81bc0400 @ SDIV 0, PDIV 4, MDIV 444 (1332MHz)
+ str r1, [r8, #0x100]
+ /* MPLL_CON */
+ ldr r1, =0x80590201 @ SDIV 1, PDIV 2, MDIV 89 (267MHz)
+ str r1, [r8, #0x104]
+ /* EPLL_CON */
+ ldr r1, =0x80870303 @ SDIV 3, PDIV 3, MDIV 135 (67.5MHz)
+ str r1, [r8, #0x108]
+ /* HPLL_CON */
+ ldr r1, =0x80600603
+ str r1, [r8, #0x10C]
+
+ /* Set Source Clock */
+ ldr r1, =0x1111 @ A, M, E, HPLL Muxing
+ str r1, [r8, #0x200] @ CLK_SRC0
+
+ ldr r1, =0x1000001 @ Uart Clock & CLK48M Muxing
+ str r1, [r8, #0x204] @ CLK_SRC1
+
+ ldr r1, =0x9000 @ ARMCLK/4
+ str r1, [r8, #0x400] @ CLK_OUT
+
+ /* wait at least 200us to stablize all clock */
+ mov r2, #0x10000
+1: subs r2, r2, #1
+ bne 1b
+
+ mov pc, lr
+
+#ifndef CONFIG_ONENAND_IPL
+/*
+ * uart_asm_init: Initialize UART's pins
+ */
+uart_asm_init:
+ mov r0, r8
+ ldr r1, =0x22222222
+ str r1, [r0, #0x0] @ GPA0_CON
+ ldr r1, =0x00022222
+ str r1, [r0, #0x20] @ GPA1_CON
+
+ mov pc, lr
+
+/*
+ * tzpc_asm_init: Initialize TZPC
+ */
+tzpc_asm_init:
+ ldr r0, =0xE3800000
+ mov r1, #0x0
+ str r1, [r0]
+ mov r1, #0xff
+ str r1, [r0, #0x804]
+ str r1, [r0, #0x810]
+
+ ldr r0, =0xE2800000
+ str r1, [r0, #0x804]
+ str r1, [r0, #0x810]
+ str r1, [r0, #0x81C]
+
+ ldr r0, =0xE2900000
+ str r1, [r0, #0x804]
+ str r1, [r0, #0x810]
+
+ mov pc, lr
+#endif
--- /dev/null
+/*
+ * Originates from Samsung's u-boot 1.1.6 port to S5PC1xx
+ *
+ * Copyright (C) 2009 Samsung Electrnoics
+ * Inki Dae <inki.dae@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <config.h>
+
+ .globl mem_ctrl_asm_init
+mem_ctrl_asm_init:
+ ldr r6, =S5PC100_DMC_BASE @ 0xE6000000
+
+ /* DLL parameter setting */
+ ldr r1, =0x50101000
+ str r1, [r6, #0x018] @ PHYCONTROL0
+ ldr r1, =0xf4
+ str r1, [r6, #0x01C] @ PHYCONTROL1
+ ldr r1, =0x0
+ str r1, [r6, #0x020] @ PHYCONTROL2
+
+ /* DLL on */
+ ldr r1, =0x50101002
+ str r1, [r6, #0x018] @ PHYCONTROL0
+
+ /* DLL start */
+ ldr r1, =0x50101003
+ str r1, [r6, #0x018] @ PHYCONTROL0
+
+ /* Force value locking for DLL off */
+ str r1, [r6, #0x018] @ PHYCONTROL0
+
+ /* DLL off */
+ ldr r1, =0x50101001
+ str r1, [r6, #0x018] @ PHYCONTROL0
+
+ /* auto refresh off */
+ ldr r1, =0xff001010
+ str r1, [r6, #0x000] @ CONCONTROL
+
+ /*
+ * Burst Length 4, 2 chips, 32-bit, LPDDR
+ * OFF: dynamic self refresh, force precharge, dynamic power down off
+ */
+ ldr r1, =0x00212100
+ str r1, [r6, #0x004] @ MEMCONTROL
+
+ /*
+ * Note:
+ * If Bank0 has OneDRAM we place it at 0x2800'0000
+ * So finally Bank1 should address start at at 0x2000'0000
+ */
+ mov r4, #0x0
+
+swap_memory:
+ /*
+ * Bank0
+ * 0x30 -> 0x30000000
+ * 0xf8 -> 0x37FFFFFF
+ * [15:12] 0: Linear
+ * [11:8 ] 2: 9 bits
+ * [ 7:4 ] 2: 14 bits
+ * [ 3:0 ] 2: 4 banks
+ */
+ ldr r1, =0x30f80222
+ /* if r4 is 1, swap the bank */
+ cmp r4, #0x1
+ orreq r1, r1, #0x08000000
+ str r1, [r6, #0x008] @ MEMCONFIG0
+
+ /*
+ * Bank1
+ * 0x38 -> 0x38000000
+ * 0xf8 -> 0x3fFFFFFF
+ * [15:12] 0: Linear
+ * [11:8 ] 2: 9 bits
+ * [ 7:4 ] 2: 14 bits
+ * [ 3:0 ] 2: 4 banks
+ */
+ ldr r1, =0x38f80222
+ /* if r4 is 1, swap the bank */
+ cmp r4, #0x1
+ biceq r1, r1, #0x08000000
+ str r1, [r6, #0x00c] @ MEMCONFIG1
+
+ ldr r1, =0x20000000
+ str r1, [r6, #0x014] @ PRECHCONFIG
+
+ /*
+ * FIXME: Please verify these values
+ * 7.8us * 166MHz %LE %LONG1294(0x50E)
+ * 7.8us * 133MHz %LE %LONG1038(0x40E),
+ * 7.8us * 100MHz %LE %LONG780(0x30C),
+ * 7.8us * 20MHz %LE %LONG156(0x9C),
+ * 7.8us * 10MHz %LE %LONG78(0x4E)
+ */
+ ldr r1, =0x0000050e
+ str r1, [r6, #0x030] @ TIMINGAREF
+
+ /* 166 MHz */
+ ldr r1, =0x0c233287
+ str r1, [r6, #0x034] @ TIMINGROW
+
+ /* twtr=3 twr=2 trtp=3 cl=3 wl=3 rl=3 */
+ ldr r1, =0x32330303
+ str r1, [r6, #0x038] @ TIMINGDATA
+
+ /* tfaw=4 sxsr=0x14 txp=0x14 tcke=3 tmrd=3 */
+ ldr r1, =0x04141433
+ str r1, [r6, #0x03C] @ TIMINGPOWER
+
+ /* chip0 Deselect */
+ ldr r1, =0x07000000
+ str r1, [r6, #0x010] @ DIRECTCMD
+
+ /* chip0 PALL */
+ ldr r1, =0x01000000
+ str r1, [r6, #0x010] @ DIRECTCMD
+
+ /* chip0 REFA */
+ ldr r1, =0x05000000
+ str r1, [r6, #0x010] @ DIRECTCMD
+ /* chip0 REFA */
+ str r1, [r6, #0x010] @ DIRECTCMD
+
+ /* chip0 MRS, CL%LE %LONG3, BL%LE %LONG4 */
+ ldr r1, =0x00000032
+ str r1, [r6, #0x010] @ DIRECTCMD
+
+ /* chip1 Deselect */
+ ldr r1, =0x07100000
+ str r1, [r6, #0x010] @ DIRECTCMD
+
+ /* chip1 PALL */
+ ldr r1, =0x01100000
+ str r1, [r6, #0x010] @ DIRECTCMD
+
+ /* chip1 REFA */
+ ldr r1, =0x05100000
+ str r1, [r6, #0x010] @ DIRECTCMD
+ /* chip1 REFA */
+ str r1, [r6, #0x010] @ DIRECTCMD
+
+ /* chip1 MRS, CL%LE %LONG3, BL%LE %LONG4 */
+ ldr r1, =0x00100032
+ str r1, [r6, #0x010] @ DIRECTCMD
+
+ /* auto refresh on */
+ ldr r1, =0xff002030
+ str r1, [r6, #0x000] @ CONCONTROL
+
+ /* PwrdnConfig */
+ ldr r1, =0x00100002
+ str r1, [r6, #0x028] @ PWRDNCONFIG
+
+ /* BL%LE %LONG */
+ ldr r1, =0xff212100
+ str r1, [r6, #0x004] @ MEMCONTROL
+
+
+ /* Try to test memory area */
+ cmp r4, #0x1
+ beq 1f
+
+ mov r4, #0x1
+ ldr r1, =0x37ffff00
+ str r4, [r1]
+ str r4, [r1, #0x4] @ dummy write
+ ldr r0, [r1]
+ cmp r0, r4
+ bne swap_memory
+
+1:
+ mov pc, lr
+
+ .ltorg
--- /dev/null
+/*
+ * Copyright (C) 2008-2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <linux/mtd/samsung_onenand.h>
+
+#include <onenand_uboot.h>
+
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+void onenand_board_init(struct mtd_info *mtd)
+{
+ struct onenand_chip *this = mtd->priv;
+ struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
+ struct samsung_onenand *onenand;
+ int value;
+
+ this->base = (void *)S5PC100_ONENAND_BASE;
+ onenand = (struct samsung_onenand *)this->base;
+
+ /* D0 Domain memory clock gating */
+ value = readl(&clk->gate_d01);
+ value &= ~(1 << 2); /* CLK_ONENANDC */
+ value |= (1 << 2);
+ writel(value, &clk->gate_d01);
+
+ value = readl(&clk->src0);
+ value &= ~(1 << 24); /* MUX_1nand: 0 from HCLKD0 */
+ value &= ~(1 << 20); /* MUX_HREF: 0 from FIN_27M */
+ writel(value, &clk->src0);
+
+ value = readl(&clk->div1);
+ value &= ~(3 << 16); /* PCLKD1_RATIO */
+ value |= (1 << 16);
+ writel(value, &clk->div1);
+
+ writel(ONENAND_MEM_RESET_COLD, &onenand->mem_reset);
+
+ while (!(readl(&onenand->int_err_stat) & RST_CMP))
+ continue;
+
+ writel(RST_CMP, &onenand->int_err_ack);
+
+ /*
+ * Access_Clock [2:0]
+ * 166 MHz, 134 Mhz : 3
+ * 100 Mhz, 60 Mhz : 2
+ */
+ writel(0x3, &onenand->acc_clock);
+
+ writel(INT_ERR_ALL, &onenand->int_err_mask);
+ writel(1 << 0, &onenand->int_pin_en); /* Enable */
+
+ value = readl(&onenand->int_err_mask);
+ value &= ~RDY_ACT;
+ writel(value, &onenand->int_err_mask);
+
+ s3c_onenand_init(mtd);
+}
--- /dev/null
+/*
+ * Copyright (C) 2008-2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ gd->bd->bi_arch_number = MACH_TYPE_SMDKC100;
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[0].size = get_ram_size((long *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
+
+ return 0;
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+int checkboard(void)
+{
+ printf("Board:\tSMDKC100\n");
+ return 0;
+}
+#endif
int board_init (void)
{
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_clock_power * const clk_power =
+ s3c24x0_get_base_clock_power();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* to reduce PLL lock time, adjust the LOCKTIME register */
clk_power->LOCKTIME = 0xFFFFFF;
void nand_init(void)
{
- S3C2410_NAND * const nand = S3C2410_GetBase_NAND();
+ struct s3c2410_nand * const nand = s3c2410_get_base_nand();
NF_Init();
#ifdef DEBUG
{
int j = 1000; /* timeout value for wait loop in us */
int result;
- S3C2400_ADC *padc;
+ struct s3c2400_adc *padc;
- padc = S3C2400_GetBase_ADC();
+ padc = s3c2400_get_base_adc();
channel &= 0x7;
adc_init ();
static void adc_init (void)
{
- S3C2400_ADC *padc;
+ struct s3c2400_adc *padc;
- padc = S3C2400_GetBase_ADC();
+ padc = s3c2400_get_base_adc();
padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */
padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
static void led_set (unsigned int state)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
led_init ();
static void led_init (void)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* configure GPA12 as output and set to High -> LED off */
gpio->PACON &= ~(1 << 12);
static void rs485_setbrg (void)
{
- S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
+ struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
int i;
unsigned int reg = 0;
static void rs485_cfgio (void)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
gpio->PFCON &= ~(0x3 << 2);
gpio->PFCON |= (0x2 << 2); /* configure GPF1 as RXD1 */
*/
int rs485_getc (void)
{
- S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
+ struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
/* wait for character to arrive */
while (!(uart->UTRSTAT & 0x1));
*/
void rs485_putc (const char c)
{
- S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
+ struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
/* wait for room in the tx FIFO */
while (!(uart->UTRSTAT & 0x2));
*/
int rs485_tstc (void)
{
- S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR);
+ struct s3c24x0_uart * const uart = s3c24x0_get_base_uart(UART_NR);
return uart->UTRSTAT & 0x1;
}
static void set_rs485de(unsigned char rs485de_state)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* This is on PORT A bit 11 */
if(rs485de_state)
#if defined(CONFIG_VFD)
extern int vfd_init_clocks(void);
#endif
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_clock_power * const clk_power =
+ s3c24x0_get_base_clock_power();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* memory and cpu-speed are setup before relocation */
#ifdef CONFIG_TRAB_50MHZ
static inline void SET_CS_TOUCH(void)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
gpio->PDDAT &= 0x5FF;
}
static inline void CLR_CS_TOUCH(void)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
gpio->PDDAT |= 0x200;
}
static void spi_init(void)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
- S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+ struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
int i;
/* Configure I/O ports. */
static void wait_transmit_done(void)
{
- S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+ struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */
}
static void tsc2000_write(unsigned int page, unsigned int reg,
unsigned int data)
{
- S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+ struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
unsigned int command;
SET_CS_TOUCH();
{
int j = 1000; /* timeout value for wait loop in us */
int result;
- S3C2400_ADC *padc;
+ struct s3c2400_adc *padc;
- padc = S3C2400_GetBase_ADC();
+ padc = s3c2400_get_base_adc();
channel &= 0x7;
padc->ADCCON &= ~ADC_STDBM; /* select normal mode */
static void adc_init (void)
{
- S3C2400_ADC *padc;
+ struct s3c2400_adc *padc;
- padc = S3C2400_GetBase_ADC();
+ padc = s3c2400_get_base_adc();
padc->ADCCON &= ~(0xff << 6); /* clear prescaler bits */
padc->ADCCON |= ((65 << 6) | ADC_PRSCEN); /* set prescaler */
{
int result;
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* configure GPE7 as input */
gpio->PECON &= ~(0x3 << (2 * 7));
int i;
long int pcup_old, pccon_old;
int vfd_board_id;
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* try to red vfd board id from the value defined by pull-ups */
{
int counter;
- S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_timers * const timers = s3c24x0_get_base_timers();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* set prescaler for timer 2, 3 and 4 */
timers->TCFG0 &= ~0xFF00;
int do_led (char **argv)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* configure PC14 and PC15 as output */
gpio->PCCON &= ~(0xF << 28);
int do_full_bridge (char **argv)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* configure PD5 and PD6 as output */
gpio->PDCON &= ~((0x3 << 5*2) | (0x3 << 6*2));
int do_motor (char **argv)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
/* Configure I/O port */
gpio->PGCON &= ~(0x3 << 0);
int do_pwm (char **argv)
{
int counter;
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
- S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+ struct s3c24x0_timers * const timers = s3c24x0_get_base_timers();
if (strcmp (argv[2], "on") == 0) {
/* configure pin GPD8 as TOUT3 */
#include <common.h>
#include <s3c2400.h>
+#include <asm/io.h>
#include <div64.h>
#include "tsc2000.h"
void tsc2000_spi_init(void)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
- S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+ struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
int i;
/* Configure I/O ports. */
void spi_wait_transmit_done(void)
{
- S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+ struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
while (!(spi->ch[0].SPSTA & 0x01)); /* wait until transfer is done */
}
void tsc2000_write(unsigned short reg, unsigned short data)
{
- S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+ struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
unsigned int command;
SET_CS_TOUCH();
unsigned short tsc2000_read (unsigned short reg)
{
unsigned short command, data;
- S3C24X0_SPI * const spi = S3C24X0_GetBase_SPI();
+ struct s3c24x0_spi * const spi = s3c24x0_get_base_spi();
SET_CS_TOUCH();
command = 0x8000 | reg;
void tsc2000_set_mux (unsigned int channel)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
CLR_MUX1_ENABLE; CLR_MUX2_ENABLE;
CLR_MUX3_ENABLE; CLR_MUX4_ENABLE;
void tsc2000_set_range (unsigned int range)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
switch (range) {
case 1:
void tsc2000_reg_init (void)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
tsc2000_write(TSC2000_REG_ADC, 0x2036);
tsc2000_write(TSC2000_REG_REF, 0x0011);
static inline void SET_CS_TOUCH(void)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
gpio->PDDAT &= 0x5FF;
}
static inline void CLR_CS_TOUCH(void)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
gpio->PDDAT |= 0x200;
}
{
int i;
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
- S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
- S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
+ struct s3c24x0_timers * const timers = s3c24x0_get_base_timers();
+ struct s3c24x0_lcd * const lcd = s3c24x0_get_base_lcd();
/* try to determine display type from the value
* defined by pull-ups
*/
int drv_vfd_init(void)
{
- S3C24X0_LCD * const lcd = S3C24X0_GetBase_LCD();
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_lcd * const lcd = s3c24x0_get_base_lcd();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
char *tmp;
ulong palette;
static int vfd_init_done = 0;
*/
void disable_vfd (void)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
VFD_DISABLE;
gpio->PDCON &= ~0xC;
#else
#error "CONFIG_SERIAL? missing."
#endif
+#elif defined(CONFIG_S5PC1XX)
+#if defined(CONFIG_SERIAL0)
+ return &s5pc1xx_serial0_device;
+#elif defined(CONFIG_SERIAL1)
+ return &s5pc1xx_serial1_device;
+#elif defined(CONFIG_SERIAL2)
+ return &s5pc1xx_serial2_device;
+#elif defined(CONFIG_SERIAL3)
+ return &s5pc1xx_serial3_device;
+#else
+#error "CONFIG_SERIAL? missing."
+#endif
#elif defined(CONFIG_OMAP3_ZOOM2)
return ZOOM2_DEFAULT_SERIAL_DEVICE;
#else
serial_register(&s3c24xx_serial0_device);
serial_register(&s3c24xx_serial1_device);
serial_register(&s3c24xx_serial2_device);
+#endif
+#if defined(CONFIG_S5PC1XX)
+ serial_register(&s5pc1xx_serial0_device);
+ serial_register(&s5pc1xx_serial1_device);
+ serial_register(&s5pc1xx_serial2_device);
+ serial_register(&s5pc1xx_serial3_device);
#endif
serial_assign (default_serial_console ()->name);
}
void do_irq (struct pt_regs *pt_regs)
{
- S3C24X0_INTERRUPT * irq = S3C24X0_GetBase_INTERRUPT();
- u_int32_t intpnd = irq->INTPND;
+ struct s3c24x0_interrupt *irq = s3c24x0_get_base_interrupt();
+ u_int32_t intpnd = readl(&irq->INTPND);
}
#include <common.h>
#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
+#include <asm/io.h>
+
#if defined(CONFIG_S3C2400)
#include <s3c2400.h>
#elif defined(CONFIG_S3C2410)
static ulong get_PLLCLK(int pllreg)
{
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- ulong r, m, p, s;
+ struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+ ulong r, m, p, s;
- if (pllreg == MPLL)
- r = clk_power->MPLLCON;
- else if (pllreg == UPLL)
- r = clk_power->UPLLCON;
- else
- hang();
+ if (pllreg == MPLL)
+ r = readl(&clk_power->MPLLCON);
+ else if (pllreg == UPLL)
+ r = readl(&clk_power->UPLLCON);
+ else
+ hang();
- m = ((r & 0xFF000) >> 12) + 8;
- p = ((r & 0x003F0) >> 4) + 2;
- s = r & 0x3;
+ m = ((r & 0xFF000) >> 12) + 8;
+ p = ((r & 0x003F0) >> 4) + 2;
+ s = r & 0x3;
- return((CONFIG_SYS_CLK_FREQ * m) / (p << s));
+ return (CONFIG_SYS_CLK_FREQ * m) / (p << s);
}
/* return FCLK frequency */
ulong get_FCLK(void)
{
- return(get_PLLCLK(MPLL));
+ return get_PLLCLK(MPLL);
}
/* return HCLK frequency */
ulong get_HCLK(void)
{
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+ struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
- return((clk_power->CLKDIVN & 0x2) ? get_FCLK()/2 : get_FCLK());
+ return (readl(&clk_power->CLKDIVN) & 2) ? get_FCLK() / 2 : get_FCLK();
}
/* return PCLK frequency */
ulong get_PCLK(void)
{
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+ struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
- return((clk_power->CLKDIVN & 0x1) ? get_HCLK()/2 : get_HCLK());
+ return (readl(&clk_power->CLKDIVN) & 1) ? get_HCLK() / 2 : get_HCLK();
}
/* return UCLK frequency */
ulong get_UCLK(void)
{
- return(get_PLLCLK(UPLL));
+ return get_PLLCLK(UPLL);
}
-#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
+#endif /* defined(CONFIG_S3C2400) ||
+ defined (CONFIG_S3C2410) ||
+ defined (CONFIG_TRAB) */
*/
#include <common.h>
-#if defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB)
+#if defined(CONFIG_S3C2400) || \
+ defined(CONFIG_S3C2410) || \
+ defined(CONFIG_TRAB)
+
+#include <asm/io.h>
#if defined(CONFIG_S3C2400)
#include <s3c2400.h>
#endif
int timer_load_val = 0;
+static ulong timer_clk;
/* macro to read the 16 bit timer */
static inline ulong READ_TIMER(void)
{
- S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
+ struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
- return (timers->TCNTO4 & 0xffff);
+ return readl(&timers->TCNTO4) & 0xffff;
}
static ulong timestamp;
static ulong lastdec;
-int timer_init (void)
+int timer_init(void)
{
- S3C24X0_TIMERS * const timers = S3C24X0_GetBase_TIMERS();
+ struct s3c24x0_timers *timers = s3c24x0_get_base_timers();
+ ulong tmr;
/* use PWM Timer 4 because it has no output */
/* prescaler for Timer 4 is 16 */
- timers->TCFG0 = 0x0f00;
- if (timer_load_val == 0)
- {
+ writel(0x0f00, &timers->TCFG0);
+ if (timer_load_val == 0) {
/*
* for 10 ms clock period @ PCLK with 4 bit divider = 1/2
* (default) and prescaler = 16. Should be 10390
* @33.25MHz and 15625 @ 50 MHz
*/
- timer_load_val = get_PCLK()/(2 * 16 * 100);
+ timer_load_val = get_PCLK() / (2 * 16 * 100);
+ timer_clk = get_PCLK() / (2 * 16);
}
/* load value for 10 ms timeout */
- lastdec = timers->TCNTB4 = timer_load_val;
+ lastdec = timer_load_val;
+ writel(timer_load_val, &timers->TCNTB4);
/* auto load, manual update of Timer 4 */
- timers->TCON = (timers->TCON & ~0x0700000) | 0x600000;
+ tmr = (readl(&timers->TCON) & ~0x0700000) | 0x0600000;
+ writel(tmr, &timers->TCON);
/* auto load, start Timer 4 */
- timers->TCON = (timers->TCON & ~0x0700000) | 0x500000;
+ tmr = (tmr & ~0x0700000) | 0x0500000;
+ writel(tmr, &timers->TCON);
timestamp = 0;
return (0);
* timer without interrupts
*/
-void reset_timer (void)
+void reset_timer(void)
{
- reset_timer_masked ();
+ reset_timer_masked();
}
-ulong get_timer (ulong base)
+ulong get_timer(ulong base)
{
- return get_timer_masked () - base;
+ return get_timer_masked() - base;
}
-void set_timer (ulong t)
+void set_timer(ulong t)
{
timestamp = t;
}
-void udelay (unsigned long usec)
+void udelay(unsigned long usec)
{
ulong tmo;
- ulong start = get_timer(0);
+ ulong start = get_ticks();
tmo = usec / 1000;
tmo *= (timer_load_val * 100);
tmo /= 1000;
- while ((ulong)(get_timer_masked () - start) < tmo)
+ while ((ulong) (get_ticks() - start) < tmo)
/*NOP*/;
}
-void reset_timer_masked (void)
+void reset_timer_masked(void)
{
/* reset time */
lastdec = READ_TIMER();
timestamp = 0;
}
-ulong get_timer_masked (void)
+ulong get_timer_masked(void)
{
- ulong now = READ_TIMER();
+ ulong tmr = get_ticks();
- if (lastdec >= now) {
- /* normal mode */
- timestamp += lastdec - now;
- } else {
- /* we have an overflow ... */
- timestamp += lastdec + timer_load_val - now;
- }
- lastdec = now;
-
- return timestamp;
+ return tmr / (timer_clk / CONFIG_SYS_HZ);
}
-void udelay_masked (unsigned long usec)
+void udelay_masked(unsigned long usec)
{
ulong tmo;
ulong endtime;
tmo /= 1000;
} else {
tmo = usec * (timer_load_val * 100);
- tmo /= (1000*1000);
+ tmo /= (1000 * 1000);
}
- endtime = get_timer_masked () + tmo;
+ endtime = get_ticks() + tmo;
do {
- ulong now = get_timer_masked ();
+ ulong now = get_ticks();
diff = endtime - now;
} while (diff >= 0);
}
*/
unsigned long long get_ticks(void)
{
- return get_timer(0);
+ ulong now = READ_TIMER();
+
+ if (lastdec >= now) {
+ /* normal mode */
+ timestamp += lastdec - now;
+ } else {
+ /* we have an overflow ... */
+ timestamp += lastdec + timer_load_val - now;
+ }
+ lastdec = now;
+
+ return timestamp;
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
*/
-ulong get_tbclk (void)
+ulong get_tbclk(void)
{
ulong tbclk;
/*
* reset the cpu by setting up the watchdog timer and let him time out
*/
-void reset_cpu (ulong ignored)
+void reset_cpu(ulong ignored)
{
- volatile S3C24X0_WATCHDOG * watchdog;
+ struct s3c24x0_watchdog *watchdog;
#ifdef CONFIG_TRAB
- extern void disable_vfd (void);
-
disable_vfd();
#endif
- watchdog = S3C24X0_GetBase_WATCHDOG();
+ watchdog = s3c24x0_get_base_watchdog();
/* Disable watchdog */
- watchdog->WTCON = 0x0000;
+ writel(0x0000, &watchdog->WTCON);
/* Initialize watchdog timer count register */
- watchdog->WTCNT = 0x0001;
+ writel(0x0001, &watchdog->WTCNT);
/* Enable watchdog timer; assert reset at timer timeout */
- watchdog->WTCON = 0x0021;
+ writel(0x0021, &watchdog->WTCON);
- while(1); /* loop forever and wait for reset to happen */
+ while (1)
+ /* loop forever and wait for reset to happen */;
/*NOTREACHED*/
}
-#endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */
+#endif /* defined(CONFIG_S3C2400) ||
+ defined (CONFIG_S3C2410) ||
+ defined (CONFIG_TRAB) */
# include <s3c2410.h>
#endif
-int usb_cpu_init (void)
-{
+#include <asm/io.h>
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+int usb_cpu_init(void)
+{
+ struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+ struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
/*
* Set the 48 MHz UPLL clocking. Values are taken from
* "PLL value selection guide", 6-23, s3c2400_UM.pdf.
*/
- clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
- gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
+ writel((40 << 12) + (1 << 4) + 2, &clk_power->UPLLCON);
+ /* 1 = use pads related USB for USB host */
+ writel(readl(&gpio->MISCCR) | 0x8, &gpio->MISCCR);
/*
* Enable USB host clock.
*/
- clk_power->CLKCON |= (1 << 4);
+ writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);
return 0;
}
-int usb_cpu_stop (void)
+int usb_cpu_stop(void)
{
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+ struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
/* may not want to do this */
- clk_power->CLKCON &= ~(1 << 4);
+ writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
return 0;
}
-int usb_cpu_init_fail (void)
+int usb_cpu_init_fail(void)
{
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- clk_power->CLKCON &= ~(1 << 4);
+ struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+ writel(readl(&clk_power->CLKCON) & ~(1 << 4), &clk_power->CLKCON);
return 0;
}
-# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */
+# endif /* defined(CONFIG_S3C2400) || defined(CONFIG_S3C2410) */
#endif /* defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT) */
#include <s3c2410.h>
#endif
+#include <asm/io.h>
#include <malloc.h>
#include <usb.h>
#include "usb_ohci.h"
#define OHCI_CONTROL_INIT \
(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
-#define readl(a) (*((volatile u32 *)(a)))
-#define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
-
-#define min_t(type,x,y) ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
+#define min_t(type, x, y) \
+ ({ type __x = (x); type __y = (y); __x < __y ? __x : __y; })
#undef DEBUG
#ifdef DEBUG
#define m16_swap(x) swap_16(x)
#define m32_swap(x) swap_32(x)
-/* global ohci_t */
-static ohci_t gohci;
+/* global struct ohci */
+static struct ohci gohci;
/* this must be aligned to a 256 byte boundary */
struct ohci_hcca ghcca[1];
/* a pointer to the aligned storage */
/* this allocates EDs for all possible endpoints */
struct ohci_device ohci_dev;
/* urb_priv */
-urb_priv_t urb_priv;
+struct urb_priv urb_priv;
/* RHSC flag */
int got_rhsc;
/* device which was disconnected */
temp = readl (&hc->regs->roothub.register); \
temp; })
-static u32 roothub_a (struct ohci *hc)
- { return read_roothub (hc, a, 0xfc0fe000); }
-static inline u32 roothub_b (struct ohci *hc)
- { return readl (&hc->regs->roothub.b); }
-static inline u32 roothub_status (struct ohci *hc)
- { return readl (&hc->regs->roothub.status); }
-static u32 roothub_portstatus (struct ohci *hc, int i)
- { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
-
+static u32 roothub_a(struct ohci *hc)
+{
+ return read_roothub(hc, a, 0xfc0fe000);
+}
+static inline u32 roothub_b(struct ohci *hc)
+{
+ return readl(&hc->regs->roothub.b);
+}
+static inline u32 roothub_status(struct ohci *hc)
+{
+ return readl(&hc->regs->roothub.status);
+}
+static u32 roothub_portstatus(struct ohci *hc, int i)
+{
+ return read_roothub(hc, portstatus[i], 0xffe0fce0);
+}
/* forward declaration */
-static int hc_interrupt (void);
-static void
-td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
- int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
+static int hc_interrupt(void);
+static void td_submit_job(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int transfer_len,
+ struct devrequest *setup, struct urb_priv *urb,
+ int interval);
/*-------------------------------------------------------------------------*
* URB support functions
/* free HCD-private data associated with this URB */
-static void urb_free_priv (urb_priv_t * urb)
+static void urb_free_priv(struct urb_priv *urb)
{
- int i;
- int last;
- struct td * td;
+ int i;
+ int last;
+ struct td *td;
last = urb->length - 1;
if (last >= 0) {
/*-------------------------------------------------------------------------*/
#ifdef DEBUG
-static int sohci_get_current_frame_number (struct usb_device * dev);
+static int sohci_get_current_frame_number(struct usb_device *dev);
/* debug| print the main components of an URB
* small: 0) header + data packets 1) just header */
-static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
- int transfer_len, struct devrequest * setup, char * str, int small)
+static void pkt_print(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, struct devrequest *setup, char *str,
+ int small)
{
- urb_priv_t * purb = &urb_priv;
+ struct urb_priv *purb = &urb_priv;
dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
- str,
- sohci_get_current_frame_number (dev),
- usb_pipedevice (pipe),
- usb_pipeendpoint (pipe),
- usb_pipeout (pipe)? 'O': 'I',
- usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
- (usb_pipecontrol (pipe)? "CTRL": "BULK"),
- purb->actual_length,
- transfer_len, dev->status);
+ str,
+ sohci_get_current_frame_number(dev),
+ usb_pipedevice(pipe),
+ usb_pipeendpoint(pipe),
+ usb_pipeout(pipe) ? 'O' : 'I',
+ usb_pipetype(pipe) < 2 ?
+ (usb_pipeint(pipe) ? "INTR" : "ISOC") :
+ (usb_pipecontrol(pipe) ? "CTRL" : "BULK"),
+ purb->actual_length, transfer_len, dev->status);
#ifdef OHCI_VERBOSE_DEBUG
if (!small) {
int i, len;
- if (usb_pipecontrol (pipe)) {
- printf (__FILE__ ": cmd(8):");
- for (i = 0; i < 8 ; i++)
- printf (" %02x", ((__u8 *) setup) [i]);
- printf ("\n");
+ if (usb_pipecontrol(pipe)) {
+ printf(__FILE__ ": cmd(8):");
+ for (i = 0; i < 8; i++)
+ printf(" %02x", ((__u8 *) setup)[i]);
+ printf("\n");
}
if (transfer_len > 0 && buffer) {
- printf (__FILE__ ": data(%d/%d):",
- purb->actual_length,
- transfer_len);
- len = usb_pipeout (pipe)?
- transfer_len: purb->actual_length;
+ printf(__FILE__ ": data(%d/%d):",
+ purb->actual_length, transfer_len);
+ len = usb_pipeout(pipe) ?
+ transfer_len : purb->actual_length;
for (i = 0; i < 16 && i < len; i++)
- printf (" %02x", ((__u8 *) buffer) [i]);
- printf ("%s\n", i < len? "...": "");
+ printf(" %02x", ((__u8 *) buffer)[i]);
+ printf("%s\n", i < len ? "..." : "");
}
}
#endif
}
-/* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
-void ep_print_int_eds (ohci_t *ohci, char * str) {
+/* just for debugging; prints non-empty branches of the
+ int ed tree inclusive iso eds*/
+void ep_print_int_eds(struct ohci *ohci, char *str)
+{
int i, j;
- __u32 * ed_p;
- for (i= 0; i < 32; i++) {
+ __u32 *ed_p;
+ for (i = 0; i < 32; i++) {
j = 5;
- ed_p = &(ohci->hcca->int_table [i]);
+ ed_p = &(ohci->hcca->int_table[i]);
if (*ed_p == 0)
- continue;
- printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
+ continue;
+ printf(__FILE__ ": %s branch int %2d(%2x):", str, i, i);
while (*ed_p != 0 && j--) {
- ed_t *ed = (ed_t *)m32_swap(ed_p);
- printf (" ed: %4x;", ed->hwINFO);
+ struct ed *ed = (struct ed *) m32_swap(ed_p);
+ printf(" ed: %4x;", ed->hwINFO);
ed_p = &ed->hwNextED;
}
- printf ("\n");
+ printf("\n");
}
}
-static void ohci_dump_intr_mask (char *label, __u32 mask)
+static void ohci_dump_intr_mask(char *label, __u32 mask)
{
- dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
- label,
- mask,
- (mask & OHCI_INTR_MIE) ? " MIE" : "",
- (mask & OHCI_INTR_OC) ? " OC" : "",
- (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
- (mask & OHCI_INTR_FNO) ? " FNO" : "",
- (mask & OHCI_INTR_UE) ? " UE" : "",
- (mask & OHCI_INTR_RD) ? " RD" : "",
- (mask & OHCI_INTR_SF) ? " SF" : "",
- (mask & OHCI_INTR_WDH) ? " WDH" : "",
- (mask & OHCI_INTR_SO) ? " SO" : ""
- );
+ dbg("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
+ label,
+ mask,
+ (mask & OHCI_INTR_MIE) ? " MIE" : "",
+ (mask & OHCI_INTR_OC) ? " OC" : "",
+ (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
+ (mask & OHCI_INTR_FNO) ? " FNO" : "",
+ (mask & OHCI_INTR_UE) ? " UE" : "",
+ (mask & OHCI_INTR_RD) ? " RD" : "",
+ (mask & OHCI_INTR_SF) ? " SF" : "",
+ (mask & OHCI_INTR_WDH) ? " WDH" : "",
+ (mask & OHCI_INTR_SO) ? " SO" : "");
}
-static void maybe_print_eds (char *label, __u32 value)
+static void maybe_print_eds(char *label, __u32 value)
{
- ed_t *edp = (ed_t *)value;
+ struct ed *edp = (struct ed *) value;
if (value) {
- dbg ("%s %08x", label, value);
- dbg ("%08x", edp->hwINFO);
- dbg ("%08x", edp->hwTailP);
- dbg ("%08x", edp->hwHeadP);
- dbg ("%08x", edp->hwNextED);
+ dbg("%s %08x", label, value);
+ dbg("%08x", edp->hwINFO);
+ dbg("%08x", edp->hwTailP);
+ dbg("%08x", edp->hwHeadP);
+ dbg("%08x", edp->hwNextED);
}
}
-static char * hcfs2string (int state)
+static char *hcfs2string(int state)
{
switch (state) {
- case OHCI_USB_RESET: return "reset";
- case OHCI_USB_RESUME: return "resume";
- case OHCI_USB_OPER: return "operational";
- case OHCI_USB_SUSPEND: return "suspend";
+ case OHCI_USB_RESET:
+ return "reset";
+ case OHCI_USB_RESUME:
+ return "resume";
+ case OHCI_USB_OPER:
+ return "operational";
+ case OHCI_USB_SUSPEND:
+ return "suspend";
}
return "?";
}
/* dump control and status registers */
-static void ohci_dump_status (ohci_t *controller)
+static void ohci_dump_status(struct ohci *controller)
{
- struct ohci_regs *regs = controller->regs;
- __u32 temp;
+ struct ohci_regs *regs = controller->regs;
+ __u32 temp;
- temp = readl (®s->revision) & 0xff;
+ temp = readl(®s->revision) & 0xff;
if (temp != 0x10)
- dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
-
- temp = readl (®s->control);
- dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
- (temp & OHCI_CTRL_RWE) ? " RWE" : "",
- (temp & OHCI_CTRL_RWC) ? " RWC" : "",
- (temp & OHCI_CTRL_IR) ? " IR" : "",
- hcfs2string (temp & OHCI_CTRL_HCFS),
- (temp & OHCI_CTRL_BLE) ? " BLE" : "",
- (temp & OHCI_CTRL_CLE) ? " CLE" : "",
- (temp & OHCI_CTRL_IE) ? " IE" : "",
- (temp & OHCI_CTRL_PLE) ? " PLE" : "",
- temp & OHCI_CTRL_CBSR
- );
-
- temp = readl (®s->cmdstatus);
- dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
- (temp & OHCI_SOC) >> 16,
- (temp & OHCI_OCR) ? " OCR" : "",
- (temp & OHCI_BLF) ? " BLF" : "",
- (temp & OHCI_CLF) ? " CLF" : "",
- (temp & OHCI_HCR) ? " HCR" : ""
- );
-
- ohci_dump_intr_mask ("intrstatus", readl (®s->intrstatus));
- ohci_dump_intr_mask ("intrenable", readl (®s->intrenable));
-
- maybe_print_eds ("ed_periodcurrent", readl (®s->ed_periodcurrent));
-
- maybe_print_eds ("ed_controlhead", readl (®s->ed_controlhead));
- maybe_print_eds ("ed_controlcurrent", readl (®s->ed_controlcurrent));
-
- maybe_print_eds ("ed_bulkhead", readl (®s->ed_bulkhead));
- maybe_print_eds ("ed_bulkcurrent", readl (®s->ed_bulkcurrent));
-
- maybe_print_eds ("donehead", readl (®s->donehead));
+ dbg("spec %d.%d", (temp >> 4), (temp & 0x0f));
+
+ temp = readl(®s->control);
+ dbg("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
+ (temp & OHCI_CTRL_RWE) ? " RWE" : "",
+ (temp & OHCI_CTRL_RWC) ? " RWC" : "",
+ (temp & OHCI_CTRL_IR) ? " IR" : "",
+ hcfs2string(temp & OHCI_CTRL_HCFS),
+ (temp & OHCI_CTRL_BLE) ? " BLE" : "",
+ (temp & OHCI_CTRL_CLE) ? " CLE" : "",
+ (temp & OHCI_CTRL_IE) ? " IE" : "",
+ (temp & OHCI_CTRL_PLE) ? " PLE" : "", temp & OHCI_CTRL_CBSR);
+
+ temp = readl(®s->cmdstatus);
+ dbg("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
+ (temp & OHCI_SOC) >> 16,
+ (temp & OHCI_OCR) ? " OCR" : "",
+ (temp & OHCI_BLF) ? " BLF" : "",
+ (temp & OHCI_CLF) ? " CLF" : "", (temp & OHCI_HCR) ? " HCR" : "");
+
+ ohci_dump_intr_mask("intrstatus", readl(®s->intrstatus));
+ ohci_dump_intr_mask("intrenable", readl(®s->intrenable));
+
+ maybe_print_eds("ed_periodcurrent", readl(®s->ed_periodcurrent));
+
+ maybe_print_eds("ed_controlhead", readl(®s->ed_controlhead));
+ maybe_print_eds("ed_controlcurrent", readl(®s->ed_controlcurrent));
+
+ maybe_print_eds("ed_bulkhead", readl(®s->ed_bulkhead));
+ maybe_print_eds("ed_bulkcurrent", readl(®s->ed_bulkcurrent));
+
+ maybe_print_eds("donehead", readl(®s->donehead));
}
-static void ohci_dump_roothub (ohci_t *controller, int verbose)
+static void ohci_dump_roothub(struct ohci *controller, int verbose)
{
- __u32 temp, ndp, i;
+ __u32 temp, ndp, i;
- temp = roothub_a (controller);
+ temp = roothub_a(controller);
ndp = (temp & RH_A_NDP);
if (verbose) {
- dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
- ((temp & RH_A_POTPGT) >> 24) & 0xff,
- (temp & RH_A_NOCP) ? " NOCP" : "",
- (temp & RH_A_OCPM) ? " OCPM" : "",
- (temp & RH_A_DT) ? " DT" : "",
- (temp & RH_A_NPS) ? " NPS" : "",
- (temp & RH_A_PSM) ? " PSM" : "",
- ndp
- );
- temp = roothub_b (controller);
- dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
- temp,
- (temp & RH_B_PPCM) >> 16,
- (temp & RH_B_DR)
- );
- temp = roothub_status (controller);
- dbg ("roothub.status: %08x%s%s%s%s%s%s",
- temp,
- (temp & RH_HS_CRWE) ? " CRWE" : "",
- (temp & RH_HS_OCIC) ? " OCIC" : "",
- (temp & RH_HS_LPSC) ? " LPSC" : "",
- (temp & RH_HS_DRWE) ? " DRWE" : "",
- (temp & RH_HS_OCI) ? " OCI" : "",
- (temp & RH_HS_LPS) ? " LPS" : ""
- );
+ dbg("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
+ ((temp & RH_A_POTPGT) >> 24) & 0xff,
+ (temp & RH_A_NOCP) ? " NOCP" : "",
+ (temp & RH_A_OCPM) ? " OCPM" : "",
+ (temp & RH_A_DT) ? " DT" : "",
+ (temp & RH_A_NPS) ? " NPS" : "",
+ (temp & RH_A_PSM) ? " PSM" : "", ndp);
+ temp = roothub_b(controller);
+ dbg("roothub.b: %08x PPCM=%04x DR=%04x",
+ temp, (temp & RH_B_PPCM) >> 16, (temp & RH_B_DR)
+ );
+ temp = roothub_status(controller);
+ dbg("roothub.status: %08x%s%s%s%s%s%s",
+ temp,
+ (temp & RH_HS_CRWE) ? " CRWE" : "",
+ (temp & RH_HS_OCIC) ? " OCIC" : "",
+ (temp & RH_HS_LPSC) ? " LPSC" : "",
+ (temp & RH_HS_DRWE) ? " DRWE" : "",
+ (temp & RH_HS_OCI) ? " OCI" : "",
+ (temp & RH_HS_LPS) ? " LPS" : "");
}
for (i = 0; i < ndp; i++) {
- temp = roothub_portstatus (controller, i);
- dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
- i,
- temp,
- (temp & RH_PS_PRSC) ? " PRSC" : "",
- (temp & RH_PS_OCIC) ? " OCIC" : "",
- (temp & RH_PS_PSSC) ? " PSSC" : "",
- (temp & RH_PS_PESC) ? " PESC" : "",
- (temp & RH_PS_CSC) ? " CSC" : "",
-
- (temp & RH_PS_LSDA) ? " LSDA" : "",
- (temp & RH_PS_PPS) ? " PPS" : "",
- (temp & RH_PS_PRS) ? " PRS" : "",
- (temp & RH_PS_POCI) ? " POCI" : "",
- (temp & RH_PS_PSS) ? " PSS" : "",
-
- (temp & RH_PS_PES) ? " PES" : "",
- (temp & RH_PS_CCS) ? " CCS" : ""
- );
+ temp = roothub_portstatus(controller, i);
+ dbg("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
+ i,
+ temp,
+ (temp & RH_PS_PRSC) ? " PRSC" : "",
+ (temp & RH_PS_OCIC) ? " OCIC" : "",
+ (temp & RH_PS_PSSC) ? " PSSC" : "",
+ (temp & RH_PS_PESC) ? " PESC" : "",
+ (temp & RH_PS_CSC) ? " CSC" : "",
+ (temp & RH_PS_LSDA) ? " LSDA" : "",
+ (temp & RH_PS_PPS) ? " PPS" : "",
+ (temp & RH_PS_PRS) ? " PRS" : "",
+ (temp & RH_PS_POCI) ? " POCI" : "",
+ (temp & RH_PS_PSS) ? " PSS" : "",
+ (temp & RH_PS_PES) ? " PES" : "",
+ (temp & RH_PS_CCS) ? " CCS" : "");
}
}
-static void ohci_dump (ohci_t *controller, int verbose)
+static void ohci_dump(struct ohci *controller, int verbose)
{
- dbg ("OHCI controller usb-%s state", controller->slot_name);
+ dbg("OHCI controller usb-%s state", controller->slot_name);
/* dumps some of the state we know about */
- ohci_dump_status (controller);
+ ohci_dump_status(controller);
if (verbose)
- ep_print_int_eds (controller, "hcca");
- dbg ("hcca frame #%04x", controller->hcca->frame_no);
- ohci_dump_roothub (controller, 1);
+ ep_print_int_eds(controller, "hcca");
+ dbg("hcca frame #%04x", controller->hcca->frame_no);
+ ohci_dump_roothub(controller, 1);
}
-
#endif /* DEBUG */
/*-------------------------------------------------------------------------*
/* get a transfer request */
int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, struct devrequest *setup, int interval)
+ int transfer_len, struct devrequest *setup, int interval)
{
- ohci_t *ohci;
- ed_t * ed;
- urb_priv_t *purb_priv;
+ struct ohci *ohci;
+ struct ed *ed;
+ struct urb_priv *purb_priv;
int i, size = 0;
ohci = &gohci;
err("sohci_submit_job: URB NOT FINISHED");
return -1;
}
- /* we're about to begin a new transaction here so mark the URB unfinished */
+ /* we're about to begin a new transaction here
+ so mark the URB unfinished */
urb_finished = 0;
/* every endpoint has a ed, locate and fill it */
- if (!(ed = ep_add_ed (dev, pipe))) {
+ ed = ep_add_ed(dev, pipe);
+ if (!ed) {
err("sohci_submit_job: ENOMEM");
return -1;
}
/* for the private part of the URB we need the number of TDs (size) */
- switch (usb_pipetype (pipe)) {
- case PIPE_BULK: /* one TD for every 4096 Byte */
- size = (transfer_len - 1) / 4096 + 1;
- break;
- case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
- size = (transfer_len == 0)? 2:
- (transfer_len - 1) / 4096 + 3;
- break;
+ switch (usb_pipetype(pipe)) {
+ case PIPE_BULK:
+ /* one TD for every 4096 Byte */
+ size = (transfer_len - 1) / 4096 + 1;
+ break;
+ case PIPE_CONTROL:
+ /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
+ size = (transfer_len == 0) ? 2 : (transfer_len - 1) / 4096 + 3;
+ break;
}
if (size >= (N_URB_TD - 1)) {
/* allocate the TDs */
/* note that td[0] was allocated in ep_add_ed */
for (i = 0; i < size; i++) {
- purb_priv->td[i] = td_alloc (dev);
+ purb_priv->td[i] = td_alloc(dev);
if (!purb_priv->td[i]) {
purb_priv->length = i;
- urb_free_priv (purb_priv);
+ urb_free_priv(purb_priv);
err("sohci_submit_job: ENOMEM");
return -1;
}
}
if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
- urb_free_priv (purb_priv);
+ urb_free_priv(purb_priv);
err("sohci_submit_job: EINVAL");
return -1;
}
/* link the ed into a chain if is not already */
if (ed->state != ED_OPER)
- ep_link (ohci, ed);
+ ep_link(ohci, ed);
/* fill the TDs and link it to the ed */
- td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
+ td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv,
+ interval);
return 0;
}
#ifdef DEBUG
/* tell us the current USB frame number */
-static int sohci_get_current_frame_number (struct usb_device *usb_dev)
+static int sohci_get_current_frame_number(struct usb_device *usb_dev)
{
- ohci_t *ohci = &gohci;
+ struct ohci *ohci = &gohci;
- return m16_swap (ohci->hcca->frame_no);
+ return m16_swap(ohci->hcca->frame_no);
}
#endif
/* link an ed into one of the HC chains */
-static int ep_link (ohci_t *ohci, ed_t *edi)
+static int ep_link(struct ohci *ohci, struct ed *edi)
{
- volatile ed_t *ed = edi;
+ struct ed *ed = edi;
ed->state = ED_OPER;
case PIPE_CONTROL:
ed->hwNextED = 0;
if (ohci->ed_controltail == NULL) {
- writel (ed, &ohci->regs->ed_controlhead);
+ writel((u32)ed, &ohci->regs->ed_controlhead);
} else {
- ohci->ed_controltail->hwNextED = (__u32)m32_swap (ed);
+ ohci->ed_controltail->hwNextED = (__u32) m32_swap(ed);
}
ed->ed_prev = ohci->ed_controltail;
if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
- !ohci->ed_rm_list[1] && !ohci->sleeping) {
+ !ohci->ed_rm_list[1] && !ohci->sleeping) {
ohci->hc_control |= OHCI_CTRL_CLE;
- writel (ohci->hc_control, &ohci->regs->control);
+ writel(ohci->hc_control, &ohci->regs->control);
}
ohci->ed_controltail = edi;
break;
case PIPE_BULK:
ed->hwNextED = 0;
if (ohci->ed_bulktail == NULL) {
- writel (ed, &ohci->regs->ed_bulkhead);
+ writel((u32)ed, &ohci->regs->ed_bulkhead);
} else {
- ohci->ed_bulktail->hwNextED = (__u32)m32_swap (ed);
+ ohci->ed_bulktail->hwNextED = (__u32) m32_swap(ed);
}
ed->ed_prev = ohci->ed_bulktail;
if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
- !ohci->ed_rm_list[1] && !ohci->sleeping) {
+ !ohci->ed_rm_list[1] && !ohci->sleeping) {
ohci->hc_control |= OHCI_CTRL_BLE;
- writel (ohci->hc_control, &ohci->regs->control);
+ writel(ohci->hc_control, &ohci->regs->control);
}
ohci->ed_bulktail = edi;
break;
* the link from the ed still points to another operational ed or 0
* so the HC can eventually finish the processing of the unlinked ed */
-static int ep_unlink (ohci_t *ohci, ed_t *ed)
+static int ep_unlink(struct ohci *ohci, struct ed *ed)
{
- ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
+ struct ed *next;
+ ed->hwINFO |= m32_swap(OHCI_ED_SKIP);
switch (ed->type) {
case PIPE_CONTROL:
if (ed->ed_prev == NULL) {
if (!ed->hwNextED) {
ohci->hc_control &= ~OHCI_CTRL_CLE;
- writel (ohci->hc_control, &ohci->regs->control);
+ writel(ohci->hc_control, &ohci->regs->control);
}
- writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
+ writel(m32_swap(*((__u32 *) &ed->hwNextED)),
+ &ohci->regs->ed_controlhead);
} else {
ed->ed_prev->hwNextED = ed->hwNextED;
}
if (ohci->ed_controltail == ed) {
ohci->ed_controltail = ed->ed_prev;
} else {
- ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
+ next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED));
+ next->ed_prev = ed->ed_prev;
}
break;
if (ed->ed_prev == NULL) {
if (!ed->hwNextED) {
ohci->hc_control &= ~OHCI_CTRL_BLE;
- writel (ohci->hc_control, &ohci->regs->control);
+ writel(ohci->hc_control, &ohci->regs->control);
}
- writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
+ writel(m32_swap(*((__u32 *) &ed->hwNextED)),
+ &ohci->regs->ed_bulkhead);
} else {
ed->ed_prev->hwNextED = ed->hwNextED;
}
if (ohci->ed_bulktail == ed) {
ohci->ed_bulktail = ed->ed_prev;
} else {
- ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
+ next = (struct ed *)m32_swap(*((__u32 *)&ed->hwNextED));
+ next->ed_prev = ed->ed_prev;
}
break;
}
return 0;
}
-
/*-------------------------------------------------------------------------*/
-/* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
- * but the USB stack is a little bit stateless so we do it at every transaction
- * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
- * in all other cases the state is left unchanged
- * the ed info fields are setted anyway even though most of them should not change */
+/* add/reinit an endpoint; this should be done once at the usb_set_configuration
+ * command, but the USB stack is a little bit stateless so we do it at every
+ * transaction. If the state of the ed is ED_NEW then a dummy td is added and
+ * the state is changed to ED_UNLINK. In all other cases the state is left
+ * unchanged. The ed info fields are setted anyway even though most of them
+ * should not change */
-static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
+static struct ed *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe)
{
- td_t *td;
- ed_t *ed_ret;
- volatile ed_t *ed;
+ struct td *td;
+ struct ed *ed_ret;
+ struct ed *ed;
- ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
- (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
+ ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint(pipe) << 1) |
+ (usb_pipecontrol(pipe) ? 0 :
+ usb_pipeout(pipe))];
if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
err("ep_add_ed: pending delete");
}
if (ed->state == ED_NEW) {
- ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
+ ed->hwINFO = m32_swap(OHCI_ED_SKIP); /* skip ed */
/* dummy td; end of td list for ed */
- td = td_alloc (usb_dev);
- ed->hwTailP = (__u32)m32_swap (td);
+ td = td_alloc(usb_dev);
+ ed->hwTailP = (__u32) m32_swap(td);
ed->hwHeadP = ed->hwTailP;
ed->state = ED_UNLINK;
- ed->type = usb_pipetype (pipe);
+ ed->type = usb_pipetype(pipe);
ohci_dev.ed_cnt++;
}
- ed->hwINFO = m32_swap (usb_pipedevice (pipe)
- | usb_pipeendpoint (pipe) << 7
- | (usb_pipeisoc (pipe)? 0x8000: 0)
- | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
- | usb_pipeslow (pipe) << 13
- | usb_maxpacket (usb_dev, pipe) << 16);
+ ed->hwINFO = m32_swap(usb_pipedevice(pipe)
+ | usb_pipeendpoint(pipe) << 7
+ | (usb_pipeisoc(pipe) ? 0x8000 : 0)
+ | (usb_pipecontrol(pipe) ? 0 :
+ (usb_pipeout(pipe) ? 0x800 : 0x1000))
+ | usb_pipeslow(pipe) << 13 |
+ usb_maxpacket(usb_dev, pipe) << 16);
return ed_ret;
}
/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
-static void td_fill (ohci_t *ohci, unsigned int info,
- void *data, int len,
- struct usb_device *dev, int index, urb_priv_t *urb_priv)
+static void td_fill(struct ohci *ohci, unsigned int info, void *data, int len,
+ struct usb_device *dev, int index,
+ struct urb_priv *urb_priv)
{
- volatile td_t *td, *td_pt;
+ struct td *td, *td_pt;
#ifdef OHCI_FILL_TRACE
int i;
#endif
return;
}
/* use this td as the next dummy */
- td_pt = urb_priv->td [index];
+ td_pt = urb_priv->td[index];
td_pt->hwNextTD = 0;
/* fill the old dummy TD */
- td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
+ td = urb_priv->td[index] =
+ (struct td *) (m32_swap(urb_priv->ed->hwTailP) & ~0xf);
td->ed = urb_priv->ed;
td->next_dl_td = NULL;
td->index = index;
- td->data = (__u32)data;
+ td->data = (__u32) data;
#ifdef OHCI_FILL_TRACE
if (usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe)) {
for (i = 0; i < len; i++)
- printf("td->data[%d] %#2x ",i, ((unsigned char *)td->data)[i]);
+ printf("td->data[%d] %#2x ", i,
+ ((unsigned char *)td->data)[i]);
printf("\n");
}
#endif
if (!len)
data = 0;
- td->hwINFO = (__u32)m32_swap (info);
- td->hwCBP = (__u32)m32_swap (data);
+ td->hwINFO = (__u32) m32_swap(info);
+ td->hwCBP = (__u32) m32_swap(data);
if (data)
- td->hwBE = (__u32)m32_swap (data + len - 1);
+ td->hwBE = (__u32) m32_swap(data + len - 1);
else
td->hwBE = 0;
- td->hwNextTD = (__u32)m32_swap (td_pt);
+ td->hwNextTD = (__u32) m32_swap(td_pt);
/* append to queue */
td->ed->hwTailP = td->hwNextTD;
/* prepare all TDs of a transfer */
-static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
+static void td_submit_job(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int transfer_len,
+ struct devrequest *setup, struct urb_priv *urb,
+ int interval)
{
- ohci_t *ohci = &gohci;
+ struct ohci *ohci = &gohci;
int data_len = transfer_len;
void *data;
int cnt = 0;
__u32 info = 0;
unsigned int toggle = 0;
- /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
- if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
+ /* OHCI handles the DATA-toggles itself, we just
+ use the USB-toggle bits for reseting */
+ if (usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
toggle = TD_T_TOGGLE;
} else {
toggle = TD_T_DATA0;
- usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
+ usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe),
+ 1);
}
urb->td_cnt = 0;
if (data_len)
else
data = 0;
- switch (usb_pipetype (pipe)) {
+ switch (usb_pipetype(pipe)) {
case PIPE_BULK:
- info = usb_pipeout (pipe)?
- TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
- while(data_len > 4096) {
- td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
- data += 4096; data_len -= 4096; cnt++;
+ info = usb_pipeout(pipe) ? TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN;
+ while (data_len > 4096) {
+ td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data,
+ 4096, dev, cnt, urb);
+ data += 4096;
+ data_len -= 4096;
+ cnt++;
}
- info = usb_pipeout (pipe)?
- TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
- td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
+ info = usb_pipeout(pipe) ?
+ TD_CC | TD_DP_OUT :
+ TD_CC | TD_R | TD_DP_IN;
+ td_fill(ohci, info | (cnt ? TD_T_TOGGLE : toggle), data,
+ data_len, dev, cnt, urb);
cnt++;
if (!ohci->sleeping)
- writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
+ /* start bulk list */
+ writel(OHCI_BLF, &ohci->regs->cmdstatus);
break;
case PIPE_CONTROL:
info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
- td_fill (ohci, info, setup, 8, dev, cnt++, urb);
+ td_fill(ohci, info, setup, 8, dev, cnt++, urb);
if (data_len > 0) {
- info = usb_pipeout (pipe)?
- TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
+ info = usb_pipeout(pipe) ?
+ TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 :
+ TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
/* NOTE: mishandles transfers >8K, some >4K */
- td_fill (ohci, info, data, data_len, dev, cnt++, urb);
+ td_fill(ohci, info, data, data_len, dev, cnt++, urb);
}
- info = usb_pipeout (pipe)?
- TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
- td_fill (ohci, info, data, 0, dev, cnt++, urb);
+ info = usb_pipeout(pipe) ?
+ TD_CC | TD_DP_IN | TD_T_DATA1 :
+ TD_CC | TD_DP_OUT | TD_T_DATA1;
+ td_fill(ohci, info, data, 0, dev, cnt++, urb);
if (!ohci->sleeping)
- writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
+ /* start Control list */
+ writel(OHCI_CLF, &ohci->regs->cmdstatus);
break;
}
if (urb->length != cnt)
/* calculate the transfer length and update the urb */
-static void dl_transfer_length(td_t * td)
+static void dl_transfer_length(struct td *td)
{
__u32 tdINFO, tdBE, tdCBP;
- urb_priv_t *lurb_priv = &urb_priv;
-
- tdINFO = m32_swap (td->hwINFO);
- tdBE = m32_swap (td->hwBE);
- tdCBP = m32_swap (td->hwCBP);
+ struct urb_priv *lurb_priv = &urb_priv;
+ tdINFO = m32_swap(td->hwINFO);
+ tdBE = m32_swap(td->hwBE);
+ tdCBP = m32_swap(td->hwCBP);
if (!(usb_pipecontrol(lurb_priv->pipe) &&
- ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
+ ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
if (tdBE != 0) {
if (td->hwCBP == 0)
lurb_priv->actual_length += tdBE - td->data + 1;
/* replies to the request have to be on a FIFO basis so
* we reverse the reversed done-list */
-static td_t * dl_reverse_done_list (ohci_t *ohci)
+static struct td *dl_reverse_done_list(struct ohci *ohci)
{
__u32 td_list_hc;
- td_t *td_rev = NULL;
- td_t *td_list = NULL;
- urb_priv_t *lurb_priv = NULL;
+ __u32 tmp;
+ struct td *td_rev = NULL;
+ struct td *td_list = NULL;
+ struct urb_priv *lurb_priv = NULL;
- td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
+ td_list_hc = m32_swap(ohci->hcca->done_head) & 0xfffffff0;
ohci->hcca->done_head = 0;
while (td_list_hc) {
- td_list = (td_t *)td_list_hc;
+ td_list = (struct td *) td_list_hc;
- if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
+ if (TD_CC_GET(m32_swap(td_list->hwINFO))) {
lurb_priv = &urb_priv;
dbg(" USB-error/status: %x : %p",
- TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
- if (td_list->ed->hwHeadP & m32_swap (0x1)) {
- if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
+ TD_CC_GET(m32_swap(td_list->hwINFO)), td_list);
+ if (td_list->ed->hwHeadP & m32_swap(0x1)) {
+ if (lurb_priv &&
+ ((td_list->index+1) < lurb_priv->length)) {
+ tmp = lurb_priv->length - 1;
td_list->ed->hwHeadP =
- (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
- (td_list->ed->hwHeadP & m32_swap (0x2));
- lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
+ (lurb_priv->td[tmp]->hwNextTD &
+ m32_swap(0xfffffff0)) |
+ (td_list->ed->hwHeadP &
+ m32_swap(0x2));
+ lurb_priv->td_cnt += lurb_priv->length -
+ td_list->index - 1;
} else
- td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
+ td_list->ed->hwHeadP &=
+ m32_swap(0xfffffff2);
}
}
td_list->next_dl_td = td_rev;
td_rev = td_list;
- td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
+ td_list_hc = m32_swap(td_list->hwNextTD) & 0xfffffff0;
}
return td_list;
/*-------------------------------------------------------------------------*/
/* td done list */
-static int dl_done_list (ohci_t *ohci, td_t *td_list)
+static int dl_done_list(struct ohci *ohci, struct td *td_list)
{
- td_t *td_list_next = NULL;
- ed_t *ed;
+ struct td *td_list_next = NULL;
+ struct ed *ed;
int cc = 0;
int stat = 0;
/* urb_t *urb; */
- urb_priv_t *lurb_priv;
+ struct urb_priv *lurb_priv;
__u32 tdINFO, edHeadP, edTailP;
while (td_list) {
td_list_next = td_list->next_dl_td;
lurb_priv = &urb_priv;
- tdINFO = m32_swap (td_list->hwINFO);
+ tdINFO = m32_swap(td_list->hwINFO);
ed = td_list->ed;
dl_transfer_length(td_list);
/* error code of transfer */
- cc = TD_CC_GET (tdINFO);
+ cc = TD_CC_GET(tdINFO);
if (cc != 0) {
dbg("ConditionCode %#x", cc);
stat = cc_to_error[cc];
if ((ed->state & (ED_OPER | ED_UNLINK)))
urb_finished = 1;
else
- dbg("dl_done_list: strange.., ED state %x, ed->state\n");
+ dbg("dl_done_list: strange.., ED state %x, "
+ "ed->state\n");
} else
- dbg("dl_done_list: processing TD %x, len %x\n", lurb_priv->td_cnt,
- lurb_priv->length);
+ dbg("dl_done_list: processing TD %x, len %x\n",
+ lurb_priv->td_cnt, lurb_priv->length);
if (ed->state != ED_NEW) {
- edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
- edTailP = m32_swap (ed->hwTailP);
+ edHeadP = m32_swap(ed->hwHeadP) & 0xfffffff0;
+ edTailP = m32_swap(ed->hwTailP);
/* unlink eds if they are not busy */
if ((edHeadP == edTailP) && (ed->state == ED_OPER))
- ep_unlink (ohci, ed);
+ ep_unlink(ohci, ed);
}
td_list = td_list_next;
*-------------------------------------------------------------------------*/
/* Device descriptor */
-static __u8 root_hub_dev_des[] =
-{
- 0x12, /* __u8 bLength; */
- 0x01, /* __u8 bDescriptorType; Device */
- 0x10, /* __u16 bcdUSB; v1.1 */
+static __u8 root_hub_dev_des[] = {
+ 0x12, /* __u8 bLength; */
+ 0x01, /* __u8 bDescriptorType; Device */
+ 0x10, /* __u16 bcdUSB; v1.1 */
0x01,
- 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
- 0x00, /* __u8 bDeviceSubClass; */
- 0x00, /* __u8 bDeviceProtocol; */
- 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
- 0x00, /* __u16 idVendor; */
+ 0x09, /* __u8 bDeviceClass; HUB_CLASSCODE */
+ 0x00, /* __u8 bDeviceSubClass; */
+ 0x00, /* __u8 bDeviceProtocol; */
+ 0x08, /* __u8 bMaxPacketSize0; 8 Bytes */
+ 0x00, /* __u16 idVendor; */
0x00,
- 0x00, /* __u16 idProduct; */
+ 0x00, /* __u16 idProduct; */
0x00,
- 0x00, /* __u16 bcdDevice; */
+ 0x00, /* __u16 bcdDevice; */
0x00,
- 0x00, /* __u8 iManufacturer; */
- 0x01, /* __u8 iProduct; */
- 0x00, /* __u8 iSerialNumber; */
- 0x01 /* __u8 bNumConfigurations; */
+ 0x00, /* __u8 iManufacturer; */
+ 0x01, /* __u8 iProduct; */
+ 0x00, /* __u8 iSerialNumber; */
+ 0x01 /* __u8 bNumConfigurations; */
};
-
/* Configuration descriptor */
-static __u8 root_hub_config_des[] =
-{
- 0x09, /* __u8 bLength; */
- 0x02, /* __u8 bDescriptorType; Configuration */
- 0x19, /* __u16 wTotalLength; */
+static __u8 root_hub_config_des[] = {
+ 0x09, /* __u8 bLength; */
+ 0x02, /* __u8 bDescriptorType; Configuration */
+ 0x19, /* __u16 wTotalLength; */
0x00,
- 0x01, /* __u8 bNumInterfaces; */
- 0x01, /* __u8 bConfigurationValue; */
- 0x00, /* __u8 iConfiguration; */
- 0x40, /* __u8 bmAttributes;
- Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
- 0x00, /* __u8 MaxPower; */
+ 0x01, /* __u8 bNumInterfaces; */
+ 0x01, /* __u8 bConfigurationValue; */
+ 0x00, /* __u8 iConfiguration; */
+ 0x40, /* __u8 bmAttributes;
+ Bit 7: Bus-powered, 6: Self-powered,
+ 5 Remote-wakwup, 4..0: resvd */
+ 0x00, /* __u8 MaxPower; */
/* interface */
- 0x09, /* __u8 if_bLength; */
- 0x04, /* __u8 if_bDescriptorType; Interface */
- 0x00, /* __u8 if_bInterfaceNumber; */
- 0x00, /* __u8 if_bAlternateSetting; */
- 0x01, /* __u8 if_bNumEndpoints; */
- 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
- 0x00, /* __u8 if_bInterfaceSubClass; */
- 0x00, /* __u8 if_bInterfaceProtocol; */
- 0x00, /* __u8 if_iInterface; */
+ 0x09, /* __u8 if_bLength; */
+ 0x04, /* __u8 if_bDescriptorType; Interface */
+ 0x00, /* __u8 if_bInterfaceNumber; */
+ 0x00, /* __u8 if_bAlternateSetting; */
+ 0x01, /* __u8 if_bNumEndpoints; */
+ 0x09, /* __u8 if_bInterfaceClass; HUB_CLASSCODE */
+ 0x00, /* __u8 if_bInterfaceSubClass; */
+ 0x00, /* __u8 if_bInterfaceProtocol; */
+ 0x00, /* __u8 if_iInterface; */
/* endpoint */
- 0x07, /* __u8 ep_bLength; */
- 0x05, /* __u8 ep_bDescriptorType; Endpoint */
- 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
- 0x03, /* __u8 ep_bmAttributes; Interrupt */
- 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
+ 0x07, /* __u8 ep_bLength; */
+ 0x05, /* __u8 ep_bDescriptorType; Endpoint */
+ 0x81, /* __u8 ep_bEndpointAddress; IN Endpoint 1 */
+ 0x03, /* __u8 ep_bmAttributes; Interrupt */
+ 0x02, /* __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
0x00,
- 0xff /* __u8 ep_bInterval; 255 ms */
+ 0xff /* __u8 ep_bInterval; 255 ms */
};
-static unsigned char root_hub_str_index0[] =
-{
- 0x04, /* __u8 bLength; */
- 0x03, /* __u8 bDescriptorType; String-descriptor */
- 0x09, /* __u8 lang ID */
- 0x04, /* __u8 lang ID */
+static unsigned char root_hub_str_index0[] = {
+ 0x04, /* __u8 bLength; */
+ 0x03, /* __u8 bDescriptorType; String-descriptor */
+ 0x09, /* __u8 lang ID */
+ 0x04, /* __u8 lang ID */
};
-static unsigned char root_hub_str_index1[] =
-{
- 28, /* __u8 bLength; */
- 0x03, /* __u8 bDescriptorType; String-descriptor */
- 'O', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'H', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'C', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'I', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- ' ', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'R', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'o', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'o', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 't', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- ' ', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'H', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'u', /* __u8 Unicode */
- 0, /* __u8 Unicode */
- 'b', /* __u8 Unicode */
- 0, /* __u8 Unicode */
+static unsigned char root_hub_str_index1[] = {
+ 28, /* __u8 bLength; */
+ 0x03, /* __u8 bDescriptorType; String-descriptor */
+ 'O', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'H', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'C', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'I', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ ' ', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'R', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'o', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'o', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 't', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ ' ', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'H', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'u', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
+ 'b', /* __u8 Unicode */
+ 0, /* __u8 Unicode */
};
/* Hub class-specific descriptor is constructed dynamically */
#define OK(x) len = (x); break
#ifdef DEBUG
-#define WR_RH_STAT(x) {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
-#define WR_RH_PORTSTAT(x) {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
+#define WR_RH_STAT(x) \
+{ \
+ info("WR:status %#8x", (x)); \
+ writel((x), &gohci.regs->roothub.status); \
+}
+#define WR_RH_PORTSTAT(x) \
+{ \
+ info("WR:portstatus[%d] %#8x", wIndex-1, (x)); \
+ writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); \
+}
#else
-#define WR_RH_STAT(x) writel((x), &gohci.regs->roothub.status)
-#define WR_RH_PORTSTAT(x) writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
+#define WR_RH_STAT(x) \
+ writel((x), &gohci.regs->roothub.status)
+#define WR_RH_PORTSTAT(x)\
+ writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
#endif
-#define RD_RH_STAT roothub_status(&gohci)
-#define RD_RH_PORTSTAT roothub_portstatus(&gohci,wIndex-1)
+#define RD_RH_STAT roothub_status(&gohci)
+#define RD_RH_PORTSTAT roothub_portstatus(&gohci, wIndex-1)
/* request to virtual root hub */
-int rh_check_port_status(ohci_t *controller)
+int rh_check_port_status(struct ohci *controller)
{
__u32 temp, ndp, i;
int res;
res = -1;
- temp = roothub_a (controller);
+ temp = roothub_a(controller);
ndp = (temp & RH_A_NDP);
for (i = 0; i < ndp; i++) {
- temp = roothub_portstatus (controller, i);
+ temp = roothub_portstatus(controller, i);
/* check for a device disconnect */
if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
- (RH_PS_PESC | RH_PS_CSC)) &&
- ((temp & RH_PS_CCS) == 0)) {
+ (RH_PS_PESC | RH_PS_CSC)) && ((temp & RH_PS_CCS) == 0)) {
res = i;
break;
}
}
static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
- void *buffer, int transfer_len, struct devrequest *cmd)
+ void *buffer, int transfer_len,
+ struct devrequest *cmd)
{
- void * data = buffer;
+ void *data = buffer;
int leni = transfer_len;
int len = 0;
int stat = 0;
__u32 datab[4];
- __u8 *data_buf = (__u8 *)datab;
+ __u8 *data_buf = (__u8 *) datab;
__u16 bmRType_bReq;
__u16 wValue;
__u16 wIndex;
__u16 wLength;
#ifdef DEBUG
-urb_priv.actual_length = 0;
-pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
+ urb_priv.actual_length = 0;
+ pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)",
+ usb_pipein(pipe));
#else
wait_ms(1);
#endif
return 0;
}
- bmRType_bReq = cmd->requesttype | (cmd->request << 8);
- wValue = m16_swap (cmd->value);
- wIndex = m16_swap (cmd->index);
- wLength = m16_swap (cmd->length);
+ bmRType_bReq = cmd->requesttype | (cmd->request << 8);
+ wValue = m16_swap(cmd->value);
+ wIndex = m16_swap(cmd->index);
+ wLength = m16_swap(cmd->length);
info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
- dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
+ dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
switch (bmRType_bReq) {
- /* Request Destination:
- without flags: Device,
- RH_INTERFACE: interface,
- RH_ENDPOINT: endpoint,
- RH_CLASS means HUB here,
- RH_OTHER | RH_CLASS almost ever means HUB_PORT here
- */
+ /* Request Destination:
+ without flags: Device,
+ RH_INTERFACE: interface,
+ RH_ENDPOINT: endpoint,
+ RH_CLASS means HUB here,
+ RH_OTHER | RH_CLASS almost ever means HUB_PORT here
+ */
case RH_GET_STATUS:
- *(__u16 *) data_buf = m16_swap (1); OK (2);
+ *(__u16 *) data_buf = m16_swap(1);
+ OK(2);
case RH_GET_STATUS | RH_INTERFACE:
- *(__u16 *) data_buf = m16_swap (0); OK (2);
+ *(__u16 *) data_buf = m16_swap(0);
+ OK(2);
case RH_GET_STATUS | RH_ENDPOINT:
- *(__u16 *) data_buf = m16_swap (0); OK (2);
+ *(__u16 *) data_buf = m16_swap(0);
+ OK(2);
case RH_GET_STATUS | RH_CLASS:
- *(__u32 *) data_buf = m32_swap (
- RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
- OK (4);
+ *(__u32 *) data_buf =
+ m32_swap(RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
+ OK(4);
case RH_GET_STATUS | RH_OTHER | RH_CLASS:
- *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
+ *(__u32 *) data_buf = m32_swap(RD_RH_PORTSTAT);
+ OK(4);
case RH_CLEAR_FEATURE | RH_ENDPOINT:
switch (wValue) {
- case (RH_ENDPOINT_STALL): OK (0);
+ case (RH_ENDPOINT_STALL):
+ OK(0);
}
break;
case RH_CLEAR_FEATURE | RH_CLASS:
switch (wValue) {
- case RH_C_HUB_LOCAL_POWER:
- OK(0);
- case (RH_C_HUB_OVER_CURRENT):
- WR_RH_STAT(RH_HS_OCIC); OK (0);
+ case RH_C_HUB_LOCAL_POWER:
+ OK(0);
+ case (RH_C_HUB_OVER_CURRENT):
+ WR_RH_STAT(RH_HS_OCIC);
+ OK(0);
}
break;
case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
switch (wValue) {
- case (RH_PORT_ENABLE):
- WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
- case (RH_PORT_SUSPEND):
- WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
- case (RH_PORT_POWER):
- WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
- case (RH_C_PORT_CONNECTION):
- WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
- case (RH_C_PORT_ENABLE):
- WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
- case (RH_C_PORT_SUSPEND):
- WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
- case (RH_C_PORT_OVER_CURRENT):
- WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
- case (RH_C_PORT_RESET):
- WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
+ case (RH_PORT_ENABLE):
+ WR_RH_PORTSTAT(RH_PS_CCS);
+ OK(0);
+ case (RH_PORT_SUSPEND):
+ WR_RH_PORTSTAT(RH_PS_POCI);
+ OK(0);
+ case (RH_PORT_POWER):
+ WR_RH_PORTSTAT(RH_PS_LSDA);
+ OK(0);
+ case (RH_C_PORT_CONNECTION):
+ WR_RH_PORTSTAT(RH_PS_CSC);
+ OK(0);
+ case (RH_C_PORT_ENABLE):
+ WR_RH_PORTSTAT(RH_PS_PESC);
+ OK(0);
+ case (RH_C_PORT_SUSPEND):
+ WR_RH_PORTSTAT(RH_PS_PSSC);
+ OK(0);
+ case (RH_C_PORT_OVER_CURRENT):
+ WR_RH_PORTSTAT(RH_PS_OCIC);
+ OK(0);
+ case (RH_C_PORT_RESET):
+ WR_RH_PORTSTAT(RH_PS_PRSC);
+ OK(0);
}
break;
case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
switch (wValue) {
- case (RH_PORT_SUSPEND):
- WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
- case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
- if (RD_RH_PORTSTAT & RH_PS_CCS)
- WR_RH_PORTSTAT (RH_PS_PRS);
- OK (0);
- case (RH_PORT_POWER):
- WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
- case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
- if (RD_RH_PORTSTAT & RH_PS_CCS)
- WR_RH_PORTSTAT (RH_PS_PES );
- OK (0);
+ case (RH_PORT_SUSPEND):
+ WR_RH_PORTSTAT(RH_PS_PSS);
+ OK(0);
+ case (RH_PORT_RESET): /* BUG IN HUP CODE ******** */
+ if (RD_RH_PORTSTAT & RH_PS_CCS)
+ WR_RH_PORTSTAT(RH_PS_PRS);
+ OK(0);
+ case (RH_PORT_POWER):
+ WR_RH_PORTSTAT(RH_PS_PPS);
+ OK(0);
+ case (RH_PORT_ENABLE): /* BUG IN HUP CODE ******** */
+ if (RD_RH_PORTSTAT & RH_PS_CCS)
+ WR_RH_PORTSTAT(RH_PS_PES);
+ OK(0);
}
break;
- case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
+ case RH_SET_ADDRESS:
+ gohci.rh.devnum = wValue;
+ OK(0);
case RH_GET_DESCRIPTOR:
switch ((wValue & 0xff00) >> 8) {
- case (0x01): /* device descriptor */
+ case (0x01): /* device descriptor */
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof(root_hub_dev_des), wLength));
+ data_buf = root_hub_dev_des;
+ OK(len);
+ case (0x02): /* configuration descriptor */
+ len = min_t(unsigned int,
+ leni,
+ min_t(unsigned int,
+ sizeof(root_hub_config_des),
+ wLength));
+ data_buf = root_hub_config_des;
+ OK(len);
+ case (0x03): /* string descriptors */
+ if (wValue == 0x0300) {
len = min_t(unsigned int,
- leni,
- min_t(unsigned int,
- sizeof (root_hub_dev_des),
- wLength));
- data_buf = root_hub_dev_des; OK(len);
- case (0x02): /* configuration descriptor */
+ leni,
+ min_t(unsigned int,
+ sizeof(root_hub_str_index0),
+ wLength));
+ data_buf = root_hub_str_index0;
+ OK(len);
+ }
+ if (wValue == 0x0301) {
len = min_t(unsigned int,
- leni,
- min_t(unsigned int,
- sizeof (root_hub_config_des),
- wLength));
- data_buf = root_hub_config_des; OK(len);
- case (0x03): /* string descriptors */
- if(wValue==0x0300) {
- len = min_t(unsigned int,
- leni,
- min_t(unsigned int,
- sizeof (root_hub_str_index0),
- wLength));
- data_buf = root_hub_str_index0;
- OK(len);
- }
- if(wValue==0x0301) {
- len = min_t(unsigned int,
- leni,
- min_t(unsigned int,
- sizeof (root_hub_str_index1),
- wLength));
- data_buf = root_hub_str_index1;
- OK(len);
+ leni,
+ min_t(unsigned int,
+ sizeof(root_hub_str_index1),
+ wLength));
+ data_buf = root_hub_str_index1;
+ OK(len);
}
- default:
- stat = USB_ST_STALLED;
+ default:
+ stat = USB_ST_STALLED;
}
break;
case RH_GET_DESCRIPTOR | RH_CLASS:
- {
- __u32 temp = roothub_a (&gohci);
-
- data_buf [0] = 9; /* min length; */
- data_buf [1] = 0x29;
- data_buf [2] = temp & RH_A_NDP;
- data_buf [3] = 0;
- if (temp & RH_A_PSM) /* per-port power switching? */
- data_buf [3] |= 0x1;
- if (temp & RH_A_NOCP) /* no overcurrent reporting? */
- data_buf [3] |= 0x10;
- else if (temp & RH_A_OCPM) /* per-port overcurrent reporting? */
- data_buf [3] |= 0x8;
-
- /* corresponds to data_buf[4-7] */
- datab [1] = 0;
- data_buf [5] = (temp & RH_A_POTPGT) >> 24;
- temp = roothub_b (&gohci);
- data_buf [7] = temp & RH_B_DR;
- if (data_buf [2] < 7) {
- data_buf [8] = 0xff;
- } else {
- data_buf [0] += 2;
- data_buf [8] = (temp & RH_B_DR) >> 8;
- data_buf [10] = data_buf [9] = 0xff;
- }
-
- len = min_t(unsigned int, leni,
- min_t(unsigned int, data_buf [0], wLength));
- OK (len);
+ {
+ __u32 temp = roothub_a(&gohci);
+
+ data_buf[0] = 9; /* min length; */
+ data_buf[1] = 0x29;
+ data_buf[2] = temp & RH_A_NDP;
+ data_buf[3] = 0;
+ if (temp & RH_A_PSM)
+ /* per-port power switching? */
+ data_buf[3] |= 0x1;
+ if (temp & RH_A_NOCP)
+ /* no overcurrent reporting? */
+ data_buf[3] |= 0x10;
+ else if (temp & RH_A_OCPM)
+ /* per-port overcurrent reporting? */
+ data_buf[3] |= 0x8;
+
+ /* corresponds to data_buf[4-7] */
+ datab[1] = 0;
+ data_buf[5] = (temp & RH_A_POTPGT) >> 24;
+ temp = roothub_b(&gohci);
+ data_buf[7] = temp & RH_B_DR;
+ if (data_buf[2] < 7) {
+ data_buf[8] = 0xff;
+ } else {
+ data_buf[0] += 2;
+ data_buf[8] = (temp & RH_B_DR) >> 8;
+ data_buf[10] = data_buf[9] = 0xff;
+ }
+
+ len = min_t(unsigned int, leni,
+ min_t(unsigned int, data_buf[0], wLength));
+ OK(len);
}
- case RH_GET_CONFIGURATION: *(__u8 *) data_buf = 0x01; OK (1);
+ case RH_GET_CONFIGURATION:
+ *(__u8 *) data_buf = 0x01;
+ OK(1);
- case RH_SET_CONFIGURATION: WR_RH_STAT (0x10000); OK (0);
+ case RH_SET_CONFIGURATION:
+ WR_RH_STAT(0x10000);
+ OK(0);
default:
- dbg ("unsupported root hub command");
+ dbg("unsupported root hub command");
stat = USB_ST_STALLED;
}
#ifdef DEBUG
- ohci_dump_roothub (&gohci, 1);
+ ohci_dump_roothub(&gohci, 1);
#else
wait_ms(1);
#endif
len = min_t(int, len, leni);
if (data != data_buf)
- memcpy (data, data_buf, len);
+ memcpy(data, data_buf, len);
dev->act_len = len;
dev->status = stat;
#ifdef DEBUG
if (transfer_len)
urb_priv.actual_length = transfer_len;
- pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
+ pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)",
+ 0 /*usb_pipein(pipe) */);
#else
wait_ms(1);
#endif
/* common code for handling submit messages - used for all but root hub */
/* accesses. */
int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, struct devrequest *setup, int interval)
+ int transfer_len, struct devrequest *setup, int interval)
{
int stat = 0;
int maxsize = usb_maxpacket(dev, pipe);
dev->status = USB_ST_CRC_ERR;
return 0;
}
-
#ifdef DEBUG
urb_priv.actual_length = 0;
- pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
+ pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB",
+ usb_pipein(pipe));
#else
wait_ms(1);
#endif
if (!maxsize) {
err("submit_common_message: pipesize for pipe %lx is zero",
- pipe);
+ pipe);
return -1;
}
- if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
+ if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) <
+ 0) {
err("sohci_submit_job failed");
return -1;
}
/* ohci_dump_status(&gohci); */
/* allow more time for a BULK device to react - some are slow */
-#define BULK_TO 5000 /* timeout in milliseconds */
+#define BULK_TO 5000 /* timeout in milliseconds */
if (usb_pipebulk(pipe))
timeout = BULK_TO;
else
/* we got an Root Hub Status Change interrupt */
if (got_rhsc) {
#ifdef DEBUG
- ohci_dump_roothub (&gohci, 1);
+ ohci_dump_roothub(&gohci, 1);
#endif
got_rhsc = 0;
/* abuse timeout */
timeout = rh_check_port_status(&gohci);
if (timeout >= 0) {
-#if 0 /* this does nothing useful, but leave it here in case that changes */
+#if 0 /* this does nothing useful, but leave it here
+ in case that changes */
/* the called routine adds 1 to the passed value */
usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
#endif
dev->act_len = transfer_len;
#ifdef DEBUG
- pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
+ pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)",
+ usb_pipein(pipe));
#else
wait_ms(1);
#endif
/* free TDs in urb_priv */
- urb_free_priv (&urb_priv);
+ urb_free_priv(&urb_priv);
return 0;
}
/* submit routines called from usb.c */
int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len)
+ int transfer_len)
{
info("submit_bulk_msg");
return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
}
int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, struct devrequest *setup)
+ int transfer_len, struct devrequest *setup)
{
int maxsize = usb_maxpacket(dev, pipe);
info("submit_control_msg");
#ifdef DEBUG
urb_priv.actual_length = 0;
- pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
+ pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB",
+ usb_pipein(pipe));
#else
wait_ms(1);
#endif
if (!maxsize) {
err("submit_control_message: pipesize for pipe %lx is zero",
- pipe);
+ pipe);
return -1;
}
if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
gohci.rh.dev = dev;
/* root hub - redirect */
return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
- setup);
+ setup);
}
return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
}
int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
- int transfer_len, int interval)
+ int transfer_len, int interval)
{
info("submit_int_msg");
return -1;
/* reset the HC and BUS */
-static int hc_reset (ohci_t *ohci)
+static int hc_reset(struct ohci *ohci)
{
int timeout = 30;
- int smm_timeout = 50; /* 0,5 sec */
+ int smm_timeout = 50; /* 0,5 sec */
- if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
- writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
+ if (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
+ /* SMM owns the HC - request ownership */
+ writel(OHCI_OCR, &ohci->regs->cmdstatus);
info("USB HC TakeOver from SMM");
- while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
- wait_ms (10);
+ while (readl(&ohci->regs->control) & OHCI_CTRL_IR) {
+ wait_ms(10);
if (--smm_timeout == 0) {
err("USB HC TakeOver failed!");
return -1;
}
/* Disable HC interrupts */
- writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
+ writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
- ohci->slot_name,
- readl (&ohci->regs->control));
+ ohci->slot_name, readl(&ohci->regs->control));
/* Reset USB (needed by some controllers) */
- writel (0, &ohci->regs->control);
+ writel(0, &ohci->regs->control);
/* HC Reset requires max 10 us delay */
- writel (OHCI_HCR, &ohci->regs->cmdstatus);
- while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
+ writel(OHCI_HCR, &ohci->regs->cmdstatus);
+ while ((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
if (--timeout == 0) {
err("USB HC reset timed out!");
return -1;
}
- udelay (1);
+ udelay(1);
}
return 0;
}
* enable interrupts
* connect the virtual root hub */
-static int hc_start (ohci_t * ohci)
+static int hc_start(struct ohci *ohci)
{
__u32 mask;
unsigned int fminterval;
/* Tell the controller where the control and bulk lists are
* The lists are empty now. */
- writel (0, &ohci->regs->ed_controlhead);
- writel (0, &ohci->regs->ed_bulkhead);
+ writel(0, &ohci->regs->ed_controlhead);
+ writel(0, &ohci->regs->ed_bulkhead);
- writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
+ /* a reset clears this */
+ writel((__u32) ohci->hcca, &ohci->regs->hcca);
fminterval = 0x2edf;
- writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
+ writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
- writel (fminterval, &ohci->regs->fminterval);
- writel (0x628, &ohci->regs->lsthresh);
+ writel(fminterval, &ohci->regs->fminterval);
+ writel(0x628, &ohci->regs->lsthresh);
/* start controller operations */
ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
ohci->disabled = 0;
- writel (ohci->hc_control, &ohci->regs->control);
+ writel(ohci->hc_control, &ohci->regs->control);
/* disable all interrupts */
mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
- OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
- OHCI_INTR_OC | OHCI_INTR_MIE);
- writel (mask, &ohci->regs->intrdisable);
+ OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
+ OHCI_INTR_OC | OHCI_INTR_MIE);
+ writel(mask, &ohci->regs->intrdisable);
/* clear all interrupts */
mask &= ~OHCI_INTR_MIE;
- writel (mask, &ohci->regs->intrstatus);
+ writel(mask, &ohci->regs->intrstatus);
/* Choose the interrupts we care about now - but w/o MIE */
mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
- writel (mask, &ohci->regs->intrenable);
+ writel(mask, &ohci->regs->intrenable);
#ifdef OHCI_USE_NPS
/* required for AMD-756 and some Mac platforms */
- writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
- &ohci->regs->roothub.a);
- writel (RH_HS_LPSC, &ohci->regs->roothub.status);
-#endif /* OHCI_USE_NPS */
+ writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM,
+ &ohci->regs->roothub.a);
+ writel(RH_HS_LPSC, &ohci->regs->roothub.status);
+#endif /* OHCI_USE_NPS */
#define mdelay(n) ({unsigned long msec=(n); while (msec--) udelay(1000);})
/* POTPGT delay is bits 24-31, in 2 ms units. */
- mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
+ mdelay((roothub_a(ohci) >> 23) & 0x1fe);
/* connect the virtual root hub */
ohci->rh.devnum = 0;
/* an interrupt happens */
-static int
-hc_interrupt (void)
+static int hc_interrupt(void)
{
- ohci_t *ohci = &gohci;
+ struct ohci *ohci = &gohci;
struct ohci_regs *regs = ohci->regs;
int ints;
int stat = -1;
if ((ohci->hcca->done_head != 0) &&
- !(m32_swap (ohci->hcca->done_head) & 0x01)) {
+ !(m32_swap(ohci->hcca->done_head) & 0x01)) {
- ints = OHCI_INTR_WDH;
+ ints = OHCI_INTR_WDH;
- } else if ((ints = readl (®s->intrstatus)) == ~(u32)0) {
- ohci->disabled++;
- err ("%s device removed!", ohci->slot_name);
- return -1;
-
- } else if ((ints &= readl (®s->intrenable)) == 0) {
- dbg("hc_interrupt: returning..\n");
- return 0xff;
+ } else {
+ ints = readl(®s->intrstatus);
+ if (ints == ~(u32) 0) {
+ ohci->disabled++;
+ err("%s device removed!", ohci->slot_name);
+ return -1;
+ }
+ ints &= readl(®s->intrenable);
+ if (ints == 0) {
+ dbg("hc_interrupt: returning..\n");
+ return 0xff;
+ }
}
- /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
+ /* dbg("Interrupt: %x frame: %x", ints,
+ le16_to_cpu(ohci->hcca->frame_no)); */
if (ints & OHCI_INTR_RHSC) {
got_rhsc = 1;
if (ints & OHCI_INTR_UE) {
ohci->disabled++;
- err ("OHCI Unrecoverable Error, controller usb-%s disabled",
- ohci->slot_name);
+ err("OHCI Unrecoverable Error, controller usb-%s disabled",
+ ohci->slot_name);
/* e.g. due to PCI Master/Target Abort */
#ifdef DEBUG
- ohci_dump (ohci, 1);
+ ohci_dump(ohci, 1);
#else
- wait_ms(1);
+ wait_ms(1);
#endif
/* FIXME: be optimistic, hope that bug won't repeat often. */
/* Make some non-interrupt context restart the controller. */
/* Count and limit the retries though; either hardware or */
/* software errors can go forever... */
- hc_reset (ohci);
+ hc_reset(ohci);
return -1;
}
if (ints & OHCI_INTR_WDH) {
wait_ms(1);
- writel (OHCI_INTR_WDH, ®s->intrdisable);
- stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
- writel (OHCI_INTR_WDH, ®s->intrenable);
+ writel(OHCI_INTR_WDH, ®s->intrdisable);
+ stat = dl_done_list(&gohci, dl_reverse_done_list(&gohci));
+ writel(OHCI_INTR_WDH, ®s->intrenable);
}
if (ints & OHCI_INTR_SO) {
dbg("USB Schedule overrun\n");
- writel (OHCI_INTR_SO, ®s->intrenable);
+ writel(OHCI_INTR_SO, ®s->intrenable);
stat = -1;
}
/* FIXME: this assumes SOF (1/ms) interrupts don't get lost... */
if (ints & OHCI_INTR_SF) {
- unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
+ unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1;
wait_ms(1);
- writel (OHCI_INTR_SF, ®s->intrdisable);
+ writel(OHCI_INTR_SF, ®s->intrdisable);
if (ohci->ed_rm_list[frame] != NULL)
- writel (OHCI_INTR_SF, ®s->intrenable);
+ writel(OHCI_INTR_SF, ®s->intrenable);
stat = 0xff;
}
- writel (ints, ®s->intrstatus);
+ writel(ints, ®s->intrstatus);
return stat;
}
/* De-allocate all resources.. */
-static void hc_release_ohci (ohci_t *ohci)
+static void hc_release_ohci(struct ohci *ohci)
{
- dbg ("USB HC release ohci usb-%s", ohci->slot_name);
+ dbg("USB HC release ohci usb-%s", ohci->slot_name);
if (!ohci->disabled)
- hc_reset (ohci);
+ hc_reset(ohci);
}
/*-------------------------------------------------------------------------*/
int usb_lowlevel_init(void)
{
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+ struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
/*
* Set the 48 MHz UPLL clocking. Values are taken from
* "PLL value selection guide", 6-23, s3c2400_UM.pdf.
*/
clk_power->UPLLCON = ((40 << 12) + (1 << 4) + 2);
- gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
+ gpio->MISCCR |= 0x8; /* 1 = use pads related USB for USB host */
/*
* Enable USB host clock.
*/
clk_power->CLKCON |= (1 << 4);
- memset (&gohci, 0, sizeof (ohci_t));
- memset (&urb_priv, 0, sizeof (urb_priv_t));
+ memset(&gohci, 0, sizeof(struct ohci));
+ memset(&urb_priv, 0, sizeof(struct urb_priv));
/* align the storage */
- if ((__u32)&ghcca[0] & 0xff) {
+ if ((__u32) &ghcca[0] & 0xff) {
err("HCCA not aligned!!");
return -1;
}
phcca = &ghcca[0];
info("aligned ghcca %p", phcca);
memset(&ohci_dev, 0, sizeof(struct ohci_device));
- if ((__u32)&ohci_dev.ed[0] & 0x7) {
+ if ((__u32) &ohci_dev.ed[0] & 0x7) {
err("EDs not aligned!!");
return -1;
}
- memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
- if ((__u32)gtd & 0x7) {
+ memset(gtd, 0, sizeof(struct td) * (NUM_TD + 1));
+ if ((__u32) gtd & 0x7) {
err("TDs not aligned!!");
return -1;
}
ptd = gtd;
gohci.hcca = phcca;
- memset (phcca, 0, sizeof (struct ohci_hcca));
+ memset(phcca, 0, sizeof(struct ohci_hcca));
gohci.disabled = 1;
gohci.sleeping = 0;
gohci.flags = 0;
gohci.slot_name = "s3c2400";
- if (hc_reset (&gohci) < 0) {
- hc_release_ohci (&gohci);
+ if (hc_reset(&gohci) < 0) {
+ hc_release_ohci(&gohci);
/* Initialization failed */
clk_power->CLKCON &= ~(1 << 4);
return -1;
/* FIXME this is a second HC reset; why?? */
gohci.hc_control = OHCI_USB_RESET;
- writel (gohci.hc_control, &gohci.regs->control);
- wait_ms (10);
+ writel(gohci.hc_control, &gohci.regs->control);
+ wait_ms(10);
- if (hc_start (&gohci) < 0) {
- err ("can't start usb-%s", gohci.slot_name);
- hc_release_ohci (&gohci);
+ if (hc_start(&gohci) < 0) {
+ err("can't start usb-%s", gohci.slot_name);
+ hc_release_ohci(&gohci);
/* Initialization failed */
clk_power->CLKCON &= ~(1 << 4);
return -1;
}
-
#ifdef DEBUG
- ohci_dump (&gohci, 1);
+ ohci_dump(&gohci, 1);
#else
wait_ms(1);
#endif
int usb_lowlevel_stop(void)
{
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+ struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
/* this gets called really early - before the controller has */
/* even been initialized! */
return 0;
/* TODO release any interrupts, etc. */
/* call hc_release_ohci() here ? */
- hc_reset (&gohci);
+ hc_reset(&gohci);
/* may not want to do this */
clk_power->CLKCON &= ~(1 << 4);
return 0;
static int cc_to_error[16] = {
/* mapping of the OHCI CC status to error codes */
- /* No Error */ 0,
- /* CRC Error */ USB_ST_CRC_ERR,
- /* Bit Stuff */ USB_ST_BIT_ERR,
- /* Data Togg */ USB_ST_CRC_ERR,
- /* Stall */ USB_ST_STALLED,
- /* DevNotResp */ -1,
- /* PIDCheck */ USB_ST_BIT_ERR,
- /* UnExpPID */ USB_ST_BIT_ERR,
- /* DataOver */ USB_ST_BUF_ERR,
- /* DataUnder */ USB_ST_BUF_ERR,
- /* reservd */ -1,
- /* reservd */ -1,
- /* BufferOver */ USB_ST_BUF_ERR,
- /* BuffUnder */ USB_ST_BUF_ERR,
- /* Not Access */ -1,
- /* Not Access */ -1
+ /* No Error */ 0,
+ /* CRC Error */ USB_ST_CRC_ERR,
+ /* Bit Stuff */ USB_ST_BIT_ERR,
+ /* Data Togg */ USB_ST_CRC_ERR,
+ /* Stall */ USB_ST_STALLED,
+ /* DevNotResp */ -1,
+ /* PIDCheck */ USB_ST_BIT_ERR,
+ /* UnExpPID */ USB_ST_BIT_ERR,
+ /* DataOver */ USB_ST_BUF_ERR,
+ /* DataUnder */ USB_ST_BUF_ERR,
+ /* reservd */ -1,
+ /* reservd */ -1,
+ /* BufferOver */ USB_ST_BUF_ERR,
+ /* BuffUnder */ USB_ST_BUF_ERR,
+ /* Not Access */ -1,
+ /* Not Access */ -1
};
/* ED States */
struct usb_device *usb_dev;
__u32 unused[3];
-} __attribute__((aligned(16)));
-typedef struct ed ed_t;
-
+} __attribute__ ((aligned(16)));
/* TD info field */
#define TD_CC 0xf0000000
-#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
-#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
+#define TD_CC_GET(td_p) (((td_p) >> 28) & 0x0f)
+#define TD_CC_SET(td_p, cc) \
+ {(td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)}
#define TD_EC 0x0C000000
#define TD_T 0x03000000
#define TD_T_DATA0 0x02000000
__u32 data;
__u32 unused2[2];
-} __attribute__((aligned(32)));
-typedef struct td td_t;
+} __attribute__ ((aligned(32)));
#define OHCI_ED_SKIP (1 << 14)
* told the base address of. It must be 256-byte aligned.
*/
-#define NUM_INTS 32 /* part of the OHCI standard */
+#define NUM_INTS 32 /* part of the OHCI standard */
struct ohci_hcca {
- __u32 int_table[NUM_INTS]; /* Interrupt ED table */
- __u16 frame_no; /* current frame number */
- __u16 pad1; /* set to 0 on each frame_no change */
- __u32 done_head; /* info returned for an interrupt */
- u8 reserved_for_hc[116];
-} __attribute__((aligned(256)));
-
+ __u32 int_table[NUM_INTS]; /* Interrupt ED table */
+ __u16 frame_no; /* current frame number */
+ __u16 pad1; /* set to 0 on each frame_no change */
+ __u32 done_head; /* info returned for an interrupt */
+ u8 reserved_for_hc[116];
+} __attribute__ ((aligned(256)));
/*
* Maximum number of root hub ports.
*/
struct ohci_regs {
/* control and status registers */
- __u32 revision;
- __u32 control;
- __u32 cmdstatus;
- __u32 intrstatus;
- __u32 intrenable;
- __u32 intrdisable;
+ __u32 revision;
+ __u32 control;
+ __u32 cmdstatus;
+ __u32 intrstatus;
+ __u32 intrenable;
+ __u32 intrdisable;
/* memory pointers */
- __u32 hcca;
- __u32 ed_periodcurrent;
- __u32 ed_controlhead;
- __u32 ed_controlcurrent;
- __u32 ed_bulkhead;
- __u32 ed_bulkcurrent;
- __u32 donehead;
+ __u32 hcca;
+ __u32 ed_periodcurrent;
+ __u32 ed_controlhead;
+ __u32 ed_controlcurrent;
+ __u32 ed_bulkhead;
+ __u32 ed_bulkcurrent;
+ __u32 donehead;
/* frame counters */
- __u32 fminterval;
- __u32 fmremaining;
- __u32 fmnumber;
- __u32 periodicstart;
- __u32 lsthresh;
+ __u32 fminterval;
+ __u32 fmremaining;
+ __u32 fmnumber;
+ __u32 periodicstart;
+ __u32 lsthresh;
/* Root hub ports */
- struct ohci_roothub_regs {
- __u32 a;
- __u32 b;
- __u32 status;
- __u32 portstatus[MAX_ROOT_PORTS];
+ struct ohci_roothub_regs {
+ __u32 a;
+ __u32 b;
+ __u32 status;
+ __u32 portstatus[MAX_ROOT_PORTS];
} roothub;
-} __attribute__((aligned(32)));
-
+} __attribute__ ((aligned(32)));
/* OHCI CONTROL AND STATUS REGISTER MASKS */
#define OHCI_INTR_OC (1 << 30) /* ownership change */
#define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
-
/* Virtual Root HUB */
struct virt_root_hub {
- int devnum; /* Address of Root Hub endpoint */
- void *dev; /* was urb */
+ int devnum; /* Address of Root Hub endpoint */
+ void *dev; /* was urb */
void *int_addr;
int send;
int interval;
/* OHCI ROOT HUB REGISTER MASKS */
/* roothub.portstatus [i] bits */
-#define RH_PS_CCS 0x00000001 /* current connect status */
-#define RH_PS_PES 0x00000002 /* port enable status*/
-#define RH_PS_PSS 0x00000004 /* port suspend status */
-#define RH_PS_POCI 0x00000008 /* port over current indicator */
-#define RH_PS_PRS 0x00000010 /* port reset status */
-#define RH_PS_PPS 0x00000100 /* port power status */
-#define RH_PS_LSDA 0x00000200 /* low speed device attached */
-#define RH_PS_CSC 0x00010000 /* connect status change */
-#define RH_PS_PESC 0x00020000 /* port enable status change */
-#define RH_PS_PSSC 0x00040000 /* port suspend status change */
-#define RH_PS_OCIC 0x00080000 /* over current indicator change */
-#define RH_PS_PRSC 0x00100000 /* port reset status change */
+#define RH_PS_CCS 0x00000001 /* current connect status */
+#define RH_PS_PES 0x00000002 /* port enable status */
+#define RH_PS_PSS 0x00000004 /* port suspend status */
+#define RH_PS_POCI 0x00000008 /* port over current indicator */
+#define RH_PS_PRS 0x00000010 /* port reset status */
+#define RH_PS_PPS 0x00000100 /* port power status */
+#define RH_PS_LSDA 0x00000200 /* low speed device attached */
+#define RH_PS_CSC 0x00010000 /* connect status change */
+#define RH_PS_PESC 0x00020000 /* port enable status change */
+#define RH_PS_PSSC 0x00040000 /* port suspend status change */
+#define RH_PS_OCIC 0x00080000 /* over current indicator change */
+#define RH_PS_PRSC 0x00100000 /* port reset status change */
/* roothub.status bits */
-#define RH_HS_LPS 0x00000001 /* local power status */
-#define RH_HS_OCI 0x00000002 /* over current indicator */
-#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
-#define RH_HS_LPSC 0x00010000 /* local power status change */
-#define RH_HS_OCIC 0x00020000 /* over current indicator change */
-#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
+#define RH_HS_LPS 0x00000001 /* local power status */
+#define RH_HS_OCI 0x00000002 /* over current indicator */
+#define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
+#define RH_HS_LPSC 0x00010000 /* local power status change */
+#define RH_HS_OCIC 0x00020000 /* over current indicator change */
+#define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
/* roothub.b masks */
-#define RH_B_DR 0x0000ffff /* device removable flags */
-#define RH_B_PPCM 0xffff0000 /* port power control mask */
+#define RH_B_DR 0x0000ffff /* device removable flags */
+#define RH_B_PPCM 0xffff0000 /* port power control mask */
/* roothub.a masks */
-#define RH_A_NDP (0xff << 0) /* number of downstream ports */
-#define RH_A_PSM (1 << 8) /* power switching mode */
-#define RH_A_NPS (1 << 9) /* no power switching */
-#define RH_A_DT (1 << 10) /* device type (mbz) */
-#define RH_A_OCPM (1 << 11) /* over current protection mode */
-#define RH_A_NOCP (1 << 12) /* no over current protection */
-#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
+#define RH_A_NDP (0xff << 0) /* number of downstream ports */
+#define RH_A_PSM (1 << 8) /* power switching mode */
+#define RH_A_NPS (1 << 9) /* no power switching */
+#define RH_A_DT (1 << 10) /* device type (mbz) */
+#define RH_A_OCPM (1 << 11) /* over current protection mode */
+#define RH_A_NOCP (1 << 12) /* no over current protection */
+#define RH_A_POTPGT (0xff << 24) /* power on to power good time */
/* urb */
#define N_URB_TD 48
-typedef struct
-{
- ed_t *ed;
- __u16 length; /* number of tds associated with this request */
- __u16 td_cnt; /* number of tds already serviced */
- int state;
+struct urb_priv {
+ struct ed *ed;
+ __u16 length; /* number of tds associated with this request */
+ __u16 td_cnt; /* number of tds already serviced */
+ int state;
unsigned long pipe;
int actual_length;
- td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
-} urb_priv_t;
+ struct td *td[N_URB_TD]; /* list pointer to all corresponding TDs
+ associated with this request */
+};
#define URB_DEL 1
/*
*/
-typedef struct ohci {
+struct ohci {
struct ohci_hcca *hcca; /* hcca */
/*dma_addr_t hcca_dma; */
struct ohci_regs *regs; /* OHCI controller's memory */
- ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
- ed_t *ed_bulktail; /* last endpoint of bulk list */
- ed_t *ed_controltail; /* last endpoint of control list */
+ struct ed *ed_rm_list[2]; /* lists of all endpoints to be removed */
+ struct ed *ed_bulktail; /* last endpoint of bulk list */
+ struct ed *ed_controltail; /* last endpoint of control list */
int intrstatus;
__u32 hc_control; /* copy of the hc control reg */
struct usb_device *dev[32];
struct virt_root_hub rh;
const char *slot_name;
-} ohci_t;
+};
#define NUM_EDS 8 /* num of preallocated endpoint descriptors */
struct ohci_device {
- ed_t ed[NUM_EDS];
+ struct ed ed[NUM_EDS];
int ed_cnt;
};
/* hcd */
/* endpoint */
-static int ep_link (ohci_t * ohci, ed_t * ed);
-static int ep_unlink (ohci_t * ohci, ed_t * ed);
-static ed_t *ep_add_ed (struct usb_device *usb_dev, unsigned long pipe);
+static int ep_link(struct ohci *ohci, struct ed *ed);
+static int ep_unlink(struct ohci *ohci, struct ed *ed);
+static struct ed *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe);
/*-------------------------------------------------------------------------*/
#define NUM_TD 64
/* +1 so we can align the storage */
-td_t gtd[NUM_TD + 1];
+struct td gtd[NUM_TD + 1];
/* pointers to aligned storage */
-td_t *ptd;
+struct td *ptd;
/* TDs ... */
-static inline struct td *td_alloc (struct usb_device *usb_dev)
+static inline struct td *td_alloc(struct usb_device *usb_dev)
{
int i;
struct td *td;
return td;
}
-static inline void ed_free (struct ed *ed)
+static inline void ed_free(struct ed *ed)
{
ed->usb_dev = NULL;
}
.globl _start
-_start: b start_code
+_start: b start_code
ldr pc, _undefined_instruction
ldr pc, _software_interrupt
ldr pc, _prefetch_abort
/*
* set the cpu to SVC32 mode
*/
- mrs r0,cpsr
- bic r0,r0,#0x1f
- orr r0,r0,#0xd3
- msr cpsr,r0
+ mrs r0, cpsr
+ bic r0, r0, #0x1f
+ orr r0, r0, #0xd3
+ msr cpsr, r0
- bl coloured_LED_init
- bl red_LED_on
+ bl coloured_LED_init
+ bl red_LED_on
#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK)
/*
/* turn off the watchdog */
# if defined(CONFIG_S3C2400)
-# define pWTCON 0x15300000
-# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
+# define pWTCON 0x15300000
+# define INTMSK 0x14400008 /* Interupt-Controller base addresses */
# define CLKDIVN 0x14800014 /* clock divisor register */
#else
-# define pWTCON 0x53000000
-# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
+# define pWTCON 0x53000000
+# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */
# define INTSUBMSK 0x4A00001C
# define CLKDIVN 0x4C000014 /* clock divisor register */
# endif
- ldr r0, =pWTCON
- mov r1, #0x0
- str r1, [r0]
+ ldr r0, =pWTCON
+ mov r1, #0x0
+ str r1, [r0]
/*
* mask all IRQs by setting all bits in the INTMR - default
relocate: /* relocate U-Boot to RAM */
adr r0, _start /* r0 <- current position of code */
ldr r1, _TEXT_BASE /* test if we run from flash or RAM */
- cmp r0, r1 /* don't reloc during debug */
- beq stack_setup
+ cmp r0, r1 /* don't reloc during debug */
+ beq stack_setup
ldr r2, _armboot_start
ldr r3, _bss_start
/* Set up the stack */
stack_setup:
ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */
- sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
- sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
+ sub r0, r0, #CONFIG_SYS_MALLOC_LEN /* malloc area */
+ sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo */
#ifdef CONFIG_USE_IRQ
sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
#define S_R1 4
#define S_R0 0
-#define MODE_SVC 0x13
-#define I_BIT 0x80
+#define MODE_SVC 0x13
+#define I_BIT 0x80
/*
* use bad_save_user_regs for abort/prefetch/undef/swi ...
ldr r2, _armboot_start
sub r2, r2, #(CONFIG_STACKSIZE)
sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)
- sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack
+ /* set base 2 words into abort stack */
+ sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
ldmia r2, {r2 - r3} @ get pc, cpsr
add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
.macro irq_save_user_regs
sub sp, sp, #S_FRAME_SIZE
stmia sp, {r0 - r12} @ Calling r0-r12
- add r7, sp, #S_PC
- stmdb r7, {sp, lr}^ @ Calling SP, LR
- str lr, [r7, #0] @ Save calling PC
- mrs r6, spsr
- str r6, [r7, #4] @ Save CPSR
- str r0, [r7, #8] @ Save OLD_R0
+ add r7, sp, #S_PC
+ stmdb r7, {sp, lr}^ @ Calling SP, LR
+ str lr, [r7, #0] @ Save calling PC
+ mrs r6, spsr
+ str r6, [r7, #4] @ Save CPSR
+ str r0, [r7, #8] @ Save OLD_R0
mov r0, sp
.endm
mov r0, r0
ldr lr, [sp, #S_PC] @ Get PC
add sp, sp, #S_FRAME_SIZE
- subs pc, lr, #4 @ return & move spsr_svc into cpsr
+ /* return & move spsr_svc into cpsr */
+ subs pc, lr, #4
.endm
.macro get_bad_stack
ldr r13, _armboot_start @ setup our mode stack
sub r13, r13, #(CONFIG_STACKSIZE)
sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)
- sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack
+ /* reserve a couple spots in abort stack */
+ sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8)
str lr, [r13] @ save caller lr / spsr
mrs lr, spsr
- str lr, [r13, #4]
+ str lr, [r13, #4]
mov r13, #MODE_SVC @ prepare SVC-Mode
@ msr spsr_c, r13
--- /dev/null
+#
+# (C) Copyright 2000-2003
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# (C) Copyright 2008
+# Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(SOC).a
+
+SOBJS = reset.o
+
+COBJS += cache.o
+COBJS += clock.o
+COBJS += cpu_info.o
+COBJS += timer.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all: $(obj).depend $(LIB)
+
+$(LIB): $(OBJS)
+ $(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
--- /dev/null
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/cache.h>
+
+void l2_cache_enable(void)
+{
+ unsigned long i;
+
+ __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
+ __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
+ __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
+}
+
+void l2_cache_disable(void)
+{
+ unsigned long i;
+
+ __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
+ __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
+ __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
+}
--- /dev/null
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+
+#define APLL 0
+#define MPLL 1
+#define EPLL 2
+#define HPLL 3
+#define VPLL 4
+
+#define CLK_M 0
+#define CLK_D 1
+#define CLK_P 2
+
+#ifndef CONFIG_SYS_CLK_FREQ_C100
+#define CONFIG_SYS_CLK_FREQ_C100 12000000
+#endif
+#ifndef CONFIG_SYS_CLK_FREQ_C110
+#define CONFIG_SYS_CLK_FREQ_C110 24000000
+#endif
+
+unsigned long (*get_pclk)(void);
+unsigned long (*get_arm_clk)(void);
+unsigned long (*get_pll_clk)(int);
+
+/* s5pc110: return pll clock frequency */
+static unsigned long s5pc100_get_pll_clk(int pllreg)
+{
+ struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
+ unsigned long r, m, p, s, mask, fout;
+ unsigned int freq;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(&clk->apll_con);
+ break;
+ case MPLL:
+ r = readl(&clk->mpll_con);
+ break;
+ case EPLL:
+ r = readl(&clk->epll_con);
+ break;
+ case HPLL:
+ r = readl(&clk->hpll_con);
+ break;
+ default:
+ printf("Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ /*
+ * APLL_CON: MIDV [25:16]
+ * MPLL_CON: MIDV [23:16]
+ * EPLL_CON: MIDV [23:16]
+ * HPLL_CON: MIDV [23:16]
+ */
+ if (pllreg == APLL)
+ mask = 0x3ff;
+ else
+ mask = 0x0ff;
+
+ m = (r >> 16) & mask;
+
+ /* PDIV [13:8] */
+ p = (r >> 8) & 0x3f;
+ /* SDIV [2:0] */
+ s = r & 0x7;
+
+ /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
+ freq = CONFIG_SYS_CLK_FREQ_C100;
+ fout = m * (freq / (p * (1 << s)));
+
+ return fout;
+}
+
+/* s5pc100: return pll clock frequency */
+static unsigned long s5pc110_get_pll_clk(int pllreg)
+{
+ struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE;
+ unsigned long r, m, p, s, mask, fout;
+ unsigned int freq;
+
+ switch (pllreg) {
+ case APLL:
+ r = readl(&clk->apll_con);
+ break;
+ case MPLL:
+ r = readl(&clk->mpll_con);
+ break;
+ case EPLL:
+ r = readl(&clk->epll_con);
+ break;
+ case VPLL:
+ r = readl(&clk->vpll_con);
+ break;
+ default:
+ printf("Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ /*
+ * APLL_CON: MIDV [25:16]
+ * MPLL_CON: MIDV [25:16]
+ * EPLL_CON: MIDV [24:16]
+ * VPLL_CON: MIDV [24:16]
+ */
+ if (pllreg == APLL || pllreg == MPLL)
+ mask = 0x3ff;
+ else
+ mask = 0x1ff;
+
+ m = (r >> 16) & mask;
+
+ /* PDIV [13:8] */
+ p = (r >> 8) & 0x3f;
+ /* SDIV [2:0] */
+ s = r & 0x7;
+
+ freq = CONFIG_SYS_CLK_FREQ_C110;
+ if (pllreg == APLL) {
+ if (s < 1)
+ s = 1;
+ /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV - 1)) */
+ fout = m * (freq / (p * (1 << (s - 1))));
+ } else
+ /* FOUT = MDIV * FIN / (PDIV * 2^SDIV) */
+ fout = m * (freq / (p * (1 << s)));
+
+ return fout;
+}
+
+/* s5pc110: return ARM clock frequency */
+static unsigned long s5pc110_get_arm_clk(void)
+{
+ struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE;
+ unsigned long div;
+ unsigned long dout_apll, armclk;
+ unsigned int apll_ratio;
+
+ div = readl(&clk->div0);
+
+ /* APLL_RATIO: [2:0] */
+ apll_ratio = div & 0x7;
+
+ dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
+ armclk = dout_apll;
+
+ return armclk;
+}
+
+/* s5pc100: return ARM clock frequency */
+static unsigned long s5pc100_get_arm_clk(void)
+{
+ struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
+ unsigned long div;
+ unsigned long dout_apll, armclk;
+ unsigned int apll_ratio, arm_ratio;
+
+ div = readl(&clk->div0);
+
+ /* ARM_RATIO: [6:4] */
+ arm_ratio = (div >> 4) & 0x7;
+ /* APLL_RATIO: [0] */
+ apll_ratio = div & 0x1;
+
+ dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
+ armclk = dout_apll / (arm_ratio + 1);
+
+ return armclk;
+}
+
+/* s5pc100: return HCLKD0 frequency */
+static unsigned long get_hclk(void)
+{
+ struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
+ unsigned long hclkd0;
+ uint div, d0_bus_ratio;
+
+ div = readl(&clk->div0);
+ /* D0_BUS_RATIO: [10:8] */
+ d0_bus_ratio = (div >> 8) & 0x7;
+
+ hclkd0 = get_arm_clk() / (d0_bus_ratio + 1);
+
+ return hclkd0;
+}
+
+/* s5pc100: return PCLKD1 frequency */
+static unsigned long get_pclkd1(void)
+{
+ struct s5pc100_clock *clk = (struct s5pc100_clock *)S5PC1XX_CLOCK_BASE;
+ unsigned long d1_bus, pclkd1;
+ uint div, d1_bus_ratio, pclkd1_ratio;
+
+ div = readl(&clk->div0);
+ /* D1_BUS_RATIO: [14:12] */
+ d1_bus_ratio = (div >> 12) & 0x7;
+ /* PCLKD1_RATIO: [18:16] */
+ pclkd1_ratio = (div >> 16) & 0x7;
+
+ /* ASYNC Mode */
+ d1_bus = get_pll_clk(MPLL) / (d1_bus_ratio + 1);
+ pclkd1 = d1_bus / (pclkd1_ratio + 1);
+
+ return pclkd1;
+}
+
+/* s5pc110: return HCLKs frequency */
+static unsigned long get_hclk_sys(int dom)
+{
+ struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE;
+ unsigned long hclk;
+ unsigned int div;
+ unsigned int offset;
+ unsigned int hclk_sys_ratio;
+
+ if (dom == CLK_M)
+ return get_hclk();
+
+ div = readl(&clk->div0);
+
+ /*
+ * HCLK_MSYS_RATIO: [10:8]
+ * HCLK_DSYS_RATIO: [19:16]
+ * HCLK_PSYS_RATIO: [27:24]
+ */
+ offset = 8 + (dom << 0x3);
+
+ hclk_sys_ratio = (div >> offset) & 0xf;
+
+ hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1);
+
+ return hclk;
+}
+
+/* s5pc110: return PCLKs frequency */
+static unsigned long get_pclk_sys(int dom)
+{
+ struct s5pc110_clock *clk = (struct s5pc110_clock *)S5PC1XX_CLOCK_BASE;
+ unsigned long pclk;
+ unsigned int div;
+ unsigned int offset;
+ unsigned int pclk_sys_ratio;
+
+ div = readl(&clk->div0);
+
+ /*
+ * PCLK_MSYS_RATIO: [14:12]
+ * PCLK_DSYS_RATIO: [22:20]
+ * PCLK_PSYS_RATIO: [30:28]
+ */
+ offset = 12 + (dom << 0x3);
+
+ pclk_sys_ratio = (div >> offset) & 0x7;
+
+ pclk = get_hclk_sys(dom) / (pclk_sys_ratio + 1);
+
+ return pclk;
+}
+
+/* s5pc110: return peripheral clock frequency */
+static unsigned long s5pc110_get_pclk(void)
+{
+ return get_pclk_sys(CLK_P);
+}
+
+/* s5pc100: return peripheral clock frequency */
+static unsigned long s5pc100_get_pclk(void)
+{
+ return get_pclkd1();
+}
+
+void s5pc1xx_clock_init(void)
+{
+ if (cpu_is_s5pc110()) {
+ get_pll_clk = s5pc110_get_pll_clk;
+ get_arm_clk = s5pc110_get_arm_clk;
+ get_pclk = s5pc110_get_pclk;
+ } else {
+ get_pll_clk = s5pc100_get_pll_clk;
+ get_arm_clk = s5pc100_get_arm_clk;
+ get_pclk = s5pc100_get_pclk;
+ }
+}
--- /dev/null
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clk.h>
+
+/* Default is s5pc100 */
+unsigned int s5pc1xx_cpu_id = 0xC100;
+
+#ifdef CONFIG_ARCH_CPU_INIT
+int arch_cpu_init(void)
+{
+ s5pc1xx_cpu_id = readl(S5PC1XX_PRO_ID);
+ s5pc1xx_cpu_id = 0xC000 | ((s5pc1xx_cpu_id & 0x00FFF000) >> 12);
+
+ s5pc1xx_clock_init();
+
+ return 0;
+}
+#endif
+
+u32 get_device_type(void)
+{
+ return s5pc1xx_cpu_id;
+}
+
+#ifdef CONFIG_DISPLAY_CPUINFO
+int print_cpuinfo(void)
+{
+ char buf[32];
+
+ printf("CPU:\tS5P%X@%sMHz\n",
+ s5pc1xx_cpu_id, strmhz(buf, get_arm_clk()));
+
+ return 0;
+}
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2009 Samsung Electronics.
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <asm/arch/cpu.h>
+
+#define S5PC100_SWRESET 0xE0200000
+#define S5PC110_SWRESET 0xE0102000
+
+.globl reset_cpu
+reset_cpu:
+ ldr r1, =S5PC1XX_PRO_ID
+ ldr r2, [r1]
+ ldr r4, =0x00010000
+ and r4, r2, r4
+ cmp r4, #0
+ bne 110f
+ /* S5PC100 */
+ ldr r1, =S5PC100_SWRESET
+ ldr r2, =0xC100
+ b 200f
+110: /* S5PC110 */
+ ldr r1, =S5PC110_SWRESET
+ mov r2, #1
+200:
+ str r2, [r1]
+_loop_forever:
+ b _loop_forever
--- /dev/null
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Heungjun Kim <riverful.kim@samsung.com>
+ * Inki Dae <inki.dae@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/pwm.h>
+#include <asm/arch/clk.h>
+
+#define PRESCALER_1 (16 - 1) /* prescaler of timer 2, 3, 4 */
+#define MUX_DIV_2 1 /* 1/2 period */
+#define MUX_DIV_4 2 /* 1/4 period */
+#define MUX_DIV_8 3 /* 1/8 period */
+#define MUX_DIV_16 4 /* 1/16 period */
+#define MUX4_DIV_SHIFT 16
+
+#define TCON_TIMER4_SHIFT 20
+
+static unsigned long count_value;
+
+/* Internal tick units */
+static unsigned long long timestamp; /* Monotonic incrementing timer */
+static unsigned long lastdec; /* Last decremneter snapshot */
+
+/* macro to read the 16 bit timer */
+static inline struct s5pc1xx_timer *s5pc1xx_get_base_timer(void)
+{
+ if (cpu_is_s5pc110())
+ return (struct s5pc1xx_timer *)S5PC110_TIMER_BASE;
+ else
+ return (struct s5pc1xx_timer *)S5PC100_TIMER_BASE;
+}
+
+int timer_init(void)
+{
+ struct s5pc1xx_timer *const timer = s5pc1xx_get_base_timer();
+ u32 val;
+
+ /*
+ * @ PWM Timer 4
+ * Timer Freq(HZ) =
+ * PCLK / { (prescaler_value + 1) * (divider_value) }
+ */
+
+ /* set prescaler : 16 */
+ /* set divider : 2 */
+ writel((PRESCALER_1 & 0xff) << 8, &timer->tcfg0);
+ writel((MUX_DIV_2 & 0xf) << MUX4_DIV_SHIFT, &timer->tcfg1);
+
+ if (count_value == 0) {
+ /* reset initial value */
+ /* count_value = 2085937.5(HZ) (per 1 sec)*/
+ count_value = get_pclk() / ((PRESCALER_1 + 1) *
+ (MUX_DIV_2 + 1));
+
+ /* count_value / 100 = 20859.375(HZ) (per 10 msec) */
+ count_value = count_value / 100;
+ }
+
+ /* set count value */
+ writel(count_value, &timer->tcntb4);
+ lastdec = count_value;
+
+ val = (readl(&timer->tcon) & ~(0x07 << TCON_TIMER4_SHIFT)) |
+ S5PC1XX_TCON4_AUTO_RELOAD;
+
+ /* auto reload & manual update */
+ writel(val | S5PC1XX_TCON4_UPDATE, &timer->tcon);
+
+ /* start PWM timer 4 */
+ writel(val | S5PC1XX_TCON4_START, &timer->tcon);
+
+ timestamp = 0;
+
+ return 0;
+}
+
+/*
+ * timer without interrupts
+ */
+void reset_timer(void)
+{
+ reset_timer_masked();
+}
+
+unsigned long get_timer(unsigned long base)
+{
+ return get_timer_masked() - base;
+}
+
+void set_timer(unsigned long t)
+{
+ timestamp = t;
+}
+
+/* delay x useconds */
+void udelay(unsigned long usec)
+{
+ unsigned long tmo, tmp;
+
+ if (usec >= 1000) {
+ /*
+ * if "big" number, spread normalization
+ * to seconds
+ * 1. start to normalize for usec to ticks per sec
+ * 2. find number of "ticks" to wait to achieve target
+ * 3. finish normalize.
+ */
+ tmo = usec / 1000;
+ tmo *= (CONFIG_SYS_HZ * count_value / 10);
+ tmo /= 1000;
+ } else {
+ /* else small number, don't kill it prior to HZ multiply */
+ tmo = usec * CONFIG_SYS_HZ * count_value / 10;
+ tmo /= (1000 * 1000);
+ }
+
+ /* get current timestamp */
+ tmp = get_timer(0);
+
+ /* if setting this fordward will roll time stamp */
+ /* reset "advancing" timestamp to 0, set lastdec value */
+ /* else, set advancing stamp wake up time */
+ if ((tmo + tmp + 1) < tmp)
+ reset_timer_masked();
+ else
+ tmo += tmp;
+
+ /* loop till event */
+ while (get_timer_masked() < tmo)
+ ; /* nop */
+}
+
+void reset_timer_masked(void)
+{
+ struct s5pc1xx_timer *const timer = s5pc1xx_get_base_timer();
+
+ /* reset time */
+ lastdec = readl(&timer->tcnto4);
+ timestamp = 0;
+}
+
+unsigned long get_timer_masked(void)
+{
+ struct s5pc1xx_timer *const timer = s5pc1xx_get_base_timer();
+ unsigned long now = readl(&timer->tcnto4);
+
+ if (lastdec >= now)
+ timestamp += lastdec - now;
+ else
+ timestamp += lastdec + count_value - now;
+
+ lastdec = now;
+
+ return timestamp;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On ARM it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On ARM it returns the number of timer ticks per second.
+ */
+unsigned long get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
--- /dev/null
+
+Summary
+=======
+
+This README is about U-Boot support for SAMSUNG's ARM Cortex-A8 based S5PC1xx
+family of SoCs (S5PC100 [1] and S5PC110).
+
+Currently the following board is supported:
+
+* SMDKC100 [2]
+
+Toolchain
+=========
+
+While ARM Cortex-A8 support ARM v7 instruction set (-march=armv7a) we compile
+with -march=armv5 to allow more compilers to work. For U-Boot code this has
+no performance impact.
+
+Build
+=====
+
+* SMDKC100
+
+make smdkc100_config
+make
+
+
+Interfaces
+==========
+
+cpu
+
+To check SoC:
+
+ if (cpu_is_s5pc100())
+ printf("cpu is s5pc100\n");
+
+ or
+
+ if (cpu_is_s5pc110())
+ printf("cpu is s5pc110\n");
+
+gpio
+ not supported yet.
+
+Links
+=====
+
+[1] S5PC100:
+
+http://www.samsung.com/global/business/semiconductor/productInfo.do?
+fmly_id=229&partnum=S5PC100
+
+[2] SMDKC100:
+
+http://meritech.co.kr/eng/products/product_view.php?num=28
#elif defined(CONFIG_S3C2410)
#include <s3c2410.h>
#endif
+
+#include <asm/io.h>
#include <i2c.h>
#ifdef CONFIG_HARD_I2C
#define I2C_OK 0
#define I2C_NOK 1
#define I2C_NACK 2
-#define I2C_NOK_LA 3 /* Lost arbitration */
-#define I2C_NOK_TOUT 4 /* time out */
-
-#define I2CSTAT_BSY 0x20 /* Busy bit */
-#define I2CSTAT_NACK 0x01 /* Nack bit */
-#define I2CCON_IRPND 0x10 /* Interrupt pending bit */
-#define I2C_MODE_MT 0xC0 /* Master Transmit Mode */
-#define I2C_MODE_MR 0x80 /* Master Receive Mode */
-#define I2C_START_STOP 0x20 /* START / STOP */
-#define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
+#define I2C_NOK_LA 3 /* Lost arbitration */
+#define I2C_NOK_TOUT 4 /* time out */
-#define I2C_TIMEOUT 1 /* 1 second */
+#define I2CSTAT_BSY 0x20 /* Busy bit */
+#define I2CSTAT_NACK 0x01 /* Nack bit */
+#define I2CCON_IRPND 0x10 /* Interrupt pending bit */
+#define I2C_MODE_MT 0xC0 /* Master Transmit Mode */
+#define I2C_MODE_MR 0x80 /* Master Receive Mode */
+#define I2C_START_STOP 0x20 /* START / STOP */
+#define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */
+#define I2C_TIMEOUT 1 /* 1 second */
static int GetI2CSDA(void)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
#ifdef CONFIG_S3C2410
- return (gpio->GPEDAT & 0x8000) >> 15;
+ return (readl(&gpio->GPEDAT) & 0x8000) >> 15;
#endif
#ifdef CONFIG_S3C2400
- return (gpio->PGDAT & 0x0020) >> 5;
+ return (readl(&gpio->PGDAT) & 0x0020) >> 5;
#endif
}
#if 0
static void SetI2CSDA(int x)
{
- rGPEDAT = (rGPEDAT & ~0x8000) | (x&1) << 15;
+ rGPEDAT = (rGPEDAT & ~0x8000) | (x & 1) << 15;
}
#endif
static void SetI2CSCL(int x)
{
- S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO();
+ struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
#ifdef CONFIG_S3C2410
- gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14;
+ writel((readl(&gpio->GPEDAT) & ~0x4000) | (x & 1) << 14, &gpio->GPEDAT);
#endif
#ifdef CONFIG_S3C2400
- gpio->PGDAT = (gpio->PGDAT & ~0x0040) | (x&1) << 6;
+ writel((readl(&gpio->PGDAT) & ~0x0040) | (x & 1) << 6, &gpio->PGDAT);
#endif
}
-
-static int WaitForXfer (void)
+static int WaitForXfer(void)
{
- S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C ();
- int i, status;
+ struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
+ int i;
i = I2C_TIMEOUT * 10000;
- status = i2c->IICCON;
- while ((i > 0) && !(status & I2CCON_IRPND)) {
- udelay (100);
- status = i2c->IICCON;
+ while (!(readl(&i2c->IICCON) & I2CCON_IRPND) && (i > 0)) {
+ udelay(100);
i--;
}
- return (status & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
+ return (readl(&i2c->IICCON) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT;
}
-static int IsACK (void)
+static int IsACK(void)
{
- S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C ();
+ struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
- return (!(i2c->IICSTAT & I2CSTAT_NACK));
+ return !(readl(&i2c->IICSTAT) & I2CSTAT_NACK);
}
-static void ReadWriteByte (void)
+static void ReadWriteByte(void)
{
- S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C ();
+ struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
- i2c->IICCON &= ~I2CCON_IRPND;
+ writel(readl(&i2c->IICCON) & ~I2CCON_IRPND, &i2c->IICCON);
}
-void i2c_init (int speed, int slaveadd)
+void i2c_init(int speed, int slaveadd)
{
- S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C ();
- S3C24X0_GPIO *const gpio = S3C24X0_GetBase_GPIO ();
+ struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
+ struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio();
ulong freq, pres = 16, div;
- int i, status;
+ int i;
/* wait for some time to give previous transfer a chance to finish */
i = I2C_TIMEOUT * 1000;
- status = i2c->IICSTAT;
- while ((i > 0) && (status & I2CSTAT_BSY)) {
- udelay (1000);
- status = i2c->IICSTAT;
+ while ((readl(&i2c->IICSTAT) && I2CSTAT_BSY) && (i > 0)) {
+ udelay(1000);
i--;
}
- if ((status & I2CSTAT_BSY) || GetI2CSDA () == 0) {
+ if ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) || GetI2CSDA() == 0) {
#ifdef CONFIG_S3C2410
- ulong old_gpecon = gpio->GPECON;
+ ulong old_gpecon = readl(&gpio->GPECON);
#endif
#ifdef CONFIG_S3C2400
- ulong old_gpecon = gpio->PGCON;
+ ulong old_gpecon = readl(&gpio->PGCON);
#endif
- /* bus still busy probably by (most) previously interrupted transfer */
+ /* bus still busy probably by (most) previously interrupted
+ transfer */
#ifdef CONFIG_S3C2410
/* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */
- gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000;
+ writel((readl(&gpio->GPECON) & ~0xF0000000) | 0x10000000,
+ &gpio->GPECON);
#endif
#ifdef CONFIG_S3C2400
/* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */
- gpio->PGCON = (gpio->PGCON & ~0x00003c00) | 0x00001000;
+ writel((readl(&gpio->PGCON) & ~0x00003c00) | 0x00001000,
+ &gpio->PGCON);
#endif
/* toggle I2CSCL until bus idle */
- SetI2CSCL (0);
- udelay (1000);
+ SetI2CSCL(0);
+ udelay(1000);
i = 10;
- while ((i > 0) && (GetI2CSDA () != 1)) {
- SetI2CSCL (1);
- udelay (1000);
- SetI2CSCL (0);
- udelay (1000);
+ while ((i > 0) && (GetI2CSDA() != 1)) {
+ SetI2CSCL(1);
+ udelay(1000);
+ SetI2CSCL(0);
+ udelay(1000);
i--;
}
- SetI2CSCL (1);
- udelay (1000);
+ SetI2CSCL(1);
+ udelay(1000);
/* restore pin functions */
#ifdef CONFIG_S3C2410
- gpio->GPECON = old_gpecon;
+ writel(old_gpecon, &gpio->GPECON);
#endif
#ifdef CONFIG_S3C2400
- gpio->PGCON = old_gpecon;
+ writel(old_gpecon, &gpio->PGCON);
#endif
}
/* calculate prescaler and divisor values */
- freq = get_PCLK ();
+ freq = get_PCLK();
if ((freq / pres / (16 + 1)) > speed)
/* set prescaler to 512 */
pres = 512;
/* set prescaler, divisor according to freq, also set
* ACKGEN, IRQ */
- i2c->IICCON = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0);
+ writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->IICCON);
/* init to SLAVE REVEIVE and set slaveaddr */
- i2c->IICSTAT = 0;
- i2c->IICADD = slaveadd;
+ writel(0, &i2c->IICSTAT);
+ writel(slaveadd, &i2c->IICADD);
/* program Master Transmit (and implicit STOP) */
- i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA;
+ writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT);
}
* 0 we skip the address write cycle.
*/
static
-int i2c_transfer (unsigned char cmd_type,
- unsigned char chip,
- unsigned char addr[],
- unsigned char addr_len,
- unsigned char data[], unsigned short data_len)
+int i2c_transfer(unsigned char cmd_type,
+ unsigned char chip,
+ unsigned char addr[],
+ unsigned char addr_len,
+ unsigned char data[], unsigned short data_len)
{
- S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C ();
- int i, status, result;
+ struct s3c24x0_i2c *i2c = s3c24x0_get_base_i2c();
+ int i, result;
if (data == 0 || data_len == 0) {
/*Don't support data transfer of no length or to address 0 */
- printf ("i2c_transfer: bad call\n");
+ printf("i2c_transfer: bad call\n");
return I2C_NOK;
}
/* Check I2C bus idle */
i = I2C_TIMEOUT * 1000;
- status = i2c->IICSTAT;
- while ((i > 0) && (status & I2CSTAT_BSY)) {
- udelay (1000);
- status = i2c->IICSTAT;
+ while ((readl(&i2c->IICSTAT) & I2CSTAT_BSY) && (i > 0)) {
+ udelay(1000);
i--;
}
- if (status & I2CSTAT_BSY)
+ if (readl(&i2c->IICSTAT) & I2CSTAT_BSY)
return I2C_NOK_TOUT;
- i2c->IICCON |= 0x80;
+ writel(readl(&i2c->IICCON) | 0x80, &i2c->IICCON);
result = I2C_OK;
switch (cmd_type) {
case I2C_WRITE:
if (addr && addr_len) {
- i2c->IICDS = chip;
+ writel(chip, &i2c->IICDS);
/* send START */
- i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP;
+ writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
+ &i2c->IICSTAT);
i = 0;
while ((i < addr_len) && (result == I2C_OK)) {
- result = WaitForXfer ();
- i2c->IICDS = addr[i];
- ReadWriteByte ();
+ result = WaitForXfer();
+ writel(addr[i], &i2c->IICDS);
+ ReadWriteByte();
i++;
}
i = 0;
while ((i < data_len) && (result == I2C_OK)) {
- result = WaitForXfer ();
- i2c->IICDS = data[i];
- ReadWriteByte ();
+ result = WaitForXfer();
+ writel(data[i], &i2c->IICDS);
+ ReadWriteByte();
i++;
}
} else {
- i2c->IICDS = chip;
+ writel(chip, &i2c->IICDS);
/* send START */
- i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP;
+ writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP,
+ &i2c->IICSTAT);
i = 0;
while ((i < data_len) && (result = I2C_OK)) {
- result = WaitForXfer ();
- i2c->IICDS = data[i];
- ReadWriteByte ();
+ result = WaitForXfer();
+ writel(data[i], &i2c->IICDS);
+ ReadWriteByte();
i++;
}
}
if (result == I2C_OK)
- result = WaitForXfer ();
+ result = WaitForXfer();
/* send STOP */
- i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA;
- ReadWriteByte ();
+ writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT);
+ ReadWriteByte();
break;
case I2C_READ:
if (addr && addr_len) {
- i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA;
- i2c->IICDS = chip;
+ writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->IICSTAT);
+ writel(chip, &i2c->IICDS);
/* send START */
- i2c->IICSTAT |= I2C_START_STOP;
- result = WaitForXfer ();
- if (IsACK ()) {
+ writel(readl(&i2c->IICSTAT) | I2C_START_STOP,
+ &i2c->IICSTAT);
+ result = WaitForXfer();
+ if (IsACK()) {
i = 0;
while ((i < addr_len) && (result == I2C_OK)) {
- i2c->IICDS = addr[i];
- ReadWriteByte ();
- result = WaitForXfer ();
+ writel(addr[i], &i2c->IICDS);
+ ReadWriteByte();
+ result = WaitForXfer();
i++;
}
- i2c->IICDS = chip;
+ writel(chip, &i2c->IICDS);
/* resend START */
- i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA |
- I2C_START_STOP;
- ReadWriteByte ();
- result = WaitForXfer ();
+ writel(I2C_MODE_MR | I2C_TXRX_ENA |
+ I2C_START_STOP, &i2c->IICSTAT);
+ ReadWriteByte();
+ result = WaitForXfer();
i = 0;
while ((i < data_len) && (result == I2C_OK)) {
/* disable ACK for final READ */
if (i == data_len - 1)
- i2c->IICCON &= ~0x80;
- ReadWriteByte ();
- result = WaitForXfer ();
- data[i] = i2c->IICDS;
+ writel(readl(&i2c->IICCON)
+ & ~0x80, &i2c->IICCON);
+ ReadWriteByte();
+ result = WaitForXfer();
+ data[i] = readl(&i2c->IICDS);
i++;
}
} else {
}
} else {
- i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA;
- i2c->IICDS = chip;
+ writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT);
+ writel(chip, &i2c->IICDS);
/* send START */
- i2c->IICSTAT |= I2C_START_STOP;
- result = WaitForXfer ();
+ writel(readl(&i2c->IICSTAT) | I2C_START_STOP,
+ &i2c->IICSTAT);
+ result = WaitForXfer();
- if (IsACK ()) {
+ if (IsACK()) {
i = 0;
while ((i < data_len) && (result == I2C_OK)) {
/* disable ACK for final READ */
if (i == data_len - 1)
- i2c->IICCON &= ~0x80;
- ReadWriteByte ();
- result = WaitForXfer ();
- data[i] = i2c->IICDS;
+ writel(readl(&i2c->IICCON) &
+ ~0x80, &i2c->IICCON);
+ ReadWriteByte();
+ result = WaitForXfer();
+ data[i] = readl(&i2c->IICDS);
i++;
}
} else {
}
/* send STOP */
- i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA;
- ReadWriteByte ();
+ writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->IICSTAT);
+ ReadWriteByte();
break;
default:
- printf ("i2c_transfer: bad call\n");
+ printf("i2c_transfer: bad call\n");
result = I2C_NOK;
break;
}
return (result);
}
-int i2c_probe (uchar chip)
+int i2c_probe(uchar chip)
{
uchar buf[1];
* address was <ACK>ed (i.e. there was a chip at that address which
* drove the data line low).
*/
- return (i2c_transfer (I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK);
+ return i2c_transfer(I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK;
}
-int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len)
+int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
uchar xaddr[4];
int ret;
if (alen > 4) {
- printf ("I2C read: addr len %d not supported\n", alen);
+ printf("I2C read: addr len %d not supported\n", alen);
return 1;
}
* hidden in the chip address.
*/
if (alen > 0)
- chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
+ chip |= ((addr >> (alen * 8)) &
+ CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
if ((ret =
- i2c_transfer (I2C_READ, chip << 1, &xaddr[4 - alen], alen,
- buffer, len)) != 0) {
- printf ("I2c read: failed %d\n", ret);
+ i2c_transfer(I2C_READ, chip << 1, &xaddr[4 - alen], alen,
+ buffer, len)) != 0) {
+ printf("I2c read: failed %d\n", ret);
return 1;
}
return 0;
}
-int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len)
+int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
uchar xaddr[4];
if (alen > 4) {
- printf ("I2C write: addr len %d not supported\n", alen);
+ printf("I2C write: addr len %d not supported\n", alen);
return 1;
}
* hidden in the chip address.
*/
if (alen > 0)
- chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
+ chip |= ((addr >> (alen * 8)) &
+ CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
#endif
return (i2c_transfer
(I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer,
len) != 0);
}
-#endif /* CONFIG_HARD_I2C */
+#endif /* CONFIG_HARD_I2C */
#include <common.h>
-#if 0
-#define DEBUGN printf
-#else
-#define DEBUGN(x, args ...) {}
-#endif
-
#include <nand.h>
#include <s3c2410.h>
#include <asm/io.h>
-#define __REGb(x) (*(volatile unsigned char *)(x))
-#define __REGi(x) (*(volatile unsigned int *)(x))
-
-#define NF_BASE 0x4e000000
-#define NFCONF __REGi(NF_BASE + 0x0)
-#define NFCMD __REGb(NF_BASE + 0x4)
-#define NFADDR __REGb(NF_BASE + 0x8)
-#define NFDATA __REGb(NF_BASE + 0xc)
-#define NFSTAT __REGb(NF_BASE + 0x10)
-#define NFECC0 __REGb(NF_BASE + 0x14)
-#define NFECC1 __REGb(NF_BASE + 0x15)
-#define NFECC2 __REGb(NF_BASE + 0x16)
-
#define S3C2410_NFCONF_EN (1<<15)
#define S3C2410_NFCONF_512BYTE (1<<14)
#define S3C2410_NFCONF_4STEP (1<<13)
static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
{
struct nand_chip *chip = mtd->priv;
+ struct s3c2410_nand *nand = s3c2410_get_base_nand();
- DEBUGN("hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl);
+ debugX(1, "hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl);
if (ctrl & NAND_CTRL_CHANGE) {
- ulong IO_ADDR_W = NF_BASE;
+ ulong IO_ADDR_W = (ulong)nand;
if (!(ctrl & NAND_CLE))
IO_ADDR_W |= S3C2410_ADDR_NCLE;
chip->IO_ADDR_W = (void *)IO_ADDR_W;
if (ctrl & NAND_NCE)
- NFCONF &= ~S3C2410_NFCONF_nFCE;
+ writel(readl(&nand->NFCONF) & ~S3C2410_NFCONF_nFCE,
+ &nand->NFCONF);
else
- NFCONF |= S3C2410_NFCONF_nFCE;
+ writel(readl(&nand->NFCONF) | S3C2410_NFCONF_nFCE,
+ &nand->NFCONF);
}
if (cmd != NAND_CMD_NONE)
static int s3c2410_dev_ready(struct mtd_info *mtd)
{
- DEBUGN("dev_ready\n");
- return (NFSTAT & 0x01);
+ struct s3c2410_nand *nand = s3c2410_get_base_nand();
+ debugX(1, "dev_ready\n");
+ return readl(&nand->NFSTAT) & 0x01;
}
#ifdef CONFIG_S3C2410_NAND_HWECC
void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
{
- DEBUGN("s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode);
- NFCONF |= S3C2410_NFCONF_INITECC;
+ struct s3c2410_nand *nand = s3c2410_get_base_nand();
+ debugX(1, "s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode);
+ writel(readl(&nand->NFCONF) | S3C2410_NFCONF_INITECC, &nand->NFCONF);
}
static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
ecc_code[0] = NFECC0;
ecc_code[1] = NFECC1;
ecc_code[2] = NFECC2;
- DEBUGN("s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n",
- mtd , ecc_code[0], ecc_code[1], ecc_code[2]);
+ debugX(1, "s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n",
+ mtd , ecc_code[0], ecc_code[1], ecc_code[2]);
return 0;
}
{
u_int32_t cfg;
u_int8_t tacls, twrph0, twrph1;
- S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER();
+ struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
+ struct s3c2410_nand *nand_reg = s3c2410_get_base_nand();
- DEBUGN("board_nand_init()\n");
+ debugX(1, "board_nand_init()\n");
- clk_power->CLKCON |= (1 << 4);
+ writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);
/* initialize hardware */
- twrph0 = 3; twrph1 = 0; tacls = 0;
+ twrph0 = 3;
+ twrph1 = 0;
+ tacls = 0;
cfg = S3C2410_NFCONF_EN;
cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
-
- NFCONF = cfg;
+ writel(cfg, &nand_reg->NFCONF);
/* initialize nand_chip data structure */
- nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)0x4e00000c;
+ nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->NFDATA;
/* read_buf and write_buf are default */
/* read_byte and write_byte are default */
nand->options = 0;
#endif
- DEBUGN("end of nand_init\n");
+ debugX(1, "end of nand_init\n");
return 0;
}
LIB := $(obj)libonenand.a
COBJS-$(CONFIG_CMD_ONENAND) := onenand_uboot.o onenand_base.o onenand_bbt.o
+COBJS-$(CONFIG_SAMSUNG_ONENAND) += samsung.o
COBJS := $(COBJS-y)
SRCS := $(COBJS:.o=.c)
--- /dev/null
+/*
+ * S3C64XX/S5PC100 OneNAND driver at U-Boot
+ *
+ * Copyright (C) 2008-2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * Implementation:
+ * Emulate the pseudo BufferRAM
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <linux/mtd/compat.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/onenand.h>
+#include <linux/mtd/samsung_onenand.h>
+
+#include <asm/io.h>
+#include <asm/errno.h>
+
+#ifdef ONENAND_DEBUG
+#define DPRINTK(format, args...) \
+do { \
+ printf("%s[%d]: " format "\n", __func__, __LINE__, ##args); \
+} while (0)
+#else
+#define DPRINTK(...) do { } while (0)
+#endif
+
+#define ONENAND_ERASE_STATUS 0x00
+#define ONENAND_MULTI_ERASE_SET 0x01
+#define ONENAND_ERASE_START 0x03
+#define ONENAND_UNLOCK_START 0x08
+#define ONENAND_UNLOCK_END 0x09
+#define ONENAND_LOCK_START 0x0A
+#define ONENAND_LOCK_END 0x0B
+#define ONENAND_LOCK_TIGHT_START 0x0C
+#define ONENAND_LOCK_TIGHT_END 0x0D
+#define ONENAND_UNLOCK_ALL 0x0E
+#define ONENAND_OTP_ACCESS 0x12
+#define ONENAND_SPARE_ACCESS_ONLY 0x13
+#define ONENAND_MAIN_ACCESS_ONLY 0x14
+#define ONENAND_ERASE_VERIFY 0x15
+#define ONENAND_MAIN_SPARE_ACCESS 0x16
+#define ONENAND_PIPELINE_READ 0x4000
+
+#if defined(CONFIG_S3C64XX)
+#define MAP_00 (0x0 << 24)
+#define MAP_01 (0x1 << 24)
+#define MAP_10 (0x2 << 24)
+#define MAP_11 (0x3 << 24)
+#elif defined(CONFIG_S5PC1XX)
+#define MAP_00 (0x0 << 26)
+#define MAP_01 (0x1 << 26)
+#define MAP_10 (0x2 << 26)
+#define MAP_11 (0x3 << 26)
+#endif
+
+/* read/write of XIP buffer */
+#define CMD_MAP_00(mem_addr) (MAP_00 | ((mem_addr) << 1))
+/* read/write to the memory device */
+#define CMD_MAP_01(mem_addr) (MAP_01 | (mem_addr))
+/* control special functions of the memory device */
+#define CMD_MAP_10(mem_addr) (MAP_10 | (mem_addr))
+/* direct interface(direct access) with the memory device */
+#define CMD_MAP_11(mem_addr) (MAP_11 | ((mem_addr) << 2))
+
+struct s3c_onenand {
+ struct mtd_info *mtd;
+ void __iomem *base;
+ void __iomem *ahb_addr;
+ int bootram_command;
+ void __iomem *page_buf;
+ void __iomem *oob_buf;
+ unsigned int (*mem_addr)(int fba, int fpa, int fsa);
+ struct samsung_onenand *reg;
+};
+
+static struct s3c_onenand *onenand;
+
+static int s3c_read_cmd(unsigned int cmd)
+{
+ return readl(onenand->ahb_addr + cmd);
+}
+
+static void s3c_write_cmd(int value, unsigned int cmd)
+{
+ writel(value, onenand->ahb_addr + cmd);
+}
+
+/*
+ * MEM_ADDR
+ *
+ * fba: flash block address
+ * fpa: flash page address
+ * fsa: flash sector address
+ *
+ * return the buffer address on the memory device
+ * It will be combined with CMD_MAP_XX
+ */
+#if defined(CONFIG_S3C64XX)
+static unsigned int s3c_mem_addr(int fba, int fpa, int fsa)
+{
+ return (fba << 12) | (fpa << 6) | (fsa << 4);
+}
+#elif defined(CONFIG_S5PC1XX)
+static unsigned int s3c_mem_addr(int fba, int fpa, int fsa)
+{
+ return (fba << 13) | (fpa << 7) | (fsa << 5);
+}
+#endif
+
+static void s3c_onenand_reset(void)
+{
+ unsigned long timeout = 0x10000;
+ int stat;
+
+ writel(ONENAND_MEM_RESET_COLD, &onenand->reg->mem_reset);
+ while (timeout--) {
+ stat = readl(&onenand->reg->int_err_stat);
+ if (stat & RST_CMP)
+ break;
+ }
+ stat = readl(&onenand->reg->int_err_stat);
+ writel(stat, &onenand->reg->int_err_ack);
+
+ /* Clear interrupt */
+ writel(0x0, &onenand->reg->int_err_ack);
+ /* Clear the ECC status */
+ writel(0x0, &onenand->reg->ecc_err_stat);
+}
+
+static unsigned short s3c_onenand_readw(void __iomem *addr)
+{
+ struct onenand_chip *this = onenand->mtd->priv;
+ int reg = addr - this->base;
+ int word_addr = reg >> 1;
+ int value;
+
+ /* It's used for probing time */
+ switch (reg) {
+ case ONENAND_REG_MANUFACTURER_ID:
+ return readl(&onenand->reg->manufact_id);
+ case ONENAND_REG_DEVICE_ID:
+ return readl(&onenand->reg->device_id);
+ case ONENAND_REG_VERSION_ID:
+ return readl(&onenand->reg->flash_ver_id);
+ case ONENAND_REG_DATA_BUFFER_SIZE:
+ return readl(&onenand->reg->data_buf_size);
+ case ONENAND_REG_TECHNOLOGY:
+ return readl(&onenand->reg->tech);
+ case ONENAND_REG_SYS_CFG1:
+ return readl(&onenand->reg->mem_cfg);
+
+ /* Used at unlock all status */
+ case ONENAND_REG_CTRL_STATUS:
+ return 0;
+
+ case ONENAND_REG_WP_STATUS:
+ return ONENAND_WP_US;
+
+ default:
+ break;
+ }
+
+ /* BootRAM access control */
+ if (reg < ONENAND_DATARAM && onenand->bootram_command) {
+ if (word_addr == 0)
+ return readl(&onenand->reg->manufact_id);
+ if (word_addr == 1)
+ return readl(&onenand->reg->device_id);
+ if (word_addr == 2)
+ return readl(&onenand->reg->flash_ver_id);
+ }
+
+ value = s3c_read_cmd(CMD_MAP_11(word_addr)) & 0xffff;
+ printk(KERN_INFO "s3c_onenand_readw: Illegal access"
+ " at reg 0x%x, value 0x%x\n", word_addr, value);
+ return value;
+}
+
+static void s3c_onenand_writew(unsigned short value, void __iomem *addr)
+{
+ struct onenand_chip *this = onenand->mtd->priv;
+ int reg = addr - this->base;
+ int word_addr = reg >> 1;
+
+ /* It's used for probing time */
+ switch (reg) {
+ case ONENAND_REG_SYS_CFG1:
+ writel(value, &onenand->reg->mem_cfg);
+ return;
+
+ case ONENAND_REG_START_ADDRESS1:
+ case ONENAND_REG_START_ADDRESS2:
+ return;
+
+ /* Lock/lock-tight/unlock/unlock_all */
+ case ONENAND_REG_START_BLOCK_ADDRESS:
+ return;
+
+ default:
+ break;
+ }
+
+ /* BootRAM access control */
+ if (reg < ONENAND_DATARAM) {
+ if (value == ONENAND_CMD_READID) {
+ onenand->bootram_command = 1;
+ return;
+ }
+ if (value == ONENAND_CMD_RESET) {
+ writel(ONENAND_MEM_RESET_COLD,
+ &onenand->reg->mem_reset);
+ onenand->bootram_command = 0;
+ return;
+ }
+ }
+
+ printk(KERN_INFO "s3c_onenand_writew: Illegal access"
+ " at reg 0x%x, value 0x%x\n", word_addr, value);
+
+ s3c_write_cmd(value, CMD_MAP_11(word_addr));
+}
+
+static int s3c_onenand_wait(struct mtd_info *mtd, int state)
+{
+ unsigned int flags = INT_ACT;
+ unsigned int stat, ecc;
+ unsigned long timeout = 0x100000;
+
+ switch (state) {
+ case FL_READING:
+ flags |= BLK_RW_CMP | LOAD_CMP;
+ break;
+ case FL_WRITING:
+ flags |= BLK_RW_CMP | PGM_CMP;
+ break;
+ case FL_ERASING:
+ flags |= BLK_RW_CMP | ERS_CMP;
+ break;
+ case FL_LOCKING:
+ flags |= BLK_RW_CMP;
+ break;
+ default:
+ break;
+ }
+
+ while (timeout--) {
+ stat = readl(&onenand->reg->int_err_stat);
+ if (stat & flags)
+ break;
+ }
+
+ /* To get correct interrupt status in timeout case */
+ stat = readl(&onenand->reg->int_err_stat);
+ writel(stat, &onenand->reg->int_err_ack);
+
+ /*
+ * In the Spec. it checks the controller status first
+ * However if you get the correct information in case of
+ * power off recovery (POR) test, it should read ECC status first
+ */
+ if (stat & LOAD_CMP) {
+ ecc = readl(&onenand->reg->ecc_err_stat);
+ if (ecc & ONENAND_ECC_4BIT_UNCORRECTABLE) {
+ printk(KERN_INFO "%s: ECC error = 0x%04x\n",
+ __func__, ecc);
+ mtd->ecc_stats.failed++;
+ return -EBADMSG;
+ }
+ }
+
+ if (stat & (LOCKED_BLK | ERS_FAIL | PGM_FAIL | LD_FAIL_ECC_ERR)) {
+ printk(KERN_INFO "%s: controller error = 0x%04x\n",
+ __func__, stat);
+ if (stat & LOCKED_BLK)
+ printk(KERN_INFO "%s: it's locked error = 0x%04x\n",
+ __func__, stat);
+
+ return -EIO;
+ }
+
+ return 0;
+}
+
+static int s3c_onenand_command(struct mtd_info *mtd, int cmd,
+ loff_t addr, size_t len)
+{
+ struct onenand_chip *this = mtd->priv;
+ unsigned int *m, *s;
+ int fba, fpa, fsa = 0;
+ unsigned int mem_addr;
+ int i, mcount, scount;
+ int index;
+
+ fba = (int) (addr >> this->erase_shift);
+ fpa = (int) (addr >> this->page_shift);
+ fpa &= this->page_mask;
+
+ mem_addr = onenand->mem_addr(fba, fpa, fsa);
+
+ switch (cmd) {
+ case ONENAND_CMD_READ:
+ case ONENAND_CMD_READOOB:
+ case ONENAND_CMD_BUFFERRAM:
+ ONENAND_SET_NEXT_BUFFERRAM(this);
+ default:
+ break;
+ }
+
+ index = ONENAND_CURRENT_BUFFERRAM(this);
+
+ /*
+ * Emulate Two BufferRAMs and access with 4 bytes pointer
+ */
+ m = (unsigned int *) onenand->page_buf;
+ s = (unsigned int *) onenand->oob_buf;
+
+ if (index) {
+ m += (this->writesize >> 2);
+ s += (mtd->oobsize >> 2);
+ }
+
+ mcount = mtd->writesize >> 2;
+ scount = mtd->oobsize >> 2;
+
+ switch (cmd) {
+ case ONENAND_CMD_READ:
+ /* Main */
+ for (i = 0; i < mcount; i++)
+ *m++ = s3c_read_cmd(CMD_MAP_01(mem_addr));
+ return 0;
+
+ case ONENAND_CMD_READOOB:
+ writel(TSRF, &onenand->reg->trans_spare);
+ /* Main */
+ for (i = 0; i < mcount; i++)
+ *m++ = s3c_read_cmd(CMD_MAP_01(mem_addr));
+
+ /* Spare */
+ for (i = 0; i < scount; i++)
+ *s++ = s3c_read_cmd(CMD_MAP_01(mem_addr));
+
+ writel(0, &onenand->reg->trans_spare);
+ return 0;
+
+ case ONENAND_CMD_PROG:
+ /* Main */
+ for (i = 0; i < mcount; i++)
+ s3c_write_cmd(*m++, CMD_MAP_01(mem_addr));
+ return 0;
+
+ case ONENAND_CMD_PROGOOB:
+ writel(TSRF, &onenand->reg->trans_spare);
+
+ /* Main - dummy write */
+ for (i = 0; i < mcount; i++)
+ s3c_write_cmd(0xffffffff, CMD_MAP_01(mem_addr));
+
+ /* Spare */
+ for (i = 0; i < scount; i++)
+ s3c_write_cmd(*s++, CMD_MAP_01(mem_addr));
+
+ writel(0, &onenand->reg->trans_spare);
+ return 0;
+
+ case ONENAND_CMD_UNLOCK_ALL:
+ s3c_write_cmd(ONENAND_UNLOCK_ALL, CMD_MAP_10(mem_addr));
+ return 0;
+
+ case ONENAND_CMD_ERASE:
+ s3c_write_cmd(ONENAND_ERASE_START, CMD_MAP_10(mem_addr));
+ return 0;
+
+ case ONENAND_CMD_MULTIBLOCK_ERASE:
+ s3c_write_cmd(ONENAND_MULTI_ERASE_SET, CMD_MAP_10(mem_addr));
+ return 0;
+
+ case ONENAND_CMD_ERASE_VERIFY:
+ s3c_write_cmd(ONENAND_ERASE_VERIFY, CMD_MAP_10(mem_addr));
+ return 0;
+
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static unsigned char *s3c_get_bufferram(struct mtd_info *mtd, int area)
+{
+ struct onenand_chip *this = mtd->priv;
+ int index = ONENAND_CURRENT_BUFFERRAM(this);
+ unsigned char *p;
+
+ if (area == ONENAND_DATARAM) {
+ p = (unsigned char *) onenand->page_buf;
+ if (index == 1)
+ p += this->writesize;
+ } else {
+ p = (unsigned char *) onenand->oob_buf;
+ if (index == 1)
+ p += mtd->oobsize;
+ }
+
+ return p;
+}
+
+static int onenand_read_bufferram(struct mtd_info *mtd, loff_t addr, int area,
+ unsigned char *buffer, int offset,
+ size_t count)
+{
+ unsigned char *p;
+
+ p = s3c_get_bufferram(mtd, area);
+ memcpy(buffer, p + offset, count);
+ return 0;
+}
+
+static int onenand_write_bufferram(struct mtd_info *mtd, loff_t addr, int area,
+ const unsigned char *buffer, int offset,
+ size_t count)
+{
+ unsigned char *p;
+
+ p = s3c_get_bufferram(mtd, area);
+ memcpy(p + offset, buffer, count);
+ return 0;
+}
+
+static int s3c_onenand_bbt_wait(struct mtd_info *mtd, int state)
+{
+ struct samsung_onenand *reg = (struct samsung_onenand *)onenand->base;
+ unsigned int flags = INT_ACT | LOAD_CMP;
+ unsigned int stat;
+ unsigned long timeout = 0x10000;
+
+ while (timeout--) {
+ stat = readl(®->int_err_stat);
+ if (stat & flags)
+ break;
+ }
+ /* To get correct interrupt status in timeout case */
+ stat = readl(&onenand->reg->int_err_stat);
+ writel(stat, &onenand->reg->int_err_ack);
+
+ if (stat & LD_FAIL_ECC_ERR) {
+ s3c_onenand_reset();
+ return ONENAND_BBT_READ_ERROR;
+ }
+
+ if (stat & LOAD_CMP) {
+ int ecc = readl(&onenand->reg->ecc_err_stat);
+ if (ecc & ONENAND_ECC_4BIT_UNCORRECTABLE) {
+ s3c_onenand_reset();
+ return ONENAND_BBT_READ_ERROR;
+ }
+ }
+
+ return 0;
+}
+
+static void s3c_onenand_check_lock_status(struct mtd_info *mtd)
+{
+ struct onenand_chip *this = mtd->priv;
+ unsigned int block, end;
+ int tmp;
+
+ end = this->chipsize >> this->erase_shift;
+
+ for (block = 0; block < end; block++) {
+ tmp = s3c_read_cmd(CMD_MAP_01(onenand->mem_addr(block, 0, 0)));
+
+ if (readl(&onenand->reg->int_err_stat) & LOCKED_BLK) {
+ printf("block %d is write-protected!\n", block);
+ writel(LOCKED_BLK, &onenand->reg->int_err_ack);
+ }
+ }
+}
+
+static void s3c_onenand_do_lock_cmd(struct mtd_info *mtd, loff_t ofs,
+ size_t len, int cmd)
+{
+ struct onenand_chip *this = mtd->priv;
+ int start, end, start_mem_addr, end_mem_addr;
+
+ start = ofs >> this->erase_shift;
+ start_mem_addr = onenand->mem_addr(start, 0, 0);
+ end = start + (len >> this->erase_shift) - 1;
+ end_mem_addr = onenand->mem_addr(end, 0, 0);
+
+ if (cmd == ONENAND_CMD_LOCK) {
+ s3c_write_cmd(ONENAND_LOCK_START, CMD_MAP_10(start_mem_addr));
+ s3c_write_cmd(ONENAND_LOCK_END, CMD_MAP_10(end_mem_addr));
+ } else {
+ s3c_write_cmd(ONENAND_UNLOCK_START, CMD_MAP_10(start_mem_addr));
+ s3c_write_cmd(ONENAND_UNLOCK_END, CMD_MAP_10(end_mem_addr));
+ }
+
+ this->wait(mtd, FL_LOCKING);
+}
+
+static void s3c_onenand_unlock_all(struct mtd_info *mtd)
+{
+ struct onenand_chip *this = mtd->priv;
+ loff_t ofs = 0;
+ size_t len = this->chipsize;
+
+ /* FIXME workaround */
+ this->subpagesize = mtd->writesize;
+ mtd->subpage_sft = 0;
+
+ if (this->options & ONENAND_HAS_UNLOCK_ALL) {
+ /* Write unlock command */
+ this->command(mtd, ONENAND_CMD_UNLOCK_ALL, 0, 0);
+
+ /* No need to check return value */
+ this->wait(mtd, FL_LOCKING);
+
+ /* Workaround for all block unlock in DDP */
+ if (!ONENAND_IS_DDP(this)) {
+ s3c_onenand_check_lock_status(mtd);
+ return;
+ }
+
+ /* All blocks on another chip */
+ ofs = this->chipsize >> 1;
+ len = this->chipsize >> 1;
+ }
+
+ s3c_onenand_do_lock_cmd(mtd, ofs, len, ONENAND_CMD_UNLOCK);
+ s3c_onenand_check_lock_status(mtd);
+}
+
+#ifdef CONFIG_S3C64XX
+static void s3c_set_width_regs(struct onenand_chip *this)
+{
+ int dev_id, density;
+ int fba, fpa, fsa;
+ int dbs_dfs;
+
+ dev_id = DEVICE_ID0_REG;
+
+ density = (dev_id >> ONENAND_DEVICE_DENSITY_SHIFT) & 0xf;
+ dbs_dfs = !!(dev_id & ONENAND_DEVICE_IS_DDP);
+
+ fba = density + 7;
+ if (dbs_dfs)
+ fba--; /* Decrease the fba */
+ fpa = 6;
+ if (density >= ONENAND_DEVICE_DENSITY_512Mb)
+ fsa = 2;
+ else
+ fsa = 1;
+
+ DPRINTK("FBA %lu, FPA %lu, FSA %lu, DDP %lu",
+ FBA_WIDTH0_REG, FPA_WIDTH0_REG, FSA_WIDTH0_REG,
+ DDP_DEVICE_REG);
+
+ DPRINTK("mem_cfg0 0x%lx, sync mode %lu, "
+ "dev_page_size %lu, BURST LEN %lu",
+ MEM_CFG0_REG, SYNC_MODE_REG,
+ DEV_PAGE_SIZE_REG, BURST_LEN0_REG);
+
+ DEV_PAGE_SIZE_REG = 0x1;
+
+ FBA_WIDTH0_REG = fba;
+ FPA_WIDTH0_REG = fpa;
+ FSA_WIDTH0_REG = fsa;
+ DBS_DFS_WIDTH0_REG = dbs_dfs;
+}
+#endif
+
+void s3c_onenand_init(struct mtd_info *mtd)
+{
+ struct onenand_chip *this = mtd->priv;
+ u32 size = (4 << 10); /* 4 KiB */
+
+ onenand = malloc(sizeof(struct s3c_onenand));
+ if (!onenand)
+ return;
+
+ onenand->page_buf = malloc(size * sizeof(char));
+ if (!onenand->page_buf)
+ return;
+ memset(onenand->page_buf, 0xff, size);
+
+ onenand->oob_buf = malloc(128 * sizeof(char));
+ if (!onenand->oob_buf)
+ return;
+ memset(onenand->oob_buf, 0xff, 128);
+
+ onenand->mtd = mtd;
+
+#if defined(CONFIG_S3C64XX)
+ onenand->base = (void *)0x70100000;
+ onenand->ahb_addr = (void *)0x20000000;
+#elif defined(CONFIG_S5PC1XX)
+ onenand->base = (void *)0xE7100000;
+ onenand->ahb_addr = (void *)0xB0000000;
+#endif
+ onenand->mem_addr = s3c_mem_addr;
+ onenand->reg = (struct samsung_onenand *)onenand->base;
+
+ this->read_word = s3c_onenand_readw;
+ this->write_word = s3c_onenand_writew;
+
+ this->wait = s3c_onenand_wait;
+ this->bbt_wait = s3c_onenand_bbt_wait;
+ this->unlock_all = s3c_onenand_unlock_all;
+ this->command = s3c_onenand_command;
+
+ this->read_bufferram = onenand_read_bufferram;
+ this->write_bufferram = onenand_write_bufferram;
+
+ this->options |= ONENAND_RUNTIME_BADBLOCK_CHECK;
+}
#endif
#include <rtc.h>
+#include <asm/io.h>
/*#define DEBUG*/
static inline void SetRTC_Access(RTC_ACCESS a)
{
- S3C24X0_RTC * const rtc = S3C24X0_GetBase_RTC();
+ struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc();
+
switch (a) {
- case RTC_ENABLE:
- rtc->RTCCON |= 0x01; break;
+ case RTC_ENABLE:
+ writeb(readb(&rtc->RTCCON) | 0x01, &rtc->RTCCON);
+ break;
- case RTC_DISABLE:
- rtc->RTCCON &= ~0x01; break;
+ case RTC_DISABLE:
+ writeb(readb(&rtc->RTCCON) & ~0x01, &rtc->RTCCON);
+ break;
}
}
/* ------------------------------------------------------------------------- */
-int rtc_get (struct rtc_time *tmp)
+int rtc_get(struct rtc_time *tmp)
{
- S3C24X0_RTC * const rtc = S3C24X0_GetBase_RTC();
+ struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc();
uchar sec, min, hour, mday, wday, mon, year;
- uchar a_sec,a_min, a_hour, a_date, a_mon, a_year, a_armed;
+ uchar a_sec, a_min, a_hour, a_date, a_mon, a_year, a_armed;
/* enable access to RTC registers */
SetRTC_Access(RTC_ENABLE);
/* read RTC registers */
do {
- sec = rtc->BCDSEC;
- min = rtc->BCDMIN;
- hour = rtc->BCDHOUR;
- mday = rtc->BCDDATE;
- wday = rtc->BCDDAY;
- mon = rtc->BCDMON;
- year = rtc->BCDYEAR;
- } while (sec != rtc->BCDSEC);
+ sec = readb(&rtc->BCDSEC);
+ min = readb(&rtc->BCDMIN);
+ hour = readb(&rtc->BCDHOUR);
+ mday = readb(&rtc->BCDDATE);
+ wday = readb(&rtc->BCDDAY);
+ mon = readb(&rtc->BCDMON);
+ year = readb(&rtc->BCDYEAR);
+ } while (sec != readb(&rtc->BCDSEC));
/* read ALARM registers */
- a_sec = rtc->ALMSEC;
- a_min = rtc->ALMMIN;
- a_hour = rtc->ALMHOUR;
- a_date = rtc->ALMDATE;
- a_mon = rtc->ALMMON;
- a_year = rtc->ALMYEAR;
- a_armed = rtc->RTCALM;
+ a_sec = readb(&rtc->ALMSEC);
+ a_min = readb(&rtc->ALMMIN);
+ a_hour = readb(&rtc->ALMHOUR);
+ a_date = readb(&rtc->ALMDATE);
+ a_mon = readb(&rtc->ALMMON);
+ a_year = readb(&rtc->ALMYEAR);
+ a_armed = readb(&rtc->RTCALM);
/* disable access to RTC registers */
SetRTC_Access(RTC_DISABLE);
#ifdef RTC_DEBUG
- printf ( "Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
- "hr: %02x min: %02x sec: %02x\n",
- year, mon, mday, wday,
- hour, min, sec);
- printf ( "Alarms: %02x: year: %02x month: %02x date: %02x hour: %02x min: %02x sec: %02x\n",
- a_armed,
- a_year, a_mon, a_date,
- a_hour, a_min, a_sec);
+ printf("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
+ "hr: %02x min: %02x sec: %02x\n",
+ year, mon, mday, wday, hour, min, sec);
+ printf("Alarms: %02x: year: %02x month: %02x date: %02x hour: "
+ "%02x min: %02x sec: %02x\n",
+ a_armed, a_year, a_mon, a_date, a_hour, a_min, a_sec);
#endif
- tmp->tm_sec = bcd2bin(sec & 0x7F);
- tmp->tm_min = bcd2bin(min & 0x7F);
+ tmp->tm_sec = bcd2bin(sec & 0x7F);
+ tmp->tm_min = bcd2bin(min & 0x7F);
tmp->tm_hour = bcd2bin(hour & 0x3F);
tmp->tm_mday = bcd2bin(mday & 0x3F);
tmp->tm_mon = bcd2bin(mon & 0x1F);
tmp->tm_year = bcd2bin(year);
tmp->tm_wday = bcd2bin(wday & 0x07);
- if(tmp->tm_year<70)
- tmp->tm_year+=2000;
+ if (tmp->tm_year < 70)
+ tmp->tm_year += 2000;
else
- tmp->tm_year+=1900;
- tmp->tm_yday = 0;
- tmp->tm_isdst= 0;
+ tmp->tm_year += 1900;
+ tmp->tm_yday = 0;
+ tmp->tm_isdst = 0;
#ifdef RTC_DEBUG
- printf ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
- tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+ printf("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
#endif
return 0;
}
-int rtc_set (struct rtc_time *tmp)
+int rtc_set(struct rtc_time *tmp)
{
- S3C24X0_RTC * const rtc = S3C24X0_GetBase_RTC();
+ struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc();
uchar sec, min, hour, mday, wday, mon, year;
#ifdef RTC_DEBUG
- printf ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
- tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
- tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
+ printf("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
+ tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
+ tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
#endif
- year = bin2bcd(tmp->tm_year % 100);
- mon = bin2bcd(tmp->tm_mon);
- wday = bin2bcd(tmp->tm_wday);
- mday = bin2bcd(tmp->tm_mday);
- hour = bin2bcd(tmp->tm_hour);
- min = bin2bcd(tmp->tm_min);
- sec = bin2bcd(tmp->tm_sec);
+ year = bin2bcd(tmp->tm_year % 100);
+ mon = bin2bcd(tmp->tm_mon);
+ wday = bin2bcd(tmp->tm_wday);
+ mday = bin2bcd(tmp->tm_mday);
+ hour = bin2bcd(tmp->tm_hour);
+ min = bin2bcd(tmp->tm_min);
+ sec = bin2bcd(tmp->tm_sec);
/* enable access to RTC registers */
SetRTC_Access(RTC_ENABLE);
/* write RTC registers */
- rtc->BCDSEC = sec;
- rtc->BCDMIN = min;
- rtc->BCDHOUR = hour;
- rtc->BCDDATE = mday;
- rtc->BCDDAY = wday;
- rtc->BCDMON = mon;
- rtc->BCDYEAR = year;
+ writeb(sec, &rtc->BCDSEC);
+ writeb(min, &rtc->BCDMIN);
+ writeb(hour, &rtc->BCDHOUR);
+ writeb(mday, &rtc->BCDDATE);
+ writeb(wday, &rtc->BCDDAY);
+ writeb(mon, &rtc->BCDMON);
+ writeb(year, &rtc->BCDYEAR);
/* disable access to RTC registers */
SetRTC_Access(RTC_DISABLE);
return 0;
}
-void rtc_reset (void)
+void rtc_reset(void)
{
- S3C24X0_RTC * const rtc = S3C24X0_GetBase_RTC();
+ struct s3c24x0_rtc *rtc = s3c24x0_get_base_rtc();
- rtc->RTCCON = (rtc->RTCCON & ~0x06) | 0x08;
- rtc->RTCCON &= ~(0x08|0x01);
+ writeb((readb(&rtc->RTCCON) & ~0x06) | 0x08, &rtc->RTCCON);
+ writeb(readb(&rtc->RTCCON) & ~(0x08 | 0x01), &rtc->RTCCON);
}
#endif
COBJS-$(CONFIG_SYS_NS16550) += ns16550.o
COBJS-$(CONFIG_DRIVER_S3C4510_UART) += s3c4510b_uart.o
COBJS-$(CONFIG_S3C64XX) += s3c64xx.o
+COBJS-$(CONFIG_S5PC1XX) += serial_s5pc1xx.o
COBJS-$(CONFIG_SYS_NS16550_SERIAL) += serial.o
COBJS-$(CONFIG_CLPS7111_SERIAL) += serial_clps7111.o
COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o
#elif defined(CONFIG_SERIAL3)
# if defined(CONFIG_TRAB)
-# #error "TRAB supports only CONFIG_SERIAL1"
+# error "TRAB supports only CONFIG_SERIAL1"
# endif
#define UART_NR S3C24X0_UART2
#error "Bad: you didn't configure serial ..."
#endif
+#include <asm/io.h>
+
#if defined(CONFIG_SERIAL_MULTI)
#include <serial.h>
/* Multi serial device functions */
#define DECLARE_S3C_SERIAL_FUNCTIONS(port) \
- int s3serial##port##_init (void) {\
- return serial_init_dev(port);}\
- void s3serial##port##_setbrg (void) {\
- serial_setbrg_dev(port);}\
- int s3serial##port##_getc (void) {\
- return serial_getc_dev(port);}\
- int s3serial##port##_tstc (void) {\
- return serial_tstc_dev(port);}\
- void s3serial##port##_putc (const char c) {\
- serial_putc_dev(port, c);}\
- void s3serial##port##_puts (const char *s) {\
- serial_puts_dev(port, s);}
-
-#define INIT_S3C_SERIAL_STRUCTURE(port,name,bus) {\
- name,\
- bus,\
- s3serial##port##_init,\
- s3serial##port##_setbrg,\
- s3serial##port##_getc,\
- s3serial##port##_tstc,\
- s3serial##port##_putc,\
- s3serial##port##_puts, }
+ int s3serial##port##_init(void) \
+ { \
+ return serial_init_dev(port); \
+ } \
+ void s3serial##port##_setbrg(void) \
+ { \
+ serial_setbrg_dev(port); \
+ } \
+ int s3serial##port##_getc(void) \
+ { \
+ return serial_getc_dev(port); \
+ } \
+ int s3serial##port##_tstc(void) \
+ { \
+ return serial_tstc_dev(port); \
+ } \
+ void s3serial##port##_putc(const char c) \
+ { \
+ serial_putc_dev(port, c); \
+ } \
+ void s3serial##port##_puts(const char *s) \
+ { \
+ serial_puts_dev(port, s); \
+ }
+
+#define INIT_S3C_SERIAL_STRUCTURE(port, name, bus) { \
+ name, \
+ bus, \
+ s3serial##port##_init, \
+ s3serial##port##_setbrg, \
+ s3serial##port##_getc, \
+ s3serial##port##_tstc, \
+ s3serial##port##_putc, \
+ s3serial##port##_puts, \
+}
#endif /* CONFIG_SERIAL_MULTI */
+#ifdef CONFIG_HWFLOW
+static int hwflow;
+#endif
+
void _serial_setbrg(const int dev_index)
{
- S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index);
+ struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
unsigned int reg = 0;
int i;
/* value is calculated so : (int)(PCLK/16./baudrate) -1 */
reg = get_PCLK() / (16 * gd->baudrate) - 1;
- uart->UBRDIV = reg;
- for (i = 0; i < 100; i++);
+ writel(reg, &uart->UBRDIV);
+ for (i = 0; i < 100; i++)
+ /* Delay */ ;
}
+
#if defined(CONFIG_SERIAL_MULTI)
-static inline void
-serial_setbrg_dev(unsigned int dev_index)
+static inline void serial_setbrg_dev(unsigned int dev_index)
{
_serial_setbrg(dev_index);
}
*/
static int serial_init_dev(const int dev_index)
{
- S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index);
+ struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
+
+#ifdef CONFIG_HWFLOW
+ hwflow = 0; /* turned off by default */
+#endif
/* FIFO enable, Tx/Rx FIFO clear */
- uart->UFCON = 0x07;
- uart->UMCON = 0x0;
+ writel(0x07, &uart->UFCON);
+ writel(0x0, &uart->UMCON);
/* Normal,No parity,1 stop,8 bit */
- uart->ULCON = 0x3;
+ writel(0x3, &uart->ULCON);
/*
* tx=level,rx=edge,disable timeout int.,enable rx error int.,
* normal,interrupt or polling
*/
- uart->UCON = 0x245;
+ writel(0x245, &uart->UCON);
#ifdef CONFIG_HWFLOW
- uart->UMCON = 0x1; /* RTS up */
+ writel(0x1, &uart->UMCON); /* RTS up */
#endif
/* FIXME: This is sooooooooooooooooooo ugly */
#if defined(CONFIG_ARCH_GTA02_v1) || defined(CONFIG_ARCH_GTA02_v2)
/* we need auto hw flow control on the gsm and gps port */
if (dev_index == 0 || dev_index == 1)
- uart->UMCON = 0x10;
+ writel(0x10, &uart->UMCON);
#endif
_serial_setbrg(dev_index);
/* Initialise the serial port. The settings are always 8 data bits, no parity,
* 1 stop bit, no start bits.
*/
-int serial_init (void)
+int serial_init(void)
{
return serial_init_dev(UART_NR);
}
* otherwise. When the function is succesfull, the character read is
* written into its argument c.
*/
-int _serial_getc (const int dev_index)
+int _serial_getc(const int dev_index)
{
- S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index);
+ struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
- /* wait for character to arrive */
- while (!(uart->UTRSTAT & 0x1));
+ while (!(readl(&uart->UTRSTAT) & 0x1))
+ /* wait for character to arrive */ ;
- return uart->URXH & 0xff;
+ return readb(&uart->URXH) & 0xff;
}
+
#if defined(CONFIG_SERIAL_MULTI)
static inline int serial_getc_dev(unsigned int dev_index)
{
return _serial_getc(dev_index);
}
#else
-int serial_getc (void)
+int serial_getc(void)
{
return _serial_getc(UART_NR);
}
#endif
#ifdef CONFIG_HWFLOW
-static int hwflow = 0; /* turned off by default */
int hwflow_onoff(int on)
{
- switch(on) {
+ switch (on) {
case 0:
default:
- break; /* return current */
+ break; /* return current */
case 1:
- hwflow = 1; /* turn on */
+ hwflow = 1; /* turn on */
break;
case -1:
- hwflow = 0; /* turn off */
+ hwflow = 0; /* turn off */
break;
}
return hwflow;
/*
* Output a single byte to the serial port.
*/
-void _serial_putc (const char c, const int dev_index)
+void _serial_putc(const char c, const int dev_index)
{
- S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index);
+ struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
#ifdef CONFIG_MODEM_SUPPORT
if (be_quiet)
return;
#endif
- /* wait for room in the tx FIFO */
- while (!(uart->UTRSTAT & 0x2));
+ while (!(readl(&uart->UTRSTAT) & 0x2))
+ /* wait for room in the tx FIFO */ ;
#ifdef CONFIG_HWFLOW
- /* Wait for CTS up */
- while(hwflow && !(uart->UMSTAT & 0x1))
- ;
+ while (hwflow && !(readl(&uart->UMSTAT) & 0x1))
+ /* Wait for CTS up */ ;
#endif
- uart->UTXH = c;
+ writeb(c, &uart->UTXH);
/* If \n, also do \r */
if (c == '\n')
- serial_putc ('\r');
+ serial_putc('\r');
}
+
#if defined(CONFIG_SERIAL_MULTI)
static inline void serial_putc_dev(unsigned int dev_index, const char c)
{
*/
int _serial_tstc(const int dev_index)
{
- S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index);
+ struct s3c24x0_uart *uart = s3c24x0_get_base_uart(dev_index);
- return uart->UTRSTAT & 0x1;
+ return readl(&uart->UTRSTAT) & 0x1;
}
+
#if defined(CONFIG_SERIAL_MULTI)
-static inline int
-serial_tstc_dev(unsigned int dev_index)
+static inline int serial_tstc_dev(unsigned int dev_index)
{
return _serial_tstc(dev_index);
}
void _serial_puts(const char *s, const int dev_index)
{
while (*s) {
- _serial_putc (*s++, dev_index);
+ _serial_putc(*s++, dev_index);
}
}
+
#if defined(CONFIG_SERIAL_MULTI)
-static inline void
-serial_puts_dev(int dev_index, const char *s)
+static inline void serial_puts_dev(int dev_index, const char *s)
{
_serial_puts(s, dev_index);
}
#else
-void
-serial_puts (const char *s)
+void serial_puts(const char *s)
{
_serial_puts(s, UART_NR);
}
#if defined(CONFIG_SERIAL_MULTI)
DECLARE_S3C_SERIAL_FUNCTIONS(0);
struct serial_device s3c24xx_serial0_device =
- INIT_S3C_SERIAL_STRUCTURE(0, "s3ser0", "S3UART1");
+INIT_S3C_SERIAL_STRUCTURE(0, "s3ser0", "S3UART1");
DECLARE_S3C_SERIAL_FUNCTIONS(1);
struct serial_device s3c24xx_serial1_device =
- INIT_S3C_SERIAL_STRUCTURE(1, "s3ser1", "S3UART2");
+INIT_S3C_SERIAL_STRUCTURE(1, "s3ser1", "S3UART2");
DECLARE_S3C_SERIAL_FUNCTIONS(2);
struct serial_device s3c24xx_serial2_device =
- INIT_S3C_SERIAL_STRUCTURE(2, "s3ser2", "S3UART3");
-
+INIT_S3C_SERIAL_STRUCTURE(2, "s3ser2", "S3UART3");
#endif /* CONFIG_SERIAL_MULTI */
--- /dev/null
+/*
+ * (C) Copyright 2009 SAMSUNG Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * based on drivers/serial/s3c64xx.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/uart.h>
+#include <asm/arch/clk.h>
+#include <serial.h>
+
+static inline struct s5pc1xx_uart *s5pc1xx_get_base_uart(int dev_index)
+{
+ u32 offset = dev_index * sizeof(struct s5pc1xx_uart);
+
+ if (cpu_is_s5pc100())
+ return (struct s5pc1xx_uart *)(S5PC100_UART_BASE + offset);
+ else
+ return (struct s5pc1xx_uart *)(S5PC110_UART_BASE + offset);
+}
+
+/*
+ * The coefficient, used to calculate the baudrate on S5PC1XX UARTs is
+ * calculated as
+ * C = UBRDIV * 16 + number_of_set_bits_in_UDIVSLOT
+ * however, section 31.6.11 of the datasheet doesn't recomment using 1 for 1,
+ * 3 for 2, ... (2^n - 1) for n, instead, they suggest using these constants:
+ */
+static const int udivslot[] = {
+ 0,
+ 0x0080,
+ 0x0808,
+ 0x0888,
+ 0x2222,
+ 0x4924,
+ 0x4a52,
+ 0x54aa,
+ 0x5555,
+ 0xd555,
+ 0xd5d5,
+ 0xddd5,
+ 0xdddd,
+ 0xdfdd,
+ 0xdfdf,
+ 0xffdf,
+};
+
+void serial_setbrg_dev(const int dev_index)
+{
+ DECLARE_GLOBAL_DATA_PTR;
+ struct s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(dev_index);
+ u32 pclk = get_pclk();
+ u32 baudrate = gd->baudrate;
+ u32 val;
+
+ val = pclk / baudrate;
+
+ writel(val / 16 - 1, &uart->ubrdiv);
+ writel(udivslot[val % 16], &uart->udivslot);
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ */
+int serial_init_dev(const int dev_index)
+{
+ struct s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(dev_index);
+
+ /* reset and enable FIFOs, set triggers to the maximum */
+ writel(0, &uart->ufcon);
+ writel(0, &uart->umcon);
+ /* 8N1 */
+ writel(0x3, &uart->ulcon);
+ /* No interrupts, no DMA, pure polling */
+ writel(0x245, &uart->ucon);
+
+ serial_setbrg_dev(dev_index);
+
+ return 0;
+}
+
+static int serial_err_check(const int dev_index)
+{
+ struct s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(dev_index);
+
+ if (readl(&uart->uerstat) & 0xf)
+ return 1;
+
+ return 0;
+}
+
+/*
+ * Read a single byte from the serial port. Returns 1 on success, 0
+ * otherwise. When the function is succesfull, the character read is
+ * written into its argument c.
+ */
+int serial_getc_dev(const int dev_index)
+{
+ struct s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(dev_index);
+
+ /* wait for character to arrive */
+ while (!(readl(&uart->utrstat) & 0x1)) {
+ if (serial_err_check(dev_index))
+ return 0;
+ }
+
+ return (int)(readl(&uart->urxh) & 0xff);
+}
+
+/*
+ * Output a single byte to the serial port.
+ */
+void serial_putc_dev(const char c, const int dev_index)
+{
+ struct s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(dev_index);
+
+ /* wait for room in the tx FIFO */
+ while (!(readl(&uart->utrstat) & 0x2)) {
+ if (serial_err_check(dev_index))
+ return;
+ }
+
+ writel(c, &uart->utxh);
+
+ /* If \n, also do \r */
+ if (c == '\n')
+ serial_putc('\r');
+}
+
+/*
+ * Test whether a character is in the RX buffer
+ */
+int serial_tstc_dev(const int dev_index)
+{
+ struct s5pc1xx_uart *const uart = s5pc1xx_get_base_uart(dev_index);
+
+ return (int)(readl(&uart->utrstat) & 0x1);
+}
+
+void serial_puts_dev(const char *s, const int dev_index)
+{
+ while (*s)
+ serial_putc_dev(*s++, dev_index);
+}
+
+/* Multi serial device functions */
+#define DECLARE_S5P_SERIAL_FUNCTIONS(port) \
+int s5p_serial##port##_init(void) { return serial_init_dev(port); } \
+void s5p_serial##port##_setbrg(void) { serial_setbrg_dev(port); } \
+int s5p_serial##port##_getc(void) { return serial_getc_dev(port); } \
+int s5p_serial##port##_tstc(void) { return serial_tstc_dev(port); } \
+void s5p_serial##port##_putc(const char c) { serial_putc_dev(c, port); } \
+void s5p_serial##port##_puts(const char *s) { serial_puts_dev(s, port); }
+
+#define INIT_S5P_SERIAL_STRUCTURE(port, name, bus) { \
+ name, \
+ bus, \
+ s5p_serial##port##_init, \
+ s5p_serial##port##_setbrg, \
+ s5p_serial##port##_getc, \
+ s5p_serial##port##_tstc, \
+ s5p_serial##port##_putc, \
+ s5p_serial##port##_puts, }
+
+DECLARE_S5P_SERIAL_FUNCTIONS(0);
+struct serial_device s5pc1xx_serial0_device =
+ INIT_S5P_SERIAL_STRUCTURE(0, "s5pser0", "S5PUART0");
+DECLARE_S5P_SERIAL_FUNCTIONS(1);
+struct serial_device s5pc1xx_serial1_device =
+ INIT_S5P_SERIAL_STRUCTURE(1, "s5pser1", "S5PUART1");
+DECLARE_S5P_SERIAL_FUNCTIONS(2);
+struct serial_device s5pc1xx_serial2_device =
+ INIT_S5P_SERIAL_STRUCTURE(2, "s5pser2", "S5PUART2");
+DECLARE_S5P_SERIAL_FUNCTIONS(3);
+struct serial_device s5pc1xx_serial3_device =
+ INIT_S5P_SERIAL_STRUCTURE(3, "s5pser3", "S5PUART3");
--- /dev/null
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_CLK_H_
+#define __ASM_ARM_ARCH_CLK_H_
+
+void s5pc1xx_clock_init(void);
+
+extern unsigned long (*get_pll_clk)(int pllreg);
+extern unsigned long (*get_arm_clk)(void);
+extern unsigned long (*get_pclk)(void);
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_CLOCK_H_
+#define __ASM_ARM_ARCH_CLOCK_H_
+
+#ifndef __ASSEMBLY__
+struct s5pc100_clock {
+ unsigned long apll_lock;
+ unsigned long mpll_lock;
+ unsigned long epll_lock;
+ unsigned long hpll_lock;
+ unsigned char res1[0xf0];
+ unsigned long apll_con;
+ unsigned long mpll_con;
+ unsigned long epll_con;
+ unsigned long hpll_con;
+ unsigned char res2[0xf0];
+ unsigned long src0;
+ unsigned long src1;
+ unsigned long src2;
+ unsigned long src3;
+ unsigned char res3[0xf0];
+ unsigned long div0;
+ unsigned long div1;
+ unsigned long div2;
+ unsigned long div3;
+ unsigned long div4;
+ unsigned char res4[0x1ec];
+ unsigned long gate_d00;
+ unsigned long gate_d01;
+ unsigned long gate_d02;
+ unsigned char res5[0x54];
+ unsigned long gate_sclk0;
+ unsigned long gate_sclk1;
+};
+
+struct s5pc110_clock {
+ unsigned long apll_lock;
+ unsigned char res1[0x4];
+ unsigned long mpll_lock;
+ unsigned char res2[0x4];
+ unsigned long epll_lock;
+ unsigned char res3[0xc];
+ unsigned long vpll_lock;
+ unsigned char res4[0xdc];
+ unsigned long apll_con;
+ unsigned char res5[0x4];
+ unsigned long mpll_con;
+ unsigned char res6[0x4];
+ unsigned long epll_con;
+ unsigned char res7[0xc];
+ unsigned long vpll_con;
+ unsigned char res8[0xdc];
+ unsigned long src0;
+ unsigned long src1;
+ unsigned long src2;
+ unsigned long src3;
+ unsigned char res9[0xf0];
+ unsigned long div0;
+ unsigned long div1;
+ unsigned long div2;
+ unsigned long div3;
+ unsigned long div4;
+ unsigned char res10[0x1ec];
+ unsigned long gate_d00;
+ unsigned long gate_d01;
+ unsigned long gate_d02;
+ unsigned char res11[0x54];
+ unsigned long gate_sclk0;
+ unsigned long gate_sclk1;
+};
+#endif
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef _S5PC1XX_CPU_H
+#define _S5PC1XX_CPU_H
+
+#define S5PC1XX_ADDR_BASE 0xE0000000
+
+#define S5PC1XX_CLOCK_BASE 0xE0100000
+
+/* S5PC100 */
+#define S5PC100_GPIO_BASE 0xE0300000
+#define S5PC100_VIC0_BASE 0xE4000000
+#define S5PC100_VIC1_BASE 0xE4100000
+#define S5PC100_VIC2_BASE 0xE4200000
+#define S5PC100_DMC_BASE 0xE6000000
+#define S5PC100_SROMC_BASE 0xE7000000
+#define S5PC100_ONENAND_BASE 0xE7100000
+#define S5PC100_PWMTIMER_BASE 0xEA000000
+#define S5PC100_WATCHDOG_BASE 0xEA200000
+#define S5PC100_UART_BASE 0xEC000000
+
+/* S5PC110 */
+#define S5PC110_GPIO_BASE 0xE0200000
+#define S5PC110_PWMTIMER_BASE 0xE2500000
+#define S5PC110_WATCHDOG_BASE 0xE2700000
+#define S5PC110_UART_BASE 0xE2900000
+#define S5PC110_SROMC_BASE 0xE8000000
+#define S5PC110_DMC0_BASE 0xF0000000
+#define S5PC110_DMC1_BASE 0xF1400000
+#define S5PC110_VIC0_BASE 0xF2000000
+#define S5PC110_VIC1_BASE 0xF2100000
+#define S5PC110_VIC2_BASE 0xF2200000
+#define S5PC110_VIC3_BASE 0xF2300000
+
+/* Chip ID */
+#define S5PC1XX_PRO_ID 0xE0000000
+
+#ifndef __ASSEMBLY__
+/* CPU detection macros */
+extern unsigned int s5pc1xx_cpu_id;
+
+#define IS_SAMSUNG_TYPE(type, id) \
+static inline int cpu_is_##type(void) \
+{ \
+ return s5pc1xx_cpu_id == id ? 1 : 0; \
+}
+
+IS_SAMSUNG_TYPE(s5pc100, 0xc100)
+IS_SAMSUNG_TYPE(s5pc110, 0xc110)
+#endif
+
+#endif /* _S5PC1XX_CPU_H */
--- /dev/null
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_GPIO_H
+#define __ASM_ARCH_GPIO_H
+
+#ifndef __ASSEMBLY__
+struct s5pc1xx_gpio_bank {
+ unsigned long con;
+ unsigned long dat;
+ unsigned long pull;
+ unsigned long drv;
+ unsigned long pdn_con;
+ unsigned long pdn_pull;
+ unsigned char res1[8];
+};
+
+struct s5pc100_gpio {
+ struct s5pc1xx_gpio_bank gpio_a0;
+ struct s5pc1xx_gpio_bank gpio_a1;
+ struct s5pc1xx_gpio_bank gpio_b;
+ struct s5pc1xx_gpio_bank gpio_c;
+ struct s5pc1xx_gpio_bank gpio_d;
+ struct s5pc1xx_gpio_bank gpio_e0;
+ struct s5pc1xx_gpio_bank gpio_e1;
+ struct s5pc1xx_gpio_bank gpio_f0;
+ struct s5pc1xx_gpio_bank gpio_f1;
+ struct s5pc1xx_gpio_bank gpio_f2;
+ struct s5pc1xx_gpio_bank gpio_f3;
+ struct s5pc1xx_gpio_bank gpio_g0;
+ struct s5pc1xx_gpio_bank gpio_g1;
+ struct s5pc1xx_gpio_bank gpio_g2;
+ struct s5pc1xx_gpio_bank gpio_g3;
+ struct s5pc1xx_gpio_bank gpio_i;
+ struct s5pc1xx_gpio_bank gpio_j0;
+ struct s5pc1xx_gpio_bank gpio_j1;
+ struct s5pc1xx_gpio_bank gpio_j2;
+ struct s5pc1xx_gpio_bank gpio_j3;
+ struct s5pc1xx_gpio_bank gpio_j4;
+ struct s5pc1xx_gpio_bank gpio_k0;
+ struct s5pc1xx_gpio_bank gpio_k1;
+ struct s5pc1xx_gpio_bank gpio_k2;
+ struct s5pc1xx_gpio_bank gpio_k3;
+ struct s5pc1xx_gpio_bank gpio_l0;
+ struct s5pc1xx_gpio_bank gpio_l1;
+ struct s5pc1xx_gpio_bank gpio_l2;
+ struct s5pc1xx_gpio_bank gpio_l3;
+ struct s5pc1xx_gpio_bank gpio_l4;
+ struct s5pc1xx_gpio_bank gpio_h0;
+ struct s5pc1xx_gpio_bank gpio_h1;
+ struct s5pc1xx_gpio_bank gpio_h2;
+ struct s5pc1xx_gpio_bank gpio_h3;
+};
+
+struct s5pc110_gpio {
+ struct s5pc1xx_gpio_bank gpio_a0;
+ struct s5pc1xx_gpio_bank gpio_a1;
+ struct s5pc1xx_gpio_bank gpio_b;
+ struct s5pc1xx_gpio_bank gpio_c0;
+ struct s5pc1xx_gpio_bank gpio_c1;
+ struct s5pc1xx_gpio_bank gpio_d0;
+ struct s5pc1xx_gpio_bank gpio_d1;
+ struct s5pc1xx_gpio_bank gpio_e0;
+ struct s5pc1xx_gpio_bank gpio_e1;
+ struct s5pc1xx_gpio_bank gpio_f0;
+ struct s5pc1xx_gpio_bank gpio_f1;
+ struct s5pc1xx_gpio_bank gpio_f2;
+ struct s5pc1xx_gpio_bank gpio_f3;
+ struct s5pc1xx_gpio_bank gpio_g0;
+ struct s5pc1xx_gpio_bank gpio_g1;
+ struct s5pc1xx_gpio_bank gpio_g2;
+ struct s5pc1xx_gpio_bank gpio_g3;
+ struct s5pc1xx_gpio_bank gpio_i;
+ struct s5pc1xx_gpio_bank gpio_j0;
+ struct s5pc1xx_gpio_bank gpio_j1;
+ struct s5pc1xx_gpio_bank gpio_j2;
+ struct s5pc1xx_gpio_bank gpio_j3;
+ struct s5pc1xx_gpio_bank gpio_j4;
+ struct s5pc1xx_gpio_bank gpio_mp0_1;
+ struct s5pc1xx_gpio_bank gpio_mp0_2;
+ struct s5pc1xx_gpio_bank gpio_mp0_3;
+ struct s5pc1xx_gpio_bank gpio_mp0_4;
+ struct s5pc1xx_gpio_bank gpio_mp0_5;
+ struct s5pc1xx_gpio_bank gpio_mp0_6;
+ struct s5pc1xx_gpio_bank gpio_mp0_7;
+ struct s5pc1xx_gpio_bank gpio_mp1_0;
+ struct s5pc1xx_gpio_bank gpio_mp1_1;
+ struct s5pc1xx_gpio_bank gpio_mp1_2;
+ struct s5pc1xx_gpio_bank gpio_mp1_3;
+ struct s5pc1xx_gpio_bank gpio_mp1_4;
+ struct s5pc1xx_gpio_bank gpio_mp1_5;
+ struct s5pc1xx_gpio_bank gpio_mp1_6;
+ struct s5pc1xx_gpio_bank gpio_mp1_7;
+ struct s5pc1xx_gpio_bank gpio_mp1_8;
+ struct s5pc1xx_gpio_bank gpio_mp2_0;
+ struct s5pc1xx_gpio_bank gpio_mp2_1;
+ struct s5pc1xx_gpio_bank gpio_mp2_2;
+ struct s5pc1xx_gpio_bank gpio_mp2_3;
+ struct s5pc1xx_gpio_bank gpio_mp2_4;
+ struct s5pc1xx_gpio_bank gpio_mp2_5;
+ struct s5pc1xx_gpio_bank gpio_mp2_6;
+ struct s5pc1xx_gpio_bank gpio_mp2_7;
+ struct s5pc1xx_gpio_bank gpio_mp2_8;
+ struct s5pc1xx_gpio_bank res1[48];
+ struct s5pc1xx_gpio_bank gpio_h0;
+ struct s5pc1xx_gpio_bank gpio_h1;
+ struct s5pc1xx_gpio_bank gpio_h2;
+ struct s5pc1xx_gpio_bank gpio_h3;
+};
+#endif
+
+#endif
--- /dev/null
+/*
+ * Copyright (c) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARM_ARCH_POWER_H_
+#define __ASM_ARM_ARCH_POWER_H_
+
+/*
+ * Power control
+ */
+#define S5PC100_OTHERS 0xE0108200
+#define S5PC100_RST_STAT 0xE0108300
+#define S5PC100_SLEEP_WAKEUP (1 << 3)
+#define S5PC100_WAKEUP_STAT 0xE0108304
+#define S5PC100_INFORM0 0xE0108400
+
+#define S5PC110_RST_STAT 0xE010A000
+#define S5PC110_SLEEP_WAKEUP (1 << 3)
+#define S5PC110_WAKEUP_STAT 0xE010C200
+#define S5PC110_OTHERS 0xE010E000
+#define S5PC110_USB_PHY_CON 0xE010E80C
+#define S5PC110_INFORM0 0xE010F000
+
+#endif
--- /dev/null
+/*
+ * Copyright (C) 2009 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ * Minkyu Kang <mk7.kang@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARM_ARCH_PWM_H_
+#define __ASM_ARM_ARCH_PWM_H_
+
+/* PWM timer addressing */
+#define S5PC100_TIMER_BASE S5PC100_PWMTIMER_BASE
+#define S5PC110_TIMER_BASE S5PC110_PWMTIMER_BASE
+
+/* Interval mode(Auto Reload) of PWM Timer 4 */
+#define S5PC1XX_TCON4_AUTO_RELOAD (1 << 22)
+/* Update TCNTB4 */
+#define S5PC1XX_TCON4_UPDATE (1 << 21)
+/* start bit of PWM Timer 4 */
+#define S5PC1XX_TCON4_START (1 << 20)
+
+#ifndef __ASSEMBLY__
+struct s5pc1xx_timer {
+ unsigned long tcfg0;
+ unsigned long tcfg1;
+ unsigned long tcon;
+ unsigned long tcntb0;
+ unsigned long tcmpb0;
+ unsigned long tcnto0;
+ unsigned long tcntb1;
+ unsigned long tcmpb1;
+ unsigned long tcnto1;
+ unsigned long tcntb2;
+ unsigned long tcmpb2;
+ unsigned long tcnto2;
+ unsigned long tcntb3;
+ unsigned long res1;
+ unsigned long tcnto3;
+ unsigned long tcntb4;
+ unsigned long tcnto4;
+ unsigned long tintcstat;
+};
+#endif /* __ASSEMBLY__ */
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Heungjun Kim <riverful.kim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARCH_UART_H_
+#define __ASM_ARCH_UART_H_
+
+#ifndef __ASSEMBLY__
+struct s5pc1xx_uart {
+ unsigned long ulcon;
+ unsigned long ucon;
+ unsigned long ufcon;
+ unsigned long umcon;
+ unsigned long utrstat;
+ unsigned long uerstat;
+ unsigned long ufstat;
+ unsigned long umstat;
+ unsigned char utxh;
+ unsigned char res1[3];
+ unsigned char urxh;
+ unsigned char res2[3];
+ unsigned long ubrdiv;
+ unsigned short udivslot;
+ unsigned char res3[2];
+ unsigned char res4[0x3d0];
+};
+#endif /* __ASSEMBLY__ */
+
+#endif
#define CONFIG_SYS_LOAD_ADDR 0x33000000 /* default load address */
-/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
-/* it to wrap 100 times (total 1562500) to get 1 sec. */
-#define CONFIG_SYS_HZ 1562500
+#define CONFIG_SYS_HZ 1000
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SYS_LOAD_ADDR 0x0cf00000 /* default load address */
-/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
-/* it to wrap 100 times (total 1562500) to get 1 sec. */
-#define CONFIG_SYS_HZ 1562500
+#define CONFIG_SYS_HZ 1000
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_SYS_LOAD_ADDR 0x33000000 /* default load address */
-/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
-/* it to wrap 100 times (total 1562500) to get 1 sec. */
-#define CONFIG_SYS_HZ 1562500
+#define CONFIG_SYS_HZ 1000
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
--- /dev/null
+/*
+ * (C) Copyright 2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * HeungJun Kim <riverful.kim@samsung.com>
+ * Inki Dae <inki.dae@samsung.com>
+ *
+ * Configuation settings for the SAMSUNG SMDKC100 board.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */
+#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */
+#define CONFIG_S5PC1XX 1 /* which is in a S5PC1XX Family */
+#define CONFIG_S5PC100 1 /* which is in a S5PC100 */
+#define CONFIG_SMDKC100 1 /* working with SMDKC100 */
+
+#include <asm/arch/cpu.h> /* get chip and board defs */
+
+#define CONFIG_ARCH_CPU_INIT
+
+#define CONFIG_DISPLAY_CPUINFO
+#define CONFIG_DISPLAY_BOARDINFO
+
+#undef CONFIG_SKIP_RELOCATE_UBOOT
+
+#define CONFIG_L2_OFF
+
+/* input clock of PLL: SMDKC100 has 12MHz input clock */
+#define CONFIG_SYS_CLK_FREQ 12000000
+
+/* DRAM Base */
+#define CONFIG_SYS_SDRAM_BASE 0x30000000
+
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_INITRD_TAG
+#define CONFIG_CMDLINE_EDITING
+
+/*
+ * Size of malloc() pool
+ * 1MB = 0x100000, 0x100000 = 1024 * 1024
+ */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
+#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes for */
+ /* initial data */
+/*
+ * select serial console configuration
+ */
+#define CONFIG_SERIAL0 1 /* use SERIAL 0 on SMDKC100 */
+#define CONFIG_SERIAL_MULTI 1
+
+/* allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_BAUDRATE 115200
+
+/***********************************************************
+ * Command definition
+ ***********************************************************/
+#include <config_cmd_default.h>
+
+#undef CONFIG_CMD_FLASH
+#undef CONFIG_CMD_IMLS
+#undef CONFIG_CMD_NAND
+#undef CONFIG_CMD_NET
+
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_ONENAND
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_MTDPARTS
+
+#define CONFIG_BOOTDELAY 3
+
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_MTD_DEVICE
+#define CONFIG_MTD_PARTITIONS
+
+#define MTDIDS_DEFAULT "onenand0=s3c-onenand"
+#define MTDPARTS_DEFAULT "mtdparts=s3c-onenand:256k(bootloader)"\
+ ",128k@0x40000(params)"\
+ ",3m@0x60000(kernel)"\
+ ",16m@0x360000(test)"\
+ ",-(UBI)"
+
+#define NORMAL_MTDPARTS_DEFAULT MTDPARTS_DEFAULT
+
+#define CONFIG_BOOTCOMMAND "run ubifsboot"
+
+#define CONFIG_RAMDISK_BOOT "root=/dev/ram0 rw rootfstype=ext2" \
+ " console=ttySAC0,115200n8" \
+ " mem=128M"
+
+#define CONFIG_COMMON_BOOT "console=ttySAC0,115200n8" \
+ " mem=128M " \
+ " " MTDPARTS_DEFAULT
+
+#define CONFIG_BOOTARGS "root=/dev/mtdblock5 ubi.mtd=4" \
+ " rootfstype=cramfs " CONFIG_COMMON_BOOT
+
+#define CONFIG_UPDATEB "updateb=onenand erase 0x0 0x40000;" \
+ " onenand write 0x32008000 0x0 0x40000\0"
+
+#define CONFIG_ENV_OVERWRITE
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ CONFIG_UPDATEB \
+ "updatek=" \
+ "onenand erase 0x60000 0x300000;" \
+ "onenand write 0x31008000 0x60000 0x300000\0" \
+ "updateu=" \
+ "onenand erase block 147-4095;" \
+ "onenand write 0x32000000 0x1260000 0x8C0000\0" \
+ "bootk=" \
+ "onenand read 0x30007FC0 0x60000 0x300000;" \
+ "bootm 0x30007FC0\0" \
+ "flashboot=" \
+ "set bootargs root=/dev/mtdblock${bootblock} " \
+ "rootfstype=${rootfstype} " \
+ "ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT ";" \
+ "run bootk\0" \
+ "ubifsboot=" \
+ "set bootargs root=ubi0!rootfs rootfstype=ubifs " \
+ " ubi.mtd=${ubiblock} ${opts} " CONFIG_COMMON_BOOT "; " \
+ "run bootk\0" \
+ "boottrace=setenv opts initcall_debug; run bootcmd\0" \
+ "android=" \
+ "set bootargs root=ubi0!ramdisk ubi.mtd=${ubiblock} " \
+ "rootfstype=ubifs init=/init.sh " CONFIG_COMMON_BOOT "; " \
+ "run bootk\0" \
+ "nfsboot=" \
+ "set bootargs root=/dev/nfs ubi.mtd=${ubiblock} " \
+ "nfsroot=${nfsroot},nolock " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:" \
+ "${netmask}:nowplus:usb0:off " CONFIG_COMMON_BOOT "; " \
+ "run bootk\0" \
+ "ramboot=" \
+ "set bootargs " CONFIG_RAMDISK_BOOT \
+ " initrd=0x33000000,8M ramdisk=8192\0" \
+ "rootfstype=cramfs\0" \
+ "mtdparts=" MTDPARTS_DEFAULT "\0" \
+ "meminfo=mem=128M\0" \
+ "nfsroot=/nfsroot/arm\0" \
+ "bootblock=5\0" \
+ "ubiblock=4\0" \
+ "ubi=enabled"
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_PROMPT "SMDKC100 # "
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+/* Boot Argument Buffer Size */
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+/* memtest works on */
+#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
+#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5e00000)
+#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
+
+#define CONFIG_SYS_HZ 1000
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+/*-----------------------------------------------------------------------
+ * Stack sizes
+ *
+ * The stack sizes are set up in start.S using the settings below
+ */
+#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
+
+/* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */
+#define CONFIG_NR_DRAM_BANKS 1
+#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* SDRAM Bank #1 */
+#define PHYS_SDRAM_1_SIZE (128 << 20) /* 0x8000000, 128 MB Bank #1 */
+
+#define CONFIG_SYS_MONITOR_BASE 0x00000000
+
+/*-----------------------------------------------------------------------
+ * FLASH and environment organization
+ */
+#define CONFIG_SYS_NO_FLASH 1
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */
+#define CONFIG_IDENT_STRING " for SMDKC100"
+
+#define CONFIG_SYS_64BIT_VSPRINTF
+
+#if !defined(CONFIG_NAND_SPL) && (TEXT_BASE >= 0xc0000000)
+#define CONFIG_ENABLE_MMU
+#endif
+
+#ifdef CONFIG_ENABLE_MMU
+#define CONFIG_SYS_MAPPED_RAM_BASE 0xc0000000
+#else
+#define CONFIG_SYS_MAPPED_RAM_BASE CONFIG_SYS_SDRAM_BASE
+#endif
+
+/*-----------------------------------------------------------------------
+ * Boot configuration
+ */
+#define CONFIG_ENV_IS_IN_ONENAND 1
+#define CONFIG_ENV_SIZE (128 << 10) /* 128KiB, 0x20000 */
+#define CONFIG_ENV_ADDR (256 << 10) /* 256KiB, 0x40000 */
+#define CONFIG_ENV_OFFSET (256 << 10) /* 256KiB, 0x40000 */
+
+#define CONFIG_USE_ONENAND_BOARD_INIT
+#define CONFIG_SAMSUNG_ONENAND 1
+#define CONFIG_SYS_ONENAND_BASE 0xE7100000
+
+#define CONFIG_DOS_PARTITION 1
+
+#endif /* __CONFIG_H */
#define CONFIG_SYS_LOAD_ADDR 0x0CF00000 /* default load address */
-#ifdef CONFIG_TRAB_50MHZ
-/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
-/* it to wrap 100 times (total 1562500) to get 1 sec. */
-/* this should _really_ be calculated !! */
-#define CONFIG_SYS_HZ 1562500
-#else
-/* the PWM TImer 4 uses a counter of 10390 for 10 ms, so we need */
-/* it to wrap 100 times (total 1039000) to get 1 sec. */
-/* this should _really_ be calculated !! */
-#define CONFIG_SYS_HZ 1039000
-#endif
+#define CONFIG_SYS_HZ 1000
/* valid baudrates */
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define ONENAND_HAS_CONT_LOCK (0x0001)
#define ONENAND_HAS_UNLOCK_ALL (0x0002)
#define ONENAND_HAS_2PLANE (0x0004)
+#define ONENAND_RUNTIME_BADBLOCK_CHECK (0x0200)
#define ONENAND_PAGEBUF_ALLOC (0x1000)
#define ONENAND_OOBBUF_ALLOC (0x2000)
#define ONENAND_CMD_LOCK_TIGHT (0x2C)
#define ONENAND_CMD_UNLOCK_ALL (0x27)
#define ONENAND_CMD_ERASE (0x94)
+#define ONENAND_CMD_MULTIBLOCK_ERASE (0x95)
+#define ONENAND_CMD_ERASE_VERIFY (0x71)
#define ONENAND_CMD_RESET (0xF0)
#define ONENAND_CMD_READID (0x90)
* ECC Status Reigser FF00h (R)
*/
#define ONENAND_ECC_1BIT (1 << 0)
+#define ONENAND_ECC_1BIT_ALL (0x5555)
#define ONENAND_ECC_2BIT (1 << 1)
#define ONENAND_ECC_2BIT_ALL (0xAAAA)
+#define ONENAND_ECC_4BIT_UNCORRECTABLE (0x1010)
#endif /* __ONENAND_REG_H */
--- /dev/null
+/*
+ * Copyright (C) 2005-2009 Samsung Electronics
+ * Minkyu Kang <mk7.kang@samsung.com>
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __SAMSUNG_ONENAND_H__
+#define __SAMSUNG_ONENAND_H__
+
+/*
+ * OneNAND Controller
+ */
+
+#ifndef __ASSEMBLY__
+struct samsung_onenand {
+ unsigned long mem_cfg; /* 0x0000 */
+ unsigned char res1[0xc];
+ unsigned long burst_len; /* 0x0010 */
+ unsigned char res2[0xc];
+ unsigned long mem_reset; /* 0x0020 */
+ unsigned char res3[0xc];
+ unsigned long int_err_stat; /* 0x0030 */
+ unsigned char res4[0xc];
+ unsigned long int_err_mask; /* 0x0040 */
+ unsigned char res5[0xc];
+ unsigned long int_err_ack; /* 0x0050 */
+ unsigned char res6[0xc];
+ unsigned long ecc_err_stat; /* 0x0060 */
+ unsigned char res7[0xc];
+ unsigned long manufact_id; /* 0x0070 */
+ unsigned char res8[0xc];
+ unsigned long device_id; /* 0x0080 */
+ unsigned char res9[0xc];
+ unsigned long data_buf_size; /* 0x0090 */
+ unsigned char res10[0xc];
+ unsigned long boot_buf_size; /* 0x00A0 */
+ unsigned char res11[0xc];
+ unsigned long buf_amount; /* 0x00B0 */
+ unsigned char res12[0xc];
+ unsigned long tech; /* 0x00C0 */
+ unsigned char res13[0xc];
+ unsigned long fba; /* 0x00D0 */
+ unsigned char res14[0xc];
+ unsigned long fpa; /* 0x00E0 */
+ unsigned char res15[0xc];
+ unsigned long fsa; /* 0x00F0 */
+ unsigned char res16[0x3c];
+ unsigned long sync_mode; /* 0x0130 */
+ unsigned char res17[0xc];
+ unsigned long trans_spare; /* 0x0140 */
+ unsigned char res18[0x3c];
+ unsigned long err_page_addr; /* 0x0180 */
+ unsigned char res19[0x1c];
+ unsigned long int_pin_en; /* 0x01A0 */
+ unsigned char res20[0x1c];
+ unsigned long acc_clock; /* 0x01C0 */
+ unsigned char res21[0x1c];
+ unsigned long err_blk_addr; /* 0x01E0 */
+ unsigned char res22[0xc];
+ unsigned long flash_ver_id; /* 0x01F0 */
+ unsigned char res23[0x6c];
+ unsigned long watchdog_cnt_low; /* 0x0260 */
+ unsigned char res24[0xc];
+ unsigned long watchdog_cnt_hi; /* 0x0270 */
+ unsigned char res25[0xc];
+ unsigned long sync_write; /* 0x0280 */
+ unsigned char res26[0x1c];
+ unsigned long cold_reset; /* 0x02A0 */
+ unsigned char res27[0xc];
+ unsigned long ddp_device; /* 0x02B0 */
+ unsigned char res28[0xc];
+ unsigned long multi_plane; /* 0x02C0 */
+ unsigned char res29[0x1c];
+ unsigned long trans_mode; /* 0x02E0 */
+ unsigned char res30[0x1c];
+ unsigned long ecc_err_stat2; /* 0x0300 */
+ unsigned char res31[0xc];
+ unsigned long ecc_err_stat3; /* 0x0310 */
+ unsigned char res32[0xc];
+ unsigned long ecc_err_stat4; /* 0x0320 */
+ unsigned char res33[0x1c];
+ unsigned long dev_page_size; /* 0x0340 */
+ unsigned char res34[0x4c];
+ unsigned long int_mon_status; /* 0x0390 */
+};
+#endif
+
+#define ONENAND_MEM_RESET_HOT 0x3
+#define ONENAND_MEM_RESET_COLD 0x2
+#define ONENAND_MEM_RESET_WARM 0x1
+
+#define INT_ERR_ALL 0x3fff
+#define CACHE_OP_ERR (1 << 13)
+#define RST_CMP (1 << 12)
+#define RDY_ACT (1 << 11)
+#define INT_ACT (1 << 10)
+#define UNSUP_CMD (1 << 9)
+#define LOCKED_BLK (1 << 8)
+#define BLK_RW_CMP (1 << 7)
+#define ERS_CMP (1 << 6)
+#define PGM_CMP (1 << 5)
+#define LOAD_CMP (1 << 4)
+#define ERS_FAIL (1 << 3)
+#define PGM_FAIL (1 << 2)
+#define INT_TO (1 << 1)
+#define LD_FAIL_ECC_ERR (1 << 0)
+
+#define TSRF (1 << 0)
+
+/* common initialize function */
+extern void s3c_onenand_init(struct mtd_info *);
+
+#endif
#define S3C24X0_SPI_CHANNELS 1
#define PALETTE (0x14A00400) /* SJS */
-typedef enum {
+enum s3c24x0_uarts_nr {
S3C24X0_UART0,
S3C24X0_UART1,
-} S3C24X0_UARTS_NR;
+};
-/* S3C2400 device base addresses */
+/*S3C2400 device base addresses */
#define S3C24X0_MEMCTL_BASE 0x14000000
#define S3C24X0_USB_HOST_BASE 0x14200000
#define S3C24X0_INTERRUPT_BASE 0x14400000
#include <s3c24x0.h>
-static inline S3C24X0_MEMCTL * S3C24X0_GetBase_MEMCTL(void)
+static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
{
- return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE;
+ return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
}
-static inline S3C24X0_USB_HOST * S3C24X0_GetBase_USB_HOST(void)
+static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
{
- return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE;
+ return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
}
-static inline S3C24X0_INTERRUPT * S3C24X0_GetBase_INTERRUPT(void)
+static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
{
- return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE;
+ return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
}
-static inline S3C24X0_DMAS * S3C24X0_GetBase_DMAS(void)
+static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
{
- return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE;
+ return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
}
-static inline S3C24X0_CLOCK_POWER * S3C24X0_GetBase_CLOCK_POWER(void)
+static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
{
- return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE;
+ return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
}
-static inline S3C24X0_LCD * S3C24X0_GetBase_LCD(void)
+static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
{
- return (S3C24X0_LCD * const)S3C24X0_LCD_BASE;
+ return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
}
-static inline S3C24X0_UART * S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
+static inline struct s3c24x0_uart
+ *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
{
- return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000));
+ return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
}
-static inline S3C24X0_TIMERS * S3C24X0_GetBase_TIMERS(void)
+static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
{
- return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE;
+ return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
}
-static inline S3C24X0_USB_DEVICE * S3C24X0_GetBase_USB_DEVICE(void)
+static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
{
- return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE;
+ return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
}
-static inline S3C24X0_WATCHDOG * S3C24X0_GetBase_WATCHDOG(void)
+static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
{
- return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE;
+ return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
}
-static inline S3C24X0_I2C * S3C24X0_GetBase_I2C(void)
+static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
{
- return (S3C24X0_I2C * const)S3C24X0_I2C_BASE;
+ return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
}
-static inline S3C24X0_I2S * S3C24X0_GetBase_I2S(void)
+static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
{
- return (S3C24X0_I2S * const)S3C24X0_I2S_BASE;
+ return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
}
-static inline S3C24X0_GPIO * S3C24X0_GetBase_GPIO(void)
+static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
{
- return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE;
+ return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
}
-static inline S3C24X0_RTC * S3C24X0_GetBase_RTC(void)
+static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
{
- return (S3C24X0_RTC * const)S3C24X0_RTC_BASE;
+ return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
}
-static inline S3C2400_ADC * S3C2400_GetBase_ADC(void)
+static inline struct s3c2400_adc *s3c2400_get_base_adc(void)
{
- return (S3C2400_ADC * const)S3C24X0_ADC_BASE;
+ return (struct s3c2400_adc *)S3C24X0_ADC_BASE;
}
-static inline S3C24X0_SPI * S3C24X0_GetBase_SPI(void)
+static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
{
- return (S3C24X0_SPI * const)S3C24X0_SPI_BASE;
+ return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
}
-static inline S3C2400_MMC * S3C2400_GetBase_MMC(void)
+static inline struct s3c2400_mmc *s3c2400_get_base_mmc(void)
{
- return (S3C2400_MMC * const)S3C2400_MMC_BASE;
+ return (struct s3c2400_mmc *)S3C2400_MMC_BASE;
}
-#if 0
-/* Memory control */
-#define rBWSCON (*(volatile unsigned *)0x14000000)
-#define rBANKCON0 (*(volatile unsigned *)0x14000004)
-#define rBANKCON1 (*(volatile unsigned *)0x14000008)
-#define rBANKCON2 (*(volatile unsigned *)0x1400000C)
-#define rBANKCON3 (*(volatile unsigned *)0x14000010)
-#define rBANKCON4 (*(volatile unsigned *)0x14000014)
-#define rBANKCON5 (*(volatile unsigned *)0x14000018)
-#define rBANKCON6 (*(volatile unsigned *)0x1400001C)
-#define rBANKCON7 (*(volatile unsigned *)0x14000020)
-#define rREFRESH (*(volatile unsigned *)0x14000024)
-#define rBANKSIZE (*(volatile unsigned *)0x14000028)
-#define rMRSRB6 (*(volatile unsigned *)0x1400002C)
-#define rMRSRB7 (*(volatile unsigned *)0x14000030)
-
-
-/* INTERRUPT */
-#define rSRCPND (*(volatile unsigned *)0x14400000)
-#define rINTMOD (*(volatile unsigned *)0x14400004)
-#define rINTMSK (*(volatile unsigned *)0x14400008)
-#define rPRIORITY (*(volatile unsigned *)0x1440000C)
-#define rINTPND (*(volatile unsigned *)0x14400010)
-#define rINTOFFSET (*(volatile unsigned *)0x14400014)
-
-
-/* DMA */
-#define rDISRC0 (*(volatile unsigned *)0x14600000)
-#define rDIDST0 (*(volatile unsigned *)0x14600004)
-#define rDCON0 (*(volatile unsigned *)0x14600008)
-#define rDSTAT0 (*(volatile unsigned *)0x1460000C)
-#define rDCSRC0 (*(volatile unsigned *)0x14600010)
-#define rDCDST0 (*(volatile unsigned *)0x14600014)
-#define rDMASKTRIG0 (*(volatile unsigned *)0x14600018)
-#define rDISRC1 (*(volatile unsigned *)0x14600020)
-#define rDIDST1 (*(volatile unsigned *)0x14600024)
-#define rDCON1 (*(volatile unsigned *)0x14600028)
-#define rDSTAT1 (*(volatile unsigned *)0x1460002C)
-#define rDCSRC1 (*(volatile unsigned *)0x14600030)
-#define rDCDST1 (*(volatile unsigned *)0x14600034)
-#define rDMASKTRIG1 (*(volatile unsigned *)0x14600038)
-#define rDISRC2 (*(volatile unsigned *)0x14600040)
-#define rDIDST2 (*(volatile unsigned *)0x14600044)
-#define rDCON2 (*(volatile unsigned *)0x14600048)
-#define rDSTAT2 (*(volatile unsigned *)0x1460004C)
-#define rDCSRC2 (*(volatile unsigned *)0x14600050)
-#define rDCDST2 (*(volatile unsigned *)0x14600054)
-#define rDMASKTRIG2 (*(volatile unsigned *)0x14600058)
-#define rDISRC3 (*(volatile unsigned *)0x14600060)
-#define rDIDST3 (*(volatile unsigned *)0x14600064)
-#define rDCON3 (*(volatile unsigned *)0x14600068)
-#define rDSTAT3 (*(volatile unsigned *)0x1460006C)
-#define rDCSRC3 (*(volatile unsigned *)0x14600070)
-#define rDCDST3 (*(volatile unsigned *)0x14600074)
-#define rDMASKTRIG3 (*(volatile unsigned *)0x14600078)
-
-
-/* CLOCK & POWER MANAGEMENT */
-#define rLOCKTIME (*(volatile unsigned *)0x14800000)
-#define rMPLLCON (*(volatile unsigned *)0x14800004)
-#define rUPLLCON (*(volatile unsigned *)0x14800008)
-#define rCLKCON (*(volatile unsigned *)0x1480000C)
-#define rCLKSLOW (*(volatile unsigned *)0x14800010)
-#define rCLKDIVN (*(volatile unsigned *)0x14800014)
-
-
-/* LCD CONTROLLER */
-#define rLCDCON1 (*(volatile unsigned *)0x14A00000)
-#define rLCDCON2 (*(volatile unsigned *)0x14A00004)
-#define rLCDCON3 (*(volatile unsigned *)0x14A00008)
-#define rLCDCON4 (*(volatile unsigned *)0x14A0000C)
-#define rLCDCON5 (*(volatile unsigned *)0x14A00010)
-#define rLCDSADDR1 (*(volatile unsigned *)0x14A00014)
-#define rLCDSADDR2 (*(volatile unsigned *)0x14A00018)
-#define rLCDSADDR3 (*(volatile unsigned *)0x14A0001C)
-#define rREDLUT (*(volatile unsigned *)0x14A00020)
-#define rGREENLUT (*(volatile unsigned *)0x14A00024)
-#define rBLUELUT (*(volatile unsigned *)0x14A00028)
-#define rDP1_2 (*(volatile unsigned *)0x14A0002C)
-#define rDP4_7 (*(volatile unsigned *)0x14A00030)
-#define rDP3_5 (*(volatile unsigned *)0x14A00034)
-#define rDP2_3 (*(volatile unsigned *)0x14A00038)
-#define rDP5_7 (*(volatile unsigned *)0x14A0003c)
-#define rDP3_4 (*(volatile unsigned *)0x14A00040)
-#define rDP4_5 (*(volatile unsigned *)0x14A00044)
-#define rDP6_7 (*(volatile unsigned *)0x14A00048)
-#define rDITHMODE (*(volatile unsigned *)0x14A0004C)
-#define rTPAL (*(volatile unsigned *)0x14A00050)
-#define PALETTE (0x14A00400) /* SJS */
-
-
-/* UART */
-#define rULCON0 (*(volatile unsigned char *)0x15000000)
-#define rUCON0 (*(volatile unsigned short *)0x15000004)
-#define rUFCON0 (*(volatile unsigned char *)0x15000008)
-#define rUMCON0 (*(volatile unsigned char *)0x1500000C)
-#define rUTRSTAT0 (*(volatile unsigned char *)0x15000010)
-#define rUERSTAT0 (*(volatile unsigned char *)0x15000014)
-#define rUFSTAT0 (*(volatile unsigned short *)0x15000018)
-#define rUMSTAT0 (*(volatile unsigned char *)0x1500001C)
-#define rUBRDIV0 (*(volatile unsigned short *)0x15000028)
-
-#define rULCON1 (*(volatile unsigned char *)0x15004000)
-#define rUCON1 (*(volatile unsigned short *)0x15004004)
-#define rUFCON1 (*(volatile unsigned char *)0x15004008)
-#define rUMCON1 (*(volatile unsigned char *)0x1500400C)
-#define rUTRSTAT1 (*(volatile unsigned char *)0x15004010)
-#define rUERSTAT1 (*(volatile unsigned char *)0x15004014)
-#define rUFSTAT1 (*(volatile unsigned short *)0x15004018)
-#define rUMSTAT1 (*(volatile unsigned char *)0x1500401C)
-#define rUBRDIV1 (*(volatile unsigned short *)0x15004028)
-
-#ifdef __BIG_ENDIAN
-#define rUTXH0 (*(volatile unsigned char *)0x15000023)
-#define rURXH0 (*(volatile unsigned char *)0x15000027)
-#define rUTXH1 (*(volatile unsigned char *)0x15004023)
-#define rURXH1 (*(volatile unsigned char *)0x15004027)
-
-#define WrUTXH0(ch) (*(volatile unsigned char *)0x15000023)=(unsigned char)(ch)
-#define RdURXH0() (*(volatile unsigned char *)0x15000027)
-#define WrUTXH1(ch) (*(volatile unsigned char *)0x15004023)=(unsigned char)(ch)
-#define RdURXH1() (*(volatile unsigned char *)0x15004027)
-
-#define UTXH0 (0x15000020+3) /* byte_access address by DMA */
-#define URXH0 (0x15000024+3)
-#define UTXH1 (0x15004020+3)
-#define URXH1 (0x15004024+3)
-
-#else /* Little Endian */
-#define rUTXH0 (*(volatile unsigned char *)0x15000020)
-#define rURXH0 (*(volatile unsigned char *)0x15000024)
-#define rUTXH1 (*(volatile unsigned char *)0x15004020)
-#define rURXH1 (*(volatile unsigned char *)0x15004024)
-
-#define WrUTXH0(ch) (*(volatile unsigned char *)0x15000020)=(unsigned char)(ch)
-#define RdURXH0() (*(volatile unsigned char *)0x15000024)
-#define WrUTXH1(ch) (*(volatile unsigned char *)0x15004020)=(unsigned char)(ch)
-#define RdURXH1() (*(volatile unsigned char *)0x15004024)
-
-#define UTXH0 (0x15000020) /* byte_access address by DMA */
-#define URXH0 (0x15000024)
-#define UTXH1 (0x15004020)
-#define URXH1 (0x15004024)
-#endif
-
-
-/* PWM TIMER */
-#define rTCFG0 (*(volatile unsigned *)0x15100000)
-#define rTCFG1 (*(volatile unsigned *)0x15100004)
-#define rTCON (*(volatile unsigned *)0x15100008)
-#define rTCNTB0 (*(volatile unsigned *)0x1510000C)
-#define rTCMPB0 (*(volatile unsigned *)0x15100010)
-#define rTCNTO0 (*(volatile unsigned *)0x15100014)
-#define rTCNTB1 (*(volatile unsigned *)0x15100018)
-#define rTCMPB1 (*(volatile unsigned *)0x1510001C)
-#define rTCNTO1 (*(volatile unsigned *)0x15100020)
-#define rTCNTB2 (*(volatile unsigned *)0x15100024)
-#define rTCMPB2 (*(volatile unsigned *)0x15100028)
-#define rTCNTO2 (*(volatile unsigned *)0x1510002C)
-#define rTCNTB3 (*(volatile unsigned *)0x15100030)
-#define rTCMPB3 (*(volatile unsigned *)0x15100034)
-#define rTCNTO3 (*(volatile unsigned *)0x15100038)
-#define rTCNTB4 (*(volatile unsigned *)0x1510003C)
-#define rTCNTO4 (*(volatile unsigned *)0x15100040)
-
-
-/* USB DEVICE */
-#define rFUNC_ADDR_REG (*(volatile unsigned *)0x15200140)
-#define rPWR_REG (*(volatile unsigned *)0x15200144)
-#define rINT_REG (*(volatile unsigned *)0x15200148)
-#define rINT_MASK_REG (*(volatile unsigned *)0x1520014C)
-#define rFRAME_NUM_REG (*(volatile unsigned *)0x15200150)
-#define rRESUME_CON_REG (*(volatile unsigned *)0x15200154)
-#define rEP0_CSR (*(volatile unsigned *)0x15200160)
-#define rEP0_MAXP (*(volatile unsigned *)0x15200164)
-#define rEP0_OUT_CNT (*(volatile unsigned *)0x15200168)
-#define rEP0_FIFO (*(volatile unsigned *)0x1520016C)
-#define rEP1_IN_CSR (*(volatile unsigned *)0x15200180)
-#define rEP1_IN_MAXP (*(volatile unsigned *)0x15200184)
-#define rEP1_FIFO (*(volatile unsigned *)0x15200188)
-#define rEP2_IN_CSR (*(volatile unsigned *)0x15200190)
-#define rEP2_IN_MAXP (*(volatile unsigned *)0x15200194)
-#define rEP2_FIFO (*(volatile unsigned *)0x15200198)
-#define rEP3_OUT_CSR (*(volatile unsigned *)0x152001A0)
-#define rEP3_OUT_MAXP (*(volatile unsigned *)0x152001A4)
-#define rEP3_OUT_CNT (*(volatile unsigned *)0x152001A8)
-#define rEP3_FIFO (*(volatile unsigned *)0x152001AC)
-#define rEP4_OUT_CSR (*(volatile unsigned *)0x152001B0)
-#define rEP4_OUT_MAXP (*(volatile unsigned *)0x152001B4)
-#define rEP4_OUT_CNT (*(volatile unsigned *)0x152001B8)
-#define rEP4_FIFO (*(volatile unsigned *)0x152001BC)
-#define rDMA_CON (*(volatile unsigned *)0x152001C0)
-#define rDMA_UNIT (*(volatile unsigned *)0x152001C4)
-#define rDMA_FIFO (*(volatile unsigned *)0x152001C8)
-#define rDMA_TX (*(volatile unsigned *)0x152001CC)
-#define rTEST_MODE (*(volatile unsigned *)0x152001F4)
-#define rIN_CON_REG (*(volatile unsigned *)0x152001F8)
-
-
-/* WATCH DOG TIMER */
-#define rWTCON (*(volatile unsigned *)0x15300000)
-#define rWTDAT (*(volatile unsigned *)0x15300004)
-#define rWTCNT (*(volatile unsigned *)0x15300008)
-
-
-/* IIC */
-#define rIICCON (*(volatile unsigned *)0x15400000)
-#define rIICSTAT (*(volatile unsigned *)0x15400004)
-#define rIICADD (*(volatile unsigned *)0x15400008)
-#define rIICDS (*(volatile unsigned *)0x1540000C)
-
-
-/* IIS */
-#define rIISCON (*(volatile unsigned *)0x15508000)
-#define rIISMOD (*(volatile unsigned *)0x15508004)
-#define rIISPSR (*(volatile unsigned *)0x15508008)
-#define rIISFIFCON (*(volatile unsigned *)0x1550800C)
-
-#ifdef __BIG_ENDIAN
-#define IISFIF ((volatile unsigned short *)0x15508012)
-
-#else /* Little Endian */
-#define IISFIF ((volatile unsigned short *)0x15508010)
-#endif
-
-
-/* I/O PORT */
-#define rPACON (*(volatile unsigned *)0x15600000)
-#define rPADAT (*(volatile unsigned *)0x15600004)
-
-#define rPBCON (*(volatile unsigned *)0x15600008)
-#define rPBDAT (*(volatile unsigned *)0x1560000C)
-#define rPBUP (*(volatile unsigned *)0x15600010)
-
-#define rPCCON (*(volatile unsigned *)0x15600014)
-#define rPCDAT (*(volatile unsigned *)0x15600018)
-#define rPCUP (*(volatile unsigned *)0x1560001C)
-
-#define rPDCON (*(volatile unsigned *)0x15600020)
-#define rPDDAT (*(volatile unsigned *)0x15600024)
-#define rPDUP (*(volatile unsigned *)0x15600028)
-
-#define rPECON (*(volatile unsigned *)0x1560002C)
-#define rPEDAT (*(volatile unsigned *)0x15600030)
-#define rPEUP (*(volatile unsigned *)0x15600034)
-
-#define rPFCON (*(volatile unsigned *)0x15600038)
-#define rPFDAT (*(volatile unsigned *)0x1560003C)
-#define rPFUP (*(volatile unsigned *)0x15600040)
-
-#define rPGCON (*(volatile unsigned *)0x15600044)
-#define rPGDAT (*(volatile unsigned *)0x15600048)
-#define rPGUP (*(volatile unsigned *)0x1560004C)
-
-#define rOPENCR (*(volatile unsigned *)0x15600050)
-#define rMISCCR (*(volatile unsigned *)0x15600054)
-#define rEXTINT (*(volatile unsigned *)0x15600058)
-
-
-/* RTC */
-#ifdef __BIG_ENDIAN
-#define rRTCCON (*(volatile unsigned char *)0x15700043)
-#define rRTCALM (*(volatile unsigned char *)0x15700053)
-#define rALMSEC (*(volatile unsigned char *)0x15700057)
-#define rALMMIN (*(volatile unsigned char *)0x1570005B)
-#define rALMHOUR (*(volatile unsigned char *)0x1570005F)
-#define rALMDAY (*(volatile unsigned char *)0x15700063)
-#define rALMMON (*(volatile unsigned char *)0x15700067)
-#define rALMYEAR (*(volatile unsigned char *)0x1570006B)
-#define rRTCRST (*(volatile unsigned char *)0x1570006F)
-#define rBCDSEC (*(volatile unsigned char *)0x15700073)
-#define rBCDMIN (*(volatile unsigned char *)0x15700077)
-#define rBCDHOUR (*(volatile unsigned char *)0x1570007B)
-#define rBCDDAY (*(volatile unsigned char *)0x1570007F)
-#define rBCDDATE (*(volatile unsigned char *)0x15700083)
-#define rBCDMON (*(volatile unsigned char *)0x15700087)
-#define rBCDYEAR (*(volatile unsigned char *)0x1570008B)
-#define rTICINT (*(volatile unsigned char *)0x15700047)
-
-#else /* Little Endian */
-#define rRTCCON (*(volatile unsigned char *)0x15700040)
-#define rRTCALM (*(volatile unsigned char *)0x15700050)
-#define rALMSEC (*(volatile unsigned char *)0x15700054)
-#define rALMMIN (*(volatile unsigned char *)0x15700058)
-#define rALMHOUR (*(volatile unsigned char *)0x1570005C)
-#define rALMDAY (*(volatile unsigned char *)0x15700060)
-#define rALMMON (*(volatile unsigned char *)0x15700064)
-#define rALMYEAR (*(volatile unsigned char *)0x15700068)
-#define rRTCRST (*(volatile unsigned char *)0x1570006C)
-#define rBCDSEC (*(volatile unsigned char *)0x15700070)
-#define rBCDMIN (*(volatile unsigned char *)0x15700074)
-#define rBCDHOUR (*(volatile unsigned char *)0x15700078)
-#define rBCDDAY (*(volatile unsigned char *)0x1570007C)
-#define rBCDDATE (*(volatile unsigned char *)0x15700080)
-#define rBCDMON (*(volatile unsigned char *)0x15700084)
-#define rBCDYEAR (*(volatile unsigned char *)0x15700088)
-#define rTICINT (*(volatile unsigned char *)0x15700044)
-#endif
-
-
-/* ADC */
-#define rADCCON (*(volatile unsigned *)0x15800000)
-#define rADCDAT (*(volatile unsigned *)0x15800004)
-
-
-/* SPI */
-#define rSPCON (*(volatile unsigned *)0x15900000)
-#define rSPSTA (*(volatile unsigned *)0x15900004)
-#define rSPPIN (*(volatile unsigned *)0x15900008)
-#define rSPPRE (*(volatile unsigned *)0x1590000C)
-#define rSPTDAT (*(volatile unsigned *)0x15900010)
-#define rSPRDAT (*(volatile unsigned *)0x15900014)
-
-
-/* MMC INTERFACE */
-#define rMMCON (*(volatile unsigned *)0x15a00000)
-#define rMMCRR (*(volatile unsigned *)0x15a00004)
-#define rMMFCON (*(volatile unsigned *)0x15a00008)
-#define rMMSTA (*(volatile unsigned *)0x15a0000C)
-#define rMMFSTA (*(volatile unsigned *)0x15a00010)
-#define rMMPRE (*(volatile unsigned *)0x15a00014)
-#define rMMLEN (*(volatile unsigned *)0x15a00018)
-#define rMMCR7 (*(volatile unsigned *)0x15a0001C)
-#define rMMRSP0 (*(volatile unsigned *)0x15a00020)
-#define rMMRSP1 (*(volatile unsigned *)0x15a00024)
-#define rMMRSP2 (*(volatile unsigned *)0x15a00028)
-#define rMMRSP3 (*(volatile unsigned *)0x15a0002C)
-#define rMMCMD0 (*(volatile unsigned *)0x15a00030)
-#define rMMCMD1 (*(volatile unsigned *)0x15a00034)
-#define rMMCR16 (*(volatile unsigned *)0x15a00038)
-#define rMMDAT (*(volatile unsigned *)0x15a0003C)
-
-
-/* ISR */
-#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0))
-#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4))
-#define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8))
-#define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xC))
-#define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10))
-#define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14))
-#define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18))
-#define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1C))
-
-#define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20))
-#define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24))
-#define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28))
-#define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2C))
-#define pISR_EINT4 (*(unsigned *)(_ISR_STARTADDRESS+0x30))
-#define pISR_EINT5 (*(unsigned *)(_ISR_STARTADDRESS+0x34))
-#define pISR_EINT6 (*(unsigned *)(_ISR_STARTADDRESS+0x38))
-#define pISR_EINT7 (*(unsigned *)(_ISR_STARTADDRESS+0x3C))
-#define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40))
-#define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44))
-#define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48))
-#define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4C))
-#define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50))
-#define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54))
-#define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58))
-#define pISR_UERR01 (*(unsigned *)(_ISR_STARTADDRESS+0x5C))
-#define pISR_NOTUSED (*(unsigned *)(_ISR_STARTADDRESS+0x60))
-#define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64))
-#define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68))
-#define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6C))
-#define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70))
-#define pISR_MMC (*(unsigned *)(_ISR_STARTADDRESS+0x74))
-#define pISR_SPI (*(unsigned *)(_ISR_STARTADDRESS+0x78))
-#define pISR_URXD0 (*(unsigned *)(_ISR_STARTADDRESS+0x7C))
-#define pISR_URXD1 (*(unsigned *)(_ISR_STARTADDRESS+0x80))
-#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84))
-#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88))
-#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8C))
-#define pISR_UTXD0 (*(unsigned *)(_ISR_STARTADDRESS+0x90))
-#define pISR_UTXD1 (*(unsigned *)(_ISR_STARTADDRESS+0x94))
-#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98))
-#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0xA0))
-
-
-/* PENDING BIT */
-#define BIT_EINT0 (0x1)
-#define BIT_EINT1 (0x1<<1)
-#define BIT_EINT2 (0x1<<2)
-#define BIT_EINT3 (0x1<<3)
-#define BIT_EINT4 (0x1<<4)
-#define BIT_EINT5 (0x1<<5)
-#define BIT_EINT6 (0x1<<6)
-#define BIT_EINT7 (0x1<<7)
-#define BIT_TICK (0x1<<8)
-#define BIT_WDT (0x1<<9)
-#define BIT_TIMER0 (0x1<<10)
-#define BIT_TIMER1 (0x1<<11)
-#define BIT_TIMER2 (0x1<<12)
-#define BIT_TIMER3 (0x1<<13)
-#define BIT_TIMER4 (0x1<<14)
-#define BIT_UERR01 (0x1<<15)
-#define BIT_NOTUSED (0x1<<16)
-#define BIT_DMA0 (0x1<<17)
-#define BIT_DMA1 (0x1<<18)
-#define BIT_DMA2 (0x1<<19)
-#define BIT_DMA3 (0x1<<20)
-#define BIT_MMC (0x1<<21)
-#define BIT_SPI (0x1<<22)
-#define BIT_URXD0 (0x1<<23)
-#define BIT_URXD1 (0x1<<24)
-#define BIT_USBD (0x1<<25)
-#define BIT_USBH (0x1<<26)
-#define BIT_IIC (0x1<<27)
-#define BIT_UTXD0 (0x1<<28)
-#define BIT_UTXD1 (0x1<<29)
-#define BIT_RTC (0x1<<30)
-#define BIT_ADC (0x1<<31)
-#define BIT_ALLMSK (0xFFFFFFFF)
-
-#define ClearPending(bit) {\
- rSRCPND = bit;\
- rINTPND = bit;\
- rINTPND;\
- }
-/* Wait until rINTPND is changed for the case that the ISR is very short. */
-#endif
#endif /*__S3C2400_H__*/
#define S3C2410_ECCSIZE 512
#define S3C2410_ECCBYTES 3
-typedef enum {
+enum s3c24x0_uarts_nr {
S3C24X0_UART0,
S3C24X0_UART1,
S3C24X0_UART2
-} S3C24X0_UARTS_NR;
+};
/* S3C2410 device base addresses */
#define S3C24X0_MEMCTL_BASE 0x48000000
#include <s3c24x0.h>
-static inline S3C24X0_MEMCTL * S3C24X0_GetBase_MEMCTL(void)
+static inline struct s3c24x0_memctl *s3c24x0_get_base_memctl(void)
{
- return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE;
+ return (struct s3c24x0_memctl *)S3C24X0_MEMCTL_BASE;
}
-static inline S3C24X0_USB_HOST * S3C24X0_GetBase_USB_HOST(void)
+static inline struct s3c24x0_usb_host *s3c24x0_get_base_usb_host(void)
{
- return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE;
+ return (struct s3c24x0_usb_host *)S3C24X0_USB_HOST_BASE;
}
-static inline S3C24X0_INTERRUPT * S3C24X0_GetBase_INTERRUPT(void)
+static inline struct s3c24x0_interrupt *s3c24x0_get_base_interrupt(void)
{
- return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE;
+ return (struct s3c24x0_interrupt *)S3C24X0_INTERRUPT_BASE;
}
-static inline S3C24X0_DMAS * S3C24X0_GetBase_DMAS(void)
+static inline struct s3c24x0_dmas *s3c24x0_get_base_dmas(void)
{
- return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE;
+ return (struct s3c24x0_dmas *)S3C24X0_DMA_BASE;
}
-static inline S3C24X0_CLOCK_POWER * S3C24X0_GetBase_CLOCK_POWER(void)
+static inline struct s3c24x0_clock_power *s3c24x0_get_base_clock_power(void)
{
- return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE;
+ return (struct s3c24x0_clock_power *)S3C24X0_CLOCK_POWER_BASE;
}
-static inline S3C24X0_LCD * S3C24X0_GetBase_LCD(void)
+static inline struct s3c24x0_lcd *s3c24x0_get_base_lcd(void)
{
- return (S3C24X0_LCD * const)S3C24X0_LCD_BASE;
+ return (struct s3c24x0_lcd *)S3C24X0_LCD_BASE;
}
-static inline S3C2410_NAND * S3C2410_GetBase_NAND(void)
+static inline struct s3c2410_nand *s3c2410_get_base_nand(void)
{
- return (S3C2410_NAND * const)S3C2410_NAND_BASE;
+ return (struct s3c2410_nand *)S3C2410_NAND_BASE;
}
-static inline S3C24X0_UART * S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
+static inline struct s3c24x0_uart
+ *s3c24x0_get_base_uart(enum s3c24x0_uarts_nr n)
{
- return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000));
+ return (struct s3c24x0_uart *)(S3C24X0_UART_BASE + (n * 0x4000));
}
-static inline S3C24X0_TIMERS * S3C24X0_GetBase_TIMERS(void)
+static inline struct s3c24x0_timers *s3c24x0_get_base_timers(void)
{
- return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE;
+ return (struct s3c24x0_timers *)S3C24X0_TIMER_BASE;
}
-static inline S3C24X0_USB_DEVICE * S3C24X0_GetBase_USB_DEVICE(void)
+static inline struct s3c24x0_usb_device *s3c24x0_get_base_usb_device(void)
{
- return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE;
+ return (struct s3c24x0_usb_device *)S3C24X0_USB_DEVICE_BASE;
}
-static inline S3C24X0_WATCHDOG * S3C24X0_GetBase_WATCHDOG(void)
+static inline struct s3c24x0_watchdog *s3c24x0_get_base_watchdog(void)
{
- return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE;
+ return (struct s3c24x0_watchdog *)S3C24X0_WATCHDOG_BASE;
}
-static inline S3C24X0_I2C * S3C24X0_GetBase_I2C(void)
+static inline struct s3c24x0_i2c *s3c24x0_get_base_i2c(void)
{
- return (S3C24X0_I2C * const)S3C24X0_I2C_BASE;
+ return (struct s3c24x0_i2c *)S3C24X0_I2C_BASE;
}
-static inline S3C24X0_I2S * S3C24X0_GetBase_I2S(void)
+static inline struct s3c24x0_i2s *s3c24x0_get_base_i2s(void)
{
- return (S3C24X0_I2S * const)S3C24X0_I2S_BASE;
+ return (struct s3c24x0_i2s *)S3C24X0_I2S_BASE;
}
-static inline S3C24X0_GPIO * S3C24X0_GetBase_GPIO(void)
+static inline struct s3c24x0_gpio *s3c24x0_get_base_gpio(void)
{
- return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE;
+ return (struct s3c24x0_gpio *)S3C24X0_GPIO_BASE;
}
-static inline S3C24X0_RTC * S3C24X0_GetBase_RTC(void)
+static inline struct s3c24x0_rtc *s3c24x0_get_base_rtc(void)
{
- return (S3C24X0_RTC * const)S3C24X0_RTC_BASE;
+ return (struct s3c24x0_rtc *)S3C24X0_RTC_BASE;
}
-static inline S3C2410_ADC * S3C2410_GetBase_ADC(void)
+static inline struct s3c2410_adc *s3c2410_get_base_adc(void)
{
- return (S3C2410_ADC * const)S3C2410_ADC_BASE;
+ return (struct s3c2410_adc *)S3C2410_ADC_BASE;
}
-static inline S3C24X0_SPI * S3C24X0_GetBase_SPI(void)
+static inline struct s3c24x0_spi *s3c24x0_get_base_spi(void)
{
- return (S3C24X0_SPI * const)S3C24X0_SPI_BASE;
+ return (struct s3c24x0_spi *)S3C24X0_SPI_BASE;
}
-static inline S3C2410_SDI * S3C2410_GetBase_SDI(void)
+static inline struct s3c2410_sdi *s3c2410_get_base_sdi(void)
{
- return (S3C2410_SDI * const)S3C2410_SDI_BASE;
+ return (struct s3c2410_sdi *)S3C2410_SDI_BASE;
}
-
-/* ISR */
-#define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0))
-#define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4))
-#define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8))
-#define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xC))
-#define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10))
-#define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14))
-#define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18))
-#define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1C))
-
-#define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20))
-#define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24))
-#define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28))
-#define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2C))
-#define pISR_EINT4_7 (*(unsigned *)(_ISR_STARTADDRESS+0x30))
-#define pISR_EINT8_23 (*(unsigned *)(_ISR_STARTADDRESS+0x34))
-#define pISR_BAT_FLT (*(unsigned *)(_ISR_STARTADDRESS+0x3C))
-#define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40))
-#define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44))
-#define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48))
-#define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4C))
-#define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50))
-#define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54))
-#define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58))
-#define pISR_UART2 (*(unsigned *)(_ISR_STARTADDRESS+0x5C))
-#define pISR_NOTUSED (*(unsigned *)(_ISR_STARTADDRESS+0x60))
-#define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64))
-#define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68))
-#define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6C))
-#define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70))
-#define pISR_SDI (*(unsigned *)(_ISR_STARTADDRESS+0x74))
-#define pISR_SPI0 (*(unsigned *)(_ISR_STARTADDRESS+0x78))
-#define pISR_UART1 (*(unsigned *)(_ISR_STARTADDRESS+0x7C))
-#define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84))
-#define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88))
-#define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8C))
-#define pISR_UART0 (*(unsigned *)(_ISR_STARTADDRESS+0x90))
-#define pISR_SPI1 (*(unsigned *)(_ISR_STARTADDRESS+0x94))
-#define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98))
-#define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0xA0))
-
-
-/* PENDING BIT */
-#define BIT_EINT0 (0x1)
-#define BIT_EINT1 (0x1<<1)
-#define BIT_EINT2 (0x1<<2)
-#define BIT_EINT3 (0x1<<3)
-#define BIT_EINT4_7 (0x1<<4)
-#define BIT_EINT8_23 (0x1<<5)
-#define BIT_BAT_FLT (0x1<<7)
-#define BIT_TICK (0x1<<8)
-#define BIT_WDT (0x1<<9)
-#define BIT_TIMER0 (0x1<<10)
-#define BIT_TIMER1 (0x1<<11)
-#define BIT_TIMER2 (0x1<<12)
-#define BIT_TIMER3 (0x1<<13)
-#define BIT_TIMER4 (0x1<<14)
-#define BIT_UART2 (0x1<<15)
-#define BIT_LCD (0x1<<16)
-#define BIT_DMA0 (0x1<<17)
-#define BIT_DMA1 (0x1<<18)
-#define BIT_DMA2 (0x1<<19)
-#define BIT_DMA3 (0x1<<20)
-#define BIT_SDI (0x1<<21)
-#define BIT_SPI0 (0x1<<22)
-#define BIT_UART1 (0x1<<23)
-#define BIT_USBD (0x1<<25)
-#define BIT_USBH (0x1<<26)
-#define BIT_IIC (0x1<<27)
-#define BIT_UART0 (0x1<<28)
-#define BIT_SPI1 (0x1<<29)
-#define BIT_RTC (0x1<<30)
-#define BIT_ADC (0x1<<31)
-#define BIT_ALLMSK (0xFFFFFFFF)
-
-#define ClearPending(bit) {\
- rSRCPND = bit;\
- rINTPND = bit;\
- rINTPND;\
- }
-/* Wait until rINTPND is changed for the case that the ISR is very short. */
#endif /*__S3C2410_H__*/
typedef volatile u32 S3C24X0_REG32;
/* Memory controller (see manual chapter 5) */
-typedef struct {
+struct s3c24x0_memctl {
S3C24X0_REG32 BWSCON;
S3C24X0_REG32 BANKCON[8];
S3C24X0_REG32 REFRESH;
S3C24X0_REG32 BANKSIZE;
S3C24X0_REG32 MRSRB6;
S3C24X0_REG32 MRSRB7;
-} /*__attribute__((__packed__))*/ S3C24X0_MEMCTL;
+};
/* USB HOST (see manual chapter 12) */
-typedef struct {
+struct s3c24x0_usb_host {
S3C24X0_REG32 HcRevision;
S3C24X0_REG32 HcControl;
S3C24X0_REG32 HcCommonStatus;
S3C24X0_REG32 HcRhStatus;
S3C24X0_REG32 HcRhPortStatus1;
S3C24X0_REG32 HcRhPortStatus2;
-} /*__attribute__((__packed__))*/ S3C24X0_USB_HOST;
+};
/* INTERRUPT (see manual chapter 14) */
-typedef struct {
+struct s3c24x0_interrupt {
S3C24X0_REG32 SRCPND;
S3C24X0_REG32 INTMOD;
S3C24X0_REG32 INTMSK;
S3C24X0_REG32 SUBSRCPND;
S3C24X0_REG32 INTSUBMSK;
#endif
-} /*__attribute__((__packed__))*/ S3C24X0_INTERRUPT;
+};
/* DMAS (see manual chapter 8) */
-typedef struct {
+struct s3c24x0_dma {
S3C24X0_REG32 DISRC;
#ifdef CONFIG_S3C2410
S3C24X0_REG32 DISRCC;
#ifdef CONFIG_S3C2410
S3C24X0_REG32 res[7];
#endif
-} /*__attribute__((__packed__))*/ S3C24X0_DMA;
+};
-typedef struct {
- S3C24X0_DMA dma[4];
-} /*__attribute__((__packed__))*/ S3C24X0_DMAS;
+struct s3c24x0_dmas {
+ struct s3c24x0_dma dma[4];
+};
/* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
/* (see S3C2410 manual chapter 7) */
-typedef struct {
+struct s3c24x0_clock_power {
S3C24X0_REG32 LOCKTIME;
S3C24X0_REG32 MPLLCON;
S3C24X0_REG32 UPLLCON;
S3C24X0_REG32 CLKCON;
S3C24X0_REG32 CLKSLOW;
S3C24X0_REG32 CLKDIVN;
-} /*__attribute__((__packed__))*/ S3C24X0_CLOCK_POWER;
+};
/* LCD CONTROLLER (see manual chapter 15) */
-typedef struct {
+struct s3c24x0_lcd {
S3C24X0_REG32 LCDCON1;
S3C24X0_REG32 LCDCON2;
S3C24X0_REG32 LCDCON3;
S3C24X0_REG32 LCDINTMSK;
S3C24X0_REG32 LPCSEL;
#endif
-} /*__attribute__((__packed__))*/ S3C24X0_LCD;
+};
/* NAND FLASH (see S3C2410 manual chapter 6) */
-typedef struct {
+struct s3c2410_nand {
S3C24X0_REG32 NFCONF;
S3C24X0_REG32 NFCMD;
S3C24X0_REG32 NFADDR;
S3C24X0_REG32 NFDATA;
S3C24X0_REG32 NFSTAT;
S3C24X0_REG32 NFECC;
-} /*__attribute__((__packed__))*/ S3C2410_NAND;
+};
/* UART (see manual chapter 11) */
-typedef struct {
+struct s3c24x0_uart {
S3C24X0_REG32 ULCON;
S3C24X0_REG32 UCON;
S3C24X0_REG32 UFCON;
S3C24X0_REG8 res2[3];
#endif
S3C24X0_REG32 UBRDIV;
-} /*__attribute__((__packed__))*/ S3C24X0_UART;
+};
/* PWM TIMER (see manual chapter 10) */
-typedef struct {
+struct s3c24x0_timer {
S3C24X0_REG32 TCNTB;
S3C24X0_REG32 TCMPB;
S3C24X0_REG32 TCNTO;
-} /*__attribute__((__packed__))*/ S3C24X0_TIMER;
+};
-typedef struct {
- S3C24X0_REG32 TCFG0;
- S3C24X0_REG32 TCFG1;
- S3C24X0_REG32 TCON;
- S3C24X0_TIMER ch[4];
- S3C24X0_REG32 TCNTB4;
- S3C24X0_REG32 TCNTO4;
-} /*__attribute__((__packed__))*/ S3C24X0_TIMERS;
+struct s3c24x0_timers {
+ S3C24X0_REG32 TCFG0;
+ S3C24X0_REG32 TCFG1;
+ S3C24X0_REG32 TCON;
+ struct s3c24x0_timer ch[4];
+ S3C24X0_REG32 TCNTB4;
+ S3C24X0_REG32 TCNTO4;
+};
/* USB DEVICE (see manual chapter 13) */
-typedef struct {
+struct s3c24x0_usb_dev_fifos {
#ifdef __BIG_ENDIAN
S3C24X0_REG8 res[3];
S3C24X0_REG8 EP_FIFO_REG;
S3C24X0_REG8 EP_FIFO_REG;
S3C24X0_REG8 res[3];
#endif
-} /*__attribute__((__packed__))*/ S3C24X0_USB_DEV_FIFOS;
+};
-typedef struct {
+struct s3c24x0_usb_dev_dmas {
#ifdef __BIG_ENDIAN
S3C24X0_REG8 res1[3];
S3C24X0_REG8 EP_DMA_CON;
S3C24X0_REG8 EP_DMA_TTC_H;
S3C24X0_REG8 res6[3];
#endif
-} /*__attribute__((__packed__))*/ S3C24X0_USB_DEV_DMAS;
+};
-typedef struct {
+struct s3c24x0_usb_device {
#ifdef __BIG_ENDIAN
S3C24X0_REG8 res1[3];
S3C24X0_REG8 FUNC_ADDR_REG;
S3C24X0_REG8 OUT_FIFO_CNT2_REG;
S3C24X0_REG8 res16[3];
#endif /* __BIG_ENDIAN */
- S3C24X0_USB_DEV_FIFOS fifo[5];
- S3C24X0_USB_DEV_DMAS dma[5];
-} /*__attribute__((__packed__))*/ S3C24X0_USB_DEVICE;
+ struct s3c24x0_usb_dev_fifos fifo[5];
+ struct s3c24x0_usb_dev_dmas dma[5];
+};
/* WATCH DOG TIMER (see manual chapter 18) */
-typedef struct {
+struct s3c24x0_watchdog {
S3C24X0_REG32 WTCON;
S3C24X0_REG32 WTDAT;
S3C24X0_REG32 WTCNT;
-} /*__attribute__((__packed__))*/ S3C24X0_WATCHDOG;
+};
/* IIC (see manual chapter 20) */
-typedef struct {
+struct s3c24x0_i2c {
S3C24X0_REG32 IICCON;
S3C24X0_REG32 IICSTAT;
S3C24X0_REG32 IICADD;
S3C24X0_REG32 IICDS;
-} /*__attribute__((__packed__))*/ S3C24X0_I2C;
+};
/* IIS (see manual chapter 21) */
-typedef struct {
+struct s3c24x0_i2s {
#ifdef __BIG_ENDIAN
S3C24X0_REG16 res1;
S3C24X0_REG16 IISCON;
S3C24X0_REG16 IISFIFO;
S3C24X0_REG16 res5;
#endif
-} /*__attribute__((__packed__))*/ S3C24X0_I2S;
+};
/* I/O PORT (see manual chapter 9) */
-typedef struct {
+struct s3c24x0_gpio {
#ifdef CONFIG_S3C2400
S3C24X0_REG32 PACON;
S3C24X0_REG32 PADAT;
S3C24X0_REG32 GSTATUS3;
S3C24X0_REG32 GSTATUS4;
#endif
-} /*__attribute__((__packed__))*/ S3C24X0_GPIO;
+};
/* RTC (see manual chapter 17) */
-typedef struct {
+struct s3c24x0_rtc {
#ifdef __BIG_ENDIAN
S3C24X0_REG8 res1[67];
S3C24X0_REG8 RTCCON;
S3C24X0_REG8 BCDYEAR;
S3C24X0_REG8 res17[3];
#endif
-} /*__attribute__((__packed__))*/ S3C24X0_RTC;
+};
/* ADC (see manual chapter 16) */
-typedef struct {
+struct s3c2400_adc {
S3C24X0_REG32 ADCCON;
S3C24X0_REG32 ADCDAT;
-} /*__attribute__((__packed__))*/ S3C2400_ADC;
+};
/* ADC (see manual chapter 16) */
-typedef struct {
+struct s3c2410_adc {
S3C24X0_REG32 ADCCON;
S3C24X0_REG32 ADCTSC;
S3C24X0_REG32 ADCDLY;
S3C24X0_REG32 ADCDAT0;
S3C24X0_REG32 ADCDAT1;
-} /*__attribute__((__packed__))*/ S3C2410_ADC;
+};
/* SPI (see manual chapter 22) */
-typedef struct {
+struct s3c24x0_spi_channel {
S3C24X0_REG8 SPCON;
S3C24X0_REG8 res1[3];
S3C24X0_REG8 SPSTA;
S3C24X0_REG8 SPRDAT;
S3C24X0_REG8 res6[3];
S3C24X0_REG8 res7[16];
-} /*__attribute__((__packed__))*/ S3C24X0_SPI_CHANNEL;
+};
-typedef struct {
- S3C24X0_SPI_CHANNEL ch[S3C24X0_SPI_CHANNELS];
-} /*__attribute__((__packed__))*/ S3C24X0_SPI;
+struct s3c24x0_spi {
+ struct s3c24x0_spi_channel ch[S3C24X0_SPI_CHANNELS];
+};
/* MMC INTERFACE (see S3C2400 manual chapter 19) */
-typedef struct {
+struct s3c2400_mmc {
#ifdef __BIG_ENDIAN
S3C24X0_REG8 res1[3];
S3C24X0_REG8 MMCON;
S3C24X0_REG8 MMDAT;
S3C24X0_REG8 res11[3];
#endif
-} /*__attribute__((__packed__))*/ S3C2400_MMC;
+};
/* SD INTERFACE (see S3C2410 manual chapter 19) */
-typedef struct {
+struct s3c2410_sdi {
S3C24X0_REG32 SDICON;
S3C24X0_REG32 SDIPRE;
S3C24X0_REG32 SDICARG;
S3C24X0_REG8 res[3];
#endif
S3C24X0_REG32 SDIIMSK;
-} /*__attribute__((__packed__))*/ S3C2410_SDI;
-
-
-#if 0
-/* Memory control */
-#define rBWSCON (*(volatile unsigned *)0x48000000)
-#define rBANKCON0 (*(volatile unsigned *)0x48000004)
-#define rBANKCON1 (*(volatile unsigned *)0x48000008)
-#define rBANKCON2 (*(volatile unsigned *)0x4800000C)
-#define rBANKCON3 (*(volatile unsigned *)0x48000010)
-#define rBANKCON4 (*(volatile unsigned *)0x48000014)
-#define rBANKCON5 (*(volatile unsigned *)0x48000018)
-#define rBANKCON6 (*(volatile unsigned *)0x4800001C)
-#define rBANKCON7 (*(volatile unsigned *)0x48000020)
-#define rREFRESH (*(volatile unsigned *)0x48000024)
-#define rBANKSIZE (*(volatile unsigned *)0x48000028)
-#define rMRSRB6 (*(volatile unsigned *)0x4800002C)
-#define rMRSRB7 (*(volatile unsigned *)0x48000030)
-
-
-/* USB HOST */
-#define rHcRevision (*(volatile unsigned *)0x49000000)
-#define rHcControl (*(volatile unsigned *)0x49000004)
-#define rHcCommonStatus (*(volatile unsigned *)0x49000008)
-#define rHcInterruptStatus (*(volatile unsigned *)0x4900000C)
-#define rHcInterruptEnable (*(volatile unsigned *)0x49000010)
-#define rHcInterruptDisable (*(volatile unsigned *)0x49000014)
-#define rHcHCCA (*(volatile unsigned *)0x49000018)
-#define rHcPeriodCuttendED (*(volatile unsigned *)0x4900001C)
-#define rHcControlHeadED (*(volatile unsigned *)0x49000020)
-#define rHcControlCurrentED (*(volatile unsigned *)0x49000024)
-#define rHcBulkHeadED (*(volatile unsigned *)0x49000028)
-#define rHcBuldCurrentED (*(volatile unsigned *)0x4900002C)
-#define rHcDoneHead (*(volatile unsigned *)0x49000030)
-#define rHcRmInterval (*(volatile unsigned *)0x49000034)
-#define rHcFmRemaining (*(volatile unsigned *)0x49000038)
-#define rHcFmNumber (*(volatile unsigned *)0x4900003C)
-#define rHcPeriodicStart (*(volatile unsigned *)0x49000040)
-#define rHcLSThreshold (*(volatile unsigned *)0x49000044)
-#define rHcRhDescriptorA (*(volatile unsigned *)0x49000048)
-#define rHcRhDescriptorB (*(volatile unsigned *)0x4900004C)
-#define rHcRhStatus (*(volatile unsigned *)0x49000050)
-#define rHcRhPortStatus1 (*(volatile unsigned *)0x49000054)
-#define rHcRhPortStatus2 (*(volatile unsigned *)0x49000058)
-
-
-/* INTERRUPT */
-#define rSRCPND (*(volatile unsigned *)0x4A000000)
-#define rINTMOD (*(volatile unsigned *)0x4A000004)
-#define rINTMSK (*(volatile unsigned *)0x4A000008)
-#define rPRIORITY (*(volatile unsigned *)0x4A00000C)
-#define rINTPND (*(volatile unsigned *)0x4A000010)
-#define rINTOFFSET (*(volatile unsigned *)0x4A000014)
-#define rSUBSRCPND (*(volatile unsigned *)0x4A000018)
-#define rINTSUBMSK (*(volatile unsigned *)0x4A00001C)
-
-
-/* DMA */
-#define rDISRC0 (*(volatile unsigned *)0x4B000000)
-#define rDISRCC0 (*(volatile unsigned *)0x4B000004)
-#define rDIDST0 (*(volatile unsigned *)0x4B000008)
-#define rDIDSTC0 (*(volatile unsigned *)0x4B00000C)
-#define rDCON0 (*(volatile unsigned *)0x4B000010)
-#define rDSTAT0 (*(volatile unsigned *)0x4B000014)
-#define rDCSRC0 (*(volatile unsigned *)0x4B000018)
-#define rDCDST0 (*(volatile unsigned *)0x4B00001C)
-#define rDMASKTRIG0 (*(volatile unsigned *)0x4B000020)
-#define rDISRC1 (*(volatile unsigned *)0x4B000040)
-#define rDISRCC1 (*(volatile unsigned *)0x4B000044)
-#define rDIDST1 (*(volatile unsigned *)0x4B000048)
-#define rDIDSTC1 (*(volatile unsigned *)0x4B00004C)
-#define rDCON1 (*(volatile unsigned *)0x4B000050)
-#define rDSTAT1 (*(volatile unsigned *)0x4B000054)
-#define rDCSRC1 (*(volatile unsigned *)0x4B000058)
-#define rDCDST1 (*(volatile unsigned *)0x4B00005C)
-#define rDMASKTRIG1 (*(volatile unsigned *)0x4B000060)
-#define rDISRC2 (*(volatile unsigned *)0x4B000080)
-#define rDISRCC2 (*(volatile unsigned *)0x4B000084)
-#define rDIDST2 (*(volatile unsigned *)0x4B000088)
-#define rDIDSTC2 (*(volatile unsigned *)0x4B00008C)
-#define rDCON2 (*(volatile unsigned *)0x4B000090)
-#define rDSTAT2 (*(volatile unsigned *)0x4B000094)
-#define rDCSRC2 (*(volatile unsigned *)0x4B000098)
-#define rDCDST2 (*(volatile unsigned *)0x4B00009C)
-#define rDMASKTRIG2 (*(volatile unsigned *)0x4B0000A0)
-#define rDISRC3 (*(volatile unsigned *)0x4B0000C0)
-#define rDISRCC3 (*(volatile unsigned *)0x4B0000C4)
-#define rDIDST3 (*(volatile unsigned *)0x4B0000C8)
-#define rDIDSTC3 (*(volatile unsigned *)0x4B0000CC)
-#define rDCON3 (*(volatile unsigned *)0x4B0000D0)
-#define rDSTAT3 (*(volatile unsigned *)0x4B0000D4)
-#define rDCSRC3 (*(volatile unsigned *)0x4B0000D8)
-#define rDCDST3 (*(volatile unsigned *)0x4B0000DC)
-#define rDMASKTRIG3 (*(volatile unsigned *)0x4B0000E0)
-
-
-/* CLOCK & POWER MANAGEMENT */
-#define rLOCKTIME (*(volatile unsigned *)0x4C000000)
-#define rMPLLCON (*(volatile unsigned *)0x4C000004)
-#define rUPLLCON (*(volatile unsigned *)0x4C000008)
-#define rCLKCON (*(volatile unsigned *)0x4C00000C)
-#define rCLKSLOW (*(volatile unsigned *)0x4C000010)
-#define rCLKDIVN (*(volatile unsigned *)0x4C000014)
-
-
-/* LCD CONTROLLER */
-#define rLCDCON1 (*(volatile unsigned *)0x4D000000)
-#define rLCDCON2 (*(volatile unsigned *)0x4D000004)
-#define rLCDCON3 (*(volatile unsigned *)0x4D000008)
-#define rLCDCON4 (*(volatile unsigned *)0x4D00000C)
-#define rLCDCON5 (*(volatile unsigned *)0x4D000010)
-#define rLCDSADDR1 (*(volatile unsigned *)0x4D000014)
-#define rLCDSADDR2 (*(volatile unsigned *)0x4D000018)
-#define rLCDSADDR3 (*(volatile unsigned *)0x4D00001C)
-#define rREDLUT (*(volatile unsigned *)0x4D000020)
-#define rGREENLUT (*(volatile unsigned *)0x4D000024)
-#define rBLUELUT (*(volatile unsigned *)0x4D000028)
-#define rDITHMODE (*(volatile unsigned *)0x4D00004C)
-#define rTPAL (*(volatile unsigned *)0x4D000050)
-#define rLCDINTPND (*(volatile unsigned *)0x4D000054)
-#define rLCDSRCPND (*(volatile unsigned *)0x4D000058)
-#define rLCDINTMSK (*(volatile unsigned *)0x4D00005C)
-
-
-/* NAND FLASH */
-#define rNFCONF (*(volatile unsigned *)0x4E000000)
-#define rNFCMD (*(volatile unsigned *)0x4E000004)
-#define rNFADDR (*(volatile unsigned *)0x4E000008)
-#define rNFDATA (*(volatile unsigned *)0x4E00000C)
-#define rNFSTAT (*(volatile unsigned *)0x4E000010)
-#define rNFECC (*(volatile unsigned *)0x4E000014)
-
-
-/* UART */
-#define rULCON0 (*(volatile unsigned *)0x50000000)
-#define rUCON0 (*(volatile unsigned *)0x50000004)
-#define rUFCON0 (*(volatile unsigned *)0x50000008)
-#define rUMCON0 (*(volatile unsigned *)0x5000000C)
-#define rUTRSTAT0 (*(volatile unsigned *)0x50000010)
-#define rUERSTAT0 (*(volatile unsigned *)0x50000014)
-#define rUFSTAT0 (*(volatile unsigned *)0x50000018)
-#define rUMSTAT0 (*(volatile unsigned *)0x5000001C)
-#define rUBRDIV0 (*(volatile unsigned *)0x50000028)
-
-#define rULCON1 (*(volatile unsigned *)0x50004000)
-#define rUCON1 (*(volatile unsigned *)0x50004004)
-#define rUFCON1 (*(volatile unsigned *)0x50004008)
-#define rUMCON1 (*(volatile unsigned *)0x5000400C)
-#define rUTRSTAT1 (*(volatile unsigned *)0x50004010)
-#define rUERSTAT1 (*(volatile unsigned *)0x50004014)
-#define rUFSTAT1 (*(volatile unsigned *)0x50004018)
-#define rUMSTAT1 (*(volatile unsigned *)0x5000401C)
-#define rUBRDIV1 (*(volatile unsigned *)0x50004028)
-
-#define rULCON2 (*(volatile unsigned *)0x50008000)
-#define rUCON2 (*(volatile unsigned *)0x50008004)
-#define rUFCON2 (*(volatile unsigned *)0x50008008)
-#define rUTRSTAT2 (*(volatile unsigned *)0x50008010)
-#define rUERSTAT2 (*(volatile unsigned *)0x50008014)
-#define rUFSTAT2 (*(volatile unsigned *)0x50008018)
-#define rUBRDIV2 (*(volatile unsigned *)0x50008028)
-
-#ifdef __BIG_ENDIAN
-#define rUTXH0 (*(volatile unsigned char *)0x50000023)
-#define rURXH0 (*(volatile unsigned char *)0x50000027)
-#define rUTXH1 (*(volatile unsigned char *)0x50004023)
-#define rURXH1 (*(volatile unsigned char *)0x50004027)
-#define rUTXH2 (*(volatile unsigned char *)0x50008023)
-#define rURXH2 (*(volatile unsigned char *)0x50008027)
-
-#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch)
-#define RdURXH0() (*(volatile unsigned char *)0x50000027)
-#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch)
-#define RdURXH1() (*(volatile unsigned char *)0x50004027)
-#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch)
-#define RdURXH2() (*(volatile unsigned char *)0x50008027)
-
-#define UTXH0 (0x50000020+3) /* byte_access address by DMA */
-#define URXH0 (0x50000024+3)
-#define UTXH1 (0x50004020+3)
-#define URXH1 (0x50004024+3)
-#define UTXH2 (0x50008020+3)
-#define URXH2 (0x50008024+3)
-
-#else /* Little Endian */
-#define rUTXH0 (*(volatile unsigned char *)0x50000020)
-#define rURXH0 (*(volatile unsigned char *)0x50000024)
-#define rUTXH1 (*(volatile unsigned char *)0x50004020)
-#define rURXH1 (*(volatile unsigned char *)0x50004024)
-#define rUTXH2 (*(volatile unsigned char *)0x50008020)
-#define rURXH2 (*(volatile unsigned char *)0x50008024)
-
-#define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch)
-#define RdURXH0() (*(volatile unsigned char *)0x50000024)
-#define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch)
-#define RdURXH1() (*(volatile unsigned char *)0x50004024)
-#define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch)
-#define RdURXH2() (*(volatile unsigned char *)0x50008024)
-
-#define UTXH0 (0x50000020) /* byte_access address by DMA */
-#define URXH0 (0x50000024)
-#define UTXH1 (0x50004020)
-#define URXH1 (0x50004024)
-#define UTXH2 (0x50008020)
-#define URXH2 (0x50008024)
-#endif
-
-
-/* PWM TIMER */
-#define rTCFG0 (*(volatile unsigned *)0x51000000)
-#define rTCFG1 (*(volatile unsigned *)0x51000004)
-#define rTCON (*(volatile unsigned *)0x51000008)
-#define rTCNTB0 (*(volatile unsigned *)0x5100000C)
-#define rTCMPB0 (*(volatile unsigned *)0x51000010)
-#define rTCNTO0 (*(volatile unsigned *)0x51000014)
-#define rTCNTB1 (*(volatile unsigned *)0x51000018)
-#define rTCMPB1 (*(volatile unsigned *)0x5100001C)
-#define rTCNTO1 (*(volatile unsigned *)0x51000020)
-#define rTCNTB2 (*(volatile unsigned *)0x51000024)
-#define rTCMPB2 (*(volatile unsigned *)0x51000028)
-#define rTCNTO2 (*(volatile unsigned *)0x5100002C)
-#define rTCNTB3 (*(volatile unsigned *)0x51000030)
-#define rTCMPB3 (*(volatile unsigned *)0x51000034)
-#define rTCNTO3 (*(volatile unsigned *)0x51000038)
-#define rTCNTB4 (*(volatile unsigned *)0x5100003C)
-#define rTCNTO4 (*(volatile unsigned *)0x51000040)
-
-
-/* USB DEVICE */
-#ifdef __BIG_ENDIAN
-#define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000143)
-#define rPWR_REG (*(volatile unsigned char *)0x52000147)
-#define rEP_INT_REG (*(volatile unsigned char *)0x5200014B)
-#define rUSB_INT_REG (*(volatile unsigned char *)0x5200015B)
-#define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015F)
-#define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016F)
-#define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000173)
-#define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000177)
-#define rINDEX_REG (*(volatile unsigned char *)0x5200017B)
-#define rMAXP_REG (*(volatile unsigned char *)0x52000183)
-#define rEP0_CSR (*(volatile unsigned char *)0x52000187)
-#define rIN_CSR1_REG (*(volatile unsigned char *)0x52000187)
-#define rIN_CSR2_REG (*(volatile unsigned char *)0x5200018B)
-#define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000193)
-#define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000197)
-#define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x5200019B)
-#define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019F)
-#define rEP0_FIFO (*(volatile unsigned char *)0x520001C3)
-#define rEP1_FIFO (*(volatile unsigned char *)0x520001C7)
-#define rEP2_FIFO (*(volatile unsigned char *)0x520001CB)
-#define rEP3_FIFO (*(volatile unsigned char *)0x520001CF)
-#define rEP4_FIFO (*(volatile unsigned char *)0x520001D3)
-#define rEP1_DMA_CON (*(volatile unsigned char *)0x52000203)
-#define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000207)
-#define rEP1_DMA_FIFO (*(volatile unsigned char *)0x5200020B)
-#define rEP1_DMA_TX_LO (*(volatile unsigned char *)0x5200020F)
-#define rEP1_DMA_TX_MD (*(volatile unsigned char *)0x52000213)
-#define rEP1_DMA_TX_HI (*(volatile unsigned char *)0x52000217)
-#define rEP2_DMA_CON (*(volatile unsigned char *)0x5200021B)
-#define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021F)
-#define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000223)
-#define rEP2_DMA_TX_LO (*(volatile unsigned char *)0x52000227)
-#define rEP2_DMA_TX_MD (*(volatile unsigned char *)0x5200022B)
-#define rEP2_DMA_TX_HI (*(volatile unsigned char *)0x5200022F)
-#define rEP3_DMA_CON (*(volatile unsigned char *)0x52000243)
-#define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000247)
-#define rEP3_DMA_FIFO (*(volatile unsigned char *)0x5200024B)
-#define rEP3_DMA_TX_LO (*(volatile unsigned char *)0x5200024F)
-#define rEP3_DMA_TX_MD (*(volatile unsigned char *)0x52000253)
-#define rEP3_DMA_TX_HI (*(volatile unsigned char *)0x52000257)
-#define rEP4_DMA_CON (*(volatile unsigned char *)0x5200025B)
-#define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025F)
-#define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000263)
-#define rEP4_DMA_TX_LO (*(volatile unsigned char *)0x52000267)
-#define rEP4_DMA_TX_MD (*(volatile unsigned char *)0x5200026B)
-#define rEP4_DMA_TX_HI (*(volatile unsigned char *)0x5200026F)
-#else /* little endian */
-#define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000140)
-#define rPWR_REG (*(volatile unsigned char *)0x52000144)
-#define rEP_INT_REG (*(volatile unsigned char *)0x52000148)
-#define rUSB_INT_REG (*(volatile unsigned char *)0x52000158)
-#define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015C)
-#define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016C)
-#define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000170)
-#define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000174)
-#define rINDEX_REG (*(volatile unsigned char *)0x52000178)
-#define rMAXP_REG (*(volatile unsigned char *)0x52000180)
-#define rEP0_CSR (*(volatile unsigned char *)0x52000184)
-#define rIN_CSR1_REG (*(volatile unsigned char *)0x52000184)
-#define rIN_CSR2_REG (*(volatile unsigned char *)0x52000188)
-#define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000190)
-#define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000194)
-#define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198)
-#define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019C)
-#define rEP0_FIFO (*(volatile unsigned char *)0x520001C0)
-#define rEP1_FIFO (*(volatile unsigned char *)0x520001C4)
-#define rEP2_FIFO (*(volatile unsigned char *)0x520001C8)
-#define rEP3_FIFO (*(volatile unsigned char *)0x520001CC)
-#define rEP4_FIFO (*(volatile unsigned char *)0x520001D0)
-#define rEP1_DMA_CON (*(volatile unsigned char *)0x52000200)
-#define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000204)
-#define rEP1_DMA_FIFO (*(volatile unsigned char *)0x52000208)
-#define rEP1_DMA_TX_LO (*(volatile unsigned char *)0x5200020C)
-#define rEP1_DMA_TX_MD (*(volatile unsigned char *)0x52000210)
-#define rEP1_DMA_TX_HI (*(volatile unsigned char *)0x52000214)
-#define rEP2_DMA_CON (*(volatile unsigned char *)0x52000218)
-#define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021C)
-#define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000220)
-#define rEP2_DMA_TX_LO (*(volatile unsigned char *)0x52000224)
-#define rEP2_DMA_TX_MD (*(volatile unsigned char *)0x52000228)
-#define rEP2_DMA_TX_HI (*(volatile unsigned char *)0x5200022C)
-#define rEP3_DMA_CON (*(volatile unsigned char *)0x52000240)
-#define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000244)
-#define rEP3_DMA_FIFO (*(volatile unsigned char *)0x52000248)
-#define rEP3_DMA_TX_LO (*(volatile unsigned char *)0x5200024C)
-#define rEP3_DMA_TX_MD (*(volatile unsigned char *)0x52000250)
-#define rEP3_DMA_TX_HI (*(volatile unsigned char *)0x52000254)
-#define rEP4_DMA_CON (*(volatile unsigned char *)0x52000258)
-#define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025C)
-#define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000260)
-#define rEP4_DMA_TX_LO (*(volatile unsigned char *)0x52000264)
-#define rEP4_DMA_TX_MD (*(volatile unsigned char *)0x52000268)
-#define rEP4_DMA_TX_HI (*(volatile unsigned char *)0x5200026C)
-#endif /* __BIG_ENDIAN */
-
-
-/* WATCH DOG TIMER */
-#define rWTCON (*(volatile unsigned *)0x53000000)
-#define rWTDAT (*(volatile unsigned *)0x53000004)
-#define rWTCNT (*(volatile unsigned *)0x53000008)
-
-
-/* IIC */
-#define rIICCON (*(volatile unsigned *)0x54000000)
-#define rIICSTAT (*(volatile unsigned *)0x54000004)
-#define rIICADD (*(volatile unsigned *)0x54000008)
-#define rIICDS (*(volatile unsigned *)0x5400000C)
-
-
-/* IIS */
-#define rIISCON (*(volatile unsigned *)0x55000000)
-#define rIISMOD (*(volatile unsigned *)0x55000004)
-#define rIISPSR (*(volatile unsigned *)0x55000008)
-#define rIISFCON (*(volatile unsigned *)0x5500000C)
-
-#ifdef __BIG_ENDIAN
-#define IISFIF ((volatile unsigned short *)0x55000012)
-#else /* little endian */
-#define IISFIF ((volatile unsigned short *)0x55000010)
-#endif
-
-
-/* I/O PORT */
-#define rGPACON (*(volatile unsigned *)0x56000000)
-#define rGPADAT (*(volatile unsigned *)0x56000004)
-
-#define rGPBCON (*(volatile unsigned *)0x56000010)
-#define rGPBDAT (*(volatile unsigned *)0x56000014)
-#define rGPBUP (*(volatile unsigned *)0x56000018)
-
-#define rGPCCON (*(volatile unsigned *)0x56000020)
-#define rGPCDAT (*(volatile unsigned *)0x56000024)
-#define rGPCUP (*(volatile unsigned *)0x56000028)
-
-#define rGPDCON (*(volatile unsigned *)0x56000030)
-#define rGPDDAT (*(volatile unsigned *)0x56000034)
-#define rGPDUP (*(volatile unsigned *)0x56000038)
-
-#define rGPECON (*(volatile unsigned *)0x56000040)
-#define rGPEDAT (*(volatile unsigned *)0x56000044)
-#define rGPEUP (*(volatile unsigned *)0x56000048)
-
-#define rGPFCON (*(volatile unsigned *)0x56000050)
-#define rGPFDAT (*(volatile unsigned *)0x56000054)
-#define rGPFUP (*(volatile unsigned *)0x56000058)
-
-#define rGPGCON (*(volatile unsigned *)0x56000060)
-#define rGPGDAT (*(volatile unsigned *)0x56000064)
-#define rGPGUP (*(volatile unsigned *)0x56000068)
-
-#define rGPHCON (*(volatile unsigned *)0x56000070)
-#define rGPHDAT (*(volatile unsigned *)0x56000074)
-#define rGPHUP (*(volatile unsigned *)0x56000078)
-
-#define rMISCCR (*(volatile unsigned *)0x56000080)
-#define rDCLKCON (*(volatile unsigned *)0x56000084)
-#define rEXTINT0 (*(volatile unsigned *)0x56000088)
-#define rEXTINT1 (*(volatile unsigned *)0x5600008C)
-#define rEXTINT2 (*(volatile unsigned *)0x56000090)
-#define rEINTFLT0 (*(volatile unsigned *)0x56000094)
-#define rEINTFLT1 (*(volatile unsigned *)0x56000098)
-#define rEINTFLT2 (*(volatile unsigned *)0x5600009C)
-#define rEINTFLT3 (*(volatile unsigned *)0x560000A0)
-#define rEINTMASK (*(volatile unsigned *)0x560000A4)
-#define rEINTPEND (*(volatile unsigned *)0x560000A8)
-#define rGSTATUS0 (*(volatile unsigned *)0x560000AC)
-#define rGSTATUS1 (*(volatile unsigned *)0x560000B0)
-
-
-/* RTC */
-#ifdef __BIG_ENDIAN
-#define rRTCCON (*(volatile unsigned char *)0x57000043)
-#define rTICNT (*(volatile unsigned char *)0x57000047)
-#define rRTCALM (*(volatile unsigned char *)0x57000053)
-#define rALMSEC (*(volatile unsigned char *)0x57000057)
-#define rALMMIN (*(volatile unsigned char *)0x5700005B)
-#define rALMHOUR (*(volatile unsigned char *)0x5700005F)
-#define rALMDATE (*(volatile unsigned char *)0x57000063)
-#define rALMMON (*(volatile unsigned char *)0x57000067)
-#define rALMYEAR (*(volatile unsigned char *)0x5700006B)
-#define rRTCRST (*(volatile unsigned char *)0x5700006F)
-#define rBCDSEC (*(volatile unsigned char *)0x57000073)
-#define rBCDMIN (*(volatile unsigned char *)0x57000077)
-#define rBCDHOUR (*(volatile unsigned char *)0x5700007B)
-#define rBCDDATE (*(volatile unsigned char *)0x5700007F)
-#define rBCDDAY (*(volatile unsigned char *)0x57000083)
-#define rBCDMON (*(volatile unsigned char *)0x57000087)
-#define rBCDYEAR (*(volatile unsigned char *)0x5700008B)
-#else /* little endian */
-#define rRTCCON (*(volatile unsigned char *)0x57000040)
-#define rTICNT (*(volatile unsigned char *)0x57000044)
-#define rRTCALM (*(volatile unsigned char *)0x57000050)
-#define rALMSEC (*(volatile unsigned char *)0x57000054)
-#define rALMMIN (*(volatile unsigned char *)0x57000058)
-#define rALMHOUR (*(volatile unsigned char *)0x5700005C)
-#define rALMDATE (*(volatile unsigned char *)0x57000060)
-#define rALMMON (*(volatile unsigned char *)0x57000064)
-#define rALMYEAR (*(volatile unsigned char *)0x57000068)
-#define rRTCRST (*(volatile unsigned char *)0x5700006C)
-#define rBCDSEC (*(volatile unsigned char *)0x57000070)
-#define rBCDMIN (*(volatile unsigned char *)0x57000074)
-#define rBCDHOUR (*(volatile unsigned char *)0x57000078)
-#define rBCDDATE (*(volatile unsigned char *)0x5700007C)
-#define rBCDDAY (*(volatile unsigned char *)0x57000080)
-#define rBCDMON (*(volatile unsigned char *)0x57000084)
-#define rBCDYEAR (*(volatile unsigned char *)0x57000088)
-#endif
-
-
-/* ADC */
-#define rADCCON (*(volatile unsigned *)0x58000000)
-#define rADCTSC (*(volatile unsigned *)0x58000004)
-#define rADCDLY (*(volatile unsigned *)0x58000008)
-#define rADCDAT0 (*(volatile unsigned *)0x5800000C)
-#define rADCDAT1 (*(volatile unsigned *)0x58000010)
-
-
-/* SPI */
-#define rSPCON0 (*(volatile unsigned *)0x59000000)
-#define rSPSTA0 (*(volatile unsigned *)0x59000004)
-#define rSPPIN0 (*(volatile unsigned *)0x59000008)
-#define rSPPRE0 (*(volatile unsigned *)0x5900000C)
-#define rSPTDAT0 (*(volatile unsigned *)0x59000010)
-#define rSPRDAT0 (*(volatile unsigned *)0x59000014)
-#define rSPCON1 (*(volatile unsigned *)0x59000020)
-#define rSPSTA1 (*(volatile unsigned *)0x59000024)
-#define rSPPIN1 (*(volatile unsigned *)0x59000028)
-#define rSPPRE1 (*(volatile unsigned *)0x5900002C)
-#define rSPTDAT1 (*(volatile unsigned *)0x59000030)
-#define rSPRDAT1 (*(volatile unsigned *)0x59000034)
-
-
-/* SD INTERFACE */
-#define rSDICON (*(volatile unsigned *)0x5A000000)
-#define rSDIPRE (*(volatile unsigned *)0x5A000004)
-#define rSDICmdArg (*(volatile unsigned *)0x5A000008)
-#define rSDICmdCon (*(volatile unsigned *)0x5A00000C)
-#define rSDICmdSta (*(volatile unsigned *)0x5A000010)
-#define rSDIRSP0 (*(volatile unsigned *)0x5A000014)
-#define rSDIRSP1 (*(volatile unsigned *)0x5A000018)
-#define rSDIRSP2 (*(volatile unsigned *)0x5A00001C)
-#define rSDIRSP3 (*(volatile unsigned *)0x5A000020)
-#define rSDIDTimer (*(volatile unsigned *)0x5A000024)
-#define rSDIBSize (*(volatile unsigned *)0x5A000028)
-#define rSDIDatCon (*(volatile unsigned *)0x5A00002C)
-#define rSDIDatCnt (*(volatile unsigned *)0x5A000030)
-#define rSDIDatSta (*(volatile unsigned *)0x5A000034)
-#define rSDIFSTA (*(volatile unsigned *)0x5A000038)
-#ifdef __BIG_ENDIAN
-#define rSDIDAT (*(volatile unsigned char *)0x5A00003F)
-#else
-#define rSDIDAT (*(volatile unsigned char *)0x5A00003C)
-#endif
-#define rSDIIntMsk (*(volatile unsigned *)0x5A000040)
-
-#endif
+};
#endif /*__S3C24X0_H__*/
extern struct serial_device s3c24xx_serial2_device;
#endif
+#if defined(CONFIG_S5PC1XX)
+extern struct serial_device s5pc1xx_serial0_device;
+extern struct serial_device s5pc1xx_serial1_device;
+extern struct serial_device s5pc1xx_serial2_device;
+extern struct serial_device s5pc1xx_serial3_device;
+#endif
+
#if defined(CONFIG_OMAP3_ZOOM2)
extern struct serial_device zoom2_serial_device0;
extern struct serial_device zoom2_serial_device1;
projects / karo-tx-uboot.git / commitdiff