Merge remote-tracking branch 'u-boot-pxa/master' into 'u-boot-arm/master'

diff --git a/Makefile b/Makefile
index 7310c4ef0af4e6da4a27fa2b5f5ba39e9e69f602..0d86b555d70d3ebb04dc9170755873b0b83d9ca9 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -350,12 +350,14 @@ endif
 
 # enable combined SPL/u-boot/dtb rules for tegra
 ifneq ($(CONFIG_TEGRA),)
+ifeq ($(CONFIG_SPL),y)
 ifeq ($(CONFIG_OF_SEPARATE),y)
 ALL-y += $(obj)u-boot-dtb-tegra.bin
 else
 ALL-y += $(obj)u-boot-nodtb-tegra.bin
 endif
 endif
+endif
 
 build := -f $(TOPDIR)/scripts/Makefile.build -C
 

diff --git a/arch/arm/cpu/arm720t/tegra-common/cpu.c b/arch/arm/cpu/arm720t/tegra-common/cpu.c
index 9294611be8155f8e819ba5b4d84cdb66600719b4..72c69b914c7fe188ff86d3e26ba7ce98ade2ec49 100644 (file)
--- a/arch/arm/cpu/arm720t/tegra-common/cpu.c
+++ b/arch/arm/cpu/arm720t/tegra-common/cpu.c
@@ -49,33 +49,68 @@ int get_num_cpus(void)
  * Timing tables for each SOC for all four oscillator options.
  */
 struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
-       /* T20: 1 GHz */
-       /*  n,  m, p, cpcon */
-       {{ 1000, 13, 0, 12},    /* OSC 13M */
-        { 625,  12, 0, 8},     /* OSC 19.2M */
-        { 1000, 12, 0, 12},    /* OSC 12M */
-        { 1000, 26, 0, 12},    /* OSC 26M */
+       /*
+        * T20: 1 GHz
+        *
+        * Register   Field  Bits   Width
+        * ------------------------------
+        * PLLX_BASE  p      22:20    3
+        * PLLX_BASE  n      17: 8   10
+        * PLLX_BASE  m       4: 0    5
+        * PLLX_MISC  cpcon  11: 8    4
+        */
+       {
+               { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
+               { .n =  625, .m = 12, .p = 0, .cpcon =  8 }, /* OSC: 19.2 MHz */
+               { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
+               { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
        },
-
-       /* T25: 1.2 GHz */
-       {{ 923, 10, 0, 12},
-        { 750, 12, 0, 8},
-        { 600,  6, 0, 12},
-        { 600, 13, 0, 12},
+       /*
+        * T25: 1.2 GHz
+        *
+        * Register   Field  Bits   Width
+        * ------------------------------
+        * PLLX_BASE  p      22:20    3
+        * PLLX_BASE  n      17: 8   10
+        * PLLX_BASE  m       4: 0    5
+        * PLLX_MISC  cpcon  11: 8    4
+        */
+       {
+               { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
+               { .n = 750, .m = 12, .p = 0, .cpcon =  8 }, /* OSC: 19.2 MHz */
+               { .n = 600, .m =  6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
+               { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
        },
-
-       /* T30: 1.4 GHz */
-       {{ 862, 8, 0, 8},
-        { 583, 8, 0, 4},
-        { 700, 6, 0, 8},
-        { 700, 13, 0, 8},
+       /*
+        * T30: 1.4 GHz
+        *
+        * Register   Field  Bits   Width
+        * ------------------------------
+        * PLLX_BASE  p      22:20    3
+        * PLLX_BASE  n      17: 8   10
+        * PLLX_BASE  m       4: 0    5
+        * PLLX_MISC  cpcon  11: 8    4
+        */
+       {
+               { .n = 862, .m =  8, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
+               { .n = 583, .m =  8, .p = 0, .cpcon = 4 }, /* OSC: 19.2 MHz */
+               { .n = 700, .m =  6, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
+               { .n = 700, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
        },
-
-       /* T114: 1.4 GHz */
-       {{ 862, 8, 0, 8},
-        { 583, 8, 0, 4},
-        { 696, 12, 0, 8},
-        { 700, 13, 0, 8},
+       /*
+        * T114: 700 MHz
+        *
+        * Register   Field  Bits   Width
+        * ------------------------------
+        * PLLX_BASE  p      23:20    4
+        * PLLX_BASE  n      15: 8    8
+        * PLLX_BASE  m       7: 0    8
+        */
+       {
+               { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
+               { .n =  73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
+               { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
+               { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
        },
 };
 
@@ -100,6 +135,7 @@ void adjust_pllp_out_freqs(void)
 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
                u32 divp, u32 cpcon)
 {
+       int chip = tegra_get_chip();
        u32 reg;
 
        /* If PLLX is already enabled, just return */
@@ -116,7 +152,10 @@ int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
        writel(reg, &pll->pll_base);
 
        /* Set cpcon to PLLX_MISC */
-       reg = (cpcon << PLL_CPCON_SHIFT);
+       if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
+               reg = (cpcon << PLL_CPCON_SHIFT);
+       else
+               reg = 0;
 
        /* Set dccon to PLLX_MISC if freq > 600MHz */
        if (divn > 600)

diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index 6fb11cb5c49c5a5dfb01e343f8757f4589964219..60d71a6c30ad01a50d2a533cd734a71b216e7f8e 100644 (file)
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -71,6 +71,7 @@ int tegra_get_chip_sku(void)
                switch (sku_id) {
                case SKU_ID_T33:
                case SKU_ID_T30:
+               case SKU_ID_TM30MQS_P_A3:
                        return TEGRA_SOC_T30;
                }
                break;

diff --git a/arch/arm/include/asm/arch-tegra/clock.h b/arch/arm/include/asm/arch-tegra/clock.h
index c3174bd7fce62e03700f464c2aef50fdb366a975..e7d0fd45ee1dc4abd52c182298b5bd0c595a36d8 100644 (file)
--- a/arch/arm/include/asm/arch-tegra/clock.h
+++ b/arch/arm/include/asm/arch-tegra/clock.h
@@ -113,9 +113,9 @@ void reset_set_enable(enum periph_id periph_id, int enable);
 enum crc_reset_id {
        /* Things we can hold in reset for each CPU */
        crc_rst_cpu = 1,
-       crc_rst_de = 1 << 2,    /* What is de? */
-       crc_rst_watchdog = 1 << 3,
-       crc_rst_debug = 1 << 4,
+       crc_rst_de = 1 << 4,    /* What is de? */
+       crc_rst_watchdog = 1 << 8,
+       crc_rst_debug = 1 << 12,
 };
 
 /**

diff --git a/arch/arm/include/asm/arch-tegra/tegra.h b/arch/arm/include/asm/arch-tegra/tegra.h
index 25d1fc4db1dd3a1133f59d4b244248e4880d5579..e99f681ffddbaadf796f0f25a4e09a98d357d34e 100644 (file)
--- a/arch/arm/include/asm/arch-tegra/tegra.h
+++ b/arch/arm/include/asm/arch-tegra/tegra.h
@@ -65,6 +65,7 @@ enum {
        SKU_ID_T25E             = 0x1c,
        SKU_ID_T33              = 0x80,
        SKU_ID_T30              = 0x81, /* Cardhu value */
+       SKU_ID_TM30MQS_P_A3     = 0xb1,
        SKU_ID_T114_ENG         = 0x00, /* Dalmore value, unfused */
        SKU_ID_T114_1           = 0x01,
 };

diff --git a/board/atmel/at91sam9x5ek/at91sam9x5ek.c b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
index 6f67c34a5389c7135b2fb9e6f33197740b4d5cd3..17a2a40b4b3dc398c75e9ebee820f398c40db918 100644 (file)
--- a/board/atmel/at91sam9x5ek/at91sam9x5ek.c
+++ b/board/atmel/at91sam9x5ek/at91sam9x5ek.c
@@ -271,7 +271,6 @@ int board_init(void)
 #endif
 
 #ifdef CONFIG_ATMEL_SPI
-       at91_spi0_hw_init(1 << 0);
        at91_spi0_hw_init(1 << 4);
 #endif
 

diff --git a/board/avionic-design/common/pinmux-config-tamonten-ng.h b/board/avionic-design/common/pinmux-config-tamonten-ng.h
new file mode 100644 (file)
index 0000000..39df731
--- /dev/null
+++ b/board/avionic-design/common/pinmux-config-tamonten-ng.h
@@ -0,0 +1,385 @@
+/*
+ * (C) Copyright 2013
+ * Avionic Design GmbH <www.avionic-design.de>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef _PINMUX_CONFIG_TAMONTEN_NG_H_
+#define _PINMUX_CONFIG_TAMONTEN_NG_H_
+
+#define DEFAULT_PINMUX(_pingroup, _mux, _pull, _tri, _io)      \
+       {                                                       \
+               .pingroup       = PINGRP_##_pingroup,           \
+               .func           = PMUX_FUNC_##_mux,             \
+               .pull           = PMUX_PULL_##_pull,            \
+               .tristate       = PMUX_TRI_##_tri,              \
+               .io             = PMUX_PIN_##_io,               \
+               .lock           = PMUX_PIN_LOCK_DEFAULT,        \
+               .od             = PMUX_PIN_OD_DEFAULT,          \
+               .ioreset        = PMUX_PIN_IO_RESET_DEFAULT,    \
+       }
+
+#define I2C_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _od) \
+       {                                                       \
+               .pingroup       = PINGRP_##_pingroup,           \
+               .func           = PMUX_FUNC_##_mux,             \
+               .pull           = PMUX_PULL_##_pull,            \
+               .tristate       = PMUX_TRI_##_tri,              \
+               .io             = PMUX_PIN_##_io,               \
+               .lock           = PMUX_PIN_LOCK_##_lock,        \
+               .od             = PMUX_PIN_OD_##_od,            \
+               .ioreset        = PMUX_PIN_IO_RESET_DEFAULT,    \
+       }
+
+#define LV_PINMUX(_pingroup, _mux, _pull, _tri, _io, _lock, _ioreset) \
+       {                                                       \
+               .pingroup       = PINGRP_##_pingroup,           \
+               .func           = PMUX_FUNC_##_mux,             \
+               .pull           = PMUX_PULL_##_pull,            \
+               .tristate       = PMUX_TRI_##_tri,              \
+               .io             = PMUX_PIN_##_io,               \
+               .lock           = PMUX_PIN_LOCK_##_lock,        \
+               .od             = PMUX_PIN_OD_DEFAULT,          \
+               .ioreset        = PMUX_PIN_IO_RESET_##_ioreset  \
+       }
+
+#define DEFAULT_PADCFG(_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) \
+       {                                                       \
+               .padgrp         = PDRIVE_PINGROUP_##_padgrp,    \
+               .slwf           = _slwf,                        \
+               .slwr           = _slwr,                        \
+               .drvup          = _drvup,                       \
+               .drvdn          = _drvdn,                       \
+               .lpmd           = PGRP_LPMD_##_lpmd,            \
+               .schmt          = PGRP_SCHMT_##_schmt,          \
+               .hsm            = PGRP_HSM_##_hsm,              \
+       }
+
+static struct pingroup_config tamonten_ng_pinmux_common[] = {
+       /* SDMMC1 pinmux */
+       DEFAULT_PINMUX(SDMMC1_CLK,  SDMMC1, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(SDMMC1_CMD,  SDMMC1, UP,     NORMAL, INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT0, SDMMC1, UP,     NORMAL, INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT1, SDMMC1, UP,     NORMAL, INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT2, SDMMC1, UP,     NORMAL, INPUT),
+       DEFAULT_PINMUX(SDMMC1_DAT3, SDMMC1, UP,     NORMAL, INPUT),
+
+       /* SDMMC3 pinmux */
+       DEFAULT_PINMUX(SDMMC3_CLK,  SDMMC3, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(SDMMC3_CMD,  SDMMC3, UP,     NORMAL, INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT0, SDMMC3, UP,     NORMAL, INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT1, SDMMC3, UP,     NORMAL, INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT2, SDMMC3, UP,     NORMAL, INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT3, SDMMC3, UP,     NORMAL, INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT4, SDMMC3, UP,     NORMAL, INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT5, SDMMC3, UP,     NORMAL, INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT6, SDMMC3, UP,     NORMAL, INPUT),
+       DEFAULT_PINMUX(SDMMC3_DAT7, SDMMC3, UP,     NORMAL, INPUT),
+       DEFAULT_PINMUX(GMI_IORDY,   RSVD1,  UP,     NORMAL, INPUT),
+       DEFAULT_PINMUX(GMI_CS6_N,   RSVD1,  UP,     NORMAL, INPUT),
+
+       /* SDMMC4 pinmux */
+       LV_PINMUX(SDMMC4_CLK,   SDMMC4, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+       LV_PINMUX(SDMMC4_CMD,   SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+       LV_PINMUX(SDMMC4_DAT0,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+       LV_PINMUX(SDMMC4_DAT1,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+       LV_PINMUX(SDMMC4_DAT2,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+       LV_PINMUX(SDMMC4_DAT3,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+       LV_PINMUX(SDMMC4_DAT4,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+       LV_PINMUX(SDMMC4_DAT5,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+       LV_PINMUX(SDMMC4_DAT6,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+       LV_PINMUX(SDMMC4_DAT7,  SDMMC4, UP,     NORMAL, INPUT, DISABLE, DISABLE),
+       LV_PINMUX(SDMMC4_RST_N, RSVD1,  DOWN,   NORMAL, INPUT, DISABLE, DISABLE),
+
+       /* I2C1 pinmux */
+       I2C_PINMUX(GEN1_I2C_SCL, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+       I2C_PINMUX(GEN1_I2C_SDA, I2C1, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+       /* I2C2 pinmux */
+       I2C_PINMUX(GEN2_I2C_SCL, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+       I2C_PINMUX(GEN2_I2C_SDA, I2C2, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+       /* I2C3 pinmux */
+       I2C_PINMUX(CAM_I2C_SCL, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+       I2C_PINMUX(CAM_I2C_SDA, I2C3, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+       /* I2C4 pinmux */
+       I2C_PINMUX(DDC_SCL, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+       I2C_PINMUX(DDC_SDA, I2C4, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+       /* Power I2C pinmux */
+       I2C_PINMUX(PWR_I2C_SCL, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+       I2C_PINMUX(PWR_I2C_SDA, I2CPWR, NORMAL, NORMAL, INPUT, DISABLE, ENABLE),
+
+       /* UART1 */
+       DEFAULT_PINMUX(ULPI_DATA0, UARTA, NORMAL, NORMAL, OUTPUT),
+       DEFAULT_PINMUX(ULPI_DATA1, UARTA, NORMAL, NORMAL, INPUT),
+
+       /* UART2 */
+       DEFAULT_PINMUX(UART2_RXD,   UARTB, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(UART2_TXD,   UARTB, NORMAL, NORMAL, OUTPUT),
+
+       /* UART3 */
+       DEFAULT_PINMUX(UART3_TXD,   UARTC, NORMAL, NORMAL, OUTPUT),
+       DEFAULT_PINMUX(UART3_RXD,   UARTC, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(UART3_CTS_N, UARTC, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(UART3_RTS_N, UARTC, NORMAL, NORMAL, OUTPUT),
+
+       /* UART4 */
+       DEFAULT_PINMUX(ULPI_CLK, UARTD, NORMAL, NORMAL, OUTPUT),
+       DEFAULT_PINMUX(ULPI_DIR, UARTD, UP,     NORMAL, INPUT),
+       DEFAULT_PINMUX(ULPI_NXT, UARTD, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(ULPI_STP, UARTD, NORMAL, NORMAL, OUTPUT),
+
+       /* DAP */
+       DEFAULT_PINMUX(CLK1_OUT, EXTPERIPH1, NORMAL, NORMAL, INPUT),
+
+       /* I2S1 */
+       DEFAULT_PINMUX(DAP2_FS,   I2S1, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(DAP2_DIN,  I2S1, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(DAP2_DOUT, I2S1, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(DAP2_SCLK, I2S1, NORMAL, NORMAL, INPUT),
+
+       /* SPDIF */
+       DEFAULT_PINMUX(SPDIF_IN,  SPDIF, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(SPDIF_OUT, SPDIF, NORMAL, NORMAL, OUTPUT),
+
+       /* I2S2 */
+       DEFAULT_PINMUX(DAP3_FS,   I2S2, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(DAP3_DIN,  I2S2, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(DAP3_DOUT, I2S2, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(DAP3_SCLK, I2S2, NORMAL, NORMAL, INPUT),
+
+       /* DAP4 */
+       DEFAULT_PINMUX(DAP4_FS,   I2S3, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(DAP4_DIN,  I2S3, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(DAP4_SCLK, I2S3, NORMAL, NORMAL, INPUT),
+
+       /* Tamonten GPIO */
+       DEFAULT_PINMUX(GPIO_PV2,   RSVD1, NORMAL, NORMAL, OUTPUT),
+       DEFAULT_PINMUX(GPIO_PV3,   RSVD1, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(SPI2_CS1_N, RSVD1, NORMAL, NORMAL, INPUT),
+
+       /* LCD */
+       DEFAULT_PINMUX(LCD_PWR1,  DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_PWR2,  DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_SDIN,  DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_SDOUT, DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_WR_N,  DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_CS0_N, DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_DC0,   DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_SCK,   DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_PWR0,  DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_PCLK,  DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_DE,    DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_HSYNC, DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_VSYNC, DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_D0,    DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_D1,    DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_D2,    DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_D3,    DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_D4,    DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_D5,    DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_D6,    DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_D7,    DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_D8,    DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_D9,    DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_D10,   DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_D11,   DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_D12,   DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_D13,   DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_D14,   DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_D15,   DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_D16,   DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_D17,   DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_D18,   DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_D19,   DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_D20,   DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_D21,   DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_D22,   DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_D23,   DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_CS1_N, DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_M1,    DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(LCD_DC1,   DISPA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(CRT_HSYNC, CRT,   NORMAL, NORMAL, OUTPUT),
+       DEFAULT_PINMUX(CRT_VSYNC, CRT,   NORMAL, NORMAL, OUTPUT),
+
+       /* BT656 */
+       LV_PINMUX(VI_MCLK,  VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+       LV_PINMUX(VI_PCLK,  VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+       LV_PINMUX(VI_HSYNC, VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+       LV_PINMUX(VI_VSYNC, VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+       LV_PINMUX(VI_D2,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+       LV_PINMUX(VI_D3,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+       LV_PINMUX(VI_D4,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+       LV_PINMUX(VI_D5,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+       LV_PINMUX(VI_D6,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+       LV_PINMUX(VI_D7,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+       LV_PINMUX(VI_D8,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+       LV_PINMUX(VI_D9,    VI,    NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+       LV_PINMUX(VI_D11,   RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+       /* GPIOs */
+       DEFAULT_PINMUX(GPIO_PU5, RSVD1, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(GPIO_PU6, RSVD1, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(GMI_AD12, RSVD1, NORMAL, NORMAL, INPUT),
+
+       /* LCD BL */
+       DEFAULT_PINMUX(GMI_AD8,  PWM0,  NORMAL, NORMAL, OUTPUT),
+       DEFAULT_PINMUX(GMI_AD10, RSVD4, NORMAL, NORMAL, OUTPUT),
+
+       /* SPI4 */
+       DEFAULT_PINMUX(GMI_A16, SPI4, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(GMI_A17, SPI4, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(GMI_A18, SPI4, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(GMI_A19, SPI4, NORMAL, NORMAL, INPUT),
+
+       /* Video input GPIO */
+       DEFAULT_PINMUX(GPIO_PCC1, RSVD1, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(GPIO_PBB0, RSVD1, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(GPIO_PBB7, RSVD1, NORMAL, NORMAL, INPUT),
+
+       /* Sensor GPIO */
+       DEFAULT_PINMUX(GPIO_PCC2, RSVD1, NORMAL, NORMAL, INPUT),
+
+       /* JTAG */
+       DEFAULT_PINMUX(JTAG_RTCK, RTCK, NORMAL, NORMAL, OUTPUT),
+
+       /* Power controls */
+       DEFAULT_PINMUX(GMI_CS2_N, RSVD1, NORMAL, NORMAL, INPUT),
+
+       /* SPI1 */
+       DEFAULT_PINMUX(SPI1_MOSI,  SPI1, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(SPI1_SCK,   SPI1, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(SPI1_CS0_N, SPI1, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(SPI1_MISO,  SPI1, NORMAL, NORMAL, INPUT),
+
+       /* PMU */
+       DEFAULT_PINMUX(GPIO_PV0,    RSVD1,  UP,     NORMAL, INPUT),
+       DEFAULT_PINMUX(SYS_CLK_REQ, SYSCLK, NORMAL, NORMAL, OUTPUT),
+       DEFAULT_PINMUX(CLK_32K_IN,  SYSCLK, NORMAL, NORMAL, INPUT),
+
+       /* PCI */
+       DEFAULT_PINMUX(PEX_L0_PRSNT_N,  PCIE, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(PEX_L0_RST_N,    PCIE, NORMAL, NORMAL, OUTPUT),
+       DEFAULT_PINMUX(PEX_L0_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(PEX_WAKE_N,      PCIE, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(PEX_L1_PRSNT_N,  PCIE, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(PEX_L1_RST_N,    PCIE, NORMAL, NORMAL, OUTPUT),
+       DEFAULT_PINMUX(PEX_L1_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(PEX_L2_PRSNT_N,  PCIE, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(PEX_L2_RST_N,    PCIE, NORMAL, NORMAL, OUTPUT),
+       DEFAULT_PINMUX(PEX_L2_CLKREQ_N, PCIE, NORMAL, NORMAL, INPUT),
+
+       /* HDMI */
+       DEFAULT_PINMUX(HDMI_CEC, CEC,   NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(HDMI_INT, RSVD1, NORMAL, TRISTATE, INPUT),
+};
+
+static struct pingroup_config unused_pins_lowpower[] = {
+       /* UART1 - NC */
+       DEFAULT_PINMUX(ULPI_DATA2, UARTA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(ULPI_DATA3, UARTA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(ULPI_DATA4, UARTA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(ULPI_DATA5, UARTA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(ULPI_DATA6, UARTA, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(ULPI_DATA7, UARTA, NORMAL, NORMAL, INPUT),
+
+       /* UART2 - NC */
+       DEFAULT_PINMUX(UART2_RTS_N, UARTB, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(UART2_CTS_N, UARTB, NORMAL, NORMAL, INPUT),
+
+       /* DAP - NC */
+       DEFAULT_PINMUX(CLK1_REQ,  RSVD1, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(CLK3_OUT,  RSVD1, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(CLK3_REQ,  RSVD1, NORMAL, NORMAL, INPUT),
+
+       /* DAP4 - NC */
+       DEFAULT_PINMUX(DAP4_DOUT, I2S3, NORMAL, NORMAL, INPUT),
+
+       /* Tamonten GPIO - NC */
+       DEFAULT_PINMUX(CLK2_OUT, EXTPERIPH2, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(CLK2_REQ, DAP,        NORMAL, NORMAL, INPUT),
+
+       /* BT656 - NC */
+       LV_PINMUX(VI_D0,  RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+       LV_PINMUX(VI_D1,  RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+       LV_PINMUX(VI_D10, RSVD1, NORMAL, NORMAL, INPUT, DISABLE, DISABLE),
+
+       /* GPIO - NC */
+       DEFAULT_PINMUX(GPIO_PU0, RSVD1, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(GPIO_PU1, RSVD1, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(GPIO_PU2, RSVD1, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(GPIO_PU3, RSVD1, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(GPIO_PU4, RSVD1, NORMAL, NORMAL, INPUT),
+
+       /* Video input - NC */
+       DEFAULT_PINMUX(CAM_MCLK,  RSVD1, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(GPIO_PBB3, RSVD1, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(GPIO_PBB5, RSVD1, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(GPIO_PBB6, RSVD1, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_ROW11,  RSVD1, NORMAL, NORMAL, INPUT),
+
+       /* KBC keys - NC */
+       DEFAULT_PINMUX(KB_ROW0,  KBC, UP, NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_ROW1,  KBC, UP, NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_ROW2,  KBC, UP, NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_ROW3,  KBC, UP, NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_ROW4,  KBC, UP, NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_ROW5,  KBC, UP, NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_ROW6,  KBC, UP, NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_ROW7,  KBC, UP, NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_ROW8,  KBC, UP, NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_ROW9,  KBC, UP, NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_ROW10, KBC, UP, NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_ROW12, KBC, UP, NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_ROW13, KBC, UP, NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_ROW14, KBC, UP, NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_ROW15, KBC, UP, NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_COL0,  KBC, UP, NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_COL1,  KBC, UP, NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_COL2,  KBC, UP, NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_COL3,  KBC, UP, NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_COL4,  KBC, UP, NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_COL5,  KBC, UP, NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_COL6,  KBC, UP, NORMAL, INPUT),
+       DEFAULT_PINMUX(KB_COL7,  KBC, UP, NORMAL, INPUT),
+
+       /* PMU - NC */
+       DEFAULT_PINMUX(CLK_32K_OUT, RSVD1, NORMAL, NORMAL, INPUT),
+
+       /* Power rails GPIO - NC */
+       DEFAULT_PINMUX(SPI2_SCK,  RSVD1, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(GPIO_PBB4, RSVD1, NORMAL, NORMAL, INPUT),
+
+       /* Others - NC */
+       DEFAULT_PINMUX(GMI_WP_N,   RSVD1, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(GPIO_PV1,   RSVD1, NORMAL, NORMAL, INPUT),
+       DEFAULT_PINMUX(GMI_WAIT,   NAND, UP,     TRISTATE, OUTPUT),
+       DEFAULT_PINMUX(GMI_ADV_N,  NAND, NORMAL, TRISTATE, OUTPUT),
+       DEFAULT_PINMUX(GMI_CLK,    NAND, NORMAL, TRISTATE, OUTPUT),
+       DEFAULT_PINMUX(GMI_CS3_N,  NAND, NORMAL, NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(GMI_CS7_N,  NAND, UP,     NORMAL,   INPUT),
+       DEFAULT_PINMUX(GMI_AD0,    NAND, NORMAL, TRISTATE, OUTPUT),
+       DEFAULT_PINMUX(GMI_AD1,    NAND, NORMAL, TRISTATE, OUTPUT),
+       DEFAULT_PINMUX(GMI_AD2,    NAND, NORMAL, TRISTATE, OUTPUT),
+       DEFAULT_PINMUX(GMI_AD3,    NAND, NORMAL, TRISTATE, OUTPUT),
+       DEFAULT_PINMUX(GMI_AD4,    NAND, NORMAL, TRISTATE, OUTPUT),
+       DEFAULT_PINMUX(GMI_AD5,    NAND, NORMAL, TRISTATE, OUTPUT),
+       DEFAULT_PINMUX(GMI_AD6,    NAND, NORMAL, TRISTATE, OUTPUT),
+       DEFAULT_PINMUX(GMI_AD7,    NAND, NORMAL, TRISTATE, OUTPUT),
+       DEFAULT_PINMUX(GMI_AD9,    PWM1, NORMAL, NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(GMI_AD11,   NAND, NORMAL, NORMAL,   OUTPUT),
+       DEFAULT_PINMUX(GMI_AD13,   NAND, UP,     NORMAL,   INPUT),
+       DEFAULT_PINMUX(GMI_WR_N,   NAND, NORMAL, TRISTATE, OUTPUT),
+       DEFAULT_PINMUX(GMI_OE_N,   NAND, NORMAL, TRISTATE, OUTPUT),
+       DEFAULT_PINMUX(GMI_DQS,    NAND, NORMAL, TRISTATE, OUTPUT),
+};
+
+static struct padctrl_config tamonten_ng_padctrl[] = {
+       /* (_padgrp, _slwf, _slwr, _drvup, _drvdn, _lpmd, _schmt, _hsm) */
+       DEFAULT_PADCFG(SDIO1, SDIOCFG_DRVUP_SLWF, SDIOCFG_DRVDN_SLWR,
+               SDIOCFG_DRVUP, SDIOCFG_DRVDN, NONE, DISABLE, DISABLE),
+};
+#endif /* _PINMUX_CONFIG_TAMONTEN_NG_H_ */

diff --git a/board/avionic-design/common/tamonten-ng.c b/board/avionic-design/common/tamonten-ng.c
new file mode 100644 (file)
index 0000000..9d395c6
--- /dev/null
+++ b/board/avionic-design/common/tamonten-ng.c
@@ -0,0 +1,85 @@
+/*
+ * (C) Copyright 2013
+ * Avionic Design GmbH <www.avionic-design.de>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/pinmux.h>
+#include <asm/arch/gp_padctrl.h>
+#include <asm/arch/gpio.h>
+#include <asm/gpio.h>
+#include "pinmux-config-tamonten-ng.h"
+#include <i2c.h>
+
+#define PMU_I2C_ADDRESS                0x2D
+
+#define PMU_REG_LDO5           0x32
+
+#define PMU_REG_LDO_HIGH_POWER 1
+
+/* Voltage selection for the LDOs with 100mV resolution */
+#define PMU_REG_LDO_SEL_100(mV)        ((((mV - 1000) / 100) + 2) << 2)
+
+#define PMU_REG_LDO_100(st, mV)        (PMU_REG_LDO_##st | PMU_REG_LDO_SEL_100(mV))
+
+#define PMU_LDO5(st, mV)       PMU_REG_LDO_100(st, mV)
+
+void pinmux_init(void)
+{
+       pinmux_config_table(tamonten_ng_pinmux_common,
+                           ARRAY_SIZE(tamonten_ng_pinmux_common));
+       pinmux_config_table(unused_pins_lowpower,
+                           ARRAY_SIZE(unused_pins_lowpower));
+
+       /* Initialize any non-default pad configs (APB_MISC_GP regs) */
+       padgrp_config_table(tamonten_ng_padctrl,
+                           ARRAY_SIZE(tamonten_ng_padctrl));
+}
+
+void gpio_early_init(void)
+{
+       /* Turn on the alive signal */
+       gpio_request(GPIO_PV2, "ALIVE");
+       gpio_direction_output(GPIO_PV2, 1);
+
+       /* Remove the reset on the external periph */
+       gpio_request(GPIO_PI4, "nRST_PERIPH");
+       gpio_direction_output(GPIO_PI4, 1);
+}
+
+void pmu_write(uchar reg, uchar data)
+{
+       i2c_set_bus_num(4);     /* PMU is on bus 4 */
+       i2c_write(PMU_I2C_ADDRESS, reg, 1, &data, 1);
+}
+
+/*
+ * Do I2C/PMU writes to bring up SD card bus power
+ *
+ */
+void board_sdmmc_voltage_init(void)
+{
+       /* Enable LDO5 with 3.3v for SDMMC3 */
+       pmu_write(PMU_REG_LDO5, PMU_LDO5(HIGH_POWER, 3300));
+
+       /* Switch the power on */
+       gpio_request(GPIO_PJ2, "EN_3V3_EMMC");
+       gpio_direction_output(GPIO_PJ2, 1);
+}
+
+/*
+ * Routine: pin_mux_mmc
+ * Description: setup the MMC muxes, power rails, etc.
+ */
+void pin_mux_mmc(void)
+{
+       /*
+        * NOTE: We don't do mmc-specific pin muxes here.
+        * They were done globally in pinmux_init().
+        */
+
+       /* Bring up the SDIO1 power rail */
+       board_sdmmc_voltage_init();
+}

diff --git a/board/avionic-design/dts/tegra30-tamonten.dtsi b/board/avionic-design/dts/tegra30-tamonten.dtsi
new file mode 100644 (file)
index 0000000..50d5762
--- /dev/null
+++ b/board/avionic-design/dts/tegra30-tamonten.dtsi
@@ -0,0 +1,69 @@
+#include "tegra30.dtsi"
+
+/ {
+       model = "Avionic Design Tamonten NG";
+       compatible = "ad,tamonten-ng", "nvidia,tegra30";
+
+       memory {
+               reg = <0x80000000 0x40000000>;
+       };
+
+       aliases {
+               i2c0 = "/i2c@7000c000";
+               i2c1 = "/i2c@7000c700";
+               i2c2 = "/i2c@7000c400";
+               i2c3 = "/i2c@7000c500";
+               i2c4 = "/i2c@7000d000";
+               sdhci0 = "/sdhci@78000600";
+               sdhci1 = "/sdhci@78000400";
+               sdhci2 = "/sdhci@78000000";
+               usb0 = "/usb@7d008000";
+       };
+
+       /* GEN1 */
+       i2c@7000c000 {
+               status = "okay";
+               clock-frequency = <100000>;
+       };
+
+       /* GEN2 */
+       i2c@7000c400 {
+               clock-frequency = <100000>;
+       };
+
+       /* CAM */
+       i2c@7000c500 {
+               status = "okay";
+               clock-frequency = <100000>;
+       };
+
+       /* DDC */
+       i2c@7000c700 {
+               status = "okay";
+               clock-frequency = <100000>;
+       };
+
+       /* PWR */
+       i2c@7000d000 {
+               status = "okay";
+               clock-frequency = <100000>;
+       };
+
+       /* SD slot on the base board */
+       sdhci@78000400 {
+               cd-gpios = <&gpio 69 1>; /* gpio PI5 */
+               wp-gpios = <&gpio 67 0>; /* gpio PI3 */
+               bus-width = <4>;
+       };
+
+       /* EMMC on the COM module */
+       sdhci@78000600 {
+               status = "okay";
+               bus-width = <8>;
+       };
+
+       usb@7d008000 {
+               status = "okay";
+       };
+
+};

diff --git a/board/avionic-design/dts/tegra30-tec-ng.dts b/board/avionic-design/dts/tegra30-tec-ng.dts
new file mode 100644 (file)
index 0000000..8a69e81
--- /dev/null
+++ b/board/avionic-design/dts/tegra30-tec-ng.dts
@@ -0,0 +1,18 @@
+/dts-v1/;
+
+#include "tegra30-tamonten.dtsi"
+
+/ {
+       model = "Avionic Design Tamonten™ NG Evaluation Carrier";
+       compatible = "ad,tec-ng", "nvidia,tegra30";
+
+       /* GEN2 */
+       i2c@7000c400 {
+               status = "okay";
+       };
+
+       /* SD card slot */
+       sdhci@78000400 {
+               status = "okay";
+       };
+};

diff --git a/board/avionic-design/tec-ng/Makefile b/board/avionic-design/tec-ng/Makefile
new file mode 100644 (file)
index 0000000..f41eb30
--- /dev/null
+++ b/board/avionic-design/tec-ng/Makefile
@@ -0,0 +1,12 @@
+#
+# (C) Copyright 2013
+# Avionic Design GmbH <www.avionic-design.de>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+$(shell mkdir -p $(obj)../common $(obj)../../nvidia/common)
+
+obj-y  := ../common/tamonten-ng.o
+
+include ../../nvidia/common/common.mk

diff --git a/board/renesas/koelsch/koelsch.c b/board/renesas/koelsch/koelsch.c
index 7153f652b53116c1152157da8ad30d34a34607eb..89f5c91c636bf7174b7533ebc79698def41e8003 100644 (file)
--- a/board/renesas/koelsch/koelsch.c
+++ b/board/renesas/koelsch/koelsch.c
@@ -16,6 +16,8 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/arch/rmobile.h>
+#include <netdev.h>
+#include <miiphy.h>
 #include <i2c.h>
 #include "qos.h"
 
@@ -207,6 +209,10 @@ void s_init(void)
 #define SMSTPCR7       0xE615014C
 #define SCIF0_MSTP721  (1 << 21)
 
+#define MSTPSR8                0xE61509A0
+#define SMSTPCR8       0xE6150990
+#define ETHER_MSTP813  (1 << 13)
+
 #define PMMR   0xE6060000
 #define GPSR4  0xE6060014
 #define IPSR14 0xE6060058
@@ -241,9 +247,16 @@ int board_early_init_f(void)
 
        mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
 
+       /* ETHER */
+       mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+
        return 0;
 }
 
+/* LSI pin pull-up control */
+#define PUPR5 0xe6060114
+#define PUPR5_ETH 0x3FFC0000
+#define PUPR5_ETH_MAGIC        (1 << 27)
 int board_init(void)
 {
        /* adress of boot parameters */
@@ -252,9 +265,59 @@ int board_init(void)
        /* Init PFC controller */
        r8a7791_pinmux_init();
 
+       /* ETHER Enable */
+       gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
+       gpio_request(GPIO_FN_ETH_RX_ER, NULL);
+       gpio_request(GPIO_FN_ETH_RXD0, NULL);
+       gpio_request(GPIO_FN_ETH_RXD1, NULL);
+       gpio_request(GPIO_FN_ETH_LINK, NULL);
+       gpio_request(GPIO_FN_ETH_REFCLK, NULL);
+       gpio_request(GPIO_FN_ETH_MDIO, NULL);
+       gpio_request(GPIO_FN_ETH_TXD1, NULL);
+       gpio_request(GPIO_FN_ETH_TX_EN, NULL);
+       gpio_request(GPIO_FN_ETH_TXD0, NULL);
+       gpio_request(GPIO_FN_ETH_MDC, NULL);
+       gpio_request(GPIO_FN_IRQ0, NULL);
+
+       mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH & ~PUPR5_ETH_MAGIC);
+       gpio_request(GPIO_GP_5_22, NULL); /* PHY_RST */
+       mstp_clrbits_le32(PUPR5, PUPR5, PUPR5_ETH_MAGIC);
+
+       gpio_direction_output(GPIO_GP_5_22, 0);
+       mdelay(20);
+       gpio_set_value(GPIO_GP_5_22, 1);
+       udelay(1);
+
        return 0;
 }
 
+#define CXR24 0xEE7003C0 /* MAC address high register */
+#define CXR25 0xEE7003C8 /* MAC address low register */
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SH_ETHER
+       int ret = -ENODEV;
+       u32 val;
+       unsigned char enetaddr[6];
+
+       ret = sh_eth_initialize(bis);
+       if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+               return ret;
+
+       /* Set Mac address */
+       val = enetaddr[0] << 24 | enetaddr[1] << 16 |
+               enetaddr[2] << 8 | enetaddr[3];
+       writel(val, CXR24);
+
+       val = enetaddr[4] << 8 | enetaddr[5];
+       writel(val, CXR25);
+
+       return ret;
+#else
+       return 0;
+#endif
+}
+
 int dram_init(void)
 {
        gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
@@ -263,6 +326,20 @@ int dram_init(void)
        return 0;
 }
 
+/* koelsch has KSZ8041NL/RNL */
+#define PHY_CONTROL1   0x1E
+#define PHY_LED_MODE   0xC0000
+#define PHY_LED_MODE_ACK       0x4000
+int board_phy_config(struct phy_device *phydev)
+{
+       int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
+       ret &= ~PHY_LED_MODE;
+       ret |= PHY_LED_MODE_ACK;
+       ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
+
+       return 0;
+}
+
 const struct rmobile_sysinfo sysinfo = {
        CONFIG_RMOBILE_BOARD_STRING
 };
@@ -280,4 +357,10 @@ int board_late_init(void)
 
 void reset_cpu(ulong addr)
 {
+       u8 val;
+
+       i2c_set_bus_num(2); /* PowerIC connected to ch2 */
+       i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+       val |= 0x02;
+       i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
 }

diff --git a/board/renesas/lager/lager.c b/board/renesas/lager/lager.c
index 5c99fc9b58c1ebdcb69af99c23677a3ad59c505e..cdd5b32135785f6886ea4c29d2c35ebd45716d7f 100644 (file)
--- a/board/renesas/lager/lager.c
+++ b/board/renesas/lager/lager.c
@@ -18,6 +18,8 @@
 #include <asm/arch/sys_proto.h>
 #include <asm/gpio.h>
 #include <asm/arch/rmobile.h>
+#include <miiphy.h>
+#include <i2c.h>
 #include "qos.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -207,6 +209,10 @@ void s_init(void)
 #define SMSTPCR7       0xE615014C
 #define SCIF0_MSTP721  (1 << 21)
 
+#define MSTPSR8        0xE61509A0
+#define SMSTPCR8       0xE6150990
+#define ETHER_MSTP813  (1 << 13)
+
 #define PMMR   0xE6060000
 #define GPSR4  0xE6060014
 #define IPSR14 0xE6060058
@@ -242,6 +248,9 @@ int board_early_init_f(void)
 
        mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF0_MSTP721);
 
+       /* ETHER */
+       mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813);
+
        return 0;
 }
 
@@ -256,6 +265,68 @@ int board_init(void)
        /* Init PFC controller */
        r8a7790_pinmux_init();
 
+       /* ETHER Enable */
+       gpio_request(GPIO_FN_ETH_CRS_DV, NULL);
+       gpio_request(GPIO_FN_ETH_RX_ER, NULL);
+       gpio_request(GPIO_FN_ETH_RXD0, NULL);
+       gpio_request(GPIO_FN_ETH_RXD1, NULL);
+       gpio_request(GPIO_FN_ETH_LINK, NULL);
+       gpio_request(GPIO_FN_ETH_REF_CLK, NULL);
+       gpio_request(GPIO_FN_ETH_MDIO, NULL);
+       gpio_request(GPIO_FN_ETH_TXD1, NULL);
+       gpio_request(GPIO_FN_ETH_TX_EN, NULL);
+       gpio_request(GPIO_FN_ETH_MAGIC, NULL);
+       gpio_request(GPIO_FN_ETH_TXD0, NULL);
+       gpio_request(GPIO_FN_ETH_MDC, NULL);
+       gpio_request(GPIO_FN_IRQ0, NULL);
+
+       gpio_request(GPIO_GP_5_31, NULL);       /* PHY_RST */
+       gpio_direction_output(GPIO_GP_5_31, 0);
+       mdelay(20);
+       gpio_set_value(GPIO_GP_5_31, 1);
+       udelay(1);
+
+       return 0;
+}
+
+#define CXR24 0xEE7003C0 /* MAC address high register */
+#define CXR25 0xEE7003C8 /* MAC address low register */
+int board_eth_init(bd_t *bis)
+{
+       int ret = -ENODEV;
+
+#ifdef CONFIG_SH_ETHER
+       u32 val;
+       unsigned char enetaddr[6];
+
+       ret = sh_eth_initialize(bis);
+       if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+               return ret;
+
+       /* Set Mac address */
+       val = enetaddr[0] << 24 | enetaddr[1] << 16 |
+           enetaddr[2] << 8 | enetaddr[3];
+       writel(val, CXR24);
+
+       val = enetaddr[4] << 8 | enetaddr[5];
+       writel(val, CXR25);
+
+#endif
+
+       return ret;
+}
+
+/* lager has KSZ8041NL/RNL */
+#define PHY_CONTROL1   0x1E
+#define PHY_LED_MODE   0xC0000
+#define PHY_LED_MODE_ACK       0x4000
+int board_phy_config(struct phy_device *phydev)
+{
+       int ret = phy_read(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1);
+       ret &= ~PHY_LED_MODE;
+       ret |= PHY_LED_MODE_ACK;
+       ret = phy_write(phydev, MDIO_DEVAD_NONE, PHY_CONTROL1, (u16)ret);
+
        return 0;
 }
 
@@ -284,4 +355,11 @@ int board_late_init(void)
 
 void reset_cpu(ulong addr)
 {
+       u8 val;
+
+       i2c_set_bus_num(3); /* PowerIC connected to ch3 */
+       i2c_init(400000, 0);
+       i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
+       val |= 0x02;
+       i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1);
 }

diff --git a/boards.cfg b/boards.cfg
index b662149e6692111fca9449c8fa4c3adaa4ac57ea..152d85e80d18c30f5e4a89d20b3b37a11c561728 100644 (file)
--- a/boards.cfg
+++ b/boards.cfg
@@ -359,9 +359,10 @@ Active  arm         armv7          vf610       freescale       vf610twr
 Active  arm         armv7          zynq        xilinx          zynq                zynq                                 -                                                                                                                                 Michal Simek <monstr@monstr.eu>
 Active  arm         armv7          zynq        xilinx          zynq                zynq_dcc                             zynq:ZYNQ_DCC                                                                                                                     Michal Simek <monstr@monstr.eu>
 Active  arm         armv7:arm720t  tegra114    nvidia          dalmore             dalmore                              -                                                                                                                                 Tom Warren <twarren@nvidia.com>
-Active  arm         armv7:arm720t  tegra20     avionic-design  medcom-wide         medcom-wide                          -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
-Active  arm         armv7:arm720t  tegra20     avionic-design  plutux              plutux                               -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
-Active  arm         armv7:arm720t  tegra20     avionic-design  tec                 tec                                  -                                                                                                                                 Thierry Reding <thierry.reding@avionic-design.de>
+Active  arm         armv7:arm720t  tegra20     avionic-design  medcom-wide         medcom-wide                          -                                                                                                                                 Alban Bedel <alban.bedel@avionic-design.de>
+Active  arm         armv7:arm720t  tegra20     avionic-design  plutux              plutux                               -                                                                                                                                 Alban Bedel <alban.bedel@avionic-design.de>
+Active  arm         armv7:arm720t  tegra20     avionic-design  tec                 tec                                  -                                                                                                                                 Alban Bedel <alban.bedel@avionic-design.de>
+Active  arm         armv7:arm720t  tegra30     avionic-design  tec-ng              tec-ng                               -                                                                                                                                 Alban Bedel <alban.bedel@avionic-design.de>
 Active  arm         armv7:arm720t  tegra20     compal          paz00               paz00                                -                                                                                                                                 Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra20     compulab        trimslice           trimslice                            -                                                                                                                                 Tom Warren <twarren@nvidia.com>:Stephen Warren <swarren@nvidia.com>
 Active  arm         armv7:arm720t  tegra20     nvidia          harmony             harmony                              -                                                                                                                                 Tom Warren <twarren@nvidia.com>

diff --git a/doc/README.rmobile b/doc/README.rmobile
index 7ec63f13ceae3696014911b6f6069235f66d22f8..4fbbcb3ef7582ca66e936fb60c6a2070afcb7d7a 100644 (file)
--- a/doc/README.rmobile
+++ b/doc/README.rmobile
@@ -2,13 +2,15 @@ Summary
 =======
 
 This README is about U-Boot support for Renesas's ARM Cortex-A9 based RMOBILE[1]
-family of SoCs. Renesas's RMOBILE SoC family contains an ARM Cortex-A9.
+and R-Car[2]family of SoCs. Renesas's RMOBILE/R-Car SoC family contains an ARM
+Cortex-A9.
 
 Currently the following boards are supported:
 
-* KMC KZM-A9-GT [2]
-
-* Atmark-Techno Armadillo-800-EVA [3]
+* KMC KZM-A9-GT [3]
+* Atmark-Techno Armadillo-800-EVA [4]
+* Renesas Electronics Lager
+* Renesas Electronics Koelsch
 
 Toolchain
 =========
@@ -17,7 +19,7 @@ ARM Cortex-A9 support ARM v7 instruction set (-march=armv7a).
 But currently we compile with -march=armv5 to allow more compilers to work.
 (For U-Boot code this has no performance impact.)
 Because there was no compiler which is supporting armv7a not much before.
-Currently, ELDK[4], Linaro[5], CodeSourcey[6] and Emdebian[7] supports -march=armv7a
+Currently, ELDK[5], Linaro[6], CodeSourcey[7] and Emdebian[8] supports -march=armv7a
 and you can get.
 
 Build
@@ -25,13 +27,26 @@ Build
 
 * KZM-A9-GT
 
-make kzm9g_config
-make
+  make kzm9g_config
+  make
 
 * Armadillo-800-EVA
 
-make armadillo-800eva_config
-make
+  make armadillo-800eva_config
+  make
+
+  Note: Armadillo-800-EVA's U-Boot supports booting from SDcard only.
+        Please see "B.2 Appendix B Boot Specifications" in hardware manual.
+
+* Lager
+
+  make lager_config
+  make
+
+* Koelsch
+
+  make koelsch_config
+  make
 
 Links
 =====
@@ -40,26 +55,30 @@ Links
 
 http://am.renesas.com/products/soc/assp/mobile/r_mobile/index.jsp
 
-[2] KZM-A9-GT
+[2] Renesas R-Car:
+
+http://am.renesas.com/products/soc/assp/automotive/index.jsp
+
+[3] KZM-A9-GT
 
 http://www.kmckk.co.jp/kzma9-gt/index.html
 
-[3] Armadillo-800-EVA
+[4] Armadillo-800-EVA
 
 http://armadillo.atmark-techno.com/armadillo-800-EVA
 
-[4] ELDK
+[5] ELDK
 
 http://www.denx.de/wiki/view/ELDK-5/WebHome#Section_1.6.
 
-[5] Linaro
+[6] Linaro
 
 http://www.linaro.org/downloads/
 
-[6] CodeSourcey
+[7] CodeSourcey
 
 http://www.mentor.com/embedded-software/codesourcery
 
-[7] Emdebian
+[8] Emdebian
 
 http://www.emdebian.org/crosstools.html

diff --git a/drivers/i2c/tegra_i2c.c b/drivers/i2c/tegra_i2c.c
index 9847cf126bf26104c268c54ddead0f22033b881d..594e5ddeb43ee8a64dc4e7956cb1d6e44bfd4d12 100644 (file)
--- a/drivers/i2c/tegra_i2c.c
+++ b/drivers/i2c/tegra_i2c.c
@@ -629,3 +629,8 @@ U_BOOT_I2C_ADAP_COMPLETE(tegra2, tegra_i2c_init, tegra_i2c_probe,
 U_BOOT_I2C_ADAP_COMPLETE(tegra3, tegra_i2c_init, tegra_i2c_probe,
                         tegra_i2c_read, tegra_i2c_write,
                         tegra_i2c_set_bus_speed, 100000, 0, 3)
+#if TEGRA_I2C_NUM_CONTROLLERS > 4
+U_BOOT_I2C_ADAP_COMPLETE(tegra4, tegra_i2c_init, tegra_i2c_probe,
+                        tegra_i2c_read, tegra_i2c_write,
+                        tegra_i2c_set_bus_speed, 100000, 0, 4)
+#endif

diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h
index ea9a50e0b1f2ba277b882445e94d686d11faa5a6..f0a6757ff66578044b84f1d628a3442bce502caf 100644 (file)
--- a/include/configs/at91sam9x5ek.h
+++ b/include/configs/at91sam9x5ek.h
@@ -44,7 +44,6 @@
 #define LCD_BPP                        LCD_COLOR16
 #define LCD_OUTPUT_BPP         24
 #define CONFIG_LCD_LOGO
-#undef LCD_TEST_PATTERN
 #define CONFIG_LCD_INFO
 #define CONFIG_LCD_INFO_BELOW_LOGO
 #define CONFIG_SYS_WHITE_ON_BLACK
@@ -62,14 +61,15 @@
 #define CONFIG_BOOTP_GATEWAY
 #define CONFIG_BOOTP_HOSTNAME
 
+/* no NOR flash */
+#define CONFIG_SYS_NO_FLASH
+
 /*
  * Command line configuration.
  */
 #include <config_cmd_default.h>
 #undef CONFIG_CMD_FPGA
 #undef CONFIG_CMD_IMI
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_LOADS
 
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
@@ -101,9 +101,6 @@
 #define CONFIG_SF_DEFAULT_SPEED                30000000
 #endif
 
-/* no NOR flash */
-#define CONFIG_SYS_NO_FLASH
-
 /* NAND flash */
 #ifdef CONFIG_CMD_NAND
 #define CONFIG_NAND_ATMEL
@@ -244,8 +241,4 @@
  */
 #define CONFIG_SYS_MALLOC_LEN          (512 * 1024 + 0x1000)
 
-#ifdef CONFIG_USE_IRQ
-#error CONFIG_USE_IRQ not supported
-#endif
-
 #endif

diff --git a/include/configs/koelsch.h b/include/configs/koelsch.h
index 59c494854be8dd52451cc4887a87ec2c751e39aa..f8cca5b28106054d8f6d66c6ee52e41e424cff61 100644 (file)
--- a/include/configs/koelsch.h
+++ b/include/configs/koelsch.h
@@ -18,13 +18,18 @@
 
 #include <asm/arch/rmobile.h>
 
-#define        CONFIG_CMD_EDITENV
-#define        CONFIG_CMD_SAVEENV
+#define CONFIG_CMD_EDITENV
+#define CONFIG_CMD_SAVEENV
 #define CONFIG_CMD_MEMORY
 #define CONFIG_CMD_DFL
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_RUN
 #define CONFIG_CMD_LOADS
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
 #define CONFIG_CMD_BOOTZ
 #define        CONFIG_CMD_FLASH
 
@@ -123,6 +128,20 @@
 #define CONFIG_ENV_SIZE                (CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN)
 
+/* SH Ether */
+#define        CONFIG_NET_MULTI
+#define CONFIG_SH_ETHER
+#define CONFIG_SH_ETHER_USE_PORT       0
+#define CONFIG_SH_ETHER_PHY_ADDR       0x1
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
+
 /* Board Clock */
 #define        CONFIG_SYS_CLK_FREQ     10000000
 #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
@@ -130,4 +149,22 @@
 #define CONFIG_SYS_TMU_CLK_DIV 4
 #define CONFIG_SYS_HZ          1000
 
+/* i2c */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_SH
+#define CONFIG_SYS_I2C_SLAVE   0x7F
+#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS      3
+#define CONFIG_SYS_I2C_SH_BASE0                0xE6500000
+#define CONFIG_SYS_I2C_SH_SPEED0       400000
+#define CONFIG_SYS_I2C_SH_BASE1                0xE6510000
+#define CONFIG_SYS_I2C_SH_SPEED1       400000
+#define CONFIG_SYS_I2C_SH_BASE2                0xE60B0000
+#define CONFIG_SYS_I2C_SH_SPEED2       400000
+#define CONFIG_SH_I2C_DATA_HIGH        4
+#define CONFIG_SH_I2C_DATA_LOW 5
+#define CONFIG_SH_I2C_CLOCK    10000000
+
+#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
+
 #endif /* __KOELSCH_H */

diff --git a/include/configs/lager.h b/include/configs/lager.h
index 7819edddc6c6cf762a26dfa61ee3c7b2ecfc0f60..893282540e3943ad20cb659c161f67dc1f7a8171 100644 (file)
--- a/include/configs/lager.h
+++ b/include/configs/lager.h
@@ -28,6 +28,11 @@
 #define CONFIG_CMD_SDRAM
 #define CONFIG_CMD_RUN
 #define CONFIG_CMD_LOADS
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_NFS
 #define CONFIG_CMD_BOOTZ
 #define        CONFIG_CMD_FLASH
 
@@ -127,12 +132,42 @@
 #define CONFIG_ENV_SIZE                (CONFIG_ENV_SECT_SIZE)
 #define CONFIG_ENV_SIZE_REDUND (CONFIG_SYS_MONITOR_LEN)
 
+/* SH Ether */
+#define        CONFIG_NET_MULTI
+#define CONFIG_SH_ETHER
+#define CONFIG_SH_ETHER_USE_PORT       0
+#define CONFIG_SH_ETHER_PHY_ADDR       0x1
+#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
+#define CONFIG_SH_ETHER_ALIGNE_SIZE    64
+#define CONFIG_SH_ETHER_CACHE_WRITEBACK
+#define CONFIG_SH_ETHER_CACHE_INVALIDATE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_MICREL
+#define CONFIG_BITBANGMII
+#define CONFIG_BITBANGMII_MULTI
+
+/* I2C */
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_RCAR
+#define CONFIG_SYS_RCAR_I2C0_BASE      0xE6508000
+#define CONFIG_SYS_RCAR_I2C0_SPEED     400000
+#define CONFIG_SYS_RCAR_I2C1_BASE      0xE6518000
+#define CONFIG_SYS_RCAR_I2C1_SPEED     400000
+#define CONFIG_SYS_RCAR_I2C2_BASE      0xE6530000
+#define CONFIG_SYS_RCAR_I2C2_SPEED     400000
+#define CONFIG_SYS_RCAR_I2C3_BASE      0xE6540000
+#define CONFIG_SYS_RCAR_I2C3_SPEED     400000
+#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS    4
+
+#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
+
 /* Board Clock */
 #define CONFIG_BASE_CLK_FREQ   20000000u
 #define CONFIG_SH_TMU_CLK_FREQ (CONFIG_BASE_CLK_FREQ / 2) /* EXT / 2 */
 #define CONFIG_PLL1_CLK_FREQ   (CONFIG_BASE_CLK_FREQ * 156 / 2)
 #define CONFIG_PLL1_DIV2_CLK_FREQ      (CONFIG_PLL1_CLK_FREQ / 2)
 #define CONFIG_MP_CLK_FREQ     (CONFIG_PLL1_DIV2_CLK_FREQ / 15)
+#define CONFIG_HP_CLK_FREQ     (CONFIG_PLL1_CLK_FREQ / 12)
 #define CONFIG_SH_SCIF_CLK_FREQ        CONFIG_MP_CLK_FREQ
 
 #define CONFIG_SYS_TMU_CLK_DIV 4

diff --git a/include/configs/tec-ng.h b/include/configs/tec-ng.h
new file mode 100644 (file)
index 0000000..13baa76
--- /dev/null
+++ b/include/configs/tec-ng.h
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2013
+ * Avionic Design GmbH <www.avionic-design.de>
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include "tegra30-common.h"
+
+/* Enable fdt support for tec-ng. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE     tegra30-tec-ng
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT                       "Tegra30 (TEC-NG) # "
+#define CONFIG_TEGRA_BOARD_STRING      "Avionic Design Tamonten™ NG Evaluation Carrier"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA_ENABLE_UARTD
+#define CONFIG_SYS_NS16550_COM1                NV_PA_APB_UARTD_BASE
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* I2C */
+#define CONFIG_SYS_I2C_TEGRA
+#define CONFIG_SYS_I2C_INIT_BOARD
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_SYS_MAX_I2C_BUS         TEGRA_I2C_NUM_CONTROLLERS
+#define CONFIG_SYS_I2C_SPEED           100000
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+
+/* SD/MMC */
+#define CONFIG_MMC
+#define CONFIG_GENERIC_MMC
+#define CONFIG_TEGRA_MMC
+#define CONFIG_CMD_MMC
+
+/* Environment in eMMC, at the end of 2nd "boot sector" */
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_ENV_OFFSET              (-CONFIG_ENV_SIZE)
+#define CONFIG_SYS_MMC_ENV_DEV         0
+#define CONFIG_SYS_MMC_ENV_PART                2
+
+/* SPI */
+#define CONFIG_TEGRA20_SLINK
+#define CONFIG_TEGRA_SLINK_CTRLS       6
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_WINBOND
+#define CONFIG_SF_DEFAULT_MODE         SPI_MODE_0
+#define CONFIG_SF_DEFAULT_SPEED        24000000
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_SF
+#define CONFIG_SPI_FLASH_SIZE          (4 << 20)
+
+/* USB Host support */
+#define CONFIG_USB_EHCI
+#define CONFIG_USB_EHCI_TEGRA
+#define CONFIG_USB_STORAGE
+#define CONFIG_CMD_USB
+
+/* USB networking support */
+#define CONFIG_USB_HOST_ETHER
+#define CONFIG_USB_ETHER_SMSC95XX
+
+/* General networking support */
+#define CONFIG_CMD_NET
+#define CONFIG_CMD_DHCP
+
+/* Tag support */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+/* support the new (FDT-based) image format */
+#define CONFIG_FIT
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */

diff --git a/include/configs/tegra114-common.h b/include/configs/tegra114-common.h
index c3de9a999e952e3f893a6ae9efa2538e53b79e3e..a4e8a5f5eb53824205ac3bb032bd8785f47d3316 100644 (file)
--- a/include/configs/tegra114-common.h
+++ b/include/configs/tegra114-common.h
@@ -82,5 +82,6 @@
 
 /* For USB EHCI controller */
 #define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_EHCI_TXFIFO_THRESH  0x10
 
 #endif /* _TEGRA114_COMMON_H_ */

diff --git a/include/configs/tegra30-common.h b/include/configs/tegra30-common.h
index 99acbfd28b29de65dad657cbd556cd523322e2c2..b5550d7d099c74bed362573f003e478196eb35f9 100644 (file)
--- a/include/configs/tegra30-common.h
+++ b/include/configs/tegra30-common.h
@@ -79,5 +79,6 @@
 
 /* For USB EHCI controller */
 #define CONFIG_EHCI_IS_TDI
+#define CONFIG_USB_EHCI_TXFIFO_THRESH  0x10
 
 #endif /* _TEGRA30_COMMON_H_ */