config: rename CONFIG_MX* to CONFIG_SOC_MX*

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 0219f4ec6010a02f5d3d508e01f8e9710a23ad43..025e44494db3969415bb9c3ad51bdb051f721f48 100644 (file)
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -58,6 +58,63 @@ config SEMIHOSTING
          the hosted environment to call out to the emulator to
          retrieve files from the host machine.
 
          the hosted environment to call out to the emulator to
          retrieve files from the host machine.
 

+config SOC_AM335X
+       bool
+       select CPU_V7
+       select OMAP_COMMON
+
+config SOC_MXS
+       bool
+       select CPU_ARM926EJS
+
+config SOC_MX23
+       bool
+       select SOC_MXS
+
+config SOC_MX28
+       bool
+       select SOC_MXS
+
+config SOC_MX5
+       bool
+       select CPU_V7
+
+config SOC_MX53
+       bool
+       select SOC_MX5
+
+config SOC_MX51
+       bool
+       select SOC_MX5
+
+config SOC_MX53
+       bool
+       select SOC_MX5
+
+config SOC_MX6
+       bool
+       select CPU_V7
+
+config SOC_MX6Q
+       bool
+       select SOC_MX6
+
+config SOC_MX6DL
+       bool
+       select SOC_MX6
+
+config SOC_MX6S
+       bool
+       select SOC_MX6
+
+config SOC_MX6SX
+       bool
+       select SOC_MX6
+
+config SOC_SAMA5D4
+       bool
+       select CPU_V7
+

 choice
        prompt "Target select"
 
 choice
        prompt "Target select"
 


@@ -255,30 +312,30 @@ config TARGET_MX25PDK
 
 config TARGET_TX25
        bool "Support tx25"
 
 config TARGET_TX25
        bool "Support tx25"

-       select CPU_ARM926EJS
+       select SOC_MX25

        select SUPPORT_SPL
 
 config TARGET_TX28
        bool "Support tx28"
        select SUPPORT_SPL
 
 config TARGET_TX28
        bool "Support tx28"

-       select CPU_ARM926EJS
+       select SOC_MX28

        select SUPPORT_SPL
 
 config TARGET_TX48
        bool "Support tx48"
        select SUPPORT_SPL
 
 config TARGET_TX48
        bool "Support tx48"

-       select CPU_V7
+       select SOC_AM335X

        select SUPPORT_SPL
 
 config TARGET_TX51
        bool "Support tx51"
        select SUPPORT_SPL
 
 config TARGET_TX51
        bool "Support tx51"

-       select CPU_V7
+       select SOC_MX51

 
 config TARGET_TX53
        bool "Support tx53"
 
 config TARGET_TX53
        bool "Support tx53"

-       select CPU_V7
+       select SOC_MX53

 
 config TARGET_TX6
        bool "Support tx6"
 
 config TARGET_TX6
        bool "Support tx6"

-       select CPU_V7
+       select SOC_MX6

 
 config TARGET_ZMX25
        bool "Support zmx25"
 
 config TARGET_ZMX25
        bool "Support zmx25"


@@ -696,15 +753,18 @@ config TARGET_OT1200
 config OMAP34XX
        bool "OMAP34XX SoC"
        select CPU_V7
 config OMAP34XX
        bool "OMAP34XX SoC"
        select CPU_V7

+       select OMAP_COMMON

 
 config OMAP44XX
        bool "OMAP44XX SoC"
        select CPU_V7
 
 config OMAP44XX
        bool "OMAP44XX SoC"
        select CPU_V7

+       select OMAP_COMMON

        select SUPPORT_SPL
 
 config OMAP54XX
        bool "OMAP54XX SoC"
        select CPU_V7
        select SUPPORT_SPL
 
 config OMAP54XX
        bool "OMAP54XX SoC"
        select CPU_V7

+       select OMAP_COMMON

        select SUPPORT_SPL
 
 config RMOBILE
        select SUPPORT_SPL
 
 config RMOBILE

diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ebb7dc34ac7d879a77de54a69654c7d18caf8549..c68144fb5f33536edc4810a48c091fb4c281c38e 100644 (file)
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -15,7 +15,7 @@ libs-y += arch/arm/cpu/
 libs-y += arch/arm/lib/
 
 ifeq ($(CONFIG_SPL_BUILD),y)
 libs-y += arch/arm/lib/
 
 ifeq ($(CONFIG_SPL_BUILD),y)

-ifneq (,$(CONFIG_MX23)$(CONFIG_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
+ifneq (,$(CONFIG_SOC_MX23)$(CONFIG_SOC_MX35)$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))

 libs-y += arch/arm/imx-common/
 endif
 else
 libs-y += arch/arm/imx-common/
 endif
 else

diff --git a/arch/arm/cpu/arm1136/Makefile b/arch/arm/cpu/arm1136/Makefile
index 56a9390b0111856fcb335f858ec5bef5a75b2277..d2b48988322be585804cd9842c3cd36870be6c54 100644 (file)
--- a/arch/arm/cpu/arm1136/Makefile
+++ b/arch/arm/cpu/arm1136/Makefile
@@ -8,5 +8,5 @@
 extra-y        = start.o
 obj-y  = cpu.o
 
 extra-y        = start.o
 obj-y  = cpu.o
 

-obj-$(CONFIG_MX31) += mx31/
-obj-$(CONFIG_MX35) += mx35/
+obj-$(CONFIG_SOC_MX31) += mx31/
+obj-$(CONFIG_SOC_MX35) += mx35/

diff --git a/arch/arm/cpu/arm926ejs/Makefile b/arch/arm/cpu/arm926ejs/Makefile
index adcea9f6834c0fbfc15e64ce1f8d084dac7e758f..f1d6c01d4f02391c864b6986c9126268f75a692e 100644 (file)
--- a/arch/arm/cpu/arm926ejs/Makefile
+++ b/arch/arm/cpu/arm926ejs/Makefile
@@ -20,8 +20,8 @@ obj-$(CONFIG_ARCH_DAVINCI) += davinci/
 obj-$(CONFIG_KIRKWOOD) += kirkwood/
 obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/
 obj-$(CONFIG_MB86R0x) += mb86r0x/
 obj-$(CONFIG_KIRKWOOD) += kirkwood/
 obj-$(if $(filter lpc32xx,$(SOC)),y) += lpc32xx/
 obj-$(CONFIG_MB86R0x) += mb86r0x/

-obj-$(CONFIG_MX25) += mx25/
-obj-$(CONFIG_MX27) += mx27/
+obj-$(CONFIG_SOC_MX25) += mx25/
+obj-$(CONFIG_SOC_MX27) += mx27/

 obj-$(if $(filter mxs,$(SOC)),y) += mxs/
 obj-$(CONFIG_ARCH_NOMADIK) += nomadik/
 obj-$(CONFIG_ORION5X) += orion5x/
 obj-$(if $(filter mxs,$(SOC)),y) += mxs/
 obj-$(CONFIG_ARCH_NOMADIK) += nomadik/
 obj-$(CONFIG_ORION5X) += orion5x/

diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile
index 6c594945582bbdd3a6a1538f7b2492f3d6a857a2..c457f32a4b0454e891a2f14599b2aab35042ecda 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mxs/Makefile
+++ b/arch/arm/cpu/arm926ejs/mxs/Makefile
@@ -14,8 +14,8 @@ obj-y += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o
 endif
 
 # Specify the target for use in elftosb call
 endif
 
 # Specify the target for use in elftosb call

-MKIMAGE_TARGET-$(CONFIG_MX23) = mxsimage.mx23.cfg
-MKIMAGE_TARGET-$(CONFIG_MX28) = mxsimage.mx28.cfg
+MKIMAGE_TARGET-$(CONFIG_SOC_MX23) = mxsimage.mx23.cfg
+MKIMAGE_TARGET-$(CONFIG_SOC_MX28) = mxsimage.mx28.cfg

 
 # Generate HAB-capable IVT
 #
 
 # Generate HAB-capable IVT
 #

diff --git a/arch/arm/cpu/arm926ejs/mxs/clock.c b/arch/arm/cpu/arm926ejs/mxs/clock.c
index 4d0cc04583324eab342cf6373a76bbc57ef6bd4f..6217c61b840f7b58226b3a2278fafe226254ad82 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mxs/clock.c
+++ b/arch/arm/cpu/arm926ejs/mxs/clock.c
@@ -28,9 +28,9 @@
 #define        PLL_FREQ_MHZ    (PLL_FREQ_KHZ / 1000)
 #define        XTAL_FREQ_MHZ   (XTAL_FREQ_KHZ / 1000)
 
 #define        PLL_FREQ_MHZ    (PLL_FREQ_KHZ / 1000)
 #define        XTAL_FREQ_MHZ   (XTAL_FREQ_KHZ / 1000)
 

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

 #define MXC_SSPCLK_MAX MXC_SSPCLK0
 #define MXC_SSPCLK_MAX MXC_SSPCLK0

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

 #define MXC_SSPCLK_MAX MXC_SSPCLK3
 #endif
 
 #define MXC_SSPCLK_MAX MXC_SSPCLK3
 #endif
 


@@ -137,10 +137,10 @@ static uint32_t mxs_get_emiclk(void)
 
 static uint32_t mxs_get_gpmiclk(void)
 {
 
 static uint32_t mxs_get_gpmiclk(void)
 {

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

        uint8_t *reg =
                &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU];
        uint8_t *reg =
                &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU];

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

        uint8_t *reg =
                &clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI];
 #endif
        uint8_t *reg =
                &clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI];
 #endif


@@ -334,9 +334,9 @@ void mxs_set_lcdclk(uint32_t freq)
        if (freq == 0)
                return;
 
        if (freq == 0)
                return;
 

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

        writel(CLKCTRL_CLKSEQ_BYPASS_PIX, &clkctrl_regs->hw_clkctrl_clkseq_clr);
        writel(CLKCTRL_CLKSEQ_BYPASS_PIX, &clkctrl_regs->hw_clkctrl_clkseq_clr);

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

        writel(CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF, &clkctrl_regs->hw_clkctrl_clkseq_clr);
 #endif
 
        writel(CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF, &clkctrl_regs->hw_clkctrl_clkseq_clr);
 #endif
 


@@ -382,7 +382,7 @@ void mxs_set_lcdclk(uint32_t freq)
 
        k_best /= 1000;
 
 
        k_best /= 1000;
 

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

        writeb(CLKCTRL_FRAC_CLKGATE,
                &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_PIX]);
        writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK),
        writeb(CLKCTRL_FRAC_CLKGATE,
                &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_PIX]);
        writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK),


@@ -398,7 +398,7 @@ void mxs_set_lcdclk(uint32_t freq)
 
        while (readl(&clkctrl_regs->hw_clkctrl_pix) & CLKCTRL_PIX_BUSY)
                ;
 
        while (readl(&clkctrl_regs->hw_clkctrl_pix) & CLKCTRL_PIX_BUSY)
                ;

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

        writeb(CLKCTRL_FRAC_CLKGATE,
                &clkctrl_regs->hw_clkctrl_frac1_set[CLKCTRL_FRAC1_PIX]);
        writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK),
        writeb(CLKCTRL_FRAC_CLKGATE,
                &clkctrl_regs->hw_clkctrl_frac1_set[CLKCTRL_FRAC1_PIX]);
        writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK),


@@ -459,7 +459,7 @@ uint32_t mxc_get_clock(enum mxc_clock clk)
                return XTAL_FREQ_KHZ * 1000;
        case MXC_SSP0_CLK:
                return mxs_get_sspclk(MXC_SSPCLK0);
                return XTAL_FREQ_KHZ * 1000;
        case MXC_SSP0_CLK:
                return mxs_get_sspclk(MXC_SSPCLK0);

-#ifdef CONFIG_MX28
+#ifdef CONFIG_SOC_MX28

        case MXC_SSP1_CLK:
                return mxs_get_sspclk(MXC_SSPCLK1);
        case MXC_SSP2_CLK:
        case MXC_SSP1_CLK:
                return mxs_get_sspclk(MXC_SSPCLK1);
        case MXC_SSP2_CLK:

diff --git a/arch/arm/cpu/arm926ejs/mxs/iomux.c b/arch/arm/cpu/arm926ejs/mxs/iomux.c
index 2e6be06fd4862489609ad86307b2a084fd70a4bf..9285f2f6a0ec88f812c9a6dc9bfbff061b7719d2 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mxs/iomux.c
+++ b/arch/arm/cpu/arm926ejs/mxs/iomux.c
@@ -14,14 +14,14 @@
 #include <asm/arch/iomux.h>
 #include <asm/arch/imx-regs.h>
 
 #include <asm/arch/iomux.h>
 #include <asm/arch/imx-regs.h>
 

-#if    defined(CONFIG_MX23)
+#if    defined(CONFIG_SOC_MX23)

 #define        DRIVE_OFFSET    0x200
 #define        PULL_OFFSET     0x400
 #define        DRIVE_OFFSET    0x200
 #define        PULL_OFFSET     0x400

-#elif  defined(CONFIG_MX28)
+#elif  defined(CONFIG_SOC_MX28)

 #define        DRIVE_OFFSET    0x300
 #define        PULL_OFFSET     0x600
 #else
 #define        DRIVE_OFFSET    0x300
 #define        PULL_OFFSET     0x600
 #else

-#error "Please select CONFIG_MX23 or CONFIG_MX28"
+#error "Please select CONFIG_SOC_MX23 or CONFIG_SOC_MX28"

 #endif
 
 /*
 #endif
 
 /*

diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index f3c1575a36897bff3c6913be37309d70c1db120f..55c9d38d2c8b5a48b583f3c083781915b823c7b9 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -255,7 +255,7 @@ int do_mx28_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
 /*
  * Initializes on-chip ethernet controllers.
  */
 /*
  * Initializes on-chip ethernet controllers.
  */

-#if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET)
+#if defined(CONFIG_SOC_MX28) && defined(CONFIG_CMD_NET)

 int cpu_eth_init(bd_t *bis)
 {
        struct mxs_clkctrl_regs *clkctrl_regs =
 int cpu_eth_init(bd_t *bis)
 {
        struct mxs_clkctrl_regs *clkctrl_regs =

diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index 49d50196e005874007e652f80ca9c5c11f7aee76..aa8af0f2d8ec2c0d81ae91e178df51c65bb600e2 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -45,14 +45,14 @@ void early_delay(int delay)
 
 #define        MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
 static const iomux_cfg_t iomux_boot[] = {
 
 #define        MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
 static const iomux_cfg_t iomux_boot[] = {

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

        MX23_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
        MX23_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
        MX23_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
        MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
        MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
        MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,
        MX23_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
        MX23_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
        MX23_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
        MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_BOOTMODE_PAD,
        MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_BOOTMODE_PAD,
        MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_BOOTMODE_PAD,

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

        MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
        MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
        MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,
        MX28_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_BOOTMODE_PAD,
        MX28_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_BOOTMODE_PAD,
        MX28_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_BOOTMODE_PAD,


@@ -71,7 +71,7 @@ static uint8_t mxs_get_bootmode_index(void)
        /* Setup IOMUX of bootmode pads to GPIO */
        mxs_iomux_setup_multiple_pads(iomux_boot, ARRAY_SIZE(iomux_boot));
 
        /* Setup IOMUX of bootmode pads to GPIO */
        mxs_iomux_setup_multiple_pads(iomux_boot, ARRAY_SIZE(iomux_boot));
 

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

        /* Setup bootmode pins as GPIO input */
        gpio_direction_input(MX23_PAD_LCD_D00__GPIO_1_0);
        gpio_direction_input(MX23_PAD_LCD_D01__GPIO_1_1);
        /* Setup bootmode pins as GPIO input */
        gpio_direction_input(MX23_PAD_LCD_D00__GPIO_1_0);
        gpio_direction_input(MX23_PAD_LCD_D01__GPIO_1_1);


@@ -85,7 +85,7 @@ static uint8_t mxs_get_bootmode_index(void)
        bootmode |= (gpio_get_value(MX23_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2;
        bootmode |= (gpio_get_value(MX23_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3;
        bootmode |= (gpio_get_value(MX23_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;
        bootmode |= (gpio_get_value(MX23_PAD_LCD_D02__GPIO_1_2) ? 1 : 0) << 2;
        bootmode |= (gpio_get_value(MX23_PAD_LCD_D03__GPIO_1_3) ? 1 : 0) << 3;
        bootmode |= (gpio_get_value(MX23_PAD_LCD_D05__GPIO_1_5) ? 1 : 0) << 5;

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

        /* Setup bootmode pins as GPIO input */
        gpio_direction_input(MX28_PAD_LCD_D00__GPIO_1_0);
        gpio_direction_input(MX28_PAD_LCD_D01__GPIO_1_1);
        /* Setup bootmode pins as GPIO input */
        gpio_direction_input(MX28_PAD_LCD_D00__GPIO_1_0);
        gpio_direction_input(MX28_PAD_LCD_D01__GPIO_1_1);

diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index d5842e68133e880ba142c65b45512f9912827a54..0aa06125b9ec995602850bbeeda92ce43cf0ecc9 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -20,7 +20,7 @@ static uint32_t dram_vals[] = {
 /*
  * i.MX28 DDR2 at 200MHz
  */
 /*
  * i.MX28 DDR2 at 200MHz
  */

-#if defined(CONFIG_MX28)
+#if defined(CONFIG_SOC_MX28)

        0x00000000, 0x00000000, 0x00000000, 0x00000000,
        0x00000000, 0x00000000, 0x00000000, 0x00000000,
        0x00000000, 0x00000000, 0x00000000, 0x00000000,
        0x00000000, 0x00000000, 0x00000000, 0x00000000,
        0x00000000, 0x00000000, 0x00000000, 0x00000000,
        0x00000000, 0x00000000, 0x00000000, 0x00000000,


@@ -73,7 +73,7 @@ static uint32_t dram_vals[] = {
 /*
  * i.MX23 DDR at 133MHz
  */
 /*
  * i.MX23 DDR at 133MHz
  */

-#elif defined(CONFIG_MX23)
+#elif defined(CONFIG_SOC_MX23)

        0x01010001, 0x00010100, 0x01000101, 0x00000001,
        0x00000101, 0x00000000, 0x00010000, 0x01000001,
        0x00000000, 0x00000001, 0x07000200, 0x00070202,
        0x01010001, 0x00010100, 0x01000101, 0x00000001,
        0x00000101, 0x00000000, 0x00010000, 0x01000001,
        0x00000000, 0x00000001, 0x07000200, 0x00070202,


@@ -94,7 +94,7 @@ __weak void mxs_adjust_memory_params(uint32_t *dram_vals)
 {
 }
 
 {
 }
 

-#ifdef CONFIG_MX28
+#ifdef CONFIG_SOC_MX28

 static void initialize_dram_values(void)
 {
        int i;
 static void initialize_dram_values(void)
 {
        int i;


@@ -138,10 +138,10 @@ static void mxs_mem_init_clock(void)
 {
        struct mxs_clkctrl_regs *clkctrl_regs =
                (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
 {
        struct mxs_clkctrl_regs *clkctrl_regs =
                (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

        /* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */
        const unsigned char divider = 33;
        /* Fractional divider for ref_emi is 33 ; 480 * 18 / 33 = 266MHz */
        const unsigned char divider = 33;

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

        /* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */
        const unsigned char divider = 21;
 #endif
        /* Fractional divider for ref_emi is 21 ; 480 * 18 / 21 = 411MHz */
        const unsigned char divider = 21;
 #endif


@@ -235,7 +235,7 @@ uint32_t mxs_mem_get_size(void)
        return sz;
 }
 
        return sz;
 }
 

-#ifdef CONFIG_MX23
+#ifdef CONFIG_SOC_MX23

 static void mx23_mem_setup_vddmem(void)
 {
        struct mxs_power_regs *power_regs =
 static void mx23_mem_setup_vddmem(void)
 {
        struct mxs_power_regs *power_regs =


@@ -292,7 +292,7 @@ static void mx23_mem_init(void)
 }
 #endif
 
 }
 #endif
 

-#ifdef CONFIG_MX28
+#ifdef CONFIG_SOC_MX28

 static void mx28_mem_init(void)
 {
        struct mxs_pinctrl_regs *pinctrl_regs =
 static void mx28_mem_init(void)
 {
        struct mxs_pinctrl_regs *pinctrl_regs =


@@ -329,9 +329,9 @@ void mxs_mem_init(void)
 
        mxs_mem_init_clock();
 
 
        mxs_mem_init_clock();
 

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

        mx23_mem_init();
        mx23_mem_init();

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

        mx28_mem_init();
 #endif
 
        mx28_mem_init();
 #endif
 

diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
index 161a1e157ac5ae369f3e64e2927757e4e72432b0..7c846da31b8ca8a499d630ab2e135af896341292 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c
@@ -881,7 +881,7 @@ static void mxs_power_configure_power_source(void)
 
        mxs_switch_vddd_to_dcdc_source();
 
 
        mxs_switch_vddd_to_dcdc_source();
 

-#ifdef CONFIG_MX23
+#ifdef CONFIG_SOC_MX23

        /* Fire up the VDDMEM LinReg now that we're all set. */
        writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
                &power_regs->hw_power_vddmemctrl);
        /* Fire up the VDDMEM LinReg now that we're all set. */
        writel(POWER_VDDMEMCTRL_ENABLE_LINREG | POWER_VDDMEMCTRL_ENABLE_ILIMIT,
                &power_regs->hw_power_vddmemctrl);


@@ -1029,7 +1029,7 @@ struct mxs_vddx_cfg {
 
 static const struct mxs_vddx_cfg mxs_vddio_cfg = {
        .reg                    = POWER_REG(hw_power_vddioctrl),
 
 static const struct mxs_vddx_cfg mxs_vddio_cfg = {
        .reg                    = POWER_REG(hw_power_vddioctrl),

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

        .step_mV                = 25,
 #else
        .step_mV                = 50,
        .step_mV                = 25,
 #else
        .step_mV                = 50,


@@ -1070,7 +1070,7 @@ static const struct mxs_vddx_cfg mxs_vdda_cfg = {
        .bo_offset_offset       = POWER_VDDACTRL_BO_OFFSET_OFFSET,
 };
 
        .bo_offset_offset       = POWER_VDDACTRL_BO_OFFSET_OFFSET,
 };
 

-#ifdef CONFIG_MX23
+#ifdef CONFIG_SOC_MX23

 static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
        .reg                    = POWER_REG(hw_power_vddmemctrl),
        .step_mV                = 50,
 static const struct mxs_vddx_cfg mxs_vddmem_cfg = {
        .reg                    = POWER_REG(hw_power_vddmemctrl),
        .step_mV                = 50,


@@ -1198,7 +1198,7 @@ static void mxs_setup_batt_detect(void)
  */
 static void mxs_ungate_power(void)
 {
  */
 static void mxs_ungate_power(void)
 {

-#ifdef CONFIG_MX23
+#ifdef CONFIG_SOC_MX23

        writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
 #endif
 }
        writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr);
 #endif
 }


@@ -1236,7 +1236,7 @@ void mxs_power_init(void)
        mxs_power_set_vddx(&mxs_vddio_cfg, VDDIO_VAL, VDDIO_BO_VAL);
        mxs_power_set_vddx(&mxs_vddd_cfg, VDDD_VAL, VDDD_BO_VAL);
        mxs_power_set_vddx(&mxs_vdda_cfg, VDDA_VAL, VDDA_BO_VAL);
        mxs_power_set_vddx(&mxs_vddio_cfg, VDDIO_VAL, VDDIO_BO_VAL);
        mxs_power_set_vddx(&mxs_vddd_cfg, VDDD_VAL, VDDD_BO_VAL);
        mxs_power_set_vddx(&mxs_vdda_cfg, VDDA_VAL, VDDA_BO_VAL);

-#ifdef CONFIG_MX23
+#ifdef CONFIG_SOC_MX23

        mxs_power_set_vddx(&mxs_vddmem_cfg, VDDMEM_VAL, VDDMEM_BO_VAL);
 
        setbits_le32(&power_regs->hw_power_vddmemctrl,
        mxs_power_set_vddx(&mxs_vddmem_cfg, VDDMEM_VAL, VDDMEM_BO_VAL);
 
        setbits_le32(&power_regs->hw_power_vddmemctrl,

diff --git a/arch/arm/cpu/arm926ejs/mxs/timer.c b/arch/arm/cpu/arm926ejs/mxs/timer.c
index 021e21f93928b07fa5b9597fd21fd823f1cfdb59..f4514f3145d3ee578fc383ddfb5cae1234a3bcd6 100644 (file)
--- a/arch/arm/cpu/arm926ejs/mxs/timer.c
+++ b/arch/arm/cpu/arm926ejs/mxs/timer.c
@@ -16,9 +16,9 @@
 #include <asm/arch/sys_proto.h>
 
 /* Maximum fixed count */
 #include <asm/arch/sys_proto.h>
 
 /* Maximum fixed count */

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

 #define TIMER_LOAD_VAL 0xffff
 #define TIMER_LOAD_VAL 0xffff

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

 #define TIMER_LOAD_VAL 0xffffffff
 #endif
 
 #define TIMER_LOAD_VAL 0xffffffff
 #endif
 


@@ -63,9 +63,9 @@ int timer_init(void)
        mxs_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);
 
        /* Set fixed_count to 0 */
        mxs_reset_block(&timrot_regs->hw_timrot_rotctrl_reg);
 
        /* Set fixed_count to 0 */

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

        writel(0, &timrot_regs->hw_timrot_timcount0);
        writel(0, &timrot_regs->hw_timrot_timcount0);

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

        writel(0, &timrot_regs->hw_timrot_fixed_count0);
 #endif
 
        writel(0, &timrot_regs->hw_timrot_fixed_count0);
 #endif
 


@@ -76,16 +76,16 @@ int timer_init(void)
 
 #ifndef DEBUG_TIMER_WRAP
        /* Set fixed_count to maximum value */
 
 #ifndef DEBUG_TIMER_WRAP
        /* Set fixed_count to maximum value */

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

        writel(TIMER_LOAD_VAL - 1, &timrot_regs->hw_timrot_timcount0);
        writel(TIMER_LOAD_VAL - 1, &timrot_regs->hw_timrot_timcount0);

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

        writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
 #endif
 #else /* DEBUG_TIMER_WRAP */
        /* Set fixed_count so that the counter will wrap after 20 seconds */
        writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
 #endif
 #else /* DEBUG_TIMER_WRAP */
        /* Set fixed_count so that the counter will wrap after 20 seconds */

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

        writel(20 * MXS_INCREMENTER_HZ - 1, &timrot_regs->hw_timrot_timcount0);
        writel(20 * MXS_INCREMENTER_HZ - 1, &timrot_regs->hw_timrot_timcount0);

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

        writel(20 * MXS_INCREMENTER_HZ,
                &timrot_regs->hw_timrot_fixed_count0);
 #endif
        writel(20 * MXS_INCREMENTER_HZ,
                &timrot_regs->hw_timrot_fixed_count0);
 #endif


@@ -98,9 +98,9 @@ int timer_init(void)
                &timrot_regs->hw_timrot_timctrl0_clr);
 #ifdef DEBUG_TIMER_WRAP
        /* Set fixed_count to maximum value for subsequent loads */
                &timrot_regs->hw_timrot_timctrl0_clr);
 #ifdef DEBUG_TIMER_WRAP
        /* Set fixed_count to maximum value for subsequent loads */

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

        writel(20 * MXS_INCREMENTER_HZ - 1, &timrot_regs->hw_timrot_timcount0);
        writel(20 * MXS_INCREMENTER_HZ - 1, &timrot_regs->hw_timrot_timcount0);

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

        writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
 #endif
 #endif /* DEBUG_TIMER_WRAP */
        writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0);
 #endif
 #endif /* DEBUG_TIMER_WRAP */


@@ -121,11 +121,11 @@ unsigned long long get_ticks(void)
        struct mxs_timrot_regs *timrot_regs =
                (struct mxs_timrot_regs *)MXS_TIMROT_BASE;
        unsigned long now;
        struct mxs_timrot_regs *timrot_regs =
                (struct mxs_timrot_regs *)MXS_TIMROT_BASE;
        unsigned long now;

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

        /* Upper bits are the valid ones. */
        now = readl(&timrot_regs->hw_timrot_timcount0) >>
                TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET;
        /* Upper bits are the valid ones. */
        now = readl(&timrot_regs->hw_timrot_timcount0) >>
                TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET;

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

        /* The timer is counting down, so subtract the register value from
         * the counter period length (implicitly 2^32) to get an incrementing
         * timestamp
        /* The timer is counting down, so subtract the register value from
         * the counter period length (implicitly 2^32) to get an incrementing
         * timestamp

diff --git a/arch/arm/cpu/armv7/Makefile b/arch/arm/cpu/armv7/Makefile
index 409e6f5651b67cf2e85fbf63ad284f01ca6b9908..21d63e1a9198bf87310a5e15bd3423a3a3341e9d 100644 (file)
--- a/arch/arm/cpu/armv7/Makefile
+++ b/arch/arm/cpu/armv7/Makefile
@@ -12,7 +12,7 @@ obj-y += cache_v7.o
 obj-y  += cpu.o
 obj-y  += syslib.o
 
 obj-y  += cpu.o
 obj-y  += syslib.o
 

-ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),)
+ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(CONFIG_TEGRA)$(CONFIG_SOC_MX6)$(CONFIG_TI81XX)$(CONFIG_AT91FAMILY)$(CONFIG_SUNXI),)

 ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
 obj-y  += lowlevel_init.o
 endif
 ifneq ($(CONFIG_SKIP_LOWLEVEL_INIT),y)
 obj-y  += lowlevel_init.o
 endif


@@ -49,7 +49,7 @@ obj-$(CONFIG_ARCH_HIGHBANK) += highbank/
 obj-$(CONFIG_ARCH_KEYSTONE) += keystone/
 obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
 obj-$(if $(filter mx5,$(SOC)),y) += mx5/
 obj-$(CONFIG_ARCH_KEYSTONE) += keystone/
 obj-$(if $(filter ls102xa,$(SOC)),y) += ls102xa/
 obj-$(if $(filter mx5,$(SOC)),y) += mx5/

-obj-$(CONFIG_MX6) += mx6/
+obj-$(CONFIG_SOC_MX6) += mx6/

 obj-$(CONFIG_OMAP34XX) += omap3/
 obj-$(CONFIG_OMAP44XX) += omap4/
 obj-$(CONFIG_OMAP54XX) += omap5/
 obj-$(CONFIG_OMAP34XX) += omap3/
 obj-$(CONFIG_OMAP44XX) += omap4/
 obj-$(CONFIG_OMAP54XX) += omap5/


@@ -61,5 +61,5 @@ obj-$(CONFIG_ARCH_SUNXI) += sunxi/
 obj-$(CONFIG_TEGRA20) += tegra20/
 obj-$(CONFIG_U8500) += u8500/
 obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/
 obj-$(CONFIG_TEGRA20) += tegra20/
 obj-$(CONFIG_U8500) += u8500/
 obj-$(CONFIG_ARCH_UNIPHIER) += uniphier/

-obj-$(CONFIG_VF610) += vf610/
+obj-$(CONFIG_SOC_VF610) += vf610/

 obj-$(CONFIG_ZYNQ) += zynq/
 obj-$(CONFIG_ZYNQ) += zynq/

diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index 443fb997826244080a4dd3d4ce7a1a979ee1e802..ed6072fdc77974ca573b1cf2964391ac6be1bd90 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -20,7 +20,7 @@ enum pll_clocks {
        PLL1_CLOCK = 0,
        PLL2_CLOCK,
        PLL3_CLOCK,
        PLL1_CLOCK = 0,
        PLL2_CLOCK,
        PLL3_CLOCK,

-#ifdef CONFIG_MX53
+#ifdef CONFIG_SOC_MX53

        PLL4_CLOCK,
 #endif
        PLL_CLOCKS,
        PLL4_CLOCK,
 #endif
        PLL_CLOCKS,


@@ -30,7 +30,7 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = {
        [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
        [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
        [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,
        [PLL1_CLOCK] = (struct mxc_pll_reg *)PLL1_BASE_ADDR,
        [PLL2_CLOCK] = (struct mxc_pll_reg *)PLL2_BASE_ADDR,
        [PLL3_CLOCK] = (struct mxc_pll_reg *)PLL3_BASE_ADDR,

-#ifdef CONFIG_MX53
+#ifdef CONFIG_SOC_MX53

        [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
 #endif
 };
        [PLL4_CLOCK] = (struct mxc_pll_reg *)PLL4_BASE_ADDR,
 #endif
 };


@@ -243,7 +243,7 @@ void ipu_di_clk_disable(int di)
        }
 }
 
        }
 }
 

-#ifdef CONFIG_MX53
+#ifdef CONFIG_SOC_MX53

 void ldb_clk_enable(int ldb)
 {
        switch (ldb) {
 void ldb_clk_enable(int ldb)
 {
        switch (ldb) {


@@ -283,9 +283,9 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
 {
        u32 mask;
 
 {
        u32 mask;
 

-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)

        if (i2c_num > 1)
        if (i2c_num > 1)

-#elif defined(CONFIG_MX53)
+#elif defined(CONFIG_SOC_MX53)

        if (i2c_num > 2)
 #endif
                return -EINVAL;
        if (i2c_num > 2)
 #endif
                return -EINVAL;


@@ -304,7 +304,7 @@ void set_usb_phy_clk(void)
        clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
 }
 
        clrbits_le32(&mxc_ccm->cscmr1, MXC_CCM_CSCMR1_USB_PHY_CLK_SEL);
 }
 

-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)

 void enable_usb_phy1_clk(bool enable)
 {
        unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
 void enable_usb_phy1_clk(bool enable)
 {
        unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;


@@ -318,7 +318,7 @@ void enable_usb_phy2_clk(bool enable)
 {
        /* i.MX51 has a single USB PHY clock, so do nothing here. */
 }
 {
        /* i.MX51 has a single USB PHY clock, so do nothing here. */
 }

-#elif defined(CONFIG_MX53)
+#elif defined(CONFIG_SOC_MX53)

 void enable_usb_phy1_clk(bool enable)
 {
        unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
 void enable_usb_phy1_clk(bool enable)
 {
        unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;


@@ -393,7 +393,7 @@ static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq)
        return ret;
 }
 
        return ret;
 }
 

-#ifdef CONFIG_MX51
+#ifdef CONFIG_SOC_MX51

 /*
  * This function returns the Frequency Pre-Multiplier clock.
  */
 /*
  * This function returns the Frequency Pre-Multiplier clock.
  */


@@ -420,9 +420,9 @@ static u32 get_lp_apm(void)
        u32 ccsr = readl(&mxc_ccm->ccsr);
 
        if (ccsr & MXC_CCM_CCSR_LP_APM)
        u32 ccsr = readl(&mxc_ccm->ccsr);
 
        if (ccsr & MXC_CCM_CCSR_LP_APM)

-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)

                ret_val = get_fpm();
                ret_val = get_fpm();

-#elif defined(CONFIG_MX53)
+#elif defined(CONFIG_SOC_MX53)

                ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
 #endif
        else
                ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
 #endif
        else


@@ -644,7 +644,7 @@ static u32 get_ddr_clk(void)
        u32 ret_val = 0;
        u32 cbcmr = readl(&mxc_ccm->cbcmr);
        u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);
        u32 ret_val = 0;
        u32 cbcmr = readl(&mxc_ccm->cbcmr);
        u32 ddr_clk_sel = MXC_CCM_CBCMR_DDR_CLK_SEL_RD(cbcmr);

-#ifdef CONFIG_MX51
+#ifdef CONFIG_SOC_MX51

        u32 cbcdr = readl(&mxc_ccm->cbcdr);
        if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
                u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);
        u32 cbcdr = readl(&mxc_ccm->cbcdr);
        if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
                u32 ddr_clk_podf = MXC_CCM_CBCDR_DDR_PODF_RD(cbcdr);


@@ -878,7 +878,7 @@ static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param)
                /* Switch back */
                __raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr);
                break;
                /* Switch back */
                __raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr);
                break;

-#ifdef CONFIG_MX53
+#ifdef CONFIG_SOC_MX53

        case PLL4_CLOCK:
                /* Switch to pll4 bypass clock */
                __raw_writel(ccsr | 0x20, &mxc_ccm->ccsr);
        case PLL4_CLOCK:
                /* Switch to pll4 bypass clock */
                __raw_writel(ccsr | 0x20, &mxc_ccm->ccsr);


@@ -1119,7 +1119,7 @@ int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk)
        return 0;
 }
 
        return 0;
 }
 

-#ifdef CONFIG_MX53
+#ifdef CONFIG_SOC_MX53

 /*
  * The clock for the external interface can be set to use internal clock
  * if fuse bank 4, row 3, bit 2 is set.
 /*
  * The clock for the external interface can be set to use internal clock
  * if fuse bank 4, row 3, bit 2 is set.


@@ -1166,7 +1166,7 @@ static int do_mx5_showclocks(void)
        pr_clk_val(PLL2, freq);
        freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
        pr_clk_val(PLL3, freq);
        pr_clk_val(PLL2, freq);
        freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK);
        pr_clk_val(PLL3, freq);

-#ifdef CONFIG_MX53
+#ifdef CONFIG_SOC_MX53

        freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
        pr_clk_val(PLL4, freq);
 #endif
        freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK);
        pr_clk_val(PLL4, freq);
 #endif

diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
index 3e7746b9bfde65b1f81ad995c446007e66c47e89..6273b7aac8fdca72eb9dfc4b69af160e929082cc 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S
@@ -36,7 +36,7 @@
                 1 << 23 |              /* disable write allocate combine */ \
                 1 << 22                /* disable write allocate */
 
                 1 << 23 |              /* disable write allocate combine */ \
                 1 << 22                /* disable write allocate */
 

-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)

        ldr r3, [r4, #ROM_SI_REV]
        cmp r3, #0x10
 
        ldr r3, [r4, #ROM_SI_REV]
        cmp r3, #0x10
 


@@ -76,7 +76,7 @@
 
 /* M4IF setup */
 .macro init_m4if
 
 /* M4IF setup */
 .macro init_m4if

-#ifdef CONFIG_MX51
+#ifdef CONFIG_SOC_MX51

        /* VPU and IPU given higher priority (0x4)
         * IPU accesses with ID=0x1 given highest priority (=0xA)
         */
        /* VPU and IPU given higher priority (0x4)
         * IPU accesses with ID=0x1 given highest priority (=0xA)
         */


@@ -163,7 +163,7 @@ setup_pll_func:
 
 .macro init_clock
        ldr r0, =CCM_BASE_ADDR
 
 .macro init_clock
        ldr r0, =CCM_BASE_ADDR

-#if defined (CONFIG_MX51)
+#if defined (CONFIG_SOC_MX51)

        /* Gate off clocks to the peripherals first */
        ldr r1, =0x3FFFFFFF
        str r1, [r0, #CLKCTL_CCGR0]
        /* Gate off clocks to the peripherals first */
        ldr r1, =0x3FFFFFFF
        str r1, [r0, #CLKCTL_CCGR0]


@@ -276,7 +276,7 @@ setup_pll_func:
        mov r1, #0x000A0000
        add r1, r1, #0x00000F0
        str r1, [r0, #CLKCTL_CCOSR]
        mov r1, #0x000A0000
        add r1, r1, #0x00000F0
        str r1, [r0, #CLKCTL_CCOSR]

-#else  /* CONFIG_MX53 */
+#else  /* CONFIG_SOC_MX53 */

        /* Gate off clocks to the peripherals first */
        ldr r1, =0x3FFFFFFF
        str r1, [r0, #CLKCTL_CCGR0]
        /* Gate off clocks to the peripherals first */
        ldr r1, =0x3FFFFFFF
        str r1, [r0, #CLKCTL_CCGR0]


@@ -420,7 +420,7 @@ setup_pll_func:
        add r1, r1, #0x00000F0
        str r1, [r0, #CLKCTL_CCOSR]
 
        add r1, r1, #0x00000F0
        str r1, [r0, #CLKCTL_CCOSR]
 

-#endif /* CONFIG_MX53 */
+#endif /* CONFIG_SOC_MX53 */

 .endm
 
 ENTRY(lowlevel_init)
 .endm
 
 ENTRY(lowlevel_init)


@@ -461,7 +461,7 @@ W_DP_800:           .word DP_OP_800
                        .word DP_MFD_800
                        .word DP_MFN_800
 #endif
                        .word DP_MFD_800
                        .word DP_MFN_800
 #endif

-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)

 W_DP_665:              .word DP_OP_665
                        .word DP_MFD_665
                        .word DP_MFN_665
 W_DP_665:              .word DP_OP_665
                        .word DP_MFD_665
                        .word DP_MFN_665

diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c
index 95564a8257d33fb1e3b8b6a0fa13a3cb87d33b99..30b90e9d281294ecf4fe35b1614debd995c1bfcc 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/soc.c
+++ b/arch/arm/cpu/armv7/mx5/soc.c
@@ -16,7 +16,7 @@
 #include <asm/io.h>
 #include <asm/imx-common/boot_mode.h>
 
 #include <asm/io.h>
 #include <asm/imx-common/boot_mode.h>
 

-#if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
+#if !(defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53))

 #error "CPU_TYPE not defined"
 #endif
 
 #error "CPU_TYPE not defined"
 #endif
 


@@ -39,14 +39,14 @@ void hw_watchdog_reset(void)
 
 u32 get_cpu_rev(void)
 {
 
 u32 get_cpu_rev(void)
 {

-#ifdef CONFIG_MX51
+#ifdef CONFIG_SOC_MX51

        int system_rev = 0x51000;
 #else
        int system_rev = 0x53000;
 #endif
        int reg = __raw_readl(ROM_SI_REV);
 
        int system_rev = 0x51000;
 #else
        int system_rev = 0x53000;
 #endif
        int reg = __raw_readl(ROM_SI_REV);
 

-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)

        switch (reg) {
        case 0x02:
                system_rev |= CHIP_REV_1_1;
        switch (reg) {
        case 0x02:
                system_rev |= CHIP_REV_1_1;


@@ -106,7 +106,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
 
 #endif
 
 
 #endif
 

-#ifdef CONFIG_MX53
+#ifdef CONFIG_SOC_MX53

 void boot_mode_apply(unsigned cfg_val)
 {
        writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);
 void boot_mode_apply(unsigned cfg_val)
 {
        writel(cfg_val, &((struct srtc_regs *)SRTC_BASE_ADDR)->lpgr);

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index dfd5e08a0276e3dbf7f225926dd37cc889889d02..7f67941e179552bfde324c38a8ef38e308a1cba7 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -172,7 +172,7 @@ void enable_usboh3_clk(unsigned char enable)
 
 }
 
 
 }
 

-#if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
+#if defined(CONFIG_FEC_MXC) && !defined(CONFIG_SOC_MX6SX)

 void enable_enet_clk(unsigned char enable)
 {
        u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
 void enable_enet_clk(unsigned char enable)
 {
        u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;


@@ -437,7 +437,7 @@ static u32 get_ipg_per_clk(void)
        u32 reg, perclk_podf;
 
        reg = __raw_readl(&imx_ccm->cscmr1);
        u32 reg, perclk_podf;
 
        reg = __raw_readl(&imx_ccm->cscmr1);

-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))

        if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
                return MXC_HCLK; /* OSC 24Mhz */
 #endif
        if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
                return MXC_HCLK; /* OSC 24Mhz */
 #endif


@@ -451,7 +451,7 @@ static u32 get_uart_clk(void)
        u32 reg, uart_podf;
        u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
        reg = __raw_readl(&imx_ccm->cscdr1);
        u32 reg, uart_podf;
        u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
        reg = __raw_readl(&imx_ccm->cscdr1);

-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))

        if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
                freq = MXC_HCLK;
 #endif
        if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
                freq = MXC_HCLK;
 #endif


@@ -617,7 +617,7 @@ static int set_nfc_clk(u32 ref, u32 freq_khz)
        return 0;
 }
 
        return 0;
 }
 

-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))

 static u32 get_mmdc_ch0_clk(void)
 {
        u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
 static u32 get_mmdc_ch0_clk(void)
 {
        u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);


@@ -657,7 +657,7 @@ static u32 get_mmdc_ch0_clk(void)
 }
 #endif
 
 }
 #endif
 

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 /* qspi_num can be from 0 - 1 */
 void enable_qspi_clk(int qspi_num)
 {
 /* qspi_num can be from 0 - 1 */
 void enable_qspi_clk(int qspi_num)
 {


@@ -740,7 +740,7 @@ int enable_fec_anatop_clock(enum enet_freq freq)
        reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
        writel(reg, &anatop->pll_enet);
 
        reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
        writel(reg, &anatop->pll_enet);
 

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

        /*
         * Set enet ahb clock to 200MHz
         * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
        /*
         * Set enet ahb clock to 200MHz
         * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB


@@ -841,7 +841,7 @@ static int enable_enet_pll(uint32_t en)
        return 0;
 }
 
        return 0;
 }
 

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 static void ungate_sata_clock(void)
 {
        struct mxc_ccm_reg *const imx_ccm =
 static void ungate_sata_clock(void)
 {
        struct mxc_ccm_reg *const imx_ccm =


@@ -861,7 +861,7 @@ static void ungate_pcie_clock(void)
        setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
 }
 
        setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
 }
 

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 int enable_sata_clock(void)
 {
        ungate_sata_clock();
 int enable_sata_clock(void)
 {
        ungate_sata_clock();


@@ -916,7 +916,7 @@ int enable_pcie_clock(void)
        clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
 
        /* Party time! Ungate the clock to the PCIe. */
        clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
 
        /* Party time! Ungate the clock to the PCIe. */

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

        ungate_sata_clock();
 #endif
        ungate_pcie_clock();
        ungate_sata_clock();
 #endif
        ungate_pcie_clock();


@@ -1379,7 +1379,7 @@ int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
        return CMD_RET_FAILURE;
 }
 
        return CMD_RET_FAILURE;
 }
 

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 void enable_ipu_clock(void)
 {
        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 void enable_ipu_clock(void)
 {
        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c
index 7a9b03a68f227a2a86a60c57d6f8ee42eabf0278..8661afac695f7218924ad0971732bb27aa3d8146 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/ddr.c
+++ b/arch/arm/cpu/armv7/mx6/ddr.c
@@ -12,7 +12,7 @@
 #include <asm/io.h>
 #include <asm/types.h>
 
 #include <asm/io.h>
 #include <asm/types.h>
 

-#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+#if defined(CONFIG_SOC_MX6QDL) || defined(CONFIG_SOC_MX6Q) || defined(CONFIG_SOC_MX6D)

 /* Configure MX6DQ mmdc iomux */
 void mx6dq_dram_iocfg(unsigned width,
                      const struct mx6dq_iomux_ddr_regs *ddr,
 /* Configure MX6DQ mmdc iomux */
 void mx6dq_dram_iocfg(unsigned width,
                      const struct mx6dq_iomux_ddr_regs *ddr,


@@ -90,7 +90,7 @@ void mx6dq_dram_iocfg(unsigned width,
 }
 #endif
 
 }
 #endif
 

-#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#if defined(CONFIG_SOC_MX6QDL) || defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)

 /* Configure MX6SDL mmdc iomux */
 void mx6sdl_dram_iocfg(unsigned width,
                       const struct mx6sdl_iomux_ddr_regs *ddr,
 /* Configure MX6SDL mmdc iomux */
 void mx6sdl_dram_iocfg(unsigned width,
                       const struct mx6sdl_iomux_ddr_regs *ddr,

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index 5cf472d24f3393ea8aa8e0bdfb17f27230983529..223cdc207f7e3b5ea7fb6c388935d92524f2456e 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -128,13 +128,13 @@ u32 __weak get_board_rev(void)
 void init_aips(void)
 {
        struct aipstz_regs *aips1, *aips2;
 void init_aips(void)
 {
        struct aipstz_regs *aips1, *aips2;

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

        struct aipstz_regs *aips3;
 #endif
 
        aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
        aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;
        struct aipstz_regs *aips3;
 #endif
 
        aips1 = (struct aipstz_regs *)AIPS1_BASE_ADDR;
        aips2 = (struct aipstz_regs *)AIPS2_BASE_ADDR;

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

        aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
 #endif
 
        aips3 = (struct aipstz_regs *)AIPS3_BASE_ADDR;
 #endif
 


@@ -163,7 +163,7 @@ void init_aips(void)
        writel(0x00000000, &aips2->opacr3);
        writel(0x00000000, &aips2->opacr4);
 
        writel(0x00000000, &aips2->opacr3);
        writel(0x00000000, &aips2->opacr4);
 

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

        /*
         * Set all MPROTx to be non-bufferable, trusted for R/W,
         * not forced to user-mode.
        /*
         * Set all MPROTx to be non-bufferable, trusted for R/W,
         * not forced to user-mode.


@@ -452,7 +452,7 @@ static void clear_mmdc_ch_mask(void)
        writel(0, &mxc_ccm->ccdr);
 }
 
        writel(0, &mxc_ccm->ccdr);
 }
 

-#ifdef CONFIG_MX6SL
+#ifdef CONFIG_SOC_MX6SL

 static void set_preclk_from_osc(void)
 {
        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 static void set_preclk_from_osc(void)
 {
        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;


@@ -480,7 +480,7 @@ int arch_cpu_init(void)
                set_ahb_rate(132000000);
 
                /* Set perclk to source from OSC 24MHz */
                set_ahb_rate(132000000);
 
                /* Set perclk to source from OSC 24MHz */

-#if defined(CONFIG_MX6SL)
+#if defined(CONFIG_SOC_MX6SL)

        set_preclk_from_osc();
 #endif
 
        set_preclk_from_osc();
 #endif
 


@@ -677,7 +677,7 @@ void v7_outer_cache_enable(void)
        struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
        unsigned int val;
 
        struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
        unsigned int val;
 

-#if defined CONFIG_MX6SL
+#if defined CONFIG_SOC_MX6SL

        struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
        val = readl(&iomux->gpr[11]);
        if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
        struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
        val = readl(&iomux->gpr[11]);
        if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {


@@ -708,7 +708,7 @@ void v7_outer_cache_enable(void)
         * double linefill feature. This is the default behavior.
         */
 
         * double linefill feature. This is the default behavior.
         */
 

-#ifndef CONFIG_MX6Q
+#ifndef CONFIG_SOC_MX6Q

        val |= 0x40800000;
 #endif
        writel(val, &pl310->pl310_prefetch_ctrl);
        val |= 0x40800000;
 #endif
        writel(val, &pl310->pl310_prefetch_ctrl);

diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index 28ccd29594ed77976f45837039e40618e527a94f..b915a0014f650fdb85efd81d9e62b38d2285a74f 100644 (file)
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -53,8 +53,8 @@ char *get_reset_cause(void)
        }
 }
 
        }
 }
 

-#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
-#if defined(CONFIG_MX53)
+#if defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)
+#if defined(CONFIG_SOC_MX53)

 #define MEMCTL_BASE    ESDCTL_BASE_ADDR
 #else
 #define MEMCTL_BASE    MMDC_P0_BASE_ADDR
 #define MEMCTL_BASE    ESDCTL_BASE_ADDR
 #else
 #define MEMCTL_BASE    MMDC_P0_BASE_ADDR


@@ -136,7 +136,7 @@ int print_cpuinfo(void)
 {
        u32 cpurev;
 
 {
        u32 cpurev;
 

-#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
+#if defined(CONFIG_SOC_MX6) && defined(CONFIG_IMX6_THERMAL)

        struct udevice *thermal_dev;
        int cpu_tmp, ret;
 #endif
        struct udevice *thermal_dev;
        int cpu_tmp, ret;
 #endif


@@ -149,7 +149,7 @@ int print_cpuinfo(void)
                (cpurev & 0x0000F) >> 0,
                mxc_get_clock(MXC_ARM_CLK) / 1000000);
 
                (cpurev & 0x0000F) >> 0,
                mxc_get_clock(MXC_ARM_CLK) / 1000000);
 

-#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
+#if defined(CONFIG_SOC_MX6) && defined(CONFIG_IMX6_THERMAL)

        ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
        if (!ret) {
                ret = thermal_get_temp(thermal_dev, &cpu_tmp);
        ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
        if (!ret) {
                ret = thermal_get_temp(thermal_dev, &cpu_tmp);


@@ -206,7 +206,7 @@ void arch_preboot_os(void)
 {
 #if defined(CONFIG_CMD_SATA)
        sata_stop();
 {
 #if defined(CONFIG_CMD_SATA)
        sata_stop();

-#if defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_MX6)

        disable_sata_clock();
 #endif
 #endif
        disable_sata_clock();
 #endif
 #endif

diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c
index b96104c0cc9f6116aab84dd9cf35d337ac9a6fba..9ec1a3cf9e3b1b337fc408deb861c9d585933ffa 100644 (file)
--- a/arch/arm/imx-common/iomux-v3.c
+++ b/arch/arm/imx-common/iomux-v3.c
@@ -11,7 +11,7 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>

-#if !defined(CONFIG_MX25) && !defined(CONFIG_VF610)
+#if !defined(CONFIG_SOC_MX25) && !defined(CONFIG_SOC_VF610)

 #include <asm/arch/sys_proto.h>
 #endif
 #include <asm/imx-common/iomux-v3.h>
 #include <asm/arch/sys_proto.h>
 #endif
 #include <asm/imx-common/iomux-v3.h>


@@ -33,7 +33,7 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
                (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
        u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
 
                (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
        u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
 

-#if defined CONFIG_MX6SL
+#if defined CONFIG_SOC_MX6SL

        /* Check whether LVE bit needs to be set */
        if (pad_ctrl & PAD_CTL_LVE) {
                pad_ctrl &= ~PAD_CTL_LVE;
        /* Check whether LVE bit needs to be set */
        if (pad_ctrl & PAD_CTL_LVE) {
                pad_ctrl &= ~PAD_CTL_LVE;


@@ -70,7 +70,7 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
        int stride;
        int i;
 
        int stride;
        int i;
 

-#if defined(CONFIG_MX6QDL)
+#if defined(CONFIG_SOC_MX6QDL)

        stride = 2;
        if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
                p += 1;
        stride = 2;
        if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
                p += 1;

diff --git a/arch/arm/imx-common/spl.c b/arch/arm/imx-common/spl.c
index ac6e40e83b807bfc29a7979bc15962b982accc87..1073b3503f35bed2aad1787739ecaadcd05be289 100644 (file)
--- a/arch/arm/imx-common/spl.c
+++ b/arch/arm/imx-common/spl.c
@@ -13,7 +13,7 @@
 #include <asm/spl.h>
 #include <spl.h>
 
 #include <asm/spl.h>
 #include <spl.h>
 

-#if defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_MX6)

 /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 register */
 u32 spl_boot_device(void)
 {
 /* determine boot device from SRC_SBMR1 (BOOT_CFG[4:1]) or SRC_GPR9 register */
 u32 spl_boot_device(void)
 {

diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c
index 1da931ab0f4a761d5e6d39eaa27910876fc7db9e..9a02716b75ecb2e83bac7a616ea2e441c55b8496 100644 (file)
--- a/arch/arm/imx-common/timer.c
+++ b/arch/arm/imx-common/timer.c
@@ -42,7 +42,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static inline int gpt_has_clk_source_osc(void)
 {
 
 static inline int gpt_has_clk_source_osc(void)
 {

-#if defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_MX6)

        if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
             (is_soc_rev(CHIP_REV_1_0) > 0)) || is_cpu_type(MXC_CPU_MX6DL) ||
              is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX))
        if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) &&
             (is_soc_rev(CHIP_REV_1_0) > 0)) || is_cpu_type(MXC_CPU_MX6DL) ||
              is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX))

diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 791551841c71ac81b7e203ce0da9af3992102a47..c58abdb38f099996c93fd21e6b2870e39e959908 100644 (file)
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -90,7 +90,7 @@
 
 #define CONFIG_SYS_FSL_SRDS_1
 
 
 #define CONFIG_SYS_FSL_SRDS_1
 

-#ifdef CONFIG_LS102XA
+#ifdef CONFIG_SOC_LS102XA

 #define CONFIG_MAX_CPUS                                2
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT          8
 #define CONFIG_NUM_DDR_CONTROLLERS             1
 #define CONFIG_MAX_CPUS                                2
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT          8
 #define CONFIG_NUM_DDR_CONTROLLERS             1

diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h
index f4582ee833a82b4884eaba639f171e8a7975bd6c..18b18b0dc7409603d79e1d570583597e9b4011b9 100644 (file)
--- a/arch/arm/include/asm/arch-mx5/clock.h
+++ b/arch/arm/include/asm/arch-mx5/clock.h
@@ -109,7 +109,7 @@ void ipu_clk_enable(void);
 void ipu_clk_disable(void);
 void ipu_di_clk_enable(int di);
 void ipu_di_clk_disable(int di);
 void ipu_clk_disable(void);
 void ipu_di_clk_enable(int di);
 void ipu_di_clk_disable(int di);

-#ifdef CONFIG_MX53
+#ifdef CONFIG_SOC_MX53

 void ldb_clk_enable(int ldb);
 void ldb_clk_disable(int ldb);
 #else
 void ldb_clk_enable(int ldb);
 void ldb_clk_disable(int ldb);
 #else


@@ -119,6 +119,6 @@ static inline void ldb_clk_enable(int ldb)
 static inline void ldb_clk_disable(int ldb)
 {
 }
 static inline void ldb_clk_disable(int ldb)
 {
 }

-#endif /* CONFIG_MX53 */
+#endif /* CONFIG_SOC_MX53 */

 
 #endif /* __ASM_ARCH_CLOCK_H */
 
 #endif /* __ASM_ARCH_CLOCK_H */

diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h
index fee81e490089fda5d9770d5f5dbb798bf144a62c..f62bf224f2c8803c6b017ff928aaa97440da7c26 100644 (file)
--- a/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -60,7 +60,7 @@ struct mxc_ccm_reg {
        u32 CCGR4;
        u32 CCGR5;
        u32 CCGR6;      /* 0x0080 */
        u32 CCGR4;
        u32 CCGR5;
        u32 CCGR6;      /* 0x0080 */

-#ifdef CONFIG_MX53
+#ifdef CONFIG_SOC_MX53

        u32 CCGR7;      /* 0x0084 */
 #endif
        u32 cmeor;
        u32 CCGR7;      /* 0x0084 */
 #endif
        u32 cmeor;


@@ -68,12 +68,12 @@ struct mxc_ccm_reg {
 
 /* Define the bits in register CCR */
 #define MXC_CCM_CCR_COSC_EN                    (0x1 << 12)
 
 /* Define the bits in register CCR */
 #define MXC_CCM_CCR_COSC_EN                    (0x1 << 12)

-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)

 #define MXC_CCM_CCR_FPM_MULT                   (0x1 << 11)
 #endif
 #define MXC_CCM_CCR_CAMP2_EN                   (0x1 << 10)
 #define MXC_CCM_CCR_CAMP1_EN                   (0x1 << 9)
 #define MXC_CCM_CCR_FPM_MULT                   (0x1 << 11)
 #endif
 #define MXC_CCM_CCR_CAMP2_EN                   (0x1 << 10)
 #define MXC_CCM_CCR_CAMP1_EN                   (0x1 << 9)

-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)

 #define MXC_CCM_CCR_FPM_EN                     (0x1 << 8)
 #endif
 #define MXC_CCM_CCR_OSCNT_OFFSET               0
 #define MXC_CCM_CCR_FPM_EN                     (0x1 << 8)
 #endif
 #define MXC_CCM_CCR_OSCNT_OFFSET               0


@@ -82,9 +82,9 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCR_OSCNT_RD(r)                        ((r) & 0xFF)
 
 /* Define the bits in register CCSR */
 #define MXC_CCM_CCR_OSCNT_RD(r)                        ((r) & 0xFF)
 
 /* Define the bits in register CCSR */

-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)

 #define MXC_CCM_CCSR_LP_APM                    (0x1 << 9)
 #define MXC_CCM_CCSR_LP_APM                    (0x1 << 9)

-#elif defined(CONFIG_MX53)
+#elif defined(CONFIG_SOC_MX53)

 #define MXC_CCM_CCSR_LP_APM                    (0x1 << 10)
 #define MXC_CCM_CCSR_PLL4_SW_CLK_SEL           (0x1 << 9)
 #endif
 #define MXC_CCM_CCSR_LP_APM                    (0x1 << 10)
 #define MXC_CCM_CCSR_PLL4_SW_CLK_SEL           (0x1 << 9)
 #endif


@@ -369,12 +369,12 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR1_I2C1(v)                          (((v) & 0x3) << 18)
 #define MXC_CCM_CCGR1_I2C2_OFFSET                      20
 #define MXC_CCM_CCGR1_I2C2(v)                          (((v) & 0x3) << 20)
 #define MXC_CCM_CCGR1_I2C1(v)                          (((v) & 0x3) << 18)
 #define MXC_CCM_CCGR1_I2C2_OFFSET                      20
 #define MXC_CCM_CCGR1_I2C2(v)                          (((v) & 0x3) << 20)

-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)

 #define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET                 22
 #define MXC_CCM_CCGR1_HSI2C_IPG(v)                     (((v) & 0x3) << 22)
 #define MXC_CCM_CCGR1_HSI2C_SERIAL_OFFSET              24
 #define MXC_CCM_CCGR1_HSI2C_SERIAL(v)                  (((v) & 0x3) << 24)
 #define MXC_CCM_CCGR1_HSI2C_IPG_OFFSET                 22
 #define MXC_CCM_CCGR1_HSI2C_IPG(v)                     (((v) & 0x3) << 22)
 #define MXC_CCM_CCGR1_HSI2C_SERIAL_OFFSET              24
 #define MXC_CCM_CCGR1_HSI2C_SERIAL(v)                  (((v) & 0x3) << 24)

-#elif defined(CONFIG_MX53)
+#elif defined(CONFIG_SOC_MX53)

 #define MXC_CCM_CCGR1_I2C3_OFFSET                      22
 #define MXC_CCM_CCGR1_I2C3(v)                          (((v) & 0x3) << 22)
 #endif
 #define MXC_CCM_CCGR1_I2C3_OFFSET                      22
 #define MXC_CCM_CCGR1_I2C3(v)                          (((v) & 0x3) << 22)
 #endif


@@ -385,7 +385,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR1_SCC_OFFSET                       30
 #define MXC_CCM_CCGR1_SCC(v)                           (((v) & 0x3) << 30)
 
 #define MXC_CCM_CCGR1_SCC_OFFSET                       30
 #define MXC_CCM_CCGR1_SCC(v)                           (((v) & 0x3) << 30)
 

-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)

 #define MXC_CCM_CCGR2_USB_PHY_OFFSET                   0
 #define MXC_CCM_CCGR2_USB_PHY(v)                       (((v) & 0x3) << 0)
 #endif
 #define MXC_CCM_CCGR2_USB_PHY_OFFSET                   0
 #define MXC_CCM_CCGR2_USB_PHY(v)                       (((v) & 0x3) << 0)
 #endif


@@ -455,12 +455,12 @@ struct mxc_ccm_reg {
 
 #define MXC_CCM_CCGR4_PATA_OFFSET                      0
 #define MXC_CCM_CCGR4_PATA(v)                          (((v) & 0x3) << 0)
 
 #define MXC_CCM_CCGR4_PATA_OFFSET                      0
 #define MXC_CCM_CCGR4_PATA(v)                          (((v) & 0x3) << 0)

-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)

 #define MXC_CCM_CCGR4_SIM_IPG_OFFSET                   2
 #define MXC_CCM_CCGR4_SIM_IPG(v)                       (((v) & 0x3) << 2)
 #define MXC_CCM_CCGR4_SIM_SERIAL_OFFSET                        4
 #define MXC_CCM_CCGR4_SIM_SERIAL(v)                    (((v) & 0x3) << 4)
 #define MXC_CCM_CCGR4_SIM_IPG_OFFSET                   2
 #define MXC_CCM_CCGR4_SIM_IPG(v)                       (((v) & 0x3) << 2)
 #define MXC_CCM_CCGR4_SIM_SERIAL_OFFSET                        4
 #define MXC_CCM_CCGR4_SIM_SERIAL(v)                    (((v) & 0x3) << 4)

-#elif defined(CONFIG_MX53)
+#elif defined(CONFIG_SOC_MX53)

 #define MXC_CCM_CCGR4_SATA_OFFSET                      2
 #define MXC_CCM_CCGR4_SATA(v)                          (((v) & 0x3) << 2)
 #define MXC_CCM_CCGR4_CAN2_IPG_OFFSET                  6
 #define MXC_CCM_CCGR4_SATA_OFFSET                      2
 #define MXC_CCM_CCGR4_SATA(v)                          (((v) & 0x3) << 2)
 #define MXC_CCM_CCGR4_CAN2_IPG_OFFSET                  6


@@ -503,10 +503,10 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR5_VPU_REF(v)                       (((v) & 0x3) << 8)
 #define MXC_CCM_CCGR5_IPU_OFFSET                       10
 #define MXC_CCM_CCGR5_IPU(v)                           (((v) & 0x3) << 10)
 #define MXC_CCM_CCGR5_VPU_REF(v)                       (((v) & 0x3) << 8)
 #define MXC_CCM_CCGR5_IPU_OFFSET                       10
 #define MXC_CCM_CCGR5_IPU(v)                           (((v) & 0x3) << 10)

-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)

 #define MXC_CCM_CCGR5_IPUMUX12_OFFSET                  12
 #define MXC_CCM_CCGR5_IPUMUX12(v)                      (((v) & 0x3) << 12)
 #define MXC_CCM_CCGR5_IPUMUX12_OFFSET                  12
 #define MXC_CCM_CCGR5_IPUMUX12(v)                      (((v) & 0x3) << 12)

-#elif defined(CONFIG_MX53)
+#elif defined(CONFIG_SOC_MX53)

 #define MXC_CCM_CCGR5_IPUMUX1_OFFSET                   12
 #define MXC_CCM_CCGR5_IPUMUX1(v)                       (((v) & 0x3) << 12)
 #endif
 #define MXC_CCM_CCGR5_IPUMUX1_OFFSET                   12
 #define MXC_CCM_CCGR5_IPUMUX1(v)                       (((v) & 0x3) << 12)
 #endif


@@ -524,14 +524,14 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR5_GPC_IPG(v)                       (((v) & 0x3) << 24)
 #define MXC_CCM_CCGR5_SPDIF0_OFFSET                    26
 #define MXC_CCM_CCGR5_SPDIF0(v)                                (((v) & 0x3) << 26)
 #define MXC_CCM_CCGR5_GPC_IPG(v)                       (((v) & 0x3) << 24)
 #define MXC_CCM_CCGR5_SPDIF0_OFFSET                    26
 #define MXC_CCM_CCGR5_SPDIF0(v)                                (((v) & 0x3) << 26)

-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)

 #define MXC_CCM_CCGR5_SPDIF1_OFFSET                    28
 #define MXC_CCM_CCGR5_SPDIF1(v)                                (((v) & 0x3) << 28)
 #endif
 #define MXC_CCM_CCGR5_SPDIF_IPG_OFFSET                 30
 #define MXC_CCM_CCGR5_SPDIF_IPG(v)                     (((v) & 0x3) << 30)
 
 #define MXC_CCM_CCGR5_SPDIF1_OFFSET                    28
 #define MXC_CCM_CCGR5_SPDIF1(v)                                (((v) & 0x3) << 28)
 #endif
 #define MXC_CCM_CCGR5_SPDIF_IPG_OFFSET                 30
 #define MXC_CCM_CCGR5_SPDIF_IPG(v)                     (((v) & 0x3) << 30)
 

-#if defined(CONFIG_MX53)
+#if defined(CONFIG_SOC_MX53)

 #define MXC_CCM_CCGR6_IPUMUX2_OFFSET                   0
 #define MXC_CCM_CCGR6_IPUMUX2(v)                       (((v) & 0x3) << 0)
 #define MXC_CCM_CCGR6_OCRAM_OFFSET                     2
 #define MXC_CCM_CCGR6_IPUMUX2_OFFSET                   0
 #define MXC_CCM_CCGR6_IPUMUX2(v)                       (((v) & 0x3) << 0)
 #define MXC_CCM_CCGR6_OCRAM_OFFSET                     2


@@ -539,12 +539,12 @@ struct mxc_ccm_reg {
 #endif
 #define MXC_CCM_CCGR6_CSI_MCLK1_OFFSET                 4
 #define MXC_CCM_CCGR6_CSI_MCLK1(v)                     (((v) & 0x3) << 4)
 #endif
 #define MXC_CCM_CCGR6_CSI_MCLK1_OFFSET                 4
 #define MXC_CCM_CCGR6_CSI_MCLK1(v)                     (((v) & 0x3) << 4)

-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)

 #define MXC_CCM_CCGR6_CSI_MCLK2_OFFSET                 6
 #define MXC_CCM_CCGR6_CSI_MCLK2(v)                     (((v) & 0x3) << 6)
 #define MXC_CCM_CCGR6_EMI_GARB_OFFSET                  8
 #define MXC_CCM_CCGR6_EMI_GARB(v)                      (((v) & 0x3) << 8)
 #define MXC_CCM_CCGR6_CSI_MCLK2_OFFSET                 6
 #define MXC_CCM_CCGR6_CSI_MCLK2(v)                     (((v) & 0x3) << 6)
 #define MXC_CCM_CCGR6_EMI_GARB_OFFSET                  8
 #define MXC_CCM_CCGR6_EMI_GARB(v)                      (((v) & 0x3) << 8)

-#elif defined(CONFIG_MX53)
+#elif defined(CONFIG_SOC_MX53)

 #define MXC_CCM_CCGR6_EMI_INT2_OFFSET                  8
 #define MXC_CCM_CCGR6_EMI_INT2(v)                      (((v) & 0x3) << 8)
 #endif
 #define MXC_CCM_CCGR6_EMI_INT2_OFFSET                  8
 #define MXC_CCM_CCGR6_EMI_INT2(v)                      (((v) & 0x3) << 8)
 #endif


@@ -554,7 +554,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR6_IPU_DI1(v)                       (((v) & 0x3) << 12)
 #define MXC_CCM_CCGR6_GPU2D_OFFSET                     14
 #define MXC_CCM_CCGR6_GPU2D(v)                         (((v) & 0x3) << 14)
 #define MXC_CCM_CCGR6_IPU_DI1(v)                       (((v) & 0x3) << 12)
 #define MXC_CCM_CCGR6_GPU2D_OFFSET                     14
 #define MXC_CCM_CCGR6_GPU2D(v)                         (((v) & 0x3) << 14)

-#if defined(CONFIG_MX53)
+#if defined(CONFIG_SOC_MX53)

 #define MXC_CCM_CCGR6_ESAI_IPG_OFFSET                  16
 #define MXC_CCM_CCGR6_ESAI_IPG(v)                      (((v) & 0x3) << 16)
 #define MXC_CCM_CCGR6_ESAI_ROOT_OFFSET                 18
 #define MXC_CCM_CCGR6_ESAI_IPG_OFFSET                  16
 #define MXC_CCM_CCGR6_ESAI_IPG(v)                      (((v) & 0x3) << 16)
 #define MXC_CCM_CCGR6_ESAI_ROOT_OFFSET                 18

diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index 091055f8f07fb723f9fbb07a3acc802bcd008059..6335c07dafb19937d6521412326f3afcc5ff3f47 100644 (file)
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -9,7 +9,7 @@
 
 #define ARCH_MXC
 
 
 #define ARCH_MXC
 

-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)

 #define IRAM_BASE_ADDR         0x1FFE0000      /* internal ram */
 #define IPU_SOC_BASE_ADDR      0x40000000
 #define SPBA0_BASE_ADDR                0x70000000
 #define IRAM_BASE_ADDR         0x1FFE0000      /* internal ram */
 #define IPU_SOC_BASE_ADDR      0x40000000
 #define SPBA0_BASE_ADDR                0x70000000


@@ -19,7 +19,7 @@
 #define CSD1_BASE_ADDR         0xA0000000
 #define NFC_BASE_ADDR_AXI      0xCFFF0000
 #define CS1_BASE_ADDR          0xB8000000
 #define CSD1_BASE_ADDR         0xA0000000
 #define NFC_BASE_ADDR_AXI      0xCFFF0000
 #define CS1_BASE_ADDR          0xB8000000

-#elif defined(CONFIG_MX53)
+#elif defined(CONFIG_SOC_MX53)

 #define IPU_SOC_BASE_ADDR      0x00000000
 #define SPBA0_BASE_ADDR                0x50000000
 #define AIPS1_BASE_ADDR                0x53F00000
 #define IPU_SOC_BASE_ADDR      0x00000000
 #define SPBA0_BASE_ADDR                0x50000000
 #define AIPS1_BASE_ADDR                0x53F00000


@@ -76,7 +76,7 @@
 #define CCM_BASE_ADDR          (AIPS1_BASE_ADDR + 0x000D4000)
 #define GPC_BASE_ADDR          (AIPS1_BASE_ADDR + 0x000D8000)
 
 #define CCM_BASE_ADDR          (AIPS1_BASE_ADDR + 0x000D4000)
 #define GPC_BASE_ADDR          (AIPS1_BASE_ADDR + 0x000D8000)
 

-#if defined(CONFIG_MX53)
+#if defined(CONFIG_SOC_MX53)

 #define GPIO5_BASE_ADDR                (AIPS1_BASE_ADDR + 0x000DC000)
 #define GPIO6_BASE_ADDR                (AIPS1_BASE_ADDR + 0x000E0000)
 #define GPIO7_BASE_ADDR                (AIPS1_BASE_ADDR + 0x000E4000)
 #define GPIO5_BASE_ADDR                (AIPS1_BASE_ADDR + 0x000DC000)
 #define GPIO6_BASE_ADDR                (AIPS1_BASE_ADDR + 0x000E0000)
 #define GPIO7_BASE_ADDR                (AIPS1_BASE_ADDR + 0x000E4000)


@@ -89,7 +89,7 @@
 #define PLL1_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00080000)
 #define PLL2_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00084000)
 #define PLL3_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00088000)
 #define PLL1_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00080000)
 #define PLL2_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00084000)
 #define PLL3_BASE_ADDR         (AIPS2_BASE_ADDR + 0x00088000)

-#ifdef CONFIG_MX53
+#ifdef CONFIG_SOC_MX53

 #define PLL4_BASE_ADDR         (AIPS2_BASE_ADDR + 0x0008c000)
 #endif
 #define AHBMAX_BASE_ADDR       (AIPS2_BASE_ADDR + 0x00094000)
 #define PLL4_BASE_ADDR         (AIPS2_BASE_ADDR + 0x0008c000)
 #endif
 #define AHBMAX_BASE_ADDR       (AIPS2_BASE_ADDR + 0x00094000)


@@ -122,7 +122,7 @@
 #define VPU_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000F4000)
 #define SAHARA_BASE_ADDR       (AIPS2_BASE_ADDR + 0x000F8000)
 
 #define VPU_BASE_ADDR          (AIPS2_BASE_ADDR + 0x000F4000)
 #define SAHARA_BASE_ADDR       (AIPS2_BASE_ADDR + 0x000F8000)
 

-#if defined(CONFIG_MX53)
+#if defined(CONFIG_SOC_MX53)

 #define UART5_BASE_ADDR                (AIPS2_BASE_ADDR + 0x00090000)
 #endif
 
 #define UART5_BASE_ADDR                (AIPS2_BASE_ADDR + 0x00090000)
 #endif
 


@@ -353,7 +353,7 @@ struct clkctl {
        u32     ccgr4;
        u32     ccgr5;
        u32     ccgr6;
        u32     ccgr4;
        u32     ccgr5;
        u32     ccgr6;

-#if defined(CONFIG_MX53)
+#if defined(CONFIG_SOC_MX53)

        u32     ccgr7;
 #endif
        u32     cmeor;
        u32     ccgr7;
 #endif
        u32     cmeor;


@@ -417,7 +417,7 @@ struct weim {
        u32     ear;
 };
 
        u32     ear;
 };
 

-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)

 struct iomuxc {
        u32     gpr[2];
        u32     omux0;
 struct iomuxc {
        u32     gpr[2];
        u32     omux0;


@@ -426,7 +426,7 @@ struct iomuxc {
        u32     omux3;
        u32     omux4;
 };
        u32     omux3;
        u32     omux4;
 };

-#elif defined(CONFIG_MX53)
+#elif defined(CONFIG_SOC_MX53)

 struct iomuxc {
        u32     gpr[3];
        u32     omux0;
 struct iomuxc {
        u32     gpr[3];
        u32     omux0;


@@ -497,9 +497,9 @@ struct iim_regs {
        struct fuse_bank {
                u32     fuse_regs[0x20];
                u32     fuse_rsvd[0xe0];
        struct fuse_bank {
                u32     fuse_regs[0x20];
                u32     fuse_rsvd[0xe0];

-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)

        } bank[4];
        } bank[4];

-#elif defined(CONFIG_MX53)
+#elif defined(CONFIG_SOC_MX53)

        } bank[5];
 #endif
 };
        } bank[5];
 #endif
 };


@@ -508,9 +508,9 @@ struct fuse_bank0_regs {
        u32     fuse0_7[8];
        u32     uid[8];
        u32     fuse16_23[8];
        u32     fuse0_7[8];
        u32     uid[8];
        u32     fuse16_23[8];

-#if defined(CONFIG_MX51)
+#if defined(CONFIG_SOC_MX51)

        u32     imei[8];
        u32     imei[8];

-#elif defined(CONFIG_MX53)
+#elif defined(CONFIG_SOC_MX53)

        u32     gp[8];
 #endif
 };
        u32     gp[8];
 #endif
 };


@@ -521,7 +521,7 @@ struct fuse_bank1_regs {
        u32     fuse15_31[0x11];
 };
 
        u32     fuse15_31[0x11];
 };
 

-#if defined(CONFIG_MX53)
+#if defined(CONFIG_SOC_MX53)

 struct fuse_bank4_regs {
        u32     fuse0_4[5];
        u32     gp[3];
 struct fuse_bank4_regs {
        u32     fuse0_4[5];
        u32     gp[3];

diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index d882d3b008c9c782699aca531fe42b3dacaa068d..261a7b38d0c3a4c52d381833a33f64f4b1775322 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -65,7 +65,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCR_WB_COUNT_MASK                      (0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET)
 #define MXC_CCM_CCR_WB_COUNT_OFFSET                    (1 << 16)
 #define MXC_CCM_CCR_COSC_EN                            (1 << 12)
 #define MXC_CCM_CCR_WB_COUNT_MASK                      (0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET)
 #define MXC_CCM_CCR_WB_COUNT_OFFSET                    (1 << 16)
 #define MXC_CCM_CCR_COSC_EN                            (1 << 12)

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define MXC_CCM_CCR_OSCNT_MASK                         0x7F
 #else
 #define MXC_CCM_CCR_OSCNT_MASK                         0xFF
 #define MXC_CCM_CCR_OSCNT_MASK                         0x7F
 #else
 #define MXC_CCM_CCR_OSCNT_MASK                         0xFF


@@ -102,7 +102,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET          27
 #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL                 (1 << 26)
 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL                   (1 << 25)
 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET          27
 #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL                 (1 << 26)
 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL                   (1 << 25)

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK               (0x7 << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET)
 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET             19
 #endif
 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK               (0x7 << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET)
 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET             19
 #endif


@@ -131,7 +131,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL             (1 << 20)
 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK          (0x3 << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET)
 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET                18
 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL             (1 << 20)
 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK          (0x3 << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET)
 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET                18

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK               (0x3 << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET)
 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET             16
 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK             (0x3 << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET)
 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK               (0x3 << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET)
 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET             16
 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK             (0x3 << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET)


@@ -139,7 +139,7 @@ struct mxc_ccm_reg {
 #endif
 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK             (0x3 << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET)
 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET           12
 #endif
 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK             (0x3 << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET)
 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET           12

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL                   (1 << 11)
 #endif
 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL                 (1 << 10)
 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL                   (1 << 11)
 #endif
 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL                 (1 << 10)


@@ -147,7 +147,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET      8
 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK          (0x3 << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET)
 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET                4
 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET      8
 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK          (0x3 << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET)
 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET                4

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL                        (1 << 1)
 #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL                        (1 << 0)
 #endif
 #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL                        (1 << 1)
 #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL                        (1 << 0)
 #endif


@@ -155,7 +155,7 @@ struct mxc_ccm_reg {
 /* Define the bits in register CSCMR1 */
 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK              (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET)
 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET            29
 /* Define the bits in register CSCMR1 */
 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK              (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET)
 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET            29

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK                 (0x7 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET)
 #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET               26
 #else
 #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK                 (0x7 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET)
 #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET               26
 #else


@@ -177,11 +177,11 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET             12
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK               (0x3 << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET             10
 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET             12
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK               (0x3 << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET             10

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK              (0x7 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET            7
 #endif
 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK              (0x7 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET            7
 #endif

-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))

 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK                        (1 << MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET              6
 #endif
 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK                        (1 << MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET              6
 #endif


@@ -189,7 +189,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK                        (0x3F << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET)
 
 /* Define the bits in register CSCMR2 */
 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK                        (0x3F << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET)
 
 /* Define the bits in register CSCMR2 */

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK                        (0x7 << MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET              21
 #endif
 #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK                        (0x7 << MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET              21
 #endif


@@ -197,7 +197,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET             19
 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV                 (1 << 11)
 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV                 (1 << 10)
 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET             19
 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV                 (1 << 11)
 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV                 (1 << 10)

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK                        (0x3 << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET              8
 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK               (0x3F << MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET)
 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK                        (0x3 << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET)
 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET              8
 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK               (0x3F << MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET)


@@ -208,7 +208,7 @@ struct mxc_ccm_reg {
 #endif
 
 /* Define the bits in register CSCDR1 */
 #endif
 
 /* Define the bits in register CSCDR1 */

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK               (0x7 << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET)
 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET             25
 #endif
 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK               (0x7 << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET)
 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET             25
 #endif


@@ -220,18 +220,18 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET              16
 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK                        (0x7 << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET)
 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET              11
 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET              16
 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK                        (0x7 << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET)
 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET              11

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET          8
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK            (0x7 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET)
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET          6
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK            (0x3 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET)
 #endif
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET          8
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK            (0x7 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET)
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET          6
 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK            (0x3 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET)
 #endif

-#ifdef CONFIG_MX6SL
+#ifdef CONFIG_SOC_MX6SL

 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK              (0x1F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
 #define MXC_CCM_CSCDR1_UART_CLK_SEL                    (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET)
 #else
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK              (0x3F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK              (0x1F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)
 #define MXC_CCM_CSCDR1_UART_CLK_SEL                    (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET)
 #else
 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK              (0x3F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET)

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define MXC_CCM_CSCDR1_UART_CLK_SEL                    (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET)
 #endif
 #endif
 #define MXC_CCM_CSCDR1_UART_CLK_SEL                    (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET)
 #endif
 #endif


@@ -253,7 +253,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET            0
 
 /* Define the bits in register CS2CDR */
 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET            0
 
 /* Define the bits in register CS2CDR */

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK             (0x3F << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET           21
 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v)               (((v) & 0x3f) << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK             (0x3F << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)
 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET           21
 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v)               (((v) & 0x3f) << MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET)


@@ -284,7 +284,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET            0
 
 /* Define the bits in register CDCDR */
 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET            0
 
 /* Define the bits in register CDCDR */

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK                 (0x7 << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET)
 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET               29
 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_MASK              (1 << MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET)
 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK                 (0x7 << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET)
 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET               29
 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL_MASK              (1 << MXC_CCM_CDCDR_HSI_TX_CLK_SEL_OFFSET)


@@ -304,7 +304,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET            7
 
 /* Define the bits in register CHSCCDR */
 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET            7
 
 /* Define the bits in register CHSCCDR */

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK          (0x7 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET)
 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET                15
 #define MXC_CCM_CHSCCDR_ENET_PODF_MASK                 (0x7 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET)
 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK          (0x7 << MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET)
 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET                15
 #define MXC_CCM_CHSCCDR_ENET_PODF_MASK                 (0x7 << MXC_CCM_CHSCCDR_ENET_PODF_OFFSET)


@@ -363,7 +363,7 @@ struct mxc_ccm_reg {
 /* Define the bits in register CDHIPR */
 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY                   (1 << 16)
 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY             (1 << 5)
 /* Define the bits in register CDHIPR */
 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY                   (1 << 16)
 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY             (1 << 5)

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY              (1 << 4)
 #endif
 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY            (1 << 3)
 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY              (1 << 4)
 #endif
 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY            (1 << 3)


@@ -374,14 +374,14 @@ struct mxc_ccm_reg {
 /* Define the bits in register CLPCR */
 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE                   (1 << 27)
 #define MXC_CCM_CLPCR_MASK_SCU_IDLE                    (1 << 26)
 /* Define the bits in register CLPCR */
 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE                   (1 << 27)
 #define MXC_CCM_CLPCR_MASK_SCU_IDLE                    (1 << 26)

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 #define MXC_CCM_CLPCR_MASK_CORE3_WFI                   (1 << 25)
 #define MXC_CCM_CLPCR_MASK_CORE2_WFI                   (1 << 24)
 #define MXC_CCM_CLPCR_MASK_CORE1_WFI                   (1 << 23)
 #endif
 #define MXC_CCM_CLPCR_MASK_CORE0_WFI                   (1 << 22)
 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS              (1 << 21)
 #define MXC_CCM_CLPCR_MASK_CORE3_WFI                   (1 << 25)
 #define MXC_CCM_CLPCR_MASK_CORE2_WFI                   (1 << 24)
 #define MXC_CCM_CLPCR_MASK_CORE1_WFI                   (1 << 23)
 #endif
 #define MXC_CCM_CLPCR_MASK_CORE0_WFI                   (1 << 22)
 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS              (1 << 21)

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS              (1 << 19)
 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM                   (1 << 17)
 #endif
 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS              (1 << 19)
 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM                   (1 << 17)
 #endif


@@ -393,7 +393,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CLPCR_DIS_REF_OSC                      (1 << 7)
 #define MXC_CCM_CLPCR_SBYOS                            (1 << 6)
 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM               (1 << 5)
 #define MXC_CCM_CLPCR_DIS_REF_OSC                      (1 << 7)
 #define MXC_CCM_CLPCR_SBYOS                            (1 << 6)
 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM               (1 << 5)

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK                        (0x3 << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET)
 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET              3
 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY          (1 << 2)
 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK                        (0x3 << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET)
 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET              3
 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY          (1 << 2)


@@ -403,7 +403,7 @@ struct mxc_ccm_reg {
 
 /* Define the bits in register CISR */
 #define MXC_CCM_CISR_ARM_PODF_LOADED                   (1 << 26)
 
 /* Define the bits in register CISR */
 #define MXC_CCM_CISR_ARM_PODF_LOADED                   (1 << 26)

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED              (1 << 23)
 #endif
 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED             (1 << 22)
 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED              (1 << 23)
 #endif
 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED             (1 << 22)


@@ -416,7 +416,7 @@ struct mxc_ccm_reg {
 
 /* Define the bits in register CIMR */
 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED              (1 << 26)
 
 /* Define the bits in register CIMR */
 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED              (1 << 26)

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED         (1 << 23)
 #endif
 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED                (1 << 22)
 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED         (1 << 23)
 #endif
 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED                (1 << 22)


@@ -477,7 +477,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR0_DCIC1_MASK                       (3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
 #define MXC_CCM_CCGR0_DCIC2_OFFSET                     26
 #define MXC_CCM_CCGR0_DCIC2_MASK                       (3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
 #define MXC_CCM_CCGR0_DCIC1_MASK                       (3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
 #define MXC_CCM_CCGR0_DCIC2_OFFSET                     26
 #define MXC_CCM_CCGR0_DCIC2_MASK                       (3 << MXC_CCM_CCGR0_DCIC2_OFFSET)

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET                  30
 #define MXC_CCM_CCGR0_AIPS_TZ3_MASK                    (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET)
 #else
 #define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET                  30
 #define MXC_CCM_CCGR0_AIPS_TZ3_MASK                    (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET)
 #else


@@ -495,7 +495,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR1_ECSPI4S_MASK                     (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET                   8
 #define MXC_CCM_CCGR1_ECSPI5S_MASK                     (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
 #define MXC_CCM_CCGR1_ECSPI4S_MASK                     (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET                   8
 #define MXC_CCM_CCGR1_ECSPI5S_MASK                     (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET           10
 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK             (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
 #endif
 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET           10
 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK             (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
 #endif


@@ -505,7 +505,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR1_EPIT2S_MASK                      (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
 #define MXC_CCM_CCGR1_ESAIS_OFFSET                     16
 #define MXC_CCM_CCGR1_ESAIS_MASK                       (3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
 #define MXC_CCM_CCGR1_EPIT2S_MASK                      (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
 #define MXC_CCM_CCGR1_ESAIS_OFFSET                     16
 #define MXC_CCM_CCGR1_ESAIS_MASK                       (3 << MXC_CCM_CCGR1_ESAIS_OFFSET)

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define MXC_CCM_CCGR1_WAKEUP_OFFSET                    18
 #define MXC_CCM_CCGR1_WAKEUP_MASK                      (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET)
 #endif
 #define MXC_CCM_CCGR1_WAKEUP_OFFSET                    18
 #define MXC_CCM_CCGR1_WAKEUP_MASK                      (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET)
 #endif


@@ -513,27 +513,27 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR1_GPT_BUS_MASK                     (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET                        22
 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK                  (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
 #define MXC_CCM_CCGR1_GPT_BUS_MASK                     (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET                        22
 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK                  (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 #define MXC_CCM_CCGR1_GPU2D_OFFSET                     24
 #define MXC_CCM_CCGR1_GPU2D_MASK                       (3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
 #endif
 #define MXC_CCM_CCGR1_GPU3D_OFFSET                     26
 #define MXC_CCM_CCGR1_GPU3D_MASK                       (3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
 #define MXC_CCM_CCGR1_GPU2D_OFFSET                     24
 #define MXC_CCM_CCGR1_GPU2D_MASK                       (3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
 #endif
 #define MXC_CCM_CCGR1_GPU3D_OFFSET                     26
 #define MXC_CCM_CCGR1_GPU3D_MASK                       (3 << MXC_CCM_CCGR1_GPU3D_OFFSET)

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define MXC_CCM_CCGR1_OCRAM_S_OFFSET                   28
 #define MXC_CCM_CCGR1_OCRAM_S_MASK                     (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET)
 #define MXC_CCM_CCGR1_CANFD_OFFSET                     30
 #define MXC_CCM_CCGR1_CANFD_MASK                       (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
 #endif
 
 #define MXC_CCM_CCGR1_OCRAM_S_OFFSET                   28
 #define MXC_CCM_CCGR1_OCRAM_S_MASK                     (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET)
 #define MXC_CCM_CCGR1_CANFD_OFFSET                     30
 #define MXC_CCM_CCGR1_CANFD_MASK                       (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
 #endif
 

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET           0
 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK             (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
 #else
 #define MXC_CCM_CCGR2_CSI_OFFSET                       2
 #define MXC_CCM_CCGR2_CSI_MASK                         (3 << MXC_CCM_CCGR2_CSI_OFFSET)
 #endif
 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET           0
 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK             (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
 #else
 #define MXC_CCM_CCGR2_CSI_OFFSET                       2
 #define MXC_CCM_CCGR2_CSI_MASK                         (3 << MXC_CCM_CCGR2_CSI_OFFSET)
 #endif

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET           4
 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK             (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
 #endif
 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET           4
 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK             (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
 #endif


@@ -555,7 +555,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR2_IPMUX3_MASK                      (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK   (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
 #define MXC_CCM_CCGR2_IPMUX3_MASK                      (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK   (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define MXC_CCM_CCGR2_LCD_OFFSET                       28
 #define MXC_CCM_CCGR2_LCD_MASK                         (3 << MXC_CCM_CCGR2_LCD_OFFSET)
 #define MXC_CCM_CCGR2_PXP_OFFSET                       30
 #define MXC_CCM_CCGR2_LCD_OFFSET                       28
 #define MXC_CCM_CCGR2_LCD_MASK                         (3 << MXC_CCM_CCGR2_LCD_OFFSET)
 #define MXC_CCM_CCGR2_PXP_OFFSET                       30


@@ -567,7 +567,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK  (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
 #endif
 
 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK  (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
 #endif
 

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define MXC_CCM_CCGR3_M4_OFFSET                                        2
 #define MXC_CCM_CCGR3_M4_MASK                                  (3 << MXC_CCM_CCGR3_M4_OFFSET)
 #define MXC_CCM_CCGR3_ENET_OFFSET                              4
 #define MXC_CCM_CCGR3_M4_OFFSET                                        2
 #define MXC_CCM_CCGR3_M4_MASK                                  (3 << MXC_CCM_CCGR3_M4_OFFSET)
 #define MXC_CCM_CCGR3_ENET_OFFSET                              4


@@ -590,7 +590,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK                                (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET                           12
 #define MXC_CCM_CCGR3_LDB_DI0_MASK                             (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK                                (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET                           12
 #define MXC_CCM_CCGR3_LDB_DI0_MASK                             (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define MXC_CCM_CCGR3_QSPI1_OFFSET                             14
 #define MXC_CCM_CCGR3_QSPI1_MASK                               (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
 #else
 #define MXC_CCM_CCGR3_QSPI1_OFFSET                             14
 #define MXC_CCM_CCGR3_QSPI1_MASK                               (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
 #else


@@ -603,7 +603,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR3_MLB_MASK                                 (3 << MXC_CCM_CCGR3_MLB_OFFSET)
 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET       20
 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK         (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
 #define MXC_CCM_CCGR3_MLB_MASK                                 (3 << MXC_CCM_CCGR3_MLB_OFFSET)
 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET       20
 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK         (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET       22
 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK         (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
 #endif
 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET       22
 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK         (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
 #endif


@@ -613,14 +613,14 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK                        (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
 #define MXC_CCM_CCGR3_OCRAM_OFFSET                             28
 #define MXC_CCM_CCGR3_OCRAM_MASK                               (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK                        (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
 #define MXC_CCM_CCGR3_OCRAM_OFFSET                             28
 #define MXC_CCM_CCGR3_OCRAM_MASK                               (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET                      30
 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK                                (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
 #endif
 
 #define MXC_CCM_CCGR4_PCIE_OFFSET                              0
 #define MXC_CCM_CCGR4_PCIE_MASK                                        (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET                      30
 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK                                (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
 #endif
 
 #define MXC_CCM_CCGR4_PCIE_OFFSET                              0
 #define MXC_CCM_CCGR4_PCIE_MASK                                        (3 << MXC_CCM_CCGR4_PCIE_OFFSET)

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET                                10
 #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK                          (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
 #else
 #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET                                10
 #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK                          (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
 #else


@@ -650,7 +650,7 @@ struct mxc_ccm_reg {
 
 #define MXC_CCM_CCGR5_ROM_OFFSET                       0
 #define MXC_CCM_CCGR5_ROM_MASK                         (3 << MXC_CCM_CCGR5_ROM_OFFSET)
 
 #define MXC_CCM_CCGR5_ROM_OFFSET                       0
 #define MXC_CCM_CCGR5_ROM_MASK                         (3 << MXC_CCM_CCGR5_ROM_OFFSET)

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 #define MXC_CCM_CCGR5_SATA_OFFSET                      4
 #define MXC_CCM_CCGR5_SATA_MASK                                (3 << MXC_CCM_CCGR5_SATA_OFFSET)
 #endif
 #define MXC_CCM_CCGR5_SATA_OFFSET                      4
 #define MXC_CCM_CCGR5_SATA_MASK                                (3 << MXC_CCM_CCGR5_SATA_OFFSET)
 #endif


@@ -670,7 +670,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR5_UART_MASK                                (3 << MXC_CCM_CCGR5_UART_OFFSET)
 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET               26
 #define MXC_CCM_CCGR5_UART_SERIAL_MASK                 (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
 #define MXC_CCM_CCGR5_UART_MASK                                (3 << MXC_CCM_CCGR5_UART_OFFSET)
 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET               26
 #define MXC_CCM_CCGR5_UART_SERIAL_MASK                 (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define MXC_CCM_CCGR5_SAI1_OFFSET                      20
 #define MXC_CCM_CCGR5_SAI1_MASK                                (3 << MXC_CCM_CCGR5_SAI1_OFFSET)
 #define MXC_CCM_CCGR5_SAI2_OFFSET                      30
 #define MXC_CCM_CCGR5_SAI1_OFFSET                      20
 #define MXC_CCM_CCGR5_SAI1_MASK                                (3 << MXC_CCM_CCGR5_SAI1_OFFSET)
 #define MXC_CCM_CCGR5_SAI2_OFFSET                      30


@@ -1072,7 +1072,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR6_USDHC4_MASK                      (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET                  10
 #define MXC_CCM_CCGR6_EMI_SLOW_MASK                    (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
 #define MXC_CCM_CCGR6_USDHC4_MASK                      (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET                  10
 #define MXC_CCM_CCGR6_EMI_SLOW_MASK                    (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define MXC_CCM_CCGR6_PWM8_OFFSET                      16
 #define MXC_CCM_CCGR6_PWM8_MASK                                (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
 #define MXC_CCM_CCGR6_VADC_OFFSET                      20
 #define MXC_CCM_CCGR6_PWM8_OFFSET                      16
 #define MXC_CCM_CCGR6_PWM8_MASK                                (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
 #define MXC_CCM_CCGR6_VADC_OFFSET                      20

diff --git a/arch/arm/include/asm/arch-mx6/hab.h b/arch/arm/include/asm/arch-mx6/hab.h
index c9e5318bfb676ae96f0a9f8ddef3409a3362b7fc..230be45204f3c5105b8c07763678259eb1dba59d 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/hab.h
+++ b/arch/arm/include/asm/arch-mx6/hab.h
@@ -53,7 +53,7 @@ typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t,
                void **, size_t *, hab_loader_callback_f_t);
 typedef void hapi_clock_init_t(void);
 
                void **, size_t *, hab_loader_callback_f_t);
 typedef void hapi_clock_init_t(void);
 

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define HAB_RVT_BASE                   0x00000100
 #else
 #define HAB_RVT_BASE                   0x00000094
 #define HAB_RVT_BASE                   0x00000100
 #else
 #define HAB_RVT_BASE                   0x00000094

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 7368572cbc9f2b8116a2f9d0398b6d63e48dc26b..bc1c58a7b1ba5bbfbaf80cf063f9cd9c8ff85bc2 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -16,12 +16,12 @@
 #define ROMCP_ARB_BASE_ADDR            0x00000000
 #define ROMCP_ARB_END_ADDR             0x000FFFFF
 
 #define ROMCP_ARB_BASE_ADDR            0x00000000
 #define ROMCP_ARB_END_ADDR             0x000FFFFF
 

-#ifdef CONFIG_MX6SL
+#ifdef CONFIG_SOC_MX6SL

 #define GPU_2D_ARB_BASE_ADDR           0x02200000
 #define GPU_2D_ARB_END_ADDR            0x02203FFF
 #define OPENVG_ARB_BASE_ADDR           0x02204000
 #define OPENVG_ARB_END_ADDR            0x02207FFF
 #define GPU_2D_ARB_BASE_ADDR           0x02200000
 #define GPU_2D_ARB_END_ADDR            0x02203FFF
 #define OPENVG_ARB_BASE_ADDR           0x02204000
 #define OPENVG_ARB_END_ADDR            0x02207FFF

-#elif defined(CONFIG_MX6SX)
+#elif defined(CONFIG_SOC_MX6SX)

 #define CAAM_ARB_BASE_ADDR             0x00100000
 #define CAAM_ARB_END_ADDR              0x00107FFF
 #define GPU_ARB_BASE_ADDR              0x01800000
 #define CAAM_ARB_BASE_ADDR             0x00100000
 #define CAAM_ARB_END_ADDR              0x00107FFF
 #define GPU_ARB_BASE_ADDR              0x01800000


@@ -47,20 +47,20 @@
 #define GPU_2D_ARB_END_ADDR            0x00137FFF
 #define DTCP_ARB_BASE_ADDR             0x00138000
 #define DTCP_ARB_END_ADDR              0x0013BFFF
 #define GPU_2D_ARB_END_ADDR            0x00137FFF
 #define DTCP_ARB_BASE_ADDR             0x00138000
 #define DTCP_ARB_END_ADDR              0x0013BFFF

-#endif /* CONFIG_MX6SL */
+#endif /* CONFIG_SOC_MX6SL */

 
 #define MXS_APBH_BASE                  APBH_DMA_ARB_BASE_ADDR
 #define MXS_GPMI_BASE                  (APBH_DMA_ARB_BASE_ADDR + 0x02000)
 #define MXS_BCH_BASE                   (APBH_DMA_ARB_BASE_ADDR + 0x04000)
 
 /* GPV - PL301 configuration ports */
 
 #define MXS_APBH_BASE                  APBH_DMA_ARB_BASE_ADDR
 #define MXS_GPMI_BASE                  (APBH_DMA_ARB_BASE_ADDR + 0x02000)
 #define MXS_BCH_BASE                   (APBH_DMA_ARB_BASE_ADDR + 0x04000)
 
 /* GPV - PL301 configuration ports */

-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))

 #define GPV2_BASE_ADDR                 0x00D00000
 #else
 #define GPV2_BASE_ADDR                 0x00200000
 #endif
 
 #define GPV2_BASE_ADDR                 0x00D00000
 #else
 #define GPV2_BASE_ADDR                 0x00200000
 #endif
 

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define GPV3_BASE_ADDR                 0x00E00000
 #define GPV4_BASE_ADDR                 0x00F00000
 #define GPV5_BASE_ADDR                 0x01000000
 #define GPV3_BASE_ADDR                 0x00E00000
 #define GPV4_BASE_ADDR                 0x00F00000
 #define GPV5_BASE_ADDR                 0x01000000


@@ -89,7 +89,7 @@
 #define AIPS1_ARB_END_ADDR             0x020FFFFF
 #define AIPS2_ARB_BASE_ADDR            0x02100000
 #define AIPS2_ARB_END_ADDR             0x021FFFFF
 #define AIPS1_ARB_END_ADDR             0x020FFFFF
 #define AIPS2_ARB_BASE_ADDR            0x02100000
 #define AIPS2_ARB_END_ADDR             0x021FFFFF

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define AIPS3_BASE_ADDR                        0x02200000
 #define AIPS3_END_ADDR                 0x022FFFFF
 #define WEIM_ARB_BASE_ADDR             0x50000000
 #define AIPS3_BASE_ADDR                        0x02200000
 #define AIPS3_END_ADDR                 0x022FFFFF
 #define WEIM_ARB_BASE_ADDR             0x50000000


@@ -113,7 +113,7 @@
 #define WEIM_ARB_END_ADDR              0x0FFFFFFF
 #endif
 
 #define WEIM_ARB_END_ADDR              0x0FFFFFFF
 #endif
 

-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
+#if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))

 #define MMDC0_ARB_BASE_ADDR            0x80000000
 #define MMDC0_ARB_END_ADDR             0xFFFFFFFF
 #define MMDC1_ARB_BASE_ADDR            0xC0000000
 #define MMDC0_ARB_BASE_ADDR            0x80000000
 #define MMDC0_ARB_END_ADDR             0xFFFFFFFF
 #define MMDC1_ARB_BASE_ADDR            0xC0000000


@@ -125,7 +125,7 @@
 #define MMDC1_ARB_END_ADDR             0xFFFFFFFF
 #endif
 
 #define MMDC1_ARB_END_ADDR             0xFFFFFFFF
 #endif
 

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 #define IPU_SOC_BASE_ADDR              IPU1_ARB_BASE_ADDR
 #define IPU_SOC_OFFSET                 0x00200000
 #endif
 #define IPU_SOC_BASE_ADDR              IPU1_ARB_BASE_ADDR
 #define IPU_SOC_OFFSET                 0x00200000
 #endif


@@ -141,7 +141,7 @@
 #define ECSPI2_BASE_ADDR           (ATZ1_BASE_ADDR + 0x0C000)
 #define ECSPI3_BASE_ADDR           (ATZ1_BASE_ADDR + 0x10000)
 #define ECSPI4_BASE_ADDR           (ATZ1_BASE_ADDR + 0x14000)
 #define ECSPI2_BASE_ADDR           (ATZ1_BASE_ADDR + 0x0C000)
 #define ECSPI3_BASE_ADDR           (ATZ1_BASE_ADDR + 0x10000)
 #define ECSPI4_BASE_ADDR           (ATZ1_BASE_ADDR + 0x14000)

-#ifdef CONFIG_MX6SL
+#ifdef CONFIG_SOC_MX6SL

 #define UART5_IPS_BASE_ADDR        (ATZ1_BASE_ADDR + 0x18000)
 #define UART1_IPS_BASE_ADDR        (ATZ1_BASE_ADDR + 0x20000)
 #define UART2_IPS_BASE_ADDR        (ATZ1_BASE_ADDR + 0x24000)
 #define UART5_IPS_BASE_ADDR        (ATZ1_BASE_ADDR + 0x18000)
 #define UART1_IPS_BASE_ADDR        (ATZ1_BASE_ADDR + 0x20000)
 #define UART2_IPS_BASE_ADDR        (ATZ1_BASE_ADDR + 0x24000)


@@ -151,7 +151,7 @@
 #define UART3_IPS_BASE_ADDR        (ATZ1_BASE_ADDR + 0x34000)
 #define UART4_IPS_BASE_ADDR        (ATZ1_BASE_ADDR + 0x38000)
 #else
 #define UART3_IPS_BASE_ADDR        (ATZ1_BASE_ADDR + 0x34000)
 #define UART4_IPS_BASE_ADDR        (ATZ1_BASE_ADDR + 0x38000)
 #else

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 #define ECSPI5_BASE_ADDR           (ATZ1_BASE_ADDR + 0x18000)
 #endif
 #define UART1_BASE                 (ATZ1_BASE_ADDR + 0x20000)
 #define ECSPI5_BASE_ADDR           (ATZ1_BASE_ADDR + 0x18000)
 #endif
 #define UART1_BASE                 (ATZ1_BASE_ADDR + 0x20000)


@@ -162,7 +162,7 @@
 #define ASRC_BASE_ADDR             (ATZ1_BASE_ADDR + 0x34000)
 #endif
 
 #define ASRC_BASE_ADDR             (ATZ1_BASE_ADDR + 0x34000)
 #endif
 

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 #define SPBA_BASE_ADDR             (ATZ1_BASE_ADDR + 0x3C000)
 #define VPU_BASE_ADDR              (ATZ1_BASE_ADDR + 0x40000)
 #endif
 #define SPBA_BASE_ADDR             (ATZ1_BASE_ADDR + 0x3C000)
 #define VPU_BASE_ADDR              (ATZ1_BASE_ADDR + 0x40000)
 #endif


@@ -196,11 +196,11 @@
 #define SRC_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x58000)
 #define GPC_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x5C000)
 #define IOMUXC_BASE_ADDR           (AIPS1_OFF_BASE_ADDR + 0x60000)
 #define SRC_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x58000)
 #define GPC_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x5C000)
 #define IOMUXC_BASE_ADDR           (AIPS1_OFF_BASE_ADDR + 0x60000)

-#ifdef CONFIG_MX6SL
+#ifdef CONFIG_SOC_MX6SL

 #define CSI_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x64000)
 #define SIPIX_BASE_ADDR                    (AIPS1_OFF_BASE_ADDR + 0x68000)
 #define SDMA_PORT_HOST_BASE_ADDR    (AIPS1_OFF_BASE_ADDR + 0x6C000)
 #define CSI_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x64000)
 #define SIPIX_BASE_ADDR                    (AIPS1_OFF_BASE_ADDR + 0x68000)
 #define SDMA_PORT_HOST_BASE_ADDR    (AIPS1_OFF_BASE_ADDR + 0x6C000)

-#elif defined(CONFIG_MX6SX)
+#elif defined(CONFIG_SOC_MX6SX)

 #define CANFD1_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x68000)
 #define SDMA_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x6C000)
 #define CANFD2_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x70000)
 #define CANFD1_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x68000)
 #define SDMA_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x6C000)
 #define CANFD2_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x70000)


@@ -221,7 +221,7 @@
 #define USB_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x4000)
 
 #define ENET_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x8000)
 #define USB_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x4000)
 
 #define ENET_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x8000)

-#ifdef CONFIG_MX6SL
+#ifdef CONFIG_SOC_MX6SL

 #define MSHC_IPS_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0xC000)
 #else
 #define MLB_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0xC000)
 #define MSHC_IPS_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0xC000)
 #else
 #define MLB_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0xC000)


@@ -236,9 +236,9 @@
 #define I2C3_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x28000)
 #define ROMCP_BASE_ADDR                    (AIPS2_OFF_BASE_ADDR + 0x2C000)
 #define MMDC_P0_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x30000)
 #define I2C3_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x28000)
 #define ROMCP_BASE_ADDR                    (AIPS2_OFF_BASE_ADDR + 0x2C000)
 #define MMDC_P0_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x30000)

-#ifdef CONFIG_MX6SL
+#ifdef CONFIG_SOC_MX6SL

 #define RNGB_IPS_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x34000)
 #define RNGB_IPS_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x34000)

-#elif defined(CONFIG_MX6SX)
+#elif defined(CONFIG_SOC_MX6SX)

 #define ENET2_BASE_ADDR                    (AIPS2_OFF_BASE_ADDR + 0x34000)
 #else
 #define MMDC_P1_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x34000)
 #define ENET2_BASE_ADDR                    (AIPS2_OFF_BASE_ADDR + 0x34000)
 #else
 #define MMDC_P1_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x34000)


@@ -249,19 +249,19 @@
 #define CSU_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x40000)
 #define IP2APB_PERFMON1_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x44000)
 #define IP2APB_PERFMON2_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x48000)
 #define CSU_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x40000)
 #define IP2APB_PERFMON1_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x44000)
 #define IP2APB_PERFMON2_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x48000)

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define DEBUG_MONITOR_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x4C000)
 #else
 #define IP2APB_PERFMON3_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x4C000)
 #endif
 #define IP2APB_TZASC1_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x50000)
 #define DEBUG_MONITOR_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x4C000)
 #else
 #define IP2APB_PERFMON3_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x4C000)
 #endif
 #define IP2APB_TZASC1_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x50000)

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define SAI1_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x54000)
 #else
 #define IP2APB_TZASC2_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x54000)
 #endif
 #define AUDMUX_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x58000)
 #define SAI1_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x54000)
 #else
 #define IP2APB_TZASC2_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x54000)
 #endif
 #define AUDMUX_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x58000)

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define SAI2_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x5C000)
 #define QSPI0_BASE_ADDR                    (AIPS2_OFF_BASE_ADDR + 0x60000)
 #define QSPI1_BASE_ADDR                    (AIPS2_OFF_BASE_ADDR + 0x64000)
 #define SAI2_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x5C000)
 #define QSPI0_BASE_ADDR                    (AIPS2_OFF_BASE_ADDR + 0x60000)
 #define QSPI1_BASE_ADDR                    (AIPS2_OFF_BASE_ADDR + 0x64000)


@@ -277,7 +277,7 @@
 #define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
 #define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
 
 #define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
 #define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
 

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define GIS_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x04000)
 #define DCIC1_BASE_ADDR                    (AIPS3_ARB_BASE_ADDR + 0x0C000)
 #define DCIC2_BASE_ADDR                    (AIPS3_ARB_BASE_ADDR + 0x10000)
 #define GIS_BASE_ADDR              (AIPS3_ARB_BASE_ADDR + 0x04000)
 #define DCIC1_BASE_ADDR                    (AIPS3_ARB_BASE_ADDR + 0x0C000)
 #define DCIC2_BASE_ADDR                    (AIPS3_ARB_BASE_ADDR + 0x10000)


@@ -308,7 +308,7 @@
 #define CHIP_REV_1_0                0x10
 #define CHIP_REV_1_2                0x12
 #define CHIP_REV_1_5                0x15
 #define CHIP_REV_1_0                0x10
 #define CHIP_REV_1_2                0x12
 #define CHIP_REV_1_5                0x15

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 #define IRAM_SIZE                   0x00040000
 #else
 #define IRAM_SIZE                   0x00020000
 #define IRAM_SIZE                   0x00040000
 #else
 #define IRAM_SIZE                   0x00020000


@@ -445,7 +445,7 @@ struct src {
 
 
 struct iomuxc {
 
 
 struct iomuxc {

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

        u32 reserved[0x1000];
 #endif
        u32 gpr[14];
        u32 reserved[0x1000];
 #endif
        u32 gpr[14];


@@ -571,7 +571,7 @@ struct cspi_regs {
 #define MXC_CSPICON_POL                4  /* SCLK polarity */
 #define MXC_CSPICON_SSPOL      12 /* SS polarity */
 #define MXC_CSPICON_CTL                20 /* inactive state of SCLK */
 #define MXC_CSPICON_POL                4  /* SCLK polarity */
 #define MXC_CSPICON_SSPOL      12 /* SS polarity */
 #define MXC_CSPICON_CTL                20 /* inactive state of SCLK */

-#if defined(CONFIG_MX6SL) || defined(CONFIG_MX6DL)
+#if defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6DL)

 #define MXC_SPI_BASE_ADDRESSES \
        ECSPI1_BASE_ADDR, \
        ECSPI2_BASE_ADDR, \
 #define MXC_SPI_BASE_ADDRESSES \
        ECSPI1_BASE_ADDR, \
        ECSPI2_BASE_ADDR, \


@@ -621,7 +621,7 @@ struct fuse_bank0_regs {
        reg_32(cfg6);
 };
 
        reg_32(cfg6);
 };
 

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 struct fuse_bank4_regs {
        u32 sjc_resp_low;
        u32 rsvd0[3];
 struct fuse_bank4_regs {
        u32 sjc_resp_low;
        u32 rsvd0[3];

diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index 5ebabfa271f572672d59c33e97ae1d5b87609eec..64f65836f640c8a70a18c9f78a986f2d2976560a 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -7,19 +7,19 @@
 #define __ASM_ARCH_MX6_DDR_H__
 
 #ifndef CONFIG_SPL_BUILD
 #define __ASM_ARCH_MX6_DDR_H__
 
 #ifndef CONFIG_SPL_BUILD

-#ifdef CONFIG_MX6Q
+#ifdef CONFIG_SOC_MX6Q

 #include "mx6q-ddr.h"
 #else
 #include "mx6q-ddr.h"
 #else

-#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)

 #include "mx6dl-ddr.h"
 #else
 #include "mx6dl-ddr.h"
 #else

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #include "mx6sx-ddr.h"
 #else
 #error "Please select cpu"
 #include "mx6sx-ddr.h"
 #else
 #error "Please select cpu"

-#endif /* CONFIG_MX6SX */
-#endif /* CONFIG_MX6DL or CONFIG_MX6S */
-#endif /* CONFIG_MX6Q */
+#endif /* CONFIG_SOC_MX6SX */
+#endif /* CONFIG_SOC_MX6DL or CONFIG_SOC_MX6S */
+#endif /* CONFIG_SOC_MX6Q */

 #else
 
 /* MMDC P0/P1 Registers */
 #else
 
 /* MMDC P0/P1 Registers */

diff --git a/arch/arm/include/asm/arch-mx6/mx6-pins.h b/arch/arm/include/asm/arch-mx6/mx6-pins.h
index 534f780be8df35d5ed4ca223547919d92043b539..6c1fbbfb920209d80705323e250008d1a9b116cc 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/mx6-pins.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-pins.h
@@ -11,7 +11,7 @@
 #define MX6_PAD_DECLARE(prefix, name, pco, mc, mm, sio, si, pc) \
        prefix##name = IOMUX_PAD(pco, mc, mm, sio, si, pc)
 
 #define MX6_PAD_DECLARE(prefix, name, pco, mc, mm, sio, si, pc) \
        prefix##name = IOMUX_PAD(pco, mc, mm, sio, si, pc)
 

-#ifdef CONFIG_MX6QDL
+#ifdef CONFIG_SOC_MX6QDL

 enum {
 #define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
        MX6_PAD_DECLARE(MX6Q_PAD_,name, pco, mc, mm, sio, si, pc),
 enum {
 #define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
        MX6_PAD_DECLARE(MX6Q_PAD_,name, pco, mc, mm, sio, si, pc),


@@ -21,24 +21,24 @@ enum {
        MX6_PAD_DECLARE(MX6DL_PAD_,name, pco, mc, mm, sio, si, pc),
 #include "mx6dl_pins.h"
 };
        MX6_PAD_DECLARE(MX6DL_PAD_,name, pco, mc, mm, sio, si, pc),
 #include "mx6dl_pins.h"
 };

-#elif defined(CONFIG_MX6Q)
+#elif defined(CONFIG_SOC_MX6Q)

 enum {
 #define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
        MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
 #include "mx6q_pins.h"
 };
 enum {
 #define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
        MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
 #include "mx6q_pins.h"
 };

-#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#elif defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)

 enum {
 #define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
        MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
 #include "mx6dl_pins.h"
 };
 enum {
 #define MX6_PAD_DECL(name, pco, mc, mm, sio, si, pc) \
        MX6_PAD_DECLARE(MX6_PAD_,name, pco, mc, mm, sio, si, pc),
 #include "mx6dl_pins.h"
 };

-#elif defined(CONFIG_MX6SL)
+#elif defined(CONFIG_SOC_MX6SL)

 #include "mx6sl_pins.h"
 #include "mx6sl_pins.h"

-#elif defined(CONFIG_MX6SX)
+#elif defined(CONFIG_SOC_MX6SX)

 #include "mx6sx_pins.h"
 #else
 #error "Please select cpu"
 #include "mx6sx_pins.h"
 #else
 #error "Please select cpu"

-#endif /* CONFIG_MX6Q */
+#endif /* CONFIG_SOC_MX6Q */

 
 #endif /*__ASM_ARCH_MX6_PINS_H__ */
 
 #endif /*__ASM_ARCH_MX6_PINS_H__ */

diff --git a/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h b/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h
index 1eb4b3c8b3b2e135a846a8b169281e28de149650..b241b12a480d15754e70be34c8f97efae5e8d4bf 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6dl-ddr.h
@@ -6,8 +6,8 @@
 #ifndef __ASM_ARCH_MX6DLS_DDR_H__
 #define __ASM_ARCH_MX6DLS_DDR_H__
 
 #ifndef __ASM_ARCH_MX6DLS_DDR_H__
 #define __ASM_ARCH_MX6DLS_DDR_H__
 

-#ifndef CONFIG_MX6DL
-#ifndef CONFIG_MX6S
+#ifndef CONFIG_SOC_MX6DL
+#ifndef CONFIG_SOC_MX6S

 #error "wrong CPU"
 #endif
 #endif
 #error "wrong CPU"
 #endif
 #endif

diff --git a/arch/arm/include/asm/arch-mx6/mx6q-ddr.h b/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
index 0aa94cffe5177bf89fbfa59cd2bc423285a96d64..25e895335e53f74e36163f57b647cf7dafaf2985 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6q-ddr.h
@@ -6,7 +6,7 @@
 #ifndef __ASM_ARCH_MX6Q_DDR_H__
 #define __ASM_ARCH_MX6Q_DDR_H__
 
 #ifndef __ASM_ARCH_MX6Q_DDR_H__
 #define __ASM_ARCH_MX6Q_DDR_H__
 

-#ifndef CONFIG_MX6Q
+#ifndef CONFIG_SOC_MX6Q

 #error "wrong CPU"
 #endif
 
 #error "wrong CPU"
 #endif
 

diff --git a/arch/arm/include/asm/arch-mx6/mx6sx-ddr.h b/arch/arm/include/asm/arch-mx6/mx6sx-ddr.h
index 2cc94aa4c7808b005b0b7c5537de2860b08bd574..150138d2557c345db52daff3a4d9aee41bbd59d9 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/mx6sx-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6sx-ddr.h
@@ -7,7 +7,7 @@
 #ifndef __ASM_ARCH_MX6SX_DDR_H__
 #define __ASM_ARCH_MX6SX_DDR_H__
 
 #ifndef __ASM_ARCH_MX6SX_DDR_H__
 #define __ASM_ARCH_MX6SX_DDR_H__
 

-#ifndef CONFIG_MX6SX
+#ifndef CONFIG_SOC_MX6SX

 #error "wrong CPU"
 #endif
 
 #error "wrong CPU"
 #endif
 

diff --git a/arch/arm/include/asm/arch-mxs/clock.h b/arch/arm/include/asm/arch-mxs/clock.h
index d3bc95b8240ac270c8fa5920dde868bdffbacf83..e52d4133c93ff5e3305e968a96c7f67c81cb18f0 100644 (file)
--- a/arch/arm/include/asm/arch-mxs/clock.h
+++ b/arch/arm/include/asm/arch-mxs/clock.h
@@ -20,7 +20,7 @@ enum mxc_clock {
        MXC_IO1_CLK,
        MXC_XTAL_CLK,
        MXC_SSP0_CLK,
        MXC_IO1_CLK,
        MXC_XTAL_CLK,
        MXC_SSP0_CLK,

-#ifdef CONFIG_MX28
+#ifdef CONFIG_SOC_MX28

        MXC_SSP1_CLK,
        MXC_SSP2_CLK,
        MXC_SSP3_CLK,
        MXC_SSP1_CLK,
        MXC_SSP2_CLK,
        MXC_SSP3_CLK,


@@ -35,7 +35,7 @@ enum mxs_ioclock {
 
 enum mxs_sspclock {
        MXC_SSPCLK0 = 0,
 
 enum mxs_sspclock {
        MXC_SSPCLK0 = 0,

-#ifdef CONFIG_MX28
+#ifdef CONFIG_SOC_MX28

        MXC_SSPCLK1,
        MXC_SSPCLK2,
        MXC_SSPCLK3,
        MXC_SSPCLK1,
        MXC_SSPCLK2,
        MXC_SSPCLK3,

diff --git a/arch/arm/include/asm/arch-mxs/imx-regs.h b/arch/arm/include/asm/arch-mxs/imx-regs.h
index 86914ef7424e1f8c0cfb7286bc2f79a38b54231e..cc42dddf53c3e2d0aea9100ba09490d0557bd83d 100644 (file)
--- a/arch/arm/include/asm/arch-mxs/imx-regs.h
+++ b/arch/arm/include/asm/arch-mxs/imx-regs.h
@@ -26,12 +26,12 @@
 #include <asm/arch/regs-usb.h>
 #include <asm/arch/regs-usbphy.h>
 
 #include <asm/arch/regs-usb.h>
 #include <asm/arch/regs-usbphy.h>
 

-#ifdef CONFIG_MX23
+#ifdef CONFIG_SOC_MX23

 #include <asm/arch/regs-clkctrl-mx23.h>
 #include <asm/arch/regs-power-mx23.h>
 #endif
 
 #include <asm/arch/regs-clkctrl-mx23.h>
 #include <asm/arch/regs-power-mx23.h>
 #endif
 

-#ifdef CONFIG_MX28
+#ifdef CONFIG_SOC_MX28

 #include <asm/arch/regs-clkctrl-mx28.h>
 #include <asm/arch/regs-power-mx28.h>
 #endif
 #include <asm/arch/regs-clkctrl-mx28.h>
 #include <asm/arch/regs-power-mx28.h>
 #endif

diff --git a/arch/arm/include/asm/arch-mxs/iomux.h b/arch/arm/include/asm/arch-mxs/iomux.h
index 3d11491300c5c2bdfa7ec89b1ead1d6e2c1200b2..4a0ad73d11e801456f44cf28eb0a80c1887b979e 100644 (file)
--- a/arch/arm/include/asm/arch-mxs/iomux.h
+++ b/arch/arm/include/asm/arch-mxs/iomux.h
@@ -59,7 +59,7 @@ typedef u32 iomux_cfg_t;
 #define PAD_16MA               3
 
 #define PAD_1V8                        0
 #define PAD_16MA               3
 
 #define PAD_1V8                        0

-#if defined(CONFIG_MX28)
+#if defined(CONFIG_SOC_MX28)

 #define PAD_3V3                        1
 #else
 #define PAD_3V3                        0
 #define PAD_3V3                        1
 #else
 #define PAD_3V3                        0

diff --git a/arch/arm/include/asm/arch-mxs/regs-base.h b/arch/arm/include/asm/arch-mxs/regs-base.h
index 213df514ba9b306f50b2757fde28255eb81e1536..006cf638ecd184fed4538b994465b7fa9ec03426 100644 (file)
--- a/arch/arm/include/asm/arch-mxs/regs-base.h
+++ b/arch/arm/include/asm/arch-mxs/regs-base.h
@@ -18,7 +18,7 @@
 /*
  * Register base addresses for i.MX23
  */
 /*
  * Register base addresses for i.MX23
  */

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

 #define        MXS_ICOLL_BASE          0x80000000
 #define        MXS_APBH_BASE           0x80004000
 #define        MXS_ECC8_BASE           0x80008000
 #define        MXS_ICOLL_BASE          0x80000000
 #define        MXS_APBH_BASE           0x80004000
 #define        MXS_ECC8_BASE           0x80008000


@@ -60,7 +60,7 @@
 /*
  * Register base addresses for i.MX28
  */
 /*
  * Register base addresses for i.MX28
  */

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

 #define        MXS_ICOL_BASE           0x80000000
 #define        MXS_HSADC_BASE          0x80002000
 #define        MXS_APBH_BASE           0x80004000
 #define        MXS_ICOL_BASE           0x80000000
 #define        MXS_HSADC_BASE          0x80002000
 #define        MXS_APBH_BASE           0x80004000


@@ -115,7 +115,7 @@
 #define        MXS_ENET0_BASE          0x800F0000
 #define        MXS_ENET1_BASE          0x800F4000
 #else
 #define        MXS_ENET0_BASE          0x800F0000
 #define        MXS_ENET1_BASE          0x800F4000
 #else

-#error Unkown SoC. Please set CONFIG_MX23 or CONFIG_MX28
+#error Unkown SoC. Please set CONFIG_SOC_MX23 or CONFIG_SOC_MX28

 #endif
 
 #endif /* __MXS_REGS_BASE_H__ */
 #endif
 
 #endif /* __MXS_REGS_BASE_H__ */

diff --git a/arch/arm/include/asm/arch-mxs/regs-lcdif.h b/arch/arm/include/asm/arch-mxs/regs-lcdif.h
index a845883911b02204ad7d5f16613d0e1a296ad4d8..0d0e2d8e756df9662ea8b17ad3b0c4b023aebb05 100644 (file)
--- a/arch/arm/include/asm/arch-mxs/regs-lcdif.h
+++ b/arch/arm/include/asm/arch-mxs/regs-lcdif.h
@@ -19,14 +19,14 @@
 struct mxs_lcdif_regs {
        mxs_reg_32(hw_lcdif_ctrl);              /* 0x00 */
        mxs_reg_32(hw_lcdif_ctrl1);             /* 0x10 */
 struct mxs_lcdif_regs {
        mxs_reg_32(hw_lcdif_ctrl);              /* 0x00 */
        mxs_reg_32(hw_lcdif_ctrl1);             /* 0x10 */

-#if defined(CONFIG_MX28)
+#if defined(CONFIG_SOC_MX28)

        mxs_reg_32(hw_lcdif_ctrl2)              /* 0x20 */
 #endif                                         /* MX23/MX28 */
        mxs_reg_32(hw_lcdif_transfer_count);    /* 0x20/0x30 */
        mxs_reg_32(hw_lcdif_cur_buf);           /* 0x30/0x40 */
        mxs_reg_32(hw_lcdif_next_buf);          /* 0x40/0x50 */
 
        mxs_reg_32(hw_lcdif_ctrl2)              /* 0x20 */
 #endif                                         /* MX23/MX28 */
        mxs_reg_32(hw_lcdif_transfer_count);    /* 0x20/0x30 */
        mxs_reg_32(hw_lcdif_cur_buf);           /* 0x30/0x40 */
        mxs_reg_32(hw_lcdif_next_buf);          /* 0x40/0x50 */
 

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

        reg_32(reserved1);                      /* 0x50 */
 #endif
 
        reg_32(reserved1);                      /* 0x50 */
 #endif
 


@@ -49,12 +49,12 @@ struct mxs_lcdif_regs {
        mxs_reg_32(hw_lcdif_csc_offset);        /* 0x160 */
        mxs_reg_32(hw_lcdif_csc_limit);         /* 0x170 */
 
        mxs_reg_32(hw_lcdif_csc_offset);        /* 0x160 */
        mxs_reg_32(hw_lcdif_csc_limit);         /* 0x170 */
 

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

        reg_32(reserved2[3]);                   /* 0x180-0x1a0 */
 #endif                                         /*  MX23/MX28 */
        mxs_reg_32(hw_lcdif_data)               /* 0x1b0/0x180 */
        mxs_reg_32(hw_lcdif_bm_error_stat)      /* 0x1c0/0x190 */
        reg_32(reserved2[3]);                   /* 0x180-0x1a0 */
 #endif                                         /*  MX23/MX28 */
        mxs_reg_32(hw_lcdif_data)               /* 0x1b0/0x180 */
        mxs_reg_32(hw_lcdif_bm_error_stat)      /* 0x1c0/0x190 */

-#if defined(CONFIG_MX28)
+#if defined(CONFIG_SOC_MX28)

        mxs_reg_32(hw_lcdif_crc_stat)           /*       0x1a0 */
 #endif
        mxs_reg_32(hw_lcdif_lcdif_stat);        /* 0x1d0/0x1b0 */
        mxs_reg_32(hw_lcdif_crc_stat)           /*       0x1a0 */
 #endif
        mxs_reg_32(hw_lcdif_lcdif_stat);        /* 0x1d0/0x1b0 */


@@ -201,10 +201,10 @@ struct mxs_lcdif_regs {
 #define        LCDIF_VDCTRL1_VSYNC_PERIOD(n)                           (((n) << LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET) & \
                                                LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)
 
 #define        LCDIF_VDCTRL1_VSYNC_PERIOD(n)                           (((n) << LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET) & \
                                                LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)
 

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

 #define        LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK                    (0xff << 24)
 #define        LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET                  24
 #define        LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK                    (0xff << 24)
 #define        LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET                  24

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

 #define        LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK                    (0x3fff << 18)
 #define        LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET                  18
 #endif
 #define        LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK                    (0x3fff << 18)
 #define        LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET                  18
 #endif

diff --git a/arch/arm/include/asm/arch-mxs/regs-ssp.h b/arch/arm/include/asm/arch-mxs/regs-ssp.h
index 464e9e0914b6f4d02cd8502499c3fbda1af4b13d..b37e9b1e27b71eaf216f12f136211cb3c9475976 100644 (file)
--- a/arch/arm/include/asm/arch-mxs/regs-ssp.h
+++ b/arch/arm/include/asm/arch-mxs/regs-ssp.h
@@ -15,7 +15,7 @@
 #include <asm/imx-common/regs-common.h>
 
 #ifndef        __ASSEMBLY__
 #include <asm/imx-common/regs-common.h>
 
 #ifndef        __ASSEMBLY__

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

 struct mxs_ssp_regs {
        mxs_reg_32(hw_ssp_ctrl0);
        mxs_reg_32(hw_ssp_cmd0);
 struct mxs_ssp_regs {
        mxs_reg_32(hw_ssp_ctrl0);
        mxs_reg_32(hw_ssp_cmd0);


@@ -34,7 +34,7 @@ struct mxs_ssp_regs {
        mxs_reg_32(hw_ssp_debug);
        mxs_reg_32(hw_ssp_version);
 };
        mxs_reg_32(hw_ssp_debug);
        mxs_reg_32(hw_ssp_version);
 };

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

 struct mxs_ssp_regs {
        mxs_reg_32(hw_ssp_ctrl0);
        mxs_reg_32(hw_ssp_cmd0);
 struct mxs_ssp_regs {
        mxs_reg_32(hw_ssp_ctrl0);
        mxs_reg_32(hw_ssp_cmd0);


@@ -61,9 +61,9 @@ struct mxs_ssp_regs {
 
 static inline int mxs_ssp_bus_id_valid(int bus)
 {
 
 static inline int mxs_ssp_bus_id_valid(int bus)
 {

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

        const unsigned int mxs_ssp_chan_count = 2;
        const unsigned int mxs_ssp_chan_count = 2;

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

        const unsigned int mxs_ssp_chan_count = 4;
 #endif
 
        const unsigned int mxs_ssp_chan_count = 4;
 #endif
 


@@ -78,9 +78,9 @@ static inline int mxs_ssp_bus_id_valid(int bus)
 
 static inline int mxs_ssp_clock_by_bus(unsigned int clock)
 {
 
 static inline int mxs_ssp_clock_by_bus(unsigned int clock)
 {

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

        return 0;
        return 0;

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

        return clock;
 #endif
 }
        return clock;
 #endif
 }


@@ -92,7 +92,7 @@ static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port)
                return (struct mxs_ssp_regs *)MXS_SSP0_BASE;
        case 1:
                return (struct mxs_ssp_regs *)MXS_SSP1_BASE;
                return (struct mxs_ssp_regs *)MXS_SSP0_BASE;
        case 1:
                return (struct mxs_ssp_regs *)MXS_SSP1_BASE;

-#ifdef CONFIG_MX28
+#ifdef CONFIG_SOC_MX28

        case 2:
                return (struct mxs_ssp_regs *)MXS_SSP2_BASE;
        case 3:
        case 2:
                return (struct mxs_ssp_regs *)MXS_SSP2_BASE;
        case 3:


@@ -124,7 +124,7 @@ static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port)
 #define        SSP_CTRL0_GET_RESP                      (1 << 17)
 #define        SSP_CTRL0_ENABLE                        (1 << 16)
 
 #define        SSP_CTRL0_GET_RESP                      (1 << 17)
 #define        SSP_CTRL0_ENABLE                        (1 << 16)
 

-#ifdef CONFIG_MX23
+#ifdef CONFIG_SOC_MX23

 #define        SSP_CTRL0_XFER_COUNT_OFFSET             0
 #define        SSP_CTRL0_XFER_COUNT_MASK               0xffff
 #endif
 #define        SSP_CTRL0_XFER_COUNT_OFFSET             0
 #define        SSP_CTRL0_XFER_COUNT_MASK               0xffff
 #endif


@@ -136,7 +136,7 @@ static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port)
 #define        SSP_CMD0_SLOW_CLKING_EN                 (1 << 22)
 #define        SSP_CMD0_CONT_CLKING_EN                 (1 << 21)
 #define        SSP_CMD0_APPEND_8CYC                    (1 << 20)
 #define        SSP_CMD0_SLOW_CLKING_EN                 (1 << 22)
 #define        SSP_CMD0_CONT_CLKING_EN                 (1 << 21)
 #define        SSP_CMD0_APPEND_8CYC                    (1 << 20)

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

 #define        SSP_CMD0_BLOCK_SIZE_MASK                (0xf << 16)
 #define        SSP_CMD0_BLOCK_SIZE_OFFSET              16
 #define        SSP_CMD0_BLOCK_COUNT_MASK               (0xff << 8)
 #define        SSP_CMD0_BLOCK_SIZE_MASK                (0xf << 16)
 #define        SSP_CMD0_BLOCK_SIZE_OFFSET              16
 #define        SSP_CMD0_BLOCK_COUNT_MASK               (0xff << 8)


@@ -215,7 +215,7 @@ static inline struct mxs_ssp_regs *mxs_ssp_regs_by_bus(unsigned int port)
 #define        SSP_CMD1_CMD_ARG_MASK                   0xffffffff
 #define        SSP_CMD1_CMD_ARG_OFFSET                 0
 
 #define        SSP_CMD1_CMD_ARG_MASK                   0xffffffff
 #define        SSP_CMD1_CMD_ARG_OFFSET                 0
 

-#if defined(CONFIG_MX28)
+#if defined(CONFIG_SOC_MX28)

 #define        SSP_XFER_SIZE_XFER_COUNT_MASK           0xffffffff
 #define        SSP_XFER_SIZE_XFER_COUNT_OFFSET         0
 
 #define        SSP_XFER_SIZE_XFER_COUNT_MASK           0xffffffff
 #define        SSP_XFER_SIZE_XFER_COUNT_OFFSET         0
 

diff --git a/arch/arm/include/asm/arch-mxs/regs-timrot.h b/arch/arm/include/asm/arch-mxs/regs-timrot.h
index 0ee3ec81bb7818baf41be1c01a14c2514f93bda5..b5160c9e02782da02b16397cccb34905b1c0035a 100644 (file)
--- a/arch/arm/include/asm/arch-mxs/regs-timrot.h
+++ b/arch/arm/include/asm/arch-mxs/regs-timrot.h
@@ -18,7 +18,7 @@
 struct mxs_timrot_regs {
        mxs_reg_32(hw_timrot_rotctrl);
        mxs_reg_32(hw_timrot_rotcount);
 struct mxs_timrot_regs {
        mxs_reg_32(hw_timrot_rotctrl);
        mxs_reg_32(hw_timrot_rotcount);

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

        mxs_reg_32(hw_timrot_timctrl0);
        mxs_reg_32(hw_timrot_timcount0);
        mxs_reg_32(hw_timrot_timctrl1);
        mxs_reg_32(hw_timrot_timctrl0);
        mxs_reg_32(hw_timrot_timcount0);
        mxs_reg_32(hw_timrot_timctrl1);


@@ -27,7 +27,7 @@ struct mxs_timrot_regs {
        mxs_reg_32(hw_timrot_timcount2);
        mxs_reg_32(hw_timrot_timctrl3);
        mxs_reg_32(hw_timrot_timcount3);
        mxs_reg_32(hw_timrot_timcount2);
        mxs_reg_32(hw_timrot_timctrl3);
        mxs_reg_32(hw_timrot_timcount3);

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

        mxs_reg_32(hw_timrot_timctrl0);
        mxs_reg_32(hw_timrot_running_count0);
        mxs_reg_32(hw_timrot_fixed_count0);
        mxs_reg_32(hw_timrot_timctrl0);
        mxs_reg_32(hw_timrot_running_count0);
        mxs_reg_32(hw_timrot_fixed_count0);


@@ -69,9 +69,9 @@ struct mxs_timrot_regs {
 #define        TIMROT_ROTCTRL_OVERSAMPLE_1X                    (0x3 << 10)
 #define        TIMROT_ROTCTRL_POLARITY_B                       (1 << 9)
 #define        TIMROT_ROTCTRL_POLARITY_A                       (1 << 8)
 #define        TIMROT_ROTCTRL_OVERSAMPLE_1X                    (0x3 << 10)
 #define        TIMROT_ROTCTRL_POLARITY_B                       (1 << 9)
 #define        TIMROT_ROTCTRL_POLARITY_A                       (1 << 8)

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

 #define        TIMROT_ROTCTRL_SELECT_B_MASK                    (0x7 << 4)
 #define        TIMROT_ROTCTRL_SELECT_B_MASK                    (0x7 << 4)

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

 #define        TIMROT_ROTCTRL_SELECT_B_MASK                    (0xf << 4)
 #endif
 #define        TIMROT_ROTCTRL_SELECT_B_OFFSET                  4
 #define        TIMROT_ROTCTRL_SELECT_B_MASK                    (0xf << 4)
 #endif
 #define        TIMROT_ROTCTRL_SELECT_B_OFFSET                  4


@@ -81,19 +81,19 @@ struct mxs_timrot_regs {
 #define        TIMROT_ROTCTRL_SELECT_B_PWM2                    (0x3 << 4)
 #define        TIMROT_ROTCTRL_SELECT_B_PWM3                    (0x4 << 4)
 #define        TIMROT_ROTCTRL_SELECT_B_PWM4                    (0x5 << 4)
 #define        TIMROT_ROTCTRL_SELECT_B_PWM2                    (0x3 << 4)
 #define        TIMROT_ROTCTRL_SELECT_B_PWM3                    (0x4 << 4)
 #define        TIMROT_ROTCTRL_SELECT_B_PWM4                    (0x5 << 4)

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

 #define        TIMROT_ROTCTRL_SELECT_B_ROTARYA         (0x6 << 4)
 #define        TIMROT_ROTCTRL_SELECT_B_ROTARYB         (0x7 << 4)
 #define        TIMROT_ROTCTRL_SELECT_B_ROTARYA         (0x6 << 4)
 #define        TIMROT_ROTCTRL_SELECT_B_ROTARYB         (0x7 << 4)

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

 #define        TIMROT_ROTCTRL_SELECT_B_PWM5                    (0x6 << 4)
 #define        TIMROT_ROTCTRL_SELECT_B_PWM6                    (0x7 << 4)
 #define        TIMROT_ROTCTRL_SELECT_B_PWM7                    (0x8 << 4)
 #define        TIMROT_ROTCTRL_SELECT_B_ROTARYA                 (0x9 << 4)
 #define        TIMROT_ROTCTRL_SELECT_B_ROTARYB                 (0xa << 4)
 #endif
 #define        TIMROT_ROTCTRL_SELECT_B_PWM5                    (0x6 << 4)
 #define        TIMROT_ROTCTRL_SELECT_B_PWM6                    (0x7 << 4)
 #define        TIMROT_ROTCTRL_SELECT_B_PWM7                    (0x8 << 4)
 #define        TIMROT_ROTCTRL_SELECT_B_ROTARYA                 (0x9 << 4)
 #define        TIMROT_ROTCTRL_SELECT_B_ROTARYB                 (0xa << 4)
 #endif

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

 #define        TIMROT_ROTCTRL_SELECT_A_MASK                    0x7
 #define        TIMROT_ROTCTRL_SELECT_A_MASK                    0x7

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

 #define        TIMROT_ROTCTRL_SELECT_A_MASK                    0xf
 #endif
 #define        TIMROT_ROTCTRL_SELECT_A_OFFSET                  0
 #define        TIMROT_ROTCTRL_SELECT_A_MASK                    0xf
 #endif
 #define        TIMROT_ROTCTRL_SELECT_A_OFFSET                  0


@@ -103,10 +103,10 @@ struct mxs_timrot_regs {
 #define        TIMROT_ROTCTRL_SELECT_A_PWM2                    0x3
 #define        TIMROT_ROTCTRL_SELECT_A_PWM3                    0x4
 #define        TIMROT_ROTCTRL_SELECT_A_PWM4                    0x5
 #define        TIMROT_ROTCTRL_SELECT_A_PWM2                    0x3
 #define        TIMROT_ROTCTRL_SELECT_A_PWM3                    0x4
 #define        TIMROT_ROTCTRL_SELECT_A_PWM4                    0x5

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

 #define        TIMROT_ROTCTRL_SELECT_A_ROTARYA         0x6
 #define        TIMROT_ROTCTRL_SELECT_A_ROTARYB         0x7
 #define        TIMROT_ROTCTRL_SELECT_A_ROTARYA         0x6
 #define        TIMROT_ROTCTRL_SELECT_A_ROTARYB         0x7

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

 #define        TIMROT_ROTCTRL_SELECT_A_PWM5                    0x6
 #define        TIMROT_ROTCTRL_SELECT_A_PWM6                    0x7
 #define        TIMROT_ROTCTRL_SELECT_A_PWM7                    0x8
 #define        TIMROT_ROTCTRL_SELECT_A_PWM5                    0x6
 #define        TIMROT_ROTCTRL_SELECT_A_PWM6                    0x7
 #define        TIMROT_ROTCTRL_SELECT_A_PWM7                    0x8


@@ -119,7 +119,7 @@ struct mxs_timrot_regs {
 
 #define        TIMROT_TIMCTRLn_IRQ                             (1 << 15)
 #define        TIMROT_TIMCTRLn_IRQ_EN                          (1 << 14)
 
 #define        TIMROT_TIMCTRLn_IRQ                             (1 << 15)
 #define        TIMROT_TIMCTRLn_IRQ_EN                          (1 << 14)

-#if defined(CONFIG_MX28)
+#if defined(CONFIG_SOC_MX28)

 #define        TIMROT_TIMCTRLn_MATCH_MODE                      (1 << 11)
 #endif
 #define        TIMROT_TIMCTRLn_POLARITY                        (1 << 8)
 #define        TIMROT_TIMCTRLn_MATCH_MODE                      (1 << 11)
 #endif
 #define        TIMROT_TIMCTRLn_POLARITY                        (1 << 8)


@@ -139,7 +139,7 @@ struct mxs_timrot_regs {
 #define        TIMROT_TIMCTRLn_SELECT_PWM2                     0x3
 #define        TIMROT_TIMCTRLn_SELECT_PWM3                     0x4
 #define        TIMROT_TIMCTRLn_SELECT_PWM4                     0x5
 #define        TIMROT_TIMCTRLn_SELECT_PWM2                     0x3
 #define        TIMROT_TIMCTRLn_SELECT_PWM3                     0x4
 #define        TIMROT_TIMCTRLn_SELECT_PWM4                     0x5

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

 #define        TIMROT_TIMCTRLn_SELECT_ROTARYA          0x6
 #define        TIMROT_TIMCTRLn_SELECT_ROTARYB          0x7
 #define        TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL               0x8
 #define        TIMROT_TIMCTRLn_SELECT_ROTARYA          0x6
 #define        TIMROT_TIMCTRLn_SELECT_ROTARYB          0x7
 #define        TIMROT_TIMCTRLn_SELECT_32KHZ_XTAL               0x8


@@ -147,7 +147,7 @@ struct mxs_timrot_regs {
 #define        TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL                0xa
 #define        TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL                0xb
 #define        TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS              0xc
 #define        TIMROT_TIMCTRLn_SELECT_4KHZ_XTAL                0xa
 #define        TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL                0xb
 #define        TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS              0xc

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

 #define        TIMROT_TIMCTRLn_SELECT_PWM5                     0x6
 #define        TIMROT_TIMCTRLn_SELECT_PWM6                     0x7
 #define        TIMROT_TIMCTRLn_SELECT_PWM7                     0x8
 #define        TIMROT_TIMCTRLn_SELECT_PWM5                     0x6
 #define        TIMROT_TIMCTRLn_SELECT_PWM6                     0x7
 #define        TIMROT_TIMCTRLn_SELECT_PWM7                     0x8


@@ -160,23 +160,23 @@ struct mxs_timrot_regs {
 #define        TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS              0xf
 #endif
 
 #define        TIMROT_TIMCTRLn_SELECT_TICK_ALWAYS              0xf
 #endif
 

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

 #define        TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK        (0xffff << 16)
 #define        TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET      16
 #define        TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK        (0xffff << 16)
 #define        TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET      16

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

 #define        TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK        0xffffffff
 #define        TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET      0
 #endif
 
 #define        TIMROT_RUNNING_COUNTn_RUNNING_COUNT_MASK        0xffffffff
 #define        TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET      0
 #endif
 

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

 #define        TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK            0xffff
 #define        TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET          0
 #define        TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK            0xffff
 #define        TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET          0

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

 #define        TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK            0xffffffff
 #define        TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET          0
 #endif
 
 #define        TIMROT_FIXED_COUNTn_FIXED_COUNT_MASK            0xffffffff
 #define        TIMROT_FIXED_COUNTn_FIXED_COUNT_OFFSET          0
 #endif
 

-#if defined(CONFIG_MX28)
+#if defined(CONFIG_SOC_MX28)

 #define        TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK            0xffffffff
 #define        TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET          0
 #endif
 #define        TIMROT_MATCH_COUNTn_MATCH_COUNT_MASK            0xffffffff
 #define        TIMROT_MATCH_COUNTn_MATCH_COUNT_OFFSET          0
 #endif


@@ -189,7 +189,7 @@ struct mxs_timrot_regs {
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2                (0x3 << 16)
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3                (0x4 << 16)
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4                (0x5 << 16)
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_PWM2                (0x3 << 16)
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_PWM3                (0x4 << 16)
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_PWM4                (0x5 << 16)

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA             (0x6 << 16)
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB             (0x7 << 16)
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL          (0x8 << 16)
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYA             (0x6 << 16)
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_ROTARYB             (0x7 << 16)
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_32KHZ_XTAL          (0x8 << 16)


@@ -197,7 +197,7 @@ struct mxs_timrot_regs {
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL           (0xa << 16)
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL           (0xb << 16)
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS         (0xc << 16)
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_4KHZ_XTAL           (0xa << 16)
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL           (0xb << 16)
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS         (0xc << 16)

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5                (0x6 << 16)
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6                (0x7 << 16)
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7                (0x8 << 16)
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_PWM5                (0x6 << 16)
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_PWM6                (0x7 << 16)
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_PWM7                (0x8 << 16)


@@ -209,13 +209,13 @@ struct mxs_timrot_regs {
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL           (0xe << 16)
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS         (0xf << 16)
 #endif
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_1KHZ_XTAL           (0xe << 16)
 #define        TIMROT_TIMCTRL3_TEST_SIGNAL_TICK_ALWAYS         (0xf << 16)
 #endif

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

 #define        TIMROT_TIMCTRL3_IRQ                             (1 << 15)
 #define        TIMROT_TIMCTRL3_IRQ_EN                          (1 << 14)
 #define        TIMROT_TIMCTRL3_DUTU_VALID                      (1 << 10)
 #endif
 #define        TIMROT_TIMCTRL3_DUTY_CYCLE                      (1 << 9)
 #define        TIMROT_TIMCTRL3_IRQ                             (1 << 15)
 #define        TIMROT_TIMCTRL3_IRQ_EN                          (1 << 14)
 #define        TIMROT_TIMCTRL3_DUTU_VALID                      (1 << 10)
 #endif
 #define        TIMROT_TIMCTRL3_DUTY_CYCLE                      (1 << 9)

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

 #define        TIMROT_TIMCTRL3_POLARITY_MASK                   (0x1 << 8)
 #define        TIMROT_TIMCTRL3_POLARITY_OFFSET         8
 #define        TIMROT_TIMCTRL3_POLARITY_POSITIVE               (0x0 << 8)
 #define        TIMROT_TIMCTRL3_POLARITY_MASK                   (0x1 << 8)
 #define        TIMROT_TIMCTRL3_POLARITY_OFFSET         8
 #define        TIMROT_TIMCTRL3_POLARITY_POSITIVE               (0x0 << 8)

diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h
index 407055c9095f170d965f867b980e18d728c63eda..2e86da5946c9c7e9fac9128f107b8e6321fe9b5f 100644 (file)
--- a/arch/arm/include/asm/arch-mxs/sys_proto.h
+++ b/arch/arm/include/asm/arch-mxs/sys_proto.h
@@ -26,9 +26,9 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
 
 #ifdef CONFIG_SPL_BUILD
 
 
 #ifdef CONFIG_SPL_BUILD
 

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

 #include <asm/arch/iomux-mx23.h>
 #include <asm/arch/iomux-mx23.h>

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

 #include <asm/arch/iomux-mx28.h>
 #endif
 
 #include <asm/arch/iomux-mx28.h>
 #endif
 


@@ -44,7 +44,7 @@ struct mxs_pair {
 };
 
 static const struct mxs_pair mxs_boot_modes[] = {
 };
 
 static const struct mxs_pair mxs_boot_modes[] = {

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

        { 0x00, 0x0f, "USB" },
        { 0x01, 0x1f, "I2C, master" },
        { 0x02, 0x1f, "SSP SPI #1, master, NOR" },
        { 0x00, 0x0f, "USB" },
        { 0x01, 0x1f, "I2C, master" },
        { 0x02, 0x1f, "SSP SPI #1, master, NOR" },


@@ -55,7 +55,7 @@ static const struct mxs_pair mxs_boot_modes[] = {
        { 0x09, 0x1f, "SSP SD/MMC #0" },
        { 0x0a, 0x1f, "SSP SD/MMC #1" },
        { 0x00, 0x00, "Reserved/Unknown/Wrong" },
        { 0x09, 0x1f, "SSP SD/MMC #0" },
        { 0x0a, 0x1f, "SSP SD/MMC #1" },
        { 0x00, 0x00, "Reserved/Unknown/Wrong" },

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

        { 0x00, 0x0f, "USB #0" },
        { 0x01, 0x1f, "I2C #0, master, 3V3" },
        { 0x11, 0x1f, "I2C #0, master, 1V8" },
        { 0x00, 0x0f, "USB #0" },
        { 0x01, 0x1f, "I2C #0, master, 3V3" },
        { 0x11, 0x1f, "I2C #0, master, 1V8" },

diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h
index be80434dee4d0dc9824f6f74e198a51be40f938b..dfa634d62efbda813e7ce1a425336da63e531267 100644 (file)
--- a/arch/arm/include/asm/config.h
+++ b/arch/arm/include/asm/config.h
@@ -23,7 +23,7 @@
 #include <asm/arch-fsl-lsch3/config.h>
 #endif
 
 #include <asm/arch-fsl-lsch3/config.h>
 #endif
 

-#ifdef CONFIG_LS102XA
+#ifdef CONFIG_SOC_LS102XA

 #include <asm/arch/config.h>
 #endif
 
 #include <asm/arch/config.h>
 #endif
 

diff --git a/arch/arm/include/asm/imx-common/dma.h b/arch/arm/include/asm/imx-common/dma.h
index 8f9a11a288264e27d35244367f49991f06ff8bee..a0eae0dffe05ffa41f19e98817e98b101b63fbda 100644 (file)
--- a/arch/arm/include/asm/imx-common/dma.h
+++ b/arch/arm/include/asm/imx-common/dma.h
@@ -27,7 +27,7 @@
 /*
  * MXS DMA channels
  */
 /*
  * MXS DMA channels
  */

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

 enum {
        MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0,
        MXS_DMA_CHANNEL_AHB_APBH_SSP0,
 enum {
        MXS_DMA_CHANNEL_AHB_APBH_LCDIF = 0,
        MXS_DMA_CHANNEL_AHB_APBH_SSP0,


@@ -39,7 +39,7 @@ enum {
        MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
        MXS_MAX_DMA_CHANNELS,
 };
        MXS_DMA_CHANNEL_AHB_APBH_GPMI3,
        MXS_MAX_DMA_CHANNELS,
 };

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

 enum {
        MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
        MXS_DMA_CHANNEL_AHB_APBH_SSP1,
 enum {
        MXS_DMA_CHANNEL_AHB_APBH_SSP0 = 0,
        MXS_DMA_CHANNEL_AHB_APBH_SSP1,


@@ -59,7 +59,7 @@ enum {
        MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
        MXS_MAX_DMA_CHANNELS,
 };
        MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
        MXS_MAX_DMA_CHANNELS,
 };

-#elif defined(CONFIG_MX6)
+#elif defined(CONFIG_SOC_MX6)

 enum {
        MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
        MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
 enum {
        MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
        MXS_DMA_CHANNEL_AHB_APBH_GPMI1,

diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h
index 9ba5f6be9622ffe68d0d1c5b7add81e66ca752d6..9af5af71c60aa59add64f581eebbaa4613d366a7 100644 (file)
--- a/arch/arm/include/asm/imx-common/iomux-v3.h
+++ b/arch/arm/include/asm/imx-common/iomux-v3.h
@@ -92,7 +92,7 @@ typedef u64 iomux_v3_cfg_t;
 #define __PAD_CTRL_VALID       (1 << 17)
 #define PAD_CTRL_VALID         ((iomux_v3_cfg_t)__PAD_CTRL_VALID << MUX_PAD_CTRL_SHIFT)
 
 #define __PAD_CTRL_VALID       (1 << 17)
 #define PAD_CTRL_VALID         ((iomux_v3_cfg_t)__PAD_CTRL_VALID << MUX_PAD_CTRL_SHIFT)
 

-#ifdef CONFIG_MX6
+#ifdef CONFIG_SOC_MX6

 
 #define PAD_CTL_HYS            __MUX_PAD_CTRL(1 << 16)
 
 
 #define PAD_CTL_HYS            __MUX_PAD_CTRL(1 << 16)
 


@@ -118,12 +118,12 @@ typedef u64 iomux_v3_cfg_t;
 #define PAD_CTL_DSE_40ohm      __MUX_PAD_CTRL(6 << 3)
 #define PAD_CTL_DSE_34ohm      __MUX_PAD_CTRL(7 << 3)
 
 #define PAD_CTL_DSE_40ohm      __MUX_PAD_CTRL(6 << 3)
 #define PAD_CTL_DSE_34ohm      __MUX_PAD_CTRL(7 << 3)
 

-#if defined CONFIG_MX6SL
+#if defined CONFIG_SOC_MX6SL

 #define PAD_CTL_LVE            __MUX_PAD_CTRL(1 << 1)
 #define PAD_CTL_LVE_BIT                __MUX_PAD_CTRL(1 << 22)
 #endif
 
 #define PAD_CTL_LVE            __MUX_PAD_CTRL(1 << 1)
 #define PAD_CTL_LVE_BIT                __MUX_PAD_CTRL(1 << 22)
 #endif
 

-#elif defined(CONFIG_VF610)
+#elif defined(CONFIG_SOC_VF610)

 
 #define PAD_MUX_MODE_SHIFT     20
 
 
 #define PAD_MUX_MODE_SHIFT     20
 


@@ -196,7 +196,7 @@ void imx_iomux_set_gpr_register(int group, int start_bit,
                                         int num_bits, int value);
 
 /* macros for declaring and using pinmux array */
                                         int num_bits, int value);
 
 /* macros for declaring and using pinmux array */

-#if defined(CONFIG_MX6QDL)
+#if defined(CONFIG_SOC_MX6QDL)

 #define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
 #define SETUP_IOMUX_PAD(def)                                   \
 if (is_cpu_type(MXC_CPU_MX6Q)) {                               \
 #define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
 #define SETUP_IOMUX_PAD(def)                                   \
 if (is_cpu_type(MXC_CPU_MX6Q)) {                               \


@@ -206,7 +206,7 @@ if (is_cpu_type(MXC_CPU_MX6Q)) {                            \
 }
 #define SETUP_IOMUX_PADS(x)                                    \
        imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)
 }
 #define SETUP_IOMUX_PADS(x)                                    \
        imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)

-#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+#elif defined(CONFIG_SOC_MX6Q) || defined(CONFIG_SOC_MX6D)

 #define IOMUX_PADS(x) MX6Q_##x
 #define SETUP_IOMUX_PAD(def)                                   \
        imx_iomux_v3_setup_pad(MX6Q_##def);
 #define IOMUX_PADS(x) MX6Q_##x
 #define SETUP_IOMUX_PAD(def)                                   \
        imx_iomux_v3_setup_pad(MX6Q_##def);

diff --git a/arch/arm/include/asm/imx-common/mxc_i2c.h b/arch/arm/include/asm/imx-common/mxc_i2c.h
index af861635350d00209405435084ef767bec5b77e6..295ef51299fb452858c61ff34bf3f68f5c6f263e 100644 (file)
--- a/arch/arm/include/asm/imx-common/mxc_i2c.h
+++ b/arch/arm/include/asm/imx-common/mxc_i2c.h
@@ -19,7 +19,7 @@ struct i2c_pads_info {
        struct i2c_pin_ctrl sda;
 };
 
        struct i2c_pin_ctrl sda;
 };
 

-#if defined(CONFIG_MX6QDL)
+#if defined(CONFIG_SOC_MX6QDL)

 #define I2C_PADS(name, scl_i2c, scl_gpio, scl_gp, sda_i2c, sda_gpio, sda_gp) \
        struct i2c_pads_info mx6q_##name = {            \
                .scl = {                                \
 #define I2C_PADS(name, scl_i2c, scl_gpio, scl_gp, sda_i2c, sda_gpio, sda_gp) \
        struct i2c_pads_info mx6q_##name = {            \
                .scl = {                                \

diff --git a/arch/arm/include/asm/imx-common/regs-apbh.h b/arch/arm/include/asm/imx-common/regs-apbh.h
index bcbde05df39c68981abb75003b314e6e4af19eb5..1b14248b6f7ec699a0314ac24b0cb899ab88e84d 100644 (file)
--- a/arch/arm/include/asm/imx-common/regs-apbh.h
+++ b/arch/arm/include/asm/imx-common/regs-apbh.h
@@ -17,7 +17,7 @@
 
 #ifndef        __ASSEMBLY__
 
 
 #ifndef        __ASSEMBLY__
 

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

 struct mxs_apbh_regs {
        mxs_reg_32(hw_apbh_ctrl0);
        mxs_reg_32(hw_apbh_ctrl1);
 struct mxs_apbh_regs {
        mxs_reg_32(hw_apbh_ctrl0);
        mxs_reg_32(hw_apbh_ctrl1);


@@ -96,7 +96,7 @@ struct mxs_apbh_regs {
        mxs_reg_32(hw_apbh_version);
 };
 
        mxs_reg_32(hw_apbh_version);
 };
 

-#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6))
+#elif (defined(CONFIG_SOC_MX28) || defined(CONFIG_SOC_MX6))

 struct mxs_apbh_regs {
        mxs_reg_32(hw_apbh_ctrl0);                              /* 0x000 */
        mxs_reg_32(hw_apbh_ctrl1);                              /* 0x010 */
 struct mxs_apbh_regs {
        mxs_reg_32(hw_apbh_ctrl0);                              /* 0x000 */
        mxs_reg_32(hw_apbh_ctrl1);                              /* 0x010 */


@@ -243,7 +243,7 @@ struct mxs_apbh_regs {
 #define        APBH_CTRL0_CLKGATE                              (1 << 30)
 #define        APBH_CTRL0_AHB_BURST8_EN                        (1 << 29)
 #define        APBH_CTRL0_APB_BURST_EN                         (1 << 28)
 #define        APBH_CTRL0_CLKGATE                              (1 << 30)
 #define        APBH_CTRL0_AHB_BURST8_EN                        (1 << 29)
 #define        APBH_CTRL0_APB_BURST_EN                         (1 << 28)

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

 #define        APBH_CTRL0_RSVD0_MASK                           (0xf << 24)
 #define        APBH_CTRL0_RSVD0_OFFSET                         24
 #define        APBH_CTRL0_RESET_CHANNEL_MASK                   (0xff << 16)
 #define        APBH_CTRL0_RSVD0_MASK                           (0xf << 24)
 #define        APBH_CTRL0_RSVD0_OFFSET                         24
 #define        APBH_CTRL0_RESET_CHANNEL_MASK                   (0xff << 16)


@@ -256,7 +256,7 @@ struct mxs_apbh_regs {
 #define        APBH_CTRL0_CLKGATE_CHANNEL_NAND1                0x20
 #define        APBH_CTRL0_CLKGATE_CHANNEL_NAND2                0x40
 #define        APBH_CTRL0_CLKGATE_CHANNEL_NAND3                0x80
 #define        APBH_CTRL0_CLKGATE_CHANNEL_NAND1                0x20
 #define        APBH_CTRL0_CLKGATE_CHANNEL_NAND2                0x40
 #define        APBH_CTRL0_CLKGATE_CHANNEL_NAND3                0x80

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

 #define        APBH_CTRL0_RSVD0_MASK                           (0xfff << 16)
 #define        APBH_CTRL0_RSVD0_OFFSET                         16
 #define        APBH_CTRL0_CLKGATE_CHANNEL_MASK                 0xffff
 #define        APBH_CTRL0_RSVD0_MASK                           (0xfff << 16)
 #define        APBH_CTRL0_RSVD0_OFFSET                         16
 #define        APBH_CTRL0_CLKGATE_CHANNEL_MASK                 0xffff


@@ -275,7 +275,7 @@ struct mxs_apbh_regs {
 #define        APBH_CTRL0_CLKGATE_CHANNEL_NAND7                0x0800
 #define        APBH_CTRL0_CLKGATE_CHANNEL_HSADC                0x1000
 #define        APBH_CTRL0_CLKGATE_CHANNEL_LCDIF                0x2000
 #define        APBH_CTRL0_CLKGATE_CHANNEL_NAND7                0x0800
 #define        APBH_CTRL0_CLKGATE_CHANNEL_HSADC                0x1000
 #define        APBH_CTRL0_CLKGATE_CHANNEL_LCDIF                0x2000

-#elif defined(CONFIG_MX6)
+#elif defined(CONFIG_SOC_MX6)

 #define        APBH_CTRL0_CLKGATE_CHANNEL_OFFSET               0
 #define        APBH_CTRL0_CLKGATE_CHANNEL_NAND0                0x0001
 #define        APBH_CTRL0_CLKGATE_CHANNEL_NAND1                0x0002
 #define        APBH_CTRL0_CLKGATE_CHANNEL_OFFSET               0
 #define        APBH_CTRL0_CLKGATE_CHANNEL_NAND0                0x0001
 #define        APBH_CTRL0_CLKGATE_CHANNEL_NAND1                0x0002


@@ -356,7 +356,7 @@ struct mxs_apbh_regs {
 #define        APBH_CTRL2_CH1_ERROR_IRQ                        (1 << 1)
 #define        APBH_CTRL2_CH0_ERROR_IRQ                        (1 << 0)
 
 #define        APBH_CTRL2_CH1_ERROR_IRQ                        (1 << 1)
 #define        APBH_CTRL2_CH0_ERROR_IRQ                        (1 << 0)
 

-#if defined(CONFIG_MX28)
+#if defined(CONFIG_SOC_MX28)

 #define        APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK            (0xffff << 16)
 #define        APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET          16
 #define        APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0            (0x0001 << 16)
 #define        APBH_CHANNEL_CTRL_RESET_CHANNEL_MASK            (0xffff << 16)
 #define        APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET          16
 #define        APBH_CHANNEL_CTRL_RESET_CHANNEL_SSP0            (0x0001 << 16)


@@ -391,11 +391,11 @@ struct mxs_apbh_regs {
 #define        APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF          0x2000
 #endif
 
 #define        APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF          0x2000
 #endif
 

-#if defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_MX6)

 #define        APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET          16
 #endif
 
 #define        APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET          16
 #endif
 

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

 #define        APBH_DEVSEL_CH7_MASK                            (0xf << 28)
 #define        APBH_DEVSEL_CH7_OFFSET                          28
 #define        APBH_DEVSEL_CH6_MASK                            (0xf << 24)
 #define        APBH_DEVSEL_CH7_MASK                            (0xf << 28)
 #define        APBH_DEVSEL_CH7_OFFSET                          28
 #define        APBH_DEVSEL_CH6_MASK                            (0xf << 24)


@@ -412,7 +412,7 @@ struct mxs_apbh_regs {
 #define        APBH_DEVSEL_CH1_OFFSET                          4
 #define        APBH_DEVSEL_CH0_MASK                            (0xf << 0)
 #define        APBH_DEVSEL_CH0_OFFSET                          0
 #define        APBH_DEVSEL_CH1_OFFSET                          4
 #define        APBH_DEVSEL_CH0_MASK                            (0xf << 0)
 #define        APBH_DEVSEL_CH0_OFFSET                          0

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

 #define        APBH_DEVSEL_CH15_MASK                           (0x3 << 30)
 #define        APBH_DEVSEL_CH15_OFFSET                         30
 #define        APBH_DEVSEL_CH14_MASK                           (0x3 << 28)
 #define        APBH_DEVSEL_CH15_MASK                           (0x3 << 30)
 #define        APBH_DEVSEL_CH15_OFFSET                         30
 #define        APBH_DEVSEL_CH14_MASK                           (0x3 << 28)


@@ -447,7 +447,7 @@ struct mxs_apbh_regs {
 #define        APBH_DEVSEL_CH0_OFFSET                          0
 #endif
 
 #define        APBH_DEVSEL_CH0_OFFSET                          0
 #endif
 

-#if defined(CONFIG_MX28)
+#if defined(CONFIG_SOC_MX28)

 #define        APBH_DMA_BURST_SIZE_CH15_MASK                   (0x3 << 30)
 #define        APBH_DMA_BURST_SIZE_CH15_OFFSET                 30
 #define        APBH_DMA_BURST_SIZE_CH14_MASK                   (0x3 << 28)
 #define        APBH_DMA_BURST_SIZE_CH15_MASK                   (0x3 << 30)
 #define        APBH_DMA_BURST_SIZE_CH15_OFFSET                 30
 #define        APBH_DMA_BURST_SIZE_CH14_MASK                   (0x3 << 28)

diff --git a/arch/arm/include/asm/imx-common/regs-bch.h b/arch/arm/include/asm/imx-common/regs-bch.h
index 1ed5d94dd46e6294f03b8333722abfb78b173d43..dfd5f96896d9d9f8031682d82efe123d91572206 100644 (file)
--- a/arch/arm/include/asm/imx-common/regs-bch.h
+++ b/arch/arm/include/asm/imx-common/regs-bch.h
@@ -125,7 +125,7 @@ struct bch_regs {
 #define        BCH_FLASHLAYOUT0_NBLOCKS_OFFSET                 24
 #define        BCH_FLASHLAYOUT0_META_SIZE_MASK                 (0xff << 16)
 #define        BCH_FLASHLAYOUT0_META_SIZE_OFFSET               16
 #define        BCH_FLASHLAYOUT0_NBLOCKS_OFFSET                 24
 #define        BCH_FLASHLAYOUT0_META_SIZE_MASK                 (0xff << 16)
 #define        BCH_FLASHLAYOUT0_META_SIZE_OFFSET               16

-#if defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_MX6)

 #define        BCH_FLASHLAYOUT0_ECC0_MASK                      (0x1f << 11)
 #define        BCH_FLASHLAYOUT0_ECC0_OFFSET                    11
 #else
 #define        BCH_FLASHLAYOUT0_ECC0_MASK                      (0x1f << 11)
 #define        BCH_FLASHLAYOUT0_ECC0_OFFSET                    11
 #else


@@ -155,7 +155,7 @@ struct bch_regs {
 
 #define        BCH_FLASHLAYOUT1_PAGE_SIZE_MASK                 (0xffff << 16)
 #define        BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET               16
 
 #define        BCH_FLASHLAYOUT1_PAGE_SIZE_MASK                 (0xffff << 16)
 #define        BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET               16

-#if defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_MX6)

 #define        BCH_FLASHLAYOUT1_ECCN_MASK                      (0x1f << 11)
 #define        BCH_FLASHLAYOUT1_ECCN_OFFSET                    11
 #else
 #define        BCH_FLASHLAYOUT1_ECCN_MASK                      (0x1f << 11)
 #define        BCH_FLASHLAYOUT1_ECCN_OFFSET                    11
 #else

diff --git a/arch/arm/lib/asm-offsets.c b/arch/arm/lib/asm-offsets.c
index faafc627cd907d22bb9b805010964d9198e32815..5aee498d35784f9ddeb7086dc1e035e557b9b92c 100644 (file)
--- a/arch/arm/lib/asm-offsets.c
+++ b/arch/arm/lib/asm-offsets.c
@@ -18,11 +18,11 @@
 #if defined(CONFIG_MB86R0x)
 #include <asm/arch/mb86r0x.h>
 #endif
 #if defined(CONFIG_MB86R0x)
 #include <asm/arch/mb86r0x.h>
 #endif

-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) \
-       || defined(CONFIG_MX51) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX35) \
+       || defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)

 #include <asm/arch/imx-regs.h>
 #endif
 #include <asm/arch/imx-regs.h>
 #endif

-#if defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_MX6)

 #include <asm/arch/crm_regs.h>
 #endif
 
 #include <asm/arch/crm_regs.h>
 #endif
 


@@ -84,7 +84,7 @@ int main(void)
        DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4]));
 #endif
 
        DEFINE(MEMC_MCFAREA4, offsetof(struct mb86r0x_memc, mcfarea[4]));
 #endif
 

-#if defined(CONFIG_MX25)
+#if defined(CONFIG_SOC_MX25)

        /* Clock Control Module */
        DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
        DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));
        /* Clock Control Module */
        DEFINE(CCM_CCTL, offsetof(struct ccm_regs, cctl));
        DEFINE(CCM_CGCR0, offsetof(struct ccm_regs, cgr0));


@@ -120,7 +120,7 @@ int main(void)
        DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
 #endif
 
        DEFINE(AIPS_MPR_8_15, offsetof(struct aips_regs, mpr_8_15));
 #endif
 

-#if defined(CONFIG_MX27)
+#if defined(CONFIG_SOC_MX27)

        DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
        DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
        DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));
        DEFINE(AIPI1_PSR0, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr0));
        DEFINE(AIPI1_PSR1, IMX_AIPI1_BASE + offsetof(struct aipi_regs, psr1));
        DEFINE(AIPI2_PSR0, IMX_AIPI2_BASE + offsetof(struct aipi_regs, psr0));


@@ -146,7 +146,7 @@ int main(void)
                offsetof(struct system_control_regs, fmcr));
 #endif
 
                offsetof(struct system_control_regs, fmcr));
 #endif
 

-#if defined(CONFIG_MX35)
+#if defined(CONFIG_SOC_MX35)

        /* Round up to make sure size gives nice stack alignment */
        DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
        DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));
        /* Round up to make sure size gives nice stack alignment */
        DEFINE(CLKCTL_CCMR, offsetof(struct ccm_regs, ccmr));
        DEFINE(CLKCTL_PDR0, offsetof(struct ccm_regs, pdr0));


@@ -196,7 +196,7 @@ int main(void)
        DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
 #endif
 
        DEFINE(AIPS_OPACR_32_39, offsetof(struct aips_regs, opacr_32_39));
 #endif
 

-#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#if defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53)

        /* Round up to make sure size gives nice stack alignment */
        DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
        DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr));
        /* Round up to make sure size gives nice stack alignment */
        DEFINE(CLKCTL_CCMR, offsetof(struct clkctl, ccr));
        DEFINE(CLKCTL_CCDR, offsetof(struct clkctl, ccdr));


@@ -232,7 +232,7 @@ int main(void)
        DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
        DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
        DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor));
        DEFINE(CLKCTL_CCGR5, offsetof(struct clkctl, ccgr5));
        DEFINE(CLKCTL_CCGR6, offsetof(struct clkctl, ccgr6));
        DEFINE(CLKCTL_CMEOR, offsetof(struct clkctl, cmeor));

-#if defined(CONFIG_MX53)
+#if defined(CONFIG_SOC_MX53)

        DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
 #endif
 
        DEFINE(CLKCTL_CCGR7, offsetof(struct clkctl, ccgr7));
 #endif
 


@@ -246,7 +246,7 @@ int main(void)
        DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
        DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
 #endif
        DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
        DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
 #endif

-#if defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_MX6)

        DEFINE(CCM_CCR, offsetof(struct mxc_ccm_reg, ccr));
        DEFINE(CCM_CCDR, offsetof(struct mxc_ccm_reg, ccdr));
        DEFINE(CCM_CSR, offsetof(struct mxc_ccm_reg, csr));
        DEFINE(CCM_CCR, offsetof(struct mxc_ccm_reg, ccr));
        DEFINE(CCM_CCDR, offsetof(struct mxc_ccm_reg, ccdr));
        DEFINE(CCM_CSR, offsetof(struct mxc_ccm_reg, csr));

diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c
index 8edf8788edc1dcc69b774f77acd54dff758d4f4b..6a406915b07300b7a8f54527083140ef088e794c 100644 (file)
--- a/board/freescale/common/arm_sleep.c
+++ b/board/freescale/common/arm_sleep.c
@@ -14,7 +14,7 @@
 #include <asm/armv7.h>
 #include <asm/cache.h>
 
 #include <asm/armv7.h>
 #include <asm/cache.h>
 

-#if defined(CONFIG_LS102XA)
+#if defined(CONFIG_SOC_LS102XA)

 #include <asm/arch/immap_ls102xa.h>
 #endif
 
 #include <asm/arch/immap_ls102xa.h>
 #endif
 

diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c
index abe56c9e31da2b08cf34cb043af04e9ca7030500..89cb916de8240d9f83dcbd1912621370397a03df 100644 (file)
--- a/board/freescale/mx6qarm2/mx6qarm2.c
+++ b/board/freescale/mx6qarm2/mx6qarm2.c
@@ -33,7 +33,7 @@ DECLARE_GLOBAL_DATA_PTR;
 
 int dram_init(void)
 {
 
 int dram_init(void)
 {

-#if defined(CONFIG_MX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \
+#if defined(CONFIG_SOC_MX6DL) && !defined(CONFIG_MX6DL_LPDDR2) && \

        defined(CONFIG_DDR_32BIT)
        gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024) / 2;
 #else
        defined(CONFIG_DDR_32BIT)
        gd->ram_size = ((phys_size_t)CONFIG_DDR_MB * 1024 * 1024) / 2;
 #else


@@ -273,7 +273,7 @@ int board_init(void)
 
 int checkboard(void)
 {
 
 int checkboard(void)
 {

-#ifdef CONFIG_MX6DL
+#ifdef CONFIG_SOC_MX6DL

        puts("Board: MX6DL-Armadillo2\n");
 #else
        puts("Board: MX6Q-Armadillo2\n");
        puts("Board: MX6DL-Armadillo2\n");
 #else
        puts("Board: MX6Q-Armadillo2\n");

diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S
index 3161c227f3ae346476425cbd389f7fd3a8bbd3b3..16f78d3a5a08c6b8fc63a5f9ae210a8dd5102178 100644 (file)
--- a/board/karo/tx6/lowlevel_init.S
+++ b/board/karo/tx6/lowlevel_init.S
@@ -470,7 +470,7 @@ ivt_end:
 #define MMDC2_MPSWDRDR7                                0x021b48b4
 #endif
 
 #define MMDC2_MPSWDRDR7                                0x021b48b4
 #endif
 

-#ifdef CONFIG_MX6Q
+#ifdef CONFIG_SOC_MX6Q

 #define IOMUXC_GPR1                            0x020e0004
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17           0x020e024c
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7                0x020e02a8
 #define IOMUXC_GPR1                            0x020e0004
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17           0x020e024c
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7                0x020e02a8


@@ -565,7 +565,7 @@ ivt_end:
 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0920
 #endif
 
 #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0920
 #endif
 

-#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)

 #define IOMUXC_GPR1                            0x020e0004
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17           0x020e0218
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7                0x020e0330
 #define IOMUXC_GPR1                            0x020e0004
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17           0x020e0218
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7                0x020e0330


@@ -681,7 +681,7 @@ dcd_hdr:
        /* UART1 pad config */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7,        0x00000001)        /* UART1 TXD */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6,        0x00000001)        /* UART1 RXD */
        /* UART1 pad config */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7,        0x00000001)        /* UART1 TXD */
        MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6,        0x00000001)        /* UART1 RXD */

-#ifdef CONFIG_MX6Q
+#ifdef CONFIG_SOC_MX6Q

        MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003)        /* UART1 RXD INPUT_SEL */
 #else
        MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000002)        /* UART1 RXD INPUT_SEL */
        MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003)        /* UART1 RXD INPUT_SEL */
 #else
        MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000002)        /* UART1 RXD INPUT_SEL */


@@ -782,7 +782,7 @@ dcd_hdr:
        /* DDRHYS */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRHYS, 0x00000000)
 
        /* DDRHYS */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRHYS, 0x00000000)
 

-#ifdef CONFIG_MX6Q
+#ifdef CONFIG_SOC_MX6Q

        /* TERM_CTL[0..7] */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0, ODT_MASK)
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1, ODT_MASK)
        /* TERM_CTL[0..7] */
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0, ODT_MASK)
        MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1, ODT_MASK)

diff --git a/board/tqc/tqma6/tqma6_mba6.c b/board/tqc/tqma6/tqma6_mba6.c
index 6f4cffd95ecd3b3dbf1df181f9998f7936a5f570..bfbe8db11c66744039f1ca5c1bd1189f7aee8263 100644 (file)
--- a/board/tqc/tqma6/tqma6_mba6.c
+++ b/board/tqc/tqma6/tqma6_mba6.c
@@ -54,12 +54,12 @@ DECLARE_GLOBAL_DATA_PTR;
        PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
        PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 
        PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
        PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 

-#if defined(CONFIG_MX6Q)
+#if defined(CONFIG_SOC_MX6Q)

 
 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII   0x02e0790
 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM       0x02e07ac
 
 
 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII   0x02e0790
 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM       0x02e07ac
 

-#elif defined(CONFIG_MX6S)
+#elif defined(CONFIG_SOC_MX6S)

 
 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII   0x02e0768
 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM       0x02e0788
 
 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII   0x02e0768
 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM       0x02e0788


@@ -261,12 +261,12 @@ int board_phy_config(struct phy_device *phydev)
  * optimized pad skew values depends on CPU variant on the TQMa6x module:
  * i.MX6Q/D or i.MX6DL/S
  */
  * optimized pad skew values depends on CPU variant on the TQMa6x module:
  * i.MX6Q/D or i.MX6DL/S
  */

-#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6Q)
+#if defined(CONFIG_SOC_MX6Q) || defined(CONFIG_SOC_MX6Q)

 #define MBA6X_KSZ9031_CTRL_SKEW        0x0032
 #define MBA6X_KSZ9031_CLK_SKEW 0x03ff
 #define MBA6X_KSZ9031_RX_SKEW  0x3333
 #define MBA6X_KSZ9031_TX_SKEW  0x2036
 #define MBA6X_KSZ9031_CTRL_SKEW        0x0032
 #define MBA6X_KSZ9031_CLK_SKEW 0x03ff
 #define MBA6X_KSZ9031_RX_SKEW  0x3333
 #define MBA6X_KSZ9031_TX_SKEW  0x2036

-#elif defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#elif defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)

 #define MBA6X_KSZ9031_CTRL_SKEW        0x0030
 #define MBA6X_KSZ9031_CLK_SKEW 0x03ff
 #define MBA6X_KSZ9031_RX_SKEW  0x3333
 #define MBA6X_KSZ9031_CTRL_SKEW        0x0030
 #define MBA6X_KSZ9031_CLK_SKEW 0x03ff
 #define MBA6X_KSZ9031_RX_SKEW  0x3333

diff --git a/configs/tx6q-1020_defconfig b/configs/tx6q-1020_defconfig
index d62964eab6a3ea024207b8fd81c69c99bde5cc57..32e15c4ec4e92d82505d5142452c27f2d627f2ec 100644 (file)
--- a/configs/tx6q-1020_defconfig
+++ b/configs/tx6q-1020_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="TX6_REV=0x2"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="TX6_REV=0x2"
 CONFIG_ARM=y

-CONFIG_MX6Q=y
+CONFIG_SOC_MX6Q=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_1020=y
 CONFIG_TX6_UBOOT=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_1020=y
 CONFIG_TX6_UBOOT=y

diff --git a/configs/tx6q-1020_mfg_defconfig b/configs/tx6q-1020_mfg_defconfig
index 8e62eba7c1bc078821059771346860a1804c4076..bb73a743c5afe1340d1a58a04c31c23aba7cbae1 100644 (file)
--- a/configs/tx6q-1020_mfg_defconfig
+++ b/configs/tx6q-1020_mfg_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="TX6_REV=0x2"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="TX6_REV=0x2"
 CONFIG_ARM=y

-CONFIG_MX6Q=y
+CONFIG_SOC_MX6Q=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_1020=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_1020=y
 CONFIG_TX6_UBOOT_MFG=y

diff --git a/configs/tx6q-1020_noenv_defconfig b/configs/tx6q-1020_noenv_defconfig
index 561c83802c32ac34b171733d414d07d82f56eb1c..577e54317a3ba79f29768b8848a11168c58200ce 100644 (file)
--- a/configs/tx6q-1020_noenv_defconfig
+++ b/configs/tx6q-1020_noenv_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="TX6_REV=0x2"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="TX6_REV=0x2"
 CONFIG_ARM=y

-CONFIG_MX6Q=y
+CONFIG_SOC_MX6Q=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_1020=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_1020=y
 CONFIG_TX6_UBOOT_NOENV=y

diff --git a/configs/tx6q-10x0_defconfig b/configs/tx6q-10x0_defconfig
index 5a81bc21cec3c8d6b52677929d1d10decb13c441..91960a8fb9661ce18b6916c6f2cffc04c7c6a2fd 100644 (file)
--- a/configs/tx6q-10x0_defconfig
+++ b/configs/tx6q-10x0_defconfig
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARM=y

-CONFIG_MX6Q=y
+CONFIG_SOC_MX6Q=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_10X0=y
 CONFIG_TX6_UBOOT=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_10X0=y
 CONFIG_TX6_UBOOT=y

diff --git a/configs/tx6q-10x0_mfg_defconfig b/configs/tx6q-10x0_mfg_defconfig
index 485e571cac7edc59f9ebba13772d788464b530b6..20e3d1a2552cb665c7a8e6a2f7eca5198e88be4f 100644 (file)
--- a/configs/tx6q-10x0_mfg_defconfig
+++ b/configs/tx6q-10x0_mfg_defconfig
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARM=y

-CONFIG_MX6Q=y
+CONFIG_SOC_MX6Q=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_10X0=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_10X0=y
 CONFIG_TX6_UBOOT_MFG=y

diff --git a/configs/tx6q-10x0_noenv_defconfig b/configs/tx6q-10x0_noenv_defconfig
index 683149a741dc23d199dca6574a5d4463f0a4ba91..b896343293345fec40067a41539e8501937a26c1 100644 (file)
--- a/configs/tx6q-10x0_noenv_defconfig
+++ b/configs/tx6q-10x0_noenv_defconfig
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARM=y

-CONFIG_MX6Q=y
+CONFIG_SOC_MX6Q=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_10X0=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_10X0=y
 CONFIG_TX6_UBOOT_NOENV=y

diff --git a/configs/tx6q-11x0_defconfig b/configs/tx6q-11x0_defconfig
index baa968b9298903a7b5a0fcf4354c4cc3a1266bff..adb4622370092fc4279f7a0adb9a85111fba93bd 100644 (file)
--- a/configs/tx6q-11x0_defconfig
+++ b/configs/tx6q-11x0_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
 CONFIG_ARM=y

-CONFIG_MX6Q=y
+CONFIG_SOC_MX6Q=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_11X0=y
 CONFIG_TX6_UBOOT=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_11X0=y
 CONFIG_TX6_UBOOT=y

diff --git a/configs/tx6q-11x0_mfg_defconfig b/configs/tx6q-11x0_mfg_defconfig
index 948cd699b31a106ad4ead5383c5c83ca0801865f..91e13853db081df84afdaa1b67acf27ae6370d54 100644 (file)
--- a/configs/tx6q-11x0_mfg_defconfig
+++ b/configs/tx6q-11x0_mfg_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
 CONFIG_ARM=y

-CONFIG_MX6Q=y
+CONFIG_SOC_MX6Q=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_11X0=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_11X0=y
 CONFIG_TX6_UBOOT_MFG=y

diff --git a/configs/tx6q-11x0_noenv_defconfig b/configs/tx6q-11x0_noenv_defconfig
index 0f9f735c97a1921f60729ec892d42015e2e30014..6068f63e9ae54e229ae21ecb19698d6333d52f39 100644 (file)
--- a/configs/tx6q-11x0_noenv_defconfig
+++ b/configs/tx6q-11x0_noenv_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
 CONFIG_ARM=y

-CONFIG_MX6Q=y
+CONFIG_SOC_MX6Q=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_11X0=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6Q_11X0=y
 CONFIG_TX6_UBOOT_NOENV=y

diff --git a/configs/tx6s-8034_defconfig b/configs/tx6s-8034_defconfig
index c4688a08a0c7530849d7cc3301113fe4e14bd97c..4917287bf4df54131dd8f9e2d9d220852be7f81e 100644 (file)
--- a/configs/tx6s-8034_defconfig
+++ b/configs/tx6s-8034_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=16"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=16"
 CONFIG_ARM=y

-CONFIG_MX6S=y
+CONFIG_SOC_MX6S=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6S_8034=y
 CONFIG_TX6_UBOOT=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6S_8034=y
 CONFIG_TX6_UBOOT=y

diff --git a/configs/tx6s-8034_mfg_defconfig b/configs/tx6s-8034_mfg_defconfig
index 491519788ca4506f9d0fbcbb17d23f850916b69a..6899025f90b14d1e3fedfc2c8cf6a298d436b50b 100644 (file)
--- a/configs/tx6s-8034_mfg_defconfig
+++ b/configs/tx6s-8034_mfg_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=16"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=16"
 CONFIG_ARM=y

-CONFIG_MX6S=y
+CONFIG_SOC_MX6S=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6S_8034=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6S_8034=y
 CONFIG_TX6_UBOOT_MFG=y

diff --git a/configs/tx6s-8034_noenv_defconfig b/configs/tx6s-8034_noenv_defconfig
index e0dca28be7bf069241348863ede9399ab749b512..220585e74be049fbcc25d082b2dd53a1095513e3 100644 (file)
--- a/configs/tx6s-8034_noenv_defconfig
+++ b/configs/tx6s-8034_noenv_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=16"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=16"
 CONFIG_ARM=y

-CONFIG_MX6S=y
+CONFIG_SOC_MX6S=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6S_8034=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6S_8034=y
 CONFIG_TX6_UBOOT_NOENV=y

diff --git a/configs/tx6s-8035_defconfig b/configs/tx6s-8035_defconfig
index dff5bc264b085c80874ddacf6b6cc9d16fab5edb..874704a249bb49e55b9ae7404a83ec3a4f42b7ae 100644 (file)
--- a/configs/tx6s-8035_defconfig
+++ b/configs/tx6s-8035_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_SDRAM_BUS_WIDTH=32"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_SDRAM_BUS_WIDTH=32"
 CONFIG_ARM=y

-CONFIG_MX6S=y
+CONFIG_SOC_MX6S=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6S_8035=y
 CONFIG_TX6_UBOOT=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6S_8035=y
 CONFIG_TX6_UBOOT=y

diff --git a/configs/tx6s-8035_mfg_defconfig b/configs/tx6s-8035_mfg_defconfig
index 15ac9306584ce94d0b97b9b718a44ab5a87af794..158c9b9156bf3e026b35ec0b55632a65d59d4f32 100644 (file)
--- a/configs/tx6s-8035_mfg_defconfig
+++ b/configs/tx6s-8035_mfg_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_SDRAM_BUS_WIDTH=32"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_SDRAM_BUS_WIDTH=32"
 CONFIG_ARM=y

-CONFIG_MX6S=y
+CONFIG_SOC_MX6S=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6S_8035=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6S_8035=y
 CONFIG_TX6_UBOOT_MFG=y

diff --git a/configs/tx6s-8035_noenv_defconfig b/configs/tx6s-8035_noenv_defconfig
index 00e824594fda400e6c29aecf4ed001cc254b3706..f704e1772df8ff3ff7117c05abc4fa6047d0e688 100644 (file)
--- a/configs/tx6s-8035_noenv_defconfig
+++ b/configs/tx6s-8035_noenv_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_SDRAM_BUS_WIDTH=32"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024,SYS_SDRAM_BUS_WIDTH=32"
 CONFIG_ARM=y

-CONFIG_MX6S=y
+CONFIG_SOC_MX6S=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6S_8035=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6S_8035=y
 CONFIG_TX6_UBOOT_NOENV=y

diff --git a/configs/tx6u-8011_defconfig b/configs/tx6u-8011_defconfig
index c0708d7df30d4c32d1b25876f4a9df954aed203a..c055fb15d2d735f5fe987e68be77e1ce667e0f99 100644 (file)
--- a/configs/tx6u-8011_defconfig
+++ b/configs/tx6u-8011_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32"
 CONFIG_ARM=y

-CONFIG_MX6DL=y
+CONFIG_SOC_MX6DL=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8011=y
 CONFIG_TX6_UBOOT=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8011=y
 CONFIG_TX6_UBOOT=y

diff --git a/configs/tx6u-8011_mfg_defconfig b/configs/tx6u-8011_mfg_defconfig
index 320f9ec03e9263ddd9a522cdc735ebd93ab73c57..5e1b5cf478f1ef566e96a6a127350bce4fdcdb88 100644 (file)
--- a/configs/tx6u-8011_mfg_defconfig
+++ b/configs/tx6u-8011_mfg_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32"
 CONFIG_ARM=y

-CONFIG_MX6DL=y
+CONFIG_SOC_MX6DL=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8011=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8011=y
 CONFIG_TX6_UBOOT_MFG=y

diff --git a/configs/tx6u-8011_noenv_defconfig b/configs/tx6u-8011_noenv_defconfig
index 0e705be15fe5927b1516796a14a939b6538e4b9d..c1cc683e2dc940d8d210de825a749054d0c740f5 100644 (file)
--- a/configs/tx6u-8011_noenv_defconfig
+++ b/configs/tx6u-8011_noenv_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32"
 CONFIG_ARM=y

-CONFIG_MX6DL=y
+CONFIG_SOC_MX6DL=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8011=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8011=y
 CONFIG_TX6_UBOOT_NOENV=y

diff --git a/configs/tx6u-8012_defconfig b/configs/tx6u-8012_defconfig
index 7e73d0bb332c11b8e44820eb04996f6dba6054ad..86e8ce8424ad748479e421e33c049f882ace4835 100644 (file)
--- a/configs/tx6u-8012_defconfig
+++ b/configs/tx6u-8012_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCKS=2048"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCKS=2048"
 CONFIG_ARM=y

-CONFIG_MX6DL=y
+CONFIG_SOC_MX6DL=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8012=y
 CONFIG_TX6_UBOOT=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8012=y
 CONFIG_TX6_UBOOT=y

diff --git a/configs/tx6u-8012_mfg_defconfig b/configs/tx6u-8012_mfg_defconfig
index 1ea69174adb5519d4e625888d1ca18c6c7b4c53f..722b295b3ee5703064187fab2b7b3e2afb3e9f53 100644 (file)
--- a/configs/tx6u-8012_mfg_defconfig
+++ b/configs/tx6u-8012_mfg_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCKS=2048"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCKS=2048"
 CONFIG_ARM=y

-CONFIG_MX6DL=y
+CONFIG_SOC_MX6DL=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8012=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8012=y
 CONFIG_TX6_UBOOT_MFG=y

diff --git a/configs/tx6u-8012_noenv_defconfig b/configs/tx6u-8012_noenv_defconfig
index cf633b21ac33169815b27ce8fbbf00925a8c47f3..e2c48190051381ca946c54d11962cd5d6872d757 100644 (file)
--- a/configs/tx6u-8012_noenv_defconfig
+++ b/configs/tx6u-8012_noenv_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCKS=2048"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_NAND_BLOCKS=2048"
 CONFIG_ARM=y

-CONFIG_MX6DL=y
+CONFIG_SOC_MX6DL=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8012=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8012=y
 CONFIG_TX6_UBOOT_NOENV=y

diff --git a/configs/tx6u-8033_defconfig b/configs/tx6u-8033_defconfig
index 8b8a07c129ff1f1f08fc231e0258562a6c9f2b58..6e37e6b16ed3eb022be2b542f74c9f845fc32fa3 100644 (file)
--- a/configs/tx6u-8033_defconfig
+++ b/configs/tx6u-8033_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
 CONFIG_ARM=y

-CONFIG_MX6DL=y
+CONFIG_SOC_MX6DL=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8033=y
 CONFIG_TX6_UBOOT=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8033=y
 CONFIG_TX6_UBOOT=y

diff --git a/configs/tx6u-8033_mfg_defconfig b/configs/tx6u-8033_mfg_defconfig
index 9f5e2337b43265cfc859135c4dad7a3347f37f01..4597a1d7d5b7fd70908736fefb5a4c3413537fed 100644 (file)
--- a/configs/tx6u-8033_mfg_defconfig
+++ b/configs/tx6u-8033_mfg_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
 CONFIG_ARM=y

-CONFIG_MX6DL=y
+CONFIG_SOC_MX6DL=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8033=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8033=y
 CONFIG_TX6_UBOOT_MFG=y

diff --git a/configs/tx6u-8033_noenv_defconfig b/configs/tx6u-8033_noenv_defconfig
index 7febbd6b529d32a7b5ec424c7df6f0a1f26c980f..eeb1615aecf4ffcda41151a16992105cfc109a70 100644 (file)
--- a/configs/tx6u-8033_noenv_defconfig
+++ b/configs/tx6u-8033_noenv_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="MMC_BOOT_SIZE=1024"
 CONFIG_ARM=y

-CONFIG_MX6DL=y
+CONFIG_SOC_MX6DL=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8033=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_8033=y
 CONFIG_TX6_UBOOT_NOENV=y

diff --git a/configs/tx6u-80x0_defconfig b/configs/tx6u-80x0_defconfig
index 4b3ea1b1da57ac420e0f4a38906c591d44a0101e..dd728acd74e4ed3327d6fe425005bb1810b406fa 100644 (file)
--- a/configs/tx6u-80x0_defconfig
+++ b/configs/tx6u-80x0_defconfig
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARM=y

-CONFIG_MX6DL=y
+CONFIG_SOC_MX6DL=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_80X0=y
 CONFIG_TX6_UBOOT=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_80X0=y
 CONFIG_TX6_UBOOT=y

diff --git a/configs/tx6u-80x0_mfg_defconfig b/configs/tx6u-80x0_mfg_defconfig
index ea4e195ff43a16861cbcf64b1bdfd51e4bd6abe6..939016e68d6c9e3a34b54cf9ca2dc71bb2a1a2e7 100644 (file)
--- a/configs/tx6u-80x0_mfg_defconfig
+++ b/configs/tx6u-80x0_mfg_defconfig
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARM=y

-CONFIG_MX6DL=y
+CONFIG_SOC_MX6DL=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_80X0=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_80X0=y
 CONFIG_TX6_UBOOT_MFG=y

diff --git a/configs/tx6u-80x0_noenv_defconfig b/configs/tx6u-80x0_noenv_defconfig
index 46be18a7a6fe65caf85def6f8a3afc6c9f7d3c1b..39654718f0853c69a94997ece85e55d97e920a6a 100644 (file)
--- a/configs/tx6u-80x0_noenv_defconfig
+++ b/configs/tx6u-80x0_noenv_defconfig
@@ -1,5 +1,5 @@
 CONFIG_ARM=y
 CONFIG_ARM=y

-CONFIG_MX6DL=y
+CONFIG_SOC_MX6DL=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_80X0=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_80X0=y
 CONFIG_TX6_UBOOT_NOENV=y

diff --git a/configs/tx6u-8111_defconfig b/configs/tx6u-8111_defconfig
index 7a5850fb57ac64f522818967d7ee152d8ef736c8..0c61bc5524455c2180c7f629d725ff82ef08c397 100644 (file)
--- a/configs/tx6u-8111_defconfig
+++ b/configs/tx6u-8111_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF"
 CONFIG_ARM=y

-CONFIG_MX6DL=y
+CONFIG_SOC_MX6DL=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_81X0=y
 CONFIG_TX6_UBOOT=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_81X0=y
 CONFIG_TX6_UBOOT=y

diff --git a/configs/tx6u-8111_mfg_defconfig b/configs/tx6u-8111_mfg_defconfig
index 1946385126396448d9f6f5320921147650ae5f4a..91770aa82190cee1126a402ec3302107ee54bb42 100644 (file)
--- a/configs/tx6u-8111_mfg_defconfig
+++ b/configs/tx6u-8111_mfg_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF"
 CONFIG_ARM=y

-CONFIG_MX6DL=y
+CONFIG_SOC_MX6DL=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_81X0=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_81X0=y
 CONFIG_TX6_UBOOT_MFG=y

diff --git a/configs/tx6u-8111_noenv_defconfig b/configs/tx6u-8111_noenv_defconfig
index ec5842d683915453d3935ce6a1522ddab6e2658a..9dd4b893a673b12dbb4878e874ea4f51f97ba2ff 100644 (file)
--- a/configs/tx6u-8111_noenv_defconfig
+++ b/configs/tx6u-8111_noenv_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF"
 CONFIG_ARM=y

-CONFIG_MX6DL=y
+CONFIG_SOC_MX6DL=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_81X0=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_81X0=y
 CONFIG_TX6_UBOOT_NOENV=y

diff --git a/configs/tx6u-81x0_defconfig b/configs/tx6u-81x0_defconfig
index ccd6acc72b10c46a87d7f45fd848574123f460c1..88b267c4f5d7ef1e57426e391884a8d1e4eb953c 100644 (file)
--- a/configs/tx6u-81x0_defconfig
+++ b/configs/tx6u-81x0_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
 CONFIG_ARM=y

-CONFIG_MX6DL=y
+CONFIG_SOC_MX6DL=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_81X0=y
 CONFIG_TX6_UBOOT=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_81X0=y
 CONFIG_TX6_UBOOT=y

diff --git a/configs/tx6u-81x0_mfg_defconfig b/configs/tx6u-81x0_mfg_defconfig
index abbc52600af73d39da0cd7e8694012c0a1a08ffd..b9b4bdedd667b514ce52f3bf278bea7a5c8f1658 100644 (file)
--- a/configs/tx6u-81x0_mfg_defconfig
+++ b/configs/tx6u-81x0_mfg_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
 CONFIG_ARM=y

-CONFIG_MX6DL=y
+CONFIG_SOC_MX6DL=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_81X0=y
 CONFIG_TX6_UBOOT_MFG=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_81X0=y
 CONFIG_TX6_UBOOT_MFG=y

diff --git a/configs/tx6u-81x0_noenv_defconfig b/configs/tx6u-81x0_noenv_defconfig
index 2419364a0de4617ee75030a8260f1854963e59b9..616429a3c7ced291d073fcb7e81866a638434164 100644 (file)
--- a/configs/tx6u-81x0_noenv_defconfig
+++ b/configs/tx6u-81x0_noenv_defconfig
@@ -1,6 +1,6 @@
 CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
 CONFIG_ARM=y
 CONFIG_SYS_EXTRA_OPTIONS="SYS_LVDS_IF"
 CONFIG_ARM=y

-CONFIG_MX6DL=y
+CONFIG_SOC_MX6DL=y

 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_81X0=y
 CONFIG_TX6_UBOOT_NOENV=y
 CONFIG_TARGET_TX6=y
 CONFIG_TARGET_TX6U_81X0=y
 CONFIG_TX6_UBOOT_NOENV=y

diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
index 01a4148a5201ebe4738fdd399d5354068e4c614c..30cc4e8cb930718cad68bcc489288b22b1e8afd9 100644 (file)
--- a/drivers/block/dwc_ahsata.c
+++ b/drivers/block/dwc_ahsata.c
@@ -559,7 +559,7 @@ int init_sata(int dev)
        u32 linkmap;
        struct ahci_probe_ent *probe_ent = NULL;
 
        u32 linkmap;
        struct ahci_probe_ent *probe_ent = NULL;
 

-#if defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_MX6)

        if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
                return 1;
 #endif
        if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
                return 1;
 #endif

diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 25cc5f80c8723a42be1480a6bdaf39ddfc2711d6..a6da34198c9935cdad270ace15104b116856d8b7 100644 (file)
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -1,7 +1,7 @@
 config APBH_DMA
        bool "Freescale MXS and i.MX6 APBH DMA support"
        default y
 config APBH_DMA
        bool "Freescale MXS and i.MX6 APBH DMA support"
        default y

-       depends on MX28 || MX6
+       depends on SOC_MX28 || SOC_MX6

 
 config APBH_DMA_BURST
        bool "Enable DMA burst mode"
 
 config APBH_DMA_BURST
        bool "Enable DMA burst mode"

diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c
index 983111ad29e8a18b360322ba09b908cc4785eb8a..4c5732e76e4cffb4bcce8a411d3f98808569b134 100644 (file)
--- a/drivers/dma/apbh_dma.c
+++ b/drivers/dma/apbh_dma.c
@@ -210,10 +210,10 @@ static int mxs_dma_disable(int channel)
 static int mxs_dma_reset(int channel)
 {
        int ret;
 static int mxs_dma_reset(int channel)
 {
        int ret;

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

        uint32_t *setreg = &apbh_regs->hw_apbh_ctrl0_set;
        uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET;
        uint32_t *setreg = &apbh_regs->hw_apbh_ctrl0_set;
        uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET;

-#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6))
+#elif (defined(CONFIG_SOC_MX28) || defined(CONFIG_SOC_MX6))

        uint32_t *setreg = &apbh_regs->hw_apbh_channel_ctrl_set;
        uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET;
 #endif
        uint32_t *setreg = &apbh_regs->hw_apbh_channel_ctrl_set;
        uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET;
 #endif

diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index a46d33e8d91b49e5861681b7546082d8a27648ed..125f24c609c5af79eb6456ab0d4004ce7687f7f6 100644 (file)
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -38,15 +38,15 @@ static unsigned long gpio_ports[] = {
        [0] = GPIO1_BASE_ADDR,
        [1] = GPIO2_BASE_ADDR,
        [2] = GPIO3_BASE_ADDR,
        [0] = GPIO1_BASE_ADDR,
        [1] = GPIO2_BASE_ADDR,
        [2] = GPIO3_BASE_ADDR,

-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
-               defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX51) || \
+               defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)

        [3] = GPIO4_BASE_ADDR,
 #endif
        [3] = GPIO4_BASE_ADDR,
 #endif

-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)

        [4] = GPIO5_BASE_ADDR,
        [5] = GPIO6_BASE_ADDR,
 #endif
        [4] = GPIO5_BASE_ADDR,
        [5] = GPIO6_BASE_ADDR,
 #endif

-#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)

        [6] = GPIO7_BASE_ADDR,
 #endif
 };
        [6] = GPIO7_BASE_ADDR,
 #endif
 };


@@ -280,15 +280,15 @@ static const struct mxc_gpio_plat mxc_plat[] = {
        { (struct gpio_regs *)GPIO1_BASE_ADDR },
        { (struct gpio_regs *)GPIO2_BASE_ADDR },
        { (struct gpio_regs *)GPIO3_BASE_ADDR },
        { (struct gpio_regs *)GPIO1_BASE_ADDR },
        { (struct gpio_regs *)GPIO2_BASE_ADDR },
        { (struct gpio_regs *)GPIO3_BASE_ADDR },

-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
-               defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX51) || \
+               defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)

        { (struct gpio_regs *)GPIO4_BASE_ADDR },
 #endif
        { (struct gpio_regs *)GPIO4_BASE_ADDR },
 #endif

-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)

        { (struct gpio_regs *)GPIO5_BASE_ADDR },
        { (struct gpio_regs *)GPIO6_BASE_ADDR },
 #endif
        { (struct gpio_regs *)GPIO5_BASE_ADDR },
        { (struct gpio_regs *)GPIO6_BASE_ADDR },
 #endif

-#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)

        { (struct gpio_regs *)GPIO7_BASE_ADDR },
 #endif
 };
        { (struct gpio_regs *)GPIO7_BASE_ADDR },
 #endif
 };


@@ -325,15 +325,15 @@ U_BOOT_DEVICES(mxc_gpios) = {
        { "gpio_mxc", &mxc_plat[0] },
        { "gpio_mxc", &mxc_plat[1] },
        { "gpio_mxc", &mxc_plat[2] },
        { "gpio_mxc", &mxc_plat[0] },
        { "gpio_mxc", &mxc_plat[1] },
        { "gpio_mxc", &mxc_plat[2] },

-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX51) || \
-               defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX51) || \
+               defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)

        { "gpio_mxc", &mxc_plat[3] },
 #endif
        { "gpio_mxc", &mxc_plat[3] },
 #endif

-#if defined(CONFIG_MX27) || defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)

        { "gpio_mxc", &mxc_plat[4] },
        { "gpio_mxc", &mxc_plat[5] },
 #endif
        { "gpio_mxc", &mxc_plat[4] },
        { "gpio_mxc", &mxc_plat[5] },
 #endif

-#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6)

        { "gpio_mxc", &mxc_plat[6] },
 #endif
 };
        { "gpio_mxc", &mxc_plat[6] },
 #endif
 };

diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c
index da0199b168ad68c8c69307e829c8fa715e3a86e4..cc7c225ccdbf059638841afde3eebe0a2b630fde 100644 (file)
--- a/drivers/gpio/mxs_gpio.c
+++ b/drivers/gpio/mxs_gpio.c
@@ -14,7 +14,7 @@
 #include <asm/arch/iomux.h>
 #include <asm/arch/imx-regs.h>
 
 #include <asm/arch/iomux.h>
 #include <asm/arch/imx-regs.h>
 

-#if    defined(CONFIG_MX23)
+#if    defined(CONFIG_SOC_MX23)

 #define        PINCTRL_BANKS           3
 #define        PINCTRL_DOUT(n)         (0x0500 + ((n) * 0x10))
 #define        PINCTRL_DIN(n)          (0x0600 + ((n) * 0x10))
 #define        PINCTRL_BANKS           3
 #define        PINCTRL_DOUT(n)         (0x0500 + ((n) * 0x10))
 #define        PINCTRL_DIN(n)          (0x0600 + ((n) * 0x10))


@@ -22,7 +22,7 @@
 #define        PINCTRL_PIN2IRQ(n)      (0x0800 + ((n) * 0x10))
 #define        PINCTRL_IRQEN(n)        (0x0900 + ((n) * 0x10))
 #define        PINCTRL_IRQSTAT(n)      (0x0c00 + ((n) * 0x10))
 #define        PINCTRL_PIN2IRQ(n)      (0x0800 + ((n) * 0x10))
 #define        PINCTRL_IRQEN(n)        (0x0900 + ((n) * 0x10))
 #define        PINCTRL_IRQSTAT(n)      (0x0c00 + ((n) * 0x10))

-#elif  defined(CONFIG_MX28)
+#elif  defined(CONFIG_SOC_MX28)

 #define        PINCTRL_BANKS           5
 #define        PINCTRL_DOUT(n)         (0x0700 + ((n) * 0x10))
 #define        PINCTRL_DIN(n)          (0x0900 + ((n) * 0x10))
 #define        PINCTRL_BANKS           5
 #define        PINCTRL_DOUT(n)         (0x0700 + ((n) * 0x10))
 #define        PINCTRL_DIN(n)          (0x0900 + ((n) * 0x10))


@@ -31,7 +31,7 @@
 #define        PINCTRL_IRQEN(n)        (0x1100 + ((n) * 0x10))
 #define        PINCTRL_IRQSTAT(n)      (0x1400 + ((n) * 0x10))
 #else
 #define        PINCTRL_IRQEN(n)        (0x1100 + ((n) * 0x10))
 #define        PINCTRL_IRQSTAT(n)      (0x1400 + ((n) * 0x10))
 #else

-#error "Please select CONFIG_MX23 or CONFIG_MX28"
+#error "Please select CONFIG_SOC_MX23 or CONFIG_SOC_MX28"

 #endif
 
 #define GPIO_INT_FALL_EDGE     0x0
 #endif
 
 #define GPIO_INT_FALL_EDGE     0x0

diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 8babe12159fee027a7c24559141aba7e4fe52756..c3e8d226ac4cca170e8d69447e905acc841e9b37 100644 (file)
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -31,6 +31,6 @@ config HARD_I2C
 config SYS_I2C_MXC
        bool "Freescale i.MX I2C controller"
        select HARD_I2C
 config SYS_I2C_MXC
        bool "Freescale i.MX I2C controller"
        select HARD_I2C

-       select I2C_QUIRK_REG if FSL_LSCH3 || LS102XA
+       select I2C_QUIRK_REG if FSL_LSCH3 || SOC_LS102XA

 
 endif
 
 endif

diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c
index fc5ee35a1ad9ec421de06ae6ba854289eac0bc52..da55c6b9b7420ad3fc08ea58400b6beb1220490f 100644 (file)
--- a/drivers/i2c/mxc_i2c.c
+++ b/drivers/i2c/mxc_i2c.c
@@ -135,7 +135,7 @@ static uint8_t i2c_imx_get_clk(unsigned int rate)
        unsigned int div;
        u8 clk_div;
 
        unsigned int div;
        u8 clk_div;
 

-#if defined(CONFIG_MX31)
+#if defined(CONFIG_SOC_MX31)

        struct clock_control_regs *sc_regs =
                (struct clock_control_regs *)CCM_BASE;
 
        struct clock_control_regs *sc_regs =
                (struct clock_control_regs *)CCM_BASE;
 


@@ -403,20 +403,20 @@ int bus_i2c_write(void *base, uchar chip, uint addr, int alen,
 }
 
 static void * const i2c_bases[] = {
 }
 
 static void * const i2c_bases[] = {

-#if defined(CONFIG_MX25)
+#if defined(CONFIG_SOC_MX25)

        (void *)IMX_I2C_BASE,
        (void *)IMX_I2C2_BASE,
        (void *)IMX_I2C3_BASE
        (void *)IMX_I2C_BASE,
        (void *)IMX_I2C2_BASE,
        (void *)IMX_I2C3_BASE

-#elif defined(CONFIG_MX27)
+#elif defined(CONFIG_SOC_MX27)

        (void *)IMX_I2C1_BASE,
        (void *)IMX_I2C2_BASE
        (void *)IMX_I2C1_BASE,
        (void *)IMX_I2C2_BASE

-#elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \
-       defined(CONFIG_MX51) || defined(CONFIG_MX53) || \
-       defined(CONFIG_MX6) || defined(CONFIG_LS102XA)
+#elif defined(CONFIG_SOC_MX31) || defined(CONFIG_SOC_MX35) || \
+       defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53) || \
+       defined(CONFIG_SOC_MX6) || defined(CONFIG_SOC_LS102XA)

        (void *)I2C1_BASE_ADDR,
        (void *)I2C2_BASE_ADDR,
        (void *)I2C3_BASE_ADDR
        (void *)I2C1_BASE_ADDR,
        (void *)I2C2_BASE_ADDR,
        (void *)I2C3_BASE_ADDR

-#elif defined(CONFIG_VF610)
+#elif defined(CONFIG_SOC_VF610)

        (void *)I2C0_BASE_ADDR
 #elif defined(CONFIG_FSL_LSCH3)
        (void *)I2C1_BASE_ADDR,
        (void *)I2C0_BASE_ADDR
 #elif defined(CONFIG_FSL_LSCH3)
        (void *)I2C1_BASE_ADDR,


@@ -543,9 +543,9 @@ U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe,
                         mxc_i2c_set_bus_speed,
                         CONFIG_SYS_MXC_I2C2_SPEED,
                         CONFIG_SYS_MXC_I2C2_SLAVE, 1)
                         mxc_i2c_set_bus_speed,
                         CONFIG_SYS_MXC_I2C2_SPEED,
                         CONFIG_SYS_MXC_I2C2_SLAVE, 1)

-#if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\
-       defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\
-       defined(CONFIG_MX6) || defined(CONFIG_LS102XA)
+#if defined(CONFIG_SOC_MX31) || defined(CONFIG_SOC_MX35) ||\
+       defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53) ||\
+       defined(CONFIG_SOC_MX6) || defined(CONFIG_SOC_LS102XA)

 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
                         mxc_i2c_read, mxc_i2c_write,
                         mxc_i2c_set_bus_speed,
 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe,
                         mxc_i2c_read, mxc_i2c_write,
                         mxc_i2c_set_bus_speed,

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index a16a268a58a74ee9a2ea25a62edd84d94f639950..ce90a2cb495d1963f638135a515522810f22765d 100644 (file)
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -1,7 +1,7 @@
 config MXC_OCOTP
        bool "Freescale OCOTP support"
 config MXC_OCOTP
        bool "Freescale OCOTP support"

-       depends on MX5 || MX6
+       depends on SOC_MX5 || SOC_MX6

 
 config MXS_OCOTP
        bool "Freescale OCOTP support"
 
 config MXS_OCOTP
        bool "Freescale OCOTP support"

-       depends on MX23 || MX28
+       depends on SOC_MXS

diff --git a/drivers/misc/fsl_iim.c b/drivers/misc/fsl_iim.c
index df3885041e5cd129802fceb1efe08831b1b176ad..008919f99b64bbc0b9cb09a4b925c5327133ea20 100644 (file)
--- a/drivers/misc/fsl_iim.c
+++ b/drivers/misc/fsl_iim.c
@@ -16,7 +16,7 @@
 #ifndef CONFIG_MPC512X
 #include <asm/arch/imx-regs.h>
 #endif
 #ifndef CONFIG_MPC512X
 #include <asm/arch/imx-regs.h>
 #endif

-#if defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#if defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53)

 #include <asm/arch/clock.h>
 #endif
 
 #include <asm/arch/clock.h>
 #endif
 


@@ -96,7 +96,7 @@ struct fsl_iim {
        } bank[8];
 };
 
        } bank[8];
 };
 

-#if !defined(CONFIG_MX51) && !defined(CONFIG_MX53)
+#if !defined(CONFIG_SOC_MX51) && !defined(CONFIG_SOC_MX53)

 #define enable_efuse_prog_supply(enable)
 #endif
 
 #define enable_efuse_prog_supply(enable)
 #endif
 

diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index b52100c2c51c21c19087b085257fda95752ef9e3..7b9b12b7f23c548c261799856eb91a3ac99cc855 100644 (file)
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -19,7 +19,7 @@ config FSL_ESDHC
 
 config FSL_USDHC
        bool "Support USDHC"
 
 config FSL_USDHC
        bool "Support USDHC"

-       depends on MX6Q
+       depends on SOC_MX6

        depends on FSL_ESDHC
 
 config SUPPORT_EMMC_BOOT
        depends on FSL_ESDHC
 
 config SUPPORT_EMMC_BOOT

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 57efda23e1f3e61a99da0d944b1e2f7cdf60f929..4b11e9da293b271d8b82596d1b2d8d7b7260305d 100644 (file)
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -103,7 +103,7 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
        else if (cmd->resp_type & MMC_RSP_PRESENT)
                xfertyp |= XFERTYP_RSPTYP_48;
 
        else if (cmd->resp_type & MMC_RSP_PRESENT)
                xfertyp |= XFERTYP_RSPTYP_48;
 

-#if defined(CONFIG_MX53) || defined(CONFIG_PPC_T4240) || defined(CONFIG_LS102XA)
+#if defined(CONFIG_SOC_MX53) || defined(CONFIG_PPC_T4240) || defined(CONFIG_SOC_LS102XA)

        if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
                xfertyp |= XFERTYP_CMDTYP_ABORT;
 #endif
        if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
                xfertyp |= XFERTYP_CMDTYP_ABORT;
 #endif

diff --git a/drivers/mmc/mxsmmc.c b/drivers/mmc/mxsmmc.c
index 6f74299adbdad53c885fc50977530e9f02f7fa2f..d9d855b87523da5c294fdf0aa837de4b59b09d24 100644 (file)
--- a/drivers/mmc/mxsmmc.c
+++ b/drivers/mmc/mxsmmc.c
@@ -212,7 +212,7 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
                ctrl0 |= SSP_CTRL0_DATA_XFER;
 
                reg = data->blocksize * data->blocks;
                ctrl0 |= SSP_CTRL0_DATA_XFER;
 
                reg = data->blocksize * data->blocks;

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

                ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;
 
                clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,
                ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK;
 
                clrsetbits_le32(&ssp_regs->hw_ssp_cmd0,


@@ -220,7 +220,7 @@ mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
                        ((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |
                        ((ffs(data->blocksize) - 1) <<
                                SSP_CMD0_BLOCK_SIZE_OFFSET));
                        ((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) |
                        ((ffs(data->blocksize) - 1) <<
                                SSP_CMD0_BLOCK_SIZE_OFFSET));

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

                writel(reg, &ssp_regs->hw_ssp_xfer_size);
 
                reg = ((data->blocks - 1) <<
                writel(reg, &ssp_regs->hw_ssp_xfer_size);
 
                reg = ((data->blocks - 1) <<

diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 791699922e2c48fb14fc81c5cfb8229eb7ba810b..1fe23929db3acd4062ed0212ed7d9dcbed9bbcd8 100644 (file)
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -67,7 +67,7 @@ config NAND_MXS
 
 config NAND_MXS_NO_BBM_SWAP
        bool "disable bad block mark swapping"
 
 config NAND_MXS_NO_BBM_SWAP
        bool "disable bad block mark swapping"

-       depends on NAND_MXS && MX6
+       depends on NAND_MXS && SOC_MX6

        select SYS_NAND_USE_FLASH_BBT
 
 endif
        select SYS_NAND_USE_FLASH_BBT
 
 endif

diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 566f55de6a572d4000e691385edb100c4bef1d60..a232e71ed944b6bc3ada0f8fee170334d069a35e 100644 (file)
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -11,15 +11,15 @@
 #include <nand.h>
 #include <linux/err.h>
 #include <asm/io.h>
 #include <nand.h>
 #include <linux/err.h>
 #include <asm/io.h>

-#if defined(CONFIG_MX25) || defined(CONFIG_MX27) || defined(CONFIG_MX35) || \
-       defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX35) || \
+       defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53)

 #include <asm/arch/imx-regs.h>
 #endif
 
 static struct mxc_nand_host mxc_host;
 static struct mxc_nand_host *host = &mxc_host;
 
 #include <asm/arch/imx-regs.h>
 #endif
 
 static struct mxc_nand_host mxc_host;
 static struct mxc_nand_host *host = &mxc_host;
 

-#ifdef CONFIG_MX27
+#ifdef CONFIG_SOC_MX27

 static int is_16bit_nand(void)
 {
        struct system_control_regs *sc_regs =
 static int is_16bit_nand(void)
 {
        struct system_control_regs *sc_regs =


@@ -30,7 +30,7 @@ static int is_16bit_nand(void)
        else
                return 0;
 }
        else
                return 0;
 }

-#elif defined(CONFIG_MX31)
+#elif defined(CONFIG_SOC_MX31)

 static int is_16bit_nand(void)
 {
        struct clock_control_regs *sc_regs =
 static int is_16bit_nand(void)
 {
        struct clock_control_regs *sc_regs =


@@ -41,7 +41,7 @@ static int is_16bit_nand(void)
        else
                return 0;
 }
        else
                return 0;
 }

-#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
+#elif defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX35)

 static int is_16bit_nand(void)
 {
        struct ccm_regs *ccm =
 static int is_16bit_nand(void)
 {
        struct ccm_regs *ccm =


@@ -52,7 +52,7 @@ static int is_16bit_nand(void)
        else
                return 0;
 }
        else
                return 0;
 }

-#elif defined(CONFIG_MX51)
+#elif defined(CONFIG_SOC_MX51)

 static int is_16bit_nand(void)
 {
        struct src *src = (struct src *)SRC_BASE_ADDR;
 static int is_16bit_nand(void)
 {
        struct src *src = (struct src *)SRC_BASE_ADDR;


@@ -62,7 +62,7 @@ static int is_16bit_nand(void)
        else
                return 0;
 }
        else
                return 0;
 }

-#elif defined(CONFIG_MX53)
+#elif defined(CONFIG_SOC_MX53)

 /* BOOT_CFG[1..3][0..7] */
 #define SRC_BOOT_CFG(m, n)             (1 << ((m) * 8 + (n)))
 static int is_16bit_nand(void)
 /* BOOT_CFG[1..3][0..7] */
 #define SRC_BOOT_CFG(m, n)             (1 << ((m) * 8 + (n)))
 static int is_16bit_nand(void)


@@ -90,19 +90,19 @@ static int is_16bit_nand(void)
 #error CONFIG_MXC_NAND_REGS_BASE not defined
 #endif
 
 #error CONFIG_MXC_NAND_REGS_BASE not defined
 #endif
 

-#if defined(CONFIG_MX27) || defined(CONFIG_MX31)
+#if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX31)

 #define nfc_is_v1()            1
 #define nfc_is_v21()           0
 #define nfc_is_v3_2()          0
 #define nfc_is_v3()            nfc_is_v3_2()
 #define NFC_VERSION            "V1"
 #define nfc_is_v1()            1
 #define nfc_is_v21()           0
 #define nfc_is_v3_2()          0
 #define nfc_is_v3()            nfc_is_v3_2()
 #define NFC_VERSION            "V1"

-#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
+#elif defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX35)

 #define nfc_is_v1()            0
 #define nfc_is_v21()           1
 #define nfc_is_v3_2()          0
 #define nfc_is_v3()            nfc_is_v3_2()
 #define NFC_VERSION            "V2"
 #define nfc_is_v1()            0
 #define nfc_is_v21()           1
 #define nfc_is_v3_2()          0
 #define nfc_is_v3()            nfc_is_v3_2()
 #define NFC_VERSION            "V2"

-#elif defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#elif defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53)

 #define nfc_is_v1()            0
 #define nfc_is_v21()           0
 #define nfc_is_v3_2()          1
 #define nfc_is_v1()            0
 #define nfc_is_v21()           0
 #define nfc_is_v3_2()          1


@@ -871,7 +871,7 @@ static void preset_v3(struct mtd_info *mtd)
        }
 
        if (mtd->writesize) {
        }
 
        if (mtd->writesize) {

-#if defined CONFIG_MX53
+#if defined CONFIG_SOC_MX53

                config2 |= MX53_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
 #else
                config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
                config2 |= MX53_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);
 #else
                config2 |= NFC_V3_CONFIG2_PPB(ffs(mtd->erasesize / mtd->writesize) - 6);

diff --git a/drivers/mtd/nand/mxc_nand.h b/drivers/mtd/nand/mxc_nand.h
index a02d6e0a5ab36dda572646653083bd7754f96aad..40b689d8c618dddf2fd6ff6b7f725186358ae075 100644 (file)
--- a/drivers/mtd/nand/mxc_nand.h
+++ b/drivers/mtd/nand/mxc_nand.h
@@ -25,17 +25,17 @@
  *     Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
  *     Also some of registers are moved and/or changed meaning as seen below.
  */
  *     Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
  *     Also some of registers are moved and/or changed meaning as seen below.
  */

-#if defined(CONFIG_MX27) || defined(CONFIG_MX31)
+#if defined(CONFIG_SOC_MX27) || defined(CONFIG_SOC_MX31)

 #define MXC_NFC_V1
 #define is_mxc_nfc_1()         1
 #define is_mxc_nfc_21()                0
 #define is_mxc_nfc_32()                0
 #define MXC_NFC_V1
 #define is_mxc_nfc_1()         1
 #define is_mxc_nfc_21()                0
 #define is_mxc_nfc_32()                0

-#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
+#elif defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX35)

 #define MXC_NFC_V2_1
 #define is_mxc_nfc_1()         0
 #define is_mxc_nfc_21()                1
 #define is_mxc_nfc_32()                0
 #define MXC_NFC_V2_1
 #define is_mxc_nfc_1()         0
 #define is_mxc_nfc_21()                1
 #define is_mxc_nfc_32()                0

-#elif defined(CONFIG_MX51) || defined(CONFIG_MX53)
+#elif defined(CONFIG_SOC_MX51) || defined(CONFIG_SOC_MX53)

 #define MXC_NFC_V3
 #define MXC_NFC_V3_2
 #define is_mxc_nfc_1()         0
 #define MXC_NFC_V3
 #define MXC_NFC_V3_2
 #define is_mxc_nfc_1()         0

diff --git a/drivers/mtd/nand/mxs_nand.c b/drivers/mtd/nand/mxs_nand.c
index 4125a4cd1afd4268cb65a6275217f65b37c63bfd..e424f60a9a05642c7d92cd52578a0dd06bd46f5c 100644 (file)
--- a/drivers/mtd/nand/mxs_nand.c
+++ b/drivers/mtd/nand/mxs_nand.c
@@ -31,7 +31,7 @@
 #define        MXS_NAND_DMA_DESCRIPTOR_COUNT           4
 
 #define        MXS_NAND_CHUNK_DATA_CHUNK_SIZE          512
 #define        MXS_NAND_DMA_DESCRIPTOR_COUNT           4
 
 #define        MXS_NAND_CHUNK_DATA_CHUNK_SIZE          512

-#if defined(CONFIG_MX6)
+#if defined(CONFIG_SOC_MX6)

 #define        MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT    2
 #else
 #define        MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT    0
 #define        MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT    2
 #else
 #define        MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT    0


@@ -589,7 +589,7 @@ static void mxs_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int length)
                length;
 
        mxs_dma_desc_append(channel, d);
                length;
 
        mxs_dma_desc_append(channel, d);

-#ifndef CONFIG_MX6Q
+#ifndef CONFIG_SOC_MX6Q

        /*
         * A DMA descriptor that waits for the command to end and the chip to
         * become ready.
        /*
         * A DMA descriptor that waits for the command to end and the chip to
         * become ready.

diff --git a/drivers/mtd/nand/vf610_nfc.c b/drivers/mtd/nand/vf610_nfc.c
index 928d58b3a732894bcf7fe143da3ef821d6caf0bb..921c06c6c8baa639f76b28f280dc2c9c5d05a123 100644 (file)
--- a/drivers/mtd/nand/vf610_nfc.c
+++ b/drivers/mtd/nand/vf610_nfc.c
@@ -134,7 +134,7 @@
  * ECC status is stored at NFC_CFG[ECCADD] +4 for little-endian
  * and +7 for big-endian SOC.
  */
  * ECC status is stored at NFC_CFG[ECCADD] +4 for little-endian
  * and +7 for big-endian SOC.
  */

-#ifdef CONFIG_VF610
+#ifdef CONFIG_SOC_VF610

 #define ECC_OFFSET     4
 #else
 #define ECC_OFFSET     7
 #define ECC_OFFSET     4
 #else
 #define ECC_OFFSET     7


@@ -476,7 +476,7 @@ static int vf610_nfc_dev_ready(struct mtd_info *mtd)
  */
 static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip)
 {
  */
 static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip)
 {

-#ifdef CONFIG_VF610
+#ifdef CONFIG_SOC_VF610

        u32 tmp = vf610_nfc_read(mtd, NFC_ROW_ADDR);
        tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK);
        tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT;
        u32 tmp = vf610_nfc_read(mtd, NFC_ROW_ADDR);
        tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK);
        tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT;

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 63f03e6202fed61f3229837541eb505104888d9a..7e732d4df487ea39bd984f9908d42504b539e2d1 100644 (file)
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -51,7 +51,7 @@ DECLARE_GLOBAL_DATA_PTR;
  * The i.MX28 operates with packets in big endian. We need to swap them before
  * sending and after receiving.
  */
  * The i.MX28 operates with packets in big endian. We need to swap them before
  * sending and after receiving.
  */

-#ifdef CONFIG_MX28
+#ifdef CONFIG_SOC_MX28

 #define CONFIG_FEC_MXC_SWAP_PACKET
 #endif
 
 #define CONFIG_FEC_MXC_SWAP_PACKET
 #endif
 


@@ -212,7 +212,7 @@ static int miiphy_restart_aneg(struct eth_device *dev)
         * Wake up from sleep if necessary
         * Reset PHY, then delay 300ns
         */
         * Wake up from sleep if necessary
         * Reset PHY, then delay 300ns
         */

-#ifdef CONFIG_MX27
+#ifdef CONFIG_SOC_MX27

        fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
 #endif
        fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
        fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
 #endif
        fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);


@@ -458,7 +458,7 @@ static int fec_open(struct eth_device *edev)
         */
        writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
                &fec->eth->ecntrl);
         */
        writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
                &fec->eth->ecntrl);

-#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
+#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6SL)

        udelay(100);
        /*
         * setup the MII gasket for RMII mode
        udelay(100);
        /*
         * setup the MII gasket for RMII mode


@@ -517,7 +517,7 @@ static int fec_open(struct eth_device *edev)
                writel(ecr, &fec->eth->ecntrl);
                writel(rcr, &fec->eth->r_cntrl);
        }
                writel(ecr, &fec->eth->ecntrl);
                writel(rcr, &fec->eth->r_cntrl);
        }

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

        {
                u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
 
        {
                u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
 


@@ -1104,7 +1104,7 @@ int fecmxc_initialize_multi(bd_t *bd, int dev_id, int phy_id, uint32_t addr)
 #endif
        int ret;
 
 #endif
        int ret;
 

-#ifdef CONFIG_MX28
+#ifdef CONFIG_SOC_MX28

        /*
         * The i.MX28 has two ethernet interfaces, but they are not equal.
         * Only the first one can access the MDIO bus.
        /*
         * The i.MX28 has two ethernet interfaces, but they are not equal.
         * Only the first one can access the MDIO bus.

diff --git a/drivers/net/fec_mxc.h b/drivers/net/fec_mxc.h
index 44170174cf422c218fd01c7a374a755f9e47180a..66b81cc7d5ccf662a514e29fe43557b0e17c1ec3 100644 (file)
--- a/drivers/net/fec_mxc.h
+++ b/drivers/net/fec_mxc.h
@@ -133,7 +133,7 @@ struct ethernet_regs {
 
        uint32_t res14[7];              /* MBAR_ETH + 0x2E4-2FC */
 
 
        uint32_t res14[7];              /* MBAR_ETH + 0x2E4-2FC */
 

-#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
+#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6SL)

        uint16_t miigsk_cfgr;           /* MBAR_ETH + 0x300 */
        uint16_t res15[3];              /* MBAR_ETH + 0x302-306 */
        uint16_t miigsk_enr;            /* MBAR_ETH + 0x308 */
        uint16_t miigsk_cfgr;           /* MBAR_ETH + 0x300 */
        uint16_t res15[3];              /* MBAR_ETH + 0x302-306 */
        uint16_t miigsk_enr;            /* MBAR_ETH + 0x308 */


@@ -200,7 +200,7 @@ struct ethernet_regs {
 #define FEC_X_DES_ACTIVE_TDAR          0x01000000
 #define FEC_R_DES_ACTIVE_RDAR          0x01000000
 
 #define FEC_X_DES_ACTIVE_TDAR          0x01000000
 #define FEC_R_DES_ACTIVE_RDAR          0x01000000
 

-#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
+#if defined(CONFIG_SOC_MX25) || defined(CONFIG_SOC_MX53) || defined(CONFIG_SOC_MX6SL)

 /* defines for MIIGSK */
 /* RMII frequency control: 0=50MHz, 1=5MHz */
 #define MIIGSK_CFGR_FRCONT             (1 << 6)
 /* defines for MIIGSK */
 /* RMII frequency control: 0=50MHz, 1=5MHz */
 #define MIIGSK_CFGR_FRCONT             (1 << 6)

diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c
index dcdba4ea827190759ea9ab0de43239a02024a096..c4cf80a3f8bd50f36cbf921f90ca5d5d4b4adc52 100644 (file)
--- a/drivers/net/tsec.c
+++ b/drivers/net/tsec.c
@@ -271,7 +271,7 @@ void redundant_init(struct eth_device *dev)
        out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
        out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
        clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
        out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
        out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
        clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);

-#ifdef CONFIG_LS102XA
+#ifdef CONFIG_SOC_LS102XA

        setbits_be32(&regs->dmactrl, DMACTRL_LE);
 #endif
 
        setbits_be32(&regs->dmactrl, DMACTRL_LE);
 #endif
 


@@ -370,7 +370,7 @@ static void startup_tsec(struct eth_device *dev)
        out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
        out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
        clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);
        out_be32(&regs->tstat, TSTAT_CLEAR_THALT);
        out_be32(&regs->rstat, RSTAT_CLEAR_RHALT);
        clrbits_be32(&regs->dmactrl, DMACTRL_GRS | DMACTRL_GTS);

-#ifdef CONFIG_LS102XA
+#ifdef CONFIG_SOC_LS102XA

        setbits_be32(&regs->dmactrl, DMACTRL_LE);
 #endif
 }
        setbits_be32(&regs->dmactrl, DMACTRL_LE);
 #endif
 }

diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c
index fd7e4d499f06b01fa8bd5a491b7eaaccff0943d3..67450cb5782ede6250f430bff2b6a182bccce206 100644 (file)
--- a/drivers/pci/pcie_imx.c
+++ b/drivers/pci/pcie_imx.c
@@ -23,7 +23,7 @@
 #define PCI_ACCESS_READ  0
 #define PCI_ACCESS_WRITE 1
 
 #define PCI_ACCESS_READ  0
 #define PCI_ACCESS_WRITE 1
 

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define MX6_DBI_ADDR   0x08ffc000
 #define MX6_IO_ADDR    0x08000000
 #define MX6_MEM_ADDR   0x08100000
 #define MX6_DBI_ADDR   0x08ffc000
 #define MX6_IO_ADDR    0x08000000
 #define MX6_MEM_ADDR   0x08100000


@@ -430,7 +430,7 @@ static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
 static int imx6_pcie_assert_core_reset(void)
 {
        struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
 static int imx6_pcie_assert_core_reset(void)
 {
        struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;

-#if defined(CONFIG_MX6SX)
+#if defined(CONFIG_SOC_MX6SX)

        struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
 
        /* SSP_EN is not used on MX6SX anymore */
        struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
 
        /* SSP_EN is not used on MX6SX anymore */


@@ -460,7 +460,7 @@ static int imx6_pcie_init_phy(void)
                        IOMUXC_GPR12_LOS_LEVEL_MASK,
                        IOMUXC_GPR12_LOS_LEVEL_9);
 
                        IOMUXC_GPR12_LOS_LEVEL_MASK,
                        IOMUXC_GPR12_LOS_LEVEL_9);
 

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

        clrsetbits_le32(&iomuxc_regs->gpr[12],
                        IOMUXC_GPR12_RX_EQ_MASK,
                        IOMUXC_GPR12_RX_EQ_2);
        clrsetbits_le32(&iomuxc_regs->gpr[12],
                        IOMUXC_GPR12_RX_EQ_MASK,
                        IOMUXC_GPR12_RX_EQ_2);


@@ -542,7 +542,7 @@ static int imx6_pcie_deassert_core_reset(void)
         */
        mdelay(50);
 
         */
        mdelay(50);
 

-#if defined(CONFIG_MX6SX)
+#if defined(CONFIG_SOC_MX6SX)

        /* SSP_EN is not used on MX6SX anymore */
        clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
        /* Clear PCIe PHY reset bit */
        /* SSP_EN is not used on MX6SX anymore */
        clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
        /* Clear PCIe PHY reset bit */

diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c
index d24651b5ba2b786e2a050cb3d98204d130365d6c..fd72259a579e2539caec80eb0413d6ba2dd5d7cf 100644 (file)
--- a/drivers/qe/qe.c
+++ b/drivers/qe/qe.c
@@ -13,7 +13,7 @@
 #include "asm/io.h"
 #include "linux/immap_qe.h"
 #include "qe.h"
 #include "asm/io.h"
 #include "linux/immap_qe.h"
 #include "qe.h"

-#ifdef CONFIG_LS102XA
+#ifdef CONFIG_SOC_LS102XA

 #include <asm/arch/immap_ls102xa.h>
 #endif
 
 #include <asm/arch/immap_ls102xa.h>
 #endif
 


@@ -338,7 +338,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
        size_t length;
        const struct qe_header *hdr;
 #ifdef CONFIG_DEEP_SLEEP
        size_t length;
        const struct qe_header *hdr;
 #ifdef CONFIG_DEEP_SLEEP

-#ifdef CONFIG_LS102XA
+#ifdef CONFIG_SOC_LS102XA

        struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 #else
        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
        struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 #else
        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);


@@ -477,7 +477,7 @@ int u_qe_upload_firmware(const struct qe_firmware *firmware)
        size_t length;
        const struct qe_header *hdr;
 #ifdef CONFIG_DEEP_SLEEP
        size_t length;
        const struct qe_header *hdr;
 #ifdef CONFIG_DEEP_SLEEP

-#ifdef CONFIG_LS102XA
+#ifdef CONFIG_SOC_LS102XA

        struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 #else
        ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
        struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
 #else
        ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 5e0b0692747cb7791c38e33783c515629f8ba6ff..b00a4328cb41d5c5cd0bf9db09e82bd23c5a4789 100644 (file)
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -14,7 +14,7 @@
 #include "fsl_qspi.h"
 
 #define RX_BUFFER_SIZE         0x80
 #include "fsl_qspi.h"
 
 #define RX_BUFFER_SIZE         0x80

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

 #define TX_BUFFER_SIZE         0x200
 #else
 #define TX_BUFFER_SIZE         0x40
 #define TX_BUFFER_SIZE         0x200
 #else
 #define TX_BUFFER_SIZE         0x40


@@ -73,14 +73,14 @@
 
 static unsigned long spi_bases[] = {
        QSPI0_BASE_ADDR,
 
 static unsigned long spi_bases[] = {
        QSPI0_BASE_ADDR,

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

        QSPI1_BASE_ADDR,
 #endif
 };
 
 static unsigned long amba_bases[] = {
        QSPI0_AMBA_BASE,
        QSPI1_BASE_ADDR,
 #endif
 };
 
 static unsigned long amba_bases[] = {
        QSPI0_AMBA_BASE,

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

        QSPI1_AMBA_BASE,
 #endif
 };
        QSPI1_AMBA_BASE,
 #endif
 };


@@ -97,7 +97,7 @@ struct fsl_qspi {
  * in hardware for LS102xA, but not for VF610 */
 static inline u32 qspi_endian_xchg(u32 data)
 {
  * in hardware for LS102xA, but not for VF610 */
 static inline u32 qspi_endian_xchg(u32 data)
 {

-#ifdef CONFIG_VF610
+#ifdef CONFIG_SOC_VF610

        return swab32(data);
 #else
        return data;
        return swab32(data);
 #else
        return data;


@@ -203,7 +203,7 @@ static void qspi_set_lut(struct fsl_qspi *qspi)
                        PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
                        PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 #endif
                        PAD0(LUT_PAD1) | INSTR0(LUT_CMD) | OPRND1(ADDR32BIT) |
                        PAD1(LUT_PAD1) | INSTR1(LUT_ADDR));
 #endif

-#ifdef CONFIG_MX6SX
+#ifdef CONFIG_SOC_MX6SX

        /*
         * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
         * So, Use IDATSZ in IPCR to determine the size and here set 0.
        /*
         * To MX6SX, OPRND0(TX_BUFFER_SIZE) can not work correctly.
         * So, Use IDATSZ in IPCR to determine the size and here set 0.

diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c
index 08815994fe5d21d0effd00394cea05ce6698508c..a70dd9dbdd223747a92873792429f1e0326297e6 100644 (file)
--- a/drivers/spi/mxc_spi.c
+++ b/drivers/spi/mxc_spi.c
@@ -14,7 +14,7 @@
 #include <asm/arch/clock.h>
 #include <asm/imx-common/spi.h>
 
 #include <asm/arch/clock.h>
 #include <asm/imx-common/spi.h>
 

-#ifdef CONFIG_MX27
+#ifdef CONFIG_SOC_MX27

 /* i.MX27 has a completely wrong register layout and register definitions in the
  * datasheet, the correct one is in the Freescale's Linux driver */
 
 /* i.MX27 has a completely wrong register layout and register definitions in the
  * datasheet, the correct one is in the Freescale's Linux driver */
 


@@ -105,7 +105,7 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs)
                MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
                MXC_CSPICTRL_DATARATE(div) |
                MXC_CSPICTRL_EN |
                MXC_CSPICTRL_BITCOUNT(MXC_CSPICTRL_MAXBITS) |
                MXC_CSPICTRL_DATARATE(div) |
                MXC_CSPICTRL_EN |

-#ifdef CONFIG_MX35
+#ifdef CONFIG_SOC_MX35

                MXC_CSPICTRL_SSCTL |
 #endif
                MXC_CSPICTRL_MODE;
                MXC_CSPICTRL_SSCTL |
 #endif
                MXC_CSPICTRL_MODE;

diff --git a/drivers/spi/mxs_spi.c b/drivers/spi/mxs_spi.c
index 2b9f395a97821568dc12c5e28feaaf42b42ffd50..093d0c246eee12400588d35f9b84ee55f80e11df 100644 (file)
--- a/drivers/spi/mxs_spi.c
+++ b/drivers/spi/mxs_spi.c
@@ -136,10 +136,10 @@ static int mxs_spi_xfer_pio(struct mxs_spi_slave *slave,
 
        while (length--) {
                /* We transfer 1 byte */
 
        while (length--) {
                /* We transfer 1 byte */

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

                writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr);
                writel(1, &ssp_regs->hw_ssp_ctrl0_set);
                writel(SSP_CTRL0_XFER_COUNT_MASK, &ssp_regs->hw_ssp_ctrl0_clr);
                writel(1, &ssp_regs->hw_ssp_ctrl0_set);

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

                writel(1, &ssp_regs->hw_ssp_xfer_size);
 #endif
 
                writel(1, &ssp_regs->hw_ssp_xfer_size);
 #endif
 


@@ -199,9 +199,9 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
        int tl;
        int ret = 0;
 
        int tl;
        int ret = 0;
 

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

        const int mxs_spi_pio_words = 1;
        const int mxs_spi_pio_words = 1;

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

        const int mxs_spi_pio_words = 4;
 #endif
 
        const int mxs_spi_pio_words = 4;
 #endif
 


@@ -285,7 +285,7 @@ static int mxs_spi_xfer_dma(struct mxs_spi_slave *slave,
                 * descriptor!
                 */
                dp->cmd.pio_words[0] = ctrl0;
                 * descriptor!
                 */
                dp->cmd.pio_words[0] = ctrl0;

-#ifdef CONFIG_MX28
+#ifdef CONFIG_SOC_MX28

                dp->cmd.pio_words[1] = 0;
                dp->cmd.pio_words[2] = 0;
                dp->cmd.pio_words[3] = tl;
                dp->cmd.pio_words[1] = 0;
                dp->cmd.pio_words[2] = 0;
                dp->cmd.pio_words[3] = tl;

diff --git a/drivers/usb/host/ehci-mx5.c b/drivers/usb/host/ehci-mx5.c
index 7566c61284eb2c29d2a0fc1cc423e4fd219570f1..838f23fee82a24b7742c6061fd1f6bec07d988b0 100644 (file)
--- a/drivers/usb/host/ehci-mx5.c
+++ b/drivers/usb/host/ehci-mx5.c
@@ -101,7 +101,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
                        else
                                /* OC/USBPWR is not used */
                                v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
                        else
                                /* OC/USBPWR is not used */
                                v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;

-#ifdef CONFIG_MX51
+#ifdef CONFIG_SOC_MX51

                        if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
                                v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
                        else
                        if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
                                v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
                        else


@@ -111,13 +111,13 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
                                        MXC_USB_PHY_CTR_FUNC_OFFSET);
 
                        v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
                                        MXC_USB_PHY_CTR_FUNC_OFFSET);
 
                        v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);

-#ifdef CONFIG_MX51
+#ifdef CONFIG_SOC_MX51

                        if (flags & MXC_EHCI_POWER_PINS_ENABLED)
                                v &= ~MXC_OTG_UCTRL_OPM_BIT;
                        else
                                v |= MXC_OTG_UCTRL_OPM_BIT;
 #endif
                        if (flags & MXC_EHCI_POWER_PINS_ENABLED)
                                v &= ~MXC_OTG_UCTRL_OPM_BIT;
                        else
                                v |= MXC_OTG_UCTRL_OPM_BIT;
 #endif

-#ifdef CONFIG_MX53
+#ifdef CONFIG_SOC_MX53

                        if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
                                v |= MXC_OTG_UCTRL_O_PWR_POL_BIT;
                        else
                        if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
                                v |= MXC_OTG_UCTRL_O_PWR_POL_BIT;
                        else


@@ -127,7 +127,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
                }
                break;
        case 1: /* Host 1 ULPI */
                }
                break;
        case 1: /* Host 1 ULPI */

-#ifdef CONFIG_MX51
+#ifdef CONFIG_SOC_MX51

                /* The clock for the USBH1 ULPI port will come externally
                   from the PHY. */
                v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET);
                /* The clock for the USBH1 ULPI port will come externally
                   from the PHY. */
                v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET);


@@ -136,13 +136,13 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 #endif
 
                v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
 #endif
 
                v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);

-#ifdef CONFIG_MX51
+#ifdef CONFIG_SOC_MX51

                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
                        v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */
                else
                        v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
 #endif
                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
                        v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */
                else
                        v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
 #endif

-#ifdef CONFIG_MX53
+#ifdef CONFIG_SOC_MX53

                if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
                        v |= MXC_H1_UCTRL_H1_PWR_POL_BIT;
                else
                if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
                        v |= MXC_H1_UCTRL_H1_PWR_POL_BIT;
                else


@@ -164,13 +164,13 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
                break;
        case 2: /* Host 2 ULPI */
                v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
                break;
        case 2: /* Host 2 ULPI */
                v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);

-#ifdef CONFIG_MX51
+#ifdef CONFIG_SOC_MX51

                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
                        v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */
                else
                        v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
 #endif
                if (flags & MXC_EHCI_POWER_PINS_ENABLED)
                        v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */
                else
                        v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
 #endif

-#ifdef CONFIG_MX53
+#ifdef CONFIG_SOC_MX53

                if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
                        v |= MXC_H2_UCTRL_H2_OC_POL_BIT;
                else
                if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
                        v |= MXC_H2_UCTRL_H2_OC_POL_BIT;
                else


@@ -186,7 +186,7 @@ int mxc_set_usbcontrol(int port, unsigned int flags)
 #endif
                __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
                break;
 #endif
                __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
                break;

-#ifdef CONFIG_MX53
+#ifdef CONFIG_SOC_MX53

        case 3: /* Host 3 ULPI */
                v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
                if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
        case 3: /* Host 3 ULPI */
                v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
                if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)

diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index f09c75a9b64d3f5750f4ae8b7f4d16e80a0bd8a8..ded991fa34375b458163321cf3b5c33ed937ffbe 100644 (file)
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -67,7 +67,7 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
        unsigned int v;
 
        v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
        unsigned int v;
 
        v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);

-#if defined(CONFIG_MX25)
+#if defined(CONFIG_SOC_MX25)

        switch (port) {
        case 0: /* OTG port */
                v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
        switch (port) {
        case 0: /* OTG port */
                v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |


@@ -116,7 +116,7 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
        default:
                return -EINVAL;
        }
        default:
                return -EINVAL;
        }

-#elif defined(CONFIG_MX31)
+#elif defined(CONFIG_SOC_MX31)

        switch (port) {
        case 0: /* OTG port */
                v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
        switch (port) {
        case 0: /* OTG port */
                v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);


@@ -151,7 +151,7 @@ static int mxc_set_usbcontrol(int port, unsigned int flags)
        default:
                return -EINVAL;
        }
        default:
                return -EINVAL;
        }

-#elif defined(CONFIG_MX35)
+#elif defined(CONFIG_SOC_MX35)

        switch (port) {
        case 0: /* OTG port */
                v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |
        switch (port) {
        case 0: /* OTG port */
                v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |


@@ -212,7 +212,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
                struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
        struct usb_ehci *ehci;
                struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 {
        struct usb_ehci *ehci;

-#ifdef CONFIG_MX31
+#ifdef CONFIG_SOC_MX31

        struct clock_control_regs *sc_regs =
                (struct clock_control_regs *)CCM_BASE;
 
        struct clock_control_regs *sc_regs =
                (struct clock_control_regs *)CCM_BASE;
 


@@ -230,7 +230,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
        setbits_le32(&ehci->usbmode, CM_HOST);
        __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
        mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
        setbits_le32(&ehci->usbmode, CM_HOST);
        __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
        mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);

-#ifdef CONFIG_MX35
+#ifdef CONFIG_SOC_MX35

        /* Workaround for ENGcm11601 */
        __raw_writel(0, &ehci->sbuscfg);
 #endif
        /* Workaround for ENGcm11601 */
        __raw_writel(0, &ehci->sbuscfg);
 #endif

diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c
index 7e249f67ab40a572888591f96700e2a1ad32a6e1..ee9c2110edaf81187254ae269c25c6b8577c9755 100644 (file)
--- a/drivers/video/ipu_common.c
+++ b/drivers/video/ipu_common.c
@@ -366,7 +366,7 @@ int ipu_probe(int di, ipu_di_clk_parent_t di_clk_parent, int di_clk_val)
        int ret;
        void *ipu_base;
        unsigned long start;
        int ret;
        void *ipu_base;
        unsigned long start;

-#if defined CONFIG_MX51
+#if defined CONFIG_SOC_MX51

        u32 temp;
        u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR;
        u32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800);
        u32 temp;
        u32 *reg_hsc_mcd = (u32 *)MIPI_HSC_BASE_ADDR;
        u32 *reg_hsc_mxt_conf = (u32 *)(MIPI_HSC_BASE_ADDR + 0x800);

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 052e24f6cde67a615bfd9035fa1862f35ebcee74..83bdddc28d1c0fe74d4354a28ec3f2e4af923a9d 100644 (file)
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -1,7 +1,7 @@
 config HW_WATCHDOG
        bool "Generic SoC specific watchdog support"
 config HW_WATCHDOG
        bool "Generic SoC specific watchdog support"

-       depends on !MX6
+       depends on !SOC_MX6

 
 config IMX_WATCHDOG
        bool "Freescale i.MX watchdog support"
 
 config IMX_WATCHDOG
        bool "Freescale i.MX watchdog support"

-       depends on MX31 || MX35 || MX5 || MX6 || VF610 || LS102XA
+       depends on SOC_MX31 || SOC_MX35 || SOC_MX5 || SOC_MX6 || SOC_VF610 || SOC_LS102XA

diff --git a/include/configs/apf27.h b/include/configs/apf27.h
index 403692d51702f5be822a4e495bedf1ae18d29d77..c8cbd5009ef6b0475132925322238a68943f2fc9 100644 (file)
--- a/include/configs/apf27.h
+++ b/include/configs/apf27.h
@@ -18,7 +18,6 @@
 /*
  * SoC configurations
  */
 /*
  * SoC configurations
  */

-#define CONFIG_MX27                    /* This is a Freescale i.MX27 Chip */

 #define CONFIG_MACH_TYPE       1698    /* APF27 */
 #define CONFIG_SYS_GENERIC_BOARD
 
 #define CONFIG_MACH_TYPE       1698    /* APF27 */
 #define CONFIG_SYS_GENERIC_BOARD
 

diff --git a/include/configs/apx4devkit.h b/include/configs/apx4devkit.h
index d1f18bc45c30878b16348875cfaa9199df405692..9536e85be5069d394dacf452ac984ac042578564 100644 (file)
--- a/include/configs/apx4devkit.h
+++ b/include/configs/apx4devkit.h
@@ -15,7 +15,6 @@
 #define __CONFIGS_APX4DEVKIT_H__
 
 /* System configurations */
 #define __CONFIGS_APX4DEVKIT_H__
 
 /* System configurations */

-#define CONFIG_MX28                            /* i.MX28 SoC */

 #define MACH_TYPE_APX4DEVKIT   3712
 #define CONFIG_MACH_TYPE       MACH_TYPE_APX4DEVKIT
 
 #define MACH_TYPE_APX4DEVKIT   3712
 #define CONFIG_MACH_TYPE       MACH_TYPE_APX4DEVKIT
 

diff --git a/include/configs/aristainetos.h b/include/configs/aristainetos.h
index e6a08df4ba7de13082e4df476120b3743a5a6a51..78deeab6e002ed219123615a39bc67b1e9313079 100644 (file)
--- a/include/configs/aristainetos.h
+++ b/include/configs/aristainetos.h
@@ -12,7 +12,6 @@
 #ifndef __ARISTAINETOS_CONFIG_H
 #define __ARISTAINETOS_CONFIG_H
 
 #ifndef __ARISTAINETOS_CONFIG_H
 #define __ARISTAINETOS_CONFIG_H
 

-#define CONFIG_MX6

 
 #include "mx6_common.h"
 #include <linux/sizes.h>
 
 #include "mx6_common.h"
 #include <linux/sizes.h>

diff --git a/include/configs/bg0900.h b/include/configs/bg0900.h
index 507d972f34c305cd28bf0855a381df41275c2253..3b93ff600e4bbaceb73d76215629ff3e3254195d 100644 (file)
--- a/include/configs/bg0900.h
+++ b/include/configs/bg0900.h
@@ -7,7 +7,6 @@
 #define __CONFIGS_BG0900_H__
 
 /* System configurations */
 #define __CONFIGS_BG0900_H__
 
 /* System configurations */

-#define CONFIG_MX28                            /* i.MX28 SoC */

 
 /* U-Boot Commands */
 #define CONFIG_SYS_NO_FLASH
 
 /* U-Boot Commands */
 #define CONFIG_SYS_NO_FLASH

diff --git a/include/configs/calimain.h b/include/configs/calimain.h
index 44c947f61869a0df9541df69263f760826a4ec49..656dda6aeef5c87ef2205a171bf8febd12cc7d1b 100644 (file)
--- a/include/configs/calimain.h
+++ b/include/configs/calimain.h
@@ -24,8 +24,6 @@
  * SoC Configuration
  */
 #define CONFIG_MACH_DAVINCI_CALIMAIN
  * SoC Configuration
  */
 #define CONFIG_MACH_DAVINCI_CALIMAIN

-#define CONFIG_SOC_DA8XX               /* TI DA8xx SoC */
-#define CONFIG_SOC_DA850               /* TI DA850 SoC */

 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 #define CONFIG_SYS_CLK_FREQ            clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ          calimain_get_osc_freq()
 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 #define CONFIG_SYS_CLK_FREQ            clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ          calimain_get_osc_freq()

diff --git a/include/configs/cam_enc_4xx.h b/include/configs/cam_enc_4xx.h
index f8785dbafcf9f968460df4fba471b3658279db54..ae0abc7c74ebc2a8a4b9564950606c3fca2adede 100644 (file)
--- a/include/configs/cam_enc_4xx.h
+++ b/include/configs/cam_enc_4xx.h
@@ -16,7 +16,6 @@
 /* SoC Configuration */
 #define CONFIG_SYS_TIMERBASE           0x01c21400      /* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK            24000000        /* timer0 freq */
 /* SoC Configuration */
 #define CONFIG_SYS_TIMERBASE           0x01c21400      /* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK            24000000        /* timer0 freq */

-#define CONFIG_SOC_DM365

 
 #define CONFIG_MACH_TYPE       MACH_TYPE_DAVINCI_DM365_EVM
 
 
 #define CONFIG_MACH_TYPE       MACH_TYPE_DAVINCI_DM365_EVM
 

diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h
index b189bf116f316649aa6c9309fcc2194fea82cd1d..6ee2dd403b7fc5103580bb205ded9740cbc1715b 100644 (file)
--- a/include/configs/cgtqmx6eval.h
+++ b/include/configs/cgtqmx6eval.h
@@ -13,7 +13,6 @@
 #ifndef __CONFIG_CGTQMX6EVAL_H
 #define __CONFIG_CGTQMX6EVAL_H
 
 #ifndef __CONFIG_CGTQMX6EVAL_H
 #define __CONFIG_CGTQMX6EVAL_H
 

-#define CONFIG_MX6

 
 #include "mx6_common.h"
 
 
 #include "mx6_common.h"
 

diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h
index f7277eb1d17a0d5f3a4c613d6033bd682c3491dd..42be7fcafdf2a7370e49be2712df59a732a359e1 100644 (file)
--- a/include/configs/cm_fx6.h
+++ b/include/configs/cm_fx6.h
@@ -16,7 +16,6 @@
 #include "mx6_common.h"
 
 /* Machine config */
 #include "mx6_common.h"
 
 /* Machine config */

-#define CONFIG_MX6

 #define CONFIG_SYS_LITTLE_ENDIAN
 #define CONFIG_MACH_TYPE               4273
 
 #define CONFIG_SYS_LITTLE_ENDIAN
 #define CONFIG_MACH_TYPE               4273
 

diff --git a/include/configs/da830evm.h b/include/configs/da830evm.h
index 0bdcef7006dfb87c760b3bfd8969be1dbb0cc70d..a07ac38de738bc809bd1b9819b5158d7f833641d 100644 (file)
--- a/include/configs/da830evm.h
+++ b/include/configs/da830evm.h
@@ -21,8 +21,6 @@
  * SoC Configuration
  */
 #define CONFIG_MACH_DAVINCI_DA830_EVM
  * SoC Configuration
  */
 #define CONFIG_MACH_DAVINCI_DA830_EVM

-#define CONFIG_SOC_DA8XX               /* TI DA8xx SoC */
-#define CONFIG_SOC_DA830               /* TI DA830 SoC */

 #define CONFIG_SYS_CLK_FREQ            clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ          24000000
 #define CONFIG_SYS_TIMERBASE           DAVINCI_TIMER0_BASE
 #define CONFIG_SYS_CLK_FREQ            clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ          24000000
 #define CONFIG_SYS_TIMERBASE           DAVINCI_TIMER0_BASE

diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h
index e5a612cfc6772614c9794b61b6ca62e23a7b4aab..4b821f70316d608cb7fb235b23e89122bb55ffe5 100644 (file)
--- a/include/configs/da850evm.h
+++ b/include/configs/da850evm.h
@@ -25,8 +25,6 @@
  * SoC Configuration
  */
 #define CONFIG_MACH_DAVINCI_DA850_EVM
  * SoC Configuration
  */
 #define CONFIG_MACH_DAVINCI_DA850_EVM

-#define CONFIG_SOC_DA8XX               /* TI DA8xx SoC */
-#define CONFIG_SOC_DA850               /* TI DA850 SoC */

 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 #define CONFIG_SYS_CLK_FREQ            clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ          24000000
 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 #define CONFIG_SYS_CLK_FREQ            clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ          24000000

diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h
index 16b901b01b758c303c2227cef5fcb58b538a2eec..6a2187266f80127f1c5f4adeeea02f522cc8c08b 100644 (file)
--- a/include/configs/davinci_dm355evm.h
+++ b/include/configs/davinci_dm355evm.h
@@ -17,7 +17,6 @@
 /* SoC Configuration */
 #define CONFIG_SYS_TIMERBASE           0x01c21400      /* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK            24000000        /* timer0 freq */
 /* SoC Configuration */
 #define CONFIG_SYS_TIMERBASE           0x01c21400      /* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK            24000000        /* timer0 freq */

-#define CONFIG_SOC_DM355

 
 /* Memory Info */
 #define CONFIG_NR_DRAM_BANKS           1
 
 /* Memory Info */
 #define CONFIG_NR_DRAM_BANKS           1

diff --git a/include/configs/davinci_dm355leopard.h b/include/configs/davinci_dm355leopard.h
index 4eed72292dfab33feb7618da0eebad272480f343..52803ae9095317c2e73ff3189f4db6697d2c0f54 100644 (file)
--- a/include/configs/davinci_dm355leopard.h
+++ b/include/configs/davinci_dm355leopard.h
@@ -16,7 +16,6 @@
 /* SoC Configuration */
 #define CONFIG_SYS_TIMERBASE           0x01c21400      /* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK            24000000        /* timer0 freq */
 /* SoC Configuration */
 #define CONFIG_SYS_TIMERBASE           0x01c21400      /* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK            24000000        /* timer0 freq */

-#define CONFIG_SOC_DM355                               /* DM355 based board */

 
 /* Memory Info */
 #define CONFIG_NR_DRAM_BANKS           1
 
 /* Memory Info */
 #define CONFIG_NR_DRAM_BANKS           1

diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h
index c50c059f65140eb7afe6385ad83c8de75a99617a..d75b43df4124f9c2e90cdf032d9d3f76c5994756 100644 (file)
--- a/include/configs/davinci_dm365evm.h
+++ b/include/configs/davinci_dm365evm.h
@@ -17,7 +17,6 @@
 /* SoC Configuration */
 #define CONFIG_SYS_TIMERBASE           0x01c21400      /* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK            24000000        /* timer0 freq */
 /* SoC Configuration */
 #define CONFIG_SYS_TIMERBASE           0x01c21400      /* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK            24000000        /* timer0 freq */

-#define CONFIG_SOC_DM365

 
 /* Memory Info */
 #define CONFIG_NR_DRAM_BANKS           1
 
 /* Memory Info */
 #define CONFIG_NR_DRAM_BANKS           1

diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h
index 2c5a837f6665c97240cb4a47a6dbbd404b112d83..a3fcd868d21bc941a9d6b050b1d5934551219341 100644 (file)
--- a/include/configs/davinci_dm6467evm.h
+++ b/include/configs/davinci_dm6467evm.h
@@ -26,7 +26,6 @@ extern unsigned int davinci_arm_clk_get(void);
 /* Timer Input clock freq */
 #define CONFIG_SYS_HZ_CLOCK            (CONFIG_SYS_CLK_FREQ/2)
 #define CONFIG_SYS_TIMERBASE           0x01c21400      /* use timer 0 */
 /* Timer Input clock freq */
 #define CONFIG_SYS_HZ_CLOCK            (CONFIG_SYS_CLK_FREQ/2)
 #define CONFIG_SYS_TIMERBASE           0x01c21400      /* use timer 0 */

-#define CONFIG_SOC_DM646X

 
 /* EEPROM definitions for EEPROM */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN         2
 
 /* EEPROM definitions for EEPROM */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN         2

diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h
index 2467f70522bed0a920f7351ed7dabe798949310d..e7710cb3f680327cfb392ccfe864d11429b0f430 100644 (file)
--- a/include/configs/davinci_dvevm.h
+++ b/include/configs/davinci_dvevm.h
@@ -43,7 +43,6 @@
 /*===================*/
 #define CONFIG_SYS_TIMERBASE           0x01c21400      /* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK            27000000        /* Timer Input clock freq */
 /*===================*/
 #define CONFIG_SYS_TIMERBASE           0x01c21400      /* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK            27000000        /* Timer Input clock freq */

-#define CONFIG_SOC_DM644X

 /*====================================================*/
 /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
 /* on Sonata/DV_EVM board. No EEPROM on schmoogie.    */
 /*====================================================*/
 /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
 /* on Sonata/DV_EVM board. No EEPROM on schmoogie.    */

diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h
index 2505465242128abdbc609805e2cab91a8beeeb2b..8776b4a2065968bc3286398bb1a9ae912c6c84e2 100644 (file)
--- a/include/configs/davinci_schmoogie.h
+++ b/include/configs/davinci_schmoogie.h
@@ -21,7 +21,6 @@
 /*===================*/
 #define CONFIG_SYS_TIMERBASE           0x01c21400      /* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK            27000000        /* Timer Input clock freq */
 /*===================*/
 #define CONFIG_SYS_TIMERBASE           0x01c21400      /* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK            27000000        /* Timer Input clock freq */

-#define CONFIG_SOC_DM644X

 /*=============*/
 /* Memory Info */
 /*=============*/
 /*=============*/
 /* Memory Info */
 /*=============*/

diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h
index e773835dd97fdaa51052b6f901d50e359d5bcaa4..dba7adeb7322fb0e9cd4e091040c6232af97586b 100644 (file)
--- a/include/configs/davinci_sffsdr.h
+++ b/include/configs/davinci_sffsdr.h
@@ -18,7 +18,6 @@
 /* SoC Configuration */
 #define CONFIG_SYS_TIMERBASE           0x01c21400      /* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK            27000000        /* Timer Input clock freq */
 /* SoC Configuration */
 #define CONFIG_SYS_TIMERBASE           0x01c21400      /* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK            27000000        /* Timer Input clock freq */

-#define CONFIG_SOC_DM644X

 /* EEPROM definitions for Atmel 24LC64 EEPROM chip */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN         2
 #define CONFIG_SYS_I2C_EEPROM_ADDR             0x50
 /* EEPROM definitions for Atmel 24LC64 EEPROM chip */
 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN         2
 #define CONFIG_SYS_I2C_EEPROM_ADDR             0x50

diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h
index dae37cdaf639bdb749203199b566d84267b7afbe..fc205471624fa87be3fc4f445df869a5e607341d 100644 (file)
--- a/include/configs/davinci_sonata.h
+++ b/include/configs/davinci_sonata.h
@@ -45,7 +45,6 @@
 /*===================*/
 #define CONFIG_SYS_TIMERBASE           0x01c21400      /* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK            27000000        /* Timer Input clock freq */
 /*===================*/
 #define CONFIG_SYS_TIMERBASE           0x01c21400      /* use timer 0 */
 #define CONFIG_SYS_HZ_CLOCK            27000000        /* Timer Input clock freq */

-#define CONFIG_SOC_DM644X

 /*====================================================*/
 /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
 /* on Sonata/DV_EVM board. No EEPROM on schmoogie.    */
 /*====================================================*/
 /* EEPROM definitions for Atmel 24C256BN SEEPROM chip */
 /* on Sonata/DV_EVM board. No EEPROM on schmoogie.    */

diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index 8a7447dcd3d73d773b86921b691a76a18b540c32..5bbd4431d1ba02d1d239390f0732f25a57ec8644 100644 (file)
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -13,24 +13,19 @@
 #define __CONFIG_H
 
 #define CONFIG_DBAU1X00                1
 #define __CONFIG_H
 
 #define CONFIG_DBAU1X00                1

-#define CONFIG_SOC_AU1X00      1  /* alchemy series cpu */

 
 #define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO
 
 #ifdef CONFIG_DBAU1000
 /* Also known as Merlot */
 
 #define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO
 
 #ifdef CONFIG_DBAU1000
 /* Also known as Merlot */

-#define CONFIG_SOC_AU1000      1

 #else
 #ifdef CONFIG_DBAU1100
 #else
 #ifdef CONFIG_DBAU1100

-#define CONFIG_SOC_AU1100      1

 #else
 #ifdef CONFIG_DBAU1500
 #else
 #ifdef CONFIG_DBAU1500

-#define CONFIG_SOC_AU1500      1

 #else
 #ifdef CONFIG_DBAU1550
 /* Cabernet */
 #else
 #ifdef CONFIG_DBAU1550
 /* Cabernet */

-#define CONFIG_SOC_AU1550      1

 #else
 #error "No valid board set"
 #endif
 #else
 #error "No valid board set"
 #endif

diff --git a/include/configs/ea20.h b/include/configs/ea20.h
index ae89368bfba18b9738976e74fd85401b4b328e43..1e616730ebabd988551c65ce8b2a605354eabc13 100644 (file)
--- a/include/configs/ea20.h
+++ b/include/configs/ea20.h
@@ -28,8 +28,6 @@
  * SoC Configuration
  */
 #define CONFIG_MACH_DAVINCI_DA850_EVM
  * SoC Configuration
  */
 #define CONFIG_MACH_DAVINCI_DA850_EVM

-#define CONFIG_SOC_DA8XX               /* TI DA8xx SoC */
-#define CONFIG_SOC_DA850               /* TI DA850 SoC */

 #define CONFIG_SYS_CLK_FREQ            clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ          24000000
 #define CONFIG_SYS_TIMERBASE           DAVINCI_TIMER0_BASE
 #define CONFIG_SYS_CLK_FREQ            clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ          24000000
 #define CONFIG_SYS_TIMERBASE           DAVINCI_TIMER0_BASE

diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h
index b4b3ae842f75b6aa71b8e15781db7ebf5a8afc2c..6bc1ac6f3a362f41e0bcba2c735d4fd7b070228c 100644 (file)
--- a/include/configs/embestmx6boards.h
+++ b/include/configs/embestmx6boards.h
@@ -27,7 +27,6 @@
 
 #define PHYS_SDRAM_SIZE                (1u * 1024 * 1024 * 1024)
 
 
 #define PHYS_SDRAM_SIZE                (1u * 1024 * 1024 * 1024)
 

-#define CONFIG_MX6

 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO

diff --git a/include/configs/enbw_cmc.h b/include/configs/enbw_cmc.h
index cdea4a854656aeabf1c70e6cf67306d66b86942d..3e622590627e6accd7ed07b05dca5a7d7efff306 100644 (file)
--- a/include/configs/enbw_cmc.h
+++ b/include/configs/enbw_cmc.h
@@ -25,8 +25,6 @@
 /*
  * SoC Configuration
  */
 /*
  * SoC Configuration
  */

-#define CONFIG_SOC_DA8XX               /* TI DA8xx SoC */
-#define CONFIG_SOC_DA850               /* TI DA850 SoC */

 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 #define CONFIG_SYS_CLK_FREQ            clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ          24000000
 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 #define CONFIG_SYS_CLK_FREQ            clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ          24000000

diff --git a/include/configs/flea3.h b/include/configs/flea3.h
index bf02829cde58f856efcf01647989fe3cdc9f603f..7f10e9b9329da904ab3fa1ce6fb6186f3e4e6207 100644 (file)
--- a/include/configs/flea3.h
+++ b/include/configs/flea3.h
@@ -16,7 +16,6 @@
 #include <asm/arch/imx-regs.h>
 
  /* High Level Configuration Options */
 #include <asm/arch/imx-regs.h>
 
  /* High Level Configuration Options */

-#define CONFIG_MX35

 
 #define CONFIG_SYS_DCACHE_OFF
 #define CONFIG_SYS_CACHELINE_SIZE      32
 
 #define CONFIG_SYS_DCACHE_OFF
 #define CONFIG_SYS_CACHELINE_SIZE      32

diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h
index 4f137fc96bf677f471adc0a9fe8a2fb1d2425d03..6e4f1264d95764e639775ea6560d27ac88823901 100644 (file)
--- a/include/configs/gw_ventana.h
+++ b/include/configs/gw_ventana.h
@@ -19,7 +19,6 @@
 
 #include "imx6_spl.h"                  /* common IMX6 SPL configuration */
 #include "mx6_common.h"
 
 #include "imx6_spl.h"                  /* common IMX6 SPL configuration */
 #include "mx6_common.h"

-#define CONFIG_MX6

 #define CONFIG_DISPLAY_CPUINFO         /* display cpu info */
 #define CONFIG_DISPLAY_BOARDINFO_LATE  /* display board info (after reloc) */
 
 #define CONFIG_DISPLAY_CPUINFO         /* display cpu info */
 #define CONFIG_DISPLAY_BOARDINFO_LATE  /* display board info (after reloc) */
 

diff --git a/include/configs/hawkboard.h b/include/configs/hawkboard.h
index 1d78e725e3cf407aabca1eb34c166e066035b0db..669e7f1f7aa0c0048ed799d024adb394d2a98958 100644 (file)
--- a/include/configs/hawkboard.h
+++ b/include/configs/hawkboard.h
@@ -20,8 +20,6 @@
  * SoC Configuration
  */
 #define CONFIG_MACH_DAVINCI_HAWK
  * SoC Configuration
  */
 #define CONFIG_MACH_DAVINCI_HAWK

-#define CONFIG_SOC_DA8XX               /* TI DA8xx SoC */
-#define CONFIG_SOC_DA850               /* TI DA850 SoC */

 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 #define CONFIG_SYS_CLK_FREQ            clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ          24000000
 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 #define CONFIG_SYS_CLK_FREQ            clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ          24000000

diff --git a/include/configs/hummingboard.h b/include/configs/hummingboard.h
index 34dbdce1a6c36e62e7b444c3c15f5bc042a95896..d58eacb1ed2b115f7c2f05c481e591451e7e7f58 100644 (file)
--- a/include/configs/hummingboard.h
+++ b/include/configs/hummingboard.h
@@ -16,7 +16,6 @@
 #include <asm/imx-common/gpio.h>
 #include <linux/sizes.h>
 
 #include <asm/imx-common/gpio.h>
 #include <linux/sizes.h>
 

-#define CONFIG_MX6

 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 


@@ -88,7 +87,6 @@
 #define CONFIG_PHY_ATHEROS
 #endif
 
 #define CONFIG_PHY_ATHEROS
 #endif
 

-#if defined(CONFIG_MX6S)

 #define CONFIG_DEFAULT_FDT_FILE                "imx6dl-hummingboard.dtb"
 #endif
 
 #define CONFIG_DEFAULT_FDT_FILE                "imx6dl-hummingboard.dtb"
 #endif
 

diff --git a/include/configs/ima3-mx53.h b/include/configs/ima3-mx53.h
index ad1614abbb922a57aeb08d8fa13f56a894de821e..b5909962f8770801ba8573fd1e07379349c4863a 100644 (file)
--- a/include/configs/ima3-mx53.h
+++ b/include/configs/ima3-mx53.h
@@ -12,7 +12,6 @@
 #define __CONFIG_H
 
 /* SOC type must be included before imx-regs.h */
 #define __CONFIG_H
 
 /* SOC type must be included before imx-regs.h */

-#define CONFIG_MX53

 #include <asm/arch/imx-regs.h>
 
 #define CONFIG_DISPLAY_CPUINFO
 #include <asm/arch/imx-regs.h>
 
 #define CONFIG_DISPLAY_CPUINFO

diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h
index 386dbd8895cdf34db16210f59b52c5594701afe3..b6909a97fcb8e594d2a25e375922abd4d89b77ed 100644 (file)
--- a/include/configs/imx27lite-common.h
+++ b/include/configs/imx27lite-common.h
@@ -13,7 +13,6 @@
 /*
  * SoC Configuration
  */
 /*
  * SoC Configuration
  */

-#define CONFIG_MX27

 #define CONFIG_MX27_CLK32      32768           /* OSC32K frequency */
 
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_MX27_CLK32      32768           /* OSC32K frequency */
 
 #define CONFIG_DISPLAY_BOARDINFO

diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h
index 0f2203254545af97739c0adaba8b1d4069de07e5..2b74402007ec683b9164c4269dbbc69557e3dee6 100644 (file)
--- a/include/configs/imx31_litekit.h
+++ b/include/configs/imx31_litekit.h
@@ -15,7 +15,6 @@
 #include <asm/arch/imx-regs.h>
 
  /* High Level Configuration Options */
 #include <asm/arch/imx-regs.h>
 
  /* High Level Configuration Options */

-#define CONFIG_MX31            1    /* This is a mx31 */

 #define CONFIG_MX31_CLK32      32000
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_MX31_CLK32      32000
 
 #define CONFIG_DISPLAY_CPUINFO

diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h
index 4195fa35330981d97e4831dfb6a8c19b21a7298a..74b0b082c3de812f17f3eebc829224cea837847f 100644 (file)
--- a/include/configs/imx31_phycore.h
+++ b/include/configs/imx31_phycore.h
@@ -15,7 +15,6 @@
 #include <asm/arch/imx-regs.h>
 
 /* High Level Configuration Options */
 #include <asm/arch/imx-regs.h>
 
 /* High Level Configuration Options */

-#define CONFIG_MX31                    /* This is a mx31 */

 #define CONFIG_MX31_CLK32      32000
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_MX31_CLK32      32000
 
 #define CONFIG_DISPLAY_CPUINFO

diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h
index 310d5e2106aca2f921fe580143e979e78c98142e..982941c9a9233adf265bb6626263bdd5f31264cf 100644 (file)
--- a/include/configs/ipam390.h
+++ b/include/configs/ipam390.h
@@ -25,8 +25,6 @@
  * SoC Configuration
  */
 #define CONFIG_MACH_DAVINCI_DA850_EVM
  * SoC Configuration
  */
 #define CONFIG_MACH_DAVINCI_DA850_EVM

-#define CONFIG_SOC_DA8XX               /* TI DA8xx SoC */
-#define CONFIG_SOC_DA850               /* TI DA850 SoC */

 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 #define CONFIG_SYS_CLK_FREQ            clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ          24000000
 #define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
 #define CONFIG_SYS_CLK_FREQ            clk_get(DAVINCI_ARM_CLKID)
 #define CONFIG_SYS_OSCIN_FREQ          24000000

diff --git a/include/configs/k2e_evm.h b/include/configs/k2e_evm.h
index d83e07e24238bcd1d124c9ddf07371bef6d38171..4992d1d2fe5930be7d888b016e7f11c1e918f685 100644 (file)
--- a/include/configs/k2e_evm.h
+++ b/include/configs/k2e_evm.h
@@ -11,7 +11,6 @@
 #define __CONFIG_K2E_EVM_H
 
 /* Platform type */
 #define __CONFIG_K2E_EVM_H
 
 /* Platform type */

-#define CONFIG_SOC_K2E

 #define CONFIG_K2E_EVM
 
 /* U-Boot general configuration */
 #define CONFIG_K2E_EVM
 
 /* U-Boot general configuration */

diff --git a/include/configs/k2hk_evm.h b/include/configs/k2hk_evm.h
index ffddf1391c435e9fbd5b43e1c6b1d93f2afbf34f..594ba0a0107a34647de86ef0e1fd2b742598b3ca 100644 (file)
--- a/include/configs/k2hk_evm.h
+++ b/include/configs/k2hk_evm.h
@@ -11,7 +11,6 @@
 #define __CONFIG_K2HK_EVM_H
 
 /* Platform type */
 #define __CONFIG_K2HK_EVM_H
 
 /* Platform type */

-#define CONFIG_SOC_K2HK

 #define CONFIG_K2HK_EVM
 
 /* U-Boot general configuration */
 #define CONFIG_K2HK_EVM
 
 /* U-Boot general configuration */

diff --git a/include/configs/k2l_evm.h b/include/configs/k2l_evm.h
index 805164a679defaa67f2f03e19df9b62ca228b2e3..9c08690ff7caadf9f58ad42cfc5c81550f305ac6 100644 (file)
--- a/include/configs/k2l_evm.h
+++ b/include/configs/k2l_evm.h
@@ -11,7 +11,6 @@
 #define __CONFIG_K2L_EVM_H
 
 /* Platform type */
 #define __CONFIG_K2L_EVM_H
 
 /* Platform type */

-#define CONFIG_SOC_K2L

 #define CONFIG_K2L_EVM
 
 /* U-Boot general configuration */
 #define CONFIG_K2L_EVM
 
 /* U-Boot general configuration */

diff --git a/include/configs/ks2_evm.h b/include/configs/ks2_evm.h
index 42280ca0a505834d8e61e2e2c8c28f25802c65f9..bf7833607a9c979e20331acf564e742b1f74af50 100644 (file)
--- a/include/configs/ks2_evm.h
+++ b/include/configs/ks2_evm.h
@@ -10,7 +10,6 @@
 #ifndef __CONFIG_KS2_EVM_H
 #define __CONFIG_KS2_EVM_H
 
 #ifndef __CONFIG_KS2_EVM_H
 #define __CONFIG_KS2_EVM_H
 

-#define CONFIG_SOC_KEYSTONE

 
 /* U-Boot Build Configuration */
 #define CONFIG_SKIP_LOWLEVEL_INIT      /* U-Boot is a 2nd stage loader */
 
 /* U-Boot Build Configuration */
 #define CONFIG_SKIP_LOWLEVEL_INIT      /* U-Boot is a 2nd stage loader */

diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h
index 2874ccc6fadd2847b98fe5018fb3c6f16479fae7..dc3c6d22949d72dadebc34459545c77db3939e16 100644 (file)
--- a/include/configs/ls1021aqds.h
+++ b/include/configs/ls1021aqds.h
@@ -9,7 +9,6 @@
 
 #include <config_cmd_default.h>
 
 
 #include <config_cmd_default.h>
 

-#define CONFIG_LS102XA

 
 #define CONFIG_SYS_GENERIC_BOARD
 
 
 #define CONFIG_SYS_GENERIC_BOARD
 

diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h
index 0a0bb5f1099ea789b8da6dabe00778745527ecf0..24b1709ad9d61efeea50c14dfce3a8ffa7732941 100644 (file)
--- a/include/configs/ls1021atwr.h
+++ b/include/configs/ls1021atwr.h
@@ -9,7 +9,6 @@
 
 #include <config_cmd_default.h>
 
 
 #include <config_cmd_default.h>
 

-#define CONFIG_LS102XA

 
 #define CONFIG_SYS_GENERIC_BOARD
 
 
 #define CONFIG_SYS_GENERIC_BOARD
 

diff --git a/include/configs/m28evk.h b/include/configs/m28evk.h
index 5c209913e544e01ff713c1ee98c15d7e3acf638e..c5e795f522786952e6164370fd746e4061425557 100644 (file)
--- a/include/configs/m28evk.h
+++ b/include/configs/m28evk.h
@@ -8,7 +8,6 @@
 #define __CONFIGS_M28EVK_H__
 
 /* System configurations */
 #define __CONFIGS_M28EVK_H__
 
 /* System configurations */

-#define CONFIG_MX28                            /* i.MX28 SoC */

 #define MACH_TYPE_M28EVK       3613
 #define CONFIG_MACH_TYPE       MACH_TYPE_M28EVK
 
 #define MACH_TYPE_M28EVK       3613
 #define CONFIG_MACH_TYPE       MACH_TYPE_M28EVK
 

diff --git a/include/configs/m53evk.h b/include/configs/m53evk.h
index c133ba9d03f504eda7b7329abd1093fcb32388b5..0f894e3fb22714119abfdff171095914cc4a9f49 100644 (file)
--- a/include/configs/m53evk.h
+++ b/include/configs/m53evk.h
@@ -8,7 +8,6 @@
 #ifndef __M53EVK_CONFIG_H__
 #define __M53EVK_CONFIG_H__
 
 #ifndef __M53EVK_CONFIG_H__
 #define __M53EVK_CONFIG_H__
 

-#define CONFIG_MX53

 #define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_MXC_GPIO
 
 #define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_MXC_GPIO
 

diff --git a/include/configs/mx23_olinuxino.h b/include/configs/mx23_olinuxino.h
index e377fea24a651da3596f33890367b83275f5a8eb..564f4ec9afc85395ae9d3f14d02242ebd8c8b48a 100644 (file)
--- a/include/configs/mx23_olinuxino.h
+++ b/include/configs/mx23_olinuxino.h
@@ -7,7 +7,6 @@
 #define __CONFIGS_MX23_OLINUXINO_H__
 
 /* System configurations */
 #define __CONFIGS_MX23_OLINUXINO_H__
 
 /* System configurations */

-#define CONFIG_MX23                            /* i.MX23 SoC */

 #define CONFIG_MACH_TYPE       4105
 
 /* U-Boot Commands */
 #define CONFIG_MACH_TYPE       4105
 
 /* U-Boot Commands */

diff --git a/include/configs/mx23evk.h b/include/configs/mx23evk.h
index b496892f0672ff01333ad564a3cdf8dc270bf488..05f5ddb6e3177bef99cea73d2e446713afb45047 100644 (file)
--- a/include/configs/mx23evk.h
+++ b/include/configs/mx23evk.h
@@ -10,7 +10,6 @@
 #define __CONFIGS_MX23EVK_H__
 
 /* System configurations */
 #define __CONFIGS_MX23EVK_H__
 
 /* System configurations */

-#define CONFIG_MX23                            /* i.MX23 SoC */

 #define CONFIG_MACH_TYPE       MACH_TYPE_MX23EVK
 
 /* U-Boot Commands */
 #define CONFIG_MACH_TYPE       MACH_TYPE_MX23EVK
 
 /* U-Boot Commands */

diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h
index c02e29be9ad64f2cde75ab3a8f8142ce495b1dc9..ec4e42f48c45d18ae746432424297de3ced3618e 100644 (file)
--- a/include/configs/mx25pdk.h
+++ b/include/configs/mx25pdk.h
@@ -11,7 +11,6 @@
 
 /* High Level Configuration Options */
 
 
 /* High Level Configuration Options */
 

-#define CONFIG_MX25

 #define CONFIG_SYS_TEXT_BASE           0x81200000
 #define CONFIG_MXC_GPIO
 #define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_SYS_TEXT_BASE           0x81200000
 #define CONFIG_MXC_GPIO
 #define CONFIG_SYS_GENERIC_BOARD

diff --git a/include/configs/mx28evk.h b/include/configs/mx28evk.h
index 9daa0bf540060ecdbde69496015a8a18a0949659..bfd51c5bba41f2ee9632a8fa2e32c98532456bb2 100644 (file)
--- a/include/configs/mx28evk.h
+++ b/include/configs/mx28evk.h
@@ -12,7 +12,6 @@
 #define __CONFIGS_MX28EVK_H__
 
 /* System configurations */
 #define __CONFIGS_MX28EVK_H__
 
 /* System configurations */

-#define CONFIG_MX28                            /* i.MX28 SoC */

 #define CONFIG_MACH_TYPE       MACH_TYPE_MX28EVK
 
 /* U-Boot Commands */
 #define CONFIG_MACH_TYPE       MACH_TYPE_MX28EVK
 
 /* U-Boot Commands */

diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
index 0f4bd91c645d0be4177fa7cf5855710b1e46cce1..f4f2670213986dae24da108c59fff6edd3ec1632 100644 (file)
--- a/include/configs/mx31ads.h
+++ b/include/configs/mx31ads.h
@@ -12,7 +12,6 @@
 #include <asm/arch/imx-regs.h>
 
  /* High Level Configuration Options */
 #include <asm/arch/imx-regs.h>
 
  /* High Level Configuration Options */

-#define CONFIG_MX31            1               /* This is a mx31 */

 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO

diff --git a/include/configs/mx31pdk.h b/include/configs/mx31pdk.h
index 2a3e53c7928ca8d32950df854307330026dce538..974a0145711a97311b13410386257b3a72012937 100644 (file)
--- a/include/configs/mx31pdk.h
+++ b/include/configs/mx31pdk.h
@@ -17,7 +17,6 @@
 #include <asm/arch/imx-regs.h>
 
 /* High Level Configuration Options */
 #include <asm/arch/imx-regs.h>
 
 /* High Level Configuration Options */

-#define CONFIG_MX31                    /* This is a mx31 */

 
 #define CONFIG_SYS_GENERIC_BOARD
 
 
 #define CONFIG_SYS_GENERIC_BOARD
 

diff --git a/include/configs/mx35pdk.h b/include/configs/mx35pdk.h
index a145f0812f39803a5572fcdb62427a4963961743..34eb1cfcd6c2ea3b3fd70f7530c7c67cf232af27 100644 (file)
--- a/include/configs/mx35pdk.h
+++ b/include/configs/mx35pdk.h
@@ -16,7 +16,6 @@
 #include <asm/arch/imx-regs.h>
 
  /* High Level Configuration Options */
 #include <asm/arch/imx-regs.h>
 
  /* High Level Configuration Options */

-#define CONFIG_MX35

 
 #define CONFIG_DISPLAY_CPUINFO
 
 
 #define CONFIG_DISPLAY_CPUINFO
 

diff --git a/include/configs/mx51_efikamx.h b/include/configs/mx51_efikamx.h
index fce7ead977a5caebb7c09a098b116a1d66358241..89c36a56a4688b84e2709fcc78451455888236a7 100644 (file)
--- a/include/configs/mx51_efikamx.h
+++ b/include/configs/mx51_efikamx.h
@@ -17,7 +17,6 @@
  * High Level Board Configuration Options
  */
 /* An i.MX51 CPU */
  * High Level Board Configuration Options
  */
 /* An i.MX51 CPU */

-#define CONFIG_MX51

 
 #define        machine_is_efikamx()    (CONFIG_MACH_TYPE == MACH_TYPE_MX51_EFIKAMX)
 #define        machine_is_efikasb()    (CONFIG_MACH_TYPE == MACH_TYPE_MX51_EFIKASB)
 
 #define        machine_is_efikamx()    (CONFIG_MACH_TYPE == MACH_TYPE_MX51_EFIKAMX)
 #define        machine_is_efikasb()    (CONFIG_MACH_TYPE == MACH_TYPE_MX51_EFIKASB)

diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h
index d6e8ec4e13e67b5609e77d6975d9d06fe832dfd8..3d4b8396b191383cb46e7d50032f896f9f139f50 100644 (file)
--- a/include/configs/mx51evk.h
+++ b/include/configs/mx51evk.h
@@ -13,7 +13,6 @@
 
  /* High Level Configuration Options */
 
 
  /* High Level Configuration Options */
 

-#define CONFIG_MX51    /* in a mx51 */

 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO

diff --git a/include/configs/mx53ard.h b/include/configs/mx53ard.h
index 134d6804bcfb5ce2a28a469d8243f82223c03469..9015d02b0f04d9f553352cda24736aa26c4a8b23 100644 (file)
--- a/include/configs/mx53ard.h
+++ b/include/configs/mx53ard.h
@@ -9,7 +9,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
 

-#define CONFIG_MX53

 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO

diff --git a/include/configs/mx53evk.h b/include/configs/mx53evk.h
index fb2072d2f0f49b7fb2a7ee79e725a0dd20db0187..007b952c7edef27d226434400df2624e12174783 100644 (file)
--- a/include/configs/mx53evk.h
+++ b/include/configs/mx53evk.h
@@ -9,7 +9,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
 

-#define CONFIG_MX53

 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO

diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h
index 42bc3c869f82b3d0b0c2ee0159c9f8a760561a3e..c3ffd38de9e5b2a420eb97a319250e992fa3164b 100644 (file)
--- a/include/configs/mx53loco.h
+++ b/include/configs/mx53loco.h
@@ -10,7 +10,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
 

-#define CONFIG_MX53

 
 #define CONFIG_DISPLAY_BOARDINFO
 
 
 #define CONFIG_DISPLAY_BOARDINFO
 

diff --git a/include/configs/mx53smd.h b/include/configs/mx53smd.h
index 3da0ef4bd0b9bc43d6e88fd6e8460ba3a653f8a8..1a97c069b748f3df47aa200b9a43a2712eb441bb 100644 (file)
--- a/include/configs/mx53smd.h
+++ b/include/configs/mx53smd.h
@@ -9,7 +9,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
 

-#define CONFIG_MX53

 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO

diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
index 76cfef123cd13d5adc5f2b51579eb5023980c3c4..906adefa89c1b90fef67f399ab04ba4b73b34406 100644 (file)
--- a/include/configs/mx6qarm2.h
+++ b/include/configs/mx6qarm2.h
@@ -9,7 +9,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
 

-#define CONFIG_MX6

 
 #include "mx6_common.h"
 
 
 #include "mx6_common.h"
 

diff --git a/include/configs/mx6qsabreauto.h b/include/configs/mx6qsabreauto.h
index 51042ca72e54b7b8e2e1084ac2e96ed9da9615ff..0f77e7f041c96098802b83266afd246d400d4599 100644 (file)
--- a/include/configs/mx6qsabreauto.h
+++ b/include/configs/mx6qsabreauto.h
@@ -12,9 +12,7 @@
 #define CONFIG_MACH_TYPE       3529
 #define CONFIG_MXC_UART_BASE   UART4_BASE
 #define CONFIG_CONSOLE_DEV             "ttymxc3"
 #define CONFIG_MACH_TYPE       3529
 #define CONFIG_MXC_UART_BASE   UART4_BASE
 #define CONFIG_CONSOLE_DEV             "ttymxc3"

-#if defined CONFIG_MX6Q

 #define CONFIG_DEFAULT_FDT_FILE        "imx6q-sabreauto.dtb"
 #define CONFIG_DEFAULT_FDT_FILE        "imx6q-sabreauto.dtb"

-#elif defined CONFIG_MX6DL

 #define CONFIG_DEFAULT_FDT_FILE        "imx6dl-sabreauto.dtb"
 #endif
 #define CONFIG_MMCROOT                 "/dev/mmcblk0p2"
 #define CONFIG_DEFAULT_FDT_FILE        "imx6dl-sabreauto.dtb"
 #endif
 #define CONFIG_MMCROOT                 "/dev/mmcblk0p2"

diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h
index f0f721e9b7ef586ed0a0776167e17365529c047c..da010ebf17c36eb34ffcd5907ac945fa46b10948 100644 (file)
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -9,7 +9,6 @@
 #ifndef __MX6QSABRE_COMMON_CONFIG_H
 #define __MX6QSABRE_COMMON_CONFIG_H
 
 #ifndef __MX6QSABRE_COMMON_CONFIG_H
 #define __MX6QSABRE_COMMON_CONFIG_H
 

-#define CONFIG_MX6

 
 #include "mx6_common.h"
 #include <linux/sizes.h>
 
 #include "mx6_common.h"
 #include <linux/sizes.h>

diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h
index 99d9d4d7cfbf5a5c54de344f7fec4ec84c92fa89..d477bb206b9297309fd24555c9dbfb69f4eb6799 100644 (file)
--- a/include/configs/mx6sabresd.h
+++ b/include/configs/mx6sabresd.h
@@ -22,9 +22,7 @@
 #define CONFIG_MXC_UART_BASE   UART1_BASE
 #define CONFIG_CONSOLE_DEV             "ttymxc0"
 #define CONFIG_MMCROOT                 "/dev/mmcblk1p2"
 #define CONFIG_MXC_UART_BASE   UART1_BASE
 #define CONFIG_CONSOLE_DEV             "ttymxc0"
 #define CONFIG_MMCROOT                 "/dev/mmcblk1p2"

-#if defined(CONFIG_MX6Q)

 #define CONFIG_DEFAULT_FDT_FILE        "imx6q-sabresd.dtb"
 #define CONFIG_DEFAULT_FDT_FILE        "imx6q-sabresd.dtb"

-#elif defined(CONFIG_MX6DL)

 #define CONFIG_DEFAULT_FDT_FILE        "imx6dl-sabresd.dtb"
 #endif
 #define PHYS_SDRAM_SIZE                (1u * 1024 * 1024 * 1024)
 #define CONFIG_DEFAULT_FDT_FILE        "imx6dl-sabresd.dtb"
 #endif
 #define PHYS_SDRAM_SIZE                (1u * 1024 * 1024 * 1024)

diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
index e6c41306a36001a52ef62e96704253eb283dd376..dd0f90041eb86a2b7bccf087b291dbbff89a3f10 100644 (file)
--- a/include/configs/mx6slevk.h
+++ b/include/configs/mx6slevk.h
@@ -14,7 +14,6 @@
 #include <linux/sizes.h>
 #include "mx6_common.h"
 
 #include <linux/sizes.h>
 #include "mx6_common.h"
 

-#define CONFIG_MX6

 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 

diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index fbaae3f505b577d9ce124dc21d1da4215eff12a0..e1de60d6e3738341926cfbd6e41b356a9e6179c1 100644 (file)
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -14,7 +14,6 @@
 #include <linux/sizes.h>
 #include "mx6_common.h"
 
 #include <linux/sizes.h>
 #include "mx6_common.h"
 

-#define CONFIG_MX6

 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 

diff --git a/include/configs/mxs.h b/include/configs/mxs.h
index dea8227aeb7c83579d6ba0280c11c3615227a1dd..70dc50ca348829c26967dfd26a97c24eed31725c 100644 (file)
--- a/include/configs/mxs.h
+++ b/include/configs/mxs.h
@@ -23,17 +23,17 @@
  * Includes
  */
 
  * Includes
  */
 

-#if defined(CONFIG_MX23) && defined(CONFIG_MX28)
-#error Select either CONFIG_MX23 or CONFIG_MX28 , never both!
-#elif !defined(CONFIG_MX23) && !defined(CONFIG_MX28)
-#error Select one of CONFIG_MX23 or CONFIG_MX28 !
+#if defined(CONFIG_SOC_MX23) && defined(CONFIG_SOC_MX28)
+#error Select either CONFIG_SOC_MX23 or CONFIG_SOC_MX28 , never both!
+#elif !defined(CONFIG_SOC_MX23) && !defined(CONFIG_SOC_MX28)
+#error Select one of CONFIG_SOC_MX23 or CONFIG_SOC_MX28 !

 #endif
 
 #include <asm/arch/regs-base.h>
 
 #endif
 
 #include <asm/arch/regs-base.h>
 

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

 #include <asm/arch/iomux-mx23.h>
 #include <asm/arch/iomux-mx23.h>

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

 #include <asm/arch/iomux-mx28.h>
 #endif
 
 #include <asm/arch/iomux-mx28.h>
 #endif
 


@@ -64,9 +64,9 @@
 
 /* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */
 #define CONFIG_SYS_INIT_RAM_ADDR       0x00000000
 
 /* OCRAM at 0x0 ; 32kB on MX23 ; 128kB on MX28 */
 #define CONFIG_SYS_INIT_RAM_ADDR       0x00000000

-#if defined(CONFIG_MX23)
+#if defined(CONFIG_SOC_MX23)

 #define CONFIG_SYS_INIT_RAM_SIZE       (32 * 1024)
 #define CONFIG_SYS_INIT_RAM_SIZE       (32 * 1024)

-#elif defined(CONFIG_MX28)
+#elif defined(CONFIG_SOC_MX28)

 #define CONFIG_SYS_INIT_RAM_SIZE       (128 * 1024)
 #endif
 
 #define CONFIG_SYS_INIT_RAM_SIZE       (128 * 1024)
 #endif
 

diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h
index 6d379ed7ad30eb1ea68c8b03c9099301e764974d..33b8554058aa946396c3d84176a79fba5b2b0910 100644 (file)
--- a/include/configs/nitrogen6x.h
+++ b/include/configs/nitrogen6x.h
@@ -11,7 +11,6 @@
 #define __CONFIG_H
 
 #include "mx6_common.h"
 #define __CONFIG_H
 
 #include "mx6_common.h"

-#define CONFIG_MX6

 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 


@@ -82,7 +81,6 @@
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 
 #define CONFIG_CMD_FAT
 #define CONFIG_DOS_PARTITION
 

-#ifdef CONFIG_MX6Q

 #define CONFIG_CMD_SATA
 #endif
 
 #define CONFIG_CMD_SATA
 #endif
 

diff --git a/include/configs/novena.h b/include/configs/novena.h
index ea75d2c2b97e3fe03256197cce8b6214c40d2d29..0eb061138ad737f799d012d1af39f88d2ffb64f9 100644 (file)
--- a/include/configs/novena.h
+++ b/include/configs/novena.h
@@ -10,7 +10,6 @@
 #define __CONFIG_H
 
 /* System configurations */
 #define __CONFIG_H
 
 /* System configurations */

-#define CONFIG_MX6

 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_LATE_INIT
 #define CONFIG_MISC_INIT_R
 #define CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_LATE_INIT
 #define CONFIG_MISC_INIT_R

diff --git a/include/configs/ot1200.h b/include/configs/ot1200.h
index 255c933baa4be2a2440e831f7fdbe97ee32627bd..9b902b5cad2fb28c754beb87fa16c3bb63f4a3f5 100644 (file)
--- a/include/configs/ot1200.h
+++ b/include/configs/ot1200.h
@@ -9,7 +9,6 @@
 #define __CONFIG_H
 
 #include "mx6_common.h"
 #define __CONFIG_H
 
 #include "mx6_common.h"

-#define CONFIG_MX6

 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 


@@ -91,7 +90,6 @@
 #define CONFIG_MXC_USB_PORTSC   (PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
 
 #define CONFIG_MXC_USB_PORTSC   (PORT_PTS_UTMI | PORT_PTS_PTW)
 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
 

-#ifdef CONFIG_MX6Q

 #define CONFIG_CMD_SATA
 #endif
 
 #define CONFIG_CMD_SATA
 #endif
 

diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h
index 61e6af384d4b21d5a957aa668d0bceed05566eef..f92004855586630a4146835c980145dadb7ba94a 100644 (file)
--- a/include/configs/pb1x00.h
+++ b/include/configs/pb1x00.h
@@ -13,19 +13,15 @@
 #define __CONFIG_H
 
 #define CONFIG_PB1X00          1
 #define __CONFIG_H
 
 #define CONFIG_PB1X00          1

-#define CONFIG_SOC_AU1X00      1  /* alchemy series cpu */

 
 #define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO
 
 #ifdef CONFIG_PB1000
 
 #define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_BOARDINFO
 
 #ifdef CONFIG_PB1000

-#define CONFIG_SOC_AU1000      1

 #else
 #ifdef CONFIG_PB1100
 #else
 #ifdef CONFIG_PB1100

-#define CONFIG_SOC_AU1100      1

 #else
 #ifdef CONFIG_PB1500
 #else
 #ifdef CONFIG_PB1500

-#define CONFIG_SOC_AU1500      1

 #else
 #error "No valid board set"
 #endif
 #else
 #error "No valid board set"
 #endif

diff --git a/include/configs/qong.h b/include/configs/qong.h
index d383fe878f547ecc58a206ba7b60e6037ca206ef..8faf6a88d96ef03c86eb41b85da44db0e856779f 100644 (file)
--- a/include/configs/qong.h
+++ b/include/configs/qong.h
@@ -12,7 +12,6 @@
 #include <asm/arch/imx-regs.h>
 
 /* High Level Configuration Options */
 #include <asm/arch/imx-regs.h>
 
 /* High Level Configuration Options */

-#define CONFIG_MX31                    /* This is a mx31 */

 #define CONFIG_QONG
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_QONG
 
 #define CONFIG_DISPLAY_CPUINFO

diff --git a/include/configs/sansa_fuze_plus.h b/include/configs/sansa_fuze_plus.h
index 8cce34af76337107fe8ba0be48efaadcf810a000..6573ac3c0b760d6e13611c74faf8873e8ce62fd0 100644 (file)
--- a/include/configs/sansa_fuze_plus.h
+++ b/include/configs/sansa_fuze_plus.h
@@ -7,7 +7,6 @@
 #define __CONFIGS_SANSA_FUZE_PLUS_H__
 
 /* System configurations */
 #define __CONFIGS_SANSA_FUZE_PLUS_H__
 
 /* System configurations */

-#define CONFIG_MX23                            /* i.MX23 SoC */

 
 /* U-Boot Commands */
 #define CONFIG_SYS_NO_FLASH
 
 /* U-Boot Commands */
 #define CONFIG_SYS_NO_FLASH

diff --git a/include/configs/sc_sps_1.h b/include/configs/sc_sps_1.h
index 16d2e2d22b40a232a8b0be78b8f1c39df9a0d485..ff74cb2639c5d7b4185fbd838ad459129c91d36d 100644 (file)
--- a/include/configs/sc_sps_1.h
+++ b/include/configs/sc_sps_1.h
@@ -10,7 +10,6 @@
 #define __CONFIGS_SC_SPS_1_H__
 
 /* System configuration */
 #define __CONFIGS_SC_SPS_1_H__
 
 /* System configuration */

-#define CONFIG_MX28                            /* i.MX28 SoC */

 #define MACH_TYPE_SC_SPS_1     4172
 #define CONFIG_MACH_TYPE       MACH_TYPE_SC_SPS_1
 
 #define MACH_TYPE_SC_SPS_1     4172
 #define CONFIG_MACH_TYPE       MACH_TYPE_SC_SPS_1
 

diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h
index 6b1f967c44eb2068ecac0cc2270c46485e705654..17eab017767944df1baca11138e6da55e7cde629 100644 (file)
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@@ -3,17 +3,13 @@
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */

-#ifndef __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__
-#define __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__

 
 #define CONFIG_SYS_GENERIC_BOARD
 
 /* Virtual target or real hardware */
 
 #define CONFIG_SYS_GENERIC_BOARD
 
 /* Virtual target or real hardware */

-#undef CONFIG_SOCFPGA_VIRTUAL_TARGET

 
 #define CONFIG_SYS_THUMB_BUILD
 
 
 #define CONFIG_SYS_THUMB_BUILD
 

-#define CONFIG_SOCFPGA

 
 /*
  * High level configuration
 
 /*
  * High level configuration


@@ -47,7 +43,6 @@
        GENERATED_GBL_DATA_SIZE)
 
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
        GENERATED_GBL_DATA_SIZE)
 
 #define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1

-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET

 #define CONFIG_SYS_TEXT_BASE           0x08000040
 #else
 #define CONFIG_SYS_TEXT_BASE           0x01000040
 #define CONFIG_SYS_TEXT_BASE           0x08000040
 #else
 #define CONFIG_SYS_TEXT_BASE           0x01000040


@@ -99,7 +94,6 @@
 /*
  * Ethernet on SoC (EMAC)
  */
 /*
  * Ethernet on SoC (EMAC)
  */

-#if defined(CONFIG_CMD_NET) && !defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)

 #define CONFIG_DESIGNWARE_ETH
 #define CONFIG_NET_MULTI
 #define CONFIG_DW_ALTDESCRIPTOR
 #define CONFIG_DESIGNWARE_ETH
 #define CONFIG_NET_MULTI
 #define CONFIG_DW_ALTDESCRIPTOR


@@ -126,7 +120,6 @@
 #define CONFIG_SYS_TIMERBASE           SOCFPGA_OSC1TIMER0_ADDRESS
 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 #define CONFIG_SYS_TIMER_COUNTER       (CONFIG_SYS_TIMERBASE + 0x4)
 #define CONFIG_SYS_TIMERBASE           SOCFPGA_OSC1TIMER0_ADDRESS
 #define CONFIG_SYS_TIMER_COUNTS_DOWN
 #define CONFIG_SYS_TIMER_COUNTER       (CONFIG_SYS_TIMERBASE + 0x4)

-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET

 #define CONFIG_SYS_TIMER_RATE          2400000
 #else
 #define CONFIG_SYS_TIMER_RATE          25000000
 #define CONFIG_SYS_TIMER_RATE          2400000
 #else
 #define CONFIG_SYS_TIMER_RATE          25000000


@@ -150,10 +143,6 @@
 #define CONFIG_BOUNCE_BUFFER
 #define CONFIG_GENERIC_MMC
 #define CONFIG_DWMMC
 #define CONFIG_BOUNCE_BUFFER
 #define CONFIG_GENERIC_MMC
 #define CONFIG_DWMMC

-#define CONFIG_SOCFPGA_DWMMC
-#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH        1024
-#define CONFIG_SOCFPGA_DWMMC_DRVSEL    3
-#define CONFIG_SOCFPGA_DWMMC_SMPSEL    0

 /* FIXME */
 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 #define CONFIG_SYS_MMC_MAX_BLK_COUNT   256     /* FIXME -- SPL only? */
 /* FIXME */
 /* using smaller max blk cnt to avoid flooding the limited stack we have */
 #define CONFIG_SYS_MMC_MAX_BLK_COUNT   256     /* FIXME -- SPL only? */


@@ -224,7 +213,6 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE    -4
 #define CONFIG_SYS_NS16550_COM1                SOCFPGA_UART0_ADDRESS
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE    -4
 #define CONFIG_SYS_NS16550_COM1                SOCFPGA_UART0_ADDRESS

-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET

 #define CONFIG_SYS_NS16550_CLK         1000000
 #else
 #define CONFIG_SYS_NS16550_CLK         100000000
 #define CONFIG_SYS_NS16550_CLK         1000000
 #else
 #define CONFIG_SYS_NS16550_CLK         100000000


@@ -317,4 +305,3 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
 #undef CONFIG_PARTITIONS
 #endif
 
 #undef CONFIG_PARTITIONS
 #endif
 

-#endif /* __CONFIG_SOCFPGA_CYCLONE5_COMMON_H__ */

diff --git a/include/configs/socfpga_cyclone5.h b/include/configs/socfpga_cyclone5.h
index c3d958cb3077ddf1211c8aa57efd46edfcbfaf94..755677e14b5610414bac070c2a028896734bbc92 100644 (file)
--- a/include/configs/socfpga_cyclone5.h
+++ b/include/configs/socfpga_cyclone5.h
@@ -3,8 +3,6 @@
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */
  *
  * SPDX-License-Identifier:    GPL-2.0+
  */

-#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
-#define __CONFIG_SOCFPGA_CYCLONE5_H__

 
 #include <asm/arch/socfpga_base_addrs.h>
 #include "../../board/altera/socfpga/pinmux_config.h"
 
 #include <asm/arch/socfpga_base_addrs.h>
 #include "../../board/altera/socfpga/pinmux_config.h"


@@ -43,7 +41,6 @@
 #define CONFIG_BOOTDELAY       3
 #define CONFIG_BOOTFILE                "zImage"
 #define CONFIG_BOOTARGS                "console=ttyS0," __stringify(CONFIG_BAUDRATE)
 #define CONFIG_BOOTDELAY       3
 #define CONFIG_BOOTFILE                "zImage"
 #define CONFIG_BOOTARGS                "console=ttyS0," __stringify(CONFIG_BAUDRATE)

-#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET

 #define CONFIG_BOOTCOMMAND     "run ramboot"
 #else
 #define CONFIG_BOOTCOMMAND     "run mmcload; run mmcboot"
 #define CONFIG_BOOTCOMMAND     "run ramboot"
 #else
 #define CONFIG_BOOTCOMMAND     "run mmcload; run mmcboot"


@@ -95,4 +92,3 @@
 /* The rest of the configuration is shared */
 #include <configs/socfpga_common.h>
 
 /* The rest of the configuration is shared */
 #include <configs/socfpga_common.h>
 

-#endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */

diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index c654a0e4ebc01bbb4f486e0c1cf977eb6342efff..9b54ba6866f894dea8454f291f84f9a1ad1249e9 100644 (file)
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -26,7 +26,6 @@
 #define CONFIG_BOOKE           1       /* BOOKE                        */
 #define CONFIG_E500            1       /* BOOKE e500 family            */
 #define CONFIG_MPC8544         1
 #define CONFIG_BOOKE           1       /* BOOKE                        */
 #define CONFIG_E500            1       /* BOOKE e500 family            */
 #define CONFIG_MPC8544         1

-#define CONFIG_SOCRATES                1

 
 #define        CONFIG_SYS_TEXT_BASE    0xfff80000
 
 
 #define        CONFIG_SYS_TEXT_BASE    0xfff80000
 

diff --git a/include/configs/tbs2910.h b/include/configs/tbs2910.h
index c097b98575d260f5a3e70d6d436ab8bf7ac4e4d6..ce651baa7092c4b3ef19ab69487095aa6aade31d 100644 (file)
--- a/include/configs/tbs2910.h
+++ b/include/configs/tbs2910.h
@@ -14,7 +14,6 @@
 #include <asm/imx-common/gpio.h>
 
 /* General configuration */
 #include <asm/imx-common/gpio.h>
 
 /* General configuration */

-#define CONFIG_MX6

 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO_LATE
 #define CONFIG_SYS_THUMB_BUILD
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO_LATE
 #define CONFIG_SYS_THUMB_BUILD

diff --git a/include/configs/titanium.h b/include/configs/titanium.h
index f9e00c5b8b7019ed7803288b8306db74a90ba457..764fd5d121a4a97aa54afa9eb19f37b9c3633e83 100644 (file)
--- a/include/configs/titanium.h
+++ b/include/configs/titanium.h
@@ -17,8 +17,6 @@
 #include <asm/arch/imx-regs.h>
 #include <asm/imx-common/gpio.h>
 
 #include <asm/arch/imx-regs.h>
 #include <asm/imx-common/gpio.h>
 

-#define CONFIG_MX6
-#define CONFIG_MX6Q

 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 

diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h
index a099687d4636ac4821da9213fe7c58eff8345827..a2422f3f071a5370e22a41bdb0dee5d779596234 100644 (file)
--- a/include/configs/tqma6.h
+++ b/include/configs/tqma6.h
@@ -9,7 +9,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
 

-#define CONFIG_MX6

 
 /* SPL */
 /* #if defined(CONFIG_SPL_BUILD) */
 
 /* SPL */
 /* #if defined(CONFIG_SPL_BUILD) */


@@ -29,17 +28,13 @@
 #include <asm/imx-common/gpio.h>
 #include <linux/sizes.h>
 
 #include <asm/imx-common/gpio.h>
 #include <linux/sizes.h>
 

-#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)

 #define PHYS_SDRAM_SIZE                        (512u * SZ_1M)
 #define PHYS_SDRAM_SIZE                        (512u * SZ_1M)

-#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)

 #define PHYS_SDRAM_SIZE                        (1024u * SZ_1M)
 #endif
 
 #if defined(CONFIG_MBA6)
 
 #define PHYS_SDRAM_SIZE                        (1024u * SZ_1M)
 #endif
 
 #if defined(CONFIG_MBA6)
 

-#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)

 #define CONFIG_DEFAULT_FDT_FILE                "imx6dl-mba6x.dtb"
 #define CONFIG_DEFAULT_FDT_FILE                "imx6dl-mba6x.dtb"

-#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6Q)

 #define CONFIG_DEFAULT_FDT_FILE                "imx6q-mba6x.dtb"
 #endif
 
 #define CONFIG_DEFAULT_FDT_FILE                "imx6q-mba6x.dtb"
 #endif
 


@@ -198,9 +193,7 @@
 #define CONFIG_LOADADDR                        0x12000000
 
 /* place code in last 4 MiB of RAM */
 #define CONFIG_LOADADDR                        0x12000000
 
 /* place code in last 4 MiB of RAM */

-#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)

 #define CONFIG_SYS_TEXT_BASE           0x2fc00000
 #define CONFIG_SYS_TEXT_BASE           0x2fc00000

-#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)

 #define CONFIG_SYS_TEXT_BASE           0x4fc00000
 #endif
 
 #define CONFIG_SYS_TEXT_BASE           0x4fc00000
 #endif
 

diff --git a/include/configs/tt01.h b/include/configs/tt01.h
index cf169a4c893ab77d2c1452d134862bab3511f65e..0f9d7e0da8001c68e55f10fb6246b7660bef4578 100644 (file)
--- a/include/configs/tt01.h
+++ b/include/configs/tt01.h
@@ -13,7 +13,6 @@
 #include <asm/arch/imx-regs.h>
 
 /* High Level Configuration Options */
 #include <asm/arch/imx-regs.h>
 
 /* High Level Configuration Options */

-#define CONFIG_MX31

 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO

diff --git a/include/configs/tx25.h b/include/configs/tx25.h
index 1d8b687905f20daf3890312908e85ee753a5dd1b..b43dafb43aff15e272f891ea542b245145a62551 100644 (file)
--- a/include/configs/tx25.h
+++ b/include/configs/tx25.h
@@ -13,7 +13,6 @@
 /*
  * KARO TX25 board - SoC Configuration
  */
 /*
  * KARO TX25 board - SoC Configuration
  */

-#define CONFIG_MX25

 #define CONFIG_MX25_CLK32              32000   /* OSC32K frequency */
 #define CONFIG_SYS_TIMER_RATE          CONFIG_MX25_CLK32
 #define CONFIG_SYS_TIMER_COUNTER       \
 #define CONFIG_MX25_CLK32              32000   /* OSC32K frequency */
 #define CONFIG_SYS_TIMER_RATE          CONFIG_MX25_CLK32
 #define CONFIG_SYS_TIMER_COUNTER       \

diff --git a/include/configs/tx28.h b/include/configs/tx28.h
index 14a178175c981912402ed866ecd7184e6051dfec..9927b171373c0e4cdd059994f368ec79f1f255ee 100644 (file)
--- a/include/configs/tx28.h
+++ b/include/configs/tx28.h
@@ -8,8 +8,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
 

-#define CONFIG_MX28                    /* must be defined before including regs-base.h */
-

 #include <linux/sizes.h>
 #include <asm/arch/regs-base.h>
 
 #include <linux/sizes.h>
 #include <asm/arch/regs-base.h>
 

diff --git a/include/configs/tx51.h b/include/configs/tx51.h
index 2ce5204ed976efb90374ea16f96fb9f567e32ed4..55ad3da20da0783f9295f09a2aeee9d99e5b8c76 100644 (file)
--- a/include/configs/tx51.h
+++ b/include/configs/tx51.h
@@ -8,7 +8,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
 

-#define CONFIG_MX51                    /* must be set before including imx-regs.h */

 
 #include <linux/sizes.h>
 #include <asm/arch/imx-regs.h>
 
 #include <linux/sizes.h>
 #include <asm/arch/imx-regs.h>

diff --git a/include/configs/tx53.h b/include/configs/tx53.h
index 2a1bf6f5e5cf9dcc35fe5fb52b17d7038669eba8..1e03ed719c7b391252221ff0850b1202e40260a3 100644 (file)
--- a/include/configs/tx53.h
+++ b/include/configs/tx53.h
@@ -8,8 +8,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
 #ifndef __CONFIG_H
 #define __CONFIG_H
 

-#define CONFIG_MX53                    /* must be defined before including imx-regs.h */
-

 #include <linux/sizes.h>
 #include <asm/arch/imx-regs.h>
 
 #include <linux/sizes.h>
 #include <asm/arch/imx-regs.h>
 

diff --git a/include/configs/tx6.h b/include/configs/tx6.h
index a89bce8a7970d7a8bf5ce0081756ff6d862f031e..0c3fc74a61d7be0598e39392de473d5903d170d3 100644 (file)
--- a/include/configs/tx6.h
+++ b/include/configs/tx6.h
@@ -54,7 +54,7 @@
 #define PHYS_SDRAM_1_WIDTH             64
 #endif
 #define PHYS_SDRAM_1_SIZE              (SZ_512M / 32 * PHYS_SDRAM_1_WIDTH)
 #define PHYS_SDRAM_1_WIDTH             64
 #endif
 #define PHYS_SDRAM_1_SIZE              (SZ_512M / 32 * PHYS_SDRAM_1_WIDTH)

-#ifdef CONFIG_MX6Q
+#ifdef CONFIG_SOC_MX6Q

 #define CONFIG_SYS_SDRAM_CLK           528
 #else
 #define CONFIG_SYS_SDRAM_CLK           400
 #define CONFIG_SYS_SDRAM_CLK           528
 #else
 #define CONFIG_SYS_SDRAM_CLK           400


@@ -68,11 +68,11 @@
  * U-Boot general configurations
  */
 #define CONFIG_SYS_LONGHELP
  * U-Boot general configurations
  */
 #define CONFIG_SYS_LONGHELP

-#if defined(CONFIG_MX6Q)
+#if defined(CONFIG_SOC_MX6Q)

 #define CONFIG_SYS_PROMPT              "TX6Q U-Boot > "
 #define CONFIG_SYS_PROMPT              "TX6Q U-Boot > "

-#elif defined(CONFIG_MX6DL)
+#elif defined(CONFIG_SOC_MX6DL)

 #define CONFIG_SYS_PROMPT              "TX6DL U-Boot > "
 #define CONFIG_SYS_PROMPT              "TX6DL U-Boot > "

-#elif defined(CONFIG_MX6S)
+#elif defined(CONFIG_SOC_MX6S)

 #define CONFIG_SYS_PROMPT              "TX6S U-Boot > "
 #else
 #error Unsupported i.MX6 processor variant
 #define CONFIG_SYS_PROMPT              "TX6S U-Boot > "
 #else
 #error Unsupported i.MX6 processor variant

diff --git a/include/configs/udoo.h b/include/configs/udoo.h
index b4a62453625bbffd1a5ebc50a681497e943d08ed..6e054c5ccbb7f4ecff2aa37a14118e7e182af903 100644 (file)
--- a/include/configs/udoo.h
+++ b/include/configs/udoo.h
@@ -14,7 +14,6 @@
 #include <asm/imx-common/gpio.h>
 #include <linux/sizes.h>
 
 #include <asm/imx-common/gpio.h>
 #include <linux/sizes.h>
 

-#define CONFIG_MX6

 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 

diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h
index 05bc7d0d9e5d0b1bc4b8253eba126ac91830119a..d5d296b9a39c2478936790a849e7edb021f4b5e0 100644 (file)
--- a/include/configs/vf610twr.h
+++ b/include/configs/vf610twr.h
@@ -12,7 +12,6 @@
 #include <asm/arch/imx-regs.h>
 #include <config_cmd_default.h>
 
 #include <asm/arch/imx-regs.h>
 #include <config_cmd_default.h>
 

-#define CONFIG_VF610

 
 #define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_CPUINFO
 
 #define CONFIG_SYS_GENERIC_BOARD
 #define CONFIG_DISPLAY_CPUINFO

diff --git a/include/configs/vision2.h b/include/configs/vision2.h
index 3f35076f9e6cfc677649b316a1314732492001a7..6beef8901a378e4d2d64ee6bf22375c4d10bf3df 100644 (file)
--- a/include/configs/vision2.h
+++ b/include/configs/vision2.h
@@ -12,7 +12,6 @@
 #define __CONFIG_H
 
 
 #define __CONFIG_H
 
 

-#define CONFIG_MX51    /* in a mx51 */

 #define CONFIG_SYS_TEXT_BASE   0x97800000
 
 #include <asm/arch/imx-regs.h>
 #define CONFIG_SYS_TEXT_BASE   0x97800000
 
 #include <asm/arch/imx-regs.h>

diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h
index 809017c5fe225278c87619e237fd0905b9c1dcf1..e513cc642fe5aaf58d3e1603d2be2a4c009f88fd 100644 (file)
--- a/include/configs/wandboard.h
+++ b/include/configs/wandboard.h
@@ -14,7 +14,6 @@
 #include <asm/imx-common/gpio.h>
 #include <linux/sizes.h>
 
 #include <asm/imx-common/gpio.h>
 #include <linux/sizes.h>
 

-#define CONFIG_MX6

 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 


@@ -124,9 +123,7 @@
 #define CONFIG_MXC_OCOTP
 #endif
 
 #define CONFIG_MXC_OCOTP
 #endif
 

-#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)

 #define CONFIG_DEFAULT_FDT_FILE                "imx6dl-wandboard.dtb"
 #define CONFIG_DEFAULT_FDT_FILE                "imx6dl-wandboard.dtb"

-#elif defined(CONFIG_MX6Q)

 #define CONFIG_DEFAULT_FDT_FILE                "imx6q-wandboard.dtb"
 #endif
 
 #define CONFIG_DEFAULT_FDT_FILE                "imx6q-wandboard.dtb"
 #endif
 

diff --git a/include/configs/woodburn_common.h b/include/configs/woodburn_common.h
index c7a17f7a49d3809693e047f4975125f34f1886fe..fb9929170dd5d542a87d085ee8a4d13177e97b22 100644 (file)
--- a/include/configs/woodburn_common.h
+++ b/include/configs/woodburn_common.h
@@ -14,7 +14,6 @@
 #include <asm/arch/imx-regs.h>
 
  /* High Level Configuration Options */
 #include <asm/arch/imx-regs.h>
 
  /* High Level Configuration Options */

-#define CONFIG_MX35

 #define CONFIG_MX35_HCLK_FREQ  24000000
 
 #define CONFIG_SYS_DCACHE_OFF
 #define CONFIG_MX35_HCLK_FREQ  24000000
 
 #define CONFIG_SYS_DCACHE_OFF

diff --git a/include/configs/xfi3.h b/include/configs/xfi3.h
index 8e6b3653644ca339872b5b2bbd304393f0c1b20b..006f5a4d1637d22e26b500a8aac77baeb1d41d22 100644 (file)
--- a/include/configs/xfi3.h
+++ b/include/configs/xfi3.h
@@ -7,7 +7,6 @@
 #define __CONFIGS_XFI3_H__
 
 /* System configurations */
 #define __CONFIGS_XFI3_H__
 
 /* System configurations */

-#define CONFIG_MX23                            /* i.MX23 SoC */

 
 /* U-Boot Commands */
 #define CONFIG_SYS_NO_FLASH
 
 /* U-Boot Commands */
 #define CONFIG_SYS_NO_FLASH

diff --git a/include/configs/zmx25.h b/include/configs/zmx25.h
index 356ac886f26051d4be4f59ed43b9d9ff045769a3..2ad0b90871a69de048eb80dd134230f9b07e8542 100644 (file)
--- a/include/configs/zmx25.h
+++ b/include/configs/zmx25.h
@@ -12,7 +12,6 @@
 
 #include <asm/arch/imx-regs.h>
 
 
 #include <asm/arch/imx-regs.h>
 

-#define CONFIG_MX25

 #define CONFIG_SYS_TEXT_BASE           0xA0000000
 
 #define CONFIG_SYS_TIMER_RATE          32768
 #define CONFIG_SYS_TEXT_BASE           0xA0000000
 
 #define CONFIG_SYS_TIMER_RATE          32768

diff --git a/include/tsec.h b/include/tsec.h
index 58cdc19df3af3bc0558a5fc4687972de553b6788..89c9091cffa1693881f819d098acfffec278d962 100644 (file)
--- a/include/tsec.h
+++ b/include/tsec.h
@@ -21,7 +21,7 @@
 #include <config.h>
 #include <phy.h>
 
 #include <config.h>
 #include <phy.h>
 

-#ifdef CONFIG_LS102XA
+#ifdef CONFIG_SOC_LS102XA

 #define TSEC_SIZE              0x40000
 #define TSEC_MDIO_OFFSET       0x40000
 #else
 #define TSEC_SIZE              0x40000
 #define TSEC_MDIO_OFFSET       0x40000
 #else


@@ -129,7 +129,7 @@
 
 #define MINFLR_INIT_SETTINGS   0x00000040
 
 
 #define MINFLR_INIT_SETTINGS   0x00000040
 

-#ifdef CONFIG_LS102XA
+#ifdef CONFIG_SOC_LS102XA

 #define DMACTRL_INIT_SETTINGS  0x00000003
 #else
 #define DMACTRL_INIT_SETTINGS  0x000000c3
 #define DMACTRL_INIT_SETTINGS  0x00000003
 #else
 #define DMACTRL_INIT_SETTINGS  0x000000c3

diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h
index e9349b5c1666db1838ef8da34d194ee5c83bbb16..ecb8b79d8605462fe167804aa772178f5015a6ce 100644 (file)
--- a/include/usb/ehci-fsl.h
+++ b/include/usb/ehci-fsl.h
@@ -163,7 +163,7 @@
 #elif defined(CONFIG_MPC512X)
 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
 #define CONFIG_SYS_FSL_USB2_ADDR       0
 #elif defined(CONFIG_MPC512X)
 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_MPC512x_USB1_ADDR
 #define CONFIG_SYS_FSL_USB2_ADDR       0

-#elif defined(CONFIG_LS102XA)
+#elif defined(CONFIG_SOC_LS102XA)

 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR
 #define CONFIG_SYS_FSL_USB2_ADDR        0
 #endif
 #define CONFIG_SYS_FSL_USB1_ADDR CONFIG_SYS_LS102XA_USB1_ADDR
 #define CONFIG_SYS_FSL_USB2_ADDR        0
 #endif

diff --git a/tools/Makefile b/tools/Makefile
index 75ab70563a59fd1c4f1bfac240626afa932d5593..578f8505d33ca9a9ea61466ff7542b6ce6f6a05c 100644 (file)
--- a/tools/Makefile
+++ b/tools/Makefile
@@ -52,7 +52,7 @@ HOSTCFLAGS_xway-swap-bytes.o := -pedantic
 hostprogs-y += mkenvimage
 mkenvimage-objs := mkenvimage.o os_support.o lib/crc32.o
 
 hostprogs-y += mkenvimage
 mkenvimage-objs := mkenvimage.o os_support.o lib/crc32.o
 

-#hostprogs-y += dumpimage mkimage
+hostprogs-y += dumpimage mkimage

 hostprogs-$(CONFIG_FIT_SIGNATURE) += fit_info fit_check_sign
 
 FIT_SIG_OBJS-$(CONFIG_FIT_SIGNATURE) := common/image-sig.o
 hostprogs-$(CONFIG_FIT_SIGNATURE) += fit_info fit_check_sign
 
 FIT_SIG_OBJS-$(CONFIG_FIT_SIGNATURE) := common/image-sig.o


@@ -103,7 +103,7 @@ fit_check_sign-objs   := $(dumpimage-mkimage-objs) fit_check_sign.o
 
 # TODO(sjg@chromium.org): Is this correct on Mac OS?
 
 
 # TODO(sjg@chromium.org): Is this correct on Mac OS?
 

-ifneq ($(CONFIG_MX23)$(CONFIG_MX28),)
+ifneq ($(CONFIG_SOC_MX23)$(CONFIG_SOC_MX28),)

 # Add CONFIG_MXS into host CFLAGS, so we can check whether or not register
 # the mxsimage support within tools/mxsimage.c .
 HOSTCFLAGS_mxsimage.o += -DCONFIG_MXS
 # Add CONFIG_MXS into host CFLAGS, so we can check whether or not register
 # the mxsimage support within tools/mxsimage.c .
 HOSTCFLAGS_mxsimage.o += -DCONFIG_MXS


@@ -116,7 +116,7 @@ HOST_EXTRACFLAGS    += -DCONFIG_FIT_SIGNATURE
 endif
 
 # MXSImage needs LibSSL
 endif
 
 # MXSImage needs LibSSL

-ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_FIT_SIGNATURE),)
+ifneq ($(CONFIG_SOC_MX23)$(CONFIG_SOC_MX28)$(CONFIG_FIT_SIGNATURE),)

 HOSTLOADLIBES_mkimage += -lssl -lcrypto
 endif
 
 HOSTLOADLIBES_mkimage += -lssl -lcrypto
 endif
 


@@ -133,8 +133,8 @@ HOSTCFLAGS_mkexynosspl.o := -pedantic
 ifdtool-objs := $(LIBFDT_OBJS) ifdtool.o
 hostprogs-$(CONFIG_X86) += ifdtool
 
 ifdtool-objs := $(LIBFDT_OBJS) ifdtool.o
 hostprogs-$(CONFIG_X86) += ifdtool
 

-hostprogs-$(CONFIG_MX23) += mxsboot
-hostprogs-$(CONFIG_MX28) += mxsboot
+hostprogs-$(CONFIG_SOC_MX23) += mxsboot
+hostprogs-$(CONFIG_SOC_MX28) += mxsboot

 HOSTCFLAGS_mxsboot.o := -pedantic
 
 hostprogs-$(CONFIG_SUNXI) += mksunxiboot
 HOSTCFLAGS_mxsboot.o := -pedantic
 
 hostprogs-$(CONFIG_SUNXI) += mksunxiboot