*.bin
*.patch
*.cfgtmp
-*.dts.tmp
+
+# host programs on Cygwin
+*.exe
# Build tree
/build-*
/errlog
/reloc_off
-/spl/*
-!/spl/Makefile
+/spl/
/tpl/
#
VERSION = 2014
PATCHLEVEL = 07
SUBLEVEL =
-EXTRAVERSION = -rc1
+EXTRAVERSION = -rc3
NAME =
# *DOCUMENTATION*
HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer
HOSTCXXFLAGS = -O2
-ifeq ($(shell $(HOSTCC) -v 2>&1 | grep -c "clang version"), 1)
-HOSTCFLAGS += -Wno-unused-value -Wno-unused-parameter \
- -Wno-missing-field-initializers -fno-delete-null-pointer-checks
-endif
-
ifeq ($(HOSTOS),cygwin)
HOSTCFLAGS += -ansi
endif
KBUILD_MODULES :=
KBUILD_BUILTIN := 1
-# If we have only "make modules", don't compile built-in objects.
-# When we're building modules with modversions, we need to consider
-# the built-in objects during the descend as well, in order to
-# make sure the checksums are up to date before we record them.
+# If we have only "make modules", don't compile built-in objects.
+# When we're building modules with modversions, we need to consider
+# the built-in objects during the descend as well, in order to
+# make sure the checksums are up to date before we record them.
ifeq ($(MAKECMDGOALS),modules)
KBUILD_BUILTIN := $(if $(CONFIG_MODVERSIONS),1)
endif
-# If we have "make <whatever> modules", compile modules
-# in addition to whatever we do anyway.
-# Just "make" or "make all" shall build modules as well
+# If we have "make <whatever> modules", compile modules
+# in addition to whatever we do anyway.
+# Just "make" or "make all" shall build modules as well
# U-Boot does not need modules
#ifneq ($(filter all _all modules,$(MAKECMDGOALS)),)
export quiet Q KBUILD_VERBOSE
-ifneq ($(CC),)
-ifeq ($(shell $(CC) -v 2>&1 | grep -c "clang version"), 1)
-COMPILER := clang
-else
-COMPILER := gcc
-endif
-export COMPILER
-endif
-
# Look for make include files relative to root of kernel src
MAKEFLAGS += --include-dir=$(srctree)
OBJCOPY = $(CROSS_COMPILE)objcopy
OBJDUMP = $(CROSS_COMPILE)objdump
AWK = awk
-RANLIB = $(CROSS_COMPILE)RANLIB
+PERL = perl
DTC = dtc
CHECK = sparse
export ARCH CPU BOARD VENDOR SOC CPUDIR BOARDDIR
export CONFIG_SHELL HOSTCC HOSTCFLAGS HOSTLDFLAGS CROSS_COMPILE AS LD CC
export CPP AR NM LDR STRIP OBJCOPY OBJDUMP
-export MAKE AWK
-export DTC CHECK CHECKFLAGS
+export MAKE AWK PERL
+export HOSTCXX HOSTCXXFLAGS DTC CHECK CHECKFLAGS
export KBUILD_CPPFLAGS NOSTDINC_FLAGS UBOOTINCLUDE OBJCOPYFLAGS LDFLAGS
export KBUILD_CFLAGS KBUILD_AFLAGS
# If there is no specified link script, we look in a number of places for it
ifndef LDSCRIPT
- ifeq ($(CONFIG_NAND_U_BOOT),y)
- LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot-nand.lds
- ifeq ($(wildcard $(LDSCRIPT)),)
- LDSCRIPT := $(srctree)/$(CPUDIR)/u-boot-nand.lds
- endif
- endif
ifeq ($(wildcard $(LDSCRIPT)),)
LDSCRIPT := $(srctree)/board/$(BOARDDIR)/u-boot.lds
endif
KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector)
-ifeq ($(COMPILER),clang)
-KBUILD_CPPFLAGS += $(call cc-option,-Qunused-arguments,)
-KBUILD_CPPFLAGS += $(call cc-option,-Wno-unknown-warning-option,)
-KBUILD_CFLAGS += $(call cc-disable-warning, unused-variable)
-KBUILD_CFLAGS += $(call cc-disable-warning, format-invalid-specifier)
-KBUILD_CFLAGS += $(call cc-disable-warning, gnu)
-# Quiet clang warning: comparison of unsigned expression < 0 is always false
-KBUILD_CFLAGS += $(call cc-disable-warning, tautological-compare)
-# CLANG uses a _MergedGlobals as optimization, but this breaks modpost, as the
-# source of a reference will be _MergedGlobals and not on of the whitelisted names.
-# See modpost pattern 2
-KBUILD_CFLAGS += $(call cc-option, -mno-global-merge,)
-endif
-
KBUILD_CFLAGS += -g
# $(KBUILD_AFLAGS) sets -g, which causes gcc to pass a suitable -g<format>
# option to the assembler.
endif
# Always append ALL so that arch config.mk's can add custom ones
-ALL-y += u-boot.srec u-boot.bin System.map
+ALL-y += u-boot.srec u-boot.bin System.map binary_size_check
-ALL-$(CONFIG_NAND_U_BOOT) += u-boot-nand.bin
ALL-$(CONFIG_ONENAND_U_BOOT) += u-boot-onenand.bin
ifeq ($(CONFIG_SPL_FSL_PBL),y)
ALL-$(CONFIG_RAMBOOT_PBL) += u-boot-with-spl-pbl.bin
OBJCOPYFLAGS_u-boot.bin := -O binary
+binary_size_check: u-boot.bin System.map FORCE
+ @file_size=`stat -c %s u-boot.bin` ; \
+ map_size=$(shell cat System.map | \
+ awk '/_image_copy_start/ {start = $$1} /_image_binary_end/ {end = $$1} END {if (start != "" && end != "") print strtonum("0x" end) - strtonum("0x" start)}'); \
+ if [ "" != "$$map_size" ]; then \
+ if test $$map_size -ne $$file_size; then \
+ echo "System.map shows a binary size of $$map_size" >&2 ; \
+ echo " but u-boot.bin shows $$file_size" >&2 ; \
+ exit 1; \
+ fi \
+ fi
+
u-boot.bin: u-boot FORCE
$(call if_changed,objcopy)
$(call DO_STATIC_RELA,$<,$@,$(CONFIG_SYS_TEXT_BASE))
u-boot.lds: $(LDSCRIPT) prepare FORCE
$(call if_changed_dep,cpp_lds)
-PHONY += nand_spl
-nand_spl: prepare
- $(Q)$(MAKE) $(build)=nand_spl/board/$(BOARDDIR) all
- @echo >&2
- @echo >&2 "==================== WARNING ====================="
- @echo >&2 "nand_spl will not be included in v2014.07 release."
- @echo >&2 "Please switch over to SPL."
- @echo >&2 "Otherwise, this board will be removed."
- @echo >&2 "=================================================="
- @echo >&2
-
-nand_spl/u-boot-spl-16k.bin: nand_spl
- @:
-
-u-boot-nand.bin: nand_spl/u-boot-spl-16k.bin u-boot.bin FORCE
- $(call if_changed,cat)
-
spl/u-boot-spl.bin: spl/u-boot-spl
@:
spl/u-boot-spl: tools prepare
- $(Q)$(MAKE) obj=spl -f $(srctree)/spl/Makefile all
+ $(Q)$(MAKE) obj=spl -f $(srctree)/scripts/Makefile.spl all
spl/sunxi-spl.bin: spl/u-boot-spl
@:
tpl/u-boot-tpl.bin: tools prepare
- $(Q)$(MAKE) obj=tpl -f $(srctree)/spl/Makefile all CONFIG_TPL_BUILD=y
+ $(Q)$(MAKE) obj=tpl -f $(srctree)/scripts/Makefile.spl all CONFIG_TPL_BUILD=y
TAG_SUBDIRS := $(u-boot-dirs) include
include/tpl-autoconf.mk
# Directories & files removed with 'make clobber'
-CLOBBER_DIRS += $(patsubst %,spl/%, $(filter-out Makefile, \
- $(shell ls -1 spl 2>/dev/null))) \
- tpl
-CLOBBER_FILES += u-boot* MLO* SPL System.map nand_spl/u-boot*
+CLOBBER_DIRS += spl tpl
+CLOBBER_FILES += u-boot* MLO* SPL System.map
# Directories & files removed with 'make mrproper'
MRPROPER_DIRS += include/config include/generated \
- .tmp_objdiff
+ .tmp_objdiff
MRPROPER_FILES += .config .config.old \
tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS \
include/config.h include/config.mk
-o -name '*.symtypes' -o -name 'modules.order' \
-o -name modules.builtin -o -name '.tmp_*.o.*' \
-o -name '*.gcno' \) -type f -print | xargs rm -f
- @find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \
- -path './nand_spl/*' -type l -print | xargs rm -f
# clobber
#
the LCD display every second with
a "rotator" |\-/|\-/
-- Board flavour: (if CONFIG_MPC8260ADS is defined)
- CONFIG_ADSTYPE
- Possible values are:
- CONFIG_SYS_8260ADS - original MPC8260ADS
- CONFIG_SYS_8266ADS - MPC8266ADS
- CONFIG_SYS_PQ2FADS - PQ2FADS-ZU or PQ2FADS-VR
- CONFIG_SYS_8272ADS - MPC8272ADS
-
- Marvell Family Member
CONFIG_SYS_MVFS - define it if you want to enable
multiple fs option at one time
CONFIG_CMD_IMLS List all images found in NOR flash
CONFIG_CMD_IMLS_NAND * List all images found in NAND flash
CONFIG_CMD_IMMAP * IMMR dump support
+ CONFIG_CMD_IOTRACE * I/O tracing for debugging
CONFIG_CMD_IMPORTENV * import an environment
CONFIG_CMD_INI * import data from an ini file into the env
CONFIG_CMD_IRQ * irqinfo
Note that if the GPIO device uses I2C, then the I2C interface
must also be configured. See I2C Support, below.
+- I/O tracing:
+ When CONFIG_IO_TRACE is selected, U-Boot intercepts all I/O
+ accesses and can checksum them or write a list of them out
+ to memory. See the 'iotrace' command for details. This is
+ useful for testing device drivers since it can confirm that
+ the driver behaves the same way before and after a code
+ change. Currently this is supported on sandbox and arm. To
+ add support for your architecture, add '#include <iotrace.h>'
+ to the bottom of arch/<arch>/include/asm/io.h and test.
+
+ Example output from the 'iotrace stats' command is below.
+ Note that if the trace buffer is exhausted, the checksum will
+ still continue to operate.
+
+ iotrace is enabled
+ Start: 10000000 (buffer start address)
+ Size: 00010000 (buffer size)
+ Offset: 00000120 (current buffer offset)
+ Output: 10000120 (start + offset)
+ Count: 00000018 (number of trace records)
+ CRC32: 9526fb66 (CRC32 of all trace records)
+
- Timestamp Support:
When CONFIG_TIMESTAMP is selected, the timestamp
CONFIG_USB_EHCI_TXFIFO_THRESH enables setting of the
txfilltuning field in the EHCI controller on reset.
- CONFIG_USB_HUB_MIN_POWER_ON_DELAY defines the minimum
- interval for usb hub power-on delay.(minimum 100msec)
-
- USB Device:
Define the below if you wish to use the USB console.
Once firmware is rebuilt from a serial console issue the
filesystem. Available commands are cbfsinit, cbfsinfo, cbfsls
and cbfsload.
+- FAT(File Allocation Table) filesystem cluster size:
+ CONFIG_FS_FAT_MAX_CLUSTSIZE
+
+ Define the max cluster size for fat operations else
+ a default value of 65536 will be defined.
+
- Keyboard Support:
CONFIG_ISA_KEYBOARD
-150 common/cmd_nand.c Incorrect FIT image format
151 common/cmd_nand.c FIT image format OK
+- legacy image format:
+ CONFIG_IMAGE_FORMAT_LEGACY
+ enables the legacy image format support in U-Boot.
+
+ Default:
+ enabled if CONFIG_FIT_SIGNATURE is not defined.
+
+ CONFIG_DISABLE_IMAGE_LEGACY
+ disable the legacy image format
+
+ This define is introduced, as the legacy image format is
+ enabled per default for backward compatibility.
+
- FIT image support:
CONFIG_FIT
Enable support for the FIT uImage format.
using a hash signed and verified using RSA. See
doc/uImage.FIT/signature.txt for more details.
+ WARNING: When relying on signed FIT images with required
+ signature check the legacy image format is default
+ disabled. If a board need legacy image format support
+ enable this through CONFIG_IMAGE_FORMAT_LEGACY
+
- Standalone program support:
CONFIG_STANDALONE_LOAD_ADDR
and make sure that your definition of IMAP_ADDR uses the same value
as your U-Boot configuration in CONFIG_SYS_IMMR.
+Note that U-Boot now has a driver model, a unified model for drivers.
+If you are adding a new driver, plumb it into driver model. If there
+is no uclass available, you are encouraged to create one. See
+doc/driver-model.
+
Configuring the Linux kernel:
-----------------------------
/*/include/asm/arch
-/*/include/asm/proc
#define __ASM_ARC_CONFIG_H_
#define CONFIG_SYS_GENERIC_GLOBAL_DATA
+#define CONFIG_SYS_BOOT_RAMDISK_HIGH
#define CONFIG_LMB
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/apb_misc.h>
#include <asm/arch-tegra/board.h>
-#include <asm/arch/spl.h>
+#include <asm/spl.h>
#include "cpu.h"
void spl_board_init(void)
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/kirkwood.h>
-#include <hush.h>
#define BUFLEN 16
debug("Starting %s process...\n", __FUNCTION__);
ret = run_command(s, 0);
- if (ret < 0)
+ if (ret != 0)
debug("Error.. %s failed\n", __FUNCTION__);
else
debug("%s process finished\n", __FUNCTION__);
#include <asm/io.h>
#include <u-boot/md5.h>
#include <asm/arch/cpu.h>
-#include <hush.h>
#define BUFLEN 16
#endif
}
#endif
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-#endif /* !CONFIG_SYS_DCACHE_OFF */
void enable_caches(void)
{
+ icache_enable();
+ dcache_enable();
}
unsigned int get_chip_id(void)
* SPDX-License-Identifier: GPL-2.0+
*/
-#include<common.h>
-#include<config.h>
+#include <common.h>
+#include <config.h>
#include <asm/arch/clock.h>
#include <asm/arch/clk.h>
#
obj-y := soc.o clock.o
+obj-$(CONFIG_SPL_BUILD) += ddr.o
obj-$(CONFIG_SECURE_BOOT) += hab.o
--- /dev/null
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/io.h>
+#include <asm/types.h>
+
+#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+/* Configure MX6DQ mmdc iomux */
+void mx6dq_dram_iocfg(unsigned width,
+ const struct mx6dq_iomux_ddr_regs *ddr,
+ const struct mx6dq_iomux_grp_regs *grp)
+{
+ volatile struct mx6dq_iomux_ddr_regs *mx6_ddr_iomux;
+ volatile struct mx6dq_iomux_grp_regs *mx6_grp_iomux;
+
+ mx6_ddr_iomux = (struct mx6dq_iomux_ddr_regs *)MX6DQ_IOM_DDR_BASE;
+ mx6_grp_iomux = (struct mx6dq_iomux_grp_regs *)MX6DQ_IOM_GRP_BASE;
+
+ /* DDR IO Type */
+ mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
+ mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
+
+ /* Clock */
+ mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
+ mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
+
+ /* Address */
+ mx6_ddr_iomux->dram_cas = ddr->dram_cas;
+ mx6_ddr_iomux->dram_ras = ddr->dram_ras;
+ mx6_grp_iomux->grp_addds = grp->grp_addds;
+
+ /* Control */
+ mx6_ddr_iomux->dram_reset = ddr->dram_reset;
+ mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
+ mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
+ mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
+ mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
+ mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
+ mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
+
+ /* Data Strobes */
+ mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
+ mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
+ mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
+ if (width >= 32) {
+ mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
+ mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
+ }
+ if (width >= 64) {
+ mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
+ mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
+ mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
+ mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
+ }
+
+ /* Data */
+ mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
+ mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
+ mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
+ if (width >= 32) {
+ mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
+ mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
+ }
+ if (width >= 64) {
+ mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
+ mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
+ mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
+ mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
+ }
+ mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
+ mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
+ if (width >= 32) {
+ mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
+ mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
+ }
+ if (width >= 64) {
+ mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
+ mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
+ mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
+ mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
+ }
+}
+#endif
+
+#if defined(CONFIG_MX6QDL) || defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+/* Configure MX6SDL mmdc iomux */
+void mx6sdl_dram_iocfg(unsigned width,
+ const struct mx6sdl_iomux_ddr_regs *ddr,
+ const struct mx6sdl_iomux_grp_regs *grp)
+{
+ volatile struct mx6sdl_iomux_ddr_regs *mx6_ddr_iomux;
+ volatile struct mx6sdl_iomux_grp_regs *mx6_grp_iomux;
+
+ mx6_ddr_iomux = (struct mx6sdl_iomux_ddr_regs *)MX6SDL_IOM_DDR_BASE;
+ mx6_grp_iomux = (struct mx6sdl_iomux_grp_regs *)MX6SDL_IOM_GRP_BASE;
+
+ /* DDR IO Type */
+ mx6_grp_iomux->grp_ddr_type = grp->grp_ddr_type;
+ mx6_grp_iomux->grp_ddrpke = grp->grp_ddrpke;
+
+ /* Clock */
+ mx6_ddr_iomux->dram_sdclk_0 = ddr->dram_sdclk_0;
+ mx6_ddr_iomux->dram_sdclk_1 = ddr->dram_sdclk_1;
+
+ /* Address */
+ mx6_ddr_iomux->dram_cas = ddr->dram_cas;
+ mx6_ddr_iomux->dram_ras = ddr->dram_ras;
+ mx6_grp_iomux->grp_addds = grp->grp_addds;
+
+ /* Control */
+ mx6_ddr_iomux->dram_reset = ddr->dram_reset;
+ mx6_ddr_iomux->dram_sdcke0 = ddr->dram_sdcke0;
+ mx6_ddr_iomux->dram_sdcke1 = ddr->dram_sdcke1;
+ mx6_ddr_iomux->dram_sdba2 = ddr->dram_sdba2;
+ mx6_ddr_iomux->dram_sdodt0 = ddr->dram_sdodt0;
+ mx6_ddr_iomux->dram_sdodt1 = ddr->dram_sdodt1;
+ mx6_grp_iomux->grp_ctlds = grp->grp_ctlds;
+
+ /* Data Strobes */
+ mx6_grp_iomux->grp_ddrmode_ctl = grp->grp_ddrmode_ctl;
+ mx6_ddr_iomux->dram_sdqs0 = ddr->dram_sdqs0;
+ mx6_ddr_iomux->dram_sdqs1 = ddr->dram_sdqs1;
+ if (width >= 32) {
+ mx6_ddr_iomux->dram_sdqs2 = ddr->dram_sdqs2;
+ mx6_ddr_iomux->dram_sdqs3 = ddr->dram_sdqs3;
+ }
+ if (width >= 64) {
+ mx6_ddr_iomux->dram_sdqs4 = ddr->dram_sdqs4;
+ mx6_ddr_iomux->dram_sdqs5 = ddr->dram_sdqs5;
+ mx6_ddr_iomux->dram_sdqs6 = ddr->dram_sdqs6;
+ mx6_ddr_iomux->dram_sdqs7 = ddr->dram_sdqs7;
+ }
+
+ /* Data */
+ mx6_grp_iomux->grp_ddrmode = grp->grp_ddrmode;
+ mx6_grp_iomux->grp_b0ds = grp->grp_b0ds;
+ mx6_grp_iomux->grp_b1ds = grp->grp_b1ds;
+ if (width >= 32) {
+ mx6_grp_iomux->grp_b2ds = grp->grp_b2ds;
+ mx6_grp_iomux->grp_b3ds = grp->grp_b3ds;
+ }
+ if (width >= 64) {
+ mx6_grp_iomux->grp_b4ds = grp->grp_b4ds;
+ mx6_grp_iomux->grp_b5ds = grp->grp_b5ds;
+ mx6_grp_iomux->grp_b6ds = grp->grp_b6ds;
+ mx6_grp_iomux->grp_b7ds = grp->grp_b7ds;
+ }
+ mx6_ddr_iomux->dram_dqm0 = ddr->dram_dqm0;
+ mx6_ddr_iomux->dram_dqm1 = ddr->dram_dqm1;
+ if (width >= 32) {
+ mx6_ddr_iomux->dram_dqm2 = ddr->dram_dqm2;
+ mx6_ddr_iomux->dram_dqm3 = ddr->dram_dqm3;
+ }
+ if (width >= 64) {
+ mx6_ddr_iomux->dram_dqm4 = ddr->dram_dqm4;
+ mx6_ddr_iomux->dram_dqm5 = ddr->dram_dqm5;
+ mx6_ddr_iomux->dram_dqm6 = ddr->dram_dqm6;
+ mx6_ddr_iomux->dram_dqm7 = ddr->dram_dqm7;
+ }
+}
+#endif
+
+/*
+ * Configure mx6 mmdc registers based on:
+ * - board-specific memory configuration
+ * - board-specific calibration data
+ * - ddr3 chip details
+ *
+ * The various calculations here are derived from the Freescale
+ * i.Mx6DQSDL DDR3 Script Aid spreadsheet (DOC-94917) designed to generate MMDC
+ * configuration registers based on memory system and memory chip parameters.
+ *
+ * The defaults here are those which were specified in the spreadsheet.
+ * For details on each register, refer to the IMX6DQRM and/or IMX6SDLRM
+ * section titled MMDC initialization
+ */
+#define MR(val, ba, cmd, cs1) \
+ ((val << 16) | (1 << 15) | (cmd << 4) | (cs1 << 3) | ba)
+void mx6_dram_cfg(const struct mx6_ddr_sysinfo *i,
+ const struct mx6_mmdc_calibration *c,
+ const struct mx6_ddr3_cfg *m)
+{
+ volatile struct mmdc_p_regs *mmdc0;
+ volatile struct mmdc_p_regs *mmdc1;
+ u32 reg;
+ u8 tcke, tcksrx, tcksre, txpdll, taofpd, taonpd, trrd;
+ u8 todtlon, taxpd, tanpd, tcwl, txp, tfaw, tcl;
+ u8 todt_idle_off = 0x4; /* from DDR3 Script Aid spreadsheet */
+ u16 trcd, trc, tras, twr, tmrd, trtp, trp, twtr, trfc, txs, txpr;
+ u16 CS0_END;
+ u16 tdllk = 0x1ff; /* DLL locking time: 512 cycles (JEDEC DDR3) */
+ int clkper; /* clock period in picoseconds */
+ int clock; /* clock freq in mHz */
+ int cs;
+
+ mmdc0 = (struct mmdc_p_regs *)MMDC_P0_BASE_ADDR;
+ mmdc1 = (struct mmdc_p_regs *)MMDC_P1_BASE_ADDR;
+
+ /* MX6D/MX6Q: 1066 MHz memory clock, clkper = 1.894ns = 1894ps */
+ if (is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) {
+ clock = 528;
+ tcwl = 4;
+ }
+ /* MX6S/MX6DL: 800 MHz memory clock, clkper = 2.5ns = 2500ps */
+ else {
+ clock = 400;
+ tcwl = 3;
+ }
+ clkper = (1000*1000)/clock; /* ps */
+ todtlon = tcwl;
+ taxpd = tcwl;
+ tanpd = tcwl;
+ tcwl = tcwl;
+
+ switch (m->density) {
+ case 1: /* 1Gb per chip */
+ trfc = DIV_ROUND_UP(110000, clkper) - 1;
+ txs = DIV_ROUND_UP(120000, clkper) - 1;
+ break;
+ case 2: /* 2Gb per chip */
+ trfc = DIV_ROUND_UP(160000, clkper) - 1;
+ txs = DIV_ROUND_UP(170000, clkper) - 1;
+ break;
+ case 4: /* 4Gb per chip */
+ trfc = DIV_ROUND_UP(260000, clkper) - 1;
+ txs = DIV_ROUND_UP(270000, clkper) - 1;
+ break;
+ case 8: /* 8Gb per chip */
+ trfc = DIV_ROUND_UP(350000, clkper) - 1;
+ txs = DIV_ROUND_UP(360000, clkper) - 1;
+ break;
+ default:
+ /* invalid density */
+ printf("invalid chip density\n");
+ hang();
+ break;
+ }
+ txpr = txs;
+
+ switch (m->mem_speed) {
+ case 800:
+ txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
+ tcke = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
+ if (m->pagesz == 1) {
+ tfaw = DIV_ROUND_UP(40000, clkper) - 1;
+ trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
+ } else {
+ tfaw = DIV_ROUND_UP(50000, clkper) - 1;
+ trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
+ }
+ break;
+ case 1066:
+ txp = DIV_ROUND_UP(MAX(3*clkper, 7500), clkper) - 1;
+ tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
+ if (m->pagesz == 1) {
+ tfaw = DIV_ROUND_UP(37500, clkper) - 1;
+ trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
+ } else {
+ tfaw = DIV_ROUND_UP(50000, clkper) - 1;
+ trrd = DIV_ROUND_UP(MAX(4*clkper, 10000), clkper) - 1;
+ }
+ break;
+ case 1333:
+ txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;
+ tcke = DIV_ROUND_UP(MAX(3*clkper, 5625), clkper) - 1;
+ if (m->pagesz == 1) {
+ tfaw = DIV_ROUND_UP(30000, clkper) - 1;
+ trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
+ } else {
+ tfaw = DIV_ROUND_UP(45000, clkper) - 1;
+ trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
+ }
+ break;
+ case 1600:
+ txp = DIV_ROUND_UP(MAX(3*clkper, 6000), clkper) - 1;
+ tcke = DIV_ROUND_UP(MAX(3*clkper, 5000), clkper) - 1;
+ if (m->pagesz == 1) {
+ tfaw = DIV_ROUND_UP(30000, clkper) - 1;
+ trrd = DIV_ROUND_UP(MAX(4*clkper, 6000), clkper) - 1;
+ } else {
+ tfaw = DIV_ROUND_UP(40000, clkper) - 1;
+ trrd = DIV_ROUND_UP(MAX(4*clkper, 7500), clkper) - 1;
+ }
+ break;
+ default:
+ printf("invalid memory speed\n");
+ hang();
+ break;
+ }
+ txpdll = DIV_ROUND_UP(MAX(10*clkper, 24000), clkper) - 1;
+ tcl = DIV_ROUND_UP(m->trcd, clkper/10) - 3;
+ tcksre = DIV_ROUND_UP(MAX(5*clkper, 10000), clkper);
+ tcksrx = tcksre;
+ taonpd = DIV_ROUND_UP(2000, clkper) - 1;
+ taofpd = taonpd;
+ trp = DIV_ROUND_UP(m->trcd, clkper/10) - 1;
+ trcd = trp;
+ trc = DIV_ROUND_UP(m->trcmin, clkper/10) - 1;
+ tras = DIV_ROUND_UP(m->trasmin, clkper/10) - 1;
+ twr = DIV_ROUND_UP(15000, clkper) - 1;
+ tmrd = DIV_ROUND_UP(MAX(12*clkper, 15000), clkper) - 1;
+ twtr = ROUND(MAX(4*clkper, 7500)/clkper, 1) - 1;
+ trtp = twtr;
+ CS0_END = ((4*i->cs_density) <= 120) ? (4*i->cs_density)+7 : 127;
+ debug("density:%d Gb (%d Gb per chip)\n", i->cs_density, m->density);
+ debug("clock: %dMHz (%d ps)\n", clock, clkper);
+ debug("memspd:%d\n", m->mem_speed);
+ debug("tcke=%d\n", tcke);
+ debug("tcksrx=%d\n", tcksrx);
+ debug("tcksre=%d\n", tcksre);
+ debug("taofpd=%d\n", taofpd);
+ debug("taonpd=%d\n", taonpd);
+ debug("todtlon=%d\n", todtlon);
+ debug("tanpd=%d\n", tanpd);
+ debug("taxpd=%d\n", taxpd);
+ debug("trfc=%d\n", trfc);
+ debug("txs=%d\n", txs);
+ debug("txp=%d\n", txp);
+ debug("txpdll=%d\n", txpdll);
+ debug("tfaw=%d\n", tfaw);
+ debug("tcl=%d\n", tcl);
+ debug("trcd=%d\n", trcd);
+ debug("trp=%d\n", trp);
+ debug("trc=%d\n", trc);
+ debug("tras=%d\n", tras);
+ debug("twr=%d\n", twr);
+ debug("tmrd=%d\n", tmrd);
+ debug("tcwl=%d\n", tcwl);
+ debug("tdllk=%d\n", tdllk);
+ debug("trtp=%d\n", trtp);
+ debug("twtr=%d\n", twtr);
+ debug("trrd=%d\n", trrd);
+ debug("txpr=%d\n", txpr);
+ debug("CS0_END=%d\n", CS0_END);
+ debug("ncs=%d\n", i->ncs);
+ debug("Rtt_wr=%d\n", i->rtt_wr);
+ debug("Rtt_nom=%d\n", i->rtt_nom);
+ debug("SRT=%d\n", m->SRT);
+ debug("tcl=%d\n", tcl);
+ debug("twr=%d\n", twr);
+
+ /*
+ * board-specific configuration:
+ * These values are determined empirically and vary per board layout
+ * see:
+ * appnote, ddr3 spreadsheet
+ */
+ mmdc0->mpwldectrl0 = c->p0_mpwldectrl0;
+ mmdc0->mpwldectrl1 = c->p0_mpwldectrl1;
+ mmdc0->mpdgctrl0 = c->p0_mpdgctrl0;
+ mmdc0->mpdgctrl1 = c->p0_mpdgctrl1;
+ mmdc0->mprddlctl = c->p0_mprddlctl;
+ mmdc0->mpwrdlctl = c->p0_mpwrdlctl;
+ if (i->dsize > 1) {
+ mmdc1->mpwldectrl0 = c->p1_mpwldectrl0;
+ mmdc1->mpwldectrl1 = c->p1_mpwldectrl1;
+ mmdc1->mpdgctrl0 = c->p1_mpdgctrl0;
+ mmdc1->mpdgctrl1 = c->p1_mpdgctrl1;
+ mmdc1->mprddlctl = c->p1_mprddlctl;
+ mmdc1->mpwrdlctl = c->p1_mpwrdlctl;
+ }
+
+ /* Read data DQ Byte0-3 delay */
+ mmdc0->mprddqby0dl = (u32)0x33333333;
+ mmdc0->mprddqby1dl = (u32)0x33333333;
+ if (i->dsize > 0) {
+ mmdc0->mprddqby2dl = (u32)0x33333333;
+ mmdc0->mprddqby3dl = (u32)0x33333333;
+ }
+ if (i->dsize > 1) {
+ mmdc1->mprddqby0dl = (u32)0x33333333;
+ mmdc1->mprddqby1dl = (u32)0x33333333;
+ mmdc1->mprddqby2dl = (u32)0x33333333;
+ mmdc1->mprddqby3dl = (u32)0x33333333;
+ }
+
+ /* MMDC Termination: rtt_nom:2 RZQ/2(120ohm), rtt_nom:1 RZQ/4(60ohm) */
+ reg = (i->rtt_nom == 2) ? 0x00011117 : 0x00022227;
+ mmdc0->mpodtctrl = reg;
+ if (i->dsize > 1)
+ mmdc1->mpodtctrl = reg;
+
+ /* complete calibration */
+ reg = (1 << 11); /* Force measurement on delay-lines */
+ mmdc0->mpmur0 = reg;
+ if (i->dsize > 1)
+ mmdc1->mpmur0 = reg;
+
+ /* Step 1: configuration request */
+ mmdc0->mdscr = (u32)(1 << 15); /* config request */
+
+ /* Step 2: Timing configuration */
+ reg = (trfc << 24) | (txs << 16) | (txp << 13) | (txpdll << 9) |
+ (tfaw << 4) | tcl;
+ mmdc0->mdcfg0 = reg;
+ reg = (trcd << 29) | (trp << 26) | (trc << 21) | (tras << 16) |
+ (1 << 15) | /* trpa */
+ (twr << 9) | (tmrd << 5) | tcwl;
+ mmdc0->mdcfg1 = reg;
+ reg = (tdllk << 16) | (trtp << 6) | (twtr << 3) | trrd;
+ mmdc0->mdcfg2 = reg;
+ reg = (taofpd << 27) | (taonpd << 24) | (tanpd << 20) | (taxpd << 16) |
+ (todtlon << 12) | (todt_idle_off << 4);
+ mmdc0->mdotc = reg;
+ mmdc0->mdasp = CS0_END; /* CS addressing */
+
+ /* Step 3: Configure DDR type */
+ reg = (i->cs1_mirror << 19) | (i->walat << 16) | (i->bi_on << 12) |
+ (i->mif3_mode << 9) | (i->ralat << 6);
+ mmdc0->mdmisc = reg;
+
+ /* Step 4: Configure delay while leaving reset */
+ reg = (txpr << 16) | (i->sde_to_rst << 8) | (i->rst_to_cke << 0);
+ mmdc0->mdor = reg;
+
+ /* Step 5: Configure DDR physical parameters (density and burst len) */
+ reg = (m->rowaddr - 11) << 24 | /* ROW */
+ (m->coladdr - 9) << 20 | /* COL */
+ (1 << 19) | /* Burst Length = 8 for DDR3 */
+ (i->dsize << 16); /* DDR data bus size */
+ mmdc0->mdctl = reg;
+
+ /* Step 6: Perform ZQ calibration */
+ reg = (u32)0xa1390001; /* one-time HW ZQ calib */
+ mmdc0->mpzqhwctrl = reg;
+ if (i->dsize > 1)
+ mmdc1->mpzqhwctrl = reg;
+
+ /* Step 7: Enable MMDC with desired chip select */
+ reg = mmdc0->mdctl |
+ (1 << 31) | /* SDE_0 for CS0 */
+ ((i->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */
+ mmdc0->mdctl = reg;
+
+ /* Step 8: Write Mode Registers to Init DDR3 devices */
+ for (cs = 0; cs < i->ncs; cs++) {
+ /* MR2 */
+ reg = (i->rtt_wr & 3) << 9 | (m->SRT & 1) << 7 |
+ ((tcwl - 3) & 3) << 3;
+ mmdc0->mdscr = (u32)MR(reg, 2, 3, cs);
+ /* MR3 */
+ mmdc0->mdscr = (u32)MR(0, 3, 3, cs);
+ /* MR1 */
+ reg = ((i->rtt_nom & 1) ? 1 : 0) << 2 |
+ ((i->rtt_nom & 2) ? 1 : 0) << 6;
+ mmdc0->mdscr = (u32)MR(reg, 1, 3, cs);
+ reg = ((tcl - 1) << 4) | /* CAS */
+ (1 << 8) | /* DLL Reset */
+ ((twr - 3) << 9); /* Write Recovery */
+ /* MR0 */
+ mmdc0->mdscr = (u32)MR(reg, 0, 3, cs);
+ /* ZQ calibration */
+ reg = (1 << 10);
+ mmdc0->mdscr = (u32)MR(reg, 0, 4, cs);
+ }
+
+ /* Step 10: Power down control and self-refresh */
+ reg = (tcke & 0x7) << 16 |
+ 5 << 12 | /* PWDT_1: 256 cycles */
+ 5 << 8 | /* PWDT_0: 256 cycles */
+ 1 << 6 | /* BOTH_CS_PD */
+ (tcksrx & 0x7) << 3 |
+ (tcksre & 0x7);
+ mmdc0->mdpdc = reg;
+ mmdc0->mapsr = (u32)0x00011006; /* ADOPT power down enabled */
+
+ /* Step 11: Configure ZQ calibration: one-time and periodic 1ms */
+ mmdc0->mpzqhwctrl = (u32)0xa1390003;
+ if (i->dsize > 1)
+ mmdc1->mpzqhwctrl = (u32)0xa1390003;
+
+ /* Step 12: Configure and activate periodic refresh */
+ reg = (1 << 14) | /* REF_SEL: Periodic refresh cycles of 32kHz */
+ (7 << 11); /* REFR: Refresh Rate - 8 refreshes */
+ mmdc0->mdref = reg;
+
+ /* Step 13: Deassert config request - init complete */
+ mmdc0->mdscr = (u32)0x00000000;
+
+ /* wait for auto-ZQ calibration to complete */
+ mdelay(1);
+}
#include <common.h>
#include <asm/io.h>
#include <asm/arch/hab.h>
+#include <asm/arch/sys_proto.h>
/* -------- start of HAB API updates ------------*/
-#define hab_rvt_report_event ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT)
-#define hab_rvt_report_status ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS)
-#define hab_rvt_authenticate_image \
- ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE)
-#define hab_rvt_entry ((hab_rvt_entry_t *)HAB_RVT_ENTRY)
-#define hab_rvt_exit ((hab_rvt_exit_t *)HAB_RVT_EXIT)
-#define hab_rvt_clock_init HAB_RVT_CLOCK_INIT
+
+#define hab_rvt_report_event_p \
+( \
+ ((is_cpu_type(MXC_CPU_MX6Q) || \
+ is_cpu_type(MXC_CPU_MX6D)) && \
+ (soc_rev() >= CHIP_REV_1_5)) ? \
+ ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
+ (is_cpu_type(MXC_CPU_MX6DL) && \
+ (soc_rev() >= CHIP_REV_1_2)) ? \
+ ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \
+ ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) \
+)
+
+#define hab_rvt_report_status_p \
+( \
+ ((is_cpu_type(MXC_CPU_MX6Q) || \
+ is_cpu_type(MXC_CPU_MX6D)) && \
+ (soc_rev() >= CHIP_REV_1_5)) ? \
+ ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
+ (is_cpu_type(MXC_CPU_MX6DL) && \
+ (soc_rev() >= CHIP_REV_1_2)) ? \
+ ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\
+ ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) \
+)
+
+#define hab_rvt_authenticate_image_p \
+( \
+ ((is_cpu_type(MXC_CPU_MX6Q) || \
+ is_cpu_type(MXC_CPU_MX6D)) && \
+ (soc_rev() >= CHIP_REV_1_5)) ? \
+ ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
+ (is_cpu_type(MXC_CPU_MX6DL) && \
+ (soc_rev() >= CHIP_REV_1_2)) ? \
+ ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \
+ ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) \
+)
+
+#define hab_rvt_entry_p \
+( \
+ ((is_cpu_type(MXC_CPU_MX6Q) || \
+ is_cpu_type(MXC_CPU_MX6D)) && \
+ (soc_rev() >= CHIP_REV_1_5)) ? \
+ ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
+ (is_cpu_type(MXC_CPU_MX6DL) && \
+ (soc_rev() >= CHIP_REV_1_2)) ? \
+ ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \
+ ((hab_rvt_entry_t *)HAB_RVT_ENTRY) \
+)
+
+#define hab_rvt_exit_p \
+( \
+ ((is_cpu_type(MXC_CPU_MX6Q) || \
+ is_cpu_type(MXC_CPU_MX6D)) && \
+ (soc_rev() >= CHIP_REV_1_5)) ? \
+ ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
+ (is_cpu_type(MXC_CPU_MX6DL) && \
+ (soc_rev() >= CHIP_REV_1_2)) ? \
+ ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \
+ ((hab_rvt_exit_t *)HAB_RVT_EXIT) \
+)
bool is_hab_enabled(void)
{
size_t bytes = sizeof(event_data); /* Event size in bytes */
enum hab_config config = 0;
enum hab_state state = 0;
+ hab_rvt_report_event_t *hab_rvt_report_event;
+ hab_rvt_report_status_t *hab_rvt_report_status;
+
+ hab_rvt_report_event = hab_rvt_report_event_p;
+ hab_rvt_report_status = hab_rvt_report_status_p;
if (is_hab_enabled())
puts("\nSecure boot enabled\n");
obj-$(CONFIG_SCSI_AHCI_PLAT) += sata.o
endif
+ifeq ($(CONFIG_SYS_DCACHE_OFF),)
+obj-y += omap-cache.o
+endif
+
ifeq ($(CONFIG_OMAP34XX),)
obj-y += boot-common.o
obj-y += lowlevel_init.o
#include <asm/emif.h>
#include <asm/omap_common.h>
#include <linux/compiler.h>
-#include <asm/cache.h>
#include <asm/system.h>
-#define ARMV7_DCACHE_WRITEBACK 0xe
-#define ARMV7_DOMAIN_CLIENT 1
-#define ARMV7_DOMAIN_MASK (0x3 << 0)
-
DECLARE_GLOBAL_DATA_PTR;
void do_set_mux(u32 base, struct pad_conf_entry const *array, int size)
return 0;
}
#endif
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-
-void dram_bank_mmu_setup(int bank)
-{
- bd_t *bd = gd->bd;
- int i;
-
- u32 start = bd->bi_dram[bank].start >> 20;
- u32 size = bd->bi_dram[bank].size >> 20;
- u32 end = start + size;
-
- debug("%s: bank: %d\n", __func__, bank);
- for (i = start; i < end; i++)
- set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
-
-}
-
-void arm_init_domains(void)
-{
- u32 reg;
-
- reg = get_dacr();
- /*
- * Set DOMAIN to client access so that all permissions
- * set in pagetables are validated by the mmu.
- */
- reg &= ~ARMV7_DOMAIN_MASK;
- reg |= ARMV7_DOMAIN_CLIENT;
- set_dacr(reg);
-}
-#endif
--- /dev/null
+/*
+ *
+ * Common functions for OMAP4/5 based boards
+ *
+ * (C) Copyright 2010
+ * Texas Instruments, <www.ti.com>
+ *
+ * Author :
+ * Aneesh V <aneesh@ti.com>
+ * Steve Sakoman <steve@sakoman.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/cache.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define ARMV7_DCACHE_WRITEBACK 0xe
+#define ARMV7_DOMAIN_CLIENT 1
+#define ARMV7_DOMAIN_MASK (0x3 << 0)
+
+void enable_caches(void)
+{
+ /* Enable D-cache. I-cache is already enabled in start.S */
+ dcache_enable();
+}
+
+void dram_bank_mmu_setup(int bank)
+{
+ bd_t *bd = gd->bd;
+ int i;
+
+ u32 start = bd->bi_dram[bank].start >> 20;
+ u32 size = bd->bi_dram[bank].size >> 20;
+ u32 end = start + size;
+
+ debug("%s: bank: %d\n", __func__, bank);
+ for (i = start; i < end; i++)
+ set_section_dcache(i, ARMV7_DCACHE_WRITEBACK);
+}
+
+void arm_init_domains(void)
+{
+ u32 reg;
+
+ reg = get_dacr();
+ /*
+ * Set DOMAIN to client access so that all permissions
+ * set in pagetables are validated by the mmu.
+ */
+ reg &= ~ARMV7_DOMAIN_MASK;
+ reg |= ARMV7_DOMAIN_CLIENT;
+ set_dacr(reg);
+}
omap3_update_aux_cr(0, 0x2);
}
#endif /* !CONFIG_SYS_L2CACHE_OFF */
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-#endif /* !CONFIG_SYS_DCACHE_OFF */
.text :
{
*(.__image_copy_start)
+ *(.vectors)
CPUDIR/start.o (.text*)
*(.text*)
}
zynq-zc770-xm010.dtb \
zynq-zc770-xm012.dtb \
zynq-zc770-xm013.dtb
+dtb-$(CONFIG_AM33XX) += am335x-boneblack.dtb
targets += $(dtb-y)
--- /dev/null
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/ {
+ model = "TI AM335x BeagleBone";
+ compatible = "ti,am335x-bone", "ti,am33xx";
+
+ cpus {
+ cpu@0 {
+ cpu0-supply = <&dcdc2_reg>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256 MB */
+ };
+
+ am33xx_pinmux: pinmux@44e10800 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&clkout2_pin>;
+
+ user_leds_s0: user_leds_s0 {
+ pinctrl-single,pins = <
+ 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
+ 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
+ 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
+ 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
+ >;
+ };
+
+ i2c0_pins: pinmux_i2c0_pins {
+ pinctrl-single,pins = <
+ 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
+ 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
+ >;
+ };
+
+ uart0_pins: pinmux_uart0_pins {
+ pinctrl-single,pins = <
+ 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
+ 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
+ >;
+ };
+
+ clkout2_pin: pinmux_clkout2_pin {
+ pinctrl-single,pins = <
+ 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
+ >;
+ };
+
+ cpsw_default: cpsw_default {
+ pinctrl-single,pins = <
+ /* Slave 1 */
+ 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
+ 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
+ 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
+ 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
+ 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
+ 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
+ 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
+ 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
+ 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
+ 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
+ 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
+ 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
+ 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
+ >;
+ };
+
+ cpsw_sleep: cpsw_sleep {
+ pinctrl-single,pins = <
+ /* Slave 1 reset value */
+ 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+
+ davinci_mdio_default: davinci_mdio_default {
+ pinctrl-single,pins = <
+ /* MDIO */
+ 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
+ 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
+ >;
+ };
+
+ davinci_mdio_sleep: davinci_mdio_sleep {
+ pinctrl-single,pins = <
+ /* MDIO reset value */
+ 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
+ >;
+ };
+ };
+
+ ocp {
+ uart0: serial@44e09000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+
+ status = "okay";
+ };
+
+ musb: usb@47400000 {
+ status = "okay";
+
+ control@44e10000 {
+ status = "okay";
+ };
+
+ usb-phy@47401300 {
+ status = "okay";
+ };
+
+ usb-phy@47401b00 {
+ status = "okay";
+ };
+
+ usb@47401000 {
+ status = "okay";
+ };
+
+ usb@47401800 {
+ status = "okay";
+ dr_mode = "host";
+ };
+
+ dma-controller@07402000 {
+ status = "okay";
+ };
+ };
+
+ i2c0: i2c@44e0b000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ tps: tps@24 {
+ reg = <0x24>;
+ };
+
+ };
+ };
+
+ leds {
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_leds_s0>;
+
+ compatible = "gpio-leds";
+
+ led@2 {
+ label = "beaglebone:green:heartbeat";
+ gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ default-state = "off";
+ };
+
+ led@3 {
+ label = "beaglebone:green:mmc0";
+ gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "mmc0";
+ default-state = "off";
+ };
+
+ led@4 {
+ label = "beaglebone:green:usr2";
+ gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+
+ led@5 {
+ label = "beaglebone:green:usr3";
+ gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
+ default-state = "off";
+ };
+ };
+};
+
+/include/ "tps65217.dtsi"
+
+&tps {
+ regulators {
+ dcdc1_reg: regulator@0 {
+ regulator-always-on;
+ };
+
+ dcdc2_reg: regulator@1 {
+ /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
+ regulator-name = "vdd_mpu";
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <1325000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ dcdc3_reg: regulator@2 {
+ /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
+ regulator-name = "vdd_core";
+ regulator-min-microvolt = <925000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ ldo1_reg: regulator@3 {
+ regulator-always-on;
+ };
+
+ ldo2_reg: regulator@4 {
+ regulator-always-on;
+ };
+
+ ldo3_reg: regulator@5 {
+ regulator-always-on;
+ };
+
+ ldo4_reg: regulator@6 {
+ regulator-always-on;
+ };
+ };
+};
+
+&cpsw_emac0 {
+ phy_id = <&davinci_mdio>, <0>;
+ phy-mode = "mii";
+};
+
+&cpsw_emac1 {
+ phy_id = <&davinci_mdio>, <1>;
+ phy-mode = "mii";
+};
+
+&mac {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&cpsw_default>;
+ pinctrl-1 = <&cpsw_sleep>;
+
+};
+
+&davinci_mdio {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&davinci_mdio_default>;
+ pinctrl-1 = <&davinci_mdio_sleep>;
+};
--- /dev/null
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+
+#include "am33xx.dtsi"
+#include "am335x-bone-common.dtsi"
+
+&ldo3_reg {
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-always-on;
+};
--- /dev/null
+/*
+ * Device Tree Source for AM33XX SoC
+ *
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/am33xx.h>
+
+#include "skeleton.dtsi"
+
+/ {
+ compatible = "ti,am33xx";
+ interrupt-parent = <&intc>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ d_can0 = &dcan0;
+ d_can1 = &dcan1;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ phy0 = &usb0_phy;
+ phy1 = &usb1_phy;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ compatible = "arm,cortex-a8";
+ device_type = "cpu";
+ reg = <0>;
+
+ /*
+ * To consider voltage drop between PMIC and SoC,
+ * tolerance value is reduced to 2% from 4% and
+ * voltage value is increased as a precaution.
+ */
+ operating-points = <
+ /* kHz uV */
+ 720000 1285000
+ 600000 1225000
+ 500000 1125000
+ 275000 1125000
+ >;
+ voltage-tolerance = <2>; /* 2 percentage */
+ clock-latency = <300000>; /* From omap-cpufreq driver */
+ };
+ };
+
+ /*
+ * The soc node represents the soc top level view. It is uses for IPs
+ * that are not memory mapped in the MPU view or for the MPU itself.
+ */
+ soc {
+ compatible = "ti,omap-infra";
+ mpu {
+ compatible = "ti,omap3-mpu";
+ ti,hwmods = "mpu";
+ };
+ };
+
+ am33xx_pinmux: pinmux@44e10800 {
+ compatible = "pinctrl-single";
+ reg = <0x44e10800 0x0238>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0x7f>;
+ };
+
+ /*
+ * XXX: Use a flat representation of the AM33XX interconnect.
+ * The real AM33XX interconnect network is quite complex.Since
+ * that will not bring real advantage to represent that in DT
+ * for the moment, just use a fake OCP bus entry to represent
+ * the whole bus hierarchy.
+ */
+ ocp {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ ti,hwmods = "l3_main";
+
+ intc: interrupt-controller@48200000 {
+ compatible = "ti,omap2-intc";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ ti,intc-size = <128>;
+ reg = <0x48200000 0x1000>;
+ };
+
+ gpio0: gpio@44e07000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio1";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x44e07000 0x1000>;
+ interrupts = <96>;
+ };
+
+ gpio1: gpio@4804c000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio2";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x4804c000 0x1000>;
+ interrupts = <98>;
+ };
+
+ gpio2: gpio@481ac000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio3";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x481ac000 0x1000>;
+ interrupts = <32>;
+ };
+
+ gpio3: gpio@481ae000 {
+ compatible = "ti,omap4-gpio";
+ ti,hwmods = "gpio4";
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ reg = <0x481ae000 0x1000>;
+ interrupts = <62>;
+ };
+
+ uart0: serial@44e09000 {
+ compatible = "ti,omap3-uart";
+ ti,hwmods = "uart1";
+ clock-frequency = <48000000>;
+ reg = <0x44e09000 0x2000>;
+ interrupts = <72>;
+ status = "disabled";
+ };
+
+ uart1: serial@48022000 {
+ compatible = "ti,omap3-uart";
+ ti,hwmods = "uart2";
+ clock-frequency = <48000000>;
+ reg = <0x48022000 0x2000>;
+ interrupts = <73>;
+ status = "disabled";
+ };
+
+ uart2: serial@48024000 {
+ compatible = "ti,omap3-uart";
+ ti,hwmods = "uart3";
+ clock-frequency = <48000000>;
+ reg = <0x48024000 0x2000>;
+ interrupts = <74>;
+ status = "disabled";
+ };
+
+ uart3: serial@481a6000 {
+ compatible = "ti,omap3-uart";
+ ti,hwmods = "uart4";
+ clock-frequency = <48000000>;
+ reg = <0x481a6000 0x2000>;
+ interrupts = <44>;
+ status = "disabled";
+ };
+
+ uart4: serial@481a8000 {
+ compatible = "ti,omap3-uart";
+ ti,hwmods = "uart5";
+ clock-frequency = <48000000>;
+ reg = <0x481a8000 0x2000>;
+ interrupts = <45>;
+ status = "disabled";
+ };
+
+ uart5: serial@481aa000 {
+ compatible = "ti,omap3-uart";
+ ti,hwmods = "uart6";
+ clock-frequency = <48000000>;
+ reg = <0x481aa000 0x2000>;
+ interrupts = <46>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@44e0b000 {
+ compatible = "ti,omap4-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c1";
+ reg = <0x44e0b000 0x1000>;
+ interrupts = <70>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@4802a000 {
+ compatible = "ti,omap4-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c2";
+ reg = <0x4802a000 0x1000>;
+ interrupts = <71>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@4819c000 {
+ compatible = "ti,omap4-i2c";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "i2c3";
+ reg = <0x4819c000 0x1000>;
+ interrupts = <30>;
+ status = "disabled";
+ };
+
+ wdt2: wdt@44e35000 {
+ compatible = "ti,omap3-wdt";
+ ti,hwmods = "wd_timer2";
+ reg = <0x44e35000 0x1000>;
+ interrupts = <91>;
+ };
+
+ dcan0: d_can@481cc000 {
+ compatible = "bosch,d_can";
+ ti,hwmods = "d_can0";
+ reg = <0x481cc000 0x2000
+ 0x44e10644 0x4>;
+ interrupts = <52>;
+ status = "disabled";
+ };
+
+ dcan1: d_can@481d0000 {
+ compatible = "bosch,d_can";
+ ti,hwmods = "d_can1";
+ reg = <0x481d0000 0x2000
+ 0x44e10644 0x4>;
+ interrupts = <55>;
+ status = "disabled";
+ };
+
+ timer1: timer@44e31000 {
+ compatible = "ti,am335x-timer-1ms";
+ reg = <0x44e31000 0x400>;
+ interrupts = <67>;
+ ti,hwmods = "timer1";
+ ti,timer-alwon;
+ };
+
+ timer2: timer@48040000 {
+ compatible = "ti,am335x-timer";
+ reg = <0x48040000 0x400>;
+ interrupts = <68>;
+ ti,hwmods = "timer2";
+ };
+
+ timer3: timer@48042000 {
+ compatible = "ti,am335x-timer";
+ reg = <0x48042000 0x400>;
+ interrupts = <69>;
+ ti,hwmods = "timer3";
+ };
+
+ timer4: timer@48044000 {
+ compatible = "ti,am335x-timer";
+ reg = <0x48044000 0x400>;
+ interrupts = <92>;
+ ti,hwmods = "timer4";
+ ti,timer-pwm;
+ };
+
+ timer5: timer@48046000 {
+ compatible = "ti,am335x-timer";
+ reg = <0x48046000 0x400>;
+ interrupts = <93>;
+ ti,hwmods = "timer5";
+ ti,timer-pwm;
+ };
+
+ timer6: timer@48048000 {
+ compatible = "ti,am335x-timer";
+ reg = <0x48048000 0x400>;
+ interrupts = <94>;
+ ti,hwmods = "timer6";
+ ti,timer-pwm;
+ };
+
+ timer7: timer@4804a000 {
+ compatible = "ti,am335x-timer";
+ reg = <0x4804a000 0x400>;
+ interrupts = <95>;
+ ti,hwmods = "timer7";
+ ti,timer-pwm;
+ };
+
+ rtc@44e3e000 {
+ compatible = "ti,da830-rtc";
+ reg = <0x44e3e000 0x1000>;
+ interrupts = <75
+ 76>;
+ ti,hwmods = "rtc";
+ };
+
+ spi0: spi@48030000 {
+ compatible = "ti,omap4-mcspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x48030000 0x400>;
+ interrupts = <65>;
+ ti,spi-num-cs = <2>;
+ ti,hwmods = "spi0";
+ status = "disabled";
+ };
+
+ spi1: spi@481a0000 {
+ compatible = "ti,omap4-mcspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x481a0000 0x400>;
+ interrupts = <125>;
+ ti,spi-num-cs = <2>;
+ ti,hwmods = "spi1";
+ status = "disabled";
+ };
+
+ usb: usb@47400000 {
+ compatible = "ti,am33xx-usb";
+ reg = <0x47400000 0x1000>;
+ ranges;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ti,hwmods = "usb_otg_hs";
+ status = "disabled";
+
+ ctrl_mod: control@44e10000 {
+ compatible = "ti,am335x-usb-ctrl-module";
+ reg = <0x44e10620 0x10
+ 0x44e10648 0x4>;
+ reg-names = "phy_ctrl", "wakeup";
+ status = "disabled";
+ };
+
+ usb0_phy: usb-phy@47401300 {
+ compatible = "ti,am335x-usb-phy";
+ reg = <0x47401300 0x100>;
+ reg-names = "phy";
+ status = "disabled";
+ ti,ctrl_mod = <&ctrl_mod>;
+ };
+
+ usb0: usb@47401000 {
+ compatible = "ti,musb-am33xx";
+ status = "disabled";
+ reg = <0x47401400 0x400
+ 0x47401000 0x200>;
+ reg-names = "mc", "control";
+
+ interrupts = <18>;
+ interrupt-names = "mc";
+ dr_mode = "otg";
+ mentor,multipoint = <1>;
+ mentor,num-eps = <16>;
+ mentor,ram-bits = <12>;
+ mentor,power = <500>;
+ phys = <&usb0_phy>;
+
+ dmas = <&cppi41dma 0 0 &cppi41dma 1 0
+ &cppi41dma 2 0 &cppi41dma 3 0
+ &cppi41dma 4 0 &cppi41dma 5 0
+ &cppi41dma 6 0 &cppi41dma 7 0
+ &cppi41dma 8 0 &cppi41dma 9 0
+ &cppi41dma 10 0 &cppi41dma 11 0
+ &cppi41dma 12 0 &cppi41dma 13 0
+ &cppi41dma 14 0 &cppi41dma 0 1
+ &cppi41dma 1 1 &cppi41dma 2 1
+ &cppi41dma 3 1 &cppi41dma 4 1
+ &cppi41dma 5 1 &cppi41dma 6 1
+ &cppi41dma 7 1 &cppi41dma 8 1
+ &cppi41dma 9 1 &cppi41dma 10 1
+ &cppi41dma 11 1 &cppi41dma 12 1
+ &cppi41dma 13 1 &cppi41dma 14 1>;
+ dma-names =
+ "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
+ "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
+ "rx14", "rx15",
+ "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
+ "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
+ "tx14", "tx15";
+ };
+
+ usb1_phy: usb-phy@47401b00 {
+ compatible = "ti,am335x-usb-phy";
+ reg = <0x47401b00 0x100>;
+ reg-names = "phy";
+ status = "disabled";
+ ti,ctrl_mod = <&ctrl_mod>;
+ };
+
+ usb1: usb@47401800 {
+ compatible = "ti,musb-am33xx";
+ status = "disabled";
+ reg = <0x47401c00 0x400
+ 0x47401800 0x200>;
+ reg-names = "mc", "control";
+ interrupts = <19>;
+ interrupt-names = "mc";
+ dr_mode = "otg";
+ mentor,multipoint = <1>;
+ mentor,num-eps = <16>;
+ mentor,ram-bits = <12>;
+ mentor,power = <500>;
+ phys = <&usb1_phy>;
+
+ dmas = <&cppi41dma 15 0 &cppi41dma 16 0
+ &cppi41dma 17 0 &cppi41dma 18 0
+ &cppi41dma 19 0 &cppi41dma 20 0
+ &cppi41dma 21 0 &cppi41dma 22 0
+ &cppi41dma 23 0 &cppi41dma 24 0
+ &cppi41dma 25 0 &cppi41dma 26 0
+ &cppi41dma 27 0 &cppi41dma 28 0
+ &cppi41dma 29 0 &cppi41dma 15 1
+ &cppi41dma 16 1 &cppi41dma 17 1
+ &cppi41dma 18 1 &cppi41dma 19 1
+ &cppi41dma 20 1 &cppi41dma 21 1
+ &cppi41dma 22 1 &cppi41dma 23 1
+ &cppi41dma 24 1 &cppi41dma 25 1
+ &cppi41dma 26 1 &cppi41dma 27 1
+ &cppi41dma 28 1 &cppi41dma 29 1>;
+ dma-names =
+ "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
+ "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
+ "rx14", "rx15",
+ "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
+ "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
+ "tx14", "tx15";
+ };
+
+ cppi41dma: dma-controller@07402000 {
+ compatible = "ti,am3359-cppi41";
+ reg = <0x47400000 0x1000
+ 0x47402000 0x1000
+ 0x47403000 0x1000
+ 0x47404000 0x4000>;
+ reg-names = "glue", "controller", "scheduler", "queuemgr";
+ interrupts = <17>;
+ interrupt-names = "glue";
+ #dma-cells = <2>;
+ #dma-channels = <30>;
+ #dma-requests = <256>;
+ status = "disabled";
+ };
+ };
+
+ epwmss0: epwmss@48300000 {
+ compatible = "ti,am33xx-pwmss";
+ reg = <0x48300000 0x10>;
+ ti,hwmods = "epwmss0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges = <0x48300100 0x48300100 0x80 /* ECAP */
+ 0x48300180 0x48300180 0x80 /* EQEP */
+ 0x48300200 0x48300200 0x80>; /* EHRPWM */
+
+ ecap0: ecap@48300100 {
+ compatible = "ti,am33xx-ecap";
+ #pwm-cells = <3>;
+ reg = <0x48300100 0x80>;
+ ti,hwmods = "ecap0";
+ status = "disabled";
+ };
+
+ ehrpwm0: ehrpwm@48300200 {
+ compatible = "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x48300200 0x80>;
+ ti,hwmods = "ehrpwm0";
+ status = "disabled";
+ };
+ };
+
+ epwmss1: epwmss@48302000 {
+ compatible = "ti,am33xx-pwmss";
+ reg = <0x48302000 0x10>;
+ ti,hwmods = "epwmss1";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges = <0x48302100 0x48302100 0x80 /* ECAP */
+ 0x48302180 0x48302180 0x80 /* EQEP */
+ 0x48302200 0x48302200 0x80>; /* EHRPWM */
+
+ ecap1: ecap@48302100 {
+ compatible = "ti,am33xx-ecap";
+ #pwm-cells = <3>;
+ reg = <0x48302100 0x80>;
+ ti,hwmods = "ecap1";
+ status = "disabled";
+ };
+
+ ehrpwm1: ehrpwm@48302200 {
+ compatible = "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x48302200 0x80>;
+ ti,hwmods = "ehrpwm1";
+ status = "disabled";
+ };
+ };
+
+ epwmss2: epwmss@48304000 {
+ compatible = "ti,am33xx-pwmss";
+ reg = <0x48304000 0x10>;
+ ti,hwmods = "epwmss2";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ status = "disabled";
+ ranges = <0x48304100 0x48304100 0x80 /* ECAP */
+ 0x48304180 0x48304180 0x80 /* EQEP */
+ 0x48304200 0x48304200 0x80>; /* EHRPWM */
+
+ ecap2: ecap@48304100 {
+ compatible = "ti,am33xx-ecap";
+ #pwm-cells = <3>;
+ reg = <0x48304100 0x80>;
+ ti,hwmods = "ecap2";
+ status = "disabled";
+ };
+
+ ehrpwm2: ehrpwm@48304200 {
+ compatible = "ti,am33xx-ehrpwm";
+ #pwm-cells = <3>;
+ reg = <0x48304200 0x80>;
+ ti,hwmods = "ehrpwm2";
+ status = "disabled";
+ };
+ };
+
+ mac: ethernet@4a100000 {
+ compatible = "ti,cpsw";
+ ti,hwmods = "cpgmac0";
+ cpdma_channels = <8>;
+ ale_entries = <1024>;
+ bd_ram_size = <0x2000>;
+ no_bd_ram = <0>;
+ rx_descs = <64>;
+ mac_control = <0x20>;
+ slaves = <2>;
+ active_slave = <0>;
+ cpts_clock_mult = <0x80000000>;
+ cpts_clock_shift = <29>;
+ reg = <0x4a100000 0x800
+ 0x4a101200 0x100>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ /*
+ * c0_rx_thresh_pend
+ * c0_rx_pend
+ * c0_tx_pend
+ * c0_misc_pend
+ */
+ interrupts = <40 41 42 43>;
+ ranges;
+
+ davinci_mdio: mdio@4a101000 {
+ compatible = "ti,davinci_mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ ti,hwmods = "davinci_mdio";
+ bus_freq = <1000000>;
+ reg = <0x4a101000 0x100>;
+ };
+
+ cpsw_emac0: slave@4a100200 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+
+ cpsw_emac1: slave@4a100300 {
+ /* Filled in by U-Boot */
+ mac-address = [ 00 00 00 00 00 00 ];
+ };
+ };
+
+ ocmcram: ocmcram@40300000 {
+ compatible = "ti,am3352-ocmcram";
+ reg = <0x40300000 0x10000>;
+ ti,hwmods = "ocmcram";
+ };
+
+ wkup_m3: wkup_m3@44d00000 {
+ compatible = "ti,am3353-wkup-m3";
+ reg = <0x44d00000 0x4000 /* M3 UMEM */
+ 0x44d80000 0x2000>; /* M3 DMEM */
+ ti,hwmods = "wkup_m3";
+ };
+
+ elm: elm@48080000 {
+ compatible = "ti,am3352-elm";
+ reg = <0x48080000 0x2000>;
+ interrupts = <4>;
+ ti,hwmods = "elm";
+ status = "disabled";
+ };
+
+ tscadc: tscadc@44e0d000 {
+ compatible = "ti,am3359-tscadc";
+ reg = <0x44e0d000 0x1000>;
+ interrupt-parent = <&intc>;
+ interrupts = <16>;
+ ti,hwmods = "adc_tsc";
+ status = "disabled";
+
+ tsc {
+ compatible = "ti,am3359-tsc";
+ };
+ am335x_adc: adc {
+ #io-channel-cells = <1>;
+ compatible = "ti,am3359-adc";
+ };
+ };
+
+ gpmc: gpmc@50000000 {
+ compatible = "ti,am3352-gpmc";
+ ti,hwmods = "gpmc";
+ reg = <0x50000000 0x2000>;
+ interrupts = <100>;
+ gpmc,num-cs = <7>;
+ gpmc,num-waitpins = <2>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ status = "disabled";
+ };
+ };
+};
--- /dev/null
+/*
+ * This header provides constants for most GPIO bindings.
+ *
+ * Most GPIO bindings include a flags cell as part of the GPIO specifier.
+ * In most cases, the format of the flags cell uses the standard values
+ * defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_GPIO_H
+#define _DT_BINDINGS_GPIO_GPIO_H
+
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW 1
+
+#endif
--- /dev/null
+/*
+ * This header provides constants specific to AM33XX pinctrl bindings.
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_AM33XX_H
+#define _DT_BINDINGS_PINCTRL_AM33XX_H
+
+#include <dt-bindings/pinctrl/omap.h>
+
+/* am33xx specific mux bit defines */
+#undef PULL_ENA
+#undef INPUT_EN
+
+#define PULL_DISABLE (1 << 3)
+#define INPUT_EN (1 << 5)
+#define SLEWCTRL_FAST (1 << 6)
+
+/* update macro depending on INPUT_EN and PULL_ENA */
+#undef PIN_OUTPUT
+#undef PIN_OUTPUT_PULLUP
+#undef PIN_OUTPUT_PULLDOWN
+#undef PIN_INPUT
+#undef PIN_INPUT_PULLUP
+#undef PIN_INPUT_PULLDOWN
+
+#define PIN_OUTPUT (PULL_DISABLE)
+#define PIN_OUTPUT_PULLUP (PULL_UP)
+#define PIN_OUTPUT_PULLDOWN 0
+#define PIN_INPUT (INPUT_EN | PULL_DISABLE)
+#define PIN_INPUT_PULLUP (INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN (INPUT_EN)
+
+/* undef non-existing modes */
+#undef PIN_OFF_NONE
+#undef PIN_OFF_OUTPUT_HIGH
+#undef PIN_OFF_OUTPUT_LOW
+#undef PIN_OFF_INPUT_PULLUP
+#undef PIN_OFF_INPUT_PULLDOWN
+#undef PIN_OFF_WAKEUPENABLE
+
+#endif
+
--- /dev/null
+/*
+ * This header provides constants for OMAP pinctrl bindings.
+ *
+ * Copyright (C) 2009 Nokia
+ * Copyright (C) 2009-2010 Texas Instruments
+ */
+
+#ifndef _DT_BINDINGS_PINCTRL_OMAP_H
+#define _DT_BINDINGS_PINCTRL_OMAP_H
+
+/* 34xx mux mode options for each pin. See TRM for options */
+#define MUX_MODE0 0
+#define MUX_MODE1 1
+#define MUX_MODE2 2
+#define MUX_MODE3 3
+#define MUX_MODE4 4
+#define MUX_MODE5 5
+#define MUX_MODE6 6
+#define MUX_MODE7 7
+
+/* 24xx/34xx mux bit defines */
+#define PULL_ENA (1 << 3)
+#define PULL_UP (1 << 4)
+#define ALTELECTRICALSEL (1 << 5)
+
+/* 34xx specific mux bit defines */
+#define INPUT_EN (1 << 8)
+#define OFF_EN (1 << 9)
+#define OFFOUT_EN (1 << 10)
+#define OFFOUT_VAL (1 << 11)
+#define OFF_PULL_EN (1 << 12)
+#define OFF_PULL_UP (1 << 13)
+#define WAKEUP_EN (1 << 14)
+
+/* 44xx specific mux bit defines */
+#define WAKEUP_EVENT (1 << 15)
+
+/* Active pin states */
+#define PIN_OUTPUT 0
+#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP)
+#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA)
+#define PIN_INPUT INPUT_EN
+#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP)
+#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN)
+
+/* Off mode states */
+#define PIN_OFF_NONE 0
+#define PIN_OFF_OUTPUT_HIGH (OFF_EN | OFFOUT_EN | OFFOUT_VAL)
+#define PIN_OFF_OUTPUT_LOW (OFF_EN | OFFOUT_EN)
+#define PIN_OFF_INPUT_PULLUP (OFF_EN | OFF_PULL_EN | OFF_PULL_UP)
+#define PIN_OFF_INPUT_PULLDOWN (OFF_EN | OFF_PULL_EN)
+#define PIN_OFF_WAKEUPENABLE WAKEUP_EN
+
+#endif
+
--- /dev/null
+../../../../include/dt-bindings
\ No newline at end of file
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
#include "skeleton.dtsi"
/ {
0 143 0x04>;
};
- gpio: gpio {
+ gpio: gpio@6000d000 {
compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
reg = <0x6000d000 0x1000>;
- interrupts = <0 32 0x04
- 0 33 0x04
- 0 34 0x04
- 0 35 0x04
- 0 55 0x04
- 0 87 0x04
- 0 89 0x04
- 0 125 0x04>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
#include "skeleton.dtsi"
/ {
gpio: gpio@6000d000 {
compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio";
reg = <0x6000d000 0x1000>;
- interrupts = <0 32 0x04
- 0 33 0x04
- 0 34 0x04
- 0 35 0x04
- 0 55 0x04
- 0 87 0x04
- 0 89 0x04
- 0 125 0x04>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
#include "skeleton.dtsi"
/ {
gpio: gpio@6000d000 {
compatible = "nvidia,tegra20-gpio";
- reg = < 0x6000d000 0x1000 >;
- interrupts = < 64 65 66 67 87 119 121 >;
+ reg = <0x6000d000 0x1000>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
+ #interrupt-cells = <2>;
+ interrupt-controller;
};
pinmux: pinmux@70000000 {
+#include <dt-bindings/gpio/tegra-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
#include "skeleton.dtsi"
/ {
clocks = <&tegra_car 34>;
};
- gpio: gpio {
+ gpio: gpio@6000d000 {
compatible = "nvidia,tegra30-gpio";
reg = <0x6000d000 0x1000>;
- interrupts = <0 32 0x04
- 0 33 0x04
- 0 34 0x04
- 0 35 0x04
- 0 55 0x04
- 0 87 0x04
- 0 89 0x04
- 0 125 0x04>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
#gpio-cells = <2>;
gpio-controller;
#interrupt-cells = <2>;
--- /dev/null
+/*
+ * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * Integrated Power Management Chip
+ * http://www.ti.com/lit/ds/symlink/tps65217.pdf
+ */
+
+&tps {
+ compatible = "ti,tps65217";
+
+ regulators {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dcdc1_reg: regulator@0 {
+ reg = <0>;
+ regulator-compatible = "dcdc1";
+ };
+
+ dcdc2_reg: regulator@1 {
+ reg = <1>;
+ regulator-compatible = "dcdc2";
+ };
+
+ dcdc3_reg: regulator@2 {
+ reg = <2>;
+ regulator-compatible = "dcdc3";
+ };
+
+ ldo1_reg: regulator@3 {
+ reg = <3>;
+ regulator-compatible = "ldo1";
+ };
+
+ ldo2_reg: regulator@4 {
+ reg = <4>;
+ regulator-compatible = "ldo2";
+ };
+
+ ldo3_reg: regulator@5 {
+ reg = <5>;
+ regulator-compatible = "ldo3";
+ };
+
+ ldo4_reg: regulator@6 {
+ reg = <6>;
+ regulator-compatible = "ldo4";
+ };
+ };
+};
endif
ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
obj-y += misc.o
+obj-$(CONFIG_SPL_BUILD) += spl.o
endif
ifeq ($(SOC),$(filter $(SOC),mx6))
obj-$(CONFIG_CMD_SATA) += sata.o
$(Q)mkdir -p $(dir $@)
$(call if_changed_dep,cpp_cfg)
-quiet_cmd_mkimage = MKIMAGE $@
-cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
- $(if $(KBUILD_VERBOSE:1=), >/dev/null)
-
MKIMAGEFLAGS_u-boot.imx = -n $(filter-out $< $(PHONY),$^) -T imximage \
-e $(CONFIG_SYS_TEXT_BASE)
static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9};
static const unsigned char bank_lookup[] = {3, 2};
+/* these MMDC registers are common to the IMX53 and IMX6 */
struct esd_mmdc_regs {
uint32_t ctl;
uint32_t pdc;
uint32_t cfg1;
uint32_t cfg2;
uint32_t misc;
- uint32_t scr;
- uint32_t ref;
- uint32_t rsvd1;
- uint32_t rsvd2;
- uint32_t rwd;
- uint32_t or;
- uint32_t mrr;
- uint32_t cfg3lp;
- uint32_t mr4;
};
#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7)
#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1)
#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1)
+/*
+ * imx_ddr_size - return size in bytes of DRAM according MMDC config
+ * The MMDC MDCTL register holds the number of bits for row, col, and data
+ * width and the MMDC MDMISC register holds the number of banks. Combine
+ * all these bits to determine the meme size the MMDC has been configured for
+ */
unsigned imx_ddr_size(void)
{
struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE;
#include <common.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
+#if !defined(CONFIG_MX25) && !defined(CONFIG_VF610)
+#include <asm/arch/sys_proto.h>
+#endif
#include <asm/imx-common/iomux-v3.h>
static void *base = (void *)IOMUXC_BASE_ADDR;
#endif
}
+/* configures a list of pads within declared with IOMUX_PADS macro */
void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
unsigned count)
{
iomux_v3_cfg_t const *p = pad_list;
+ int stride;
int i;
- for (i = 0; i < count; i++)
- imx_iomux_v3_setup_pad(*p++);
+#if defined(CONFIG_MX6QDL)
+ stride = 2;
+ if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+ p += 1;
+#else
+ stride = 1;
+#endif
+ for (i = 0; i < count; i++) {
+ imx_iomux_v3_setup_pad(*p);
+ p += stride;
+ }
}
#include <asm/arch/iomux.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
int setup_sata(void)
{
struct iomuxc_base_regs *const iomuxc_regs
= (struct iomuxc_base_regs *)IOMUXC_BASE_ADDR;
+ int ret;
- int ret = enable_sata_clock();
+ if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+ return 1;
+
+ ret = enable_sata_clock();
if (ret)
return ret;
--- /dev/null
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/spl.h>
+#include <spl.h>
+
+#if defined(CONFIG_MX6)
+/* determine boot device from SRC_SBMR1 register (BOOT_CFG[4:1]) */
+u32 spl_boot_device(void)
+{
+ struct src *psrc = (struct src *)SRC_BASE_ADDR;
+ unsigned reg = readl(&psrc->sbmr1);
+
+ /* BOOT_CFG1[7:4] - see IMX6DQRM Table 8-8 */
+ switch ((reg & 0x000000FF) >> 4) {
+ /* EIM: See 8.5.1, Table 8-9 */
+ case 0x0:
+ /* BOOT_CFG1[3]: NOR/OneNAND Selection */
+ if ((reg & 0x00000008) >> 3)
+ return BOOT_DEVICE_ONENAND;
+ else
+ return BOOT_DEVICE_NOR;
+ break;
+ /* SATA: See 8.5.4, Table 8-20 */
+ case 0x2:
+ return BOOT_DEVICE_SATA;
+ /* Serial ROM: See 8.5.5.1, Table 8-22 */
+ case 0x3:
+ /* BOOT_CFG4[2:0] */
+ switch ((reg & 0x07000000) >> 24) {
+ case 0x0 ... 0x4:
+ return BOOT_DEVICE_SPI;
+ case 0x5 ... 0x7:
+ return BOOT_DEVICE_I2C;
+ }
+ break;
+ /* SD/eSD: 8.5.3, Table 8-15 */
+ case 0x4:
+ case 0x5:
+ return BOOT_DEVICE_MMC1;
+ /* MMC/eMMC: 8.5.3 */
+ case 0x6:
+ case 0x7:
+ return BOOT_DEVICE_MMC1;
+ /* NAND Flash: 8.5.2 */
+ case 0x8 ... 0xf:
+ return BOOT_DEVICE_NAND;
+ }
+ return BOOT_DEVICE_NONE;
+}
+#endif
+
+#if defined(CONFIG_SPL_MMC_SUPPORT)
+/* called from spl_mmc to see type of boot mode for storage (RAW or FAT) */
+u32 spl_boot_mode(void)
+{
+ switch (spl_boot_device()) {
+ /* for MMC return either RAW or FAT mode */
+ case BOOT_DEVICE_MMC1:
+ case BOOT_DEVICE_MMC2:
+#ifdef CONFIG_SPL_FAT_SUPPORT
+ return MMCSD_MODE_FAT;
+#else
+ return MMCSD_MODE_RAW;
+#endif
+ break;
+ default:
+ puts("spl: ERROR: unsupported device\n");
+ hang();
+ }
+}
+#endif
+++ /dev/null
-/*
- * Copyright (C) 2013 Atmel Corporation
- * Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_SPL_H_
-#define _ASM_ARCH_SPL_H_
-
-enum {
- BOOT_DEVICE_NONE,
-#ifdef CONFIG_SYS_USE_MMC
- BOOT_DEVICE_MMC1,
- BOOT_DEVICE_MMC2,
- BOOT_DEVICE_MMC2_2,
-#elif CONFIG_SYS_USE_NANDFLASH
- BOOT_DEVICE_NAND,
-#elif CONFIG_SYS_USE_SERIALFLASH
- BOOT_DEVICE_SPI,
-#endif
-};
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2012
- * Texas Instruments, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _ASM_ARCH_SPL_H_
-#define _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_NAND 1
-#define BOOT_DEVICE_SPI 2
-#define BOOT_DEVICE_MMC1 3
-#define BOOT_DEVICE_MMC2 4 /* dummy */
-#define BOOT_DEVICE_MMC2_2 5 /* dummy */
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2012
- * Texas Instruments, <www.ti.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _ASM_ARCH_SPL_H_
-#define _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_NONE 0
-#define BOOT_DEVICE_XIP 1
-#define BOOT_DEVICE_XIPWAIT 2
-#define BOOT_DEVICE_NAND 3
-#define BOOT_DEVICE_ONENAND 4
-#define BOOT_DEVICE_MMC1 5
-#define BOOT_DEVICE_MMC2 6
-#define BOOT_DEVICE_MMC2_2 7
-#define BOOT_DEVICE_NOR 8
-#define BOOT_DEVICE_I2C 9
-#define BOOT_DEVICE_SPI 10
-
-#endif
+++ /dev/null
-/*
- * Copyright (C) 2013 Marek Vasut <marex@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __ASM_ARCH_SPL_H__
-#define __ASM_ARCH_SPL_H__
-
-#define BOOT_DEVICE_NONE 0
-#define BOOT_DEVICE_NAND 1
-
-#endif /* __ASM_ARCH_SPL_H__ */
void **, size_t *, hab_loader_callback_f_t);
typedef void hapi_clock_init_t(void);
-#define HAB_RVT_REPORT_EVENT (*(uint32_t *)0x000000B4)
-#define HAB_RVT_REPORT_STATUS (*(uint32_t *)0x000000B8)
-#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x000000A4)
-#define HAB_RVT_ENTRY (*(uint32_t *)0x00000098)
-#define HAB_RVT_EXIT (*(uint32_t *)0x0000009C)
-#define HAB_RVT_CLOCK_INIT ((hapi_clock_init_t *)0x0000024D)
+#define HAB_RVT_REPORT_EVENT (*(uint32_t *)0x000000B4)
+#define HAB_RVT_REPORT_STATUS (*(uint32_t *)0x000000B8)
+#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x000000A4)
+#define HAB_RVT_ENTRY (*(uint32_t *)0x00000098)
+#define HAB_RVT_EXIT (*(uint32_t *)0x0000009C)
+
+#define HAB_RVT_REPORT_EVENT_NEW (*(uint32_t *)0x000000B8)
+#define HAB_RVT_REPORT_STATUS_NEW (*(uint32_t *)0x000000BC)
+#define HAB_RVT_AUTHENTICATE_IMAGE_NEW (*(uint32_t *)0x000000A8)
+#define HAB_RVT_ENTRY_NEW (*(uint32_t *)0x0000009C)
+#define HAB_RVT_EXIT_NEW (*(uint32_t *)0x000000A0)
#define HAB_CID_ROM 0 /**< ROM Caller ID */
#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/
#define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
#define CHIP_REV_1_0 0x10
+#define CHIP_REV_1_2 0x12
+#define CHIP_REV_1_5 0x15
#define IRAM_SIZE 0x00040000
#define FEC_QUIRK_ENET_MAC
#define IOMUXC_GPR12_LOS_LEVEL_MASK (0x1f << 4)
#define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 << 10)
#define IOMUXC_GPR12_DEVICE_TYPE_EP (0x0 << 12)
-#define IOMUXC_GPR12_DEVICE_TYPE_RC (0x2 << 12)
+#define IOMUXC_GPR12_DEVICE_TYPE_RC (0x4 << 12)
#define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf << 12)
/*
#ifndef __ASM_ARCH_MX6_DDR_H__
#define __ASM_ARCH_MX6_DDR_H__
+#ifndef CONFIG_SPL_BUILD
#ifdef CONFIG_MX6Q
#include "mx6q-ddr.h"
#else
#error "Please select cpu"
#endif /* CONFIG_MX6DL or CONFIG_MX6S */
#endif /* CONFIG_MX6Q */
+#else
+
+/* MMDC P0/P1 Registers */
+struct mmdc_p_regs {
+ u32 mdctl;
+ u32 mdpdc;
+ u32 mdotc;
+ u32 mdcfg0;
+ u32 mdcfg1;
+ u32 mdcfg2;
+ u32 mdmisc;
+ u32 mdscr;
+ u32 mdref;
+ u32 res1[2];
+ u32 mdrwd;
+ u32 mdor;
+ u32 res2[3];
+ u32 mdasp;
+ u32 res3[240];
+ u32 mapsr;
+ u32 res4[254];
+ u32 mpzqhwctrl;
+ u32 res5[2];
+ u32 mpwldectrl0;
+ u32 mpwldectrl1;
+ u32 res6;
+ u32 mpodtctrl;
+ u32 mprddqby0dl;
+ u32 mprddqby1dl;
+ u32 mprddqby2dl;
+ u32 mprddqby3dl;
+ u32 res7[4];
+ u32 mpdgctrl0;
+ u32 mpdgctrl1;
+ u32 res8;
+ u32 mprddlctl;
+ u32 res9;
+ u32 mpwrdlctl;
+ u32 res10[25];
+ u32 mpmur0;
+};
+
+/*
+ * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
+ */
+#define MX6DQ_IOM_DDR_BASE 0x020e0500
+struct mx6dq_iomux_ddr_regs {
+ u32 res1[3];
+ u32 dram_sdqs5;
+ u32 dram_dqm5;
+ u32 dram_dqm4;
+ u32 dram_sdqs4;
+ u32 dram_sdqs3;
+ u32 dram_dqm3;
+ u32 dram_sdqs2;
+ u32 dram_dqm2;
+ u32 res2[16];
+ u32 dram_cas;
+ u32 res3[2];
+ u32 dram_ras;
+ u32 dram_reset;
+ u32 res4[2];
+ u32 dram_sdclk_0;
+ u32 dram_sdba2;
+ u32 dram_sdcke0;
+ u32 dram_sdclk_1;
+ u32 dram_sdcke1;
+ u32 dram_sdodt0;
+ u32 dram_sdodt1;
+ u32 res5;
+ u32 dram_sdqs0;
+ u32 dram_dqm0;
+ u32 dram_sdqs1;
+ u32 dram_dqm1;
+ u32 dram_sdqs6;
+ u32 dram_dqm6;
+ u32 dram_sdqs7;
+ u32 dram_dqm7;
+};
+
+#define MX6DQ_IOM_GRP_BASE 0x020e0700
+struct mx6dq_iomux_grp_regs {
+ u32 res1[18];
+ u32 grp_b7ds;
+ u32 grp_addds;
+ u32 grp_ddrmode_ctl;
+ u32 res2;
+ u32 grp_ddrpke;
+ u32 res3[6];
+ u32 grp_ddrmode;
+ u32 res4[3];
+ u32 grp_b0ds;
+ u32 grp_b1ds;
+ u32 grp_ctlds;
+ u32 res5;
+ u32 grp_b2ds;
+ u32 grp_ddr_type;
+ u32 grp_b3ds;
+ u32 grp_b4ds;
+ u32 grp_b5ds;
+ u32 grp_b6ds;
+};
+
+#define MX6SDL_IOM_DDR_BASE 0x020e0400
+struct mx6sdl_iomux_ddr_regs {
+ u32 res1[25];
+ u32 dram_cas;
+ u32 res2[2];
+ u32 dram_dqm0;
+ u32 dram_dqm1;
+ u32 dram_dqm2;
+ u32 dram_dqm3;
+ u32 dram_dqm4;
+ u32 dram_dqm5;
+ u32 dram_dqm6;
+ u32 dram_dqm7;
+ u32 dram_ras;
+ u32 dram_reset;
+ u32 res3[2];
+ u32 dram_sdba2;
+ u32 dram_sdcke0;
+ u32 dram_sdcke1;
+ u32 dram_sdclk_0;
+ u32 dram_sdclk_1;
+ u32 dram_sdodt0;
+ u32 dram_sdodt1;
+ u32 dram_sdqs0;
+ u32 dram_sdqs1;
+ u32 dram_sdqs2;
+ u32 dram_sdqs3;
+ u32 dram_sdqs4;
+ u32 dram_sdqs5;
+ u32 dram_sdqs6;
+ u32 dram_sdqs7;
+};
+
+#define MX6SDL_IOM_GRP_BASE 0x020e0700
+struct mx6sdl_iomux_grp_regs {
+ u32 res1[18];
+ u32 grp_b7ds;
+ u32 grp_addds;
+ u32 grp_ddrmode_ctl;
+ u32 grp_ddrpke;
+ u32 res2[2];
+ u32 grp_ddrmode;
+ u32 grp_b0ds;
+ u32 res3;
+ u32 grp_ctlds;
+ u32 grp_b1ds;
+ u32 grp_ddr_type;
+ u32 grp_b2ds;
+ u32 grp_b3ds;
+ u32 grp_b4ds;
+ u32 grp_b5ds;
+ u32 res4;
+ u32 grp_b6ds;
+};
+
+/* Device Information: Varies per DDR3 part number and speed grade */
+struct mx6_ddr3_cfg {
+ u16 mem_speed; /* ie 1600 for DDR3-1600 (800,1066,1333,1600) */
+ u8 density; /* chip density (Gb) (1,2,4,8) */
+ u8 width; /* bus width (bits) (4,8,16) */
+ u8 banks; /* number of banks */
+ u8 rowaddr; /* row address bits (11-16)*/
+ u8 coladdr; /* col address bits (9-12) */
+ u8 pagesz; /* page size (K) (1-2) */
+ u16 trcd; /* tRCD=tRP=CL (ns*100) */
+ u16 trcmin; /* tRC min (ns*100) */
+ u16 trasmin; /* tRAS min (ns*100) */
+ u8 SRT; /* self-refresh temperature: 0=normal, 1=extended */
+};
+
+/* System Information: Varies per board design, layout, and term choices */
+struct mx6_ddr_sysinfo {
+ u8 dsize; /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */
+ u8 cs_density; /* density per chip select (Gb) */
+ u8 ncs; /* number chip selects used (1|2) */
+ char cs1_mirror;/* enable address mirror (0|1) */
+ char bi_on; /* Bank interleaving enable */
+ u8 rtt_nom; /* Rtt_Nom (DDR3_RTT_*) */
+ u8 rtt_wr; /* Rtt_Wr (DDR3_RTT_*) */
+ u8 ralat; /* Read Additional Latency (0-7) */
+ u8 walat; /* Write Additional Latency (0-3) */
+ u8 mif3_mode; /* Command prediction working mode */
+ u8 rst_to_cke; /* Time from SDE enable to CKE rise */
+ u8 sde_to_rst; /* Time from SDE enable until DDR reset# is high */
+};
+
+/*
+ * Board specific calibration:
+ * This includes write leveling calibration values as well as DQS gating
+ * and read/write delays. These values are board/layout/device specific.
+ * Freescale recommends using the i.MX6 DDR Stress Test Tool V1.0.2
+ * (DOC-96412) to determine these values over a range of boards and
+ * temperatures.
+ */
+struct mx6_mmdc_calibration {
+ /* write leveling calibration */
+ u32 p0_mpwldectrl0;
+ u32 p0_mpwldectrl1;
+ u32 p1_mpwldectrl0;
+ u32 p1_mpwldectrl1;
+ /* read DQS gating */
+ u32 p0_mpdgctrl0;
+ u32 p0_mpdgctrl1;
+ u32 p1_mpdgctrl0;
+ u32 p1_mpdgctrl1;
+ /* read delay */
+ u32 p0_mprddlctl;
+ u32 p1_mprddlctl;
+ /* write delay */
+ u32 p0_mpwrdlctl;
+ u32 p1_mpwrdlctl;
+};
+
+/* configure iomux (pinctl/padctl) */
+void mx6dq_dram_iocfg(unsigned width,
+ const struct mx6dq_iomux_ddr_regs *,
+ const struct mx6dq_iomux_grp_regs *);
+void mx6sdl_dram_iocfg(unsigned width,
+ const struct mx6sdl_iomux_ddr_regs *,
+ const struct mx6sdl_iomux_grp_regs *);
+
+/* configure mx6 mmdc registers */
+void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
+ const struct mx6_mmdc_calibration *,
+ const struct mx6_ddr3_cfg *);
+
+#endif /* CONFIG_SPL_BUILD */
#define MX6_MMDC_P0_MDCTL 0x021b0000
#define MX6_MMDC_P0_MDPDC 0x021b0004
#include <asm/imx-common/regs-common.h>
#include "../arch-imx/cpu.h"
-#define is_soc_rev(rev) ((get_cpu_rev() & 0xFF) - rev)
+#define soc_rev() (get_cpu_rev() & 0xFF)
+#define is_soc_rev(rev) (soc_rev() - rev)
+
u32 get_cpu_rev(void);
/* returns MXC_CPU_ value */
+++ /dev/null
-/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef _ASM_ARCH_SPL_H_
-#define _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_RAM 1
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2010-2013
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef _ASM_ARCH_SPL_H_
-#define _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_RAM 1
-
-#endif /* _ASM_ARCH_SPL_H_ */
+++ /dev/null
-/*
- * (C) Copyright 2012
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _ASM_ARCH_SPL_H_
-#define _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_RAM 1
-
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2012
- * NVIDIA Corporation <www.nvidia.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef _ASM_ARCH_SPL_H_
-#define _ASM_ARCH_SPL_H_
-
-#define BOOT_DEVICE_RAM 1
-
-#endif
#define ATOMIC_INIT(i) { (i) }
#ifdef __KERNEL__
-#include <asm/proc/system.h>
+#include <asm/proc-armv/system.h>
#define atomic_read(v) ((v)->counter)
#define atomic_set(v,i) (((v)->counter) = (i))
#ifdef __KERNEL__
-#include <asm/proc/system.h>
+#include <asm/proc-armv/system.h>
#define smp_mb__before_clear_bit() do { } while (0)
#define smp_mb__after_clear_bit() do { } while (0)
void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list,
unsigned count);
+/* macros for declaring and using pinmux array */
+#if defined(CONFIG_MX6QDL)
+#define IOMUX_PADS(x) (MX6Q_##x), (MX6DL_##x)
+#define SETUP_IOMUX_PAD(def) \
+if (is_cpu_type(MXC_CPU_MX6Q)) { \
+ imx_iomux_v3_setup_pad(MX6Q_##def); \
+} else { \
+ imx_iomux_v3_setup_pad(MX6DL_##def); \
+}
+#define SETUP_IOMUX_PADS(x) \
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x)/2)
+#elif defined(CONFIG_MX6Q) || defined(CONFIG_MX6D)
+#define IOMUX_PADS(x) MX6Q_##x
+#define SETUP_IOMUX_PAD(def) \
+ imx_iomux_v3_setup_pad(MX6Q_##def);
+#define SETUP_IOMUX_PADS(x) \
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#else
+#define IOMUX_PADS(x) MX6DL_##x
+#define SETUP_IOMUX_PAD(def) \
+ imx_iomux_v3_setup_pad(MX6DL_##def);
+#define SETUP_IOMUX_PADS(x) \
+ imx_iomux_v3_setup_multiple_pads(x, ARRAY_SIZE(x))
+#endif
+
#endif /* __MACH_IOMUX_V3_H__*/
#endif /* __mem_isa */
#endif /* __KERNEL__ */
+
+#include <iotrace.h>
+
#endif /* __ASM_ARM_IO_H */
#ifndef __ASM_PROC_PROCESSOR_H
#define __ASM_PROC_PROCESSOR_H
-#include <asm/proc/domain.h>
+#include <asm/proc-armv/domain.h>
#define KERNEL_STACK_SIZE PAGE_SIZE
#if 0 /* XXX###XXX */
#include <asm/arch/memory.h>
#endif /* XXX###XXX */
-#include <asm/proc/processor.h>
+#include <asm/proc-armv/processor.h>
#include <asm/types.h>
union debug_insn {
/* options set using PTRACE_SETOPTIONS */
#define PTRACE_O_TRACESYSGOOD 0x00000001
-#include <asm/proc/ptrace.h>
+#include <asm/proc-armv/ptrace.h>
#ifndef __ASSEMBLY__
#define pc_pointer(v) \
#ifndef _ASM_SPL_H_
#define _ASM_SPL_H_
+#if defined(CONFIG_OMAP) || defined(CONFIG_SOCFPGA) || defined(CONFIG_ZYNQ) \
+ || defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5) \
+ || defined(CONFIG_EXYNOS4210)
/* Platform-specific defines */
#include <asm/arch/spl.h>
+#else
+enum {
+ BOOT_DEVICE_RAM,
+ BOOT_DEVICE_MMC1,
+ BOOT_DEVICE_MMC2,
+ BOOT_DEVICE_MMC2_2,
+ BOOT_DEVICE_NAND,
+ BOOT_DEVICE_ONENAND,
+ BOOT_DEVICE_NOR,
+ BOOT_DEVICE_UART,
+ BOOT_DEVICE_SPI,
+ BOOT_DEVICE_SATA,
+ BOOT_DEVICE_I2C,
+ BOOT_DEVICE_NONE
+};
+#endif
+
/* Linker symbols. */
extern char __bss_start[], __bss_end[];
gd->mon_len = (ulong)&__bss_end - (ulong)_start;
#ifdef CONFIG_OF_EMBED
/* Get a pointer to the FDT */
- gd->fdt_blob = __dtb_db_begin;
+ gd->fdt_blob = __dtb_dt_begin;
#elif defined CONFIG_OF_SEPARATE
/* FDT is at end of image */
gd->fdt_blob = &_end;
sync_write_buffer();
}
-void dcache_invalidate_range(volatile void *start, size_t size)
+void invalidate_dcache_range(unsigned long start, unsigned long stop)
{
- unsigned long v, begin, end, linesz;
+ unsigned long v, linesz;
linesz = CONFIG_SYS_DCACHE_LINESZ;
/* You asked for it, you got it */
- begin = (unsigned long)start & ~(linesz - 1);
- end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
+ start = start & ~(linesz - 1);
+ stop = (stop + linesz - 1) & ~(linesz - 1);
- for (v = begin; v < end; v += linesz)
+ for (v = start; v < stop; v += linesz)
dcache_invalidate_line((void *)v);
}
-void dcache_flush_range(volatile void *start, size_t size)
+void flush_dcache_range(unsigned long start, unsigned long stop)
{
- unsigned long v, begin, end, linesz;
+ unsigned long v, linesz;
linesz = CONFIG_SYS_DCACHE_LINESZ;
/* You asked for it, you got it */
- begin = (unsigned long)start & ~(linesz - 1);
- end = ((unsigned long)start + size + linesz - 1) & ~(linesz - 1);
+ start = start & ~(linesz - 1);
+ stop = (stop + linesz - 1) & ~(linesz - 1);
- for (v = begin; v < end; v += linesz)
+ for (v = start; v < stop; v += linesz)
dcache_flush_line((void *)v);
sync_write_buffer();
* Applies the above functions on all lines that are touched by the
* specified virtual address range.
*/
-void dcache_invalidate_range(volatile void *start, size_t len);
void dcache_clean_range(volatile void *start, size_t len);
-void dcache_flush_range(volatile void *start, size_t len);
void icache_invalidate_range(volatile void *start, size_t len);
static inline void dcache_flush_unlocked(void)
switch (dir) {
case DMA_BIDIRECTIONAL:
- dcache_flush_range(vaddr, len);
+ flush_dcache_range((unsigned long)vaddr,
+ (unsigned long)vaddr + len);
break;
case DMA_TO_DEVICE:
dcache_clean_range(vaddr, len);
break;
case DMA_FROM_DEVICE:
- dcache_invalidate_range(vaddr, len);
+ invalidate_dcache_range((unsigned long)vaddr,
+ (unsigned long)vaddr + len);
break;
default:
/* This will cause a linker error */
printf("DMA: Using memory from 0x%08lx to 0x%08lx\n",
dma_alloc_start, dma_alloc_end);
- dcache_invalidate_range(cached(dma_alloc_start),
- dma_alloc_end - dma_alloc_start);
+ invalidate_dcache_range((unsigned long)cached(dma_alloc_start),
+ dma_alloc_end);
}
void *dma_alloc_coherent(size_t len, unsigned long *handle)
scm2_t *scm2 = (scm2_t *) MMAP_SCM2;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
+#ifndef CONFIG_WATCHDOG
wdog_t *wdog = (wdog_t *) MMAP_WDOG;
/* watchdog is enabled by default - disable the watchdog */
-#ifndef CONFIG_WATCHDOG
out_be16(&wdog->cr, 0);
#endif
int fecpin_setclear(struct eth_device *dev, int setclear)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
+#ifdef CONFIG_MCF5445x
struct fec_info_s *info = (struct fec_info_s *)dev->priv;
-#ifdef CONFIG_MCF5445x
if (setclear) {
#ifdef CONFIG_SYS_FEC_NO_SHARED_PHY
if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
#define writew(b,addr) ((*(volatile u16 *) (addr)) = (b))
#define writel(b,addr) ((*(volatile u32 *) (addr)) = (b))
#else
-#define readw(addr) in_le16((volatile u16 *)(addr))
-#define readl(addr) in_le32((volatile u32 *)(addr))
-#define writew(b,addr) out_le16((volatile u16 *)(addr),(b))
-#define writel(b,addr) out_le32((volatile u32 *)(addr),(b))
+#define readw(addr) in_be16((volatile u16 *)(addr))
+#define readl(addr) in_be32((volatile u32 *)(addr))
+#define writew(b,addr) out_be16((volatile u16 *)(addr),(b))
+#define writel(b,addr) out_be32((volatile u32 *)(addr),(b))
#endif
/*
typedef int __kernel_pid_t;
typedef unsigned int __kernel_uid_t;
typedef unsigned int __kernel_gid_t;
-typedef unsigned int __kernel_size_t;
+typedef unsigned long __kernel_size_t;
typedef int __kernel_ssize_t;
typedef long __kernel_ptrdiff_t;
typedef long __kernel_time_t;
#endif
#include <net.h>
#include <serial.h>
-#if defined(CONFIG_CMD_BEDBUG)
-#include <cmd_bedbug.h>
-#endif
#ifdef CONFIG_SYS_ALLOC_DPRAM
#include <commproc.h>
#endif
last_stage_init ();
#endif
-#if defined(CONFIG_CMD_BEDBUG)
- WATCHDOG_RESET ();
- bedbug_init ();
-#endif
-
#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER)
/*
* Export available size of memory for Linux,
}
#endif
-#ifdef CONFIG_MODEM_SUPPORT
- {
- extern int do_mdm_init;
- do_mdm_init = gd->do_mdm_init;
- }
-#endif
-
#ifdef CONFIG_WATCHDOG
/* disable watchdog if environment is set */
if ((s = getenv ("watchdog")) != NULL) {
int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *images)
{
- ulong rd_len;
- ulong initrd_start, initrd_end;
int ret;
-
- ulong cmd_start, cmd_end;
bd_t *kbd;
void (*kernel) (bd_t *, ulong, ulong, ulong, ulong);
struct lmb *lmb = &images->lmb;
* sp+16: Start of command line string
* sp+20: End of command line string
*/
- (*kernel) (kbd, initrd_start, initrd_end, cmd_start, cmd_end);
+ (*kernel)(kbd, images->initrd_start, images->initrd_end,
+ images->cmdline_start, images->cmdline_end);
/* does not return */
error:
return 1;
--- /dev/null
+../../../../include/dt-bindings
\ No newline at end of file
/* fixup the initrd now that we know where it should be */
if (images->rd_start && images->rd_end && of_flat_tree)
ret = fdt_initrd(of_flat_tree, images->rd_start,
- images->rd_end, 1);
+ images->rd_end);
if (ret)
return 1;
/*
* (C) Copyright 2011, Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
* (C) Copyright 2011, Julius Baxter <julius@opencores.org>
+ * (C) Copyright 2014, Franck Jullien <franck.jullien@gmail.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
l.ori r3,r0,SPR_SR_SM
l.mtspr r0,r3,SPR_SR
+ l.jal _cur
+ l.nop
+_cur:
+ l.ori r8, r9, 0 /* Get _cur current address */
+
+ l.movhi r3, hi(_cur)
+ l.ori r3, r3, lo(_cur)
+ l.sfeq r8, r3 /* If we are running at the linked address */
+ l.bf _no_vector_reloc /* there is not need for relocation */
+ l.sub r8, r8, r3
+
+ l.mfspr r4, r0, SPR_CPUCFGR
+ l.andi r4, r4, SPR_CPUCFGR_EVBARP /* Exception Vector Base Address Register present ? */
+ l.sfnei r4,0
+ l.bnf _reloc_vectors
+ l.movhi r5, 0 /* Destination */
+
+ l.mfspr r4, r0, SPR_EVBAR
+ l.add r5, r5, r4
+
+_reloc_vectors:
+ /* Relocate vectors*/
+ l.movhi r5, 0 /* Destination */
+ l.movhi r6, hi(__start) /* Length */
+ l.ori r6, r6, lo(__start)
+ l.ori r3, r8, 0
+
+.L_relocvectors:
+ l.lwz r7, 0(r3)
+ l.sw 0(r5), r7
+ l.addi r5, r5, 4
+ l.sfeq r5, r6
+ l.bnf .L_relocvectors
+ l.addi r3, r3, 4
+
+_no_vector_reloc:
+
/* Relocate u-boot */
- l.movhi r3,hi(__start) /* source start address */
+ l.movhi r3,hi(__start) /* source start offset */
l.ori r3,r3,lo(__start)
+ l.add r3,r8,r3
+
l.movhi r4,hi(_stext) /* dest start address */
l.ori r4,r4,lo(_stext)
l.movhi r5,hi(__end) /* dest end address */
l.bf .L_reloc
l.addi r4,r4,4 /* delay slot */
-#ifdef CONFIG_SYS_RELOCATE_VECTORS
- /* Relocate vectors from 0xf0000000 to 0x00000000 */
- l.movhi r4, 0xf000 /* source */
- l.movhi r5, 0 /* destination */
- l.addi r6, r5, CONFIG_SYS_VECTORS_LEN /* length */
-.L_relocvectors:
- l.lwz r7, 0(r4)
- l.sw 0(r5), r7
- l.addi r5, r5, 4
- l.sfeq r5,r6
- l.bnf .L_relocvectors
- l.addi r4,r4, 4
-#endif
l.movhi r4,hi(_start)
l.ori r4,r4,lo(_start)
l.jr r4
#define SPR_ICCFGR (SPRGROUP_SYS + 6)
#define SPR_DCFGR (SPRGROUP_SYS + 7)
#define SPR_PCCFGR (SPRGROUP_SYS + 8)
+#define SPR_VR2 (SPRGROUP_SYS + 9)
+#define SPR_AVR (SPRGROUP_SYS + 10)
+#define SPR_EVBAR (SPRGROUP_SYS + 11)
+#define SPR_AECR (SPRGROUP_SYS + 12)
+#define SPR_AESR (SPRGROUP_SYS + 13)
#define SPR_NPC (SPRGROUP_SYS + 16)
#define SPR_SR (SPRGROUP_SYS + 17)
#define SPR_PPC (SPRGROUP_SYS + 18)
#define SPR_CPUCFGR_OF32S 0x00000080 /* ORFPX32 supported */
#define SPR_CPUCFGR_OF64S 0x00000100 /* ORFPX64 supported */
#define SPR_CPUCFGR_OV64S 0x00000200 /* ORVDX64 supported */
-#define SPR_CPUCFGR_RES 0xfffffc00 /* Reserved */
+#define SPR_CPUCFGR_ND 0x00000400 /* No delay slot */
+#define SPR_CPUCFGR_AVRP 0x00000800 /* Arch. Version Register present */
+#define SPR_CPUCFGR_EVBARP 0x00001000 /* Exception Vector Base Address Register (EVBAR) present */
+#define SPR_CPUCFGR_ISRP 0x00002000 /* Implementation-Specific Registers (ISR0-7) present */
+#define SPR_CPUCFGR_AECSRP 0x00004000 /* Arithmetic Exception Control Register (AECR) and */
+ /* Arithmetic Exception Status Register (AESR) presents */
+#define SPR_CPUCFGR_RES 0xffffc000 /* Reserved */
/*
* Bit definitions for the Debug configuration register and other
immap->im_siu_conf.sc_siumcr =
(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
| SIUMCR_LBPC01;
-#elif defined(CONFIG_ADSTYPE) && CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
-/* nothing to do for this board here */
#elif defined CONFIG_MPC8272
immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr &
~SIUMCR_BBD &
.globl _start
_start:
-#if defined(CONFIG_MPC8260ADS) && defined(CONFIG_SYS_DEFAULT_IMMR)
- lis r3, CONFIG_SYS_DEFAULT_IMMR@h
- nop
- lwz r4, 0(r3)
- nop
- rlwinm r4, r4, 0, 8, 5
- nop
- oris r4, r4, 0x0200
- nop
- stw r4, 0(r3)
- nop
-#endif /* CONFIG_MPC8260ADS && CONFIG_SYS_DEFAULT_IMMR */
-
mfmsr r5 /* save msr contents */
#if defined(CONFIG_COGENT)
if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
puts("Work-around for Erratum NMG ETSEC129 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004508
+ puts("Work-around for Erratum A004508 enabled\n");
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
puts("Work-around for Erratum A004510 enabled\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
puts("Work-around for Erratum USB14 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+ puts("Work-around for Erratum A007186 enabled\n");
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
puts("Work-around for Erratum A006593 enabled\n");
#endif
}
#endif
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+#ifdef CONFIG_POST
+#error POST memory test cannot be enabled with TDM
+#endif
+static void enable_tdm_law(void)
+{
+ int ret;
+ char buffer[HWCONFIG_BUFFER_SIZE] = {0};
+ int tdm_hwconfig_enabled = 0;
+
+ /*
+ * Extract hwconfig from environment since environment
+ * is not setup properly yet. Search for tdm entry in
+ * hwconfig.
+ */
+ ret = getenv_f("hwconfig", buffer, sizeof(buffer));
+ if (ret > 0) {
+ tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
+ /* If tdm is defined in hwconfig, set law for tdm workaround */
+ if (tdm_hwconfig_enabled)
+ set_next_law(T1040_TDM_QUIRK_CCSR_BASE, LAW_SIZE_16M,
+ LAW_TRGT_IF_CCSR);
+ }
+}
+#endif
+
static void enable_cpc(void)
{
int i;
disable_cpc_sram();
#endif
enable_cpc();
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+ enable_tdm_law();
+#endif
#ifndef CONFIG_SYS_FSL_NO_SERDES
/* needs to be in ram since code uses global static vars */
#include <linux/ctype.h>
#include <asm/io.h>
#include <asm/fsl_portals.h>
+#include <hwconfig.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif
u32 bootpg = determine_mp_bootpg(NULL);
u32 id = get_my_id();
const char *enable_method;
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+ int ret;
+ int tdm_hwconfig_enabled = 0;
+ char buffer[HWCONFIG_BUFFER_SIZE] = {0};
+#endif
off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
while (off != -FDT_ERR_NOTFOUND) {
"device_type", "cpu", 4);
}
+#if defined(T1040_TDM_QUIRK_CCSR_BASE)
+#define CONFIG_MEM_HOLE_16M 0x1000000
+ /*
+ * Extract hwconfig from environment.
+ * Search for tdm entry in hwconfig.
+ */
+ ret = getenv_f("hwconfig", buffer, sizeof(buffer));
+ if (ret > 0)
+ tdm_hwconfig_enabled = hwconfig_f("tdm", buffer);
+
+ /* Reserve the memory hole created by TDM LAW, so OSes dont use it */
+ if (tdm_hwconfig_enabled) {
+ off = fdt_add_mem_rsv(blob, T1040_TDM_QUIRK_CCSR_BASE,
+ CONFIG_MEM_HOLE_16M);
+ if (off < 0)
+ printf("Failed to reserve memory for tdm: %s\n",
+ fdt_strerror(off));
+ }
+#endif
+
/* Reserve the boot page so OSes dont use it */
if ((u64)bootpg < memory_limit) {
off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
return -ENODEV;
}
+#define BC3_SHIFT 9
+#define DC3_SHIFT 6
+#define FC3_SHIFT 0
+#define BC2_SHIFT 19
+#define DC2_SHIFT 16
+#define FC2_SHIFT 10
+#define BC1_SHIFT 29
+#define DC1_SHIFT 26
+#define FC1_SHIFT 20
+#define BC_MASK 0x1
+#define DC_MASK 0x7
+#define FC_MASK 0x3F
+
+#define FUSE_VAL_MASK 0x00000003
+#define FUSE_VAL_SHIFT 30
+#define CR0_DCBIAS_SHIFT 5
+#define CR1_FCAP_SHIFT 15
+#define CR1_BCAP_SHIFT 29
+#define FCAP_MASK 0x001F8000
+#define BCAP_MASK 0x20000000
+#define BCAP_OVD_MASK 0x10000000
+#define BYP_CAL_MASK 0x02000000
+
u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
{
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u64 serdes_prtcl_map = 0;
u32 cfg;
int lane;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+ struct ccsr_sfp_regs __iomem *sfp_regs =
+ (struct ccsr_sfp_regs __iomem *)(CONFIG_SYS_SFP_ADDR);
+ u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1;
+ u32 bc_status, fc_status, dc_status, pll_sr2;
+ serdes_corenet_t __iomem *srds_regs = (void *)sd_addr;
+ u32 sfp_spfr0, sel;
+#endif
cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
/* Is serdes enabled at all? */
return 0;
}
+/* Erratum A-007186
+ * Freescale Scratch Pad Fuse Register n (SFP_FSPFR0)
+ * The workaround requires factory pre-set SerDes calibration values to be
+ * read from a fuse block(Freescale Scratch Pad Fuse Register SFP_FSPFR0)
+ * These values have been shown to work across the
+ * entire temperature range for all SerDes. These values are then written into
+ * the SerDes registers to calibrate the SerDes PLL.
+ *
+ * This workaround for the protocols and rates that only have the Ring VCO.
+ */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+ sfp_spfr0 = in_be32(&sfp_regs->fsl_spfr0);
+ debug("A007186: sfp_spfr0= %x\n", sfp_spfr0);
+
+ sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK;
+
+ if (sel == 0x01 || sel == 0x02) {
+ for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) {
+ pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
+ debug("A007186: pll_num=%x pllcr0=%x\n",
+ pll_num, pll_status);
+ /* STEP 1 */
+ /* Read factory pre-set SerDes calibration values
+ * from fuse block(SFP scratch register-sfp_spfr0)
+ */
+ switch (pll_status & SRDS_PLLCR0_FRATE_SEL_MASK) {
+ case SRDS_PLLCR0_FRATE_SEL_3_0:
+ case SRDS_PLLCR0_FRATE_SEL_3_072:
+ debug("A007186: 3.0/3.072 protocol rate\n");
+ bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
+ dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
+ fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
+ break;
+ case SRDS_PLLCR0_FRATE_SEL_3_125:
+ debug("A007186: 3.125 protocol rate\n");
+ bc = (sfp_spfr0 >> BC2_SHIFT) & BC_MASK;
+ dc = (sfp_spfr0 >> DC2_SHIFT) & DC_MASK;
+ fc = (sfp_spfr0 >> FC2_SHIFT) & FC_MASK;
+ break;
+ case SRDS_PLLCR0_FRATE_SEL_3_75:
+ debug("A007186: 3.75 protocol rate\n");
+ bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
+ dc = (sfp_spfr0 >> DC1_SHIFT) & DC_MASK;
+ fc = (sfp_spfr0 >> FC1_SHIFT) & FC_MASK;
+ break;
+ default:
+ continue;
+ }
+
+ /* STEP 2 */
+ /* Write SRDSxPLLnCR1[11:16] = FC
+ * Write SRDSxPLLnCR1[2] = BC
+ */
+ pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
+ pll_cr_upd = (((bc << CR1_BCAP_SHIFT) & BCAP_MASK) |
+ ((fc << CR1_FCAP_SHIFT) & FCAP_MASK));
+ out_be32(&srds_regs->bank[pll_num].pllcr1,
+ (pll_cr_upd | pll_cr1));
+ debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
+ pll_num, (pll_cr_upd | pll_cr1));
+ /* Write SRDSxPLLnCR0[24:26] = DC
+ */
+ pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
+ out_be32(&srds_regs->bank[pll_num].pllcr0,
+ pll_cr0 | (dc << CR0_DCBIAS_SHIFT));
+ debug("A007186: pll_num=%x, Updated PLLCR0=%x\n",
+ pll_num, (pll_cr0 | (dc << CR0_DCBIAS_SHIFT)));
+ /* Write SRDSxPLLnCR1[3] = 1
+ * Write SRDSxPLLnCR1[6] = 1
+ */
+ pll_cr1 = in_be32(&srds_regs->bank[pll_num].pllcr1);
+ pll_cr_upd = (BCAP_OVD_MASK | BYP_CAL_MASK);
+ out_be32(&srds_regs->bank[pll_num].pllcr1,
+ (pll_cr_upd | pll_cr1));
+ debug("A007186: pll_num=%x Updated PLLCR1=%x\n",
+ pll_num, (pll_cr_upd | pll_cr1));
+
+ /* STEP 3 */
+ /* Read the status Registers */
+ /* Verify SRDSxPLLnSR2[8] = BC */
+ pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
+ debug("A007186: pll_num=%x pllsr2=%x\n",
+ pll_num, pll_sr2);
+ bc_status = (pll_sr2 >> 23) & BC_MASK;
+ if (bc_status != bc)
+ debug("BC mismatch\n");
+ fc_status = (pll_sr2 >> 16) & FC_MASK;
+ if (fc_status != fc)
+ debug("FC mismatch\n");
+ pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
+ out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 |
+ 0x02000000);
+ pll_sr2 = in_be32(&srds_regs->bank[pll_num].pllsr2);
+ dc_status = (pll_sr2 >> 17) & DC_MASK;
+ if (dc_status != dc)
+ debug("DC mismatch\n");
+ pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0);
+ out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 &
+ 0xfdffffff);
+
+ /* STEP 4 */
+ /* Wait 750us to verify the PLL is locked
+ * by checking SRDSxPLLnCR0[8] = 1.
+ */
+ udelay(750);
+ pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
+ debug("A007186: pll_num=%x pllcr0=%x\n",
+ pll_num, pll_status);
+
+ if ((pll_status & SRDS_PLLCR0_PLL_LCK) == 0)
+ printf("A007186 Serdes PLL not locked\n");
+ else
+ debug("A007186 Serdes PLL locked\n");
+ }
+ }
+#endif
+
cfg >>= sd_prctl_shift;
printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
if (!is_serdes_prtcl_valid(sd, cfg))
/* SET_NEXUS_LIODN(557), -- not yet implemented */
SET_QE_LIODN(559),
+ SET_TDM_LIODN(560),
};
int liodn_tbl_sz = ARRAY_SIZE(liodn_tbl);
{0x6C, {XFI_FM1_MAC9, XFI_FM1_MAC10,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
PCIE4, PCIE4, PCIE4, PCIE4} },
+ {0x1B, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0x1C, {SGMII_FM1_DTSEC9, SGMII_FM1_DTSEC10,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x50, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+ XAUI_FM1_MAC9, XAUI_FM1_MAC9,
+ PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0x51, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
XAUI_FM1_MAC9, XAUI_FM1_MAC9,
PCIE4, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x5E, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0x5F, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
PCIE4, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x64, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
+ PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0x65, {HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
PCIE4, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0x6A, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+ XFI_FM1_MAC1, XFI_FM1_MAC2,
+ PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0x6B, {XFI_FM1_MAC9, XFI_FM1_MAC10,
XFI_FM1_MAC1, XFI_FM1_MAC2,
PCIE4, SGMII_FM1_DTSEC4,
{0xD9, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
+ {0xD2, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
+ SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
+ SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0xD3, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
{0x66, {XFI_FM1_MAC9, XFI_FM1_MAC10,
XFI_FM1_MAC1, XFI_FM1_MAC2,
PCIE4, PCIE4, PCIE4, PCIE4} },
-
-#if defined(CONFIG_PPC_T2081)
{0xAA, {PCIE3, PCIE3, PCIE3, PCIE3,
PCIE4, PCIE4, PCIE4, PCIE4} },
{0xCA, {PCIE3, SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC1,
{0x70, {XFI_FM1_MAC9, XFI_FM1_MAC10, SGMII_FM1_DTSEC1,
SGMII_FM1_DTSEC2, PCIE4, SGMII_FM1_DTSEC4,
SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6} },
-#endif
{}
};
{0x29, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
{0x2D, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO1, SRIO1, SRIO1, SRIO1} },
{0x15, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, SATA1, SATA2} },
+ {0x27, {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, SATA1, SATA2} },
{0x18, {PCIE1, PCIE1, PCIE1, PCIE1, AURORA, AURORA, SATA1, SATA2} },
{0x02, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
{0x36, {SRIO2, SRIO2, SRIO2, SRIO2, AURORA, AURORA, SATA1, SATA2} },
HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10}},
+ {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
{28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+ {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
{36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4}},
+ {37, {NONE, NONE, QSGMII_FM1_B, NONE,
+ NONE, NONE, QSGMII_FM1_A, NONE} },
{38, {NONE, NONE, QSGMII_FM1_B, NONE,
NONE, NONE, QSGMII_FM1_A, NONE}},
+ {39, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ NONE, NONE, QSGMII_FM1_A, NONE} },
{40, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
NONE, NONE, QSGMII_FM1_A, NONE}},
+ {45, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ NONE, NONE, QSGMII_FM1_A, NONE} },
{46, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
NONE, NONE, QSGMII_FM1_A, NONE}},
+ {47, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ NONE, NONE, QSGMII_FM1_A, NONE} },
{48, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
NONE, NONE, QSGMII_FM1_A, NONE}},
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC10, HIGIG_FM2_MAC10,
HIGIG_FM2_MAC10, HIGIG_FM2_MAC10}},
+ {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4}},
+ {37, {NONE, NONE, QSGMII_FM2_B, NONE,
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{38, {NONE, NONE, QSGMII_FM2_B, NONE,
NONE, NONE, QSGMII_FM2_A, NONE} },
+ {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
NONE, NONE, QSGMII_FM2_A, NONE} },
+ {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
NONE, NONE, QSGMII_FM2_A, NONE} },
+ {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
NONE, NONE, QSGMII_FM2_A, NONE} },
+ {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
NONE, NONE, QSGMII_FM2_A, NONE} },
+ {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
NONE, NONE, QSGMII_FM2_A, NONE} },
+ {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ NONE, NONE, QSGMII_FM2_A, NONE} },
{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
NONE, NONE, QSGMII_FM2_A, NONE} },
+ {55, {XFI_FM1_MAC9, XFI_FM1_MAC10,
+ XFI_FM2_MAC10, XFI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{56, {XFI_FM1_MAC9, XFI_FM1_MAC10,
XFI_FM2_MAC10, XFI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
};
static const struct serdes_config serdes3_cfg_tbl[] = {
/* SerDes 3 */
+ {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
{2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1}},
+ {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2}},
+ {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1}},
+ {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
{8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE}},
{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN}},
+ {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ PCIE2, PCIE2, PCIE2, PCIE2} },
{12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
PCIE2, PCIE2, PCIE2, PCIE2}},
+ {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ PCIE2, PCIE2, PCIE2, PCIE2} },
{14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
PCIE2, PCIE2, PCIE2, PCIE2}},
+ {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ SRIO1, SRIO1, SRIO1, SRIO1} },
{16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
SRIO1, SRIO1, SRIO1, SRIO1}},
{17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
SRIO1, SRIO1, SRIO1, SRIO1}},
+ {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ SRIO1, SRIO1, SRIO1, SRIO1} },
{19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
SRIO1, SRIO1, SRIO1, SRIO1}},
{20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
};
static const struct serdes_config serdes4_cfg_tbl[] = {
/* SerDes 4 */
+ {1, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3} },
{2, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3, PCIE3}},
+ {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
{4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4}},
+ {5, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
{6, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+ {7, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2} },
{8, {PCIE3, PCIE3, PCIE3, PCIE3, SRIO2, SRIO2, SRIO2, SRIO2}},
+ {9, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
{10, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, SATA1, SATA2} },
+ {11, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
{12, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SATA1, SATA2} },
+ {13, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
{14, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
+ {15, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2} },
{16, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, SRIO2, SRIO2}},
{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
{}
HIGIG_FM1_MAC9, HIGIG_FM1_MAC9,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10,
HIGIG_FM1_MAC10, HIGIG_FM1_MAC10} },
+ {27, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
{28, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
+ {35, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
+ SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
+ SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
{36, {SGMII_FM1_DTSEC5, SGMII_FM1_DTSEC6,
SGMII_FM1_DTSEC10, SGMII_FM1_DTSEC9,
SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4} },
+ {37, {NONE, NONE, QSGMII_FM1_B, NONE,
+ NONE, NONE, QSGMII_FM1_A, NONE} },
{38, {NONE, NONE, QSGMII_FM1_B, NONE,
NONE, NONE, QSGMII_FM1_A, NONE} },
{}
};
static const struct serdes_config serdes2_cfg_tbl[] = {
/* SerDes 2 */
+ {6, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{7, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {12, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{13, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {15, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{16, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {21, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{22, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {24, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{25, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
NONE, NONE} },
+ {27, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{28, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {35, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{36, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
+ {37, {NONE, NONE, QSGMII_FM2_B, NONE,
+ NONE, QSGMII_FM1_A, NONE, NONE} },
{38, {NONE, NONE, QSGMII_FM2_B, NONE,
NONE, QSGMII_FM1_A, NONE, NONE} },
+ {39, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, QSGMII_FM1_A, NONE, NONE} },
{40, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
NONE, QSGMII_FM1_A, NONE, NONE} },
+ {45, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, QSGMII_FM1_A, NONE, NONE} },
{46, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
NONE, QSGMII_FM1_A, NONE, NONE} },
+ {47, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
+ SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
+ NONE, QSGMII_FM1_A, NONE, NONE} },
{48, {SGMII_FM2_DTSEC5, SGMII_FM2_DTSEC6,
SGMII_FM2_DTSEC10, SGMII_FM2_DTSEC9,
NONE, QSGMII_FM1_A, NONE, NONE} },
+ {49, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ XAUI_FM2_MAC9, XAUI_FM2_MAC9,
+ NONE, NONE, NONE, NONE} },
{50, {XAUI_FM2_MAC9, XAUI_FM2_MAC9,
XAUI_FM2_MAC9, XAUI_FM2_MAC9,
NONE, NONE, NONE, NONE} },
+ {51, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ NONE, NONE, NONE, NONE} },
{52, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
NONE, NONE, NONE, NONE} },
+ {53, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
+ NONE, NONE, NONE, NONE} },
{54, {HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
HIGIG_FM2_MAC9, HIGIG_FM2_MAC9,
NONE, NONE, NONE, NONE} },
+ {55, {NONE, XFI_FM1_MAC10,
+ XFI_FM2_MAC10, NONE,
+ SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
+ SGMII_FM2_DTSEC3, SGMII_FM2_DTSEC4} },
{56, {NONE, XFI_FM1_MAC10,
XFI_FM2_MAC10, NONE,
SGMII_FM2_DTSEC1, SGMII_FM2_DTSEC2,
};
static const struct serdes_config serdes3_cfg_tbl[] = {
/* SerDes 3 */
+ {1, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
{2, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1} },
+ {3, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
{4, {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2} },
+ {5, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
{6, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, SRIO1, SRIO1, SRIO1} },
+ {7, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
{8, {PCIE1, PCIE1, PCIE1, PCIE1, SRIO1, NONE, NONE, NONE} },
{9, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
{10, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN} },
+ {11, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ PCIE2, PCIE2, PCIE2, PCIE2} },
{12, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
PCIE2, PCIE2, PCIE2, PCIE2} },
+ {13, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ PCIE2, PCIE2, PCIE2, PCIE2} },
{14, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
PCIE2, PCIE2, PCIE2, PCIE2} },
+ {15, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ SRIO1, SRIO1, SRIO1, SRIO1} },
{16, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
SRIO1, SRIO1, SRIO1, SRIO1} },
{17, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
SRIO1, SRIO1, SRIO1, SRIO1} },
+ {18, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
+ SRIO1, SRIO1, SRIO1, SRIO1} },
{19, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
SRIO1, SRIO1, SRIO1, SRIO1} },
{20, {INTERLAKEN, INTERLAKEN, INTERLAKEN, INTERLAKEN,
};
static const struct serdes_config serdes4_cfg_tbl[] = {
/* SerDes 4 */
+ {3, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
{4, {PCIE3, PCIE3, PCIE3, PCIE3, PCIE4, PCIE4, PCIE4, PCIE4} },
+ {5, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
{6, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
+ {7, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
{8, {SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2, SRIO2} },
+ {9, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
{10, {PCIE3, PCIE3, PCIE3, PCIE3, SATA1, SATA1, SATA2, SATA2} },
+ {11, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
{12, {AURORA, AURORA, AURORA, AURORA, SATA1, SATA1, SATA2, SATA2} },
+ {13, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
{14, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
+ {15, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
{16, {AURORA, AURORA, AURORA, AURORA, SRIO2, SRIO2, SRIO2, SRIO2} },
{18, {AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA, AURORA} },
{}
#if defined(SDR0_PINSTP_SHIFT)
printf (" Bootstrap Option %c - ", bootstrap_char[bootstrap_option()]);
printf ("Boot ROM Location %s", bootstrap_str[bootstrap_option()]);
-#ifdef CONFIG_NAND_U_BOOT
- puts(", booting from NAND");
-#endif /* CONFIG_NAND_U_BOOT */
putc('\n');
#endif /* SDR0_PINSTP_SHIFT */
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_MPC8540)
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_MPC8572)
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_DDR_115
#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_P1010)
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A007075
#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x10
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
/* P1012 is single core version of P1021 */
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
/* P1013 is single core version of P1022 */
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_FSL_SATA_ERRATUM_A001
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_P1014)
#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
+#define CONFIG_SYS_FSL_ERRATUM_A004508
/* P1017 is single core version of P1023 */
#elif defined(CONFIG_P1017)
#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_P1020)
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_FSL_SATA_ERRATUM_A001
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_P1023)
#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_SYS_FSL_ERRATUM_I2C_A004447
#define CONFIG_SYS_FSL_A004447_SVR_REV 0x11
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
/* P1025 is lower end variant of P1021 */
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
/* P2010 is single core version of P2020 */
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#elif defined(CONFIG_P2020)
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
#define CONFIG_SYS_FSL_RMU
#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
+#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
+
#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
#define CONFIG_SYS_FSL_ERRATUM_A005871
#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_ERRATUM_A006379
+#define CONFIG_SYS_FSL_ERRATUM_A007186
#define CONFIG_SYS_FSL_ERRATUM_A006593
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+#define CONFIG_SYS_FSL_SFP_VER_3_0
#define CONFIG_SYS_FSL_PCI_VER_3_X
#elif defined(CONFIG_PPC_B4860) || defined(CONFIG_PPC_B4420)
#define CONFIG_SYS_FSL_ERRATUM_A_004934
#define CONFIG_SYS_FSL_ERRATUM_A005871
#define CONFIG_SYS_FSL_ERRATUM_A006379
+#define CONFIG_SYS_FSL_ERRATUM_A007186
#define CONFIG_SYS_FSL_ERRATUM_A006593
#define CONFIG_SYS_FSL_ERRATUM_A007075
#define CONFIG_SYS_FSL_ERRATUM_A006475
#define CONFIG_SYS_FSL_ERRATUM_A006384
#define CONFIG_SYS_FSL_ERRATUM_A007212
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+#define CONFIG_SYS_FSL_SFP_VER_3_0
#ifdef CONFIG_PPC_B4860
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_SYS_FSL_ERRATUM_A006261
#define CONFIG_SYS_FSL_ERRATUM_A006593
+#define CONFIG_SYS_FSL_ERRATUM_A007186
#define CONFIG_SYS_FSL_ERRATUM_A006379
#define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
+#define CONFIG_SYS_FSL_SFP_VER_3_0
#elif defined(CONFIG_PPC_C29X)
LAW_TRGT_IF_DDR_INTLV_1234 = 0x16,
LAW_TRGT_IF_BMAN = 0x18,
LAW_TRGT_IF_DCSR = 0x1d,
+ LAW_TRGT_IF_CCSR = 0x1e,
LAW_TRGT_IF_LBC = 0x1f,
LAW_TRGT_IF_QMAN = 0x3c,
SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\
CONFIG_SYS_MPC85xx_QE_OFFSET)
+#define SET_TDM_LIODN(liodn) \
+ SET_GUTS_LIODN("fsl,tdm1.0", liodn, tdmliodnr,\
+ CONFIG_SYS_MPC85xx_TDM_OFFSET)
+
#define SET_QMAN_LIODN(liodn) \
SET_LIODN_ENTRY_1("fsl,qman", liodn, offsetof(ccsr_qman_t, liodnr) + \
CONFIG_SYS_FSL_QMAN_OFFSET, \
u32 sata2liodnr; /* SATA 2 LIODN */
u32 sata3liodnr; /* SATA 3 LIODN */
u32 sata4liodnr; /* SATA 4 LIODN */
- u8 res22[24];
+ u8 res22[20];
+ u32 tdmliodnr; /* TDM LIODN */
u32 qeliodnr; /* QE LIODN */
u8 res_57c[4];
u32 dma1liodnr; /* DMA 1 LIODN */
#define SRDS_PLLCR0_RFCK_SEL_150 0x30000000
#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000
#define SRDS_PLLCR0_RFCK_SEL_122_88 0x50000000
+#define SRDS_PLLCR0_PLL_LCK 0x00800000
#define SRDS_PLLCR0_DCBIAS_OUT_EN 0x02000000
#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f0000
#define SRDS_PLLCR0_FRATE_SEL_5 0x00000000
+#define SRDS_PLLCR0_FRATE_SEL_4_9152 0x00030000
#define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000
#define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000
#define SRDS_PLLCR0_FRATE_SEL_4 0x00070000
-#define SRDS_PLLCR0_FRATE_SEL_3_12 0x00090000
-#define SRDS_PLLCR0_FRATE_SEL_3 0x000a0000
+#define SRDS_PLLCR0_FRATE_SEL_3_125 0x00090000
+#define SRDS_PLLCR0_FRATE_SEL_3_0 0x000a0000
+#define SRDS_PLLCR0_FRATE_SEL_3_072 0x000c0000
#define SRDS_PLLCR0_DCBIAS_OVRD 0x000000F0
#define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT 4
u32 pllcr1; /* PLL Control Register 1 */
u8 res_f4[0xf0c];
};
#endif
+#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
+struct ccsr_sfp_regs {
+ u32 ospr; /* 0x200 */
+ u32 reserved0[14];
+ u32 srk_hash[8]; /* 0x23c Super Root Key Hash */
+ u32 oem_uid; /* 0x9c OEM Unique ID */
+ u8 reserved2[0x04];
+ u32 ovpr; /* 0xA4 Intent To Secure */
+ u8 reserved4[0x08];
+ u32 fsl_uid; /* 0xB0 FSL Unique ID */
+ u8 reserved5[0x04];
+ u32 fsl_spfr0; /* Scratch Pad Fuse Register 0 */
+ u32 fsl_spfr1; /* Scratch Pad Fuse Register 1 */
+};
+#endif
#ifdef CONFIG_FSL_CORENET
#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
#define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
+#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
+/* In SFPv3, OSPR register is now at offset 0x200.
+ * * So directly mapping sfp register map to this address */
+#define CONFIG_SYS_OSPR_OFFSET 0x200
+#define CONFIG_SYS_SFP_OFFSET (0xE8000 + CONFIG_SYS_OSPR_OFFSET)
+#else
+#define CONFIG_SYS_SFP_OFFSET 0xE8000
+#endif
#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000
+#define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000
#define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000
#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_PPC_B4860)\
#define CONFIG_SYS_PCIE4_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET)
+#define CONFIG_SYS_SFP_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET)
+
#define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
#define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
#if defined(CONFIG_8xx)
#define _machine _MACH_8xx
#define have_of 0
-#elif defined(CONFIG_OAK)
-#define _machine _MACH_oak
-#define have_of 0
#elif defined(CONFIG_WALNUT)
#define _machine _MACH_walnut
#define have_of 0
-#elif defined(CONFIG_APUS)
-#define _machine _MACH_apus
-#define have_of 0
-#elif defined(CONFIG_GEMINI)
-#define _machine _MACH_gemini
-#define have_of 0
#elif defined(CONFIG_MPC8260)
#define _machine _MACH_8260
#define have_of 0
#elif defined(CONFIG_SANDPOINT)
#define _machine _MACH_sandpoint
-#elif defined(CONFIG_HIDDEN_DRAGON)
-#define _machine _MACH_hidden_dragon
-#define have_of 0
#else
#error "Machine not defined correctly"
#endif
kbd_init();
#endif
-#ifdef CONFIG_MODEM_SUPPORT
- {
- extern int do_mdm_init;
-
- do_mdm_init = gd->do_mdm_init;
- }
-#endif
-
/* Initialization complete - start the monitor */
/* main_loop() can return to retry autoboot, if so just run it again. */
ret = -ENOMEM;
goto done;
}
+ next->next = NULL;
strcpy(next->name, entry.d_name);
switch (entry.d_type) {
case DT_REG:
--- /dev/null
+../../../../include/dt-bindings
\ No newline at end of file
#ifndef __ASM_SANDBOX_BITOPS_H
#define __ASM_SANDBOX_BITOPS_H
+#include <linux/compiler.h>
#include <asm/system.h>
#ifdef __KERNEL__
static inline int test_and_set_bit(int nr, void *addr)
{
- unsigned long flags;
+ unsigned long __always_unused flags;
int out;
local_irq_save(flags);
static inline int test_and_clear_bit(int nr, void *addr)
{
- unsigned long flags;
+ unsigned long __always_unused flags;
int out;
local_irq_save(flags);
* @param gp GPIO number
* @return -1 on error, 0 if GPIO is low, >0 if high
*/
-int sandbox_gpio_get_value(struct device *dev, unsigned int offset);
+int sandbox_gpio_get_value(struct udevice *dev, unsigned int offset);
/**
* Set the simulated value of a GPIO (used only in sandbox test code)
* @param value value to set (0 for low, non-zero for high)
* @return -1 on error, 0 if ok
*/
-int sandbox_gpio_set_value(struct device *dev, unsigned int offset, int value);
+int sandbox_gpio_set_value(struct udevice *dev, unsigned int offset, int value);
/**
* Return the simulated direction of a GPIO (used only in sandbox test code)
* @param gp GPIO number
* @return -1 on error, 0 if GPIO is input, >0 if output
*/
-int sandbox_gpio_get_direction(struct device *dev, unsigned int offset);
+int sandbox_gpio_get_direction(struct udevice *dev, unsigned int offset);
/**
* Set the simulated direction of a GPIO (used only in sandbox test code)
* @param output 0 to set as input, 1 to set as output
* @return -1 on error, 0 if ok
*/
-int sandbox_gpio_set_direction(struct device *dev, unsigned int offset,
+int sandbox_gpio_set_direction(struct udevice *dev, unsigned int offset,
int output);
#endif
/* Map from a pointer to our RAM buffer */
phys_addr_t map_to_sysmem(const void *ptr);
+/* Define nops for sandbox I/O access */
+#define readb(addr) 0
+#define readw(addr) 0
+#define readl(addr) 0
+#define writeb(v, addr)
+#define writew(v, addr)
+#define writel(v, addr)
+
+#include <iotrace.h>
+
#endif
#define __ASM_SANDBOX_SYSTEM_H
/* Define this as nops for sandbox architecture */
-static inline void local_irq_save(unsigned flags __attribute__((unused)))
-{
-}
-
+#define local_irq_save(x)
#define local_irq_enable()
#define local_irq_disable()
#define local_save_flags(x)
PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86)
PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm
PLATFORM_CPPFLAGS += -DREALMODE_BASE=0x7c0
+PLATFORM_CPPFLAGS += -march=i386 -m32
# Support generic board on x86
__HAVE_ARCH_GENERIC_BOARD := y
PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden
-PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions
+PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions -m elf_i386
LDFLAGS_FINAL += --gc-sections -pie
LDFLAGS_FINAL += --wrap=__divdi3 --wrap=__udivdi3
LDFLAGS_FINAL += --wrap=__moddi3 --wrap=__umoddi3
-export NORMAL_LIBGCC = $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
+export NORMAL_LIBGCC = $(shell $(CC) $(PLATFORM_CPPFLAGS) -print-libgcc-file-name)
CONFIG_USE_PRIVATE_LIBGCC := arch/x86/lib
CROSS_COMPILE ?= i386-linux-
-PLATFORM_CPPFLAGS += -DCONFIG_X86 -D__I386__ -march=i386 -Werror
+PLATFORM_CPPFLAGS += -DCONFIG_X86 -D__I386__ -Werror
# DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING!
LDPPFLAGS += -DRESET_SEG_START=0xffff0000
--- /dev/null
+../../../../include/dt-bindings
\ No newline at end of file
/* includes */
-#include"core.h"
-#include"memory.h"
+#include "core.h"
+#include "memory.h"
/* According to PCI REV 2.1 MAX agents allowed on the bus are -21- */
#define PCI_MAX_DEVICES 22
--- /dev/null
+#
+# (C) Copyright 2014 Pierrick Hascoet, Abilis Systems
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += tb100.o
--- /dev/null
+/*
+ * (C) Copyright 2014 Pierrick Hascoet, Abilis Systems
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/io.h>
+
+void reset_cpu(ulong addr)
+{
+#define CRM_SWRESET 0xff101044
+ writel(0x1, (void *)CRM_SWRESET);
+}
+
+int board_eth_init(bd_t *bis)
+{
+ if (designware_initialize(ETH0_BASE_ADDRESS, 0) >= 0)
+ return 1;
+
+ return 0;
+}
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2004 Arabella Software Ltd.
-# Yuli Barcohen <yuli@arabellasw.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := adder.o
+++ /dev/null
-/*
- * Copyright (C) 2004-2005 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * Support for Analogue&Micro Adder boards family.
- * Tested on AdderII and Adder87x.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8xx.h>
-#if defined(CONFIG_OF_LIBFDT)
- #include <libfdt.h>
-#endif
-
-/*
- * SDRAM is single Samsung K4S643232F-T70 chip (8MB)
- * or single Micron MT48LC4M32B2TG-7 chip (16MB).
- * Minimal CPU frequency is 40MHz.
- */
-static uint sdram_table[] = {
- /* Single read (offset 0x00 in UPM RAM) */
- 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
- 0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
-
- /* Burst read (offset 0x08 in UPM RAM) */
- 0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
- 0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
- 0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
- 0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
-
- /* Single write (offset 0x18 in UPM RAM) */
- 0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
- 0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
- /* Burst write (offset 0x20 in UPM RAM) */
- 0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
- 0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
- 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
- /* Refresh (offset 0x30 in UPM RAM) */
- 0x1ff5fc84, 0xfffffc04, 0xfffffc04, 0xfffffc04,
- 0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
- 0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
-
- /* Exception (offset 0x3C in UPM RAM) */
- 0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04
-};
-
-phys_size_t initdram (int board_type)
-{
- long int msize;
- volatile immap_t *immap = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8xx_t *memctl = &immap->im_memctl;
-
- upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
-
- /* Configure SDRAM refresh */
- memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
-
- memctl->memc_mamr = (94 << 24) | CONFIG_SYS_MAMR; /* No refresh */
- udelay(200);
-
- /* Run precharge from location 0x15 */
- memctl->memc_mar = 0x0;
- memctl->memc_mcr = 0x80002115;
- udelay(200);
-
- /* Run 8 refresh cycles */
- memctl->memc_mcr = 0x80002830;
- udelay(200);
-
- /* Run MRS pattern from location 0x16 */
- memctl->memc_mar = 0x88;
- memctl->memc_mcr = 0x80002116;
- udelay(200);
-
- memctl->memc_mamr |= MAMR_PTAE; /* Enable refresh */
- memctl->memc_or1 = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
- memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
-
- msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE);
- memctl->memc_or1 |= ~(msize - 1);
-
- return msize;
-}
-
-int checkboard( void )
-{
- puts("Board: Adder");
-#if defined(CONFIG_MPC885_FAMILY)
- puts("87x\n");
-#elif defined(CONFIG_MPC866_FAMILY)
- puts("II\n");
-#endif
-
- return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-
-}
-#endif
+++ /dev/null
-/*
- * (C) Copyright 2001-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Modified by Yuli Barcohen <yuli@arabellasw.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
- /* Read-only sections, merged into text segment: */
- . = + SIZEOF_HEADERS;
- .text :
- {
- arch/powerpc/cpu/mpc8xx/start.o (.text*)
- arch/powerpc/cpu/mpc8xx/traps.o (.text*)
- *(.text*)
- . = ALIGN(16);
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- /* Read-write section, merged into data segment: */
- . = (. + 0x0FFF) & 0xFFFFF000;
- _erotext = .;
- PROVIDE (erotext = .);
- .reloc :
- {
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- _FIXUP_TABLE_ = .;
- KEEP(*(.fixup))
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
- __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
-
- .data :
- {
- *(.data*)
- *(.sdata*)
- }
- _edata = .;
- PROVIDE (edata = .);
-
- . = .;
-
- . = ALIGN(4);
- .u_boot_list : {
- KEEP(*(SORT(.u_boot_list*)));
- }
-
-
- . = .;
- __start___ex_table = .;
- __ex_table : { *(__ex_table) }
- __stop___ex_table = .;
-
- . = ALIGN(4096);
- __init_begin = .;
- .text.init : { *(.text.init) }
- .data.init : { *(.data.init) }
- . = ALIGN(4096);
- __init_end = .;
-
- __bss_start = .;
- .bss (NOLOAD) :
- {
- *(.bss*)
- *(.sbss*)
- *(COMMON)
- . = ALIGN(4);
- }
- __bss_end = . ;
- PROVIDE (end = .);
-}
-ENTRY(_start)
*/
#include <common.h>
+#include <cli.h>
#include <errno.h>
-#include <hush.h>
#include <linux/mtd/nand.h>
#include <nand.h>
#include <miiphy.h>
sprintf(output, "%s old: %s value: ", name, getenv(name));
memset(cbuf, 0, CONFIG_SYS_CBSIZE);
- readret = readline_into_buffer(output, cbuf, 0);
+ readret = cli_readline_into_buffer(output, cbuf, 0);
if (readret >= 0) {
ret = setenv(name, cbuf);
+++ /dev/null
-/*
- * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
- * Stephan Linz <linz@li-pro.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * common/sevenseg.c
- *
- * NIOS PIO based seven segment led support functions
- */
-
-#include <common.h>
-#include <nios-io.h>
-
-#ifdef CONFIG_SEVENSEG
-
-#define SEVENDEG_MASK_DP ((SEVENSEG_DIGIT_DP << 8) | SEVENSEG_DIGIT_DP)
-
-#ifdef SEVENSEG_WRONLY /* emulate read access */
-#if (SEVENSEG_ACTIVE == 0)
-static unsigned int sevenseg_portval = ~0;
-#else
-static unsigned int sevenseg_portval = 0;
-#endif
-#endif
-
-static int sevenseg_init_done = 0;
-
-static inline void __sevenseg_set_masked (unsigned int mask, int value)
-{
- nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
-
-#ifdef SEVENSEG_WRONLY /* emulate read access */
-
-#if (SEVENSEG_ACTIVE == 0)
- if (value)
- sevenseg_portval &= ~mask;
- else
- sevenseg_portval |= mask;
-#else
- if (value)
- sevenseg_portval |= mask;
- else
- sevenseg_portval &= ~mask;
-#endif
-
- piop->data = sevenseg_portval;
-
-#else /* !SEVENSEG_WRONLY */
-
-#if (SEVENSEG_ACTIVE == 0)
- if (value)
- piop->data &= ~mask;
- else
- piop->data |= mask;
-#else
- if (value)
- piop->data |= mask;
- else
- piop->data &= ~mask;
-#endif
-
-#endif /* SEVENSEG_WRONLY */
-}
-
-static inline void __sevenseg_toggle_masked (unsigned int mask)
-{
- nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE;
-
-#ifdef SEVENSEG_WRONLY /* emulate read access */
-
- sevenseg_portval ^= mask;
- piop->data = sevenseg_portval;
-
-#else /* !SEVENSEG_WRONLY */
-
- piop->data ^= mask;
-
-#endif /* SEVENSEG_WRONLY */
-}
-
-static inline void __sevenseg_set (unsigned int value)
-{
- nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
-
-#ifdef SEVENSEG_WRONLY /* emulate read access */
-
-#if (SEVENSEG_ACTIVE == 0)
- sevenseg_portval = (sevenseg_portval & SEVENDEG_MASK_DP)
- | ((~value) & (~SEVENDEG_MASK_DP));
-#else
- sevenseg_portval = (sevenseg_portval & SEVENDEG_MASK_DP)
- | (value);
-#endif
-
- piop->data = sevenseg_portval;
-
-#else /* !SEVENSEG_WRONLY */
-
-#if (SEVENSEG_ACTIVE == 0)
- piop->data = (piop->data & SEVENDEG_MASK_DP)
- | ((~value) & (~SEVENDEG_MASK_DP));
-#else
- piop->data = (piop->data & SEVENDEG_MASK_DP)
- | (value);
-#endif
-
-#endif /* SEVENSEG_WRONLY */
-}
-
-static inline void __sevenseg_init (void)
-{
- nios_pio_t *piop __attribute__((unused)) = (nios_pio_t*)SEVENSEG_BASE;
-
- __sevenseg_set(0);
-
-#ifndef SEVENSEG_WRONLY /* setup direction */
-
- piop->direction |= mask;
-
-#endif /* SEVENSEG_WRONLY */
-}
-
-
-void sevenseg_set(int value)
-{
- unsigned char digits[] = {
- SEVENSEG_DIGITS_0,
- SEVENSEG_DIGITS_1,
- SEVENSEG_DIGITS_2,
- SEVENSEG_DIGITS_3,
- SEVENSEG_DIGITS_4,
- SEVENSEG_DIGITS_5,
- SEVENSEG_DIGITS_6,
- SEVENSEG_DIGITS_7,
- SEVENSEG_DIGITS_8,
- SEVENSEG_DIGITS_9,
- SEVENSEG_DIGITS_A,
- SEVENSEG_DIGITS_B,
- SEVENSEG_DIGITS_C,
- SEVENSEG_DIGITS_D,
- SEVENSEG_DIGITS_E,
- SEVENSEG_DIGITS_F
- };
-
- if (!sevenseg_init_done) {
- __sevenseg_init();
- sevenseg_init_done++;
- }
-
- switch (value & SEVENSEG_MASK_CTRL) {
-
- case SEVENSEG_RAW:
- __sevenseg_set( (
- (digits[((value & SEVENSEG_MASK_VAL) >> 4)] << 8) |
- digits[((value & SEVENSEG_MASK_VAL) & 0xf)] ) );
- return;
- break; /* paranoia */
-
- case SEVENSEG_OFF:
- __sevenseg_set(0);
- __sevenseg_set_masked(SEVENDEG_MASK_DP, 0);
- return;
- break; /* paranoia */
-
- case SEVENSEG_SET_DPL:
- __sevenseg_set_masked(SEVENSEG_DIGIT_DP, 1);
- return;
- break; /* paranoia */
-
- case SEVENSEG_SET_DPH:
- __sevenseg_set_masked((SEVENSEG_DIGIT_DP << 8), 1);
- return;
- break; /* paranoia */
-
- case SEVENSEG_RES_DPL:
- __sevenseg_set_masked(SEVENSEG_DIGIT_DP, 0);
- return;
- break; /* paranoia */
-
- case SEVENSEG_RES_DPH:
- __sevenseg_set_masked((SEVENSEG_DIGIT_DP << 8), 0);
- return;
- break; /* paranoia */
-
- case SEVENSEG_TOG_DPL:
- __sevenseg_toggle_masked(SEVENSEG_DIGIT_DP);
- return;
- break; /* paranoia */
-
- case SEVENSEG_TOG_DPH:
- __sevenseg_toggle_masked((SEVENSEG_DIGIT_DP << 8));
- return;
- break; /* paranoia */
-
- case SEVENSEG_LO:
- case SEVENSEG_HI:
- case SEVENSEG_STR:
- default:
- break;
- }
-}
-
-#endif /* CONFIG_SEVENSEG */
+++ /dev/null
-/*
- * (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
- * Stephan Linz <linz@li-pro.net>
- *
- * SPDX-License-Identifier: GPL-2.0+
- *
- * common/sevenseg.h
- *
- * NIOS PIO based seven segment led support functions
- */
-
-#ifndef __DK1S10_SEVENSEG_H__
-#define __DK1S10_SEVENSEG_H__
-
-#ifdef CONFIG_SEVENSEG
-
-/*
- * 15 8 7 0
- * |-----------------------|--------|
- * | controll value | value |
- * ----------------------------------
- */
-#define SEVENSEG_RAW (int)(0) /* write out byte value (hex) */
-#define SEVENSEG_OFF (int)( 1 << 8) /* display switch off */
-#define SEVENSEG_SET_DPL (int)( 2 << 8) /* set dp low nibble */
-#define SEVENSEG_SET_DPH (int)( 3 << 8) /* set dp high nibble */
-#define SEVENSEG_RES_DPL (int)( 4 << 8) /* reset dp low nibble */
-#define SEVENSEG_RES_DPH (int)( 5 << 8) /* reset dp high nibble */
-#define SEVENSEG_TOG_DPL (int)( 6 << 8) /* toggle dp low nibble */
-#define SEVENSEG_TOG_DPH (int)( 7 << 8) /* toggle dp high nibble */
-#define SEVENSEG_LO (int)( 8 << 8) /* write out low nibble only */
-#define SEVENSEG_HI (int)( 9 << 8) /* write out high nibble only */
-#define SEVENSEG_STR (int)(10 << 8) /* write out a string */
-
-#define SEVENSEG_MASK_VAL (0xff) /* only used by SEVENSEG_RAW */
-#define SEVENSEG_MASK_CTRL (~SEVENSEG_MASK_VAL)
-
-#ifdef SEVENSEG_DIGIT_HI_LO_EQUAL
-
-#define SEVENSEG_DIGITS_0 ( SEVENSEG_DIGIT_A \
- | SEVENSEG_DIGIT_B \
- | SEVENSEG_DIGIT_C \
- | SEVENSEG_DIGIT_D \
- | SEVENSEG_DIGIT_E \
- | SEVENSEG_DIGIT_F )
-#define SEVENSEG_DIGITS_1 ( SEVENSEG_DIGIT_B \
- | SEVENSEG_DIGIT_C )
-#define SEVENSEG_DIGITS_2 ( SEVENSEG_DIGIT_A \
- | SEVENSEG_DIGIT_B \
- | SEVENSEG_DIGIT_D \
- | SEVENSEG_DIGIT_E \
- | SEVENSEG_DIGIT_G )
-#define SEVENSEG_DIGITS_3 ( SEVENSEG_DIGIT_A \
- | SEVENSEG_DIGIT_B \
- | SEVENSEG_DIGIT_C \
- | SEVENSEG_DIGIT_D \
- | SEVENSEG_DIGIT_G )
-#define SEVENSEG_DIGITS_4 ( SEVENSEG_DIGIT_B \
- | SEVENSEG_DIGIT_C \
- | SEVENSEG_DIGIT_F \
- | SEVENSEG_DIGIT_G )
-#define SEVENSEG_DIGITS_5 ( SEVENSEG_DIGIT_A \
- | SEVENSEG_DIGIT_C \
- | SEVENSEG_DIGIT_D \
- | SEVENSEG_DIGIT_F \
- | SEVENSEG_DIGIT_G )
-#define SEVENSEG_DIGITS_6 ( SEVENSEG_DIGIT_A \
- | SEVENSEG_DIGIT_C \
- | SEVENSEG_DIGIT_D \
- | SEVENSEG_DIGIT_E \
- | SEVENSEG_DIGIT_F \
- | SEVENSEG_DIGIT_G )
-#define SEVENSEG_DIGITS_7 ( SEVENSEG_DIGIT_A \
- | SEVENSEG_DIGIT_B \
- | SEVENSEG_DIGIT_C )
-#define SEVENSEG_DIGITS_8 ( SEVENSEG_DIGIT_A \
- | SEVENSEG_DIGIT_B \
- | SEVENSEG_DIGIT_C \
- | SEVENSEG_DIGIT_D \
- | SEVENSEG_DIGIT_E \
- | SEVENSEG_DIGIT_F \
- | SEVENSEG_DIGIT_G )
-#define SEVENSEG_DIGITS_9 ( SEVENSEG_DIGIT_A \
- | SEVENSEG_DIGIT_B \
- | SEVENSEG_DIGIT_C \
- | SEVENSEG_DIGIT_D \
- | SEVENSEG_DIGIT_F \
- | SEVENSEG_DIGIT_G )
-#define SEVENSEG_DIGITS_A ( SEVENSEG_DIGIT_A \
- | SEVENSEG_DIGIT_B \
- | SEVENSEG_DIGIT_C \
- | SEVENSEG_DIGIT_E \
- | SEVENSEG_DIGIT_F \
- | SEVENSEG_DIGIT_G )
-#define SEVENSEG_DIGITS_B ( SEVENSEG_DIGIT_C \
- | SEVENSEG_DIGIT_D \
- | SEVENSEG_DIGIT_E \
- | SEVENSEG_DIGIT_F \
- | SEVENSEG_DIGIT_G )
-#define SEVENSEG_DIGITS_C ( SEVENSEG_DIGIT_D \
- | SEVENSEG_DIGIT_E \
- | SEVENSEG_DIGIT_G )
-#define SEVENSEG_DIGITS_D ( SEVENSEG_DIGIT_B \
- | SEVENSEG_DIGIT_C \
- | SEVENSEG_DIGIT_D \
- | SEVENSEG_DIGIT_E \
- | SEVENSEG_DIGIT_G )
-#define SEVENSEG_DIGITS_E ( SEVENSEG_DIGIT_A \
- | SEVENSEG_DIGIT_D \
- | SEVENSEG_DIGIT_E \
- | SEVENSEG_DIGIT_F \
- | SEVENSEG_DIGIT_G )
-#define SEVENSEG_DIGITS_F ( SEVENSEG_DIGIT_A \
- | SEVENSEG_DIGIT_E \
- | SEVENSEG_DIGIT_F \
- | SEVENSEG_DIGIT_G )
-
-#else /* !SEVENSEG_DIGIT_HI_LO_EQUAL */
-#error SEVENSEG: different pin asssignments not supported
-#endif
-
-void sevenseg_set(int value);
-
-#endif /* CONFIG_SEVENSEG */
-
-#endif /* __DK1S10_SEVENSEG_H__ */
obj-y := nios2-generic.o
obj-$(CONFIG_CMD_IDE) += ../common/cfide.o
obj-$(CONFIG_EPLED) += ../common/epled.o
-obj-$(CONFIG_SEVENSEG) += ../common/sevenseg.o
obj-y += text_base.o
*/
#include <common.h>
+#include <cli.h>
#include <command.h>
#include "yucca.h"
#include <i2c.h>
do {
printf("enter sys clock frequency 33 or 66 MHz or quit to abort\n");
- nbytes = readline (" ? ");
+ nbytes = cli_readline(" ? ");
if (strcmp(console_buffer, "quit") == 0)
return 0;
printf("enter cpu clock frequency 400, 500, 533 MHz or quit to abort\n");
#endif
}
- nbytes = readline (" ? ");
+ nbytes = cli_readline(" ? ");
if (strcmp(console_buffer, "quit") == 0)
return 0;
printf("enter plb clock frequency 133, 166 MHz or quit to abort\n");
#endif
- nbytes = readline (" ? ");
+ nbytes = cli_readline(" ? ");
if (strcmp(console_buffer, "quit") == 0)
return 0;
do {
printf("enter Pci-X clock frequency 33, 66, 100 or 133 MHz or quit to abort\n");
- nbytes = readline (" ? ");
+ nbytes = cli_readline(" ? ");
if (strcmp(console_buffer, "quit") == 0)
return 0;
printf("Pci-X clk = %s MHz\n", pcixClock);
do {
- printf("\npress [y] to write I2C bootstrap \n");
- printf("or [n] to abort. \n");
- printf("Don't forget to set board switches \n");
- printf("according to your choice before re-starting \n");
- printf("(refer to 440spe_uboot_kit_um_1_01.pdf) \n");
+ printf("\npress [y] to write I2C bootstrap\n");
+ printf("or [n] to abort.\n");
+ printf("Don't forget to set board switches\n");
+ printf("according to your choice before re-starting\n");
+ printf("(refer to 440spe_uboot_kit_um_1_01.pdf)\n");
- nbytes = readline (" ? ");
+ nbytes = cli_readline(" ? ");
if (strcmp(console_buffer, "n") == 0)
return 0;
* writing the complete buffer in one function is much faster,
* then calling it for every bit
*/
-int altera_write_fn(void *buf, size_t len, int flush, int cookie)
+int altera_write_fn(const void *buf, size_t len, int flush, int cookie)
{
size_t bytecount = 0;
gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
* (Do not rely on the SDCS register(s) being set to 0x00000000
* during reset as stated in the data sheet.)
*/
- return get_ram_size((unsigned long *)CONFIG_SYS_SDRAM_BASE,
+ return get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
0x80000000 - CONFIG_SYS_SDRAM_BASE);
}
#ifdef CONFIG_LCD
vidinfo_t panel_info = {
- vl_col: 240,
- vl_row: 320,
- vl_clk: 4965000,
- vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
- ATMEL_LCDC_INVFRAME_INVERTED,
- vl_bpix: 3,
- vl_tft: 1,
- vl_hsync_len: 5,
- vl_left_margin: 1,
- vl_right_margin:33,
- vl_vsync_len: 1,
- vl_upper_margin:1,
- vl_lower_margin:0,
- mmio: ATMEL_BASE_LCDC,
+ .vl_col = 240,
+ .vl_row = 320,
+ .vl_clk = 4965000,
+ .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
+ ATMEL_LCDC_INVFRAME_INVERTED,
+ .vl_bpix = 3,
+ .vl_tft = 1,
+ .vl_hsync_len = 5,
+ .vl_left_margin = 1,
+ .vl_right_margin = 33,
+ .vl_vsync_len = 1,
+ .vl_upper_margin = 1,
+ .vl_lower_margin = 0,
+ .mmio = ATMEL_BASE_LCDC,
};
void lcd_enable(void)
#ifdef CONFIG_LCD
vidinfo_t panel_info = {
- vl_col: 240,
- vl_row: 320,
- vl_clk: 4965000,
- vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
- ATMEL_LCDC_INVFRAME_INVERTED,
- vl_bpix: 3,
- vl_tft: 1,
- vl_hsync_len: 5,
- vl_left_margin: 1,
- vl_right_margin:33,
- vl_vsync_len: 1,
- vl_upper_margin:1,
- vl_lower_margin:0,
- mmio: ATMEL_BASE_LCDC,
+ .vl_col = 240,
+ .vl_row = 320,
+ .vl_clk = 4965000,
+ .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
+ ATMEL_LCDC_INVFRAME_INVERTED,
+ .vl_bpix = 3,
+ .vl_tft = 1,
+ .vl_hsync_len = 5,
+ .vl_left_margin = 1,
+ .vl_right_margin = 33,
+ .vl_vsync_len = 1,
+ .vl_upper_margin = 1,
+ .vl_lower_margin = 0,
+ .mmio = ATMEL_BASE_LCDC,
};
void lcd_enable(void)
#ifdef CONFIG_LCD
vidinfo_t panel_info = {
- vl_col: 480,
- vl_row: 272,
- vl_clk: 9000000,
- vl_sync: ATMEL_LCDC_INVLINE_NORMAL |
- ATMEL_LCDC_INVFRAME_NORMAL,
- vl_bpix: 3,
- vl_tft: 1,
- vl_hsync_len: 45,
- vl_left_margin: 1,
- vl_right_margin:1,
- vl_vsync_len: 1,
- vl_upper_margin:40,
- vl_lower_margin:1,
- mmio : ATMEL_BASE_LCDC,
+ .vl_col = 480,
+ .vl_row = 272,
+ .vl_clk = 9000000,
+ .vl_sync = ATMEL_LCDC_INVLINE_NORMAL |
+ ATMEL_LCDC_INVFRAME_NORMAL,
+ .vl_bpix = 3,
+ .vl_tft = 1,
+ .vl_hsync_len = 45,
+ .vl_left_margin = 1,
+ .vl_right_margin = 1,
+ .vl_vsync_len = 1,
+ .vl_upper_margin = 40,
+ .vl_lower_margin = 1,
+ .mmio = ATMEL_BASE_LCDC,
};
#ifdef CONFIG_LCD
vidinfo_t panel_info = {
- vl_col: 240,
- vl_row: 320,
- vl_clk: 4965000,
- vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
- ATMEL_LCDC_INVFRAME_INVERTED,
- vl_bpix: 3,
- vl_tft: 1,
- vl_hsync_len: 5,
- vl_left_margin: 1,
- vl_right_margin:33,
- vl_vsync_len: 1,
- vl_upper_margin:1,
- vl_lower_margin:0,
- mmio: ATMEL_BASE_LCDC,
+ .vl_col = 240,
+ .vl_row = 320,
+ .vl_clk = 4965000,
+ .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
+ ATMEL_LCDC_INVFRAME_INVERTED,
+ .vl_bpix = 3,
+ .vl_tft = 1,
+ .vl_hsync_len = 5,
+ .vl_left_margin = 1,
+ .vl_right_margin = 33,
+ .vl_vsync_len = 1,
+ .vl_upper_margin = 1,
+ .vl_lower_margin = 0,
+ .mmio = ATMEL_BASE_LCDC,
};
void lcd_enable(void)
*(.__rel_dyn_end)
}
+ .hash : { *(.hash*) }
+
.end :
{
*(.__end)
}
.dynsym _image_binary_end : { *(.dynsym) }
- .hash : { *(.hash) }
- .got.plt : { *(.got.plt) }
.dynbss : { *(.dynbss) }
.dynstr : { *(.dynstr*) }
.dynamic : { *(.dynamic*) }
$(obj)/bootscript.c: $(obj)/bootscript.image $(src)/x2c.awk
$(call cmd,awk)
-quiet_cmd_mkimage = MKIMAGE $@
-cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
- $(if $(KBUILD_VERBOSE:1=), >/dev/null)
-
MKIMAGEFLAGS_bootscript.image := -A ppc -O linux -T script -C none \
-a 0 -e 0 -n bootscript
$(obj)/bootscript.image: $(src)/bootscript.hush
$(call cmd,mkimage)
-clean-files := bootscript.c bootscript.image
\ No newline at end of file
+clean-files := bootscript.c bootscript.image
#include <asm/arch/clock.h>
#include <asm/arch/iomux-mx53.h>
#include <asm/imx-common/mx5_video.h>
-#include <asm/arch/spl.h>
+#include <asm/spl.h>
#include <asm/errno.h>
#include <netdev.h>
#include <i2c.h>
/* includes */
#include <common.h>
+#include <cli.h>
#include <linux/ctype.h>
#include <pci.h>
#include <net.h>
printf ("Press key:\n <c> to copy current revision info to nvram.\n");
printf (" <r> to reenter revision info.\n");
printf ("=> ");
- if (0 != readline (NULL)) {
+ if (0 != cli_readline(NULL)) {
switch ((char) toupper (console_buffer[0])) {
case 'C':
copyNv = 1;
memcpy (buf, &eerev.revision[0][0], 14); /* save all revision info */
printf ("Enter revision number (0-9): %c ",
eerev.revision[0][0]);
- if (0 != readline (NULL)) {
+ if (0 != cli_readline(NULL)) {
eerev.revision[0][0] =
(char) toupper (console_buffer[0]);
memcpy (&eerev.revision[1][0], buf, 12); /* shift rest of rev info */
printf ("Enter revision character (A-Z): %c ",
eerev.revision[0][1]);
- if (1 == readline (NULL)) {
+ if (1 == cli_readline(NULL)) {
eerev.revision[0][1] =
(char) toupper (console_buffer[0]);
}
printf ("Enter board name (V-XXXX-XXXX): %s ",
(char *) &eerev.board);
- if (11 == readline (NULL)) {
+ if (11 == cli_readline(NULL)) {
for (i = 0; i < 11; i++)
eerev.board[i] =
(char) toupper (console_buffer[i]);
}
printf ("Enter serial number: %s ", (char *) &eerev.serial);
- if (6 == readline (NULL)) {
+ if (6 == cli_readline(NULL)) {
for (i = 0; i < 6; i++)
eerev.serial[i] = console_buffer[i];
eerev.serial[6] = '\0';
}
printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", eerev.etheraddr[0], eerev.etheraddr[1], eerev.etheraddr[2], eerev.etheraddr[3], eerev.etheraddr[4], eerev.etheraddr[5]);
- if (12 == readline (NULL)) {
+ if (12 == cli_readline(NULL)) {
for (i = 0; i < 12; i += 2)
eerev.etheraddr[i >> 1] =
(char) (16 *
l = strlen ((char *) &eerev.text);
printf ("Add to text section (max 64 chr): %s ",
(char *) &eerev.text);
- if (0 != readline (NULL)) {
+ if (0 != cli_readline(NULL)) {
for (i = l; i < 63; i++)
eerev.text[i] = console_buffer[i - l];
eerev.text[63] = '\0';
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
+#include <cli.h>
#include <linux/ctype.h>
#include <commproc.h>
#include "mpc8xx.h"
if (strncmp ((char *) &mhpcRevInfo.board[2], "MHPC", 4) != 0) {
printf ("Enter revision number (0-9): %c ",
mhpcRevInfo.revision[0]);
- if (0 != readline (NULL)) {
+ if (0 != cli_readline(NULL)) {
mhpcRevInfo.revision[0] =
(char) toupper (console_buffer[0]);
}
printf ("Enter revision character (A-Z): %c ",
mhpcRevInfo.revision[1]);
- if (1 == readline (NULL)) {
+ if (1 == cli_readline(NULL)) {
mhpcRevInfo.revision[1] =
(char) toupper (console_buffer[0]);
}
printf ("Enter board name (V-XXXX-XXXX): %s ",
(char *) &mhpcRevInfo.board);
- if (11 == readline (NULL)) {
+ if (11 == cli_readline(NULL)) {
for (i = 0; i < 11; i++) {
mhpcRevInfo.board[i] =
(char) toupper (console_buffer[i]);
do {
printf ("\nEnter sensor number (0-255): %d ",
(int) mhpcRevInfo.sensor);
- if (0 != readline (NULL)) {
+ if (0 != cli_readline(NULL)) {
mhpcRevInfo.sensor =
(unsigned char)
simple_strtoul (console_buffer, NULL,
printf ("Enter serial number: %s ",
(char *) &mhpcRevInfo.serial);
- if (6 == readline (NULL)) {
+ if (6 == cli_readline(NULL)) {
for (i = 0; i < 6; i++) {
mhpcRevInfo.serial[i] = console_buffer[i];
}
}
printf ("Enter ether node ID with leading zero (HEX): %02x%02x%02x%02x%02x%02x ", mhpcRevInfo.etheraddr[0], mhpcRevInfo.etheraddr[1], mhpcRevInfo.etheraddr[2], mhpcRevInfo.etheraddr[3], mhpcRevInfo.etheraddr[4], mhpcRevInfo.etheraddr[5]);
- if (12 == readline (NULL)) {
+ if (12 == cli_readline(NULL)) {
for (i = 0; i < 12; i += 2) {
mhpcRevInfo.etheraddr[i >> 1] =
(char) (16 *
+++ /dev/null
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := ep8248.o
+++ /dev/null
-/*
- * Copyright (C) 2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * Support for Embedded Planet EP8248 boards.
- * Tested on EP8248E.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8260.h>
-#include <ioports.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-#define CONFIG_SYS_FCC1 (CONFIG_ETHER_ON_FCC1 == 1)
-#define CONFIG_SYS_FCC2 (CONFIG_ETHER_ON_FCC2 == 1)
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
- /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
- /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
- /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
- /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
- /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
- /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
- /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
- /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
- /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
- /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
- /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
- /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
- /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
- /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
- /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
- /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
- /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
- /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
- /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
- /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
- /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
- /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TxD */
- /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RxD */
- /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
- /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
- /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
- },
-
- /* Port B */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
- /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
- /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
- /* PC22 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK10) */
- /* PC21 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK11) */
- /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
- /* PC19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK13) */
- /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */
- /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
- /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
- /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
- /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
- /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* MDIO */
- /* PC8 */ { 1, 0, 0, 1, 0, 1 }, /* MDC */
- /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
- /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */
- /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */
- /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
- /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
- /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */
- /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */
- /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
- /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
- /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
- /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
- /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
- }
-};
-
-int board_early_init_f (void)
-{
- vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
-
- bcsr[4] |= 0x30; /* Turn the LEDs off */
-
-#if defined(CONFIG_CONS_ON_SMC) || defined(CONFIG_KGDB_ON_SMC)
- bcsr[6] |= 0x10;
-#endif
-#if defined(CONFIG_CONS_ON_SCC) || defined(CONFIG_KGDB_ON_SCC)
- bcsr[7] |= 0x10;
-#endif
-
-#if CONFIG_SYS_FCC1
- bcsr[8] |= 0xC0;
-#endif /* CONFIG_SYS_FCC1 */
-#if CONFIG_SYS_FCC2
- bcsr[8] |= 0x30;
-#endif /* CONFIG_SYS_FCC2 */
-
- return 0;
-}
-
-phys_size_t initdram(int board_type)
-{
- vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
- long int msize = 16L << (bcsr[2] & 3);
-
-#ifndef CONFIG_SYS_RAMBOOT
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
- vu_char *ramaddr = (vu_char *)CONFIG_SYS_SDRAM_BASE;
- uchar c = 0xFF;
- uint psdmr = CONFIG_SYS_PSDMR;
- int i;
-
- immap->im_siu_conf.sc_ppc_acr = 0x02;
- immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
- immap->im_siu_conf.sc_tescr1 = 0x00004000;
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
- /* Initialise 60x bus SDRAM */
- memctl->memc_psrt = CONFIG_SYS_PSRT;
- memctl->memc_or1 = CONFIG_SYS_SDRAM_OR;
- memctl->memc_br1 = CONFIG_SYS_SDRAM_BR;
- memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
- *ramaddr = c;
- memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
- for (i = 0; i < 8; i++)
- *ramaddr = c;
- memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */
- *ramaddr = c;
- memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */
- *ramaddr = c;
-#endif /* !CONFIG_SYS_RAMBOOT */
-
- /* Return total 60x bus SDRAM size */
- return msize * 1024 * 1024;
-}
-
-int checkboard(void)
-{
- vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
-
- puts("Board: ");
- switch (bcsr[0]) {
- case 0x0C:
- printf("EP8248E 1.0 CPLD revision %d\n", bcsr[1]);
- break;
- default:
- printf("unknown: ID=%02X\n", bcsr[0]);
- }
-
- return 0;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
-void ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup( blob, bd);
-}
-#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = debris.o flash.o phantom.o
+++ /dev/null
-/*
- * (C) Copyright 2000
- * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <net.h>
-#include <pci.h>
-#include <i2c.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int checkboard (void)
-{
- /*TODO: Check processor type */
-
- puts ( "Board: Debris "
-#ifdef CONFIG_MPC8240
- "8240"
-#endif
-#ifdef CONFIG_MPC8245
- "8245"
-#endif
- " ##Test not implemented yet##\n");
- return 0;
-}
-
-#if 0 /* NOT USED */
-int checkflash (void)
-{
- /* TODO: XXX XXX XXX */
- printf ("## Test not implemented yet ##\n");
-
- return (0);
-}
-#endif
-
-phys_size_t initdram (int board_type)
-{
- int m, row, col, bank, i;
- unsigned long start, end;
- uint32_t mccr1;
- uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
- uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
- uint8_t mber = 0;
-
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-
- if (i2c_reg_read (0x50, 2) != 0x04) return 0; /* Memory type */
- m = i2c_reg_read (0x50, 5); /* # of physical banks */
- row = i2c_reg_read (0x50, 3); /* # of rows */
- col = i2c_reg_read (0x50, 4); /* # of columns */
- bank = i2c_reg_read (0x50, 17); /* # of logical banks */
-
- CONFIG_READ_WORD(MCCR1, mccr1);
- mccr1 &= 0xffff0000;
-
- start = CONFIG_SYS_SDRAM_BASE;
- end = start + (1 << (col + row + 3) ) * bank - 1;
-
- for (i = 0; i < m; i++) {
- mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
- if (i < 4) {
- msar1 |= ((start >> 20) & 0xff) << i * 8;
- emsar1 |= ((start >> 28) & 0xff) << i * 8;
- mear1 |= ((end >> 20) & 0xff) << i * 8;
- emear1 |= ((end >> 28) & 0xff) << i * 8;
- } else {
- msar2 |= ((start >> 20) & 0xff) << (i-4) * 8;
- emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
- mear2 |= ((end >> 20) & 0xff) << (i-4) * 8;
- emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
- }
- mber |= 1 << i;
- start += (1 << (col + row + 3) ) * bank;
- end += (1 << (col + row + 3) ) * bank;
- }
- for (; i < 8; i++) {
- if (i < 4) {
- msar1 |= 0xff << i * 8;
- emsar1 |= 0x30 << i * 8;
- mear1 |= 0xff << i * 8;
- emear1 |= 0x30 << i * 8;
- } else {
- msar2 |= 0xff << (i-4) * 8;
- emsar2 |= 0x30 << (i-4) * 8;
- mear2 |= 0xff << (i-4) * 8;
- emear2 |= 0x30 << (i-4) * 8;
- }
- }
-
- CONFIG_WRITE_WORD(MCCR1, mccr1);
- CONFIG_WRITE_WORD(MSAR1, msar1);
- CONFIG_WRITE_WORD(EMSAR1, emsar1);
- CONFIG_WRITE_WORD(MEAR1, mear1);
- CONFIG_WRITE_WORD(EMEAR1, emear1);
- CONFIG_WRITE_WORD(MSAR2, msar2);
- CONFIG_WRITE_WORD(EMSAR2, emsar2);
- CONFIG_WRITE_WORD(MEAR2, mear2);
- CONFIG_WRITE_WORD(EMEAR2, emear2);
- CONFIG_WRITE_BYTE(MBER, mber);
-
- return (1 << (col + row + 3) ) * bank * m;
-}
-
-/*
- * Initialize PCI Devices, report devices found.
- */
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_debris_config_table[] = {
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
- PCI_ENET1_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
- { }
-};
-#endif
-
-struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
- config_table: pci_debris_config_table,
-#endif
-};
-
-void pci_init_board(void)
-{
- pci_mpc824x_init(&hose);
-}
-
-void *nvram_read(void *dest, const long src, size_t count)
-{
- volatile uchar *d = (volatile uchar*) dest;
- volatile uchar *s = (volatile uchar*) src;
- while(count--) {
- *d++ = *s++;
- asm volatile("sync");
- }
- return dest;
-}
-
-void nvram_write(long dest, const void *src, size_t count)
-{
- volatile uchar *d = (volatile uchar*)dest;
- volatile uchar *s = (volatile uchar*)src;
- while(count--) {
- *d++ = *s++;
- asm volatile("sync");
- }
-}
-
-int misc_init_r(void)
-{
- uchar ethaddr[6];
-
- if (eth_getenv_enetaddr("ethaddr", ethaddr))
- /* Write ethernet addr in NVRAM for VxWorks */
- nvram_write(CONFIG_ENV_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS,
- ethaddr, 6);
-
- return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
+++ /dev/null
-/*
- * board/eva/flash.c
- *
- * (C) Copyright 2002
- * Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/pci_io.h>
-#include <mpc824x.h>
-#include <asm/mmu.h>
-
-int (*do_flash_erase)(flash_info_t*, uint32_t, uint32_t);
-int (*write_dword)(flash_info_t*, ulong, uint64_t);
-
-typedef uint64_t cfi_word;
-
-#define cfi_read(flash, addr) *((volatile cfi_word*)(flash->start[0] + addr))
-
-#define cfi_write(flash, val, addr) \
- move64((cfi_word*)&val, \
- (cfi_word*)(flash->start[0] + addr))
-
-#define CMD(x) ((((cfi_word)x)<<48)|(((cfi_word)x)<<32)|(((cfi_word)x)<<16)|(((cfi_word)x)))
-
-static void write32(unsigned long addr, uint32_t value)
-{
- *(volatile uint32_t*)(addr) = value;
- asm volatile("sync");
-}
-
-static uint32_t read32(unsigned long addr)
-{
- uint32_t value;
- value = *(volatile uint32_t*)addr;
- asm volatile("sync");
- return value;
-}
-
-static cfi_word cfi_cmd(flash_info_t *flash, uint8_t cmd, uint32_t addr)
-{
- uint32_t base = flash->start[0];
- uint32_t val=(cmd << 16) | cmd;
- addr <<= 3;
- write32(base + addr, val);
- return addr;
-}
-
-static uint16_t cfi_read_query(flash_info_t *flash, uint32_t addr)
-{
- uint32_t base = flash->start[0];
- addr <<= 3;
- return (uint16_t)read32(base + addr);
-}
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-static void move64(uint64_t *src, uint64_t *dest)
-{
- asm volatile("lfd 0, 0(3)\n\t" /* fpr0 = *scr */
- "stfd 0, 0(4)" /* *dest = fpr0 */
- : : : "fr0" ); /* Clobbers fr0 */
- return;
-}
-
-static int cfi_write_dword(flash_info_t *flash, ulong dest, cfi_word data)
-{
- unsigned long start;
- cfi_word status = 0;
-
- status = cfi_read(flash, dest);
- data &= status;
-
- cfi_cmd(flash, 0x40, 0);
- cfi_write(flash, data, dest);
-
- udelay(10);
- start = get_timer (0);
- for(;;) {
- status = cfi_read(flash, dest);
- status &= CMD(0x80);
- if(status == CMD(0x80))
- break;
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- cfi_cmd(flash, 0xff, 0);
- return 1;
- }
- udelay(1);
- }
- cfi_cmd(flash, 0xff, 0);
-
- return 0;
-}
-
-static int jedec_write_dword (flash_info_t *flash, ulong dest, cfi_word data)
-{
- ulong start;
- cfi_word status = 0;
-
- status = cfi_read(flash, dest);
- if(status != CMD(0xffff)) return 2;
-
- cfi_cmd(flash, 0xaa, 0x555);
- cfi_cmd(flash, 0x55, 0x2aa);
- cfi_cmd(flash, 0xa0, 0x555);
-
- cfi_write(flash, data, dest);
-
- udelay(10);
- start = get_timer (0);
- status = ~data;
- while(status != data) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
- return 1;
- status = cfi_read(flash, dest);
- udelay(1);
- }
- return 0;
-}
-
-static __inline__ unsigned long get_msr(void)
-{
- unsigned long msr;
- __asm__ __volatile__ ("mfmsr %0" : "=r" (msr) :);
- return msr;
-}
-
-static __inline__ void set_msr(unsigned long msr)
-{
- __asm__ __volatile__ ("mtmsr %0" : : "r" (msr));
-}
-
-int write_buff (flash_info_t *flash, uchar *src, ulong addr, ulong cnt)
-{
- ulong wp;
- int i, s, l, rc;
- cfi_word data;
- uint8_t *t = (uint8_t*)&data;
- unsigned long base = flash->start[0];
- uint32_t msr;
-
- if (flash->flash_id == FLASH_UNKNOWN)
- return 4;
-
- if (cnt == 0)
- return 0;
-
- addr -= base;
-
- msr = get_msr();
- set_msr(msr|MSR_FP);
-
- wp = (addr & ~7); /* get lower word aligned address */
-
- if((addr-wp) != 0) {
- data = cfi_read(flash, wp);
- s = addr & 7;
- l = ( cnt < (8-s) ) ? cnt : (8-s);
- for(i = 0; i < l; i++)
- t[s+i] = *src++;
- if ((rc = write_dword(flash, wp, data)) != 0)
- goto DONE;
- wp += 8;
- cnt -= l;
- }
-
- while (cnt >= 8) {
- for (i = 0; i < 8; i++)
- t[i] = *src++;
- if ((rc = write_dword(flash, wp, data)) != 0)
- goto DONE;
- wp += 8;
- cnt -= 8;
- }
-
- if (cnt == 0) {
- rc = 0;
- goto DONE;
- }
-
- data = cfi_read(flash, wp);
- for(i = 0; i < cnt; i++)
- t[i] = *src++;
- rc = write_dword(flash, wp, data);
-DONE:
- set_msr(msr);
- return rc;
-}
-
-static int cfi_erase_oneblock(flash_info_t *flash, uint32_t sect)
-{
- int sa;
- int flag;
- ulong start, last, now;
- cfi_word status;
-
- flag = disable_interrupts();
-
- sa = (flash->start[sect] - flash->start[0]);
- write32(flash->start[sect], 0x00200020);
- write32(flash->start[sect], 0x00d000d0);
-
- if (flag)
- enable_interrupts();
-
- udelay(1000);
- start = get_timer (0);
- last = start;
-
- for (;;) {
- status = cfi_read(flash, sa);
- status &= CMD(0x80);
- if (status == CMD(0x80))
- break;
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- cfi_cmd(flash, 0xff, 0);
- printf ("Timeout\n");
- return ERR_TIMOUT;
- }
-
- if ((now - last) > 1000) {
- serial_putc ('.');
- last = now;
- }
- udelay(10);
- }
- cfi_cmd(flash, 0xff, 0);
- return ERR_OK;
-}
-
-static int cfi_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last)
-{
- int sect;
- int rc = ERR_OK;
-
- for (sect = s_first; sect <= s_last; sect++) {
- if (flash->protect[sect] == 0) {
- rc = cfi_erase_oneblock(flash, sect);
- if (rc != ERR_OK) break;
- }
- }
- printf (" done\n");
- return rc;
-}
-
-static int jedec_erase(flash_info_t *flash, uint32_t s_first, uint32_t s_last)
-{
- int sect;
- cfi_word status;
- int sa = -1;
- int flag;
- ulong start, last, now;
-
- flag = disable_interrupts();
-
- cfi_cmd(flash, 0xaa, 0x555);
- cfi_cmd(flash, 0x55, 0x2aa);
- cfi_cmd(flash, 0x80, 0x555);
- cfi_cmd(flash, 0xaa, 0x555);
- cfi_cmd(flash, 0x55, 0x2aa);
- for ( sect = s_first; sect <= s_last; sect++) {
- if (flash->protect[sect] == 0) {
- sa = flash->start[sect] - flash->start[0];
- write32(flash->start[sect], 0x00300030);
- }
- }
- if (flag)
- enable_interrupts();
-
- if (sa < 0)
- goto DONE;
-
- udelay (1000);
- start = get_timer (0);
- last = start;
- for(;;) {
- status = cfi_read(flash, sa);
- if (status == CMD(0xffff))
- break;
-
- if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return ERR_TIMOUT;
- }
-
- if ((now - last) > 1000) {
- serial_putc ('.');
- last = now;
- }
- udelay(10);
- }
-DONE:
- cfi_cmd(flash, 0xf0, 0);
-
- printf (" done\n");
-
- return ERR_OK;
-}
-
-int flash_erase (flash_info_t *flash, int s_first, int s_last)
-{
- int sect;
- int prot;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (flash->flash_id == FLASH_UNKNOWN)
- printf ("- missing\n");
- else
- printf ("- no sectors to erase\n");
- return ERR_NOT_ERASED;
- }
- if (flash->flash_id == FLASH_UNKNOWN) {
- printf ("Can't erase unknown flash type - aborted\n");
- return ERR_NOT_ERASED;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; sect++)
- if (flash->protect[sect]) prot++;
-
- if (prot)
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- else
- printf ("\n");
-
- return do_flash_erase(flash, s_first, s_last);
-}
-
-struct jedec_flash_info {
- const uint16_t mfr_id;
- const uint16_t dev_id;
- const char *name;
- const int DevSize;
- const int InterfaceDesc;
- const int NumEraseRegions;
- const ulong regions[4];
-};
-
-#define ERASEINFO(size,blocks) (size<<8)|(blocks-1)
-
-#define SIZE_1MiB 20
-#define SIZE_2MiB 21
-#define SIZE_4MiB 22
-
-static const struct jedec_flash_info jedec_table[] = {
- {
- mfr_id: (uint16_t)AMD_MANUFACT,
- dev_id: (uint16_t)AMD_ID_LV800T,
- name: "AMD AM29LV800T",
- DevSize: SIZE_1MiB,
- NumEraseRegions: 4,
- regions: {ERASEINFO(0x10000,15),
- ERASEINFO(0x08000,1),
- ERASEINFO(0x02000,2),
- ERASEINFO(0x04000,1)
- }
- }, {
- mfr_id: (uint16_t)AMD_MANUFACT,
- dev_id: (uint16_t)AMD_ID_LV800B,
- name: "AMD AM29LV800B",
- DevSize: SIZE_1MiB,
- NumEraseRegions: 4,
- regions: {ERASEINFO(0x10000,15),
- ERASEINFO(0x08000,1),
- ERASEINFO(0x02000,2),
- ERASEINFO(0x04000,1)
- }
- }, {
- mfr_id: (uint16_t)AMD_MANUFACT,
- dev_id: (uint16_t)AMD_ID_LV160T,
- name: "AMD AM29LV160T",
- DevSize: SIZE_2MiB,
- NumEraseRegions: 4,
- regions: {ERASEINFO(0x10000,31),
- ERASEINFO(0x08000,1),
- ERASEINFO(0x02000,2),
- ERASEINFO(0x04000,1)
- }
- }, {
- mfr_id: (uint16_t)AMD_MANUFACT,
- dev_id: (uint16_t)AMD_ID_LV160B,
- name: "AMD AM29LV160B",
- DevSize: SIZE_2MiB,
- NumEraseRegions: 4,
- regions: {ERASEINFO(0x04000,1),
- ERASEINFO(0x02000,2),
- ERASEINFO(0x08000,1),
- ERASEINFO(0x10000,31)
- }
- }, {
- mfr_id: (uint16_t)AMD_MANUFACT,
- dev_id: (uint16_t)AMD_ID_LV320T,
- name: "AMD AM29LV320T",
- DevSize: SIZE_4MiB,
- NumEraseRegions: 2,
- regions: {ERASEINFO(0x10000,63),
- ERASEINFO(0x02000,8)
- }
-
- }, {
- mfr_id: (uint16_t)AMD_MANUFACT,
- dev_id: (uint16_t)AMD_ID_LV320B,
- name: "AMD AM29LV320B",
- DevSize: SIZE_4MiB,
- NumEraseRegions: 2,
- regions: {ERASEINFO(0x02000,8),
- ERASEINFO(0x10000,63)
- }
- }
-};
-
-static ulong cfi_init(uint32_t base, flash_info_t *flash)
-{
- int sector;
- int block;
- int block_count;
- int offset = 0;
- int reverse = 0;
- int primary;
- int mfr_id;
- int dev_id;
-
- flash->start[0] = base;
- cfi_cmd(flash, 0xF0, 0);
- cfi_cmd(flash, 0x98, 0);
- if ( !( cfi_read_query(flash, 0x10) == 'Q' &&
- cfi_read_query(flash, 0x11) == 'R' &&
- cfi_read_query(flash, 0x12) == 'Y' )) {
- cfi_cmd(flash, 0xff, 0);
- return 0;
- }
-
- flash->size = 1 << cfi_read_query(flash, 0x27);
- flash->size *= 4;
- block_count = cfi_read_query(flash, 0x2c);
- primary = cfi_read_query(flash, 0x15);
- if ( cfi_read_query(flash, primary + 4) == 0x30)
- reverse = (cfi_read_query(flash, 0x1) & 0x01);
- else
- reverse = (cfi_read_query(flash, primary+15) == 3);
-
- flash->sector_count = 0;
-
- for ( block = reverse ? block_count - 1 : 0;
- reverse ? block >= 0 : block < block_count;
- reverse ? block-- : block ++) {
- int sector_size =
- (cfi_read_query(flash, 0x2d + block*4+2) |
- (cfi_read_query(flash, 0x2d + block*4+3) << 8)) << 8;
- int sector_count =
- (cfi_read_query(flash, 0x2d + block*4+0) |
- (cfi_read_query(flash, 0x2d + block*4+1) << 8)) + 1;
- for(sector = 0; sector < sector_count; sector++) {
- flash->start[flash->sector_count++] = base + offset;
- offset += sector_size * 4;
- }
- }
- mfr_id = cfi_read_query(flash, 0x00);
- dev_id = cfi_read_query(flash, 0x01);
-
- cfi_cmd(flash, 0xff, 0);
-
- flash->flash_id = (mfr_id << 16) | dev_id;
-
- for (sector = 0; sector < flash->sector_count; sector++) {
- write32(flash->start[sector], 0x00600060);
- write32(flash->start[sector], 0x00d000d0);
- }
- cfi_cmd(flash, 0xff, 0);
-
- for (sector = 0; sector < flash->sector_count; sector++)
- flash->protect[sector] = 0;
-
- do_flash_erase = cfi_erase;
- write_dword = cfi_write_dword;
-
- return flash->size;
-}
-
-static ulong jedec_init(unsigned long base, flash_info_t *flash)
-{
- int i;
- int block, block_count;
- int sector, offset;
- int mfr_id, dev_id;
- flash->start[0] = base;
- cfi_cmd(flash, 0xF0, 0x000);
- cfi_cmd(flash, 0xAA, 0x555);
- cfi_cmd(flash, 0x55, 0x2AA);
- cfi_cmd(flash, 0x90, 0x555);
- mfr_id = cfi_read_query(flash, 0x000);
- dev_id = cfi_read_query(flash, 0x0001);
- cfi_cmd(flash, 0xf0, 0x000);
-
- for(i=0; i<sizeof(jedec_table)/sizeof(struct jedec_flash_info); i++) {
- if((jedec_table[i].mfr_id == mfr_id) &&
- (jedec_table[i].dev_id == dev_id)) {
-
- flash->flash_id = (mfr_id << 16) | dev_id;
- flash->size = 1 << jedec_table[0].DevSize;
- flash->size *= 4;
- block_count = jedec_table[i].NumEraseRegions;
- offset = 0;
- flash->sector_count = 0;
- for (block = 0; block < block_count; block++) {
- int sector_size = jedec_table[i].regions[block];
- int sector_count = (sector_size & 0xff) + 1;
- sector_size >>= 8;
- for (sector=0; sector<sector_count; sector++) {
- flash->start[flash->sector_count++] =
- base + offset;
- offset += sector_size * 4;
- }
- }
- break;
- }
- }
-
- for (sector = 0; sector < flash->sector_count; sector++)
- flash->protect[sector] = 0;
-
- do_flash_erase = jedec_erase;
- write_dword = jedec_write_dword;
-
- return flash->size;
-}
-
-inline void mtibat1u(unsigned int x)
-{
- __asm__ __volatile__ ("mtspr 530, %0" :: "r" (x));
-}
-
-inline void mtibat1l(unsigned int x)
-{
- __asm__ __volatile__ ("mtspr 531, %0" :: "r" (x));
-}
-
-inline void mtdbat1u(unsigned int x)
-{
- __asm__ __volatile__ ("mtspr 538, %0" :: "r" (x));
-}
-
-inline void mtdbat1l(unsigned int x)
-{
- __asm__ __volatile__ ("mtspr 539, %0" :: "r" (x));
-}
-
-unsigned long flash_init (void)
-{
- unsigned long size = 0;
- int i;
- unsigned int msr;
-
- /* BAT1 */
- CONFIG_WRITE_WORD(ERCR3, 0x0C00000C);
- CONFIG_WRITE_WORD(ERCR4, 0x0800000C);
- msr = get_msr();
- set_msr(msr & ~(MSR_IR | MSR_DR));
- mtibat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
- mtibat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
- mtdbat1l(0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
- mtdbat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
- set_msr(msr);
-
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
- flash_info[i].flash_id = FLASH_UNKNOWN;
- size = cfi_init(FLASH_BASE0_PRELIM, &flash_info[0]);
- if (!size)
- size = jedec_init(FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN)
- printf ("# Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n",
- size, size<<20);
-
- return size;
-}
-
-void flash_print_info (flash_info_t *flash)
-{
- int i;
- int k;
- int size;
- int erased;
- volatile unsigned long *p;
-
- if (flash->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- flash_init();
- }
-
- if (flash->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (((flash->flash_id) >> 16) & 0xff) {
- case 0x01:
- printf ("AMD ");
- break;
- case 0x04:
- printf("FUJITSU ");
- break;
- case 0x20:
- printf("STM ");
- break;
- case 0xBF:
- printf("SST ");
- break;
- case 0x89:
- case 0xB0:
- printf("INTEL ");
- break;
- default:
- printf ("Unknown Vendor ");
- break;
- }
-
- switch ((flash->flash_id) & 0xffff) {
- case (uint16_t)AMD_ID_LV800T:
- printf ("AM29LV800T\n");
- break;
- case (uint16_t)AMD_ID_LV800B:
- printf ("AM29LV800B\n");
- break;
- case (uint16_t)AMD_ID_LV160T:
- printf ("AM29LV160T\n");
- break;
- case (uint16_t)AMD_ID_LV160B:
- printf ("AM29LV160B\n");
- break;
- case (uint16_t)AMD_ID_LV320T:
- printf ("AM29LV320T\n");
- break;
- case (uint16_t)AMD_ID_LV320B:
- printf ("AM29LV320B\n");
- break;
- case (uint16_t)INTEL_ID_28F800C3T:
- printf ("28F800C3T\n");
- break;
- case (uint16_t)INTEL_ID_28F800C3B:
- printf ("28F800C3B\n");
- break;
- case (uint16_t)INTEL_ID_28F160C3T:
- printf ("28F160C3T\n");
- break;
- case (uint16_t)INTEL_ID_28F160C3B:
- printf ("28F160C3B\n");
- break;
- case (uint16_t)INTEL_ID_28F320C3T:
- printf ("28F320C3T\n");
- break;
- case (uint16_t)INTEL_ID_28F320C3B:
- printf ("28F320C3B\n");
- break;
- case (uint16_t)INTEL_ID_28F640C3T:
- printf ("28F640C3T\n");
- break;
- case (uint16_t)INTEL_ID_28F640C3B:
- printf ("28F640C3B\n");
- break;
- default:
- printf ("Unknown Chip Type\n");
- break;
- }
-
- if (flash->size >= (1 << 20)) {
- printf (" Size: %ld MB in %d Sectors\n",
- flash->size >> 20, flash->sector_count);
- } else {
- printf (" Size: %ld kB in %d Sectors\n",
- flash->size >> 10, flash->sector_count);
- }
-
- printf (" Sector Start Addresses:");
- for (i = 0; i < flash->sector_count; ++i) {
- /* Check if whole sector is erased*/
- if (i != (flash->sector_count-1))
- size = flash->start[i+1] - flash->start[i];
- else
- size = flash->start[0] + flash->size - flash->start[i];
-
- erased = 1;
- p = (volatile unsigned long *)flash->start[i];
- size = size >> 2; /* divide by 4 for longword access */
- for (k=0; k<size; k++) {
- if (*p++ != 0xffffffff) {
- erased = 0;
- break;
- }
- }
-
- if ((i % 5) == 0)
- printf ("\n ");
-
- printf (" %08lX%s%s",
- flash->start[i],
- erased ? " E" : " ",
- flash->protect[i] ? "RO " : " ");
- }
- printf ("\n");
-}
+++ /dev/null
-/*
- * board/eva/phantom.c
- *
- * Phantom RTC device driver for EVA
- *
- * Author: Sangmoon Kim
- * dogoil@etinsys.com
- *
- * Copyright 2002 Etinsys Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <rtc.h>
-
-#if defined(CONFIG_CMD_DATE)
-
-#define RTC_BASE (CONFIG_SYS_NVRAM_BASE_ADDR + 0x7fff8)
-
-#define RTC_YEAR ( RTC_BASE + 7 )
-#define RTC_MONTH ( RTC_BASE + 6 )
-#define RTC_DAY_OF_MONTH ( RTC_BASE + 5 )
-#define RTC_DAY_OF_WEEK ( RTC_BASE + 4 )
-#define RTC_HOURS ( RTC_BASE + 3 )
-#define RTC_MINUTES ( RTC_BASE + 2 )
-#define RTC_SECONDS ( RTC_BASE + 1 )
-#define RTC_CENTURY ( RTC_BASE + 0 )
-
-#define RTC_CONTROLA RTC_CENTURY
-#define RTC_CONTROLB RTC_SECONDS
-#define RTC_CONTROLC RTC_DAY_OF_WEEK
-
-#define RTC_CA_WRITE 0x80
-#define RTC_CA_READ 0x40
-
-#define RTC_CB_OSC_DISABLE 0x80
-
-#define RTC_CC_BATTERY_FLAG 0x80
-#define RTC_CC_FREQ_TEST 0x40
-
-
-static int phantom_flag = -1;
-static int century_flag = -1;
-
-static uchar rtc_read(unsigned int addr)
-{
- return *(volatile unsigned char *)(addr);
-}
-
-static void rtc_write(unsigned int addr, uchar val)
-{
- *(volatile unsigned char *)(addr) = val;
-}
-
-static unsigned char phantom_rtc_sequence[] = {
- 0xc5, 0x3a, 0xa3, 0x5c, 0xc5, 0x3a, 0xa3, 0x5c
-};
-
-static unsigned char* phantom_rtc_read(int addr, unsigned char rtc[8])
-{
- int i, j;
- unsigned char v;
- unsigned char save = rtc_read(addr);
-
- for (j = 0; j < 8; j++) {
- v = phantom_rtc_sequence[j];
- for (i = 0; i < 8; i++) {
- rtc_write(addr, v & 1);
- v >>= 1;
- }
- }
- for (j = 0; j < 8; j++) {
- v = 0;
- for (i = 0; i < 8; i++) {
- if(rtc_read(addr) & 1)
- v |= 1 << i;
- }
- rtc[j] = v;
- }
- rtc_write(addr, save);
- return rtc;
-}
-
-static void phantom_rtc_write(int addr, unsigned char rtc[8])
-{
- int i, j;
- unsigned char v;
- unsigned char save = rtc_read(addr);
- for (j = 0; j < 8; j++) {
- v = phantom_rtc_sequence[j];
- for (i = 0; i < 8; i++) {
- rtc_write(addr, v & 1);
- v >>= 1;
- }
- }
- for (j = 0; j < 8; j++) {
- v = rtc[j];
- for (i = 0; i < 8; i++) {
- rtc_write(addr, v & 1);
- v >>= 1;
- }
- }
- rtc_write(addr, save);
-}
-
-static int get_phantom_flag(void)
-{
- int i;
- unsigned char rtc[8];
-
- phantom_rtc_read(RTC_BASE, rtc);
-
- for(i = 1; i < 8; i++) {
- if (rtc[i] != rtc[0])
- return 1;
- }
- return 0;
-}
-
-void rtc_reset(void)
-{
- if (phantom_flag < 0)
- phantom_flag = get_phantom_flag();
-
- if (phantom_flag) {
- unsigned char rtc[8];
- phantom_rtc_read(RTC_BASE, rtc);
- if(rtc[4] & 0x30) {
- printf( "real-time-clock was stopped. Now starting...\n" );
- rtc[4] &= 0x07;
- phantom_rtc_write(RTC_BASE, rtc);
- }
- } else {
- uchar reg_a, reg_b, reg_c;
- reg_a = rtc_read( RTC_CONTROLA );
- reg_b = rtc_read( RTC_CONTROLB );
-
- if ( reg_b & RTC_CB_OSC_DISABLE )
- {
- printf( "real-time-clock was stopped. Now starting...\n" );
- reg_a |= RTC_CA_WRITE;
- reg_b &= ~RTC_CB_OSC_DISABLE;
- rtc_write( RTC_CONTROLA, reg_a );
- rtc_write( RTC_CONTROLB, reg_b );
- }
-
- /* make sure read/write clock register bits are cleared */
- reg_a &= ~( RTC_CA_WRITE | RTC_CA_READ );
- rtc_write( RTC_CONTROLA, reg_a );
-
- reg_c = rtc_read( RTC_CONTROLC );
- if (( reg_c & RTC_CC_BATTERY_FLAG ) == 0 )
- printf( "RTC battery low. Clock setting may not be reliable.\n");
- }
-}
-
-static int get_century_flag(void)
-{
- int flag = 0;
- int bcd, century;
- bcd = rtc_read( RTC_CENTURY );
- century = bcd2bin( bcd & 0x3F );
- rtc_write( RTC_CENTURY, bin2bcd(century+1));
- if (bcd == rtc_read( RTC_CENTURY ))
- flag = 1;
- rtc_write( RTC_CENTURY, bcd);
- return flag;
-}
-
-int rtc_get( struct rtc_time *tmp)
-{
- if (phantom_flag < 0)
- phantom_flag = get_phantom_flag();
-
- if (phantom_flag)
- {
- unsigned char rtc[8];
-
- phantom_rtc_read(RTC_BASE, rtc);
-
- tmp->tm_sec = bcd2bin(rtc[1] & 0x7f);
- tmp->tm_min = bcd2bin(rtc[2] & 0x7f);
- tmp->tm_hour = bcd2bin(rtc[3] & 0x1f);
- tmp->tm_wday = bcd2bin(rtc[4] & 0x7);
- tmp->tm_mday = bcd2bin(rtc[5] & 0x3f);
- tmp->tm_mon = bcd2bin(rtc[6] & 0x1f);
- tmp->tm_year = bcd2bin(rtc[7]) + 1900;
- tmp->tm_yday = 0;
- tmp->tm_isdst = 0;
-
- if( (rtc[3] & 0x80) && (rtc[3] & 0x40) ) tmp->tm_hour += 12;
- if (tmp->tm_year < 1970) tmp->tm_year += 100;
- } else {
- uchar sec, min, hour;
- uchar mday, wday, mon, year;
-
- int century;
-
- uchar reg_a;
-
- if (century_flag < 0)
- century_flag = get_century_flag();
-
- reg_a = rtc_read( RTC_CONTROLA );
- /* lock clock registers for read */
- rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_READ ));
-
- sec = rtc_read( RTC_SECONDS );
- min = rtc_read( RTC_MINUTES );
- hour = rtc_read( RTC_HOURS );
- mday = rtc_read( RTC_DAY_OF_MONTH );
- wday = rtc_read( RTC_DAY_OF_WEEK );
- mon = rtc_read( RTC_MONTH );
- year = rtc_read( RTC_YEAR );
- century = rtc_read( RTC_CENTURY );
-
- /* unlock clock registers after read */
- rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_READ ));
-
- tmp->tm_sec = bcd2bin( sec & 0x7F );
- tmp->tm_min = bcd2bin( min & 0x7F );
- tmp->tm_hour = bcd2bin( hour & 0x3F );
- tmp->tm_mday = bcd2bin( mday & 0x3F );
- tmp->tm_mon = bcd2bin( mon & 0x1F );
- tmp->tm_wday = bcd2bin( wday & 0x07 );
-
- if (century_flag) {
- tmp->tm_year = bcd2bin( year ) +
- ( bcd2bin( century & 0x3F ) * 100 );
- } else {
- tmp->tm_year = bcd2bin( year ) + 1900;
- if (tmp->tm_year < 1970) tmp->tm_year += 100;
- }
-
- tmp->tm_yday = 0;
- tmp->tm_isdst= 0;
- }
-
- return 0;
-}
-
-int rtc_set( struct rtc_time *tmp )
-{
- if (phantom_flag < 0)
- phantom_flag = get_phantom_flag();
-
- if (phantom_flag) {
- uint year;
- unsigned char rtc[8];
-
- year = tmp->tm_year;
- year -= (year < 2000) ? 1900 : 2000;
-
- rtc[0] = bin2bcd(0);
- rtc[1] = bin2bcd(tmp->tm_sec);
- rtc[2] = bin2bcd(tmp->tm_min);
- rtc[3] = bin2bcd(tmp->tm_hour);
- rtc[4] = bin2bcd(tmp->tm_wday);
- rtc[5] = bin2bcd(tmp->tm_mday);
- rtc[6] = bin2bcd(tmp->tm_mon);
- rtc[7] = bin2bcd(year);
-
- phantom_rtc_write(RTC_BASE, rtc);
- } else {
- uchar reg_a;
- if (century_flag < 0)
- century_flag = get_century_flag();
-
- /* lock clock registers for write */
- reg_a = rtc_read( RTC_CONTROLA );
- rtc_write( RTC_CONTROLA, ( reg_a | RTC_CA_WRITE ));
-
- rtc_write( RTC_MONTH, bin2bcd( tmp->tm_mon ));
-
- rtc_write( RTC_DAY_OF_WEEK, bin2bcd( tmp->tm_wday ));
- rtc_write( RTC_DAY_OF_MONTH, bin2bcd( tmp->tm_mday ));
- rtc_write( RTC_HOURS, bin2bcd( tmp->tm_hour ));
- rtc_write( RTC_MINUTES, bin2bcd( tmp->tm_min ));
- rtc_write( RTC_SECONDS, bin2bcd( tmp->tm_sec ));
-
- /* break year up into century and year in century */
- if (century_flag) {
- rtc_write( RTC_YEAR, bin2bcd( tmp->tm_year % 100 ));
- rtc_write( RTC_CENTURY, bin2bcd( tmp->tm_year / 100 ));
- reg_a &= 0xc0;
- reg_a |= bin2bcd( tmp->tm_year / 100 );
- } else {
- rtc_write(RTC_YEAR, bin2bcd(tmp->tm_year -
- ((tmp->tm_year < 2000) ? 1900 : 2000)));
- }
-
- /* unlock clock registers after read */
- rtc_write( RTC_CONTROLA, ( reg_a & ~RTC_CA_WRITE ));
- }
-
- return 0;
-}
-
-#endif
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = kvme080.o multiverse.o
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Sangmoon Kim, Etin Systems. dogoil@etinsys.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <pci.h>
-#include <i2c.h>
-#include <netdev.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-
-int checkboard(void)
-{
- puts ("Board: KVME080\n");
- return 0;
-}
-
-unsigned long setdram(int m, int row, int col, int bank)
-{
- int i;
- unsigned long start, end;
- uint32_t mccr1;
- uint32_t mear1 = 0, emear1 = 0, msar1 = 0, emsar1 = 0;
- uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
- uint8_t mber = 0;
-
- CONFIG_READ_WORD(MCCR1, mccr1);
- mccr1 &= 0xffff0000;
-
- start = CONFIG_SYS_SDRAM_BASE;
- end = start + (1 << (col + row + 3) ) * bank - 1;
-
- for (i = 0; i < m; i++) {
- mccr1 |= ((row == 13)? 2 : (bank == 4)? 0 : 3) << i * 2;
- if (i < 4) {
- msar1 |= ((start >> 20) & 0xff) << i * 8;
- emsar1 |= ((start >> 28) & 0xff) << i * 8;
- mear1 |= ((end >> 20) & 0xff) << i * 8;
- emear1 |= ((end >> 28) & 0xff) << i * 8;
- } else {
- msar2 |= ((start >> 20) & 0xff) << (i-4) * 8;
- emsar2 |= ((start >> 28) & 0xff) << (i-4) * 8;
- mear2 |= ((end >> 20) & 0xff) << (i-4) * 8;
- emear2 |= ((end >> 28) & 0xff) << (i-4) * 8;
- }
- mber |= 1 << i;
- start += (1 << (col + row + 3) ) * bank;
- end += (1 << (col + row + 3) ) * bank;
- }
- for (; i < 8; i++) {
- if (i < 4) {
- msar1 |= 0xff << i * 8;
- emsar1 |= 0x30 << i * 8;
- mear1 |= 0xff << i * 8;
- emear1 |= 0x30 << i * 8;
- } else {
- msar2 |= 0xff << (i-4) * 8;
- emsar2 |= 0x30 << (i-4) * 8;
- mear2 |= 0xff << (i-4) * 8;
- emear2 |= 0x30 << (i-4) * 8;
- }
- }
-
- CONFIG_WRITE_WORD(MCCR1, mccr1);
- CONFIG_WRITE_WORD(MSAR1, msar1);
- CONFIG_WRITE_WORD(EMSAR1, emsar1);
- CONFIG_WRITE_WORD(MEAR1, mear1);
- CONFIG_WRITE_WORD(EMEAR1, emear1);
- CONFIG_WRITE_WORD(MSAR2, msar2);
- CONFIG_WRITE_WORD(EMSAR2, emsar2);
- CONFIG_WRITE_WORD(MEAR2, mear2);
- CONFIG_WRITE_WORD(EMEAR2, emear2);
- CONFIG_WRITE_BYTE(MBER, mber);
-
- return (1 << (col + row + 3) ) * bank * m;
-}
-
-phys_size_t initdram(int board_type)
-{
- unsigned int msr;
- long int size = 0;
-
- msr = mfmsr();
- mtmsr(msr & ~(MSR_IR | MSR_DR));
- mtspr(IBAT2L, CONFIG_SYS_IBAT0L + 0x10000000);
- mtspr(IBAT2U, CONFIG_SYS_IBAT0U + 0x10000000);
- mtspr(DBAT2L, CONFIG_SYS_DBAT0L + 0x10000000);
- mtspr(DBAT2U, CONFIG_SYS_DBAT0U + 0x10000000);
- mtmsr(msr);
-
- if (setdram(2,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x20000000))
- size = 0x20000000; /* 512MB */
- else if (setdram(1,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
- size = 0x10000000; /* 256MB */
- else if (setdram(2,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
- size = 0x10000000; /* 256MB */
- else if (setdram(1,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
- size = 0x08000000; /* 128MB */
- else if (setdram(2,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
- size = 0x08000000; /* 128MB */
- else if (setdram(1,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x04000000))
- size = 0x04000000; /* 64MB */
-
- msr = mfmsr();
- mtmsr(msr & ~(MSR_IR | MSR_DR));
- mtspr(IBAT2L, CONFIG_SYS_IBAT2L);
- mtspr(IBAT2U, CONFIG_SYS_IBAT2U);
- mtspr(DBAT2L, CONFIG_SYS_DBAT2L);
- mtspr(DBAT2U, CONFIG_SYS_DBAT2U);
- mtmsr(msr);
-
- return size;
-}
-
-struct pci_controller hose;
-
-void pci_init_board(void)
-{
- pci_mpc824x_init(&hose);
-}
-
-int board_early_init_f(void)
-{
- *(volatile unsigned char *)(0xff080120) = 0xfb;
-
- return 0;
-}
-
-int board_early_init_r(void)
-{
- unsigned int msr;
-
- CONFIG_WRITE_WORD(ERCR1, 0x95ff8000);
- CONFIG_WRITE_WORD(ERCR3, 0x0c00000e);
- CONFIG_WRITE_WORD(ERCR4, 0x0800000e);
-
- msr = mfmsr();
- mtmsr(msr & ~(MSR_IR | MSR_DR));
- mtspr(IBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
- mtspr(IBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
- mtspr(DBAT1L, 0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT);
- mtspr(DBAT1U, 0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
- mtmsr(msr);
-
- return 0;
-}
-
-extern int multiverse_init(void);
-
-int misc_init_r(void)
-{
- multiverse_init();
- return 0;
-}
-
-void *nvram_read(void *dest, const long src, size_t count)
-{
- volatile uchar *d = (volatile uchar*) dest;
- volatile uchar *s = (volatile uchar*) src;
- while(count--) {
- *d++ = *s++;
- asm volatile("sync");
- }
- return dest;
-}
-
-void nvram_write(long dest, const void *src, size_t count)
-{
- volatile uchar *d = (volatile uchar*)dest;
- volatile uchar *s = (volatile uchar*)src;
- while(count--) {
- *d++ = *s++;
- asm volatile("sync");
- }
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
+++ /dev/null
-/*
- * multiverse.c
- *
- * VME driver for Multiverse
- *
- * Author : Sangmoon Kim
- * dogoil@etinsys.com
- *
- * Copyright 2005 ETIN SYSTEMS Co.,Ltd.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <pci.h>
-#include <linux/compiler.h>
-
-#include "multiverse.h"
-
-static unsigned long vme_asi_addr;
-static unsigned long vme_iack_addr;
-static unsigned long pci_reg_addr;
-static unsigned long vme_reg_addr;
-
-int multiv_reset(unsigned long base)
-{
- writeb(0x09, base + VME_SLAVE32_AM);
- writeb(0x39, base + VME_SLAVE24_AM);
- writeb(0x29, base + VME_SLAVE16_AM);
- writeb(0x2f, base + VME_SLAVE_REG_AM);
- writeb((VME_A32_SLV_BUS >> 24) & 0xff, base + VME_SLAVE32_A);
- writeb((VME_A24_SLV_BUS >> 16) & 0xff, base + VME_SLAVE24_A);
- writeb((VME_A16_SLV_BUS >> 8 ) & 0xff, base + VME_SLAVE16_A);
-#ifdef A32_SLV_WINDOW
- if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
- writeb(((~(VME_A32_SLV_SIZE-1)) >> 24) & 0xff,
- base + VME_SLAVE32_MASK);
- writeb(0x01, base + VME_SLAVE32_EN);
- } else {
- writeb(0xff, base + VME_SLAVE32_MASK);
- writeb(0x00, base + VME_SLAVE32_EN);
- }
-#else
- writeb(0xff, base + VME_SLAVE32_MASK);
- writeb(0x00, base + VME_SLAVE32_EN);
-#endif
-#ifdef A24_SLV_WINDOW
- if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
- writeb(((~(VME_A24_SLV_SIZE-1)) >> 16) & 0xff,
- base + VME_SLAVE24_MASK);
- writeb(0x01, base + VME_SLAVE24_EN);
- } else {
- writeb(0xff, base + VME_SLAVE24_MASK);
- writeb(0x00, base + VME_SLAVE24_EN);
- }
-#else
- writeb(0xff, base + VME_SLAVE24_MASK);
- writeb(0x00, base + VME_SLAVE24_EN);
-#endif
-#ifdef A16_SLV_WINDOW
- if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
- writeb(((~(VME_A16_SLV_SIZE-1)) >> 8) & 0xff,
- base + VME_SLAVE16_MASK);
- writeb(0x01, base + VME_SLAVE16_EN);
- } else {
- writeb(0xff, base + VME_SLAVE16_MASK);
- writeb(0x00, base + VME_SLAVE16_EN);
- }
-#else
- writeb(0xff, base + VME_SLAVE16_MASK);
- writeb(0x00, base + VME_SLAVE16_EN);
-#endif
-#ifdef REG_SLV_WINDOW
- if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
- writeb(((~(VME_REG_SLV_SIZE-1)) >> 16) & 0xff,
- base + VME_SLAVE_REG_MASK);
- writeb(0x01, base + VME_SLAVE_REG_EN);
- } else {
- writeb(0xf8, base + VME_SLAVE_REG_MASK);
- }
-#else
- writeb(0xf8, base + VME_SLAVE_REG_MASK);
-#endif
- writeb(0x09, base + VME_MASTER32_AM);
- writeb(0x39, base + VME_MASTER24_AM);
- writeb(0x29, base + VME_MASTER16_AM);
- writeb(0x2f, base + VME_MASTER_REG_AM);
- writel(0x00000000, base + VME_RMW_ADRS);
- writeb(0x00, base + VME_IRQ);
- writeb(0x00, base + VME_INT_EN);
- writel(0x00000000, base + VME_IRQ1_REG);
- writel(0x00000000, base + VME_IRQ2_REG);
- writel(0x00000000, base + VME_IRQ3_REG);
- writel(0x00000000, base + VME_IRQ4_REG);
- writel(0x00000000, base + VME_IRQ5_REG);
- writel(0x00000000, base + VME_IRQ6_REG);
- writel(0x00000000, base + VME_IRQ7_REG);
- return 0;
-}
-
-void multiv_auto_slot_id(unsigned long base)
-{
- __maybe_unused unsigned int vector;
- int slot_id = 1;
- if (readb(base + VME_CTRL) & VME_CTRL_SYSFAIL) {
- *(volatile unsigned int*)(base + VME_IRQ2_REG) = 0xfe;
- writeb(readb(base + VME_IRQ) | 0x04, base + VME_IRQ);
- writeb(readb(base + VME_CTRL) & ~VME_CTRL_SYSFAIL,
- base + VME_CTRL);
- while (readb(base + VME_STATUS) & VME_STATUS_SYSFAIL);
- if (readb(base + VME_STATUS) & VME_STATUS_SYSCON) {
- while (readb(base + VME_INT) & 0x04) {
- vector = *(volatile unsigned int*)
- (vme_iack_addr + VME_IACK2);
- *(unsigned char*)(vme_asi_addr + 0x7ffff)
- = (slot_id << 3) & 0xff;
- slot_id ++;
- if (slot_id > 31)
- break;
- }
- }
- }
-}
-
-int multiverse_init(void)
-{
- int i;
- pci_dev_t pdev;
- unsigned int bar[6];
-
- pdev = pci_find_device(0x1895, 0x0001, 0);
-
- if (pdev == 0)
- return -1;
-
- for (i = 0; i < 6; i++)
- pci_read_config_dword (pdev,
- PCI_BASE_ADDRESS_0 + i * 4, &bar[i]);
-
- pci_reg_addr = bar[0];
- vme_reg_addr = bar[1] + 0x00F00000;
- vme_iack_addr = bar[1] + 0x00200000;
- vme_asi_addr = bar[3];
-
- pci_write_config_dword (pdev, PCI_COMMAND,
- PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
-
- writel(0xFF000000, pci_reg_addr + P_TA1);
- writel(0x04, pci_reg_addr + P_IMG_CTRL1);
- writel(0xf0000000, pci_reg_addr + P_TA2);
- writel(0x04, pci_reg_addr + P_IMG_CTRL2);
- writel(0xF1000000, pci_reg_addr + P_TA3);
- writel(0x04, pci_reg_addr + P_IMG_CTRL3);
- writel(VME_A32_MSTR_BUS, pci_reg_addr + P_TA5);
- writel(~(VME_A32_MSTR_SIZE-1), pci_reg_addr + P_AM5);
- writel(0x04, pci_reg_addr + P_IMG_CTRL5);
-
- writel(VME_A32_SLV_BUS, pci_reg_addr + W_BA1);
- writel(~(VME_A32_SLV_SIZE-1), pci_reg_addr + W_AM1);
- writel(VME_A32_SLV_LOCAL, pci_reg_addr + W_TA1);
- writel(0x04, pci_reg_addr + W_IMG_CTRL1);
-
- writel(0xF0000000, pci_reg_addr + W_BA2);
- writel(0xFF000000, pci_reg_addr + W_AM2);
- writel(VME_A24_SLV_LOCAL, pci_reg_addr + W_TA2);
- writel(0x04, pci_reg_addr + W_IMG_CTRL2);
-
- writel(0xFF000000, pci_reg_addr + W_BA3);
- writel(0xFF000000, pci_reg_addr + W_AM3);
- writel(VME_A16_SLV_LOCAL, pci_reg_addr + W_TA3);
- writel(0x04, pci_reg_addr + W_IMG_CTRL3);
-
- writel(0x00000001, pci_reg_addr + W_ERR_CS);
- writel(0x00000001, pci_reg_addr + P_ERR_CS);
-
- multiv_reset(vme_reg_addr);
- writeb(readb(vme_reg_addr + VME_CTRL) | VME_CTRL_SHORT_D,
- vme_reg_addr + VME_CTRL);
-
- multiv_auto_slot_id(vme_reg_addr);
-
- return 0;
-}
+++ /dev/null
-/*
- * multiverse.h
- *
- * VME driver for Multiverse
- *
- * Author : Sangmoon Kim
- * dogoil@etinsys.com
- *
- * Copyright 2005 ETIN SYSTEMS Co.,Ltd.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __MULTIVERSE_H__
-#define __MULTIVERSE_H__
-
-#define VME_A32_MSTR_BUS 0x90000000
-#define VME_A32_MSTR_SIZE 0x01000000
-
-#define VME_A32_SLV_SIZE 0x01000000
-
-#define VME_A32_SLV_BUS 0x90000000
-#define VME_A24_SLV_BUS 0x00000000
-#define VME_A16_SLV_BUS 0x00000000
-
-#define VME_A32_SLV_LOCAL 0x00000000
-#define VME_A24_SLV_LOCAL 0x00000000
-#define VME_A16_SLV_LOCAL 0x00000000
-
-#define A32_SLV_WINDOW
-#undef A24_SLV_WINDOW
-#undef A16_SLV_WINDOW
-#undef REG_SLV_WINDOW
-
-/* PCI Registers */
-
-#define P_IMG_CTRL0 0x100
-#define P_BA0 0x104
-#define P_AM0 0x108
-#define P_TA0 0x10C
-#define P_IMG_CTRL1 0x110
-#define P_BA1 0x114
-#define P_AM1 0x118
-#define P_TA1 0x11C
-#define P_IMG_CTRL2 0x120
-#define P_BA2 0x124
-#define P_AM2 0x128
-#define P_TA2 0x12C
-#define P_IMG_CTRL3 0x130
-#define P_BA3 0x134
-#define P_AM3 0x138
-#define P_TA3 0x13C
-#define P_IMG_CTRL4 0x140
-#define P_BA4 0x144
-#define P_AM4 0x148
-#define P_TA4 0x14C
-#define P_IMG_CTRL5 0x150
-#define P_BA5 0x154
-#define P_AM5 0x158
-#define P_TA5 0x15C
-#define P_ERR_CS 0x160
-#define P_ERR_ADDR 0x164
-#define P_ERR_DATA 0x168
-
-#define WB_CONF_SPC_BAR 0x180
-#define W_IMG_CTRL1 0x184
-#define W_BA1 0x188
-#define W_AM1 0x18C
-#define W_TA1 0x190
-#define W_IMG_CTRL2 0x194
-#define W_BA2 0x198
-#define W_AM2 0x19C
-#define W_TA2 0x1A0
-#define W_IMG_CTRL3 0x1A4
-#define W_BA3 0x1A8
-#define W_AM3 0x1AC
-#define W_TA3 0x1B0
-#define W_IMG_CTRL4 0x1B4
-#define W_BA4 0x1B8
-#define W_AM4 0x1BC
-#define W_TA4 0x1C0
-#define W_IMG_CTRL5 0x1C4
-#define W_BA5 0x1C8
-#define W_AM5 0x1CC
-#define W_TA5 0x1D0
-#define W_ERR_CS 0x1D4
-#define W_ERR_ADDR 0x1D8
-#define W_ERR_DATA 0x1DC
-#define CNF_ADDR 0x1E0
-#define CNF_DATA 0x1E4
-#define INT_ACK 0x1E8
-#define ICR 0x1EC
-#define ISR 0x1F0
-
-/* VME registers */
-
-#define VME_SLAVE32_AM 0x03
-#define VME_SLAVE24_AM 0x02
-#define VME_SLAVE16_AM 0x01
-#define VME_SLAVE_REG_AM 0x00
-#define VME_SLAVE32_A 0x07
-#define VME_SLAVE24_A 0x06
-#define VME_SLAVE16_A 0x05
-#define VME_SLAVE_REG_A 0x04
-#define VME_SLAVE32_MASK 0x0B
-#define VME_SLAVE24_MASK 0x0A
-#define VME_SLAVE16_MASK 0x09
-#define VME_SLAVE_REG_MASK 0x08
-#define VME_SLAVE32_EN 0x0F
-#define VME_SLAVE24_EN 0x0E
-#define VME_SLAVE16_EN 0x0D
-#define VME_SLAVE_REG_EN 0x0C
-#define VME_MASTER32_AM 0x13
-#define VME_MASTER24_AM 0x12
-#define VME_MASTER16_AM 0x11
-#define VME_MASTER_REG_AM 0x10
-#define VME_RMW_ADRS 0x14
-#define VME_MBOX 0x18
-#define VME_STATUS 0x1E
-#define VME_CTRL 0x1C
-#define VME_IRQ 0x20
-#define VME_INT_EN 0x21
-#define VME_INT 0x22
-#define VME_IRQ1_REG 0x24
-#define VME_IRQ2_REG 0x28
-#define VME_IRQ3_REG 0x2C
-#define VME_IRQ4_REG 0x30
-#define VME_IRQ5_REG 0x34
-#define VME_IRQ6_REG 0x38
-#define VME_IRQ7_REG 0x3C
-
-/* VME control register */
-
-#define VME_CTRL_BRDRST 0x01
-#define VME_CTRL_SYSRST 0x02
-#define VME_CTRL_RMW 0x04
-#define VME_CTRL_SHORT_D 0x08
-#define VME_CTRL_SYSFAIL 0x10
-#define VME_CTRL_VOWN 0x20
-#define VME_CTRL_A16_REG_MODE 0x40
-
-/* VME status register */
-
-#define VME_STATUS_SYSCON 0x01
-#define VME_STATUS_SYSFAIL 0x02
-#define VME_STATUS_ACFAIL 0x04
-#define VME_STATUS_SYSRST 0x08
-#define VME_STATUS_VOWN 0x10
-
-/* Interrupt types */
-
-#define LVL1 0x0002
-#define LVL2 0x0004
-#define LVL3 0x0008
-#define LVL4 0x0010
-#define LVL5 0x0020
-#define LVL6 0x0040
-#define LVL7 0x0080
-#define MULTIVERSE_INTI_INT 0x0100
-#define MULTIVERSE_WB_INT 0x0200
-#define MULTIVERSE_PCI_INT 0x0400
-
-/* interrupt acknowledge */
-
-#define VME_IACK1 0x04
-#define VME_IACK2 0x08
-#define VME_IACK3 0x0c
-#define VME_IACK4 0x10
-#define VME_IACK5 0x14
-#define VME_IACK6 0x18
-#define VME_IACK7 0x1c
-
-#endif /* __MULTIVERSE_H__ */
}
switch (serdes2_prtcl) {
+#ifdef CONFIG_PPC_B4420
+ case 0x9d:
+#endif
case 0x9E:
case 0x9A:
case 0x98:
* For this SerDes2's Refclk1 need to be set to 100MHz
*/
switch (serdes2_prtcl) {
+#ifdef CONFIG_PPC_B4420
+ case 0x9d:
+#endif
case 0x9E:
case 0x9A:
case 0xb2:
{
FPWV *addr;
int flag, prot, sect, count;
- ulong type, start, last;
+ ulong type, start;
int rcode = 0, flashtype = 0;
if ((s_first < 0) || (s_first > s_last)) {
flag = disable_interrupts();
start = get_timer(0);
- last = start;
if ((s_last - s_first) == (CONFIG_SYS_SST_SECT - 1)) {
if (prot == 0) {
{
ulong wp, count;
u16 data;
- int rc, port_width;
+ int rc;
if (info->flash_id == FLASH_UNKNOWN)
return 4;
/* get lower word aligned address */
wp = addr;
- port_width = sizeof(FPW);
/* handle unaligned start bytes */
if (wp & 1) {
+++ /dev/null
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := mpc8260ads.o flash.o
+++ /dev/null
-/*
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
- * Add support the Sharp chips on the mpc8260ads.
- * I started with board/ip860/flash.c and made changes I found in
- * the MTD project by David Schleef.
- *
- * (C) Copyright 2003 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- * Re-written to support multi-bank flash SIMMs.
- * Added support for real protection and JFFS2.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-
-/* Intel-compatible flash ID */
-#define INTEL_COMPAT 0x89898989
-#define INTEL_ALT 0xB0B0B0B0
-
-/* Intel-compatible flash commands */
-#define INTEL_PROGRAM 0x10101010
-#define INTEL_ERASE 0x20202020
-#define INTEL_CLEAR 0x50505050
-#define INTEL_LOCKBIT 0x60606060
-#define INTEL_PROTECT 0x01010101
-#define INTEL_STATUS 0x70707070
-#define INTEL_READID 0x90909090
-#define INTEL_CONFIRM 0xD0D0D0D0
-#define INTEL_RESET 0xFFFFFFFF
-
-/* Intel-compatible flash status bits */
-#define INTEL_FINISHED 0x80808080
-#define INTEL_OK 0x80808080
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-/*-----------------------------------------------------------------------
- * This board supports 32-bit wide flash SIMMs (4x8-bit configuration.)
- * Up to 32MB of flash supported (up to 4 banks.)
- * BCSR is used for flash presence detect (page 4-65 of the User's Manual)
- *
- * The following code can not run from flash!
- */
-unsigned long flash_init (void)
-{
- ulong size = 0, sect_start, sect_size = 0, bank_size;
- ushort sect_count = 0;
- int i, j, nbanks;
- vu_long *addr = (vu_long *)CONFIG_SYS_FLASH_BASE;
- vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
-
- switch (bcsr[2] & 0xF) {
- case 0:
- nbanks = 4;
- break;
- case 1:
- nbanks = 2;
- break;
- case 2:
- nbanks = 1;
- break;
- default: /* Unsupported configurations */
- nbanks = CONFIG_SYS_MAX_FLASH_BANKS;
- }
-
- if (nbanks > CONFIG_SYS_MAX_FLASH_BANKS)
- nbanks = CONFIG_SYS_MAX_FLASH_BANKS;
-
- for (i = 0; i < nbanks; i++) {
- *addr = INTEL_READID; /* Read Intelligent Identifier */
- if ((addr[0] == INTEL_COMPAT) || (addr[0] == INTEL_ALT)) {
- switch (addr[1]) {
- case SHARP_ID_28F016SCL:
- case SHARP_ID_28F016SCZ:
- flash_info[i].flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
- sect_count = 32;
- sect_size = 0x40000;
- break;
- default:
- flash_info[i].flash_id = FLASH_UNKNOWN;
- sect_count = CONFIG_SYS_MAX_FLASH_SECT;
- sect_size =
- CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_BANKS / CONFIG_SYS_MAX_FLASH_SECT;
- }
- }
- else
- flash_info[i].flash_id = FLASH_UNKNOWN;
- if (flash_info[i].flash_id == FLASH_UNKNOWN) {
- printf("### Unknown flash ID %08lX %08lX at address %08lX ###\n",
- addr[0], addr[1], (ulong)addr);
- size = 0;
- *addr = INTEL_RESET; /* Reset bank to Read Array mode */
- break;
- }
- flash_info[i].sector_count = sect_count;
- flash_info[i].size = bank_size = sect_size * sect_count;
- size += bank_size;
- sect_start = (ulong)addr;
- for (j = 0; j < sect_count; j++) {
- addr = (vu_long *)sect_start;
- flash_info[i].start[j] = sect_start;
- flash_info[i].protect[j] = (addr[2] == 0x01010101);
- sect_start += sect_size;
- }
- *addr = INTEL_RESET; /* Reset bank to Read Array mode */
- addr = (vu_long *)sect_start;
- }
-
- if (size == 0) { /* Unknown flash, fill with hard-coded values */
- sect_start = CONFIG_SYS_FLASH_BASE;
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- flash_info[i].size = CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_BANKS;
- flash_info[i].sector_count = sect_count;
- for (j = 0; j < sect_count; j++) {
- flash_info[i].start[j] = sect_start;
- flash_info[i].protect[j] = 0;
- sect_start += sect_size;
- }
- }
- size = CONFIG_SYS_FLASH_SIZE;
- }
- else
- for (i = nbanks; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- flash_info[i].size = 0;
- flash_info[i].sector_count = 0;
- }
-
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[0]);
-#endif
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL: printf ("Intel "); break;
- case FLASH_MAN_SHARP: printf ("Sharp "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
- break;
- case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
- break;
- case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
- break;
- case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-}
-
-/*-----------------------------------------------------------------------
- */
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong start, now, last;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
- && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- vu_long *addr = (vu_long *)(info->start[sect]);
-
- last = start = get_timer (0);
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Clear Status Register */
- *addr = INTEL_CLEAR;
- /* Single Block Erase Command */
- *addr = INTEL_ERASE;
- /* Confirm */
- *addr = INTEL_CONFIRM;
-
- if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
- /* Resume Command, as per errata update */
- *addr = INTEL_CONFIRM;
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = INTEL_RESET; /* reset bank */
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
-
- if (*addr != INTEL_OK) {
- printf("Block erase failed at %08X, CSR=%08X\n",
- (uint)addr, (uint)*addr);
- *addr = INTEL_RESET; /* reset bank */
- return 1;
- }
-
- /* reset to read mode */
- *addr = INTEL_RESET;
- }
- }
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- ulong start;
- int rc = 0;
- int flag;
- vu_long *addr = (vu_long *)dest;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- return (2);
- }
-
- *addr = INTEL_CLEAR; /* Clear status register */
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Write Command */
- *addr = INTEL_PROGRAM;
-
- /* Write Data */
- *addr = data;
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- printf("Write timed out\n");
- rc = 1;
- break;
- }
- }
- if (*addr != INTEL_OK) {
- printf ("Write failed at %08X, CSR=%08X\n", (uint)addr, (uint)*addr);
- rc = 1;
- }
-
- *addr = INTEL_RESET; /* Reset to read array mode */
-
- return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- *(vu_long *)wp = INTEL_RESET; /* Reset to read array mode */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- rc = write_word(info, wp, data);
-
- return rc;
-}
-
-/*-----------------------------------------------------------------------
- * Set/Clear sector's lock bit, returns:
- * 0 - OK
- * 1 - Error (timeout, voltage problems, etc.)
- */
-int flash_real_protect(flash_info_t *info, long sector, int prot)
-{
- ulong start;
- int i;
- int rc = 0;
- vu_long *addr = (vu_long *)(info->start[sector]);
- int flag = disable_interrupts();
-
- *addr = INTEL_CLEAR; /* Clear status register */
- if (prot) { /* Set sector lock bit */
- *addr = INTEL_LOCKBIT; /* Sector lock bit */
- *addr = INTEL_PROTECT; /* set */
- }
- else { /* Clear sector lock bit */
- *addr = INTEL_LOCKBIT; /* All sectors lock bits */
- *addr = INTEL_CONFIRM; /* clear */
- }
-
- start = get_timer(0);
- while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
- if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
- printf("Flash lock bit operation timed out\n");
- rc = 1;
- break;
- }
- }
-
- if (*addr != INTEL_OK) {
- printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
- (uint)addr, (uint)*addr);
- rc = 1;
- }
-
- if (!rc)
- info->protect[sector] = prot;
-
- /*
- * Clear lock bit command clears all sectors lock bits, so
- * we have to restore lock bits of protected sectors.
- */
- if (!prot)
- for (i = 0; i < info->sector_count; i++)
- if (info->protect[i]) {
- addr = (vu_long *)(info->start[i]);
- *addr = INTEL_LOCKBIT; /* Sector lock bit */
- *addr = INTEL_PROTECT; /* set */
- udelay(CONFIG_SYS_FLASH_LOCK_TOUT * 1000);
- }
-
- if (flag)
- enable_interrupts();
-
- *addr = INTEL_RESET; /* Reset to read array mode */
-
- return rc;
-}
+++ /dev/null
-/*
- * (C) Copyright 2001-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Modified during 2001 by
- * Advanced Communications Technologies (Australia) Pty. Ltd.
- * Howard Walker, Tuong Vu-Dinh
- *
- * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
- * Added support for the 16M dram simm on the 8260ads boards
- *
- * (C) Copyright 2003-2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init.
- *
- * Copyright (c) 2005 MontaVista Software, Inc.
- * Vitaly Bordug <vbordug@ru.mvista.com>
- * Added support for PCI.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <asm/m8260_pci.h>
-#include <i2c.h>
-#include <spd.h>
-#include <miiphy.h>
-#ifdef CONFIG_PCI
-#include <pci.h>
-#endif
-#ifdef CONFIG_OF_LIBFDT
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1)
-#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2)
-#define CONFIG_SYS_FCC3 (CONFIG_ETHER_INDEX == 3)
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
- /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
- /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
- /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
- /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
- /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
- /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
- /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
- /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
- /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
- /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
- /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
- /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
- /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
- /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
- /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
- /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
- /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
- /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
- /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
- /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
- /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
- /* PA9 */ { 0, 0, 0, 0, 0, 0 }, /* PA9 */
- /* PA8 */ { 0, 0, 0, 0, 0, 0 }, /* PA8 */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
- },
-
- /* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
- /* PB16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
- /* PB15 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
- /* PB14 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
- /* PB13 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:COL */
- /* PB12 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
- /* PB11 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB10 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB9 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB8 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB7 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB6 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB5 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB4 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
- /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
- /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
- /* PC22 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Tx Clock (CLK10) */
- /* PC21 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII Rx Clock (CLK11) */
- /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
- /* PC19 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
- /* PC18 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
- /* PC17 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK15) */
- /* PC16 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK16) */
-#else
- /* PC19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
- /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
- /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
- /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
- /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
- /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
- /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
-#else
- /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* FETHMDC */
- /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* FETHMDIO */
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
- /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
- /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
- /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 UART RxD */
- /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 UART TxD */
- /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
- /* PD28 */ { 0, 1, 0, 0, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 1, 1, 1, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
- /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-void reset_phy (void)
-{
- vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
-
- /* Reset the PHY */
-#if CONFIG_SYS_PHY_ADDR == 0
- bcsr[1] &= ~(FETHIEN1 | FETH1_RST);
- udelay(2);
- bcsr[1] |= FETH1_RST;
-#else
- bcsr[3] &= ~(FETHIEN2 | FETH2_RST);
- udelay(2);
- bcsr[3] |= FETH2_RST;
-#endif /* CONFIG_SYS_PHY_ADDR == 0 */
- udelay(1000);
-#ifdef CONFIG_MII
-#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
- /*
- * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
- * Enable autonegotiation.
- */
- bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, 16, 0x610);
- bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_BMCR,
- BMCR_ANENABLE | BMCR_ANRESTART);
-#else
- /*
- * Ethernet PHY is configured (by means of configuration pins)
- * to work at 10Mb/s only. We reconfigure it using MII
- * to advertise all capabilities, including 100Mb/s, and
- * restart autonegotiation.
- */
-
- /* Advertise all capabilities */
- bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_ADVERTISE, 0x01E1);
-
- /* Do not bypass Rx/Tx (de)scrambler */
- bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_FCSCOUNTER, 0x0000);
-
- bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, MII_BMCR,
- BMCR_ANENABLE | BMCR_ANRESTART);
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
-#endif /* CONFIG_MII */
-}
-
-#ifdef CONFIG_PCI
-typedef struct pci_ic_s {
- unsigned long pci_int_stat;
- unsigned long pci_int_mask;
-}pci_ic_t;
-#endif
-
-int board_early_init_f (void)
-{
- vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
-
-#ifdef CONFIG_PCI
- volatile pci_ic_t* pci_ic = (pci_ic_t *) CONFIG_SYS_PCI_INT;
-
- /* mask alll the PCI interrupts */
- pci_ic->pci_int_mask |= 0xfff00000;
-#endif
-#if (CONFIG_CONS_INDEX == 1) || (CONFIG_KGDB_INDEX == 1)
- bcsr[1] &= ~RS232EN_1;
-#endif
-#if (CONFIG_CONS_INDEX > 1) || (CONFIG_KGDB_INDEX > 1)
- bcsr[1] &= ~RS232EN_2;
-#endif
-
-#if CONFIG_ADSTYPE != CONFIG_SYS_8260ADS /* PCI mode can be selected */
-#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
- if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
- {
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-
- immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
- immap->im_siu_conf.sc_siumcr =
- (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
- | SIUMCR_LBPC01;
- }
-#endif /* CONFIG_ADSTYPE != CONFIG_SYS_8260ADS */
-
- return 0;
-}
-
-#define ns2clk(ns) (ns / (1000000000 / CONFIG_8260_CLKIN) + 1)
-
-phys_size_t initdram (int board_type)
-{
-#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
- long int msize = 32;
-#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
- long int msize = 64;
-#else
- long int msize = 16;
-#endif
-
-#ifndef CONFIG_SYS_RAMBOOT
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
- volatile uchar *ramaddr, c = 0xff;
- uint or;
- uint psdmr;
- uint psrt;
-
- int i;
-
- immap->im_siu_conf.sc_ppc_acr = 0x00000002;
- immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
- immap->im_siu_conf.sc_tescr1 = 0x00004000;
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-#ifdef CONFIG_SYS_LSDRAM_BASE
- /*
- Initialise local bus SDRAM only if the pins
- are configured as local bus pins and not as PCI.
- The configuration is determined by the HRCW.
- */
- if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
- memctl->memc_lsrt = CONFIG_SYS_LSRT;
-#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS /* CS3 */
- memctl->memc_or3 = 0xFF803280;
- memctl->memc_br3 = CONFIG_SYS_LSDRAM_BASE | 0x00001861;
-#else /* CS4 */
- memctl->memc_or4 = 0xFFC01480;
- memctl->memc_br4 = CONFIG_SYS_LSDRAM_BASE | 0x00001861;
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x28000000;
- ramaddr = (uchar *) CONFIG_SYS_LSDRAM_BASE;
- *ramaddr = c;
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x08000000;
- for (i = 0; i < 8; i++)
- *ramaddr = c;
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x18000000;
- *ramaddr = c;
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x40000000;
- }
-#endif /* CONFIG_SYS_LSDRAM_BASE */
-
- /* Init 60x bus SDRAM */
-#ifdef CONFIG_SPD_EEPROM
- {
- spd_eeprom_t spd;
- uint pbi, bsel, rowst, lsb, tmp;
-
- i2c_read (CONFIG_SPD_ADDR, 0, 1, (uchar *) & spd, sizeof (spd));
-
- /* Bank-based interleaving is not supported for physical bank
- sizes greater than 128MB which is encoded as 0x20 in SPD
- */
- pbi = (spd.row_dens > 32) ? 1 : CONFIG_SDRAM_PBI;
- msize = spd.nrows * (4 * spd.row_dens); /* Mixed size not supported */
- or = ~(msize - 1) << 20; /* SDAM */
- switch (spd.nbanks) { /* BPD */
- case 2:
- bsel = 1;
- break;
- case 4:
- bsel = 2;
- or |= 0x00002000;
- break;
- case 8:
- bsel = 3;
- or |= 0x00004000;
- break;
- }
- lsb = 3; /* For 64-bit port, lsb is 3 bits */
-
- if (pbi) { /* Bus partition depends on interleaving */
- rowst = 32 - (spd.nrow_addr + spd.ncol_addr + bsel + lsb);
- or |= (rowst << 9); /* ROWST */
- } else {
- rowst = 32 - (spd.nrow_addr + spd.ncol_addr + lsb);
- or |= ((rowst * 2 - 12) << 9); /* ROWST */
- }
- or |= ((spd.nrow_addr - 9) << 6); /* NUMR */
-
- psdmr = (pbi << 31); /* PBI */
- /* Bus multiplexing parameters */
- tmp = 32 - (lsb + spd.nrow_addr); /* Tables 10-19 and 10-20 */
- psdmr |= ((tmp - (rowst - 5) - 13) << 24); /* SDAM */
- psdmr |= ((tmp - 3 - 12) << 21); /* BSMA */
-
- tmp = (31 - lsb - 10) - tmp;
- /* Pin connected to SDA10 is (31 - lsb - 10).
- rowst is multiplexed over (32 - (lsb + spd.nrow_addr)),
- so (rowst + tmp) alternates with AP.
- */
- if (pbi) /* Table 10-7 */
- psdmr |= ((10 - (rowst + tmp)) << 18); /* SDA10 */
- else
- psdmr |= ((12 - (rowst + tmp)) << 18); /* SDA10 */
-
- /* SDRAM device-specific parameters */
- tmp = ns2clk (70); /* Refresh recovery is not in SPD, so assume 70ns */
- switch (tmp) { /* RFRC */
- case 1:
- case 2:
- psdmr |= (1 << 15);
- break;
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
- case 8:
- psdmr |= ((tmp - 2) << 15);
- break;
- default:
- psdmr |= (7 << 15);
- }
- psdmr |= (ns2clk (spd.trp) % 8 << 12); /* PRETOACT */
- psdmr |= (ns2clk (spd.trcd) % 8 << 9); /* ACTTORW */
- /* BL=0 because for 64-bit SDRAM burst length must be 4 */
- /* LDOTOPRE ??? */
- for (i = 0, tmp = spd.write_lat; (i < 4) && ((tmp & 1) == 0); i++)
- tmp >>= 1;
- switch (i) { /* WRC */
- case 0:
- case 1:
- psdmr |= (1 << 4);
- break;
- case 2:
- case 3:
- psdmr |= (i << 4);
- break;
- }
- /* EAMUX=0 - no external address multiplexing */
- /* BUFCMD=0 - no external buffers */
- for (i = 1, tmp = spd.cas_lat; (i < 3) && ((tmp & 1) == 0); i++)
- tmp >>= 1;
- psdmr |= i; /* CL */
-
- switch (spd.refresh & 0x7F) {
- case 1:
- tmp = 3900;
- break;
- case 2:
- tmp = 7800;
- break;
- case 3:
- tmp = 31300;
- break;
- case 4:
- tmp = 62500;
- break;
- case 5:
- tmp = 125000;
- break;
- default:
- tmp = 15625;
- }
- psrt = tmp / (1000000000 / CONFIG_8260_CLKIN *
- ((memctl->memc_mptpr >> 8) + 1)) - 1;
-#ifdef SPD_DEBUG
- printf ("\nDIMM type: %-18.18s\n", spd.mpart);
- printf ("SPD size: %d\n", spd.info_size);
- printf ("EEPROM size: %d\n", 1 << spd.chip_size);
- printf ("Memory type: %d\n", spd.mem_type);
- printf ("Row addr: %d\n", spd.nrow_addr);
- printf ("Column addr: %d\n", spd.ncol_addr);
- printf ("# of rows: %d\n", spd.nrows);
- printf ("Row density: %d\n", spd.row_dens);
- printf ("# of banks: %d\n", spd.nbanks);
- printf ("Data width: %d\n",
- 256 * spd.dataw_msb + spd.dataw_lsb);
- printf ("Chip width: %d\n", spd.primw);
- printf ("Refresh rate: %02X\n", spd.refresh);
- printf ("CAS latencies: %02X\n", spd.cas_lat);
- printf ("Write latencies: %02X\n", spd.write_lat);
- printf ("tRP: %d\n", spd.trp);
- printf ("tRCD: %d\n", spd.trcd);
-
- printf ("OR=%X, PSDMR=%08X, PSRT=%0X\n", or, psdmr, psrt);
-#endif /* SPD_DEBUG */
- }
-#else /* !CONFIG_SPD_EEPROM */
- or = CONFIG_SYS_OR2;
- psdmr = CONFIG_SYS_PSDMR;
- psrt = CONFIG_SYS_PSRT;
-#endif /* CONFIG_SPD_EEPROM */
- memctl->memc_psrt = psrt;
- memctl->memc_or2 = or;
- memctl->memc_br2 = CONFIG_SYS_SDRAM_BASE | 0x00000041;
- ramaddr = (uchar *) CONFIG_SYS_SDRAM_BASE;
- memctl->memc_psdmr = psdmr | 0x28000000; /* Precharge all banks */
- *ramaddr = c;
- memctl->memc_psdmr = psdmr | 0x08000000; /* CBR refresh */
- for (i = 0; i < 8; i++)
- *ramaddr = c;
-
- memctl->memc_psdmr = psdmr | 0x18000000; /* Mode Register write */
- *ramaddr = c;
- memctl->memc_psdmr = psdmr | 0x40000000; /* Refresh enable */
- *ramaddr = c;
-#endif /* CONFIG_SYS_RAMBOOT */
-
- /* return total 60x bus SDRAM size */
- return (msize * 1024 * 1024);
-}
-
-int checkboard (void)
-{
-#if CONFIG_ADSTYPE == CONFIG_SYS_8260ADS
- puts ("Board: Motorola MPC8260ADS\n");
-#elif CONFIG_ADSTYPE == CONFIG_SYS_8266ADS
- puts ("Board: Motorola MPC8266ADS\n");
-#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
- puts ("Board: Motorola PQ2FADS-ZU\n");
-#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
- puts ("Board: Motorola MPC8272ADS\n");
-#else
- puts ("Board: unknown\n");
-#endif
- return 0;
-}
-
-#ifdef CONFIG_PCI
-struct pci_controller hose;
-
-extern void pci_mpc8250_init(struct pci_controller *);
-
-void pci_init_board(void)
-{
- pci_mpc8250_init(&hose);
-}
-#endif
-
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
-}
-#endif
* VDD 5V: To the left (off)
* Hold Button: Down (off)
+To boot MX28EVK from SPI NOR flash, set the boot mode DIP switches as:
+
+ * Boot Mode Select: 0 0 1 0 (Boot from SSP2)
+ * JTAG PSWITCH RESET: To the right (reset disabled)
+ * Battery Source: Down
+ * Wall 5V: Up
+ * VDD 5V: To the left (off)
+ * Hold Button: Down (off)
Environment Storage
-------------------
-There are two targets for mx28evk:
+There are three targets for mx28evk:
"make mx28evk_config" - store environment variables into MMC
"make mx28evk_nand_config" - store environment variables into NAND flash
+or
+
+"make mx28evk_spi_config" - store enviroment variables into SPI NOR flash
+
Choose the target accordingly.
Note: The mx28evk board does not come with a NAND flash populated from the
factory. It comes with an empty slot (U23), which allows the insertion of a
48-pin TSOP flash device.
-Follow the instructions from doc/README.mxs to generate a bootable SD card.
+mx28evk does not come with SPI NOR flash populated from the factory either.
+It is possible to solder a SOIC memory on U49 or use a DIP8 on J89.
+To get SPI communication to work R320, R321,R322 and C178 need to be populated.
+Look in the schematics for the proper component values.
-Insert the SD card in slot 0, power up the board and U-boot will boot.
+Follow the instructions from doc/README.mxs to generate a bootable SD card or
+to generate a binary to be flashed into SPI NOR.
*(.__rel_dyn_end)
}
+ .hash : { *(.hash*) }
+
.end :
{
*(.__end)
.dynbss : { *(.dynbss) }
.dynstr : { *(.dynstr*) }
.dynamic : { *(.dynamic*) }
- .hash : { *(.hash*) }
+ .gnu.hash : { *(.gnu.hash) }
.plt : { *(.plt*) }
.interp : { *(.interp*) }
.gnu : { *(.gnu*) }
--- /dev/null
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ * Jason Liu <r64343@freescale.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ *
+ * Refer doc/README.imximage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+BOOT_FROM sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type Address Value
+ *
+ * where:
+ * Addr-type register length (1,2 or 4 bytes)
+ * Address absolute address of the register
+ * value value to be stored in the register
+ */
+DATA 4 0x020e0774 0x000C0000
+DATA 4 0x020e0754 0x00000000
+DATA 4 0x020e04ac 0x00000030
+DATA 4 0x020e04b0 0x00000030
+DATA 4 0x020e0464 0x00000030
+DATA 4 0x020e0490 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e0494 0x00000030
+DATA 4 0x020e04a0 0x00000000
+DATA 4 0x020e04b4 0x00000030
+DATA 4 0x020e04b8 0x00000030
+DATA 4 0x020e076c 0x00000030
+DATA 4 0x020e0750 0x00020000
+DATA 4 0x020e04bc 0x00000028
+DATA 4 0x020e04c0 0x00000028
+DATA 4 0x020e04c4 0x00000028
+DATA 4 0x020e04c8 0x00000028
+DATA 4 0x020e04cc 0x00000028
+DATA 4 0x020e04d0 0x00000028
+DATA 4 0x020e04d4 0x00000028
+DATA 4 0x020e04d8 0x00000028
+DATA 4 0x020e0760 0x00020000
+DATA 4 0x020e0764 0x00000028
+DATA 4 0x020e0770 0x00000028
+DATA 4 0x020e0778 0x00000028
+DATA 4 0x020e077c 0x00000028
+DATA 4 0x020e0780 0x00000028
+DATA 4 0x020e0784 0x00000028
+DATA 4 0x020e078c 0x00000028
+DATA 4 0x020e0748 0x00000028
+DATA 4 0x020e0470 0x00000028
+DATA 4 0x020e0474 0x00000028
+DATA 4 0x020e0478 0x00000028
+DATA 4 0x020e047c 0x00000028
+DATA 4 0x020e0480 0x00000028
+DATA 4 0x020e0484 0x00000028
+DATA 4 0x020e0488 0x00000028
+DATA 4 0x020e048c 0x00000028
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+DATA 4 0x021b480c 0x001F001F
+DATA 4 0x021b4810 0x001F001F
+DATA 4 0x021b083c 0x42190217
+DATA 4 0x021b0840 0x017B017B
+DATA 4 0x021b483c 0x4176017B
+DATA 4 0x021b4840 0x015F016C
+DATA 4 0x021b0848 0x4C4C4D4C
+DATA 4 0x021b4848 0x4A4D4C48
+DATA 4 0x021b0850 0x3F3F3F40
+DATA 4 0x021b4850 0x3538382E
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+DATA 4 0x021b0004 0x00020025
+DATA 4 0x021b0008 0x00333030
+DATA 4 0x021b000c 0x676B5313
+DATA 4 0x021b0010 0xB66E8B63
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b0018 0x00001740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x006B1023
+DATA 4 0x021b0040 0x00000047
+DATA 4 0x021b0000 0x841A0000
+DATA 4 0x021b001c 0x04008032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00048031
+DATA 4 0x021b001c 0x05208030
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b4818 0x00011117
+DATA 4 0x021b0004 0x00025565
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0xFFFFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x00000FFF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F
#include <asm/arch/mx6-pins.h>
#include <asm/errno.h>
#include <asm/gpio.h>
+#include <asm/imx-common/mxc_i2c.h>
#include <asm/imx-common/iomux-v3.h>
#include <asm/imx-common/boot_mode.h>
#include <asm/imx-common/video.h>
#include <asm/arch/crm_regs.h>
#include <asm/io.h>
#include <asm/arch/sys_proto.h>
+#include <i2c.h>
+#include <power/pmic.h>
+#include <power/pfuze100_pmic.h>
DECLARE_GLOBAL_DATA_PTR;
#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+#define I2C_PMIC 1
+
+#define I2C_PAD MUX_PAD_CTRL(I2C_PAD_CTRL)
+
int dram_init(void)
{
gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
+static struct i2c_pads_info i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | I2C_PAD,
+ .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | I2C_PAD,
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | I2C_PAD,
+ .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | I2C_PAD,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+
static void setup_spi(void)
{
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
+
+ return 0;
+}
+
+static int pfuze_init(void)
+{
+ struct pmic *p;
+ int ret;
+ unsigned int reg;
+
+ ret = power_pfuze100_init(I2C_PMIC);
+ if (ret)
+ return ret;
+
+ p = pmic_get("PFUZE100_PMIC");
+ ret = pmic_probe(p);
+ if (ret)
+ return ret;
+
+ pmic_reg_read(p, PFUZE100_DEVICEID, ®);
+ printf("PMIC: PFUZE100 ID=0x%02x\n", reg);
+
+ /* Increase VGEN3 from 2.5 to 2.8V */
+ pmic_reg_read(p, PFUZE100_VGEN3VOL, ®);
+ reg &= ~0xf;
+ reg |= 0xa;
+ pmic_reg_write(p, PFUZE100_VGEN3VOL, reg);
+
+ /* Increase VGEN5 from 2.8 to 3V */
+ pmic_reg_read(p, PFUZE100_VGEN5VOL, ®);
+ reg &= ~0xf;
+ reg |= 0xc;
+ pmic_reg_write(p, PFUZE100_VGEN5VOL, reg);
+
+ /* Set SW1AB stanby volage to 0.975V */
+ pmic_reg_read(p, PFUZE100_SW1ABSTBY, ®);
+ reg &= ~0x3f;
+ reg |= 0x1b;
+ pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+
+ /* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
+ pmic_reg_read(p, PUZE_100_SW1ABCONF, ®);
+ reg &= ~0xc0;
+ reg |= 0x40;
+ pmic_reg_write(p, PUZE_100_SW1ABCONF, reg);
+
+ /* Set SW1C standby voltage to 0.975V */
+ pmic_reg_read(p, PFUZE100_SW1CSTBY, ®);
+ reg &= ~0x3f;
+ reg |= 0x1b;
+ pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+
+ /* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
+ pmic_reg_read(p, PFUZE100_SW1CCONF, ®);
+ reg &= ~0xc0;
+ reg |= 0x40;
+ pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
return 0;
}
#ifdef CONFIG_CMD_BMODE
add_board_boot_modes(board_boot_modes);
#endif
+ pfuze_init();
return 0;
}
fdt_fixup_memory(blob, (u64)base, (u64)size);
- /* By default NOR is on, and NAND is disabled */
-#ifdef CONFIG_NAND_U_BOOT
- do_fixup_by_path_string(blob, "nor_flash", "status", "disabled");
- do_fixup_by_path_string(blob, "nand_flash", "status", "okay");
-#endif
#ifdef CONFIG_HAS_FSL_DR_USB
fdt_fixup_dr_usb(blob, bd);
#endif
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 1, BOOKE_PAGESZ_4M, 1),
-#ifndef CONFIG_NAND_SPL
/* *W*G* - BCSR and NOR flash on local bus*/
/* This will be changed to *I*G* after relocation to RAM. */
SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_1M, 1),
-#endif
/* *I*G - NAND */
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
static const struct board_specific_parameters udimm0[] = {
/*
* memory controller 0
- * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
- * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
+ * num| hi| rank| clk| wrlvl | wrlvl | wrlvl |
+ * ranks| mhz| GB |adjst| start | ctl2 | ctl3 |
*/
- {2, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
- {2, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
- {2, 1600, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
- {2, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
- {2, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
- {2, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b},
- {1, 1200, 2, 5, 7, 0x0808090a, 0x0b0c0c0a},
- {1, 1500, 2, 5, 6, 0x07070809, 0x0a0b0b09},
- {1, 1600, 2, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
- {1, 1700, 2, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
- {1, 1900, 2, 5, 9, 0x0a0b0c0e, 0x0f10120c},
- {1, 2140, 2, 4, 8, 0x090a0b0d, 0x0e0f110b},
+ {2, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a},
+ {2, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09},
+ {2, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
+ {2, 1700, 0, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
+ {2, 1900, 0, 5, 9, 0x0a0b0c0e, 0x0f10120c},
+ {2, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b},
+ {1, 1200, 0, 5, 7, 0x0808090a, 0x0b0c0c0a},
+ {1, 1500, 0, 5, 6, 0x07070809, 0x0a0b0b09},
+ {1, 1600, 0, 5, 8, 0x090b0b0d, 0x0d0e0f0b},
+ {1, 1700, 0, 4, 7, 0x080a0a0c, 0x0c0d0e0a},
+ {1, 1900, 0, 5, 9, 0x0a0b0c0e, 0x0f10120c},
+ {1, 2140, 0, 4, 8, 0x090a0b0d, 0x0e0f110b},
{}
};
fm_info_set_phy_address(FM1_DTSEC10, RGMII_PHY2_ADDR);
switch (srds_s1) {
+ case 0x1b:
case 0x1c:
case 0x95:
case 0xa2:
fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
break;
+ case 0x50:
case 0x51:
+ case 0x5e:
case 0x5f:
+ case 0x64:
case 0x65:
/* T2080QDS: XAUI/HiGig in Slot3; T2081QDS: in Slot2 */
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
break;
case 0x66:
+ case 0x67:
/*
* XFI does not need a PHY to work, but to avoid U-boot use
* default PHY address which is zero to a MAC when it found
fm_info_set_phy_address(FM1_10GEC3, 6);
fm_info_set_phy_address(FM1_10GEC4, 7);
break;
+ case 0x6a:
case 0x6b:
fm_info_set_phy_address(FM1_10GEC1, 4);
fm_info_set_phy_address(FM1_10GEC2, 5);
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT4_PHY_ADDR);
break;
+ case 0x70:
case 0x71:
/* SGMII in Slot3 */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT3_PHY_ADDR);
fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
if ((srds_s1 == 0x66) || (srds_s1 == 0x6b) ||
+ (srds_s1 == 0x6a) || (srds_s1 == 0x70) ||
(srds_s1 == 0x6c) || (srds_s1 == 0x6d) ||
(srds_s1 == 0x71)) {
/* As XFI is in cage intead of a slot, so
#SerDes Protocol: 0x66_0x16
#Core/DDR: 1533Mhz/2133MT/s
12100017 15000000 00000000 00000000
-66160002 00008400 e8104000 c1000000
+66150002 00008400 e8104000 c1000000
00000000 00000000 00000000 000307fc
00000000 00000000 00000000 00000004
/* SerDes1 is not enabled */
break;
#if defined(CONFIG_T2080QDS)
+ case 0x1b:
case 0x1c:
case 0xa2:
/* SD1(A:D) => SLOT3 SGMII
*/
QIXIS_WRITE(brdcfg[12], 0x3a);
break;
+ case 0x50:
case 0x51:
/* SD1(A:D) => SLOT3 XAUI
* SD1(E) => SLOT1 PCIe4
*/
QIXIS_WRITE(brdcfg[12], 0xfe);
break;
+ case 0x6a:
case 0x6b:
/* SD1(A:D) => XFI cage
* SD1(E) => SLOT1 PCIe4
QIXIS_WRITE(brdcfg[12], 0x1a);
break;
#elif defined(CONFIG_T2081QDS)
+ case 0x50:
case 0x51:
/* SD1(A:D) => SLOT2 XAUI
* SD1(E) => SLOT1 PCIe4 x1
QIXIS_WRITE(brdcfg[12], 0x98);
QIXIS_WRITE(brdcfg[13], 0x70);
break;
+ case 0x6a:
case 0x6b:
/* SD1(A:D) => XFI SFP Module
* SD1(E) => SLOT1 PCIe4 x1
QIXIS_WRITE(brdcfg[13], 0x70);
break;
case 0x6c:
- /* SD1(A:B) => XFI SFP Module
- * SD1(C:D) => SLOT2 SGMII
- * SD1(E:H) => SLOT1 PCIe4 x4
- */
- QIXIS_WRITE(brdcfg[12], 0xe8);
- QIXIS_WRITE(brdcfg[13], 0x0);
- break;
case 0x6d:
/* SD1(A:B) => XFI SFP Module
* SD1(C:D) => SLOT2 SGMII
#SerDes Protocol: 0x66_0x16
#Core/DDR: 1533Mhz/1600MT/s
120c0017 15000000 00000000 00000000
-66160002 00008400 ec104000 c1000000
+66150002 00008400 ec104000 c1000000
00000000 00000000 00000000 000307fc
00000000 00000000 00000000 00000004
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
fm_info_set_phy_address(FM1_10GEC2, FM1_10GEC2_PHY_ADDR);
break;
+ case 27:
case 28:
+ case 35:
case 36:
/* SGMII in Slot1 and Slot2 */
fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
slot_qsgmii_phyaddr[1][2]);
}
break;
+ case 37:
case 38:
fm_info_set_phy_address(FM1_DTSEC1, slot_qsgmii_phyaddr[2][0]);
fm_info_set_phy_address(FM1_DTSEC2, slot_qsgmii_phyaddr[2][1]);
slot_qsgmii_phyaddr[1][3]);
}
break;
+ case 39:
case 40:
+ case 45:
case 46:
+ case 47:
case 48:
fm_info_set_phy_address(FM1_DTSEC5, slot_qsgmii_phyaddr[1][0]);
fm_info_set_phy_address(FM1_DTSEC6, slot_qsgmii_phyaddr[1][1]);
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
fm_info_set_phy_address(FM2_10GEC2, FM2_10GEC2_PHY_ADDR);
break;
+ case 6:
case 7:
+ case 12:
case 13:
case 14:
+ case 15:
case 16:
+ case 21:
case 22:
case 23:
+ case 24:
case 25:
case 26:
/* XAUI/HiGig in Slot3, SGMII in Slot4 */
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
break;
+ case 27:
case 28:
+ case 35:
case 36:
/* SGMII in Slot3 and Slot4 */
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][3]);
fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][2]);
break;
+ case 37:
case 38:
/* QSGMII in Slot3 and Slot4 */
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
fm_info_set_phy_address(FM2_DTSEC9, slot_qsgmii_phyaddr[3][2]);
fm_info_set_phy_address(FM2_DTSEC10, slot_qsgmii_phyaddr[3][3]);
break;
+ case 39:
case 40:
+ case 45:
case 46:
+ case 47:
case 48:
/* SGMII in Slot3 */
fm_info_set_phy_address(FM2_DTSEC5, slot_qsgmii_phyaddr[3][0]);
fm_info_set_phy_address(FM2_DTSEC3, slot_qsgmii_phyaddr[4][2]);
fm_info_set_phy_address(FM2_DTSEC4, slot_qsgmii_phyaddr[4][3]);
break;
+ case 49:
case 50:
+ case 51:
case 52:
+ case 53:
case 54:
fm_info_set_phy_address(FM2_10GEC1, FM2_10GEC1_PHY_ADDR);
fm_info_set_phy_address(FM2_DTSEC1, slot_qsgmii_phyaddr[4][0]);
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
switch (srds_prtcl_s1) {
+ case 37:
case 38:
/* swap first lane and third lane on slot1 */
vsc3316_fsm1_tx[0][1] = 14;
vsc3316_fsm1_tx[6][1] = 0;
vsc3316_fsm1_rx[1][1] = 2;
vsc3316_fsm1_rx[6][1] = 13;
+ case 39:
case 40:
+ case 45:
case 46:
+ case 47:
case 48:
/* swap first lane and third lane on slot2 */
vsc3316_fsm1_tx[2][1] = 8;
FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
switch (srds_prtcl_s2) {
+ case 37:
case 38:
/* swap first lane and third lane on slot3 */
vsc3316_fsm2_tx[2][1] = 11;
vsc3316_fsm2_tx[5][1] = 4;
vsc3316_fsm2_rx[2][1] = 9;
vsc3316_fsm2_rx[4][1] = 7;
+ case 39:
case 40:
+ case 45:
case 46:
+ case 47:
case 48:
+ case 49:
case 50:
+ case 51:
case 52:
+ case 53:
case 54:
/* swap first lane and third lane on slot4 */
vsc3316_fsm2_tx[6][1] = 3;
case 0:
/* SerDes3 is not enabled */
break;
+ case 1:
case 2:
case 9:
case 10:
brdcfg |= BRDCFG12_SD3MX_SLOT5;
QIXIS_WRITE(brdcfg[12], brdcfg);
break;
+ case 3:
case 4:
+ case 5:
case 6:
+ case 7:
case 8:
+ case 11:
case 12:
+ case 13:
case 14:
+ case 15:
case 16:
case 17:
+ case 18:
case 19:
case 20:
/* SD3(4:7) => SLOT6(0:3) */
case 0:
/* SerDes4 is not enabled */
break;
+ case 1:
case 2:
/* 10b, SD4(0:7) => SLOT7(0:7) */
brdcfg = QIXIS_READ(brdcfg[12]);
brdcfg |= BRDCFG12_SD4MX_SLOT7;
QIXIS_WRITE(brdcfg[12], brdcfg);
break;
+ case 3:
case 4:
+ case 5:
case 6:
+ case 7:
case 8:
/* x1b, SD4(4:7) => SLOT8(0:3) */
brdcfg = QIXIS_READ(brdcfg[12]);
brdcfg |= BRDCFG12_SD4MX_SLOT8;
QIXIS_WRITE(brdcfg[12], brdcfg);
break;
+ case 9:
case 10:
+ case 11:
case 12:
+ case 13:
case 14:
+ case 15:
case 16:
case 18:
/* 00b, SD4(4:5) => AURORA, SD4(6:7) => SATA */
#PBL preamble and RCW header
aa55aa55 010e0100
-#serdes protocol 1_28_6_12
+#serdes protocol 1_27_5_11
16070019 18101916 00000000 00000000
-04383060 30548c00 ec020000 f5000000
+04362858 30548c00 ec020000 f5000000
00000000 ee0000ee 00000000 000307fc
00000000 00000000 00000000 00000028
/* Register the 10G MDIO bus */
fm_memac_mdio_init(bis, &tgec_mdio_info);
- if (srds_prtcl_s1 == 28) {
+ if ((srds_prtcl_s1 == 28) || (srds_prtcl_s1 == 27)) {
/* SGMII */
fm_info_set_phy_address(FM1_DTSEC1, SGMII_PHY_ADDR1);
fm_info_set_phy_address(FM1_DTSEC2, SGMII_PHY_ADDR2);
#PBL preamble and RCW header
aa55aa55 010e0100
-#serdes protocol 28_56_2_10
+#serdes protocol 27_56_1_9
16070019 18101916 00000000 00000000
-70701050 00448c00 6c020000 f5000000
+6c700848 00448c00 6c020000 f5000000
00000000 ee0000ee 00000000 000287fc
00000000 50000000 00000000 00000028
# SPDX-License-Identifier: GPL-2.0+
#
-obj-y := gw_ventana.o gsc.o
+obj-y := gw_ventana.o gsc.o eeprom.o
+obj-$(CONFIG_SPL_BUILD) += gw_ventana_spl.o
This file contains information for the port of U-Boot to the Gateworks
Ventana Product family boards.
-1. Boot source, boot from NAND
+1. Secondary Program Loader (SPL)
+---------------------------------
+
+The i.MX6 has a BOOT ROM PPL (Primary Program Loader) which supports loading
+an executable image from various boot devices.
+
+The Gateworks Ventana board config uses an SPL build configuration. This
+will build the following artifacts from u-boot source:
+ - SPL - Secondary Program Loader that the i.MX6 BOOT ROM (Primary Program
+ Loader) boots. This detects CPU/DRAM configuration, configures
+ The DRAM controller, loads u-boot.img from the detected boot device,
+ and jumps to it. As this is booted from the PPL, it has an IVT/DCD
+ table.
+ - u-boot.img - The main u-boot core which is u-boot.bin with a image header.
+
+
+2. Build
+--------
+
+To build U-Boot for the Gateworks Ventana product family:
+
+ make gwventana_config
+ make
+
+
+3. Boot source, boot from NAND
------------------------------
The i.MX6 BOOT ROM expects some structures that provide details of NAND layout
and bad block information (referred to as 'bootstreams') which are replicated
-multiple times in NAND. The number of replications is configurable through
-board strapping options and eFUSE settings. The Freescale 'kobs-ng'
-application from the Freescale LTIB BSP, which runs under Linux, must be used
-to program the bootstream in order to setup the replicated headers correctly.
+multiple times in NAND. The number of replications and their spacing (referred
+to as search stride) is configurable through board strapping options and/or
+eFUSE settings (BOOT_SEARCH_COUNT / Pages in block from BOOT_CFG2). In
+addition, the i.MX6 BOOT ROM Flash Configuration Block (FCB) supports two
+copies of a bootloader in flash in the case that a bad block has corrupted one.
+The Freescale 'kobs-ng' application from the Freescale LTIB BSP, which runs
+under Linux and operates on an MTD partition, must be used to program the
+bootstream in order to setup this flash structure correctly.
The Gateworks Ventana boards with NAND flash have been factory programmed
such that their eFUSE settings expect 2 copies of the boostream (this is
specified by providing kobs-ng with the --search_exponent=1 argument). Once in
-Linux with MTD support for the NAND on /dev/mtd0 you can program the boostream
+Linux with MTD support for the NAND on /dev/mtd0 you can program the SPL
with:
-kobs-ng init -v -x --search_exponent=1 u-boot.imx
+kobs-ng init -v -x --search_exponent=1 SPL
-The kobs-ng application uses an imximage (u-boot.imx) which contains the
-Image Vector Table (IVT) and Device Configuration Data (DCD) structures that
-the i.MX6 BOOT ROM requires to boot. The kobs-ng adds the Firmware
-Configuration Block (FCB) and Discovered Bad Block Table (DBBT).
+The kobs-ng application uses an imximage which contains the Image Vector Table
+(IVT) and Device Configuration Data (DCD) structures that the i.MX6 BOOT ROM
+requires to boot. The kobs-ng adds the Firmware Configuration Block (FCB) and
+Discovered Bad Block Table (DBBT). The SPL build artifact from u-boot is
+an imximage.
-This information is taken from:
- http://trac.gateworks.com/wiki/ventana/bootloader#NANDFLASH
+The u-boot.img, which is the non SPL u-boot binary appended to a u-boot image
+header must be programmed in the NAND flash boot device at an offset hard
+coded in the SPL. For the Ventana boards, this has been chosen to be 14MB.
+The image can be programmed from either u-boot or Linux:
-More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual.
-
-2. Build
---------
+u-boot:
+Ventana > setenv mtdparts mtdparts=nand:14m(spl),2m(uboot),1m(env),-(rootfs)
+Ventana > tftp ${loadaddr} u-boot.img && nand erase.part uboot && \
+ nand write ${loadaddr} uboot ${filesize}
-There are several Gateworks Ventana boards that share a simliar design but
-vary based on CPU, Memory configuration, and subloaded devices. Although
-the subloaded devices are handled dynamically in the bootloader using
-factory configured EEPROM data to modify the device-tree, the CPU choice
-(IMX6Q vs IMX6DL) and memory configurations are currently compile-time
-options.
+Linux:
+nandwrite /dev/mtd1 u-boot.img
-The following Gateworks Ventana configurations exist:
- gwventanaq1gspi: MX6Q,1GB,SPI FLASH
- gwventanaq : MX6Q,512MB,NAND FLASH
- gwventanaq1g : MX6Q,1GB,NAND FLASH
- gwventanadl : MX6DL,512MB,NAND FLASH
- gwventanadl1g : MX6DL,1GB,NAND FLASH
+The above assumes the default Ventana partitioning scheme which is configured
+via the mtdparts env var:
+ - spl: 14MB
+ - uboot: 2M
+ - env: 1M
+ - rootfs: the rest
-To build U-Boot for the MX6Q,1GB,NAND FLASH for example:
+This information is taken from:
+ http://trac.gateworks.com/wiki/ventana/bootloader#NANDFLASH
- make gwventanaq1g_config
- make
+More details about the i.MX6 BOOT ROM can be found in the IMX6 reference manual.
--- /dev/null
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#include "gsc.h"
+#include "ventana_eeprom.h"
+
+/* read ventana EEPROM, check for validity, and return baseboard type */
+int
+read_eeprom(int bus, struct ventana_board_info *info)
+{
+ int i;
+ int chksum;
+ char baseboard;
+ int type;
+ unsigned char *buf = (unsigned char *)info;
+
+ memset(info, 0, sizeof(*info));
+
+ /*
+ * On a board with a missing/depleted backup battery for GSC, the
+ * board may be ready to probe the GSC before its firmware is
+ * running. We will wait here indefinately for the GSC/EEPROM.
+ */
+ while (1) {
+ if (0 == i2c_set_bus_num(bus) &&
+ 0 == i2c_probe(GSC_EEPROM_ADDR))
+ break;
+ mdelay(1);
+ }
+
+ /* read eeprom config section */
+ if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(*info))) {
+ puts("EEPROM: Failed to read EEPROM\n");
+ info->model[0] = 0;
+ return GW_UNKNOWN;
+ }
+
+ /* sanity checks */
+ if (info->model[0] != 'G' || info->model[1] != 'W') {
+ puts("EEPROM: Invalid Model in EEPROM\n");
+ info->model[0] = 0;
+ return GW_UNKNOWN;
+ }
+
+ /* validate checksum */
+ for (chksum = 0, i = 0; i < sizeof(*info)-2; i++)
+ chksum += buf[i];
+ if ((info->chksum[0] != chksum>>8) ||
+ (info->chksum[1] != (chksum&0xff))) {
+ puts("EEPROM: Failed EEPROM checksum\n");
+ info->model[0] = 0;
+ return GW_UNKNOWN;
+ }
+
+ /* original GW5400-A prototype */
+ baseboard = info->model[3];
+ if (strncasecmp((const char *)info->model, "GW5400-A", 8) == 0)
+ baseboard = '0';
+
+ switch (baseboard) {
+ case '0': /* original GW5400-A prototype */
+ type = GW54proto;
+ break;
+ case '1':
+ type = GW51xx;
+ break;
+ case '2':
+ type = GW52xx;
+ break;
+ case '3':
+ type = GW53xx;
+ break;
+ case '4':
+ type = GW54xx;
+ break;
+ default:
+ printf("EEPROM: Unknown model in EEPROM: %s\n", info->model);
+ type = GW_UNKNOWN;
+ break;
+ }
+ return type;
+}
*/
static struct ventana_board_info ventana_info;
-enum {
- GW54proto, /* original GW5400-A prototype */
- GW51xx,
- GW52xx,
- GW53xx,
- GW54xx,
- GW_UNKNOWN,
-};
-
int board_type;
/* UART1: Function varies per baseboard */
iomux_v3_cfg_t const uart1_pads[] = {
- MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
/* UART2: Serial Console */
iomux_v3_cfg_t const uart2_pads[] = {
- MX6_PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
- MX6_PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
+ IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
};
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1: GSC */
-struct i2c_pads_info i2c_pad_info0 = {
+struct i2c_pads_info mx6q_i2c_pad_info0 = {
.scl = {
- .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
- .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
+ .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
+ .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
.gp = IMX_GPIO_NR(3, 21)
},
.sda = {
- .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
- .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
+ .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
+ .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
+ .gp = IMX_GPIO_NR(3, 28)
+ }
+};
+struct i2c_pads_info mx6dl_i2c_pad_info0 = {
+ .scl = {
+ .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
+ .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
+ .gp = IMX_GPIO_NR(3, 21)
+ },
+ .sda = {
+ .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
+ .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
.gp = IMX_GPIO_NR(3, 28)
}
};
/* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
-struct i2c_pads_info i2c_pad_info1 = {
+struct i2c_pads_info mx6q_i2c_pad_info1 = {
+ .scl = {
+ .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
+ .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
+ .gp = IMX_GPIO_NR(4, 12)
+ },
+ .sda = {
+ .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+ .gp = IMX_GPIO_NR(4, 13)
+ }
+};
+struct i2c_pads_info mx6dl_i2c_pad_info1 = {
.scl = {
- .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
- .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
+ .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
+ .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
.gp = IMX_GPIO_NR(4, 12)
},
.sda = {
- .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
- .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
+ .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
+ .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
.gp = IMX_GPIO_NR(4, 13)
}
};
/* I2C3: Misc/Expansion */
-struct i2c_pads_info i2c_pad_info2 = {
+struct i2c_pads_info mx6q_i2c_pad_info2 = {
.scl = {
- .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
- .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
+ .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
+ .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
.gp = IMX_GPIO_NR(1, 3)
},
.sda = {
- .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
- .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
+ .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
+ .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
+ .gp = IMX_GPIO_NR(1, 6)
+ }
+};
+struct i2c_pads_info mx6dl_i2c_pad_info2 = {
+ .scl = {
+ .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
+ .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
+ .gp = IMX_GPIO_NR(1, 3)
+ },
+ .sda = {
+ .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
+ .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
.gp = IMX_GPIO_NR(1, 6)
}
};
/* MMC */
iomux_v3_cfg_t const usdhc3_pads[] = {
- MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
- MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+ IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
+ /* CD */
+ IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
/* ENET */
iomux_v3_cfg_t const enet_pads[] = {
- MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
- MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
+ IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
+ MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
+ MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
+ IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
+ MUX_PAD_CTRL(ENET_PAD_CTRL)),
/* PHY nRST */
- MX6_PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
/* NAND */
iomux_v3_cfg_t const nfc_pads[] = {
- MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
- MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
+ IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
#ifdef CONFIG_CMD_NAND
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
/* config gpmi nand iomux */
- imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
+ SETUP_IOMUX_PADS(nfc_pads);
/* config gpmi and bch clock to 100 MHz */
clrsetbits_le32(&mxc_ccm->cs2cdr,
static void setup_iomux_enet(void)
{
- imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
+ SETUP_IOMUX_PADS(enet_pads);
/* toggle PHY_RST# */
gpio_direction_output(GP_PHY_RST, 0);
static void setup_iomux_uart(void)
{
- imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
- imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+ SETUP_IOMUX_PADS(uart1_pads);
+ SETUP_IOMUX_PADS(uart2_pads);
}
#ifdef CONFIG_USB_EHCI_MX6
iomux_v3_cfg_t const usb_pads[] = {
- MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(DIO_PAD_CTRL),
- MX6_PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(DIO_PAD_CTRL),
- MX6_PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(DIO_PAD_CTRL), /* OTG PWR */
+ IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(DIO_PAD_CTRL)),
+ IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(DIO_PAD_CTRL)),
+ /* OTG PWR */
+ IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22 | MUX_PAD_CTRL(DIO_PAD_CTRL)),
};
int board_ehci_hcd_init(int port)
{
struct ventana_board_info *info = &ventana_info;
- imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
+ SETUP_IOMUX_PADS(usb_pads);
/* Reset USB HUB (present on GW54xx/GW53xx) */
switch (info->model[3]) {
case '3': /* GW53xx */
- imx_iomux_v3_setup_pad(MX6_PAD_GPIO_9__GPIO1_IO09|
- MUX_PAD_CTRL(NO_PAD_CTRL));
+ SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 |
+ MUX_PAD_CTRL(NO_PAD_CTRL));
gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
mdelay(2);
gpio_set_value(IMX_GPIO_NR(1, 9), 1);
break;
case '4': /* GW54xx */
- imx_iomux_v3_setup_pad(MX6_PAD_SD1_DAT0__GPIO1_IO16 |
- MUX_PAD_CTRL(NO_PAD_CTRL));
+ SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 |
+ MUX_PAD_CTRL(NO_PAD_CTRL));
gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
mdelay(2);
gpio_set_value(IMX_GPIO_NR(1, 16), 1);
int board_mmc_init(bd_t *bis)
{
/* Only one USDHC controller on Ventana */
- imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+ SETUP_IOMUX_PADS(usdhc3_pads);
usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
usdhc_cfg.max_bus_width = 4;
#ifdef CONFIG_MXC_SPI
iomux_v3_cfg_t const ecspi1_pads[] = {
/* SS1 */
- MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
- MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
+ IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
+ IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
};
static void setup_spi(void)
{
gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
- imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
- ARRAY_SIZE(ecspi1_pads));
+ SETUP_IOMUX_PADS(ecspi1_pads);
}
#endif
writel(reg, &iomux->gpr[2]);
/* Enable Backlight */
- imx_iomux_v3_setup_pad(MX6_PAD_SD1_CMD__GPIO1_IO18 |
- MUX_PAD_CTRL(NO_PAD_CTRL));
+ SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL));
gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
}
writel(reg, &iomux->gpr[3]);
/* Backlight CABEN on LVDS connector */
- imx_iomux_v3_setup_pad(MX6_PAD_SD2_CLK__GPIO1_IO10 |
- MUX_PAD_CTRL(NO_PAD_CTRL));
+ SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL));
gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
}
#endif /* CONFIG_VIDEO_IPUV3 */
-/* read ventana EEPROM, check for validity, and return baseboard type */
-static int
-read_eeprom(void)
-{
- int i;
- int chksum;
- char baseboard;
- int type;
- struct ventana_board_info *info = &ventana_info;
- unsigned char *buf = (unsigned char *)&ventana_info;
-
- memset(info, 0, sizeof(ventana_info));
-
- /*
- * On a board with a missing/depleted backup battery for GSC, the
- * board may be ready to probe the GSC before its firmware is
- * running. We will wait here indefinately for the GSC/EEPROM.
- */
- while (1) {
- if (0 == i2c_set_bus_num(I2C_GSC) &&
- 0 == i2c_probe(GSC_EEPROM_ADDR))
- break;
- mdelay(1);
- }
-
- /* read eeprom config section */
- if (gsc_i2c_read(GSC_EEPROM_ADDR, 0x00, 1, buf, sizeof(ventana_info))) {
- puts("EEPROM: Failed to read EEPROM\n");
- info->model[0] = 0;
- return GW_UNKNOWN;
- }
-
- /* sanity checks */
- if (info->model[0] != 'G' || info->model[1] != 'W') {
- puts("EEPROM: Invalid Model in EEPROM\n");
- info->model[0] = 0;
- return GW_UNKNOWN;
- }
-
- /* validate checksum */
- for (chksum = 0, i = 0; i < sizeof(*info)-2; i++)
- chksum += buf[i];
- if ((info->chksum[0] != chksum>>8) ||
- (info->chksum[1] != (chksum&0xff))) {
- puts("EEPROM: Failed EEPROM checksum\n");
- info->model[0] = 0;
- return GW_UNKNOWN;
- }
-
- /* original GW5400-A prototype */
- baseboard = info->model[3];
- if (strncasecmp((const char *)info->model, "GW5400-A", 8) == 0)
- baseboard = '0';
-
- switch (baseboard) {
- case '0': /* original GW5400-A prototype */
- type = GW54proto;
- break;
- case '1':
- type = GW51xx;
- break;
- case '2':
- type = GW52xx;
- break;
- case '3':
- type = GW53xx;
- break;
- case '4':
- type = GW54xx;
- break;
- default:
- printf("EEPROM: Unknown model in EEPROM: %s\n", info->model);
- type = GW_UNKNOWN;
- break;
- }
- return type;
-}
-
/*
* Baseboard specific GPIO
*/
/* common to add baseboards */
static iomux_v3_cfg_t const gw_gpio_pads[] = {
/* MSATA_EN */
- MX6_PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* RS232_EN# */
- MX6_PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
/* prototype */
static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
/* PANLEDG# */
- MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* PANLEDR# */
- MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* LOCLED# */
- MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* RS485_EN */
- MX6_PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* IOEXP_PWREN# */
- MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* IOEXP_IRQ# */
- MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* VID_EN */
- MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* DIOI2C_DIS# */
- MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* PCICK_SSON */
- MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* PCI_RST# */
- MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
/* PANLEDG# */
- MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* PANLEDR# */
- MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* IOEXP_PWREN# */
- MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* IOEXP_IRQ# */
- MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* GPS_SHDN */
- MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* VID_PWR */
- MX6_PAD_CSI0_DATA_EN__GPIO5_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* PCI_RST# */
- MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
/* PANLEDG# */
- MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* PANLEDR# */
- MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* IOEXP_PWREN# */
- MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* IOEXP_IRQ# */
- MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* MX6_LOCLED# */
- MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* GPS_SHDN */
- MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* USBOTG_SEL */
- MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* VID_PWR */
- MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* PCI_RST# */
- MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
/* PANLEDG# */
- MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* PANLEDR# */
- MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* IOEXP_PWREN# */
- MX6_PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* IOEXP_IRQ# */
- MX6_PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* MX6_LOCLED# */
- MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* GPS_SHDN */
- MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* VID_EN */
- MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* PCI_RST# */
- MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
/* PANLEDG# */
- MX6_PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* PANLEDR# */
- MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* MX6_LOCLED# */
- MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* MIPI_DIO */
- MX6_PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* RS485_EN */
- MX6_PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* IOEXP_PWREN# */
- MX6_PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* IOEXP_IRQ# */
- MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* DIOI2C_DIS# */
- MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* DIOI2C_DIS# */
- MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* PCICK_SSON */
- MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
/* PCI_RST# */
- MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
+ IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
};
/*
* be pinmuxed as a GPIO or in some cases a PWM
*/
struct dio_cfg {
- iomux_v3_cfg_t gpio_padmux;
+ iomux_v3_cfg_t gpio_padmux[2];
unsigned gpio_param;
- iomux_v3_cfg_t pwm_padmux;
+ iomux_v3_cfg_t pwm_padmux[2];
unsigned pwm_param;
};
/* GW5400proto */
{
.gpio_pads = gw54xx_gpio_pads,
- .num_pads = ARRAY_SIZE(gw54xx_gpio_pads),
+ .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
.dio_cfg = {
- { MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9),
- MX6_PAD_GPIO_9__PWM1_OUT, 1 },
- { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
- MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
- { MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9),
- MX6_PAD_SD4_DAT1__PWM3_OUT, 3 },
- { MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10),
- MX6_PAD_SD4_DAT2__PWM4_OUT, 4 },
+ {
+ { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
+ IMX_GPIO_NR(1, 9),
+ { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
+ 1
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+ IMX_GPIO_NR(1, 19),
+ { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+ 2
+ },
+ {
+ { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
+ IMX_GPIO_NR(2, 9),
+ { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
+ 3
+ },
+ {
+ { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
+ IMX_GPIO_NR(2, 10),
+ { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
+ 4
+ },
},
.leds = {
IMX_GPIO_NR(4, 6),
/* GW51xx */
{
.gpio_pads = gw51xx_gpio_pads,
- .num_pads = ARRAY_SIZE(gw51xx_gpio_pads),
+ .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
.dio_cfg = {
- { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
- 0, 0 },
- { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
- MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
- { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
- MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
- { MX6_PAD_SD1_CMD__GPIO1_IO18, IMX_GPIO_NR(1, 18),
- MX6_PAD_SD1_CMD__PWM4_OUT, 4 },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+ IMX_GPIO_NR(1, 16),
+ { 0, 0 },
+ 0
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+ IMX_GPIO_NR(1, 19),
+ { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+ 2
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+ IMX_GPIO_NR(1, 17),
+ { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+ 3
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
+ IMX_GPIO_NR(1, 18),
+ { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
+ 4
+ },
},
.leds = {
IMX_GPIO_NR(4, 6),
/* GW52xx */
{
.gpio_pads = gw52xx_gpio_pads,
- .num_pads = ARRAY_SIZE(gw52xx_gpio_pads),
+ .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
.dio_cfg = {
- { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
- 0, 0 },
- { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
- MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
- { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
- MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
- { MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20),
- 0, 0 },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+ IMX_GPIO_NR(1, 16),
+ { 0, 0 },
+ 0
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+ IMX_GPIO_NR(1, 19),
+ { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+ 2
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+ IMX_GPIO_NR(1, 17),
+ { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+ 3
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
+ IMX_GPIO_NR(1, 20),
+ { 0, 0 },
+ 0
+ },
},
.leds = {
IMX_GPIO_NR(4, 6),
/* GW53xx */
{
.gpio_pads = gw53xx_gpio_pads,
- .num_pads = ARRAY_SIZE(gw53xx_gpio_pads),
+ .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
.dio_cfg = {
- { MX6_PAD_SD1_DAT0__GPIO1_IO16, IMX_GPIO_NR(1, 16),
- 0, 0 },
- { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
- MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
- { MX6_PAD_SD1_DAT1__GPIO1_IO17, IMX_GPIO_NR(1, 17),
- MX6_PAD_SD1_DAT1__PWM3_OUT, 3 },
- { MX6_PAD_SD1_CLK__GPIO1_IO20, IMX_GPIO_NR(1, 20),
- 0, 0 },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
+ IMX_GPIO_NR(1, 16),
+ { 0, 0 },
+ 0
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+ IMX_GPIO_NR(1, 19),
+ { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+ 2
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
+ IMX_GPIO_NR(1, 17),
+ { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
+ 3
+ },
+ {
+ {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
+ IMX_GPIO_NR(1, 20),
+ { 0, 0 },
+ 0
+ },
},
.leds = {
IMX_GPIO_NR(4, 6),
/* GW54xx */
{
.gpio_pads = gw54xx_gpio_pads,
- .num_pads = ARRAY_SIZE(gw54xx_gpio_pads),
+ .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
.dio_cfg = {
- { MX6_PAD_GPIO_9__GPIO1_IO09, IMX_GPIO_NR(1, 9),
- MX6_PAD_GPIO_9__PWM1_OUT, 1 },
- { MX6_PAD_SD1_DAT2__GPIO1_IO19, IMX_GPIO_NR(1, 19),
- MX6_PAD_SD1_DAT2__PWM2_OUT, 2 },
- { MX6_PAD_SD4_DAT1__GPIO2_IO09, IMX_GPIO_NR(2, 9),
- MX6_PAD_SD4_DAT1__PWM3_OUT, 3 },
- { MX6_PAD_SD4_DAT2__GPIO2_IO10, IMX_GPIO_NR(2, 10),
- MX6_PAD_SD4_DAT2__PWM4_OUT, 4 },
+ {
+ { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
+ IMX_GPIO_NR(1, 9),
+ { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
+ 1
+ },
+ {
+ { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
+ IMX_GPIO_NR(1, 19),
+ { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
+ 2
+ },
+ {
+ { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
+ IMX_GPIO_NR(2, 9),
+ { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
+ 3
+ },
+ {
+ { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
+ IMX_GPIO_NR(2, 10),
+ { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
+ 4
+ },
},
.leds = {
IMX_GPIO_NR(4, 6),
for (i = 0; i < 4; i++) {
struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
unsigned ctrl = DIO_PAD_CTRL;
+ unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
sprintf(arg, "dio%d", i);
if (!hwconfig(arg))
cfg->gpio_param%32,
cfg->gpio_param);
}
- imx_iomux_v3_setup_pad(cfg->gpio_padmux |
+ imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
MUX_PAD_CTRL(ctrl));
gpio_direction_input(cfg->gpio_param);
} else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
cfg->pwm_padmux) {
if (!quiet)
printf("DIO%d: pwm%d\n", i, cfg->pwm_param);
- imx_iomux_v3_setup_pad(cfg->pwm_padmux |
+ imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
MUX_PAD_CTRL(ctrl));
}
}
int imx6_pcie_toggle_reset(void)
{
if (board_type < GW_UNKNOWN) {
- gpio_direction_output(gpio_cfg[board_type].pcie_rst, 0);
+ uint pin = gpio_cfg[board_type].pcie_rst;
+ gpio_direction_output(pin, 0);
mdelay(50);
- gpio_direction_output(gpio_cfg[board_type].pcie_rst, 1);
+ gpio_direction_output(pin, 1);
}
return 0;
}
* Board Support
*/
+/* called from SPL board_init_f() */
int board_early_init_f(void)
{
setup_iomux_uart();
int dram_init(void)
{
- gd->ram_size = get_ram_size((void *)PHYS_SDRAM,
- CONFIG_DDR_MB*1024*1024);
-
+ gd->ram_size = imx_ddr_size();
return 0;
}
#ifdef CONFIG_MXC_SPI
setup_spi();
#endif
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
- setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
- setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+ if (is_cpu_type(MXC_CPU_MX6Q)) {
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
+ } else {
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
+ setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
+ }
#ifdef CONFIG_CMD_SATA
setup_sata();
#endif
/* read Gateworks EEPROM into global struct (used later) */
- board_type = read_eeprom();
+ board_type = read_eeprom(I2C_GSC, &ventana_info);
/* board-specifc GPIO iomux */
+ SETUP_IOMUX_PADS(gw_gpio_pads);
if (board_type < GW_UNKNOWN) {
- imx_iomux_v3_setup_multiple_pads(gw_gpio_pads,
- ARRAY_SIZE(gw_gpio_pads));
- imx_iomux_v3_setup_multiple_pads(gpio_cfg[board_type].gpio_pads,
- gpio_cfg[board_type].num_pads);
+ iomux_v3_cfg_t const *p = gpio_cfg[board_type].gpio_pads;
+ int count = gpio_cfg[board_type].num_pads;
+
+ imx_iomux_v3_setup_multiple_pads(p, count);
}
return 0;
* env scripts will try loading each from most specific to
* least.
*/
- if (is_cpu_type(MXC_CPU_MX6Q))
+ if (is_cpu_type(MXC_CPU_MX6Q) ||
+ is_cpu_type(MXC_CPU_MX6D))
cputype = "imx6q";
- else if (is_cpu_type(MXC_CPU_MX6DL))
+ else if (is_cpu_type(MXC_CPU_MX6DL) ||
+ is_cpu_type(MXC_CPU_MX6SOLO))
cputype = "imx6dl";
memset(str, 0, sizeof(str));
for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
#define __ASSEMBLY__
#include <config.h>
-#include "asm/arch/mx6-ddr.h"
#include "asm/arch/iomux.h"
#include "asm/arch/crm_regs.h"
-
-/* Memory configuration (size is overridden via eeprom config) */
-#include "../../boundary/nitrogen6x/ddr-setup.cfg"
-#if defined(CONFIG_MX6Q) && CONFIG_DDR_MB == 1024
- #include "../../boundary/nitrogen6x/1066mhz_4x128mx16.cfg"
-#elif defined(CONFIG_MX6DL) && CONFIG_DDR_MB == 1024
- #include "../../boundary/nitrogen6x/800mhz_4x128mx16.cfg"
-#elif defined(CONFIG_MX6DL) && CONFIG_DDR_MB == 512
- #include "../../boundary/nitrogen6x/800mhz_2x128mx16.cfg"
-#elif defined(CONFIG_MX6Q) && CONFIG_DDR_MB == 512
- #include "../../boundary/nitrogen6x/800mhz_2x128mx16.cfg"
-#else
- #error "Unsupported CPU/Memory configuration"
-#endif
#include "clocks.cfg"
--- /dev/null
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/mx6-ddr.h>
+#include <asm/arch/mx6-pins.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/imx-common/boot_mode.h>
+#include <asm/imx-common/iomux-v3.h>
+#include <asm/imx-common/mxc_i2c.h>
+#include <spl.h>
+
+#include "ventana_eeprom.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */
+#define I2C_GSC 0
+#define GSC_EEPROM_ADDR 0x51
+#define GSC_EEPROM_DDR_SIZE 0x2B /* enum (512,1024,2048) MB */
+#define GSC_EEPROM_DDR_WIDTH 0x2D /* enum (32,64) bit */
+#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
+ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
+ PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* I2C1: GSC */
+static struct i2c_pads_info mx6q_i2c_pad_info0 = {
+ .scl = {
+ .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
+ .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
+ .gp = IMX_GPIO_NR(3, 21)
+ },
+ .sda = {
+ .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
+ .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
+ .gp = IMX_GPIO_NR(3, 28)
+ }
+};
+static struct i2c_pads_info mx6dl_i2c_pad_info0 = {
+ .scl = {
+ .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
+ .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
+ .gp = IMX_GPIO_NR(3, 21)
+ },
+ .sda = {
+ .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
+ .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
+ .gp = IMX_GPIO_NR(3, 28)
+ }
+};
+
+static void i2c_setup_iomux(void)
+{
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
+ else
+ setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
+}
+
+/* configure MX6Q/DUAL mmdc DDR io registers */
+struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = {
+ /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
+ .dram_sdclk_0 = 0x00020030,
+ .dram_sdclk_1 = 0x00020030,
+ .dram_cas = 0x00020030,
+ .dram_ras = 0x00020030,
+ .dram_reset = 0x00020030,
+ /* SDCKE[0:1]: 100k pull-up */
+ .dram_sdcke0 = 0x00003000,
+ .dram_sdcke1 = 0x00003000,
+ /* SDBA2: pull-up disabled */
+ .dram_sdba2 = 0x00000000,
+ /* SDODT[0:1]: 100k pull-up, 40 ohm */
+ .dram_sdodt0 = 0x00003030,
+ .dram_sdodt1 = 0x00003030,
+ /* SDQS[0:7]: Differential input, 40 ohm */
+ .dram_sdqs0 = 0x00000030,
+ .dram_sdqs1 = 0x00000030,
+ .dram_sdqs2 = 0x00000030,
+ .dram_sdqs3 = 0x00000030,
+ .dram_sdqs4 = 0x00000030,
+ .dram_sdqs5 = 0x00000030,
+ .dram_sdqs6 = 0x00000030,
+ .dram_sdqs7 = 0x00000030,
+
+ /* DQM[0:7]: Differential input, 40 ohm */
+ .dram_dqm0 = 0x00020030,
+ .dram_dqm1 = 0x00020030,
+ .dram_dqm2 = 0x00020030,
+ .dram_dqm3 = 0x00020030,
+ .dram_dqm4 = 0x00020030,
+ .dram_dqm5 = 0x00020030,
+ .dram_dqm6 = 0x00020030,
+ .dram_dqm7 = 0x00020030,
+};
+
+/* configure MX6Q/DUAL mmdc GRP io registers */
+struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = {
+ /* DDR3 */
+ .grp_ddr_type = 0x000c0000,
+ .grp_ddrmode_ctl = 0x00020000,
+ /* disable DDR pullups */
+ .grp_ddrpke = 0x00000000,
+ /* ADDR[00:16], SDBA[0:1]: 40 ohm */
+ .grp_addds = 0x00000030,
+ /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
+ .grp_ctlds = 0x00000030,
+ /* DATA[00:63]: Differential input, 40 ohm */
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = 0x00000030,
+ .grp_b1ds = 0x00000030,
+ .grp_b2ds = 0x00000030,
+ .grp_b3ds = 0x00000030,
+ .grp_b4ds = 0x00000030,
+ .grp_b5ds = 0x00000030,
+ .grp_b6ds = 0x00000030,
+ .grp_b7ds = 0x00000030,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc DDR io registers */
+struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = {
+ /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
+ .dram_sdclk_0 = 0x00020030,
+ .dram_sdclk_1 = 0x00020030,
+ .dram_cas = 0x00020030,
+ .dram_ras = 0x00020030,
+ .dram_reset = 0x00020030,
+ /* SDCKE[0:1]: 100k pull-up */
+ .dram_sdcke0 = 0x00003000,
+ .dram_sdcke1 = 0x00003000,
+ /* SDBA2: pull-up disabled */
+ .dram_sdba2 = 0x00000000,
+ /* SDODT[0:1]: 100k pull-up, 40 ohm */
+ .dram_sdodt0 = 0x00003030,
+ .dram_sdodt1 = 0x00003030,
+ /* SDQS[0:7]: Differential input, 40 ohm */
+ .dram_sdqs0 = 0x00000030,
+ .dram_sdqs1 = 0x00000030,
+ .dram_sdqs2 = 0x00000030,
+ .dram_sdqs3 = 0x00000030,
+ .dram_sdqs4 = 0x00000030,
+ .dram_sdqs5 = 0x00000030,
+ .dram_sdqs6 = 0x00000030,
+ .dram_sdqs7 = 0x00000030,
+
+ /* DQM[0:7]: Differential input, 40 ohm */
+ .dram_dqm0 = 0x00020030,
+ .dram_dqm1 = 0x00020030,
+ .dram_dqm2 = 0x00020030,
+ .dram_dqm3 = 0x00020030,
+ .dram_dqm4 = 0x00020030,
+ .dram_dqm5 = 0x00020030,
+ .dram_dqm6 = 0x00020030,
+ .dram_dqm7 = 0x00020030,
+};
+
+/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
+struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = {
+ /* DDR3 */
+ .grp_ddr_type = 0x000c0000,
+ /* SDQS[0:7]: Differential input, 40 ohm */
+ .grp_ddrmode_ctl = 0x00020000,
+ /* disable DDR pullups */
+ .grp_ddrpke = 0x00000000,
+ /* ADDR[00:16], SDBA[0:1]: 40 ohm */
+ .grp_addds = 0x00000030,
+ /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
+ .grp_ctlds = 0x00000030,
+ /* DATA[00:63]: Differential input, 40 ohm */
+ .grp_ddrmode = 0x00020000,
+ .grp_b0ds = 0x00000030,
+ .grp_b1ds = 0x00000030,
+ .grp_b2ds = 0x00000030,
+ .grp_b3ds = 0x00000030,
+ .grp_b4ds = 0x00000030,
+ .grp_b5ds = 0x00000030,
+ .grp_b6ds = 0x00000030,
+ .grp_b7ds = 0x00000030,
+};
+
+/* MT41K128M16JT-125 */
+static struct mx6_ddr3_cfg mt41k128m16jt_125 = {
+ .mem_speed = 1600,
+ .density = 2,
+ .width = 16,
+ .banks = 8,
+ .rowaddr = 14,
+ .coladdr = 10,
+ .pagesz = 2,
+ .trcd = 1375,
+ .trcmin = 4875,
+ .trasmin = 3500,
+};
+
+/* GW54xx specific calibration */
+static struct mx6_mmdc_calibration gw54xxq_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x00190018,
+ .p0_mpwldectrl1 = 0x0021001D,
+ .p1_mpwldectrl0 = 0x00160027,
+ .p1_mpwldectrl1 = 0x0012001E,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x43370346,
+ .p0_mpdgctrl1 = 0x032A0321,
+ .p1_mpdgctrl0 = 0x433A034D,
+ .p1_mpdgctrl1 = 0x032F0235,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x3C313539,
+ .p1_mprddlctl = 0x37333140,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x37393C38,
+ .p1_mpwrdlctl = 0x42334538,
+};
+
+/* GW53xx specific calibration */
+static struct mx6_mmdc_calibration gw53xxq_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x00160013,
+ .p0_mpwldectrl1 = 0x00090024,
+ .p1_mpwldectrl0 = 0x001F0018,
+ .p1_mpwldectrl1 = 0x000C001C,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x433A034C,
+ .p0_mpdgctrl1 = 0x0336032F,
+ .p1_mpdgctrl0 = 0x4343034A,
+ .p1_mpdgctrl1 = 0x03370222,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x3F343638,
+ .p1_mprddlctl = 0x38373442,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x343A3E39,
+ .p1_mpwrdlctl = 0x44344239,
+};
+static struct mx6_mmdc_calibration gw53xxdl_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x003C003C,
+ .p0_mpwldectrl1 = 0x00330038,
+ .p1_mpwldectrl0 = 0x001F002A,
+ .p1_mpwldectrl1 = 0x0022003F,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x42410244,
+ .p0_mpdgctrl1 = 0x022D022D,
+ .p1_mpdgctrl0 = 0x4234023A,
+ .p1_mpdgctrl1 = 0x021C0228,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x484A4C4B,
+ .p1_mprddlctl = 0x4B4D4E4B,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x33342B32,
+ .p1_mpwrdlctl = 0x3933332B,
+};
+
+/* GW52xx specific calibration */
+static struct mx6_mmdc_calibration gw52xxdl_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x0040003F,
+ .p0_mpwldectrl1 = 0x00370037,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x42420244,
+ .p0_mpdgctrl1 = 0x022F022F,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x49464B4A,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x32362C32,
+};
+
+/* GW51xx specific calibration */
+static struct mx6_mmdc_calibration gw51xxq_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x00150016,
+ .p0_mpwldectrl1 = 0x001F0017,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x433D034D,
+ .p0_mpdgctrl1 = 0x033D032F,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x3F313639,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x33393F36,
+};
+
+static struct mx6_mmdc_calibration gw51xxdl_mmdc_calib = {
+ /* write leveling calibration determine */
+ .p0_mpwldectrl0 = 0x003D003F,
+ .p0_mpwldectrl1 = 0x002F0038,
+ /* Read DQS Gating calibration */
+ .p0_mpdgctrl0 = 0x423A023A,
+ .p0_mpdgctrl1 = 0x022A0228,
+ /* Read Calibration: DQS delay relative to DQ read access */
+ .p0_mprddlctl = 0x48494C4C,
+ /* Write Calibration: DQ/DM delay relative to DQS write access */
+ .p0_mpwrdlctl = 0x34352D31,
+};
+
+static void spl_dram_init(int width, int size, int board_model)
+{
+ struct mx6_ddr3_cfg *mem = &mt41k128m16jt_125;
+ struct mx6_mmdc_calibration *calib;
+ struct mx6_ddr_sysinfo sysinfo = {
+ /* width of data bus:0=16,1=32,2=64 */
+ .dsize = width/32,
+ /* config for full 4GB range so that get_mem_size() works */
+ .cs_density = 32, /* 32Gb per CS */
+ /* single chip select */
+ .ncs = 1,
+ .cs1_mirror = 0,
+ .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */
+#ifdef RTT_NOM_120OHM
+ .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */
+#else
+ .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */
+#endif
+ .walat = 1, /* Write additional latency */
+ .ralat = 5, /* Read additional latency */
+ .mif3_mode = 3, /* Command prediction working mode */
+ .bi_on = 1, /* Bank interleaving enabled */
+ .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
+ .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
+ };
+
+ /*
+ * MMDC Calibration requires the following data:
+ * mx6_mmdc_calibration - board-specific calibration (routing delays)
+ * mx6_ddr_sysinfo - board-specific memory architecture (width/cs/etc)
+ * mx6_ddr_cfg - chip specific timing/layout details
+ */
+ switch (board_model) {
+ default:
+ case GW51xx:
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ calib = &gw51xxq_mmdc_calib;
+ else
+ calib = &gw51xxdl_mmdc_calib;
+ break;
+ case GW52xx:
+ calib = &gw52xxdl_mmdc_calib;
+ break;
+ case GW53xx:
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ calib = &gw53xxq_mmdc_calib;
+ else
+ calib = &gw53xxdl_mmdc_calib;
+ break;
+ case GW54xx:
+ calib = &gw54xxq_mmdc_calib;
+ break;
+ }
+
+ if (is_cpu_type(MXC_CPU_MX6Q))
+ mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs,
+ &mx6dq_grp_ioregs);
+ else
+ mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs,
+ &mx6sdl_grp_ioregs);
+ mx6_dram_cfg(&sysinfo, calib, mem);
+}
+
+/*
+ * called from C runtime startup code (arch/arm/lib/crt0.S:_main)
+ * - we have a stack and a place to store GD, both in SRAM
+ * - no variable global data is available
+ */
+void board_init_f(ulong dummy)
+{
+ struct ventana_board_info ventana_info;
+ int board_model;
+
+ /*
+ * Zero out global data:
+ * - this shoudl be done by crt0.S
+ * - failure to zero it will cause i2c_setup to fail
+ */
+ memset((void *)gd, 0, sizeof(struct global_data));
+
+ /* setup AIPS and disable watchdog */
+ arch_cpu_init();
+
+ /* iomux and setup of i2c */
+ board_early_init_f();
+ i2c_setup_iomux();
+
+ /* setup GP timer */
+ timer_init();
+
+ /* UART clocks enabled and gd valid - init serial console */
+ preloader_console_init();
+
+ /* read/validate EEPROM info to determine board model and SDRAM cfg */
+ board_model = read_eeprom(I2C_GSC, &ventana_info);
+
+ /* provide some some default: 32bit 128MB */
+ if (GW_UNKNOWN == board_model) {
+ ventana_info.sdram_width = 2;
+ ventana_info.sdram_size = 3;
+ }
+
+ /* configure MMDC for SDRAM width/size and per-model calibration */
+ spl_dram_init(8 << ventana_info.sdram_width,
+ 16 << ventana_info.sdram_size,
+ board_model);
+
+ /* Clear the BSS. */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ /* load/boot image from boot device */
+ board_init_r(NULL, 0);
+}
+
+void reset_cpu(ulong addr)
+{
+}
EECONFIG_RES15,
};
+enum {
+ GW54proto, /* original GW5400-A prototype */
+ GW51xx,
+ GW52xx,
+ GW53xx,
+ GW54xx,
+ GW_UNKNOWN,
+};
+
+int read_eeprom(int bus, struct ventana_board_info *);
+
#endif
for (fpga = 0; fpga < 2; ++fpga) {
for (k = 0; k < 32; ++k) {
u16 status;
- FPGA_GET_REG(k, ch[k].status_int, &status);
+ FPGA_GET_REG(fpga, ch[k].status_int, &status);
if (!(status & (1 << 4))) {
failed = 1;
printf("fpga %d channel %d: no serdes lock\n",
for (fpga = 0; fpga < 2; ++fpga) {
for (k = 0; k < 32; ++k) {
u16 status;
- FPGA_GET_REG(k, hicb_ch[k].status_int, &status);
+ FPGA_GET_REG(fpga, hicb_ch[k].status_int, &status);
if (status)
printf("fpga %d hicb %d: hicb status %04x\n",
fpga, k, status);
#include <i2c.h>
#include <mmc.h>
#include <tpm.h>
-#include <sha1.h>
+#include <u-boot/sha1.h>
#include <asm/byteorder.h>
#include <asm/unaligned.h>
#include <pca9698.h>
#ifdef CONFIG_TRAILBLAZER
int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- int rcode = 0;
-
- if (run_command(getenv("bootcmd"), flag) < 0)
- rcode = 1;
- return rcode;
+ return run_command(getenv("bootcmd"), flag);
}
int board_early_init_r(void)
+++ /dev/null
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = hidden_dragon.o flash.o
+++ /dev/null
-U-Boot for Hidden Dragon board
-------------------------------
-
-Hidden Dragon is a MPC824x-based board by Motorola. For the most
-part it is similar to Sandpoint8245 board. So unless otherwise
-mentioned, the codes in this directory are adapted from ../sandpoint
-directory.
-
-Apparently there are very few of this board out there. Even Motorola
-website does not have any info on it.
-
-RAM:
- start = 0x0000 0000
- size = 0x0200 0000 (32 MB)
-
-Flash:
- BANK ONE:
- start = 0xFFE0 0000
- size = 0x0020 0000 (2 MB)
- flash chip = 29LV160TE (1x16 Mbits or 2x8 Mbits)
- flash sectors = 16K, 2x8K, 32K, 31x64K
-
- BANK TWO:
- NONE
-
-The processor interrupt vectors reside on the first 256 bytes
-starting from address 0xFFF00000. The "reset vector" (first
-instruction executed after reset) is located on 0xFFF0 0100.
-
-U-Boot is configured to reside in flash starting at the address of
-0xFFF00000. The environment space is located in flash separately from
-U-Boot, at the second sector of the first flash bank, starting from
-0xFFE04000 until 0xFFE06000 (8KB).
-
-Network:
- - RTL8139 chip on the base board (SUPPORTED)
- - RTL8129 chip on the processor board (NOT SUPPORTED)
-
-Serial:
- - Two NS16550 compatible UART on the processor board (SUPPORTED)
- - One NS16550 compatible UART on the base board (UNTESTED)
-
-Misc:
- VIA686A PCI SuperIO peripheral controller
- - 2 USB ports (UNTESTED)
- - 2 PS2 ports (UNTESTED)
- - Parallel port (UNTESTED)
- - IDE & floppy interface (UNTESTED)
-
- S3 Savage4 video card (UNTESTED)
-
-TODO:
------
-- Support for the VIA686A based peripherals
-- The RTL8139 driver frequently gives rx error.
-- Support for RTL8129 network controller. (Why is the support removed from
- rtl8139.c driver?)
-
-(C) Copyright 2004
-Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
- *
- * (C) Copyright 2000-2005
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <asm/processor.h>
-#include <asm/pci_io.h>
-#include <w83c553f.h>
-
-#define ROM_CS0_START 0xFF800000
-#define ROM_CS1_START 0xFF000000
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-
-/*flash command address offsets*/
-
-#define ADDR0 (0xAAA)
-#define ADDR1 (0x555)
-#define ADDR3 (0x001)
-
-#define FLASH_WORD_SIZE unsigned char
-
-/*-----------------------------------------------------------------------
- */
-
-static unsigned long flash_id (unsigned char mfct, unsigned char chip)
- __attribute__ ((const));
-
-typedef struct {
- FLASH_WORD_SIZE extval;
- unsigned short intval;
-} map_entry;
-
-static unsigned long flash_id (unsigned char mfct, unsigned char chip)
-{
- static const map_entry mfct_map[] = {
- {(FLASH_WORD_SIZE) AMD_MANUFACT,
- (unsigned short) ((unsigned long) FLASH_MAN_AMD >> 16)},
- {(FLASH_WORD_SIZE) FUJ_MANUFACT,
- (unsigned short) ((unsigned long) FLASH_MAN_FUJ >> 16)},
- {(FLASH_WORD_SIZE) STM_MANUFACT,
- (unsigned short) ((unsigned long) FLASH_MAN_STM >> 16)},
- {(FLASH_WORD_SIZE) MT_MANUFACT,
- (unsigned short) ((unsigned long) FLASH_MAN_MT >> 16)},
- {(FLASH_WORD_SIZE) INTEL_MANUFACT,
- (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)},
- {(FLASH_WORD_SIZE) INTEL_ALT_MANU,
- (unsigned short) ((unsigned long) FLASH_MAN_INTEL >> 16)}
- };
-
- static const map_entry chip_map[] = {
- {AMD_ID_F040B, FLASH_AM040},
- {(FLASH_WORD_SIZE) STM_ID_x800AB, FLASH_STM800AB}
- };
-
- const map_entry *p;
- unsigned long result = FLASH_UNKNOWN;
-
- /* find chip id */
- for (p = &chip_map[0];
- p < &chip_map[sizeof chip_map / sizeof chip_map[0]]; p++)
- if (p->extval == chip) {
- result = FLASH_VENDMASK | p->intval;
- break;
- }
-
- /* find vendor id */
- for (p = &mfct_map[0];
- p < &mfct_map[sizeof mfct_map / sizeof mfct_map[0]]; p++)
- if (p->extval == mfct) {
- result &= ~FLASH_VENDMASK;
- result |= (unsigned long) p->intval << 16;
- break;
- }
-
- return result;
-}
-
-unsigned long flash_init (void)
-{
- unsigned long i;
- unsigned char j;
- static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS;
-
- /* Init: no FLASHes known */
- for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
- flash_info_t *const pflinfo = &flash_info[i];
-
- pflinfo->flash_id = FLASH_UNKNOWN;
- pflinfo->size = 0;
- pflinfo->sector_count = 0;
- }
-
- /* Enable writes to Hidden Dragon flash */
- {
- register unsigned char temp;
-
- CONFIG_READ_BYTE (CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR,
- temp);
- temp &= ~0x20; /* clear BIOSWP bit */
- CONFIG_WRITE_BYTE (CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR,
- temp);
- }
-
- for (i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++) {
- flash_info_t *const pflinfo = &flash_info[i];
- const unsigned long base_address = flash_banks[i];
- volatile FLASH_WORD_SIZE *const flash =
- (FLASH_WORD_SIZE *) base_address;
-
- flash[0xAAA << (3 * i)] = 0xaa;
- flash[0x555 << (3 * i)] = 0x55;
- flash[0xAAA << (3 * i)] = 0x90;
- __asm__ __volatile__ ("sync");
-
- pflinfo->flash_id =
- flash_id (flash[0x0], flash[0x2 + 14 * i]);
-
- switch (pflinfo->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- pflinfo->size = 0x00080000;
- pflinfo->sector_count = 8;
- for (j = 0; j < 8; j++) {
- pflinfo->start[j] =
- base_address + 0x00010000 * j;
- pflinfo->protect[j] = flash[(j << 16) | 0x2];
- }
- break;
- case FLASH_STM800AB:
- pflinfo->size = 0x00100000;
- pflinfo->sector_count = 19;
- pflinfo->start[0] = base_address;
- pflinfo->start[1] = base_address + 0x4000;
- pflinfo->start[2] = base_address + 0x6000;
- pflinfo->start[3] = base_address + 0x8000;
- for (j = 1; j < 16; j++) {
- pflinfo->start[j + 3] =
- base_address + 0x00010000 * j;
- }
- break;
- default:
- /* The chip used is not listed in flash_id
- TODO: Change this to explicitly detect the flash type
- */
- {
- int sector_addr = base_address;
-
- pflinfo->size = 0x00200000;
- pflinfo->sector_count = 35;
- pflinfo->start[0] = sector_addr;
- sector_addr += 0x4000; /* 16K */
- pflinfo->start[1] = sector_addr;
- sector_addr += 0x2000; /* 8K */
- pflinfo->start[2] = sector_addr;
- sector_addr += 0x2000; /* 8K */
- pflinfo->start[3] = sector_addr;
- sector_addr += 0x8000; /* 32K */
-
- for (j = 4; j < 35; j++) {
- pflinfo->start[j] = sector_addr;
- sector_addr += 0x10000; /* 64K */
- }
- }
- break;
- }
- /* Protect monitor and environment sectors
- */
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
- &flash_info[0]);
-#endif
-
-#if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
- flash_protect (FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
- &flash_info[0]);
-#endif
-
- /* reset device to read mode */
- flash[0x0000] = 0xf0;
- __asm__ __volatile__ ("sync");
- }
-
- /* only have 1 bank */
- return flash_info[0].size;
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t * info)
-{
- static const char unk[] = "Unknown";
- const char *mfct = unk, *type = unk;
- unsigned int i;
-
- if (info->flash_id != FLASH_UNKNOWN) {
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_AMD:
- mfct = "AMD";
- break;
- case FLASH_MAN_FUJ:
- mfct = "FUJITSU";
- break;
- case FLASH_MAN_STM:
- mfct = "STM";
- break;
- case FLASH_MAN_SST:
- mfct = "SST";
- break;
- case FLASH_MAN_BM:
- mfct = "Bright Microelectonics";
- break;
- case FLASH_MAN_INTEL:
- mfct = "Intel";
- break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_AM040:
- type = "AM29F040B (512K * 8, uniform sector size)";
- break;
- case FLASH_AM400B:
- type = "AM29LV400B (4 Mbit, bottom boot sect)";
- break;
- case FLASH_AM400T:
- type = "AM29LV400T (4 Mbit, top boot sector)";
- break;
- case FLASH_AM800B:
- type = "AM29LV800B (8 Mbit, bottom boot sect)";
- break;
- case FLASH_AM800T:
- type = "AM29LV800T (8 Mbit, top boot sector)";
- break;
- case FLASH_AM160T:
- type = "AM29LV160T (16 Mbit, top boot sector)";
- break;
- case FLASH_AM320B:
- type = "AM29LV320B (32 Mbit, bottom boot sect)";
- break;
- case FLASH_AM320T:
- type = "AM29LV320T (32 Mbit, top boot sector)";
- break;
- case FLASH_STM800AB:
- type = "M29W800AB (8 Mbit, bottom boot sect)";
- break;
- case FLASH_SST800A:
- type = "SST39LF/VF800 (8 Mbit, uniform sector size)";
- break;
- case FLASH_SST160A:
- type = "SST39LF/VF160 (16 Mbit, uniform sector size)";
- break;
- }
- }
-
- printf ("\n Brand: %s Type: %s\n"
- " Size: %lu KB in %d Sectors\n",
- mfct, type, info->size >> 10, info->sector_count);
-
- printf (" Sector Start Addresses:");
-
- for (i = 0; i < info->sector_count; i++) {
- unsigned long size;
- unsigned int erased;
- unsigned long *flash = (unsigned long *) info->start[i];
-
- /*
- * Check if whole sector is erased
- */
- size = (i != (info->sector_count - 1)) ?
- (info->start[i + 1] - info->start[i]) >> 2 :
- (info->start[0] + info->size - info->start[i]) >> 2;
-
- for (flash = (unsigned long *) info->start[i], erased = 1;
- (flash != (unsigned long *) info->start[i] + size)
- && erased; flash++)
- erased = *flash == ~0x0UL;
-
- printf ("%s %08lX %s %s",
- (i % 5) ? "" : "\n ",
- info->start[i],
- erased ? "E" : " ", info->protect[i] ? "RO" : " ");
- }
-
- puts ("\n");
- return;
-}
-
-int flash_erase (flash_info_t * info, int s_first, int s_last)
-{
- volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
- int flag, prot, sect, l_sect;
- ulong start, now, last;
- unsigned char sh8b;
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ((info->flash_id == FLASH_UNKNOWN) ||
- (info->flash_id > (FLASH_MAN_STM | FLASH_AMD_COMP))) {
- printf ("Can't erase unknown flash type - aborted\n");
- return 1;
- }
-
- prot = 0;
- for (sect = s_first; sect <= s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n", prot);
- } else {
- printf ("\n");
- }
-
- l_sect = -1;
-
- /* Check the ROM CS */
- if ((info->start[0] >= ROM_CS1_START)
- && (info->start[0] < ROM_CS0_START))
- sh8b = 3;
- else
- sh8b = 0;
-
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00800080;
- addr[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
-
- /* Start erase on unprotected sectors */
- for (sect = s_first; sect <= s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- addr = (FLASH_WORD_SIZE *) (info->start[0] +
- ((info->start[sect] -
- info->start[0]) << sh8b));
- if (info->flash_id & FLASH_MAN_SST) {
- addr[ADDR0 << sh8b] =
- (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1 << sh8b] =
- (FLASH_WORD_SIZE) 0x00550055;
- addr[ADDR0 << sh8b] =
- (FLASH_WORD_SIZE) 0x00800080;
- addr[ADDR0 << sh8b] =
- (FLASH_WORD_SIZE) 0x00AA00AA;
- addr[ADDR1 << sh8b] =
- (FLASH_WORD_SIZE) 0x00550055;
- addr[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */
- udelay (30000); /* wait 30 ms */
- } else
- addr[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */
- l_sect = sect;
- }
- }
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* wait at least 80us - let's wait 1 ms */
- udelay (1000);
-
- /*
- * We wait for the last triggered sector
- */
- if (l_sect < 0)
- goto DONE;
-
- start = get_timer (0);
- last = start;
- addr = (FLASH_WORD_SIZE *) (info->start[0] + ((info->start[l_sect] -
- info->
- start[0]) << sh8b));
- while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
- (FLASH_WORD_SIZE) 0x00800080) {
- if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- serial_putc ('.');
- last = now;
- }
- }
-
- DONE:
- /* reset to read mode */
- addr = (FLASH_WORD_SIZE *) info->start[0];
- addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
-
- printf (" done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data;
- int i, l, rc;
-
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i = 0, cp = wp; i < l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
- for (; i < 4 && cnt > 0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt == 0 && i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i = 0; i < 4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word (info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i < 4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *) cp);
- }
-
- return (write_word (info, wp, data));
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t * info, ulong dest, ulong data)
-{
- volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) info->start[0];
- volatile FLASH_WORD_SIZE *dest2;
- volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data;
- ulong start;
- int flag;
- int i;
- unsigned char sh8b;
-
- /* Check the ROM CS */
- if ((info->start[0] >= ROM_CS1_START)
- && (info->start[0] < ROM_CS0_START))
- sh8b = 3;
- else
- sh8b = 0;
-
- dest2 = (FLASH_WORD_SIZE *) (((dest - info->start[0]) << sh8b) +
- info->start[0]);
-
- /* Check if Flash is (sufficiently) erased */
- if ((*dest2 & (FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts ();
-
- for (i = 0; i < 4 / sizeof (FLASH_WORD_SIZE); i++) {
- addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00AA00AA;
- addr2[ADDR1 << sh8b] = (FLASH_WORD_SIZE) 0x00550055;
- addr2[ADDR0 << sh8b] = (FLASH_WORD_SIZE) 0x00A000A0;
-
- dest2[i << sh8b] = data2[i];
-
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts ();
-
- /* data polling for D7 */
- start = get_timer (0);
- while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) !=
- (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
- if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- return (1);
- }
- }
- }
-
- return (0);
-}
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
- *
- * (C) Copyright 2000
- * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc824x.h>
-#include <pci.h>
-#include <netdev.h>
-
-int checkboard (void)
-{
- /*TODO: Check processor type */
-
- puts ( "Board: Hidden Dragon "
-#ifdef CONFIG_MPC8240
- "8240"
-#endif
-#ifdef CONFIG_MPC8245
- "8245"
-#endif
- " ##Test not implemented yet##\n");
- /* TODO: Implement board test */
- return 0;
-}
-
-phys_size_t initdram (int board_type)
-{
- long size;
- long new_bank0_end;
- long mear1;
- long emear1;
-
- size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
-
- new_bank0_end = size - 1;
- mear1 = mpc824x_mpc107_getreg(MEAR1);
- emear1 = mpc824x_mpc107_getreg(EMEAR1);
- mear1 = (mear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
- emear1 = (emear1 & 0xFFFFFF00) |
- ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
- mpc824x_mpc107_setreg(MEAR1, mear1);
- mpc824x_mpc107_setreg(EMEAR1, emear1);
-
- return (size);
-}
-
-/*
- * Initialize PCI Devices, report devices found.
- */
-#ifndef CONFIG_PCI_PNP
-static struct pci_config_table pci_hidden_dragon_config_table[] = {
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
- PCI_ENET0_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
- { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
- pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
- PCI_ENET1_MEMADDR,
- PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
- { }
-};
-#endif
-
-struct pci_controller hose = {
-#ifndef CONFIG_PCI_PNP
- config_table: pci_hidden_dragon_config_table,
-#endif
-};
-
-void pci_init_board(void)
-{
- pci_mpc824x_init(&hose);
-}
-
-int board_eth_init(bd_t *bis)
-{
- return pci_eth_init(bis);
-}
*/
#include <common.h>
+#include <bootretry.h>
+#include <cli.h>
#include <mpc8260.h>
#include <mpc8260_irq.h>
#include <ioports.h>
hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
int rc;
-#ifdef CONFIG_BOOT_RETRY_TIME
/*
- * we use the readline () function, but we also want
+ * we use the cli_readline() function, but we also want
* command timeout enabled
*/
- init_cmd_timeout ();
-#endif
+ bootretry_init_cmd_timeout();
memset ((void *) cp, 0, sizeof (*cp));
*/
#include <common.h>
+#include <bootretry.h>
+#include <cli.h>
int
hymod_get_serno (const char *prompt)
int n, serno;
char *p;
-#ifdef CONFIG_BOOT_RETRY_TIME
- reset_cmd_timeout ();
-#endif
+ bootretry_reset_cmd_timeout();
- n = readline (prompt);
+ n = cli_readline(prompt);
if (n < 0)
return (n);
for (;;) {
int n;
-#ifdef CONFIG_BOOT_RETRY_TIME
- reset_cmd_timeout ();
-#endif
+ bootretry_reset_cmd_timeout();
- n = readline ("Enter board ethernet address: ");
+ n = cli_readline("Enter board ethernet address: ");
if (n < 0)
return (n);
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# Copyright (C) 2004 Arabella Software Ltd.
-# Yuli Barcohen <yuli@arabellasw.com>
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := ispan.o
+++ /dev/null
-/*
- * Copyright (C) 2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * Support for Interphase iSPAN Communications Controllers
- * (453x and others). Tested on 4532.
- *
- * Derived from iSPAN 4539 port (iphase4539) by
- * Wolfgang Grandegger <wg@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <asm/io.h>
-
-/*
- * I/O Ports configuration table
- *
- * If conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1)
-#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2)
-#define CONFIG_SYS_FCC3 (CONFIG_ETHER_INDEX == 3)
-
-const iop_conf_t iop_conf_tab[4][32] = {
- /* Port A */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
- /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
- /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
- /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
- /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
- /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
- /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
- /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
- /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
- /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */
- /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
- /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
- /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
- /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
- /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
- /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
- /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
- /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
- /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
- /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
- /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
- /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
- /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 SMTXD */
- /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 SMRXD */
- /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
- /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
- /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
- },
-
- /* Port B */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
- /* PB16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
- /* PB15 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
- /* PB14 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
- /* PB13 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
- /* PB12 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
- /* PB11 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */
- /* PB10 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */
- /* PB9 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */
- /* PB8 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */
- /* PB7 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */
- /* PB6 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */
- /* PB5 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */
- /* PB4 */ { CONFIG_SYS_FCC3, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
- /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
- /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
- /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */
- /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
- /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
- /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */
- /* PC18 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Rx Clock (CLK14) */
- /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
- /* PC16 */ { CONFIG_SYS_FCC3, 1, 0, 0, 0, 0 }, /* FCC3 MII Tx Clock (CLK16) */
- /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
- /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
- /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
- /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* PC9 */
- /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
- /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
- /* PC0 */ { 0, 0, 0, 0, 0, 0 } /* PC0 */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 0, 0, 0, 0, 0, 0 }, /* PD31 */
- /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */
- /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
- /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 1, 1, 0, 0, 0 }, /* SPICLK */
- /* PD17 */ { 0, 1, 1, 0, 0, 0 }, /* SPIMOSI */
- /* PD16 */ { 0, 1, 1, 0, 0, 0 }, /* SPIMISO */
- /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
- /* PD13 */ { 1, 0, 0, 0, 0, 0 }, /* MII MDIO */
- /* PD12 */ { 1, 0, 0, 1, 0, 0 }, /* MII MDC */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 SMTXD */
- /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 SMRXD */
- /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
- /* PD6 */ { CONFIG_SYS_FCC3, 0, 0, 1, 0, 1 }, /* MII PHY Reset */
- /* PD5 */ { CONFIG_SYS_FCC3, 0, 0, 1, 0, 0 }, /* MII PHY Enable */
- /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-#define PSPAN_ADDR 0xF0020000
-#define EEPROM_REG 0x408
-#define EEPROM_READ_CMD 0xA000
-#define PSPAN_WRITE(a,v) \
- *((volatile unsigned long *)(PSPAN_ADDR+(a))) = v; eieio()
-#define PSPAN_READ(a) \
- *((volatile unsigned long *)(PSPAN_ADDR+(a)))
-
-static int seeprom_read (int addr, uchar * data, int size)
-{
- ulong val, cmd;
- int i;
-
- for (i = 0; i < size; i++) {
-
- cmd = EEPROM_READ_CMD;
- cmd |= ((addr + i) << 24) & 0xff000000;
-
- /* Wait for ACT to authorize write */
- while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
- eieio ();
-
- /* Write command */
- PSPAN_WRITE (EEPROM_REG, cmd);
-
- /* Wait for data to be valid */
- while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
- eieio ();
- /* Do it twice, first read might be erratic */
- while ((val = PSPAN_READ (EEPROM_REG)) & 0x80)
- eieio ();
-
- /* Read error */
- if (val & 0x00000040) {
- return -1;
- } else {
- data[i] = (val >> 16) & 0xff;
- }
- }
- return 0;
-}
-
-/***************************************************************
- * We take some basic Hardware Configuration Parameter from the
- * Serial EEPROM conected to the PSpan bridge. We keep it as
- * simple as possible.
- */
-#ifdef DEBUG
-static int hwc_flash_size (void)
-{
- uchar byte;
-
- if (!seeprom_read (0x40, &byte, sizeof (byte))) {
- switch ((byte >> 2) & 0x3) {
- case 0x1:
- return 0x0400000;
- break;
- case 0x2:
- return 0x0800000;
- break;
- case 0x3:
- return 0x1000000;
- default:
- return 0x0100000;
- }
- }
- return -1;
-}
-
-static int hwc_local_sdram_size (void)
-{
- uchar byte;
-
- if (!seeprom_read (0x40, &byte, sizeof (byte))) {
- switch ((byte & 0x03)) {
- case 0x1:
- return 0x0800000;
- case 0x2:
- return 0x1000000;
- default:
- return 0; /* not present */
- }
- }
- return -1;
-}
-#endif /* DEBUG */
-
-static int hwc_main_sdram_size (void)
-{
- uchar byte;
-
- if (!seeprom_read (0x41, &byte, sizeof (byte))) {
- return 0x1000000 << ((byte >> 5) & 0x7);
- }
- return -1;
-}
-
-static int hwc_serial_number (void)
-{
- int sn = -1;
-
- if (!seeprom_read (0xa0, (uchar *) &sn, sizeof (sn))) {
- sn = cpu_to_le32 (sn);
- }
- return sn;
-}
-
-static int hwc_mac_address (char *str)
-{
- char mac[6];
-
- if (!seeprom_read (0xb0, (uchar *)mac, sizeof (mac))) {
- sprintf (str, "%02X:%02X:%02X:%02X:%02X:%02X",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
- } else {
- strcpy (str, "ERROR");
- return -1;
- }
- return 0;
-}
-
-static int hwc_manufact_date (char *str)
-{
- uchar byte;
- int value;
-
- if (seeprom_read (0x92, &byte, sizeof (byte)))
- goto out;
- value = byte;
- if (seeprom_read (0x93, &byte, sizeof (byte)))
- goto out;
- value += byte << 8;
- sprintf (str, "%02d/%02d/%04d",
- value & 0x1F, (value >> 5) & 0xF,
- 1980 + ((value >> 9) & 0x1FF));
- return 0;
-
-out:
- strcpy (str, "ERROR");
- return -1;
-}
-
-static int hwc_board_type (char **str)
-{
- ushort id = 0;
-
- if (seeprom_read (7, (uchar *) & id, sizeof (id)) == 0) {
- switch (id) {
- case 0x9080:
- *str = "4532-002";
- break;
- case 0x9081:
- *str = "4532-001";
- break;
- case 0x9082:
- *str = "4532-000";
- break;
- default:
- *str = "Unknown";
- }
- } else {
- *str = "Unknown";
- }
-
- return id;
-}
-
-phys_size_t initdram (int board_type)
-{
- long maxsize = hwc_main_sdram_size();
-
-#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_USE_FIRMWARE)
- volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
- volatile uchar *base;
- int i;
-
- immap->im_siu_conf.sc_ppc_acr = 0x00000026;
- immap->im_siu_conf.sc_ppc_alrh = 0x01276345;
- immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
- immap->im_siu_conf.sc_lcl_acr = 0x00000000;
- immap->im_siu_conf.sc_lcl_alrh = 0x01234567;
- immap->im_siu_conf.sc_lcl_alrl = 0x89ABCDEF;
- immap->im_siu_conf.sc_tescr1 = 0x00004000;
- immap->im_siu_conf.sc_ltescr1 = 0x00004000;
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
- /* Initialise 60x bus SDRAM */
- base = (uchar *)(CONFIG_SYS_SDRAM_BASE | 0x110);
- memctl->memc_psrt = CONFIG_SYS_PSRT;
- memctl->memc_or1 = CONFIG_SYS_60x_OR;
- memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | CONFIG_SYS_60x_BR;
-
- memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x28000000;
- *base = 0xFF;
- memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x08000000;
- for (i = 0; i < 8; i++)
- *base = 0xFF;
- memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x18000000;
- *base = 0xFF;
- memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x40000000;
-
- /* Initialise local bus SDRAM */
- base = (uchar *)CONFIG_SYS_LSDRAM_BASE;
- memctl->memc_lsrt = CONFIG_SYS_LSRT;
- memctl->memc_or2 = CONFIG_SYS_LOC_OR;
- memctl->memc_br2 = CONFIG_SYS_LSDRAM_BASE | CONFIG_SYS_LOC_BR;
-
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x28000000;
- *base = 0xFF;
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x08000000;
- for (i = 0; i < 8; i++)
- *base = 0xFF;
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x18000000;
- *base = 0xFF;
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x40000000;
-
- /* We must be able to test a location outsize the maximum legal size
- * to find out THAT we are outside; but this address still has to be
- * mapped by the controller. That means, that the initial mapping has
- * to be (at least) twice as large as the maximum expected size.
- */
- maxsize = (~(memctl->memc_or1 & BRx_BA_MSK) + 1) / 2;
-
- maxsize = get_ram_size((long *)(memctl->memc_br1 & BRx_BA_MSK), maxsize);
-
- memctl->memc_or1 |= ~(maxsize - 1);
-
- if (maxsize != hwc_main_sdram_size())
- puts("Oops: memory test has not found all memory!\n");
-#endif /* !CONFIG_SYS_RAMBOOT && !CONFIG_SYS_USE_FIRMWARE */
-
- /* Return total RAM size (size of 60x SDRAM) */
- return maxsize;
-}
-
-int checkboard(void)
-{
- char string[32], *id;
-
- hwc_manufact_date(string);
- hwc_board_type(&id);
- printf("Board: Interphase iSPAN %s (#%d %s)\n",
- id, hwc_serial_number(), string);
-#ifdef DEBUG
- printf("Manufacturing date: %s\n", string);
- printf("Serial number : %d\n", hwc_serial_number());
- printf("FLASH size : %d MB\n", hwc_flash_size() >> 20);
- printf("Main SDRAM size : %d MB\n", hwc_main_sdram_size() >> 20);
- printf("Local SDRAM size : %d MB\n", hwc_local_sdram_size() >> 20);
- hwc_mac_address(string);
- printf("MAC address : %s\n", string);
-#endif
- return 0;
-}
-
-int misc_init_r(void)
-{
- char *s, str[32];
- int num;
-
- if ((s = getenv("serial#")) == NULL &&
- (num = hwc_serial_number()) != -1) {
- sprintf(str, "%06d", num);
- setenv("serial#", str);
- }
- if ((s = getenv("ethaddr")) == NULL && hwc_mac_address(str) == 0) {
- setenv("ethaddr", str);
- }
-
- return 0;
-}
#include <ioports.h>
#include <command.h>
#include <malloc.h>
-#include <hush.h>
+#include <cli_hush.h>
#include <net.h>
#include <netdev.h>
#include <asm/io.h>
*/
#include <common.h>
-#include <hush.h>
+#include <cli_hush.h>
#include <i2c.h>
#include "common.h"
/* Look for the requested number of CR. */
while ((cr != nr) && (addr < INVENTORYDATASIZE)) {
- if ((buf[addr] == '\r'))
+ if (buf[addr] == '\r')
cr++;
addr++;
}
extra-y := bootscript.img
-quiet_cmd_mkimage = MKIMAGE $@
-cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
- $(if $(KBUILD_VERBOSE:1=), >/dev/null)
-
MKIMAGEFLAGS_bootscript.image := -T script -C none -n M7_script
$(obj)/bootscript.img: $(src)/bootscript
extra-y := bootscript.img
-quiet_cmd_mkimage = MKIMAGE $@
-cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
- $(if $(KBUILD_VERBOSE:1=), >/dev/null)
-
MKIMAGEFLAGS_bootscript.image := -T script -C none -n mvSMR_Script
$(obj)/bootscript.img: $(src)/bootscript
#include <usb.h>
#include <part.h>
-#ifdef CONFIG_SYS_HUSH_PARSER
-#include <hush.h>
-#endif
-
-
#ifdef CONFIG_AUTO_UPDATE
#ifndef CONFIG_USB_OHCI
/* parse_string_outer() runs off the end. */
addr[image_get_data_size (hdr)] = 0;
addr += 8;
- parse_string_outer(addr, FLAG_PARSE_SEMICOLON);
+ run_command_list(addr, -1, 0);
return 0;
}
#include <asm/processor.h>
#include <spd_sdram.h>
#include <status_led.h>
-#include <sha1.h>
+#include <u-boot/sha1.h>
#include <asm/io.h>
#include <net.h>
#include <ata.h>
#include <common.h>
-#if defined(CONFIG_NIOS)
-#include <nios.h>
-#else
#include <asm/io.h>
-#endif
#define SECTSZ (64 * 1024)
flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = quad100hd.o nand.o
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <config.h>
-#if defined(CONFIG_CMD_NAND)
-#include <asm/ppc4xx-gpio.h>
-#include <asm/io.h>
-#include <nand.h>
-
-/*
- * hardware specific access to control-lines
- */
-static void quad100hd_hwcontrol(struct mtd_info *mtd,
- int cmd, unsigned int ctrl)
-{
- struct nand_chip *this = mtd->priv;
-
- if (ctrl & NAND_CTRL_CHANGE) {
- gpio_write_bit(CONFIG_SYS_NAND_CLE, !!(ctrl & NAND_CLE));
- gpio_write_bit(CONFIG_SYS_NAND_ALE, !!(ctrl & NAND_ALE));
- gpio_write_bit(CONFIG_SYS_NAND_CE, !(ctrl & NAND_NCE));
- }
-
- if (cmd != NAND_CMD_NONE)
- writeb(cmd, this->IO_ADDR_W);
-}
-
-static int quad100hd_nand_ready(struct mtd_info *mtd)
-{
- return gpio_read_in_bit(CONFIG_SYS_NAND_RDY);
-}
-
-/*
- * Main initialization routine
- */
-int board_nand_init(struct nand_chip *nand)
-{
- /* Set address of hardware control function */
- nand->cmd_ctrl = quad100hd_hwcontrol;
- nand->dev_ready = quad100hd_nand_ready;
- nand->ecc.mode = NAND_ECC_SOFT;
- /* 15 us command delay time */
- nand->chip_delay = 20;
-
- /* Return happy */
- return 0;
-}
-#endif /* CONFIG_CMD_NAND */
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
- *
- * Based in part on board/icecube/icecube.c from PPCBoot
- * (C) Copyright 2003 Intrinsyc Software
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <command.h>
-#include <malloc.h>
-#include <environment.h>
-#include <logbuff.h>
-#include <post.h>
-
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <asm/ppc4xx-gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int board_early_init_f(void)
-{
- /* taken from PPCBoot */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000);
- mtdcr(UIC0PR, 0xFFFF7FFE); /* set int polarities */
- mtdcr(UIC0TR, 0x00000000); /* set int trigger levels */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority */
-
- mtdcr(CPC0_SRR, 0x00040000); /* Hold PCI bridge in reset */
-
- return 0;
-}
-
-/*
- * Check Board Identity:
- */
-int checkboard(void)
-{
- char buf[64];
- int i = getenv_f("serial#", buf, sizeof(buf));
-#ifdef DISPLAY_BOARD_INFO
- sys_info_t sysinfo;
-#endif
-
- puts("Board: Quad100hd");
-
- if (i > 0) {
- puts(", serial# ");
- puts(buf);
- }
- putc('\n');
-
-#ifdef DISPLAY_BOARD_INFO
- /* taken from ppcboot */
- get_sys_info(&sysinfo);
-
- printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz);
- printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
- printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
- printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
- printf("\tEPB: %lu MHz\n", sysinfo.freqPLB / (sysinfo.pllExtBusDiv *
- 1000000));
- printf("\tPCI: %lu MHz\n", sysinfo.freqPCI / 1000000);
-#endif
-
- return 0;
-}
+++ /dev/null
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := rattler.o
+++ /dev/null
-/*
- * Copyright (C) 2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * Support for Analogue&Micro Rattler boards family.
- * Tested on Rattler8248.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc8260.h>
-#include <ioports.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1)
-#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2)
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */
- /* PA30 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */
- /* PA29 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */
- /* PA28 */ { CONFIG_SYS_FCC1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */
- /* PA27 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */
- /* PA26 */ { CONFIG_SYS_FCC1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */
- /* PA25 */ { 0, 0, 0, 0, 0, 0 }, /* PA25 */
- /* PA24 */ { 0, 0, 0, 0, 0, 0 }, /* PA24 */
- /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */
- /* PA22 */ { 1, 0, 0, 1, 0, 1 }, /* Eth PHYs reset */
- /* PA21 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */
- /* PA20 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */
- /* PA19 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */
- /* PA18 */ { CONFIG_SYS_FCC1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */
- /* PA17 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */
- /* PA16 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */
- /* PA15 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */
- /* PA14 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */
- /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */
- /* PA12 */ { 0, 0, 0, 0, 0, 0 }, /* PA12 */
- /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */
- /* PA10 */ { 0, 0, 0, 0, 0, 0 }, /* PA10 */
- /* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC2 TxD */
- /* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC2 RxD */
- /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
- /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
- /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
- },
-
- /* Port B */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { CONFIG_SYS_FCC2, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { CONFIG_SYS_FCC2, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB15 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB14 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB12 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB8 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */
- /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
- /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */
- /* PC22 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 TxClk (CLK10) */
- /* PC21 */ { CONFIG_SYS_FCC1, 1, 0, 0, 0, 0 }, /* FCC1 RxClk (CLK11) */
- /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
- /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */
- /* PC18 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 TxClk (CLK14) */
- /* PC17 */ { CONFIG_SYS_FCC2, 1, 0, 0, 0, 0 }, /* FCC2 RxClk (CLK15) */
- /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
- /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */
- /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
- /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */
- /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* MDIO */
- /* PC8 */ { 1, 0, 0, 1, 0, 1 }, /* MDC */
- /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
- /* PC5 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */
- /* PC4 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */
- /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
- /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
- /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */
- /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */
- /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */
- /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */
- /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */
- /* PD15 */ { 0, 0, 0, 0, 0, 0 }, /* PD15 */
- /* PD14 */ { 0, 0, 0, 0, 0, 0 }, /* PD14 */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 0, 0, 0, 0, 0 }, /* PD9 */
- /* PD8 */ { 0, 0, 0, 0, 0, 0 }, /* PD8 */
- /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */
- }
-};
-
-phys_size_t initdram(int board_type)
-{
- long int msize = CONFIG_SYS_SDRAM_SIZE;
-
-#ifndef CONFIG_SYS_RAMBOOT
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
- vu_char *ramaddr = (vu_char *)CONFIG_SYS_SDRAM_BASE;
- uchar c = 0xFF;
- uint psdmr = CONFIG_SYS_PSDMR;
- int i;
-
- immap->im_siu_conf.sc_ppc_acr = 0x02;
- immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
- immap->im_siu_conf.sc_tescr1 = 0x00004000;
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
- /* Initialise 60x bus SDRAM */
- memctl->memc_psrt = CONFIG_SYS_PSRT;
- memctl->memc_or1 = CONFIG_SYS_SDRAM_OR;
- memctl->memc_br1 = CONFIG_SYS_SDRAM_BR;
- memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
- *ramaddr = c;
- memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
- for (i = 0; i < 8; i++)
- *ramaddr = c;
- memctl->memc_psdmr = psdmr | PSDMR_OP_MRW; /* Mode Register write */
- *ramaddr = c;
- memctl->memc_psdmr = psdmr | PSDMR_RFEN; /* Refresh enable */
- *ramaddr = c;
-#endif /* !CONFIG_SYS_RAMBOOT */
-
- /* Return total 60x bus SDRAM size */
- return msize * 1024 * 1024;
-}
-
-int checkboard(void)
-{
- vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
-
- printf("Board: Rattler Rev. %c\n", bcsr[0x20] + 0x40);
- return 0;
-}
#ifdef CONFIG_LCD
vidinfo_t panel_info = {
- vl_col: 240,
- vl_row: 320,
- vl_clk: 4965000,
- vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
- ATMEL_LCDC_INVFRAME_INVERTED,
- vl_bpix: 3,
- vl_tft: 1,
- vl_hsync_len: 5,
- vl_left_margin: 1,
- vl_right_margin:33,
- vl_vsync_len: 1,
- vl_upper_margin:1,
- vl_lower_margin:0,
- mmio: ATMEL_BASE_LCDC,
+ .vl_col = 240,
+ .vl_row = 320,
+ .vl_clk = 4965000,
+ .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
+ ATMEL_LCDC_INVFRAME_INVERTED,
+ .vl_bpix = 3,
+ .vl_tft = 1,
+ .vl_hsync_len = 5,
+ .vl_left_margin = 1,
+ .vl_right_margin = 33,
+ .vl_vsync_len = 1,
+ .vl_upper_margin = 1,
+ .vl_lower_margin = 0,
+ .mmio = ATMEL_BASE_LCDC,
};
void lcd_enable(void)
#ifdef CONFIG_LCD
vidinfo_t panel_info = {
- vl_col: 240,
- vl_row: 320,
- vl_clk: 4965000,
- vl_sync: ATMEL_LCDC_INVLINE_INVERTED |
- ATMEL_LCDC_INVFRAME_INVERTED,
- vl_bpix: 3,
- vl_tft: 1,
- vl_hsync_len: 5,
- vl_left_margin: 1,
- vl_right_margin:33,
- vl_vsync_len: 1,
- vl_upper_margin:1,
- vl_lower_margin:0,
- mmio: ATMEL_BASE_LCDC,
+ .vl_col = 240,
+ .vl_row = 320,
+ .vl_clk = 4965000,
+ .vl_sync = ATMEL_LCDC_INVLINE_INVERTED |
+ ATMEL_LCDC_INVFRAME_INVERTED,
+ .vl_bpix = 3,
+ .vl_tft = 1,
+ .vl_hsync_len = 5,
+ .vl_left_margin = 1,
+ .vl_right_margin = 33,
+ .vl_vsync_len = 1,
+ .vl_upper_margin = 1,
+ .vl_lower_margin = 0,
+ .mmio = ATMEL_BASE_LCDC,
};
void lcd_enable(void)
+++ /dev/null
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := simpc8313.o sdram.o
+++ /dev/null
-Sheldon Instruments SIMPC8313 Board
------------------------------------------
-
-1. Board Switches and Jumpers
-
- S2 is used to set CFG_RESET_SOURCE.
-
- To boot the image in Large page NAND flash, use these DIP
- switch settings for S2:
-
- +----------+ ON
- | * * **** |
- | * * |
- +----------+
- 12345678
-
- To boot the image in Small page NAND flash, use these DIP
- switch settings for S2:
-
- +----------+ ON
- | *** **** |
- | * |
- +----------+
- 12345678
- (where the '*' indicates the position of the tab of the switch.)
-
-2. Memory Map
- The memory map looks like this:
-
- 0x0000_0000 0x1fff_ffff DDR 512M
- 0x8000_0000 0x8fff_ffff PCI MEM 256M
- 0x9000_0000 0x9fff_ffff PCI_MMIO 256M
- 0xe000_0000 0xe00f_ffff IMMR 1M
- 0xe200_0000 0xe20f_ffff PCI IO 16M
- 0xe280_0000 0xe280_7fff NAND FLASH (CS0) 32K
- or
- 0xe280_0000 0xe281_ffff NAND FLASH (CS0) 128K
- 0xff00_0000 0xff00_7fff FPGA (CS1) 1M
-
-3. Compilation
-
- Assuming you're using BASH (or similar) as your shell:
-
- export CROSS_COMPILE=your-cross-compiler-prefix-
- make distclean
- make SIMPC8313_LP_config
- (or make SIMPC8313_SP_config, depending on the page size
- of your NAND flash)
- make
-
-4. Downloading and Flashing Images
-
-4.1 Reflash U-boot Image using U-boot
-
- =>run update_uboot
-
- You may want to try
- =>tftp $loadaddr $uboot
- first, to make sure that the TFTP load will succeed before it
- goes ahead and wipes out your current firmware. And of course,
- if the new u-boot doesn't boot, you can plug the board into
- your PCI slot and with the supplied driver and sample app
- you can reburn a working u-boot.
-
-4.2 Downloading and Booting Linux Kernel
-
- Ensure that all networking-related environment variables are set
- properly (including ipaddr, serverip, gatewayip (if needed),
- netmask, ethaddr, eth1addr, fdtfile, and bootfile).
-
- =>tftp $loadaddr uImage
- =>nand write $loadaddr kernel $filesize
- =>tftp $loadaddr $fdtfile
- =>nand write $loadaddr 7e0000 1800
-
- =>boot
-
-5 Notes
-
- The console baudrate for SIMPC8313 is 115200bps.
+++ /dev/null
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
- * Copyright (C) Sheldon Instruments, Inc. 2008
- *
- * Author: Ron Madrid <info@sheldoninst.com>
- *
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <mpc83xx.h>
-#include <spd_sdram.h>
-#include <asm/bitops.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static long fixed_sdram(void);
-
-#if defined(CONFIG_NAND_SPL)
-void si_wait_i2c(void)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
-
- while (!(__raw_readb(&im->i2c[0].sr) & 0x02))
- ;
-
- __raw_writeb(0x00, &im->i2c[0].sr);
-
- sync();
-
- return;
-}
-
-void si_read_i2c(u32 lbyte, int count, u8 *buffer)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 i;
- u8 chip = 0x50 << 1; /* boot sequencer I2C */
- u32 ubyte = (lbyte & 0xff00) >> 8;
-
- lbyte &= 0xff;
-
- /*
- * Set up controller
- */
- __raw_writeb(0x3f, &im->i2c[0].fdr);
- __raw_writeb(0x00, &im->i2c[0].adr);
- __raw_writeb(0x00, &im->i2c[0].sr);
- __raw_writeb(0x00, &im->i2c[0].dr);
-
- while (__raw_readb(&im->i2c[0].sr) & 0x20)
- ;
-
- /*
- * Writing address to device
- */
- __raw_writeb(0xb0, &im->i2c[0].cr);
- sync();
- __raw_writeb(chip, &im->i2c[0].dr);
- si_wait_i2c();
-
- __raw_writeb(0xb0, &im->i2c[0].cr);
- sync();
- __raw_writeb(ubyte, &im->i2c[0].dr);
- si_wait_i2c();
-
- __raw_writeb(lbyte, &im->i2c[0].dr);
- si_wait_i2c();
-
- __raw_writeb(0xb4, &im->i2c[0].cr);
- sync();
- __raw_writeb(chip + 1, &im->i2c[0].dr);
- si_wait_i2c();
-
- __raw_writeb(0xa0, &im->i2c[0].cr);
- sync();
-
- /*
- * Dummy read
- */
- __raw_readb(&im->i2c[0].dr);
-
- si_wait_i2c();
-
- /*
- * Read actual data
- */
- for (i = 0; i < count; i++)
- {
- if (i == (count - 2)) /* Reached next to last byte, No ACK */
- __raw_writeb(0xa8, &im->i2c[0].cr);
- if (i == (count - 1)) /* Reached last byte, STOP */
- __raw_writeb(0x88, &im->i2c[0].cr);
-
- /* Read byte of data */
- buffer[i] = __raw_readb(&im->i2c[0].dr);
-
- if (i == (count - 1))
- break;
- si_wait_i2c();
- }
-
- return;
-}
-#endif /* CONFIG_NAND_SPL */
-
-phys_size_t initdram(int board_type)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- volatile fsl_lbc_t *lbc = &im->im_lbc;
- u32 msize;
-
- if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im)
- return -1;
-
- /* DDR SDRAM - Main SODIMM */
- __raw_writel(CONFIG_SYS_DDR_BASE & LAWBAR_BAR, &im->sysconf.ddrlaw[0].bar);
-
- msize = fixed_sdram();
-
- /* Local Bus setup lbcr and mrtpr */
- __raw_writel(CONFIG_SYS_LBC_LBCR, &lbc->lbcr);
- __raw_writel(CONFIG_SYS_LBC_MRTPR, &lbc->mrtpr);
- sync();
-
- /* return total bus SDRAM size(bytes) -- DDR */
- return (msize * 1024 * 1024);
-}
-
-/*************************************************************************
- * fixed sdram init -- reads values from boot sequencer I2C
- ************************************************************************/
-static long fixed_sdram(void)
-{
- volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
- u32 msizelog2, msize = 1;
-#if defined(CONFIG_NAND_SPL)
- u32 i;
- const u8 bytecount = 135;
- u8 buffer[bytecount];
- u32 addr, data;
-
- si_read_i2c(0, bytecount, buffer);
-
- for (i = 18; i < bytecount; i += 7){
- addr = (u32)buffer[i];
- addr <<= 8;
- addr |= (u32)buffer[i + 1];
- addr <<= 2;
- data = (u32)buffer[i + 2];
- data <<= 8;
- data |= (u32)buffer[i + 3];
- data <<= 8;
- data |= (u32)buffer[i + 4];
- data <<= 8;
- data |= (u32)buffer[i + 5];
-
- __raw_writel(data, (u32 *)(CONFIG_SYS_IMMR + addr));
- }
-
- sync();
-
- /* enable DDR controller */
- __raw_writel((__raw_readl(&im->ddr.sdram_cfg) | SDRAM_CFG_MEM_EN), &im->ddr.sdram_cfg);
-#endif /* (CONFIG_NAND_SPL) */
-
- msizelog2 = ((__raw_readl(&im->sysconf.ddrlaw[0].ar) & LAWAR_SIZE) + 1);
- msize <<= (msizelog2 - 20);
-
- return msize;
-}
+++ /dev/null
-/*
- * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
- * Copyright (C) Sheldon Instruments, Inc. 2008
- *
- * Author: Ron Madrid <info@sheldoninst.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <libfdt.h>
-#include <pci.h>
-#include <mpc83xx.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <asm/io.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#ifndef CONFIG_NAND_SPL
-int checkboard(void)
-{
- puts("Board: Sheldon Instruments SIMPC8313\n");
- return 0;
-}
-
-static struct pci_region pci_regions[] = {
- {
- bus_start: CONFIG_SYS_PCI1_MEM_BASE,
- phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
- size: CONFIG_SYS_PCI1_MEM_SIZE,
- flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
- },
- {
- bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
- phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
- size: CONFIG_SYS_PCI1_MMIO_SIZE,
- flags: PCI_REGION_MEM
- },
- {
- bus_start: CONFIG_SYS_PCI1_IO_BASE,
- phys_start: CONFIG_SYS_PCI1_IO_PHYS,
- size: CONFIG_SYS_PCI1_IO_SIZE,
- flags: PCI_REGION_IO
- }
-};
-
-void pci_init_board(void)
-{
- volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
- volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
- volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
- struct pci_region *reg[] = { pci_regions };
-
- /* Enable all 3 PCI_CLK_OUTPUTs. */
- clk->occr |= 0xe0000000;
-
- /*
- * Configure PCI Local Access Windows
- */
- pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
- pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
-
- pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
- pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
-
- mpc83xx_pci_init(1, reg);
-}
-
-/*
- * Miscellaneous late-boot configurations
- */
-int misc_init_r(void)
-{
- int rc = 0;
- immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
- fsl_lbc_t *lbus = &immap->im_lbc;
- u32 *mxmr = &lbus->mamr; /* Pointer to mamr */
-
- /* UPM Table Configuration Code */
- static uint UPMATable[] = {
- /* Read Single-Beat (RSS) */
- 0x0fff0c00, 0x0fffdc00, 0x0fff0c05, 0xfffffc00,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
- /* Read Burst (RBS) */
- 0x0fff0c00, 0x0ffcdc00, 0x0ffc0c00, 0x0ffc0f0c,
- 0x0ffccf0c, 0x0ffc0f0c, 0x0ffcce0c, 0x3ffc0c05,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
- /* Write Single-Beat (WSS) */
- 0x0ffc0c00, 0x0ffcdc00, 0x0ffc0c05, 0xfffffc00,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
- /* Write Burst (WBS) */
- 0x0ffc0c00, 0x0fffcc0c, 0x0fff0c00, 0x0fffcc00,
- 0x0fff1c00, 0x0fffcf0c, 0x0fff0f0c, 0x0fffcf0c,
- 0x0fff0c0c, 0x0fffcc0c, 0x0fff0c05, 0xfffffc00,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
- /* Refresh Timer (RTS) */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
- /* Exception Condition (EXS) */
- 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
- };
-
- upmconfig(UPMA, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
-
- /* Set LUPWAIT to be active low and enabled */
- out_be32(mxmr, MxMR_UWPL | MxMR_GPL_x4DIS);
-
- return rc;
-}
-
-#if defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
-#ifdef CONFIG_PCI
- ft_pci_setup(blob, bd);
-#endif
-}
-#endif
-#else /* CONFIG_NAND_SPL */
-void board_init_f(ulong bootflag)
-{
- NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
- CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
- puts("NAND boot... ");
- init_timebase();
- initdram(0);
- relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
- CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- nand_boot();
-}
-
-void putc(char c)
-{
- if (gd->flags & GD_FLG_SILENT)
- return;
-
- if (c == '\n')
- NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
-
- NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
-}
-#endif
*(.__rel_dyn_end)
}
+ .hash : { *(.hash*) }
+
.end :
{
*(.__end)
.dynbss : { *(.dynbss) }
.dynstr : { *(.dynstr*) }
.dynamic : { *(.dynamic*) }
- .hash : { *(.hash*) }
.gnu.hash : { *(.gnu.hash) }
.plt : { *(.plt*) }
.interp : { *(.interp*) }
/* ESDCTL0: Enable controller */
DATA 4 0x83fd9000 0x83220000
-/* Init DRAM on CS0 /
+/* Init DRAM on CS0 */
/* ESDSCR: Precharge command */
DATA 4 0x83fd9014 0x04008008
/* ESDSCR: Refresh command */
+++ /dev/null
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y := zpc1900.o
+++ /dev/null
-/*
- * (C) Copyright 2001-2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2003-2005 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ioports.h>
-#include <mpc8260.h>
-#include <miiphy.h>
-
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
- /* Port A */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
- /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
- /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
- /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
- /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
- /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
- /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
- /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
- /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
- /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
- /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
- /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
- /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
- /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
- /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
- /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
- /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
- /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
- /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
- /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
- /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
- /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
- /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* SMC2 TXD */
- /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* SMC2 RXD */
- /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
- /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
- /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
- /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
- },
-
- /* Port B */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
- /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
- /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
- /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
- /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
- /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
- /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- },
-
- /* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN CLSN */
- /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
- /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
- /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
- /* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
- /* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
- /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
- /* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RENA */
- /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
- /* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT972 MDC */
- /* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT972 MDIO */
- /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
- /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
- /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
- },
-
- /* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
- /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
- /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
- /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
- /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
- /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
- /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
- /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
- }
-};
-
-#ifdef CONFIG_SYS_NVRAM_ACCESS_ROUTINE
-void *nvram_read(void *dest, long src, size_t count)
-{
- return memcpy(dest, (const void *)src, count);
-}
-
-void nvram_write(long dest, const void *src, size_t count)
-{
- vu_char *p1 = (vu_char *)(CONFIG_SYS_EEPROM + 0x1555);
- vu_char *p2 = (vu_char *)(CONFIG_SYS_EEPROM + 0x0AAA);
- vu_char *d = (vu_char *)dest;
- const uchar *s = (const uchar *)src;
-
- /* Unprotect the EEPROM */
- *p1 = 0xAA;
- *p2 = 0x55;
- *p1 = 0x80;
- *p1 = 0xAA;
- *p2 = 0x55;
- *p1 = 0x20;
- udelay(10000);
-
- /* Write the data to the EEPROM */
- while (count--) {
- *d++ = *s++;
- while (*(d - 1) != *(s - 1))
- /* wait */;
- }
-
- /* Protect the EEPROM */
- *p1 = 0xAA;
- *p2 = 0x55;
- *p1 = 0xA0;
- udelay(10000);
-}
-#endif /* CONFIG_SYS_NVRAM_ACCESS_ROUTINE */
-
-phys_size_t initdram(int board_type)
-{
- vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
- volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
- volatile memctl8260_t *memctl = &immap->im_memctl;
- vu_char *ramaddr;
- uchar c = 0xFF;
- long int msize = CONFIG_SYS_SDRAM_SIZE;
- int i;
-
- if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */
- immap->im_clkrst.car_sccr |= SCCR_PCI_MODE;
- immap->im_siu_conf.sc_siumcr =
- (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
- | SIUMCR_LBPC01;
- }
-
-#ifndef CONFIG_SYS_RAMBOOT
- immap->im_siu_conf.sc_ppc_acr = 0x03;
- immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
- immap->im_siu_conf.sc_tescr1 = 0x00004000;
-
- memctl->memc_mptpr = CONFIG_SYS_MPTPR;
-
-#ifdef CONFIG_SYS_LSDRAM_BASE
- /*
- Initialise local bus SDRAM only if the pins
- are configured as local bus pins and not as PCI.
- */
- if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
- memctl->memc_lsrt = CONFIG_SYS_LSRT;
- memctl->memc_or4 = CONFIG_SYS_LSDRAM_OR;
- memctl->memc_br4 = CONFIG_SYS_LSDRAM_BR;
- ramaddr = (vu_char *)CONFIG_SYS_LSDRAM_BASE;
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_PREA;
- *ramaddr = c;
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_CBRR;
- for (i = 0; i < 8; i++)
- *ramaddr = c;
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_MRW;
- *ramaddr = c;
- memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_RFEN;
- }
-#endif /* CONFIG_SYS_LSDRAM_BASE */
-
- /* Initialise 60x bus SDRAM */
- memctl->memc_psrt = CONFIG_SYS_PSRT;
- memctl->memc_or2 = CONFIG_SYS_PSDRAM_OR;
- memctl->memc_br2 = CONFIG_SYS_PSDRAM_BR;
- /*
- * The mode data for Mode Register Write command must appear on
- * the address lines during a mode-set cycle. It is driven by
- * the memory controller, in single PowerQUICC II mode,
- * according to PSDMR[CL] and PSDMR[BL] fields. In
- * 60x-compatible mode, software must drive the correct value on
- * the address lines. BL=0 because for 64-bit port size burst
- * length must be 4.
- */
- ramaddr = (vu_char *)(CONFIG_SYS_SDRAM_BASE |
- ((CONFIG_SYS_PSDMR & PSDMR_CL_MSK) << 7) | 0x10);
- memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_PREA; /* Precharge all banks */
- *ramaddr = c;
- memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_CBRR; /* CBR refresh */
- for (i = 0; i < 8; i++)
- *ramaddr = c;
- memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_MRW; /* Mode Register write */
- *ramaddr = c;
- memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_RFEN; /* Refresh enable */
- *ramaddr = c;
-#endif /* CONFIG_SYS_RAMBOOT */
-
- /* Return total 60x bus SDRAM size */
- return msize * 1024 * 1024;
-}
-
-int checkboard(void)
-{
- vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
-
- printf("Board: Zephyr ZPC.1900 Rev. %c\n", bcsr[2] + 0x40);
- return 0;
-}
Active arc arc700 - synopsys - axs101 - Alexey Brodkin <abrodkin@synopsys.com>
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Active arm arm926ejs at91 emk top9000 top9000eval_xe top9000:EVAL9000 Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
Active arm arm926ejs mxs freescale mx28evk mx28evk mx28evk:ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com>
Active arm arm926ejs mxs freescale mx28evk mx28evk_auart_console mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com>
Active arm arm926ejs mxs freescale mx28evk mx28evk_nand mx28evk:ENV_IS_IN_NAND Fabio Estevam <fabio.estevam@freescale.com>
+Active arm arm926ejs mxs freescale mx28evk mx28evk_spi mx28evk:ENV_IS_IN_SPI_FLASH Fabio Estevam <fabio.estevam@freescale.com>
Active arm arm926ejs mxs olimex mx23_olinuxino mx23_olinuxino - Marek Vasut <marek.vasut@gmail.com>
Active arm arm926ejs mxs ppcag bg0900 bg0900 - Marek Vasut <marex@denx.de>
Active arm arm926ejs mxs sandisk sansa_fuze_plus sansa_fuze_plus - Marek Vasut <marek.vasut@gmail.com>
Active arm armv7 am33xx siemens rut rut - Roger Meier <r.meier@siemens.com>
Active arm armv7 am33xx silica pengwyn pengwyn - Lothar Felten <lothar.felten@gmail.com>
Active arm armv7 am33xx ti am335x am335x_boneblack am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT Tom Rini <trini@ti.com>
+Active arm armv7 am33xx ti am335x am335x_boneblack_vboot am335x_evm:SERIAL1,CONS_INDEX=1,EMMC_BOOT,ENABLE_VBOOT Tom Rini <trini@ti.com>
Active arm armv7 am33xx ti am335x am335x_evm am335x_evm:SERIAL1,CONS_INDEX=1,NAND Tom Rini <trini@ti.com>
Active arm armv7 am33xx ti am335x am335x_evm_nor am335x_evm:SERIAL1,CONS_INDEX=1,NAND,NOR Tom Rini <trini@ti.com>
Active arm armv7 am33xx ti am335x am335x_evm_norboot am335x_evm:SERIAL1,CONS_INDEX=1,NOR,NOR_BOOT Tom Rini <trini@ti.com>
Active arm armv7 mx6 boundary nitrogen6x nitrogen6q2g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Eric Nelson <eric.nelson@boundarydevices.com>
Active arm armv7 mx6 boundary nitrogen6x nitrogen6s nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Eric Nelson <eric.nelson@boundarydevices.com>
Active arm armv7 mx6 boundary nitrogen6x nitrogen6s1g nitrogen6x:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024 Eric Nelson <eric.nelson@boundarydevices.com>
-Active arm armv7 mx6 congatec cgtqmx6eval cgtqmx6qeval cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Leo Sartre <lsartre@adeneo-embedded.com>
Active arm armv7 mx6 embest mx6boards marsboard embestmx6boards:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024,ENV_IS_IN_SPI_FLASH Eric Bénard <eric@eukrea.com>
Active arm armv7 mx6 embest mx6boards riotboard embestmx6boards:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s1g.cfg,MX6S,DDR_MB=1024,ENV_IS_IN_MMC Eric Bénard <eric@eukrea.com>
Active arm armv7 mx6 freescale mx6qarm2 mx6qarm2 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg Jason Liu <r64343@freescale.com>
Active arm armv7 mx6 freescale mx6qsabreauto mx6qsabreauto mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com>
+Active arm armv7 mx6 freescale mx6qsabreauto mx6dlsabreauto mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/mx6dl.cfg,MX6DL Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 freescale mx6sabresd mx6dlsabresd mx6sabresd:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 freescale mx6sabresd mx6qsabresd mx6sabresd:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Fabio Estevam <fabio.estevam@freescale.com>
Active arm armv7 mx6 freescale mx6slevk mx6slevk mx6slevk:IMX_CONFIG=board/freescale/mx6slevk/imximage.cfg,MX6SL Fabio Estevam <fabio.estevam@freescale.com>
-Active arm armv7 mx6 gateworks gw_ventana gwventanadl gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=512 Tim Harvey <tharvey@gateworks.com>
-Active arm armv7 mx6 gateworks gw_ventana gwventanadl1g gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6DL,DDR_MB=1024 Tim Harvey <tharvey@gateworks.com>
-Active arm armv7 mx6 gateworks gw_ventana gwventanaq gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=512 Tim Harvey <tharvey@gateworks.com>
-Active arm armv7 mx6 gateworks gw_ventana gwventanaq1g gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024 Tim Harvey <tharvey@gateworks.com>
-Active arm armv7 mx6 gateworks gw_ventana gwventanaq1gspi gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6Q,DDR_MB=1024,SPI_FLASH Tim Harvey <tharvey@gateworks.com>
+Active arm armv7 mx6 gateworks gw_ventana gwventana gw_ventana:IMX_CONFIG=board/gateworks/gw_ventana/gw_ventana.cfg,MX6QDL,SPL Tim Harvey <tharvey@gateworks.com>
Active arm armv7 mx6 solidrun hummingboard hummingboard_solo hummingboard:IMX_CONFIG=board/solidrun/hummingboard/solo.cfg,MX6S,DDR_MB=512 Jon Nettleton <jon.nettleton@gmail.com>
Active arm armv7 omap3 - overo omap3_overo - Steve Sakoman <sakoman@gmail.com>
Active arm armv7 omap3 - pandora omap3_pandora - Grazvydas Ignotas <notasas@gmail.com>
Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp>
Active arm armv7 rmobile renesas koelsch koelsch - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
-Active arm armv7 rmobile renesas koelsch koelsch_nor koelsch:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 rmobile renesas lager lager - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
-Active arm armv7 rmobile renesas lager lager_nor lager:NORFLASH Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Active arm armv7 s5pc1xx samsung goni s5p_goni - Przemyslaw Marczak <p.marczak@samsung.com>
Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang <mk7.kang@samsung.com>
Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - -
Active arm pxa - - - h2200 - Lukasz Dalek <luk0104@gmail.com>
Active arm pxa - - - palmld - Marek Vasut <marek.vasut@gmail.com>
Active arm pxa - - - palmtc - Marek Vasut <marek.vasut@gmail.com>
-Active arm pxa - - - palmtreo680 - Mike Dunn <mikedunn@newsguy.com>
Active arm pxa - - - pxa255_idp - Cliff Brake <cliff.brake@gmail.com>
Active arm pxa - - - trizepsiv - Stefano Babic <sbabic@denx.de>
Active arm pxa - - - xaeniax - -
Active arm pxa - icpdas lp8x4x lp8x4x - Sergey Yanovich <ynvich@gmail.com>
Active arm pxa - toradex - colibri_pxa270 - Marek Vasut <marek.vasut@gmail.com>
Active arm sa1100 - - - jornada - Kristoffer Ericson <kristoffer.ericson@gmail.com>
-Active avr32 at32ap at32ap700x atmel - atngw100 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Active avr32 at32ap at32ap700x atmel - atngw100mkii - Andreas Bießmann <andreas.devel@googlemail.com>
-Active avr32 at32ap at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
-Active avr32 at32ap at32ap700x atmel atstk1000 atstk1003 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
-Active avr32 at32ap at32ap700x atmel atstk1000 atstk1004 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
-Active avr32 at32ap at32ap700x atmel atstk1000 atstk1006 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
-Active avr32 at32ap at32ap700x earthlcd - favr-32-ezkit - Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
Active avr32 at32ap at32ap700x in-circuit - grasshopper - Andreas Bießmann <andreas.devel@googlemail.com>
Active avr32 at32ap at32ap700x mimc - mimc200 - Mark Jackson <mpfj@mimc.co.uk>
-Active avr32 at32ap at32ap700x miromico - hammerhead -
Julien May <julien.may@miromico.ch>:Alex Raimondi <alex.raimondi@miromico.ch>
+Active avr32 at32ap at32ap700x miromico - hammerhead - Alex Raimondi <alex.raimondi@miromico.ch>
Active blackfin blackfin - - - bct-brettl2 - Peter Meerwald <devel@bct-electronic.com>
Active blackfin blackfin - - - bf506f-ezkit - Sonic Zhang <sonic.adi@gmail.com>
Active blackfin blackfin - - - bf518f-ezbrd - Sonic Zhang <sonic.adi@gmail.com>
Active blackfin blackfin - - - bf537-stamp - Sonic Zhang <sonic.adi@gmail.com>
Active blackfin blackfin - - - bf538f-ezkit - Sonic Zhang <sonic.adi@gmail.com>
Active blackfin blackfin - - - bf548-ezkit - Sonic Zhang <sonic.adi@gmail.com>
-Active blackfin blackfin - - - bf561-acvilon - Anton Shurpin <shurpin.aa@niistt.ru>:Valentin Yakovenkov <yakovenkov@niistt.ru>
+Active blackfin blackfin - - - bf561-acvilon - Valentin Yakovenkov <yakovenkov@niistt.ru>
Active blackfin blackfin - - - bf561-ezkit - Sonic Zhang <sonic.adi@gmail.com>
Active blackfin blackfin - - - bf609-ezkit - Sonic Zhang <sonic.adi@gmail.com>
Active blackfin blackfin - - - blackstamp - Wojtek Skulski <skulski@pas.rochester.edu>:Wojtek Skulski <info@skutek.com>:Benjamin Matthews <mben12@gmail.com>
Active blackfin blackfin - - - br4 - Dimitar Penev <dpn@switchfin.org>
Active blackfin blackfin - - - dnp5370 - M.Hasewinkel (MHA) <info@ssv-embedded.de>
Active blackfin blackfin - - - ibf-dsp561 - I-SYST Micromodule <support@i-syst.com>
-Active blackfin blackfin - - - ip04 - Brent Kandetzki <brentk@teleco.com>
Active blackfin blackfin - - - pr1 - Dimitar Penev <dpn@switchfin.org>
Active blackfin blackfin - - bf527-ezkit bf527-ezkit-v2 bf527-ezkit:BF527_EZKIT_REV_2_1 Sonic Zhang <sonic.adi@gmail.com>
Active m68k mcf5227x - freescale m52277evb M52277EVB M52277EVB:SYS_SPANSION_BOOT,SYS_TEXT_BASE=0x00000000 TsiChung Liew <Tsi-Chung.Liew@freescale.com>
Active m68k mcf52x2 - freescale m5208evbe M5208EVBE - -
Active m68k mcf52x2 - freescale m5249evb M5249EVB - -
Active m68k mcf52x2 - freescale m5253demo M5253DEMO - TsiChung Liew <Tsi-Chung.Liew@freescale.com>
-Active m68k mcf52x2 - freescale m5253evbe M5253EVBE - Hayden Fraser <Hayden.Fraser@freescale.com>
Active m68k mcf52x2 - freescale m5272c3 M5272C3 - -
Active m68k mcf52x2 - freescale m5275evb M5275EVB - -
Active m68k mcf52x2 - freescale m5282evb M5282EVB - -
Active powerpc mpc5xxx - - a3m071 a4m2k a3m071:A4M2K Stefan Roese <sr@denx.de>
Active powerpc mpc5xxx - - a4m072 a4m072 - Sergei Poselenov <sposelenov@emcraft.com>
Active powerpc mpc5xxx - - bc3450 BC3450 - -
-Active powerpc mpc5xxx - - galaxy5200 galaxy5200 galaxy5200:galaxy5200 Eric Millbrandt <emillbrandt@dekaresearch.com>
-Active powerpc mpc5xxx - - galaxy5200 galaxy5200_LOWBOOT galaxy5200:galaxy5200_LOWBOOT Eric Millbrandt <emillbrandt@dekaresearch.com>
Active powerpc mpc5xxx - - icecube icecube_5200 IceCube Wolfgang Denk <wd@denx.de>
Active powerpc mpc5xxx - - icecube icecube_5200_DDR IceCube:MPC5200_DDR -
Active powerpc mpc5xxx - - icecube icecube_5200_DDR_LOWBOOT IceCube:SYS_TEXT_BASE=0xFF800000,MPC5200_DDR -
Active powerpc mpc824x - - mvblue MVBLUE - -
Active powerpc mpc824x - - sandpoint Sandpoint8240 - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8260 - - - atc - Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8260 - - - ep8260 - Frank Panno <fpanno@delphintech.com>
Active powerpc mpc8260 - - - ep82xxm - -
Active powerpc mpc8260 - - - gw8260 - Oliver Brown <obrown@adventnetworks.com>
Active powerpc mpc8260 - - - hymod - Murray Jensen <Murray.Jensen@csiro.au>
-Active powerpc mpc8260 - - - sacsng - Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
Active powerpc mpc8260 - - cogent cogent_mpc8260 - Murray Jensen <Murray.Jensen@csiro.au>
Active powerpc mpc8260 - - cpu86 CPU86 - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8260 - - cpu86 CPU86_ROMBOOT CPU86:BOOT_ROM Wolfgang Denk <wd@denx.de>
Active powerpc mpc8260 - - cpu87 CPU87 - -
Active powerpc mpc8260 - - cpu87 CPU87_ROMBOOT CPU87:BOOT_ROM -
-Active powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen <yuli@arabellasw.com>
Active powerpc mpc8260 - - iphase4539 IPHASE4539 - Wolfgang Grandegger <wg@denx.de>
Active powerpc mpc8260 - - muas3001 muas3001 - Heiko Schocher <hs@denx.de>
Active powerpc mpc8260 - - muas3001 muas3001_dev muas3001:MUAS_DEV_BOARD Heiko Schocher <hs@denx.de>
Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_33 MPC8313ERDB:SYS_33MHZ,NAND -
Active powerpc mpc83xx - freescale mpc8313erdb MPC8313ERDB_NAND_66 MPC8313ERDB:SYS_66MHZ,NAND -
Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB - Dave Liu <daveliu@freescale.com>
-Active powerpc mpc83xx - freescale mpc8315erdb MPC8315ERDB_NAND MPC8315ERDB:NAND_U_BOOT Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc8323erdb MPC8323ERDB - Michael Barkowski <michael.barkowski@freescale.com>
Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS - Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc832xemds MPC832XEMDS_ATM MPC832XEMDS:PQ_MDS_PIB=1,PQ_MDS_PIB_ATM=1 Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc8360emds MPC8360EMDS_66_SLAVE MPC8360EMDS:CLKIN_66MHZ,PCI,PCISLAVE Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS - Dave Liu <daveliu@freescale.com>
Active powerpc mpc83xx - freescale mpc837xemds MPC837XEMDS_HOST MPC837XEMDS:PCI Dave Liu <daveliu@freescale.com>
-Active powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio <ljd015@freescale.com>
Active powerpc mpc83xx - ids ids8313 ids8313 ids8313:SYS_TEXT_BASE=0xFFF00000 Heiko Schocher <hs@denx.de>
Active powerpc mpc83xx - keymile km83xx kmcoge5ne km8360:KMCOGE5NE Holger Brunck <holger.brunck@keymile.com>
Active powerpc mpc83xx - keymile km83xx kmeter1 km8360:KMETER1 Holger Brunck <holger.brunck@keymile.com>
Active powerpc mpc83xx - keymile km83xx suvd3 suvd3:SUVD3 Holger Brunck <holger.brunck@keymile.com>
Active powerpc mpc83xx - keymile km83xx tuge1 tuxx1:TUGE1 Holger Brunck <holger.brunck@keymile.com>
Active powerpc mpc83xx - keymile km83xx tuxx1 tuxx1:TUXX1 Holger Brunck <holger.brunck@keymile.com>
-Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_LP SIMPC8313:NAND_LP Ron Madrid <info@sheldoninst.com>
-Active powerpc mpc83xx - sheldon simpc8313 SIMPC8313_SP SIMPC8313:NAND_SP Ron Madrid <info@sheldoninst.com>
Active powerpc mpc83xx - tqc tqm834x TQM834x - -
Active powerpc mpc85xx - - sbc8548 sbc8548 - Paul Gortmaker <paul.gortmaker@windriver.com>
Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_33 sbc8548:PCI,33 Paul Gortmaker <paul.gortmaker@windriver.com>
Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_66 sbc8548:PCI,66 Paul Gortmaker <paul.gortmaker@windriver.com>
Active powerpc mpc85xx - - sbc8548 sbc8548_PCI_66_PCIE sbc8548:PCI,66,PCIE Paul Gortmaker <paul.gortmaker@windriver.com>
Active powerpc mpc85xx - - socrates socrates - -
-Active powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett <Kyle.D.Moffett@boeing.com>
Active powerpc mpc85xx - freescale b4860qds B4420QDS B4860QDS:PPC_B4420 -
Active powerpc mpc85xx - freescale b4860qds B4420QDS_NAND B4860QDS:PPC_B4420,RAMBOOT_PBL,SPL_FSL_PBL,NAND -
Active powerpc mpc85xx - freescale b4860qds B4420QDS_SPIFLASH B4860QDS:PPC_B4420,RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale corenet_ds P5040DS_SPIFLASH P5040DS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF40000 -
Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS - -
Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_36BIT MPC8536DS:36BIT -
-Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_NAND MPC8536DS:NAND -
Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SDCARD MPC8536DS:SDCARD -
Active powerpc mpc85xx - freescale mpc8536ds MPC8536DS_SPIFLASH MPC8536DS:SPIFLASH -
-Active powerpc mpc85xx - freescale mpc8540ads MPC8540ADS - Kumar Gala <kumar.gala@freescale.com>
-Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS - Kumar Gala <kumar.gala@freescale.com>
-Active powerpc mpc85xx - freescale mpc8541cds MPC8541CDS_legacy MPC8541CDS:LEGACY Kumar Gala <kumar.gala@freescale.com>
Active powerpc mpc85xx - freescale mpc8544ds MPC8544DS - -
Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS - -
Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_36BIT MPC8548CDS:36BIT -
Active powerpc mpc85xx - freescale mpc8548cds MPC8548CDS_legacy MPC8548CDS:LEGACY -
-Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS - Kumar Gala <kumar.gala@freescale.com>
-Active powerpc mpc85xx - freescale mpc8555cds MPC8555CDS_legacy MPC8555CDS:LEGACY Kumar Gala <kumar.gala@freescale.com>
-Active powerpc mpc85xx - freescale mpc8560ads MPC8560ADS - Kumar Gala <kumar.gala@freescale.com>
Active powerpc mpc85xx - freescale mpc8568mds MPC8568MDS - -
Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS - -
Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_ATM MPC8569MDS:ATM -
-Active powerpc mpc85xx - freescale mpc8569mds MPC8569MDS_NAND MPC8569MDS:NAND -
Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS - York Sun <yorksun@freescale.com>
Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_36BIT MPC8572DS:36BIT York Sun <yorksun@freescale.com>
-Active powerpc mpc85xx - freescale mpc8572ds MPC8572DS_NAND MPC8572DS:NAND -
Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND P1010RDB:P1010RDB_PA,36BIT,NAND -
Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NAND_SECBOOT P1010RDB:P1010RDB_PA,36BIT,NAND_SECBOOT,SECURE_BOOT -
Active powerpc mpc85xx - freescale p1010rdb P1010RDB-PA_36BIT_NOR P1010RDB:P1010RDB_PA,36BIT -
Active powerpc mpc85xx - freescale p1022ds P1022DS_SPIFLASH P1022DS:SPIFLASH Timur Tabi <timur@freescale.com>
Active powerpc mpc85xx - freescale p1023rdb P1023RDB - -
Active powerpc mpc85xx - freescale p1023rds P1023RDS - Roy Zang <tie-fei.zang@freescale.com>
-Active powerpc mpc85xx - freescale p1023rds P1023RDS_NAND P1023RDS:NAND Roy Zang <tie-fei.zang@freescale.com>
Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB P1_P2_RDB:P1011RDB -
Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT P1_P2_RDB:P1011RDB,36BIT -
Active powerpc mpc85xx - freescale p1_p2_rdb P1011RDB_36BIT_SDCARD P1_P2_RDB:P1011RDB,36BIT,SDCARD -
Active powerpc mpc85xx - gdsys p1022 controlcenterd_TRAILBLAZER_DEVELOP controlcenterd:TRAILBLAZER,SPIFLASH,DEVELOP Dirk Eibach <eibach@gdsys.de>
Active powerpc mpc85xx - keymile kmp204x kmcoge4 kmp204x:KMCOGE4 Valentin Longchamp <valentin.longchamp@keymile.com>
Active powerpc mpc85xx - keymile kmp204x kmlion1 kmp204x:KMLION1 Valentin Longchamp <valentin.longchamp@keymile.com>
-Active powerpc mpc85xx - stx stxgp3 stxgp3 - Dan Malek <dan@embeddedalley.com>
-Active powerpc mpc85xx - stx stxssa stxssa - Dan Malek <dan@embeddedalley.com>
-Active powerpc mpc85xx - stx stxssa stxssa_4M stxssa:STXSSA_4M Dan Malek <dan@embeddedalley.com>
Active powerpc mpc85xx - xes - xpedite520x - -
Active powerpc mpc85xx - xes - xpedite537x - -
Active powerpc mpc85xx - xes - xpedite550x - -
Active powerpc mpc86xx - - - sbc8641d - Paul Gortmaker <paul.gortmaker@windriver.com>
Active powerpc mpc86xx - freescale mpc8610hpcd MPC8610HPCD - -
-Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN - Kumar Gala <kumar.gala@freescale.com>
-Active powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN_36BIT MPC8641HPCN:PHYS_64BIT Kumar Gala <kumar.gala@freescale.com>
Active powerpc mpc86xx - xes - xpedite517x - -
Active powerpc mpc8xx - - - hermes - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - - lwmon - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - - quantum - -
Active powerpc mpc8xx - - - RRvision - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - - spc1920 - -
-Active powerpc mpc8xx - - - svm_sc8xx - John Zhan <zhanz@sinovee.com>
Active powerpc mpc8xx - - - v37 - -
Active powerpc mpc8xx - - cogent cogent_mpc8xx - Murray Jensen <Murray.Jensen@csiro.au>
Active powerpc mpc8xx - - esteem192e ESTEEM192E - Conn Clark <clark@esteem.com>
Active powerpc mpc8xx - - fads MPC86xADS - -
Active powerpc mpc8xx - - fads MPC885ADS - -
-Active powerpc mpc8xx - - flagadm FLAGADM - Kári DavÃðsson <kd@flaga.is>
-Active powerpc mpc8xx - - gen860t GEN860T - Keith Outwater <Keith_Outwater@mvis.com>
-Active powerpc mpc8xx - - gen860t GEN860T_SC GEN860T:SC Keith Outwater <Keith_Outwater@mvis.com>
Active powerpc mpc8xx - - icu862 ICU862 - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - icu862 ICU862_100MHz ICU862:100MHz Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - ip860 IP860 - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_64_LCD RPXlite_DW:RPXlite_64MHz,LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM -
Active powerpc mpc8xx - - RPXlite_dw RPXlite_DW_NVRAM_LCD RPXlite_DW:LCD,NEC_NL6448BC20,ENV_IS_IN_NVRAM -
Active powerpc mpc8xx - - RRvision RRvision_LCD RRvision:LCD,SHARP_LQ104V7DS01 Wolfgang Denk <wd@denx.de>
-Active powerpc mpc8xx - - sixnet SXNI855T - Dave Ellis <DGE@sixnetio.com>
Active powerpc mpc8xx - - spd8xx SPD823TS - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - eltec mhpc MHPC - Frank Gottschling <fgottschling@eltec.de>
Active powerpc mpc8xx - emk top860 TOP860 - Reinhard Meyer <reinhard.meyer@emk-elektronik.de>
Active powerpc mpc8xx - snmc qs850 QS823 - -
Active powerpc mpc8xx - snmc qs850 QS850 - -
Active powerpc mpc8xx - snmc qs860t QS860T - -
-Active powerpc mpc8xx - stx stxxtc stxxtc - Dan Malek <dan@embeddedalley.com>
Active powerpc mpc8xx - tqc tqm8xx FPS850L - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - tqc tqm8xx FPS860L - Wolfgang Denk <wd@denx.de>
Active powerpc mpc8xx - tqc tqm8xx NSCU - -
Active powerpc ppc4xx - - - korat - Larry Johnson <lrj@acm.org>
Active powerpc ppc4xx - - - lwmon5 - Stefan Roese <sr@denx.de>
Active powerpc ppc4xx - - - pcs440ep - Stefan Roese <sr@denx.de>
-Active powerpc ppc4xx - - - quad100hd - Gary Jennejohn <garyj@denx.de>
Active powerpc ppc4xx - - - sbc405 - -
Active powerpc ppc4xx - - - sc3 - Heiko Schocher <hs@denx.de>
Active powerpc ppc4xx - - - t3corp - Stefan Roese <sr@denx.de>
Active sparc leon3 - gaisler - gr_xc3s_1500 - -
Active sparc leon3 - gaisler - grsim - -
Active x86 x86 coreboot chromebook-x86 coreboot coreboot-x86 coreboot:SYS_TEXT_BASE=0x01110000 Simon Glass <sjg@chromium.org>
+# The following were moved to "Orphan" in June, 2014
+Orphan arm arm1176 tnetv107x ti tnetv107xevm tnetv107x_evm - Chan-Taek Park <c-park@ti.com>
+Orphan arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_eeprom sbc35_a9g20:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Orphan arm arm926ejs at91 calao sbc35_a9g20 sbc35_a9g20_nandflash sbc35_a9g20:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Orphan arm arm926ejs at91 calao tny_a9260 tny_a9260_eeprom tny_a9260:AT91SAM9260,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Orphan arm arm926ejs at91 calao tny_a9260 tny_a9260_nandflash tny_a9260:AT91SAM9260,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Orphan arm arm926ejs at91 calao tny_a9260 tny_a9g20_eeprom tny_a9260:AT91SAM9G20,SYS_USE_EEPROM Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Orphan arm arm926ejs at91 calao tny_a9260 tny_a9g20_nandflash tny_a9260:AT91SAM9G20,SYS_USE_NANDFLASH Albin Tonnerre <albin.tonnerre@free-electrons.com>
+Orphan arm armv7 mx6 congatec cgtqmx6eval cgtqmx6qeval cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q Leo Sartre <lsartre@adeneo-embedded.com>
+Orphan arm pxa - - - palmtreo680 - Mike Dunn <mikedunn@newsguy.com>
+Orphan avr32 at32ap at32ap700x atmel - atngw100 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Orphan avr32 at32ap at32ap700x atmel atstk1000 atstk1002 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Orphan avr32 at32ap at32ap700x atmel atstk1000 atstk1003 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Orphan avr32 at32ap at32ap700x atmel atstk1000 atstk1004 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Orphan avr32 at32ap at32ap700x atmel atstk1000 atstk1006 - Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
+Orphan avr32 at32ap at32ap700x earthlcd - favr-32-ezkit - Hans-Christian Egtvedt <hans-christian.egtvedt@atmel.com>
+Orphan blackfin blackfin - - - ip04 - Brent Kandetzki <brentk@teleco.com>
+Orphan m68k mcf52x2 - freescale m5253evbe M5253EVBE - Hayden Fraser <Hayden.Fraser@freescale.com>
+Orphan powerpc mpc5xxx - - galaxy5200 galaxy5200 galaxy5200:galaxy5200 Eric Millbrandt <emillbrandt@dekaresearch.com>
+Orphan powerpc mpc5xxx - - galaxy5200 galaxy5200_LOWBOOT galaxy5200:galaxy5200_LOWBOOT Eric Millbrandt <emillbrandt@dekaresearch.com>
+Orphan powerpc mpc8260 - - - ep8260 - Frank Panno <fpanno@delphintech.com>
+Orphan powerpc mpc8260 - - - sacsng - Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
+Orphan powerpc mpc83xx - freescale mpc837xerdb MPC837XERDB - Joe D'Abbraccio <ljd015@freescale.com>
+Orphan powerpc mpc85xx - exmeritus hww1u1a HWW1U1A - Kyle Moffett <Kyle.D.Moffett@boeing.com>
+Orphan powerpc mpc85xx - freescale mpc8540ads MPC8540ADS - Kumar Gala <kumar.gala@freescale.com>
+Orphan powerpc mpc85xx - freescale mpc8541cds MPC8541CDS - Kumar Gala <kumar.gala@freescale.com>
+Orphan powerpc mpc85xx - freescale mpc8541cds MPC8541CDS_legacy MPC8541CDS:LEGACY Kumar Gala <kumar.gala@freescale.com>
+Orphan powerpc mpc85xx - freescale mpc8555cds MPC8555CDS - Kumar Gala <kumar.gala@freescale.com>
+Orphan powerpc mpc85xx - freescale mpc8555cds MPC8555CDS_legacy MPC8555CDS:LEGACY Kumar Gala <kumar.gala@freescale.com>
+Orphan powerpc mpc85xx - freescale mpc8560ads MPC8560ADS - Kumar Gala <kumar.gala@freescale.com>
+Orphan powerpc mpc85xx - stx stxgp3 stxgp3 - Dan Malek <dan@embeddedalley.com>
+Orphan powerpc mpc85xx - stx stxssa stxssa - Dan Malek <dan@embeddedalley.com>
+Orphan powerpc mpc85xx - stx stxssa stxssa_4M stxssa:STXSSA_4M Dan Malek <dan@embeddedalley.com>
+Orphan powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN - Kumar Gala <kumar.gala@freescale.com>
+Orphan powerpc mpc86xx - freescale mpc8641hpcn MPC8641HPCN_36BIT MPC8641HPCN:PHYS_64BIT Kumar Gala <kumar.gala@freescale.com>
+Orphan powerpc mpc8xx - - - svm_sc8xx - John Zhan <zhanz@sinovee.com>
+Orphan powerpc mpc8xx - - flagadm FLAGADM - Kári DavÃðsson <kd@flaga.is>
+Orphan powerpc mpc8xx - - gen860t GEN860T - Keith Outwater <Keith_Outwater@mvis.com>
+Orphan powerpc mpc8xx - - gen860t GEN860T_SC GEN860T:SC Keith Outwater <Keith_Outwater@mvis.com>
+Orphan powerpc mpc8xx - - sixnet SXNI855T - Dave Ellis <DGE@sixnetio.com>
+Orphan powerpc mpc8xx - stx stxxtc stxxtc - Dan Malek <dan@embeddedalley.com>
# The following were moved to "Orphan" in April, 2014
Orphan powerpc 74xx_7xx - - evb64260 ZUMA - Nye Liu <nyet@zumanetworks.com>
Orphan powerpc mpc824x - - musenki MUSENKI - Jim Thompson <jim@musenki.com>
Orphan blackfin blackfin - - - tcm-bf537 - Bluetechnix Tinyboards <bluetechnix@blackfin.uclinux.org>
Orphan powerpc mpc5xxx - matrix_vision mvbc_p MVBC_P MVBC_P:MVBC_P Andre Schwarz <andre.schwarz@matrix-vision.de>
Orphan powerpc mpc5xxx - matrix_vision mvsmr MVSMR - Andre Schwarz <andre.schwarz@matrix-vision.de>
-Orphan powerpc mpc824x - - hidden_dragon HIDDEN_DRAGON - Yusdi Santoso <yusdi_santoso@adaptec.com>
-Orphan powerpc mpc824x - etin - debris - Sangmoon Kim <dogoil@etinsys.com>
-Orphan powerpc mpc824x - etin - kvme080 - Sangmoon Kim <dogoil@etinsys.com>
-Orphan powerpc mpc8260 - - ep8248 ep8248 - Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - - ispan ISPAN - Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - - ispan ISPAN_REVB ISPAN:SYS_REV_B Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - - rattler Rattler - Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - - rattler Rattler8248 Rattler:MPC8248 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - - zpc1900 ZPC1900 - Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_33MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=33000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_40MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,8260_CLKIN=40000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads MPC8260ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8260ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads MPC8272ADS MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads MPC8272ADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_8272ADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-VR_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_66MHz_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,8260_CLKIN=66000000,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS-ZU_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8260 - freescale mpc8260ads PQ2FADS_lowboot MPC8260ADS:ADSTYPE=CONFIG_SYS_PQ2FADS,SYS_TEXT_BASE=0xFF800000 Yuli Barcohen <yuli@arabellasw.com>
Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK - Anton Vorontsov <avorontsov@ru.mvista.com>
Orphan powerpc mpc83xx - freescale mpc8360erdk MPC8360ERDK_33 MPC8360ERDK:CLKIN_33MHZ Anton Vorontsov <avorontsov@ru.mvista.com>
Orphan powerpc mpc83xx - matrix_vision mergerbox MERGERBOX - Andre Schwarz <andre.schwarz@matrix-vision.de>
Orphan powerpc mpc83xx - matrix_vision mvblm7 MVBLM7 - Andre Schwarz <andre.schwarz@matrix-vision.de>
-Orphan powerpc mpc8xx - - adder Adder - Yuli Barcohen <yuli@arabellasw.com>
-Orphan powerpc mpc8xx - - adder AdderII Adder:MPC852T Yuli Barcohen <yuli@arabellasw.com>
Orphan powerpc ppc4xx - amcc - bluestone - Tirumala Marri <tmarri@apm.com>
Orphan powerpc ppc4xx - cray L1 CRAYL1 - David Updegraff <dave@cray.com>
Orphan powerpc ppc4xx - sandburst karef KAREF - Travis Sawyer <travis.sawyer@sandburst.com>
obj-y += command.o
obj-y += exports.o
obj-y += hash.o
-obj-$(CONFIG_SYS_HUSH_PARSER) += hush.o
+ifdef CONFIG_SYS_HUSH_PARSER
+obj-y += cli_hush.o
+endif
+
+# We always have this since drivers/ddr/fs/interactive.c needs it
+obj-y += cli_simple.o
+
+obj-y += cli.o
+obj-y += cli_readline.o
obj-y += s_record.o
obj-y += xyzModem.o
obj-y += cmd_disk.o
+# This option is not just y/n - it can have a numeric value
+ifdef CONFIG_BOOTDELAY
+obj-y += autoboot.o
+endif
+
+# This option is not just y/n - it can have a numeric value
+ifdef CONFIG_BOOT_RETRY_TIME
+obj-y += bootretry.o
+endif
+
# boards
obj-$(CONFIG_SYS_GENERIC_BOARD) += board_f.o
obj-$(CONFIG_SYS_GENERIC_BOARD) += board_r.o
# core command
obj-y += cmd_boot.o
-obj-$(CONFIG_CMD_BOOTM) += cmd_bootm.o
+obj-$(CONFIG_CMD_BOOTM) += cmd_bootm.o bootm.o bootm_os.o
obj-y += cmd_help.o
obj-y += cmd_version.o
obj-$(CONFIG_CMD_GETTIME) += cmd_gettime.o
obj-$(CONFIG_CMD_GPIO) += cmd_gpio.o
obj-$(CONFIG_CMD_I2C) += cmd_i2c.o
+obj-$(CONFIG_CMD_IOTRACE) += cmd_iotrace.o
obj-$(CONFIG_CMD_HASH) += cmd_hash.o
obj-$(CONFIG_CMD_IDE) += cmd_ide.o
obj-$(CONFIG_CMD_IMMAP) += cmd_immap.o
obj-$(CONFIG_OF_LIBFDT) += image-fdt.o
obj-$(CONFIG_FIT) += image-fit.o
obj-$(CONFIG_FIT_SIGNATURE) += image-sig.o
+obj-$(CONFIG_IO_TRACE) += iotrace.o
obj-y += memsize.o
obj-y += stdio.o
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <bootretry.h>
+#include <cli.h>
+#include <fdtdec.h>
+#include <menu.h>
+#include <post.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MAX_DELAY_STOP_STR 32
+
+#ifndef DEBUG_BOOTKEYS
+#define DEBUG_BOOTKEYS 0
+#endif
+#define debug_bootkeys(fmt, args...) \
+ debug_cond(DEBUG_BOOTKEYS, fmt, ##args)
+
+/* Stored value of bootdelay, used by autoboot_command() */
+static int stored_bootdelay;
+
+/***************************************************************************
+ * Watch for 'delay' seconds for autoboot stop or autoboot delay string.
+ * returns: 0 - no key string, allow autoboot 1 - got key string, abort
+ */
+# if defined(CONFIG_AUTOBOOT_KEYED)
+static int abortboot_keyed(int bootdelay)
+{
+ int abort = 0;
+ uint64_t etime = endtick(bootdelay);
+ struct {
+ char *str;
+ u_int len;
+ int retry;
+ }
+ delaykey[] = {
+ { .str = getenv("bootdelaykey"), .retry = 1 },
+ { .str = getenv("bootdelaykey2"), .retry = 1 },
+ { .str = getenv("bootstopkey"), .retry = 0 },
+ { .str = getenv("bootstopkey2"), .retry = 0 },
+ };
+
+ char presskey[MAX_DELAY_STOP_STR];
+ u_int presskey_len = 0;
+ u_int presskey_max = 0;
+ u_int i;
+
+#ifndef CONFIG_ZERO_BOOTDELAY_CHECK
+ if (bootdelay == 0)
+ return 0;
+#endif
+
+# ifdef CONFIG_AUTOBOOT_PROMPT
+ printf(CONFIG_AUTOBOOT_PROMPT);
+# endif
+
+# ifdef CONFIG_AUTOBOOT_DELAY_STR
+ if (delaykey[0].str == NULL)
+ delaykey[0].str = CONFIG_AUTOBOOT_DELAY_STR;
+# endif
+# ifdef CONFIG_AUTOBOOT_DELAY_STR2
+ if (delaykey[1].str == NULL)
+ delaykey[1].str = CONFIG_AUTOBOOT_DELAY_STR2;
+# endif
+# ifdef CONFIG_AUTOBOOT_STOP_STR
+ if (delaykey[2].str == NULL)
+ delaykey[2].str = CONFIG_AUTOBOOT_STOP_STR;
+# endif
+# ifdef CONFIG_AUTOBOOT_STOP_STR2
+ if (delaykey[3].str == NULL)
+ delaykey[3].str = CONFIG_AUTOBOOT_STOP_STR2;
+# endif
+
+ for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i++) {
+ delaykey[i].len = delaykey[i].str == NULL ?
+ 0 : strlen(delaykey[i].str);
+ delaykey[i].len = delaykey[i].len > MAX_DELAY_STOP_STR ?
+ MAX_DELAY_STOP_STR : delaykey[i].len;
+
+ presskey_max = presskey_max > delaykey[i].len ?
+ presskey_max : delaykey[i].len;
+
+ debug_bootkeys("%s key:<%s>\n",
+ delaykey[i].retry ? "delay" : "stop",
+ delaykey[i].str ? delaykey[i].str : "NULL");
+ }
+
+ /* In order to keep up with incoming data, check timeout only
+ * when catch up.
+ */
+ do {
+ if (tstc()) {
+ if (presskey_len < presskey_max) {
+ presskey[presskey_len++] = getc();
+ } else {
+ for (i = 0; i < presskey_max - 1; i++)
+ presskey[i] = presskey[i + 1];
+
+ presskey[i] = getc();
+ }
+ }
+
+ for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i++) {
+ if (delaykey[i].len > 0 &&
+ presskey_len >= delaykey[i].len &&
+ memcmp(presskey + presskey_len -
+ delaykey[i].len, delaykey[i].str,
+ delaykey[i].len) == 0) {
+ debug_bootkeys("got %skey\n",
+ delaykey[i].retry ? "delay" :
+ "stop");
+
+ /* don't retry auto boot */
+ if (!delaykey[i].retry)
+ bootretry_dont_retry();
+ abort = 1;
+ }
+ }
+ } while (!abort && get_ticks() <= etime);
+
+ if (!abort)
+ debug_bootkeys("key timeout\n");
+
+#ifdef CONFIG_SILENT_CONSOLE
+ if (abort)
+ gd->flags &= ~GD_FLG_SILENT;
+#endif
+
+ return abort;
+}
+
+# else /* !defined(CONFIG_AUTOBOOT_KEYED) */
+
+#ifdef CONFIG_MENUKEY
+static int menukey;
+#endif
+
+static int abortboot_normal(int bootdelay)
+{
+ int abort = 0;
+ unsigned long ts;
+
+#ifdef CONFIG_MENUPROMPT
+ printf(CONFIG_MENUPROMPT);
+#else
+ if (bootdelay >= 0)
+ printf("Hit any key to stop autoboot: %2d ", bootdelay);
+#endif
+
+#if defined CONFIG_ZERO_BOOTDELAY_CHECK
+ /*
+ * Check if key already pressed
+ * Don't check if bootdelay < 0
+ */
+ if (bootdelay >= 0) {
+ if (tstc()) { /* we got a key press */
+ (void) getc(); /* consume input */
+ puts("\b\b\b 0");
+ abort = 1; /* don't auto boot */
+ }
+ }
+#endif
+
+ while ((bootdelay > 0) && (!abort)) {
+ --bootdelay;
+ /* delay 1000 ms */
+ ts = get_timer(0);
+ do {
+ if (tstc()) { /* we got a key press */
+ abort = 1; /* don't auto boot */
+ bootdelay = 0; /* no more delay */
+# ifdef CONFIG_MENUKEY
+ menukey = getc();
+# else
+ (void) getc(); /* consume input */
+# endif
+ break;
+ }
+ udelay(10000);
+ } while (!abort && get_timer(ts) < 1000);
+
+ printf("\b\b\b%2d ", bootdelay);
+ }
+
+ putc('\n');
+
+#ifdef CONFIG_SILENT_CONSOLE
+ if (abort)
+ gd->flags &= ~GD_FLG_SILENT;
+#endif
+
+ return abort;
+}
+# endif /* CONFIG_AUTOBOOT_KEYED */
+
+static int abortboot(int bootdelay)
+{
+#ifdef CONFIG_AUTOBOOT_KEYED
+ return abortboot_keyed(bootdelay);
+#else
+ return abortboot_normal(bootdelay);
+#endif
+}
+
+static void process_fdt_options(const void *blob)
+{
+#if defined(CONFIG_OF_CONTROL)
+ ulong addr;
+
+ /* Add an env variable to point to a kernel payload, if available */
+ addr = fdtdec_get_config_int(gd->fdt_blob, "kernel-offset", 0);
+ if (addr)
+ setenv_addr("kernaddr", (void *)(CONFIG_SYS_TEXT_BASE + addr));
+
+ /* Add an env variable to point to a root disk, if available */
+ addr = fdtdec_get_config_int(gd->fdt_blob, "rootdisk-offset", 0);
+ if (addr)
+ setenv_addr("rootaddr", (void *)(CONFIG_SYS_TEXT_BASE + addr));
+#endif /* CONFIG_OF_CONTROL */
+}
+
+const char *bootdelay_process(void)
+{
+ char *s;
+ int bootdelay;
+#ifdef CONFIG_BOOTCOUNT_LIMIT
+ unsigned long bootcount = 0;
+ unsigned long bootlimit = 0;
+#endif /* CONFIG_BOOTCOUNT_LIMIT */
+
+#ifdef CONFIG_BOOTCOUNT_LIMIT
+ bootcount = bootcount_load();
+ bootcount++;
+ bootcount_store(bootcount);
+ setenv_ulong("bootcount", bootcount);
+ bootlimit = getenv_ulong("bootlimit", 10, 0);
+#endif /* CONFIG_BOOTCOUNT_LIMIT */
+
+ s = getenv("bootdelay");
+ bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY;
+
+#ifdef CONFIG_OF_CONTROL
+ bootdelay = fdtdec_get_config_int(gd->fdt_blob, "bootdelay",
+ bootdelay);
+#endif
+
+ debug("### main_loop entered: bootdelay=%d\n\n", bootdelay);
+
+#if defined(CONFIG_MENU_SHOW)
+ bootdelay = menu_show(bootdelay);
+#endif
+ bootretry_init_cmd_timeout();
+
+#ifdef CONFIG_POST
+ if (gd->flags & GD_FLG_POSTFAIL) {
+ s = getenv("failbootcmd");
+ } else
+#endif /* CONFIG_POST */
+#ifdef CONFIG_BOOTCOUNT_LIMIT
+ if (bootlimit && (bootcount > bootlimit)) {
+ printf("Warning: Bootlimit (%u) exceeded. Using altbootcmd.\n",
+ (unsigned)bootlimit);
+ s = getenv("altbootcmd");
+ } else
+#endif /* CONFIG_BOOTCOUNT_LIMIT */
+ s = getenv("bootcmd");
+
+ process_fdt_options(gd->fdt_blob);
+ stored_bootdelay = bootdelay;
+
+ return s;
+}
+
+void autoboot_command(const char *s)
+{
+ debug("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>");
+
+ if (stored_bootdelay != -1 && s && !abortboot(stored_bootdelay)) {
+#if defined(CONFIG_AUTOBOOT_KEYED) && !defined(CONFIG_AUTOBOOT_KEYED_CTRLC)
+ int prev = disable_ctrlc(1); /* disable Control C checking */
+#endif
+
+ run_command_list(s, -1, 0);
+
+#if defined(CONFIG_AUTOBOOT_KEYED) && !defined(CONFIG_AUTOBOOT_KEYED_CTRLC)
+ disable_ctrlc(prev); /* restore Control C checking */
+#endif
+ }
+
+#ifdef CONFIG_MENUKEY
+ if (menukey == CONFIG_MENUKEY) {
+ s = getenv("menucmd");
+ if (s)
+ run_command_list(s, -1, 0);
+ }
+#endif /* CONFIG_MENUKEY */
+}
}
#endif
-#ifdef CONFIG_MODEM_SUPPORT
-static int initr_modem(void)
-{
- /* TODO: with new initcalls, move this into the driver */
- extern int do_mdm_init;
-
- do_mdm_init = gd->do_mdm_init;
- return 0;
-}
-#endif
-
static int run_main_loop(void)
{
#ifdef CONFIG_SANDBOX
#endif
#ifdef CONFIG_PS2KBD
initr_kbd,
-#endif
-#ifdef CONFIG_MODEM_SUPPORT
- initr_modem,
#endif
run_main_loop,
};
--- /dev/null
+/*
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef USE_HOSTCC
+#include <common.h>
+#include <bootstage.h>
+#include <bzlib.h>
+#include <fdt_support.h>
+#include <lmb.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <linux/lzo.h>
+#include <lzma/LzmaTypes.h>
+#include <lzma/LzmaDec.h>
+#include <lzma/LzmaTools.h>
+#if defined(CONFIG_CMD_USB)
+#include <usb.h>
+#endif
+#else
+#include "mkimage.h"
+#endif
+
+#include <command.h>
+#include <bootm.h>
+#include <image.h>
+
+#ifndef CONFIG_SYS_BOOTM_LEN
+/* use 8MByte as default max gunzip size */
+#define CONFIG_SYS_BOOTM_LEN 0x800000
+#endif
+
+#define IH_INITRD_ARCH IH_ARCH_DEFAULT
+
+#ifndef USE_HOSTCC
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const void *boot_get_kernel(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[], bootm_headers_t *images,
+ ulong *os_data, ulong *os_len);
+
+#ifdef CONFIG_LMB
+static void boot_start_lmb(bootm_headers_t *images)
+{
+ ulong mem_start;
+ phys_size_t mem_size;
+
+ lmb_init(&images->lmb);
+
+ mem_start = getenv_bootm_low();
+ mem_size = getenv_bootm_size();
+
+ lmb_add(&images->lmb, (phys_addr_t)mem_start, mem_size);
+
+ arch_lmb_reserve(&images->lmb);
+ board_lmb_reserve(&images->lmb);
+}
+#else
+#define lmb_reserve(lmb, base, size)
+static inline void boot_start_lmb(bootm_headers_t *images) { }
+#endif
+
+static int bootm_start(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ memset((void *)&images, 0, sizeof(images));
+ images.verify = getenv_yesno("verify");
+
+ boot_start_lmb(&images);
+
+ bootstage_mark_name(BOOTSTAGE_ID_BOOTM_START, "bootm_start");
+ images.state = BOOTM_STATE_START;
+
+ return 0;
+}
+
+static int bootm_find_os(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ const void *os_hdr;
+ bool ep_found = false;
+
+ /* get kernel image header, start address and length */
+ os_hdr = boot_get_kernel(cmdtp, flag, argc, argv,
+ &images, &images.os.image_start, &images.os.image_len);
+ if (images.os.image_len == 0) {
+ puts("ERROR: can't get kernel image!\n");
+ return 1;
+ }
+
+ /* get image parameters */
+ switch (genimg_get_format(os_hdr)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+ case IMAGE_FORMAT_LEGACY:
+ images.os.type = image_get_type(os_hdr);
+ images.os.comp = image_get_comp(os_hdr);
+ images.os.os = image_get_os(os_hdr);
+
+ images.os.end = image_get_image_end(os_hdr);
+ images.os.load = image_get_load(os_hdr);
+ break;
+#endif
+#if defined(CONFIG_FIT)
+ case IMAGE_FORMAT_FIT:
+ if (fit_image_get_type(images.fit_hdr_os,
+ images.fit_noffset_os,
+ &images.os.type)) {
+ puts("Can't get image type!\n");
+ bootstage_error(BOOTSTAGE_ID_FIT_TYPE);
+ return 1;
+ }
+
+ if (fit_image_get_comp(images.fit_hdr_os,
+ images.fit_noffset_os,
+ &images.os.comp)) {
+ puts("Can't get image compression!\n");
+ bootstage_error(BOOTSTAGE_ID_FIT_COMPRESSION);
+ return 1;
+ }
+
+ if (fit_image_get_os(images.fit_hdr_os, images.fit_noffset_os,
+ &images.os.os)) {
+ puts("Can't get image OS!\n");
+ bootstage_error(BOOTSTAGE_ID_FIT_OS);
+ return 1;
+ }
+
+ images.os.end = fit_get_end(images.fit_hdr_os);
+
+ if (fit_image_get_load(images.fit_hdr_os, images.fit_noffset_os,
+ &images.os.load)) {
+ puts("Can't get image load address!\n");
+ bootstage_error(BOOTSTAGE_ID_FIT_LOADADDR);
+ return 1;
+ }
+ break;
+#endif
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+ case IMAGE_FORMAT_ANDROID:
+ images.os.type = IH_TYPE_KERNEL;
+ images.os.comp = IH_COMP_NONE;
+ images.os.os = IH_OS_LINUX;
+ images.ep = images.os.load;
+ ep_found = true;
+
+ images.os.end = android_image_get_end(os_hdr);
+ images.os.load = android_image_get_kload(os_hdr);
+ break;
+#endif
+ default:
+ puts("ERROR: unknown image format type!\n");
+ return 1;
+ }
+
+ /* find kernel entry point */
+ if (images.legacy_hdr_valid) {
+ images.ep = image_get_ep(&images.legacy_hdr_os_copy);
+#if defined(CONFIG_FIT)
+ } else if (images.fit_uname_os) {
+ int ret;
+
+ ret = fit_image_get_entry(images.fit_hdr_os,
+ images.fit_noffset_os, &images.ep);
+ if (ret) {
+ puts("Can't get entry point property!\n");
+ return 1;
+ }
+#endif
+ } else if (!ep_found) {
+ puts("Could not find kernel entry point!\n");
+ return 1;
+ }
+
+ if (images.os.type == IH_TYPE_KERNEL_NOLOAD) {
+ images.os.load = images.os.image_start;
+ images.ep += images.os.load;
+ }
+
+ images.os.start = (ulong)os_hdr;
+
+ return 0;
+}
+
+static int bootm_find_ramdisk(int flag, int argc, char * const argv[])
+{
+ int ret;
+
+ /* find ramdisk */
+ ret = boot_get_ramdisk(argc, argv, &images, IH_INITRD_ARCH,
+ &images.rd_start, &images.rd_end);
+ if (ret) {
+ puts("Ramdisk image is corrupt or invalid\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT)
+static int bootm_find_fdt(int flag, int argc, char * const argv[])
+{
+ int ret;
+
+ /* find flattened device tree */
+ ret = boot_get_fdt(flag, argc, argv, IH_ARCH_DEFAULT, &images,
+ &images.ft_addr, &images.ft_len);
+ if (ret) {
+ puts("Could not find a valid device tree\n");
+ return 1;
+ }
+
+ set_working_fdt_addr(images.ft_addr);
+
+ return 0;
+}
+#endif
+
+int bootm_find_ramdisk_fdt(int flag, int argc, char * const argv[])
+{
+ if (bootm_find_ramdisk(flag, argc, argv))
+ return 1;
+
+#if defined(CONFIG_OF_LIBFDT)
+ if (bootm_find_fdt(flag, argc, argv))
+ return 1;
+#endif
+
+ return 0;
+}
+
+static int bootm_find_other(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ if (((images.os.type == IH_TYPE_KERNEL) ||
+ (images.os.type == IH_TYPE_KERNEL_NOLOAD) ||
+ (images.os.type == IH_TYPE_MULTI)) &&
+ (images.os.os == IH_OS_LINUX ||
+ images.os.os == IH_OS_VXWORKS))
+ return bootm_find_ramdisk_fdt(flag, argc, argv);
+
+ return 0;
+}
+#endif /* USE_HOSTCC */
+
+/**
+ * decomp_image() - decompress the operating system
+ *
+ * @comp: Compression algorithm that is used (IH_COMP_...)
+ * @load: Destination load address in U-Boot memory
+ * @image_start Image start address (where we are decompressing from)
+ * @type: OS type (IH_OS_...)
+ * @load_bug: Place to decompress to
+ * @image_buf: Address to decompress from
+ * @return 0 if OK, -ve on error (BOOTM_ERR_...)
+ */
+static int decomp_image(int comp, ulong load, ulong image_start, int type,
+ void *load_buf, void *image_buf, ulong image_len,
+ ulong *load_end)
+{
+ const char *type_name = genimg_get_type_name(type);
+ __attribute__((unused)) uint unc_len = CONFIG_SYS_BOOTM_LEN;
+
+ *load_end = load;
+ switch (comp) {
+ case IH_COMP_NONE:
+ if (load == image_start) {
+ printf(" XIP %s ... ", type_name);
+ } else {
+ printf(" Loading %s ... ", type_name);
+ memmove_wd(load_buf, image_buf, image_len, CHUNKSZ);
+ }
+ *load_end = load + image_len;
+ break;
+#ifdef CONFIG_GZIP
+ case IH_COMP_GZIP:
+ printf(" Uncompressing %s ... ", type_name);
+ if (gunzip(load_buf, unc_len, image_buf, &image_len) != 0) {
+ puts("GUNZIP: uncompress, out-of-mem or overwrite error - must RESET board to recover\n");
+ return BOOTM_ERR_RESET;
+ }
+
+ *load_end = load + image_len;
+ break;
+#endif /* CONFIG_GZIP */
+#ifdef CONFIG_BZIP2
+ case IH_COMP_BZIP2:
+ printf(" Uncompressing %s ... ", type_name);
+ /*
+ * If we've got less than 4 MB of malloc() space,
+ * use slower decompression algorithm which requires
+ * at most 2300 KB of memory.
+ */
+ int i = BZ2_bzBuffToBuffDecompress(load_buf, &unc_len,
+ image_buf, image_len,
+ CONFIG_SYS_MALLOC_LEN < (4096 * 1024), 0);
+ if (i != BZ_OK) {
+ printf("BUNZIP2: uncompress or overwrite error %d - must RESET board to recover\n",
+ i);
+ return BOOTM_ERR_RESET;
+ }
+
+ *load_end = load + unc_len;
+ break;
+#endif /* CONFIG_BZIP2 */
+#ifdef CONFIG_LZMA
+ case IH_COMP_LZMA: {
+ SizeT lzma_len = unc_len;
+ int ret;
+
+ printf(" Uncompressing %s ... ", type_name);
+
+ ret = lzmaBuffToBuffDecompress(load_buf, &lzma_len,
+ image_buf, image_len);
+ unc_len = lzma_len;
+ if (ret != SZ_OK) {
+ printf("LZMA: uncompress or overwrite error %d - must RESET board to recover\n",
+ ret);
+ bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE);
+ return BOOTM_ERR_RESET;
+ }
+ *load_end = load + unc_len;
+ break;
+ }
+#endif /* CONFIG_LZMA */
+#ifdef CONFIG_LZO
+ case IH_COMP_LZO: {
+ size_t size = unc_len;
+ int ret;
+
+ printf(" Uncompressing %s ... ", type_name);
+
+ ret = lzop_decompress(image_buf, image_len, load_buf, &size);
+ if (ret != LZO_E_OK) {
+ printf("LZO: uncompress or overwrite error %d - must RESET board to recover\n",
+ ret);
+ return BOOTM_ERR_RESET;
+ }
+
+ *load_end = load + size;
+ break;
+ }
+#endif /* CONFIG_LZO */
+ default:
+ printf("Unimplemented compression type %d\n", comp);
+ return BOOTM_ERR_UNIMPLEMENTED;
+ }
+
+ puts("OK\n");
+
+ return 0;
+}
+
+#ifndef USE_HOSTCC
+static int bootm_load_os(bootm_headers_t *images, unsigned long *load_end,
+ int boot_progress)
+{
+ image_info_t os = images->os;
+ ulong load = os.load;
+ ulong blob_start = os.start;
+ ulong blob_end = os.end;
+ ulong image_start = os.image_start;
+ ulong image_len = os.image_len;
+ bool no_overlap;
+ void *load_buf, *image_buf;
+ int err;
+
+ load_buf = map_sysmem(load, 0);
+ image_buf = map_sysmem(os.image_start, image_len);
+ err = decomp_image(os.comp, load, os.image_start, os.type, load_buf,
+ image_buf, image_len, load_end);
+ if (err) {
+ bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE);
+ return err;
+ }
+ flush_cache(load, (*load_end - load) * sizeof(ulong));
+
+ debug(" kernel loaded at 0x%08lx, end = 0x%08lx\n", load, *load_end);
+ bootstage_mark(BOOTSTAGE_ID_KERNEL_LOADED);
+
+ no_overlap = (os.comp == IH_COMP_NONE && load == image_start);
+
+ if (!no_overlap && (load < blob_end) && (*load_end > blob_start)) {
+ debug("images.os.start = 0x%lX, images.os.end = 0x%lx\n",
+ blob_start, blob_end);
+ debug("images.os.load = 0x%lx, load_end = 0x%lx\n", load,
+ *load_end);
+
+ /* Check what type of image this is. */
+ if (images->legacy_hdr_valid) {
+ if (image_get_type(&images->legacy_hdr_os_copy)
+ == IH_TYPE_MULTI)
+ puts("WARNING: legacy format multi component image overwritten\n");
+ return BOOTM_ERR_OVERLAP;
+ } else {
+ puts("ERROR: new format image overwritten - must RESET the board to recover\n");
+ bootstage_error(BOOTSTAGE_ID_OVERWRITTEN);
+ return BOOTM_ERR_RESET;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * bootm_disable_interrupts() - Disable interrupts in preparation for load/boot
+ *
+ * @return interrupt flag (0 if interrupts were disabled, non-zero if they were
+ * enabled)
+ */
+ulong bootm_disable_interrupts(void)
+{
+ ulong iflag;
+
+ /*
+ * We have reached the point of no return: we are going to
+ * overwrite all exception vector code, so we cannot easily
+ * recover from any failures any more...
+ */
+ iflag = disable_interrupts();
+#ifdef CONFIG_NETCONSOLE
+ /* Stop the ethernet stack if NetConsole could have left it up */
+ eth_halt();
+ eth_unregister(eth_get_dev());
+#endif
+
+#if defined(CONFIG_CMD_USB)
+ /*
+ * turn off USB to prevent the host controller from writing to the
+ * SDRAM while Linux is booting. This could happen (at least for OHCI
+ * controller), because the HCCA (Host Controller Communication Area)
+ * lies within the SDRAM and the host controller writes continously to
+ * this area (as busmaster!). The HccaFrameNumber is for example
+ * updated every 1 ms within the HCCA structure in SDRAM! For more
+ * details see the OpenHCI specification.
+ */
+ usb_stop();
+#endif
+ return iflag;
+}
+
+#if defined(CONFIG_SILENT_CONSOLE) && !defined(CONFIG_SILENT_U_BOOT_ONLY)
+
+#define CONSOLE_ARG "console="
+#define CONSOLE_ARG_LEN (sizeof(CONSOLE_ARG) - 1)
+
+static void fixup_silent_linux(void)
+{
+ char *buf;
+ const char *env_val;
+ char *cmdline = getenv("bootargs");
+ int want_silent;
+
+ /*
+ * Only fix cmdline when requested. The environment variable can be:
+ *
+ * no - we never fixup
+ * yes - we always fixup
+ * unset - we rely on the console silent flag
+ */
+ want_silent = getenv_yesno("silent_linux");
+ if (want_silent == 0)
+ return;
+ else if (want_silent == -1 && !(gd->flags & GD_FLG_SILENT))
+ return;
+
+ debug("before silent fix-up: %s\n", cmdline);
+ if (cmdline && (cmdline[0] != '\0')) {
+ char *start = strstr(cmdline, CONSOLE_ARG);
+
+ /* Allocate space for maximum possible new command line */
+ buf = malloc(strlen(cmdline) + 1 + CONSOLE_ARG_LEN + 1);
+ if (!buf) {
+ debug("%s: out of memory\n", __func__);
+ return;
+ }
+
+ if (start) {
+ char *end = strchr(start, ' ');
+ int num_start_bytes = start - cmdline + CONSOLE_ARG_LEN;
+
+ strncpy(buf, cmdline, num_start_bytes);
+ if (end)
+ strcpy(buf + num_start_bytes, end);
+ else
+ buf[num_start_bytes] = '\0';
+ } else {
+ sprintf(buf, "%s %s", cmdline, CONSOLE_ARG);
+ }
+ env_val = buf;
+ } else {
+ buf = NULL;
+ env_val = CONSOLE_ARG;
+ }
+
+ setenv("bootargs", env_val);
+ debug("after silent fix-up: %s\n", env_val);
+ free(buf);
+}
+#endif /* CONFIG_SILENT_CONSOLE */
+
+/**
+ * Execute selected states of the bootm command.
+ *
+ * Note the arguments to this state must be the first argument, Any 'bootm'
+ * or sub-command arguments must have already been taken.
+ *
+ * Note that if states contains more than one flag it MUST contain
+ * BOOTM_STATE_START, since this handles and consumes the command line args.
+ *
+ * Also note that aside from boot_os_fn functions and bootm_load_os no other
+ * functions we store the return value of in 'ret' may use a negative return
+ * value, without special handling.
+ *
+ * @param cmdtp Pointer to bootm command table entry
+ * @param flag Command flags (CMD_FLAG_...)
+ * @param argc Number of subcommand arguments (0 = no arguments)
+ * @param argv Arguments
+ * @param states Mask containing states to run (BOOTM_STATE_...)
+ * @param images Image header information
+ * @param boot_progress 1 to show boot progress, 0 to not do this
+ * @return 0 if ok, something else on error. Some errors will cause this
+ * function to perform a reboot! If states contains BOOTM_STATE_OS_GO
+ * then the intent is to boot an OS, so this function will not return
+ * unless the image type is standalone.
+ */
+int do_bootm_states(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+ int states, bootm_headers_t *images, int boot_progress)
+{
+ boot_os_fn *boot_fn;
+ ulong iflag = 0;
+ int ret = 0, need_boot_fn;
+
+ images->state |= states;
+
+ /*
+ * Work through the states and see how far we get. We stop on
+ * any error.
+ */
+ if (states & BOOTM_STATE_START)
+ ret = bootm_start(cmdtp, flag, argc, argv);
+
+ if (!ret && (states & BOOTM_STATE_FINDOS))
+ ret = bootm_find_os(cmdtp, flag, argc, argv);
+
+ if (!ret && (states & BOOTM_STATE_FINDOTHER)) {
+ ret = bootm_find_other(cmdtp, flag, argc, argv);
+ argc = 0; /* consume the args */
+ }
+
+ /* Load the OS */
+ if (!ret && (states & BOOTM_STATE_LOADOS)) {
+ ulong load_end;
+
+ iflag = bootm_disable_interrupts();
+ ret = bootm_load_os(images, &load_end, 0);
+ if (ret == 0)
+ lmb_reserve(&images->lmb, images->os.load,
+ (load_end - images->os.load));
+ else if (ret && ret != BOOTM_ERR_OVERLAP)
+ goto err;
+ else if (ret == BOOTM_ERR_OVERLAP)
+ ret = 0;
+#if defined(CONFIG_SILENT_CONSOLE) && !defined(CONFIG_SILENT_U_BOOT_ONLY)
+ if (images->os.os == IH_OS_LINUX)
+ fixup_silent_linux();
+#endif
+ }
+
+ /* Relocate the ramdisk */
+#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
+ if (!ret && (states & BOOTM_STATE_RAMDISK)) {
+ ulong rd_len = images->rd_end - images->rd_start;
+
+ ret = boot_ramdisk_high(&images->lmb, images->rd_start,
+ rd_len, &images->initrd_start, &images->initrd_end);
+ if (!ret) {
+ setenv_hex("initrd_start", images->initrd_start);
+ setenv_hex("initrd_end", images->initrd_end);
+ }
+ }
+#endif
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_LMB)
+ if (!ret && (states & BOOTM_STATE_FDT)) {
+ boot_fdt_add_mem_rsv_regions(&images->lmb, images->ft_addr);
+ ret = boot_relocate_fdt(&images->lmb, &images->ft_addr,
+ &images->ft_len);
+ }
+#endif
+
+ /* From now on, we need the OS boot function */
+ if (ret)
+ return ret;
+ boot_fn = bootm_os_get_boot_func(images->os.os);
+ need_boot_fn = states & (BOOTM_STATE_OS_CMDLINE |
+ BOOTM_STATE_OS_BD_T | BOOTM_STATE_OS_PREP |
+ BOOTM_STATE_OS_FAKE_GO | BOOTM_STATE_OS_GO);
+ if (boot_fn == NULL && need_boot_fn) {
+ if (iflag)
+ enable_interrupts();
+ printf("ERROR: booting os '%s' (%d) is not supported\n",
+ genimg_get_os_name(images->os.os), images->os.os);
+ bootstage_error(BOOTSTAGE_ID_CHECK_BOOT_OS);
+ return 1;
+ }
+
+ /* Call various other states that are not generally used */
+ if (!ret && (states & BOOTM_STATE_OS_CMDLINE))
+ ret = boot_fn(BOOTM_STATE_OS_CMDLINE, argc, argv, images);
+ if (!ret && (states & BOOTM_STATE_OS_BD_T))
+ ret = boot_fn(BOOTM_STATE_OS_BD_T, argc, argv, images);
+ if (!ret && (states & BOOTM_STATE_OS_PREP))
+ ret = boot_fn(BOOTM_STATE_OS_PREP, argc, argv, images);
+
+#ifdef CONFIG_TRACE
+ /* Pretend to run the OS, then run a user command */
+ if (!ret && (states & BOOTM_STATE_OS_FAKE_GO)) {
+ char *cmd_list = getenv("fakegocmd");
+
+ ret = boot_selected_os(argc, argv, BOOTM_STATE_OS_FAKE_GO,
+ images, boot_fn);
+ if (!ret && cmd_list)
+ ret = run_command_list(cmd_list, -1, flag);
+ }
+#endif
+
+ /* Check for unsupported subcommand. */
+ if (ret) {
+ puts("subcommand not supported\n");
+ return ret;
+ }
+
+ /* Now run the OS! We hope this doesn't return */
+ if (!ret && (states & BOOTM_STATE_OS_GO))
+ ret = boot_selected_os(argc, argv, BOOTM_STATE_OS_GO,
+ images, boot_fn);
+
+ /* Deal with any fallout */
+err:
+ if (iflag)
+ enable_interrupts();
+
+ if (ret == BOOTM_ERR_UNIMPLEMENTED)
+ bootstage_error(BOOTSTAGE_ID_DECOMP_UNIMPL);
+ else if (ret == BOOTM_ERR_RESET)
+ do_reset(cmdtp, flag, argc, argv);
+
+ return ret;
+}
+
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+/**
+ * image_get_kernel - verify legacy format kernel image
+ * @img_addr: in RAM address of the legacy format image to be verified
+ * @verify: data CRC verification flag
+ *
+ * image_get_kernel() verifies legacy image integrity and returns pointer to
+ * legacy image header if image verification was completed successfully.
+ *
+ * returns:
+ * pointer to a legacy image header if valid image was found
+ * otherwise return NULL
+ */
+static image_header_t *image_get_kernel(ulong img_addr, int verify)
+{
+ image_header_t *hdr = (image_header_t *)img_addr;
+
+ if (!image_check_magic(hdr)) {
+ puts("Bad Magic Number\n");
+ bootstage_error(BOOTSTAGE_ID_CHECK_MAGIC);
+ return NULL;
+ }
+ bootstage_mark(BOOTSTAGE_ID_CHECK_HEADER);
+
+ if (!image_check_hcrc(hdr)) {
+ puts("Bad Header Checksum\n");
+ bootstage_error(BOOTSTAGE_ID_CHECK_HEADER);
+ return NULL;
+ }
+
+ bootstage_mark(BOOTSTAGE_ID_CHECK_CHECKSUM);
+ image_print_contents(hdr);
+
+ if (verify) {
+ puts(" Verifying Checksum ... ");
+ if (!image_check_dcrc(hdr)) {
+ printf("Bad Data CRC\n");
+ bootstage_error(BOOTSTAGE_ID_CHECK_CHECKSUM);
+ return NULL;
+ }
+ puts("OK\n");
+ }
+ bootstage_mark(BOOTSTAGE_ID_CHECK_ARCH);
+
+ if (!image_check_target_arch(hdr)) {
+ printf("Unsupported Architecture 0x%x\n", image_get_arch(hdr));
+ bootstage_error(BOOTSTAGE_ID_CHECK_ARCH);
+ return NULL;
+ }
+ return hdr;
+}
+#endif
+
+/**
+ * boot_get_kernel - find kernel image
+ * @os_data: pointer to a ulong variable, will hold os data start address
+ * @os_len: pointer to a ulong variable, will hold os data length
+ *
+ * boot_get_kernel() tries to find a kernel image, verifies its integrity
+ * and locates kernel data.
+ *
+ * returns:
+ * pointer to image header if valid image was found, plus kernel start
+ * address and length, otherwise NULL
+ */
+static const void *boot_get_kernel(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[], bootm_headers_t *images,
+ ulong *os_data, ulong *os_len)
+{
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+ image_header_t *hdr;
+#endif
+ ulong img_addr;
+ const void *buf;
+#if defined(CONFIG_FIT)
+ const char *fit_uname_config = NULL;
+ const char *fit_uname_kernel = NULL;
+ int os_noffset;
+#endif
+
+ /* find out kernel image address */
+ if (argc < 1) {
+ img_addr = load_addr;
+ debug("* kernel: default image load address = 0x%08lx\n",
+ load_addr);
+#if defined(CONFIG_FIT)
+ } else if (fit_parse_conf(argv[0], load_addr, &img_addr,
+ &fit_uname_config)) {
+ debug("* kernel: config '%s' from image at 0x%08lx\n",
+ fit_uname_config, img_addr);
+ } else if (fit_parse_subimage(argv[0], load_addr, &img_addr,
+ &fit_uname_kernel)) {
+ debug("* kernel: subimage '%s' from image at 0x%08lx\n",
+ fit_uname_kernel, img_addr);
+#endif
+ } else {
+ img_addr = simple_strtoul(argv[0], NULL, 16);
+ debug("* kernel: cmdline image address = 0x%08lx\n",
+ img_addr);
+ }
+
+ bootstage_mark(BOOTSTAGE_ID_CHECK_MAGIC);
+
+ /* copy from dataflash if needed */
+ img_addr = genimg_get_image(img_addr);
+
+ /* check image type, for FIT images get FIT kernel node */
+ *os_data = *os_len = 0;
+ buf = map_sysmem(img_addr, 0);
+ switch (genimg_get_format(buf)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+ case IMAGE_FORMAT_LEGACY:
+ printf("## Booting kernel from Legacy Image at %08lx ...\n",
+ img_addr);
+ hdr = image_get_kernel(img_addr, images->verify);
+ if (!hdr)
+ return NULL;
+ bootstage_mark(BOOTSTAGE_ID_CHECK_IMAGETYPE);
+
+ /* get os_data and os_len */
+ switch (image_get_type(hdr)) {
+ case IH_TYPE_KERNEL:
+ case IH_TYPE_KERNEL_NOLOAD:
+ *os_data = image_get_data(hdr);
+ *os_len = image_get_data_size(hdr);
+ break;
+ case IH_TYPE_MULTI:
+ image_multi_getimg(hdr, 0, os_data, os_len);
+ break;
+ case IH_TYPE_STANDALONE:
+ *os_data = image_get_data(hdr);
+ *os_len = image_get_data_size(hdr);
+ break;
+ default:
+ printf("Wrong Image Type for %s command\n",
+ cmdtp->name);
+ bootstage_error(BOOTSTAGE_ID_CHECK_IMAGETYPE);
+ return NULL;
+ }
+
+ /*
+ * copy image header to allow for image overwrites during
+ * kernel decompression.
+ */
+ memmove(&images->legacy_hdr_os_copy, hdr,
+ sizeof(image_header_t));
+
+ /* save pointer to image header */
+ images->legacy_hdr_os = hdr;
+
+ images->legacy_hdr_valid = 1;
+ bootstage_mark(BOOTSTAGE_ID_DECOMP_IMAGE);
+ break;
+#endif
+#if defined(CONFIG_FIT)
+ case IMAGE_FORMAT_FIT:
+ os_noffset = fit_image_load(images, img_addr,
+ &fit_uname_kernel, &fit_uname_config,
+ IH_ARCH_DEFAULT, IH_TYPE_KERNEL,
+ BOOTSTAGE_ID_FIT_KERNEL_START,
+ FIT_LOAD_IGNORED, os_data, os_len);
+ if (os_noffset < 0)
+ return NULL;
+
+ images->fit_hdr_os = map_sysmem(img_addr, 0);
+ images->fit_uname_os = fit_uname_kernel;
+ images->fit_uname_cfg = fit_uname_config;
+ images->fit_noffset_os = os_noffset;
+ break;
+#endif
+#ifdef CONFIG_ANDROID_BOOT_IMAGE
+ case IMAGE_FORMAT_ANDROID:
+ printf("## Booting Android Image at 0x%08lx ...\n", img_addr);
+ if (android_image_get_kernel(buf, images->verify,
+ os_data, os_len))
+ return NULL;
+ break;
+#endif
+ default:
+ printf("Wrong Image Format for %s command\n", cmdtp->name);
+ bootstage_error(BOOTSTAGE_ID_FIT_KERNEL_INFO);
+ return NULL;
+ }
+
+ debug(" kernel data at 0x%08lx, len = 0x%08lx (%ld)\n",
+ *os_data, *os_len, *os_len);
+
+ return buf;
+}
+#else /* USE_HOSTCC */
+
+void memmove_wd(void *to, void *from, size_t len, ulong chunksz)
+{
+ memmove(to, from, len);
+}
+
+static int bootm_host_load_image(const void *fit, int req_image_type)
+{
+ const char *fit_uname_config = NULL;
+ ulong data, len;
+ bootm_headers_t images;
+ int noffset;
+ ulong load_end;
+ uint8_t image_type;
+ uint8_t imape_comp;
+ void *load_buf;
+ int ret;
+
+ memset(&images, '\0', sizeof(images));
+ images.verify = 1;
+ noffset = fit_image_load(&images, (ulong)fit,
+ NULL, &fit_uname_config,
+ IH_ARCH_DEFAULT, req_image_type, -1,
+ FIT_LOAD_IGNORED, &data, &len);
+ if (noffset < 0)
+ return noffset;
+ if (fit_image_get_type(fit, noffset, &image_type)) {
+ puts("Can't get image type!\n");
+ return -EINVAL;
+ }
+
+ if (fit_image_get_comp(fit, noffset, &imape_comp)) {
+ puts("Can't get image compression!\n");
+ return -EINVAL;
+ }
+
+ /* Allow the image to expand by a factor of 4, should be safe */
+ load_buf = malloc((1 << 20) + len * 4);
+ ret = decomp_image(imape_comp, 0, data, image_type, load_buf,
+ (void *)data, len, &load_end);
+ free(load_buf);
+ if (ret && ret != BOOTM_ERR_UNIMPLEMENTED)
+ return ret;
+
+ return 0;
+}
+
+int bootm_host_load_images(const void *fit, int cfg_noffset)
+{
+ static uint8_t image_types[] = {
+ IH_TYPE_KERNEL,
+ IH_TYPE_FLATDT,
+ IH_TYPE_RAMDISK,
+ };
+ int err = 0;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(image_types); i++) {
+ int ret;
+
+ ret = bootm_host_load_image(fit, image_types[i]);
+ if (!err && ret && ret != -ENOENT)
+ err = ret;
+ }
+
+ /* Return the first error we found */
+ return err;
+}
+
+#endif /* ndef USE_HOSTCC */
--- /dev/null
+/*
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <bootm.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <malloc.h>
+#include <vxworks.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int do_bootm_standalone(int flag, int argc, char * const argv[],
+ bootm_headers_t *images)
+{
+ char *s;
+ int (*appl)(int, char *const[]);
+
+ /* Don't start if "autostart" is set to "no" */
+ s = getenv("autostart");
+ if ((s != NULL) && !strcmp(s, "no")) {
+ setenv_hex("filesize", images->os.image_len);
+ return 0;
+ }
+ appl = (int (*)(int, char * const []))images->ep;
+ appl(argc, argv);
+ return 0;
+}
+
+/*******************************************************************/
+/* OS booting routines */
+/*******************************************************************/
+
+#if defined(CONFIG_BOOTM_NETBSD) || defined(CONFIG_BOOTM_PLAN9)
+static void copy_args(char *dest, int argc, char * const argv[], char delim)
+{
+ int i;
+
+ for (i = 0; i < argc; i++) {
+ if (i > 0)
+ *dest++ = delim;
+ strcpy(dest, argv[i]);
+ dest += strlen(argv[i]);
+ }
+}
+#endif
+
+#ifdef CONFIG_BOOTM_NETBSD
+static int do_bootm_netbsd(int flag, int argc, char * const argv[],
+ bootm_headers_t *images)
+{
+ void (*loader)(bd_t *, image_header_t *, char *, char *);
+ image_header_t *os_hdr, *hdr;
+ ulong kernel_data, kernel_len;
+ char *consdev;
+ char *cmdline;
+
+ if (flag != BOOTM_STATE_OS_GO)
+ return 0;
+
+#if defined(CONFIG_FIT)
+ if (!images->legacy_hdr_valid) {
+ fit_unsupported_reset("NetBSD");
+ return 1;
+ }
+#endif
+ hdr = images->legacy_hdr_os;
+
+ /*
+ * Booting a (NetBSD) kernel image
+ *
+ * This process is pretty similar to a standalone application:
+ * The (first part of an multi-) image must be a stage-2 loader,
+ * which in turn is responsible for loading & invoking the actual
+ * kernel. The only differences are the parameters being passed:
+ * besides the board info strucure, the loader expects a command
+ * line, the name of the console device, and (optionally) the
+ * address of the original image header.
+ */
+ os_hdr = NULL;
+ if (image_check_type(&images->legacy_hdr_os_copy, IH_TYPE_MULTI)) {
+ image_multi_getimg(hdr, 1, &kernel_data, &kernel_len);
+ if (kernel_len)
+ os_hdr = hdr;
+ }
+
+ consdev = "";
+#if defined(CONFIG_8xx_CONS_SMC1)
+ consdev = "smc1";
+#elif defined(CONFIG_8xx_CONS_SMC2)
+ consdev = "smc2";
+#elif defined(CONFIG_8xx_CONS_SCC2)
+ consdev = "scc2";
+#elif defined(CONFIG_8xx_CONS_SCC3)
+ consdev = "scc3";
+#endif
+
+ if (argc > 0) {
+ ulong len;
+ int i;
+
+ for (i = 0, len = 0; i < argc; i += 1)
+ len += strlen(argv[i]) + 1;
+ cmdline = malloc(len);
+ copy_args(cmdline, argc, argv, ' ');
+ } else {
+ cmdline = getenv("bootargs");
+ if (cmdline == NULL)
+ cmdline = "";
+ }
+
+ loader = (void (*)(bd_t *, image_header_t *, char *, char *))images->ep;
+
+ printf("## Transferring control to NetBSD stage-2 loader (at address %08lx) ...\n",
+ (ulong)loader);
+
+ bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+
+ /*
+ * NetBSD Stage-2 Loader Parameters:
+ * arg[0]: pointer to board info data
+ * arg[1]: image load address
+ * arg[2]: char pointer to the console device to use
+ * arg[3]: char pointer to the boot arguments
+ */
+ (*loader)(gd->bd, os_hdr, consdev, cmdline);
+
+ return 1;
+}
+#endif /* CONFIG_BOOTM_NETBSD*/
+
+#ifdef CONFIG_LYNXKDI
+static int do_bootm_lynxkdi(int flag, int argc, char * const argv[],
+ bootm_headers_t *images)
+{
+ image_header_t *hdr = &images->legacy_hdr_os_copy;
+
+ if (flag != BOOTM_STATE_OS_GO)
+ return 0;
+
+#if defined(CONFIG_FIT)
+ if (!images->legacy_hdr_valid) {
+ fit_unsupported_reset("Lynx");
+ return 1;
+ }
+#endif
+
+ lynxkdi_boot((image_header_t *)hdr);
+
+ return 1;
+}
+#endif /* CONFIG_LYNXKDI */
+
+#ifdef CONFIG_BOOTM_RTEMS
+static int do_bootm_rtems(int flag, int argc, char * const argv[],
+ bootm_headers_t *images)
+{
+ void (*entry_point)(bd_t *);
+
+ if (flag != BOOTM_STATE_OS_GO)
+ return 0;
+
+#if defined(CONFIG_FIT)
+ if (!images->legacy_hdr_valid) {
+ fit_unsupported_reset("RTEMS");
+ return 1;
+ }
+#endif
+
+ entry_point = (void (*)(bd_t *))images->ep;
+
+ printf("## Transferring control to RTEMS (at address %08lx) ...\n",
+ (ulong)entry_point);
+
+ bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+
+ /*
+ * RTEMS Parameters:
+ * r3: ptr to board info data
+ */
+ (*entry_point)(gd->bd);
+
+ return 1;
+}
+#endif /* CONFIG_BOOTM_RTEMS */
+
+#if defined(CONFIG_BOOTM_OSE)
+static int do_bootm_ose(int flag, int argc, char * const argv[],
+ bootm_headers_t *images)
+{
+ void (*entry_point)(void);
+
+ if (flag != BOOTM_STATE_OS_GO)
+ return 0;
+
+#if defined(CONFIG_FIT)
+ if (!images->legacy_hdr_valid) {
+ fit_unsupported_reset("OSE");
+ return 1;
+ }
+#endif
+
+ entry_point = (void (*)(void))images->ep;
+
+ printf("## Transferring control to OSE (at address %08lx) ...\n",
+ (ulong)entry_point);
+
+ bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+
+ /*
+ * OSE Parameters:
+ * None
+ */
+ (*entry_point)();
+
+ return 1;
+}
+#endif /* CONFIG_BOOTM_OSE */
+
+#if defined(CONFIG_BOOTM_PLAN9)
+static int do_bootm_plan9(int flag, int argc, char * const argv[],
+ bootm_headers_t *images)
+{
+ void (*entry_point)(void);
+ char *s;
+
+ if (flag != BOOTM_STATE_OS_GO)
+ return 0;
+
+#if defined(CONFIG_FIT)
+ if (!images->legacy_hdr_valid) {
+ fit_unsupported_reset("Plan 9");
+ return 1;
+ }
+#endif
+
+ /* See README.plan9 */
+ s = getenv("confaddr");
+ if (s != NULL) {
+ char *confaddr = (char *)simple_strtoul(s, NULL, 16);
+
+ if (argc > 0) {
+ copy_args(confaddr, argc, argv, '\n');
+ } else {
+ s = getenv("bootargs");
+ if (s != NULL)
+ strcpy(confaddr, s);
+ }
+ }
+
+ entry_point = (void (*)(void))images->ep;
+
+ printf("## Transferring control to Plan 9 (at address %08lx) ...\n",
+ (ulong)entry_point);
+
+ bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+
+ /*
+ * Plan 9 Parameters:
+ * None
+ */
+ (*entry_point)();
+
+ return 1;
+}
+#endif /* CONFIG_BOOTM_PLAN9 */
+
+#if defined(CONFIG_BOOTM_VXWORKS) && \
+ (defined(CONFIG_PPC) || defined(CONFIG_ARM))
+
+void do_bootvx_fdt(bootm_headers_t *images)
+{
+#if defined(CONFIG_OF_LIBFDT)
+ int ret;
+ char *bootline;
+ ulong of_size = images->ft_len;
+ char **of_flat_tree = &images->ft_addr;
+ struct lmb *lmb = &images->lmb;
+
+ if (*of_flat_tree) {
+ boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree);
+
+ ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size);
+ if (ret)
+ return;
+
+ ret = fdt_add_subnode(*of_flat_tree, 0, "chosen");
+ if ((ret >= 0 || ret == -FDT_ERR_EXISTS)) {
+ bootline = getenv("bootargs");
+ if (bootline) {
+ ret = fdt_find_and_setprop(*of_flat_tree,
+ "/chosen", "bootargs",
+ bootline,
+ strlen(bootline) + 1, 1);
+ if (ret < 0) {
+ printf("## ERROR: %s : %s\n", __func__,
+ fdt_strerror(ret));
+ return;
+ }
+ }
+ } else {
+ printf("## ERROR: %s : %s\n", __func__,
+ fdt_strerror(ret));
+ return;
+ }
+ }
+#endif
+
+ boot_prep_vxworks(images);
+
+ bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+
+#if defined(CONFIG_OF_LIBFDT)
+ printf("## Starting vxWorks at 0x%08lx, device tree at 0x%08lx ...\n",
+ (ulong)images->ep, (ulong)*of_flat_tree);
+#else
+ printf("## Starting vxWorks at 0x%08lx\n", (ulong)images->ep);
+#endif
+
+ boot_jump_vxworks(images);
+
+ puts("## vxWorks terminated\n");
+}
+
+static int do_bootm_vxworks(int flag, int argc, char * const argv[],
+ bootm_headers_t *images)
+{
+ if (flag != BOOTM_STATE_OS_GO)
+ return 0;
+
+#if defined(CONFIG_FIT)
+ if (!images->legacy_hdr_valid) {
+ fit_unsupported_reset("VxWorks");
+ return 1;
+ }
+#endif
+
+ do_bootvx_fdt(images);
+
+ return 1;
+}
+#endif
+
+#if defined(CONFIG_CMD_ELF)
+static int do_bootm_qnxelf(int flag, int argc, char * const argv[],
+ bootm_headers_t *images)
+{
+ char *local_args[2];
+ char str[16];
+
+ if (flag != BOOTM_STATE_OS_GO)
+ return 0;
+
+#if defined(CONFIG_FIT)
+ if (!images->legacy_hdr_valid) {
+ fit_unsupported_reset("QNX");
+ return 1;
+ }
+#endif
+
+ sprintf(str, "%lx", images->ep); /* write entry-point into string */
+ local_args[0] = argv[0];
+ local_args[1] = str; /* and provide it via the arguments */
+ do_bootelf(NULL, 0, 2, local_args);
+
+ return 1;
+}
+#endif
+
+#ifdef CONFIG_INTEGRITY
+static int do_bootm_integrity(int flag, int argc, char * const argv[],
+ bootm_headers_t *images)
+{
+ void (*entry_point)(void);
+
+ if (flag != BOOTM_STATE_OS_GO)
+ return 0;
+
+#if defined(CONFIG_FIT)
+ if (!images->legacy_hdr_valid) {
+ fit_unsupported_reset("INTEGRITY");
+ return 1;
+ }
+#endif
+
+ entry_point = (void (*)(void))images->ep;
+
+ printf("## Transferring control to INTEGRITY (at address %08lx) ...\n",
+ (ulong)entry_point);
+
+ bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+
+ /*
+ * INTEGRITY Parameters:
+ * None
+ */
+ (*entry_point)();
+
+ return 1;
+}
+#endif
+
+static boot_os_fn *boot_os[] = {
+ [IH_OS_U_BOOT] = do_bootm_standalone,
+#ifdef CONFIG_BOOTM_LINUX
+ [IH_OS_LINUX] = do_bootm_linux,
+#endif
+#ifdef CONFIG_BOOTM_NETBSD
+ [IH_OS_NETBSD] = do_bootm_netbsd,
+#endif
+#ifdef CONFIG_LYNXKDI
+ [IH_OS_LYNXOS] = do_bootm_lynxkdi,
+#endif
+#ifdef CONFIG_BOOTM_RTEMS
+ [IH_OS_RTEMS] = do_bootm_rtems,
+#endif
+#if defined(CONFIG_BOOTM_OSE)
+ [IH_OS_OSE] = do_bootm_ose,
+#endif
+#if defined(CONFIG_BOOTM_PLAN9)
+ [IH_OS_PLAN9] = do_bootm_plan9,
+#endif
+#if defined(CONFIG_BOOTM_VXWORKS) && \
+ (defined(CONFIG_PPC) || defined(CONFIG_ARM))
+ [IH_OS_VXWORKS] = do_bootm_vxworks,
+#endif
+#if defined(CONFIG_CMD_ELF)
+ [IH_OS_QNX] = do_bootm_qnxelf,
+#endif
+#ifdef CONFIG_INTEGRITY
+ [IH_OS_INTEGRITY] = do_bootm_integrity,
+#endif
+};
+
+/* Allow for arch specific config before we boot */
+static void __arch_preboot_os(void)
+{
+ /* please define platform specific arch_preboot_os() */
+}
+void arch_preboot_os(void) __attribute__((weak, alias("__arch_preboot_os")));
+
+int boot_selected_os(int argc, char * const argv[], int state,
+ bootm_headers_t *images, boot_os_fn *boot_fn)
+{
+ arch_preboot_os();
+ boot_fn(state, argc, argv, images);
+
+ /* Stand-alone may return when 'autostart' is 'no' */
+ if (images->os.type == IH_TYPE_STANDALONE ||
+ state == BOOTM_STATE_OS_FAKE_GO) /* We expect to return */
+ return 0;
+ bootstage_error(BOOTSTAGE_ID_BOOT_OS_RETURNED);
+#ifdef DEBUG
+ puts("\n## Control returned to monitor - resetting...\n");
+#endif
+ return BOOTM_ERR_RESET;
+}
+
+boot_os_fn *bootm_os_get_boot_func(int os)
+{
+#ifdef CONFIG_NEEDS_MANUAL_RELOC
+ static bool relocated;
+
+ if (!relocated) {
+ int i;
+
+ /* relocate boot function table */
+ for (i = 0; i < ARRAY_SIZE(boot_os); i++)
+ if (boot_os[i] != NULL)
+ boot_os[i] += gd->reloc_off;
+
+ relocated = true;
+ }
+#endif
+ return boot_os[os];
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <bootretry.h>
+#include <cli.h>
+#include <errno.h>
+#include <watchdog.h>
+
+#ifndef CONFIG_BOOT_RETRY_MIN
+#define CONFIG_BOOT_RETRY_MIN CONFIG_BOOT_RETRY_TIME
+#endif
+
+static uint64_t endtime; /* must be set, default is instant timeout */
+static int retry_time = -1; /* -1 so can call readline before main_loop */
+
+/***************************************************************************
+ * initialize command line timeout
+ */
+void bootretry_init_cmd_timeout(void)
+{
+ char *s = getenv("bootretry");
+
+ if (s != NULL)
+ retry_time = (int)simple_strtol(s, NULL, 10);
+ else
+ retry_time = CONFIG_BOOT_RETRY_TIME;
+
+ if (retry_time >= 0 && retry_time < CONFIG_BOOT_RETRY_MIN)
+ retry_time = CONFIG_BOOT_RETRY_MIN;
+}
+
+/***************************************************************************
+ * reset command line timeout to retry_time seconds
+ */
+void bootretry_reset_cmd_timeout(void)
+{
+ endtime = endtick(retry_time);
+}
+
+int bootretry_tstc_timeout(void)
+{
+ while (!tstc()) { /* while no incoming data */
+ if (retry_time >= 0 && get_ticks() > endtime)
+ return -ETIMEDOUT;
+ WATCHDOG_RESET();
+ }
+
+ return 0;
+}
+
+void bootretry_dont_retry(void)
+{
+ retry_time = -1;
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Add to readline cmdline-editing by
+ * (C) Copyright 2005
+ * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <cli.h>
+#include <cli_hush.h>
+#include <fdtdec.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Run a command using the selected parser.
+ *
+ * @param cmd Command to run
+ * @param flag Execution flags (CMD_FLAG_...)
+ * @return 0 on success, or != 0 on error.
+ */
+int run_command(const char *cmd, int flag)
+{
+#ifndef CONFIG_SYS_HUSH_PARSER
+ /*
+ * cli_run_command can return 0 or 1 for success, so clean up
+ * its result.
+ */
+ if (cli_simple_run_command(cmd, flag) == -1)
+ return 1;
+
+ return 0;
+#else
+ return parse_string_outer(cmd,
+ FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP);
+#endif
+}
+
+/*
+ * Run a command using the selected parser, and check if it is repeatable.
+ *
+ * @param cmd Command to run
+ * @param flag Execution flags (CMD_FLAG_...)
+ * @return 0 (not repeatable) or 1 (repeatable) on success, -1 on error.
+ */
+int run_command_repeatable(const char *cmd, int flag)
+{
+#ifndef CONFIG_SYS_HUSH_PARSER
+ return cli_simple_run_command(cmd, flag);
+#else
+ /*
+ * parse_string_outer() returns 1 for failure, so clean up
+ * its result.
+ */
+ if (parse_string_outer(cmd,
+ FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP))
+ return -1;
+
+ return 0;
+#endif
+}
+
+int run_command_list(const char *cmd, int len, int flag)
+{
+ int need_buff = 1;
+ char *buff = (char *)cmd; /* cast away const */
+ int rcode = 0;
+
+ if (len == -1) {
+ len = strlen(cmd);
+#ifdef CONFIG_SYS_HUSH_PARSER
+ /* hush will never change our string */
+ need_buff = 0;
+#else
+ /* the built-in parser will change our string if it sees \n */
+ need_buff = strchr(cmd, '\n') != NULL;
+#endif
+ }
+ if (need_buff) {
+ buff = malloc(len + 1);
+ if (!buff)
+ return 1;
+ memcpy(buff, cmd, len);
+ buff[len] = '\0';
+ }
+#ifdef CONFIG_SYS_HUSH_PARSER
+ rcode = parse_string_outer(buff, FLAG_PARSE_SEMICOLON);
+#else
+ /*
+ * This function will overwrite any \n it sees with a \0, which
+ * is why it can't work with a const char *. Here we are making
+ * using of internal knowledge of this function, to avoid always
+ * doing a malloc() which is actually required only in a case that
+ * is pretty rare.
+ */
+ rcode = cli_simple_run_command_list(buff, flag);
+ if (need_buff)
+ free(buff);
+#endif
+
+ return rcode;
+}
+
+/****************************************************************************/
+
+#if defined(CONFIG_CMD_RUN)
+int do_run(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int i;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ for (i = 1; i < argc; ++i) {
+ char *arg;
+
+ arg = getenv(argv[i]);
+ if (arg == NULL) {
+ printf("## Error: \"%s\" not defined\n", argv[i]);
+ return 1;
+ }
+
+ if (run_command(arg, flag) != 0)
+ return 1;
+ }
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_OF_CONTROL
+bool cli_process_fdt(const char **cmdp)
+{
+ /* Allow the fdt to override the boot command */
+ char *env = fdtdec_get_config_string(gd->fdt_blob, "bootcmd");
+ if (env)
+ *cmdp = env;
+ /*
+ * If the bootsecure option was chosen, use secure_boot_cmd().
+ * Always use 'env' in this case, since bootsecure requres that the
+ * bootcmd was specified in the FDT too.
+ */
+ return fdtdec_get_config_int(gd->fdt_blob, "bootsecure", 0) != 0;
+}
+
+/*
+ * Runs the given boot command securely. Specifically:
+ * - Doesn't run the command with the shell (run_command or parse_string_outer),
+ * since that's a lot of code surface that an attacker might exploit.
+ * Because of this, we don't do any argument parsing--the secure boot command
+ * has to be a full-fledged u-boot command.
+ * - Doesn't check for keypresses before booting, since that could be a
+ * security hole; also disables Ctrl-C.
+ * - Doesn't allow the command to return.
+ *
+ * Upon any failures, this function will drop into an infinite loop after
+ * printing the error message to console.
+ */
+void cli_secure_boot_cmd(const char *cmd)
+{
+ cmd_tbl_t *cmdtp;
+ int rc;
+
+ if (!cmd) {
+ printf("## Error: Secure boot command not specified\n");
+ goto err;
+ }
+
+ /* Disable Ctrl-C just in case some command is used that checks it. */
+ disable_ctrlc(1);
+
+ /* Find the command directly. */
+ cmdtp = find_cmd(cmd);
+ if (!cmdtp) {
+ printf("## Error: \"%s\" not defined\n", cmd);
+ goto err;
+ }
+
+ /* Run the command, forcing no flags and faking argc and argv. */
+ rc = (cmdtp->cmd)(cmdtp, 0, 1, (char **)&cmd);
+
+ /* Shouldn't ever return from boot command. */
+ printf("## Error: \"%s\" returned (code %d)\n", cmd, rc);
+
+err:
+ /*
+ * Not a whole lot to do here. Rebooting won't help much, since we'll
+ * just end up right back here. Just loop.
+ */
+ hang();
+}
+#endif /* CONFIG_OF_CONTROL */
+
+void cli_loop(void)
+{
+#ifdef CONFIG_SYS_HUSH_PARSER
+ parse_file_outer();
+ /* This point is never reached */
+ for (;;);
+#else
+ cli_simple_loop();
+#endif /*CONFIG_SYS_HUSH_PARSER*/
+}
+
+void cli_init(void)
+{
+#ifdef CONFIG_SYS_HUSH_PARSER
+ u_boot_hush_start();
+#endif
+
+#if defined(CONFIG_HUSH_INIT_VAR)
+ hush_init_var();
+#endif
+}
#include <malloc.h> /* malloc, free, realloc*/
#include <linux/ctype.h> /* isalpha, isdigit */
#include <common.h> /* readline */
-#include <hush.h>
+#include <bootretry.h>
+#include <cli.h>
+#include <cli_hush.h>
#include <command.h> /* find_cmd */
#ifndef CONFIG_SYS_PROMPT_HUSH_PS2
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif
char **argv; /* program name and arguments */
/* was quoted when parsed; copy of struct o_string.nonnull field */
- int *argv_nonnull;
+ int *argv_nonnull;
#ifdef __U_BOOT__
int argc; /* number of program arguments */
#endif
int n;
static char the_command[CONFIG_SYS_CBSIZE + 1];
-#ifdef CONFIG_BOOT_RETRY_TIME
-# ifndef CONFIG_RESET_TO_RETRY
-# error "This currently only works with CONFIG_RESET_TO_RETRY enabled"
-# endif
- reset_cmd_timeout();
-#endif
+ bootretry_reset_cmd_timeout();
i->__promptme = 1;
if (i->promptmode == 1) {
- n = readline(CONFIG_SYS_PROMPT);
+ n = cli_readline(CONFIG_SYS_PROMPT);
} else {
- n = readline(CONFIG_SYS_PROMPT_HUSH_PS2);
+ n = cli_readline(CONFIG_SYS_PROMPT_HUSH_PS2);
}
#ifdef CONFIG_BOOT_RETRY_TIME
if (n == -2) {
if (rmode == RES_DO) {
if (!flag_rep) continue;
}
- if ((rmode == RES_DONE)) {
+ if (rmode == RES_DONE) {
if (flag_rep) {
flag_restore = 1;
} else {
free_pipe_list(ctx.list_head,0);
}
b_free(&temp);
- } while (rcode != -1 && !(flag & FLAG_EXIT_FROM_LOOP)); /* loop on syntax errors, return on EOF */
+ /* loop on syntax errors, return on EOF */
+ } while (rcode != -1 && !(flag & FLAG_EXIT_FROM_LOOP) &&
+ (inp->peek != static_peek || b_peek(inp)));
#ifndef __U_BOOT__
return 0;
#else
p3 = insert_var_value(inp[i]);
p1 = p3;
while (*p1) {
- if ((*p1 == ' ')) {
+ if (*p1 == ' ') {
p1++;
continue;
}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Add to readline cmdline-editing by
+ * (C) Copyright 2005
+ * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <bootretry.h>
+#include <cli.h>
+#include <watchdog.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const char erase_seq[] = "\b \b"; /* erase sequence */
+static const char tab_seq[] = " "; /* used to expand TABs */
+
+char console_buffer[CONFIG_SYS_CBSIZE + 1]; /* console I/O buffer */
+
+static char *delete_char (char *buffer, char *p, int *colp, int *np, int plen)
+{
+ char *s;
+
+ if (*np == 0)
+ return p;
+
+ if (*(--p) == '\t') { /* will retype the whole line */
+ while (*colp > plen) {
+ puts(erase_seq);
+ (*colp)--;
+ }
+ for (s = buffer; s < p; ++s) {
+ if (*s == '\t') {
+ puts(tab_seq + ((*colp) & 07));
+ *colp += 8 - ((*colp) & 07);
+ } else {
+ ++(*colp);
+ putc(*s);
+ }
+ }
+ } else {
+ puts(erase_seq);
+ (*colp)--;
+ }
+ (*np)--;
+
+ return p;
+}
+
+#ifdef CONFIG_CMDLINE_EDITING
+
+/*
+ * cmdline-editing related codes from vivi.
+ * Author: Janghoon Lyu <nandy@mizi.com>
+ */
+
+#define putnstr(str, n) printf("%.*s", (int)n, str)
+
+#define CTL_CH(c) ((c) - 'a' + 1)
+#define CTL_BACKSPACE ('\b')
+#define DEL ((char)255)
+#define DEL7 ((char)127)
+#define CREAD_HIST_CHAR ('!')
+
+#define getcmd_putch(ch) putc(ch)
+#define getcmd_getch() getc()
+#define getcmd_cbeep() getcmd_putch('\a')
+
+#define HIST_MAX 20
+#define HIST_SIZE CONFIG_SYS_CBSIZE
+
+static int hist_max;
+static int hist_add_idx;
+static int hist_cur = -1;
+static unsigned hist_num;
+
+static char *hist_list[HIST_MAX];
+static char hist_lines[HIST_MAX][HIST_SIZE + 1]; /* Save room for NULL */
+
+#define add_idx_minus_one() ((hist_add_idx == 0) ? hist_max : hist_add_idx-1)
+
+static void hist_init(void)
+{
+ int i;
+
+ hist_max = 0;
+ hist_add_idx = 0;
+ hist_cur = -1;
+ hist_num = 0;
+
+ for (i = 0; i < HIST_MAX; i++) {
+ hist_list[i] = hist_lines[i];
+ hist_list[i][0] = '\0';
+ }
+}
+
+static void cread_add_to_hist(char *line)
+{
+ strcpy(hist_list[hist_add_idx], line);
+
+ if (++hist_add_idx >= HIST_MAX)
+ hist_add_idx = 0;
+
+ if (hist_add_idx > hist_max)
+ hist_max = hist_add_idx;
+
+ hist_num++;
+}
+
+static char *hist_prev(void)
+{
+ char *ret;
+ int old_cur;
+
+ if (hist_cur < 0)
+ return NULL;
+
+ old_cur = hist_cur;
+ if (--hist_cur < 0)
+ hist_cur = hist_max;
+
+ if (hist_cur == hist_add_idx) {
+ hist_cur = old_cur;
+ ret = NULL;
+ } else {
+ ret = hist_list[hist_cur];
+ }
+
+ return ret;
+}
+
+static char *hist_next(void)
+{
+ char *ret;
+
+ if (hist_cur < 0)
+ return NULL;
+
+ if (hist_cur == hist_add_idx)
+ return NULL;
+
+ if (++hist_cur > hist_max)
+ hist_cur = 0;
+
+ if (hist_cur == hist_add_idx)
+ ret = "";
+ else
+ ret = hist_list[hist_cur];
+
+ return ret;
+}
+
+#ifndef CONFIG_CMDLINE_EDITING
+static void cread_print_hist_list(void)
+{
+ int i;
+ unsigned long n;
+
+ n = hist_num - hist_max;
+
+ i = hist_add_idx + 1;
+ while (1) {
+ if (i > hist_max)
+ i = 0;
+ if (i == hist_add_idx)
+ break;
+ printf("%s\n", hist_list[i]);
+ n++;
+ i++;
+ }
+}
+#endif /* CONFIG_CMDLINE_EDITING */
+
+#define BEGINNING_OF_LINE() { \
+ while (num) { \
+ getcmd_putch(CTL_BACKSPACE); \
+ num--; \
+ } \
+}
+
+#define ERASE_TO_EOL() { \
+ if (num < eol_num) { \
+ printf("%*s", (int)(eol_num - num), ""); \
+ do { \
+ getcmd_putch(CTL_BACKSPACE); \
+ } while (--eol_num > num); \
+ } \
+}
+
+#define REFRESH_TO_EOL() { \
+ if (num < eol_num) { \
+ wlen = eol_num - num; \
+ putnstr(buf + num, wlen); \
+ num = eol_num; \
+ } \
+}
+
+static void cread_add_char(char ichar, int insert, unsigned long *num,
+ unsigned long *eol_num, char *buf, unsigned long len)
+{
+ unsigned long wlen;
+
+ /* room ??? */
+ if (insert || *num == *eol_num) {
+ if (*eol_num > len - 1) {
+ getcmd_cbeep();
+ return;
+ }
+ (*eol_num)++;
+ }
+
+ if (insert) {
+ wlen = *eol_num - *num;
+ if (wlen > 1)
+ memmove(&buf[*num+1], &buf[*num], wlen-1);
+
+ buf[*num] = ichar;
+ putnstr(buf + *num, wlen);
+ (*num)++;
+ while (--wlen)
+ getcmd_putch(CTL_BACKSPACE);
+ } else {
+ /* echo the character */
+ wlen = 1;
+ buf[*num] = ichar;
+ putnstr(buf + *num, wlen);
+ (*num)++;
+ }
+}
+
+static void cread_add_str(char *str, int strsize, int insert,
+ unsigned long *num, unsigned long *eol_num,
+ char *buf, unsigned long len)
+{
+ while (strsize--) {
+ cread_add_char(*str, insert, num, eol_num, buf, len);
+ str++;
+ }
+}
+
+static int cread_line(const char *const prompt, char *buf, unsigned int *len,
+ int timeout)
+{
+ unsigned long num = 0;
+ unsigned long eol_num = 0;
+ unsigned long wlen;
+ char ichar;
+ int insert = 1;
+ int esc_len = 0;
+ char esc_save[8];
+ int init_len = strlen(buf);
+ int first = 1;
+
+ if (init_len)
+ cread_add_str(buf, init_len, 1, &num, &eol_num, buf, *len);
+
+ while (1) {
+ if (bootretry_tstc_timeout())
+ return -2; /* timed out */
+ if (first && timeout) {
+ uint64_t etime = endtick(timeout);
+
+ while (!tstc()) { /* while no incoming data */
+ if (get_ticks() >= etime)
+ return -2; /* timed out */
+ WATCHDOG_RESET();
+ }
+ first = 0;
+ }
+
+ ichar = getcmd_getch();
+
+ if ((ichar == '\n') || (ichar == '\r')) {
+ putc('\n');
+ break;
+ }
+
+ /*
+ * handle standard linux xterm esc sequences for arrow key, etc.
+ */
+ if (esc_len != 0) {
+ if (esc_len == 1) {
+ if (ichar == '[') {
+ esc_save[esc_len] = ichar;
+ esc_len = 2;
+ } else {
+ cread_add_str(esc_save, esc_len,
+ insert, &num, &eol_num,
+ buf, *len);
+ esc_len = 0;
+ }
+ continue;
+ }
+
+ switch (ichar) {
+ case 'D': /* <- key */
+ ichar = CTL_CH('b');
+ esc_len = 0;
+ break;
+ case 'C': /* -> key */
+ ichar = CTL_CH('f');
+ esc_len = 0;
+ break; /* pass off to ^F handler */
+ case 'H': /* Home key */
+ ichar = CTL_CH('a');
+ esc_len = 0;
+ break; /* pass off to ^A handler */
+ case 'A': /* up arrow */
+ ichar = CTL_CH('p');
+ esc_len = 0;
+ break; /* pass off to ^P handler */
+ case 'B': /* down arrow */
+ ichar = CTL_CH('n');
+ esc_len = 0;
+ break; /* pass off to ^N handler */
+ default:
+ esc_save[esc_len++] = ichar;
+ cread_add_str(esc_save, esc_len, insert,
+ &num, &eol_num, buf, *len);
+ esc_len = 0;
+ continue;
+ }
+ }
+
+ switch (ichar) {
+ case 0x1b:
+ if (esc_len == 0) {
+ esc_save[esc_len] = ichar;
+ esc_len = 1;
+ } else {
+ puts("impossible condition #876\n");
+ esc_len = 0;
+ }
+ break;
+
+ case CTL_CH('a'):
+ BEGINNING_OF_LINE();
+ break;
+ case CTL_CH('c'): /* ^C - break */
+ *buf = '\0'; /* discard input */
+ return -1;
+ case CTL_CH('f'):
+ if (num < eol_num) {
+ getcmd_putch(buf[num]);
+ num++;
+ }
+ break;
+ case CTL_CH('b'):
+ if (num) {
+ getcmd_putch(CTL_BACKSPACE);
+ num--;
+ }
+ break;
+ case CTL_CH('d'):
+ if (num < eol_num) {
+ wlen = eol_num - num - 1;
+ if (wlen) {
+ memmove(&buf[num], &buf[num+1], wlen);
+ putnstr(buf + num, wlen);
+ }
+
+ getcmd_putch(' ');
+ do {
+ getcmd_putch(CTL_BACKSPACE);
+ } while (wlen--);
+ eol_num--;
+ }
+ break;
+ case CTL_CH('k'):
+ ERASE_TO_EOL();
+ break;
+ case CTL_CH('e'):
+ REFRESH_TO_EOL();
+ break;
+ case CTL_CH('o'):
+ insert = !insert;
+ break;
+ case CTL_CH('x'):
+ case CTL_CH('u'):
+ BEGINNING_OF_LINE();
+ ERASE_TO_EOL();
+ break;
+ case DEL:
+ case DEL7:
+ case 8:
+ if (num) {
+ wlen = eol_num - num;
+ num--;
+ memmove(&buf[num], &buf[num+1], wlen);
+ getcmd_putch(CTL_BACKSPACE);
+ putnstr(buf + num, wlen);
+ getcmd_putch(' ');
+ do {
+ getcmd_putch(CTL_BACKSPACE);
+ } while (wlen--);
+ eol_num--;
+ }
+ break;
+ case CTL_CH('p'):
+ case CTL_CH('n'):
+ {
+ char *hline;
+
+ esc_len = 0;
+
+ if (ichar == CTL_CH('p'))
+ hline = hist_prev();
+ else
+ hline = hist_next();
+
+ if (!hline) {
+ getcmd_cbeep();
+ continue;
+ }
+
+ /* nuke the current line */
+ /* first, go home */
+ BEGINNING_OF_LINE();
+
+ /* erase to end of line */
+ ERASE_TO_EOL();
+
+ /* copy new line into place and display */
+ strcpy(buf, hline);
+ eol_num = strlen(buf);
+ REFRESH_TO_EOL();
+ continue;
+ }
+#ifdef CONFIG_AUTO_COMPLETE
+ case '\t': {
+ int num2, col;
+
+ /* do not autocomplete when in the middle */
+ if (num < eol_num) {
+ getcmd_cbeep();
+ break;
+ }
+
+ buf[num] = '\0';
+ col = strlen(prompt) + eol_num;
+ num2 = num;
+ if (cmd_auto_complete(prompt, buf, &num2, &col)) {
+ col = num2 - num;
+ num += col;
+ eol_num += col;
+ }
+ break;
+ }
+#endif
+ default:
+ cread_add_char(ichar, insert, &num, &eol_num, buf,
+ *len);
+ break;
+ }
+ }
+ *len = eol_num;
+ buf[eol_num] = '\0'; /* lose the newline */
+
+ if (buf[0] && buf[0] != CREAD_HIST_CHAR)
+ cread_add_to_hist(buf);
+ hist_cur = hist_add_idx;
+
+ return 0;
+}
+
+#endif /* CONFIG_CMDLINE_EDITING */
+
+/****************************************************************************/
+
+int cli_readline(const char *const prompt)
+{
+ /*
+ * If console_buffer isn't 0-length the user will be prompted to modify
+ * it instead of entering it from scratch as desired.
+ */
+ console_buffer[0] = '\0';
+
+ return cli_readline_into_buffer(prompt, console_buffer, 0);
+}
+
+
+int cli_readline_into_buffer(const char *const prompt, char *buffer,
+ int timeout)
+{
+ char *p = buffer;
+#ifdef CONFIG_CMDLINE_EDITING
+ unsigned int len = CONFIG_SYS_CBSIZE;
+ int rc;
+ static int initted;
+
+ /*
+ * History uses a global array which is not
+ * writable until after relocation to RAM.
+ * Revert to non-history version if still
+ * running from flash.
+ */
+ if (gd->flags & GD_FLG_RELOC) {
+ if (!initted) {
+ hist_init();
+ initted = 1;
+ }
+
+ if (prompt)
+ puts(prompt);
+
+ rc = cread_line(prompt, p, &len, timeout);
+ return rc < 0 ? rc : len;
+
+ } else {
+#endif /* CONFIG_CMDLINE_EDITING */
+ char *p_buf = p;
+ int n = 0; /* buffer index */
+ int plen = 0; /* prompt length */
+ int col; /* output column cnt */
+ char c;
+
+ /* print prompt */
+ if (prompt) {
+ plen = strlen(prompt);
+ puts(prompt);
+ }
+ col = plen;
+
+ for (;;) {
+ if (bootretry_tstc_timeout())
+ return -2; /* timed out */
+ WATCHDOG_RESET(); /* Trigger watchdog, if needed */
+
+#ifdef CONFIG_SHOW_ACTIVITY
+ while (!tstc()) {
+ show_activity(0);
+ WATCHDOG_RESET();
+ }
+#endif
+ c = getc();
+
+ /*
+ * Special character handling
+ */
+ switch (c) {
+ case '\r': /* Enter */
+ case '\n':
+ *p = '\0';
+ puts("\r\n");
+ return p - p_buf;
+
+ case '\0': /* nul */
+ continue;
+
+ case 0x03: /* ^C - break */
+ p_buf[0] = '\0'; /* discard input */
+ return -1;
+
+ case 0x15: /* ^U - erase line */
+ while (col > plen) {
+ puts(erase_seq);
+ --col;
+ }
+ p = p_buf;
+ n = 0;
+ continue;
+
+ case 0x17: /* ^W - erase word */
+ p = delete_char(p_buf, p, &col, &n, plen);
+ while ((n > 0) && (*p != ' '))
+ p = delete_char(p_buf, p, &col, &n, plen);
+ continue;
+
+ case 0x08: /* ^H - backspace */
+ case 0x7F: /* DEL - backspace */
+ p = delete_char(p_buf, p, &col, &n, plen);
+ continue;
+
+ default:
+ /*
+ * Must be a normal character then
+ */
+ if (n < CONFIG_SYS_CBSIZE-2) {
+ if (c == '\t') { /* expand TABs */
+#ifdef CONFIG_AUTO_COMPLETE
+ /*
+ * if auto completion triggered just
+ * continue
+ */
+ *p = '\0';
+ if (cmd_auto_complete(prompt,
+ console_buffer,
+ &n, &col)) {
+ p = p_buf + n; /* reset */
+ continue;
+ }
+#endif
+ puts(tab_seq + (col & 07));
+ col += 8 - (col & 07);
+ } else {
+ char buf[2];
+
+ /*
+ * Echo input using puts() to force an
+ * LCD flush if we are using an LCD
+ */
+ ++col;
+ buf[0] = c;
+ buf[1] = '\0';
+ puts(buf);
+ }
+ *p++ = c;
+ ++n;
+ } else { /* Buffer full */
+ putc('\a');
+ }
+ }
+ }
+#ifdef CONFIG_CMDLINE_EDITING
+ }
+#endif
+}
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Add to readline cmdline-editing by
+ * (C) Copyright 2005
+ * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <bootretry.h>
+#include <cli.h>
+#include <linux/ctype.h>
+
+#define DEBUG_PARSER 0 /* set to 1 to debug */
+
+#define debug_parser(fmt, args...) \
+ debug_cond(DEBUG_PARSER, fmt, ##args)
+
+
+int cli_simple_parse_line(char *line, char *argv[])
+{
+ int nargs = 0;
+
+ debug_parser("%s: \"%s\"\n", __func__, line);
+ while (nargs < CONFIG_SYS_MAXARGS) {
+ /* skip any white space */
+ while (isblank(*line))
+ ++line;
+
+ if (*line == '\0') { /* end of line, no more args */
+ argv[nargs] = NULL;
+ debug_parser("%s: nargs=%d\n", __func__, nargs);
+ return nargs;
+ }
+
+ argv[nargs++] = line; /* begin of argument string */
+
+ /* find end of string */
+ while (*line && !isblank(*line))
+ ++line;
+
+ if (*line == '\0') { /* end of line, no more args */
+ argv[nargs] = NULL;
+ debug_parser("parse_line: nargs=%d\n", nargs);
+ return nargs;
+ }
+
+ *line++ = '\0'; /* terminate current arg */
+ }
+
+ printf("** Too many args (max. %d) **\n", CONFIG_SYS_MAXARGS);
+
+ debug_parser("%s: nargs=%d\n", __func__, nargs);
+ return nargs;
+}
+
+static void process_macros(const char *input, char *output)
+{
+ char c, prev;
+ const char *varname_start = NULL;
+ int inputcnt = strlen(input);
+ int outputcnt = CONFIG_SYS_CBSIZE;
+ int state = 0; /* 0 = waiting for '$' */
+
+ /* 1 = waiting for '(' or '{' */
+ /* 2 = waiting for ')' or '}' */
+ /* 3 = waiting for ''' */
+ char *output_start = output;
+
+ debug_parser("[PROCESS_MACROS] INPUT len %zd: \"%s\"\n", strlen(input),
+ input);
+
+ prev = '\0'; /* previous character */
+
+ while (inputcnt && outputcnt) {
+ c = *input++;
+ inputcnt--;
+
+ if (state != 3) {
+ /* remove one level of escape characters */
+ if ((c == '\\') && (prev != '\\')) {
+ if (inputcnt-- == 0)
+ break;
+ prev = c;
+ c = *input++;
+ }
+ }
+
+ switch (state) {
+ case 0: /* Waiting for (unescaped) $ */
+ if ((c == '\'') && (prev != '\\')) {
+ state = 3;
+ break;
+ }
+ if ((c == '$') && (prev != '\\')) {
+ state++;
+ } else {
+ *(output++) = c;
+ outputcnt--;
+ }
+ break;
+ case 1: /* Waiting for ( */
+ if (c == '(' || c == '{') {
+ state++;
+ varname_start = input;
+ } else {
+ state = 0;
+ *(output++) = '$';
+ outputcnt--;
+
+ if (outputcnt) {
+ *(output++) = c;
+ outputcnt--;
+ }
+ }
+ break;
+ case 2: /* Waiting for ) */
+ if (c == ')' || c == '}') {
+ int i;
+ char envname[CONFIG_SYS_CBSIZE], *envval;
+ /* Varname # of chars */
+ int envcnt = input - varname_start - 1;
+
+ /* Get the varname */
+ for (i = 0; i < envcnt; i++)
+ envname[i] = varname_start[i];
+ envname[i] = 0;
+
+ /* Get its value */
+ envval = getenv(envname);
+
+ /* Copy into the line if it exists */
+ if (envval != NULL)
+ while ((*envval) && outputcnt) {
+ *(output++) = *(envval++);
+ outputcnt--;
+ }
+ /* Look for another '$' */
+ state = 0;
+ }
+ break;
+ case 3: /* Waiting for ' */
+ if ((c == '\'') && (prev != '\\')) {
+ state = 0;
+ } else {
+ *(output++) = c;
+ outputcnt--;
+ }
+ break;
+ }
+ prev = c;
+ }
+
+ if (outputcnt)
+ *output = 0;
+ else
+ *(output - 1) = 0;
+
+ debug_parser("[PROCESS_MACROS] OUTPUT len %zd: \"%s\"\n",
+ strlen(output_start), output_start);
+}
+
+ /*
+ * WARNING:
+ *
+ * We must create a temporary copy of the command since the command we get
+ * may be the result from getenv(), which returns a pointer directly to
+ * the environment data, which may change magicly when the command we run
+ * creates or modifies environment variables (like "bootp" does).
+ */
+int cli_simple_run_command(const char *cmd, int flag)
+{
+ char cmdbuf[CONFIG_SYS_CBSIZE]; /* working copy of cmd */
+ char *token; /* start of token in cmdbuf */
+ char *sep; /* end of token (separator) in cmdbuf */
+ char finaltoken[CONFIG_SYS_CBSIZE];
+ char *str = cmdbuf;
+ char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */
+ int argc, inquotes;
+ int repeatable = 1;
+ int rc = 0;
+
+ debug_parser("[RUN_COMMAND] cmd[%p]=\"", cmd);
+ if (DEBUG_PARSER) {
+ /* use puts - string may be loooong */
+ puts(cmd ? cmd : "NULL");
+ puts("\"\n");
+ }
+ clear_ctrlc(); /* forget any previous Control C */
+
+ if (!cmd || !*cmd)
+ return -1; /* empty command */
+
+ if (strlen(cmd) >= CONFIG_SYS_CBSIZE) {
+ puts("## Command too long!\n");
+ return -1;
+ }
+
+ strcpy(cmdbuf, cmd);
+
+ /* Process separators and check for invalid
+ * repeatable commands
+ */
+
+ debug_parser("[PROCESS_SEPARATORS] %s\n", cmd);
+ while (*str) {
+ /*
+ * Find separator, or string end
+ * Allow simple escape of ';' by writing "\;"
+ */
+ for (inquotes = 0, sep = str; *sep; sep++) {
+ if ((*sep == '\'') &&
+ (*(sep - 1) != '\\'))
+ inquotes = !inquotes;
+
+ if (!inquotes &&
+ (*sep == ';') && /* separator */
+ (sep != str) && /* past string start */
+ (*(sep - 1) != '\\')) /* and NOT escaped */
+ break;
+ }
+
+ /*
+ * Limit the token to data between separators
+ */
+ token = str;
+ if (*sep) {
+ str = sep + 1; /* start of command for next pass */
+ *sep = '\0';
+ } else {
+ str = sep; /* no more commands for next pass */
+ }
+ debug_parser("token: \"%s\"\n", token);
+
+ /* find macros in this token and replace them */
+ process_macros(token, finaltoken);
+
+ /* Extract arguments */
+ argc = cli_simple_parse_line(finaltoken, argv);
+ if (argc == 0) {
+ rc = -1; /* no command at all */
+ continue;
+ }
+
+ if (cmd_process(flag, argc, argv, &repeatable, NULL))
+ rc = -1;
+
+ /* Did the user stop this? */
+ if (had_ctrlc())
+ return -1; /* if stopped then not repeatable */
+ }
+
+ return rc ? rc : repeatable;
+}
+
+void cli_simple_loop(void)
+{
+ static char lastcommand[CONFIG_SYS_CBSIZE] = { 0, };
+
+ int len;
+ int flag;
+ int rc = 1;
+
+ for (;;) {
+ if (rc >= 0) {
+ /* Saw enough of a valid command to
+ * restart the timeout.
+ */
+ bootretry_reset_cmd_timeout();
+ }
+ len = cli_readline(CONFIG_SYS_PROMPT);
+
+ flag = 0; /* assume no special flags for now */
+ if (len > 0)
+ strcpy(lastcommand, console_buffer);
+ else if (len == 0)
+ flag |= CMD_FLAG_REPEAT;
+#ifdef CONFIG_BOOT_RETRY_TIME
+ else if (len == -2) {
+ /* -2 means timed out, retry autoboot
+ */
+ puts("\nTimed out waiting for command\n");
+# ifdef CONFIG_RESET_TO_RETRY
+ /* Reinit board to run initialization code again */
+ do_reset(NULL, 0, 0, NULL);
+# else
+ return; /* retry autoboot */
+# endif
+ }
+#endif
+
+ if (len == -1)
+ puts("<INTERRUPT>\n");
+ else
+ rc = run_command_repeatable(lastcommand, flag);
+
+ if (rc <= 0) {
+ /* invalid command or not repeatable, forget it */
+ lastcommand[0] = 0;
+ }
+ }
+}
+
+int cli_simple_run_command_list(char *cmd, int flag)
+{
+ char *line, *next;
+ int rcode = 0;
+
+ /*
+ * Break into individual lines, and execute each line; terminate on
+ * error.
+ */
+ next = cmd;
+ line = cmd;
+ while (*next) {
+ if (*next == '\n') {
+ *next = '\0';
+ /* run only non-empty commands */
+ if (*line) {
+ debug("** exec: \"%s\"\n", line);
+ if (cli_simple_run_command(line, 0) < 0) {
+ rcode = 1;
+ break;
+ }
+ }
+ line = next + 1;
+ }
+ ++next;
+ }
+ if (rcode == 0 && *line)
+ rcode = (cli_simple_run_command(line, 0) < 0);
+
+ return rcode;
+}
*/
#include <common.h>
+#include <cli.h>
#include <command.h>
#include <linux/ctype.h>
#include <net.h>
ulong dis_last_addr = 0; /* Last address disassembled */
ulong dis_last_len = 20; /* Default disassembler length */
CPU_DEBUG_CTX bug_ctx; /* Bedbug context structure */
-\f
+
/* ======================================================================
* U-Boot's puts function does not append a newline, so the bedbug stuff
printf ("%s\r\n", str);
return 0;
} /* bedbug_puts */
-\f
+
/* ======================================================================
return;
} /* bedbug_init */
-\f
+
/* ======================================================================
U_BOOT_CMD (ds, 3, 1, do_bedbug_dis,
"disassemble memory",
"ds <address> [# instructions]");
-\f
+
/* ======================================================================
* Entry point from the interpreter to the assembler. Assembles
* instructions in consecutive memory locations until a '.' (period) is
F_RADHEX);
sprintf (prompt, "%08lx: ", mem_addr);
- readline (prompt);
+ cli_readline(prompt);
if (console_buffer[0] && strcmp (console_buffer, ".")) {
if ((instr =
U_BOOT_CMD (as, 2, 0, do_bedbug_asm,
"assemble memory", "as <address>");
-\f
+
/* ======================================================================
* Used to set a break point from the interpreter. Simply calls into the
* CPU-specific break point set routine.
"break <address> - Break at an address\n"
"break off <bp#> - Disable breakpoint.\n"
"break show - List breakpoints.");
-\f
+
/* ======================================================================
* Called from the debug interrupt routine. Simply calls the CPU-specific
* breakpoint handling routine.
return;
} /* do_bedbug_breakpoint */
-\f
+
/* ======================================================================
/* A miniature main loop */
while (bug_ctx.stopped) {
- len = readline (prompt_str);
+ len = cli_readline(prompt_str);
flag = 0; /* assume no special flags for now */
if (len == -1)
printf ("<INTERRUPT>\n");
else
- rc = run_command(lastcommand, flag);
+ rc = run_command_repeatable(lastcommand, flag);
if (rc <= 0) {
/* invalid command or not repeatable, forget it */
return;
} /* bedbug_main_loop */
-\f
+
/* ======================================================================
U_BOOT_CMD (continue, 1, 0, do_bedbug_continue,
"continue from a breakpoint",
"");
-\f
+
/* ======================================================================
* Interpreter command to continue to the next instruction, stepping into
* subroutines. Works by calling the find_next_addr() routine to compute
U_BOOT_CMD (step, 1, 1, do_bedbug_step,
"single step execution.",
"");
-\f
+
/* ======================================================================
* Interpreter command to continue to the next instruction, stepping over
* subroutines. Works by calling the find_next_addr() routine to compute
U_BOOT_CMD (next, 1, 1, do_bedbug_next,
"single step execution, stepping over subroutines.",
"");
-\f
+
/* ======================================================================
* Interpreter command to print the current stack. This assumes an EABI
* architecture, so it starts with GPR R1 and works back up the stack.
U_BOOT_CMD (where, 1, 1, do_bedbug_stack,
"Print the running stack.",
"");
-\f
+
/* ======================================================================
* Interpreter command to dump the registers. Calls the CPU-specific
* show registers routine.
* SPDX-License-Identifier: GPL-2.0+
*/
-
/*
* Boot support
*/
#include <common.h>
-#include <watchdog.h>
+#include <bootm.h>
#include <command.h>
-#include <image.h>
-#include <malloc.h>
-#include <u-boot/zlib.h>
-#include <bzlib.h>
#include <environment.h>
+#include <image.h>
#include <lmb.h>
-#include <linux/ctype.h>
+#include <malloc.h>
+#include <nand.h>
#include <asm/byteorder.h>
-#include <asm/io.h>
#include <linux/compiler.h>
-
-#if defined(CONFIG_BOOTM_VXWORKS) && \
- (defined(CONFIG_PPC) || defined(CONFIG_ARM))
-#include <vxworks.h>
-#endif
-
-#if defined(CONFIG_CMD_USB)
-#include <usb.h>
-#endif
-
-#ifdef CONFIG_SYS_HUSH_PARSER
-#include <hush.h>
-#endif
-
-#if defined(CONFIG_OF_LIBFDT)
-#include <libfdt.h>
-#include <fdt_support.h>
-#endif
-
-#ifdef CONFIG_LZMA
-#include <lzma/LzmaTypes.h>
-#include <lzma/LzmaDec.h>
-#include <lzma/LzmaTools.h>
-#endif /* CONFIG_LZMA */
-
-#ifdef CONFIG_LZO
-#include <linux/lzo.h>
-#endif /* CONFIG_LZO */
+#include <linux/ctype.h>
+#include <linux/err.h>
+#include <u-boot/zlib.h>
DECLARE_GLOBAL_DATA_PTR;
-#ifndef CONFIG_SYS_BOOTM_LEN
-#define CONFIG_SYS_BOOTM_LEN 0x800000 /* use 8MByte as default max gunzip size */
-#endif
-
-#ifdef CONFIG_BZIP2
-extern void bz_internal_error(int);
-#endif
-
#if defined(CONFIG_CMD_IMI)
static int image_info(unsigned long addr);
#endif
static int do_imls(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
#endif
-#include <linux/err.h>
-#include <nand.h>
-
-#if defined(CONFIG_SILENT_CONSOLE) && !defined(CONFIG_SILENT_U_BOOT_ONLY)
-static void fixup_silent_linux(void);
-#endif
-
-static int do_bootm_standalone(int flag, int argc, char * const argv[],
- bootm_headers_t *images);
-
-static const void *boot_get_kernel(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[], bootm_headers_t *images,
- ulong *os_data, ulong *os_len);
-
-/*
- * Continue booting an OS image; caller already has:
- * - copied image header to global variable `header'
- * - checked header magic number, checksums (both header & image),
- * - verified image architecture (PPC) and type (KERNEL or MULTI),
- * - loaded (first part of) image to header load address,
- * - disabled interrupts.
- *
- * @flag: Flags indicating what to do (BOOTM_STATE_...)
- * @argc: Number of arguments. Note that the arguments are shifted down
- * so that 0 is the first argument not processed by U-Boot, and
- * argc is adjusted accordingly. This avoids confusion as to how
- * many arguments are available for the OS.
- * @images: Pointers to os/initrd/fdt
- * @return 1 on error. On success the OS boots so this function does
- * not return.
- */
-typedef int boot_os_fn(int flag, int argc, char * const argv[],
- bootm_headers_t *images);
-
-#ifdef CONFIG_BOOTM_LINUX
-extern boot_os_fn do_bootm_linux;
-#endif
-#ifdef CONFIG_BOOTM_NETBSD
-static boot_os_fn do_bootm_netbsd;
-#endif
-#if defined(CONFIG_LYNXKDI)
-static boot_os_fn do_bootm_lynxkdi;
-extern void lynxkdi_boot(image_header_t *);
-#endif
-#ifdef CONFIG_BOOTM_RTEMS
-static boot_os_fn do_bootm_rtems;
-#endif
-#if defined(CONFIG_BOOTM_OSE)
-static boot_os_fn do_bootm_ose;
-#endif
-#if defined(CONFIG_BOOTM_PLAN9)
-static boot_os_fn do_bootm_plan9;
-#endif
-#if defined(CONFIG_BOOTM_VXWORKS) && \
- (defined(CONFIG_PPC) || defined(CONFIG_ARM))
-static boot_os_fn do_bootm_vxworks;
-#endif
-#if defined(CONFIG_CMD_ELF)
-static boot_os_fn do_bootm_qnxelf;
-int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-int do_bootelf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
-#endif
-#if defined(CONFIG_INTEGRITY)
-static boot_os_fn do_bootm_integrity;
-#endif
-
-static boot_os_fn *boot_os[] = {
- [IH_OS_U_BOOT] = do_bootm_standalone,
-#ifdef CONFIG_BOOTM_LINUX
- [IH_OS_LINUX] = do_bootm_linux,
-#endif
-#ifdef CONFIG_BOOTM_NETBSD
- [IH_OS_NETBSD] = do_bootm_netbsd,
-#endif
-#ifdef CONFIG_LYNXKDI
- [IH_OS_LYNXOS] = do_bootm_lynxkdi,
-#endif
-#ifdef CONFIG_BOOTM_RTEMS
- [IH_OS_RTEMS] = do_bootm_rtems,
-#endif
-#if defined(CONFIG_BOOTM_OSE)
- [IH_OS_OSE] = do_bootm_ose,
-#endif
-#if defined(CONFIG_BOOTM_PLAN9)
- [IH_OS_PLAN9] = do_bootm_plan9,
-#endif
-#if defined(CONFIG_BOOTM_VXWORKS) && \
- (defined(CONFIG_PPC) || defined(CONFIG_ARM))
- [IH_OS_VXWORKS] = do_bootm_vxworks,
-#endif
-#if defined(CONFIG_CMD_ELF)
- [IH_OS_QNX] = do_bootm_qnxelf,
-#endif
-#ifdef CONFIG_INTEGRITY
- [IH_OS_INTEGRITY] = do_bootm_integrity,
-#endif
-};
-
bootm_headers_t images; /* pointers to os/initrd/fdt images */
-/* Allow for arch specific config before we boot */
-static void __arch_preboot_os(void)
-{
- /* please define platform specific arch_preboot_os() */
-}
-void arch_preboot_os(void) __attribute__((weak, alias("__arch_preboot_os")));
-
-#define IH_INITRD_ARCH IH_ARCH_DEFAULT
-
-#ifdef CONFIG_LMB
-static void boot_start_lmb(bootm_headers_t *images)
-{
- ulong mem_start;
- phys_size_t mem_size;
-
- lmb_init(&images->lmb);
-
- mem_start = getenv_bootm_low();
- mem_size = getenv_bootm_size();
-
- lmb_add(&images->lmb, (phys_addr_t)mem_start, mem_size);
-
- arch_lmb_reserve(&images->lmb);
- board_lmb_reserve(&images->lmb);
-}
-#else
-#define lmb_reserve(lmb, base, size)
-static inline void boot_start_lmb(bootm_headers_t *images) { }
-#endif
-
-static int bootm_start(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- memset((void *)&images, 0, sizeof(images));
- images.verify = getenv_yesno("verify");
-
- boot_start_lmb(&images);
-
- bootstage_mark_name(BOOTSTAGE_ID_BOOTM_START, "bootm_start");
- images.state = BOOTM_STATE_START;
-
- return 0;
-}
-
-static int bootm_find_os(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- const void *os_hdr;
- bool ep_found = false;
-
- /* get kernel image header, start address and length */
- os_hdr = boot_get_kernel(cmdtp, flag, argc, argv,
- &images, &images.os.image_start, &images.os.image_len);
- if (images.os.image_len == 0) {
- puts("ERROR: can't get kernel image!\n");
- return 1;
- }
-
- /* get image parameters */
- switch (genimg_get_format(os_hdr)) {
- case IMAGE_FORMAT_LEGACY:
- images.os.type = image_get_type(os_hdr);
- images.os.comp = image_get_comp(os_hdr);
- images.os.os = image_get_os(os_hdr);
-
- images.os.end = image_get_image_end(os_hdr);
- images.os.load = image_get_load(os_hdr);
- break;
-#if defined(CONFIG_FIT)
- case IMAGE_FORMAT_FIT:
- if (fit_image_get_type(images.fit_hdr_os,
- images.fit_noffset_os, &images.os.type)) {
- puts("Can't get image type!\n");
- bootstage_error(BOOTSTAGE_ID_FIT_TYPE);
- return 1;
- }
-
- if (fit_image_get_comp(images.fit_hdr_os,
- images.fit_noffset_os, &images.os.comp)) {
- puts("Can't get image compression!\n");
- bootstage_error(BOOTSTAGE_ID_FIT_COMPRESSION);
- return 1;
- }
-
- if (fit_image_get_os(images.fit_hdr_os,
- images.fit_noffset_os, &images.os.os)) {
- puts("Can't get image OS!\n");
- bootstage_error(BOOTSTAGE_ID_FIT_OS);
- return 1;
- }
-
- images.os.end = fit_get_end(images.fit_hdr_os);
-
- if (fit_image_get_load(images.fit_hdr_os, images.fit_noffset_os,
- &images.os.load)) {
- puts("Can't get image load address!\n");
- bootstage_error(BOOTSTAGE_ID_FIT_LOADADDR);
- return 1;
- }
- break;
-#endif
-#ifdef CONFIG_ANDROID_BOOT_IMAGE
- case IMAGE_FORMAT_ANDROID:
- images.os.type = IH_TYPE_KERNEL;
- images.os.comp = IH_COMP_NONE;
- images.os.os = IH_OS_LINUX;
- images.ep = images.os.load;
- ep_found = true;
-
- images.os.end = android_image_get_end(os_hdr);
- images.os.load = android_image_get_kload(os_hdr);
- break;
-#endif
- default:
- puts("ERROR: unknown image format type!\n");
- return 1;
- }
-
- /* find kernel entry point */
- if (images.legacy_hdr_valid) {
- images.ep = image_get_ep(&images.legacy_hdr_os_copy);
-#if defined(CONFIG_FIT)
- } else if (images.fit_uname_os) {
- int ret;
-
- ret = fit_image_get_entry(images.fit_hdr_os,
- images.fit_noffset_os, &images.ep);
- if (ret) {
- puts("Can't get entry point property!\n");
- return 1;
- }
-#endif
- } else if (!ep_found) {
- puts("Could not find kernel entry point!\n");
- return 1;
- }
-
- if (images.os.type == IH_TYPE_KERNEL_NOLOAD) {
- images.os.load = images.os.image_start;
- images.ep += images.os.load;
- }
-
- images.os.start = (ulong)os_hdr;
-
- return 0;
-}
-
-static int bootm_find_ramdisk(int flag, int argc, char * const argv[])
-{
- int ret;
-
- /* find ramdisk */
- ret = boot_get_ramdisk(argc, argv, &images, IH_INITRD_ARCH,
- &images.rd_start, &images.rd_end);
- if (ret) {
- puts("Ramdisk image is corrupt or invalid\n");
- return 1;
- }
-
- return 0;
-}
-
-#if defined(CONFIG_OF_LIBFDT)
-static int bootm_find_fdt(int flag, int argc, char * const argv[])
-{
- int ret;
-
- /* find flattened device tree */
- ret = boot_get_fdt(flag, argc, argv, IH_ARCH_DEFAULT, &images,
- &images.ft_addr, &images.ft_len);
- if (ret) {
- puts("Could not find a valid device tree\n");
- return 1;
- }
-
- set_working_fdt_addr(images.ft_addr);
-
- return 0;
-}
-#endif
-
-static int bootm_find_other(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- if (((images.os.type == IH_TYPE_KERNEL) ||
- (images.os.type == IH_TYPE_KERNEL_NOLOAD) ||
- (images.os.type == IH_TYPE_MULTI)) &&
- (images.os.os == IH_OS_LINUX ||
- images.os.os == IH_OS_VXWORKS)) {
- if (bootm_find_ramdisk(flag, argc, argv))
- return 1;
-
-#if defined(CONFIG_OF_LIBFDT)
- if (bootm_find_fdt(flag, argc, argv))
- return 1;
-#endif
- }
-
- return 0;
-}
-
-#define BOOTM_ERR_RESET -1
-#define BOOTM_ERR_OVERLAP -2
-#define BOOTM_ERR_UNIMPLEMENTED -3
-static int bootm_load_os(bootm_headers_t *images, unsigned long *load_end,
- int boot_progress)
-{
- image_info_t os = images->os;
- uint8_t comp = os.comp;
- ulong load = os.load;
- ulong blob_start = os.start;
- ulong blob_end = os.end;
- ulong image_start = os.image_start;
- ulong image_len = os.image_len;
- __maybe_unused uint unc_len = CONFIG_SYS_BOOTM_LEN;
- int no_overlap = 0;
- void *load_buf, *image_buf;
-#if defined(CONFIG_LZMA) || defined(CONFIG_LZO)
- int ret;
-#endif /* defined(CONFIG_LZMA) || defined(CONFIG_LZO) */
-
- const char *type_name = genimg_get_type_name(os.type);
-
- load_buf = map_sysmem(load, unc_len);
- image_buf = map_sysmem(image_start, image_len);
- switch (comp) {
- case IH_COMP_NONE:
- if (load == image_start) {
- printf(" XIP %s ... ", type_name);
- no_overlap = 1;
- } else {
- printf(" Loading %s ... ", type_name);
- memmove_wd(load_buf, image_buf, image_len, CHUNKSZ);
- }
- *load_end = load + image_len;
- break;
-#ifdef CONFIG_GZIP
- case IH_COMP_GZIP:
- printf(" Uncompressing %s ... ", type_name);
- if (gunzip(load_buf, unc_len, image_buf, &image_len) != 0) {
- puts("GUNZIP: uncompress, out-of-mem or overwrite "
- "error - must RESET board to recover\n");
- if (boot_progress)
- bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE);
- return BOOTM_ERR_RESET;
- }
-
- *load_end = load + image_len;
- break;
-#endif /* CONFIG_GZIP */
-#ifdef CONFIG_BZIP2
- case IH_COMP_BZIP2:
- printf(" Uncompressing %s ... ", type_name);
- /*
- * If we've got less than 4 MB of malloc() space,
- * use slower decompression algorithm which requires
- * at most 2300 KB of memory.
- */
- int i = BZ2_bzBuffToBuffDecompress(load_buf, &unc_len,
- image_buf, image_len,
- CONFIG_SYS_MALLOC_LEN < (4096 * 1024), 0);
- if (i != BZ_OK) {
- printf("BUNZIP2: uncompress or overwrite error %d "
- "- must RESET board to recover\n", i);
- if (boot_progress)
- bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE);
- return BOOTM_ERR_RESET;
- }
-
- *load_end = load + unc_len;
- break;
-#endif /* CONFIG_BZIP2 */
-#ifdef CONFIG_LZMA
- case IH_COMP_LZMA: {
- SizeT lzma_len = unc_len;
- printf(" Uncompressing %s ... ", type_name);
-
- ret = lzmaBuffToBuffDecompress(load_buf, &lzma_len,
- image_buf, image_len);
- unc_len = lzma_len;
- if (ret != SZ_OK) {
- printf("LZMA: uncompress or overwrite error %d "
- "- must RESET board to recover\n", ret);
- bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE);
- return BOOTM_ERR_RESET;
- }
- *load_end = load + unc_len;
- break;
- }
-#endif /* CONFIG_LZMA */
-#ifdef CONFIG_LZO
- case IH_COMP_LZO: {
- size_t size = unc_len;
-
- printf(" Uncompressing %s ... ", type_name);
-
- ret = lzop_decompress(image_buf, image_len, load_buf, &size);
- if (ret != LZO_E_OK) {
- printf("LZO: uncompress or overwrite error %d "
- "- must RESET board to recover\n", ret);
- if (boot_progress)
- bootstage_error(BOOTSTAGE_ID_DECOMP_IMAGE);
- return BOOTM_ERR_RESET;
- }
-
- *load_end = load + size;
- break;
- }
-#endif /* CONFIG_LZO */
- default:
- printf("Unimplemented compression type %d\n", comp);
- return BOOTM_ERR_UNIMPLEMENTED;
- }
-
- flush_cache(load, (*load_end - load) * sizeof(ulong));
-
- puts("OK\n");
- debug(" kernel loaded at 0x%08lx, end = 0x%08lx\n", load, *load_end);
- bootstage_mark(BOOTSTAGE_ID_KERNEL_LOADED);
-
- if (!no_overlap && (load < blob_end) && (*load_end > blob_start)) {
- debug("images.os.start = 0x%lX, images.os.end = 0x%lx\n",
- blob_start, blob_end);
- debug("images.os.load = 0x%lx, load_end = 0x%lx\n", load,
- *load_end);
-
- /* Check what type of image this is. */
- if (images->legacy_hdr_valid) {
- if (image_get_type(&images->legacy_hdr_os_copy)
- == IH_TYPE_MULTI)
- puts("WARNING: legacy format multi component image overwritten\n");
- return BOOTM_ERR_OVERLAP;
- } else {
- puts("ERROR: new format image overwritten - must RESET the board to recover\n");
- bootstage_error(BOOTSTAGE_ID_OVERWRITTEN);
- return BOOTM_ERR_RESET;
- }
- }
-
- return 0;
-}
-
-static int do_bootm_standalone(int flag, int argc, char * const argv[],
- bootm_headers_t *images)
-{
- char *s;
- int (*appl)(int, char * const []);
-
- /* Don't start if "autostart" is set to "no" */
- if (((s = getenv("autostart")) != NULL) && (strcmp(s, "no") == 0)) {
- setenv_hex("filesize", images->os.image_len);
- return 0;
- }
- appl = (int (*)(int, char * const []))images->ep;
- appl(argc, argv);
- return 0;
-}
-
/* we overload the cmd field with our state machine info instead of a
* function pointer */
static cmd_tbl_t cmd_bootm_sub[] = {
U_BOOT_CMD_MKENT(go, 0, 1, (void *)BOOTM_STATE_OS_GO, "", ""),
};
-static int boot_selected_os(int argc, char * const argv[], int state,
- bootm_headers_t *images, boot_os_fn *boot_fn)
-{
- arch_preboot_os();
- boot_fn(state, argc, argv, images);
-
- /* Stand-alone may return when 'autostart' is 'no' */
- if (images->os.type == IH_TYPE_STANDALONE ||
- state == BOOTM_STATE_OS_FAKE_GO) /* We expect to return */
- return 0;
- bootstage_error(BOOTSTAGE_ID_BOOT_OS_RETURNED);
-#ifdef DEBUG
- puts("\n## Control returned to monitor - resetting...\n");
-#endif
- return BOOTM_ERR_RESET;
-}
-
-/**
- * bootm_disable_interrupts() - Disable interrupts in preparation for load/boot
- *
- * @return interrupt flag (0 if interrupts were disabled, non-zero if they were
- * enabled)
- */
-static ulong bootm_disable_interrupts(void)
-{
- ulong iflag;
-
- /*
- * We have reached the point of no return: we are going to
- * overwrite all exception vector code, so we cannot easily
- * recover from any failures any more...
- */
- iflag = disable_interrupts();
-#ifdef CONFIG_NETCONSOLE
- /* Stop the ethernet stack if NetConsole could have left it up */
- eth_halt();
- eth_unregister(eth_get_dev());
-#endif
-
-#if defined(CONFIG_CMD_USB)
- /*
- * turn off USB to prevent the host controller from writing to the
- * SDRAM while Linux is booting. This could happen (at least for OHCI
- * controller), because the HCCA (Host Controller Communication Area)
- * lies within the SDRAM and the host controller writes continously to
- * this area (as busmaster!). The HccaFrameNumber is for example
- * updated every 1 ms within the HCCA structure in SDRAM! For more
- * details see the OpenHCI specification.
- */
- usb_stop();
-#endif
- return iflag;
-}
-
-/**
- * Execute selected states of the bootm command.
- *
- * Note the arguments to this state must be the first argument, Any 'bootm'
- * or sub-command arguments must have already been taken.
- *
- * Note that if states contains more than one flag it MUST contain
- * BOOTM_STATE_START, since this handles and consumes the command line args.
- *
- * Also note that aside from boot_os_fn functions and bootm_load_os no other
- * functions we store the return value of in 'ret' may use a negative return
- * value, without special handling.
- *
- * @param cmdtp Pointer to bootm command table entry
- * @param flag Command flags (CMD_FLAG_...)
- * @param argc Number of subcommand arguments (0 = no arguments)
- * @param argv Arguments
- * @param states Mask containing states to run (BOOTM_STATE_...)
- * @param images Image header information
- * @param boot_progress 1 to show boot progress, 0 to not do this
- * @return 0 if ok, something else on error. Some errors will cause this
- * function to perform a reboot! If states contains BOOTM_STATE_OS_GO
- * then the intent is to boot an OS, so this function will not return
- * unless the image type is standalone.
- */
-static int do_bootm_states(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[], int states, bootm_headers_t *images,
- int boot_progress)
-{
- boot_os_fn *boot_fn;
- ulong iflag = 0;
- int ret = 0, need_boot_fn;
-
- images->state |= states;
-
- /*
- * Work through the states and see how far we get. We stop on
- * any error.
- */
- if (states & BOOTM_STATE_START)
- ret = bootm_start(cmdtp, flag, argc, argv);
-
- if (!ret && (states & BOOTM_STATE_FINDOS))
- ret = bootm_find_os(cmdtp, flag, argc, argv);
-
- if (!ret && (states & BOOTM_STATE_FINDOTHER)) {
- ret = bootm_find_other(cmdtp, flag, argc, argv);
- argc = 0; /* consume the args */
- }
-
- /* Load the OS */
- if (!ret && (states & BOOTM_STATE_LOADOS)) {
- ulong load_end;
-
- iflag = bootm_disable_interrupts();
- ret = bootm_load_os(images, &load_end, 0);
- if (ret == 0)
- lmb_reserve(&images->lmb, images->os.load,
- (load_end - images->os.load));
- else if (ret && ret != BOOTM_ERR_OVERLAP)
- goto err;
- else if (ret == BOOTM_ERR_OVERLAP)
- ret = 0;
-#if defined(CONFIG_SILENT_CONSOLE) && !defined(CONFIG_SILENT_U_BOOT_ONLY)
- if (images->os.os == IH_OS_LINUX)
- fixup_silent_linux();
-#endif
- }
-
- /* Relocate the ramdisk */
-#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
- if (!ret && (states & BOOTM_STATE_RAMDISK)) {
- ulong rd_len = images->rd_end - images->rd_start;
-
- ret = boot_ramdisk_high(&images->lmb, images->rd_start,
- rd_len, &images->initrd_start, &images->initrd_end);
- if (!ret) {
- setenv_hex("initrd_start", images->initrd_start);
- setenv_hex("initrd_end", images->initrd_end);
- }
- }
-#endif
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_LMB)
- if (!ret && (states & BOOTM_STATE_FDT)) {
- boot_fdt_add_mem_rsv_regions(&images->lmb, images->ft_addr);
- ret = boot_relocate_fdt(&images->lmb, &images->ft_addr,
- &images->ft_len);
- }
-#endif
-
- /* From now on, we need the OS boot function */
- if (ret)
- return ret;
- boot_fn = boot_os[images->os.os];
- need_boot_fn = states & (BOOTM_STATE_OS_CMDLINE |
- BOOTM_STATE_OS_BD_T | BOOTM_STATE_OS_PREP |
- BOOTM_STATE_OS_FAKE_GO | BOOTM_STATE_OS_GO);
- if (boot_fn == NULL && need_boot_fn) {
- if (iflag)
- enable_interrupts();
- printf("ERROR: booting os '%s' (%d) is not supported\n",
- genimg_get_os_name(images->os.os), images->os.os);
- bootstage_error(BOOTSTAGE_ID_CHECK_BOOT_OS);
- return 1;
- }
-
- /* Call various other states that are not generally used */
- if (!ret && (states & BOOTM_STATE_OS_CMDLINE))
- ret = boot_fn(BOOTM_STATE_OS_CMDLINE, argc, argv, images);
- if (!ret && (states & BOOTM_STATE_OS_BD_T))
- ret = boot_fn(BOOTM_STATE_OS_BD_T, argc, argv, images);
- if (!ret && (states & BOOTM_STATE_OS_PREP))
- ret = boot_fn(BOOTM_STATE_OS_PREP, argc, argv, images);
-
-#ifdef CONFIG_TRACE
- /* Pretend to run the OS, then run a user command */
- if (!ret && (states & BOOTM_STATE_OS_FAKE_GO)) {
- char *cmd_list = getenv("fakegocmd");
-
- ret = boot_selected_os(argc, argv, BOOTM_STATE_OS_FAKE_GO,
- images, boot_fn);
- if (!ret && cmd_list)
- ret = run_command_list(cmd_list, -1, flag);
- }
-#endif
-
- /* Check for unsupported subcommand. */
- if (ret) {
- puts("subcommand not supported\n");
- return ret;
- }
-
- /* Now run the OS! We hope this doesn't return */
- if (!ret && (states & BOOTM_STATE_OS_GO))
- ret = boot_selected_os(argc, argv, BOOTM_STATE_OS_GO,
- images, boot_fn);
-
- /* Deal with any fallout */
-err:
- if (iflag)
- enable_interrupts();
-
- if (ret == BOOTM_ERR_UNIMPLEMENTED)
- bootstage_error(BOOTSTAGE_ID_DECOMP_UNIMPL);
- else if (ret == BOOTM_ERR_RESET)
- do_reset(cmdtp, flag, argc, argv);
-
- return ret;
-}
-
static int do_bootm_subcommand(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
if (!relocated) {
int i;
- /* relocate boot function table */
- for (i = 0; i < ARRAY_SIZE(boot_os); i++)
- if (boot_os[i] != NULL)
- boot_os[i] += gd->reloc_off;
-
/* relocate names of sub-command table */
for (i = 0; i < ARRAY_SIZE(cmd_bootm_sub); i++)
cmd_bootm_sub[i].name += gd->reloc_off;
return 0;
}
-/**
- * image_get_kernel - verify legacy format kernel image
- * @img_addr: in RAM address of the legacy format image to be verified
- * @verify: data CRC verification flag
- *
- * image_get_kernel() verifies legacy image integrity and returns pointer to
- * legacy image header if image verification was completed successfully.
- *
- * returns:
- * pointer to a legacy image header if valid image was found
- * otherwise return NULL
- */
-static image_header_t *image_get_kernel(ulong img_addr, int verify)
-{
- image_header_t *hdr = (image_header_t *)img_addr;
-
- if (!image_check_magic(hdr)) {
- puts("Bad Magic Number\n");
- bootstage_error(BOOTSTAGE_ID_CHECK_MAGIC);
- return NULL;
- }
- bootstage_mark(BOOTSTAGE_ID_CHECK_HEADER);
-
- if (!image_check_hcrc(hdr)) {
- puts("Bad Header Checksum\n");
- bootstage_error(BOOTSTAGE_ID_CHECK_HEADER);
- return NULL;
- }
-
- bootstage_mark(BOOTSTAGE_ID_CHECK_CHECKSUM);
- image_print_contents(hdr);
-
- if (verify) {
- puts(" Verifying Checksum ... ");
- if (!image_check_dcrc(hdr)) {
- printf("Bad Data CRC\n");
- bootstage_error(BOOTSTAGE_ID_CHECK_CHECKSUM);
- return NULL;
- }
- puts("OK\n");
- }
- bootstage_mark(BOOTSTAGE_ID_CHECK_ARCH);
-
- if (!image_check_target_arch(hdr)) {
- printf("Unsupported Architecture 0x%x\n", image_get_arch(hdr));
- bootstage_error(BOOTSTAGE_ID_CHECK_ARCH);
- return NULL;
- }
- return hdr;
-}
-
-/**
- * boot_get_kernel - find kernel image
- * @os_data: pointer to a ulong variable, will hold os data start address
- * @os_len: pointer to a ulong variable, will hold os data length
- *
- * boot_get_kernel() tries to find a kernel image, verifies its integrity
- * and locates kernel data.
- *
- * returns:
- * pointer to image header if valid image was found, plus kernel start
- * address and length, otherwise NULL
- */
-static const void *boot_get_kernel(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[], bootm_headers_t *images, ulong *os_data,
- ulong *os_len)
-{
- image_header_t *hdr;
- ulong img_addr;
- const void *buf;
-#if defined(CONFIG_FIT)
- const char *fit_uname_config = NULL;
- const char *fit_uname_kernel = NULL;
- int os_noffset;
-#endif
-
- /* find out kernel image address */
- if (argc < 1) {
- img_addr = load_addr;
- debug("* kernel: default image load address = 0x%08lx\n",
- load_addr);
-#if defined(CONFIG_FIT)
- } else if (fit_parse_conf(argv[0], load_addr, &img_addr,
- &fit_uname_config)) {
- debug("* kernel: config '%s' from image at 0x%08lx\n",
- fit_uname_config, img_addr);
- } else if (fit_parse_subimage(argv[0], load_addr, &img_addr,
- &fit_uname_kernel)) {
- debug("* kernel: subimage '%s' from image at 0x%08lx\n",
- fit_uname_kernel, img_addr);
-#endif
- } else {
- img_addr = simple_strtoul(argv[0], NULL, 16);
- debug("* kernel: cmdline image address = 0x%08lx\n", img_addr);
- }
-
- bootstage_mark(BOOTSTAGE_ID_CHECK_MAGIC);
-
- /* copy from dataflash if needed */
- img_addr = genimg_get_image(img_addr);
-
- /* check image type, for FIT images get FIT kernel node */
- *os_data = *os_len = 0;
- buf = map_sysmem(img_addr, 0);
- switch (genimg_get_format(buf)) {
- case IMAGE_FORMAT_LEGACY:
- printf("## Booting kernel from Legacy Image at %08lx ...\n",
- img_addr);
- hdr = image_get_kernel(img_addr, images->verify);
- if (!hdr)
- return NULL;
- bootstage_mark(BOOTSTAGE_ID_CHECK_IMAGETYPE);
-
- /* get os_data and os_len */
- switch (image_get_type(hdr)) {
- case IH_TYPE_KERNEL:
- case IH_TYPE_KERNEL_NOLOAD:
- *os_data = image_get_data(hdr);
- *os_len = image_get_data_size(hdr);
- break;
- case IH_TYPE_MULTI:
- image_multi_getimg(hdr, 0, os_data, os_len);
- break;
- case IH_TYPE_STANDALONE:
- *os_data = image_get_data(hdr);
- *os_len = image_get_data_size(hdr);
- break;
- default:
- printf("Wrong Image Type for %s command\n",
- cmdtp->name);
- bootstage_error(BOOTSTAGE_ID_CHECK_IMAGETYPE);
- return NULL;
- }
-
- /*
- * copy image header to allow for image overwrites during
- * kernel decompression.
- */
- memmove(&images->legacy_hdr_os_copy, hdr,
- sizeof(image_header_t));
-
- /* save pointer to image header */
- images->legacy_hdr_os = hdr;
-
- images->legacy_hdr_valid = 1;
- bootstage_mark(BOOTSTAGE_ID_DECOMP_IMAGE);
- break;
-#if defined(CONFIG_FIT)
- case IMAGE_FORMAT_FIT:
- os_noffset = fit_image_load(images, FIT_KERNEL_PROP,
- img_addr,
- &fit_uname_kernel, &fit_uname_config,
- IH_ARCH_DEFAULT, IH_TYPE_KERNEL,
- BOOTSTAGE_ID_FIT_KERNEL_START,
- FIT_LOAD_IGNORED, os_data, os_len);
- if (os_noffset < 0)
- return NULL;
-
- images->fit_hdr_os = map_sysmem(img_addr, 0);
- images->fit_uname_os = fit_uname_kernel;
- images->fit_uname_cfg = fit_uname_config;
- images->fit_noffset_os = os_noffset;
- break;
-#endif
-#ifdef CONFIG_ANDROID_BOOT_IMAGE
- case IMAGE_FORMAT_ANDROID:
- printf("## Booting Android Image at 0x%08lx ...\n", img_addr);
- if (android_image_get_kernel((void *)img_addr, images->verify,
- os_data, os_len))
- return NULL;
- break;
-#endif
- default:
- printf("Wrong Image Format for %s command\n", cmdtp->name);
- bootstage_error(BOOTSTAGE_ID_FIT_KERNEL_INFO);
- return NULL;
- }
-
- debug(" kernel data at 0x%08lx, len = 0x%08lx (%ld)\n",
- *os_data, *os_len, *os_len);
-
- return buf;
-}
-
#ifdef CONFIG_SYS_LONGHELP
static char bootm_help_text[] =
"[addr [arg ...]]\n - boot application image stored in memory\n"
#if defined(CONFIG_CMD_BOOTD)
int do_bootd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- int rcode = 0;
-
- if (run_command(getenv("bootcmd"), flag) < 0)
- rcode = 1;
- return rcode;
+ return run_command(getenv("bootcmd"), flag);
}
U_BOOT_CMD(
printf("\n## Checking Image at %08lx ...\n", addr);
switch (genimg_get_format(hdr)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
puts(" Legacy image found\n");
if (!image_check_magic(hdr)) {
}
puts("OK\n");
return 0;
+#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
puts(" FIT image found\n");
goto next_sector;
switch (genimg_get_format(hdr)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
if (!image_check_hcrc(hdr))
goto next_sector;
puts("OK\n");
}
break;
+#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
if (!fit_check_format(hdr))
}
switch (genimg_get_format(buffer)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
header = (const image_header_t *)buffer;
len = image_get_image_size(header);
nand_imls_legacyimage(nand, nand_dev, off, len);
break;
+#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
len = fit_get_size(buffer);
);
#endif
-/*******************************************************************/
-/* helper routines */
-/*******************************************************************/
-#if defined(CONFIG_SILENT_CONSOLE) && !defined(CONFIG_SILENT_U_BOOT_ONLY)
-
-#define CONSOLE_ARG "console="
-#define CONSOLE_ARG_LEN (sizeof(CONSOLE_ARG) - 1)
-
-static void fixup_silent_linux(void)
-{
- char *buf;
- const char *env_val;
- char *cmdline = getenv("bootargs");
- int want_silent;
-
- /*
- * Only fix cmdline when requested. The environment variable can be:
- *
- * no - we never fixup
- * yes - we always fixup
- * unset - we rely on the console silent flag
- */
- want_silent = getenv_yesno("silent_linux");
- if (want_silent == 0)
- return;
- else if (want_silent == -1 && !(gd->flags & GD_FLG_SILENT))
- return;
-
- debug("before silent fix-up: %s\n", cmdline);
- if (cmdline && (cmdline[0] != '\0')) {
- char *start = strstr(cmdline, CONSOLE_ARG);
-
- /* Allocate space for maximum possible new command line */
- buf = malloc(strlen(cmdline) + 1 + CONSOLE_ARG_LEN + 1);
- if (!buf) {
- debug("%s: out of memory\n", __func__);
- return;
- }
-
- if (start) {
- char *end = strchr(start, ' ');
- int num_start_bytes = start - cmdline + CONSOLE_ARG_LEN;
-
- strncpy(buf, cmdline, num_start_bytes);
- if (end)
- strcpy(buf + num_start_bytes, end);
- else
- buf[num_start_bytes] = '\0';
- } else {
- sprintf(buf, "%s %s", cmdline, CONSOLE_ARG);
- }
- env_val = buf;
- } else {
- buf = NULL;
- env_val = CONSOLE_ARG;
- }
-
- setenv("bootargs", env_val);
- debug("after silent fix-up: %s\n", env_val);
- free(buf);
-}
-#endif /* CONFIG_SILENT_CONSOLE */
-
-#if defined(CONFIG_BOOTM_NETBSD) || defined(CONFIG_BOOTM_PLAN9)
-static void copy_args(char *dest, int argc, char * const argv[], char delim)
-{
- int i;
-
- for (i = 0; i < argc; i++) {
- if (i > 0)
- *dest++ = delim;
- strcpy(dest, argv[i]);
- dest += strlen(argv[i]);
- }
-}
-#endif
-
-/*******************************************************************/
-/* OS booting routines */
-/*******************************************************************/
-
-#ifdef CONFIG_BOOTM_NETBSD
-static int do_bootm_netbsd(int flag, int argc, char * const argv[],
- bootm_headers_t *images)
-{
- void (*loader)(bd_t *, image_header_t *, char *, char *);
- image_header_t *os_hdr, *hdr;
- ulong kernel_data, kernel_len;
- char *consdev;
- char *cmdline;
-
- if (flag != BOOTM_STATE_OS_GO)
- return 0;
-
-#if defined(CONFIG_FIT)
- if (!images->legacy_hdr_valid) {
- fit_unsupported_reset("NetBSD");
- return 1;
- }
-#endif
- hdr = images->legacy_hdr_os;
-
- /*
- * Booting a (NetBSD) kernel image
- *
- * This process is pretty similar to a standalone application:
- * The (first part of an multi-) image must be a stage-2 loader,
- * which in turn is responsible for loading & invoking the actual
- * kernel. The only differences are the parameters being passed:
- * besides the board info strucure, the loader expects a command
- * line, the name of the console device, and (optionally) the
- * address of the original image header.
- */
- os_hdr = NULL;
- if (image_check_type(&images->legacy_hdr_os_copy, IH_TYPE_MULTI)) {
- image_multi_getimg(hdr, 1, &kernel_data, &kernel_len);
- if (kernel_len)
- os_hdr = hdr;
- }
-
- consdev = "";
-#if defined(CONFIG_8xx_CONS_SMC1)
- consdev = "smc1";
-#elif defined(CONFIG_8xx_CONS_SMC2)
- consdev = "smc2";
-#elif defined(CONFIG_8xx_CONS_SCC2)
- consdev = "scc2";
-#elif defined(CONFIG_8xx_CONS_SCC3)
- consdev = "scc3";
-#endif
-
- if (argc > 0) {
- ulong len;
- int i;
-
- for (i = 0, len = 0; i < argc; i += 1)
- len += strlen(argv[i]) + 1;
- cmdline = malloc(len);
- copy_args(cmdline, argc, argv, ' ');
- } else if ((cmdline = getenv("bootargs")) == NULL) {
- cmdline = "";
- }
-
- loader = (void (*)(bd_t *, image_header_t *, char *, char *))images->ep;
-
- printf("## Transferring control to NetBSD stage-2 loader "
- "(at address %08lx) ...\n",
- (ulong)loader);
-
- bootstage_mark(BOOTSTAGE_ID_RUN_OS);
-
- /*
- * NetBSD Stage-2 Loader Parameters:
- * arg[0]: pointer to board info data
- * arg[1]: image load address
- * arg[2]: char pointer to the console device to use
- * arg[3]: char pointer to the boot arguments
- */
- (*loader)(gd->bd, os_hdr, consdev, cmdline);
-
- return 1;
-}
-#endif /* CONFIG_BOOTM_NETBSD*/
-
-#ifdef CONFIG_LYNXKDI
-static int do_bootm_lynxkdi(int flag, int argc, char * const argv[],
- bootm_headers_t *images)
-{
- image_header_t *hdr = &images->legacy_hdr_os_copy;
-
- if (flag != BOOTM_STATE_OS_GO)
- return 0;
-
-#if defined(CONFIG_FIT)
- if (!images->legacy_hdr_valid) {
- fit_unsupported_reset("Lynx");
- return 1;
- }
-#endif
-
- lynxkdi_boot((image_header_t *)hdr);
-
- return 1;
-}
-#endif /* CONFIG_LYNXKDI */
-
-#ifdef CONFIG_BOOTM_RTEMS
-static int do_bootm_rtems(int flag, int argc, char * const argv[],
- bootm_headers_t *images)
-{
- void (*entry_point)(bd_t *);
-
- if (flag != BOOTM_STATE_OS_GO)
- return 0;
-
-#if defined(CONFIG_FIT)
- if (!images->legacy_hdr_valid) {
- fit_unsupported_reset("RTEMS");
- return 1;
- }
-#endif
-
- entry_point = (void (*)(bd_t *))images->ep;
-
- printf("## Transferring control to RTEMS (at address %08lx) ...\n",
- (ulong)entry_point);
-
- bootstage_mark(BOOTSTAGE_ID_RUN_OS);
-
- /*
- * RTEMS Parameters:
- * r3: ptr to board info data
- */
- (*entry_point)(gd->bd);
-
- return 1;
-}
-#endif /* CONFIG_BOOTM_RTEMS */
-
-#if defined(CONFIG_BOOTM_OSE)
-static int do_bootm_ose(int flag, int argc, char * const argv[],
- bootm_headers_t *images)
-{
- void (*entry_point)(void);
-
- if (flag != BOOTM_STATE_OS_GO)
- return 0;
-
-#if defined(CONFIG_FIT)
- if (!images->legacy_hdr_valid) {
- fit_unsupported_reset("OSE");
- return 1;
- }
-#endif
-
- entry_point = (void (*)(void))images->ep;
-
- printf("## Transferring control to OSE (at address %08lx) ...\n",
- (ulong)entry_point);
-
- bootstage_mark(BOOTSTAGE_ID_RUN_OS);
-
- /*
- * OSE Parameters:
- * None
- */
- (*entry_point)();
-
- return 1;
-}
-#endif /* CONFIG_BOOTM_OSE */
-
-#if defined(CONFIG_BOOTM_PLAN9)
-static int do_bootm_plan9(int flag, int argc, char * const argv[],
- bootm_headers_t *images)
-{
- void (*entry_point)(void);
- char *s;
-
- if (flag != BOOTM_STATE_OS_GO)
- return 0;
-
-#if defined(CONFIG_FIT)
- if (!images->legacy_hdr_valid) {
- fit_unsupported_reset("Plan 9");
- return 1;
- }
-#endif
-
- /* See README.plan9 */
- s = getenv("confaddr");
- if (s != NULL) {
- char *confaddr = (char *)simple_strtoul(s, NULL, 16);
-
- if (argc > 0) {
- copy_args(confaddr, argc, argv, '\n');
- } else {
- s = getenv("bootargs");
- if (s != NULL)
- strcpy(confaddr, s);
- }
- }
-
- entry_point = (void (*)(void))images->ep;
-
- printf("## Transferring control to Plan 9 (at address %08lx) ...\n",
- (ulong)entry_point);
-
- bootstage_mark(BOOTSTAGE_ID_RUN_OS);
-
- /*
- * Plan 9 Parameters:
- * None
- */
- (*entry_point)();
-
- return 1;
-}
-#endif /* CONFIG_BOOTM_PLAN9 */
-
-#if defined(CONFIG_BOOTM_VXWORKS) && \
- (defined(CONFIG_PPC) || defined(CONFIG_ARM))
-
-void do_bootvx_fdt(bootm_headers_t *images)
-{
-#if defined(CONFIG_OF_LIBFDT)
- int ret;
- char *bootline;
- ulong of_size = images->ft_len;
- char **of_flat_tree = &images->ft_addr;
- struct lmb *lmb = &images->lmb;
-
- if (*of_flat_tree) {
- boot_fdt_add_mem_rsv_regions(lmb, *of_flat_tree);
-
- ret = boot_relocate_fdt(lmb, of_flat_tree, &of_size);
- if (ret)
- return;
-
- ret = fdt_add_subnode(*of_flat_tree, 0, "chosen");
- if ((ret >= 0 || ret == -FDT_ERR_EXISTS)) {
- bootline = getenv("bootargs");
- if (bootline) {
- ret = fdt_find_and_setprop(*of_flat_tree,
- "/chosen", "bootargs",
- bootline,
- strlen(bootline) + 1, 1);
- if (ret < 0) {
- printf("## ERROR: %s : %s\n", __func__,
- fdt_strerror(ret));
- return;
- }
- }
- } else {
- printf("## ERROR: %s : %s\n", __func__,
- fdt_strerror(ret));
- return;
- }
- }
-#endif
-
- boot_prep_vxworks(images);
-
- bootstage_mark(BOOTSTAGE_ID_RUN_OS);
-
-#if defined(CONFIG_OF_LIBFDT)
- printf("## Starting vxWorks at 0x%08lx, device tree at 0x%08lx ...\n",
- (ulong)images->ep, (ulong)*of_flat_tree);
-#else
- printf("## Starting vxWorks at 0x%08lx\n", (ulong)images->ep);
-#endif
-
- boot_jump_vxworks(images);
-
- puts("## vxWorks terminated\n");
-}
-
-static int do_bootm_vxworks(int flag, int argc, char * const argv[],
- bootm_headers_t *images)
-{
- if (flag != BOOTM_STATE_OS_GO)
- return 0;
-
-#if defined(CONFIG_FIT)
- if (!images->legacy_hdr_valid) {
- fit_unsupported_reset("VxWorks");
- return 1;
- }
-#endif
-
- do_bootvx_fdt(images);
-
- return 1;
-}
-#endif
-
-#if defined(CONFIG_CMD_ELF)
-static int do_bootm_qnxelf(int flag, int argc, char * const argv[],
- bootm_headers_t *images)
-{
- char *local_args[2];
- char str[16];
-
- if (flag != BOOTM_STATE_OS_GO)
- return 0;
-
-#if defined(CONFIG_FIT)
- if (!images->legacy_hdr_valid) {
- fit_unsupported_reset("QNX");
- return 1;
- }
-#endif
-
- sprintf(str, "%lx", images->ep); /* write entry-point into string */
- local_args[0] = argv[0];
- local_args[1] = str; /* and provide it via the arguments */
- do_bootelf(NULL, 0, 2, local_args);
-
- return 1;
-}
-#endif
-
-#ifdef CONFIG_INTEGRITY
-static int do_bootm_integrity(int flag, int argc, char * const argv[],
- bootm_headers_t *images)
-{
- void (*entry_point)(void);
-
- if (flag != BOOTM_STATE_OS_GO)
- return 0;
-
-#if defined(CONFIG_FIT)
- if (!images->legacy_hdr_valid) {
- fit_unsupported_reset("INTEGRITY");
- return 1;
- }
-#endif
-
- entry_point = (void (*)(void))images->ep;
-
- printf("## Transferring control to INTEGRITY (at address %08lx) ...\n",
- (ulong)entry_point);
-
- bootstage_mark(BOOTSTAGE_ID_RUN_OS);
-
- /*
- * INTEGRITY Parameters:
- * None
- */
- (*entry_point)();
-
- return 1;
-}
-#endif
-
#ifdef CONFIG_CMD_BOOTZ
int __weak bootz_setup(ulong image, ulong *start, ulong *end)
* Handle the BOOTM_STATE_FINDOTHER state ourselves as we do not
* have a header that provide this informaiton.
*/
- if (bootm_find_ramdisk(flag, argc, argv))
+ if (bootm_find_ramdisk_fdt(flag, argc, argv))
return 1;
-#if defined(CONFIG_OF_LIBFDT)
- if (bootm_find_fdt(flag, argc, argv))
- return 1;
-#endif
-
return 0;
}
#include <command.h>
#include <ansi.h>
#include <menu.h>
-#include <hush.h>
#include <watchdog.h>
#include <malloc.h>
#include <linux/string.h>
*/
#include <common.h>
+#include <cli.h>
#include <config.h>
#include <command.h>
do {
value = get_dcr (dcrn);
printf ("%04x: %08lx", dcrn, value);
- nbytes = readline (" ? ");
+ nbytes = cli_readline(" ? ");
if (nbytes == 0) {
/*
* <CR> pressed as only input, don't modify current
#include <dm-demo.h>
#include <asm/io.h>
-struct device *demo_dev;
+struct udevice *demo_dev;
static int do_demo_hello(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
int do_demo_list(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- struct device *dev;
+ struct udevice *dev;
int i, ret;
puts("Demo uclass entries:\n");
ulong addr = CONFIG_SYS_LOAD_ADDR;
ulong cnt;
disk_partition_t info;
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
image_header_t *hdr;
+#endif
block_dev_desc_t *dev_desc;
#if defined(CONFIG_FIT)
bootstage_mark(BOOTSTAGE_ID_IDE_PART_READ);
switch (genimg_get_format((void *) addr)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
hdr = (image_header_t *) addr;
cnt = image_get_image_size(hdr);
break;
+#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
fit_hdr = (const void *) addr;
#include <s_record.h>
#include <net.h>
#include <ata.h>
+#include <asm/io.h>
#include <part.h>
#include <fat.h>
#include <fs.h>
disk_partition_t info;
int dev = 0;
int part = 1;
+ void *buf;
if (argc < 5)
return cmd_usage(cmdtp);
addr = simple_strtoul(argv[3], NULL, 16);
count = simple_strtoul(argv[5], NULL, 16);
- size = file_fat_write(argv[4], (void *)addr, count);
+ buf = map_sysmem(addr, count);
+ size = file_fat_write(argv[4], buf, count);
+ unmap_sysmem(buf);
if (size == -1) {
printf("\n** Unable to write \"%s\" from %s %d:%d **\n",
argv[4], argv[1], dev, part);
FD_GEO_STRUCT *pFG = (FD_GEO_STRUCT *)floppy_type;
FDC_COMMAND_STRUCT *pCMD = &cmd;
unsigned long addr,imsize;
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
image_header_t *hdr; /* used for fdc boot */
+#endif
unsigned char boot_drive;
int i,nrofblk;
#if defined(CONFIG_FIT)
}
switch (genimg_get_format ((void *)addr)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
hdr = (image_header_t *)addr;
image_print_contents (hdr);
imsize = image_get_image_size (hdr);
break;
+#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
fit_hdr = (const void *)addr;
initrd_end = simple_strtoul(argv[3], NULL, 16);
}
- fdt_chosen(working_fdt, 1);
- fdt_initrd(working_fdt, initrd_start, initrd_end, 1);
+ fdt_chosen(working_fdt);
+ fdt_initrd(working_fdt, initrd_start, initrd_end);
#if defined(CONFIG_FIT_SIGNATURE)
} else if (strncmp(argv[1], "che", 3) == 0) {
}
ret = fit_config_verify(working_fdt, cfg_noffset);
- if (ret == 1)
+ if (ret == 0)
return CMD_RET_SUCCESS;
else
return CMD_RET_FAILURE;
#if defined(CONFIG_CMD_FPGA_LOADMK)
case FPGA_LOADMK:
switch (genimg_get_format(fpga_data)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
{
image_header_t *hdr =
BIT_FULL);
}
break;
+#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
{
"unknown",
};
-static void show_gpio(struct device *dev, const char *bank_name, int offset)
+static void show_gpio(struct udevice *dev, const char *bank_name, int offset)
{
struct dm_gpio_ops *ops = gpio_get_ops(dev);
char buf[80];
static int do_gpio_status(const char *gpio_name)
{
- struct device *dev;
+ struct udevice *dev;
int newline = 0;
int ret;
*/
#include <common.h>
+#include <bootretry.h>
+#include <cli.h>
#include <command.h>
#include <edid.h>
#include <environment.h>
if (argc != 3)
return CMD_RET_USAGE;
-#ifdef CONFIG_BOOT_RETRY_TIME
- reset_cmd_timeout(); /* got a good command to get here */
-#endif
+ bootretry_reset_cmd_timeout(); /* got a good command to get here */
/*
* We use the last specified parameters, unless new ones are
* entered.
printf(" %08lx", data);
}
- nbytes = readline (" ? ");
+ nbytes = cli_readline(" ? ");
if (nbytes == 0) {
/*
* <CR> pressed as only input, don't modify current
if (incrflag)
addr += size;
nbytes = size;
-#ifdef CONFIG_BOOT_RETRY_TIME
- reset_cmd_timeout(); /* good enough to not time out */
-#endif
+ /* good enough to not time out */
+ bootretry_reset_cmd_timeout();
}
#ifdef CONFIG_BOOT_RETRY_TIME
else if (nbytes == -2)
data = be32_to_cpu(data);
nbytes = endp - console_buffer;
if (nbytes) {
-#ifdef CONFIG_BOOT_RETRY_TIME
/*
* good enough to not time out
*/
- reset_cmd_timeout();
-#endif
+ bootretry_reset_cmd_timeout();
if (i2c_write(chip, addr, alen, (uchar *)&data, size) != 0)
puts ("Error writing the chip.\n");
#ifdef CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS
--- /dev/null
+/*
+ * Copyright (c) 2014 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <command.h>
+#include <iotrace.h>
+
+static void do_print_stats(void)
+{
+ ulong start, size, offset, count;
+
+ printf("iotrace is %sabled\n", iotrace_get_enabled() ? "en" : "dis");
+ iotrace_get_buffer(&start, &size, &offset, &count);
+ printf("Start: %08lx\n", start);
+ printf("Size: %08lx\n", size);
+ printf("Offset: %08lx\n", offset);
+ printf("Output: %08lx\n", start + offset);
+ printf("Count: %08lx\n", count);
+ printf("CRC32: %08lx\n", (ulong)iotrace_get_checksum());
+}
+
+static int do_set_buffer(int argc, char * const argv[])
+{
+ ulong addr = 0, size = 0;
+
+ if (argc == 2) {
+ addr = simple_strtoul(*argv++, NULL, 16);
+ size = simple_strtoul(*argv++, NULL, 16);
+ } else if (argc != 0) {
+ return CMD_RET_USAGE;
+ }
+
+ iotrace_set_buffer(addr, size);
+
+ return 0;
+}
+
+int do_iotrace(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ const char *cmd = argc < 2 ? NULL : argv[1];
+
+ if (!cmd)
+ return cmd_usage(cmdtp);
+ switch (*cmd) {
+ case 'b':
+ return do_set_buffer(argc - 2, argv + 2);
+ case 'p':
+ iotrace_set_enabled(0);
+ break;
+ case 'r':
+ iotrace_set_enabled(1);
+ break;
+ case 's':
+ do_print_stats();
+ break;
+ default:
+ return CMD_RET_USAGE;
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ iotrace, 4, 1, do_iotrace,
+ "iotrace utility commands",
+ "stats - display iotrace stats\n"
+ "iotrace buffer <address> <size> - set iotrace buffer\n"
+ "iotrace pause - pause tracing\n"
+ "iotrace resume - resume tracing"
+);
l = simple_strtoul(s, NULL, 16);
}
- return (l & ((1 << (w * 8)) - 1));
+ return l & ((1UL << (w * 8)) - 1);
}
static char * evalstr(char *s)
sprintf(str_ptr, "%02x", sum[i]);
str_ptr += 2;
}
- str_ptr = '\0';
setenv(dest, str_output);
}
}
*/
#include <common.h>
+#include <bootretry.h>
+#include <cli.h>
#include <command.h>
#ifdef CONFIG_HAS_DATAFLASH
#include <dataflash.h>
if (argc != 2)
return CMD_RET_USAGE;
-#ifdef CONFIG_BOOT_RETRY_TIME
- reset_cmd_timeout(); /* got a good command to get here */
-#endif
+ bootretry_reset_cmd_timeout(); /* got a good command to get here */
/* We use the last specified parameters, unless new ones are
* entered.
*/
else
printf(" %02x", *((u8 *)ptr));
- nbytes = readline (" ? ");
+ nbytes = cli_readline(" ? ");
if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
/* <CR> pressed as only input, don't modify current
* location and move to next. "-" pressed will go back.
if (incrflag)
addr += nbytes ? -size : size;
nbytes = 1;
-#ifdef CONFIG_BOOT_RETRY_TIME
- reset_cmd_timeout(); /* good enough to not time out */
-#endif
+ /* good enough to not time out */
+ bootretry_reset_cmd_timeout();
}
#ifdef CONFIG_BOOT_RETRY_TIME
else if (nbytes == -2) {
#endif
nbytes = endp - console_buffer;
if (nbytes) {
-#ifdef CONFIG_BOOT_RETRY_TIME
/* good enough to not time out
*/
- reset_cmd_timeout();
-#endif
+ bootretry_reset_cmd_timeout();
if (size == 4)
*((u32 *)ptr) = i;
#ifdef CONFIG_SYS_SUPPORT_64BIT_DATA
printf("Bus Width: %d-bit\n", mmc->bus_width);
}
-static struct mmc *init_mmc_device(int dev)
+static struct mmc *init_mmc_device(int dev, bool force_init)
{
struct mmc *mmc;
mmc = find_mmc_device(dev);
printf("no mmc device at slot %x\n", dev);
return NULL;
}
+ if (force_init)
+ mmc->has_init = 0;
if (mmc_init(mmc))
return NULL;
return mmc;
}
}
- mmc = init_mmc_device(curr_device);
+ mmc = init_mmc_device(curr_device, false);
if (!mmc)
return CMD_RET_FAILURE;
if (flag == CMD_FLAG_REPEAT && !cp->repeatable)
return CMD_RET_SUCCESS;
- mmc = init_mmc_device(curr_device);
+ mmc = init_mmc_device(curr_device, false);
if (!mmc)
return CMD_RET_FAILURE;
blk = simple_strtoul(argv[2], NULL, 16);
cnt = simple_strtoul(argv[3], NULL, 16);
- mmc = init_mmc_device(curr_device);
+ mmc = init_mmc_device(curr_device, false);
if (!mmc)
return CMD_RET_FAILURE;
blk = simple_strtoul(argv[2], NULL, 16);
cnt = simple_strtoul(argv[3], NULL, 16);
- mmc = init_mmc_device(curr_device);
+ mmc = init_mmc_device(curr_device, false);
if (!mmc)
return CMD_RET_FAILURE;
blk = simple_strtoul(argv[1], NULL, 16);
cnt = simple_strtoul(argv[2], NULL, 16);
- mmc = init_mmc_device(curr_device);
+ mmc = init_mmc_device(curr_device, false);
if (!mmc)
return CMD_RET_FAILURE;
{
struct mmc *mmc;
- mmc = find_mmc_device(curr_device);
- if (!mmc) {
- printf("no mmc device at slot %x\n", curr_device);
+ mmc = init_mmc_device(curr_device, true);
+ if (!mmc)
return CMD_RET_FAILURE;
- }
-
- mmc->has_init = 0;
- if (mmc_init(mmc))
- return CMD_RET_FAILURE;
return CMD_RET_SUCCESS;
}
static int do_mmc_part(cmd_tbl_t *cmdtp, int flag,
block_dev_desc_t *mmc_dev;
struct mmc *mmc;
- mmc = init_mmc_device(curr_device);
+ mmc = init_mmc_device(curr_device, false);
if (!mmc)
return CMD_RET_FAILURE;
static int do_mmc_dev(cmd_tbl_t *cmdtp, int flag,
int argc, char * const argv[])
{
- int dev, part = -1, ret;
+ int dev, part = 0, ret;
struct mmc *mmc;
if (argc == 1) {
return CMD_RET_USAGE;
}
- mmc = init_mmc_device(dev);
+ mmc = init_mmc_device(dev, true);
if (!mmc)
return CMD_RET_FAILURE;
- if (part != -1) {
- ret = mmc_select_hwpart(dev, part);
- printf("switch to partitions #%d, %s\n",
- part, (!ret) ? "OK" : "ERROR");
- if (ret)
- return 1;
- }
+ ret = mmc_select_hwpart(dev, part);
+ printf("switch to partitions #%d, %s\n",
+ part, (!ret) ? "OK" : "ERROR");
+ if (ret)
+ return 1;
+
curr_device = dev;
if (mmc->part_config == MMCPART_NOAVAILABLE)
printf("mmc%d is current device\n", curr_device);
reset = simple_strtoul(argv[3], NULL, 10);
mode = simple_strtoul(argv[4], NULL, 10);
- mmc = init_mmc_device(dev);
+ mmc = init_mmc_device(dev, false);
if (!mmc)
return CMD_RET_FAILURE;
bootsize = simple_strtoul(argv[2], NULL, 10);
rpmbsize = simple_strtoul(argv[3], NULL, 10);
- mmc = init_mmc_device(dev);
+ mmc = init_mmc_device(dev, false);
if (!mmc)
return CMD_RET_FAILURE;
part_num = simple_strtoul(argv[3], NULL, 10);
access = simple_strtoul(argv[4], NULL, 10);
- mmc = init_mmc_device(dev);
+ mmc = init_mmc_device(dev, false);
if (!mmc)
return CMD_RET_FAILURE;
return CMD_RET_USAGE;
}
- mmc = init_mmc_device(dev);
+ mmc = init_mmc_device(dev, false);
if (!mmc)
return CMD_RET_FAILURE;
int r;
char *s;
size_t cnt;
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
image_header_t *hdr;
+#endif
#if defined(CONFIG_FIT)
const void *fit_hdr = NULL;
#endif
bootstage_mark(BOOTSTAGE_ID_NAND_HDR_READ);
switch (genimg_get_format ((void *)addr)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
hdr = (image_header_t *)addr;
cnt = image_get_image_size (hdr);
break;
+#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
fit_hdr = (const void *)addr;
*/
#include <common.h>
+#include <cli.h>
#include <command.h>
#include <environment.h>
#include <search.h>
return 1;
/* prompt for input */
- len = readline(message);
+ len = cli_readline(message);
if (size < len)
console_buffer[size] = '\0';
else
buffer[0] = '\0';
- if (readline_into_buffer("edit: ", buffer, 0) < 0)
+ if (cli_readline_into_buffer("edit: ", buffer, 0) < 0)
return 1;
return setenv(argv[1], buffer);
*/
#include <common.h>
+#include <bootretry.h>
+#include <cli.h>
#include <command.h>
#include <asm/processor.h>
#include <asm/io.h>
printf(" %02x", val1);
}
- nbytes = readline (" ? ");
+ nbytes = cli_readline(" ? ");
if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
/* <CR> pressed as only input, don't modify current
* location and move to next. "-" pressed will go back.
if (incrflag)
addr += nbytes ? -size : size;
nbytes = 1;
-#ifdef CONFIG_BOOT_RETRY_TIME
- reset_cmd_timeout(); /* good enough to not time out */
-#endif
+ /* good enough to not time out */
+ bootretry_reset_cmd_timeout();
}
#ifdef CONFIG_BOOT_RETRY_TIME
else if (nbytes == -2) {
i = simple_strtoul(console_buffer, &endp, 16);
nbytes = endp - console_buffer;
if (nbytes) {
-#ifdef CONFIG_BOOT_RETRY_TIME
/* good enough to not time out
*/
- reset_cmd_timeout();
-#endif
+ bootretry_reset_cmd_timeout();
pci_cfg_write (bdf, addr, size, i);
if (incrflag)
addr += size;
U_BOOT_CMD(
sb, 8, 1, do_sandbox,
"Miscellaneous sandbox commands",
- "load host
<dev> <addr> <filename> [<bytes> <offset>] - "
+ "load host
fs - <addr> <filename> [<bytes> <offset>] - "
"load a file from host\n"
- "sb ls host <filename> - list files on host\n"
- "sb save host
<dev> <filename> <addr> <bytes> [<offset>] - "
+ "sb ls hostfs - <filename> - list files on host\n"
+ "sb save host
fs - <filename> <addr> <bytes> [<offset>] - "
"save a file to host\n"
"sb bind <dev> [<filename>] - bind \"host\" device to file\n"
- "sb info [<dev>] - show device binding & info"
+ "sb info [<dev>] - show device binding & info\n"
+ "sb commands use the \"hostfs\" device. The \"host\" device is used\n"
+ "with standard IO commands such as fatls or ext2load"
);
#include <common.h>
#include <command.h>
#include <hash.h>
-#include <sha1.h>
+#include <u-boot/sha1.h>
int do_sha1sum(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
source (ulong addr, const char *fit_uname)
{
ulong len;
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
const image_header_t *hdr;
+#endif
ulong *data;
int verify;
void *buf;
buf = map_sysmem(addr, 0);
switch (genimg_get_format(buf)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
hdr = buf;
*/
while (*data++);
break;
+#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
if (fit_uname == NULL) {
{
ulong addr = load_addr;
ulong dest = 0;
- ulong data, len, count;
+ ulong data, len;
int verify;
int part = 0;
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
+ ulong count;
image_header_t *hdr = NULL;
+#endif
#if defined(CONFIG_FIT)
const char *uname = NULL;
const void* fit_hdr;
}
switch (genimg_get_format((void *)addr)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
printf("## Copying part %d from legacy image "
image_multi_getimg(hdr, part, &data, &len);
break;
+#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
if (uname == NULL) {
}
break;
#endif
-#if defined(CONFIG_BZIP2)
+#if defined(CONFIG_BZIP2) && defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IH_COMP_BZIP2:
{
int i;
#ifdef CONFIG_ENV_OFFSET_REDUND
int env_init(void)
{
+#ifdef ENV_IS_EMBEDDED
ulong len, crc[2], crc_tmp;
unsigned int off, off_env[2];
uchar buf[64], flags[2];
gd->env_addr = off_env[1] + offsetof(env_t, data);
else if (gd->env_valid == 1)
gd->env_addr = off_env[0] + offsetof(env_t, data);
-
+#else
+ gd->env_addr = (ulong)&default_environment[0];
+ gd->env_valid = 1;
+#endif
return 0;
}
#else
int env_init(void)
{
+#ifdef ENV_IS_EMBEDDED
ulong crc, len, new;
unsigned off;
uchar buf[64];
gd->env_addr = 0;
gd->env_valid = 0;
}
-
+#else
+ gd->env_addr = (ulong)&default_environment[0];
+ gd->env_valid = 1;
+#endif
return 0;
}
#endif
* a seperate section. Note that ENV_CRC is only defined when building
* U-Boot itself.
*/
-#if (defined(CONFIG_SYS_USE_PPCENV) || defined(CONFIG_NAND_U_BOOT)) && \
+#if defined(CONFIG_SYS_USE_PPCENV) && \
defined(ENV_CRC) /* Environment embedded in U-Boot .ppcenv section */
/* XXX - This only works with GNU C */
# define __PPCENV__ __attribute__ ((section(".ppcenv")))
#include <fdt_support.h>
#include <exports.h>
-/*
- * Global data (for the gd->bd)
- */
-DECLARE_GLOBAL_DATA_PTR;
-
/*
* Get cells len in bytes
* if #NNNN-cells property is 2 then len is 8
* otherwise len is 4
*/
-static int get_cells_len(void *blob, char *nr_cells_name)
+static int get_cells_len(const void *fdt, const char *nr_cells_name)
{
const fdt32_t *cell;
- cell = fdt_getprop(blob, 0, nr_cells_name, NULL);
+ cell = fdt_getprop(fdt, 0, nr_cells_name, NULL);
if (cell && fdt32_to_cpu(*cell) == 2)
return 8;
return 4;
}
-/*
- * Write a 4 or 8 byte big endian cell
- */
-static void write_cell(u8 *addr, u64 val, int size)
-{
- int shift = (size - 1) * 8;
- while (size-- > 0) {
- *addr++ = (val >> shift) & 0xff;
- shift -= 8;
- }
-}
-
/**
* fdt_getprop_u32_default_node - Return a node's property or a default
*
return fdt_setprop(fdt, nodeoff, prop, val, len);
}
-#ifdef CONFIG_OF_STDOUT_VIA_ALIAS
+/**
+ * fdt_find_or_add_subnode - find or possibly add a subnode of a given node
+ * @fdt: pointer to the device tree blob
+ * @parentoffset: structure block offset of a node
+ * @name: name of the subnode to locate
+ *
+ * fdt_subnode_offset() finds a subnode of the node with a given name.
+ * If the subnode does not exist, it will be created.
+ */
+static int fdt_find_or_add_subnode(void *fdt, int parentoffset,
+ const char *name)
+{
+ int offset;
+
+ offset = fdt_subnode_offset(fdt, parentoffset, name);
+
+ if (offset == -FDT_ERR_NOTFOUND)
+ offset = fdt_add_subnode(fdt, parentoffset, name);
-#ifdef CONFIG_CONS_INDEX
+ if (offset < 0)
+ printf("%s: %s: %s\n", __func__, name, fdt_strerror(offset));
+
+ return offset;
+}
+
+/* rename to CONFIG_OF_STDOUT_PATH ? */
+#if defined(OF_STDOUT_PATH)
+static int fdt_fixup_stdout(void *fdt, int chosenoff)
+{
+ return fdt_setprop(fdt, chosenoff, "linux,stdout-path",
+ OF_STDOUT_PATH, strlen(OF_STDOUT_PATH) + 1);
+}
+#elif defined(CONFIG_OF_STDOUT_VIA_ALIAS) && defined(CONFIG_CONS_INDEX)
static void fdt_fill_multisername(char *sername, size_t maxlen)
{
const char *outname = stdio_devices[stdout]->name;
if (strcmp(outname + 1, "serial") > 0)
strncpy(sername, outname + 1, maxlen);
}
-#endif
static int fdt_fixup_stdout(void *fdt, int chosenoff)
{
- int err = 0;
-#ifdef CONFIG_CONS_INDEX
- int node;
+ int err;
+ int aliasoff;
char sername[9] = { 0 };
- const char *path;
+ const void *path;
+ int len;
+ char tmp[256]; /* long enough */
fdt_fill_multisername(sername, sizeof(sername) - 1);
if (!sername[0])
sprintf(sername, "serial%d", CONFIG_CONS_INDEX - 1);
- err = node = fdt_path_offset(fdt, "/aliases");
- if (node >= 0) {
- int len;
- path = fdt_getprop(fdt, node, sername, &len);
- if (path) {
- char *p = malloc(len);
- err = -FDT_ERR_NOSPACE;
- if (p) {
- memcpy(p, path, len);
- err = fdt_setprop(fdt, chosenoff,
- "linux,stdout-path", p, len);
- free(p);
- }
- } else {
- err = len;
- }
+ aliasoff = fdt_path_offset(fdt, "/aliases");
+ if (aliasoff < 0) {
+ err = aliasoff;
+ goto error;
}
-#endif
+
+ path = fdt_getprop(fdt, aliasoff, sername, &len);
+ if (!path) {
+ err = len;
+ goto error;
+ }
+
+ /* fdt_setprop may break "path" so we copy it to tmp buffer */
+ memcpy(tmp, path, len);
+
+ err = fdt_setprop(fdt, chosenoff, "linux,stdout-path", tmp, len);
+error:
if (err < 0)
printf("WARNING: could not set linux,stdout-path %s.\n",
- fdt_strerror(err));
+ fdt_strerror(err));
return err;
}
+#else
+static int fdt_fixup_stdout(void *fdt, int chosenoff)
+{
+ return 0;
+}
#endif
-int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force)
+static inline int fdt_setprop_uxx(void *fdt, int nodeoffset, const char *name,
+ uint64_t val, int is_u64)
+{
+ if (is_u64)
+ return fdt_setprop_u64(fdt, nodeoffset, name, val);
+ else
+ return fdt_setprop_u32(fdt, nodeoffset, name, (uint32_t)val);
+}
+
+
+int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end)
{
- int nodeoffset, addr_cell_len;
+ int nodeoffset;
int err, j, total;
- fdt64_t tmp;
- const char *path;
+ int is_u64;
uint64_t addr, size;
- /* Find the "chosen" node. */
- nodeoffset = fdt_path_offset (fdt, "/chosen");
+ /* just return if the size of initrd is zero */
+ if (initrd_start == initrd_end)
+ return 0;
- /* If there is no "chosen" node in the blob return */
- if (nodeoffset < 0) {
- printf("fdt_initrd: %s\n", fdt_strerror(nodeoffset));
+ /* find or create "/chosen" node. */
+ nodeoffset = fdt_find_or_add_subnode(fdt, 0, "chosen");
+ if (nodeoffset < 0)
return nodeoffset;
- }
-
- /* just return if initrd_start/end aren't valid */
- if ((initrd_start == 0) || (initrd_end == 0))
- return 0;
total = fdt_num_mem_rsv(fdt);
return err;
}
- addr_cell_len = get_cells_len(fdt, "#address-cells");
+ is_u64 = (get_cells_len(fdt, "#address-cells") == 8);
- path = fdt_getprop(fdt, nodeoffset, "linux,initrd-start", NULL);
- if ((path == NULL) || force) {
- write_cell((u8 *)&tmp, initrd_start, addr_cell_len);
- err = fdt_setprop(fdt, nodeoffset,
- "linux,initrd-start", &tmp, addr_cell_len);
- if (err < 0) {
- printf("WARNING: "
- "could not set linux,initrd-start %s.\n",
- fdt_strerror(err));
- return err;
- }
- write_cell((u8 *)&tmp, initrd_end, addr_cell_len);
- err = fdt_setprop(fdt, nodeoffset,
- "linux,initrd-end", &tmp, addr_cell_len);
- if (err < 0) {
- printf("WARNING: could not set linux,initrd-end %s.\n",
- fdt_strerror(err));
+ err = fdt_setprop_uxx(fdt, nodeoffset, "linux,initrd-start",
+ (uint64_t)initrd_start, is_u64);
- return err;
- }
+ if (err < 0) {
+ printf("WARNING: could not set linux,initrd-start %s.\n",
+ fdt_strerror(err));
+ return err;
+ }
+
+ err = fdt_setprop_uxx(fdt, nodeoffset, "linux,initrd-end",
+ (uint64_t)initrd_end, is_u64);
+
+ if (err < 0) {
+ printf("WARNING: could not set linux,initrd-end %s.\n",
+ fdt_strerror(err));
+
+ return err;
}
return 0;
}
-int fdt_chosen(void *fdt, int force)
+int fdt_chosen(void *fdt)
{
int nodeoffset;
int err;
char *str; /* used to set string properties */
- const char *path;
err = fdt_check_header(fdt);
if (err < 0) {
return err;
}
- /*
- * Find the "chosen" node.
- */
- nodeoffset = fdt_path_offset (fdt, "/chosen");
-
- /*
- * If there is no "chosen" node in the blob, create it.
- */
- if (nodeoffset < 0) {
- /*
- * Create a new node "/chosen" (offset 0 is root level)
- */
- nodeoffset = fdt_add_subnode(fdt, 0, "chosen");
- if (nodeoffset < 0) {
- printf("WARNING: could not create /chosen %s.\n",
- fdt_strerror(nodeoffset));
- return nodeoffset;
- }
- }
+ /* find or create "/chosen" node. */
+ nodeoffset = fdt_find_or_add_subnode(fdt, 0, "chosen");
+ if (nodeoffset < 0)
+ return nodeoffset;
- /*
- * Create /chosen properites that don't exist in the fdt.
- * If the property exists, update it only if the "force" parameter
- * is true.
- */
str = getenv("bootargs");
- if (str != NULL) {
- path = fdt_getprop(fdt, nodeoffset, "bootargs", NULL);
- if ((path == NULL) || force) {
- err = fdt_setprop(fdt, nodeoffset,
- "bootargs", str, strlen(str)+1);
- if (err < 0)
- printf("WARNING: could not set bootargs %s.\n",
- fdt_strerror(err));
+ if (str) {
+ err = fdt_setprop(fdt, nodeoffset, "bootargs", str,
+ strlen(str) + 1);
+ if (err < 0) {
+ printf("WARNING: could not set bootargs %s.\n",
+ fdt_strerror(err));
+ return err;
}
}
-#ifdef CONFIG_OF_STDOUT_VIA_ALIAS
- path = fdt_getprop(fdt, nodeoffset, "linux,stdout-path", NULL);
- if ((path == NULL) || force)
- err = fdt_fixup_stdout(fdt, nodeoffset);
-#endif
-
-#ifdef OF_STDOUT_PATH
- path = fdt_getprop(fdt, nodeoffset, "linux,stdout-path", NULL);
- if ((path == NULL) || force) {
- err = fdt_setprop(fdt, nodeoffset,
- "linux,stdout-path", OF_STDOUT_PATH, strlen(OF_STDOUT_PATH)+1);
- if (err < 0)
- printf("WARNING: could not set linux,stdout-path %s.\n",
- fdt_strerror(err));
- }
-#endif
-
- return err;
+ return fdt_fixup_stdout(fdt, nodeoffset);
}
void do_fixup_by_path(void *fdt, const char *path, const char *prop,
do_fixup_by_compat(fdt, compat, prop, &tmp, 4, create);
}
+/*
+ * fdt_pack_reg - pack address and size array into the "reg"-suitable stream
+ */
+static int fdt_pack_reg(const void *fdt, void *buf, uint64_t *address,
+ uint64_t *size, int n)
+{
+ int i;
+ int address_len = get_cells_len(fdt, "#address-cells");
+ int size_len = get_cells_len(fdt, "#size-cells");
+ char *p = buf;
+
+ for (i = 0; i < n; i++) {
+ if (address_len == 8)
+ *(fdt64_t *)p = cpu_to_fdt64(address[i]);
+ else
+ *(fdt32_t *)p = cpu_to_fdt32(address[i]);
+ p += address_len;
+
+ if (size_len == 8)
+ *(fdt64_t *)p = cpu_to_fdt64(size[i]);
+ else
+ *(fdt32_t *)p = cpu_to_fdt32(size[i]);
+ p += size_len;
+ }
+
+ return p - (char *)buf;
+}
+
#ifdef CONFIG_NR_DRAM_BANKS
#define MEMORY_BANKS_MAX CONFIG_NR_DRAM_BANKS
#else
int fdt_fixup_memory_banks(void *blob, u64 start[], u64 size[], int banks)
{
int err, nodeoffset;
- int addr_cell_len, size_cell_len, len;
+ int len;
u8 tmp[MEMORY_BANKS_MAX * 16]; /* Up to 64-bit address + 64-bit size */
- int bank;
if (banks > MEMORY_BANKS_MAX) {
printf("%s: num banks %d exceeds hardcoded limit %d."
return err;
}
- /* update, or add and update /memory node */
- nodeoffset = fdt_path_offset(blob, "/memory");
- if (nodeoffset < 0) {
- nodeoffset = fdt_add_subnode(blob, 0, "memory");
- if (nodeoffset < 0) {
- printf("WARNING: could not create /memory: %s.\n",
- fdt_strerror(nodeoffset));
+ /* find or create "/memory" node. */
+ nodeoffset = fdt_find_or_add_subnode(blob, 0, "memory");
+ if (nodeoffset < 0)
return nodeoffset;
- }
- }
+
err = fdt_setprop(blob, nodeoffset, "device_type", "memory",
sizeof("memory"));
if (err < 0) {
return err;
}
- addr_cell_len = get_cells_len(blob, "#address-cells");
- size_cell_len = get_cells_len(blob, "#size-cells");
-
- for (bank = 0, len = 0; bank < banks; bank++) {
- write_cell(tmp + len, start[bank], addr_cell_len);
- len += addr_cell_len;
-
- write_cell(tmp + len, size[bank], size_cell_len);
- len += size_cell_len;
- }
+ len = fdt_pack_reg(blob, tmp, start, size, banks);
err = fdt_setprop(blob, nodeoffset, "reg", tmp, len);
if (err < 0) {
if (node < 0)
return;
+ if (!getenv("ethaddr")) {
+ if (getenv("usbethaddr")) {
+ strcpy(mac, "usbethaddr");
+ } else {
+ debug("No ethernet MAC Address defined\n");
+ return;
+ }
+ } else {
+ strcpy(mac, "ethaddr");
+ }
+
i = 0;
- strcpy(mac, "ethaddr");
while ((tmp = getenv(mac)) != NULL) {
sprintf(enet, "ethernet%d", i);
path = fdt_getprop(fdt, node, enet, NULL);
#include <malloc.h>
#include <hw_sha.h>
#include <hash.h>
-#include <sha1.h>
-#include <sha256.h>
+#include <u-boot/sha1.h>
+#include <u-boot/sha256.h>
#include <asm/io.h>
#include <asm/errno.h>
* @allow_env_vars: non-zero to permit storing the result to an
* variable environment
*/
-static void store_result(struct hash_algo *algo, const u8 *sum,
+static void store_result(struct hash_algo *algo, const uint8_t *sum,
const char *dest, int allow_env_vars)
{
unsigned int i;
sprintf(str_ptr, "%02x", sum[i]);
str_ptr += 2;
}
- str_ptr = '\0';
+ *str_ptr = '\0';
setenv(dest, str_output);
} else {
ulong addr;
* address, and the * prefix is not expected.
* @return 0 if ok, non-zero on error
*/
-static int parse_verify_sum(struct hash_algo *algo, char *verify_str, u8 *vsum,
- int allow_env_vars)
+static int parse_verify_sum(struct hash_algo *algo, char *verify_str,
+ uint8_t *vsum, int allow_env_vars)
{
int env_var = 0;
return -EPROTONOSUPPORT;
}
-static void show_hash(struct hash_algo *algo, ulong addr, ulong len,
- u8 *output)
+void hash_show(struct hash_algo *algo, ulong addr, ulong len, uint8_t *output)
{
int i;
if (multi_hash()) {
struct hash_algo *algo;
- u8 output[HASH_MAX_DIGEST_SIZE];
- u8 vsum[HASH_MAX_DIGEST_SIZE];
+ uint8_t output[HASH_MAX_DIGEST_SIZE];
+ uint8_t vsum[HASH_MAX_DIGEST_SIZE];
void *buf;
if (hash_lookup_algo(algo_name, &algo)) {
if (memcmp(output, vsum, algo->digest_size) != 0) {
int i;
- show_hash(algo, addr, len, output);
+ hash_show(algo, addr, len, output);
printf(" != ");
for (i = 0; i < algo->digest_size; i++)
printf("%02x", vsum[i]);
return 1;
}
} else {
- show_hash(algo, addr, len, output);
+ hash_show(algo, addr, len, output);
printf("\n");
if (argc) {
puts(" - must RESET the board to recover.\n");
}
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
static const image_header_t *image_get_fdt(ulong fdt_addr)
{
const image_header_t *fdt_hdr = map_sysmem(fdt_addr, 0);
}
return fdt_hdr;
}
+#endif
/**
* boot_fdt_add_mem_rsv_regions - Mark the memreserve sections as unusable
int boot_get_fdt(int flag, int argc, char * const argv[], uint8_t arch,
bootm_headers_t *images, char **of_flat_tree, ulong *of_size)
{
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
const image_header_t *fdt_hdr;
+ ulong load, load_end;
+ ulong image_start, image_data, image_end;
+#endif
ulong fdt_addr;
char *fdt_blob = NULL;
- ulong image_start, image_data, image_end;
- ulong load, load_end;
void *buf;
#if defined(CONFIG_FIT)
const char *fit_uname_config = images->fit_uname_cfg;
*/
buf = map_sysmem(fdt_addr, 0);
switch (genimg_get_format(buf)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
/* verify fdt_addr points to a valid image header */
printf("## Flattened Device Tree from Legacy Image at %08lx\n",
fdt_addr = load;
break;
+#endif
case IMAGE_FORMAT_FIT:
/*
* This case will catch both: new uImage format
ulong load, len;
fdt_noffset = fit_image_load(images,
- FIT_FDT_PROP,
fdt_addr, &fit_uname_fdt,
&fit_uname_config,
arch, IH_TYPE_FLATDT,
ulong *initrd_end = &images->initrd_end;
int ret;
- if (fdt_chosen(blob, 1) < 0) {
+ if (fdt_chosen(blob) < 0) {
puts("ERROR: /chosen node create failed");
puts(" - must RESET the board to recover.\n");
return -1;
/* Create a new LMB reservation */
lmb_reserve(lmb, (ulong)blob, of_size);
- fdt_initrd(blob, *initrd_start, *initrd_end, 1);
+ fdt_initrd(blob, *initrd_start, *initrd_end);
if (!ft_verify_fdt(blob))
return -1;
#endif /* !USE_HOSTCC*/
#include <bootstage.h>
-#include <sha1.h>
-#include <sha256.h>
#include <u-boot/crc.h>
#include <u-boot/md5.h>
+#include <u-boot/sha1.h>
+#include <u-boot/sha256.h>
/*****************************************************************************/
/* New uImage format routines */
*
* returns:
* 0, on success
- * -1, on property read failure
+ * -ENOSPC if no space in device tree, -1 for other error
*/
int fit_set_timestamp(void *fit, int noffset, time_t timestamp)
{
printf("Can't set '%s' property for '%s' node (%s)\n",
FIT_TIMESTAMP_PROP, fit_get_name(fit, noffset, NULL),
fdt_strerror(ret));
- return -1;
+ return ret == -FDT_ERR_NOSPACE ? -ENOSPC : -1;
}
return 0;
return noffset;
}
-int fit_image_load(bootm_headers_t *images, const char *prop_name, ulong addr,
+/**
+ * fit_get_image_type_property() - get property name for IH_TYPE_...
+ *
+ * @return the properly name where we expect to find the image in the
+ * config node
+ */
+static const char *fit_get_image_type_property(int type)
+{
+ /*
+ * This is sort-of available in the uimage_type[] table in image.c
+ * but we don't have access to the sohrt name, and "fdt" is different
+ * anyway. So let's just keep it here.
+ */
+ switch (type) {
+ case IH_TYPE_FLATDT:
+ return FIT_FDT_PROP;
+ case IH_TYPE_KERNEL:
+ return FIT_KERNEL_PROP;
+ case IH_TYPE_RAMDISK:
+ return FIT_RAMDISK_PROP;
+ }
+
+ return "unknown";
+}
+
+int fit_image_load(bootm_headers_t *images, ulong addr,
const char **fit_unamep, const char **fit_uname_configp,
int arch, int image_type, int bootstage_id,
enum fit_load_op load_op, ulong *datap, ulong *lenp)
size_t size;
int type_ok, os_ok;
ulong load, data, len;
+ const char *prop_name;
int ret;
fit = map_sysmem(addr, 0);
fit_uname = fit_unamep ? *fit_unamep : NULL;
fit_uname_config = fit_uname_configp ? *fit_uname_configp : NULL;
+ prop_name = fit_get_image_type_property(image_type);
printf("## Loading %s from FIT Image at %08lx ...\n", prop_name, addr);
bootstage_mark(bootstage_id + BOOTSTAGE_SUB_FORMAT);
images->fit_uname_cfg = fit_uname_config;
if (IMAGE_ENABLE_VERIFY && images->verify) {
puts(" Verifying Hash Integrity ... ");
- if (!fit_config_verify(fit, cfg_noffset)) {
+ if (fit_config_verify(fit, cfg_noffset)) {
puts("Bad Data Hash\n");
bootstage_error(bootstage_id +
BOOTSTAGE_SUB_HASH);
}
bootstage_mark(bootstage_id + BOOTSTAGE_SUB_CHECK_ARCH);
+#ifndef USE_HOSTCC
if (!fit_image_check_target_arch(fit, noffset)) {
puts("Unsupported Architecture\n");
bootstage_error(bootstage_id + BOOTSTAGE_SUB_CHECK_ARCH);
return -ENOEXEC;
}
-
+#endif
if (image_type == IH_TYPE_FLATDT &&
!fit_image_check_comp(fit, noffset, IH_COMP_NONE)) {
puts("FDT image is compressed");
/*
* Work-around for eldk-4.2 which gives this warning if we try to
- * case in the unmap_sysmem() call:
+ * cast in the unmap_sysmem() call:
* warning: initialization discards qualifiers from pointer target type
*/
{
DECLARE_GLOBAL_DATA_PTR;
#endif /* !USE_HOSTCC*/
#include <image.h>
-#include <rsa.h>
-#include <rsa-checksum.h>
+#include <u-boot/rsa.h>
+#include <u-boot/rsa-checksum.h>
#define IMAGE_MAX_HASHED_NODES 100
int fit_config_verify(const void *fit, int conf_noffset)
{
- return !fit_config_verify_required_sigs(fit, conf_noffset,
- gd_fdt_blob());
+ return fit_config_verify_required_sigs(fit, conf_noffset,
+ gd_fdt_blob());
}
#endif
#include <u-boot/md5.h>
-#include <sha1.h>
+#include <u-boot/sha1.h>
#include <asm/errno.h>
#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
static const image_header_t *image_get_ramdisk(ulong rd_addr, uint8_t arch,
int verify);
+#endif
#else
#include "mkimage.h"
#include <u-boot/md5.h>
#ifndef USE_HOSTCC
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
/**
* image_get_ramdisk - get and verify ramdisk image
* @rd_addr: ramdisk image start address
return rd_hdr;
}
+#endif
#endif /* !USE_HOSTCC */
/*****************************************************************************/
*/
int genimg_get_format(const void *img_addr)
{
- ulong format = IMAGE_FORMAT_INVALID;
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
const image_header_t *hdr;
hdr = (const image_header_t *)img_addr;
if (image_check_magic(hdr))
- format = IMAGE_FORMAT_LEGACY;
+ return IMAGE_FORMAT_LEGACY;
+#endif
#if defined(CONFIG_FIT) || defined(CONFIG_OF_LIBFDT)
- else if (fdt_check_header(img_addr) == 0)
- format = IMAGE_FORMAT_FIT;
+ if (fdt_check_header(img_addr) == 0)
+ return IMAGE_FORMAT_FIT;
#endif
#ifdef CONFIG_ANDROID_BOOT_IMAGE
- else if (android_image_check_header(img_addr) == 0)
- format = IMAGE_FORMAT_ANDROID;
+ if (android_image_check_header(img_addr) == 0)
+ return IMAGE_FORMAT_ANDROID;
#endif
- return format;
+ return IMAGE_FORMAT_INVALID;
}
/**
/* get data size */
switch (genimg_get_format(buf)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
d_size = image_get_data_size(buf);
debug(" Legacy format image found at 0x%08lx, "
"size 0x%08lx\n",
ram_addr, d_size);
break;
+#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
d_size = fit_get_size(buf) - h_size;
{
ulong rd_addr, rd_load;
ulong rd_data, rd_len;
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
const image_header_t *rd_hdr;
+#endif
void *buf;
#ifdef CONFIG_SUPPORT_RAW_INITRD
char *end;
*/
buf = map_sysmem(rd_addr, 0);
switch (genimg_get_format(buf)) {
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
case IMAGE_FORMAT_LEGACY:
printf("## Loading init Ramdisk from Legacy "
"Image at %08lx ...\n", rd_addr);
rd_len = image_get_data_size(rd_hdr);
rd_load = image_get_load(rd_hdr);
break;
+#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
- rd_noffset = fit_image_load(images, FIT_RAMDISK_PROP,
+ rd_noffset = fit_image_load(images,
rd_addr, &fit_uname_ramdisk,
&fit_uname_config, arch,
IH_TYPE_RAMDISK,
--- /dev/null
+/*
+ * Copyright (c) 2014 Google, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#define IOTRACE_IMPL
+
+#include <common.h>
+#include <asm/io.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Support up to the machine word length for now */
+typedef ulong iovalue_t;
+
+enum iotrace_flags {
+ IOT_8 = 0,
+ IOT_16,
+ IOT_32,
+
+ IOT_READ = 0 << 3,
+ IOT_WRITE = 1 << 3,
+};
+
+/**
+ * struct iotrace_record - Holds a single I/O trace record
+ *
+ * @flags: I/O access type
+ * @addr: Address of access
+ * @value: Value written or read
+ */
+struct iotrace_record {
+ enum iotrace_flags flags;
+ phys_addr_t addr;
+ iovalue_t value;
+};
+
+/**
+ * struct iotrace - current trace status and checksum
+ *
+ * @start: Start address of iotrace buffer
+ * @size: Size of iotrace buffer in bytes
+ * @offset: Current write offset into iotrace buffer
+ * @crc32: Current value of CRC chceksum of trace records
+ * @enabled: true if enabled, false if disabled
+ */
+static struct iotrace {
+ ulong start;
+ ulong size;
+ ulong offset;
+ u32 crc32;
+ bool enabled;
+} iotrace;
+
+static void add_record(int flags, const void *ptr, ulong value)
+{
+ struct iotrace_record srec, *rec = &srec;
+
+ /*
+ * We don't support iotrace before relocation. Since the trace buffer
+ * is set up by a command, it can't be enabled at present. To change
+ * this we would need to set the iotrace buffer at build-time. See
+ * lib/trace.c for how this might be done if you are interested.
+ */
+ if (!(gd->flags & GD_FLG_RELOC) || !iotrace.enabled)
+ return;
+
+ /* Store it if there is room */
+ if (iotrace.offset + sizeof(*rec) < iotrace.size) {
+ rec = (struct iotrace_record *)map_sysmem(
+ iotrace.start + iotrace.offset,
+ sizeof(value));
+ }
+
+ rec->flags = flags;
+ rec->addr = map_to_sysmem(ptr);
+ rec->value = value;
+
+ /* Update our checksum */
+ iotrace.crc32 = crc32(iotrace.crc32, (unsigned char *)rec,
+ sizeof(*rec));
+
+ iotrace.offset += sizeof(struct iotrace_record);
+}
+
+u32 iotrace_readl(const void *ptr)
+{
+ u32 v;
+
+ v = readl(ptr);
+ add_record(IOT_32 | IOT_READ, ptr, v);
+
+ return v;
+}
+
+void iotrace_writel(ulong value, const void *ptr)
+{
+ add_record(IOT_32 | IOT_WRITE, ptr, value);
+ writel(value, ptr);
+}
+
+u16 iotrace_readw(const void *ptr)
+{
+ u32 v;
+
+ v = readw(ptr);
+ add_record(IOT_16 | IOT_READ, ptr, v);
+
+ return v;
+}
+
+void iotrace_writew(ulong value, const void *ptr)
+{
+ add_record(IOT_16 | IOT_WRITE, ptr, value);
+ writew(value, ptr);
+}
+
+u8 iotrace_readb(const void *ptr)
+{
+ u32 v;
+
+ v = readb(ptr);
+ add_record(IOT_8 | IOT_READ, ptr, v);
+
+ return v;
+}
+
+void iotrace_writeb(ulong value, const void *ptr)
+{
+ add_record(IOT_8 | IOT_WRITE, ptr, value);
+ writeb(value, ptr);
+}
+
+void iotrace_reset_checksum(void)
+{
+ iotrace.crc32 = 0;
+}
+
+u32 iotrace_get_checksum(void)
+{
+ return iotrace.crc32;
+}
+
+void iotrace_set_enabled(int enable)
+{
+ iotrace.enabled = enable;
+}
+
+int iotrace_get_enabled(void)
+{
+ return iotrace.enabled;
+}
+
+void iotrace_set_buffer(ulong start, ulong size)
+{
+ iotrace.start = start;
+ iotrace.size = size;
+ iotrace.offset = 0;
+ iotrace.crc32 = 0;
+}
+
+void iotrace_get_buffer(ulong *start, ulong *size, ulong *offset, ulong *count)
+{
+ *start = iotrace.start;
+ *size = iotrace.size;
+ *offset = iotrace.offset;
+ *count = iotrace.offset / sizeof(struct iotrace_record);
+}
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
- * Add to readline cmdline-editing by
- * (C) Copyright 2005
- * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
- *
* SPDX-License-Identifier: GPL-2.0+
*/
/* #define DEBUG */
#include <common.h>
-#include <command.h>
-#include <fdtdec.h>
-#include <hush.h>
-#include <malloc.h>
-#include <menu.h>
-#include <post.h>
+#include <autoboot.h>
+#include <cli.h>
#include <version.h>
-#include <watchdog.h>
-#include <linux/ctype.h>
DECLARE_GLOBAL_DATA_PTR;
void inline __show_boot_progress (int val) {}
void show_boot_progress (int val) __attribute__((weak, alias("__show_boot_progress")));
-#define MAX_DELAY_STOP_STR 32
-
-#define DEBUG_PARSER 0 /* set to 1 to debug */
-
-#define debug_parser(fmt, args...) \
- debug_cond(DEBUG_PARSER, fmt, ##args)
-
-#ifndef DEBUG_BOOTKEYS
-#define DEBUG_BOOTKEYS 0
-#endif
-#define debug_bootkeys(fmt, args...) \
- debug_cond(DEBUG_BOOTKEYS, fmt, ##args)
-
-char console_buffer[CONFIG_SYS_CBSIZE + 1]; /* console I/O buffer */
-
-static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen);
-static const char erase_seq[] = "\b \b"; /* erase sequence */
-static const char tab_seq[] = " "; /* used to expand TABs */
-
-#ifdef CONFIG_BOOT_RETRY_TIME
-static uint64_t endtime = 0; /* must be set, default is instant timeout */
-static int retry_time = -1; /* -1 so can call readline before main_loop */
-#endif
-
-#define endtick(seconds) (get_ticks() + (uint64_t)(seconds) * get_tbclk())
-
-#ifndef CONFIG_BOOT_RETRY_MIN
-#define CONFIG_BOOT_RETRY_MIN CONFIG_BOOT_RETRY_TIME
-#endif
-
-#ifdef CONFIG_MODEM_SUPPORT
-int do_mdm_init = 0;
-extern void mdm_init(void); /* defined in board.c */
-#endif
-
-/***************************************************************************
- * Watch for 'delay' seconds for autoboot stop or autoboot delay string.
- * returns: 0 - no key string, allow autoboot 1 - got key string, abort
- */
-#if defined(CONFIG_BOOTDELAY)
-# if defined(CONFIG_AUTOBOOT_KEYED)
-static int abortboot_keyed(int bootdelay)
-{
- int abort = 0;
- uint64_t etime = endtick(bootdelay);
- struct {
- char* str;
- u_int len;
- int retry;
- }
- delaykey [] = {
- { str: getenv ("bootdelaykey"), retry: 1 },
- { str: getenv ("bootdelaykey2"), retry: 1 },
- { str: getenv ("bootstopkey"), retry: 0 },
- { str: getenv ("bootstopkey2"), retry: 0 },
- };
-
- char presskey [MAX_DELAY_STOP_STR];
- u_int presskey_len = 0;
- u_int presskey_max = 0;
- u_int i;
-
-#ifndef CONFIG_ZERO_BOOTDELAY_CHECK
- if (bootdelay == 0)
- return 0;
-#endif
-
-# ifdef CONFIG_AUTOBOOT_PROMPT
- printf(CONFIG_AUTOBOOT_PROMPT);
-# endif
-
-# ifdef CONFIG_AUTOBOOT_DELAY_STR
- if (delaykey[0].str == NULL)
- delaykey[0].str = CONFIG_AUTOBOOT_DELAY_STR;
-# endif
-# ifdef CONFIG_AUTOBOOT_DELAY_STR2
- if (delaykey[1].str == NULL)
- delaykey[1].str = CONFIG_AUTOBOOT_DELAY_STR2;
-# endif
-# ifdef CONFIG_AUTOBOOT_STOP_STR
- if (delaykey[2].str == NULL)
- delaykey[2].str = CONFIG_AUTOBOOT_STOP_STR;
-# endif
-# ifdef CONFIG_AUTOBOOT_STOP_STR2
- if (delaykey[3].str == NULL)
- delaykey[3].str = CONFIG_AUTOBOOT_STOP_STR2;
-# endif
-
- for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i ++) {
- delaykey[i].len = delaykey[i].str == NULL ?
- 0 : strlen (delaykey[i].str);
- delaykey[i].len = delaykey[i].len > MAX_DELAY_STOP_STR ?
- MAX_DELAY_STOP_STR : delaykey[i].len;
-
- presskey_max = presskey_max > delaykey[i].len ?
- presskey_max : delaykey[i].len;
-
- debug_bootkeys("%s key:<%s>\n",
- delaykey[i].retry ? "delay" : "stop",
- delaykey[i].str ? delaykey[i].str : "NULL");
- }
-
- /* In order to keep up with incoming data, check timeout only
- * when catch up.
- */
- do {
- if (tstc()) {
- if (presskey_len < presskey_max) {
- presskey [presskey_len ++] = getc();
- }
- else {
- for (i = 0; i < presskey_max - 1; i ++)
- presskey [i] = presskey [i + 1];
-
- presskey [i] = getc();
- }
- }
-
- for (i = 0; i < sizeof(delaykey) / sizeof(delaykey[0]); i ++) {
- if (delaykey[i].len > 0 &&
- presskey_len >= delaykey[i].len &&
- memcmp (presskey + presskey_len - delaykey[i].len,
- delaykey[i].str,
- delaykey[i].len) == 0) {
- debug_bootkeys("got %skey\n",
- delaykey[i].retry ? "delay" :
- "stop");
-
-# ifdef CONFIG_BOOT_RETRY_TIME
- /* don't retry auto boot */
- if (! delaykey[i].retry)
- retry_time = -1;
-# endif
- abort = 1;
- }
- }
- } while (!abort && get_ticks() <= etime);
-
- if (!abort)
- debug_bootkeys("key timeout\n");
-
-#ifdef CONFIG_SILENT_CONSOLE
- if (abort)
- gd->flags &= ~GD_FLG_SILENT;
-#endif
-
- return abort;
-}
-
-# else /* !defined(CONFIG_AUTOBOOT_KEYED) */
-
-#ifdef CONFIG_MENUKEY
-static int menukey = 0;
-#endif
-
-static int abortboot_normal(int bootdelay)
+static void modem_init(void)
{
- int abort = 0;
- unsigned long ts;
-
-#ifdef CONFIG_MENUPROMPT
- printf(CONFIG_MENUPROMPT);
-#else
- if (bootdelay >= 0)
- printf("Hit any key to stop autoboot: %2d ", bootdelay);
-#endif
-
-#if defined CONFIG_ZERO_BOOTDELAY_CHECK
- /*
- * Check if key already pressed
- * Don't check if bootdelay < 0
- */
- if (bootdelay >= 0) {
- if (tstc()) { /* we got a key press */
- (void) getc(); /* consume input */
- puts ("\b\b\b 0");
- abort = 1; /* don't auto boot */
- }
- }
-#endif
-
- while ((bootdelay > 0) && (!abort)) {
- --bootdelay;
- /* delay 1000 ms */
- ts = get_timer(0);
- do {
- if (tstc()) { /* we got a key press */
- abort = 1; /* don't auto boot */
- bootdelay = 0; /* no more delay */
-# ifdef CONFIG_MENUKEY
- menukey = getc();
-# else
- (void) getc(); /* consume input */
-# endif
- break;
- }
- udelay(10000);
- } while (!abort && get_timer(ts) < 1000);
-
- printf("\b\b\b%2d ", bootdelay);
- }
-
- putc('\n');
-
-#ifdef CONFIG_SILENT_CONSOLE
- if (abort)
- gd->flags &= ~GD_FLG_SILENT;
-#endif
-
- return abort;
-}
-# endif /* CONFIG_AUTOBOOT_KEYED */
-
-static int abortboot(int bootdelay)
-{
-#ifdef CONFIG_AUTOBOOT_KEYED
- return abortboot_keyed(bootdelay);
-#else
- return abortboot_normal(bootdelay);
-#endif
-}
-#endif /* CONFIG_BOOTDELAY */
-
-/*
- * Runs the given boot command securely. Specifically:
- * - Doesn't run the command with the shell (run_command or parse_string_outer),
- * since that's a lot of code surface that an attacker might exploit.
- * Because of this, we don't do any argument parsing--the secure boot command
- * has to be a full-fledged u-boot command.
- * - Doesn't check for keypresses before booting, since that could be a
- * security hole; also disables Ctrl-C.
- * - Doesn't allow the command to return.
- *
- * Upon any failures, this function will drop into an infinite loop after
- * printing the error message to console.
- */
-
-#if defined(CONFIG_BOOTDELAY) && defined(CONFIG_OF_CONTROL)
-static void secure_boot_cmd(char *cmd)
-{
- cmd_tbl_t *cmdtp;
- int rc;
-
- if (!cmd) {
- printf("## Error: Secure boot command not specified\n");
- goto err;
- }
-
- /* Disable Ctrl-C just in case some command is used that checks it. */
- disable_ctrlc(1);
+#ifdef CONFIG_MODEM_SUPPORT
+ debug("DEBUG: main_loop: gd->do_mdm_init=%lu\n", gd->do_mdm_init);
+ if (gd->do_mdm_init) {
+ char *str = getenv("mdm_cmd");
- /* Find the command directly. */
- cmdtp = find_cmd(cmd);
- if (!cmdtp) {
- printf("## Error: \"%s\" not defined\n", cmd);
- goto err;
+ setenv("preboot", str); /* set or delete definition */
+ mdm_init(); /* wait for modem connection */
}
-
- /* Run the command, forcing no flags and faking argc and argv. */
- rc = (cmdtp->cmd)(cmdtp, 0, 1, &cmd);
-
- /* Shouldn't ever return from boot command. */
- printf("## Error: \"%s\" returned (code %d)\n", cmd, rc);
-
-err:
- /*
- * Not a whole lot to do here. Rebooting won't help much, since we'll
- * just end up right back here. Just loop.
- */
- hang();
-}
-
-static void process_fdt_options(const void *blob)
-{
- ulong addr;
-
- /* Add an env variable to point to a kernel payload, if available */
- addr = fdtdec_get_config_int(gd->fdt_blob, "kernel-offset", 0);
- if (addr)
- setenv_addr("kernaddr", (void *)(CONFIG_SYS_TEXT_BASE + addr));
-
- /* Add an env variable to point to a root disk, if available */
- addr = fdtdec_get_config_int(gd->fdt_blob, "rootdisk-offset", 0);
- if (addr)
- setenv_addr("rootaddr", (void *)(CONFIG_SYS_TEXT_BASE + addr));
+#endif /* CONFIG_MODEM_SUPPORT */
}
-#endif /* CONFIG_OF_CONTROL */
-#ifdef CONFIG_BOOTDELAY
-static void process_boot_delay(void)
+static void run_preboot_environment_command(void)
{
-#ifdef CONFIG_OF_CONTROL
- char *env;
-#endif
- char *s;
- int bootdelay;
-#ifdef CONFIG_BOOTCOUNT_LIMIT
- unsigned long bootcount = 0;
- unsigned long bootlimit = 0;
-#endif /* CONFIG_BOOTCOUNT_LIMIT */
-
-#ifdef CONFIG_BOOTCOUNT_LIMIT
- bootcount = bootcount_load();
- bootcount++;
- bootcount_store (bootcount);
- setenv_ulong("bootcount", bootcount);
- bootlimit = getenv_ulong("bootlimit", 10, 0);
-#endif /* CONFIG_BOOTCOUNT_LIMIT */
-
- s = getenv ("bootdelay");
- bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY;
-
-#ifdef CONFIG_OF_CONTROL
- bootdelay = fdtdec_get_config_int(gd->fdt_blob, "bootdelay",
- bootdelay);
-#endif
-
- debug ("### main_loop entered: bootdelay=%d\n\n", bootdelay);
-
-#if defined(CONFIG_MENU_SHOW)
- bootdelay = menu_show(bootdelay);
-#endif
-# ifdef CONFIG_BOOT_RETRY_TIME
- init_cmd_timeout ();
-# endif /* CONFIG_BOOT_RETRY_TIME */
-
-#ifdef CONFIG_POST
- if (gd->flags & GD_FLG_POSTFAIL) {
- s = getenv("failbootcmd");
- }
- else
-#endif /* CONFIG_POST */
-#ifdef CONFIG_BOOTCOUNT_LIMIT
- if (bootlimit && (bootcount > bootlimit)) {
- printf ("Warning: Bootlimit (%u) exceeded. Using altbootcmd.\n",
- (unsigned)bootlimit);
- s = getenv ("altbootcmd");
- }
- else
-#endif /* CONFIG_BOOTCOUNT_LIMIT */
- s = getenv ("bootcmd");
-#ifdef CONFIG_OF_CONTROL
- /* Allow the fdt to override the boot command */
- env = fdtdec_get_config_string(gd->fdt_blob, "bootcmd");
- if (env)
- s = env;
-
- process_fdt_options(gd->fdt_blob);
-
- /*
- * If the bootsecure option was chosen, use secure_boot_cmd().
- * Always use 'env' in this case, since bootsecure requres that the
- * bootcmd was specified in the FDT too.
- */
- if (fdtdec_get_config_int(gd->fdt_blob, "bootsecure", 0))
- secure_boot_cmd(env);
-
-#endif /* CONFIG_OF_CONTROL */
-
- debug ("### main_loop: bootcmd=\"%s\"\n", s ? s : "<UNDEFINED>");
+#ifdef CONFIG_PREBOOT
+ char *p;
- if (bootdelay != -1 && s && !abortboot(bootdelay)) {
-#if defined(CONFIG_AUTOBOOT_KEYED) && !defined(CONFIG_AUTOBOOT_KEYED_CTRLC)
+ p = getenv("preboot");
+ if (p != NULL) {
+# ifdef CONFIG_AUTOBOOT_KEYED
int prev = disable_ctrlc(1); /* disable Control C checking */
-#endif
+# endif
- run_command_list(s, -1, 0);
+ run_command_list(p, -1, 0);
-#if defined(CONFIG_AUTOBOOT_KEYED) && !defined(CONFIG_AUTOBOOT_KEYED_CTRLC)
+# ifdef CONFIG_AUTOBOOT_KEYED
disable_ctrlc(prev); /* restore Control C checking */
-#endif
- }
-
-#ifdef CONFIG_MENUKEY
- if (menukey == CONFIG_MENUKEY) {
- s = getenv("menucmd");
- if (s)
- run_command_list(s, -1, 0);
+# endif
}
-#endif /* CONFIG_MENUKEY */
+#endif /* CONFIG_PREBOOT */
}
-#endif /* CONFIG_BOOTDELAY */
+/* We come here after U-Boot is initialised and ready to process commands */
void main_loop(void)
{
-#ifndef CONFIG_SYS_HUSH_PARSER
- static char lastcommand[CONFIG_SYS_CBSIZE] = { 0, };
- int len;
- int rc = 1;
- int flag;
-#endif
-#ifdef CONFIG_PREBOOT
- char *p;
-#endif
+ const char *s;
bootstage_mark_name(BOOTSTAGE_ID_MAIN_LOOP, "main_loop");
puts("upgraded by the late 2014 may break or be removed.\n");
#endif
-#ifdef CONFIG_MODEM_SUPPORT
- debug("DEBUG: main_loop: do_mdm_init=%d\n", do_mdm_init);
- if (do_mdm_init) {
- char *str = strdup(getenv("mdm_cmd"));
- setenv("preboot", str); /* set or delete definition */
- if (str != NULL)
- free(str);
- mdm_init(); /* wait for modem connection */
- }
-#endif /* CONFIG_MODEM_SUPPORT */
-
+ modem_init();
#ifdef CONFIG_VERSION_VARIABLE
- {
- setenv("ver", version_string); /* set version variable */
- }
+ setenv("ver", version_string); /* set version variable */
#endif /* CONFIG_VERSION_VARIABLE */
-#ifdef CONFIG_SYS_HUSH_PARSER
- u_boot_hush_start();
-#endif
-
-#if defined(CONFIG_HUSH_INIT_VAR)
- hush_init_var();
-#endif
-
-#ifdef CONFIG_PREBOOT
- p = getenv("preboot");
- if (p != NULL) {
-# ifdef CONFIG_AUTOBOOT_KEYED
- int prev = disable_ctrlc(1); /* disable Control C checking */
-# endif
+ cli_init();
- run_command_list(p, -1, 0);
-
-# ifdef CONFIG_AUTOBOOT_KEYED
- disable_ctrlc(prev); /* restore Control C checking */
-# endif
- }
-#endif /* CONFIG_PREBOOT */
+ run_preboot_environment_command();
#if defined(CONFIG_UPDATE_TFTP)
update_tftp(0UL);
#endif /* CONFIG_UPDATE_TFTP */
-#ifdef CONFIG_BOOTDELAY
- process_boot_delay();
-#endif
- /*
- * Main Loop for Monitor Command Processing
- */
-#ifdef CONFIG_SYS_HUSH_PARSER
- parse_file_outer();
- /* This point is never reached */
- for (;;);
-#else
- for (;;) {
-#ifdef CONFIG_BOOT_RETRY_TIME
- if (rc >= 0) {
- /* Saw enough of a valid command to
- * restart the timeout.
- */
- reset_cmd_timeout();
- }
-#endif
- len = readline (CONFIG_SYS_PROMPT);
-
- flag = 0; /* assume no special flags for now */
- if (len > 0)
- strcpy (lastcommand, console_buffer);
- else if (len == 0)
- flag |= CMD_FLAG_REPEAT;
-#ifdef CONFIG_BOOT_RETRY_TIME
- else if (len == -2) {
- /* -2 means timed out, retry autoboot
- */
- puts ("\nTimed out waiting for command\n");
-# ifdef CONFIG_RESET_TO_RETRY
- /* Reinit board to run initialization code again */
- do_reset (NULL, 0, 0, NULL);
-# else
- return; /* retry autoboot */
-# endif
- }
-#endif
-
- if (len == -1)
- puts ("<INTERRUPT>\n");
- else
- rc = run_command(lastcommand, flag);
-
- if (rc <= 0) {
- /* invalid command or not repeatable, forget it */
- lastcommand[0] = 0;
- }
- }
-#endif /*CONFIG_SYS_HUSH_PARSER*/
-}
-
-#ifdef CONFIG_BOOT_RETRY_TIME
-/***************************************************************************
- * initialize command line timeout
- */
-void init_cmd_timeout(void)
-{
- char *s = getenv ("bootretry");
-
- if (s != NULL)
- retry_time = (int)simple_strtol(s, NULL, 10);
- else
- retry_time = CONFIG_BOOT_RETRY_TIME;
-
- if (retry_time >= 0 && retry_time < CONFIG_BOOT_RETRY_MIN)
- retry_time = CONFIG_BOOT_RETRY_MIN;
-}
-
-/***************************************************************************
- * reset command line timeout to retry_time seconds
- */
-void reset_cmd_timeout(void)
-{
- endtime = endtick(retry_time);
-}
-#endif
-
-#ifdef CONFIG_CMDLINE_EDITING
-
-/*
- * cmdline-editing related codes from vivi.
- * Author: Janghoon Lyu <nandy@mizi.com>
- */
-
-#define putnstr(str,n) do { \
- printf ("%.*s", (int)n, str); \
- } while (0)
-
-#define CTL_CH(c) ((c) - 'a' + 1)
-#define CTL_BACKSPACE ('\b')
-#define DEL ((char)255)
-#define DEL7 ((char)127)
-#define CREAD_HIST_CHAR ('!')
-
-#define getcmd_putch(ch) putc(ch)
-#define getcmd_getch() getc()
-#define getcmd_cbeep() getcmd_putch('\a')
-
-#define HIST_MAX 20
-#define HIST_SIZE CONFIG_SYS_CBSIZE
-
-static int hist_max;
-static int hist_add_idx;
-static int hist_cur = -1;
-static unsigned hist_num;
-
-static char *hist_list[HIST_MAX];
-static char hist_lines[HIST_MAX][HIST_SIZE + 1]; /* Save room for NULL */
-
-#define add_idx_minus_one() ((hist_add_idx == 0) ? hist_max : hist_add_idx-1)
-
-static void hist_init(void)
-{
- int i;
-
- hist_max = 0;
- hist_add_idx = 0;
- hist_cur = -1;
- hist_num = 0;
-
- for (i = 0; i < HIST_MAX; i++) {
- hist_list[i] = hist_lines[i];
- hist_list[i][0] = '\0';
- }
-}
-
-static void cread_add_to_hist(char *line)
-{
- strcpy(hist_list[hist_add_idx], line);
-
- if (++hist_add_idx >= HIST_MAX)
- hist_add_idx = 0;
-
- if (hist_add_idx > hist_max)
- hist_max = hist_add_idx;
-
- hist_num++;
-}
-
-static char* hist_prev(void)
-{
- char *ret;
- int old_cur;
-
- if (hist_cur < 0)
- return NULL;
-
- old_cur = hist_cur;
- if (--hist_cur < 0)
- hist_cur = hist_max;
-
- if (hist_cur == hist_add_idx) {
- hist_cur = old_cur;
- ret = NULL;
- } else
- ret = hist_list[hist_cur];
-
- return (ret);
-}
-
-static char* hist_next(void)
-{
- char *ret;
-
- if (hist_cur < 0)
- return NULL;
-
- if (hist_cur == hist_add_idx)
- return NULL;
-
- if (++hist_cur > hist_max)
- hist_cur = 0;
-
- if (hist_cur == hist_add_idx) {
- ret = "";
- } else
- ret = hist_list[hist_cur];
-
- return (ret);
-}
-
-#ifndef CONFIG_CMDLINE_EDITING
-static void cread_print_hist_list(void)
-{
- int i;
- unsigned long n;
-
- n = hist_num - hist_max;
-
- i = hist_add_idx + 1;
- while (1) {
- if (i > hist_max)
- i = 0;
- if (i == hist_add_idx)
- break;
- printf("%s\n", hist_list[i]);
- n++;
- i++;
- }
-}
-#endif /* CONFIG_CMDLINE_EDITING */
-
-#define BEGINNING_OF_LINE() { \
- while (num) { \
- getcmd_putch(CTL_BACKSPACE); \
- num--; \
- } \
-}
-
-#define ERASE_TO_EOL() { \
- if (num < eol_num) { \
- printf("%*s", (int)(eol_num - num), ""); \
- do { \
- getcmd_putch(CTL_BACKSPACE); \
- } while (--eol_num > num); \
- } \
-}
-
-#define REFRESH_TO_EOL() { \
- if (num < eol_num) { \
- wlen = eol_num - num; \
- putnstr(buf + num, wlen); \
- num = eol_num; \
- } \
-}
-
-static void cread_add_char(char ichar, int insert, unsigned long *num,
- unsigned long *eol_num, char *buf, unsigned long len)
-{
- unsigned long wlen;
-
- /* room ??? */
- if (insert || *num == *eol_num) {
- if (*eol_num > len - 1) {
- getcmd_cbeep();
- return;
- }
- (*eol_num)++;
- }
-
- if (insert) {
- wlen = *eol_num - *num;
- if (wlen > 1) {
- memmove(&buf[*num+1], &buf[*num], wlen-1);
- }
+ s = bootdelay_process();
+ if (cli_process_fdt(&s))
+ cli_secure_boot_cmd(s);
- buf[*num] = ichar;
- putnstr(buf + *num, wlen);
- (*num)++;
- while (--wlen) {
- getcmd_putch(CTL_BACKSPACE);
- }
- } else {
- /* echo the character */
- wlen = 1;
- buf[*num] = ichar;
- putnstr(buf + *num, wlen);
- (*num)++;
- }
-}
+ autoboot_command(s);
-static void cread_add_str(char *str, int strsize, int insert, unsigned long *num,
- unsigned long *eol_num, char *buf, unsigned long len)
-{
- while (strsize--) {
- cread_add_char(*str, insert, num, eol_num, buf, len);
- str++;
- }
+ cli_loop();
}
-
-static int cread_line(const char *const prompt, char *buf, unsigned int *len,
- int timeout)
-{
- unsigned long num = 0;
- unsigned long eol_num = 0;
- unsigned long wlen;
- char ichar;
- int insert = 1;
- int esc_len = 0;
- char esc_save[8];
- int init_len = strlen(buf);
- int first = 1;
-
- if (init_len)
- cread_add_str(buf, init_len, 1, &num, &eol_num, buf, *len);
-
- while (1) {
-#ifdef CONFIG_BOOT_RETRY_TIME
- while (!tstc()) { /* while no incoming data */
- if (retry_time >= 0 && get_ticks() > endtime)
- return (-2); /* timed out */
- WATCHDOG_RESET();
- }
-#endif
- if (first && timeout) {
- uint64_t etime = endtick(timeout);
-
- while (!tstc()) { /* while no incoming data */
- if (get_ticks() >= etime)
- return -2; /* timed out */
- WATCHDOG_RESET();
- }
- first = 0;
- }
-
- ichar = getcmd_getch();
-
- if ((ichar == '\n') || (ichar == '\r')) {
- putc('\n');
- break;
- }
-
- /*
- * handle standard linux xterm esc sequences for arrow key, etc.
- */
- if (esc_len != 0) {
- if (esc_len == 1) {
- if (ichar == '[') {
- esc_save[esc_len] = ichar;
- esc_len = 2;
- } else {
- cread_add_str(esc_save, esc_len, insert,
- &num, &eol_num, buf, *len);
- esc_len = 0;
- }
- continue;
- }
-
- switch (ichar) {
-
- case 'D': /* <- key */
- ichar = CTL_CH('b');
- esc_len = 0;
- break;
- case 'C': /* -> key */
- ichar = CTL_CH('f');
- esc_len = 0;
- break; /* pass off to ^F handler */
- case 'H': /* Home key */
- ichar = CTL_CH('a');
- esc_len = 0;
- break; /* pass off to ^A handler */
- case 'A': /* up arrow */
- ichar = CTL_CH('p');
- esc_len = 0;
- break; /* pass off to ^P handler */
- case 'B': /* down arrow */
- ichar = CTL_CH('n');
- esc_len = 0;
- break; /* pass off to ^N handler */
- default:
- esc_save[esc_len++] = ichar;
- cread_add_str(esc_save, esc_len, insert,
- &num, &eol_num, buf, *len);
- esc_len = 0;
- continue;
- }
- }
-
- switch (ichar) {
- case 0x1b:
- if (esc_len == 0) {
- esc_save[esc_len] = ichar;
- esc_len = 1;
- } else {
- puts("impossible condition #876\n");
- esc_len = 0;
- }
- break;
-
- case CTL_CH('a'):
- BEGINNING_OF_LINE();
- break;
- case CTL_CH('c'): /* ^C - break */
- *buf = '\0'; /* discard input */
- return (-1);
- case CTL_CH('f'):
- if (num < eol_num) {
- getcmd_putch(buf[num]);
- num++;
- }
- break;
- case CTL_CH('b'):
- if (num) {
- getcmd_putch(CTL_BACKSPACE);
- num--;
- }
- break;
- case CTL_CH('d'):
- if (num < eol_num) {
- wlen = eol_num - num - 1;
- if (wlen) {
- memmove(&buf[num], &buf[num+1], wlen);
- putnstr(buf + num, wlen);
- }
-
- getcmd_putch(' ');
- do {
- getcmd_putch(CTL_BACKSPACE);
- } while (wlen--);
- eol_num--;
- }
- break;
- case CTL_CH('k'):
- ERASE_TO_EOL();
- break;
- case CTL_CH('e'):
- REFRESH_TO_EOL();
- break;
- case CTL_CH('o'):
- insert = !insert;
- break;
- case CTL_CH('x'):
- case CTL_CH('u'):
- BEGINNING_OF_LINE();
- ERASE_TO_EOL();
- break;
- case DEL:
- case DEL7:
- case 8:
- if (num) {
- wlen = eol_num - num;
- num--;
- memmove(&buf[num], &buf[num+1], wlen);
- getcmd_putch(CTL_BACKSPACE);
- putnstr(buf + num, wlen);
- getcmd_putch(' ');
- do {
- getcmd_putch(CTL_BACKSPACE);
- } while (wlen--);
- eol_num--;
- }
- break;
- case CTL_CH('p'):
- case CTL_CH('n'):
- {
- char * hline;
-
- esc_len = 0;
-
- if (ichar == CTL_CH('p'))
- hline = hist_prev();
- else
- hline = hist_next();
-
- if (!hline) {
- getcmd_cbeep();
- continue;
- }
-
- /* nuke the current line */
- /* first, go home */
- BEGINNING_OF_LINE();
-
- /* erase to end of line */
- ERASE_TO_EOL();
-
- /* copy new line into place and display */
- strcpy(buf, hline);
- eol_num = strlen(buf);
- REFRESH_TO_EOL();
- continue;
- }
-#ifdef CONFIG_AUTO_COMPLETE
- case '\t': {
- int num2, col;
-
- /* do not autocomplete when in the middle */
- if (num < eol_num) {
- getcmd_cbeep();
- break;
- }
-
- buf[num] = '\0';
- col = strlen(prompt) + eol_num;
- num2 = num;
- if (cmd_auto_complete(prompt, buf, &num2, &col)) {
- col = num2 - num;
- num += col;
- eol_num += col;
- }
- break;
- }
-#endif
- default:
- cread_add_char(ichar, insert, &num, &eol_num, buf, *len);
- break;
- }
- }
- *len = eol_num;
- buf[eol_num] = '\0'; /* lose the newline */
-
- if (buf[0] && buf[0] != CREAD_HIST_CHAR)
- cread_add_to_hist(buf);
- hist_cur = hist_add_idx;
-
- return 0;
-}
-
-#endif /* CONFIG_CMDLINE_EDITING */
-
-/****************************************************************************/
-
-/*
- * Prompt for input and read a line.
- * If CONFIG_BOOT_RETRY_TIME is defined and retry_time >= 0,
- * time out when time goes past endtime (timebase time in ticks).
- * Return: number of read characters
- * -1 if break
- * -2 if timed out
- */
-int readline (const char *const prompt)
-{
- /*
- * If console_buffer isn't 0-length the user will be prompted to modify
- * it instead of entering it from scratch as desired.
- */
- console_buffer[0] = '\0';
-
- return readline_into_buffer(prompt, console_buffer, 0);
-}
-
-
-int readline_into_buffer(const char *const prompt, char *buffer, int timeout)
-{
- char *p = buffer;
-#ifdef CONFIG_CMDLINE_EDITING
- unsigned int len = CONFIG_SYS_CBSIZE;
- int rc;
- static int initted = 0;
-
- /*
- * History uses a global array which is not
- * writable until after relocation to RAM.
- * Revert to non-history version if still
- * running from flash.
- */
- if (gd->flags & GD_FLG_RELOC) {
- if (!initted) {
- hist_init();
- initted = 1;
- }
-
- if (prompt)
- puts (prompt);
-
- rc = cread_line(prompt, p, &len, timeout);
- return rc < 0 ? rc : len;
-
- } else {
-#endif /* CONFIG_CMDLINE_EDITING */
- char * p_buf = p;
- int n = 0; /* buffer index */
- int plen = 0; /* prompt length */
- int col; /* output column cnt */
- char c;
-
- /* print prompt */
- if (prompt) {
- plen = strlen (prompt);
- puts (prompt);
- }
- col = plen;
-
- for (;;) {
-#ifdef CONFIG_BOOT_RETRY_TIME
- while (!tstc()) { /* while no incoming data */
- if (retry_time >= 0 && get_ticks() > endtime)
- return (-2); /* timed out */
- WATCHDOG_RESET();
- }
-#endif
- WATCHDOG_RESET(); /* Trigger watchdog, if needed */
-
-#ifdef CONFIG_SHOW_ACTIVITY
- while (!tstc()) {
- show_activity(0);
- WATCHDOG_RESET();
- }
-#endif
- c = getc();
-
- /*
- * Special character handling
- */
- switch (c) {
- case '\r': /* Enter */
- case '\n':
- *p = '\0';
- puts ("\r\n");
- return p - p_buf;
-
- case '\0': /* nul */
- continue;
-
- case 0x03: /* ^C - break */
- p_buf[0] = '\0'; /* discard input */
- return -1;
-
- case 0x15: /* ^U - erase line */
- while (col > plen) {
- puts (erase_seq);
- --col;
- }
- p = p_buf;
- n = 0;
- continue;
-
- case 0x17: /* ^W - erase word */
- p=delete_char(p_buf, p, &col, &n, plen);
- while ((n > 0) && (*p != ' ')) {
- p=delete_char(p_buf, p, &col, &n, plen);
- }
- continue;
-
- case 0x08: /* ^H - backspace */
- case 0x7F: /* DEL - backspace */
- p=delete_char(p_buf, p, &col, &n, plen);
- continue;
-
- default:
- /*
- * Must be a normal character then
- */
- if (n < CONFIG_SYS_CBSIZE-2) {
- if (c == '\t') { /* expand TABs */
-#ifdef CONFIG_AUTO_COMPLETE
- /* if auto completion triggered just continue */
- *p = '\0';
- if (cmd_auto_complete(prompt, console_buffer, &n, &col)) {
- p = p_buf + n; /* reset */
- continue;
- }
-#endif
- puts (tab_seq+(col&07));
- col += 8 - (col&07);
- } else {
- char buf[2];
-
- /*
- * Echo input using puts() to force an
- * LCD flush if we are using an LCD
- */
- ++col;
- buf[0] = c;
- buf[1] = '\0';
- puts(buf);
- }
- *p++ = c;
- ++n;
- } else { /* Buffer full */
- putc ('\a');
- }
- }
- }
-#ifdef CONFIG_CMDLINE_EDITING
- }
-#endif
-}
-
-/****************************************************************************/
-
-static char * delete_char (char *buffer, char *p, int *colp, int *np, int plen)
-{
- char *s;
-
- if (*np == 0) {
- return (p);
- }
-
- if (*(--p) == '\t') { /* will retype the whole line */
- while (*colp > plen) {
- puts (erase_seq);
- (*colp)--;
- }
- for (s=buffer; s<p; ++s) {
- if (*s == '\t') {
- puts (tab_seq+((*colp) & 07));
- *colp += 8 - ((*colp) & 07);
- } else {
- ++(*colp);
- putc (*s);
- }
- }
- } else {
- puts (erase_seq);
- (*colp)--;
- }
- (*np)--;
- return (p);
-}
-
-/****************************************************************************/
-
-int parse_line (char *line, char *argv[])
-{
- int nargs = 0;
-
- debug_parser("parse_line: \"%s\"\n", line);
- while (nargs < CONFIG_SYS_MAXARGS) {
-
- /* skip any white space */
- while (isblank(*line))
- ++line;
-
- if (*line == '\0') { /* end of line, no more args */
- argv[nargs] = NULL;
- debug_parser("parse_line: nargs=%d\n", nargs);
- return nargs;
- }
-
- argv[nargs++] = line; /* begin of argument string */
-
- /* find end of string */
- while (*line && !isblank(*line))
- ++line;
-
- if (*line == '\0') { /* end of line, no more args */
- argv[nargs] = NULL;
- debug_parser("parse_line: nargs=%d\n", nargs);
- return nargs;
- }
-
- *line++ = '\0'; /* terminate current arg */
- }
-
- printf ("** Too many args (max. %d) **\n", CONFIG_SYS_MAXARGS);
-
- debug_parser("parse_line: nargs=%d\n", nargs);
- return (nargs);
-}
-
-/****************************************************************************/
-
-#ifndef CONFIG_SYS_HUSH_PARSER
-static void process_macros (const char *input, char *output)
-{
- char c, prev;
- const char *varname_start = NULL;
- int inputcnt = strlen (input);
- int outputcnt = CONFIG_SYS_CBSIZE;
- int state = 0; /* 0 = waiting for '$' */
-
- /* 1 = waiting for '(' or '{' */
- /* 2 = waiting for ')' or '}' */
- /* 3 = waiting for ''' */
- char *output_start = output;
-
- debug_parser("[PROCESS_MACROS] INPUT len %zd: \"%s\"\n", strlen(input),
- input);
-
- prev = '\0'; /* previous character */
-
- while (inputcnt && outputcnt) {
- c = *input++;
- inputcnt--;
-
- if (state != 3) {
- /* remove one level of escape characters */
- if ((c == '\\') && (prev != '\\')) {
- if (inputcnt-- == 0)
- break;
- prev = c;
- c = *input++;
- }
- }
-
- switch (state) {
- case 0: /* Waiting for (unescaped) $ */
- if ((c == '\'') && (prev != '\\')) {
- state = 3;
- break;
- }
- if ((c == '$') && (prev != '\\')) {
- state++;
- } else {
- *(output++) = c;
- outputcnt--;
- }
- break;
- case 1: /* Waiting for ( */
- if (c == '(' || c == '{') {
- state++;
- varname_start = input;
- } else {
- state = 0;
- *(output++) = '$';
- outputcnt--;
-
- if (outputcnt) {
- *(output++) = c;
- outputcnt--;
- }
- }
- break;
- case 2: /* Waiting for ) */
- if (c == ')' || c == '}') {
- int i;
- char envname[CONFIG_SYS_CBSIZE], *envval;
- int envcnt = input - varname_start - 1; /* Varname # of chars */
-
- /* Get the varname */
- for (i = 0; i < envcnt; i++) {
- envname[i] = varname_start[i];
- }
- envname[i] = 0;
-
- /* Get its value */
- envval = getenv (envname);
-
- /* Copy into the line if it exists */
- if (envval != NULL)
- while ((*envval) && outputcnt) {
- *(output++) = *(envval++);
- outputcnt--;
- }
- /* Look for another '$' */
- state = 0;
- }
- break;
- case 3: /* Waiting for ' */
- if ((c == '\'') && (prev != '\\')) {
- state = 0;
- } else {
- *(output++) = c;
- outputcnt--;
- }
- break;
- }
- prev = c;
- }
-
- if (outputcnt)
- *output = 0;
- else
- *(output - 1) = 0;
-
- debug_parser("[PROCESS_MACROS] OUTPUT len %zd: \"%s\"\n",
- strlen(output_start), output_start);
-}
-
-/****************************************************************************
- * returns:
- * 1 - command executed, repeatable
- * 0 - command executed but not repeatable, interrupted commands are
- * always considered not repeatable
- * -1 - not executed (unrecognized, bootd recursion or too many args)
- * (If cmd is NULL or "" or longer than CONFIG_SYS_CBSIZE-1 it is
- * considered unrecognized)
- *
- * WARNING:
- *
- * We must create a temporary copy of the command since the command we get
- * may be the result from getenv(), which returns a pointer directly to
- * the environment data, which may change magicly when the command we run
- * creates or modifies environment variables (like "bootp" does).
- */
-static int builtin_run_command(const char *cmd, int flag)
-{
- char cmdbuf[CONFIG_SYS_CBSIZE]; /* working copy of cmd */
- char *token; /* start of token in cmdbuf */
- char *sep; /* end of token (separator) in cmdbuf */
- char finaltoken[CONFIG_SYS_CBSIZE];
- char *str = cmdbuf;
- char *argv[CONFIG_SYS_MAXARGS + 1]; /* NULL terminated */
- int argc, inquotes;
- int repeatable = 1;
- int rc = 0;
-
- debug_parser("[RUN_COMMAND] cmd[%p]=\"", cmd);
- if (DEBUG_PARSER) {
- /* use puts - string may be loooong */
- puts(cmd ? cmd : "NULL");
- puts("\"\n");
- }
- clear_ctrlc(); /* forget any previous Control C */
-
- if (!cmd || !*cmd) {
- return -1; /* empty command */
- }
-
- if (strlen(cmd) >= CONFIG_SYS_CBSIZE) {
- puts ("## Command too long!\n");
- return -1;
- }
-
- strcpy (cmdbuf, cmd);
-
- /* Process separators and check for invalid
- * repeatable commands
- */
-
- debug_parser("[PROCESS_SEPARATORS] %s\n", cmd);
- while (*str) {
-
- /*
- * Find separator, or string end
- * Allow simple escape of ';' by writing "\;"
- */
- for (inquotes = 0, sep = str; *sep; sep++) {
- if ((*sep=='\'') &&
- (*(sep-1) != '\\'))
- inquotes=!inquotes;
-
- if (!inquotes &&
- (*sep == ';') && /* separator */
- ( sep != str) && /* past string start */
- (*(sep-1) != '\\')) /* and NOT escaped */
- break;
- }
-
- /*
- * Limit the token to data between separators
- */
- token = str;
- if (*sep) {
- str = sep + 1; /* start of command for next pass */
- *sep = '\0';
- }
- else
- str = sep; /* no more commands for next pass */
- debug_parser("token: \"%s\"\n", token);
-
- /* find macros in this token and replace them */
- process_macros (token, finaltoken);
-
- /* Extract arguments */
- if ((argc = parse_line (finaltoken, argv)) == 0) {
- rc = -1; /* no command at all */
- continue;
- }
-
- if (cmd_process(flag, argc, argv, &repeatable, NULL))
- rc = -1;
-
- /* Did the user stop this? */
- if (had_ctrlc ())
- return -1; /* if stopped then not repeatable */
- }
-
- return rc ? rc : repeatable;
-}
-#endif
-
-/*
- * Run a command using the selected parser.
- *
- * @param cmd Command to run
- * @param flag Execution flags (CMD_FLAG_...)
- * @return 0 on success, or != 0 on error.
- */
-int run_command(const char *cmd, int flag)
-{
-#ifndef CONFIG_SYS_HUSH_PARSER
- /*
- * builtin_run_command can return 0 or 1 for success, so clean up
- * its result.
- */
- if (builtin_run_command(cmd, flag) == -1)
- return 1;
-
- return 0;
-#else
- return parse_string_outer(cmd,
- FLAG_PARSE_SEMICOLON | FLAG_EXIT_FROM_LOOP);
-#endif
-}
-
-#ifndef CONFIG_SYS_HUSH_PARSER
-/**
- * Execute a list of command separated by ; or \n using the built-in parser.
- *
- * This function cannot take a const char * for the command, since if it
- * finds newlines in the string, it replaces them with \0.
- *
- * @param cmd String containing list of commands
- * @param flag Execution flags (CMD_FLAG_...)
- * @return 0 on success, or != 0 on error.
- */
-static int builtin_run_command_list(char *cmd, int flag)
-{
- char *line, *next;
- int rcode = 0;
-
- /*
- * Break into individual lines, and execute each line; terminate on
- * error.
- */
- line = next = cmd;
- while (*next) {
- if (*next == '\n') {
- *next = '\0';
- /* run only non-empty commands */
- if (*line) {
- debug("** exec: \"%s\"\n", line);
- if (builtin_run_command(line, 0) < 0) {
- rcode = 1;
- break;
- }
- }
- line = next + 1;
- }
- ++next;
- }
- if (rcode == 0 && *line)
- rcode = (builtin_run_command(line, 0) >= 0);
-
- return rcode;
-}
-#endif
-
-int run_command_list(const char *cmd, int len, int flag)
-{
- int need_buff = 1;
- char *buff = (char *)cmd; /* cast away const */
- int rcode = 0;
-
- if (len == -1) {
- len = strlen(cmd);
-#ifdef CONFIG_SYS_HUSH_PARSER
- /* hush will never change our string */
- need_buff = 0;
-#else
- /* the built-in parser will change our string if it sees \n */
- need_buff = strchr(cmd, '\n') != NULL;
-#endif
- }
- if (need_buff) {
- buff = malloc(len + 1);
- if (!buff)
- return 1;
- memcpy(buff, cmd, len);
- buff[len] = '\0';
- }
-#ifdef CONFIG_SYS_HUSH_PARSER
- rcode = parse_string_outer(buff, FLAG_PARSE_SEMICOLON);
-#else
- /*
- * This function will overwrite any \n it sees with a \0, which
- * is why it can't work with a const char *. Here we are making
- * using of internal knowledge of this function, to avoid always
- * doing a malloc() which is actually required only in a case that
- * is pretty rare.
- */
- rcode = builtin_run_command_list(buff, flag);
- if (need_buff)
- free(buff);
-#endif
-
- return rcode;
-}
-
-/****************************************************************************/
-
-#if defined(CONFIG_CMD_RUN)
-int do_run (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- int i;
-
- if (argc < 2)
- return CMD_RET_USAGE;
-
- for (i=1; i<argc; ++i) {
- char *arg;
-
- if ((arg = getenv (argv[i])) == NULL) {
- printf ("## Error: \"%s\" not defined\n", argv[i]);
- return 1;
- }
-
- if (run_command_list(arg, -1, flag) != 0)
- return 1;
- }
- return 0;
-}
-#endif
*/
#include <common.h>
+#include <cli.h>
#include <malloc.h>
#include <errno.h>
#include <linux/list.h>
menu_display(m);
if (!m->item_choice) {
- readret = readline_into_buffer("Enter choice: ", cbuf,
- m->timeout / 10);
+ readret = cli_readline_into_buffer("Enter choice: ",
+ cbuf,
+ m->timeout / 10);
if (readret >= 0) {
choice_item = menu_item_by_key(m, cbuf);
#include <asm/4xx_pci.h>
#endif
-#ifndef CONFIG_USB_HUB_MIN_POWER_ON_DELAY
-#define CONFIG_USB_HUB_MIN_POWER_ON_DELAY 100
-#endif
-
#define USB_BUFSIZ 512
static struct usb_hub_device hub_dev[USB_MAX_HUB];
debug("port %d returns %lX\n", i + 1, dev->status);
}
- /* Wait for power to become stable */
- mdelay(max(pgood_delay, CONFIG_USB_HUB_MIN_POWER_ON_DELAY));
+ /*
+ * Wait for power to become stable,
+ * plus spec-defined max time for device to connect
+ */
+ mdelay(pgood_delay + 1000);
}
void usb_hub_reset(void)
* If we don't eat it now, RedBoot will think the user typed it.
*/
ZM_DEBUG (zm_dprintf ("Trailing gunk:\n"));
- while ((c = (*getc) ()) > -1);
+ while ((c = (*getc) ()) > -1)
+ ;
ZM_DEBUG (zm_dprintf ("\n"));
/*
* Make a small delay to give terminal programs like minicom
block_dev_desc_t *dev_desc = reloc_get_dev(dev);
if (!dev_desc)
return NULL;
- if (hwpart == -1)
+ if (hwpart == 0 && !select_hwpart)
return dev_desc;
if (!select_hwpart)
return NULL;
block_dev_desc_t *get_dev(const char *ifname, int dev)
{
- return get_dev_hwpart(ifname, dev, -1);
+ return get_dev_hwpart(ifname, dev, 0);
}
#else
block_dev_desc_t *get_dev_hwpart(const char *ifname, int dev, int hwpart)
hwpart_str++;
} else {
dev_str = dev_hwpart_str;
- hwpart = -1;
+ hwpart = 0;
}
dev = simple_strtoul(dev_str, &ep, 16);
int part;
disk_partition_t tmpinfo;
+ /*
+ * Special-case a psuedo block device "hostfs", to allow access to the
+ * host's own filesystem.
+ */
+ if (0 == strcmp(ifname, "hostfs")) {
+ *dev_desc = NULL;
+ info->start = 0;
+ info->size = 0;
+ info->blksz = 0;
+ info->bootable = 0;
+ strcpy((char *)info->type, BOOT_PART_TYPE);
+ strcpy((char *)info->name, "Sandbox host");
+#ifdef CONFIG_PARTITION_UUIDS
+ info->uuid[0] = 0;
+#endif
+
+ return 0;
+ }
+
/* If no dev_part_str, use bootdevice environment variable */
if (!dev_part_str || !strlen(dev_part_str) ||
!strcmp(dev_part_str, "-"))
#ifdef HAVE_BLOCK_DEVICE
+#define DOS_PART_DEFAULT_SECTOR 512
+
/* Convert char[4] in little endian format to the host format integer
*/
static inline int le32_to_int(unsigned char *le32)
ALLOC_CACHE_ALIGN_BUFFER(unsigned char, buffer, dev_desc->blksz);
dos_partition_t *pt;
int i;
+ int dos_type;
if (dev_desc->block_read (dev_desc->dev, ext_part_sector, 1, (ulong *) buffer) != 1) {
printf ("** Can't read partition table on %d:%d **\n",
(pt->sys_ind != 0) &&
(part_num == which_part) &&
(is_extended(pt->sys_ind) == 0)) {
- info->blksz = 512;
- info->start = ext_part_sector + le32_to_int (pt->start4);
- info->size = le32_to_int (pt->size4);
+ info->blksz = DOS_PART_DEFAULT_SECTOR;
+ info->start = (lbaint_t)(ext_part_sector +
+ le32_to_int(pt->start4));
+ info->size = (lbaint_t)le32_to_int(pt->size4);
switch(dev_desc->if_type) {
case IF_TYPE_IDE:
case IF_TYPE_SATA:
part_num, which_part, info, disksig);
}
}
+
+ /* Check for DOS PBR if no partition is found */
+ dos_type = test_block_type(buffer);
+
+ if (dos_type == DOS_PBR) {
+ info->start = 0;
+ info->size = dev_desc->lba;
+ info->blksz = DOS_PART_DEFAULT_SECTOR;
+ info->bootable = 0;
+ sprintf ((char *)info->type, "U-Boot");
+#ifdef CONFIG_PARTITION_UUIDS
+ info->uuid[0] = 0;
+#endif
+ return 0;
+ }
+
return -1;
}
*/
/*
- * Problems with CONFIG_SYS_64BIT_LBA:
- *
- * struct disk_partition.start in include/part.h is sized as ulong.
- * When CONFIG_SYS_64BIT_LBA is activated, lbaint_t changes from ulong to uint64_t.
- * For now, it is cast back to ulong at assignment.
- *
- * This limits the maximum size of addressable storage to < 2 Terra Bytes
+ * NOTE:
+ * when CONFIG_SYS_64BIT_LBA is not defined, lbaint_t is 32 bits; this
+ * limits the maximum size of addressable storage to < 2 Terra Bytes
*/
#include <asm/unaligned.h>
#include <common.h>
static int pmbr_part_valid(struct partition *part);
static int is_pmbr_valid(legacy_mbr * mbr);
-static int is_gpt_valid(block_dev_desc_t * dev_desc, unsigned long long lba,
- gpt_header * pgpt_head, gpt_entry ** pgpt_pte);
+static int is_gpt_valid(block_dev_desc_t *dev_desc, u64 lba,
+ gpt_header *pgpt_head, gpt_entry **pgpt_pte);
static gpt_entry *alloc_read_gpt_entries(block_dev_desc_t * dev_desc,
gpt_header * pgpt_head);
static int is_pte_valid(gpt_entry * pte);
return -1;
}
- /* The ulong casting limits the maximum disk size to 2 TB */
- info->start = (u64)le64_to_cpu(gpt_pte[part - 1].starting_lba);
+ /* The 'lbaint_t' casting may limit the maximum disk size to 2 TB */
+ info->start = (lbaint_t)le64_to_cpu(gpt_pte[part - 1].starting_lba);
/* The ending LBA is inclusive, to calculate size, add 1 to it */
- info->size = ((u64)le64_to_cpu(gpt_pte[part - 1].ending_lba) + 1)
+ info->size = (lbaint_t)le64_to_cpu(gpt_pte[part - 1].ending_lba) + 1
- info->start;
info->blksz = dev_desc->blksz;
UUID_STR_FORMAT_GUID);
#endif
- debug("%s: start 0x" LBAF ", size 0x" LBAF ", name %s", __func__,
+ debug("%s: start 0x" LBAF ", size 0x" LBAF ", name %s\n", __func__,
info->start, info->size, info->name);
/* Remember to free pte */
return 0;
}
+int get_partition_info_efi_by_name(block_dev_desc_t *dev_desc,
+ const char *name, disk_partition_t *info)
+{
+ int ret;
+ int i;
+ for (i = 1; i < GPT_ENTRY_NUMBERS; i++) {
+ ret = get_partition_info_efi(dev_desc, i, info);
+ if (ret != 0) {
+ /* no more entries in table */
+ return -1;
+ }
+ if (strcmp(name, (const char *)info->name) == 0) {
+ /* matched */
+ return 0;
+ }
+ }
+ return -2;
+}
+
int test_part_efi(block_dev_desc_t * dev_desc)
{
ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, legacymbr, 1, dev_desc->blksz);
gpt_h->header_crc32 = cpu_to_le32(calc_crc32);
if (dev_desc->block_write(dev_desc->dev,
- le32_to_cpu(gpt_h->last_usable_lba + 1),
+ (lbaint_t)le64_to_cpu(gpt_h->last_usable_lba)
+ + 1,
pte_blk_cnt, gpt_e) != pte_blk_cnt)
goto err;
if (dev_desc->block_write(dev_desc->dev,
- le32_to_cpu(gpt_h->my_lba), 1, gpt_h) != 1)
+ (lbaint_t)le64_to_cpu(gpt_h->my_lba), 1,
+ gpt_h) != 1)
goto err;
debug("GPT successfully written to block device!\n");
int gpt_fill_pte(gpt_header *gpt_h, gpt_entry *gpt_e,
disk_partition_t *partitions, int parts)
{
- u32 offset = (u32)le32_to_cpu(gpt_h->first_usable_lba);
- ulong start;
+ lbaint_t offset = (lbaint_t)le64_to_cpu(gpt_h->first_usable_lba);
+ lbaint_t start;
+ lbaint_t last_usable_lba = (lbaint_t)
+ le64_to_cpu(gpt_h->last_usable_lba);
int i, k;
size_t efiname_len, dosname_len;
#ifdef CONFIG_PARTITION_UUIDS
gpt_e[i].starting_lba = cpu_to_le64(offset);
offset += partitions[i].size;
}
- if (offset >= gpt_h->last_usable_lba) {
+ if (offset >= last_usable_lba) {
printf("Partitions layout exceds disk size\n");
return -1;
}
gpt_e[i].partition_name[k] =
(efi_char16_t)(partitions[i].name[k]);
- debug("%s: name: %s offset[%d]: 0x%x size[%d]: 0x" LBAF "\n",
+ debug("%s: name: %s offset[%d]: 0x" LBAF
+ " size[%d]: 0x" LBAF "\n",
__func__, partitions[i].name, i,
offset, i, partitions[i].size);
}
* Description: returns 1 if valid, 0 on error.
* If valid, returns pointers to PTEs.
*/
-static int is_gpt_valid(block_dev_desc_t * dev_desc, unsigned long long lba,
- gpt_header * pgpt_head, gpt_entry ** pgpt_pte)
+static int is_gpt_valid(block_dev_desc_t *dev_desc, u64 lba,
+ gpt_header *pgpt_head, gpt_entry **pgpt_pte)
{
u32 crc32_backup = 0;
u32 calc_crc32;
- unsigned long long lastlba;
+ u64 lastlba;
if (!dev_desc || !pgpt_head) {
printf("%s: Invalid Argument(s)\n", __func__);
}
/* Read GPT Header from device */
- if (dev_desc->block_read(dev_desc->dev, lba, 1, pgpt_head) != 1) {
+ if (dev_desc->block_read(dev_desc->dev, (lbaint_t)lba, 1, pgpt_head)
+ != 1) {
printf("*** ERROR: Can't read GPT header ***\n");
return 0;
}
}
/* Check the first_usable_lba and last_usable_lba are within the disk. */
- lastlba = (unsigned long long)dev_desc->lba;
+ lastlba = (u64)dev_desc->lba;
if (le64_to_cpu(pgpt_head->first_usable_lba) > lastlba) {
printf("GPT: first_usable_lba incorrect: %llX > %llX\n",
le64_to_cpu(pgpt_head->first_usable_lba), lastlba);
}
if (le64_to_cpu(pgpt_head->last_usable_lba) > lastlba) {
printf("GPT: last_usable_lba incorrect: %llX > %llX\n",
- (u64) le64_to_cpu(pgpt_head->last_usable_lba), lastlba);
+ le64_to_cpu(pgpt_head->last_usable_lba), lastlba);
return 0;
}
/* Read GPT Entries from device */
blk_cnt = BLOCK_CNT(count, dev_desc);
if (dev_desc->block_read (dev_desc->dev,
- le64_to_cpu(pgpt_head->partition_entry_lba),
+ (lbaint_t)le64_to_cpu(pgpt_head->partition_entry_lba),
(lbaint_t) (blk_cnt), pte)
!= blk_cnt) {
To use this feature you will need to get the device tree compiler here:
- git://jdl.com/software/dtc.git
+ git://git.kernel.org/pub/scm/utils/dtc/dtc.git
For example:
- $ git clone git://jdl.com/software/dtc.git
+ $ git clone git://git.kernel.org/pub/scm/utils/dtc/dtc.git
$ cd dtc
$ make
$ sudo make install
arch/<arch>/dts, and then make any adjustments required.
If CONFIG_OF_EMBED is defined, then it will be picked up and built into
-the U-Boot image (including u-boot.bin).
+the U-Boot image (including u-boot.bin). This is suitable for debugging
+and development only and is not recommended for production devices.
If CONFIG_OF_SEPARATE is defined, then it will be built and placed in
a u-boot.dtb file alongside u-boot.bin. A common approach is then to
cat u-boot.bin u-boot.dtb >image.bin
-and then flash image.bin onto your board.
+and then flash image.bin onto your board. Note that U-Boot creates
+u-boot-dtb.bin which does the above step for you also. If you are using
+CONFIG_SPL_FRAMEWORK, then u-boot.img will be built to include the device
+tree binary.
If CONFIG_OF_HOSTFILE is defined, then it will be read from a file on
startup. This is only useful for sandbox. Use the -d flag to U-Boot to
You cannot use more than one of these options at the same time.
+To use a device tree file that you have compiled yourself, pass
+EXT_DTB=<filename> to 'make', as in:
+
+ make EXT_DTB=boot/am335x-boneblack-pubkey.dtb
+
+Then U-Boot will copy that file to u-boot.dtb, put it in the .img file
+if used, and u-boot-dtb.bin.
+
If you wish to put the fdt at a different address in memory, you can
define the "fdtcontroladdr" environment variable. This is the hex
address of the fdt binary blob, and will override either of the options.
2) Compiling U-Boot for a MXS based board
3) Installation of U-Boot for a MXS based board to SD card
4) Installation of U-Boot into NAND flash on a MX28 based board
+5) Installation of U-boot into SPI NOR flash on a MX28 based board
1) Prerequisites
----------------
In case the user needs to boot a firmware image bigger than 1Mb, the
user has to adjust the "update_nand_firmware_maxsz" variable for the
update scripts to work properly.
+
+5) Installation of U-Boot into SPI NOR flash on a MX28 based board
+------------------------------------------------------------------
+
+The u-boot.sb file can be directly written to SPI NOR from U-boot prompt.
+
+Load u-boot.sb into RAM, this can be done in several ways and one way is to use
+tftp:
+ => tftp u-boot.sb 0x42000000
+
+Probe the SPI NOR flash:
+ => sf probe
+
+(SPI NOR should be succesfully detected in this step)
+
+Erase the blocks where U-boot binary will be written to:
+ => sf erase 0x0 0x80000
+
+Write u-boot.sb to SPI NOR:
+ => sf write 0x42000000 0 0x80000
+
+Power off the board and set the boot mode DIP switches to boot from the SPI NOR
+according to MX28 manual section 12.2.1 (Table 12-2)
+
+Last step is to power up the board and U-boot should start from SPI NOR.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
-lubbock arm pxa - 2014-04-04 Kyle Harris <kharris@nexus-tech.net>
-MOUSSE powerpc mpc824x - 2014-04-04
-rsdproto powerpc mpc8260 - 2014-04-04
-RPXsuper powerpc mpc8260 - 2014-04-04
-RPXClassic powerpc mpc8xx - 2014-04-04
-RPXlite powerpc mpc8xx - 2014-04-04
-genietv powerpc mpc8xx - 2014-04-04
-mbx8xx powerpc mpc8xx - 2014-04-04
-nx823 powerpc mpc8xx - 2014-04-04
+simpc8313 powerpc mpc83xx - 2014-04-28 Ron Madrid <info@sheldoninst.com>
+hidden_dragon powerpc mpc824x 3fe1a854 2014-05-30 Yusdi Santoso <yusdi_santoso@adaptec.com>
+debris powerpc mpc824x 7edb1f7b 2014-05-30 Sangmoon Kim <dogoil@etinsys.com>
+kvme080 powerpc mpc824x 2868f862 2014-05-30 Sangmoon Kim <dogoil@etinsys.com>
+ep8248 powerpc mpc8260 49ad566d 2014-05-30 Yuli Barcohen <yuli@arabellasw.com>
+ispan powerpc mpc8260 80bae39a 2014-05-30 Yuli Barcohen <yuli@arabellasw.com>
+rattler powerpc mpc8260 d0664db4 2014-05-30 Yuli Barcohen <yuli@arabellasw.com>
+zpc1900 powerpc mpc8260 6f80bb48 2014-05-30 Yuli Barcohen <yuli@arabellasw.com>
+mpc8260ads powerpc mpc8260 facb6725 2014-05-30 Yuli Barcohen <yuli@arabellasw.com>
+adder powerpc mpc8xx 373a9788 2014-05-30 Yuli Barcohen <yuli@arabellasw.com>
+quad100hd powerpc ppc405ep 3569571d 2014-05-30 Gary Jennejohn <gljennjohn@googlemail.com>
+lubbock arm pxa 36bf57b 2014-04-18 Kyle Harris <kharris@nexus-tech.net>
+EVB64260 powerpc mpc824x bb3aef9 2014-04-18
+MOUSSE powerpc mpc824x 03f2ecc 2014-04-18
+rsdproto powerpc mpc8260 8b043e6 2014-04-18
+RPXsuper powerpc mpc8260 0ebf5f5 2014-04-18
+RPXClassic powerpc mpc8xx 4fb3925 2014-04-18
+RPXlite powerpc mpc8xx 4fb3925 2014-04-18
+FADS powerpc mpc8xx aa6e1e4 2014-04-18
+genietv powerpc mpc8xx b8a49bd 2014-04-18
+mbx8xx powerpc mpc8xx d6b11fd 2014-04-18
+nx823 powerpc mpc8xx a146e8b 2014-04-18
idmr m68k mcf52x2 ba650e9b 2014-01-28
M5271EVB m68k mcf52x2 ba650e9b 2014-01-28
dvl_host arm ixp e317de6b 2014-01-28 Michael Schwingen <michael@schwingen.org>
-----------
Uclass - a group of devices which operate in the same way. A uclass provides
- a way of accessing invidual devices within the group, but always
+ a way of accessing individual devices within the group, but always
using the same interface. For example a GPIO uclass provides
operations for get/set value. An I2C uclass may have 10 I2C ports,
4 with one driver, and 6 with another.
-----------------
Let's start at the top. The demo command is in common/cmd_demo.c. It does
-the usual command procesing and then:
+the usual command processing and then:
- struct device *demo_dev;
+ struct udevice *demo_dev;
ret = uclass_get_device(UCLASS_DEMO, devnum, &demo_dev);
The code for demo_hello() is in drivers/demo/demo-uclass.c:
-int demo_hello(struct device *dev, int ch)
+int demo_hello(struct udevice *dev, int ch)
{
const struct demo_ops *ops = device_get_ops(dev);
As you can see it just calls the relevant driver method. One of these is
in drivers/demo/demo-simple.c:
-static int simple_hello(struct device *dev, int ch)
+static int simple_hello(struct udevice *dev, int ch)
{
const struct dm_demo_pdata *pdata = dev_get_platdata(dev);
Platform Data
-------------
-Where does the platform data come from? See demo-pdata.c which
+Platform data is like Linux platform data, if you are familiar with that.
+It provides the board-specific information to start up a device.
+
+Why is this information not just stored in the device driver itself? The
+idea is that the device driver is generic, and can in principle operate on
+any board that has that type of device. For example, with modern
+highly-complex SoCs it is common for the IP to come from an IP vendor, and
+therefore (for example) the MMC controller may be the same on chips from
+different vendors. It makes no sense to write independent drivers for the
+MMC controller on each vendor's SoC, when they are all almost the same.
+Similarly, we may have 6 UARTs in an SoC, all of which are mostly the same,
+but lie at different addresses in the address space.
+
+Using the UART example, we have a single driver and it is instantiated 6
+times by supplying 6 lots of platform data. Each lot of platform data
+gives the driver name and a pointer to a structure containing information
+about this instance - e.g. the address of the register space. It may be that
+one of the UARTS supports RS-485 operation - this can be added as a flag in
+the platform data, which is set for this one port and clear for the rest.
+
+Think of your driver as a generic piece of code which knows how to talk to
+a device, but needs to know where it is, any variant/option information and
+so on. Platform data provides this link between the generic piece of code
+and the specific way it is bound on a particular board.
+
+Examples of platform data include:
+
+ - The base address of the IP block's register space
+ - Configuration options, like:
+ - the SPI polarity and maximum speed for a SPI controller
+ - the I2C speed to use for an I2C device
+ - the number of GPIOs available in a GPIO device
+
+Where does the platform data come from? It is either held in a structure
+which is compiled into U-Boot, or it can be parsed from the Device Tree
+(see 'Device Tree' below).
+
+For an example of how it can be compiled in, see demo-pdata.c which
sets up a table of driver names and their associated platform data.
The data can be interpreted by the drivers however they like - it is
basically a communication scheme between the board-specific code and
the generic drivers, which are intended to work on any board.
-Drivers can acceess their data via dev->info->platdata. Here is
+Drivers can access their data via dev->info->platdata. Here is
the declaration for the platform data, which would normally appear
in the board file.
sides = <4>;
};
+This means that instead of having lots of U_BOOT_DEVICE() declarations in
+the board file, we put these in the device tree. This approach allows a lot
+more generality, since the same board file can support many types of boards
+(e,g. with the same SoC) just by using different device trees. An added
+benefit is that the Linux device tree can be used, thus further simplifying
+the task of board-bring up either for U-Boot or Linux devs (whoever gets to
+the board first!).
The easiest way to make this work it to add a few members to the driver:
.platdata_auto_alloc_size = sizeof(struct dm_test_pdata),
.ofdata_to_platdata = testfdt_ofdata_to_platdata,
- .probe = testfdt_drv_probe,
The 'auto_alloc' feature allowed space for the platdata to be allocated
-and zeroed before the driver's ofdata_to_platdata method is called. This
-method reads the information out of the device tree and puts it in
-dev->platdata. Then the probe method is called to set up the device.
+and zeroed before the driver's ofdata_to_platdata() method is called. The
+ofdata_to_platdata() method, which the driver write supplies, should parse
+the device tree node for this device and place it in dev->platdata. Thus
+when the probe method is called later (to set up the device ready for use)
+the platform data will be present.
Note that both methods are optional. If you provide an ofdata_to_platdata
-method then it wlil be called first (after bind). If you provide a probe
-method it will be called next.
+method then it will be called first (during activation). If you provide a
+probe method it will be called next. See Driver Lifecycle below for more
+details.
If you don't want to have the platdata automatically allocated then you
can leave out platdata_auto_alloc_size. In this case you can use malloc
end of the enum there, then declare your uclass as above.
+Driver Lifecycle
+----------------
+
+Here are the stages that a device goes through in driver model. Note that all
+methods mentioned here are optional - e.g. if there is no probe() method for
+a device then it will not be called. A simple device may have very few
+methods actually defined.
+
+1. Bind stage
+
+A device and its driver are bound using one of these two methods:
+
+ - Scan the U_BOOT_DEVICE() definitions. U-Boot It looks up the
+name specified by each, to find the appropriate driver. It then calls
+device_bind() to create a new device and bind' it to its driver. This will
+call the device's bind() method.
+
+ - Scan through the device tree definitions. U-Boot looks at top-level
+nodes in the the device tree. It looks at the compatible string in each node
+and uses the of_match part of the U_BOOT_DRIVER() structure to find the
+right driver for each node. It then calls device_bind() to bind the
+newly-created device to its driver (thereby creating a device structure).
+This will also call the device's bind() method.
+
+At this point all the devices are known, and bound to their drivers. There
+is a 'struct udevice' allocated for all devices. However, nothing has been
+activated (except for the root device). Each bound device that was created
+from a U_BOOT_DEVICE() declaration will hold the platdata pointer specified
+in that declaration. For a bound device created from the device tree,
+platdata will be NULL, but of_offset will be the offset of the device tree
+node that caused the device to be created. The uclass is set correctly for
+the device.
+
+The device's bind() method is permitted to perform simple actions, but
+should not scan the device tree node, not initialise hardware, nor set up
+structures or allocate memory. All of these tasks should be left for
+the probe() method.
+
+Note that compared to Linux, U-Boot's driver model has a separate step of
+probe/remove which is independent of bind/unbind. This is partly because in
+U-Boot it may be expensive to probe devices and we don't want to do it until
+they are needed, or perhaps until after relocation.
+
+2. Activation/probe
+
+When a device needs to be used, U-Boot activates it, by following these
+steps (see device_probe()):
+
+ a. If priv_auto_alloc_size is non-zero, then the device-private space
+ is allocated for the device and zeroed. It will be accessible as
+ dev->priv. The driver can put anything it likes in there, but should use
+ it for run-time information, not platform data (which should be static
+ and known before the device is probed).
+
+ b. If platdata_auto_alloc_size is non-zero, then the platform data space
+ is allocated. This is only useful for device tree operation, since
+ otherwise you would have to specific the platform data in the
+ U_BOOT_DEVICE() declaration. The space is allocated for the device and
+ zeroed. It will be accessible as dev->platdata.
+
+ c. If the device's uclass specifies a non-zero per_device_auto_alloc_size,
+ then this space is allocated and zeroed also. It is allocated for and
+ stored in the device, but it is uclass data. owned by the uclass driver.
+ It is possible for the device to access it.
+
+ d. All parent devices are probed. It is not possible to activate a device
+ unless its predecessors (all the way up to the root device) are activated.
+ This means (for example) that an I2C driver will require that its bus
+ be activated.
+
+ e. If the driver provides an ofdata_to_platdata() method, then this is
+ called to convert the device tree data into platform data. This should
+ do various calls like fdtdec_get_int(gd->fdt_blob, dev->of_offset, ...)
+ to access the node and store the resulting information into dev->platdata.
+ After this point, the device works the same way whether it was bound
+ using a device tree node or U_BOOT_DEVICE() structure. In either case,
+ the platform data is now stored in the platdata structure. Typically you
+ will use the platdata_auto_alloc_size feature to specify the size of the
+ platform data structure, and U-Boot will automatically allocate and zero
+ it for you before entry to ofdata_to_platdata(). But if not, you can
+ allocate it yourself in ofdata_to_platdata(). Note that it is preferable
+ to do all the device tree decoding in ofdata_to_platdata() rather than
+ in probe(). (Apart from the ugliness of mixing configuration and run-time
+ data, one day it is possible that U-Boot will cache platformat data for
+ devices which are regularly de/activated).
+
+ f. The device's probe() method is called. This should do anything that
+ is required by the device to get it going. This could include checking
+ that the hardware is actually present, setting up clocks for the
+ hardware and setting up hardware registers to initial values. The code
+ in probe() can access:
+
+ - platform data in dev->platdata (for configuration)
+ - private data in dev->priv (for run-time state)
+ - uclass data in dev->uclass_priv (for things the uclass stores
+ about this device)
+
+ Note: If you don't use priv_auto_alloc_size then you will need to
+ allocate the priv space here yourself. The same applies also to
+ platdata_auto_alloc_size. Remember to free them in the remove() method.
+
+ g. The device is marked 'activated'
+
+ h. The uclass's post_probe() method is called, if one exists. This may
+ cause the uclass to do some housekeeping to record the device as
+ activated and 'known' by the uclass.
+
+3. Running stage
+
+The device is now activated and can be used. From now until it is removed
+all of the above structures are accessible. The device appears in the
+uclass's list of devices (so if the device is in UCLASS_GPIO it will appear
+as a device in the GPIO uclass). This is the 'running' state of the device.
+
+4. Removal stage
+
+When the device is no-longer required, you can call device_remove() to
+remove it. This performs the probe steps in reverse:
+
+ a. The uclass's pre_remove() method is called, if one exists. This may
+ cause the uclass to do some housekeeping to record the device as
+ deactivated and no-longer 'known' by the uclass.
+
+ b. All the device's children are removed. It is not permitted to have
+ an active child device with a non-active parent. This means that
+ device_remove() is called for all the children recursively at this point.
+
+ c. The device's remove() method is called. At this stage nothing has been
+ deallocated so platform data, private data and the uclass data will all
+ still be present. This is where the hardware can be shut down. It is
+ intended that the device be completely inactive at this point, For U-Boot
+ to be sure that no hardware is running, it should be enough to remove
+ all devices.
+
+ d. The device memory is freed (platform data, private data, uclass data).
+
+ Note: Because the platform data for a U_BOOT_DEVICE() is defined with a
+ static pointer, it is not de-allocated during the remove() method. For
+ a device instantiated using the device tree data, the platform data will
+ be dynamically allocated, and thus needs to be deallocated during the
+ remove() method, either:
+
+ 1. if the platdata_auto_alloc_size is non-zero, the deallocation
+ happens automatically within the driver model core; or
+
+ 2. when platdata_auto_alloc_size is 0, both the allocation (in probe()
+ or preferably ofdata_to_platdata()) and the deallocation in remove()
+ are the responsibility of the driver author.
+
+ e. The device is marked inactive. Note that it is still bound, so the
+ device structure itself is not freed at this point. Should the device be
+ activated again, then the cycle starts again at step 2 above.
+
+5. Unbind stage
+
+The device is unbound. This is the step that actually destroys the device.
+If a parent has children these will be destroyed first. After this point
+the device does not exist and its memory has be deallocated.
+
+
Data Structures
---------------
For the record, this implementation uses a very similar approach to the
original patches, but makes at least the following changes:
-- Tried to agressively remove boilerplate, so that for most drivers there
+- Tried to aggressively remove boilerplate, so that for most drivers there
is little or no 'driver model' code to write.
- Moved some data from code into data structure - e.g. store a pointer to
the driver operations structure in the driver, rather than passing it
to the driver bind function.
-- Rename some structures to make them more similar to Linux (struct device
+- Rename some structures to make them more similar to Linux (struct udevice
instead of struct instance, struct platdata, etc.)
- Change the name 'core' to 'uclass', meaning U-Boot class. It seems that
this concept relates to a class of drivers (or a subsystem). We shouldn't
use 'class' since it is a C++ reserved word, so U-Boot class (uclass) seems
better than 'core'.
-- Remove 'struct driver_instance' and just use a single 'struct device'.
+- Remove 'struct driver_instance' and just use a single 'struct udevice'.
This removes a level of indirection that doesn't seem necessary.
- Built in device tree support, to avoid the need for platdata
- Removed the concept of driver relocation, and just make it possible for
--- /dev/null
+Verified Boot on the Beaglebone Black
+=====================================
+
+Introduction
+------------
+
+Before reading this, please read verified-boot.txt and signature.txt. These
+instructions are for mainline U-Boot from v2014.07 onwards.
+
+There is quite a bit of documentation in this directory describing how
+verified boot works in U-Boot. There is also a test which runs through the
+entire process of signing an image and running U-Boot (sandbox) to check it.
+However, it might be useful to also have an example on a real board.
+
+Beaglebone Black is a fairly common board so seems to be a reasonable choice
+for an example of how to enable verified boot using U-Boot.
+
+First a note that may to help avoid confusion. U-Boot and Linux both use
+device tree. They may use the same device tree source, but it is seldom useful
+for them to use the exact same binary from the same place. More typically,
+U-Boot has its device tree packaged wtih it, and the kernel's device tree is
+packaged with the kernel. In particular this is important with verified boot,
+since U-Boot's device tree must be immutable. If it can be changed then the
+public keys can be changed and verified boot is useless. An attacker can
+simply generate a new key and put his public key into U-Boot so that
+everything verifies. On the other hand the kernel's device tree typically
+changes when the kernel changes, so it is useful to package an updated device
+tree with the kernel binary. U-Boot supports the latter with its flexible FIT
+format (Flat Image Tree).
+
+
+Overview
+--------
+
+The steps are roughly as follows:
+
+1. Build U-Boot for the board, with the verified boot options enabled.
+
+2. Obtain a suitable Linux kernel
+
+3. Create a Image Tree Source file (ITS) file describing how you want the
+kernel to be packaged, compressed and signed.
+
+4. Create a key pair
+
+5. Sign the kernel
+
+6. Put the public key into U-Boot's image
+
+7. Put U-Boot and the kernel onto the board
+
+8. Try it
+
+
+Step 1: Build U-Boot
+--------------------
+
+a. Set up the environment variable to point to your toolchain. You will need
+this for U-Boot and also for the kernel if you build it. For example if you
+installed a Linaro version manually it might be something like:
+
+ export CROSS_COMPILE=/opt/linaro/gcc-linaro-arm-linux-gnueabihf-4.8-2013.08_linux/bin/arm-linux-gnueabihf-
+
+or if you just installed gcc-arm-linux-gnueabi then it might be
+
+ export CROSS_COMPILE=arm-linux-gnueabi-
+
+b. Configure and build U-Boot with verified boot enabled:
+
+ export ARCH=arm
+ export UBOOT=/path/to/u-boot
+ cd $UBOOT
+ # You can add -j10 if you have 10 CPUs to make it faster
+ make O=b/am335x_boneblack_vboot am335x_boneblack_vboot_config all
+ export UOUT=$UBOOT/b/am335x_boneblack_vboot
+
+c. You will now have a U-Boot image:
+
+ file b/am335x_boneblack_vboot/u-boot-dtb.img
+b/am335x_boneblack_vboot/u-boot-dtb.img: u-boot legacy uImage, U-Boot 2014.07-rc2-00065-g2f69f8, Firmware/ARM, Firmware Image (Not compressed), 395375 bytes, Sat May 31 16:19:04 2014, Load Address: 0x80800000, Entry Point: 0x00000000, Header CRC: 0x0ABD6ACA, Data CRC: 0x36DEF7E4
+
+
+Step 2: Build Linux
+--------------------
+
+a. Find the kernel image ('Image') and device tree (.dtb) file you plan to
+use. In our case it is am335x-boneblack.dtb and it is built with the kernel.
+At the time of writing an SD Boot image can be obtained from here:
+
+ http://www.elinux.org/Beagleboard:Updating_The_Software#Image_For_Booting_From_microSD
+
+You can write this to an SD card and then mount it to extract the kernel and
+device tree files.
+
+You can also build a kernel. Instructions for this are are here:
+
+ http://elinux.org/Building_BBB_Kernel
+
+or you can use your favourite search engine. Following these instructions
+produces a kernel Image and device tree files. For the record the steps were:
+
+ export KERNEL=/path/to/kernel
+ cd $KERNEL
+ git clone git://github.com/beagleboard/kernel.git .
+ git checkout v3.14
+ ./patch.sh
+ cp configs/beaglebone kernel/arch/arm/configs/beaglebone_defconfig
+ cd kernel
+ make beaglebone_defconfig
+ make uImage dtbs # -j10 if you have 10 CPUs
+ export OKERNEL=$KERNEL/kernel/arch/arm/boot
+
+c. You now have the 'Image' and 'am335x-boneblack.dtb' files needed to boot.
+
+
+Step 3: Create the ITS
+----------------------
+
+Set up a directory for your work.
+
+ export WORK=/path/to/dir
+ cd $WORK
+
+Put this into a file in that directory called sign.its:
+
+/dts-v1/;
+
+/ {
+ description = "Beaglebone black";
+ #address-cells = <1>;
+
+ images {
+ kernel@1 {
+ data = /incbin/("Image.lzo");
+ type = "kernel";
+ arch = "arm";
+ os = "linux";
+ compression = "lzo";
+ load = <0x80008000>;
+ entry = <0x80008000>;
+ hash@1 {
+ algo = "sha1";
+ };
+ };
+ fdt@1 {
+ description = "beaglebone-black";
+ data = /incbin/("am335x-boneblack.dtb");
+ type = "flat_dt";
+ arch = "arm";
+ compression = "none";
+ hash@1 {
+ algo = "sha1";
+ };
+ };
+ };
+ configurations {
+ default = "conf@1";
+ conf@1 {
+ kernel = "kernel@1";
+ fdt = "fdt@1";
+ signature@1 {
+ algo = "sha1,rsa2048";
+ key-name-hint = "dev";
+ sign-images = "fdt", "kernel";
+ };
+ };
+ };
+};
+
+
+The explanation for this is all in the documentation you have already read.
+But briefly it packages a kernel and device tree, and provides a single
+configuration to be signed with a key named 'dev'. The kernel is compressed
+with LZO to make it smaller.
+
+
+Step 4: Create a key pair
+-------------------------
+
+See signature.txt for details on this step.
+
+ cd $WORK
+ mkdir keys
+ openssl genrsa -F4 -out keys/dev.key 2048
+ openssl req -batch -new -x509 -key keys/dev.key -out keys/dev.crt
+
+Note: keys/dev.key contains your private key and is very secret. If anyone
+gets access to that file they can sign kernels with it. Keep it secure.
+
+
+Step 5: Sign the kernel
+-----------------------
+
+We need to use mkimage (which was built when you built U-Boot) to package the
+Linux kernel into a FIT (Flat Image Tree, a flexible file format that U-Boot
+can load) using the ITS file you just created.
+
+At the same time we must put the public key into U-Boot device tree, with the
+'required' property, which tells U-Boot that this key must be verified for the
+image to be valid. You will make this key available to U-Boot for booting in
+step 6.
+
+ ln -s $OKERNEL/dts/am335x-boneblack.dtb
+ ln -s $OKERNEL/Image
+ ln -s $UOUT/u-boot-dtb.img
+ cp $UOUT/arch/arm/dts/am335x-boneblack.dtb am335x-boneblack-pubkey.dtb
+ lzop Image
+ $UOUT/tools/mkimage -f sign.its -K am335x-boneblack-pubkey.dtb -k keys -r image.fit
+
+You should see something like this:
+
+FIT description: Beaglebone black
+Created: Sun Jun 1 12:50:30 2014
+ Image 0 (kernel@1)
+ Description: unavailable
+ Created: Sun Jun 1 12:50:30 2014
+ Type: Kernel Image
+ Compression: lzo compressed
+ Data Size: 7790938 Bytes = 7608.34 kB = 7.43 MB
+ Architecture: ARM
+ OS: Linux
+ Load Address: 0x80008000
+ Entry Point: 0x80008000
+ Hash algo: sha1
+ Hash value: c94364646427e10f423837e559898ef02c97b988
+ Image 1 (fdt@1)
+ Description: beaglebone-black
+ Created: Sun Jun 1 12:50:30 2014
+ Type: Flat Device Tree
+ Compression: uncompressed
+ Data Size: 31547 Bytes = 30.81 kB = 0.03 MB
+ Architecture: ARM
+ Hash algo: sha1
+ Hash value: cb09202f889d824f23b8e4404b781be5ad38a68d
+ Default Configuration: 'conf@1'
+ Configuration 0 (conf@1)
+ Description: unavailable
+ Kernel: kernel@1
+ FDT: fdt@1
+
+
+Now am335x-boneblack-pubkey.dtb contains the public key and image.fit contains
+the signed kernel. Jump to step 6 if you like, or continue reading to increase
+your understanding.
+
+You can also run fit_check_sign to check it:
+
+ $UOUT/tools/fit_check_sign -f image.fit -k am335x-boneblack-pubkey.dtb
+
+which results in:
+
+Verifying Hash Integrity ... sha1,rsa2048:dev+
+## Loading kernel from FIT Image at 7fc6ee469000 ...
+ Using 'conf@1' configuration
+ Verifying Hash Integrity ...
+sha1,rsa2048:dev+
+OK
+
+ Trying 'kernel@1' kernel subimage
+ Description: unavailable
+ Created: Sun Jun 1 12:50:30 2014
+ Type: Kernel Image
+ Compression: lzo compressed
+ Data Size: 7790938 Bytes = 7608.34 kB = 7.43 MB
+ Architecture: ARM
+ OS: Linux
+ Load Address: 0x80008000
+ Entry Point: 0x80008000
+ Hash algo: sha1
+ Hash value: c94364646427e10f423837e559898ef02c97b988
+ Verifying Hash Integrity ...
+sha1+
+OK
+
+Unimplemented compression type 4
+## Loading fdt from FIT Image at 7fc6ee469000 ...
+ Using 'conf@1' configuration
+ Trying 'fdt@1' fdt subimage
+ Description: beaglebone-black
+ Created: Sun Jun 1 12:50:30 2014
+ Type: Flat Device Tree
+ Compression: uncompressed
+ Data Size: 31547 Bytes = 30.81 kB = 0.03 MB
+ Architecture: ARM
+ Hash algo: sha1
+ Hash value: cb09202f889d824f23b8e4404b781be5ad38a68d
+ Verifying Hash Integrity ...
+sha1+
+OK
+
+ Loading Flat Device Tree ... OK
+
+## Loading ramdisk from FIT Image at 7fc6ee469000 ...
+ Using 'conf@1' configuration
+Could not find subimage node
+
+Signature check OK
+
+
+At the top, you see "sha1,rsa2048:dev+". This means that it checked an RSA key
+of size 2048 bits using SHA1 as the hash algorithm. The key name checked was
+'dev' and the '+' means that it verified. If it showed '-' that would be bad.
+
+Once the configuration is verified it is then possible to rely on the hashes
+in each image referenced by that configuration. So fit_check_sign goes on to
+load each of the images. We have a kernel and an FDT but no ramkdisk. In each
+case fit_check_sign checks the hash and prints sha1+ meaning that the SHA1
+hash verified. This means that none of the images has been tampered with.
+
+There is a test in test/vboot which uses U-Boot's sandbox build to verify that
+the above flow works.
+
+But it is fun to do this by hand, so you can load image.fit into a hex editor
+like ghex, and change a byte in the kernel:
+
+ $UOUT/tools/fit_info -f image.fit -n /images/kernel@1 -p data
+NAME: kernel@1
+LEN: 7790938
+OFF: 168
+
+This tells us that the kernel starts at byte offset 168 (decimal) in image.fit
+and extends for about 7MB. Try changing a byte at 0x2000 (say) and run
+fit_check_sign again. You should see something like:
+
+Verifying Hash Integrity ... sha1,rsa2048:dev+
+## Loading kernel from FIT Image at 7f5a39571000 ...
+ Using 'conf@1' configuration
+ Verifying Hash Integrity ...
+sha1,rsa2048:dev+
+OK
+
+ Trying 'kernel@1' kernel subimage
+ Description: unavailable
+ Created: Sun Jun 1 13:09:21 2014
+ Type: Kernel Image
+ Compression: lzo compressed
+ Data Size: 7790938 Bytes = 7608.34 kB = 7.43 MB
+ Architecture: ARM
+ OS: Linux
+ Load Address: 0x80008000
+ Entry Point: 0x80008000
+ Hash algo: sha1
+ Hash value: c94364646427e10f423837e559898ef02c97b988
+ Verifying Hash Integrity ...
+sha1 error
+Bad hash value for 'hash@1' hash node in 'kernel@1' image node
+Bad Data Hash
+
+## Loading fdt from FIT Image at 7f5a39571000 ...
+ Using 'conf@1' configuration
+ Trying 'fdt@1' fdt subimage
+ Description: beaglebone-black
+ Created: Sun Jun 1 13:09:21 2014
+ Type: Flat Device Tree
+ Compression: uncompressed
+ Data Size: 31547 Bytes = 30.81 kB = 0.03 MB
+ Architecture: ARM
+ Hash algo: sha1
+ Hash value: cb09202f889d824f23b8e4404b781be5ad38a68d
+ Verifying Hash Integrity ...
+sha1+
+OK
+
+ Loading Flat Device Tree ... OK
+
+## Loading ramdisk from FIT Image at 7f5a39571000 ...
+ Using 'conf@1' configuration
+Could not find subimage node
+
+Signature check Bad (error 1)
+
+
+It has detected the change in the kernel.
+
+You can also be sneaky and try to switch images, using the libfdt utilities
+that come with dtc (package name is device-tree-compiler but you will need a
+recent version like 1.4:
+
+ dtc -v
+Version: DTC 1.4.0
+
+First we can check which nodes are actually hashed by the configuration:
+
+ fdtget -l image.fit /
+images
+configurations
+
+ fdtget -l image.fit /configurations
+conf@1
+fdtget -l image.fit /configurations/conf@1
+signature@1
+
+ fdtget -p image.fit /configurations/conf@1/signature@1
+hashed-strings
+hashed-nodes
+timestamp
+signer-version
+signer-name
+value
+algo
+key-name-hint
+sign-images
+
+ fdtget image.fit /configurations/conf@1/signature@1 hashed-nodes
+/ /configurations/conf@1 /images/fdt@1 /images/fdt@1/hash@1 /images/kernel@1 /images/kernel@1/hash@1
+
+This gives us a bit of a look into the signature that mkimage added. Note you
+can also use fdtdump to list the entire device tree.
+
+Say we want to change the kernel that this configuration uses
+(/images/kernel@1). We could just put a new kernel in the image, but we will
+need to change the hash to match. Let's simulate that by changing a byte of
+the hash:
+
+ fdtget -tx image.fit /images/kernel@1/hash@1 value
+c9436464 6427e10f 423837e5 59898ef0 2c97b988
+ fdtput -tx image.fit /images/kernel@1/hash@1 value c9436464 6427e10f 423837e5 59898ef0 2c97b981
+
+Now check it again:
+
+ $UOUT/tools/fit_check_sign -f image.fit -k am335x-boneblack-pubkey.dtb
+Verifying Hash Integrity ... sha1,rsa2048:devrsa_verify_with_keynode: RSA failed to verify: -13
+rsa_verify_with_keynode: RSA failed to verify: -13
+-
+Failed to verify required signature 'key-dev'
+Signature check Bad (error 1)
+
+This time we don't even get as far as checking the images, since the
+configuration signature doesn't match. We can't change any hashes without the
+signature check noticing. The configuration is essentially locked. U-Boot has
+a public key for which it requires a match, and will not permit the use of any
+configuration that does not match that public key. The only way the
+configuration will match is if it was signed by the matching private key.
+
+It would also be possible to add a new signature node that does match your new
+configuration. But that won't work since you are not allowed to change the
+configuration in any way. Try it with a fresh (valid) image if you like by
+running the mkimage link again. Then:
+
+ fdtput -p image.fit /configurations/conf@1/signature@2 value fred
+ $UOUT/tools/fit_check_sign -f image.fit -k am335x-boneblack-pubkey.dtb
+Verifying Hash Integrity ... -
+sha1,rsa2048:devrsa_verify_with_keynode: RSA failed to verify: -13
+rsa_verify_with_keynode: RSA failed to verify: -13
+-
+Failed to verify required signature 'key-dev'
+Signature check Bad (error 1)
+
+
+Of course it would be possible to add an entirely new configuration and boot
+with that, but it still needs to be signed, so it won't help.
+
+
+6. Put the public key into U-Boot's image
+-----------------------------------------
+
+Having confirmed that the signature is doing its job, let's try it out in
+U-Boot on the board. U-Boot needs access to the public key corresponding to
+the private key that you signed with so that it can verify any kernels that
+you sign.
+
+ cd $UBOOT
+ make O=b/am335x_boneblack_vboot EXT_DTB=${WORK}/am335x-boneblack-pubkey.dtb
+
+Here we are overrriding the normal device tree file with our one, which
+contains the public key.
+
+Now you have a special U-Boot image with the public key. It can verify can
+kernel that you sign with the private key as in step 5.
+
+If you like you can take a look at the public key information that mkimage
+added to U-Boot's device tree:
+
+ fdtget -p am335x-boneblack-pubkey.dtb /signature/key-dev
+required
+algo
+rsa,r-squared
+rsa,modulus
+rsa,n0-inverse
+rsa,num-bits
+key-name-hint
+
+This has information about the key and some pre-processed values which U-Boot
+can use to verify against it. These values are obtained from the public key
+certificate by mkimage, but require quite a bit of code to generate. To save
+code space in U-Boot, the information is extracted and written in raw form for
+U-Boot to easily use. The same mechanism is used in Google's Chrome OS.
+
+Notice the 'required' property. This marks the key as required - U-Boot will
+not boot any image that does not verify against this key.
+
+
+7. Put U-Boot and the kernel onto the board
+-------------------------------------------
+
+The method here varies depending on how you are booting. For this example we
+are booting from an micro-SD card with two partitions, one for U-Boot and one
+for Linux. Put it into your machine and write U-Boot and the kernel to it.
+Here the card is /dev/sde:
+
+ cd $WORK
+ export UDEV=/dev/sde1 # Change thes two lines to the correct device
+ export KDEV=/dev/sde2
+ sudo mount $UDEV /mnt/tmp && sudo cp $UOUT/u-boot-dtb.img /mnt/tmp/u-boot.img && sleep 1 && sudo umount $UDEV
+ sudo mount $KDEV /mnt/tmp && sudo cp $WORK/image.fit /mnt/tmp/boot/image.fit && sleep 1 && sudo umount $KDEV
+
+
+8. Try it
+---------
+
+Boot the board using the commands below:
+
+ setenv bootargs console=ttyO0,115200n8 quiet root=/dev/mmcblk0p2 ro rootfstype=ext4 rootwait
+ ext2load mmc 0:2 82000000 /boot/image.fit
+ bootm 82000000
+
+You should then see something like this:
+
+U-Boot# setenv bootargs console=ttyO0,115200n8 quiet root=/dev/mmcblk0p2 ro rootfstype=ext4 rootwait
+U-Boot# ext2load mmc 0:2 82000000 /boot/image.fit
+7824930 bytes read in 589 ms (12.7 MiB/s)
+U-Boot# bootm 82000000
+## Loading kernel from FIT Image at 82000000 ...
+ Using 'conf@1' configuration
+ Verifying Hash Integrity ... sha1,rsa2048:dev+ OK
+ Trying 'kernel@1' kernel subimage
+ Description: unavailable
+ Created: 2014-06-01 19:32:54 UTC
+ Type: Kernel Image
+ Compression: lzo compressed
+ Data Start: 0x820000a8
+ Data Size: 7790938 Bytes = 7.4 MiB
+ Architecture: ARM
+ OS: Linux
+ Load Address: 0x80008000
+ Entry Point: 0x80008000
+ Hash algo: sha1
+ Hash value: c94364646427e10f423837e559898ef02c97b988
+ Verifying Hash Integrity ... sha1+ OK
+## Loading fdt from FIT Image at 82000000 ...
+ Using 'conf@1' configuration
+ Trying 'fdt@1' fdt subimage
+ Description: beaglebone-black
+ Created: 2014-06-01 19:32:54 UTC
+ Type: Flat Device Tree
+ Compression: uncompressed
+ Data Start: 0x8276e2ec
+ Data Size: 31547 Bytes = 30.8 KiB
+ Architecture: ARM
+ Hash algo: sha1
+ Hash value: cb09202f889d824f23b8e4404b781be5ad38a68d
+ Verifying Hash Integrity ... sha1+ OK
+ Booting using the fdt blob at 0x8276e2ec
+ Uncompressing Kernel Image ... OK
+ Loading Device Tree to 8fff5000, end 8ffffb3a ... OK
+
+Starting kernel ...
+
+[ 0.582377] omap_init_mbox: hwmod doesn't have valid attrs
+[ 2.589651] musb-hdrc musb-hdrc.0.auto: Failed to request rx1.
+[ 2.595830] musb-hdrc musb-hdrc.0.auto: musb_init_controller failed with status -517
+[ 2.606470] musb-hdrc musb-hdrc.1.auto: Failed to request rx1.
+[ 2.612723] musb-hdrc musb-hdrc.1.auto: musb_init_controller failed with status -517
+[ 2.940808] drivers/rtc/hctosys.c: unable to open rtc device (rtc0)
+[ 7.248889] libphy: PHY 4a101000.mdio:01 not found
+[ 7.253995] net eth0: phy 4a101000.mdio:01 not found on slave 1
+systemd-fsck[83]: Angstrom: clean, 50607/218160 files, 306348/872448 blocks
+
+.---O---.
+| | .-. o o
+| | |-----.-----.-----.| | .----..-----.-----.
+| | | __ | ---'| '--.| .-'| | |
+| | | | | |--- || --'| | | ' | | | |
+'---'---'--'--'--. |-----''----''--' '-----'-'-'-'
+ -' |
+ '---'
+
+The Angstrom Distribution beaglebone ttyO0
+
+Angstrom v2012.12 - Kernel 3.14.1+
+
+beaglebone login:
+
+At this point your kernel has been verified and you can be sure that it is one
+that you signed. As an exercise, try changing image.fit as in step 5 and see
+what happens.
+
+
+Further Improvements
+--------------------
+
+Several of the steps here can be easily automated. In particular it would be
+capital if signing and packaging a kernel were easy, perhaps a simple make
+target in the kernel.
+
+Some mention of how to use multiple .dtb files in a FIT might be useful.
+
+U-Boot's verified boot mechanism has not had a robust and independent security
+review. Such a review should look at the implementation and its resistance to
+attacks.
+
+Perhaps the verified boot feature could could be integrated into the Amstrom
+distribution.
+
+
+Simon Glass
+sjg@chromium.org
+2-June-14
(mkimage) is invoked directly. dtc is called from within mkimage and operates
behind the scenes, but needs to be present in the $PATH nevertheless. It is
important that the dtc used has support for binary includes -- refer to
-www.jdl.com for its latest version. mkimage (together with dtc) takes as input
+
+ git://git.kernel.org/pub/scm/utils/dtc/dtc.git
+
+for its latest version. mkimage (together with dtc) takes as input
an image source file, which describes the contents of the image and defines
its various properties used during booting. By convention, image source file
has the ".its" extension, also, the details of its format are given in
CONFIG_FIT_SIGNATURE - enable signing and verfication in FITs
CONFIG_RSA - enable RSA algorithm for signing
+WARNING: When relying on signed FIT images with required signature check
+the legacy image format is default disabled by not defining
+CONFIG_IMAGE_FORMAT_LEGACY
Testing
-------
Sign images
Test Verified Boot Run: signed config: OK
check signed config on the host
+Signature check OK
OK
Test Verified Boot Run: signed config: OK
Test Verified Boot Run: signed config with bad hash: OK
Sign images
Test Verified Boot Run: signed config: OK
check signed config on the host
+Signature check OK
OK
Test Verified Boot Run: signed config: OK
Test Verified Boot Run: signed config with bad hash: OK
Test passed
+
Future Work
-----------
- Roll-back protection using a TPM is done using the tpm command. This can
#include <asm/io.h>
#include <linux/bitops.h>
#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
#include "dwc_ahsata.h"
struct sata_port_regs {
u32 linkmap;
struct ahci_probe_ent *probe_ent = NULL;
+#if defined(CONFIG_MX6)
+ if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D))
+ return 1;
+#endif
if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
printf("The sata index %d is out of ranges\n\r", dev);
return -1;
* @dev: The device that is to be stripped of its children
* @return 0 on success, -ve on error
*/
-static int device_chld_unbind(struct device *dev)
+static int device_chld_unbind(struct udevice *dev)
{
- struct device *pos, *n;
+ struct udevice *pos, *n;
int ret, saved_ret = 0;
assert(dev);
* @dev: The device whose children are to be removed
* @return 0 on success, -ve on error
*/
-static int device_chld_remove(struct device *dev)
+static int device_chld_remove(struct udevice *dev)
{
- struct device *pos, *n;
+ struct udevice *pos, *n;
int ret;
assert(dev);
return 0;
}
-int device_bind(struct device *parent, struct driver *drv, const char *name,
- void *platdata, int of_offset, struct device **devp)
+int device_bind(struct udevice *parent, struct driver *drv, const char *name,
+ void *platdata, int of_offset, struct udevice **devp)
{
- struct device *dev;
+ struct udevice *dev;
struct uclass *uc;
int ret = 0;
if (ret)
return ret;
- dev = calloc(1, sizeof(struct device));
+ dev = calloc(1, sizeof(struct udevice));
if (!dev)
return -ENOMEM;
return ret;
}
-int device_bind_by_name(struct device *parent, const struct driver_info *info,
- struct device **devp)
+int device_bind_by_name(struct udevice *parent, const struct driver_info *info,
+ struct udevice **devp)
{
struct driver *drv;
-1, devp);
}
-int device_unbind(struct device *dev)
+int device_unbind(struct udevice *dev)
{
struct driver *drv;
int ret;
* device_free() - Free memory buffers allocated by a device
* @dev: Device that is to be started
*/
-static void device_free(struct device *dev)
+static void device_free(struct udevice *dev)
{
int size;
}
}
-int device_probe(struct device *dev)
+int device_probe(struct udevice *dev)
{
struct driver *drv;
int size = 0;
return ret;
}
-int device_remove(struct device *dev)
+int device_remove(struct udevice *dev)
{
struct driver *drv;
int ret;
return ret;
}
-void *dev_get_platdata(struct device *dev)
+void *dev_get_platdata(struct udevice *dev)
{
if (!dev) {
dm_warn("%s: null device", __func__);
return dev->platdata;
}
-void *dev_get_priv(struct device *dev)
+void *dev_get_priv(struct udevice *dev)
{
if (!dev) {
dm_warn("%s: null device", __func__);
#include <dm/platdata.h>
#include <dm/uclass.h>
#include <dm/util.h>
+#include <fdtdec.h>
#include <linux/compiler.h>
struct driver *lists_driver_lookup_name(const char *name)
return NULL;
}
-int lists_bind_drivers(struct device *parent)
+int lists_bind_drivers(struct udevice *parent)
{
struct driver_info *info =
ll_entry_start(struct driver_info, driver_info);
const int n_ents = ll_entry_count(struct driver_info, driver_info);
struct driver_info *entry;
- struct device *dev;
+ struct udevice *dev;
int result = 0;
int ret;
* tree error
*/
static int driver_check_compatible(const void *blob, int offset,
- const struct device_id *of_match)
+ const struct udevice_id *of_match)
{
int ret;
return -ENOENT;
}
-int lists_bind_fdt(struct device *parent, const void *blob, int offset)
+int lists_bind_fdt(struct udevice *parent, const void *blob, int offset)
{
struct driver *driver = ll_entry_start(struct driver, driver);
const int n_ents = ll_entry_count(struct driver, driver);
struct driver *entry;
- struct device *dev;
+ struct udevice *dev;
const char *name;
int result = 0;
int ret;
#include <common.h>
#include <errno.h>
#include <malloc.h>
+#include <libfdt.h>
#include <dm/device.h>
#include <dm/device-internal.h>
#include <dm/lists.h>
.name = "root_driver",
};
-struct device *dm_root(void)
+struct udevice *dm_root(void)
{
if (!gd->dm_root) {
dm_warn("Virtual root driver does not exist!\n");
dm_warn("Virtual root driver already exists!\n");
return -EINVAL;
}
- INIT_LIST_HEAD(&gd->uclass_root);
+ INIT_LIST_HEAD(&DM_UCLASS_ROOT_NON_CONST);
- ret = device_bind_by_name(NULL, &root_info, &gd->dm_root);
+ ret = device_bind_by_name(NULL, &root_info, &DM_ROOT_NON_CONST);
if (ret)
return ret;
{
int ret;
- ret = lists_bind_drivers(gd->dm_root);
+ ret = lists_bind_drivers(DM_ROOT_NON_CONST);
if (ret == -ENOENT) {
dm_warn("Some drivers were not found\n");
ret = 0;
uc->uc_drv = uc_drv;
INIT_LIST_HEAD(&uc->sibling_node);
INIT_LIST_HEAD(&uc->dev_head);
- list_add(&uc->sibling_node, &gd->uclass_root);
+ list_add(&uc->sibling_node, &DM_UCLASS_ROOT_NON_CONST);
if (uc_drv->init) {
ret = uc_drv->init(uc);
int uclass_destroy(struct uclass *uc)
{
struct uclass_driver *uc_drv;
- struct device *dev, *tmp;
+ struct udevice *dev, *tmp;
int ret;
list_for_each_entry_safe(dev, tmp, &uc->dev_head, uclass_node) {
return 0;
}
-int uclass_find_device(enum uclass_id id, int index, struct device **devp)
+int uclass_find_device(enum uclass_id id, int index, struct udevice **devp)
{
struct uclass *uc;
- struct device *dev;
+ struct udevice *dev;
int ret;
*devp = NULL;
return -ENODEV;
}
-int uclass_get_device(enum uclass_id id, int index, struct device **devp)
+int uclass_get_device(enum uclass_id id, int index, struct udevice **devp)
{
- struct device *dev;
+ struct udevice *dev;
int ret;
*devp = NULL;
return 0;
}
-int uclass_first_device(enum uclass_id id, struct device **devp)
+int uclass_first_device(enum uclass_id id, struct udevice **devp)
{
struct uclass *uc;
- struct device *dev;
+ struct udevice *dev;
int ret;
*devp = NULL;
if (list_empty(&uc->dev_head))
return 0;
- dev = list_first_entry(&uc->dev_head, struct device, uclass_node);
+ dev = list_first_entry(&uc->dev_head, struct udevice, uclass_node);
ret = device_probe(dev);
if (ret)
return ret;
return 0;
}
-int uclass_next_device(struct device **devp)
+int uclass_next_device(struct udevice **devp)
{
- struct device *dev = *devp;
+ struct udevice *dev = *devp;
int ret;
*devp = NULL;
if (list_is_last(&dev->uclass_node, &dev->uclass->dev_head))
return 0;
- dev = list_entry(dev->uclass_node.next, struct device, uclass_node);
+ dev = list_entry(dev->uclass_node.next, struct udevice,
+ uclass_node);
ret = device_probe(dev);
if (ret)
return ret;
return 0;
}
-int uclass_bind_device(struct device *dev)
+int uclass_bind_device(struct udevice *dev)
{
struct uclass *uc;
int ret;
return 0;
}
-int uclass_unbind_device(struct device *dev)
+int uclass_unbind_device(struct udevice *dev)
{
struct uclass *uc;
int ret;
return 0;
}
-int uclass_post_probe_device(struct device *dev)
+int uclass_post_probe_device(struct udevice *dev)
{
struct uclass_driver *uc_drv = dev->uclass->uc_drv;
return 0;
}
-int uclass_pre_remove_device(struct device *dev)
+int uclass_pre_remove_device(struct udevice *dev)
{
struct uclass_driver *uc_drv;
struct uclass *uc;
#include "ace_sha.h"
#ifdef CONFIG_SHA_HW_ACCEL
-#include <sha256.h>
-#include <sha1.h>
+#include <u-boot/sha256.h>
+#include <u-boot/sha1.h>
#include <asm/errno.h>
/* SHA1 value for the message of zero length */
ddr->debug[2] = 0x00000400;
ddr->debug[4] = 0xff800000;
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A004508
+ if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
+ ddr->debug[2] |= 0x00000200; /* set bit 22 */
+#endif
+
return check_fsl_memctl_config_regs(ddr);
}
*/
#include <common.h>
+#include <cli.h>
#include <linux/ctype.h>
#include <asm/types.h>
#include <asm/io.h>
printf("%-3d-%3d: ", 128, 255);
for (i = 128; i <= 255; i++)
- printf("%02x", spd->mod_section.uc[i - 60]);
+ printf("%02x", spd->mod_section.uc[i - 128]);
break;
}
} else {
/*
* No need to worry for buffer overflow here in
- * this function; readline() maxes out at CFG_CBSIZE
+ * this function; cli_readline() maxes out at
+ * CFG_CBSIZE
*/
- readline_into_buffer(prompt, buffer, 0);
+ cli_readline_into_buffer(prompt, buffer, 0);
}
- argc = parse_line(buffer, argv);
+ argc = cli_simple_parse_line(buffer, argv);
if (argc == 0)
continue;
};
/* Crazy little function to draw shapes on the console */
-static int shape_hello(struct device *dev, int ch)
+static int shape_hello(struct udevice *dev, int ch)
{
const struct dm_demo_pdata *pdata = dev_get_platdata(dev);
struct shape_data *data = dev_get_priv(dev);
return 0;
}
-static int shape_status(struct device *dev, int *status)
+static int shape_status(struct udevice *dev, int *status)
{
struct shape_data *data = dev_get_priv(dev);
.status = shape_status,
};
-static int shape_ofdata_to_platdata(struct device *dev)
+static int shape_ofdata_to_platdata(struct udevice *dev)
{
struct dm_demo_pdata *pdata = dev_get_platdata(dev);
int ret;
return 0;
}
-static const struct device_id demo_shape_id[] = {
+static const struct udevice_id demo_shape_id[] = {
{ "demo-shape", 0 },
{ },
};
#include <dm-demo.h>
#include <asm/io.h>
-static int simple_hello(struct device *dev, int ch)
+static int simple_hello(struct udevice *dev, int ch)
{
const struct dm_demo_pdata *pdata = dev_get_platdata(dev);
.hello = simple_hello,
};
-static int demo_shape_ofdata_to_platdata(struct device *dev)
+static int demo_shape_ofdata_to_platdata(struct udevice *dev)
{
/* Parse the data that is common with all demo devices */
return demo_parse_dt(dev);
}
-static const struct device_id demo_shape_id[] = {
+static const struct udevice_id demo_shape_id[] = {
{ "demo-simple", 0 },
{ },
};
.id = UCLASS_DEMO,
};
-int demo_hello(struct device *dev, int ch)
+int demo_hello(struct udevice *dev, int ch)
{
const struct demo_ops *ops = device_get_ops(dev);
return ops->hello(dev, ch);
}
-int demo_status(struct device *dev, int *status)
+int demo_status(struct udevice *dev, int *status)
{
const struct demo_ops *ops = device_get_ops(dev);
return ops->status(dev, status);
}
-int demo_parse_dt(struct device *dev)
+int demo_parse_dt(struct udevice *dev)
{
struct dm_demo_pdata *pdata = dev_get_platdata(dev);
int dn = dev->of_offset;
#include <mmc.h>
#include <fat.h>
#include <dfu.h>
+#include <hash.h>
#include <linux/list.h>
#include <linux/compiler.h>
static LIST_HEAD(dfu_list);
static int dfu_alt_num;
static int alt_num_cnt;
+static struct hash_algo *dfu_hash_algo;
bool dfu_reset(void)
{
return dfu_buf;
}
+static char *dfu_get_hash_algo(void)
+{
+ char *s;
+
+ s = getenv("dfu_hash_algo");
+ if (!s)
+ return NULL;
+
+ if (!strcmp(s, "crc32")) {
+ debug("%s: DFU hash method: %s\n", __func__, s);
+ return s;
+ }
+
+ error("DFU hash method: %s not supported!\n", s);
+ return NULL;
+}
+
static int dfu_write_buffer_drain(struct dfu_entity *dfu)
{
long w_size;
if (w_size == 0)
return 0;
- /* update CRC32 */
- dfu->crc = crc32(dfu->crc, dfu->i_buf_start, w_size);
+ if (dfu_hash_algo)
+ dfu_hash_algo->hash_update(dfu_hash_algo, &dfu->crc,
+ dfu->i_buf_start, w_size, 0);
ret = dfu->write_medium(dfu, dfu->offset, dfu->i_buf_start, &w_size);
if (ret)
if (dfu->flush_medium)
ret = dfu->flush_medium(dfu);
- printf("\nDFU complete CRC32: 0x%08x\n", dfu->crc);
+ if (dfu_hash_algo)
+ printf("\nDFU complete %s: 0x%08x\n", dfu_hash_algo->name,
+ dfu->crc);
/* clear everything */
dfu_free_buf();
/* consume */
if (chunk > 0) {
memcpy(buf, dfu->i_buf, chunk);
- dfu->crc = crc32(dfu->crc, buf, chunk);
+ if (dfu_hash_algo)
+ dfu_hash_algo->hash_update(dfu_hash_algo,
+ &dfu->crc, buf,
+ chunk, 0);
+
dfu->i_buf += chunk;
dfu->b_left -= chunk;
dfu->r_left -= chunk;
}
if (ret < size) {
- debug("%s: %s CRC32: 0x%x\n", __func__, dfu->name, dfu->crc);
+ if (dfu_hash_algo)
+ debug("%s: %s %s: 0x%x\n", __func__, dfu->name,
+ dfu_hash_algo->name, dfu->crc);
puts("\nUPLOAD ... done\nCtrl+C to exit ...\n");
dfu_free_buf();
dfu_alt_num = dfu_find_alt_num(env);
debug("%s: dfu_alt_num=%d\n", __func__, dfu_alt_num);
+ dfu_hash_algo = NULL;
+ s = dfu_get_hash_algo();
+ if (s) {
+ ret = hash_lookup_algo(s, &dfu_hash_algo);
+ if (ret)
+ error("Hash algorithm %s not supported\n", s);
+ }
+
dfu = calloc(sizeof(*dfu), dfu_alt_num);
if (!dfu)
return -1;
printf ("Unsupported interface type, %d\n", desc->iface);
}
- printf ("Device Size: \t%d bytes\n"
- "Cookie: \t0x%x (%d)\n",
- desc->size, desc->cookie, desc->cookie);
+ printf("Device Size: \t%zd bytes\n"
+ "Cookie: \t0x%x (%d)\n",
+ desc->size, desc->cookie, desc->cookie);
if (desc->iface_fns) {
printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
printf ("Unsupported interface type, %d\n", desc->iface);
}
- printf ("Device Size: \t%d bytes\n"
- "Cookie: \t0x%x (%d)\n",
- desc->size, desc->cookie, desc->cookie);
+ printf("Device Size: \t%zd bytes\n"
+ "Cookie: \t0x%x (%d)\n",
+ desc->size, desc->cookie, desc->cookie);
if (desc->name)
printf("Device name: \t%s\n", desc->name);
* or GPIO blocks registered with the GPIO controller. Returns
* entry on success, NULL on error.
*/
-static int gpio_to_device(unsigned int gpio, struct device **devp,
+static int gpio_to_device(unsigned int gpio, struct udevice **devp,
unsigned int *offset)
{
struct gpio_dev_priv *uc_priv;
- struct device *dev;
+ struct udevice *dev;
int ret;
for (ret = uclass_first_device(UCLASS_GPIO, &dev);
return ret ? ret : -EINVAL;
}
-int gpio_lookup_name(const char *name, struct device **devp,
+int gpio_lookup_name(const char *name, struct udevice **devp,
unsigned int *offsetp, unsigned int *gpiop)
{
struct gpio_dev_priv *uc_priv;
- struct device *dev;
+ struct udevice *dev;
int ret;
if (devp)
uc_priv = dev->uclass_priv;
len = uc_priv->bank_name ? strlen(uc_priv->bank_name) : 0;
- if (!strncmp(name, uc_priv->bank_name, len)) {
+ if (!strncasecmp(name, uc_priv->bank_name, len)) {
if (strict_strtoul(name + len, 10, &offset))
continue;
if (devp)
int gpio_request(unsigned gpio, const char *label)
{
unsigned int offset;
- struct device *dev;
+ struct udevice *dev;
int ret;
ret = gpio_to_device(gpio, &dev, &offset);
int gpio_free(unsigned gpio)
{
unsigned int offset;
- struct device *dev;
+ struct udevice *dev;
int ret;
ret = gpio_to_device(gpio, &dev, &offset);
int gpio_direction_input(unsigned gpio)
{
unsigned int offset;
- struct device *dev;
+ struct udevice *dev;
int ret;
ret = gpio_to_device(gpio, &dev, &offset);
int gpio_direction_output(unsigned gpio, int value)
{
unsigned int offset;
- struct device *dev;
+ struct udevice *dev;
int ret;
ret = gpio_to_device(gpio, &dev, &offset);
int gpio_get_value(unsigned gpio)
{
unsigned int offset;
- struct device *dev;
+ struct udevice *dev;
int ret;
ret = gpio_to_device(gpio, &dev, &offset);
int gpio_set_value(unsigned gpio, int value)
{
unsigned int offset;
- struct device *dev;
+ struct udevice *dev;
int ret;
ret = gpio_to_device(gpio, &dev, &offset);
return gpio_get_ops(dev)->set_value(dev, offset, value);
}
-const char *gpio_get_bank_info(struct device *dev, int *bit_count)
+const char *gpio_get_bank_info(struct udevice *dev, int *bit_count)
{
struct gpio_dev_priv *priv;
static int gpio_renumber(void)
{
struct gpio_dev_priv *uc_priv;
- struct device *dev;
+ struct udevice *dev;
struct uclass *uc;
unsigned base;
int ret;
return 0;
}
-static int gpio_post_probe(struct device *dev)
+static int gpio_post_probe(struct udevice *dev)
{
return gpio_renumber();
}
-static int gpio_pre_remove(struct device *dev)
+static int gpio_pre_remove(struct udevice *dev)
{
return gpio_renumber();
}
};
/* Access routines for GPIO state */
-static u8 *get_gpio_flags(struct device *dev, unsigned offset)
+static u8 *get_gpio_flags(struct udevice *dev, unsigned offset)
{
struct gpio_dev_priv *uc_priv = dev->uclass_priv;
struct gpio_state *state = dev_get_priv(dev);
return &state[offset].flags;
}
-static int get_gpio_flag(struct device *dev, unsigned offset, int flag)
+static int get_gpio_flag(struct udevice *dev, unsigned offset, int flag)
{
return (*get_gpio_flags(dev, offset) & flag) != 0;
}
-static int set_gpio_flag(struct device *dev, unsigned offset, int flag,
+static int set_gpio_flag(struct udevice *dev, unsigned offset, int flag,
int value)
{
u8 *gpio = get_gpio_flags(dev, offset);
return 0;
}
-static int check_reserved(struct device *dev, unsigned offset,
+static int check_reserved(struct udevice *dev, unsigned offset,
const char *func)
{
if (!get_gpio_flag(dev, offset, GPIOF_RESERVED)) {
* Back-channel sandbox-internal-only access to GPIO state
*/
-int sandbox_gpio_get_value(struct device *dev, unsigned offset)
+int sandbox_gpio_get_value(struct udevice *dev, unsigned offset)
{
if (get_gpio_flag(dev, offset, GPIOF_OUTPUT))
debug("sandbox_gpio: get_value on output gpio %u\n", offset);
return get_gpio_flag(dev, offset, GPIOF_HIGH);
}
-int sandbox_gpio_set_value(struct device *dev, unsigned offset, int value)
+int sandbox_gpio_set_value(struct udevice *dev, unsigned offset, int value)
{
return set_gpio_flag(dev, offset, GPIOF_HIGH, value);
}
-int sandbox_gpio_get_direction(struct device *dev, unsigned offset)
+int sandbox_gpio_get_direction(struct udevice *dev, unsigned offset)
{
return get_gpio_flag(dev, offset, GPIOF_OUTPUT);
}
-int sandbox_gpio_set_direction(struct device *dev, unsigned offset, int output)
+int sandbox_gpio_set_direction(struct udevice *dev, unsigned offset, int output)
{
return set_gpio_flag(dev, offset, GPIOF_OUTPUT, output);
}
*/
/* set GPIO port 'offset' as an input */
-static int sb_gpio_direction_input(struct device *dev, unsigned offset)
+static int sb_gpio_direction_input(struct udevice *dev, unsigned offset)
{
debug("%s: offset:%u\n", __func__, offset);
}
/* set GPIO port 'offset' as an output, with polarity 'value' */
-static int sb_gpio_direction_output(struct device *dev, unsigned offset,
+static int sb_gpio_direction_output(struct udevice *dev, unsigned offset,
int value)
{
debug("%s: offset:%u, value = %d\n", __func__, offset, value);
}
/* read GPIO IN value of port 'offset' */
-static int sb_gpio_get_value(struct device *dev, unsigned offset)
+static int sb_gpio_get_value(struct udevice *dev, unsigned offset)
{
debug("%s: offset:%u\n", __func__, offset);
}
/* write GPIO OUT value to port 'offset' */
-static int sb_gpio_set_value(struct device *dev, unsigned offset, int value)
+static int sb_gpio_set_value(struct udevice *dev, unsigned offset, int value)
{
debug("%s: offset:%u, value = %d\n", __func__, offset, value);
return sandbox_gpio_set_value(dev, offset, value);
}
-static int sb_gpio_request(struct device *dev, unsigned offset,
+static int sb_gpio_request(struct udevice *dev, unsigned offset,
const char *label)
{
struct gpio_dev_priv *uc_priv = dev->uclass_priv;
return set_gpio_flag(dev, offset, GPIOF_RESERVED, 1);
}
-static int sb_gpio_free(struct device *dev, unsigned offset)
+static int sb_gpio_free(struct udevice *dev, unsigned offset)
{
struct gpio_state *state = dev_get_priv(dev);
return set_gpio_flag(dev, offset, GPIOF_RESERVED, 0);
}
-static int sb_gpio_get_state(struct device *dev, unsigned int offset,
+static int sb_gpio_get_state(struct udevice *dev, unsigned int offset,
char *buf, int bufsize)
{
struct gpio_dev_priv *uc_priv = dev->uclass_priv;
.get_state = sb_gpio_get_state,
};
-static int sandbox_gpio_ofdata_to_platdata(struct device *dev)
+static int sandbox_gpio_ofdata_to_platdata(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev->uclass_priv;
return 0;
}
-static int gpio_sandbox_probe(struct device *dev)
+static int gpio_sandbox_probe(struct udevice *dev)
{
struct gpio_dev_priv *uc_priv = dev->uclass_priv;
return 0;
}
-static const struct device_id sandbox_gpio_ids[] = {
+static const struct udevice_id sandbox_gpio_ids[] = {
{ .compatible = "sandbox,gpio" },
{ }
};
static int kona_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
int alen, uchar *buffer, int len)
{
- struct i2c_msg msg[0];
+ struct i2c_msg msg[1];
unsigned char msgbuf0[64];
unsigned int i;
struct bcm_kona_i2c_dev *dev = kona_get_dev(adap);
#include <hash.h>
#include <malloc.h>
#include <os.h>
-#include <sha256.h>
+#include <u-boot/sha256.h>
#include <spi.h>
#include <asm/state.h>
#include <asm/sdl.h>
__func__, dev_index);
ret = -EINVAL;
}
- if (ret)
+ if (ret) {
+ free(host);
return ret;
+ }
host->name = "kona-sdhci";
host->ioaddr = reg_base;
host->quirks = quirks;
host->host_caps = MMC_MODE_HC;
- if (init_kona_mmc_core(host))
+ if (init_kona_mmc_core(host)) {
+ free(host);
return -EINVAL;
+ }
if (quirks & SDHCI_QUIRK_REG32_RW)
host->version = sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
#include <config.h>
#include <common.h>
#include <command.h>
+#include <errno.h>
#include <mmc.h>
#include <part.h>
#include <malloc.h>
int ret;
if (!mmc)
- return -1;
+ return -ENODEV;
if (mmc->part_num == hwpart)
return 0;
if (mmc->part_config == MMCPART_NOAVAILABLE) {
printf("Card doesn't support part_switch\n");
- return -1;
+ return -EMEDIUMTYPE;
}
ret = mmc_switch_part(dev_num, hwpart);
if (ret)
- return -1;
+ return ret;
mmc->part_num = hwpart;
#include <config.h>
#include <common.h>
#include <mmc.h>
-#include <sha256.h>
+#include <u-boot/sha256.h>
#include "mmc_private.h"
/* Request codes */
obj-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_spl.o
obj-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_spl.o
obj-$(CONFIG_NAND_MXC) += mxc_nand_spl.o
+obj-$(CONFIG_NAND_MXS) += mxs_nand_spl.o mxs_nand.o
endif # drivers
--- /dev/null
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include <common.h>
+#include <nand.h>
+#include <malloc.h>
+
+static nand_info_t mtd;
+static struct nand_chip nand_chip;
+
+static void mxs_nand_command(struct mtd_info *mtd, unsigned int command,
+ int column, int page_addr)
+{
+ register struct nand_chip *chip = mtd->priv;
+ u32 timeo, time_start;
+
+ /* write out the command to the device */
+ chip->cmd_ctrl(mtd, command, NAND_CLE);
+
+ /* Serially input address */
+ if (column != -1) {
+ chip->cmd_ctrl(mtd, column, NAND_ALE);
+ chip->cmd_ctrl(mtd, column >> 8, NAND_ALE);
+ }
+ if (page_addr != -1) {
+ chip->cmd_ctrl(mtd, page_addr, NAND_ALE);
+ chip->cmd_ctrl(mtd, page_addr >> 8, NAND_ALE);
+ /* One more address cycle for devices > 128MiB */
+ if (chip->chipsize > (128 << 20))
+ chip->cmd_ctrl(mtd, page_addr >> 16, NAND_ALE);
+ }
+ chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0);
+
+ if (command == NAND_CMD_READ0) {
+ chip->cmd_ctrl(mtd, NAND_CMD_READSTART, NAND_CLE);
+ chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0);
+ }
+
+ /* wait for nand ready */
+ ndelay(100);
+ timeo = (CONFIG_SYS_HZ * 20) / 1000;
+ time_start = get_timer(0);
+ while (get_timer(time_start) < timeo) {
+ if (chip->dev_ready(mtd))
+ break;
+ }
+}
+
+static int mxs_flash_ident(struct mtd_info *mtd)
+{
+ register struct nand_chip *chip = mtd->priv;
+ int i;
+ u8 mfg_id, dev_id;
+ u8 id_data[8];
+ struct nand_onfi_params *p = &chip->onfi_params;
+
+ /* Reset the chip */
+ chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+
+ /* Send the command for reading device ID */
+ chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+
+ /* Read manufacturer and device IDs */
+ mfg_id = chip->read_byte(mtd);
+ dev_id = chip->read_byte(mtd);
+
+ /* Try again to make sure */
+ chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+ for (i = 0; i < 8; i++)
+ id_data[i] = chip->read_byte(mtd);
+ if (id_data[0] != mfg_id || id_data[1] != dev_id) {
+ printf("second ID read did not match");
+ return -1;
+ }
+ debug("0x%02x:0x%02x ", mfg_id, dev_id);
+
+ /* read ONFI */
+ chip->onfi_version = 0;
+ chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
+ if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
+ chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I') {
+ return -2;
+ }
+
+ /* we have ONFI, probe it */
+ chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
+ chip->read_buf(mtd, (uint8_t *)p, sizeof(*p));
+ mtd->name = p->model;
+ mtd->writesize = le32_to_cpu(p->byte_per_page);
+ mtd->erasesize = le32_to_cpu(p->pages_per_block) * mtd->writesize;
+ mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
+ chip->chipsize = le32_to_cpu(p->blocks_per_lun);
+ chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
+ /* Calculate the address shift from the page size */
+ chip->page_shift = ffs(mtd->writesize) - 1;
+ chip->phys_erase_shift = ffs(mtd->erasesize) - 1;
+ /* Convert chipsize to number of pages per chip -1 */
+ chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
+ chip->badblockbits = 8;
+
+ debug("erasesize=%d (>>%d)\n", mtd->erasesize, chip->phys_erase_shift);
+ debug("writesize=%d (>>%d)\n", mtd->writesize, chip->page_shift);
+ debug("oobsize=%d\n", mtd->oobsize);
+ debug("chipsize=%lld\n", chip->chipsize);
+
+ return 0;
+}
+
+static int mxs_read_page_ecc(struct mtd_info *mtd, void *buf, unsigned int page)
+{
+ register struct nand_chip *chip = mtd->priv;
+ int ret;
+
+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0x0, page);
+ ret = nand_chip.ecc.read_page(mtd, chip, buf, 1, page);
+ if (ret < 0) {
+ printf("read_page failed %d\n", ret);
+ return -1;
+ }
+ return 0;
+}
+
+static int is_badblock(struct mtd_info *mtd, loff_t offs, int allowbbt)
+{
+ register struct nand_chip *chip = mtd->priv;
+ unsigned int block = offs >> chip->phys_erase_shift;
+ unsigned int page = offs >> chip->page_shift;
+
+ debug("%s offs=0x%08x block:%d page:%d\n", __func__, (int)offs, block,
+ page);
+ chip->cmdfunc(mtd, NAND_CMD_READ0, mtd->writesize, page);
+ memset(chip->oob_poi, 0, mtd->oobsize);
+ chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+
+ return chip->oob_poi[0] != 0xff;
+}
+
+/* setup mtd and nand structs and init mxs_nand driver */
+static int mxs_nand_init(void)
+{
+ /* return if already initalized */
+ if (nand_chip.numchips)
+ return 0;
+
+ /* init mxs nand driver */
+ board_nand_init(&nand_chip);
+ mtd.priv = &nand_chip;
+ /* set mtd functions */
+ nand_chip.cmdfunc = mxs_nand_command;
+ nand_chip.numchips = 1;
+
+ /* identify flash device */
+ puts("NAND : ");
+ if (mxs_flash_ident(&mtd)) {
+ printf("Failed to identify\n");
+ return -1;
+ }
+
+ /* allocate and initialize buffers */
+ nand_chip.buffers = memalign(ARCH_DMA_MINALIGN,
+ sizeof(*nand_chip.buffers));
+ nand_chip.oob_poi = nand_chip.buffers->databuf + mtd.writesize;
+ /* setup flash layout (does not scan as we override that) */
+ mtd.size = nand_chip.chipsize;
+ nand_chip.scan_bbt(&mtd);
+
+ printf("%llu MiB\n", (mtd.size / (1024 * 1024)));
+ return 0;
+}
+
+int nand_spl_load_image(uint32_t offs, unsigned int size, void *buf)
+{
+ struct nand_chip *chip;
+ unsigned int page;
+ unsigned int nand_page_per_block;
+ unsigned int sz = 0;
+
+ if (mxs_nand_init())
+ return -ENODEV;
+ chip = mtd.priv;
+ page = offs >> chip->page_shift;
+ nand_page_per_block = mtd.erasesize / mtd.writesize;
+
+ debug("%s offset:0x%08x len:%d page:%d\n", __func__, offs, size, page);
+
+ size = roundup(size, mtd.writesize);
+ while (sz < size) {
+ if (mxs_read_page_ecc(&mtd, buf, page) < 0)
+ return -1;
+ sz += mtd.writesize;
+ offs += mtd.writesize;
+ page++;
+ buf += mtd.writesize;
+
+ /*
+ * Check if we have crossed a block boundary, and if so
+ * check for bad block.
+ */
+ if (!(page % nand_page_per_block)) {
+ /*
+ * Yes, new block. See if this block is good. If not,
+ * loop until we find a good block.
+ */
+ while (is_badblock(&mtd, offs, 1)) {
+ page = page + nand_page_per_block;
+ /* Check i we've reached the end of flash. */
+ if (page >= mtd.size >> chip->page_shift)
+ return -ENOMEM;
+ }
+ }
+ }
+
+ return 0;
+}
+
+int nand_default_bbt(struct mtd_info *mtd)
+{
+ return 0;
+}
+
+void nand_init(void)
+{
+}
+
+void nand_deselect(void)
+{
+}
+
{"S25FL256S_64K", 0x010219, 0x4d01, 64 * 1024, 512, RD_FULL, WR_QPP},
{"S25FL512S_256K", 0x010220, 0x4d00, 256 * 1024, 256, RD_FULL, WR_QPP},
{"S25FL512S_64K", 0x010220, 0x4d01, 64 * 1024, 1024, RD_FULL, WR_QPP},
+ {"S25FL512S_512K", 0x010220, 0x4f00, 256 * 1024, 256, RD_FULL, WR_QPP},
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO /* STMICRO */
{"M25P10", 0x202011, 0x0, 32 * 1024, 4, 0, 0},
/* Go for default supported write cmd */
flash->write_cmd = CMD_PAGE_PROGRAM;
- /* Set the quad enable bit - only for quad commands */
- if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
- (flash->read_cmd == CMD_READ_QUAD_IO_FAST) ||
- (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
- if (spi_flash_set_qeb(flash, idcode[0])) {
- debug("SF: Fail to set QEB for %02x\n", idcode[0]);
- return NULL;
- }
- }
-
/* Read dummy_byte: dummy byte is determined based on the
* dummy cycles of a particular command.
* Fast commands - dummy_byte = dummy_cycles/8
if (!flash)
goto err_read_id;
+ /* Set the quad enable bit - only for quad commands */
+ if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
+ (flash->read_cmd == CMD_READ_QUAD_IO_FAST) ||
+ (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
+ if (spi_flash_set_qeb(flash, idcode[0])) {
+ debug("SF: Fail to set QEB for %02x\n", idcode[0]);
+ return NULL;
+ }
+ }
+
#ifdef CONFIG_OF_CONTROL
if (spi_flash_decode_fdt(gd->fdt_blob, flash)) {
debug("SF: FDT decode error\n");
#include "macb.h"
-#define CONFIG_SYS_MACB_RX_BUFFER_SIZE 4096
-#define CONFIG_SYS_MACB_RX_RING_SIZE (CONFIG_SYS_MACB_RX_BUFFER_SIZE / 128)
-#define CONFIG_SYS_MACB_TX_RING_SIZE 16
-#define CONFIG_SYS_MACB_TX_TIMEOUT 1000
-#define CONFIG_SYS_MACB_AUTONEG_TIMEOUT 5000000
+#define MACB_RX_BUFFER_SIZE 4096
+#define MACB_RX_RING_SIZE (MACB_RX_BUFFER_SIZE / 128)
+#define MACB_TX_RING_SIZE 16
+#define MACB_TX_TIMEOUT 1000
+#define MACB_AUTONEG_TIMEOUT 5000000
struct macb_dma_desc {
u32 addr;
u32 ctrl;
};
+#define DMA_DESC_BYTES(n) (n * sizeof(struct macb_dma_desc))
+#define MACB_TX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_TX_RING_SIZE))
+#define MACB_RX_DMA_DESC_SIZE (DMA_DESC_BYTES(MACB_RX_RING_SIZE))
+
#define RXADDR_USED 0x00000001
#define RXADDR_WRAP 0x00000002
struct eth_device *dev = eth_get_dev_by_name(devname);
struct macb_device *macb = to_macb(dev);
- if ( macb->phy_addr != phy_adr )
+ if (macb->phy_addr != phy_adr)
return -1;
arch_get_mdio_control(devname);
struct eth_device *dev = eth_get_dev_by_name(devname);
struct macb_device *macb = to_macb(dev);
- if ( macb->phy_addr != phy_adr )
+ if (macb->phy_addr != phy_adr)
return -1;
arch_get_mdio_control(devname);
}
#endif
+#define RX 1
+#define TX 0
+static inline void macb_invalidate_ring_desc(struct macb_device *macb, bool rx)
+{
+ if (rx)
+ invalidate_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
+ MACB_RX_DMA_DESC_SIZE);
+ else
+ invalidate_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
+ MACB_TX_DMA_DESC_SIZE);
+}
+
+static inline void macb_flush_ring_desc(struct macb_device *macb, bool rx)
+{
+ if (rx)
+ flush_dcache_range(macb->rx_ring_dma, macb->rx_ring_dma +
+ MACB_RX_DMA_DESC_SIZE);
+ else
+ flush_dcache_range(macb->tx_ring_dma, macb->tx_ring_dma +
+ MACB_TX_DMA_DESC_SIZE);
+}
+
+static inline void macb_flush_rx_buffer(struct macb_device *macb)
+{
+ flush_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
+ MACB_RX_BUFFER_SIZE);
+}
+
+static inline void macb_invalidate_rx_buffer(struct macb_device *macb)
+{
+ invalidate_dcache_range(macb->rx_buffer_dma, macb->rx_buffer_dma +
+ MACB_RX_BUFFER_SIZE);
+}
#if defined(CONFIG_CMD_NET)
ctrl = length & TXBUF_FRMLEN_MASK;
ctrl |= TXBUF_FRAME_END;
- if (tx_head == (CONFIG_SYS_MACB_TX_RING_SIZE - 1)) {
+ if (tx_head == (MACB_TX_RING_SIZE - 1)) {
ctrl |= TXBUF_WRAP;
macb->tx_head = 0;
- } else
+ } else {
macb->tx_head++;
+ }
macb->tx_ring[tx_head].ctrl = ctrl;
macb->tx_ring[tx_head].addr = paddr;
barrier();
+ macb_flush_ring_desc(macb, TX);
+ /* Do we need check paddr and length is dcache line aligned? */
+ flush_dcache_range(paddr, paddr + length);
macb_writel(macb, NCR, MACB_BIT(TE) | MACB_BIT(RE) | MACB_BIT(TSTART));
/*
* I guess this is necessary because the networking core may
* re-use the transmit buffer as soon as we return...
*/
- for (i = 0; i <= CONFIG_SYS_MACB_TX_TIMEOUT; i++) {
+ for (i = 0; i <= MACB_TX_TIMEOUT; i++) {
barrier();
+ macb_invalidate_ring_desc(macb, TX);
ctrl = macb->tx_ring[tx_head].ctrl;
if (ctrl & TXBUF_USED)
break;
dma_unmap_single(packet, length, paddr);
- if (i <= CONFIG_SYS_MACB_TX_TIMEOUT) {
+ if (i <= MACB_TX_TIMEOUT) {
if (ctrl & TXBUF_UNDERRUN)
printf("%s: TX underrun\n", netdev->name);
if (ctrl & TXBUF_EXHAUSTED)
unsigned int i;
i = macb->rx_tail;
+
+ macb_invalidate_ring_desc(macb, RX);
while (i > new_tail) {
macb->rx_ring[i].addr &= ~RXADDR_USED;
i++;
- if (i > CONFIG_SYS_MACB_RX_RING_SIZE)
+ if (i > MACB_RX_RING_SIZE)
i = 0;
}
}
barrier();
+ macb_flush_ring_desc(macb, RX);
macb->rx_tail = new_tail;
}
u32 status;
for (;;) {
+ macb_invalidate_ring_desc(macb, RX);
+
if (!(macb->rx_ring[rx_tail].addr & RXADDR_USED))
return -1;
if (status & RXBUF_FRAME_END) {
buffer = macb->rx_buffer + 128 * macb->rx_tail;
length = status & RXBUF_FRMLEN_MASK;
+
+ macb_invalidate_rx_buffer(macb);
if (wrapped) {
unsigned int headlen, taillen;
- headlen = 128 * (CONFIG_SYS_MACB_RX_RING_SIZE
+ headlen = 128 * (MACB_RX_RING_SIZE
- macb->rx_tail);
taillen = length - headlen;
memcpy((void *)NetRxPackets[0],
}
NetReceive(buffer, length);
- if (++rx_tail >= CONFIG_SYS_MACB_RX_RING_SIZE)
+ if (++rx_tail >= MACB_RX_RING_SIZE)
rx_tail = 0;
reclaim_rx_buffers(macb, rx_tail);
} else {
- if (++rx_tail >= CONFIG_SYS_MACB_RX_RING_SIZE) {
+ if (++rx_tail >= MACB_RX_RING_SIZE) {
wrapped = 1;
rx_tail = 0;
}
macb_mdio_write(macb, MII_BMCR, (BMCR_ANENABLE
| BMCR_ANRESTART));
- for (i = 0; i < CONFIG_SYS_MACB_AUTONEG_TIMEOUT / 100; i++) {
+ for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
status = macb_mdio_read(macb, MII_BMSR);
if (status & BMSR_ANEGCOMPLETE)
break;
arch_get_mdio_control(netdev->name);
#ifdef CONFIG_MACB_SEARCH_PHY
/* Auto-detect phy_addr */
- if (!macb_phy_find(macb)) {
+ if (!macb_phy_find(macb))
return 0;
- }
#endif /* CONFIG_MACB_SEARCH_PHY */
/* Check if the PHY is up to snuff... */
/* Try to re-negotiate if we don't have link already. */
macb_phy_reset(macb);
- for (i = 0; i < CONFIG_SYS_MACB_AUTONEG_TIMEOUT / 100; i++) {
+ for (i = 0; i < MACB_AUTONEG_TIMEOUT / 100; i++) {
status = macb_mdio_read(macb, MII_BMSR);
if (status & BMSR_LSTATUS)
break;
/* initialize DMA descriptors */
paddr = macb->rx_buffer_dma;
- for (i = 0; i < CONFIG_SYS_MACB_RX_RING_SIZE; i++) {
- if (i == (CONFIG_SYS_MACB_RX_RING_SIZE - 1))
+ for (i = 0; i < MACB_RX_RING_SIZE; i++) {
+ if (i == (MACB_RX_RING_SIZE - 1))
paddr |= RXADDR_WRAP;
macb->rx_ring[i].addr = paddr;
macb->rx_ring[i].ctrl = 0;
paddr += 128;
}
- for (i = 0; i < CONFIG_SYS_MACB_TX_RING_SIZE; i++) {
+ macb_flush_ring_desc(macb, RX);
+ macb_flush_rx_buffer(macb);
+
+ for (i = 0; i < MACB_TX_RING_SIZE; i++) {
macb->tx_ring[i].addr = 0;
- if (i == (CONFIG_SYS_MACB_TX_RING_SIZE - 1))
+ if (i == (MACB_TX_RING_SIZE - 1))
macb->tx_ring[i].ctrl = TXBUF_USED | TXBUF_WRAP;
else
macb->tx_ring[i].ctrl = TXBUF_USED;
}
- macb->rx_tail = macb->tx_head = macb->tx_tail = 0;
+ macb_flush_ring_desc(macb, TX);
+
+ macb->rx_tail = 0;
+ macb->tx_head = 0;
+ macb->tx_tail = 0;
macb_writel(macb, RBQP, macb->rx_ring_dma);
macb_writel(macb, TBQP, macb->tx_ring_dma);
netdev = &macb->netdev;
- macb->rx_buffer = dma_alloc_coherent(CONFIG_SYS_MACB_RX_BUFFER_SIZE,
+ macb->rx_buffer = dma_alloc_coherent(MACB_RX_BUFFER_SIZE,
&macb->rx_buffer_dma);
- macb->rx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_RX_RING_SIZE
- * sizeof(struct macb_dma_desc),
+ macb->rx_ring = dma_alloc_coherent(MACB_RX_DMA_DESC_SIZE,
&macb->rx_ring_dma);
- macb->tx_ring = dma_alloc_coherent(CONFIG_SYS_MACB_TX_RING_SIZE
- * sizeof(struct macb_dma_desc),
+ macb->tx_ring = dma_alloc_coherent(MACB_TX_DMA_DESC_SIZE,
&macb->tx_ring_dma);
+ /* TODO: we need check the rx/tx_ring_dma is dcache line aligned */
+
macb->regs = regs;
macb->phy_addr = phy_addr;
while (phy_mask) {
int addr = ffs(phy_mask) - 1;
int r = get_phy_id(bus, addr, devad, &phy_id);
- if (r < 0)
- return ERR_PTR(r);
/* If the PHY ID is mostly f's, we didn't find anything */
- if ((phy_id & 0x1fffffff) != 0x1fffffff)
+ if (r == 0 && (phy_id & 0x1fffffff) != 0x1fffffff)
return phy_device_create(bus, addr, phy_id, interface);
phy_mask &= ~(1 << addr);
}
/* packet must be a 4 byte boundary */
if ((int)packet & 3) {
- printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n", __func__);
+ printf(SHETHER_NAME ": %s: packet not 4 byte alligned\n"
+ , __func__);
ret = -EFAULT;
goto err;
}
static int sh_eth_reset(struct sh_eth_dev *eth)
{
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
int ret = 0, i;
/* Start e-dmac transmitter and receiver */
/* Perform a software reset and wait for it to complete */
sh_eth_write(eth, EDMR_SRST, EDMR);
- for (i = 0; i < TIMEOUT_CNT ; i++) {
+ for (i = 0; i < TIMEOUT_CNT; i++) {
if (!(sh_eth_read(eth, EDMR) & EDMR_SRST))
break;
udelay(1000);
/* Point the controller to the tx descriptor list. Must use physical
addresses */
sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDLAR);
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
sh_eth_write(eth, ADDR_TO_PHY(port_info->tx_desc_base), TDFAR);
sh_eth_write(eth, ADDR_TO_PHY(cur_tx_desc), TDFXR);
sh_eth_write(eth, 0x01, TDFFR);/* Last discriptor bit */
/* Point the controller to the rx descriptor list */
sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
sh_eth_write(eth, ADDR_TO_PHY(port_info->rx_desc_base), RDFAR);
sh_eth_write(eth, ADDR_TO_PHY(cur_rx_desc), RDFXR);
sh_eth_write(eth, RDFFR_RDLF, RDFFR);
sh_eth_write(eth, 0, TFTR);
sh_eth_write(eth, (FIFO_SIZE_T | FIFO_SIZE_R), FDR);
sh_eth_write(eth, RMCR_RST, RMCR);
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
sh_eth_write(eth, 0, RPADIR);
#endif
sh_eth_write(eth, (FIFO_F_D_RFF | FIFO_F_D_RFD), FCFTR);
sh_eth_write(eth, RFLR_RFL_MIN, RFLR);
#if defined(SH_ETH_TYPE_GETHER)
sh_eth_write(eth, 0, PIPR);
+#endif
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
sh_eth_write(eth, APR_AP, APR);
sh_eth_write(eth, MPR_MP, MPR);
sh_eth_write(eth, TPAUSER_TPAUSE, TPAUSER);
int sh_eth_initialize(bd_t *bd)
{
- int ret = 0;
+ int ret = 0;
struct sh_eth_dev *eth = NULL;
- struct eth_device *dev = NULL;
+ struct eth_device *dev = NULL;
- eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
+ eth = (struct sh_eth_dev *)malloc(sizeof(struct sh_eth_dev));
if (!eth) {
printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
ret = -ENOMEM;
goto err;
}
- dev = (struct eth_device *)malloc(sizeof(struct eth_device));
+ dev = (struct eth_device *)malloc(sizeof(struct eth_device));
if (!dev) {
printf(SHETHER_NAME ": %s: malloc failed\n", __func__);
ret = -ENOMEM;
goto err;
}
- memset(dev, 0, sizeof(struct eth_device));
- memset(eth, 0, sizeof(struct sh_eth_dev));
+ memset(dev, 0, sizeof(struct eth_device));
+ memset(eth, 0, sizeof(struct sh_eth_dev));
eth->port = CONFIG_SH_ETHER_USE_PORT;
eth->port_info[eth->port].phy_addr = CONFIG_SH_ETHER_PHY_ADDR;
- dev->priv = (void *)eth;
- dev->iobase = 0;
- dev->init = sh_eth_init;
- dev->halt = sh_eth_halt;
- dev->send = sh_eth_send;
- dev->recv = sh_eth_recv;
- eth->port_info[eth->port].dev = dev;
+ dev->priv = (void *)eth;
+ dev->iobase = 0;
+ dev->init = sh_eth_init;
+ dev->halt = sh_eth_halt;
+ dev->send = sh_eth_send;
+ dev->recv = sh_eth_recv;
+ eth->port_info[eth->port].dev = dev;
sprintf(dev->name, SHETHER_NAME);
- /* Register Device to EtherNet subsystem */
- eth_register(dev);
+ /* Register Device to EtherNet subsystem */
+ eth_register(dev);
bb_miiphy_buses[0].priv = eth;
miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write);
[RMII_MII] = 0x0790,
};
+#if defined(SH_ETH_TYPE_RZ)
+static const u16 sh_eth_offset_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
+ [EDSR] = 0x0000,
+ [EDMR] = 0x0400,
+ [EDTRR] = 0x0408,
+ [EDRRR] = 0x0410,
+ [EESR] = 0x0428,
+ [EESIPR] = 0x0430,
+ [TDLAR] = 0x0010,
+ [TDFAR] = 0x0014,
+ [TDFXR] = 0x0018,
+ [TDFFR] = 0x001c,
+ [RDLAR] = 0x0030,
+ [RDFAR] = 0x0034,
+ [RDFXR] = 0x0038,
+ [RDFFR] = 0x003c,
+ [TRSCER] = 0x0438,
+ [RMFCR] = 0x0440,
+ [TFTR] = 0x0448,
+ [FDR] = 0x0450,
+ [RMCR] = 0x0458,
+ [RPADIR] = 0x0460,
+ [FCFTR] = 0x0468,
+ [CSMR] = 0x04E4,
+
+ [ECMR] = 0x0500,
+ [ECSR] = 0x0510,
+ [ECSIPR] = 0x0518,
+ [PSR] = 0x0528,
+ [PIPR] = 0x052c,
+ [RFLR] = 0x0508,
+ [APR] = 0x0554,
+ [MPR] = 0x0558,
+ [PFTCR] = 0x055c,
+ [PFRCR] = 0x0560,
+ [TPAUSER] = 0x0564,
+ [GECMR] = 0x05b0,
+ [BCULR] = 0x05b4,
+ [MAHR] = 0x05c0,
+ [MALR] = 0x05c8,
+ [TROCR] = 0x0700,
+ [CDCR] = 0x0708,
+ [LCCR] = 0x0710,
+ [CEFCR] = 0x0740,
+ [FRECR] = 0x0748,
+ [TSFRCR] = 0x0750,
+ [TLFRCR] = 0x0758,
+ [RFCR] = 0x0760,
+ [CERCR] = 0x0768,
+ [CEECR] = 0x0770,
+ [MAFCR] = 0x0778,
+ [RMII_MII] = 0x0790,
+};
+#endif
+
static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
[ECMR] = 0x0100,
[RFLR] = 0x0108,
#elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791)
#define SH_ETH_TYPE_ETHER
#define BASE_IO_ADDR 0xEE700200
+#elif defined(CONFIG_R7S72100)
+#define SH_ETH_TYPE_RZ
+#define BASE_IO_ADDR 0xE8203000
#endif
/*
* Register's bits
* Copy from Linux driver source code
*/
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
/* EDSR */
enum EDSR_BIT {
EDSR_ENT = 0x01, EDSR_ENR = 0x02,
/* EDMR */
enum DMAC_M_BIT {
EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
EDMR_SRST = 0x03, /* Receive/Send reset */
EMDR_DESC_R = 0x30, /* Descriptor reserve size */
EDMR_EL = 0x40, /* Litte endian */
/* EDTRR */
enum DMAC_T_BIT {
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
EDTRR_TRNS = 0x03,
#else
EDTRR_TRNS = 0x01,
/* EESR */
enum EESR_BIT {
-
#if defined(SH_ETH_TYPE_ETHER)
EESR_TWB = 0x40000000,
#else
EESR_CD = 0x00000200, EESR_RTO = 0x00000100,
EESR_RMAF = 0x00000080, EESR_CEEF = 0x00000040,
EESR_CELF = 0x00000020, EESR_RRF = 0x00000010,
- rESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
+ EESR_RTLF = 0x00000008, EESR_RTSF = 0x00000004,
EESR_PRE = 0x00000002, EESR_CERF = 0x00000001,
};
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
# define TX_CHECK (EESR_TC1 | EESR_FTC)
# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
| EESR_RFRMER | EESR_TFE | EESR_TDE | EESR_ECI)
/* Transfer descriptor bit */
enum TD_STS_BIT {
-#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_ETHER) || \
+ defined(SH_ETH_TYPE_RZ)
TD_TACT = 0x80000000,
#else
TD_TACT = 0x7fffffff,
enum RECV_RST_BIT { RMCR_RST = 0x01, };
/* ECMR */
enum FELIC_MODE_BIT {
-#if defined(SH_ETH_TYPE_GETHER)
- ECMR_TRCCM=0x04000000, ECMR_RCSC= 0x00800000, ECMR_DPAD= 0x00200000,
- ECMR_RZPF = 0x00100000,
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
+ ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
+ ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
#endif
ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
};
-#if defined(SH_ETH_TYPE_GETHER)
-#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | ECMR_RXF | \
- ECMR_TXF | ECMR_MCT)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
+#define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_ZPF | ECMR_PFR | \
+ ECMR_RXF | ECMR_TXF | ECMR_MCT)
#elif defined(SH_ETH_TYPE_ETHER)
#define ECMR_CHG_DM (ECMR_ZPF | ECMR_PFR | ECMR_RXF | ECMR_TXF)
#else
ECSR_MPD = 0x02, ECSR_ICD = 0x01,
};
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
# define ECSR_INIT (ECSR_ICD | ECSIPR_MPDIP)
#else
# define ECSR_INIT (ECSR_BRCRX | ECSR_PSRTO | \
ECSIPR_ICDIP = 0x01,
};
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
# define ECSIPR_INIT (ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
#else
# define ECSIPR_INIT (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | \
RPADIR_PADR = 0x0003f,
};
-#if defined(SH_ETH_TYPE_GETHER)
+#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
# define RPADIR_INIT (0x00)
#else
# define RPADIR_INIT (RPADIR_PADS1)
const u16 *reg_offset = sh_eth_offset_gigabit;
#elif defined(SH_ETH_TYPE_ETHER)
const u16 *reg_offset = sh_eth_offset_fast_sh4;
+#elif defined(SH_ETH_TYPE_RZ)
+ const u16 *reg_offset = sh_eth_offset_rz;
#else
#error
#endif
}
bus = i2c_get_bus_num_fdt(parent);
- if (p->bus < 0) {
+ if (bus < 0) {
debug("%s: Cannot find I2C bus\n", __func__);
return -ENOENT;
}
#define UCR3_DSR (1<<10) /* Data set ready */
#define UCR3_DCD (1<<9) /* Data carrier detect */
#define UCR3_RI (1<<8) /* Ring indicator */
-#define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
+#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
while (!(__REG(UART_PHYS + UCR2) & UCR2_SRST));
- __REG(UART_PHYS + UCR3) = 0x0704;
+ __REG(UART_PHYS + UCR3) = 0x0704 | UCR3_ADNIMP;
__REG(UART_PHYS + UCR4) = 0x8000;
__REG(UART_PHYS + UESC) = 0x002b;
__REG(UART_PHYS + UTIM) = 0x0;
struct fsl_spi_slave {
struct spi_slave slave;
+ ccsr_espi_t *espi;
unsigned int div16;
unsigned int pm;
+ int tx_timeout;
unsigned int mode;
size_t cmd_len;
u8 cmd_buf[16];
};
#define to_fsl_spi_slave(s) container_of(s, struct fsl_spi_slave, slave)
+#define US_PER_SECOND 1000000UL
#define ESPI_MAX_CS_NUM 4
+#define ESPI_FIFO_WIDTH_BIT 32
#define ESPI_EV_RNE (1 << 9)
#define ESPI_EV_TNF (1 << 8)
+#define ESPI_EV_DON (1 << 14)
+#define ESPI_EV_TXE (1 << 15)
+#define ESPI_EV_RFCNT_SHIFT 24
+#define ESPI_EV_RFCNT_MASK (0x3f << ESPI_EV_RFCNT_SHIFT)
#define ESPI_MODE_EN (1 << 31) /* Enable interface */
#define ESPI_MODE_TXTHR(x) ((x) << 8) /* Tx FIFO threshold */
struct fsl_spi_slave *fsl;
sys_info_t sysinfo;
unsigned long spibrg = 0;
+ unsigned long spi_freq = 0;
unsigned char pm = 0;
if (!spi_cs_is_valid(bus, cs))
if (!fsl)
return NULL;
+ fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
fsl->mode = mode;
fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN;
pm--;
fsl->pm = pm;
+ if (fsl->div16)
+ spi_freq = spibrg / ((pm + 1) * 2 * 16);
+ else
+ spi_freq = spibrg / ((pm + 1) * 2);
+
+ /* set tx_timeout to 10 times of one espi FIFO entry go out */
+ fsl->tx_timeout = DIV_ROUND_UP((US_PER_SECOND * ESPI_FIFO_WIDTH_BIT
+ * 10), spi_freq);
+
return &fsl->slave;
}
int spi_claim_bus(struct spi_slave *slave)
{
struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
- ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
+ ccsr_espi_t *espi = fsl->espi;
unsigned char pm = fsl->pm;
unsigned int cs = slave->cs;
unsigned int mode = fsl->mode;
}
+static void fsl_espi_tx(struct fsl_spi_slave *fsl, const void *dout)
+{
+ ccsr_espi_t *espi = fsl->espi;
+ unsigned int tmpdout, event;
+ int tmp_tx_timeout;
+
+ if (dout)
+ tmpdout = *(u32 *)dout;
+ else
+ tmpdout = 0;
+
+ out_be32(&espi->tx, tmpdout);
+ out_be32(&espi->event, ESPI_EV_TNF);
+ debug("***spi_xfer:...%08x written\n", tmpdout);
+
+ tmp_tx_timeout = fsl->tx_timeout;
+ /* Wait for eSPI transmit to go out */
+ while (tmp_tx_timeout--) {
+ event = in_be32(&espi->event);
+ if (event & ESPI_EV_DON || event & ESPI_EV_TXE) {
+ out_be32(&espi->event, ESPI_EV_TXE);
+ break;
+ }
+ udelay(1);
+ }
+
+ if (tmp_tx_timeout < 0)
+ debug("***spi_xfer:...Tx timeout! event = %08x\n", event);
+}
+
+static int fsl_espi_rx(struct fsl_spi_slave *fsl, void *din, unsigned int bytes)
+{
+ ccsr_espi_t *espi = fsl->espi;
+ unsigned int tmpdin, rx_times;
+ unsigned char *buf, *p_cursor;
+
+ if (bytes <= 0)
+ return 0;
+
+ rx_times = DIV_ROUND_UP(bytes, 4);
+ buf = (unsigned char *)malloc(4 * rx_times);
+ if (!buf) {
+ debug("SF: Failed to malloc memory.\n");
+ return -1;
+ }
+ p_cursor = buf;
+ while (rx_times--) {
+ tmpdin = in_be32(&espi->rx);
+ debug("***spi_xfer:...%08x readed\n", tmpdin);
+ *(u32 *)p_cursor = tmpdin;
+ p_cursor += 4;
+ }
+
+ if (din)
+ memcpy(din, buf, bytes);
+
+ free(buf);
+ out_be32(&espi->event, ESPI_EV_RNE);
+
+ return bytes;
+}
+
int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *data_out,
void *data_in, unsigned long flags)
{
struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
- ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
- unsigned int tmpdout, tmpdin, event;
+ ccsr_espi_t *espi = fsl->espi;
+ unsigned int event, rx_bytes;
const void *dout = NULL;
void *din = NULL;
int len = 0;
int num_blks, num_chunks, max_tran_len, tran_len;
int num_bytes;
- unsigned char *ch;
unsigned char *buffer = NULL;
size_t buf_len;
u8 *cmd_buf = fsl->cmd_buf;
size_t cmd_len = fsl->cmd_len;
size_t data_len = bitlen / 8;
size_t rx_offset = 0;
+ int rf_cnt;
max_tran_len = fsl->max_transfer_length;
switch (flags) {
break;
}
- debug("spi_xfer: slave %u:%u dout %08X(%p) din %08X(%p) len %u\n",
- slave->bus, slave->cs, *(uint *) dout,
- dout, *(uint *) din, din, len);
+ debug("spi_xfer: data_out %08X(%p) data_in %08X(%p) len %u\n",
+ *(uint *)data_out, data_out, *(uint *)data_in, data_in, len);
num_chunks = DIV_ROUND_UP(data_len, max_tran_len);
while (num_chunks--) {
/* Clear all eSPI events */
out_be32(&espi->event , 0xffffffff);
/* handle data in 32-bit chunks */
- while (num_blks--) {
-
+ while (num_blks) {
event = in_be32(&espi->event);
if (event & ESPI_EV_TNF) {
- tmpdout = *(u32 *)dout;
-
+ fsl_espi_tx(fsl, dout);
/* Set up the next iteration */
if (len > 4) {
len -= 4;
dout += 4;
}
-
- out_be32(&espi->tx, tmpdout);
- out_be32(&espi->event, ESPI_EV_TNF);
- debug("***spi_xfer:...%08x written\n", tmpdout);
}
- /* Wait for eSPI transmit to get out */
- udelay(80);
-
event = in_be32(&espi->event);
if (event & ESPI_EV_RNE) {
- tmpdin = in_be32(&espi->rx);
- if (num_blks == 0 && num_bytes != 0) {
- ch = (unsigned char *)&tmpdin;
- while (num_bytes--)
- *(unsigned char *)din++ = *ch++;
- } else {
- *(u32 *) din = tmpdin;
- din += 4;
+ rf_cnt = ((event & ESPI_EV_RFCNT_MASK)
+ >> ESPI_EV_RFCNT_SHIFT);
+ if (rf_cnt >= 4)
+ rx_bytes = 4;
+ else if (num_blks == 1 && rf_cnt == num_bytes)
+ rx_bytes = num_bytes;
+ else
+ continue;
+ if (fsl_espi_rx(fsl, din, rx_bytes)
+ == rx_bytes) {
+ num_blks--;
+ if (din)
+ din = (unsigned char *)din
+ + rx_bytes;
}
-
- out_be32(&espi->event, in_be32(&espi->event)
- | ESPI_EV_RNE);
- debug("***spi_xfer:...%08x readed\n", tmpdin);
}
}
if (data_in) {
void spi_cs_activate(struct spi_slave *slave)
{
struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
- ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
+ ccsr_espi_t *espi = fsl->espi;
unsigned int com = 0;
size_t data_len = fsl->data_len;
void spi_cs_deactivate(struct spi_slave *slave)
{
- ccsr_espi_t *espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR);
+ struct fsl_spi_slave *fsl = to_fsl_spi_slave(slave);
+ ccsr_espi_t *espi = fsl->espi;
/* clear the RXCNT and TXCNT */
out_be32(&espi->mode, in_be32(&espi->mode) & (~ESPI_MODE_EN));
/*
* Check if it is time to work on a new byte.
*/
- if((j % 8) == 0) {
- tmpdout = *txd++;
+ if ((j % 8) == 0) {
+ if (txd)
+ tmpdout = *txd++;
+ else
+ tmpdout = 0;
if(j != 0) {
- *rxd++ = tmpdin;
+ if (rxd)
+ *rxd++ = tmpdin;
}
tmpdin = 0;
}
* bits over to left-justify them. Then store the last byte
* read in.
*/
- if((bitlen % 8) != 0)
- tmpdin <<= 8 - (bitlen % 8);
- *rxd++ = tmpdin;
+ if (rxd) {
+ if ((bitlen % 8) != 0)
+ tmpdin <<= 8 - (bitlen % 8);
+ *rxd++ = tmpdin;
+ }
if (flags & SPI_XFER_END)
spi_cs_deactivate(slave);
}
#endif
-static struct usb_endpoint_descriptor ep0_out_desc = {
- .bLength = sizeof(struct usb_endpoint_descriptor),
- .bDescriptorType = USB_DT_ENDPOINT,
- .bEndpointAddress = 0,
- .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
-};
-
-static struct usb_endpoint_descriptor ep0_in_desc = {
+static struct usb_endpoint_descriptor ep0_desc = {
.bLength = sizeof(struct usb_endpoint_descriptor),
.bDescriptorType = USB_DT_ENDPOINT,
.bEndpointAddress = USB_DIR_IN,
static struct usb_request *
ci_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags)
{
+ struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
+ int num;
struct ci_req *ci_req;
+ num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+ if (num == 0 && controller.ep0_req)
+ return &controller.ep0_req->req;
+
ci_req = memalign(ARCH_DMA_MINALIGN, sizeof(*ci_req));
if (!ci_req)
return NULL;
INIT_LIST_HEAD(&ci_req->queue);
ci_req->b_buf = 0;
+ if (num == 0)
+ controller.ep0_req = ci_req;
+
return &ci_req->req;
}
static void ci_ep_free_request(struct usb_ep *ep, struct usb_request *req)
{
- struct ci_req *ci_req;
+ struct ci_ep *ci_ep = container_of(ep, struct ci_ep, ep);
+ struct ci_req *ci_req = container_of(req, struct ci_req, req);
+ int num;
+
+ num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+ if (num == 0)
+ controller.ep0_req = 0;
- ci_req = container_of(req, struct ci_req, req);
if (ci_req->b_buf)
free(ci_req->b_buf);
free(ci_req);
ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue);
len = ci_req->req.length;
- item->next = TERMINATE;
- item->info = INFO_BYTES(len) | INFO_IOC | INFO_ACTIVE;
+ item->info = INFO_BYTES(len) | INFO_ACTIVE;
item->page0 = (uint32_t)ci_req->hw_buf;
item->page1 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x1000;
item->page2 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x2000;
item->page3 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x3000;
item->page4 = ((uint32_t)ci_req->hw_buf & 0xfffff000) + 0x4000;
- ci_flush_qtd(num);
head->next = (unsigned) item;
head->info = 0;
+ /*
+ * When sending the data for an IN transaction, the attached host
+ * knows that all data for the IN is sent when one of the following
+ * occurs:
+ * a) A zero-length packet is transmitted.
+ * b) A packet with length that isn't an exact multiple of the ep's
+ * maxpacket is transmitted.
+ * c) Enough data is sent to exactly fill the host's maximum expected
+ * IN transaction size.
+ *
+ * One of these conditions MUST apply at the end of an IN transaction,
+ * or the transaction will not be considered complete by the host. If
+ * none of (a)..(c) already applies, then we must force (a) to apply
+ * by explicitly sending an extra zero-length packet.
+ */
+ /* IN !a !b !c */
+ if (in && len && !(len % ci_ep->ep.maxpacket) && ci_req->req.zero) {
+ /*
+ * Each endpoint has 2 items allocated, even though typically
+ * only 1 is used at a time since either an IN or an OUT but
+ * not both is queued. For an IN transaction, item currently
+ * points at the second of these items, so we know that we
+ * can use (item - 1) to transmit the extra zero-length packet
+ */
+ item->next = (unsigned)(item - 1);
+ item--;
+ item->info = INFO_ACTIVE;
+ }
+
+ item->next = TERMINATE;
+ item->info |= INFO_IOC;
+
+ ci_flush_qtd(num);
+
DBG("ept%d %s queue len %x, req %p, buffer %p\n",
num, in ? "in" : "out", len, ci_req, ci_req->hw_buf);
ci_flush_qh(num);
num = ci_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
in = (ci_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
+ if (!num && ci_ep->req_primed) {
+ /*
+ * The flipping of ep0 between IN and OUT relies on
+ * ci_ep_queue consuming the current IN/OUT setting
+ * immediately. If this is deferred to a later point when the
+ * req is pulled out of ci_req->queue, then the IN/OUT setting
+ * may have been changed since the req was queued, and state
+ * will get out of sync. This condition doesn't occur today,
+ * but could if bugs were introduced later, and this error
+ * check will save a lot of debugging time.
+ */
+ printf("%s: ep0 transaction already in progress\n", __func__);
+ return -EPROTO;
+ }
+
ret = ci_bounce(ci_req, in);
if (ret)
return ret;
return 0;
}
+static void flip_ep0_direction(void)
+{
+ if (ep0_desc.bEndpointAddress == USB_DIR_IN) {
+ DBG("%s: Flipping ep0 ot OUT\n", __func__);
+ ep0_desc.bEndpointAddress = 0;
+ } else {
+ DBG("%s: Flipping ep0 ot IN\n", __func__);
+ ep0_desc.bEndpointAddress = USB_DIR_IN;
+ }
+}
+
static void handle_ep_complete(struct ci_ep *ep)
{
struct ept_queue_item *item;
num = ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
in = (ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
- if (num == 0)
- ep->desc = &ep0_out_desc;
item = ci_get_qtd(num, in);
ci_invalidate_qtd(num);
DBG("ept%d %s req %p, complete %x\n",
num, in ? "in" : "out", ci_req, len);
- ci_req->req.complete(&ep->ep, &ci_req->req);
- if (num == 0) {
+ if (num != 0 || controller.ep0_data_phase)
+ ci_req->req.complete(&ep->ep, &ci_req->req);
+ if (num == 0 && controller.ep0_data_phase) {
+ /*
+ * Data Stage is complete, so flip ep0 dir for Status Stage,
+ * which always transfers a packet in the opposite direction.
+ */
+ DBG("%s: flip ep0 dir for Status Stage\n", __func__);
+ flip_ep0_direction();
+ controller.ep0_data_phase = false;
ci_req->req.length = 0;
usb_ep_queue(&ep->ep, &ci_req->req, 0);
- ep->desc = &ep0_in_desc;
}
}
int num, in, _num, _in, i;
char *buf;
- ci_req = list_first_entry(&ci_ep->queue, struct ci_req, queue);
+ ci_req = controller.ep0_req;
req = &ci_req->req;
head = ci_get_qh(0, 0); /* EP0 OUT */
#else
writel(EPT_RX(0), &udc->epstat);
#endif
- DBG("handle setup %s, %x, %x index %x value %x\n", reqname(r.bRequest),
- r.bRequestType, r.bRequest, r.wIndex, r.wValue);
+ DBG("handle setup %s, %x, %x index %x value %x length %x\n",
+ reqname(r.bRequest), r.bRequestType, r.bRequest, r.wIndex,
+ r.wValue, r.wLength);
+
+ /* Set EP0 dir for Data Stage based on Setup Stage data */
+ if (r.bRequestType & USB_DIR_IN) {
+ DBG("%s: Set ep0 to IN for Data Stage\n", __func__);
+ ep0_desc.bEndpointAddress = USB_DIR_IN;
+ } else {
+ DBG("%s: Set ep0 to OUT for Data Stage\n", __func__);
+ ep0_desc.bEndpointAddress = 0;
+ }
+ if (r.wLength) {
+ controller.ep0_data_phase = true;
+ } else {
+ /* 0 length -> no Data Stage. Flip dir for Status Stage */
+ DBG("%s: 0 length: flip ep0 dir for Status Stage\n", __func__);
+ flip_ep0_direction();
+ controller.ep0_data_phase = false;
+ }
list_del_init(&ci_req->queue);
ci_ep->req_primed = false;
return value;
}
+void udc_disconnect(void)
+{
+ struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
+ /* disable pullup */
+ stop_activity();
+ writel(USBCMD_FS2, &udc->usbcmd);
+ udelay(800);
+ if (controller.driver)
+ controller.driver->disconnect(&controller.gadget);
+}
+
static int ci_pullup(struct usb_gadget *gadget, int is_on)
{
struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
/* Turn on the USB connection by enabling the pullup resistor */
writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RUN, &udc->usbcmd);
} else {
- stop_activity();
- writel(USBCMD_FS2, &udc->usbcmd);
- udelay(800);
- if (controller.driver)
- controller.driver->disconnect(gadget);
+ udc_disconnect();
}
return 0;
}
-void udc_disconnect(void)
-{
- struct ci_udc *udc = (struct ci_udc *)controller.ctrl->hcor;
- /* disable pullup */
- stop_activity();
- writel(USBCMD_FS2, &udc->usbcmd);
- udelay(800);
- if (controller.driver)
- controller.driver->disconnect(&controller.gadget);
-}
-
static int ci_udc_probe(void)
{
struct ept_queue_head *head;
/* Init EP 0 */
memcpy(&controller.ep[0].ep, &ci_ep_init[0], sizeof(*ci_ep_init));
- controller.ep[0].desc = &ep0_in_desc;
+ controller.ep[0].desc = &ep0_desc;
INIT_LIST_HEAD(&controller.ep[0].queue);
controller.ep[0].req_primed = false;
controller.gadget.ep0 = &controller.ep[0].ep;
&controller.gadget.ep_list);
}
+ ci_ep_alloc_request(&controller.ep[0].ep, 0);
+ if (!controller.ep0_req) {
+ free(controller.items_mem);
+ free(controller.epts);
+ return -ENOMEM;
+ }
+
return 0;
}
int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
{
+ udc_disconnect();
+
+ ci_ep_free_request(&controller.ep[0].ep, &controller.ep0_req->req);
+ free(controller.items_mem);
+ free(controller.epts);
+
return 0;
}
struct ci_drv {
struct usb_gadget gadget;
+ struct ci_req *ep0_req;
+ bool ep0_data_phase;
struct usb_gadget_driver *driver;
struct ehci_ctrl *ctrl;
struct ept_queue_head *epts;
| LCDC_BASECTRL_DMAIEN | LCDC_BASECTRL_DFETCH;
desc->next = (u32)desc;
+ /* Flush the DMA descriptor if we enabled dcache */
+ flush_dcache_range((u32)desc, (u32)desc + sizeof(*desc));
+
lcdc_writel(®s->lcdc_baseaddr, desc->address);
lcdc_writel(®s->lcdc_basectrl, desc->control);
lcdc_writel(®s->lcdc_basenext, desc->next);
lcdc_writel(®s->lcdc_lcden, value | LCDC_LCDEN_PWMEN);
while (!(lcdc_readl(®s->lcdc_lcdsr) & LCDC_LCDSR_PWMSTS))
udelay(1);
+
+ /* Enable flushing if we enabled dcache */
+ lcd_set_flush_dcache(1);
}
DEVICE_TREE := unset
endif
+ifneq ($(EXT_DTB),)
+DTB := $(EXT_DTB)
+else
DTB := arch/$(ARCH)/dts/$(DEVICE_TREE).dtb
-
-quiet_cmd_copy = COPY $@
- cmd_copy = cp $< $@
+endif
$(obj)/dt.dtb: $(DTB) FORCE
- $(call if_changed,copy)
+ $(call if_changed,shipped)
targets += dt.dtb
unsigned int no_blks_reqd = 0;
/* allocation of direct blocks */
- for (i = 0; i < INDIRECT_BLOCKS; i++) {
+ for (i = 0; total_remaining_blocks && i < INDIRECT_BLOCKS; i++) {
direct_blockno = ext4fs_get_new_blk_no();
if (direct_blockno == -1) {
printf("no block left to assign\n");
debug("DB %ld: %u\n", direct_blockno, total_remaining_blocks);
total_remaining_blocks--;
- if (total_remaining_blocks == 0)
- break;
}
alloc_single_indirect_block(file_inode, &total_remaining_blocks,
unsigned int ibmap_idx;
struct ext_filesystem *fs = get_fs();
ALLOC_CACHE_ALIGN_BUFFER(char, filename, 256);
- memset(filename, 0x00, sizeof(filename));
+ memset(filename, 0x00, 256);
g_parent_inode = zalloc(sizeof(struct ext2_inode));
if (!g_parent_inode)
total_sector = bs.total_sect;
if (total_sector == 0)
- total_sector = cur_part_info.size;
+ total_sector = (int)cur_part_info.size; /* cast of lbaint_t */
if (mydata->fatsize == 32)
mydata->fatlength = bs.fat32_length;
for (b = pL->frag.listHead; b != NULL; b = b->next) {
jNode = (struct jffs2_raw_inode *) get_node_mem(b->offset,
pL->readbuf);
- if ((inode == jNode->ino)) {
+ if (inode == jNode->ino) {
#if 0
putLabeledWord("\r\n\r\nread_inode: totlen = ", jNode->totlen);
putLabeledWord("read_inode: inode = ", jNode->ino);
struct global_data *new_gd; /* relocated global data */
#ifdef CONFIG_DM
- struct device *dm_root; /* Root instance for Driver Model */
+ struct udevice *dm_root;/* Root instance for Driver Model */
struct list_head uclass_root; /* Head of core tree */
#endif
GPIOF_UNKNOWN,
};
-struct device;
+struct udevice;
/**
* struct struct dm_gpio_ops - Driver model GPIO operations
* all devices. Be careful not to confuse offset with gpio in the parameters.
*/
struct dm_gpio_ops {
- int (*request)(struct device *dev, unsigned offset, const char *label);
- int (*free)(struct device *dev, unsigned offset);
- int (*direction_input)(struct device *dev, unsigned offset);
- int (*direction_output)(struct device *dev, unsigned offset,
+ int (*request)(struct udevice *dev, unsigned offset, const char *label);
+ int (*free)(struct udevice *dev, unsigned offset);
+ int (*direction_input)(struct udevice *dev, unsigned offset);
+ int (*direction_output)(struct udevice *dev, unsigned offset,
int value);
- int (*get_value)(struct device *dev, unsigned offset);
- int (*set_value)(struct device *dev, unsigned offset, int value);
- int (*get_function)(struct device *dev, unsigned offset);
- int (*get_state)(struct device *dev, unsigned offset, char *state,
+ int (*get_value)(struct udevice *dev, unsigned offset);
+ int (*set_value)(struct udevice *dev, unsigned offset, int value);
+ int (*get_function)(struct udevice *dev, unsigned offset);
+ int (*get_state)(struct udevice *dev, unsigned offset, char *state,
int maxlen);
};
* @offset_count: Returns number of GPIOs within this bank
* @return bank name of this device
*/
-const char *gpio_get_bank_info(struct device *dev, int *offset_count);
+const char *gpio_get_bank_info(struct udevice *dev, int *offset_count);
/**
* gpio_lookup_name - Look up a GPIO name and return its details
* @offsetp: Returns the offset number within this device
* @gpiop: Returns the absolute GPIO number, numbered from 0
*/
-int gpio_lookup_name(const char *name, struct device **devp,
+int gpio_lookup_name(const char *name, struct udevice **devp,
unsigned int *offsetp, unsigned int *gpiop);
#endif /* _ASM_GENERIC_GPIO_H_ */
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * Add to readline cmdline-editing by
+ * (C) Copyright 2005
+ * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __AUTOBOOT_H
+#define __AUTOBOOT_H
+
+#ifdef CONFIG_BOOTDELAY
+/**
+ * bootdelay_process() - process the bootd delay
+ *
+ * Process the boot delay, boot limit, then get the value of either
+ * bootcmd, failbootcmd or altbootcmd depending on the current state.
+ * Return this command so it can be executed.
+ *
+ * @return command to executed
+ */
+const char *bootdelay_process(void);
+
+/**
+ * autoboot_command() - run the autoboot command
+ *
+ * If enabled, run the autoboot command returned from bootdelay_process().
+ * Also do the CONFIG_MENUKEY processing if enabled.
+ *
+ * @cmd: Command to run
+ */
+void autoboot_command(const char *cmd);
+#else
+static inline const char *bootdelay_process(void)
+{
+ return NULL;
+}
+
+static inline void autoboot_command(const char *s)
+{
+}
+#endif
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2000-2009
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _BOOTM_H
+#define _BOOTM_H
+
+#include <command.h>
+#include <image.h>
+
+#define BOOTM_ERR_RESET (-1)
+#define BOOTM_ERR_OVERLAP (-2)
+#define BOOTM_ERR_UNIMPLEMENTED (-3)
+
+/*
+ * Continue booting an OS image; caller already has:
+ * - copied image header to global variable `header'
+ * - checked header magic number, checksums (both header & image),
+ * - verified image architecture (PPC) and type (KERNEL or MULTI),
+ * - loaded (first part of) image to header load address,
+ * - disabled interrupts.
+ *
+ * @flag: Flags indicating what to do (BOOTM_STATE_...)
+ * @argc: Number of arguments. Note that the arguments are shifted down
+ * so that 0 is the first argument not processed by U-Boot, and
+ * argc is adjusted accordingly. This avoids confusion as to how
+ * many arguments are available for the OS.
+ * @images: Pointers to os/initrd/fdt
+ * @return 1 on error. On success the OS boots so this function does
+ * not return.
+ */
+typedef int boot_os_fn(int flag, int argc, char * const argv[],
+ bootm_headers_t *images);
+
+extern boot_os_fn do_bootm_linux;
+int do_bootelf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
+void lynxkdi_boot(image_header_t *hdr);
+
+boot_os_fn *bootm_os_get_boot_func(int os);
+
+int bootm_host_load_images(const void *fit, int cfg_noffset);
+
+int boot_selected_os(int argc, char * const argv[], int state,
+ bootm_headers_t *images, boot_os_fn *boot_fn);
+
+ulong bootm_disable_interrupts(void);
+
+/* This is a special function used by bootz */
+int bootm_find_ramdisk_fdt(int flag, int argc, char * const argv[]);
+
+int do_bootm_states(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[],
+ int states, bootm_headers_t *images, int boot_progress);
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __BOOTRETRY_H
+#define __BOOTRETRY_H
+
+#ifdef CONFIG_BOOT_RETRY_TIME
+/**
+ * bootretry_tstc_timeout() - ensure we get a keypress before timeout
+ *
+ * Check for a keypress repeatedly, resetting the watchdog each time. If a
+ * keypress is not received within the command timeout, return an error.
+ *
+ * @return 0 if a key is received in time, -ETIMEDOUT if not
+ */
+int bootretry_tstc_timeout(void);
+
+/**
+ * bootretry_init_cmd_timeout() - set up command timeout
+ *
+ * Get the required command timeout from the environment.
+ */
+void bootretry_init_cmd_timeout(void);
+
+/**
+ * bootretry_reset_cmd_timeout() - reset command timeout
+ *
+ * Reset the command timeout so that the user has a fresh start. This is
+ * typically used when input is received from the user.
+ */
+void bootretry_reset_cmd_timeout(void);
+
+/** bootretry_dont_retry() - Indicate that we should not retry the boot */
+void bootretry_dont_retry(void);
+#else
+static inline int bootretry_tstc_timeout(void)
+{
+ return 0;
+}
+
+static inline void bootretry_init_cmd_timeout(void)
+{
+}
+
+static inline void bootretry_reset_cmd_timeout(void)
+{
+}
+
+static inline void bootretry_dont_retry(void)
+{
+}
+
+#endif
+
+#endif
--- /dev/null
+/*
+ * (C) Copyright 2014 Google, Inc
+ * Simon Glass <sjg@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __CLI_H
+#define __CLI_H
+
+/**
+ * Go into the command loop
+ *
+ * This will return if we get a timeout waiting for a command. See
+ * CONFIG_BOOT_RETRY_TIME.
+ */
+void cli_simple_loop(void);
+
+/**
+ * cli_simple_run_command() - Execute a command with the simple CLI
+ *
+ * @cmd: String containing the command to execute
+ * @flag Flag value - see CMD_FLAG_...
+ * @return 1 - command executed, repeatable
+ * 0 - command executed but not repeatable, interrupted commands are
+ * always considered not repeatable
+ * -1 - not executed (unrecognized, bootd recursion or too many args)
+ * (If cmd is NULL or "" or longer than CONFIG_SYS_CBSIZE-1 it is
+ * considered unrecognized)
+ */
+int cli_simple_run_command(const char *cmd, int flag);
+
+/**
+ * cli_simple_run_command_list() - Execute a list of command
+ *
+ * The commands should be separated by ; or \n and will be executed
+ * by the built-in parser.
+ *
+ * This function cannot take a const char * for the command, since if it
+ * finds newlines in the string, it replaces them with \0.
+ *
+ * @param cmd String containing list of commands
+ * @param flag Execution flags (CMD_FLAG_...)
+ * @return 0 on success, or != 0 on error.
+ */
+int cli_simple_run_command_list(char *cmd, int flag);
+
+/**
+ * cli_readline() - read a line into the console_buffer
+ *
+ * This is a convenience function which calls cli_readline_into_buffer().
+ *
+ * @prompt: Prompt to display
+ * @return command line length excluding terminator, or -ve on error
+ */
+int cli_readline(const char *const prompt);
+
+/**
+ * readline_into_buffer() - read a line into a buffer
+ *
+ * Display the prompt, then read a command line into @buffer. The
+ * maximum line length is CONFIG_SYS_CBSIZE including a \0 terminator, which
+ * will always be added.
+ *
+ * The command is echoed as it is typed. Command editing is supported if
+ * CONFIG_CMDLINE_EDITING is defined. Tab auto-complete is supported if
+ * CONFIG_AUTO_COMPLETE is defined. If CONFIG_BOOT_RETRY_TIME is defined,
+ * then a timeout will be applied.
+ *
+ * If CONFIG_BOOT_RETRY_TIME is defined and retry_time >= 0,
+ * time out when time goes past endtime (timebase time in ticks).
+ *
+ * @prompt: Prompt to display
+ * @buffer: Place to put the line that is entered
+ * @timeout: Timeout in milliseconds, 0 if none
+ * @return command line length excluding terminator, or -ve on error: of the
+ * timeout is exceeded (either CONFIG_BOOT_RETRY_TIME or the timeout
+ * parameter), then -2 is returned. If a break is detected (Ctrl-C) then
+ * -1 is returned.
+ */
+int cli_readline_into_buffer(const char *const prompt, char *buffer,
+ int timeout);
+
+/**
+ * parse_line() - split a command line down into separate arguments
+ *
+ * The argv[] array is filled with pointers into @line, and each argument
+ * is terminated by \0 (i.e. @line is changed in the process unless there
+ * is only one argument).
+ *
+ * #argv is terminated by a NULL after the last argument pointer.
+ *
+ * At most CONFIG_SYS_MAXARGS arguments are permited - if there are more
+ * than that then an error is printed, and this function returns
+ * CONFIG_SYS_MAXARGS, with argv[] set up to that point.
+ *
+ * @line: Command line to parse
+ * @args: Array to hold arguments
+ * @return number of arguments
+ */
+int cli_simple_parse_line(char *line, char *argv[]);
+
+#ifdef CONFIG_OF_CONTROL
+/**
+ * cli_process_fdt() - process the boot command from the FDT
+ *
+ * If bootcmmd is defined in the /config node of the FDT, we use that
+ * as the boot command. Further, if bootsecure is set to 1 (in the same
+ * node) then we return true, indicating that the command should be executed
+ * as securely as possible, avoiding the CLI parser.
+ *
+ * @cmdp: On entry, the command that will be executed if the FDT does
+ * not have a command. Returns the command to execute after
+ * checking the FDT.
+ * @return true to execute securely, else false
+ */
+bool cli_process_fdt(const char **cmdp);
+
+/** cli_secure_boot_cmd() - execute a command as securely as possible
+ *
+ * This avoids using the parser, thus executing the command with the
+ * smallest amount of code. Parameters are not supported.
+ */
+void cli_secure_boot_cmd(const char *cmd);
+#else
+static inline bool cli_process_fdt(const char **cmdp)
+{
+ return false;
+}
+
+static inline void cli_secure_boot_cmd(const char *cmd)
+{
+}
+#endif /* CONFIG_OF_CONTROL */
+
+/**
+ * Go into the command loop
+ *
+ * This will return if we get a timeout waiting for a command, but only for
+ * the simple parser (not hush). See CONFIG_BOOT_RETRY_TIME.
+ */
+void cli_loop(void);
+
+/** Set up the command line interpreter ready for action */
+void cli_init(void);
+
+#define endtick(seconds) (get_ticks() + (uint64_t)(seconds) * get_tbclk())
+
+#endif
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef _HUSH_H_
-#define _HUSH_H_
+#ifndef _CLI_HUSH_H_
+#define _CLI_HUSH_H_
#define FLAG_EXIT_FROM_LOOP 1
#define FLAG_PARSE_SEMICOLON (1 << 1) /* symbol ';' is special for parser */
#ifndef __COMMAND_H
#define __COMMAND_H
-#include <config.h>
#include <linker_lists.h>
#ifndef NULL
#include <asm/immap_512x.h>
#elif defined(CONFIG_MPC8260)
#if defined(CONFIG_MPC8247) \
- || defined(CONFIG_MPC8248) \
- || defined(CONFIG_MPC8271) \
|| defined(CONFIG_MPC8272)
#define CONFIG_MPC8272_FAMILY 1
#endif
/* common/main.c */
void main_loop (void);
int run_command(const char *cmd, int flag);
+int run_command_repeatable(const char *cmd, int flag);
/**
* Run a list of commands separated by ; or even \0
* @return 0 on success, or != 0 on error.
*/
int run_command_list(const char *cmd, int len, int flag);
-int readline (const char *const prompt);
-int readline_into_buffer(const char *const prompt, char *buffer,
- int timeout);
-int parse_line (char *, char *[]);
-void init_cmd_timeout(void);
-void reset_cmd_timeout(void);
extern char console_buffer[];
/* arch/$(ARCH)/lib/board.c */
int mac_read_from_eeprom(void);
extern u8 __dtb_dt_begin[]; /* embedded device tree blob */
int set_cpu_clk_info(void);
+int mdm_init(void);
#if defined(CONFIG_DISPLAY_CPUINFO)
int print_cpuinfo(void);
#else
#define CONFIG_SYS_HZ 1000
#endif
+#ifndef CONFIG_FIT_SIGNATURE
+#define CONFIG_IMAGE_FORMAT_LEGACY
+#endif
+
+#ifdef CONFIG_DISABLE_IMAGE_LEGACY
+#undef CONFIG_IMAGE_FORMAT_LEGACY
+#endif
+
#endif /* __CONFIG_FALLBACKS_H */
+++ /dev/null
-/*
- * Copyright (C) 2004-2005 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * Support for Analogue&Micro Adder boards family.
- * Tested on AdderII and Adder87x.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#if !defined(CONFIG_MPC875) && !defined(CONFIG_MPC852T)
-#define CONFIG_MPC875
-#endif
-
-#define CONFIG_ADDER /* Analogue&Micro Adder board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFE000000
-
-#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
-#define CONFIG_BAUDRATE 38400
-
-#define CONFIG_ETHER_ON_FEC1
-#define CONFIG_ETHER_ON_FEC2
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-
-#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
-#define CONFIG_SYS_DISCOVER_PHY
-#define CONFIG_MII_INIT 1
-#define FEC_ENET
-#endif /* CONFIG_ETHER_ON_FEC || CONFIG_ETHER_ON_FEC2 */
-
-#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
-#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
-#define CONFIG_SYS_8xx_CPUCLK_MIN 40000000
-#ifdef CONFIG_MPC852T
-#define CONFIG_SYS_8xx_CPUCLK_MAX 50000000
-#else
-#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000
-#endif /* CONFIG_MPC852T */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-
-
-#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */
-#define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */
-#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=1M(ROM)ro,-(root)"
-
-#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
-#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP /* #undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_LOAD_ADDR 0x400000 /* Default load address */
-
-/*-----------------------------------------------------------------------
- * RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero)
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_MAX_SIZE 0x01000000 /* Up to 16 Mbyte */
-
-#define CONFIG_SYS_MAMR 0x00002114
-
-/*
- * 4096 Up to 4096 SDRAM rows
- * 1000 factor s -> ms
- * 32 PTP (pre-divider from MPTPR)
- * 4 Number of refresh cycles per period
- * 64 Refresh cycle in ms per number of rows
- */
-#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */
-
-#define CONFIG_SYS_RESET_ADDRESS 0x09900000
-
-/*-----------------------------------------------------------------------
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */
-#ifdef CONFIG_BZIP2
-#define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
-#else
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
-#endif /* CONFIG_BZIP2 */
-
-/*-----------------------------------------------------------------------
- * Flash organisation
- */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max num of sects on one chip */
-
-/* Environment is in flash */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_SYS_OR0_PRELIM 0xFF000774
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V)
-
-#define CONFIG_SYS_DIRECT_FLASH_TFTP
-
-/*-----------------------------------------------------------------------
- * Internal Memory Map Register
- */
-#define CONFIG_SYS_IMMR 0xFF000000
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Configuration registers
- */
-#ifdef CONFIG_WATCHDOG
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
- SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \
- SYPCR_SWP)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
- SYPCR_SWF | SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11)
-
-/* TBSCR - Time Base Status and Control Register */
-#define CONFIG_SYS_TBSCR (TBSCR_TBF | TBSCR_TBE)
-
-/* PISCR - Periodic Interrupt Status and Control */
-#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
-
-/* PLPRCR - PLL, Low-Power, and Reset Control Register */
-/* #define CONFIG_SYS_PLPRCR PLPRCR_TEXPS */
-
-/* SCCR - System Clock and reset Control Register */
-#define SCCR_MASK SCCR_EBDF11
-#define CONFIG_SYS_SCCR SCCR_RTSEL
-
-#define CONFIG_SYS_DER 0
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx chips */
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2004
- * Yusdi Santoso, Adaptec Inc., yusdi_santoso@adaptec.com
- *
- * (C) Copyright 2001, 2002
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8245 1
-#define CONFIG_HIDDEN_DRAGON 1
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-#if 0
-#define USE_DINK32 1
-#else
-#undef USE_DINK32
-#endif
-
-#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_DRAM_SPEED 100 /* MHz */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_NET
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#undef CONFIG_PCI_PNP
-
-
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-
-#define PCI_ENET0_IOADDR 0x80000000
-#define PCI_ENET0_MEMADDR 0x80000000
-#define PCI_ENET1_IOADDR 0x81000000
-#define PCI_ENET1_MEMADDR 0x81000000
-
-#define CONFIG_RTL8139
-
-/* Make sure the ethaddr can be overwritten
- TODO: Remove this on final product
-*/
-#define CONFIG_ENV_OVERWRITE
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_MAX_RAM_SIZE 0x02000000
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-
-#if defined (USE_DINK32)
-#define CONFIG_SYS_MONITOR_LEN 0x00030000
-#define CONFIG_SYS_MONITOR_BASE 0x00090000
-#define CONFIG_SYS_RAMBOOT 1
-#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#else
-#undef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_MONITOR_LEN 0x00030000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#endif
-
-#define CONFIG_SYS_FLASH_BASE 0xFFE00000
-#define CONFIG_SYS_FLASH_SIZE (2 * 1024 * 1024) /* Unity has onboard 1MByte flash */
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
-#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
-
-#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
-
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
-
-#define CONFIG_SYS_EUMB_ADDR 0xFC000000
-
-#define CONFIG_SYS_ISA_MEM 0xFD000000
-#define CONFIG_SYS_ISA_IO 0xFE000000
-
-#define CONFIG_SYS_FLASH_RANGE_BASE 0xFFE00000 /* flash memory address range */
-#define CONFIG_SYS_FLASH_RANGE_SIZE 0x00200000
-#define FLASH_BASE0_PRELIM 0xFFE00000 /* processor board flash */
-
-/*
- * select i2c support configuration
- *
- * Supported configurations are {none, software, hardware} drivers.
- * If the software driver is chosen, there are some additional
- * configuration items that the driver uses to drive the port pins.
- */
-#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-#ifdef CONFIG_SYS_I2C_SOFT
-#error "Soft I2C is not configured properly. Please review!"
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
-#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00010000)
-#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
-#define I2C_READ ((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
- else iop->pdat &= ~0x00010000
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
- else iop->pdat &= ~0x00020000
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SYS_I2C_SOFT */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM }
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-
-/* #define CONFIG_WINBOND_83C553 1 / *has a winbond bridge */
-#define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
-#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
-#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
-
-#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
-#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
-
-/* TODO: Change this to VIA686A */
-
-/*
- * NS87308 Configuration
- */
-#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */
-
-#define CONFIG_SYS_NS87308_BADDR_10 1
-
-#define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 | \
- CONFIG_SYS_NS87308_UART2 | \
- CONFIG_SYS_NS87308_POWRMAN | \
- CONFIG_SYS_NS87308_RTC_APC )
-
-#undef CONFIG_SYS_NS87308_PS2MOD
-
-#define CONFIG_SYS_NS87308_CS0_BASE 0x0076
-#define CONFIG_SYS_NS87308_CS0_CONF 0x30
-#define CONFIG_SYS_NS87308_CS1_BASE 0x0075
-#define CONFIG_SYS_NS87308_CS1_CONF 0x30
-#define CONFIG_SYS_NS87308_CS2_BASE 0x0074
-#define CONFIG_SYS_NS87308_CS2_CONF 0x30
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-
-#if (CONFIG_CONS_INDEX > 2)
-#define CONFIG_SYS_NS16550_CLK CONFIG_DRAM_SPEED*1000000
-#else
-#define CONFIG_SYS_NS16550_CLK 1843200
-#endif
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_EUMB_ADDR + 0x4500)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_EUMB_ADDR + 0x4600)
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-
-#define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */
-#define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */
-
-#define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */
-
-/* the following are for SDRAM only*/
-#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
-#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
-#define CONFIG_SYS_RDLAT 4 /* data latency from read command */
-#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
-#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
-#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
-#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
-#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
-#if 0
-#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
-#endif
-
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-#define CONFIG_SYS_EXTROM 1
-#define CONFIG_SYS_REGDIMM 0
-
-
-/* memory bank settings*/
-/*
- * only bits 20-29 are actually used from these vales to set the
- * start/end address the upper two bits will be 0, and the lower 20
- * bits will be set to 0x00000 for a start address, or 0xfffff for an
- * end address
- */
-#define CONFIG_SYS_BANK0_START 0x00000000
-#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
-#define CONFIG_SYS_BANK0_ENABLE 1
-#define CONFIG_SYS_BANK1_START 0x3ff00000
-#define CONFIG_SYS_BANK1_END 0x3fffffff
-#define CONFIG_SYS_BANK1_ENABLE 0
-#define CONFIG_SYS_BANK2_START 0x3ff00000
-#define CONFIG_SYS_BANK2_END 0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE 0
-#define CONFIG_SYS_BANK3_START 0x3ff00000
-#define CONFIG_SYS_BANK3_END 0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE 0
-#define CONFIG_SYS_BANK4_START 0x00000000
-#define CONFIG_SYS_BANK4_END 0x00000000
-#define CONFIG_SYS_BANK4_ENABLE 0
-#define CONFIG_SYS_BANK5_START 0x00000000
-#define CONFIG_SYS_BANK5_END 0x00000000
-#define CONFIG_SYS_BANK5_ENABLE 0
-#define CONFIG_SYS_BANK6_START 0x00000000
-#define CONFIG_SYS_BANK6_END 0x00000000
-#define CONFIG_SYS_BANK6_ENABLE 0
-#define CONFIG_SYS_BANK7_START 0x00000000
-#define CONFIG_SYS_BANK7_END 0x00000000
-#define CONFIG_SYS_BANK7_ENABLE 0
-/*
- * Memory bank enable bitmask, specifying which of the banks defined above
- are actually present. MSB is for bank #7, LSB is for bank #0.
- */
-#define CONFIG_SYS_BANK_ENABLE 0x01
-
-#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */
- /* see 8240 book for bit definitions */
-#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
- /* currently accessed page in memory */
- /* see 8240 book for details */
-
-/* SDRAM 0 - 256MB */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* stack in DCACHE @ 1GB (no backing mem) */
-#if defined(USE_DINK32)
-#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 )
-#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K )
-#else
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#endif
-
-/* PCI memory */
-#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* Flash, config addrs, etc */
-#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 36 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/* values according to the manual */
-#define CONFIG_DRAM_50MHZ 1
-#define CONFIG_SDRAM_50MHZ
-
-#undef NR_8259_INTS
-#define NR_8259_INTS 1
-
-#define CONFIG_DISK_SPINUP_TIME 1000000
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Copyright (C) 2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * Support for Interphase iSPAN Communications Controllers
- * (453x and others). Tested on 4532.
- *
- * Derived from iSPAN 4539 port (iphase4539) by
- * Wolfgang Grandegger <wg@denx.de>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_ISPAN /* ...on one of Interphase iSPAN boards */
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-#define CONFIG_SYS_TEXT_BASE 0xFE7A0000
-
-/*-----------------------------------------------------------------------
- * Select serial console configuration
- *
- * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * If CONFIG_CONS_NONE is defined, then the serial console routines must be
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#define CONFIG_CONS_ON_SMC /* Define if console on SMC */
-#undef CONFIG_CONS_ON_SCC /* Define if console on SCC */
-#undef CONFIG_CONS_NONE /* Define if console on something else */
-#define CONFIG_CONS_INDEX 1 /* Which serial channel for console */
-
-/*-----------------------------------------------------------------------
- * Select Ethernet configuration
- *
- * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC).
- *
- * If CONFIG_ETHER_NONE is defined, then either the Ethernet routines must
- * be defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef CONFIG_ETHER_ON_SCC /* Define if Ethernet on SCC */
-#define CONFIG_ETHER_ON_FCC /* Define if Ethernet on FCC */
-#undef CONFIG_ETHER_NONE /* Define if Ethernet on something else */
-#define CONFIG_ETHER_INDEX 3 /* Which channel for Ethernrt */
-
-#ifdef CONFIG_ETHER_ON_FCC
-
-#if CONFIG_ETHER_INDEX == 3
-
-#define CONFIG_SYS_PHY_ADDR 0
-#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
-#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
-
-#endif /* CONFIG_ETHER_INDEX == 3 */
-
-#define CONFIG_SYS_CPMFCR_RAMTYPE 0
-#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_BITBANGMII /* Bit-bang MII PHY management */
-/*
- * GPIO pins used for bit-banged MII communications
- */
-#define MDIO_PORT 3 /* Port D */
-#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-#define MDC_DECLARE MDIO_DECLARE
-
-
-#define CONFIG_SYS_MDIO_PIN 0x00040000 /* PD13 */
-#define CONFIG_SYS_MDC_PIN 0x00080000 /* PD12 */
-
-#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
-#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
-#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
-
-#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
- else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
-
-#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
- else iop->pdat &= ~CONFIG_SYS_MDC_PIN
-
-#define MIIDELAY udelay(1)
-
-#endif /* CONFIG_ETHER_ON_FCC */
-
-#define CONFIG_8260_CLKIN 65536000 /* in Hz */
-#define CONFIG_BAUDRATE 38400
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_BOOTCOMMAND "bootm fe010000" /* autoboot command */
-#define CONFIG_BOOTARGS "root=/dev/ram rw"
-
-#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */
-#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP /* #undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x03B00000 /* 1 ... 59 MB in SDRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* Default load address */
-
-#define CONFIG_SYS_RESET_ADDRESS 0x09900000
-
-#define CONFIG_MISC_INIT_R /* We need misc_init_r() */
-
-/*-----------------------------------------------------------------------
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
-#ifdef CONFIG_BZIP2
-#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
-#else
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
-#endif /* CONFIG_BZIP2 */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_BASE 0xFE000000
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 142 /* Max num of sects on one chip */
-
-/* Environment is in flash, there is little space left in Serial EEPROM */
-#define CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
-#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
-
-/*-----------------------------------------------------------------------
- * Hard Reset Configuration Words
- *
- * If you change bits in the HRCW, you must also change the CONFIG_SYS_*
- * defines for the various registers affected by the HRCW e.g. changing
- * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
- */
-/* 0x1686B245 */
-#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM | HRCW_BPS01 | HRCW_CIP |\
- HRCW_L2CPC10 | HRCW_ISB110 |\
- HRCW_BMS | HRCW_MMR11 | HRCW_APPC10 |\
- HRCW_CS10PC01 | HRCW_MODCK_H0101 \
- )
-/* No slaves */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-/*-----------------------------------------------------------------------
- * Internal Memory Mapped Register
- */
-#define CONFIG_SYS_IMMR 0xF0F00000
-#ifdef CONFIG_SYS_REV_B
-#define CONFIG_SYS_DEFAULT_IMMR 0xFF000000
-#endif /* CONFIG_SYS_REV_B */
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-
-/*-----------------------------------------------------------------------
- * HIDx - Hardware Implementation-dependent Registers 2-11
- *-----------------------------------------------------------------------
- * HID0 also contains cache control.
- *
- * HID1 has only read-only information - nothing to set.
- */
-#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
- HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE)
-#define CONFIG_SYS_HID2 0
-
-/*-----------------------------------------------------------------------
- * RMR - Reset Mode Register 5-5
- *-----------------------------------------------------------------------
- * turn on Checkstop Reset Enable
- */
-#define CONFIG_SYS_RMR RMR_CSRE
-
-/*-----------------------------------------------------------------------
- * BCR - Bus Configuration 4-25
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_BCR 0xA01C0000
-
-/*-----------------------------------------------------------------------
- * SIUMCR - SIU Module Configuration 4-31
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_SIUMCR 0x42250000/* 0x4205C000 */
-
-/*-----------------------------------------------------------------------
- * SYPCR - System Protection Control 4-35
- * SYPCR can only be written once after reset!
- *-----------------------------------------------------------------------
- * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
- */
-#if defined (CONFIG_WATCHDOG)
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
-#else
-#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
- SYPCR_SWRI|SYPCR_SWP)
-#endif /* CONFIG_WATCHDOG */
-
-/*-----------------------------------------------------------------------
- * TMCNTSC - Time Counter Status and Control 4-40
- * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
- * and enable Time Counter
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-
-/*-----------------------------------------------------------------------
- * PISCR - Periodic Interrupt Status and Control 4-42
- *-----------------------------------------------------------------------
- * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
- * Periodic timer
- */
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-
-/*-----------------------------------------------------------------------
- * SCCR - System Clock Control 9-8
- *-----------------------------------------------------------------------
- * Ensure DFBRG is Divide by 16
- */
-#define CONFIG_SYS_SCCR SCCR_DFBRG01
-
-/*-----------------------------------------------------------------------
- * RCCR - RISC Controller Configuration 13-7
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_RCCR 0
-
-/*-----------------------------------------------------------------------
- * Init Memory Controller:
- *
- * Bank Bus Machine PortSize Device
- * ---- --- ------- ----------------------------- ------
- * 0 60x GPCM 8 bit (Rev.B)/16 bit (Rev.D) Flash
- * 1 60x SDRAM 64 bit SDRAM
- * 2 Local SDRAM 32 bit SDRAM
- */
-#define CONFIG_SYS_USE_FIRMWARE /* If defined - do not initialise memory
- controller, rely on initialisation
- performed by the Interphase boot firmware.
- */
-
-#define CONFIG_SYS_OR0_PRELIM 0xFE000882
-#ifdef CONFIG_SYS_REV_B
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BRx_PS_8 | BRx_V)
-#else /* Rev. D */
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BRx_PS_16 | BRx_V)
-#endif /* CONFIG_SYS_REV_B */
-
-#define CONFIG_SYS_MPTPR 0x7F00
-
-/* Please note that 60x SDRAM MUST start at 0 */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_60x_BR 0x00000041
-#define CONFIG_SYS_60x_OR 0xF0002CD0
-#define CONFIG_SYS_PSDMR 0x0049929A
-#define CONFIG_SYS_PSRT 0x07
-
-#define CONFIG_SYS_LSDRAM_BASE 0xF7000000
-#define CONFIG_SYS_LOC_BR 0x00001861
-#define CONFIG_SYS_LOC_OR 0xFF803280
-#define CONFIG_SYS_LSDMR 0x8285A552
-#define CONFIG_SYS_LSRT 0x07
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2001
- * Stuart Hughes <stuarth@lineo.com>
- * This file is based on similar values for other boards found in other
- * U-Boot config files, and some that I found in the mpc8260ads manual.
- *
- * Note: my board is a PILOT rev.
- * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address.
- *
- * (C) Copyright 2003-2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- * Added support for SDRAM DIMMs SPD EEPROM, MII, JFFS2.
- * Ported to PQ2FADS-ZU and PQ2FADS-VR boards.
- * Ported to MPC8272ADS board.
- *
- * Copyright (c) 2005 MontaVista Software, Inc.
- * Vitaly Bordug <vbordug@ru.mvista.com>
- * Added support for PCI bridge on MPC8272ADS
- *
- * Copyright (C) Freescale Semiconductor, Inc. 2006-2009.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8260ADS 1 /* Motorola PQ2 ADS family board */
-
-#ifndef CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */
-#endif
-
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-/*
- * Figure out if we are booting low via flash HRCW or high via the BCSR.
- */
-#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */
-# define CONFIG_SYS_LOWBOOT 1
-#endif
-
-/* ADS flavours */
-#define CONFIG_SYS_8260ADS 1 /* MPC8260ADS */
-#define CONFIG_SYS_8266ADS 2 /* MPC8266ADS */
-#define CONFIG_SYS_PQ2FADS 3 /* PQ2FADS-ZU or PQ2FADS-VR */
-#define CONFIG_SYS_8272ADS 4 /* MPC8272ADS */
-
-#ifndef CONFIG_ADSTYPE
-#define CONFIG_ADSTYPE CONFIG_SYS_8260ADS
-#endif /* CONFIG_ADSTYPE */
-
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
-#define CONFIG_MPC8272 1
-#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
-/*
- * Actually MPC8275, but the code is littered with ifdefs that
- * apply to both, or which use this ifdef to assume board-specific
- * details. :-(
- */
-#define CONFIG_MPC8272 1
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
-
-/* allow serial and ethaddr to be overwritten */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * select serial console configuration
- *
- * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- *
- * if CONFIG_CONS_NONE is defined, then the serial console routines must
- * defined elsewhere (for example, on the cogent platform, there are serial
- * ports on the motherboard which are used for the serial console - see
- * cogent/cma101/serial.[ch]).
- */
-#undef CONFIG_CONS_ON_SMC /* define if console on SMC */
-#define CONFIG_CONS_ON_SCC /* define if console on SCC */
-#undef CONFIG_CONS_NONE /* define if console on something else */
-#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
-
-/*
- * select ethernet configuration
- *
- * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
- * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
- * for FCC)
- *
- * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
- */
-#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
-#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
-#undef CONFIG_ETHER_NONE /* define if ether on something else */
-
-#ifdef CONFIG_ETHER_ON_FCC
-
-#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
-
-#if CONFIG_ETHER_INDEX == 1
-
-# define CONFIG_SYS_PHY_ADDR 0
-# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
-# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
-
-#elif CONFIG_ETHER_INDEX == 2
-
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS /* RxCLK is CLK15, TxCLK is CLK16 */
-# define CONFIG_SYS_PHY_ADDR 3
-# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16)
-#else /* RxCLK is CLK13, TxCLK is CLK14 */
-# define CONFIG_SYS_PHY_ADDR 0
-# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
-
-# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-
-#endif /* CONFIG_ETHER_INDEX */
-
-#define CONFIG_SYS_CPMFCR_RAMTYPE 0 /* BDs and buffers on 60x bus */
-#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) /* Full duplex */
-
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
-/*
- * GPIO pins used for bit-banged MII communications
- */
-#define MDIO_PORT 2 /* Port C */
-#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-#define MDC_DECLARE MDIO_DECLARE
-
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
-#define CONFIG_SYS_MDIO_PIN 0x00002000 /* PC18 */
-#define CONFIG_SYS_MDC_PIN 0x00001000 /* PC19 */
-#else
-#define CONFIG_SYS_MDIO_PIN 0x00400000 /* PC9 */
-#define CONFIG_SYS_MDC_PIN 0x00200000 /* PC10 */
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
-
-#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
-#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
-#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
-
-#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
- else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
-
-#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
- else iop->pdat &= ~CONFIG_SYS_MDC_PIN
-
-#define MIIDELAY udelay(1)
-
-#endif /* CONFIG_ETHER_ON_FCC */
-
-#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
-#undef CONFIG_SPD_EEPROM /* On new boards, SDRAM is soldered */
-#else
-#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-#if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR)
-#define CONFIG_SPD_ADDR 0x50
-#endif
-#endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
-
-/*PCI*/
-#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
-#define CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_PNP
-#define CONFIG_PCI_BOOTDELAY 0
-#define CONFIG_PCI_SCAN_SHOW
-#endif
-
-#ifndef CONFIG_SDRAM_PBI
-#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */
-#endif
-
-#ifndef CONFIG_8260_CLKIN
-#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
-#define CONFIG_8260_CLKIN 100000000 /* in Hz */
-#else
-#define CONFIG_8260_CLKIN 66000000 /* in Hz */
-#endif
-#endif
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#if defined(CONFIG_OF_LIBFDT)
-#define OF_TBCLK (bd->bi_busfreq / 4)
-#endif
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_CDP
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_PORTIO
-#define CONFIG_CMD_REGINFO
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_SDRAM
-
-#undef CONFIG_CMD_XIMG
-
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
- #undef CONFIG_CMD_SDRAM
- #undef CONFIG_CMD_I2C
-
-#elif CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
- #undef CONFIG_CMD_SDRAM
- #undef CONFIG_CMD_I2C
-
-#else
- #undef CONFIG_CMD_PCI
-
-#endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */
-
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */
-#define CONFIG_BOOTARGS "root=/dev/mtdblock2"
-
-#if defined(CONFIG_CMD_KGDB)
-#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
-#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
-#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
-#endif
-
-#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
-#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_SYS_FLASH_BASE 0xff800000
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */
-#define CONFIG_SYS_FLASH_SIZE 8
-#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
-#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
-
-/*
- * JFFS2 partitions
- *
- * Note: fake mtd_id used, no linux mtd map file
- */
-#define MTDIDS_DEFAULT "nor0=mpc8260ads-0"
-#define MTDPARTS_DEFAULT "mtdparts=mpc8260ads-0:-@1m(jffs2)"
-#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
-
-/* this is stuff came out of the Motorola docs */
-#ifndef CONFIG_SYS_LOWBOOT
-#define CONFIG_SYS_DEFAULT_IMMR 0x0F010000
-#endif
-
-#define CONFIG_SYS_IMMR 0xF0000000
-#define CONFIG_SYS_BCSR 0xF4500000
-#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
-#define CONFIG_SYS_PCI_INT 0xF8200000
-#endif
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_LSDRAM_BASE 0xFD000000
-
-#define RS232EN_1 0x02000002
-#define RS232EN_2 0x01000001
-#define FETHIEN1 0x08000008
-#define FETH1_RST 0x04000004
-#define FETHIEN2 0x10000000
-#define FETH2_RST 0x08000000
-#define BCSR_PCI_MODE 0x01000000
-
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#ifdef CONFIG_SYS_LOWBOOT
-/* PQ2FADS flash HRCW = 0x0EB4B645 */
-#define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
- ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 ) |\
- ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\
- ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
- )
-#else
-/* PQ2FADS BCSR HRCW = 0x0CB23645 */
-#define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\
- ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\
- ( HRCW_BMS | HRCW_APPC10 ) |\
- ( HRCW_MODCK_H0101 ) \
- )
-#endif
-/* no slaves */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-# define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#ifdef CONFIG_BZIP2
-#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
-#else
-#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */
-#endif /* CONFIG_BZIP2 */
-
-#ifndef CONFIG_SYS_RAMBOOT
-# define CONFIG_ENV_IS_IN_FLASH 1
-# define CONFIG_ENV_SECT_SIZE 0x40000
-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_ENV_SECT_SIZE)
-#else
-# define CONFIG_ENV_IS_IN_NVRAM 1
-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
-# define CONFIG_ENV_SIZE 0x200
-#endif /* CONFIG_SYS_RAMBOOT */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE )
-
-#define CONFIG_SYS_HID2 0
-
-#define CONFIG_SYS_SYPCR 0xFFFFFFC3
-#define CONFIG_SYS_BCR 0x100C0000
-#define CONFIG_SYS_SIUMCR 0x0A200000
-#define CONFIG_SYS_SCCR SCCR_DFBRG01
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801)
-#define CONFIG_SYS_OR0_PRELIM 0xFF800876
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00001801)
-#define CONFIG_SYS_OR1_PRELIM 0xFFFF8010
-
-/*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/
-
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
-#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
-#define CONFIG_SYS_OR3_PRELIM 0xFFFF8010
-#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
-#define CONFIG_SYS_BR8_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */
-#define CONFIG_SYS_OR8_PRELIM 0xFFFF8010
-#endif
-
-#define CONFIG_SYS_RMR RMR_CSRE
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-#define CONFIG_SYS_RCCR 0
-
-#if (CONFIG_ADSTYPE == CONFIG_SYS_8266ADS) || (CONFIG_ADSTYPE == CONFIG_SYS_8272ADS)
-#undef CONFIG_SYS_LSDRAM_BASE /* No local bus SDRAM on these boards */
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8266ADS */
-
-#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
-#define CONFIG_SYS_OR2 0xFE002EC0
-#define CONFIG_SYS_PSDMR 0x824B36A3
-#define CONFIG_SYS_PSRT 0x13
-#define CONFIG_SYS_LSDMR 0x828737A3
-#define CONFIG_SYS_LSRT 0x13
-#define CONFIG_SYS_MPTPR 0x2800
-#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
-#define CONFIG_SYS_OR2 0xFC002CC0
-#define CONFIG_SYS_PSDMR 0x834E24A3
-#define CONFIG_SYS_PSRT 0x13
-#define CONFIG_SYS_MPTPR 0x2800
-#else
-#define CONFIG_SYS_OR2 0xFF000CA0
-#define CONFIG_SYS_PSDMR 0x016EB452
-#define CONFIG_SYS_PSRT 0x21
-#define CONFIG_SYS_LSDMR 0x0086A522
-#define CONFIG_SYS_LSRT 0x21
-#define CONFIG_SYS_MPTPR 0x1900
-#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
-
-#define CONFIG_SYS_RESET_ADDRESS 0x04400000
-
-#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
-
-/* PCI Memory map (if different from default map */
-#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */
-#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */
-#define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \
- PICMR_PREFETCH_EN)
-
-/*
- * These are the windows that allow the CPU to access PCI address space.
- * All three PCI master windows, which allow the CPU to access PCI
- * prefetch, non prefetch, and IO space (see below), must all fit within
- * these windows.
- */
-
-/*
- * Master window that allows the CPU to access PCI Memory (prefetch).
- * This window will be setup with the second set of Outbound ATU registers
- * in the bridge.
- */
-
-#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */
-#define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */
-#define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL
-#define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */
-#define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN)
-
-/*
- * Master window that allows the CPU to access PCI Memory (non-prefetch).
- * This window will be setup with the second set of Outbound ATU registers
- * in the bridge.
- */
-
-#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */
-#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */
-#define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL
-#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */
-#define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE)
-
-/*
- * Master window that allows the CPU to access PCI IO space.
- * This window will be setup with the first set of Outbound ATU registers
- * in the bridge.
- */
-
-#define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */
-#define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */
-#define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL
-#define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */
-#define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO)
-
-
-/* PCIBR0 - for PCI IO*/
-#define CONFIG_SYS_PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL /* Local base */
-#define CONFIG_SYS_PCIMSK0_MASK ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U) /* Size of window */
-/* PCIBR1 - prefetch and non-prefetch regions joined together */
-#define CONFIG_SYS_PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL
-#define CONFIG_SYS_PCIMSK1_MASK ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U)
-
-#endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/
-
-#define CONFIG_HAS_ETH0
-
-#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
-#define CONFIG_HAS_ETH1
-#endif
-
-#define CONFIG_NETDEV eth0
-#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" __stringify(CONFIG_NETDEV) "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
- "fdtaddr=400000\0" \
- "console=ttyCPM0\0" \
- "setbootargs=setenv bootargs " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
- "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv rootdev /dev/nfs;" \
- "run setipargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv rootdev /dev/ram;" \
- "run setbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#endif /* __CONFIG_H */
#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
-#ifdef CONFIG_NAND_U_BOOT
-#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
-#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
-#endif /* CONFIG_NAND_SPL */
-#endif /* CONFIG_NAND_U_BOOT */
-
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xFE000000
#endif
*/
#define CONFIG_SYS_IMMR 0xE0000000
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
-#endif
-
/*
* Arbiter Setup
*/
| OR_FCM_EHTR)
/* 0xFFFF8396 */
-#ifdef CONFIG_NAND_U_BOOT
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
-#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
-#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
-#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
-#endif
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
/*
* Environment
*/
-#if defined(CONFIG_NAND_U_BOOT)
- #define CONFIG_ENV_IS_IN_NAND 1
- #define CONFIG_ENV_OFFSET (512 * 1024)
- #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
- #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
- #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
- #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
- #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + \
- CONFIG_ENV_RANGE)
-#elif !defined(CONFIG_SYS_RAMBOOT)
+#if !defined(CONFIG_SYS_RAMBOOT)
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR \
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_CMD_DATE
#define CONFIG_CMD_PCI
-#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
#undef CONFIG_CMD_SAVEENV
#undef CONFIG_CMD_LOADS
#endif
#define CONFIG_PHYS_64BIT 1
#endif
-#ifdef CONFIG_NAND
-#define CONFIG_NAND_U_BOOT 1
-#define CONFIG_RAMBOOT_NAND 1
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
-#else
-#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
-#define CONFIG_SYS_TEXT_BASE 0xf8f82000
-#endif /* CONFIG_NAND_SPL */
-#endif
-
#ifdef CONFIG_SDCARD
#define CONFIG_RAMBOOT_SDCARD 1
#define CONFIG_SYS_TEXT_BASE 0xf8f40000
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#if defined(CONFIG_RAMBOOT_NAND) || defined(CONFIG_RAMBOOT_SDCARD) || \
- defined(CONFIG_RAMBOOT_SPIFLASH)
+#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#else
| OR_FCM_TRLX \
| OR_FCM_EHTR)
-#ifdef CONFIG_RAMBOOT_NAND
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
#define CONFIG_SYS_BR4_PRELIM \
(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
*/
#if defined(CONFIG_SYS_RAMBOOT)
-#if defined(CONFIG_RAMBOOT_NAND)
-#define CONFIG_ENV_IS_IN_NAND 1
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
-#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
-#elif defined(CONFIG_RAMBOOT_SPIFLASH)
+#if defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_L2_CACHE /* toggle L2 cache */
#define CONFIG_BTB /* toggle branch predition */
-#ifdef CONFIG_NAND
-#define CONFIG_NAND_U_BOOT 1
-#define CONFIG_RAMBOOT_NAND 1
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
-#else
-#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
-#define CONFIG_SYS_TEXT_BASE 0xf8f82000
-#endif
-#endif
-
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xfff80000
#endif
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#if defined(CONFIG_RAMBOOT_NAND)
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#else
#undef CONFIG_SYS_RAMBOOT
-#endif
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
| OR_FCM_TRLX \
| OR_FCM_EHTR)
-#ifdef CONFIG_RAMBOOT_NAND
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM/* NAND Options */
-#define CONFIG_SYS_BR3_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR3_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
#define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */
* Environment
*/
#if defined(CONFIG_SYS_RAMBOOT)
-#if defined(CONFIG_RAMBOOT_NAND)
-#define CONFIG_ENV_IS_IN_NAND 1
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
-#endif
#else
#define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_PHYS_64BIT
#endif
-#ifdef CONFIG_NAND
-#define CONFIG_NAND_U_BOOT
-#define CONFIG_RAMBOOT_NAND
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
-#else
-#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
-#define CONFIG_SYS_TEXT_BASE 0xf8f82000
-#endif /* CONFIG_NAND_SPL */
-#endif
-
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#if defined(CONFIG_RAMBOOT_NAND)
-#define CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_EXTRA_ENV_RELOC
-#else
#undef CONFIG_SYS_RAMBOOT
-#endif
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
| OR_FCM_TRLX \
| OR_FCM_EHTR)
-#ifdef CONFIG_RAMBOOT_NAND
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
-#define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
-#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-#endif
#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
*/
#if defined(CONFIG_SYS_RAMBOOT)
-#if defined(CONFIG_RAMBOOT_NAND)
-#define CONFIG_ENV_IS_IN_NAND 1
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET ((512 * 1024)\
- + CONFIG_SYS_NAND_BLOCK_SIZE)
-#endif
#else
#define CONFIG_ENV_IS_IN_FLASH 1
#ifndef __CONFIG_H
#define __CONFIG_H
-#ifdef CONFIG_NAND
-#define CONFIG_NAND_U_BOOT
-#define CONFIG_RAMBOOT_NAND
-#endif
-
-#ifdef CONFIG_NAND_U_BOOT
-#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
-#define CONFIG_SYS_TEXT_BASE 0x11001000
-
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
-#else
-#define CONFIG_SYS_LDSCRIPT $(CPUDIR)/u-boot-nand.lds
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif /* CONFIG_NAND_SPL */
-#endif
-
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0xeff40000
#endif
#define CONFIG_SYS_BCSR_BASE 0xe0000000 /* start of on board FPGA */
#define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE
-#ifndef CONFIG_NAND
#define CONFIG_SYS_FLASH_BASE 0xee000000 /* start of FLASH 32M */
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
-#else
-#define CONFIG_SYS_NO_FLASH
-#endif
-#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
+#if defined(CONFIG_SYS_SPL)
#define CONFIG_SYS_RAMBOOT
#endif
| OR_FCM_TRLX \
| OR_FCM_EHTR)
-#ifdef CONFIG_RAMBOOT_NAND
-/* NAND Base Address */
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
-/* chip select 1 - BCSR */
-#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_BCSR_BASE_PHYS) \
- | BR_MS_GPCM | BR_PS_8 | BR_V)
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
- | OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
- | OR_GPCM_EAD)
-#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
/* chip select 1 - BCSR */
#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB | OR_GPCM_CSNT | OR_GPCM_XACS \
| OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR \
| OR_GPCM_EAD)
-#endif
/* Serial Port
* open - index 2
#define CONFIG_ENV_OVERWRITE
#if defined(CONFIG_SYS_RAMBOOT)
-#if defined(CONFIG_RAMBOOT_NAND)
-#define CONFIG_ENV_IS_IN_NAND
-#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
-#define CONFIG_ENV_OFFSET ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
-#else
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x4000)
#define CONFIG_ENV_SIZE 0x2000
-#endif
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_PHY_MARVELL
#endif
-#ifndef CONFIG_NAND
/* Default address of microcode for the Linux Fman driver */
/* QE microcode/firmware address */
#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
-#else
-#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
-#define CONFIG_SYS_FMAN_FW_ADDR 0x1f00000
-#endif
#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+++ /dev/null
-/*
- * Copyright (C) 2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * U-Boot configuration for Analogue&Micro Rattler boards.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#ifdef CONFIG_MPC8248
-#define CPU_ID_STR "MPC8248"
-#else
-#define CPU_ID_STR "MPC8250"
-#endif /* CONFIG_MPC8248 */
-
-#define CONFIG_SYS_TEXT_BASE 0xFE000000
-
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-#define CONFIG_RATTLER /* Analogue&Micro Rattler board */
-
-/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * Select serial console configuration
- *
- * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- */
-#define CONFIG_CONS_ON_SMC /* Console is on SMC */
-#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
-#undef CONFIG_CONS_NONE /* It's not on external UART */
-#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
-
-/*
- * Select ethernet configuration
- *
- * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
- * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
- * SCC, 1-3 for FCC)
- *
- * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
- * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
- * must be unset.
- */
-#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
-#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
-#undef CONFIG_ETHER_NONE /* No external Ethernet */
-
-#ifdef CONFIG_ETHER_ON_FCC
-
-#define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */
-
-#if (CONFIG_ETHER_INDEX == 1)
-
-/* - Rx clock is CLK11
- * - Tx clock is CLK10
- * - BDs/buffers on 60x bus
- * - Full duplex
- */
-#define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
-#define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10)
-#define CONFIG_SYS_CPMFCR_RAMTYPE 0
-#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#elif (CONFIG_ETHER_INDEX == 2)
-
-/* - Rx clock is CLK15
- * - Tx clock is CLK14
- * - BDs/buffers on 60x bus
- * - Full duplex
- */
-#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK14)
-#define CONFIG_SYS_CPMFCR_RAMTYPE 0
-#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_INDEX */
-
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
-/*
- * GPIO pins used for bit-banged MII communications
- */
-#define MDIO_PORT 2 /* Port C */
-#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-#define MDC_DECLARE MDIO_DECLARE
-
-#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
-#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
-#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
-
-#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
- else iop->pdat &= ~0x00400000
-
-#define MDC(bit) if(bit) iop->pdat |= 0x00800000; \
- else iop->pdat &= ~0x00800000
-
-#define MIIDELAY udelay(1)
-
-#endif /* CONFIG_ETHER_ON_FCC */
-
-#ifndef CONFIG_8260_CLKIN
-#define CONFIG_8260_CLKIN 100000000 /* in Hz */
-#endif
-
-#define CONFIG_BAUDRATE 38400
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_BOOTCOMMAND "bootm FE040000" /* autoboot command */
-#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw mtdparts=phys:1M(ROM)ro,-(root)"
-
-#if defined(CONFIG_CMD_KGDB)
-#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
-#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
-#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
-#endif
-
-#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
-#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_SYS_FLASH_BASE 0xFE000000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
-
-#define CONFIG_SYS_DIRECT_FLASH_TFTP
-
-#if defined(CONFIG_CMD_JFFS2)
-#define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS
-#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00100000
-
-/* mtdparts command line support */
-/* Note: fake mtd_id used, no linux mtd map file */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor0=rattler-0"
-#define MTDPARTS_DEFAULT "mtdparts=rattler-0:-@1m(jffs2)"
-*/
-#endif /* CONFIG_CMD_JFFS2 */
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-
-#define CONFIG_ENV_IS_IN_FLASH
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x10000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-#define CONFIG_SYS_DEFAULT_IMMR 0xFF010000
-
-#define CONFIG_SYS_IMMR 0xF0000000
-
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 32
-#define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00000041)
-#define CONFIG_SYS_SDRAM_OR 0xFE002EC0
-
-#define CONFIG_SYS_BCSR 0xFC000000
-
-/* Hard reset configuration word */
-#define CONFIG_SYS_HRCW_MASTER 0x0A06875A /* Not used - provided by FPGA */
-/* No slaves */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
-
-#define CONFIG_SYS_HID2 0
-
-#define CONFIG_SYS_SIUMCR 0x0E04C000
-#define CONFIG_SYS_SYPCR 0xFFFFFFC3
-#define CONFIG_SYS_BCR 0x00000000
-#define CONFIG_SYS_SCCR SCCR_DFBRG01
-
-#define CONFIG_SYS_RMR RMR_CSRE
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-#define CONFIG_SYS_RCCR 0
-
-#define CONFIG_SYS_PSDMR 0x8249A452
-#define CONFIG_SYS_PSRT 0x1F
-#define CONFIG_SYS_MPTPR 0x2000
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001001)
-#define CONFIG_SYS_OR0_PRELIM 0xFF001ED6
-#define CONFIG_SYS_BR7_PRELIM (CONFIG_SYS_BCSR | 0x00000801)
-#define CONFIG_SYS_OR7_PRELIM 0xFFFF87F6
-
-#define CONFIG_SYS_RESET_ADDRESS 0xC0000000
-
-#endif /* __CONFIG_H */
+++ /dev/null
-/*
- * Copyright (C) Sheldon Instruments, Inc. 2008
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-/*
- * simpc8313 board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- */
-#define CONFIG_NAND_U_BOOT
-
-#define CONFIG_E300 1
-#define CONFIG_MPC831x 1
-#define CONFIG_MPC8313 1
-
-#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
-#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
-#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
-#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
-#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
-
-#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
-#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
-
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
-#else
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-#endif
-
-#define CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_FSL_ELBC 1
-
-#define CONFIG_MISC_INIT_R
-
-/*
- * On-board devices
- *
- * TSEC1 is Marvell PHY 88E1118
- */
-
-#define CONFIG_SYS_33MHZ
-
-#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
-
-#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
-
-#define CONFIG_SYS_IMMR 0xE0000000
-
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
-#endif
-
-#define CONFIG_SYS_MEMTEST_START 0x00001000
-#define CONFIG_SYS_MEMTEST_END 0x07f00000
-
-#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
-#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
-
-/*
- * Device configurations
- */
-#define CONFIG_TSEC1
-
-/*
- * DDR Setup
- */
- /* DDR is system memory*/
-#define CONFIG_SYS_DDR_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
-
-#define CONFIG_VERY_BIG_RAM
-#define CONFIG_MAX_MEM_MAPPED (512 << 20)
-
-#define CONFIG_SYS_DDRCDR (DDRCDR_EN \
- | DDRCDR_PZ_NOMZ \
- | DDRCDR_NZ_NOMZ \
- | DDRCDR_M_ODR)
- /* 0x73000002 TODO ODR & DRN ? */
-
-/*
- * FLASH on the Local Bus
- */
-#define CONFIG_SYS_NO_FLASH
-
-#if !defined(CONFIG_NAND_SPL)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET \
- (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
-
-/*
- * Local Bus LCRR and LBCR regs
- */
-#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
-#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
-#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
- | (0xFF << LBCR_BMT_SHIFT) \
- | 0xF) /* 0x0004ff0f */
-
- /* LB refresh timer prescal, 266MHz/32 */
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-
-/* drivers/mtd/nand/nand.c */
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_SYS_NAND_BASE 0xFFF00000
-#else
-#define CONFIG_SYS_NAND_BASE 0xE2800000
-#endif
-#define CONFIG_SYS_FPGA_BASE 0xFF000000
-
-#define CONFIG_CMD_NAND
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-#define CONFIG_MTD_NAND_VERIFY_WRITE
-#define CONFIG_NAND_FSL_ELBC 1
-
-#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
- | BR_DECC_CHK_GEN /* Use HW ECC */ \
- | BR_PS_8 /* 8 bit Port */ \
- | BR_MS_FCM /* MSEL = FCM */ \
- | BR_V) /* valid */
-
-#ifdef CONFIG_NAND_SP
-#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
-#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
- /* NAND chip block size */
-#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10)
-#define NAND_CACHE_PAGES 32
-#elif defined(CONFIG_NAND_LP)
-#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB \
- | OR_FCM_PGS \
- | OR_FCM_CSCT \
- | OR_FCM_CST \
- | OR_FCM_CHT \
- | OR_FCM_SCY_1 \
- | OR_FCM_TRLX \
- | OR_FCM_EHTR)
-#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
-#define CONFIG_SYS_NAND_PAGE_SIZE 2048 /* NAND chip page size */
- /* NAND chip block size */
-#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
-#define NAND_CACHE_PAGES 64
-#else
-#error Page size of NAND not defined.
-#endif /* CONFIG_NAND_SP */
-
-#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SYS_NAND_BLOCK_SIZE
-
-#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
-#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
-
-#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_NAND_BASE
-
-#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
-#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM
-
-#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA_BASE \
- | BR_PS_16 \
- | BR_MS_UPMA \
- | BR_V)
-#define CONFIG_SYS_OR1_PRELIM (OR_AM_2MB \
- | OR_UPM_BCTLD)
-
-#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA_BASE
-#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_2MB)
-
-/*
- * JFFS2 configuration
- */
-#define CONFIG_JFFS2_NAND
-#define CONFIG_JFFS2_DEV "nand0"
-
-/* mtdparts command line support */
-#define CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
-#define MTDIDS_DEFAULT "nand0=nand0"
-#define MTDPARTS_DEFAULT "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-#define CONFIG_OF_STDOUT_VIA_ALIAS 1
-
-/*
- * Serial Port
- */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#ifdef CONFIG_NAND_SPL
-#define CONFIG_NS16550_MIN_FUNCTIONS
-#endif
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_FSL
-#define CONFIG_SYS_FSL_I2C_SPEED 400000
-#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
-#define CONFIG_SYS_FSL_I2C2_SPEED 400000
-#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
-#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
-#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
-#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
-#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
-#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
-#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
-#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
-
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
-
-/*
- * TSEC
- */
-#define CONFIG_TSEC_ENET /* TSEC ethernet support */
-
-#define CONFIG_GMII /* MII PHY management */
-
-#ifdef CONFIG_TSEC1
-#define CONFIG_HAS_ETH0
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_SYS_TSEC1_OFFSET 0x24000
-#define TSEC1_PHY_ADDR 0x0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC1_PHYIDX 0
-#endif
-
-#ifdef CONFIG_TSEC2
-#define CONFIG_HAS_ETH1
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define CONFIG_SYS_TSEC2_OFFSET 0x25000
-#define TSEC2_PHY_ADDR 4
-#define TSEC2_FLAGS TSEC_GIGABIT
-#define TSEC2_PHYIDX 0
-#endif
-
-
-/* Options are: TSEC[0-1] */
-#define CONFIG_ETHPRIME "TSEC1"
-
-/*
- * Configure on-board RTC
- */
-#define CONFIG_RTC_DS1337
-#define CONFIG_SYS_I2C_RTC_ADDR 0x68
-
-/*
- * Environment
- */
-#if defined(CONFIG_NAND_U_BOOT)
- #define CONFIG_ENV_IS_IN_NAND 1
- #define CONFIG_ENV_OFFSET (768 * 1024)
- #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
- #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
- #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
- #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
- #define CONFIG_ENV_OFFSET_REDUND \
- (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
-#elif !defined(CONFIG_SYS_RAMBOOT)
- #define CONFIG_ENV_IS_IN_FLASH 1
- #define CONFIG_ENV_ADDR \
- (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
- #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
- #define CONFIG_ENV_SIZE 0x2000
-
-/* Address and size of Redundant Environment Sector */
-#else
- #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
- #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
- #define CONFIG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-#undef CONFIG_CMD_IMLS
-#undef CONFIG_CMD_FLASH
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_JFFS2
-
-#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#endif
-
-#define CONFIG_CMDLINE_EDITING 1
-#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
- + sizeof(CONFIG_SYS_PROMPT) \
- + 16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
- /* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 256 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
- /* Initial Memory map for Linux*/
-#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
-
-#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
-
-#define CONFIG_SYS_HRCW_LOW (HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \
- | 0x20000000 /* reserved */ \
- | HRCWL_DDR_TO_SCB_CLK_2X1 \
- | HRCWL_CSB_TO_CLKIN_4X1 \
- | HRCWL_CORE_TO_CSB_2_5X1)
-
-#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 4)
-
-#define CONFIG_SYS_HRCW_HIGH_BASE (HRCWH_PCI_HOST \
- | HRCWH_PCI1_ARBITER_ENABLE \
- | HRCWH_CORE_ENABLE \
- | HRCWH_BOOTSEQ_DISABLE \
- | HRCWH_SW_WATCHDOG_DISABLE \
- | HRCWH_TSEC1M_IN_RGMII \
- | HRCWH_TSEC2M_IN_RGMII \
- | HRCWH_BIG_ENDIAN \
- | HRCWH_LALE_NORMAL)
-
-#ifdef CONFIG_NAND_LP
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE \
- | HRCWH_FROM_0XFFF00100 \
- | HRCWH_ROM_LOC_NAND_LP_8BIT \
- | HRCWH_RL_EXT_NAND)
-#else
-#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE \
- | HRCWH_FROM_0XFFF00100 \
- | HRCWH_ROM_LOC_NAND_SP_8BIT \
- | HRCWH_RL_EXT_NAND)
-#endif
-
-/* System IO Config */
-#define CONFIG_SYS_SICRH (SICRH_ETSEC2_B \
- | SICRH_ETSEC2_C \
- | SICRH_ETSEC2_D \
- | SICRH_ETSEC2_E \
- | SICRH_ETSEC2_F \
- | SICRH_ETSEC2_G \
- | SICRH_TSOBI1 \
- | SICRH_TSOBI2)
-#define CONFIG_SYS_SICRL (SICRL_LBC \
- | SICRL_USBDR_10 \
- | SICRL_ETSEC2_A)
-
-#define CONFIG_SYS_HID0_INIT 0x000000000
-#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
- | HID0_ENABLE_INSTRUCTION_CACHE \
- | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-
-#define CONFIG_SYS_HID2 HID2_HBE
-
-#define CONFIG_HIGH_BATS 1 /* High BATs supported */
-
-/* DDR @ 0x00000000 */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
- | BATL_PP_RW)
-#define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* PCI @ 0x80000000 */
-#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
-#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* PCI2 not supported on 8313 */
-#define CONFIG_SYS_IBAT4L (0)
-#define CONFIG_SYS_IBAT4U (0)
-
-/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
-#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
- | BATL_PP_RW \
- | BATL_CACHEINHIBIT \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
-#define CONFIG_SYS_IBAT6L (0xF0000000 \
- | BATL_PP_RW \
- | BATL_GUARDEDSTORAGE)
-#define CONFIG_SYS_IBAT6U (0xF0000000 \
- | BATU_BL_256M \
- | BATU_VS \
- | BATU_VP)
-
-#define CONFIG_SYS_IBAT7L (0)
-#define CONFIG_SYS_IBAT7U (0)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
-#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
-#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
-#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
-#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
-#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
-#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
-#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
-
-/*
- * Environment Configuration
- */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_NETDEV "eth1"
-
-#define CONFIG_HOSTNAME simpc8313
-#define CONFIG_ROOTPATH "/tftpboot/"
-#define CONFIG_BOOTFILE "/tftpboot/uImage"
- /* U-Boot image on TFTP server */
-#define CONFIG_UBOOTPATH "u-boot-nand.bin"
-#define CONFIG_FDTFILE "simpc8313.dtb"
-
- /* default location for tftp and bootm */
-#define CONFIG_LOADADDR 500000
-#define CONFIG_BOOTDELAY 5 /* 5 second delay */
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "netdev=" CONFIG_NETDEV "\0" \
- "ethprime=TSEC1\0" \
- "uboot=" CONFIG_UBOOTPATH "\0" \
- "tftpflash=tftpboot $loadaddr $uboot; " \
- "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize; " \
- "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
- " +$filesize; " \
- "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
- " $filesize\0" \
- "fdtaddr=ae0000\0" \
- "fdtfile=" CONFIG_FDTFILE "\0" \
- "console=ttyS0\0" \
- "setbootargs=setenv bootargs " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
- "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
- "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
- "$netdev:off " \
- "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
- "load_uboot=tftp 100000 u-boot-nand.bin\0" \
- "burn_uboot=nand erase u-boot 80000; " \
- "nand write 100000 u-boot $filesize\0" \
- "update_uboot=run load_uboot;run burn_uboot\0" \
- "mtdids=nand0=nand0\0" \
- "mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0" \
- "nfsargs=setenv bootargs root=/dev/nfs rw " \
- "nfsroot=${serverip}:${rootpath}\0" \
- "ramargs=setenv bootargs root=/dev/ram rw\0" \
- "addip=setenv bootargs ${bootargs} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
- ":${hostname}:${netdev}:off panic=1\0" \
- "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
- "bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw " \
- "console=ttyS0,115200\0" \
- ""
-
-#define CONFIG_NFSBOOTCOMMAND \
- "setenv rootdev /dev/nfs;" \
- "run setbootargs;" \
- "run setipargs;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND \
- "setenv rootdev /dev/ram;" \
- "run setbootargs;" \
- "tftp $ramdiskaddr $ramdiskfile;" \
- "tftp $loadaddr $bootfile;" \
- "tftp $fdtaddr $fdtfile;" \
- "bootm $loadaddr $ramdiskaddr $fdtaddr"
-
-#endif /* __CONFIG_H */
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+
+/*
+ * TDM Definition
+ */
+#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
+
/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
CSPR_MSEL_NOR | \
CSPR_V)
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
+
+/*
+ * TDM Definition
+ */
+#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
+
/* NOR Flash Timing Params */
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
#define CONFIG_VERY_BIG_RAM
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_DIMM_SLOTS_PER_CTLR 2
+#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
#define CONFIG_DDR_SPD
#define CONFIG_SYS_FSL_DDR3
#undef CONFIG_FSL_DDR_INTERACTIVE
+++ /dev/null
-/*
- * Copyright (C) 2003-2005 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * U-Boot configuration for Zephyr Engineering ZPC.1900 board.
- * This port was developed and tested on Revision C board.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_ZPC1900 1 /* ...on Zephyr ZPC.1900 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFE000000
-
-#define CPU_ID_STR "MPC8265"
-#define CONFIG_CPM2 1 /* Has a CPM2 */
-
-/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * Select serial console configuration
- *
- * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- */
-#define CONFIG_CONS_ON_SMC /* Console is on SMC */
-#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
-#undef CONFIG_CONS_NONE /* It's not on external UART */
-#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
-
-/*
- * Select ethernet configuration
- *
- * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
- * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
- * SCC, 1-3 for FCC)
- *
- * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
- * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
- * must be unset.
- */
-#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
-#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
-#undef CONFIG_ETHER_NONE /* No external Ethernet */
-
-#ifdef CONFIG_ETHER_ON_FCC
-
-#define CONFIG_ETHER_INDEX 2 /* FCC2 is used for Ethernet */
-
-#if (CONFIG_ETHER_INDEX == 2)
-/*
- * - Rx clock is CLK13
- * - Tx clock is CLK14
- * - Select bus for bd/buffers (see 28-13)
- * - Full duplex
- */
-# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-# define CONFIG_SYS_CPMFCR_RAMTYPE 0
-# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#endif /* CONFIG_ETHER_INDEX */
-
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
-/*
- * GPIO pins used for bit-banged MII communications
- */
-#define MDIO_PORT 2 /* Port C */
-#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
- (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
-#define MDC_DECLARE MDIO_DECLARE
-
-#define MDIO_ACTIVE (iop->pdir |= 0x00400000)
-#define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
-#define MDIO_READ ((iop->pdat & 0x00400000) != 0)
-
-#define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
- else iop->pdat &= ~0x00400000
-
-#define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
- else iop->pdat &= ~0x00200000
-
-#define MIIDELAY udelay(1)
-
-#endif /* CONFIG_ETHER_ON_FCC */
-
-#ifndef CONFIG_8260_CLKIN
-#define CONFIG_8260_CLKIN 66666666 /* in Hz */
-#endif
-
-#define CONFIG_BAUDRATE 38400
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_BOOTCOMMAND "dhcp;bootm" /* autoboot command */
-#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=:::::eth0:dhcp"
-
-#if defined(CONFIG_CMD_KGDB)
-#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
-#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
-#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
-#endif
-
-#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
-#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x03800000 /* 1 ... 56 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_SIZE 64
-
-#define CONFIG_SYS_IMMR 0xF0000000
-#define CONFIG_SYS_LSDRAM_BASE 0xFC000000
-#define CONFIG_SYS_FLASH_BASE 0xFE000000
-#define CONFIG_SYS_BCSR 0xFEA00000
-#define CONFIG_SYS_EEPROM 0xFEB00000
-#define CONFIG_SYS_FLSIMM_BASE 0xFF000000
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 32 /* max num of sects on one chip */
-
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLSIMM_BASE }
-
-#define BCSR_PCI_MODE 0x01
-
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/* Hard reset configuration word */
-#define CONFIG_SYS_HRCW_MASTER (HRCW_EBM | HRCW_BPS01| HRCW_CIP |\
- HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB100 |\
- HRCW_BMS | HRCW_LBPC00 | HRCW_APPC10 |\
- HRCW_MODCK_H0111 \
- ) /* 0x16848207 */
-/* No slaves */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#if !defined(CONFIG_ENV_IS_IN_FLASH) && !defined(CONFIG_ENV_IS_IN_NVRAM)
-#define CONFIG_ENV_IS_IN_NVRAM 1
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-# define CONFIG_ENV_SECT_SIZE 0x10000
-# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#else
-# define CONFIG_ENV_ADDR (CONFIG_SYS_EEPROM + 0x400)
-# define CONFIG_ENV_SIZE 0x1000
-# define CONFIG_SYS_NVRAM_ACCESS_ROUTINE
-#endif
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-#define CONFIG_SYS_HID0_INIT (HID0_ICFI)
-#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
-
-#define CONFIG_SYS_HID2 0
-
-#define CONFIG_SYS_SIUMCR 0x42200000
-#define CONFIG_SYS_SYPCR 0xFFFFFFC3
-#define CONFIG_SYS_BCR 0x90000000
-#define CONFIG_SYS_SCCR SCCR_DFBRG01
-
-#define CONFIG_SYS_RMR RMR_CSRE
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-#define CONFIG_SYS_RCCR 0
-
-#define CONFIG_SYS_PSDMR /* 0x834DA43B */0x014DA43A
-#define CONFIG_SYS_PSRT 0x0F/* 0x0C */
-#define CONFIG_SYS_LSDMR 0x0085A562
-#define CONFIG_SYS_LSRT 0x0F
-#define CONFIG_SYS_MPTPR 0x4000
-
-#define CONFIG_SYS_PSDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00000041)
-#define CONFIG_SYS_PSDRAM_OR 0xFC0028C0
-#define CONFIG_SYS_LSDRAM_BR (CONFIG_SYS_LSDRAM_BASE | 0x00001861)
-#define CONFIG_SYS_LSDRAM_OR 0xFF803480
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00000801)
-#define CONFIG_SYS_OR0_PRELIM 0xFFE00856
-#define CONFIG_SYS_BR5_PRELIM (CONFIG_SYS_EEPROM | 0x00000801)
-#define CONFIG_SYS_OR5_PRELIM 0xFFFF03F6
-#define CONFIG_SYS_BR6_PRELIM (CONFIG_SYS_FLSIMM_BASE | 0x00001801)
-#define CONFIG_SYS_OR6_PRELIM 0xFF000856
-#define CONFIG_SYS_BR7_PRELIM (CONFIG_SYS_BCSR | 0x00000801)
-#define CONFIG_SYS_OR7_PRELIM 0xFFFF83F6
-
-#define CONFIG_SYS_RESET_ADDRESS 0xC0000000
-
-#endif /* __CONFIG_H */
#include <configs/ti_am335x_common.h>
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_FIT
+# define CONFIG_TIMESTAMP
+# define CONFIG_LZO
+# ifdef CONFIG_ENABLE_VBOOT
+# define CONFIG_OF_CONTROL
+# define CONFIG_OF_SEPARATE
+# define CONFIG_DEFAULT_DEVICE_TREE am335x-boneblack
+# define CONFIG_FIT_SIGNATURE
+# define CONFIG_RSA
+# endif
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN (16 << 20)
+
#define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */
#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
#define CONFIG_BOARD_LATE_INIT
#define CONFIG_SYS_MAX_FLASH_SECT 135
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_TEXT_BASE 0x00000000
#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
#define CONFIG_ARMV7
#define CONFIG_KONA
#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_GENERIC_BOARD
/*
* Memory configuration
#define CONFIG_USB_DEVICE
#define CONFIG_USB_TTY
#define CONFIG_SYS_CONSOLE_IS_IN_ENV
-/* This delay is really for slow-to-power-on USB sticks, not the hub */
-#define CONFIG_USB_HUB_MIN_POWER_ON_DELAY 500
/* commands to include */
#include <config_cmd_default.h>
+++ /dev/null
-/*
- * (C) Copyright 2001, 2002
- * Sangmoon Kim, Etin Systems, dogoil@etinsys.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/* ------------------------------------------------------------------------- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-/* Environments */
-
-/* bootargs */
-#define CONFIG_BOOTARGS \
- "console=ttyS0,9600 init=/linuxrc " \
- "root=/dev/nfs rw nfsroot=192.168.0.1:" \
- "/tftpboot/target " \
- "ip=192.168.0.2:192.168.0.1:192.168.0.1:" \
- "255.255.255.0:debris:eth0:none " \
- "mtdparts=phys:12m(root),-(kernel)"
-
-/* bootcmd */
-#define CONFIG_BOOTCOMMAND \
- "tftp 800000 pImage; " \
- "setenv bootargs console=ttyS0,9600 init=/linuxrc " \
- "root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:" \
- "${netmask}:${hostname}:eth0:none " \
- "mtdparts=phys:12m(root),-(kernel); " \
- "bootm 800000"
-
-/* bootdelay */
-#define CONFIG_BOOTDELAY 5 /* autoboot 5s */
-
-/* baudrate */
-#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
-
-/* loads_echo */
-#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
-
-/* ethaddr */
-#undef CONFIG_ETHADDR
-
-/* eth2addr */
-#undef CONFIG_ETH2ADDR
-
-/* eth3addr */
-#undef CONFIG_ETH3ADDR
-
-/* ipaddr */
-#define CONFIG_IPADDR 192.168.0.2
-
-/* serverip */
-#define CONFIG_SERVERIP 192.168.0.1
-
-/* autoload */
-#undef CONFIG_SYS_AUTOLOAD
-
-/* rootpath */
-#define CONFIG_ROOTPATH "/tftpboot/target"
-
-/* gatewayip */
-#define CONFIG_GATEWAYIP 192.168.0.1
-
-/* netmask */
-#define CONFIG_NETMASK 255.255.255.0
-
-/* hostname */
-#define CONFIG_HOSTNAME debris
-
-/* bootfile */
-#define CONFIG_BOOTFILE "pImage"
-
-/* loadaddr */
-#define CONFIG_LOADADDR 800000
-
-/* preboot */
-#undef CONFIG_PREBOOT
-
-/* clocks_in_mhz */
-#undef CONFIG_CLOCKS_IN_MHZ
-
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_MPC8245 1
-#define CONFIG_DEBRIS 1
-
-#if 0
-#define USE_DINK32 1
-#else
-#undef USE_DINK32
-#endif
-
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_DRAM_SPEED 100 /* MHz */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_KGDB
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SAVES
-#define CONFIG_CMD_SDRAM
-
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
-#define CONFIG_PCI_PNP
-
-#define CONFIG_EEPRO100
-#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
-#define CONFIG_EEPRO100_SROM_WRITE
-
-#define PCI_ENET0_IOADDR 0x80000000
-#define PCI_ENET0_MEMADDR 0x80000000
-#define PCI_ENET1_IOADDR 0x81000000
-#define PCI_ENET1_MEMADDR 0x81000000
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-
-#if defined (USE_DINK32)
-#define CONFIG_SYS_MONITOR_LEN 0x00040000
-#define CONFIG_SYS_MONITOR_BASE 0x00090000
-#define CONFIG_SYS_RAMBOOT 1
-#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-#else
-#undef CONFIG_SYS_RAMBOOT
-#define CONFIG_SYS_MONITOR_LEN 0x00040000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#endif
-
-#define CONFIG_SYS_FLASH_BASE 0x7C000000
-#define CONFIG_SYS_FLASH_SIZE (16*1024*1024) /* debris has tiny eeprom */
-
-#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
-
-#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
-
-#define CONFIG_SYS_EUMB_ADDR 0xFC000000
-
-#define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
-#define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000
-#define FLASH_BASE0_PRELIM 0x7C000000 /* debris flash */
-
-/*
- * JFFS2 partitions
- *
- */
-/* No command line, one static partition, whole device */
-#undef CONFIG_CMD_MTDPARTS
-#define CONFIG_JFFS2_DEV "nor0"
-#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
-#define CONFIG_JFFS2_PART_OFFSET 0x00000000
-
-/* mtdparts command line support */
-
-/* Use first bank for JFFS2, second bank contains U-Boot.
- *
- * Note: fake mtd_id's used, no linux mtd map file.
- */
-/*
-#define CONFIG_CMD_MTDPARTS
-#define MTDIDS_DEFAULT "nor0=debris-0"
-#define MTDPARTS_DEFAULT "mtdparts=debris-0:-(jffs2)"
-*/
-
-#define CONFIG_ENV_IS_IN_NVRAM 1
-#define CONFIG_ENV_OVERWRITE 1
-#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1
-#define CONFIG_ENV_ADDR 0xFF000000 /* right at the start of NVRAM */
-#define CONFIG_ENV_SIZE 0x400 /* Size of the Environment - 8K */
-#define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xff000000
-
-/*
- * CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS =
- * NV_RAM_ADDRS + NV_BOOT_OFFSET + NV_ENET_OFFSET
- */
-#define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900
-
-/*
- * select i2c support configuration
- *
- * Supported configurations are {none, software, hardware} drivers.
- * If the software driver is chosen, there are some additional
- * configuration items that the driver uses to drive the port pins.
- */
-#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-#ifdef CONFIG_SYS_I2C_SOFT
-#error "Soft I2C is not configured properly. Please review!"
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SOFT_SPEED 50000
-#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
-#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
-#define I2C_ACTIVE (iop->pdir |= 0x00010000)
-#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
-#define I2C_READ ((iop->pdat & 0x00010000) != 0)
-#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
- else iop->pdat &= ~0x00010000
-#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
- else iop->pdat &= ~0x00020000
-#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
-#endif /* CONFIG_SYS_I2C_SOFT */
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM }
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in DPRAM)
- */
-
-/*
- * NS16550 Configuration
- */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-
-#define CONFIG_SYS_NS16550_CLK 7372800
-
-#define CONFIG_SYS_NS16550_COM1 0xFF080000
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_NS16550_COM1 + 8)
-#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_NS16550_COM1 + 16)
-#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_NS16550_COM1 + 24)
-
-/*
- * Low Level Configuration Settings
- * (address mappings, register initial values, etc.)
- * You should know what you are doing if you make changes here.
- */
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 3
-
-#define CONFIG_SYS_DLL_EXTEND 0x00
-#define CONFIG_SYS_PCI_HOLD_DEL 0x20
-
-#define CONFIG_SYS_ROMNAL 15 /* rom/flash next access time */
-#define CONFIG_SYS_ROMFAL 31 /* rom/flash access time */
-
-#define CONFIG_SYS_REFINT 430 /* # of clocks between CBR refresh cycles */
-
-#define CONFIG_SYS_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */
-
-/* the following are for SDRAM only*/
-#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
-#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
-#define CONFIG_SYS_RDLAT 4 /* data latency from read command */
-#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
-#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
-#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
-#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
-#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
-#if 0
-#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
-#endif
-
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-#define CONFIG_SYS_EXTROM 1
-#define CONFIG_SYS_REGDIMM 0
-
-
-/* memory bank settings*/
-/*
- * only bits 20-29 are actually used from these vales to set the
- * start/end address the upper two bits will be 0, and the lower 20
- * bits will be set to 0x00000 for a start address, or 0xfffff for an
- * end address
- */
-#define CONFIG_SYS_BANK0_START 0x00000000
-#define CONFIG_SYS_BANK0_END (0x4000000 - 1)
-#define CONFIG_SYS_BANK0_ENABLE 1
-#define CONFIG_SYS_BANK1_START 0x04000000
-#define CONFIG_SYS_BANK1_END (0x8000000 - 1)
-#define CONFIG_SYS_BANK1_ENABLE 1
-#define CONFIG_SYS_BANK2_START 0x3ff00000
-#define CONFIG_SYS_BANK2_END 0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE 0
-#define CONFIG_SYS_BANK3_START 0x3ff00000
-#define CONFIG_SYS_BANK3_END 0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE 0
-#define CONFIG_SYS_BANK4_START 0x00000000
-#define CONFIG_SYS_BANK4_END 0x00000000
-#define CONFIG_SYS_BANK4_ENABLE 0
-#define CONFIG_SYS_BANK5_START 0x00000000
-#define CONFIG_SYS_BANK5_END 0x00000000
-#define CONFIG_SYS_BANK5_ENABLE 0
-#define CONFIG_SYS_BANK6_START 0x00000000
-#define CONFIG_SYS_BANK6_END 0x00000000
-#define CONFIG_SYS_BANK6_ENABLE 0
-#define CONFIG_SYS_BANK7_START 0x00000000
-#define CONFIG_SYS_BANK7_END 0x00000000
-#define CONFIG_SYS_BANK7_ENABLE 0
-/*
- * Memory bank enable bitmask, specifying which of the banks defined above
- are actually present. MSB is for bank #7, LSB is for bank #0.
- */
-#define CONFIG_SYS_BANK_ENABLE 0x01
-
-#define CONFIG_SYS_ODCR 0x75 /* configures line driver impedances, */
- /* see 8240 book for bit definitions */
-#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
- /* currently accessed page in memory */
- /* see 8240 book for details */
-
-/* SDRAM 0 - 256MB */
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* stack in DCACHE @ 1GB (no backing mem) */
-#if defined(USE_DINK32)
-#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 )
-#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K )
-#else
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-#endif
-
-/* PCI memory */
-#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-/* Flash, config addrs, etc */
-#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-/* values according to the manual */
-
-#define CONFIG_DRAM_50MHZ 1
-#define CONFIG_SDRAM_50MHZ
-
-#define CONFIG_DISK_SPINUP_TIME 1000000
-
-#endif /* __CONFIG_H */
#include <linux/sizes.h>
#define CONFIG_MXC_UART_BASE UART2_BASE
-#define CONFIG_CONSOLE_DEV "ttymxc0"
+#define CONFIG_CONSOLE_DEV "ttymxc1"
#define CONFIG_MMCROOT "/dev/mmcblk1p2"
#define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
#if defined(CONFIG_ENV_IS_IN_MMC)
/* RiOTboard */
-#define CONFIG_DEFAULT_FDT_FILE "imx6s-riotboard.dtb"
+#define CONFIG_DEFAULT_FDT_FILE "imx6dl-riotboard.dtb"
#define CONFIG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SYS_MMC_ENV_DEV 2 /* SDHC4 */
#define CONFIG_ENV_OFFSET (6 * 64 * 1024)
+++ /dev/null
-/*
- * Copyright (C) 2004 Arabella Software Ltd.
- * Yuli Barcohen <yuli@arabellasw.com>
- *
- * U-Boot configuration for Embedded Planet EP8248 boards.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MPC8248
-#define CPU_ID_STR "MPC8248"
-
-#define CONFIG_EP8248 /* Embedded Planet EP8248 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-
-/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
-#define CONFIG_ENV_OVERWRITE
-
-/*
- * Select serial console configuration
- *
- * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
- * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
- * for SCC).
- */
-#define CONFIG_CONS_ON_SMC /* Console is on SMC */
-#undef CONFIG_CONS_ON_SCC /* It's not on SCC */
-#undef CONFIG_CONS_NONE /* It's not on external UART */
-#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */
-
-#define CONFIG_SYS_BCSR 0xFA000000
-
-/* Pass open firmware flat device tree */
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_OF_BOARD_SETUP 1
-
-#define OF_TBCLK (bd->bi_busfreq / 4)
-#define OF_STDOUT_PATH "/soc/cpm/serial <at> 11a80"
-
-/* Select ethernet configuration */
-#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */
-#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */
-#undef CONFIG_ETHER_NONE /* No external Ethernet */
-
-#define CONFIG_SYS_CPMFCR_RAMTYPE 0
-#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
-
-#define CONFIG_HAS_ETH0
-#define CONFIG_ETHER_ON_FCC1 1
-/* - Rx clock is CLK10
- * - Tx clock is CLK11
- * - BDs/buffers on 60x bus
- * - Full duplex
- */
-#define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
-#define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK10 | CMXFCR_TF1CS_CLK11)
-
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETHER_ON_FCC2 1
-/* - Rx clock is CLK13
- * - Tx clock is CLK14
- * - BDs/buffers on 60x bus
- * - Full duplex
- */
-#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
-#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
-
-#define CONFIG_MII /* MII PHY management */
-#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */
-/*
- * GPIO pins used for bit-banged MII communications
- */
-#define MDIO_PORT 0 /* Not used - implemented in BCSR */
-
-#define MDIO_ACTIVE (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB)
-#define MDIO_TRISTATE (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04)
-#define MDIO_READ (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1)
-
-#define MDIO(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \
- else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE
-
-#define MDC(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \
- else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD
-
-#define MIIDELAY udelay(1)
-
-#ifndef CONFIG_8260_CLKIN
-#define CONFIG_8260_CLKIN 66000000 /* in Hz */
-#endif
-
-#define CONFIG_BAUDRATE 38400
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_ECHO
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_IMMAP
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-
-
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-#define CONFIG_BOOTCOMMAND "bootm FF860000" /* autoboot command */
-#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=phys:7M(root),-(root)ro"
-
-#if defined(CONFIG_CMD_KGDB)
-#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
-#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
-#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
-#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */
-#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
-#endif
-
-#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
-#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-
-#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-
-#define CONFIG_SYS_FLASH_BASE 0xFF800000
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
-
-#define CONFIG_SYS_DIRECT_FLASH_TFTP
-
-#if defined(CONFIG_CMD_JFFS2)
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0
-#define CONFIG_SYS_JFFS2_LAST_SECTOR 62
-#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
-#define CONFIG_SYS_JFFS_CUSTOM_PART
-#endif
-
-#if defined(CONFIG_CMD_I2C)
-#define CONFIG_HARD_I2C 1 /* To enable I2C support */
-#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */
-#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */
-#endif
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#endif
-
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */
-
-#define CONFIG_ENV_IS_IN_FLASH
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x20000
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-#endif /* CONFIG_ENV_IS_IN_FLASH */
-
-#define CONFIG_SYS_DEFAULT_IMMR 0x00010000
-
-#define CONFIG_SYS_IMMR 0xF0000000
-
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
-#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/* Hard reset configuration word */
-#define CONFIG_SYS_HRCW_MASTER 0x0C40025A /* Not used - provided by FPGA */
-/* No slaves */
-#define CONFIG_SYS_HRCW_SLAVE1 0
-#define CONFIG_SYS_HRCW_SLAVE2 0
-#define CONFIG_SYS_HRCW_SLAVE3 0
-#define CONFIG_SYS_HRCW_SLAVE4 0
-#define CONFIG_SYS_HRCW_SLAVE5 0
-#define CONFIG_SYS_HRCW_SLAVE6 0
-#define CONFIG_SYS_HRCW_SLAVE7 0
-
-#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
-#endif
-
-#define CONFIG_SYS_HID0_INIT 0
-#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE)
-
-#define CONFIG_SYS_HID2 0
-
-#define CONFIG_SYS_SIUMCR 0x01240200
-#define CONFIG_SYS_SYPCR 0xFFFF0683
-#define CONFIG_SYS_BCR 0x00000000
-#define CONFIG_SYS_SCCR SCCR_DFBRG01
-
-#define CONFIG_SYS_RMR RMR_CSRE
-#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
-#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
-#define CONFIG_SYS_RCCR 0
-
-#define CONFIG_SYS_MPTPR 0x1300
-#define CONFIG_SYS_PSDMR 0x82672522
-#define CONFIG_SYS_PSRT 0x4B
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00001841)
-#define CONFIG_SYS_SDRAM_OR 0xFF0030C0
-
-#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801)
-#define CONFIG_SYS_OR0_PRELIM 0xFF8008C2
-#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_BCSR | 0x00000801)
-#define CONFIG_SYS_OR2_PRELIM 0xFFF00864
-
-#define CONFIG_SYS_RESET_ADDRESS 0xC0000000
-
-#endif /* __CONFIG_H */
#include <asm/hardware.h>
+#define CONFIG_SYS_GENERIC_BOARD
+
/* The first stage boot loader expects u-boot running at this address. */
#define CONFIG_SYS_TEXT_BASE 0x27000000 /* 16MB available */
#ifndef __CONFIG_H
#define __CONFIG_H
+/* SPL */
+#define CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SPL_FAT_SUPPORT
+/*
+#define CONFIG_SPL_SATA_SUPPORT
+*/
+/* Location in NAND to read U-Boot from */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS (14 * 1024 * 1024)
+
+#include "imx6_spl.h" /* common IMX6 SPL configuration */
#include "mx6_common.h"
#define CONFIG_MX6
#define CONFIG_DISPLAY_CPUINFO /* display cpu info */
#define CONFIG_USB_ETH_CDC
#define CONFIG_NETCONSOLE
#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
-#define CONFIG_USB_HUB_MIN_POWER_ON_DELAY 1200
/* Framebuffer and LCD */
#define CONFIG_VIDEO
#define CONFIG_MPC8313
#define CONFIG_IDS8313
+#define CONFIG_SYS_GENERIC_BOARD
+
#define CONFIG_FSL_ELBC
#define CONFIG_MISC_INIT_R
#define CONFIG_FIT
#define CONFIG_FIT_SIGNATURE
+#define CONFIG_IMAGE_FORMAT_LEGACY
#define CONFIG_CMD_FDT
#define CONFIG_CMD_HASH
#define CONFIG_RSA
#define CONFIG_SHA1
#define CONFIG_SHA256
-#define CONFIG_OF_CONTROL
#endif /* __CONFIG_H */
--- /dev/null
+/*
+ * Copyright (C) 2014 Gateworks Corporation
+ * Author: Tim Harvey <tharvey@gateworks.com>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef __IMX6_SPL_CONFIG_H
+#define __IMX6_SPL_CONFIG_H
+
+#ifdef CONFIG_SPL
+
+#define CONFIG_SPL_FRAMEWORK
+
+/*
+ * see Figure 8-3 in IMX6DQ/IMX6SDL Reference manuals:
+ * - IMX6SDL OCRAM (IRAM) is from 0x00907000 to 0x0091FFFF
+ * - IMX6DQ has 2x IRAM of IMX6SDL but we intend to support IMX6SDL as well
+ * - BOOT ROM stack is at 0x0091FFB8
+ * - if icache/dcache is enabled (eFuse/strapping controlled) then the
+ * IMX BOOT ROM will setup MMU table at 0x00918000, therefore we need to
+ * fit between 0x00907000 and 0x00918000.
+ * - Additionally the BOOT ROM loads what they consider the firmware image
+ * which consists of a 4K header in front of us that contains the IVT, DCD
+ * and some padding thus 'our' max size is really 0x00908000 - 0x00918000
+ * or 64KB
+ */
+#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/omap-common/u-boot-spl.lds"
+#define CONFIG_SPL_TEXT_BASE 0x00908000
+#define CONFIG_SPL_MAX_SIZE (64 * 1024)
+#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7"
+#define CONFIG_SPL_STACK 0x0091FFB8
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_GPIO_SUPPORT
+
+/* NAND support */
+#if defined(CONFIG_SPL_NAND_SUPPORT)
+#define CONFIG_SPL_NAND_MXS
+#define CONFIG_SPL_DMA_SUPPORT
+#endif
+
+/* MMC support */
+#if defined(CONFIG_SPL_MMC_SUPPORT)
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 138 /* offset 69KB */
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 800 /* 400 KB */
+#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
+#define CONFIG_SYS_MONITOR_LEN (CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS/2*1024)
+#endif
+
+/* SATA support */
+#if defined(CONFIG_SPL_SATA_SUPPORT)
+#define CONFIG_SPL_SATA_BOOT_DEVICE 0
+#define CONFIG_SYS_SATA_FAT_BOOT_PARTITION 1
+#endif
+
+/* Define the payload for FAT/EXT support */
+#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
+#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
+#define CONFIG_SPL_LIBDISK_SUPPORT
+#endif
+
+#define CONFIG_SPL_BSS_START_ADDR 0x18200000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */
+#define CONFIG_SYS_SPL_MALLOC_START 0x18300000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x3200000 /* 50 MB */
+#define CONFIG_SYS_TEXT_BASE 0x17800000
+#endif
+
+#endif
* Commands additional to the ones defined in amcc-common.h
*/
#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_FPGA
-#define CONFIG_CMD_FPGA_LOADMK
+#define CONFIG_CMD_FPGAD
#undef CONFIG_CMD_EEPROM
/*
+++ /dev/null
-/*
- * (C) Copyright 2005
- * Sangmoon Kim, dogoil@etinsys.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#define CONFIG_MPC8245 1
-#define CONFIG_KVME080 1
-
-#define CONFIG_SYS_TEXT_BASE 0xFFF00000
-
-#define CONFIG_CONS_INDEX 1
-
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_BOOTDELAY 5
-
-#define CONFIG_IPADDR 192.168.0.2
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_SERVERIP 192.168.0.1
-
-#define CONFIG_BOOTARGS \
- "console=ttyS0,115200 " \
- "root=/dev/nfs rw nfsroot=192.168.0.1:/opt/eldk/ppc_82xx " \
- "ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:" \
- "kvme080:eth0:none " \
- "mtdparts=phys_mapped_flash:12m(root),-(kernel)"
-
-#define CONFIG_BOOTCOMMAND \
- "tftp 800000 kvme080/uImage; " \
- "bootm 800000"
-
-#define CONFIG_LOADADDR 800000
-
-#define CONFIG_BOARD_EARLY_INIT_F
-#define CONFIG_BOARD_EARLY_INIT_R
-#define CONFIG_MISC_INIT_R
-
-#define CONFIG_LOADS_ECHO 1
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE
-
-#undef CONFIG_WATCHDOG
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_SUBNETMASK
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_BOOTFILESIZE
-
-
-#define CONFIG_MAC_PARTITION
-#define CONFIG_DOS_PARTITION
-
-#define CONFIG_RTC_DS164x
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_ASKENV
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DATE
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_JFFS2
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_PCI
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_SDRAM
-#define CONFIG_CMD_SNTP
-
-
-#define CONFIG_NETCONSOLE
-
-#define CONFIG_SYS_LONGHELP
-#define CONFIG_SYS_CBSIZE 256
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
-#define CONFIG_SYS_MAXARGS 16
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-
-#define CONFIG_SYS_MEMTEST_START 0x00400000
-#define CONFIG_SYS_MEMTEST_END 0x07C00000
-
-#define CONFIG_SYS_LOAD_ADDR 0x00100000
-
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
-#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0x7C000000
-#define CONFIG_SYS_EUMB_ADDR 0xFC000000
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFF000000
-#define CONFIG_SYS_NS16550_COM1 0xFF080000
-#define CONFIG_SYS_NS16550_COM2 0xFF080010
-#define CONFIG_SYS_NS16550_COM3 0xFF080020
-#define CONFIG_SYS_NS16550_COM4 0xFF080030
-#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
-
-#define CONFIG_SYS_MAX_RAM_SIZE 0x20000000
-#define CONFIG_SYS_FLASH_SIZE (16 * 1024 * 1024)
-#define CONFIG_SYS_NVRAM_SIZE 0x7FFF8
-
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_SYS_MONITOR_LEN 0x00040000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
-#define CONFIG_SYS_MALLOC_LEN (512 << 10)
-
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
-
-#define CONFIG_SYS_FLASH_CFI
-#define CONFIG_FLASH_CFI_DRIVER
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
-#define CONFIG_SYS_FLASH_PROTECTION
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_PROTECT_CLEAR
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_MAX_FLASH_SECT 256
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500
-
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-
-#define CONFIG_ENV_IS_IN_NVRAM 1
-#define CONFIG_ENV_OVERWRITE 1
-#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE
-#define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR
-#define CONFIG_ENV_SIZE 0x400
-#define CONFIG_ENV_OFFSET 0
-
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK 14745600
-
-#define CONFIG_PCI
-#define CONFIG_PCI_INDIRECT_BRIDGE
-#define CONFIG_PCI_PNP
-
-#define CONFIG_EEPRO100
-#define CONFIG_EEPRO100_SROM_WRITE
-
-#define CONFIG_SYS_RX_ETH_BUFFER 8
-
-#define CONFIG_HARD_I2C 1
-#define CONFIG_SYS_I2C_SPEED 400000
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
-
-#define CONFIG_SYS_CLK_FREQ 33333333
-
-#define CONFIG_SYS_CACHELINE_SIZE 32
-#if defined(CONFIG_CMD_KGDB)
-# define CONFIG_SYS_CACHELINE_SHIFT 5
-#endif
-
-#define CONFIG_SYS_DLL_EXTEND 0x00
-#define CONFIG_SYS_PCI_HOLD_DEL 0x20
-
-#define CONFIG_SYS_ROMNAL 15
-#define CONFIG_SYS_ROMFAL 31
-
-#define CONFIG_SYS_REFINT 430
-
-#define CONFIG_SYS_DBUS_SIZE2 1
-
-#define CONFIG_SYS_BSTOPRE 121
-#define CONFIG_SYS_REFREC 8
-#define CONFIG_SYS_RDLAT 4
-#define CONFIG_SYS_PRETOACT 3
-#define CONFIG_SYS_ACTTOPRE 5
-#define CONFIG_SYS_ACTORW 3
-#define CONFIG_SYS_SDMODE_CAS_LAT 3
-#define CONFIG_SYS_SDMODE_WRAP 0
-
-#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
-#define CONFIG_SYS_EXTROM 1
-#define CONFIG_SYS_REGDIMM 0
-
-#define CONFIG_SYS_BANK0_START 0x00000000
-#define CONFIG_SYS_BANK0_END (0x4000000 - 1)
-#define CONFIG_SYS_BANK0_ENABLE 1
-#define CONFIG_SYS_BANK1_START 0x04000000
-#define CONFIG_SYS_BANK1_END (0x8000000 - 1)
-#define CONFIG_SYS_BANK1_ENABLE 1
-#define CONFIG_SYS_BANK2_START 0x3ff00000
-#define CONFIG_SYS_BANK2_END 0x3fffffff
-#define CONFIG_SYS_BANK2_ENABLE 0
-#define CONFIG_SYS_BANK3_START 0x3ff00000
-#define CONFIG_SYS_BANK3_END 0x3fffffff
-#define CONFIG_SYS_BANK3_ENABLE 0
-#define CONFIG_SYS_BANK4_START 0x00000000
-#define CONFIG_SYS_BANK4_END 0x00000000
-#define CONFIG_SYS_BANK4_ENABLE 0
-#define CONFIG_SYS_BANK5_START 0x00000000
-#define CONFIG_SYS_BANK5_END 0x00000000
-#define CONFIG_SYS_BANK5_ENABLE 0
-#define CONFIG_SYS_BANK6_START 0x00000000
-#define CONFIG_SYS_BANK6_END 0x00000000
-#define CONFIG_SYS_BANK6_ENABLE 0
-#define CONFIG_SYS_BANK7_START 0x00000000
-#define CONFIG_SYS_BANK7_END 0x00000000
-#define CONFIG_SYS_BANK7_ENABLE 0
-
-#define CONFIG_SYS_BANK_ENABLE 0x03
-
-#define CONFIG_SYS_ODCR 0x75
-#define CONFIG_SYS_PGMAX 0x32
-
-#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
-
-#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
-#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
-#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
-#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
-#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
-#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
-#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
-#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
-
-#endif /* __CONFIG_H */
#define __M53EVK_CONFIG_H__
#define CONFIG_MX53
+#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_MXC_GPIO
#include <asm/arch/imx-regs.h>
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Environment */
+#ifndef CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SIZE (16 * 1024)
+#else
+#define CONFIG_ENV_SIZE (4 * 1024)
+#endif
#define CONFIG_ENV_OVERWRITE
/* Environment is in MMC */
/* Environemnt is in SPI flash */
#if defined(CONFIG_CMD_SF) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
-#define CONFIG_ENV_SIZE 0x1000 /* 4KB */
#define CONFIG_ENV_OFFSET 0x40000 /* 256K */
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_ENV_SECT_SIZE 0x1000
#ifndef __MX6_COMMON_H
#define __MX6_COMMON_H
-#define CONFIG_ARM_ERRATA_742230
#define CONFIG_ARM_ERRATA_743622
#define CONFIG_ARM_ERRATA_751472
#define CONFIG_ARM_ERRATA_794072
#define CONFIG_MACH_TYPE 3529
#define CONFIG_MXC_UART_BASE UART4_BASE
#define CONFIG_CONSOLE_DEV "ttymxc3"
+#if defined CONFIG_MX6Q
#define CONFIG_DEFAULT_FDT_FILE "imx6q-sabreauto.dtb"
+#elif defined CONFIG_MX6DL
+#define CONFIG_DEFAULT_FDT_FILE "imx6dl-sabreauto.dtb"
+#endif
#define CONFIG_MMCROOT "/dev/mmcblk0p2"
#define PHYS_SDRAM_SIZE (2u * 1024 * 1024 * 1024)
#define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(3, 19)
#endif
+/* I2C Configs */
+#define CONFIG_CMD_I2C
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_MXC
+#define CONFIG_SYS_I2C_SPEED 100000
+
+/* PMIC */
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_PFUZE100
+#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+
#endif /* __MX6QSABRESD_CONFIG_H */
+++ /dev/null
-/*
- * (C) Copyright 2008
- * Gary Jennejohn, DENX Software Engineering GmbH, garyj@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/************************************************************************
- * quad100hd.h - configuration for Quad100hd board
- ***********************************************************************/
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*-----------------------------------------------------------------------
- * High Level Configuration Options
- *----------------------------------------------------------------------*/
-#define CONFIG_QUAD100HD 1 /* Board is Quad100hd */
-#define CONFIG_405EP 1 /* Specifc 405EP support*/
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
-
-#define PLLMR0_DEFAULT PLLMR0_266_133_66 /* no PCI */
-#define PLLMR1_DEFAULT PLLMR1_266_133_66 /* no PCI */
-
-/* the environment is in the EEPROM by default */
-#define CONFIG_ENV_IS_IN_EEPROM
-#undef CONFIG_ENV_IS_IN_FLASH
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_HAS_ETH1 1
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0x01 /* PHY address */
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */
-#define CONFIG_PHY_RESET 1
-#define CONFIG_PHY_RESET_DELAY 300 /* PHY RESET recovery delay */
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#undef CONFIG_CMD_ASKENV
-#undef CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
-#undef CONFIG_CMD_DIAG
-#define CONFIG_CMD_EEPROM
-#undef CONFIG_CMD_ELF
-#define CONFIG_CMD_I2C
-#undef CONFIG_CMD_IRQ
-#define CONFIG_CMD_JFFS2
-#undef CONFIG_CMD_MII
-#define CONFIG_CMD_NAND
-#undef CONFIG_CMD_PING
-#define CONFIG_CMD_REGINFO
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*-----------------------------------------------------------------------
- * SDRAM
- *----------------------------------------------------------------------*/
-/*
- * SDRAM configuration (please see cpu/ppc/sdram.[ch])
- */
-#define CONFIG_SDRAM_BANK0 1
-
-/* FIX! SDRAM timings used in datasheet */
-#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
-#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
-#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
-#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
-#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
-
-/*
- * JFFS2
- */
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0
-#ifdef CONFIG_SYS_KERNEL_IN_JFFS2
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0 /* JFFS starts at block 0 */
-#else /* kernel not in JFFS */
-#define CONFIG_SYS_JFFS2_FIRST_SECTOR 8 /* block 0-7 is kernel (1MB = 8 sectors) */
-#endif
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1
-
-/*-----------------------------------------------------------------------
- * Serial Port
- *----------------------------------------------------------------------*/
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
-#define CONFIG_SYS_BASE_BAUD 691200
-#define CONFIG_BAUDRATE 115200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
-
-/*-----------------------------------------------------------------------
- * Miscellaneous configurable options
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_info (bd_t) */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
-#define CONFIG_LOOPW 1 /* enable loopw command */
-#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-/*-----------------------------------------------------------------------
- * I2C
- *----------------------------------------------------------------------*/
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* base address */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* bytes of address */
-
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 8 byte write page size */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-#define CONFIG_SYS_EEPROM_SIZE 0x2000
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFC00000
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE)
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
-#define CONFIG_FLASH_CFI_DRIVER
-
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
-#define CONFIG_SYS_FLASH_INCREMENT 0 /* there is only one bank */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
-#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
-/* the environment is located before u-boot */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_TEXT_BASE - CONFIG_ENV_SECT_SIZE)
-
-/* Address and size of Redundant Environment Sector */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_EEPROM
-#define CONFIG_ENV_SIZE 0x400 /* Size of Environment vars */
-#define CONFIG_ENV_OFFSET 0x00000000
-#define CONFIG_SYS_ENABLE_CRC_16 1 /* Intrinsyc formatting used crc16 */
-#endif
-
-/* partly from PPCBoot */
-/* NAND */
-#define CONFIG_NAND
-#ifdef CONFIG_NAND
-#define CONFIG_SYS_NAND_BASE 0x60000000
-#define CONFIG_SYS_NAND_CS 10 /* our CS is GPIO10 */
-#define CONFIG_SYS_NAND_RDY 23 /* our RDY is GPIO23 */
-#define CONFIG_SYS_NAND_CE 24 /* our CE is GPIO24 */
-#define CONFIG_SYS_NAND_CLE 31 /* our CLE is GPIO31 */
-#define CONFIG_SYS_NAND_ALE 30 /* our ALE is GPIO30 */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1
-
-#endif
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory (OCM) for temperary stack until sdram is tested */
-/* see ./arch/powerpc/cpu/ppc4xx/start.S */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of OCM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- * Taken from PPCBoot board/icecube/icecube.h
- */
-
-/* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/ndfc.c */
-#define CONFIG_SYS_EBC_PB0AP 0x04002480
-/* AMD NOR flash - this corresponds to FLASH_BASE so may be correct */
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
-#define CONFIG_SYS_EBC_PB1AP 0x04005480
-#define CONFIG_SYS_EBC_PB1CR 0x60018000
-#define CONFIG_SYS_EBC_PB2AP 0x00000000
-#define CONFIG_SYS_EBC_PB2CR 0x00000000
-#define CONFIG_SYS_EBC_PB3AP 0x00000000
-#define CONFIG_SYS_EBC_PB3CR 0x00000000
-#define CONFIG_SYS_EBC_PB4AP 0x00000000
-#define CONFIG_SYS_EBC_PB4CR 0x00000000
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * Taken in part from PPCBoot board/icecube/icecube.h
- */
-/* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */
-#define CONFIG_SYS_GPIO0_OSRL 0x55555550
-#define CONFIG_SYS_GPIO0_OSRH 0x00000110
-#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
-#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
-#define CONFIG_SYS_GPIO0_TSRL 0x00000000
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
-#define CONFIG_SYS_GPIO0_TCR 0xFFFF8097
-#define CONFIG_SYS_GPIO0_ODR 0x00000000
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#endif
-
-/* ENVIRONMENT VARS */
-
-#define CONFIG_IPADDR 192.168.1.67
-#define CONFIG_SERVERIP 192.168.1.50
-#define CONFIG_GATEWAYIP 192.168.1.1
-#define CONFIG_NETMASK 255.255.255.0
-#define CONFIG_LOADADDR 300000
-#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT 1
-
-#endif /* __CONFIG_H */
#endif
+#define CONFIG_IO_TRACE
+#define CONFIG_CMD_IOTRACE
+
#define CONFIG_SYS_TIMER_RATE 1000000
#define CONFIG_BOOTSTAGE
#define CONFIG_RSA
#define CONFIG_CMD_FDT
#define CONFIG_DEFAULT_DEVICE_TREE sandbox
+#define CONFIG_ANDROID_BOOT_IMAGE
#define CONFIG_FS_FAT
#define CONFIG_FS_EXT4
--- /dev/null
+/*
+ * Copyright (C) 2011-2014 Pierrick Hascoet, Abilis Systems
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CONFIG_TB100_H_
+#define _CONFIG_TB100_H_
+
+#include <linux/sizes.h>
+
+/*
+ * CPU configuration
+ */
+#define CONFIG_ARC700
+#define CONFIG_ARC_MMU_VER 3
+#define CONFIG_SYS_CACHELINE_SIZE 32
+#define CONFIG_SYS_CLK_FREQ 500000000
+#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
+
+/*
+ * Board configuration
+ */
+#define CONFIG_SYS_GENERIC_BOARD
+#define CONFIG_ARCH_EARLY_INIT_R
+
+/*
+ * Memory configuration
+ */
+#define CONFIG_SYS_TEXT_BASE 0x84000000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
+#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
+#define CONFIG_SYS_SDRAM_SIZE SZ_128M
+
+#define CONFIG_SYS_INIT_SP_ADDR \
+ (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_SYS_MALLOC_LEN SZ_128K
+#define CONFIG_SYS_BOOTM_LEN SZ_32M
+#define CONFIG_SYS_LOAD_ADDR 0x82000000
+
+#define CONFIG_SYS_NO_FLASH
+
+/*
+ * UART configuration
+ */
+#define CONFIG_CONS_INDEX 1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE -4
+#define CONFIG_SYS_NS16550_CLK 166666666
+#define CONFIG_SYS_NS16550_COM1 0xFF100000
+#define CONFIG_SYS_NS16550_MEM32
+
+#define CONFIG_BAUDRATE 115200
+
+/*
+ * Ethernet PHY configuration
+ */
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_GIGE
+
+/*
+ * Even though the board houses Realtek RTL8211E PHY
+ * corresponding PHY driver (drivers/net/phy/realtek.c) behaves unexpectedly.
+ * In particular "parse_status" reports link is down.
+ *
+ * Until Realtek PHY driver is fixed fall back to generic PHY driver
+ * which implements all required functionality and behaves much more stable.
+ *
+ * #define CONFIG_PHY_REALTEK
+ *
+ */
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_DESIGNWARE_ETH
+#define ETH0_BASE_ADDRESS 0xFE100000
+#define ETH1_BASE_ADDRESS 0xFE110000
+
+/*
+ * Command line configuration
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_PING
+
+#define CONFIG_OF_LIBFDT
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_SYS_MAXARGS 16
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE SZ_2K
+#define CONFIG_ENV_OFFSET 0
+
+/*
+ * Environment configuration
+ */
+#define CONFIG_BOOTDELAY 3
+#define CONFIG_BOOTFILE "uImage"
+#define CONFIG_BOOTARGS "console=ttyS0,115200n8"
+#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
+
+/*
+ * Console configuration
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "[tb100]:~# "
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+#endif /* _CONFIG_TB100_H_ */
#include <asm/arch/tegra.h> /* get chip and board defs */
+#define CONFIG_DM
+#define CONFIG_CMD_DM
+
#define CONFIG_SYS_TIMER_RATE 1000000
#define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE
* we are on so we do not need to rely on the command prompt. We set a
* console baudrate of 115200 and use the default baud rate table.
*/
-#define CONFIG_SYS_MALLOC_LEN (1024 << 10)
+#define CONFIG_SYS_MALLOC_LEN (16 << 20)
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT "U-Boot# "
#define CONFIG_SYS_CONSOLE_INFO_QUIET
/* FIT support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */
+#define CONFIG_IMAGE_FORMAT_LEGACY /* enable also legacy image format */
/* FDT support */
#define CONFIG_OF_CONTROL
};
struct demo_ops {
- int (*hello)(struct device *dev, int ch);
- int (*status)(struct device *dev, int *status);
+ int (*hello)(struct udevice *dev, int ch);
+ int (*status)(struct udevice *dev, int *status);
};
-int demo_hello(struct device *dev, int ch);
-int demo_status(struct device *dev, int *status);
+int demo_hello(struct udevice *dev, int ch);
+int demo_status(struct udevice *dev, int *status);
int demo_list(void);
-int demo_parse_dt(struct device *dev);
+int demo_parse_dt(struct udevice *dev);
#endif
*/
#ifndef _DM_H_
-#define _DM_H
+#define _DM_H_
#include <dm/device.h>
#include <dm/platdata.h>
#ifndef _DM_DEVICE_INTERNAL_H
#define _DM_DEVICE_INTERNAL_H
-struct device;
+struct udevice;
/**
* device_bind() - Create a device and bind it to a driver
* @devp: Returns a pointer to the bound device
* @return 0 if OK, -ve on error
*/
-int device_bind(struct device *parent, struct driver *drv,
+int device_bind(struct udevice *parent, struct driver *drv,
const char *name, void *platdata, int of_offset,
- struct device **devp);
+ struct udevice **devp);
/**
* device_bind_by_name: Create a device and bind it to a driver
* @devp: Returns a pointer to the bound device
* @return 0 if OK, -ve on error
*/
-int device_bind_by_name(struct device *parent, const struct driver_info *info,
- struct device **devp);
+int device_bind_by_name(struct udevice *parent, const struct driver_info *info,
+ struct udevice **devp);
/**
* device_probe() - Probe a device, activating it
* @dev: Pointer to device to probe
* @return 0 if OK, -ve on error
*/
-int device_probe(struct device *dev);
+int device_probe(struct udevice *dev);
/**
* device_remove() - Remove a device, de-activating it
* @dev: Pointer to device to remove
* @return 0 if OK, -ve on error (an error here is normally a very bad thing)
*/
-int device_remove(struct device *dev);
+int device_remove(struct udevice *dev);
/**
* device_unbind() - Unbind a device, destroying it
* @dev: Pointer to device to unbind
* @return 0 if OK, -ve on error
*/
-int device_unbind(struct device *dev);
+int device_unbind(struct udevice *dev);
+
+/* Cast away any volatile pointer */
+#define DM_ROOT_NON_CONST (((gd_t *)gd)->dm_root)
+#define DM_UCLASS_ROOT_NON_CONST (((gd_t *)gd)->uclass_root)
#endif
#define DM_FLAG_ACTIVATED (1 << 0)
/* DM is responsible for allocating and freeing platdata */
-#define DM_FLAG_ALLOC_PDATA (2 << 0)
+#define DM_FLAG_ALLOC_PDATA (1 << 1)
/**
- * struct device - An instance of a driver
+ * struct udevice - An instance of a driver
*
* This holds information about a device, which is a driver bound to a
* particular port or peripheral (essentially a driver instance).
* @sibling_node: Next device in list of all devices
* @flags: Flags for this device DM_FLAG_...
*/
-struct device {
+struct udevice {
struct driver *driver;
const char *name;
void *platdata;
int of_offset;
- struct device *parent;
+ struct udevice *parent;
void *priv;
struct uclass *uclass;
void *uclass_priv;
#define device_active(dev) ((dev)->flags & DM_FLAG_ACTIVATED)
/**
- * struct device_id - Lists the compatible strings supported by a driver
+ * struct udevice_id - Lists the compatible strings supported by a driver
* @compatible: Compatible string
* @data: Data for this compatible string
*/
-struct device_id {
+struct udevice_id {
const char *compatible;
ulong data;
};
struct driver {
char *name;
enum uclass_id id;
- const struct device_id *of_match;
- int (*bind)(struct device *dev);
- int (*probe)(struct device *dev);
- int (*remove)(struct device *dev);
- int (*unbind)(struct device *dev);
- int (*ofdata_to_platdata)(struct device *dev);
+ const struct udevice_id *of_match;
+ int (*bind)(struct udevice *dev);
+ int (*probe)(struct udevice *dev);
+ int (*remove)(struct udevice *dev);
+ int (*unbind)(struct udevice *dev);
+ int (*ofdata_to_platdata)(struct udevice *dev);
int priv_auto_alloc_size;
int platdata_auto_alloc_size;
const void *ops; /* driver-specific operations */
* @dev Device to check
* @return platform data, or NULL if none
*/
-void *dev_get_platdata(struct device *dev);
+void *dev_get_platdata(struct udevice *dev);
/**
* dev_get_priv() - Get the private data for a device
* @dev Device to check
* @return private data, or NULL if none
*/
-void *dev_get_priv(struct device *dev);
+void *dev_get_priv(struct udevice *dev);
#endif
*/
struct uclass_driver *lists_uclass_lookup(enum uclass_id id);
-int lists_bind_drivers(struct device *parent);
+/**
+ * lists_bind_drivers() - search for and bind all drivers to parent
+ *
+ * This searches the U_BOOT_DEVICE() structures and creates new devices for
+ * each one. The devices will have @parent as their parent.
+ *
+ * @parent: parent driver (root)
+ * @early_only: If true, bind only drivers with the DM_INIT_F flag. If false
+ * bind all drivers.
+ */
+int lists_bind_drivers(struct udevice *parent);
-int lists_bind_fdt(struct device *parent, const void *blob, int offset);
+/**
+ * lists_bind_fdt() - bind a device tree node
+ *
+ * This creates a new device bound to the given device tree node, with
+ * @parent as its parent.
+ *
+ * @parent: parent driver (root)
+ * @blob: device tree blob
+ * @offset: offset of this device tree node
+ */
+int lists_bind_fdt(struct udevice *parent, const void *blob, int offset);
#endif
#ifndef _DM_ROOT_H_
#define _DM_ROOT_H_
-struct device;
+struct udevice;
/**
* dm_root() - Return pointer to the top of the driver tree
*
* @return pointer to root device, or NULL if not inited yet
*/
-struct device *dm_root(void);
+struct udevice *dm_root(void);
/**
* dm_scan_platdata() - Scan all platform data and bind drivers
int dm_scan_fdt(const void *blob);
/**
- * dm_init() - Initialize Driver Model structures
+ * dm_init() - Initialise Driver Model structures
*
* This function will initialize roots of driver tree and class tree.
* This needs to be called before anything uses the DM
* @return 0 if OK, -ve on error
*/
struct test_ops {
- int (*ping)(struct device *dev, int pingval, int *pingret);
+ int (*ping)(struct udevice *dev, int pingval, int *pingret);
};
/* Operations that our test driver supports */
* @skip_post_probe: Skip uclass post-probe processing
*/
struct dm_test_state {
- struct device *root;
- struct device *testdev;
+ struct udevice *root;
+ struct udevice *testdev;
int fail_count;
int force_fail_alloc;
int skip_post_probe;
}
/* Declare ping methods for the drivers */
-int test_ping(struct device *dev, int pingval, int *pingret);
-int testfdt_ping(struct device *dev, int pingval, int *pingret);
+int test_ping(struct udevice *dev, int pingval, int *pingret);
+int testfdt_ping(struct udevice *dev, int pingval, int *pingret);
/**
* dm_check_operations() - Check that we can perform ping operations
* @priv: Pointer to private test information
* @return 0 if OK, -ve on error
*/
-int dm_check_operations(struct dm_test_state *dms, struct device *dev,
+int dm_check_operations(struct dm_test_state *dms, struct udevice *dev,
uint32_t base, struct dm_test_priv *priv);
/**
* @return the uclass pointer of a child at the given index or
* return NULL on error.
*/
-int uclass_find_device(enum uclass_id id, int index, struct device **devp);
+int uclass_find_device(enum uclass_id id, int index, struct udevice **devp);
/**
* uclass_bind_device() - Associate device with a uclass
* @dev: Pointer to the device
* #return 0 on success, -ve on error
*/
-int uclass_bind_device(struct device *dev);
+int uclass_bind_device(struct udevice *dev);
/**
* uclass_unbind_device() - Deassociate device with a uclass
* @dev: Pointer to the device
* #return 0 on success, -ve on error
*/
-int uclass_unbind_device(struct device *dev);
+int uclass_unbind_device(struct udevice *dev);
/**
* uclass_post_probe_device() - Deal with a device that has just been probed
* @dev: Pointer to the device
* #return 0 on success, -ve on error
*/
-int uclass_post_probe_device(struct device *dev);
+int uclass_post_probe_device(struct udevice *dev);
/**
* uclass_pre_remove_device() - Handle a device which is about to be removed
* @dev: Pointer to the device
* #return 0 on success, -ve on error
*/
-int uclass_pre_remove_device(struct device *dev);
+int uclass_pre_remove_device(struct udevice *dev);
/**
* uclass_find() - Find uclass by its id
* @priv: Private data for this uclass
* @uc_drv: The driver for the uclass itself, not to be confused with a
* 'struct driver'
- * dev_head: List of devices in this uclass (devices are attached to their
+ * @dev_head: List of devices in this uclass (devices are attached to their
* uclass when their bind method is called)
* @sibling_node: Next uclass in the linked list of uclasses
*/
struct list_head sibling_node;
};
-struct device;
+struct udevice;
/**
* struct uclass_driver - Driver for the uclass
struct uclass_driver {
const char *name;
enum uclass_id id;
- int (*post_bind)(struct device *dev);
- int (*pre_unbind)(struct device *dev);
- int (*post_probe)(struct device *dev);
- int (*pre_remove)(struct device *dev);
+ int (*post_bind)(struct udevice *dev);
+ int (*pre_unbind)(struct udevice *dev);
+ int (*post_probe)(struct udevice *dev);
+ int (*pre_remove)(struct udevice *dev);
int (*init)(struct uclass *class);
int (*destroy)(struct uclass *class);
int priv_auto_alloc_size;
/**
* uclass_get_device() - Get a uclass device based on an ID and index
*
+ * The device is probed to activate it ready for use.
+ *
* id: ID to look up
* @index: Device number within that uclass (0=first)
- * @ucp: Returns pointer to uclass (there is only one per for each ID)
+ * @devp: Returns pointer to device (there is only one per for each ID)
* @return 0 if OK, -ve on error
*/
-int uclass_get_device(enum uclass_id id, int index, struct device **ucp);
+int uclass_get_device(enum uclass_id id, int index, struct udevice **devp);
/**
* uclass_first_device() - Get the first device in a uclass
* @devp: Returns pointer to the first device in that uclass, or NULL if none
* @return 0 if OK (found or not found), -1 on error
*/
-int uclass_first_device(enum uclass_id id, struct device **devp);
+int uclass_first_device(enum uclass_id id, struct udevice **devp);
/**
* uclass_next_device() - Get the next device in a uclass
* to the next device in the same uclass, or NULL if none
* @return 0 if OK (found or not found), -1 on error
*/
-int uclass_next_device(struct device **devp);
+int uclass_next_device(struct udevice **devp);
/**
* uclass_foreach_dev() - Helper function to iteration through devices
* This creates a for() loop which works through the available devices in
* a uclass in order from start to end.
*
- * @pos: struct device * to hold the current device. Set to NULL when there
+ * @pos: struct udevice * to hold the current device. Set to NULL when there
* are no more devices.
- * uc: uclass to scan
+ * @uc: uclass to scan
*/
#define uclass_foreach_dev(pos, uc) \
for (pos = list_entry((&(uc)->dev_head)->next, typeof(*pos), \
--- /dev/null
+/*
+ * This header provides constants for most GPIO bindings.
+ *
+ * Most GPIO bindings include a flags cell as part of the GPIO specifier.
+ * In most cases, the format of the flags cell uses the standard values
+ * defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_GPIO_H
+#define _DT_BINDINGS_GPIO_GPIO_H
+
+#define GPIO_ACTIVE_HIGH 0
+#define GPIO_ACTIVE_LOW 1
+
+#endif
--- /dev/null
+/*
+ * This header provides constants for binding nvidia,tegra*-gpio.
+ *
+ * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
+ * provide names for this.
+ *
+ * The second cell contains standard flag values specified in gpio.h.
+ */
+
+#ifndef _DT_BINDINGS_GPIO_TEGRA_GPIO_H
+#define _DT_BINDINGS_GPIO_TEGRA_GPIO_H
+
+#include <dt-bindings/gpio/gpio.h>
+
+#define TEGRA_GPIO_BANK_ID_A 0
+#define TEGRA_GPIO_BANK_ID_B 1
+#define TEGRA_GPIO_BANK_ID_C 2
+#define TEGRA_GPIO_BANK_ID_D 3
+#define TEGRA_GPIO_BANK_ID_E 4
+#define TEGRA_GPIO_BANK_ID_F 5
+#define TEGRA_GPIO_BANK_ID_G 6
+#define TEGRA_GPIO_BANK_ID_H 7
+#define TEGRA_GPIO_BANK_ID_I 8
+#define TEGRA_GPIO_BANK_ID_J 9
+#define TEGRA_GPIO_BANK_ID_K 10
+#define TEGRA_GPIO_BANK_ID_L 11
+#define TEGRA_GPIO_BANK_ID_M 12
+#define TEGRA_GPIO_BANK_ID_N 13
+#define TEGRA_GPIO_BANK_ID_O 14
+#define TEGRA_GPIO_BANK_ID_P 15
+#define TEGRA_GPIO_BANK_ID_Q 16
+#define TEGRA_GPIO_BANK_ID_R 17
+#define TEGRA_GPIO_BANK_ID_S 18
+#define TEGRA_GPIO_BANK_ID_T 19
+#define TEGRA_GPIO_BANK_ID_U 20
+#define TEGRA_GPIO_BANK_ID_V 21
+#define TEGRA_GPIO_BANK_ID_W 22
+#define TEGRA_GPIO_BANK_ID_X 23
+#define TEGRA_GPIO_BANK_ID_Y 24
+#define TEGRA_GPIO_BANK_ID_Z 25
+#define TEGRA_GPIO_BANK_ID_AA 26
+#define TEGRA_GPIO_BANK_ID_BB 27
+#define TEGRA_GPIO_BANK_ID_CC 28
+#define TEGRA_GPIO_BANK_ID_DD 29
+#define TEGRA_GPIO_BANK_ID_EE 30
+#define TEGRA_GPIO_BANK_ID_FF 31
+
+#define TEGRA_GPIO(bank, offset) \
+ ((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
+
+#endif
--- /dev/null
+/*
+ * This header provides constants for the ARM GIC.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/* interrupt specific cell 0 */
+
+#define GIC_SPI 0
+#define GIC_PPI 1
+
+/*
+ * Interrupt specifier cell 2.
+ * The flaggs in irq.h are valid, plus those below.
+ */
+#define GIC_CPU_MASK_RAW(x) ((x) << 8)
+#define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1)
+
+#endif
--- /dev/null
+/*
+ * This header provides constants for most IRQ bindings.
+ *
+ * Most IRQ bindings include a flags cell as part of the IRQ specifier.
+ * In most cases, the format of the flags cell uses the standard values
+ * defined in this header.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_IRQ_H
+
+#define IRQ_TYPE_NONE 0
+#define IRQ_TYPE_EDGE_RISING 1
+#define IRQ_TYPE_EDGE_FALLING 2
+#define IRQ_TYPE_EDGE_BOTH (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
+#define IRQ_TYPE_LEVEL_HIGH 4
+#define IRQ_TYPE_LEVEL_LOW 8
+
+#endif
#define VFAT_MAXSEQ 9 /* Up to 9 of 13 2-byte UTF-16 entries */
#define PREFETCH_BLOCKS 2
-#define MAX_CLUSTSIZE 65536
+#ifndef CONFIG_FS_FAT_MAX_CLUSTSIZE
+#define CONFIG_FS_FAT_MAX_CLUSTSIZE 65536
+#endif
+#define MAX_CLUSTSIZE CONFIG_FS_FAT_MAX_CLUSTSIZE
+
#define DIRENTSPERBLOCK (mydata->sect_size / sizeof(dir_entry))
#define DIRENTSPERCLUST ((mydata->clust_size * mydata->sect_size) / \
sizeof(dir_entry))
const char *prop, const u32 dflt);
u32 fdt_getprop_u32_default(const void *fdt, const char *path,
const char *prop, const u32 dflt);
-int fdt_chosen(void *fdt, int force);
-int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end, int force);
+int fdt_chosen(void *fdt);
+int fdt_initrd(void *fdt, ulong initrd_start, ulong initrd_end);
void do_fixup_by_path(void *fdt, const char *path, const char *prop,
const void *val, int len, int create);
void do_fixup_by_path_u32(void *fdt, const char *path, const char *prop,
#ifndef _HASH_H
#define _HASH_H
+/*
+ * Maximum digest size for all algorithms we support. Having this value
+ * avoids a malloc() or C99 local declaration in common/cmd_hash.c.
+ */
+#define HASH_MAX_DIGEST_SIZE 32
+
+enum {
+ HASH_FLAG_VERIFY = 1 << 0, /* Enable verify mode */
+ HASH_FLAG_ENV = 1 << 1, /* Allow env vars */
+};
+
+#ifndef USE_HOSTCC
#if defined(CONFIG_SHA1SUM_VERIFY) || defined(CONFIG_CRC32_VERIFY)
#define CONFIG_HASH_VERIFY
#endif
int size);
};
-/*
- * Maximum digest size for all algorithms we support. Having this value
- * avoids a malloc() or C99 local declaration in common/cmd_hash.c.
- */
-#define HASH_MAX_DIGEST_SIZE 32
-
-enum {
- HASH_FLAG_VERIFY = 1 << 0, /* Enable verify mode */
- HASH_FLAG_ENV = 1 << 1, /* Allow env vars */
-};
-
/**
* hash_command: Process a hash command for a particular algorithm
*
* @return 0 if ok, -EPROTONOSUPPORT for an unknown algorithm.
*/
int hash_lookup_algo(const char *algo_name, struct hash_algo **algop);
+
+/**
+ * hash_show() - Print out a hash algorithm and value
+ *
+ * You will get a message like this (without a newline at the end):
+ *
+ * "sha1 for 9eb3337c ... 9eb3338f ==> 7942ef1df479fd3130f716eb9613d107dab7e257"
+ *
+ * @algo: Algorithm used for hash
+ * @addr: Address of data that was hashed
+ * @len: Length of data that was hashed
+ * @output: Hash value to display
+ */
+void hash_show(struct hash_algo *algo, ulong addr, ulong len,
+ uint8_t *output);
+#endif /* !USE_HOSTCC */
#endif
#endif /* USE_HOSTCC */
#if defined(CONFIG_FIT)
+#include <hash.h>
#include <libfdt.h>
#include <fdt_support.h>
# ifdef CONFIG_SPL_BUILD
#ifndef USE_HOSTCC
/* Image format types, returned by _get_format() routine */
#define IMAGE_FORMAT_INVALID 0x00
+#if defined(CONFIG_IMAGE_FORMAT_LEGACY)
#define IMAGE_FORMAT_LEGACY 0x01 /* legacy image_header based format */
+#endif
#define IMAGE_FORMAT_FIT 0x02 /* new, libfdt based format */
#define IMAGE_FORMAT_ANDROID 0x03 /* Android boot image */
int boot_get_ramdisk(int argc, char * const argv[], bootm_headers_t *images,
uint8_t arch, ulong *rd_start, ulong *rd_end);
+#endif
/**
* fit_image_load() - load an image from a FIT
* out progress messages, checking the type/arch/os and optionally copying it
* to the right load address.
*
+ * The property to look up is defined by image_type.
+ *
* @param images Boot images structure
- * @param prop_name Property name to look up (FIT_..._PROP)
* @param addr Address of FIT in memory
* @param fit_unamep On entry this is the requested image name
* (e.g. "kernel@1") or NULL to use the default. On exit
* @param load_op Decribes what to do with the load address
* @param datap Returns address of loaded image
* @param lenp Returns length of loaded image
+ * @return node offset of image, or -ve error code on error
*/
-int fit_image_load(bootm_headers_t *images, const char *prop_name, ulong addr,
+int fit_image_load(bootm_headers_t *images, ulong addr,
const char **fit_unamep, const char **fit_uname_configp,
int arch, int image_type, int bootstage_id,
enum fit_load_op load_op, ulong *datap, ulong *lenp);
+#ifndef USE_HOSTCC
/**
* fit_get_node_from_config() - Look up an image a FIT by type
*
ulong getenv_bootm_low(void);
phys_size_t getenv_bootm_size(void);
phys_size_t getenv_bootm_mapsize(void);
-void memmove_wd(void *to, void *from, size_t len, ulong chunksz);
#endif
+void memmove_wd(void *to, void *from, size_t len, ulong chunksz);
static inline int image_check_magic(const image_header_t *hdr)
{
#define FIT_FDT_PROP "fdt"
#define FIT_DEFAULT_PROP "default"
-#define FIT_MAX_HASH_LEN 20 /* max(crc32_len(4), sha1_len(20)) */
+#define FIT_MAX_HASH_LEN HASH_MAX_DIGEST_SIZE
/* cmdline argument format parsing */
int fit_parse_conf(const char *spec, ulong addr_curr,
};
#if IMAGE_ENABLE_VERIFY
-# include <rsa-checksum.h>
+# include <u-boot/rsa-checksum.h>
#endif
struct checksum_algo {
const char *name;
--- /dev/null
+/*
+ * Copyright (c) 2014 Google, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __IOTRACE_H
+#define __IOTRACE_H
+
+#include <linux/types.h>
+
+/*
+ * This file is designed to be included in arch/<arch>/include/asm/io.h.
+ * It redirects all IO access through a tracing/checksumming feature for
+ * testing purposes.
+ */
+
+#if defined(CONFIG_IO_TRACE) && !defined(IOTRACE_IMPL) && \
+ !defined(CONFIG_SPL_BUILD)
+
+#undef readl
+#define readl(addr) iotrace_readl((const void *)(addr))
+
+#undef writel
+#define writel(val, addr) iotrace_writel(val, (const void *)(addr))
+
+#undef readw
+#define readw(addr) iotrace_readw((const void *)(addr))
+
+#undef writew
+#define writew(val, addr) iotrace_writew(val, (const void *)(addr))
+
+#undef readb
+#define readb(addr) iotrace_readb((const void *)(addr))
+
+#undef writeb
+#define writeb(val, addr) iotrace_writeb(val, (const void *)(addr))
+
+#endif
+
+/* Tracing functions which mirror their io.h counterparts */
+u32 iotrace_readl(const void *ptr);
+void iotrace_writel(ulong value, const void *ptr);
+u16 iotrace_readw(const void *ptr);
+void iotrace_writew(ulong value, const void *ptr);
+u8 iotrace_readb(const void *ptr);
+void iotrace_writeb(ulong value, const void *ptr);
+
+/**
+ * iotrace_reset_checksum() - Reset the iotrace checksum
+ */
+void iotrace_reset_checksum(void);
+
+/**
+ * iotrace_get_checksum() - Get the current checksum value
+ *
+ * @return currect checksum value
+ */
+u32 iotrace_get_checksum(void);
+
+/**
+ * iotrace_set_enabled() - Set whether iotracing is enabled or not
+ *
+ * This controls whether the checksum is updated and a trace record added
+ * for each I/O access.
+ *
+ * @enable: true to enable iotracing, false to disable
+ */
+void iotrace_set_enabled(int enable);
+
+/**
+ * iotrace_get_enabled() - Get whether iotracing is enabled or not
+ *
+ * @return true if enabled, false if disabled
+ */
+int iotrace_get_enabled(void);
+
+/**
+ * iotrace_set_buffer() - Set position and size of iotrace buffer
+ *
+ * Defines where the iotrace buffer goes, and resets the output pointer to
+ * the start of the buffer.
+ *
+ * The buffer can be 0 size in which case the checksum is updated but no
+ * trace records are writen. If the buffer is exhausted, the offset will
+ * continue to increase but not new data will be written.
+ *
+ * @start: Start address of buffer
+ * @size: Size of buffer in bytes
+ */
+void iotrace_set_buffer(ulong start, ulong size);
+
+/**
+ * iotrace_get_buffer() - Get buffer information
+ *
+ * @start: Returns start address of buffer
+ * @size: Returns size of buffer in bytes
+ * @offset: Returns the byte offset where the next output trace record will
+ * @count: Returns the number of trace records recorded
+ * be written (or would be if the buffer was large enough)
+ */
+void iotrace_get_buffer(ulong *start, ulong *size, ulong *offset, ulong *count);
+
+#endif /* __IOTRACE_H */
#if defined(CONFIG_MPC8272_FAMILY)
#ifdef CONFIG_MPC8247
#define CPU_ID_STR "MPC8247"
-#elif defined CONFIG_MPC8248
-#define CPU_ID_STR "MPC8248"
-#elif defined CONFIG_MPC8271
-#define CPU_ID_STR "MPC8271"
#else
#define CPU_ID_STR "MPC8272"
#endif
#include <part_efi.h>
/* disk/part_efi.c */
int get_partition_info_efi (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
+/**
+ * get_partition_info_efi_by_name() - Find the specified GPT partition table entry
+ *
+ * @param dev_desc - block device descriptor
+ * @param gpt_name - the specified table entry name
+ * @param info - returns the disk partition info
+ *
+ * @return - '0' on match, '-1' on no match, otherwise error
+ */
+int get_partition_info_efi_by_name(block_dev_desc_t *dev_desc,
+ const char *name, disk_partition_t *info);
void print_part_efi (block_dev_desc_t *dev_desc);
int test_part_efi (block_dev_desc_t *dev_desc);
PFUZE100_FABID = 0x04,
PFUZE100_SW1ABVOL = 0x20,
+ PFUZE100_SW1ABSTBY = 0x21,
+ PUZE_100_SW1ABCONF = 0x24,
PFUZE100_SW1CVOL = 0x2e,
+ PFUZE100_SW1CSTBY = 0x2f,
+ PFUZE100_SW1CCONF = 0x32,
PFUZE100_SW2VOL = 0x35,
PFUZE100_SW3AVOL = 0x3c,
PFUZE100_SW3BVOL = 0x43,
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef __H_
+#ifndef _TPS6586X_H_
#define _TPS6586X_H_
enum {
#include <errno.h>
#include <image.h>
-#include <sha1.h>
-#include <sha256.h>
+#include <u-boot/sha1.h>
+#include <u-boot/sha256.h>
extern const uint8_t padding_sha256_rsa4096[];
extern const uint8_t padding_sha256_rsa2048[];
*
* @info: Specifies key and FIT information
* @keydest: Destination FDT blob for public key data
- * @return: 0, on success, -ve on error
+ * @return: 0, on success, -ENOSPC if the keydest FDT blob ran out of space,
+ other -ve value on error
*/
int rsa_add_verify_data(struct image_sign_info *info, void *keydest);
#else
obj-y += crc7.o
obj-y += crc8.o
obj-y += crc16.o
+obj-$(CONFIG_FIT) += fdtdec_common.o
+obj-$(CONFIG_OF_CONTROL) += fdtdec_common.o
obj-$(CONFIG_OF_CONTROL) += fdtdec.o
obj-$(CONFIG_TEST_FDTDEC) += fdtdec_test.o
obj-$(CONFIG_GZIP) += gunzip.o
return fdtdec_get_addr_size(blob, node, prop_name, NULL);
}
-s32 fdtdec_get_int(const void *blob, int node, const char *prop_name,
- s32 default_val)
-{
- const s32 *cell;
- int len;
-
- debug("%s: %s: ", __func__, prop_name);
- cell = fdt_getprop(blob, node, prop_name, &len);
- if (cell && len >= sizeof(s32)) {
- s32 val = fdt32_to_cpu(cell[0]);
-
- debug("%#x (%d)\n", val, val);
- return val;
- }
- debug("(not found)\n");
- return default_val;
-}
-
uint64_t fdtdec_get_uint64(const void *blob, int node, const char *prop_name,
uint64_t default_val)
{
return 0;
}
-#else
-#include "libfdt.h"
-#include "fdt_support.h"
-
-int fdtdec_get_int(const void *blob, int node, const char *prop_name,
- int default_val)
-{
- const int *cell;
- int len;
-
- cell = fdt_getprop_w((void *)blob, node, prop_name, &len);
- if (cell && len >= sizeof(int)) {
- int val = fdt32_to_cpu(cell[0]);
-
- return val;
- }
- return default_val;
-}
#endif
--- /dev/null
+/*
+ * Copyright (c) 2014
+ * Heiko Schocher, DENX Software Engineering, hs@denx.de.
+ *
+ * Based on lib/fdtdec.c:
+ * Copyright (c) 2011 The Chromium OS Authors.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef USE_HOSTCC
+#include <common.h>
+#include <libfdt.h>
+#include <fdtdec.h>
+#else
+#include "libfdt.h"
+#include "fdt_support.h"
+
+#define debug(...)
+#endif
+
+int fdtdec_get_int(const void *blob, int node, const char *prop_name,
+ int default_val)
+{
+ const int *cell;
+ int len;
+
+ debug("%s: %s: ", __func__, prop_name);
+ cell = fdt_getprop(blob, node, prop_name, &len);
+ if (cell && len >= sizeof(int)) {
+ int val = fdt32_to_cpu(cell[0]);
+
+ debug("%#x (%d)\n", val, val);
+ return val;
+ }
+ debug("(not found)\n");
+ return default_val;
+}
{
const char *p = fdt_string(fdt, stroffset);
- return (strlen(p) == len) && (memcmp(p, s, len) == 0);
+ return (strnlen(p, len + 1) == len) && (memcmp(p, s, len) == 0);
}
int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size)
#include <linux/string.h>
#include <malloc.h>
-static void *SzAlloc(void *p, size_t size) { p = p; return malloc(size); }
-static void SzFree(void *p, void *address) { p = p; free(address); }
+static void *SzAlloc(void *p, size_t size) { return malloc(size); }
+static void SzFree(void *p, void *address) { free(address); }
int lzmaBuffToBuffDecompress (unsigned char *outStream, SizeT *uncompressedSize,
unsigned char *inStream, SizeT length)
#else
#include "fdt_host.h"
#endif
-#include <rsa.h>
-#include <sha1.h>
-#include <sha256.h>
+#include <u-boot/rsa.h>
+#include <u-boot/sha1.h>
+#include <u-boot/sha256.h>
/* PKCS 1.5 paddings as described in the RSA PKCS#1 v2.1 standard. */
if (parent == -FDT_ERR_NOTFOUND) {
parent = fdt_add_subnode(keydest, 0, FIT_SIG_NODENAME);
if (parent < 0) {
- fprintf(stderr, "Couldn't create signature node: %s\n",
- fdt_strerror(parent));
- return -EINVAL;
+ ret = parent;
+ if (ret != -FDT_ERR_NOSPACE) {
+ fprintf(stderr, "Couldn't create signature node: %s\n",
+ fdt_strerror(parent));
+ }
}
}
+ if (ret)
+ goto done;
/* Either create or overwrite the named key node */
snprintf(name, sizeof(name), "key-%s", info->keyname);
if (node == -FDT_ERR_NOTFOUND) {
node = fdt_add_subnode(keydest, parent, name);
if (node < 0) {
- fprintf(stderr, "Could not create key subnode: %s\n",
- fdt_strerror(node));
- return -EINVAL;
+ ret = node;
+ if (ret != -FDT_ERR_NOSPACE) {
+ fprintf(stderr, "Could not create key subnode: %s\n",
+ fdt_strerror(node));
+ }
}
} else if (node < 0) {
fprintf(stderr, "Cannot select keys parent: %s\n",
fdt_strerror(node));
- return -ENOSPC;
+ ret = node;
}
- ret = fdt_setprop_string(keydest, node, "key-name-hint",
+ if (!ret) {
+ ret = fdt_setprop_string(keydest, node, "key-name-hint",
info->keyname);
- ret |= fdt_setprop_u32(keydest, node, "rsa,num-bits", bits);
- ret |= fdt_setprop_u32(keydest, node, "rsa,n0-inverse", n0_inv);
- ret |= fdt_add_bignum(keydest, node, "rsa,modulus", modulus, bits);
- ret |= fdt_add_bignum(keydest, node, "rsa,r-squared", r_squared, bits);
- ret |= fdt_setprop_string(keydest, node, FIT_ALGO_PROP,
- info->algo->name);
+ }
+ if (!ret)
+ ret = fdt_setprop_u32(keydest, node, "rsa,num-bits", bits);
+ if (!ret)
+ ret = fdt_setprop_u32(keydest, node, "rsa,n0-inverse", n0_inv);
+ if (!ret) {
+ ret = fdt_add_bignum(keydest, node, "rsa,modulus", modulus,
+ bits);
+ }
+ if (!ret) {
+ ret = fdt_add_bignum(keydest, node, "rsa,r-squared", r_squared,
+ bits);
+ }
+ if (!ret) {
+ ret = fdt_setprop_string(keydest, node, FIT_ALGO_PROP,
+ info->algo->name);
+ }
if (info->require_keys) {
- fdt_setprop_string(keydest, node, "required",
- info->require_keys);
+ ret = fdt_setprop_string(keydest, node, "required",
+ info->require_keys);
}
+done:
BN_free(modulus);
BN_free(r_squared);
if (ret)
- return -EIO;
+ return ret == -FDT_ERR_NOSPACE ? -ENOSPC : -EIO;
return 0;
}
#include "mkimage.h"
#include <fdt_support.h>
#endif
-#include <rsa.h>
-#include <sha1.h>
-#include <sha256.h>
+#include <u-boot/rsa.h>
+#include <u-boot/sha1.h>
+#include <u-boot/sha256.h>
#define UINT64_MULT32(v, multby) (((uint64_t)(v)) * ((uint32_t)(multby)))
#include <string.h>
#endif /* USE_HOSTCC */
#include <watchdog.h>
-#include "sha1.h"
+#include <u-boot/sha1.h>
/*
* 32-bit integer manipulation macros (big endian)
#include <string.h>
#endif /* USE_HOSTCC */
#include <watchdog.h>
-#include <sha256.h>
+#include <u-boot/sha256.h>
/*
* 32-bit integer manipulation macros (big endian)
#include <common.h>
#include <stdarg.h>
-#include <sha1.h>
+#include <u-boot/sha1.h>
#include <tpm.h>
#include <asm/unaligned.h>
ln -s ${LNPREFIX}arch-${soc} asm/arch
fi
-if [ "${arch}" = "arm" ] ; then
- rm -f asm/proc
- ln -s ${LNPREFIX}proc-armv asm/proc
-fi
-
if [ -z "$KBUILD_SRC" ] ; then
cd ${srctree}/include
fi
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-# (C) Copyright 2008 Freescale Semiconductor
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PAD_TO := 0xfff04000
-
-nandobj := $(objtree)/nand_spl/
-
-LDSCRIPT= $(srctree)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
- $(LDFLAGS) $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS = start.o ticks.o
-COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o spl_minimal.o \
- time.o cache.o
-
-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-
-# create symbolic links for common files
-
-$(obj)/start.S:
- ln -sf $(srctree)/arch/powerpc/cpu/mpc83xx/start.S $@
-
-$(obj)/nand_boot_fsl_elbc.c:
- ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
-
-$(obj)/sdram.c:
- ln -sf $(srctree)/board/$(BOARDDIR)/sdram.c $@
-
-$(obj)/$(BOARD).c:
- ln -sf $(srctree)/board/$(BOARDDIR)/$(BOARD).c $@
-
-$(obj)/ns16550.c:
- ln -sf $(srctree)/drivers/serial/ns16550.c $@
-
-$(obj)/spl_minimal.c:
- ln -sf $(srctree)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $@
-
-$(obj)/cache.c:
- ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
-
-$(obj)/time.c:
- ln -sf $(srctree)/arch/powerpc/lib/time.c $@
-
-$(obj)/ticks.S:
- ln -sf $(srctree)/arch/powerpc/lib/ticks.S $@
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
- . = 0xfff00000;
- .text : {
- *(.text*)
- . = ALIGN(16);
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- . = ALIGN(8);
- .data : {
- *(.data*)
- *(.sdata*)
- _GOT2_TABLE_ = .;
- KEEP(*(.got2))
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-
- . = ALIGN(8);
- __bss_start = .;
- .bss (NOLOAD) : {
- *(.*bss)
- }
- __bss_end = .;
-}
-ENTRY(_start)
-ASSERT(__bss_end <= 0xfff01000, "NAND bootstrap too big");
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# Copyright 2009-2011 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
-PAD_TO := 0xfff01000
-
-nandobj := $(objtree)/nand_spl/
-
-LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
-LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
- $(LDFLAGS) $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS = start.o resetvec.o
-COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
- nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
-
-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
- -ansi -D__ASSEMBLY__ -P - <$< >$@
-
-# create symbolic links for common files
-
-$(obj)/cache.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
-
-$(obj)/cpu_init_early.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
-
-$(obj)/spl_minimal.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
-
-$(obj)/fsl_law.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
-
-$(obj)/law.c:
- @rm -f $@
- ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
-
-$(obj)/nand_boot_fsl_elbc.c:
- @rm -f $@
- ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
-
-$(obj)/ns16550.c:
- @rm -f $@
- ln -sf $(srctree)/drivers/serial/ns16550.c $@
-
-$(obj)/resetvec.S:
- @rm -f $@
- ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
-
-$(obj)/start.S:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@
-
-$(obj)/tlb.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/tlb.c $@
-
-$(obj)/tlb_table.c:
- @rm -f $@
- ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
+++ /dev/null
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-
-u32 sysclk_tbl[] = {
- 33333000, 39999600, 49999500, 66666000,
- 83332500, 99999000, 133332000, 166665000
-};
-
-void board_init_f(ulong bootflag)
-{
- int px_spd;
- u32 plat_ratio, bus_clk, sys_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
- /* for FPGA */
- set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
- set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
-#else
-#error CONFIG_SYS_BR3_PRELIM, CONFIG_SYS_OR3_PRELIM must be defined
-#endif
-
- /* initialize selected port with appropriate baud rate */
- px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
- sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK];
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- bus_clk = sys_clk * plat_ratio / 2;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
- CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# Copyright 2009-2011 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
-PAD_TO := 0xfff01000
-
-nandobj := $(objtree)/nand_spl/
-
-LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
-LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
- $(LDFLAGS) $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS = start.o resetvec.o
-COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
- nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
-
-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
- -ansi -D__ASSEMBLY__ -P - <$< >$@
-
-# create symbolic links for common files
-
-$(obj)/cache.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
-
-$(obj)/cpu_init_early.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
-
-$(obj)/spl_minimal.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
-
-$(obj)/fsl_law.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
-
-$(obj)/law.c:
- @rm -f $@
- ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
-
-$(obj)/nand_boot_fsl_elbc.c:
- @rm -f $@
- ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
-
-$(obj)/ns16550.c:
- @rm -f $@
- ln -sf $(srctree)/drivers/serial/ns16550.c $@
-
-$(obj)/resetvec.S:
- @rm -f $@
- ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
-
-$(obj)/start.S:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@
-
-$(obj)/tlb.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/tlb.c $@
-
-$(obj)/tlb_table.c:
- @rm -f $@
- ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
+++ /dev/null
-/*
- * Copyright 2009 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-#include <common.h>
-#include <mpc85xx.h>
-#include <asm/io.h>
-#include <ns16550.h>
-#include <nand.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/fsl_law.h>
-
-#define SYSCLK_66 66666666
-
-DECLARE_GLOBAL_DATA_PTR;
-
-void board_init_f(ulong bootflag)
-{
- uint plat_ratio, bus_clk, sys_clk;
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-
- sys_clk = SYSCLK_66;
-
- plat_ratio = gur->porpllsr & 0x0000003e;
- plat_ratio >>= 1;
- bus_clk = plat_ratio * sys_clk;
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
-
- /* copy code to DDR and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
- CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-#
-# Copyright 2009-2011 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-CONFIG_SYS_TEXT_BASE_SPL := 0xfff00000
-PAD_TO := 0xfff01000
-
-nandobj := $(objtree)/nand_spl/
-
-LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
-LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
- $(LDFLAGS) $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS = start.o resetvec.o
-COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
- nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
-
-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
- -ansi -D__ASSEMBLY__ -P - <$< >$@
-
-# create symbolic links for common files
-
-$(obj)/cache.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
-
-$(obj)/cpu_init_early.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/cpu_init_early.c $@
-
-$(obj)/spl_minimal.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/spl_minimal.c $@
-
-$(obj)/fsl_law.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
-
-$(obj)/law.c:
- @rm -f $@
- ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
-
-$(obj)/nand_boot_fsl_elbc.c:
- @rm -f $@
- ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
-
-$(obj)/ns16550.c:
- @rm -f $@
- ln -sf $(srctree)/drivers/serial/ns16550.c $@
-
-$(obj)/resetvec.S:
- @rm -f $@
- ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
-
-$(obj)/start.S:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/start.S $@
-
-$(obj)/tlb.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc85xx/tlb.c $@
-
-$(obj)/tlb_table.c:
- @rm -f $@
- ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
+++ /dev/null
-/*
- * Copyright 2009-2010 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-
-u32 sysclk_tbl[] = {
- 33333000, 39999600, 49999500, 66666000,
- 83332500, 99999000, 133332000, 166665000
-};
-
-void board_init_f(ulong bootflag)
-{
- int px_spd;
- u32 plat_ratio, bus_clk, sys_clk;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
-#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
- /* for FPGA */
- set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
- set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
-#else
-#error CONFIG_SYS_BR3_PRELIM, CONFIG_SYS_OR3_PRELIM must be defined
-#endif
-
- /* initialize selected port with appropriate baud rate */
- px_spd = in_8((unsigned char *)(PIXIS_BASE + PIXIS_SPD));
- sys_clk = sysclk_tbl[px_spd & PIXIS_SPD_SYSCLK_MASK];
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- bus_clk = sys_clk * plat_ratio / 2;
-
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
-
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
- CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
+++ /dev/null
-#
-# Copyright 2010-2011 Freescale Semiconductor, Inc.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-PAD_TO := 0xfff01000
-
-nandobj := $(objtree)/nand_spl/
-
-LDSCRIPT= $(srctree)/$(CPUDIR)/u-boot-nand_spl.lds
-LDFLAGS := -T $(nandobj)u-boot-nand_spl.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
- $(LDFLAGS) $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS = start.o resetvec.o
-COBJS = cache.o cpu_init_early.o spl_minimal.o fsl_law.o law.o \
- nand_boot.o nand_boot_fsl_elbc.o ns16550.o tlb.o tlb_table.o
-
-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot-nand_spl.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)u-boot-nand_spl.lds: $(LDSCRIPT)
- $(CPP) $(cpp_flags) $(LDPPFLAGS) -I$(nandobj)/board/$(BOARDDIR) \
- -ansi -D__ASSEMBLY__ -P - <$< >$@
-
-# create symbolic links for common files
-
-$(obj)/cache.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/lib/cache.c $@
-
-$(obj)/cpu_init_early.c:
- @rm -f $@
- ln -sf $(srctree)/$(CPUDIR)/cpu_init_early.c $@
-
-$(obj)/spl_minimal.c:
- @rm -f $@
- ln -sf $(srctree)/$(CPUDIR)/spl_minimal.c $@
-
-$(obj)/fsl_law.c:
- @rm -f $@
- ln -sf $(srctree)/arch/powerpc/cpu/mpc8xxx/law.c $@
-
-$(obj)/law.c:
- @rm -f $@
- ln -sf $(srctree)/board/$(BOARDDIR)/law.c $@
-
-$(obj)/nand_boot_fsl_elbc.c:
- @rm -f $@
- ln -sf $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
-
-$(obj)/ns16550.c:
- @rm -f $@
- ln -sf $(srctree)/drivers/serial/ns16550.c $@
-
-$(obj)/resetvec.S:
- @rm -f $@
- ln -s $(srctree)/$(CPUDIR)/resetvec.S $@
-
-$(obj)/start.S:
- @rm -f $@
- ln -sf $(srctree)/$(CPUDIR)/start.S $@
-
-$(obj)/tlb.c:
- @rm -f $@
- ln -sf $(srctree)/$(CPUDIR)/tlb.c $@
-
-$(obj)/tlb_table.c:
- @rm -f $@
- ln -sf $(srctree)/board/$(BOARDDIR)/tlb.c $@
+++ /dev/null
-/*
- * Copyright 2010-2011 Freescale Semiconductor, Inc.
- * Author: Roy Zang <tie-fei.zang@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <ns16550.h>
-#include <asm/io.h>
-#include <nand.h>
-#include <asm/fsl_law.h>
-#include <fsl_ddr_sdram.h>
-#include <asm/global_data.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-/* Fixed sdram init -- doesn't use serial presence detect. */
-void sdram_init(void)
-{
- struct ccsr_ddr __iomem *ddr =
- (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
-
- set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
-
- __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
- __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);
- __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds);
- __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config);
- __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3);
- __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0);
- __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1);
- __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_CONTROL2, &ddr->sdram_cfg_2);
- __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode);
- __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2);
- __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval);
- __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init);
- __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl);
- __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4);
- __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5);
- __raw_writel(CONFIG_SYS_DDR_ZQ_CNTL, &ddr->ddr_zq_cntl);
- __raw_writel(CONFIG_SYS_DDR_WRLVL_CNTL, &ddr->ddr_wrlvl_cntl);
- __raw_writel(CONFIG_SYS_DDR_CDR_1, &ddr->ddr_cdr1);
- __raw_writel(CONFIG_SYS_DDR_CDR_2, &ddr->ddr_cdr2);
- /* Set, but do not enable the memory */
- __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg);
-
- asm volatile("sync;isync");
- udelay(500);
-
- /* Let the controller go */
- out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN);
-}
-
-void board_init_f(ulong bootflag)
-{
- u32 plat_ratio;
- ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
-
- /* initialize selected port with appropriate baud rate */
- plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
- plat_ratio >>= 1;
- gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
- NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
- gd->bus_clk / 16 / CONFIG_BAUDRATE);
-
- puts("\nNAND boot... ");
- /* Initialize the DDR3 */
- sdram_init();
- /* copy code to RAM and jump to it - this should not return */
- /* NOTE - code has to be copied out of NAND buffer before
- * other blocks can be read.
- */
- relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, 0,
- CONFIG_SYS_NAND_U_BOOT_RELOC);
-}
-
-void board_init_r(gd_t *gd, ulong dest_addr)
-{
- nand_boot();
-}
-
-void putc(char c)
-{
- if (c == '\n')
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
-
- NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
-}
-
-void puts(const char *str)
-{
- while (*str)
- putc(*str++);
-}
+++ /dev/null
-#
-# (C) Copyright 2007
-# Stefan Roese, DENX Software Engineering, sr@denx.de.
-# (C) Copyright 2008 Freescale Semiconductor
-# (C) Copyright Sheldon Instruments, Inc. 2008
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-include $(srctree)/$(src)/config.mk
-
-nandobj := $(objtree)/nand_spl/
-
-LDSCRIPT= $(srctree)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-LDFLAGS := -T $(nandobj)u-boot.lds -Ttext $(CONFIG_SYS_TEXT_BASE_SPL) \
- $(LDFLAGS) $(LDFLAGS_FINAL)
-asflags-y += -DCONFIG_NAND_SPL
-ccflags-y += -DCONFIG_NAND_SPL
-
-SOBJS = start.o ticks.o
-COBJS = nand_boot_fsl_elbc.o $(BOARD).o sdram.o ns16550.o spl_minimal.o \
- time.o cache.o
-
-OBJS := $(addprefix $(obj)/,$(SOBJS) $(COBJS))
-__OBJS := $(SOBJS) $(COBJS)
-LNDIR := $(nandobj)board/$(BOARDDIR)
-
-targets += $(__OBJS)
-
-all: $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin
-
-$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) --pad-to=$(PAD_TO) -O binary $< $@
-
-$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
- $(OBJCOPY) $(OBJCOPYFLAGS) -O binary $< $@
-
-$(nandobj)u-boot-spl: $(OBJS) $(nandobj)u-boot.lds
- cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) $(PLATFORM_LIBS) \
- -Map $(nandobj)u-boot-spl.map -o $@
-
-$(nandobj)u-boot.lds: $(LDSCRIPT)
- $(CPP) $(cpp_flags) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - <$^ >$@
-
-# create symbolic links for common files
-
-$(obj)/start.S:
- @rm -f $@
- ln -s $(srctree)/arch/powerpc/cpu/mpc83xx/start.S $@
-
-$(obj)/nand_boot_fsl_elbc.c:
- @rm -f $@
- ln -s $(srctree)/nand_spl/nand_boot_fsl_elbc.c $@
-
-$(obj)/sdram.c:
- @rm -f $@
- ln -s $(srctree)/board/$(BOARDDIR)/sdram.c $@
-
-$(obj)/$(BOARD).c:
- @rm -f $@
- ln -s $(srctree)/board/$(BOARDDIR)/$(BOARD).c $@
-
-$(obj)/ns16550.c:
- @rm -f $@
- ln -s $(srctree)/drivers/serial/ns16550.c $@
-
-$(obj)/spl_minimal.c:
- @rm -f $@
- ln -s $(srctree)/arch/powerpc/cpu/mpc83xx/spl_minimal.c $@
-
-$(obj)/cache.c:
- @rm -f $@
- ln -s $(srctree)/arch/powerpc/lib/cache.c $@
-
-$(obj)/time.c:
- @rm -f $@
- ln -s $(srctree)/arch/powerpc/lib/time.c $@
-
-$(obj)/ticks.S:
- @rm -f $@
- ln -s $(srctree)/arch/powerpc/lib/ticks.S $@
+++ /dev/null
-ifdef CONFIG_NAND_LP
-PAD_TO = 0xFFF20000
-else
-PAD_TO = 0xFFF04000
-endif
+++ /dev/null
-/*
- * (C) Copyright 2006
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-OUTPUT_ARCH(powerpc)
-SECTIONS
-{
- . = 0xfff00000;
- .text : {
- *(.text*)
- . = ALIGN(16);
- *(.eh_frame)
- *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
- }
-
- . = ALIGN(8);
- .data : {
- *(.data*)
- *(.sdata*)
- _GOT2_TABLE_ = .;
- *(.got2)
- KEEP(*(.got))
- PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
- }
- __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
-
- . = ALIGN(8);
- __bss_start = .;
- .bss (NOLOAD) : { *(.*bss) }
- __bss_end = .;
-}
-ENTRY(_start)
-ASSERT(__bss_end <= 0xfff01000, "NAND bootstrap too big");
+++ /dev/null
-/*
- * (C) Copyright 2006-2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <nand.h>
-#include <asm/io.h>
-
-static int nand_ecc_pos[] = CONFIG_SYS_NAND_ECCPOS;
-
-#define ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \
- CONFIG_SYS_NAND_ECCSIZE)
-#define ECCTOTAL (ECCSTEPS * CONFIG_SYS_NAND_ECCBYTES)
-
-
-#if (CONFIG_SYS_NAND_PAGE_SIZE <= 512)
-/*
- * NAND command for small page NAND devices (512)
- */
-static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
-{
- struct nand_chip *this = mtd->priv;
- int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
-
- while (!this->dev_ready(mtd))
- ;
-
- /* Begin command latch cycle */
- this->cmd_ctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
- /* Set ALE and clear CLE to start address cycle */
- /* Column address */
- this->cmd_ctrl(mtd, offs, NAND_CTRL_ALE | NAND_CTRL_CHANGE);
- this->cmd_ctrl(mtd, page_addr & 0xff, NAND_CTRL_ALE); /* A[16:9] */
- this->cmd_ctrl(mtd, (page_addr >> 8) & 0xff,
- NAND_CTRL_ALE); /* A[24:17] */
-#ifdef CONFIG_SYS_NAND_4_ADDR_CYCLE
- /* One more address cycle for devices > 32MiB */
- this->cmd_ctrl(mtd, (page_addr >> 16) & 0x0f,
- NAND_CTRL_ALE); /* A[28:25] */
-#endif
- /* Latch in address */
- this->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
-
- /*
- * Wait a while for the data to be ready
- */
- while (!this->dev_ready(mtd))
- ;
-
- return 0;
-}
-#else
-/*
- * NAND command for large page NAND devices (2k)
- */
-static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd)
-{
- struct nand_chip *this = mtd->priv;
- int page_addr = page + block * CONFIG_SYS_NAND_PAGE_COUNT;
- void (*hwctrl)(struct mtd_info *mtd, int cmd,
- unsigned int ctrl) = this->cmd_ctrl;
-
- while (!this->dev_ready(mtd))
- ;
-
- /* Emulate NAND_CMD_READOOB */
- if (cmd == NAND_CMD_READOOB) {
- offs += CONFIG_SYS_NAND_PAGE_SIZE;
- cmd = NAND_CMD_READ0;
- }
-
- /* Shift the offset from byte addressing to word addressing. */
- if (this->options & NAND_BUSWIDTH_16)
- offs >>= 1;
-
- /* Begin command latch cycle */
- hwctrl(mtd, cmd, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
- /* Set ALE and clear CLE to start address cycle */
- /* Column address */
- hwctrl(mtd, offs & 0xff,
- NAND_CTRL_ALE | NAND_CTRL_CHANGE); /* A[7:0] */
- hwctrl(mtd, (offs >> 8) & 0xff, NAND_CTRL_ALE); /* A[11:9] */
- /* Row address */
- hwctrl(mtd, (page_addr & 0xff), NAND_CTRL_ALE); /* A[19:12] */
- hwctrl(mtd, ((page_addr >> 8) & 0xff),
- NAND_CTRL_ALE); /* A[27:20] */
-#ifdef CONFIG_SYS_NAND_5_ADDR_CYCLE
- /* One more address cycle for devices > 128MiB */
- hwctrl(mtd, (page_addr >> 16) & 0x0f,
- NAND_CTRL_ALE); /* A[31:28] */
-#endif
- /* Latch in address */
- hwctrl(mtd, NAND_CMD_READSTART,
- NAND_CTRL_CLE | NAND_CTRL_CHANGE);
- hwctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
-
- /*
- * Wait a while for the data to be ready
- */
- while (!this->dev_ready(mtd))
- ;
-
- return 0;
-}
-#endif
-
-static int nand_is_bad_block(struct mtd_info *mtd, int block)
-{
- struct nand_chip *this = mtd->priv;
-
- nand_command(mtd, block, 0, CONFIG_SYS_NAND_BAD_BLOCK_POS, NAND_CMD_READOOB);
-
- /*
- * Read one byte (or two if it's a 16 bit chip).
- */
- if (this->options & NAND_BUSWIDTH_16) {
- if (readw(this->IO_ADDR_R) != 0xffff)
- return 1;
- } else {
- if (readb(this->IO_ADDR_R) != 0xff)
- return 1;
- }
-
- return 0;
-}
-
-#if defined(CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST)
-static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
-{
- struct nand_chip *this = mtd->priv;
- u_char ecc_calc[ECCTOTAL];
- u_char ecc_code[ECCTOTAL];
- u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
- int i;
- int eccsize = CONFIG_SYS_NAND_ECCSIZE;
- int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
- int eccsteps = ECCSTEPS;
- uint8_t *p = dst;
-
- nand_command(mtd, block, page, 0, NAND_CMD_READOOB);
- this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
- nand_command(mtd, block, page, 0, NAND_CMD_READ0);
-
- /* Pick the ECC bytes out of the oob data */
- for (i = 0; i < ECCTOTAL; i++)
- ecc_code[i] = oob_data[nand_ecc_pos[i]];
-
-
- for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
- this->ecc.hwctl(mtd, NAND_ECC_READ);
- this->read_buf(mtd, p, eccsize);
- this->ecc.calculate(mtd, p, &ecc_calc[i]);
- this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
- }
-
- return 0;
-}
-#else
-static int nand_read_page(struct mtd_info *mtd, int block, int page, uchar *dst)
-{
- struct nand_chip *this = mtd->priv;
- u_char ecc_calc[ECCTOTAL];
- u_char ecc_code[ECCTOTAL];
- u_char oob_data[CONFIG_SYS_NAND_OOBSIZE];
- int i;
- int eccsize = CONFIG_SYS_NAND_ECCSIZE;
- int eccbytes = CONFIG_SYS_NAND_ECCBYTES;
- int eccsteps = ECCSTEPS;
- uint8_t *p = dst;
-
- nand_command(mtd, block, page, 0, NAND_CMD_READ0);
-
- for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
- this->ecc.hwctl(mtd, NAND_ECC_READ);
- this->read_buf(mtd, p, eccsize);
- this->ecc.calculate(mtd, p, &ecc_calc[i]);
- }
- this->read_buf(mtd, oob_data, CONFIG_SYS_NAND_OOBSIZE);
-
- /* Pick the ECC bytes out of the oob data */
- for (i = 0; i < ECCTOTAL; i++)
- ecc_code[i] = oob_data[nand_ecc_pos[i]];
-
- eccsteps = ECCSTEPS;
- p = dst;
-
- for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
- /* No chance to do something with the possible error message
- * from correct_data(). We just hope that all possible errors
- * are corrected by this routine.
- */
- this->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
- }
-
- return 0;
-}
-#endif /* #if defined(CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST) */
-
-static int nand_load(struct mtd_info *mtd, unsigned int offs,
- unsigned int uboot_size, uchar *dst)
-{
- unsigned int block, lastblock;
- unsigned int page;
-
- /*
- * offs has to be aligned to a page address!
- */
- block = offs / CONFIG_SYS_NAND_BLOCK_SIZE;
- lastblock = (offs + uboot_size - 1) / CONFIG_SYS_NAND_BLOCK_SIZE;
- page = (offs % CONFIG_SYS_NAND_BLOCK_SIZE) / CONFIG_SYS_NAND_PAGE_SIZE;
-
- while (block <= lastblock) {
- if (!nand_is_bad_block(mtd, block)) {
- /*
- * Skip bad blocks
- */
- while (page < CONFIG_SYS_NAND_PAGE_COUNT) {
- nand_read_page(mtd, block, page, dst);
- dst += CONFIG_SYS_NAND_PAGE_SIZE;
- page++;
- }
-
- page = 0;
- } else {
- lastblock++;
- }
-
- block++;
- }
-
- return 0;
-}
-
-/*
- * The main entry for NAND booting. It's necessary that SDRAM is already
- * configured and available since this code loads the main U-Boot image
- * from NAND into SDRAM and starts it from there.
- */
-void nand_boot(void)
-{
- struct nand_chip nand_chip;
- nand_info_t nand_info;
- __attribute__((noreturn)) void (*uboot)(void);
-
- /*
- * Init board specific nand support
- */
- nand_chip.select_chip = NULL;
- nand_info.priv = &nand_chip;
- nand_chip.IO_ADDR_R = nand_chip.IO_ADDR_W = (void __iomem *)CONFIG_SYS_NAND_BASE;
- nand_chip.dev_ready = NULL; /* preset to NULL */
- nand_chip.options = 0;
- board_nand_init(&nand_chip);
-
- if (nand_chip.select_chip)
- nand_chip.select_chip(&nand_info, 0);
-
- /*
- * Load U-Boot image from NAND into RAM
- */
- nand_load(&nand_info, CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
- (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
-
-#ifdef CONFIG_NAND_ENV_DST
- nand_load(&nand_info, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_NAND_ENV_DST);
-
-#ifdef CONFIG_ENV_OFFSET_REDUND
- nand_load(&nand_info, CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
- (uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
-#endif
-#endif
-
- if (nand_chip.select_chip)
- nand_chip.select_chip(&nand_info, -1);
-
- /*
- * Jump to U-Boot image
- */
- uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
- (*uboot)();
-}
+++ /dev/null
-/*
- * NAND boot for Freescale Enhanced Local Bus Controller, Flash Control Machine
- *
- * (C) Copyright 2006-2008
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Copyright (c) 2008 Freescale Semiconductor, Inc.
- * Author: Scott Wood <scottwood@freescale.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/fsl_lbc.h>
-#include <linux/mtd/nand.h>
-
-#define WINDOW_SIZE 8192
-
-static void nand_wait(void)
-{
- fsl_lbc_t *regs = LBC_BASE_ADDR;
-
- for (;;) {
- uint32_t status = in_be32(®s->ltesr);
-
- if (status == 1)
- return;
-
- if (status & 1) {
- puts("read failed (ltesr)\n");
- for (;;);
- }
- }
-}
-
-static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
-{
- fsl_lbc_t *regs = LBC_BASE_ADDR;
- uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
- const int large = CONFIG_SYS_NAND_OR_PRELIM & OR_FCM_PGS;
- const int block_shift = large ? 17 : 14;
- const int block_size = 1 << block_shift;
- const int page_size = large ? 2048 : 512;
- const int bad_marker = large ? page_size + 0 : page_size + 5;
- int fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT) | 2;
- int pos = 0;
-
- if (offs & (block_size - 1)) {
- puts("bad offset\n");
- for (;;);
- }
-
- if (large) {
- fmr |= FMR_ECCM;
- __raw_writel((NAND_CMD_READ0 << FCR_CMD0_SHIFT) |
- (NAND_CMD_READSTART << FCR_CMD1_SHIFT),
- ®s->fcr);
- __raw_writel(
- (FIR_OP_CW0 << FIR_OP0_SHIFT) |
- (FIR_OP_CA << FIR_OP1_SHIFT) |
- (FIR_OP_PA << FIR_OP2_SHIFT) |
- (FIR_OP_CW1 << FIR_OP3_SHIFT) |
- (FIR_OP_RBW << FIR_OP4_SHIFT),
- ®s->fir);
- } else {
- __raw_writel(NAND_CMD_READ0 << FCR_CMD0_SHIFT, ®s->fcr);
- __raw_writel(
- (FIR_OP_CW0 << FIR_OP0_SHIFT) |
- (FIR_OP_CA << FIR_OP1_SHIFT) |
- (FIR_OP_PA << FIR_OP2_SHIFT) |
- (FIR_OP_RBW << FIR_OP3_SHIFT),
- ®s->fir);
- }
-
- __raw_writel(0, ®s->fbcr);
-
- while (pos < uboot_size) {
- int i = 0;
- __raw_writel(offs >> block_shift, ®s->fbar);
-
- do {
- int j;
- unsigned int page_offs = (offs & (block_size - 1)) << 1;
-
- __raw_writel(~0, ®s->ltesr);
- __raw_writel(0, ®s->lteatr);
- __raw_writel(page_offs, ®s->fpar);
- __raw_writel(fmr, ®s->fmr);
- sync();
- __raw_writel(0, ®s->lsor);
- nand_wait();
-
- page_offs %= WINDOW_SIZE;
-
- /*
- * If either of the first two pages are marked bad,
- * continue to the next block.
- */
- if (i++ < 2 && buf[page_offs + bad_marker] != 0xff) {
- puts("skipping\n");
- offs = (offs + block_size) & ~(block_size - 1);
- pos &= ~(block_size - 1);
- break;
- }
-
- for (j = 0; j < page_size; j++)
- dst[pos + j] = buf[page_offs + j];
-
- pos += page_size;
- offs += page_size;
- } while ((offs & (block_size - 1)) && (pos < uboot_size));
- }
-}
-
-/*
- * The main entry for NAND booting. It's necessary that SDRAM is already
- * configured and available since this code loads the main U-Boot image
- * from NAND into SDRAM and starts it from there.
- */
-void nand_boot(void)
-{
- __attribute__((noreturn)) void (*uboot)(void);
-
- /*
- * Load U-Boot image from NAND into RAM
- */
- nand_load(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE,
- (uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
-
- /*
- * Jump to U-Boot image
- */
- puts("transfering control\n");
- /*
- * Clean d-cache and invalidate i-cache, to
- * make sure that no stale data is executed.
- */
- flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
- uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
- uboot();
-}
CDPStart();
break;
#endif
-#ifdef CONFIG_NETCONSOLE
+#if defined (CONFIG_NETCONSOLE) && !(CONFIG_SPL_BUILD)
case NETCONS:
NcStart();
break;
#endif
-#ifdef CONFIG_NETCONSOLE
+#if defined (CONFIG_NETCONSOLE) && !(CONFIG_SPL_BUILD)
nc_input_packet((uchar *)ip + IP_UDP_HDR_SIZE,
src_ip,
ntohs(ip->udp_dst),
$(real-objs-m:.o=.s): modkern_aflags := $(KBUILD_AFLAGS_MODULE) $(AFLAGS_MODULE)
quiet_cmd_as_s_S = CPP $(quiet_modtag) $@
-cmd_as_s_S = $(CPP) $(a_flags) -o $@ $<
+cmd_as_s_S = $(CPP) $(a_flags) -o $@ $<
$(obj)/%.s: $(src)/%.S FORCE
$(call if_changed_dep,as_s_S)
$(filter $(addprefix $(obj)/, \
$($(subst $(obj)/,,$(@:.o=-objs))) \
$($(subst $(obj)/,,$(@:.o=-y)))), $^)
-
+
quiet_cmd_link_multi-y = LD $@
cmd_link_multi-y = $(LD) $(ld_flags) -r -o $@ $(link_multi_deps) $(cmd_secanalysis)
$(call if_changed,host-cshlib)
targets += $(host-csingle) $(host-cmulti) $(host-cobjs)\
- $(host-cxxmulti) $(host-cxxobjs) $(host-cshlib) $(host-cshobjs)
-
+ $(host-cxxmulti) $(host-cxxobjs) $(host-cshlib) $(host-cshobjs)
# ---------------------------------------------------------------------------
# o if we encounter foo/ in $(obj-y), replace it by foo/built-in.o
# and add the directory to the list of dirs to descend into: $(subdir-y)
-# o if we encounter foo/ in $(obj-m), remove it from $(obj-m)
+# o if we encounter foo/ in $(obj-m), remove it from $(obj-m)
# and add the directory to the list of dirs to descend into: $(subdir-m)
# Determine modorder.
subdir-ym := $(sort $(subdir-y) $(subdir-m))
-# if $(foo-objs) exists, foo.o is a composite object
+# if $(foo-objs) exists, foo.o is a composite object
multi-used-y := $(sort $(foreach m,$(obj-y), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y))), $(m))))
multi-used-m := $(sort $(foreach m,$(obj-m), $(if $(strip $($(m:.o=-objs)) $($(m:.o=-y))), $(m))))
multi-used := $(multi-used-y) $(multi-used-m)
# These flags are needed for modversions and compiling, so we define them here
# already
-# $(modname_flags) #defines KBUILD_MODNAME as the name of the module it will
+# $(modname_flags) #defines KBUILD_MODNAME as the name of the module it will
# end up in (or would, if it gets compiled in)
# Note: Files that end up in two or more modules are compiled without the
# KBUILD_MODNAME definition. The reason is that any made-up name would
# Modified for U-Boot
dtc_cpp_flags = -Wp,-MD,$(depfile).pre.tmp -nostdinc \
-I$(srctree)/arch/$(ARCH)/dts \
+ -I$(srctree)/arch/$(ARCH)/dts/include \
-undef -D__DTS__
# Finds the multi-part object the current object will be linked into
# Commands useful for building a boot image
# ===========================================================================
-#
+#
# Use as following:
#
# target: source(s) FORCE
quiet_cmd_ld = LD $@
cmd_ld = $(LD) $(LDFLAGS) $(ldflags-y) $(LDFLAGS_$(@F)) \
- $(filter-out FORCE,$^) -o $@
+ $(filter-out FORCE,$^) -o $@
# Objcopy
# ---------------------------------------------------------------------------
cmd_xzmisc = (cat $(filter-out FORCE,$^) | \
xz --check=crc32 --lzma2=dict=1MiB) > $@ || \
(rm -f $@ ; false)
+
+# Additional commands for U-Boot
+#
+# mkimage
+# ---------------------------------------------------------------------------
+quiet_cmd_mkimage = MKIMAGE $@
+cmd_mkimage = $(objtree)/tools/mkimage $(MKIMAGEFLAGS_$(@F)) -d $< $@ \
+ $(if $(KBUILD_VERBOSE:1=), >/dev/null)
exit(2);
}
if (fstat(fd, &st) < 0) {
- fprintf(stderr, "fixdep: error fstat'ing depfile: ");
- perror(depfile);
- exit(2);
- }
+ fprintf(stderr, "fixdep: error fstat'ing depfile: ");
+ perror(depfile);
+ exit(2);
+ }
if (st.st_size == 0) {
fprintf(stderr,"fixdep: %s is empty\n",depfile);
close(fd);
static void add_new_symbol(struct symfile *sym, char * symname)
{
sym->symbollist =
- realloc(sym->symbollist, (sym->symbolcnt + 1) * sizeof(char *));
+ realloc(sym->symbollist, (sym->symbolcnt + 1) * sizeof(char *));
sym->symbollist[sym->symbolcnt++].name = strdup(symname);
}
char *p;
char *e;
if (((p = strstr(line, "EXPORT_SYMBOL_GPL")) != NULL) ||
- ((p = strstr(line, "EXPORT_SYMBOL")) != NULL)) {
+ ((p = strstr(line, "EXPORT_SYMBOL")) != NULL)) {
/* Skip EXPORT_SYMBOL{_GPL} */
while (isalnum(*p) || *p == '_')
p++;
static void singfunc(char * filename, char * line)
{
char *vec[200]; /* Enough for specific functions */
- int i, idx = 0;
- int startofsym = 1;
+ int i, idx = 0;
+ int startofsym = 1;
vec[idx++] = KERNELDOC;
vec[idx++] = DOCBOOK;
vec[idx++] = SHOWNOTFOUND;
- /* Split line up in individual parameters preceded by FUNCTION */
- for (i=0; line[i]; i++) {
- if (isspace(line[i])) {
- line[i] = '\0';
- startofsym = 1;
- continue;
- }
- if (startofsym) {
- startofsym = 0;
- vec[idx++] = FUNCTION;
- vec[idx++] = &line[i];
- }
- }
+ /* Split line up in individual parameters preceded by FUNCTION */
+ for (i=0; line[i]; i++) {
+ if (isspace(line[i])) {
+ line[i] = '\0';
+ startofsym = 1;
+ continue;
+ }
+ if (startofsym) {
+ startofsym = 0;
+ vec[idx++] = FUNCTION;
+ vec[idx++] = &line[i];
+ }
+ }
for (i = 0; i < idx; i++) {
- if (strcmp(vec[i], FUNCTION))
- continue;
+ if (strcmp(vec[i], FUNCTION))
+ continue;
consume_symbol(vec[i + 1]);
}
vec[idx++] = filename;
break;
case 'D':
while (*s && !isspace(*s)) s++;
- *s = '\0';
- symbolsonly(line+2);
- break;
+ *s = '\0';
+ symbolsonly(line+2);
+ break;
case 'F':
/* filename */
while (*s && !isspace(*s)) s++;
*s++ = '\0';
- /* function names */
+ /* function names */
while (isspace(*s))
s++;
singlefunctions(line +2, s);
}
/* Open file, exit on error */
infile = fopen(argv[2], "r");
- if (infile == NULL) {
- fprintf(stderr, "docproc: ");
- perror(argv[2]);
- exit(2);
- }
+ if (infile == NULL) {
+ fprintf(stderr, "docproc: ");
+ perror(argv[2]);
+ exit(2);
+ }
if (strcmp("doc", argv[1]) == 0) {
/* Need to do this in two passes.
"setenv list ${list}3", strlen("setenv list 1"), 0);
assert(!strcmp("1", getenv("list")));
+ assert(run_command("false", 0) == 1);
+ assert(run_command("echo", 0) == 0);
+ assert(run_command_list("false", -1, 0) == 1);
+ assert(run_command_list("echo", -1, 0) == 0);
+
#ifdef CONFIG_SYS_HUSH_PARSER
/* Test the 'test' command */
#ifdef CONFIG_SANDBOX
/* File existence */
- HUSH_TEST(e, "-e host - creating_this_file_breaks_uboot_unit_test", n);
- run_command("sb save host - creating_this_file_breaks_uboot_unit_test 0 1", 0);
- HUSH_TEST(e, "-e host - creating_this_file_breaks_uboot_unit_test", y);
+ HUSH_TEST(e, "-e hostfs - creating_this_file_breaks_uboot_unit_test", n);
+ run_command("sb save hostfs - creating_this_file_breaks_uboot_unit_test 0 1", 0);
+ HUSH_TEST(e, "-e hostfs - creating_this_file_breaks_uboot_unit_test", y);
/* Perhaps this could be replaced by an "rm" shell command one day */
assert(!os_unlink("creating_this_file_breaks_uboot_unit_test"));
- HUSH_TEST(e, "-e host - creating_this_file_breaks_uboot_unit_test", n);
+ HUSH_TEST(e, "-e hostfs - creating_this_file_breaks_uboot_unit_test", n);
#endif
#endif
# subsystem you must add sandbox tests here.
obj-$(CONFIG_DM_TEST) += core.o
obj-$(CONFIG_DM_TEST) += ut.o
+ifneq ($(CONFIG_SANDBOX),)
obj-$(CONFIG_DM_GPIO) += gpio.o
+endif
#include <dm/test.h>
#include <dm/uclass-internal.h>
-static int display_succ(struct device *in, char *buf)
+static int display_succ(struct udevice *in, char *buf)
{
int len;
int ip = 0;
char local[16];
- struct device *pos, *n, *prev = NULL;
+ struct udevice *pos, *n, *prev = NULL;
- printf("%s- %s @ %08x", buf, in->name, map_to_sysmem(in));
- if (in->flags & DM_FLAG_ACTIVATED)
- puts(" - activated");
+ printf("%s- %c %s @ %08lx", buf,
+ in->flags & DM_FLAG_ACTIVATED ? '*' : ' ',
+ in->name, (ulong)map_to_sysmem(in));
puts("\n");
if (list_empty(&in->child_head))
return 0;
}
-static int dm_dump(struct device *dev)
+static int dm_dump(struct udevice *dev)
{
if (!dev)
return -EINVAL;
static int do_dm_dump_all(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
- struct device *root;
+ struct udevice *root;
root = dm_root();
- printf("ROOT %08x\n", map_to_sysmem(root));
+ printf("ROOT %08lx\n", (ulong)map_to_sysmem(root));
return dm_dump(root);
}
int id;
for (id = 0; id < UCLASS_COUNT; id++) {
- struct device *dev;
+ struct udevice *dev;
ret = uclass_get(id, &uc);
if (ret)
for (ret = uclass_first_device(id, &dev);
dev;
ret = uclass_next_device(&dev)) {
- printf(" %s @ %08x:\n", dev->name,
- map_to_sysmem(dev));
+ printf(" %c %s @ %08lx:\n",
+ dev->flags & DM_FLAG_ACTIVATED ? '*' : ' ',
+ dev->name, (ulong)map_to_sysmem(dev));
}
puts("\n");
}
return 0;
}
+#ifdef CONFIG_DM_TEST
static int do_dm_test(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
return dm_test_main();
}
+#define TEST_HELP "\ndm test Run tests"
+#else
+#define TEST_HELP
+#endif
static cmd_tbl_t test_commands[] = {
U_BOOT_CMD_MKENT(tree, 0, 1, do_dm_dump_all, "", ""),
U_BOOT_CMD_MKENT(uclass, 1, 1, do_dm_dump_uclass, "", ""),
+#ifdef CONFIG_DM_TEST
U_BOOT_CMD_MKENT(test, 1, 1, do_dm_test, "", ""),
+#endif
};
static int do_dm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
dm, 2, 1, do_dm,
"Driver model low level access",
"tree Dump driver model tree\n"
- "dm uclass Dump list of instances for each uclass\n"
- "dm test Run tests"
+ "dm uclass Dump list of instances for each uclass"
+ TEST_HELP
);
/* Test that binding with platdata occurs correctly */
static int dm_test_autobind(struct dm_test_state *dms)
{
- struct device *dev;
+ struct udevice *dev;
/*
* We should have a single class (UCLASS_ROOT) and a single root
static int dm_test_autoprobe(struct dm_test_state *dms)
{
int expected_base_add;
- struct device *dev;
+ struct udevice *dev;
struct uclass *uc;
int i;
static int dm_test_platdata(struct dm_test_state *dms)
{
const struct dm_test_pdata *pdata;
- struct device *dev;
+ struct udevice *dev;
int i;
for (i = 0; i < 3; i++) {
static int dm_test_lifecycle(struct dm_test_state *dms)
{
int op_count[DM_TEST_OP_COUNT];
- struct device *dev, *test_dev;
+ struct udevice *dev, *test_dev;
int pingret;
int ret;
/* Test that we can bind/unbind and the lists update correctly */
static int dm_test_ordering(struct dm_test_state *dms)
{
- struct device *dev, *dev_penultimate, *dev_last, *test_dev;
+ struct udevice *dev, *dev_penultimate, *dev_last, *test_dev;
int pingret;
ut_assertok(device_bind_by_name(dms->root, &driver_info_manual,
DM_TEST(dm_test_ordering, DM_TESTF_SCAN_PDATA);
/* Check that we can perform operations on a device (do a ping) */
-int dm_check_operations(struct dm_test_state *dms, struct device *dev,
+int dm_check_operations(struct dm_test_state *dms, struct udevice *dev,
uint32_t base, struct dm_test_priv *priv)
{
int expected;
/* Check that we can perform operations on devices */
static int dm_test_operations(struct dm_test_state *dms)
{
- struct device *dev;
+ struct udevice *dev;
int i;
/*
/* Remove all drivers and check that things work */
static int dm_test_remove(struct dm_test_state *dms)
{
- struct device *dev;
+ struct udevice *dev;
int i;
for (i = 0; i < 3; i++) {
for (i = 0; i < 2; i++) {
struct mallinfo start, end;
- struct device *dev;
+ struct udevice *dev;
int ret;
int id;
* this array.
* @return 0 if OK, -ve on error
*/
-static int create_children(struct dm_test_state *dms, struct device *parent,
- int count, int key, struct device *child[])
+static int create_children(struct dm_test_state *dms, struct udevice *parent,
+ int count, int key, struct udevice *child[])
{
- struct device *dev;
+ struct udevice *dev;
int i;
for (i = 0; i < count; i++) {
static int dm_test_children(struct dm_test_state *dms)
{
- struct device *top[NODE_COUNT];
- struct device *child[NODE_COUNT];
- struct device *grandchild[NODE_COUNT];
- struct device *dev;
+ struct udevice *top[NODE_COUNT];
+ struct udevice *child[NODE_COUNT];
+ struct udevice *grandchild[NODE_COUNT];
+ struct udevice *dev;
int total;
int ret;
int i;
{
unsigned int offset, gpio;
struct dm_gpio_ops *ops;
- struct device *dev;
+ struct udevice *dev;
const char *name;
int offset_count;
char buf[80];
int dm_testdrv_op_count[DM_TEST_OP_COUNT];
static struct dm_test_state *dms = &global_test_state;
-static int testdrv_ping(struct device *dev, int pingval, int *pingret)
+static int testdrv_ping(struct udevice *dev, int pingval, int *pingret)
{
const struct dm_test_pdata *pdata = dev_get_platdata(dev);
struct dm_test_priv *priv = dev_get_priv(dev);
.ping = testdrv_ping,
};
-static int test_bind(struct device *dev)
+static int test_bind(struct udevice *dev)
{
/* Private data should not be allocated */
ut_assert(!dev_get_priv(dev));
return 0;
}
-static int test_probe(struct device *dev)
+static int test_probe(struct udevice *dev)
{
struct dm_test_priv *priv = dev_get_priv(dev);
return 0;
}
-static int test_remove(struct device *dev)
+static int test_remove(struct udevice *dev)
{
/* Private data should still be allocated */
ut_assert(dev_get_priv(dev));
return 0;
}
-static int test_unbind(struct device *dev)
+static int test_unbind(struct udevice *dev)
{
/* Private data should not be allocated */
ut_assert(!dev->priv);
.priv_auto_alloc_size = sizeof(struct dm_test_priv),
};
-static int test_manual_drv_ping(struct device *dev, int pingval, int *pingret)
+static int test_manual_drv_ping(struct udevice *dev, int pingval, int *pingret)
{
*pingret = pingval + 2;
.ping = test_manual_drv_ping,
};
-static int test_manual_bind(struct device *dev)
+static int test_manual_bind(struct udevice *dev)
{
dm_testdrv_op_count[DM_TEST_OP_BIND]++;
return 0;
}
-static int test_manual_probe(struct device *dev)
+static int test_manual_probe(struct udevice *dev)
{
dm_testdrv_op_count[DM_TEST_OP_PROBE]++;
if (!dms->force_fail_alloc)
return 0;
}
-static int test_manual_remove(struct device *dev)
+static int test_manual_remove(struct udevice *dev)
{
dm_testdrv_op_count[DM_TEST_OP_REMOVE]++;
return 0;
}
-static int test_manual_unbind(struct device *dev)
+static int test_manual_unbind(struct udevice *dev)
{
dm_testdrv_op_count[DM_TEST_OP_UNBIND]++;
return 0;
DECLARE_GLOBAL_DATA_PTR;
-static int testfdt_drv_ping(struct device *dev, int pingval, int *pingret)
+static int testfdt_drv_ping(struct udevice *dev, int pingval, int *pingret)
{
const struct dm_test_pdata *pdata = dev->platdata;
struct dm_test_priv *priv = dev_get_priv(dev);
.ping = testfdt_drv_ping,
};
-static int testfdt_ofdata_to_platdata(struct device *dev)
+static int testfdt_ofdata_to_platdata(struct udevice *dev)
{
struct dm_test_pdata *pdata = dev_get_platdata(dev);
return 0;
}
-static int testfdt_drv_probe(struct device *dev)
+static int testfdt_drv_probe(struct udevice *dev)
{
struct dm_test_priv *priv = dev_get_priv(dev);
return 0;
}
-static const struct device_id testfdt_ids[] = {
+static const struct udevice_id testfdt_ids[] = {
{
.compatible = "denx,u-boot-fdt-test",
.data = DM_TEST_TYPE_FIRST },
};
/* From here is the testfdt uclass code */
-int testfdt_ping(struct device *dev, int pingval, int *pingret)
+int testfdt_ping(struct udevice *dev, int pingval, int *pingret)
{
const struct test_ops *ops = device_get_ops(dev);
static int dm_test_fdt(struct dm_test_state *dms)
{
const int num_drivers = 3;
- struct device *dev;
+ struct udevice *dev;
struct uclass *uc;
int ret;
int i;
/* Ensure all the test devices are probed */
static int do_autoprobe(struct dm_test_state *dms)
{
- struct device *dev;
+ struct udevice *dev;
int ret;
/* Scanning the uclass is enough to probe all the devices */
static struct dm_test_state *dms = &global_test_state;
-int test_ping(struct device *dev, int pingval, int *pingret)
+int test_ping(struct udevice *dev, int pingval, int *pingret)
{
const struct test_ops *ops = device_get_ops(dev);
return ops->ping(dev, pingval, pingret);
}
-static int test_post_bind(struct device *dev)
+static int test_post_bind(struct udevice *dev)
{
dm_testdrv_op_count[DM_TEST_OP_POST_BIND]++;
return 0;
}
-static int test_pre_unbind(struct device *dev)
+static int test_pre_unbind(struct udevice *dev)
{
dm_testdrv_op_count[DM_TEST_OP_PRE_UNBIND]++;
return 0;
}
-static int test_post_probe(struct device *dev)
+static int test_post_probe(struct udevice *dev)
{
- struct device *prev = list_entry(dev->uclass_node.prev, struct device,
- uclass_node);
+ struct udevice *prev = list_entry(dev->uclass_node.prev,
+ struct udevice, uclass_node);
+
struct dm_test_uclass_perdev_priv *priv = dev->uclass_priv;
struct uclass *uc = dev->uclass;
return 0;
}
-static int test_pre_remove(struct device *dev)
+static int test_pre_remove(struct udevice *dev)
{
dm_testdrv_op_count[DM_TEST_OP_PRE_REMOVE]++;
-#!/bin/sh
+#!/bin/bash
#
# Copyright (c) 2013, Google Inc.
#
run_uboot() {
echo -n "Test Verified Boot Run: $1: "
${uboot} -d sandbox-u-boot.dtb >${tmp} -c '
-sb load host 0 100 test.fit;
+sb load hostfs - 100 test.fit;
fdt addr 100;
bootm 100;
reset'
/relocate-rela
/ubsha1
/xway-swap-bytes
-/*.exe
/easylogo/easylogo
/gdb/gdbcont
/gdb/gdbsend
+
+/lib/
+/common/
# SPDX-License-Identifier: GPL-2.0+
#
-#
-# toolchains targeting win32 generate .exe files
-#
-ifneq (,$(findstring WIN32 ,$(shell $(HOSTCC) -E -dM -xc /dev/null)))
-SFX = .exe
-else
-SFX =
-endif
-
# Enable all the config-independent tools
ifneq ($(HOST_TOOLS_ALL),)
CONFIG_LCD_LOGO = y
ENVCRC-$(CONFIG_ENV_IS_IN_SPI_FLASH) = y
CONFIG_BUILD_ENVCRC ?= $(ENVCRC-y)
-hostprogs-$(CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER) += atmel_pmecc_params$(SFX)
+hostprogs-$(CONFIG_SPL_GENERATE_ATMEL_PMECC_HEADER) += atmel_pmecc_params
# TODO: CONFIG_CMD_LICENSE does not work
-hostprogs-$(CONFIG_CMD_LICENSE) += bin2header$(SFX)
-hostprogs-$(CONFIG_LCD_LOGO) += bmp_logo$(SFX)
-hostprogs-$(CONFIG_VIDEO_LOGO) += bmp_logo$(SFX)
-HOSTCFLAGS_bmp_logo$(SFX).o := -pedantic
+hostprogs-$(CONFIG_CMD_LICENSE) += bin2header
+hostprogs-$(CONFIG_LCD_LOGO) += bmp_logo
+hostprogs-$(CONFIG_VIDEO_LOGO) += bmp_logo
+HOSTCFLAGS_bmp_logo.o := -pedantic
-hostprogs-$(CONFIG_BUILD_ENVCRC) += envcrc$(SFX)
-envcrc$(SFX)-objs := crc32.o env_embedded.o envcrc.o sha1.o
+hostprogs-$(CONFIG_BUILD_ENVCRC) += envcrc
+envcrc-objs := envcrc.o lib/crc32.o common/env_embedded.o lib/sha1.o
-hostprogs-$(CONFIG_CMD_NET) += gen_eth_addr$(SFX)
-HOSTCFLAGS_gen_eth_addr$(SFX).o := -pedantic
+hostprogs-$(CONFIG_CMD_NET) += gen_eth_addr
+HOSTCFLAGS_gen_eth_addr.o := -pedantic
-hostprogs-$(CONFIG_CMD_LOADS) += img2srec$(SFX)
-HOSTCFLAGS_img2srec$(SFX).o := -pedantic
+hostprogs-$(CONFIG_CMD_LOADS) += img2srec
+HOSTCFLAGS_img2srec.o := -pedantic
-hostprogs-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX)
-HOSTCFLAGS_xway-swap-bytes$(SFX).o := -pedantic
+hostprogs-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes
+HOSTCFLAGS_xway-swap-bytes.o := -pedantic
-hostprogs-y += mkenvimage$(SFX)
-mkenvimage$(SFX)-objs := crc32.o mkenvimage.o os_support.o
+hostprogs-y += mkenvimage
+mkenvimage-objs := mkenvimage.o os_support.o lib/crc32.o
-hostprogs-y += dumpimage$(SFX) mkimage$(SFX)
-hostprogs-$(CONFIG_FIT_SIGNATURE) += fit_info$(SFX) fit_check_sign$(SFX)
+hostprogs-y += dumpimage mkimage
+hostprogs-$(CONFIG_FIT_SIGNATURE) += fit_info fit_check_sign
-FIT_SIG_OBJS-$(CONFIG_FIT_SIGNATURE) := image-sig.o
+FIT_SIG_OBJS-$(CONFIG_FIT_SIGNATURE) := common/image-sig.o
# Flattened device tree objects
-LIBFDT_OBJS := fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_wip.o
-RSA_OBJS-$(CONFIG_FIT_SIGNATURE) := rsa-sign.o rsa-verify.o rsa-checksum.o
+LIBFDT_OBJS := $(addprefix lib/libfdt/, \
+ fdt.o fdt_ro.o fdt_rw.o fdt_strerror.o fdt_wip.o)
+RSA_OBJS-$(CONFIG_FIT_SIGNATURE) := $(addprefix lib/rsa/, \
+ rsa-sign.o rsa-verify.o rsa-checksum.o)
# common objs for dumpimage and mkimage
dumpimage-mkimage-objs := aisimage.o \
atmelimage.o \
$(FIT_SIG_OBJS-y) \
- crc32.o \
+ common/bootm.o \
+ lib/crc32.o \
default_image.o \
- fdtdec.o \
+ lib/fdtdec_common.o \
+ lib/fdtdec.o \
fit_common.o \
fit_image.o \
gpimage.o \
gpimage-common.o \
- image-fit.o \
+ common/image-fit.o \
image-host.o \
- image.o \
+ common/image.o \
imagetool.o \
imximage.o \
kwbimage.o \
- md5.o \
+ lib/md5.o \
mxsimage.o \
omapimage.o \
os_support.o \
pblimage.o \
- sha1.o \
- sha256.o \
+ pbl_crc32.o \
+ lib/sha1.o \
+ lib/sha256.o \
ublimage.o \
$(LIBFDT_OBJS) \
$(RSA_OBJS-y)
-dumpimage$(SFX)-objs := $(dumpimage-mkimage-objs) dumpimage.o
-mkimage$(SFX)-objs := $(dumpimage-mkimage-objs) mkimage.o
-fit_info$(SFX)-objs := $(dumpimage-mkimage-objs) fit_info.o
-fit_check_sign$(SFX)-objs := $(dumpimage-mkimage-objs) fit_check_sign.o
+dumpimage-objs := $(dumpimage-mkimage-objs) dumpimage.o
+mkimage-objs := $(dumpimage-mkimage-objs) mkimage.o
+fit_info-objs := $(dumpimage-mkimage-objs) fit_info.o
+fit_check_sign-objs := $(dumpimage-mkimage-objs) fit_check_sign.o
# TODO(sjg@chromium.org): Is this correct on Mac OS?
-# MXSImage needs LibSSL
ifneq ($(CONFIG_MX23)$(CONFIG_MX28),)
-HOSTLOADLIBES_dumpimage$(SFX) := -lssl -lcrypto
-HOSTLOADLIBES_mkimage$(SFX) := -lssl -lcrypto
-HOSTLOADLIBES_fit_info$(SFX) := -lssl -lcrypto
-HOSTLOADLIBES_fit_check_sign$(SFX) := -lssl -lcrypto
# Add CONFIG_MXS into host CFLAGS, so we can check whether or not register
# the mxsimage support within tools/mxsimage.c .
HOSTCFLAGS_mxsimage.o += -DCONFIG_MXS
endif
ifdef CONFIG_FIT_SIGNATURE
-HOSTLOADLIBES_dumpimage$(SFX) := -lssl -lcrypto
-HOSTLOADLIBES_mkimage$(SFX) := -lssl -lcrypto
-HOSTLOADLIBES_fit_info$(SFX) := -lssl -lcrypto
-HOSTLOADLIBES_fit_check_sign$(SFX) := -lssl -lcrypto
-
# This affects include/image.h, but including the board config file
# is tricky, so manually define this options here.
HOST_EXTRACFLAGS += -DCONFIG_FIT_SIGNATURE
endif
-hostprogs-$(CONFIG_EXYNOS5250) += mkexynosspl$(SFX)
-hostprogs-$(CONFIG_EXYNOS5420) += mkexynosspl$(SFX)
-HOSTCFLAGS_mkexynosspl$(SFX).o := -pedantic
+# MXSImage needs LibSSL
+ifneq ($(CONFIG_MX23)$(CONFIG_MX28)$(CONFIG_FIT_SIGNATURE),)
+HOSTLOADLIBES_mkimage += -lssl -lcrypto
+endif
+
+HOSTLOADLIBES_dumpimage := $(HOSTLOADLIBES_mkimage)
+HOSTLOADLIBES_fit_info := $(HOSTLOADLIBES_mkimage)
+HOSTLOADLIBES_fit_check_sign := $(HOSTLOADLIBES_mkimage)
+
+hostprogs-$(CONFIG_EXYNOS5250) += mkexynosspl
+hostprogs-$(CONFIG_EXYNOS5420) += mkexynosspl
+HOSTCFLAGS_mkexynosspl.o := -pedantic
-hostprogs-$(CONFIG_MX23) += mxsboot$(SFX)
-hostprogs-$(CONFIG_MX28) += mxsboot$(SFX)
-HOSTCFLAGS_mxsboot$(SFX).o := -pedantic
+hostprogs-$(CONFIG_MX23) += mxsboot
+hostprogs-$(CONFIG_MX28) += mxsboot
+HOSTCFLAGS_mxsboot.o := -pedantic
-hostprogs-$(CONFIG_SUNXI) += mksunxiboot$(SFX)
+hostprogs-$(CONFIG_SUNXI) += mksunxiboot
-hostprogs-$(CONFIG_NETCONSOLE) += ncb$(SFX)
-hostprogs-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)
+hostprogs-$(CONFIG_NETCONSOLE) += ncb
+hostprogs-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1
-ubsha1$(SFX)-objs := os_support.o sha1.o ubsha1.o
+ubsha1-objs := os_support.o ubsha1.o lib/sha1.o
HOSTCFLAGS_ubsha1.o := -pedantic
-hostprogs-$(CONFIG_KIRKWOOD) += kwboot$(SFX)
-hostprogs-y += proftool$(SFX)
-hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela$(SFX)
+hostprogs-$(CONFIG_KIRKWOOD) += kwboot
+hostprogs-y += proftool
+hostprogs-$(CONFIG_STATIC_RELA) += relocate-rela
# We build some files with extra pedantic flags to try to minimize things
# that won't build on some weird host compiler -- though there are lots of
HOSTCFLAGS_sha256.o := -pedantic
# Don't build by default
-#hostprogs-$(CONFIG_PPC) += mpc86x_clk$(SFX)
-#HOSTCFLAGS_mpc86x_clk$(SFX).o := -pedantic
+#hostprogs-$(CONFIG_PPC) += mpc86x_clk
+#HOSTCFLAGS_mpc86x_clk.o := -pedantic
+
+quiet_cmd_wrap = WRAP $@
+cmd_wrap = echo "\#include <$(srctree)/$(patsubst $(obj)/%,%,$@)>" >$@
+
+$(obj)/lib/%.c $(obj)/common/%.c:
+ $(call cmd,wrap)
+
+clean-dirs := lib common
always := $(hostprogs-y)
+++ /dev/null
-#include "../lib/crc32.c"
#include <sys/stat.h>
#include <time.h>
#include <unistd.h>
-#include <sha1.h>
+#include <u-boot/sha1.h>
#include "fdt_host.h"
#include "imagetool.h"
+++ /dev/null
-#include "../common/env_embedded.c"
+++ /dev/null
-#include "../lib/libfdt/fdt.c"
+++ /dev/null
-#include "../lib/libfdt/fdt_ro.c"
+++ /dev/null
-#include "../lib/libfdt/fdt_rw.c"
+++ /dev/null
-#include "../lib/libfdt/fdt_strerror.c"
+++ /dev/null
-#include "../lib/libfdt/fdt_wip.c"
+++ /dev/null
-#include "../lib/fdtdec.c"
void *fit_blob;
char *fdtfile = NULL;
char *keyfile = NULL;
- char cmdname[50];
+ char cmdname[256];
int ret;
void *key_blob;
int c;
- strcpy(cmdname, *argv);
+ strncpy(cmdname, *argv, sizeof(cmdname) - 1);
+ cmdname[sizeof(cmdname) - 1] = '\0';
while ((c = getopt(argc, argv, "f:k:")) != -1)
switch (c) {
case 'f':
break;
}
- ffd = mmap_fdt(cmdname, fdtfile, &fit_blob, &fsbuf, 0);
+ if (!fdtfile) {
+ fprintf(stderr, "%s: Missing fdt file\n", *argv);
+ usage(*argv);
+ }
+ if (!keyfile) {
+ fprintf(stderr, "%s: Missing key file\n", *argv);
+ usage(*argv);
+ }
+
+ ffd = mmap_fdt(cmdname, fdtfile, 0, &fit_blob, &fsbuf, false);
if (ffd < 0)
return EXIT_FAILURE;
- kfd = mmap_fdt(cmdname, keyfile, &key_blob, &ksbuf, 0);
+ kfd = mmap_fdt(cmdname, keyfile, 0, &key_blob, &ksbuf, false);
if (ffd < 0)
return EXIT_FAILURE;
image_set_host_blob(key_blob);
ret = fit_check_sign(fit_blob, key_blob);
-
- if (ret)
+ if (!ret) {
ret = EXIT_SUCCESS;
- else
+ fprintf(stderr, "Signature check OK\n");
+ } else {
ret = EXIT_FAILURE;
+ fprintf(stderr, "Signature check Bad (error %d)\n", ret);
+ }
(void) munmap((void *)fit_blob, fsbuf.st_size);
(void) munmap((void *)key_blob, ksbuf.st_size);
return EXIT_FAILURE;
}
-int mmap_fdt(char *cmdname, const char *fname, void **blobp,
- struct stat *sbuf, int useunlink)
+int mmap_fdt(const char *cmdname, const char *fname, size_t size_inc,
+ void **blobp, struct stat *sbuf, bool delete_on_error)
{
void *ptr;
int fd;
if (fd < 0) {
fprintf(stderr, "%s: Can't open %s: %s\n",
cmdname, fname, strerror(errno));
- if (useunlink)
- unlink(fname);
- return -1;
+ goto err;
}
if (fstat(fd, sbuf) < 0) {
fprintf(stderr, "%s: Can't stat %s: %s\n",
cmdname, fname, strerror(errno));
- if (useunlink)
- unlink(fname);
- return -1;
+ goto err;
+ }
+
+ if (size_inc) {
+ sbuf->st_size += size_inc;
+ if (ftruncate(fd, sbuf->st_size)) {
+ fprintf(stderr, "%s: Can't expand %s: %s\n",
+ cmdname, fname, strerror(errno));
+ goto err;
+ }
}
errno = 0;
if ((ptr == MAP_FAILED) || (errno != 0)) {
fprintf(stderr, "%s: Can't read %s: %s\n",
cmdname, fname, strerror(errno));
- if (useunlink)
- unlink(fname);
- return -1;
+ goto err;
}
/* check if ptr has a valid blob */
if (fdt_check_header(ptr)) {
fprintf(stderr, "%s: Invalid FIT blob\n", cmdname);
- if (useunlink)
- unlink(fname);
- return -1;
+ goto err;
+ }
+
+ /* expand if needed */
+ if (size_inc) {
+ int ret;
+
+ ret = fdt_open_into(ptr, ptr, sbuf->st_size);
+ if (ret) {
+ fprintf(stderr, "%s: Cannot expand FDT: %s\n",
+ cmdname, fdt_strerror(ret));
+ goto err;
+ }
}
*blobp = ptr;
return fd;
+
+err:
+ if (fd >= 0)
+ close(fd);
+ if (delete_on_error)
+ unlink(fname);
+
+ return -1;
}
int fit_check_image_types(uint8_t type);
-int mmap_fdt(char *cmdname, const char *fname, void **blobp,
- struct stat *sbuf, int useunlink);
+/**
+ * Map an FDT into memory, optionally increasing its size
+ *
+ * @cmdname: Tool name (for displaying with error messages)
+ * @fname: Filename containing FDT
+ * @size_inc: Amount to increase size by (0 = leave it alone)
+ * @blobp: Returns pointer to FDT blob
+ * @sbuf: File status information is stored here
+ * @delete_on_error: true to delete the file if we get an error
+ * @return 0 if OK, -1 on error.
+ */
+int mmap_fdt(const char *cmdname, const char *fname, size_t size_inc,
+ void **blobp, struct stat *sbuf, bool delete_on_error);
#endif /* _FIT_COMMON_H_ */
static image_header_t header;
+static int fit_add_file_data(struct image_tool_params *params, size_t size_inc,
+ const char *tmpfile)
+{
+ int tfd, destfd = 0;
+ void *dest_blob = NULL;
+ off_t destfd_size = 0;
+ struct stat sbuf;
+ void *ptr;
+ int ret = 0;
+
+ tfd = mmap_fdt(params->cmdname, tmpfile, size_inc, &ptr, &sbuf, true);
+ if (tfd < 0)
+ return -EIO;
+
+ if (params->keydest) {
+ struct stat dest_sbuf;
+
+ destfd = mmap_fdt(params->cmdname, params->keydest, size_inc,
+ &dest_blob, &dest_sbuf, false);
+ if (destfd < 0) {
+ ret = -EIO;
+ goto err_keydest;
+ }
+ destfd_size = dest_sbuf.st_size;
+ }
+
+ /* for first image creation, add a timestamp at offset 0 i.e., root */
+ if (params->datafile)
+ ret = fit_set_timestamp(ptr, 0, sbuf.st_mtime);
+
+ if (!ret) {
+ ret = fit_add_verification_data(params->keydir, dest_blob, ptr,
+ params->comment,
+ params->require_keys);
+ }
+
+ if (dest_blob) {
+ munmap(dest_blob, destfd_size);
+ close(destfd);
+ }
+
+err_keydest:
+ munmap(ptr, sbuf.st_size);
+ close(tfd);
+
+ return ret;
+}
+
/**
* fit_handle_file - main FIT file processing function
*
{
char tmpfile[MKIMAGE_MAX_TMPFILE_LEN];
char cmd[MKIMAGE_MAX_DTC_CMDLINE_LEN];
- int tfd, destfd = 0;
- void *dest_blob = NULL;
- struct stat sbuf;
- void *ptr;
- off_t destfd_size = 0;
+ size_t size_inc;
+ int ret;
/* Flattened Image Tree (FIT) format handling */
debug ("FIT format handling\n");
goto err_system;
}
- if (params->keydest) {
- destfd = mmap_fdt(params->cmdname, params->keydest,
- &dest_blob, &sbuf, 1);
- if (destfd < 0)
- goto err_keydest;
- destfd_size = sbuf.st_size;
+ /*
+ * Set hashes for images in the blob. Unfortunately we may need more
+ * space in either FDT, so keep trying until we succeed.
+ *
+ * Note: this is pretty inefficient for signing, since we must
+ * calculate the signature every time. It would be better to calculate
+ * all the data and then store it in a separate step. However, this
+ * would be considerably more complex to implement. Generally a few
+ * steps of this loop is enough to sign with several keys.
+ */
+ for (size_inc = 0; size_inc < 64 * 1024; size_inc += 1024) {
+ ret = fit_add_file_data(params, size_inc, tmpfile);
+ if (!ret || ret != -ENOSPC)
+ break;
}
- tfd = mmap_fdt(params->cmdname, tmpfile, &ptr, &sbuf, 1);
- if (tfd < 0)
- goto err_mmap;
-
- /* set hashes for images in the blob */
- if (fit_add_verification_data(params->keydir,
- dest_blob, ptr, params->comment,
- params->require_keys)) {
+ if (ret) {
fprintf(stderr, "%s Can't add hashes to FIT blob\n",
params->cmdname);
- goto err_add_hashes;
- }
-
- /* for first image creation, add a timestamp at offset 0 i.e., root */
- if (params->datafile && fit_set_timestamp(ptr, 0, sbuf.st_mtime)) {
- fprintf (stderr, "%s: Can't add image timestamp\n",
- params->cmdname);
- goto err_add_timestamp;
- }
- debug ("Added timestamp successfully\n");
-
- munmap ((void *)ptr, sbuf.st_size);
- close (tfd);
- if (dest_blob) {
- munmap(dest_blob, destfd_size);
- close(destfd);
+ goto err_system;
}
if (rename (tmpfile, params->imagefile) == -1) {
strerror (errno));
unlink (tmpfile);
unlink (params->imagefile);
- return (EXIT_FAILURE);
+ return EXIT_FAILURE;
}
- return (EXIT_SUCCESS);
+ return EXIT_SUCCESS;
-err_add_timestamp:
-err_add_hashes:
- munmap(ptr, sbuf.st_size);
-err_mmap:
- if (dest_blob)
- munmap(dest_blob, destfd_size);
-err_keydest:
err_system:
unlink(tmpfile);
return -1;
break;
}
- ffd = mmap_fdt(cmdname, fdtfile, &fit_blob, &fsbuf, 0);
+ if (!fdtfile) {
+ fprintf(stderr, "%s: Missing fdt file\n", *argv);
+ usage(*argv);
+ }
+ if (!nodename) {
+ fprintf(stderr, "%s: Missing node name\n", *argv);
+ usage(*argv);
+ }
+ if (!propertyname) {
+ fprintf(stderr, "%s: Missing property name\n", *argv);
+ usage(*argv);
+ }
+ ffd = mmap_fdt(cmdname, fdtfile, 0, &fit_blob, &fsbuf, false);
if (ffd < 0) {
printf("Could not open %s\n", fdtfile);
+++ /dev/null
-#include "../common/image-fit.c"
*/
#include "mkimage.h"
+#include <bootm.h>
#include <image.h>
#include <version.h>
ret = fit_image_write_sig(fit, noffset, value, value_len, comment,
NULL, 0);
if (ret) {
- printf("Can't write signature for '%s' signature node in '%s' image node: %s\n",
+ if (ret == -FDT_ERR_NOSPACE)
+ return -ENOSPC;
+ printf("Can't write signature for '%s' signature node in '%s' conf node: %s\n",
node_name, image_name, fdt_strerror(ret));
return -1;
}
return -1;
}
- if (fit_image_write_sig(fit, noffset, value, value_len, comment,
- region_prop, region_proplen)) {
- printf("Can't write signature for '%s' signature node in '%s' conf node\n",
- node_name, conf_name);
+ ret = fit_image_write_sig(fit, noffset, value, value_len, comment,
+ region_prop, region_proplen);
+ if (ret) {
+ if (ret == -FDT_ERR_NOSPACE)
+ return -ENOSPC;
+ printf("Can't write signature for '%s' signature node in '%s' conf node: %s\n",
+ node_name, conf_name, fdt_strerror(ret));
return -1;
}
free(value);
info.keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL);
/* Write the public key into the supplied FDT file */
- if (keydest && info.algo->add_verify_data(&info, keydest)) {
- printf("Failed to add verification data for '%s' signature node in '%s' image node\n",
- node_name, conf_name);
- return -1;
+ if (keydest) {
+ ret = info.algo->add_verify_data(&info, keydest);
+ if (ret == -ENOSPC)
+ return -ENOSPC;
+ if (ret) {
+ printf("Failed to add verification data for '%s' signature node in '%s' image node\n",
+ node_name, conf_name);
+ }
+ return ret;
}
return 0;
}
#ifdef CONFIG_FIT_SIGNATURE
-int fit_check_sign(const void *working_fdt, const void *key)
+int fit_check_sign(const void *fit, const void *key)
{
int cfg_noffset;
int ret;
- cfg_noffset = fit_conf_get_node(working_fdt, NULL);
+ cfg_noffset = fit_conf_get_node(fit, NULL);
if (!cfg_noffset)
return -1;
- ret = fit_config_verify(working_fdt, cfg_noffset);
+ printf("Verifying Hash Integrity ... ");
+ ret = fit_config_verify(fit, cfg_noffset);
+ if (ret)
+ return ret;
+ ret = bootm_host_load_images(fit, cfg_noffset);
+
return ret;
}
#endif
+++ /dev/null
-#include "../common/image-sig.c"
+++ /dev/null
-#include "../common/image.c"
#include <sys/stat.h>
#include <time.h>
#include <unistd.h>
-#include <sha1.h>
+#include <u-boot/sha1.h>
#include "fdt_host.h"
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+++ /dev/null
-#include "../lib/md5.c"
#include <sys/stat.h>
#include <time.h>
#include <unistd.h>
-#include <sha1.h>
+#include <u-boot/sha1.h>
#include "fdt_host.h"
#include "imagetool.h"
#include "imagetool.h"
#include "mxsimage.h"
+#include "pbl_crc32.h"
#include <image.h>
return sb_aes_init(ictx, iv, enc);
}
-/*
- * CRC32
- */
-static uint32_t crc32(uint8_t *data, uint32_t len)
-{
- const uint32_t poly = 0x04c11db7;
- uint32_t crc32 = 0xffffffff;
- unsigned int byte, bit;
-
- for (byte = 0; byte < len; byte++) {
- crc32 ^= data[byte] << 24;
-
- for (bit = 8; bit > 0; bit--) {
- if (crc32 & (1UL << 31))
- crc32 = (crc32 << 1) ^ poly;
- else
- crc32 = (crc32 << 1);
- }
- }
-
- return crc32;
-}
-
/*
* Debug
*/
ccmd->load.address = dest;
ccmd->load.count = cctx->length;
- ccmd->load.crc32 = crc32(cctx->data, cctx->length);
+ ccmd->load.crc32 = pbl_crc32(0,
+ (const char *)cctx->data,
+ cctx->length);
cctx->size = sizeof(*ccmd) + cctx->length;
EVP_DigestUpdate(&ictx->md_ctx, cctx->data, asize);
sb_aes_crypt(ictx, cctx->data, cctx->data, asize);
- if (ccmd->load.crc32 != crc32(cctx->data, asize)) {
+ if (ccmd->load.crc32 != pbl_crc32(0,
+ (const char *)cctx->data,
+ asize)) {
fprintf(stderr,
"ERR: SB LOAD command payload CRC32 invalid!\n");
return -EINVAL;
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * Cleaned up and refactored by Charles Manning.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#include "pblimage.h"
+
+static uint32_t crc_table[256];
+static int crc_table_valid;
+
+static void make_crc_table(void)
+{
+ uint32_t mask;
+ int i, j;
+ uint32_t poly; /* polynomial exclusive-or pattern */
+
+ if (crc_table_valid)
+ return;
+
+ /*
+ * the polynomial used by PBL is 1 + x1 + x2 + x4 + x5 + x7 + x8 + x10
+ * + x11 + x12 + x16 + x22 + x23 + x26 + x32.
+ */
+ poly = 0x04c11db7;
+
+ for (i = 0; i < 256; i++) {
+ mask = i << 24;
+ for (j = 0; j < 8; j++) {
+ if (mask & 0x80000000)
+ mask = (mask << 1) ^ poly;
+ else
+ mask <<= 1;
+ }
+ crc_table[i] = mask;
+ }
+
+ crc_table_valid = 1;
+}
+
+uint32_t pbl_crc32(uint32_t in_crc, const char *buf, uint32_t len)
+{
+ uint32_t crc32_val;
+ int i;
+
+ make_crc_table();
+
+ crc32_val = ~in_crc;
+
+ for (i = 0; i < len; i++)
+ crc32_val = (crc32_val << 8) ^
+ crc_table[(crc32_val >> 24) ^ (*buf++ & 0xff)];
+
+ return crc32_val;
+}
--- /dev/null
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef PBLCRC32_H
+#define PBLCRC32_H
+
+#include <stdint.h>
+uint32_t pbl_crc32(uint32_t in_crc, const char *buf, uint32_t len);
+
+#endif
#include "imagetool.h"
#include <image.h>
#include "pblimage.h"
+#include "pbl_crc32.h"
/*
* Initialize to an invalid value.
fclose(fd);
}
-static uint32_t crc_table[256];
-
-static void make_crc_table(void)
-{
- uint32_t mask;
- int i, j;
- uint32_t poly; /* polynomial exclusive-or pattern */
-
- /*
- * the polynomial used by PBL is 1 + x1 + x2 + x4 + x5 + x7 + x8 + x10
- * + x11 + x12 + x16 + x22 + x23 + x26 + x32.
- */
- poly = 0x04c11db7;
-
- for (i = 0; i < 256; i++) {
- mask = i << 24;
- for (j = 0; j < 8; j++) {
- if (mask & 0x80000000)
- mask = (mask << 1) ^ poly;
- else
- mask <<= 1;
- }
- crc_table[i] = mask;
- }
-}
-
-unsigned long pbl_crc32(unsigned long crc, const char *buf, uint32_t len)
-{
- uint32_t crc32_val = 0xffffffff;
- uint32_t xor = 0x0;
- int i;
-
- make_crc_table();
-
- for (i = 0; i < len; i++)
- crc32_val = (crc32_val << 8) ^
- crc_table[(crc32_val >> 24) ^ (*buf++ & 0xff)];
-
- crc32_val = crc32_val ^ xor;
- if (crc32_val < 0) {
- crc32_val += 0xffffffff;
- crc32_val += 1;
- }
- return crc32_val;
-}
-
static uint32_t reverse_byte(uint32_t val)
{
uint32_t temp;
+++ /dev/null
-#include "../lib/rsa/rsa-checksum.c"
+++ /dev/null
-#include "../lib/rsa/rsa-sign.c"
+++ /dev/null
-#include "../lib/rsa/rsa-verify.c"
+++ /dev/null
-#include "../lib/sha1.c"
+++ /dev/null
-#include "../lib/sha256.c"
#include <errno.h>
#include <string.h>
#include <sys/stat.h>
-#include "sha1.h"
+#include <u-boot/sha1.h>
int main (int argc, char **argv)
{
projects / karo-tx-uboot.git / commitdiff