cosmetic changes to bcm570x driver

This is a cosmetic only changes submission.
It affects files relevant to bcm570x driver.
the commands used to generate this change was

cd drivers
Lindent -pcs -l80  bcm570x.c   bcm570x_lm.h   bcm570x_mm.h  tigon3.c  tigon3.h

The BMW target (the only one using this chip so far) builds cleanly, the
`before and after' generated object files for drivers/bcm570x.c and
drivers/tigon3.o are identical as reported by objdump -d

Signed-off-by: Vadim Bendebury <vbendeb@google.com>
Signed-off-by: Ben Warren <bwarren@qstreams.com>

diff --git a/drivers/bcm570x.c b/drivers/bcm570x.c
index 5f632a64692a8253482bc516d0eb859607d43527..7aeb5474b13fea6bad896e347d094cf0f7b7a731 100644 (file)
--- a/drivers/bcm570x.c
+++ b/drivers/bcm570x.c
@@ -18,7 +18,6 @@
 #include <pci.h>
 #include <malloc.h>
 
 #include <pci.h>
 #include <malloc.h>
 

-

 /*
  * PCI Registers and definitions.
  */
 /*
  * PCI Registers and definitions.
  */


@@ -31,7 +30,6 @@
 #define BCM570X_MBAR   0x80100000
 #define BCM570X_ILINE   1
 
 #define BCM570X_MBAR   0x80100000
 #define BCM570X_ILINE   1
 

-

 #define SECOND_USEC    1000000
 #define MAX_PACKET_SIZE 1600
 #define MAX_UNITS       4
 #define SECOND_USEC    1000000
 #define MAX_PACKET_SIZE 1600
 #define MAX_UNITS       4


@@ -39,62 +37,61 @@
 /* Globals to this module */
 int initialized = 0;
 unsigned int ioBase = 0;
 /* Globals to this module */
 int initialized = 0;
 unsigned int ioBase = 0;

-volatile PLM_DEVICE_BLOCK    pDevice = NULL;        /* 570x softc */
-volatile PUM_DEVICE_BLOCK    pUmDevice = NULL;
+volatile PLM_DEVICE_BLOCK pDevice = NULL;      /* 570x softc */
+volatile PUM_DEVICE_BLOCK pUmDevice = NULL;

 
 /* Used to pass the full-duplex flag, etc. */
 
 /* Used to pass the full-duplex flag, etc. */

-int line_speed[MAX_UNITS] = {0,0,0,0};
-static int full_duplex[MAX_UNITS] = {1,1,1,1};
-static int rx_flow_control[MAX_UNITS] = {0,0,0,0};
-static int tx_flow_control[MAX_UNITS] = {0,0,0,0};
-static int auto_flow_control[MAX_UNITS] = {0,0,0,0};
-static int tx_checksum[MAX_UNITS] = {1,1,1,1};
-static int rx_checksum[MAX_UNITS] = {1,1,1,1};
-static int auto_speed[MAX_UNITS] = {1,1,1,1};
+int line_speed[MAX_UNITS] = { 0, 0, 0, 0 };
+static int full_duplex[MAX_UNITS] = { 1, 1, 1, 1 };
+static int rx_flow_control[MAX_UNITS] = { 0, 0, 0, 0 };
+static int tx_flow_control[MAX_UNITS] = { 0, 0, 0, 0 };
+static int auto_flow_control[MAX_UNITS] = { 0, 0, 0, 0 };
+static int tx_checksum[MAX_UNITS] = { 1, 1, 1, 1 };
+static int rx_checksum[MAX_UNITS] = { 1, 1, 1, 1 };
+static int auto_speed[MAX_UNITS] = { 1, 1, 1, 1 };

 
 #if JUMBO_FRAMES
 /* Jumbo MTU for interfaces. */
 
 #if JUMBO_FRAMES
 /* Jumbo MTU for interfaces. */

-static int mtu[MAX_UNITS] = {0,0,0,0};
+static int mtu[MAX_UNITS] = { 0, 0, 0, 0 };

 #endif
 
 /* Turn on Wake-on lan for a device unit */
 #endif
 
 /* Turn on Wake-on lan for a device unit */

-static int enable_wol[MAX_UNITS] = {0,0,0,0};
+static int enable_wol[MAX_UNITS] = { 0, 0, 0, 0 };

 
 #define TX_DESC_CNT DEFAULT_TX_PACKET_DESC_COUNT
 static unsigned int tx_pkt_desc_cnt[MAX_UNITS] =
 
 #define TX_DESC_CNT DEFAULT_TX_PACKET_DESC_COUNT
 static unsigned int tx_pkt_desc_cnt[MAX_UNITS] =

-       {TX_DESC_CNT,TX_DESC_CNT,TX_DESC_CNT, TX_DESC_CNT};
+    { TX_DESC_CNT, TX_DESC_CNT, TX_DESC_CNT, TX_DESC_CNT };

 
 #define RX_DESC_CNT DEFAULT_STD_RCV_DESC_COUNT
 static unsigned int rx_std_desc_cnt[MAX_UNITS] =
 
 #define RX_DESC_CNT DEFAULT_STD_RCV_DESC_COUNT
 static unsigned int rx_std_desc_cnt[MAX_UNITS] =

-       {RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT,RX_DESC_CNT};
+    { RX_DESC_CNT, RX_DESC_CNT, RX_DESC_CNT, RX_DESC_CNT };

 
 

-static unsigned int rx_adaptive_coalesce[MAX_UNITS] = {1,1,1,1};
+static unsigned int rx_adaptive_coalesce[MAX_UNITS] = { 1, 1, 1, 1 };

 
 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
 #define JBO_DESC_CNT DEFAULT_JUMBO_RCV_DESC_COUNT
 static unsigned int rx_jumbo_desc_cnt[MAX_UNITS] =
 
 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
 #define JBO_DESC_CNT DEFAULT_JUMBO_RCV_DESC_COUNT
 static unsigned int rx_jumbo_desc_cnt[MAX_UNITS] =

-       {JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT};
+    { JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT, JBO_DESC_CNT };

 #endif
 #define RX_COAL_TK DEFAULT_RX_COALESCING_TICKS
 static unsigned int rx_coalesce_ticks[MAX_UNITS] =
 #endif
 #define RX_COAL_TK DEFAULT_RX_COALESCING_TICKS
 static unsigned int rx_coalesce_ticks[MAX_UNITS] =

-       {RX_COAL_TK, RX_COAL_TK, RX_COAL_TK, RX_COAL_TK};
+    { RX_COAL_TK, RX_COAL_TK, RX_COAL_TK, RX_COAL_TK };

 
 #define RX_COAL_FM DEFAULT_RX_MAX_COALESCED_FRAMES
 static unsigned int rx_max_coalesce_frames[MAX_UNITS] =
 
 #define RX_COAL_FM DEFAULT_RX_MAX_COALESCED_FRAMES
 static unsigned int rx_max_coalesce_frames[MAX_UNITS] =

-       {RX_COAL_FM, RX_COAL_FM, RX_COAL_FM, RX_COAL_FM};
+    { RX_COAL_FM, RX_COAL_FM, RX_COAL_FM, RX_COAL_FM };

 
 #define TX_COAL_TK DEFAULT_TX_COALESCING_TICKS
 static unsigned int tx_coalesce_ticks[MAX_UNITS] =
 
 #define TX_COAL_TK DEFAULT_TX_COALESCING_TICKS
 static unsigned int tx_coalesce_ticks[MAX_UNITS] =

-       {TX_COAL_TK, TX_COAL_TK, TX_COAL_TK, TX_COAL_TK};
+    { TX_COAL_TK, TX_COAL_TK, TX_COAL_TK, TX_COAL_TK };

 
 #define TX_COAL_FM DEFAULT_TX_MAX_COALESCED_FRAMES
 static unsigned int tx_max_coalesce_frames[MAX_UNITS] =
 
 #define TX_COAL_FM DEFAULT_TX_MAX_COALESCED_FRAMES
 static unsigned int tx_max_coalesce_frames[MAX_UNITS] =

-       {TX_COAL_FM, TX_COAL_FM, TX_COAL_FM, TX_COAL_FM};
+    { TX_COAL_FM, TX_COAL_FM, TX_COAL_FM, TX_COAL_FM };

 
 #define ST_COAL_TK DEFAULT_STATS_COALESCING_TICKS
 static unsigned int stats_coalesce_ticks[MAX_UNITS] =
 
 #define ST_COAL_TK DEFAULT_STATS_COALESCING_TICKS
 static unsigned int stats_coalesce_ticks[MAX_UNITS] =

-       {ST_COAL_TK, ST_COAL_TK, ST_COAL_TK, ST_COAL_TK};
-
+    { ST_COAL_TK, ST_COAL_TK, ST_COAL_TK, ST_COAL_TK };

 
 /*
  * Legitimate values for BCM570x device types
 
 /*
  * Legitimate values for BCM570x device types


@@ -134,707 +131,701 @@ typedef enum {
 
 /* Chip-Rev names for each device-type */
 static struct {
 
 /* Chip-Rev names for each device-type */
 static struct {

-    char* name;
+       char *name;

 } chip_rev[] = {
 } chip_rev[] = {

-       {"BCM5700VIGIL"},
-       {"BCM5700A6"},
-       {"BCM5700T6"},
-       {"BCM5700A9"},
-       {"BCM5700T9"},
-       {"BCM5700"},
-       {"BCM5701A5"},
-       {"BCM5701T1"},
-       {"BCM5701T8"},
-       {"BCM5701A7"},
-       {"BCM5701A10"},
-       {"BCM5701A12"},
-       {"BCM5701"},
-       {"BCM5702"},
-       {"BCM5703"},
-       {"BCM5703A31"},
-       {"TC996T"},
-       {"TC996ST"},
-       {"TC996SSX"},
-       {"TC996SX"},
-       {"TC996BT"},
-       {"TC997T"},
-       {"TC997SX"},
-       {"TC1000T"},
-       {"TC940BR01"},
-       {"TC942BR01"},
-       {"NC6770"},
-       {"NC7760"},
-       {"NC7770"},
-       {"NC7780"},
-       {0}
+       {
+       "BCM5700VIGIL"}, {
+       "BCM5700A6"}, {
+       "BCM5700T6"}, {
+       "BCM5700A9"}, {
+       "BCM5700T9"}, {
+       "BCM5700"}, {
+       "BCM5701A5"}, {
+       "BCM5701T1"}, {
+       "BCM5701T8"}, {
+       "BCM5701A7"}, {
+       "BCM5701A10"}, {
+       "BCM5701A12"}, {
+       "BCM5701"}, {
+       "BCM5702"}, {
+       "BCM5703"}, {
+       "BCM5703A31"}, {
+       "TC996T"}, {
+       "TC996ST"}, {
+       "TC996SSX"}, {
+       "TC996SX"}, {
+       "TC996BT"}, {
+       "TC997T"}, {
+       "TC997SX"}, {
+       "TC1000T"}, {
+       "TC940BR01"}, {
+       "TC942BR01"}, {
+       "NC6770"}, {
+       "NC7760"}, {
+       "NC7770"}, {
+       "NC7780"}, {
+       0}

 };
 
 };
 

-

 /* indexed by board_t, above */
 static struct {
 /* indexed by board_t, above */
 static struct {

-    char *name;
+       char *name;

 } board_info[] = {
 } board_info[] = {

-       { "Broadcom Vigil B5700 1000Base-T" },
-       { "Broadcom BCM5700 1000Base-T" },
-       { "Broadcom BCM5700 1000Base-SX" },
-       { "Broadcom BCM5700 1000Base-SX" },
-       { "Broadcom BCM5700 1000Base-T" },
-       { "Broadcom BCM5700" },
-       { "Broadcom BCM5701 1000Base-T" },
-       { "Broadcom BCM5701 1000Base-T" },
-       { "Broadcom BCM5701 1000Base-T" },
-       { "Broadcom BCM5701 1000Base-SX" },
-       { "Broadcom BCM5701 1000Base-T" },
-       { "Broadcom BCM5701 1000Base-T" },
-       { "Broadcom BCM5701" },
-       { "Broadcom BCM5702 1000Base-T" },
-       { "Broadcom BCM5703 1000Base-T" },
-       { "Broadcom BCM5703 1000Base-SX" },
-       { "3Com 3C996 10/100/1000 Server NIC" },
-       { "3Com 3C996 10/100/1000 Server NIC" },
-       { "3Com 3C996 Gigabit Fiber-SX Server NIC" },
-       { "3Com 3C996 Gigabit Fiber-SX Server NIC" },
-       { "3Com 3C996B Gigabit Server NIC" },
-       { "3Com 3C997 Gigabit Server NIC" },
-       { "3Com 3C997 Gigabit Fiber-SX Server NIC" },
-       { "3Com 3C1000 Gigabit NIC" },
-       { "3Com 3C940 Gigabit LOM (21X21)" },
-       { "3Com 3C942 Gigabit LOM (31X31)" },
-       { "Compaq NC6770 Gigabit Server Adapter" },
-       { "Compaq NC7760 Gigabit Server Adapter" },
-       { "Compaq NC7770 Gigabit Server Adapter" },
-       { "Compaq NC7780 Gigabit Server Adapter" },
-       { 0 },
-};
+       {
+       "Broadcom Vigil B5700 1000Base-T"}, {
+       "Broadcom BCM5700 1000Base-T"}, {
+       "Broadcom BCM5700 1000Base-SX"}, {
+       "Broadcom BCM5700 1000Base-SX"}, {
+       "Broadcom BCM5700 1000Base-T"}, {
+       "Broadcom BCM5700"}, {
+       "Broadcom BCM5701 1000Base-T"}, {
+       "Broadcom BCM5701 1000Base-T"}, {
+       "Broadcom BCM5701 1000Base-T"}, {
+       "Broadcom BCM5701 1000Base-SX"}, {
+       "Broadcom BCM5701 1000Base-T"}, {
+       "Broadcom BCM5701 1000Base-T"}, {
+       "Broadcom BCM5701"}, {
+       "Broadcom BCM5702 1000Base-T"}, {
+       "Broadcom BCM5703 1000Base-T"}, {
+       "Broadcom BCM5703 1000Base-SX"}, {
+       "3Com 3C996 10/100/1000 Server NIC"}, {
+       "3Com 3C996 10/100/1000 Server NIC"}, {
+       "3Com 3C996 Gigabit Fiber-SX Server NIC"}, {
+       "3Com 3C996 Gigabit Fiber-SX Server NIC"}, {
+       "3Com 3C996B Gigabit Server NIC"}, {
+       "3Com 3C997 Gigabit Server NIC"}, {
+       "3Com 3C997 Gigabit Fiber-SX Server NIC"}, {
+       "3Com 3C1000 Gigabit NIC"}, {
+       "3Com 3C940 Gigabit LOM (21X21)"}, {
+       "3Com 3C942 Gigabit LOM (31X31)"}, {
+       "Compaq NC6770 Gigabit Server Adapter"}, {
+       "Compaq NC7760 Gigabit Server Adapter"}, {
+       "Compaq NC7770 Gigabit Server Adapter"}, {
+       "Compaq NC7780 Gigabit Server Adapter"}, {
+0},};

 
 /* PCI Devices which use the 570x chipset */
 struct pci_device_table {
 
 /* PCI Devices which use the 570x chipset */
 struct pci_device_table {

-    unsigned short vendor_id, device_id; /* Vendor/DeviceID */
-    unsigned short subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
-    unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
-    unsigned long board_id;        /* Data private to the driver */
-    int io_size, min_latency;
+       unsigned short vendor_id, device_id;    /* Vendor/DeviceID */
+       unsigned short subvendor, subdevice;    /* Subsystem ID's or PCI_ANY_ID */
+       unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
+       unsigned long board_id; /* Data private to the driver */
+       int io_size, min_latency;

 } bcm570xDevices[] = {
 } bcm570xDevices[] = {

-       {0x14e4, 0x1644, 0x1014, 0x0277, 0, 0, BCM5700VIGIL ,128,32},
-       {0x14e4, 0x1644, 0x14e4, 0x1644, 0, 0, BCM5700A6 ,128,32},
-       {0x14e4, 0x1644, 0x14e4, 0x2, 0, 0, BCM5700T6 ,128,32},
-       {0x14e4, 0x1644, 0x14e4, 0x3, 0, 0, BCM5700A9 ,128,32},
-       {0x14e4, 0x1644, 0x14e4, 0x4, 0, 0, BCM5700T9 ,128,32},
-       {0x14e4, 0x1644, 0x1028, 0xd1, 0, 0, BCM5700 ,128,32},
-       {0x14e4, 0x1644, 0x1028, 0x0106, 0, 0, BCM5700 ,128,32},
-       {0x14e4, 0x1644, 0x1028, 0x0109, 0, 0, BCM5700 ,128,32},
-       {0x14e4, 0x1644, 0x1028, 0x010a, 0, 0, BCM5700 ,128,32},
-       {0x14e4, 0x1644, 0x10b7, 0x1000, 0, 0, TC996T ,128,32},
-       {0x14e4, 0x1644, 0x10b7, 0x1001, 0, 0, TC996ST ,128,32},
-       {0x14e4, 0x1644, 0x10b7, 0x1002, 0, 0, TC996SSX ,128,32},
-       {0x14e4, 0x1644, 0x10b7, 0x1003, 0, 0, TC997T ,128,32},
-       {0x14e4, 0x1644, 0x10b7, 0x1005, 0, 0, TC997SX ,128,32},
-       {0x14e4, 0x1644, 0x10b7, 0x1008, 0, 0, TC942BR01 ,128,32},
-       {0x14e4, 0x1644, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5700 ,128,32},
-       {0x14e4, 0x1645, 0x14e4, 1, 0, 0, BCM5701A5 ,128,32},
-       {0x14e4, 0x1645, 0x14e4, 5, 0, 0, BCM5701T1 ,128,32},
-       {0x14e4, 0x1645, 0x14e4, 6, 0, 0, BCM5701T8 ,128,32},
-       {0x14e4, 0x1645, 0x14e4, 7, 0, 0, BCM5701A7 ,128,32},
-       {0x14e4, 0x1645, 0x14e4, 8, 0, 0, BCM5701A10 ,128,32},
-       {0x14e4, 0x1645, 0x14e4, 0x8008, 0, 0, BCM5701A12 ,128,32},
-       {0x14e4, 0x1645, 0x0e11, 0xc1, 0, 0, NC6770 ,128,32},
-       {0x14e4, 0x1645, 0x0e11, 0x7c, 0, 0, NC7770 ,128,32},
-       {0x14e4, 0x1645, 0x0e11, 0x85, 0, 0, NC7780 ,128,32},
-       {0x14e4, 0x1645, 0x1028, 0x0121, 0, 0, BCM5701 ,128,32},
-       {0x14e4, 0x1645, 0x10b7, 0x1004, 0, 0, TC996SX ,128,32},
-       {0x14e4, 0x1645, 0x10b7, 0x1006, 0, 0, TC996BT ,128,32},
-       {0x14e4, 0x1645, 0x10b7, 0x1007, 0, 0, TC1000T ,128,32},
-       {0x14e4, 0x1645, 0x10b7, 0x1008, 0, 0, TC940BR01 ,128,32},
-       {0x14e4, 0x1645, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5701 ,128,32},
-       {0x14e4, 0x1646, 0x14e4, 0x8009, 0, 0, BCM5702 ,128,32},
-       {0x14e4, 0x1646, 0x0e11, 0xbb, 0, 0, NC7760 ,128,32},
-       {0x14e4, 0x1646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702 ,128,32},
-       {0x14e4, 0x16a6, 0x14e4, 0x8009, 0, 0, BCM5702 ,128,32},
-       {0x14e4, 0x16a6, 0x0e11, 0xbb, 0, 0, NC7760 ,128,32},
-       {0x14e4, 0x16a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702 ,128,32},
-       {0x14e4, 0x1647, 0x14e4, 0x0009, 0, 0, BCM5703 ,128,32},
-       {0x14e4, 0x1647, 0x14e4, 0x000a, 0, 0, BCM5703A31 ,128,32},
-       {0x14e4, 0x1647, 0x14e4, 0x000b, 0, 0, BCM5703 ,128,32},
-       {0x14e4, 0x1647, 0x14e4, 0x800a, 0, 0, BCM5703 ,128,32},
-       {0x14e4, 0x1647, 0x0e11, 0x9a, 0, 0, NC7770 ,128,32},
-       {0x14e4, 0x1647, 0x0e11, 0x99, 0, 0, NC7780 ,128,32},
-       {0x14e4, 0x1647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703 ,128,32},
-       {0x14e4, 0x16a7, 0x14e4, 0x0009, 0, 0, BCM5703 ,128,32},
-       {0x14e4, 0x16a7, 0x14e4, 0x000a, 0, 0, BCM5703A31 ,128,32},
-       {0x14e4, 0x16a7, 0x14e4, 0x000b, 0, 0, BCM5703 ,128,32},
-       {0x14e4, 0x16a7, 0x14e4, 0x800a, 0, 0, BCM5703 ,128,32},
-       {0x14e4, 0x16a7, 0x0e11, 0x9a, 0, 0, NC7770 ,128,32},
-       {0x14e4, 0x16a7, 0x0e11, 0x99, 0, 0, NC7780 ,128,32},
-       {0x14e4, 0x16a7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703 ,128,32}
+       {
+       0x14e4, 0x1644, 0x1014, 0x0277, 0, 0, BCM5700VIGIL, 128, 32}, {
+       0x14e4, 0x1644, 0x14e4, 0x1644, 0, 0, BCM5700A6, 128, 32}, {
+       0x14e4, 0x1644, 0x14e4, 0x2, 0, 0, BCM5700T6, 128, 32}, {
+       0x14e4, 0x1644, 0x14e4, 0x3, 0, 0, BCM5700A9, 128, 32}, {
+       0x14e4, 0x1644, 0x14e4, 0x4, 0, 0, BCM5700T9, 128, 32}, {
+       0x14e4, 0x1644, 0x1028, 0xd1, 0, 0, BCM5700, 128, 32}, {
+       0x14e4, 0x1644, 0x1028, 0x0106, 0, 0, BCM5700, 128, 32}, {
+       0x14e4, 0x1644, 0x1028, 0x0109, 0, 0, BCM5700, 128, 32}, {
+       0x14e4, 0x1644, 0x1028, 0x010a, 0, 0, BCM5700, 128, 32}, {
+       0x14e4, 0x1644, 0x10b7, 0x1000, 0, 0, TC996T, 128, 32}, {
+       0x14e4, 0x1644, 0x10b7, 0x1001, 0, 0, TC996ST, 128, 32}, {
+       0x14e4, 0x1644, 0x10b7, 0x1002, 0, 0, TC996SSX, 128, 32}, {
+       0x14e4, 0x1644, 0x10b7, 0x1003, 0, 0, TC997T, 128, 32}, {
+       0x14e4, 0x1644, 0x10b7, 0x1005, 0, 0, TC997SX, 128, 32}, {
+       0x14e4, 0x1644, 0x10b7, 0x1008, 0, 0, TC942BR01, 128, 32}, {
+       0x14e4, 0x1644, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5700, 128, 32}, {
+       0x14e4, 0x1645, 0x14e4, 1, 0, 0, BCM5701A5, 128, 32}, {
+       0x14e4, 0x1645, 0x14e4, 5, 0, 0, BCM5701T1, 128, 32}, {
+       0x14e4, 0x1645, 0x14e4, 6, 0, 0, BCM5701T8, 128, 32}, {
+       0x14e4, 0x1645, 0x14e4, 7, 0, 0, BCM5701A7, 128, 32}, {
+       0x14e4, 0x1645, 0x14e4, 8, 0, 0, BCM5701A10, 128, 32}, {
+       0x14e4, 0x1645, 0x14e4, 0x8008, 0, 0, BCM5701A12, 128, 32}, {
+       0x14e4, 0x1645, 0x0e11, 0xc1, 0, 0, NC6770, 128, 32}, {
+       0x14e4, 0x1645, 0x0e11, 0x7c, 0, 0, NC7770, 128, 32}, {
+       0x14e4, 0x1645, 0x0e11, 0x85, 0, 0, NC7780, 128, 32}, {
+       0x14e4, 0x1645, 0x1028, 0x0121, 0, 0, BCM5701, 128, 32}, {
+       0x14e4, 0x1645, 0x10b7, 0x1004, 0, 0, TC996SX, 128, 32}, {
+       0x14e4, 0x1645, 0x10b7, 0x1006, 0, 0, TC996BT, 128, 32}, {
+       0x14e4, 0x1645, 0x10b7, 0x1007, 0, 0, TC1000T, 128, 32}, {
+       0x14e4, 0x1645, 0x10b7, 0x1008, 0, 0, TC940BR01, 128, 32}, {
+       0x14e4, 0x1645, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5701, 128, 32}, {
+       0x14e4, 0x1646, 0x14e4, 0x8009, 0, 0, BCM5702, 128, 32}, {
+       0x14e4, 0x1646, 0x0e11, 0xbb, 0, 0, NC7760, 128, 32}, {
+       0x14e4, 0x1646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702, 128, 32}, {
+       0x14e4, 0x16a6, 0x14e4, 0x8009, 0, 0, BCM5702, 128, 32}, {
+       0x14e4, 0x16a6, 0x0e11, 0xbb, 0, 0, NC7760, 128, 32}, {
+       0x14e4, 0x16a6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5702, 128, 32}, {
+       0x14e4, 0x1647, 0x14e4, 0x0009, 0, 0, BCM5703, 128, 32}, {
+       0x14e4, 0x1647, 0x14e4, 0x000a, 0, 0, BCM5703A31, 128, 32}, {
+       0x14e4, 0x1647, 0x14e4, 0x000b, 0, 0, BCM5703, 128, 32}, {
+       0x14e4, 0x1647, 0x14e4, 0x800a, 0, 0, BCM5703, 128, 32}, {
+       0x14e4, 0x1647, 0x0e11, 0x9a, 0, 0, NC7770, 128, 32}, {
+       0x14e4, 0x1647, 0x0e11, 0x99, 0, 0, NC7780, 128, 32}, {
+       0x14e4, 0x1647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703, 128, 32}, {
+       0x14e4, 0x16a7, 0x14e4, 0x0009, 0, 0, BCM5703, 128, 32}, {
+       0x14e4, 0x16a7, 0x14e4, 0x000a, 0, 0, BCM5703A31, 128, 32}, {
+       0x14e4, 0x16a7, 0x14e4, 0x000b, 0, 0, BCM5703, 128, 32}, {
+       0x14e4, 0x16a7, 0x14e4, 0x800a, 0, 0, BCM5703, 128, 32}, {
+       0x14e4, 0x16a7, 0x0e11, 0x9a, 0, 0, NC7770, 128, 32}, {
+       0x14e4, 0x16a7, 0x0e11, 0x99, 0, 0, NC7780, 128, 32}, {
+       0x14e4, 0x16a7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BCM5703, 128, 32}

 };
 
 #define n570xDevices   (sizeof(bcm570xDevices)/sizeof(bcm570xDevices[0]))
 
 };
 
 #define n570xDevices   (sizeof(bcm570xDevices)/sizeof(bcm570xDevices[0]))
 

-

 /*
  * Allocate a packet buffer from the bcm570x packet pool.
  */
 /*
  * Allocate a packet buffer from the bcm570x packet pool.
  */

-void *
-bcm570xPktAlloc(int u, int pksize)
+void *bcm570xPktAlloc (int u, int pksize)

 {
 {

-    return malloc(pksize);
+       return malloc (pksize);

 }
 
 /*
  * Free a packet previously allocated from the bcm570x packet
  * buffer pool.
  */
 }
 
 /*
  * Free a packet previously allocated from the bcm570x packet
  * buffer pool.
  */

-void
-bcm570xPktFree(int u, void *p)
+void bcm570xPktFree (int u, void *p)

 {
 {

-    free(p);
+       free (p);

 }
 
 }
 

-int
-bcm570xReplenishRxBuffers(PUM_DEVICE_BLOCK pUmDevice)
+int bcm570xReplenishRxBuffers (PUM_DEVICE_BLOCK pUmDevice)

 {
 {

-    PLM_PACKET pPacket;
-    PUM_PACKET pUmPacket;
-    void *skb;
-    int queue_rx = 0;
-    int ret = 0;
-
-    while ((pUmPacket = (PUM_PACKET)
-           QQ_PopHead(&pUmDevice->rx_out_of_buf_q.Container)) != 0) {
-
-       pPacket = (PLM_PACKET) pUmPacket;
-
-       /* reuse an old skb */
-       if (pUmPacket->skbuff) {
-           QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
-           queue_rx = 1;
-           continue;
-       }
-       if ( ( skb = bcm570xPktAlloc(pUmDevice->index,
-                                    pPacket->u.Rx.RxBufferSize + 2)) == 0) {
-           QQ_PushHead(&pUmDevice->rx_out_of_buf_q.Container,pPacket);
-           printf("NOTICE: Out of RX memory.\n");
-           ret = 1;
-           break;
-       }
+       PLM_PACKET pPacket;
+       PUM_PACKET pUmPacket;
+       void *skb;
+       int queue_rx = 0;
+       int ret = 0;
+
+       while ((pUmPacket = (PUM_PACKET)
+               QQ_PopHead (&pUmDevice->rx_out_of_buf_q.Container)) != 0) {
+
+               pPacket = (PLM_PACKET) pUmPacket;
+
+               /* reuse an old skb */
+               if (pUmPacket->skbuff) {
+                       QQ_PushTail (&pDevice->RxPacketFreeQ.Container,
+                                    pPacket);
+                       queue_rx = 1;
+                       continue;
+               }
+               if ((skb = bcm570xPktAlloc (pUmDevice->index,
+                                           pPacket->u.Rx.RxBufferSize + 2)) ==
+                   0) {
+                       QQ_PushHead (&pUmDevice->rx_out_of_buf_q.Container,
+                                    pPacket);
+                       printf ("NOTICE: Out of RX memory.\n");
+                       ret = 1;
+                       break;
+               }

 
 

-       pUmPacket->skbuff = skb;
-       QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
-       queue_rx = 1;
-    }
+               pUmPacket->skbuff = skb;
+               QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
+               queue_rx = 1;
+       }

 
 

-    if (queue_rx) {
-       LM_QueueRxPackets(pDevice);
-    }
+       if (queue_rx) {
+               LM_QueueRxPackets (pDevice);
+       }

 
 

-    return ret;
+       return ret;

 }
 
 /*
  * Probe, Map, and Init 570x device.
  */
 }
 
 /*
  * Probe, Map, and Init 570x device.
  */

-int eth_init(bd_t *bis)
+int eth_init (bd_t * bis)

 {
 {

-    int i, rv, devFound = FALSE;
-    pci_dev_t  devbusfn;
-    unsigned short status;
-
-    /* Find PCI device, if it exists, configure ...  */
-    for( i = 0; i < n570xDevices; i++){
-       devbusfn = pci_find_device(bcm570xDevices[i].vendor_id,
-                                  bcm570xDevices[i].device_id, 0);
-       if(devbusfn == -1) {
-           continue; /* No device of that vendor/device ID */
+       int i, rv, devFound = FALSE;
+       pci_dev_t devbusfn;
+       unsigned short status;
+
+       /* Find PCI device, if it exists, configure ...  */
+       for (i = 0; i < n570xDevices; i++) {
+               devbusfn = pci_find_device (bcm570xDevices[i].vendor_id,
+                                           bcm570xDevices[i].device_id, 0);
+               if (devbusfn == -1) {
+                       continue;       /* No device of that vendor/device ID */
+               } else {
+
+                       /* Set ILINE */
+                       pci_write_config_byte (devbusfn,
+                                              PCI_INTERRUPT_LINE,
+                                              BCM570X_ILINE);
+
+                       /*
+                        * 0x10 - 0x14 define one 64-bit MBAR.
+                        * 0x14 is the higher-order address bits of the BAR.
+                        */
+                       pci_write_config_dword (devbusfn,
+                                               PCI_BASE_ADDRESS_1, 0);
+
+                       ioBase = BCM570X_MBAR;
+
+                       pci_write_config_dword (devbusfn,
+                                               PCI_BASE_ADDRESS_0, ioBase);
+
+                       /*
+                        * Enable PCI memory, IO, and Master -- don't
+                        * reset any status bits in doing so.
+                        */
+                       pci_read_config_word (devbusfn, PCI_COMMAND, &status);
+
+                       status |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
+
+                       pci_write_config_word (devbusfn, PCI_COMMAND, status);
+
+                       printf
+                           ("\n%s: bus %d, device %d, function %d: MBAR=0x%x\n",
+                            board_info[bcm570xDevices[i].board_id].name,
+                            PCI_BUS (devbusfn), PCI_DEV (devbusfn),
+                            PCI_FUNC (devbusfn), ioBase);
+
+                       /* Allocate once, but always clear on init */
+                       if (!pDevice) {
+                               pDevice = malloc (sizeof (UM_DEVICE_BLOCK));
+                               pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+                               memset (pDevice, 0x0, sizeof (UM_DEVICE_BLOCK));
+                       }
+
+                       /* Configure pci dev structure */
+                       pUmDevice->pdev = devbusfn;
+                       pUmDevice->index = 0;
+                       pUmDevice->tx_pkt = 0;
+                       pUmDevice->rx_pkt = 0;
+                       devFound = TRUE;
+                       break;
+               }
+       }
+
+       if (!devFound) {
+               printf
+                   ("eth_init: FAILURE: no BCM570x Ethernet devices found.\n");
+               return -1;
+       }
+
+       /* Setup defaults for chip */
+       pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
+
+       if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0) {
+               pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;

        } else {
 
        } else {
 

-           /* Set ILINE */
-           pci_write_config_byte(devbusfn,
-                                 PCI_INTERRUPT_LINE, BCM570X_ILINE);
-
-           /*
-            * 0x10 - 0x14 define one 64-bit MBAR.
-            * 0x14 is the higher-order address bits of the BAR.
-            */
-           pci_write_config_dword(devbusfn,
-                                  PCI_BASE_ADDRESS_1, 0);
-
-           ioBase = BCM570X_MBAR;
-
-           pci_write_config_dword(devbusfn,
-                                  PCI_BASE_ADDRESS_0, ioBase);
-
-           /*
-            * Enable PCI memory, IO, and Master -- don't
-            * reset any status bits in doing so.
-            */
-           pci_read_config_word(devbusfn,
-                                PCI_COMMAND, &status);
-
-           status |= PCI_COMMAND_MEMORY|PCI_COMMAND_MASTER;
-
-           pci_write_config_word(devbusfn,
-                                 PCI_COMMAND, status);
-
-           printf("\n%s: bus %d, device %d, function %d: MBAR=0x%x\n",
-                  board_info[bcm570xDevices[i].board_id].name,
-                  PCI_BUS(devbusfn),
-                  PCI_DEV(devbusfn),
-                  PCI_FUNC(devbusfn),
-                  ioBase);
-
-           /* Allocate once, but always clear on init */
-           if (!pDevice) {
-               pDevice = malloc(sizeof(UM_DEVICE_BLOCK));
-               pUmDevice = (PUM_DEVICE_BLOCK)pDevice;
-               memset(pDevice, 0x0, sizeof(UM_DEVICE_BLOCK));
-           }
-
-           /* Configure pci dev structure */
-           pUmDevice->pdev = devbusfn;
-           pUmDevice->index = 0;
-           pUmDevice->tx_pkt = 0;
-           pUmDevice->rx_pkt = 0;
-           devFound = TRUE;
-           break;
+               if (rx_checksum[i]) {
+                       pDevice->TaskToOffload |=
+                           LM_TASK_OFFLOAD_RX_TCP_CHECKSUM |
+                           LM_TASK_OFFLOAD_RX_UDP_CHECKSUM;
+               }
+
+               if (tx_checksum[i]) {
+                       pDevice->TaskToOffload |=
+                           LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
+                           LM_TASK_OFFLOAD_TX_UDP_CHECKSUM;
+                       pDevice->NoTxPseudoHdrChksum = TRUE;
+               }
+       }
+
+       /* Set Device PCI Memory base address */
+       pDevice->pMappedMemBase = (PLM_UINT8) ioBase;
+
+       /* Pull down adapter info */
+       if ((rv = LM_GetAdapterInfo (pDevice)) != LM_STATUS_SUCCESS) {
+               printf ("bcm570xEnd: LM_GetAdapterInfo failed: rv=%d!\n", rv);
+               return -2;

        }
        }

-    }

 
 

-    if(!devFound){
-       printf("eth_init: FAILURE: no BCM570x Ethernet devices found.\n");
-       return -1;
-    }
+       /* Lock not needed */
+       pUmDevice->do_global_lock = 0;

 
 

-    /* Setup defaults for chip */
-    pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
+       if (T3_ASIC_REV (pUmDevice->lm_dev.ChipRevId) == T3_ASIC_REV_5700) {
+               /* The 5700 chip works best without interleaved register */
+               /* accesses on certain machines. */
+               pUmDevice->do_global_lock = 1;
+       }

 
 

-    if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0) {
-       pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
-    } else {
+       /* Setup timer delays */
+       if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+               pDevice->UseTaggedStatus = TRUE;
+               pUmDevice->timer_interval = CFG_HZ;
+       } else {
+               pUmDevice->timer_interval = CFG_HZ / 50;
+       }

 
 

-       if (rx_checksum[i]) {
-           pDevice->TaskToOffload |=
-               LM_TASK_OFFLOAD_RX_TCP_CHECKSUM |
-               LM_TASK_OFFLOAD_RX_UDP_CHECKSUM;
+       /* Grab name .... */
+       pUmDevice->name =
+           (char *)malloc (strlen (board_info[bcm570xDevices[i].board_id].name)
+                           + 1);
+       strcpy (pUmDevice->name, board_info[bcm570xDevices[i].board_id].name);
+
+       memcpy (pDevice->NodeAddress, bis->bi_enetaddr, 6);
+       LM_SetMacAddress (pDevice, bis->bi_enetaddr);
+       /* Init queues  .. */
+       QQ_InitQueue (&pUmDevice->rx_out_of_buf_q.Container,
+                     MAX_RX_PACKET_DESC_COUNT);
+       pUmDevice->rx_last_cnt = pUmDevice->tx_last_cnt = 0;
+
+       /* delay for 4 seconds */
+       pUmDevice->delayed_link_ind = (4 * CFG_HZ) / pUmDevice->timer_interval;
+
+       pUmDevice->adaptive_expiry = CFG_HZ / pUmDevice->timer_interval;
+
+       /* Sometimes we get spurious ints. after reset when link is down. */
+       /* This field tells the isr to service the int. even if there is */
+       /* no status block update. */
+       pUmDevice->adapter_just_inited =
+           (3 * CFG_HZ) / pUmDevice->timer_interval;
+
+       /* Initialize 570x */
+       if (LM_InitializeAdapter (pDevice) != LM_STATUS_SUCCESS) {
+               printf ("ERROR: Adapter initialization failed.\n");
+               return ERROR;

        }
 
        }
 

-       if (tx_checksum[i]) {
-           pDevice->TaskToOffload |=
-               LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
-               LM_TASK_OFFLOAD_TX_UDP_CHECKSUM;
-           pDevice->NoTxPseudoHdrChksum = TRUE;
+       /* Enable chip ISR */
+       LM_EnableInterrupt (pDevice);
+
+       /* Clear MC table */
+       LM_MulticastClear (pDevice);
+
+       /* Enable Multicast */
+       LM_SetReceiveMask (pDevice,
+                          pDevice->ReceiveMask | LM_ACCEPT_ALL_MULTICAST);
+
+       pUmDevice->opened = 1;
+       pUmDevice->tx_full = 0;
+       pUmDevice->tx_pkt = 0;
+       pUmDevice->rx_pkt = 0;
+       printf ("eth%d: %s @0x%lx,",
+               pDevice->index, pUmDevice->name, (unsigned long)ioBase);
+       printf ("node addr ");
+       for (i = 0; i < 6; i++) {
+               printf ("%2.2x", pDevice->NodeAddress[i]);

        }
        }

-    }
-
-    /* Set Device PCI Memory base address */
-    pDevice->pMappedMemBase = (PLM_UINT8) ioBase;
-
-    /* Pull down adapter info */
-    if ((rv = LM_GetAdapterInfo(pDevice)) != LM_STATUS_SUCCESS) {
-       printf("bcm570xEnd: LM_GetAdapterInfo failed: rv=%d!\n", rv );
-       return -2;
-    }
-
-    /* Lock not needed */
-    pUmDevice->do_global_lock = 0;
-
-    if (T3_ASIC_REV(pUmDevice->lm_dev.ChipRevId) == T3_ASIC_REV_5700) {
-       /* The 5700 chip works best without interleaved register */
-       /* accesses on certain machines. */
-       pUmDevice->do_global_lock = 1;
-    }
-
-    /* Setup timer delays */
-    if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) {
-       pDevice->UseTaggedStatus = TRUE;
-       pUmDevice->timer_interval = CFG_HZ;
-    }
-    else {
-       pUmDevice->timer_interval = CFG_HZ / 50;
-    }
-
-    /* Grab name .... */
-    pUmDevice->name =
-       (char*)malloc(strlen(board_info[bcm570xDevices[i].board_id].name)+1);
-    strcpy(pUmDevice->name,board_info[bcm570xDevices[i].board_id].name);
-
-    memcpy(pDevice->NodeAddress, bis->bi_enetaddr, 6);
-    LM_SetMacAddress(pDevice, bis->bi_enetaddr);
-    /* Init queues  .. */
-    QQ_InitQueue(&pUmDevice->rx_out_of_buf_q.Container,
-                MAX_RX_PACKET_DESC_COUNT);
-    pUmDevice->rx_last_cnt = pUmDevice->tx_last_cnt = 0;
-
-    /* delay for 4 seconds */
-    pUmDevice->delayed_link_ind =
-       (4 * CFG_HZ) / pUmDevice->timer_interval;
-
-    pUmDevice->adaptive_expiry =
-       CFG_HZ / pUmDevice->timer_interval;
-
-    /* Sometimes we get spurious ints. after reset when link is down. */
-    /* This field tells the isr to service the int. even if there is */
-    /* no status block update. */
-    pUmDevice->adapter_just_inited =
-       (3 * CFG_HZ) / pUmDevice->timer_interval;
-
-    /* Initialize 570x */
-    if (LM_InitializeAdapter(pDevice) != LM_STATUS_SUCCESS) {
-       printf("ERROR: Adapter initialization failed.\n");
-       return ERROR;
-    }
-
-    /* Enable chip ISR */
-    LM_EnableInterrupt(pDevice);
-
-    /* Clear MC table */
-    LM_MulticastClear(pDevice);
-
-    /* Enable Multicast */
-    LM_SetReceiveMask(pDevice,
-                     pDevice->ReceiveMask | LM_ACCEPT_ALL_MULTICAST);
-
-    pUmDevice->opened = 1;
-    pUmDevice->tx_full = 0;
-    pUmDevice->tx_pkt = 0;
-    pUmDevice->rx_pkt = 0;
-    printf("eth%d: %s @0x%lx,",
-          pDevice->index, pUmDevice->name, (unsigned long)ioBase);
-    printf(    "node addr ");
-    for (i = 0; i < 6; i++) {
-       printf("%2.2x", pDevice->NodeAddress[i]);
-    }
-    printf("\n");
-
-    printf("eth%d: ", pDevice->index);
-    printf("%s with ",
-          chip_rev[bcm570xDevices[i].board_id].name);
-
-    if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5400_PHY_ID)
-       printf("Broadcom BCM5400 Copper ");
-    else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
-       printf("Broadcom BCM5401 Copper ");
-    else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5411_PHY_ID)
-       printf("Broadcom BCM5411 Copper ");
-    else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5701_PHY_ID)
-       printf("Broadcom BCM5701 Integrated Copper ");
-    else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5703_PHY_ID)
-       printf("Broadcom BCM5703 Integrated Copper ");
-    else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM8002_PHY_ID)
-       printf("Broadcom BCM8002 SerDes ");
-    else if (pDevice->EnableTbi)
-       printf("Agilent HDMP-1636 SerDes ");
-    else
-       printf("Unknown ");
-    printf("transceiver found\n");
-
-    printf("eth%d: %s, MTU: %d,",
-          pDevice->index, pDevice->BusSpeedStr, 1500);
-
-    if ((pDevice->ChipRevId != T3_CHIP_ID_5700_B0) &&
-       rx_checksum[i])
-       printf("Rx Checksum ON\n");
-    else
-       printf("Rx Checksum OFF\n");
-    initialized++;
-
-    return 0;
+       printf ("\n");
+
+       printf ("eth%d: ", pDevice->index);
+       printf ("%s with ", chip_rev[bcm570xDevices[i].board_id].name);
+
+       if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5400_PHY_ID)
+               printf ("Broadcom BCM5400 Copper ");
+       else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
+               printf ("Broadcom BCM5401 Copper ");
+       else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5411_PHY_ID)
+               printf ("Broadcom BCM5411 Copper ");
+       else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5701_PHY_ID)
+               printf ("Broadcom BCM5701 Integrated Copper ");
+       else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5703_PHY_ID)
+               printf ("Broadcom BCM5703 Integrated Copper ");
+       else if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM8002_PHY_ID)
+               printf ("Broadcom BCM8002 SerDes ");
+       else if (pDevice->EnableTbi)
+               printf ("Agilent HDMP-1636 SerDes ");
+       else
+               printf ("Unknown ");
+       printf ("transceiver found\n");
+
+       printf ("eth%d: %s, MTU: %d,",
+               pDevice->index, pDevice->BusSpeedStr, 1500);
+
+       if ((pDevice->ChipRevId != T3_CHIP_ID_5700_B0) && rx_checksum[i])
+               printf ("Rx Checksum ON\n");
+       else
+               printf ("Rx Checksum OFF\n");
+       initialized++;
+
+       return 0;

 }
 
 /* Ethernet Interrupt service routine */
 }
 
 /* Ethernet Interrupt service routine */

-void
-eth_isr(void)
+void eth_isr (void)

 {
 {

-    LM_UINT32 oldtag, newtag;
-    int i;
-
-    pUmDevice->interrupt = 1;
-
-    if (pDevice->UseTaggedStatus) {
-       if ((pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) ||
-           pUmDevice->adapter_just_inited) {
-           MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1);
-           oldtag = pDevice->pStatusBlkVirt->StatusTag;
-
-           for (i = 0; ; i++) {
-               pDevice->pStatusBlkVirt->Status &= ~STATUS_BLOCK_UPDATED;
-               LM_ServiceInterrupts(pDevice);
-               newtag = pDevice->pStatusBlkVirt->StatusTag;
-               if ((newtag == oldtag) || (i > 50)) {
-                   MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, newtag << 24);
-                   if (pDevice->UndiFix) {
-                       REG_WR(pDevice, Grc.LocalCtrl,
-                              pDevice->GrcLocalCtrl | 0x2);
-                   }
-                   break;
-                }
-               oldtag = newtag;
-           }
+       LM_UINT32 oldtag, newtag;
+       int i;
+
+       pUmDevice->interrupt = 1;
+
+       if (pDevice->UseTaggedStatus) {
+               if ((pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) ||
+                   pUmDevice->adapter_just_inited) {
+                       MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 1);
+                       oldtag = pDevice->pStatusBlkVirt->StatusTag;
+
+                       for (i = 0;; i++) {
+                               pDevice->pStatusBlkVirt->Status &=
+                                   ~STATUS_BLOCK_UPDATED;
+                               LM_ServiceInterrupts (pDevice);
+                               newtag = pDevice->pStatusBlkVirt->StatusTag;
+                               if ((newtag == oldtag) || (i > 50)) {
+                                       MB_REG_WR (pDevice,
+                                                  Mailbox.Interrupt[0].Low,
+                                                  newtag << 24);
+                                       if (pDevice->UndiFix) {
+                                               REG_WR (pDevice, Grc.LocalCtrl,
+                                                       pDevice->
+                                                       GrcLocalCtrl | 0x2);
+                                       }
+                                       break;
+                               }
+                               oldtag = newtag;
+                       }
+               }
+       } else {
+               while (pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) {
+                       unsigned int dummy;
+
+                       pDevice->pMemView->Mailbox.Interrupt[0].Low = 1;
+                       pDevice->pStatusBlkVirt->Status &=
+                           ~STATUS_BLOCK_UPDATED;
+                       LM_ServiceInterrupts (pDevice);
+                       pDevice->pMemView->Mailbox.Interrupt[0].Low = 0;
+                       dummy = pDevice->pMemView->Mailbox.Interrupt[0].Low;
+               }
+       }
+
+       /* Allocate new RX buffers */
+       if (QQ_GetEntryCnt (&pUmDevice->rx_out_of_buf_q.Container)) {
+               bcm570xReplenishRxBuffers (pUmDevice);

        }
        }

-    }
-    else {
-       while (pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) {
-           unsigned int dummy;
-
-           pDevice->pMemView->Mailbox.Interrupt[0].Low = 1;
-           pDevice->pStatusBlkVirt->Status &= ~STATUS_BLOCK_UPDATED;
-           LM_ServiceInterrupts(pDevice);
-           pDevice->pMemView->Mailbox.Interrupt[0].Low = 0;
-           dummy = pDevice->pMemView->Mailbox.Interrupt[0].Low;
+
+       /* Queue packets */
+       if (QQ_GetEntryCnt (&pDevice->RxPacketFreeQ.Container)) {
+               LM_QueueRxPackets (pDevice);
+       }
+
+       if (pUmDevice->tx_queued) {
+               pUmDevice->tx_queued = 0;

        }
        }

-    }
-
-    /* Allocate new RX buffers */
-    if (QQ_GetEntryCnt(&pUmDevice->rx_out_of_buf_q.Container)) {
-       bcm570xReplenishRxBuffers(pUmDevice);
-    }
-
-    /* Queue packets */
-    if (QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container)) {
-       LM_QueueRxPackets(pDevice);
-    }
-
-    if (pUmDevice->tx_queued) {
-       pUmDevice->tx_queued = 0;
-    }
-
-    if(pUmDevice->tx_full){
-       if(pDevice->LinkStatus != LM_STATUS_LINK_DOWN){
-           printf("NOTICE: tx was previously blocked, restarting MUX\n");
-           pUmDevice->tx_full = 0;
+
+       if (pUmDevice->tx_full) {
+               if (pDevice->LinkStatus != LM_STATUS_LINK_DOWN) {
+                       printf
+                           ("NOTICE: tx was previously blocked, restarting MUX\n");
+                       pUmDevice->tx_full = 0;
+               }

        }
        }

-    }

 
 

-    pUmDevice->interrupt = 0;
+       pUmDevice->interrupt = 0;

 
 }
 
 
 }
 

-int
-eth_send(volatile void *packet, int length)
+int eth_send (volatile void *packet, int length)

 {
 {

-    int status = 0;
+       int status = 0;

 #if ET_DEBUG
 #if ET_DEBUG

-    unsigned char* ptr = (unsigned char*)packet;
+       unsigned char *ptr = (unsigned char *)packet;

 #endif
 #endif

-    PLM_PACKET pPacket;
-    PUM_PACKET pUmPacket;
+       PLM_PACKET pPacket;
+       PUM_PACKET pUmPacket;

 
 

-    /* Link down, return */
-    while(pDevice->LinkStatus == LM_STATUS_LINK_DOWN) {
+       /* Link down, return */
+       while (pDevice->LinkStatus == LM_STATUS_LINK_DOWN) {

 #if 0
 #if 0

-       printf("eth%d: link down - check cable or link partner.\n",
-              pUmDevice->index);
+               printf ("eth%d: link down - check cable or link partner.\n",
+                       pUmDevice->index);

 #endif
 #endif

-       eth_isr();
+               eth_isr ();
+
+               /* Wait to see link for one-half a second before sending ... */
+               udelay (1500000);

 
 

-       /* Wait to see link for one-half a second before sending ... */
-       udelay(1500000);
+       }

 
 

-    }
+       /* Clear sent flag */
+       pUmDevice->tx_pkt = 0;

 
 

-    /* Clear sent flag */
-    pUmDevice->tx_pkt = 0;
+       /* Previously blocked */
+       if (pUmDevice->tx_full) {
+               printf ("eth%d: tx blocked.\n", pUmDevice->index);
+               return 0;
+       }

 
 

-    /* Previously blocked */
-    if(pUmDevice->tx_full){
-       printf("eth%d: tx blocked.\n", pUmDevice->index);
-       return 0;
-    }
+       pPacket = (PLM_PACKET)
+           QQ_PopHead (&pDevice->TxPacketFreeQ.Container);

 
 

-    pPacket = (PLM_PACKET)
-       QQ_PopHead(&pDevice->TxPacketFreeQ.Container);
+       if (pPacket == 0) {
+               pUmDevice->tx_full = 1;
+               printf ("bcm570xEndSend: TX full!\n");
+               return 0;
+       }

 
 

-    if (pPacket == 0) {
-       pUmDevice->tx_full = 1;
-       printf("bcm570xEndSend: TX full!\n");
-       return 0;
-    }
+       if (pDevice->SendBdLeft.counter == 0) {
+               pUmDevice->tx_full = 1;
+               printf ("bcm570xEndSend: no more TX descriptors!\n");
+               QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket);
+               return 0;
+       }

 
 

-    if (pDevice->SendBdLeft.counter == 0) {
-       pUmDevice->tx_full = 1;
-       printf("bcm570xEndSend: no more TX descriptors!\n");
-       QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket);
-       return 0;
-    }
-
-    if (length <= 0){
-       printf("eth: bad packet size: %d\n", length);
-       goto out;
-    }
-
-    /* Get packet buffers and fragment list */
-    pUmPacket = (PUM_PACKET) pPacket;
-    /* Single DMA Descriptor transmit.
-     * Fragments may be provided, but one DMA descriptor max is
-     * used to send the packet.
-     */
-    if (MM_CoalesceTxBuffer (pDevice, pPacket) != LM_STATUS_SUCCESS) {
-       if (pUmPacket->skbuff == NULL){
-           /* Packet was discarded */
-           printf("TX: failed (1)\n");
-           status = 1;
-       } else{
-           printf("TX: failed (2)\n");
-           status = 2;
+       if (length <= 0) {
+               printf ("eth: bad packet size: %d\n", length);
+               goto out;

        }
        }

-       QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket);
-       return status;
-    }
-
-    /* Copy packet to DMA buffer */
-    memset(pUmPacket->skbuff, 0x0, MAX_PACKET_SIZE);
-    memcpy((void*)pUmPacket->skbuff, (void*)packet, length);
-    pPacket->PacketSize = length;
-    pPacket->Flags |= SND_BD_FLAG_END|SND_BD_FLAG_COAL_NOW;
-    pPacket->u.Tx.FragCount = 1;
-    /* We've already provided a frame ready for transmission */
-    pPacket->Flags &= ~SND_BD_FLAG_TCP_UDP_CKSUM;
-
-    if ( LM_SendPacket(pDevice, pPacket) == LM_STATUS_FAILURE){
-       /*
-        *  A lower level send failure will push the packet descriptor back
-        *  in the free queue, so just deal with the VxWorks clusters.
+
+       /* Get packet buffers and fragment list */
+       pUmPacket = (PUM_PACKET) pPacket;
+       /* Single DMA Descriptor transmit.
+        * Fragments may be provided, but one DMA descriptor max is
+        * used to send the packet.

         */
         */

-       if (pUmPacket->skbuff == NULL){
-           printf("TX failed (1)!\n");
-           /* Packet was discarded */
-           status = 3;
-       } else {
-           /* A resource problem ... */
-           printf("TX failed (2)!\n");
-           status = 4;
+       if (MM_CoalesceTxBuffer (pDevice, pPacket) != LM_STATUS_SUCCESS) {
+               if (pUmPacket->skbuff == NULL) {
+                       /* Packet was discarded */
+                       printf ("TX: failed (1)\n");
+                       status = 1;
+               } else {
+                       printf ("TX: failed (2)\n");
+                       status = 2;
+               }
+               QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket);
+               return status;

        }
 
        }
 

-       if (QQ_GetEntryCnt(&pDevice->TxPacketFreeQ.Container) == 0) {
-           printf("TX: emptyQ!\n");
-           pUmDevice->tx_full = 1;
+       /* Copy packet to DMA buffer */
+       memset (pUmPacket->skbuff, 0x0, MAX_PACKET_SIZE);
+       memcpy ((void *)pUmPacket->skbuff, (void *)packet, length);
+       pPacket->PacketSize = length;
+       pPacket->Flags |= SND_BD_FLAG_END | SND_BD_FLAG_COAL_NOW;
+       pPacket->u.Tx.FragCount = 1;
+       /* We've already provided a frame ready for transmission */
+       pPacket->Flags &= ~SND_BD_FLAG_TCP_UDP_CKSUM;
+
+       if (LM_SendPacket (pDevice, pPacket) == LM_STATUS_FAILURE) {
+               /*
+                *  A lower level send failure will push the packet descriptor back
+                *  in the free queue, so just deal with the VxWorks clusters.
+                */
+               if (pUmPacket->skbuff == NULL) {
+                       printf ("TX failed (1)!\n");
+                       /* Packet was discarded */
+                       status = 3;
+               } else {
+                       /* A resource problem ... */
+                       printf ("TX failed (2)!\n");
+                       status = 4;
+               }
+
+               if (QQ_GetEntryCnt (&pDevice->TxPacketFreeQ.Container) == 0) {
+                       printf ("TX: emptyQ!\n");
+                       pUmDevice->tx_full = 1;
+               }

        }
        }

-    }

 
 

-    while(pUmDevice->tx_pkt == 0){
-       /* Service TX */
-       eth_isr();
-    }
+       while (pUmDevice->tx_pkt == 0) {
+               /* Service TX */
+               eth_isr ();
+       }

 #if ET_DEBUG
 #if ET_DEBUG

-    printf("eth_send: 0x%x, %d bytes\n"
-          "[%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x] ...\n",
-          (int)pPacket, length,
-          ptr[0],ptr[1],ptr[2],ptr[3],ptr[4],ptr[5],
-          ptr[6],ptr[7],ptr[8],ptr[9],ptr[10],ptr[11],ptr[12],
-          ptr[13],ptr[14],ptr[15]);
+       printf ("eth_send: 0x%x, %d bytes\n"
+               "[%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x] ...\n",
+               (int)pPacket, length,
+               ptr[0], ptr[1], ptr[2], ptr[3], ptr[4], ptr[5],
+               ptr[6], ptr[7], ptr[8], ptr[9], ptr[10], ptr[11], ptr[12],
+               ptr[13], ptr[14], ptr[15]);

 #endif
 #endif

-    pUmDevice->tx_pkt = 0;
-    QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket);
+       pUmDevice->tx_pkt = 0;
+       QQ_PushHead (&pDevice->TxPacketFreeQ.Container, pPacket);

 
 

-    /* Done with send */
- out:
-    return status;
+       /* Done with send */
+      out:
+       return status;

 }
 
 }
 

-

 /* Ethernet receive */
 /* Ethernet receive */

-int
-eth_rx(void)
+int eth_rx (void)

 {
 {

-    PLM_PACKET          pPacket = NULL;
-    PUM_PACKET          pUmPacket = NULL;
-    void *skb;
-    int size=0;
+       PLM_PACKET pPacket = NULL;
+       PUM_PACKET pUmPacket = NULL;
+       void *skb;
+       int size = 0;

 
 

-    while(TRUE) {
+       while (TRUE) {

 
 

-    bcm570x_service_isr:
-       /* Pull down packet if it is there */
-       eth_isr();
+             bcm570x_service_isr:
+               /* Pull down packet if it is there */
+               eth_isr ();

 
 

-       /* Indicate RX packets called */
-       if(pUmDevice->rx_pkt){
-           /* printf("eth_rx: got a packet...\n"); */
-           pUmDevice->rx_pkt = 0;
-       } else {
-           /* printf("eth_rx: waiting for packet...\n"); */
-           goto bcm570x_service_isr;
-       }
+               /* Indicate RX packets called */
+               if (pUmDevice->rx_pkt) {
+                       /* printf("eth_rx: got a packet...\n"); */
+                       pUmDevice->rx_pkt = 0;
+               } else {
+                       /* printf("eth_rx: waiting for packet...\n"); */
+                       goto bcm570x_service_isr;
+               }

 
 

-       pPacket = (PLM_PACKET)
-           QQ_PopHead(&pDevice->RxPacketReceivedQ.Container);
+               pPacket = (PLM_PACKET)
+                   QQ_PopHead (&pDevice->RxPacketReceivedQ.Container);

 
 

-       if (pPacket == 0){
-           printf("eth_rx: empty packet!\n");
-           goto bcm570x_service_isr;
-       }
+               if (pPacket == 0) {
+                       printf ("eth_rx: empty packet!\n");
+                       goto bcm570x_service_isr;
+               }

 
 

-       pUmPacket = (PUM_PACKET) pPacket;
+               pUmPacket = (PUM_PACKET) pPacket;

 #if ET_DEBUG
 #if ET_DEBUG

-       printf("eth_rx: packet @0x%x\n",
-              (int)pPacket);
+               printf ("eth_rx: packet @0x%x\n", (int)pPacket);

 #endif
 #endif

-       /* If the packet generated an error, reuse buffer */
-       if ((pPacket->PacketStatus != LM_STATUS_SUCCESS) ||
-           ((size = pPacket->PacketSize) > pDevice->RxMtu)) {
-
-           /* reuse skb */
-           QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
-           printf("eth_rx: error in packet dma!\n");
-           goto bcm570x_service_isr;
-       }
+               /* If the packet generated an error, reuse buffer */
+               if ((pPacket->PacketStatus != LM_STATUS_SUCCESS) ||
+                   ((size = pPacket->PacketSize) > pDevice->RxMtu)) {
+
+                       /* reuse skb */
+                       QQ_PushTail (&pDevice->RxPacketFreeQ.Container,
+                                    pPacket);
+                       printf ("eth_rx: error in packet dma!\n");
+                       goto bcm570x_service_isr;
+               }

 
 

-       /* Set size and address */
-       skb = pUmPacket->skbuff;
-       size = pPacket->PacketSize;
+               /* Set size and address */
+               skb = pUmPacket->skbuff;
+               size = pPacket->PacketSize;

 
 

-       /* Pass the packet up to the protocol
-        * layers.
-        */
-       NetReceive(skb, size);
+               /* Pass the packet up to the protocol
+                * layers.
+                */
+               NetReceive (skb, size);

 
 

-       /* Free packet buffer */
-       bcm570xPktFree (pUmDevice->index, skb);
-       pUmPacket->skbuff = NULL;
+               /* Free packet buffer */
+               bcm570xPktFree (pUmDevice->index, skb);
+               pUmPacket->skbuff = NULL;

 
 

-       /* Reuse SKB */
-       QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
+               /* Reuse SKB */
+               QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);

 
 

-       return 0; /* Got a packet, bail ... */
-    }
-    return size;
+               return 0;       /* Got a packet, bail ... */
+       }
+       return size;

 }
 
 }
 

-

 /* Shut down device */
 /* Shut down device */

-void
-eth_halt(void)
+void eth_halt (void)

 {
 {

-    int i;
-    if ( initialized)
-    if (pDevice && pUmDevice && pUmDevice->opened){
-       printf("\neth%d:%s,", pUmDevice->index, pUmDevice->name);
-       printf("HALT,");
-       /* stop device */
-       LM_Halt(pDevice);
-       printf("POWER DOWN,");
-       LM_SetPowerState(pDevice, LM_POWER_STATE_D3);
-
-       /* Free the memory allocated by the device in tigon3 */
-       for (i = 0; i < pUmDevice->mem_list_num; i++)  {
-           if (pUmDevice->mem_list[i])  {
-               /* sanity check */
-               if (pUmDevice->dma_list[i]) {  /* cache-safe memory */
-                   free(pUmDevice->mem_list[i]);
-               } else {
-                   free(pUmDevice->mem_list[i]);  /* normal memory   */
+       int i;
+       if (initialized)
+               if (pDevice && pUmDevice && pUmDevice->opened) {
+                       printf ("\neth%d:%s,", pUmDevice->index,
+                               pUmDevice->name);
+                       printf ("HALT,");
+                       /* stop device */
+                       LM_Halt (pDevice);
+                       printf ("POWER DOWN,");
+                       LM_SetPowerState (pDevice, LM_POWER_STATE_D3);
+
+                       /* Free the memory allocated by the device in tigon3 */
+                       for (i = 0; i < pUmDevice->mem_list_num; i++) {
+                               if (pUmDevice->mem_list[i]) {
+                                       /* sanity check */
+                                       if (pUmDevice->dma_list[i]) {   /* cache-safe memory */
+                                               free (pUmDevice->mem_list[i]);
+                                       } else {
+                                               free (pUmDevice->mem_list[i]);  /* normal memory   */
+                                       }
+                               }
+                       }
+                       pUmDevice->opened = 0;
+                       free (pDevice);
+                       pDevice = NULL;
+                       pUmDevice = NULL;
+                       initialized = 0;
+                       printf ("done - offline.\n");

                }
                }

-           }
-       }
-       pUmDevice->opened = 0;
-       free(pDevice);
-       pDevice = NULL;
-       pUmDevice = NULL;
-       initialized = 0;
-       printf("done - offline.\n");
-    }

 }
 
 }
 

-

 /*
  *
  * Middle Module: Interface between the HW driver (tigon3 modules) and
 /*
  *
  * Middle Module: Interface between the HW driver (tigon3 modules) and


@@ -843,409 +834,380 @@ eth_halt(void)
  */
 
 /* Middle module dependency - size of a packet descriptor */
  */
 
 /* Middle module dependency - size of a packet descriptor */

-int MM_Packet_Desc_Size = sizeof(UM_PACKET);
-
+int MM_Packet_Desc_Size = sizeof (UM_PACKET);

 
 LM_STATUS
 
 LM_STATUS

-MM_ReadConfig32(PLM_DEVICE_BLOCK pDevice,
-               LM_UINT32 Offset,
-               LM_UINT32 *pValue32)
+MM_ReadConfig32 (PLM_DEVICE_BLOCK pDevice,
+                LM_UINT32 Offset, LM_UINT32 * pValue32)

 {
 {

-    UM_DEVICE_BLOCK *pUmDevice;
-    pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
-    pci_read_config_dword(pUmDevice->pdev,
-                         Offset, (u32 *) pValue32);
-    return LM_STATUS_SUCCESS;
+       UM_DEVICE_BLOCK *pUmDevice;
+       pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
+       pci_read_config_dword (pUmDevice->pdev, Offset, (u32 *) pValue32);
+       return LM_STATUS_SUCCESS;

 }
 
 }
 

-

 LM_STATUS
 LM_STATUS

-MM_WriteConfig32(PLM_DEVICE_BLOCK pDevice,
-                LM_UINT32 Offset,
-                LM_UINT32 Value32)
+MM_WriteConfig32 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT32 Value32)

 {
 {

-    UM_DEVICE_BLOCK *pUmDevice;
-    pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
-    pci_write_config_dword(pUmDevice->pdev,
-                          Offset, Value32);
-    return LM_STATUS_SUCCESS;
+       UM_DEVICE_BLOCK *pUmDevice;
+       pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
+       pci_write_config_dword (pUmDevice->pdev, Offset, Value32);
+       return LM_STATUS_SUCCESS;

 }
 
 }
 

-

 LM_STATUS
 LM_STATUS

-MM_ReadConfig16(PLM_DEVICE_BLOCK pDevice,
-               LM_UINT32 Offset,
-               LM_UINT16 *pValue16)
+MM_ReadConfig16 (PLM_DEVICE_BLOCK pDevice,
+                LM_UINT32 Offset, LM_UINT16 * pValue16)

 {
 {

-    UM_DEVICE_BLOCK *pUmDevice;
-    pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
-    pci_read_config_word(pUmDevice->pdev,
-                        Offset, (u16*) pValue16);
-    return LM_STATUS_SUCCESS;
+       UM_DEVICE_BLOCK *pUmDevice;
+       pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
+       pci_read_config_word (pUmDevice->pdev, Offset, (u16 *) pValue16);
+       return LM_STATUS_SUCCESS;

 }
 
 LM_STATUS
 }
 
 LM_STATUS

-MM_WriteConfig16(PLM_DEVICE_BLOCK pDevice,
-                LM_UINT32 Offset,
-                LM_UINT16 Value16)
+MM_WriteConfig16 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT16 Value16)

 {
 {

-    UM_DEVICE_BLOCK *pUmDevice;
-    pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
-    pci_write_config_word(pUmDevice->pdev,
-                         Offset, Value16);
-    return LM_STATUS_SUCCESS;
+       UM_DEVICE_BLOCK *pUmDevice;
+       pUmDevice = (UM_DEVICE_BLOCK *) pDevice;
+       pci_write_config_word (pUmDevice->pdev, Offset, Value16);
+       return LM_STATUS_SUCCESS;

 }
 
 }
 

-

 LM_STATUS
 LM_STATUS

-MM_AllocateSharedMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
-                       PLM_VOID *pMemoryBlockVirt,
-                       PLM_PHYSICAL_ADDRESS pMemoryBlockPhy,
-                       LM_BOOL Cached)
+MM_AllocateSharedMemory (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
+                        PLM_VOID * pMemoryBlockVirt,
+                        PLM_PHYSICAL_ADDRESS pMemoryBlockPhy, LM_BOOL Cached)

 {
 {

-    PLM_VOID pvirt;
-    PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
-    dma_addr_t mapping;
+       PLM_VOID pvirt;
+       PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+       dma_addr_t mapping;

 
 

-    pvirt = malloc(BlockSize);
-    mapping = (dma_addr_t)(pvirt);
-    if (!pvirt)
-       return LM_STATUS_FAILURE;
+       pvirt = malloc (BlockSize);
+       mapping = (dma_addr_t) (pvirt);
+       if (!pvirt)
+               return LM_STATUS_FAILURE;

 
 

-    pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt;
-    pUmDevice->dma_list[pUmDevice->mem_list_num] = mapping;
-    pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize;
-    memset(pvirt, 0, BlockSize);
+       pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt;
+       pUmDevice->dma_list[pUmDevice->mem_list_num] = mapping;
+       pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize;
+       memset (pvirt, 0, BlockSize);

 
 

-    *pMemoryBlockVirt = (PLM_VOID) pvirt;
-    MM_SetAddr (pMemoryBlockPhy, (dma_addr_t) mapping);
+       *pMemoryBlockVirt = (PLM_VOID) pvirt;
+       MM_SetAddr (pMemoryBlockPhy, (dma_addr_t) mapping);

 
 

-    return LM_STATUS_SUCCESS;
+       return LM_STATUS_SUCCESS;

 }
 
 }
 

-

 LM_STATUS
 LM_STATUS

-MM_AllocateMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
-       PLM_VOID *pMemoryBlockVirt)
+MM_AllocateMemory (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
+                  PLM_VOID * pMemoryBlockVirt)

 {
 {

-    PLM_VOID pvirt;
-    PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+       PLM_VOID pvirt;
+       PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;

 
 

-    pvirt = malloc(BlockSize);
+       pvirt = malloc (BlockSize);

 
 

-    if (!pvirt)
-       return LM_STATUS_FAILURE;
+       if (!pvirt)
+               return LM_STATUS_FAILURE;

 
 

-    pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt;
-    pUmDevice->dma_list[pUmDevice->mem_list_num] = 0;
-    pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize;
-    memset(pvirt, 0, BlockSize);
-    *pMemoryBlockVirt = pvirt;
+       pUmDevice->mem_list[pUmDevice->mem_list_num] = pvirt;
+       pUmDevice->dma_list[pUmDevice->mem_list_num] = 0;
+       pUmDevice->mem_size_list[pUmDevice->mem_list_num++] = BlockSize;
+       memset (pvirt, 0, BlockSize);
+       *pMemoryBlockVirt = pvirt;

 
 

-    return LM_STATUS_SUCCESS;
+       return LM_STATUS_SUCCESS;

 }
 
 }
 

-LM_STATUS
-MM_MapMemBase(PLM_DEVICE_BLOCK pDevice)
+LM_STATUS MM_MapMemBase (PLM_DEVICE_BLOCK pDevice)

 {
 {

-    printf("BCM570x PCI Memory base address @0x%x\n",
-          (unsigned int)pDevice->pMappedMemBase);
-    return LM_STATUS_SUCCESS;
+       printf ("BCM570x PCI Memory base address @0x%x\n",
+               (unsigned int)pDevice->pMappedMemBase);
+       return LM_STATUS_SUCCESS;

 }
 
 }
 

-LM_STATUS
-MM_InitializeUmPackets(PLM_DEVICE_BLOCK pDevice)
+LM_STATUS MM_InitializeUmPackets (PLM_DEVICE_BLOCK pDevice)

 {
 {

-    int i;
-    void* skb;
-    PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
-    PUM_PACKET pUmPacket = NULL;
-    PLM_PACKET pPacket = NULL;
-
-    for (i = 0; i < pDevice->RxPacketDescCnt; i++) {
-       pPacket = QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
-       pUmPacket = (PUM_PACKET) pPacket;
+       int i;
+       void *skb;
+       PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+       PUM_PACKET pUmPacket = NULL;
+       PLM_PACKET pPacket = NULL;
+
+       for (i = 0; i < pDevice->RxPacketDescCnt; i++) {
+               pPacket = QQ_PopHead (&pDevice->RxPacketFreeQ.Container);
+               pUmPacket = (PUM_PACKET) pPacket;
+
+               if (pPacket == 0) {
+                       printf ("MM_InitializeUmPackets: Bad RxPacketFreeQ\n");
+               }

 
 

-       if (pPacket == 0) {
-           printf("MM_InitializeUmPackets: Bad RxPacketFreeQ\n");
-       }
+               skb = bcm570xPktAlloc (pUmDevice->index,
+                                      pPacket->u.Rx.RxBufferSize + 2);

 
 

-       skb = bcm570xPktAlloc(pUmDevice->index,
-                             pPacket->u.Rx.RxBufferSize + 2);
+               if (skb == 0) {
+                       pUmPacket->skbuff = 0;
+                       QQ_PushTail (&pUmDevice->rx_out_of_buf_q.Container,
+                                    pPacket);
+                       printf ("MM_InitializeUmPackets: out of buffer.\n");
+                       continue;
+               }

 
 

-       if (skb == 0) {
-           pUmPacket->skbuff = 0;
-           QQ_PushTail(&pUmDevice->rx_out_of_buf_q.Container, pPacket);
-           printf("MM_InitializeUmPackets: out of buffer.\n");
-           continue;
+               pUmPacket->skbuff = skb;
+               QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);

        }
 
        }
 

-       pUmPacket->skbuff = skb;
-       QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
-    }
-
-    pUmDevice->rx_low_buf_thresh = pDevice->RxPacketDescCnt / 8;
+       pUmDevice->rx_low_buf_thresh = pDevice->RxPacketDescCnt / 8;

 
 

-    return LM_STATUS_SUCCESS;
+       return LM_STATUS_SUCCESS;

 }
 
 }
 

-LM_STATUS
-MM_GetConfig(PLM_DEVICE_BLOCK pDevice)
+LM_STATUS MM_GetConfig (PLM_DEVICE_BLOCK pDevice)

 {
 {

-    PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
-    int index = pDevice->index;
-
-    if (auto_speed[index] == 0)
-       pDevice->DisableAutoNeg = TRUE;
-    else
-       pDevice->DisableAutoNeg = FALSE;
-
-    if (line_speed[index] == 0) {
-       pDevice->RequestedMediaType =
-           LM_REQUESTED_MEDIA_TYPE_AUTO;
-       pDevice->DisableAutoNeg = FALSE;
-    }
-    else {
-       if (line_speed[index] == 1000) {
-           if (pDevice->EnableTbi) {
-               pDevice->RequestedMediaType =
-                   LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX;
-           }
-           else if (full_duplex[index]) {
-               pDevice->RequestedMediaType =
-                   LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX;
-           }
-           else {
-               pDevice->RequestedMediaType =
-                   LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS;
-           }
-           if (!pDevice->EnableTbi)
+       PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+       int index = pDevice->index;
+
+       if (auto_speed[index] == 0)
+               pDevice->DisableAutoNeg = TRUE;
+       else

                pDevice->DisableAutoNeg = FALSE;
                pDevice->DisableAutoNeg = FALSE;

+
+       if (line_speed[index] == 0) {
+               pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_AUTO;
+               pDevice->DisableAutoNeg = FALSE;
+       } else {
+               if (line_speed[index] == 1000) {
+                       if (pDevice->EnableTbi) {
+                               pDevice->RequestedMediaType =
+                                   LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX;
+                       } else if (full_duplex[index]) {
+                               pDevice->RequestedMediaType =
+                                   LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX;
+                       } else {
+                               pDevice->RequestedMediaType =
+                                   LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS;
+                       }
+                       if (!pDevice->EnableTbi)
+                               pDevice->DisableAutoNeg = FALSE;
+               } else if (line_speed[index] == 100) {
+                       if (full_duplex[index]) {
+                               pDevice->RequestedMediaType =
+                                   LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX;
+                       } else {
+                               pDevice->RequestedMediaType =
+                                   LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS;
+                       }
+               } else if (line_speed[index] == 10) {
+                       if (full_duplex[index]) {
+                               pDevice->RequestedMediaType =
+                                   LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX;
+                       } else {
+                               pDevice->RequestedMediaType =
+                                   LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS;
+                       }
+               } else {
+                       pDevice->RequestedMediaType =
+                           LM_REQUESTED_MEDIA_TYPE_AUTO;
+                       pDevice->DisableAutoNeg = FALSE;
+               }
+

        }
        }

-       else if (line_speed[index] == 100) {
-           if (full_duplex[index]) {
-               pDevice->RequestedMediaType =
-                   LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX;
-           }
-           else {
-               pDevice->RequestedMediaType =
-                   LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS;
-           }
-       }
-       else if (line_speed[index] == 10) {
-           if (full_duplex[index]) {
-               pDevice->RequestedMediaType =
-                   LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX;
-           }
-           else {
-               pDevice->RequestedMediaType =
-                   LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS;
-           }
+       pDevice->FlowControlCap = 0;
+       if (rx_flow_control[index] != 0) {
+               pDevice->FlowControlCap |= LM_FLOW_CONTROL_RECEIVE_PAUSE;

        }
        }

-       else {
-           pDevice->RequestedMediaType =
-               LM_REQUESTED_MEDIA_TYPE_AUTO;
-           pDevice->DisableAutoNeg = FALSE;
+       if (tx_flow_control[index] != 0) {
+               pDevice->FlowControlCap |= LM_FLOW_CONTROL_TRANSMIT_PAUSE;

        }
        }

-
-    }
-    pDevice->FlowControlCap = 0;
-    if (rx_flow_control[index] != 0) {
-       pDevice->FlowControlCap |= LM_FLOW_CONTROL_RECEIVE_PAUSE;
-    }
-    if (tx_flow_control[index] != 0) {
-       pDevice->FlowControlCap |= LM_FLOW_CONTROL_TRANSMIT_PAUSE;
-    }
-    if ((auto_flow_control[index] != 0) &&
-       (pDevice->DisableAutoNeg == FALSE)) {
-
-       pDevice->FlowControlCap |= LM_FLOW_CONTROL_AUTO_PAUSE;
-       if ((tx_flow_control[index] == 0) &&
-           (rx_flow_control[index] == 0)) {
-           pDevice->FlowControlCap |=
-               LM_FLOW_CONTROL_TRANSMIT_PAUSE |
-               LM_FLOW_CONTROL_RECEIVE_PAUSE;
+       if ((auto_flow_control[index] != 0) &&
+           (pDevice->DisableAutoNeg == FALSE)) {
+
+               pDevice->FlowControlCap |= LM_FLOW_CONTROL_AUTO_PAUSE;
+               if ((tx_flow_control[index] == 0) &&
+                   (rx_flow_control[index] == 0)) {
+                       pDevice->FlowControlCap |=
+                           LM_FLOW_CONTROL_TRANSMIT_PAUSE |
+                           LM_FLOW_CONTROL_RECEIVE_PAUSE;
+               }

        }
        }

-    }

 
 

-    /* Default MTU for now */
-    pUmDevice->mtu = 1500;
+       /* Default MTU for now */
+       pUmDevice->mtu = 1500;

 
 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
 
 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT

-    if (pUmDevice->mtu > 1500) {
-       pDevice->RxMtu = pUmDevice->mtu;
-       pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT;
-    }
-    else {
-       pDevice->RxJumboDescCnt = 0;
-    }
-    pDevice->RxJumboDescCnt = rx_jumbo_desc_cnt[index];
+       if (pUmDevice->mtu > 1500) {
+               pDevice->RxMtu = pUmDevice->mtu;
+               pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT;
+       } else {
+               pDevice->RxJumboDescCnt = 0;
+       }
+       pDevice->RxJumboDescCnt = rx_jumbo_desc_cnt[index];

 #else
 #else

-    pDevice->RxMtu = pUmDevice->mtu;
+       pDevice->RxMtu = pUmDevice->mtu;

 #endif
 
 #endif
 

-    if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701) {
-       pDevice->UseTaggedStatus = TRUE;
-       pUmDevice->timer_interval = CFG_HZ;
-    }
-    else {
-       pUmDevice->timer_interval = CFG_HZ/50;
-    }
-
-    pDevice->TxPacketDescCnt = tx_pkt_desc_cnt[index];
-    pDevice->RxStdDescCnt = rx_std_desc_cnt[index];
-    /* Note:  adaptive coalescence really isn't adaptive in this driver */
-    pUmDevice->rx_adaptive_coalesce = rx_adaptive_coalesce[index];
-    if (!pUmDevice->rx_adaptive_coalesce) {
-       pDevice->RxCoalescingTicks = rx_coalesce_ticks[index];
-       if (pDevice->RxCoalescingTicks > MAX_RX_COALESCING_TICKS)
-           pDevice->RxCoalescingTicks = MAX_RX_COALESCING_TICKS;
-       pUmDevice->rx_curr_coalesce_ticks =pDevice->RxCoalescingTicks;
-
-       pDevice->RxMaxCoalescedFrames = rx_max_coalesce_frames[index];
-       if (pDevice->RxMaxCoalescedFrames>MAX_RX_MAX_COALESCED_FRAMES)
-           pDevice->RxMaxCoalescedFrames =
-                               MAX_RX_MAX_COALESCED_FRAMES;
-       pUmDevice->rx_curr_coalesce_frames =
-           pDevice->RxMaxCoalescedFrames;
-       pDevice->StatsCoalescingTicks = stats_coalesce_ticks[index];
-       if (pDevice->StatsCoalescingTicks>MAX_STATS_COALESCING_TICKS)
-           pDevice->StatsCoalescingTicks=
-               MAX_STATS_COALESCING_TICKS;
-       }
-       else {
-           pUmDevice->rx_curr_coalesce_frames =
-               DEFAULT_RX_MAX_COALESCED_FRAMES;
-           pUmDevice->rx_curr_coalesce_ticks =
-               DEFAULT_RX_COALESCING_TICKS;
+       if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+               pDevice->UseTaggedStatus = TRUE;
+               pUmDevice->timer_interval = CFG_HZ;
+       } else {
+               pUmDevice->timer_interval = CFG_HZ / 50;

        }
        }

-    pDevice->TxCoalescingTicks = tx_coalesce_ticks[index];
-    if (pDevice->TxCoalescingTicks > MAX_TX_COALESCING_TICKS)
-       pDevice->TxCoalescingTicks = MAX_TX_COALESCING_TICKS;
-    pDevice->TxMaxCoalescedFrames = tx_max_coalesce_frames[index];
-    if (pDevice->TxMaxCoalescedFrames > MAX_TX_MAX_COALESCED_FRAMES)
-       pDevice->TxMaxCoalescedFrames = MAX_TX_MAX_COALESCED_FRAMES;

 
 

-    if (enable_wol[index]) {
-       pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_MAGIC_PACKET;
-       pDevice->WakeUpMode = LM_WAKE_UP_MODE_MAGIC_PACKET;
-    }
-    pDevice->NicSendBd = TRUE;
+       pDevice->TxPacketDescCnt = tx_pkt_desc_cnt[index];
+       pDevice->RxStdDescCnt = rx_std_desc_cnt[index];
+       /* Note:  adaptive coalescence really isn't adaptive in this driver */
+       pUmDevice->rx_adaptive_coalesce = rx_adaptive_coalesce[index];
+       if (!pUmDevice->rx_adaptive_coalesce) {
+               pDevice->RxCoalescingTicks = rx_coalesce_ticks[index];
+               if (pDevice->RxCoalescingTicks > MAX_RX_COALESCING_TICKS)
+                       pDevice->RxCoalescingTicks = MAX_RX_COALESCING_TICKS;
+               pUmDevice->rx_curr_coalesce_ticks = pDevice->RxCoalescingTicks;
+
+               pDevice->RxMaxCoalescedFrames = rx_max_coalesce_frames[index];
+               if (pDevice->RxMaxCoalescedFrames > MAX_RX_MAX_COALESCED_FRAMES)
+                       pDevice->RxMaxCoalescedFrames =
+                           MAX_RX_MAX_COALESCED_FRAMES;
+               pUmDevice->rx_curr_coalesce_frames =
+                   pDevice->RxMaxCoalescedFrames;
+               pDevice->StatsCoalescingTicks = stats_coalesce_ticks[index];
+               if (pDevice->StatsCoalescingTicks > MAX_STATS_COALESCING_TICKS)
+                       pDevice->StatsCoalescingTicks =
+                           MAX_STATS_COALESCING_TICKS;
+       } else {
+               pUmDevice->rx_curr_coalesce_frames =
+                   DEFAULT_RX_MAX_COALESCED_FRAMES;
+               pUmDevice->rx_curr_coalesce_ticks = DEFAULT_RX_COALESCING_TICKS;
+       }
+       pDevice->TxCoalescingTicks = tx_coalesce_ticks[index];
+       if (pDevice->TxCoalescingTicks > MAX_TX_COALESCING_TICKS)
+               pDevice->TxCoalescingTicks = MAX_TX_COALESCING_TICKS;
+       pDevice->TxMaxCoalescedFrames = tx_max_coalesce_frames[index];
+       if (pDevice->TxMaxCoalescedFrames > MAX_TX_MAX_COALESCED_FRAMES)
+               pDevice->TxMaxCoalescedFrames = MAX_TX_MAX_COALESCED_FRAMES;
+
+       if (enable_wol[index]) {
+               pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_MAGIC_PACKET;
+               pDevice->WakeUpMode = LM_WAKE_UP_MODE_MAGIC_PACKET;
+       }
+       pDevice->NicSendBd = TRUE;

 
 

-    /* Don't update status blocks during interrupt */
-    pDevice->RxCoalescingTicksDuringInt = 0;
-    pDevice->TxCoalescingTicksDuringInt = 0;
+       /* Don't update status blocks during interrupt */
+       pDevice->RxCoalescingTicksDuringInt = 0;
+       pDevice->TxCoalescingTicksDuringInt = 0;

 
 

-    return LM_STATUS_SUCCESS;
+       return LM_STATUS_SUCCESS;

 
 }
 
 
 }
 

-
-LM_STATUS
-MM_StartTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
+LM_STATUS MM_StartTxDma (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)

 {
 {

-    PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
-    printf("Start TX DMA: dev=%d packet @0x%x\n",
-          (int)pUmDevice->index, (unsigned int)pPacket);
+       PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+       printf ("Start TX DMA: dev=%d packet @0x%x\n",
+               (int)pUmDevice->index, (unsigned int)pPacket);

 
 

-    return LM_STATUS_SUCCESS;
+       return LM_STATUS_SUCCESS;

 }
 
 }
 

-LM_STATUS
-MM_CompleteTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
+LM_STATUS MM_CompleteTxDma (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)

 {
 {

-    PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
-    printf("Complete TX DMA: dev=%d packet @0x%x\n",
-          (int)pUmDevice->index, (unsigned int)pPacket);
-    return LM_STATUS_SUCCESS;
+       PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+       printf ("Complete TX DMA: dev=%d packet @0x%x\n",
+               (int)pUmDevice->index, (unsigned int)pPacket);
+       return LM_STATUS_SUCCESS;

 }
 
 }
 

-
-LM_STATUS
-MM_IndicateStatus(PLM_DEVICE_BLOCK pDevice, LM_STATUS Status)
+LM_STATUS MM_IndicateStatus (PLM_DEVICE_BLOCK pDevice, LM_STATUS Status)

 {
 {

-    char buf[128];
-    char lcd[4];
-    PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
-    LM_FLOW_CONTROL flow_control;
-
-    pUmDevice->delayed_link_ind = 0;
-    memset(lcd, 0x0, 4);
-
-    if (Status == LM_STATUS_LINK_DOWN) {
-       sprintf(buf,"eth%d: %s: NIC Link is down\n",
-               pUmDevice->index,pUmDevice->name);
-       lcd[0] = 'L';lcd[1]='N';lcd[2]='K';lcd[3] = '?';
-    } else if (Status == LM_STATUS_LINK_ACTIVE) {
-       sprintf(buf,"eth%d:%s: ", pUmDevice->index, pUmDevice->name);
-
-       if (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS){
-           strcat(buf,"1000 Mbps ");
-           lcd[0] = '1';lcd[1]='G';lcd[2]='B';
-       } else if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS){
-           strcat(buf,"100 Mbps ");
-           lcd[0] = '1';lcd[1]='0';lcd[2]='0';
-       } else if (pDevice->LineSpeed == LM_LINE_SPEED_10MBPS){
-           strcat(buf,"10 Mbps ");
-           lcd[0] = '1';lcd[1]='0';lcd[2]=' ';
-       }
-       if (pDevice->DuplexMode == LM_DUPLEX_MODE_FULL){
-           strcat(buf, "full duplex");
-           lcd[3] = 'F';
-       } else {
-           strcat(buf, "half duplex");
-           lcd[3] = 'H';
-       }
-       strcat(buf, " link up");
-
-       flow_control = pDevice->FlowControl &
-           (LM_FLOW_CONTROL_RECEIVE_PAUSE |
-            LM_FLOW_CONTROL_TRANSMIT_PAUSE);
-
-       if (flow_control) {
-           if (flow_control & LM_FLOW_CONTROL_RECEIVE_PAUSE) {
-               strcat(buf,", receive ");
-               if (flow_control & LM_FLOW_CONTROL_TRANSMIT_PAUSE)
-                   strcat(buf," & transmit ");
-           }
-           else {
-               strcat(buf,", transmit ");
-           }
-           strcat(buf,"flow control ON");
-       } else {
-           strcat(buf, ", flow control OFF");
+       char buf[128];
+       char lcd[4];
+       PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+       LM_FLOW_CONTROL flow_control;
+
+       pUmDevice->delayed_link_ind = 0;
+       memset (lcd, 0x0, 4);
+
+       if (Status == LM_STATUS_LINK_DOWN) {
+               sprintf (buf, "eth%d: %s: NIC Link is down\n",
+                        pUmDevice->index, pUmDevice->name);
+               lcd[0] = 'L';
+               lcd[1] = 'N';
+               lcd[2] = 'K';
+               lcd[3] = '?';
+       } else if (Status == LM_STATUS_LINK_ACTIVE) {
+               sprintf (buf, "eth%d:%s: ", pUmDevice->index, pUmDevice->name);
+
+               if (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) {
+                       strcat (buf, "1000 Mbps ");
+                       lcd[0] = '1';
+                       lcd[1] = 'G';
+                       lcd[2] = 'B';
+               } else if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS) {
+                       strcat (buf, "100 Mbps ");
+                       lcd[0] = '1';
+                       lcd[1] = '0';
+                       lcd[2] = '0';
+               } else if (pDevice->LineSpeed == LM_LINE_SPEED_10MBPS) {
+                       strcat (buf, "10 Mbps ");
+                       lcd[0] = '1';
+                       lcd[1] = '0';
+                       lcd[2] = ' ';
+               }
+               if (pDevice->DuplexMode == LM_DUPLEX_MODE_FULL) {
+                       strcat (buf, "full duplex");
+                       lcd[3] = 'F';
+               } else {
+                       strcat (buf, "half duplex");
+                       lcd[3] = 'H';
+               }
+               strcat (buf, " link up");
+
+               flow_control = pDevice->FlowControl &
+                   (LM_FLOW_CONTROL_RECEIVE_PAUSE |
+                    LM_FLOW_CONTROL_TRANSMIT_PAUSE);
+
+               if (flow_control) {
+                       if (flow_control & LM_FLOW_CONTROL_RECEIVE_PAUSE) {
+                               strcat (buf, ", receive ");
+                               if (flow_control &
+                                   LM_FLOW_CONTROL_TRANSMIT_PAUSE)
+                                       strcat (buf, " & transmit ");
+                       } else {
+                               strcat (buf, ", transmit ");
+                       }
+                       strcat (buf, "flow control ON");
+               } else {
+                       strcat (buf, ", flow control OFF");
+               }
+               strcat (buf, "\n");
+               printf ("%s", buf);

        }
        }

-       strcat(buf,"\n");
-       printf("%s",buf);
-    }

 #if 0
 #if 0

-    sysLedDsply(lcd[0],lcd[1],lcd[2],lcd[3]);
+       sysLedDsply (lcd[0], lcd[1], lcd[2], lcd[3]);

 #endif
 #endif

-    return LM_STATUS_SUCCESS;
+       return LM_STATUS_SUCCESS;

 }
 
 }
 

-LM_STATUS
-MM_FreeRxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
+LM_STATUS MM_FreeRxBuffer (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)

 {
 
 {
 

-    PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
-    PUM_PACKET pUmPacket;
-    void *skb;
+       PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+       PUM_PACKET pUmPacket;
+       void *skb;

 
 

-    pUmPacket = (PUM_PACKET) pPacket;
+       pUmPacket = (PUM_PACKET) pPacket;

 
 

-    if ((skb = pUmPacket->skbuff))
-       bcm570xPktFree(pUmDevice->index, skb);
+       if ((skb = pUmPacket->skbuff))
+               bcm570xPktFree (pUmDevice->index, skb);

 
 

-    pUmPacket->skbuff = 0;
+       pUmPacket->skbuff = 0;

 
 

-    return LM_STATUS_SUCCESS;
+       return LM_STATUS_SUCCESS;

 }
 
 }
 

-unsigned long
-MM_AnGetCurrentTime_us(PAN_STATE_INFO pAnInfo)
+unsigned long MM_AnGetCurrentTime_us (PAN_STATE_INFO pAnInfo)

 {
 {

-    return get_timer(0);
+       return get_timer (0);

 }
 
 /*
 }
 
 /*


@@ -1258,86 +1220,82 @@ MM_AnGetCurrentTime_us(PAN_STATE_INFO pAnInfo)
  *   non-fatal.  The incoming cluster chain is not freed, giving
  *   the caller the choice of whether to try a retransmit later.
  */
  *   non-fatal.  The incoming cluster chain is not freed, giving
  *   the caller the choice of whether to try a retransmit later.
  */

-LM_STATUS
-MM_CoalesceTxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
+LM_STATUS MM_CoalesceTxBuffer (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)

 {
 {

-    PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
-    PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
-    void *skbnew;
-    int len = 0;
-
-    if (len == 0)
-       return (LM_STATUS_SUCCESS);
-
-    if (len > MAX_PACKET_SIZE){
-       printf ("eth%d: xmit frame discarded, too big!, size = %d\n",
-               pUmDevice->index, len);
-       return (LM_STATUS_FAILURE);
-    }
+       PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
+       PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+       void *skbnew;
+       int len = 0;
+
+       if (len == 0)
+               return (LM_STATUS_SUCCESS);
+
+       if (len > MAX_PACKET_SIZE) {
+               printf ("eth%d: xmit frame discarded, too big!, size = %d\n",
+                       pUmDevice->index, len);
+               return (LM_STATUS_FAILURE);
+       }

 
 

-    skbnew = bcm570xPktAlloc(pUmDevice->index, MAX_PACKET_SIZE);
+       skbnew = bcm570xPktAlloc (pUmDevice->index, MAX_PACKET_SIZE);

 
 

-    if (skbnew == NULL) {
-       pUmDevice->tx_full = 1;
-       printf ("eth%d: out of transmit buffers", pUmDevice->index);
-       return (LM_STATUS_FAILURE);
-    }
+       if (skbnew == NULL) {
+               pUmDevice->tx_full = 1;
+               printf ("eth%d: out of transmit buffers", pUmDevice->index);
+               return (LM_STATUS_FAILURE);
+       }

 
 

-    /* New packet values */
-    pUmPacket->skbuff = skbnew;
-    pUmPacket->lm_packet.u.Tx.FragCount = 1;
+       /* New packet values */
+       pUmPacket->skbuff = skbnew;
+       pUmPacket->lm_packet.u.Tx.FragCount = 1;

 
 

-    return (LM_STATUS_SUCCESS);
+       return (LM_STATUS_SUCCESS);

 }
 
 }
 

-
-LM_STATUS
-MM_IndicateRxPackets(PLM_DEVICE_BLOCK pDevice)
+LM_STATUS MM_IndicateRxPackets (PLM_DEVICE_BLOCK pDevice)

 {
 {

-    PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
-    pUmDevice->rx_pkt = 1;
-    return LM_STATUS_SUCCESS;
+       PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+       pUmDevice->rx_pkt = 1;
+       return LM_STATUS_SUCCESS;

 }
 
 }
 

-LM_STATUS
-MM_IndicateTxPackets(PLM_DEVICE_BLOCK pDevice)
+LM_STATUS MM_IndicateTxPackets (PLM_DEVICE_BLOCK pDevice)

 {
 {

-    PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
-    PLM_PACKET pPacket;
-    PUM_PACKET pUmPacket;
-    void *skb;
-    while ( TRUE ) {
-
-       pPacket = (PLM_PACKET)
-           QQ_PopHead(&pDevice->TxPacketXmittedQ.Container);
-
-       if (pPacket == 0)
-           break;
-
-       pUmPacket = (PUM_PACKET) pPacket;
-       skb = (void*)pUmPacket->skbuff;
-
-       /*
-       * Free MBLK if we transmitted a fragmented packet or a
-       * non-fragmented packet straight from the VxWorks
-       * buffer pool. If packet was copied to a local transmit
-       * buffer, then there's no MBUF to free, just free
-       * the transmit buffer back to the cluster pool.
-       */
-
-       if (skb)
-           bcm570xPktFree (pUmDevice->index, skb);
-
-       pUmPacket->skbuff = 0;
-       QQ_PushTail(&pDevice->TxPacketFreeQ.Container, pPacket);
-       pUmDevice->tx_pkt = 1;
-    }
-    if (pUmDevice->tx_full) {
-       if (QQ_GetEntryCnt(&pDevice->TxPacketFreeQ.Container) >=
-           (QQ_GetSize(&pDevice->TxPacketFreeQ.Container) >> 1))
-           pUmDevice->tx_full = 0;
-    }
-    return LM_STATUS_SUCCESS;
+       PUM_DEVICE_BLOCK pUmDevice = (PUM_DEVICE_BLOCK) pDevice;
+       PLM_PACKET pPacket;
+       PUM_PACKET pUmPacket;
+       void *skb;
+       while (TRUE) {
+
+               pPacket = (PLM_PACKET)
+                   QQ_PopHead (&pDevice->TxPacketXmittedQ.Container);
+
+               if (pPacket == 0)
+                       break;
+
+               pUmPacket = (PUM_PACKET) pPacket;
+               skb = (void *)pUmPacket->skbuff;
+
+               /*
+                * Free MBLK if we transmitted a fragmented packet or a
+                * non-fragmented packet straight from the VxWorks
+                * buffer pool. If packet was copied to a local transmit
+                * buffer, then there's no MBUF to free, just free
+                * the transmit buffer back to the cluster pool.
+                */
+
+               if (skb)
+                       bcm570xPktFree (pUmDevice->index, skb);
+
+               pUmPacket->skbuff = 0;
+               QQ_PushTail (&pDevice->TxPacketFreeQ.Container, pPacket);
+               pUmDevice->tx_pkt = 1;
+       }
+       if (pUmDevice->tx_full) {
+               if (QQ_GetEntryCnt (&pDevice->TxPacketFreeQ.Container) >=
+                   (QQ_GetSize (&pDevice->TxPacketFreeQ.Container) >> 1))
+                       pUmDevice->tx_full = 0;
+       }
+       return LM_STATUS_SUCCESS;

 }
 
 /*
 }
 
 /*


@@ -1345,16 +1303,12 @@ MM_IndicateTxPackets(PLM_DEVICE_BLOCK pDevice)
  *  Return its length and physical address.
  */
 void MM_MapTxDma
  *  Return its length and physical address.
  */
 void MM_MapTxDma

-    (
-    PLM_DEVICE_BLOCK pDevice,
-    struct _LM_PACKET *pPacket,
-    T3_64BIT_HOST_ADDR *paddr,
-    LM_UINT32 *len,
-    int frag)
-{
-    PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
-    *len = pPacket->PacketSize;
-    MM_SetT3Addr(paddr, (dma_addr_t) pUmPacket->skbuff);
+    (PLM_DEVICE_BLOCK pDevice,
+     struct _LM_PACKET *pPacket,
+     T3_64BIT_HOST_ADDR * paddr, LM_UINT32 * len, int frag) {
+       PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
+       *len = pPacket->PacketSize;
+       MM_SetT3Addr (paddr, (dma_addr_t) pUmPacket->skbuff);

 }
 
 /*
 }
 
 /*


@@ -1362,35 +1316,31 @@ void MM_MapTxDma
  *  to a physical address as seen from a PCI device.  Store the
  *  result at paddr.
  */
  *  to a physical address as seen from a PCI device.  Store the
  *  result at paddr.
  */

-void MM_MapRxDma(
-                PLM_DEVICE_BLOCK pDevice,
-                struct _LM_PACKET *pPacket,
-                T3_64BIT_HOST_ADDR *paddr)
+void MM_MapRxDma (PLM_DEVICE_BLOCK pDevice,
+                 struct _LM_PACKET *pPacket, T3_64BIT_HOST_ADDR * paddr)

 {
 {

-    PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
-    MM_SetT3Addr(paddr, (dma_addr_t) pUmPacket->skbuff);
+       PUM_PACKET pUmPacket = (PUM_PACKET) pPacket;
+       MM_SetT3Addr (paddr, (dma_addr_t) pUmPacket->skbuff);

 }
 
 }
 

-void
-MM_SetAddr (LM_PHYSICAL_ADDRESS *paddr, dma_addr_t addr)
+void MM_SetAddr (LM_PHYSICAL_ADDRESS * paddr, dma_addr_t addr)

 {
 #if (BITS_PER_LONG == 64)
 {
 #if (BITS_PER_LONG == 64)

-       paddr->High = ((unsigned long) addr) >> 32;
-       paddr->Low = ((unsigned long) addr) & 0xffffffff;
+       paddr->High = ((unsigned long)addr) >> 32;
+       paddr->Low = ((unsigned long)addr) & 0xffffffff;

 #else
        paddr->High = 0;
 #else
        paddr->High = 0;

-       paddr->Low = (unsigned long) addr;
+       paddr->Low = (unsigned long)addr;

 #endif
 }
 
 #endif
 }
 

-void
-MM_SetT3Addr(T3_64BIT_HOST_ADDR *paddr, dma_addr_t addr)
+void MM_SetT3Addr (T3_64BIT_HOST_ADDR * paddr, dma_addr_t addr)

 {
 {

-       unsigned long baddr = (unsigned long) addr;
+       unsigned long baddr = (unsigned long)addr;

 #if (BITS_PER_LONG == 64)
 #if (BITS_PER_LONG == 64)

-       set_64bit_addr(paddr, baddr & 0xffffffff, baddr >> 32);
+       set_64bit_addr (paddr, baddr & 0xffffffff, baddr >> 32);

 #else
 #else

-       set_64bit_addr(paddr, baddr, 0);
+       set_64bit_addr (paddr, baddr, 0);

 #endif
 }
 
 #endif
 }
 


@@ -1403,42 +1353,38 @@ MM_SetT3Addr(T3_64BIT_HOST_ADDR *paddr, dma_addr_t addr)
  * If any uses of the function remain, they will refer to the single copy
  * in the library.
  */
  * If any uses of the function remain, they will refer to the single copy
  * in the library.
  */

-void
-atomic_set(atomic_t* entry, int val)
+void atomic_set (atomic_t * entry, int val)

 {
 {

-    entry->counter = val;
+       entry->counter = val;

 }
 }

-int
-atomic_read(atomic_t* entry)
+
+int atomic_read (atomic_t * entry)

 {
 {

-    return entry->counter;
+       return entry->counter;

 }
 }

-void
-atomic_inc(atomic_t* entry)
+
+void atomic_inc (atomic_t * entry)

 {
 {

-    if(entry)
-       entry->counter++;
+       if (entry)
+               entry->counter++;

 }
 
 }
 

-void
-atomic_dec(atomic_t* entry)
+void atomic_dec (atomic_t * entry)

 {
 {

-    if(entry)
-       entry->counter--;
+       if (entry)
+               entry->counter--;

 }
 
 }
 

-void
-atomic_sub(int a, atomic_t* entry)
+void atomic_sub (int a, atomic_t * entry)

 {
 {

-    if(entry)
-       entry->counter -= a;
+       if (entry)
+               entry->counter -= a;

 }
 
 }
 

-void
-atomic_add(int a, atomic_t* entry)
+void atomic_add (int a, atomic_t * entry)

 {
 {

-    if(entry)
-       entry->counter += a;
+       if (entry)
+               entry->counter += a;

 }
 
 /******************************************************************************/
 }
 
 /******************************************************************************/


@@ -1446,68 +1392,57 @@ atomic_add(int a, atomic_t* entry)
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-void
-QQ_InitQueue(
-PQQ_CONTAINER pQueue,
-unsigned int QueueSize) {
-    pQueue->Head = 0;
-    pQueue->Tail = 0;
-    pQueue->Size = QueueSize+1;
-    atomic_set(&pQueue->EntryCnt, 0);
-} /* QQ_InitQueue */
-
+void QQ_InitQueue (PQQ_CONTAINER pQueue, unsigned int QueueSize)
+{
+       pQueue->Head = 0;
+       pQueue->Tail = 0;
+       pQueue->Size = QueueSize + 1;
+       atomic_set (&pQueue->EntryCnt, 0);
+}                              /* QQ_InitQueue */

 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-char
-QQ_Full(
-PQQ_CONTAINER pQueue) {
-    unsigned int NewHead;
-
-    NewHead = (pQueue->Head + 1) % pQueue->Size;
+char QQ_Full (PQQ_CONTAINER pQueue)
+{
+       unsigned int NewHead;

 
 

-    return(NewHead == pQueue->Tail);
-} /* QQ_Full */
+       NewHead = (pQueue->Head + 1) % pQueue->Size;

 
 

+       return (NewHead == pQueue->Tail);
+}                              /* QQ_Full */

 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-char
-QQ_Empty(
-PQQ_CONTAINER pQueue) {
-    return(pQueue->Head == pQueue->Tail);
-} /* QQ_Empty */
-
+char QQ_Empty (PQQ_CONTAINER pQueue)
+{
+       return (pQueue->Head == pQueue->Tail);
+}                              /* QQ_Empty */

 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-unsigned int
-QQ_GetSize(
-PQQ_CONTAINER pQueue) {
-    return pQueue->Size;
-} /* QQ_GetSize */
-
+unsigned int QQ_GetSize (PQQ_CONTAINER pQueue)
+{
+       return pQueue->Size;
+}                              /* QQ_GetSize */

 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-unsigned int
-QQ_GetEntryCnt(
-PQQ_CONTAINER pQueue) {
-    return atomic_read(&pQueue->EntryCnt);
-} /* QQ_GetEntryCnt */
-
+unsigned int QQ_GetEntryCnt (PQQ_CONTAINER pQueue)
+{
+       return atomic_read (&pQueue->EntryCnt);
+}                              /* QQ_GetEntryCnt */

 
 /******************************************************************************/
 /* Description:                                                               */
 
 /******************************************************************************/
 /* Description:                                                               */


@@ -1516,28 +1451,25 @@ PQQ_CONTAINER pQueue) {
 /*    TRUE entry was added successfully.                                      */
 /*    FALSE queue is full.                                                    */
 /******************************************************************************/
 /*    TRUE entry was added successfully.                                      */
 /*    FALSE queue is full.                                                    */
 /******************************************************************************/

-char
-QQ_PushHead(
-PQQ_CONTAINER pQueue,
-PQQ_ENTRY pEntry) {
-    unsigned int Head;
+char QQ_PushHead (PQQ_CONTAINER pQueue, PQQ_ENTRY pEntry)
+{
+       unsigned int Head;

 
 

-    Head = (pQueue->Head + 1) % pQueue->Size;
+       Head = (pQueue->Head + 1) % pQueue->Size;

 
 #if !defined(QQ_NO_OVERFLOW_CHECK)
 
 #if !defined(QQ_NO_OVERFLOW_CHECK)

-    if(Head == pQueue->Tail) {
-       return 0;
-    } /* if */
-#endif /* QQ_NO_OVERFLOW_CHECK */
+       if (Head == pQueue->Tail) {
+               return 0;
+       }                       /* if */
+#endif                         /* QQ_NO_OVERFLOW_CHECK */

 
 

-    pQueue->Array[pQueue->Head] = pEntry;
-    wmb();
-    pQueue->Head = Head;
-    atomic_inc(&pQueue->EntryCnt);
-
-    return -1;
-} /* QQ_PushHead */
+       pQueue->Array[pQueue->Head] = pEntry;
+       wmb ();
+       pQueue->Head = Head;
+       atomic_inc (&pQueue->EntryCnt);

 
 

+       return -1;
+}                              /* QQ_PushHead */

 
 /******************************************************************************/
 /* Description:                                                               */
 
 /******************************************************************************/
 /* Description:                                                               */


@@ -1546,146 +1478,126 @@ PQQ_ENTRY pEntry) {
 /*    TRUE entry was added successfully.                                      */
 /*    FALSE queue is full.                                                    */
 /******************************************************************************/
 /*    TRUE entry was added successfully.                                      */
 /*    FALSE queue is full.                                                    */
 /******************************************************************************/

-char
-QQ_PushTail(
-PQQ_CONTAINER pQueue,
-PQQ_ENTRY pEntry) {
-    unsigned int Tail;
-
-    Tail = pQueue->Tail;
-    if(Tail == 0) {
-       Tail = pQueue->Size;
-    } /* if */
-    Tail--;
+char QQ_PushTail (PQQ_CONTAINER pQueue, PQQ_ENTRY pEntry)
+{
+       unsigned int Tail;

 
 

-#if !defined(QQ_NO_OVERFLOW_CHECK)
-    if(Tail == pQueue->Head) {
-       return 0;
-    } /* if */
-#endif /* QQ_NO_OVERFLOW_CHECK */
+       Tail = pQueue->Tail;
+       if (Tail == 0) {
+               Tail = pQueue->Size;
+       }                       /* if */
+       Tail--;

 
 

-    pQueue->Array[Tail] = pEntry;
-    wmb();
-    pQueue->Tail = Tail;
-    atomic_inc(&pQueue->EntryCnt);
+#if !defined(QQ_NO_OVERFLOW_CHECK)
+       if (Tail == pQueue->Head) {
+               return 0;
+       }                       /* if */
+#endif                         /* QQ_NO_OVERFLOW_CHECK */

 
 

-    return -1;
-} /* QQ_PushTail */
+       pQueue->Array[Tail] = pEntry;
+       wmb ();
+       pQueue->Tail = Tail;
+       atomic_inc (&pQueue->EntryCnt);

 
 

+       return -1;
+}                              /* QQ_PushTail */

 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-PQQ_ENTRY
-QQ_PopHead(
-PQQ_CONTAINER pQueue) {
-    unsigned int Head;
-    PQQ_ENTRY Entry;
+PQQ_ENTRY QQ_PopHead (PQQ_CONTAINER pQueue)
+{
+       unsigned int Head;
+       PQQ_ENTRY Entry;

 
 

-    Head = pQueue->Head;
+       Head = pQueue->Head;

 
 #if !defined(QQ_NO_UNDERFLOW_CHECK)
 
 #if !defined(QQ_NO_UNDERFLOW_CHECK)

-    if(Head == pQueue->Tail) {
-       return (PQQ_ENTRY) 0;
-    } /* if */
-#endif /* QQ_NO_UNDERFLOW_CHECK */
-
-    if(Head == 0) {
-       Head = pQueue->Size;
-    } /* if */
-    Head--;
+       if (Head == pQueue->Tail) {
+               return (PQQ_ENTRY) 0;
+       }                       /* if */
+#endif                         /* QQ_NO_UNDERFLOW_CHECK */

 
 

-    Entry = pQueue->Array[Head];
-    membar();
+       if (Head == 0) {
+               Head = pQueue->Size;
+       }                       /* if */
+       Head--;

 
 

-    pQueue->Head = Head;
-    atomic_dec(&pQueue->EntryCnt);
+       Entry = pQueue->Array[Head];
+       membar ();

 
 

-    return Entry;
-} /* QQ_PopHead */
+       pQueue->Head = Head;
+       atomic_dec (&pQueue->EntryCnt);

 
 

+       return Entry;
+}                              /* QQ_PopHead */

 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-PQQ_ENTRY
-QQ_PopTail(
-PQQ_CONTAINER pQueue) {
-    unsigned int Tail;
-    PQQ_ENTRY Entry;
+PQQ_ENTRY QQ_PopTail (PQQ_CONTAINER pQueue)
+{
+       unsigned int Tail;
+       PQQ_ENTRY Entry;

 
 

-    Tail = pQueue->Tail;
+       Tail = pQueue->Tail;

 
 #if !defined(QQ_NO_UNDERFLOW_CHECK)
 
 #if !defined(QQ_NO_UNDERFLOW_CHECK)

-    if(Tail == pQueue->Head) {
-       return (PQQ_ENTRY) 0;
-    } /* if */
-#endif /* QQ_NO_UNDERFLOW_CHECK */
-
-    Entry = pQueue->Array[Tail];
-    membar();
-    pQueue->Tail = (Tail + 1) % pQueue->Size;
-    atomic_dec(&pQueue->EntryCnt);
+       if (Tail == pQueue->Head) {
+               return (PQQ_ENTRY) 0;
+       }                       /* if */
+#endif                         /* QQ_NO_UNDERFLOW_CHECK */

 
 

-    return Entry;
-} /* QQ_PopTail */
+       Entry = pQueue->Array[Tail];
+       membar ();
+       pQueue->Tail = (Tail + 1) % pQueue->Size;
+       atomic_dec (&pQueue->EntryCnt);

 
 

+       return Entry;
+}                              /* QQ_PopTail */

 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-PQQ_ENTRY
-QQ_GetHead(
-    PQQ_CONTAINER pQueue,
-    unsigned int Idx)
+PQQ_ENTRY QQ_GetHead (PQQ_CONTAINER pQueue, unsigned int Idx)

 {
 {

-    if(Idx >= atomic_read(&pQueue->EntryCnt))
-    {
-       return (PQQ_ENTRY) 0;
-    }
-
-    if(pQueue->Head > Idx)
-    {
-       Idx = pQueue->Head - Idx;
-    }
-    else
-    {
-       Idx = pQueue->Size - (Idx - pQueue->Head);
-    }
-    Idx--;
-
-    return pQueue->Array[Idx];
-}
+       if (Idx >= atomic_read (&pQueue->EntryCnt)) {
+               return (PQQ_ENTRY) 0;
+       }
+
+       if (pQueue->Head > Idx) {
+               Idx = pQueue->Head - Idx;
+       } else {
+               Idx = pQueue->Size - (Idx - pQueue->Head);
+       }
+       Idx--;

 
 

+       return pQueue->Array[Idx];
+}

 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-PQQ_ENTRY
-QQ_GetTail(
-    PQQ_CONTAINER pQueue,
-    unsigned int Idx)
+PQQ_ENTRY QQ_GetTail (PQQ_CONTAINER pQueue, unsigned int Idx)

 {
 {

-    if(Idx >= atomic_read(&pQueue->EntryCnt))
-    {
-       return (PQQ_ENTRY) 0;
-    }
-
-    Idx += pQueue->Tail;
-    if(Idx >= pQueue->Size)
-    {
-       Idx = Idx - pQueue->Size;
-    }
-
-    return pQueue->Array[Idx];
+       if (Idx >= atomic_read (&pQueue->EntryCnt)) {
+               return (PQQ_ENTRY) 0;
+       }
+
+       Idx += pQueue->Tail;
+       if (Idx >= pQueue->Size) {
+               Idx = Idx - pQueue->Size;
+       }
+
+       return pQueue->Array[Idx];

 }
 
 }
 

-#endif /* CFG_CMD_NET, !CONFIG_NET_MULTI, CONFIG_BCM570x */
+#endif                         /* CFG_CMD_NET, !CONFIG_NET_MULTI, CONFIG_BCM570x */

diff --git a/drivers/bcm570x_lm.h b/drivers/bcm570x_lm.h
index 607f3fd067caa1775a16ad87673f379b2bc5ebac..2ea6ca8fa9c5a116f9930ac2762a262d410e124e 100644 (file)
--- a/drivers/bcm570x_lm.h
+++ b/drivers/bcm570x_lm.h
@@ -19,29 +19,28 @@
 #include "bcm570x_queue.h"
 #include "bcm570x_bits.h"
 
 #include "bcm570x_queue.h"
 #include "bcm570x_bits.h"
 

-

 /******************************************************************************/
 /* Basic types. */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Basic types. */
 /******************************************************************************/
 

-typedef char           LM_CHAR,    *PLM_CHAR;
-typedef unsigned int   LM_UINT,    *PLM_UINT;
-typedef unsigned char  LM_UINT8,   *PLM_UINT8;
-typedef unsigned short LM_UINT16,  *PLM_UINT16;
-typedef unsigned int   LM_UINT32,  *PLM_UINT32;
-typedef unsigned int   LM_COUNTER, *PLM_COUNTER;
-typedef void           LM_VOID,    *PLM_VOID;
-typedef char           LM_BOOL,    *PLM_BOOL;
+typedef char LM_CHAR, *PLM_CHAR;
+typedef unsigned int LM_UINT, *PLM_UINT;
+typedef unsigned char LM_UINT8, *PLM_UINT8;
+typedef unsigned short LM_UINT16, *PLM_UINT16;
+typedef unsigned int LM_UINT32, *PLM_UINT32;
+typedef unsigned int LM_COUNTER, *PLM_COUNTER;
+typedef void LM_VOID, *PLM_VOID;
+typedef char LM_BOOL, *PLM_BOOL;

 
 /* 64bit value. */
 typedef struct {
 #ifdef BIG_ENDIAN_HOST
 
 /* 64bit value. */
 typedef struct {
 #ifdef BIG_ENDIAN_HOST

-    LM_UINT32 High;
-    LM_UINT32 Low;
-#else /* BIG_ENDIAN_HOST */
-    LM_UINT32 Low;
-    LM_UINT32 High;
-#endif /* !BIG_ENDIAN_HOST */
+       LM_UINT32 High;
+       LM_UINT32 Low;
+#else                          /* BIG_ENDIAN_HOST */
+       LM_UINT32 Low;
+       LM_UINT32 High;
+#endif                         /* !BIG_ENDIAN_HOST */

 } LM_UINT64, *PLM_UINT64;
 
 typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS;
 } LM_UINT64, *PLM_UINT64;
 
 typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS;


@@ -58,15 +57,13 @@ typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS;
        }                                                   \
     }
 
        }                                                   \
     }
 

-

 #ifndef NULL
 #define NULL                ((void *) 0)
 #ifndef NULL
 #define NULL                ((void *) 0)

-#endif /* NULL */
+#endif                         /* NULL */

 
 #ifndef OFFSETOF
 #define OFFSETOF(_s, _m)    (MM_UINT_PTR(&(((_s *) 0)->_m)))
 
 #ifndef OFFSETOF
 #define OFFSETOF(_s, _m)    (MM_UINT_PTR(&(((_s *) 0)->_m)))

-#endif /* OFFSETOF */
-
+#endif                         /* OFFSETOF */

 
 /******************************************************************************/
 /* Simple macros. */
 
 /******************************************************************************/
 /* Simple macros. */


@@ -100,26 +97,24 @@ typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS;
     ((unsigned char *) (_Dst))[4] = ((unsigned char *) (_Src))[4];          \
     ((unsigned char *) (_Dst))[5] = ((unsigned char *) (_Src))[5];
 
     ((unsigned char *) (_Dst))[4] = ((unsigned char *) (_Src))[4];          \
     ((unsigned char *) (_Dst))[5] = ((unsigned char *) (_Src))[5];
 

-

 /******************************************************************************/
 /* Constants. */
 /******************************************************************************/
 
 #define ETHERNET_ADDRESS_SIZE           6
 #define ETHERNET_PACKET_HEADER_SIZE     14
 /******************************************************************************/
 /* Constants. */
 /******************************************************************************/
 
 #define ETHERNET_ADDRESS_SIZE           6
 #define ETHERNET_PACKET_HEADER_SIZE     14

-#define MIN_ETHERNET_PACKET_SIZE        64      /* with 4 byte crc. */
-#define MAX_ETHERNET_PACKET_SIZE        1518    /* with 4 byte crc. */
+#define MIN_ETHERNET_PACKET_SIZE        64     /* with 4 byte crc. */
+#define MAX_ETHERNET_PACKET_SIZE        1518   /* with 4 byte crc. */

 #define MIN_ETHERNET_PACKET_SIZE_NO_CRC 60
 #define MAX_ETHERNET_PACKET_SIZE_NO_CRC 1514
 #define MIN_ETHERNET_PACKET_SIZE_NO_CRC 60
 #define MAX_ETHERNET_PACKET_SIZE_NO_CRC 1514

-#define MAX_ETHERNET_PACKET_BUFFER_SIZE 1536    /* A nice even number. */
+#define MAX_ETHERNET_PACKET_BUFFER_SIZE 1536   /* A nice even number. */

 
 #ifndef LM_MAX_MC_TABLE_SIZE
 #define LM_MAX_MC_TABLE_SIZE            32
 
 #ifndef LM_MAX_MC_TABLE_SIZE
 #define LM_MAX_MC_TABLE_SIZE            32

-#endif /* LM_MAX_MC_TABLE_SIZE */
+#endif                         /* LM_MAX_MC_TABLE_SIZE */

 #define LM_MC_ENTRY_SIZE                (ETHERNET_ADDRESS_SIZE+1)
 #define LM_MC_INSTANCE_COUNT_INDEX      (LM_MC_ENTRY_SIZE-1)
 
 #define LM_MC_ENTRY_SIZE                (ETHERNET_ADDRESS_SIZE+1)
 #define LM_MC_INSTANCE_COUNT_INDEX      (LM_MC_ENTRY_SIZE-1)
 

-

 /* Receive filter masks. */
 #define LM_ACCEPT_UNICAST               0x0001
 #define LM_ACCEPT_MULTICAST             0x0002
 /* Receive filter masks. */
 #define LM_ACCEPT_UNICAST               0x0001
 #define LM_ACCEPT_MULTICAST             0x0002


@@ -129,7 +124,6 @@ typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS;
 
 #define LM_PROMISCUOUS_MODE             0x10000
 
 
 #define LM_PROMISCUOUS_MODE             0x10000
 

-

 /******************************************************************************/
 /* PCI registers. */
 /******************************************************************************/
 /******************************************************************************/
 /* PCI registers. */
 /******************************************************************************/


@@ -169,20 +163,20 @@ typedef LM_UINT64 LM_PHYSICAL_ADDRESS, *PLM_PHYSICAL_ADDRESS;
 /******************************************************************************/
 
 typedef struct {
 /******************************************************************************/
 
 typedef struct {

-    LM_UINT32 FragSize;
-    LM_PHYSICAL_ADDRESS FragBuf;
+       LM_UINT32 FragSize;
+       LM_PHYSICAL_ADDRESS FragBuf;

 } LM_FRAG, *PLM_FRAG;
 
 typedef struct {
 } LM_FRAG, *PLM_FRAG;
 
 typedef struct {

-    /* FragCount is initialized for the caller to the maximum array size, on */
-    /* return FragCount is the number of the actual fragments in the array. */
-    LM_UINT32 FragCount;
+       /* FragCount is initialized for the caller to the maximum array size, on */
+       /* return FragCount is the number of the actual fragments in the array. */
+       LM_UINT32 FragCount;

 
 

-    /* Total buffer size. */
-    LM_UINT32 TotalSize;
+       /* Total buffer size. */
+       LM_UINT32 TotalSize;

 
 

-    /* Fragment array buffer. */
-    LM_FRAG Fragments[1];
+       /* Fragment array buffer. */
+       LM_FRAG Fragments[1];

 } LM_FRAG_LIST, *PLM_FRAG_LIST;
 
 #define DECLARE_FRAG_LIST_BUFFER_TYPE(_FRAG_LIST_TYPE_NAME, _MAX_FRAG_COUNT) \
 } LM_FRAG_LIST, *PLM_FRAG_LIST;
 
 #define DECLARE_FRAG_LIST_BUFFER_TYPE(_FRAG_LIST_TYPE_NAME, _MAX_FRAG_COUNT) \


@@ -191,7 +185,6 @@ typedef struct {
        LM_FRAG FragListBuffer[_MAX_FRAG_COUNT-1];                           \
     } _FRAG_LIST_TYPE_NAME, *P##_FRAG_LIST_TYPE_NAME
 
        LM_FRAG FragListBuffer[_MAX_FRAG_COUNT-1];                           \
     } _FRAG_LIST_TYPE_NAME, *P##_FRAG_LIST_TYPE_NAME
 

-

 /******************************************************************************/
 /* Status codes. */
 /******************************************************************************/
 /******************************************************************************/
 /* Status codes. */
 /******************************************************************************/


@@ -217,7 +210,6 @@ typedef struct {
 
 typedef LM_UINT LM_STATUS, *PLM_STATUS;
 
 
 typedef LM_UINT LM_STATUS, *PLM_STATUS;
 

-

 /******************************************************************************/
 /* Requested media type. */
 /******************************************************************************/
 /******************************************************************************/
 /* Requested media type. */
 /******************************************************************************/


@@ -240,7 +232,6 @@ typedef LM_UINT LM_STATUS, *PLM_STATUS;
 
 typedef LM_UINT32 LM_REQUESTED_MEDIA_TYPE, *PLM_REQUESTED_MEDIA_TYPE;
 
 
 typedef LM_UINT32 LM_REQUESTED_MEDIA_TYPE, *PLM_REQUESTED_MEDIA_TYPE;
 

-

 /******************************************************************************/
 /* Media type. */
 /******************************************************************************/
 /******************************************************************************/
 /* Media type. */
 /******************************************************************************/


@@ -254,7 +245,6 @@ typedef LM_UINT32 LM_REQUESTED_MEDIA_TYPE, *PLM_REQUESTED_MEDIA_TYPE;
 
 typedef LM_UINT32 LM_MEDIA_TYPE, *PLM_MEDIA_TYPE;
 
 
 typedef LM_UINT32 LM_MEDIA_TYPE, *PLM_MEDIA_TYPE;
 

-

 /******************************************************************************/
 /* Line speed. */
 /******************************************************************************/
 /******************************************************************************/
 /* Line speed. */
 /******************************************************************************/


@@ -266,7 +256,6 @@ typedef LM_UINT32 LM_MEDIA_TYPE, *PLM_MEDIA_TYPE;
 
 typedef LM_UINT32 LM_LINE_SPEED, *PLM_LINE_SPEED;
 
 
 typedef LM_UINT32 LM_LINE_SPEED, *PLM_LINE_SPEED;
 

-

 /******************************************************************************/
 /* Duplex mode. */
 /******************************************************************************/
 /******************************************************************************/
 /* Duplex mode. */
 /******************************************************************************/


@@ -277,7 +266,6 @@ typedef LM_UINT32 LM_LINE_SPEED, *PLM_LINE_SPEED;
 
 typedef LM_UINT32 LM_DUPLEX_MODE, *PLM_DUPLEX_MODE;
 
 
 typedef LM_UINT32 LM_DUPLEX_MODE, *PLM_DUPLEX_MODE;
 

-

 /******************************************************************************/
 /* Power state. */
 /******************************************************************************/
 /******************************************************************************/
 /* Power state. */
 /******************************************************************************/


@@ -289,7 +277,6 @@ typedef LM_UINT32 LM_DUPLEX_MODE, *PLM_DUPLEX_MODE;
 
 typedef LM_UINT32 LM_POWER_STATE, *PLM_POWER_STATE;
 
 
 typedef LM_UINT32 LM_POWER_STATE, *PLM_POWER_STATE;
 

-

 /******************************************************************************/
 /* Task offloading. */
 /******************************************************************************/
 /******************************************************************************/
 /* Task offloading. */
 /******************************************************************************/


@@ -305,7 +292,6 @@ typedef LM_UINT32 LM_POWER_STATE, *PLM_POWER_STATE;
 
 typedef LM_UINT32 LM_TASK_OFFLOAD, *PLM_TASK_OFFLOAD;
 
 
 typedef LM_UINT32 LM_TASK_OFFLOAD, *PLM_TASK_OFFLOAD;
 

-

 /******************************************************************************/
 /* Flow control. */
 /******************************************************************************/
 /******************************************************************************/
 /* Flow control. */
 /******************************************************************************/


@@ -324,7 +310,6 @@ typedef LM_UINT32 LM_TASK_OFFLOAD, *PLM_TASK_OFFLOAD;
 
 typedef LM_UINT32 LM_FLOW_CONTROL, *PLM_FLOW_CONTROL;
 
 
 typedef LM_UINT32 LM_FLOW_CONTROL, *PLM_FLOW_CONTROL;
 

-

 /******************************************************************************/
 /* Wake up mode. */
 /******************************************************************************/
 /******************************************************************************/
 /* Wake up mode. */
 /******************************************************************************/


@@ -336,7 +321,6 @@ typedef LM_UINT32 LM_FLOW_CONTROL, *PLM_FLOW_CONTROL;
 
 typedef LM_UINT32 LM_WAKE_UP_MODE, *PLM_WAKE_UP_MODE;
 
 
 typedef LM_UINT32 LM_WAKE_UP_MODE, *PLM_WAKE_UP_MODE;
 

-

 /******************************************************************************/
 /* Counters. */
 /******************************************************************************/
 /******************************************************************************/
 /* Counters. */
 /******************************************************************************/


@@ -362,7 +346,6 @@ typedef LM_UINT32 LM_WAKE_UP_MODE, *PLM_WAKE_UP_MODE;
 
 typedef LM_UINT32 LM_COUNTER_TYPE, *PLM_COUNTER_TYPE;
 
 
 typedef LM_UINT32 LM_COUNTER_TYPE, *PLM_COUNTER_TYPE;
 

-

 /******************************************************************************/
 /* Forward definition. */
 /******************************************************************************/
 /******************************************************************************/
 /* Forward definition. */
 /******************************************************************************/


@@ -370,82 +353,82 @@ typedef LM_UINT32 LM_COUNTER_TYPE, *PLM_COUNTER_TYPE;
 typedef struct _LM_DEVICE_BLOCK *PLM_DEVICE_BLOCK;
 typedef struct _LM_PACKET *PLM_PACKET;
 
 typedef struct _LM_DEVICE_BLOCK *PLM_DEVICE_BLOCK;
 typedef struct _LM_PACKET *PLM_PACKET;
 

-

 /******************************************************************************/
 /* Function prototypes. */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Function prototypes. */
 /******************************************************************************/
 

-LM_STATUS LM_GetAdapterInfo(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_InitializeAdapter(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_ResetAdapter(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_DisableInterrupt(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_EnableInterrupt(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
-LM_STATUS LM_ServiceInterrupts(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_QueueRxPackets(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_SetReceiveMask(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask);
-LM_STATUS LM_Halt(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_Abort(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_MulticastAdd(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress);
-LM_STATUS LM_MulticastDel(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress);
-LM_STATUS LM_MulticastClear(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_SetMacAddress(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMacAddress);
-LM_STATUS LM_LoopbackAddress(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pAddress);
-
-LM_UINT32 LM_GetCrcCounter(PLM_DEVICE_BLOCK pDevice);
-
-LM_WAKE_UP_MODE LM_PMCapabilities(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_NwufAdd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize,
-    LM_UINT8 *pByteMask, LM_UINT8 *pPattern);
-LM_STATUS LM_NwufRemove(PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize,
-    LM_UINT8 *pByteMask, LM_UINT8 *pPattern);
-LM_STATUS LM_SetPowerState(PLM_DEVICE_BLOCK pDevice, LM_POWER_STATE PowerLevel);
-
-LM_VOID LM_ReadPhy(PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg,
-    PLM_UINT32 pData32);
-LM_VOID LM_WritePhy(PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg,
-    LM_UINT32 Data32);
-
-LM_STATUS LM_ControlLoopBack(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Control);
-LM_STATUS LM_SetupPhy(PLM_DEVICE_BLOCK pDevice);
-int LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDuration);
-
+LM_STATUS LM_GetAdapterInfo (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_InitializeAdapter (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_ResetAdapter (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_DisableInterrupt (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_EnableInterrupt (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_SendPacket (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
+LM_STATUS LM_ServiceInterrupts (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_QueueRxPackets (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_SetReceiveMask (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask);
+LM_STATUS LM_Halt (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_Abort (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_MulticastAdd (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress);
+LM_STATUS LM_MulticastDel (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress);
+LM_STATUS LM_MulticastClear (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_SetMacAddress (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMacAddress);
+LM_STATUS LM_LoopbackAddress (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pAddress);
+
+LM_UINT32 LM_GetCrcCounter (PLM_DEVICE_BLOCK pDevice);
+
+LM_WAKE_UP_MODE LM_PMCapabilities (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_NwufAdd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize,
+                     LM_UINT8 * pByteMask, LM_UINT8 * pPattern);
+LM_STATUS LM_NwufRemove (PLM_DEVICE_BLOCK pDevice, LM_UINT32 ByteMaskSize,
+                        LM_UINT8 * pByteMask, LM_UINT8 * pPattern);
+LM_STATUS LM_SetPowerState (PLM_DEVICE_BLOCK pDevice,
+                           LM_POWER_STATE PowerLevel);
+
+LM_VOID LM_ReadPhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg,
+                   PLM_UINT32 pData32);
+LM_VOID LM_WritePhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg,
+                    LM_UINT32 Data32);
+
+LM_STATUS LM_ControlLoopBack (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Control);
+LM_STATUS LM_SetupPhy (PLM_DEVICE_BLOCK pDevice);
+int LM_BlinkLED (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDuration);

 
 /******************************************************************************/
 /* These are the OS specific functions called by LMAC. */
 /******************************************************************************/
 
 
 /******************************************************************************/
 /* These are the OS specific functions called by LMAC. */
 /******************************************************************************/
 

-LM_STATUS MM_ReadConfig16(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
-    LM_UINT16 *pValue16);
-LM_STATUS MM_WriteConfig16(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
-    LM_UINT16 Value16);
-LM_STATUS MM_ReadConfig32(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
-    LM_UINT32 *pValue32);
-LM_STATUS MM_WriteConfig32(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
-    LM_UINT32 Value32);
-LM_STATUS MM_MapMemBase(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS MM_MapIoBase(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS MM_IndicateRxPackets(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS MM_IndicateTxPackets(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS MM_StartTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
-LM_STATUS MM_CompleteTxDma(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
-LM_STATUS MM_AllocateMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
-    PLM_VOID *pMemoryBlockVirt);
-LM_STATUS MM_AllocateSharedMemory(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
-    PLM_VOID *pMemoryBlockVirt, PLM_PHYSICAL_ADDRESS pMemoryBlockPhy,
-    LM_BOOL Cached);
-LM_STATUS MM_GetConfig(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS MM_IndicateStatus(PLM_DEVICE_BLOCK pDevice, LM_STATUS Status);
-LM_STATUS MM_InitializeUmPackets(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS MM_FreeRxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
-LM_STATUS MM_CoalesceTxBuffer(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
-LM_STATUS LM_MbufWorkAround(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_SetLinkSpeed(PLM_DEVICE_BLOCK pDevice,
-                         LM_REQUESTED_MEDIA_TYPE RequestedMediaType);
+LM_STATUS MM_ReadConfig16 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
+                          LM_UINT16 * pValue16);
+LM_STATUS MM_WriteConfig16 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
+                           LM_UINT16 Value16);
+LM_STATUS MM_ReadConfig32 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
+                          LM_UINT32 * pValue32);
+LM_STATUS MM_WriteConfig32 (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset,
+                           LM_UINT32 Value32);
+LM_STATUS MM_MapMemBase (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS MM_MapIoBase (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS MM_IndicateRxPackets (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS MM_IndicateTxPackets (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS MM_StartTxDma (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
+LM_STATUS MM_CompleteTxDma (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
+LM_STATUS MM_AllocateMemory (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlockSize,
+                            PLM_VOID * pMemoryBlockVirt);
+LM_STATUS MM_AllocateSharedMemory (PLM_DEVICE_BLOCK pDevice,
+                                  LM_UINT32 BlockSize,
+                                  PLM_VOID * pMemoryBlockVirt,
+                                  PLM_PHYSICAL_ADDRESS pMemoryBlockPhy,
+                                  LM_BOOL Cached);
+LM_STATUS MM_GetConfig (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS MM_IndicateStatus (PLM_DEVICE_BLOCK pDevice, LM_STATUS Status);
+LM_STATUS MM_InitializeUmPackets (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS MM_FreeRxBuffer (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
+LM_STATUS MM_CoalesceTxBuffer (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket);
+LM_STATUS LM_MbufWorkAround (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_SetLinkSpeed (PLM_DEVICE_BLOCK pDevice,
+                          LM_REQUESTED_MEDIA_TYPE RequestedMediaType);

 
 #if INCLUDE_5703_A0_FIX
 
 #if INCLUDE_5703_A0_FIX

-LM_STATUS LM_Load5703DmaWFirmware(PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_Load5703DmaWFirmware (PLM_DEVICE_BLOCK pDevice);

 #endif
 
 #endif
 

-
-#endif /* LM_H */
+#endif                         /* LM_H */

diff --git a/drivers/bcm570x_mm.h b/drivers/bcm570x_mm.h
index b7cbf8abd4ba76e1137382981652c9285b6a4ac9..ff5302f47c80c0bc34ee6b9ddbbdf72550924b9a 100644 (file)
--- a/drivers/bcm570x_mm.h
+++ b/drivers/bcm570x_mm.h
@@ -45,7 +45,7 @@ extern int MM_Packet_Desc_Size;
 
 #define MM_PACKET_DESC_SIZE MM_Packet_Desc_Size
 
 
 #define MM_PACKET_DESC_SIZE MM_Packet_Desc_Size
 

-DECLARE_QUEUE_TYPE(UM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT+1);
+DECLARE_QUEUE_TYPE (UM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT + 1);

 
 #define MAX_MEM 16
 
 
 #define MAX_MEM 16
 


@@ -65,51 +65,50 @@ typedef struct _UM_DEVICE_BLOCK {
        int mtu;
        int index;
        int opened;
        int mtu;
        int index;
        int opened;

-       int delayed_link_ind; /* Delay link status during initial load */
-       int adapter_just_inited; /* the first few seconds after init. */
-       int spurious_int;            /* new -- unsupported */
+       int delayed_link_ind;   /* Delay link status during initial load */
+       int adapter_just_inited;        /* the first few seconds after init. */
+       int spurious_int;       /* new -- unsupported */

        int timer_interval;
        int adaptive_expiry;
        int timer_interval;
        int adaptive_expiry;

-       int crc_counter_expiry;         /* new -- unsupported */
-       int poll_tib_expiry;         /* new -- unsupported */
+       int crc_counter_expiry; /* new -- unsupported */
+       int poll_tib_expiry;    /* new -- unsupported */

        int tx_full;
        int tx_queued;
        int line_speed;         /* in Mbps, 0 if link is down */
        UM_RX_PACKET_Q rx_out_of_buf_q;
        int rx_out_of_buf;
        int tx_full;
        int tx_queued;
        int line_speed;         /* in Mbps, 0 if link is down */
        UM_RX_PACKET_Q rx_out_of_buf_q;
        int rx_out_of_buf;

-       int rx_low_buf_thresh; /* changed to rx_buf_repl_thresh */
+       int rx_low_buf_thresh;  /* changed to rx_buf_repl_thresh */

        int rx_buf_repl_panic_thresh;
        int rx_buf_repl_panic_thresh;

-       int rx_buf_align;            /* new -- unsupported */
+       int rx_buf_align;       /* new -- unsupported */

        int do_global_lock;
        mutex_t global_lock;
        mutex_t undi_lock;
        long undi_flags;
        volatile int interrupt;
        int tasklet_pending;
        int do_global_lock;
        mutex_t global_lock;
        mutex_t undi_lock;
        long undi_flags;
        volatile int interrupt;
        int tasklet_pending;

-       int tasklet_busy;            /* new -- unsupported */
+       int tasklet_busy;       /* new -- unsupported */

        int rx_pkt;
        int tx_pkt;
        int rx_pkt;
        int tx_pkt;

-#ifdef NICE_SUPPORT   /* unsupported, this is a linux ioctl */
-       void (*nice_rx)(void*, void* );
-       void* nice_ctx;
-#endif /* NICE_SUPPORT */
+#ifdef NICE_SUPPORT            /* unsupported, this is a linux ioctl */
+       void (*nice_rx) (void *, void *);
+       void *nice_ctx;
+#endif                         /* NICE_SUPPORT */

        int rx_adaptive_coalesce;
        unsigned int rx_last_cnt;
        unsigned int tx_last_cnt;
        unsigned int rx_curr_coalesce_frames;
        unsigned int rx_curr_coalesce_ticks;
        int rx_adaptive_coalesce;
        unsigned int rx_last_cnt;
        unsigned int tx_last_cnt;
        unsigned int rx_curr_coalesce_frames;
        unsigned int rx_curr_coalesce_ticks;

-       unsigned int tx_curr_coalesce_frames;  /* new -- unsupported */
-#if TIGON3_DEBUG          /* new -- unsupported */
+       unsigned int tx_curr_coalesce_frames;   /* new -- unsupported */
+#if TIGON3_DEBUG               /* new -- unsupported */

        uint tx_zc_count;
        uint tx_chksum_count;
        uint tx_himem_count;
        uint rx_good_chksum_count;
 #endif
        uint tx_zc_count;
        uint tx_chksum_count;
        uint tx_himem_count;
        uint rx_good_chksum_count;
 #endif

-       unsigned int rx_bad_chksum_count;   /* new -- unsupported */
-       unsigned int rx_misc_errors;        /* new -- unsupported */
+       unsigned int rx_bad_chksum_count;       /* new -- unsupported */
+       unsigned int rx_misc_errors;    /* new -- unsupported */

 } UM_DEVICE_BLOCK, *PUM_DEVICE_BLOCK;
 
 } UM_DEVICE_BLOCK, *PUM_DEVICE_BLOCK;
 

-

 /* Physical/PCI DMA address */
 typedef union {
        dma_addr_t dma_map;
 /* Physical/PCI DMA address */
 typedef union {
        dma_addr_t dma_map;


@@ -117,9 +116,9 @@ typedef union {
 
 /* Packet */
 typedef struct
 
 /* Packet */
 typedef struct

-_UM_PACKET {
-    LM_PACKET lm_packet;
-    void* skbuff;      /* Address of packet buffer */
+    _UM_PACKET {
+       LM_PACKET lm_packet;
+       void *skbuff;           /* Address of packet buffer */

 } UM_PACKET, *PUM_PACKET;
 
 #define MM_ACQUIRE_UNDI_LOCK(_pDevice)
 } UM_PACKET, *PUM_PACKET;
 
 #define MM_ACQUIRE_UNDI_LOCK(_pDevice)


@@ -137,15 +136,14 @@ _UM_PACKET {
 
 #define MEM_TO_PCI_PHYS(addr) (addr)
 
 
 #define MEM_TO_PCI_PHYS(addr) (addr)
 

-extern void MM_SetAddr (LM_PHYSICAL_ADDRESS *paddr, dma_addr_t addr);
-extern void MM_SetT3Addr(T3_64BIT_HOST_ADDR *paddr, dma_addr_t addr);
+extern void MM_SetAddr (LM_PHYSICAL_ADDRESS * paddr, dma_addr_t addr);
+extern void MM_SetT3Addr (T3_64BIT_HOST_ADDR * paddr, dma_addr_t addr);

 extern void MM_MapTxDma (PLM_DEVICE_BLOCK pDevice,
 extern void MM_MapTxDma (PLM_DEVICE_BLOCK pDevice,

-                        struct _LM_PACKET *pPacket, T3_64BIT_HOST_ADDR *paddr,
-                        LM_UINT32 *len, int frag);
-extern void MM_MapRxDma ( PLM_DEVICE_BLOCK pDevice,
-                         struct _LM_PACKET *pPacket,
-                         T3_64BIT_HOST_ADDR *paddr);
-
+                        struct _LM_PACKET *pPacket, T3_64BIT_HOST_ADDR * paddr,
+                        LM_UINT32 * len, int frag);
+extern void MM_MapRxDma (PLM_DEVICE_BLOCK pDevice,
+                        struct _LM_PACKET *pPacket,
+                        T3_64BIT_HOST_ADDR * paddr);

 
 /* BSP needs to provide sysUsecDelay and sysSerialPrintString */
 extern void sysSerialPrintString (char *s);
 
 /* BSP needs to provide sysUsecDelay and sysSerialPrintString */
 extern void sysSerialPrintString (char *s);


@@ -157,4 +155,4 @@ extern void sysSerialPrintString (char *s);
 #if 0
 #define cpu_to_le32(val) LONGSWAP(val)
 #endif
 #if 0
 #define cpu_to_le32(val) LONGSWAP(val)
 #endif

-#endif /* MM_H */
+#endif                         /* MM_H */

diff --git a/drivers/tigon3.c b/drivers/tigon3.c
index ec2cd2ac36ff29b7ef3e5ab628a8b28ea8765b86..91e22ebd21c87bac1699a67ed77f9ecaef92f135 100644 (file)
--- a/drivers/tigon3.c
+++ b/drivers/tigon3.c
@@ -26,69 +26,70 @@
 /* Local functions. */
 /******************************************************************************/
 
 /* Local functions. */
 /******************************************************************************/
 

-LM_STATUS LM_Abort(PLM_DEVICE_BLOCK pDevice);
-LM_STATUS LM_QueueRxPackets(PLM_DEVICE_BLOCK pDevice);
-
-static LM_STATUS LM_TranslateRequestedMediaType(
-    LM_REQUESTED_MEDIA_TYPE RequestedMediaType,
-    PLM_MEDIA_TYPE pMediaType, PLM_LINE_SPEED pLineSpeed,
-    PLM_DUPLEX_MODE pDuplexMode);
-
-static LM_STATUS LM_InitBcm540xPhy(PLM_DEVICE_BLOCK pDevice);
-
-__inline static LM_VOID LM_ServiceRxInterrupt(PLM_DEVICE_BLOCK pDevice);
-__inline static LM_VOID LM_ServiceTxInterrupt(PLM_DEVICE_BLOCK pDevice);
-
-static LM_STATUS LM_ForceAutoNegBcm540xPhy(PLM_DEVICE_BLOCK pDevice,
-    LM_REQUESTED_MEDIA_TYPE RequestedMediaType);
-static LM_STATUS LM_ForceAutoNeg(PLM_DEVICE_BLOCK pDevice,
-    LM_REQUESTED_MEDIA_TYPE RequestedMediaType);
-static LM_UINT32 GetPhyAdFlowCntrlSettings(PLM_DEVICE_BLOCK pDevice);
-STATIC LM_STATUS LM_SetFlowControl(PLM_DEVICE_BLOCK pDevice,
-    LM_UINT32 LocalPhyAd, LM_UINT32 RemotePhyAd);
+LM_STATUS LM_Abort (PLM_DEVICE_BLOCK pDevice);
+LM_STATUS LM_QueueRxPackets (PLM_DEVICE_BLOCK pDevice);
+
+static LM_STATUS LM_TranslateRequestedMediaType (LM_REQUESTED_MEDIA_TYPE
+                                                RequestedMediaType,
+                                                PLM_MEDIA_TYPE pMediaType,
+                                                PLM_LINE_SPEED pLineSpeed,
+                                                PLM_DUPLEX_MODE pDuplexMode);
+
+static LM_STATUS LM_InitBcm540xPhy (PLM_DEVICE_BLOCK pDevice);
+
+__inline static LM_VOID LM_ServiceRxInterrupt (PLM_DEVICE_BLOCK pDevice);
+__inline static LM_VOID LM_ServiceTxInterrupt (PLM_DEVICE_BLOCK pDevice);
+
+static LM_STATUS LM_ForceAutoNegBcm540xPhy (PLM_DEVICE_BLOCK pDevice,
+                                           LM_REQUESTED_MEDIA_TYPE
+                                           RequestedMediaType);
+static LM_STATUS LM_ForceAutoNeg (PLM_DEVICE_BLOCK pDevice,
+                                 LM_REQUESTED_MEDIA_TYPE RequestedMediaType);
+static LM_UINT32 GetPhyAdFlowCntrlSettings (PLM_DEVICE_BLOCK pDevice);
+STATIC LM_STATUS LM_SetFlowControl (PLM_DEVICE_BLOCK pDevice,
+                                   LM_UINT32 LocalPhyAd,
+                                   LM_UINT32 RemotePhyAd);

 #if INCLUDE_TBI_SUPPORT
 #if INCLUDE_TBI_SUPPORT

-STATIC LM_STATUS LM_SetupFiberPhy(PLM_DEVICE_BLOCK pDevice);
-STATIC LM_STATUS LM_InitBcm800xPhy(PLM_DEVICE_BLOCK pDevice);
+STATIC LM_STATUS LM_SetupFiberPhy (PLM_DEVICE_BLOCK pDevice);
+STATIC LM_STATUS LM_InitBcm800xPhy (PLM_DEVICE_BLOCK pDevice);

 #endif
 #endif

-STATIC LM_STATUS LM_SetupCopperPhy(PLM_DEVICE_BLOCK pDevice);
-STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid(LM_UINT16 Svid, LM_UINT16 Ssid);
-STATIC LM_STATUS LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
-          LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize);
-STATIC LM_STATUS LM_HaltCpu(PLM_DEVICE_BLOCK pDevice,LM_UINT32 cpu_number);
-STATIC LM_STATUS LM_ResetChip(PLM_DEVICE_BLOCK pDevice);
-STATIC LM_STATUS LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket,
-    PT3_SND_BD pSendBd);
+STATIC LM_STATUS LM_SetupCopperPhy (PLM_DEVICE_BLOCK pDevice);
+STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid (LM_UINT16 Svid,
+                                                LM_UINT16 Ssid);
+STATIC LM_STATUS LM_DmaTest (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
+                            LM_PHYSICAL_ADDRESS BufferPhy,
+                            LM_UINT32 BufferSize);
+STATIC LM_STATUS LM_HaltCpu (PLM_DEVICE_BLOCK pDevice, LM_UINT32 cpu_number);
+STATIC LM_STATUS LM_ResetChip (PLM_DEVICE_BLOCK pDevice);
+STATIC LM_STATUS LM_Test4GBoundary (PLM_DEVICE_BLOCK pDevice,
+                                   PLM_PACKET pPacket, PT3_SND_BD pSendBd);

 
 /******************************************************************************/
 /* External functions. */
 /******************************************************************************/
 
 
 /******************************************************************************/
 /* External functions. */
 /******************************************************************************/
 

-LM_STATUS LM_LoadRlsFirmware(PLM_DEVICE_BLOCK pDevice);
-
+LM_STATUS LM_LoadRlsFirmware (PLM_DEVICE_BLOCK pDevice);

 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-LM_UINT32
-LM_RegRdInd(
-PLM_DEVICE_BLOCK pDevice,
-LM_UINT32 Register) {
-    LM_UINT32 Value32;
+LM_UINT32 LM_RegRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register)
+{
+       LM_UINT32 Value32;

 
 #if PCIX_TARGET_WORKAROUND
 
 #if PCIX_TARGET_WORKAROUND

-    MM_ACQUIRE_UNDI_LOCK(pDevice);
+       MM_ACQUIRE_UNDI_LOCK (pDevice);

 #endif
 #endif

-    MM_WriteConfig32(pDevice, T3_PCI_REG_ADDR_REG, Register);
-    MM_ReadConfig32(pDevice, T3_PCI_REG_DATA_REG, &Value32);
+       MM_WriteConfig32 (pDevice, T3_PCI_REG_ADDR_REG, Register);
+       MM_ReadConfig32 (pDevice, T3_PCI_REG_DATA_REG, &Value32);

 #if PCIX_TARGET_WORKAROUND
 #if PCIX_TARGET_WORKAROUND

-    MM_RELEASE_UNDI_LOCK(pDevice);
+       MM_RELEASE_UNDI_LOCK (pDevice);

 #endif
 
 #endif
 

-    return Value32;
-} /* LM_RegRdInd */
-
+       return Value32;
+}                              /* LM_RegRdInd */

 
 /******************************************************************************/
 /* Description:                                                               */
 
 /******************************************************************************/
 /* Description:                                                               */


@@ -96,47 +97,41 @@ LM_UINT32 Register) {
 /* Return:                                                                    */
 /******************************************************************************/
 LM_VOID
 /* Return:                                                                    */
 /******************************************************************************/
 LM_VOID

-LM_RegWrInd(
-PLM_DEVICE_BLOCK pDevice,
-LM_UINT32 Register,
-LM_UINT32 Value32) {
+LM_RegWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register, LM_UINT32 Value32)
+{

 
 #if PCIX_TARGET_WORKAROUND
 
 #if PCIX_TARGET_WORKAROUND

-    MM_ACQUIRE_UNDI_LOCK(pDevice);
+       MM_ACQUIRE_UNDI_LOCK (pDevice);

 #endif
 #endif

-    MM_WriteConfig32(pDevice, T3_PCI_REG_ADDR_REG, Register);
-    MM_WriteConfig32(pDevice, T3_PCI_REG_DATA_REG, Value32);
+       MM_WriteConfig32 (pDevice, T3_PCI_REG_ADDR_REG, Register);
+       MM_WriteConfig32 (pDevice, T3_PCI_REG_DATA_REG, Value32);

 #if PCIX_TARGET_WORKAROUND
 #if PCIX_TARGET_WORKAROUND

-    MM_RELEASE_UNDI_LOCK(pDevice);
+       MM_RELEASE_UNDI_LOCK (pDevice);

 #endif
 #endif

-} /* LM_RegWrInd */
-
+}                              /* LM_RegWrInd */

 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-LM_UINT32
-LM_MemRdInd(
-PLM_DEVICE_BLOCK pDevice,
-LM_UINT32 MemAddr) {
-    LM_UINT32 Value32;
+LM_UINT32 LM_MemRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr)
+{
+       LM_UINT32 Value32;

 
 

-    MM_ACQUIRE_UNDI_LOCK(pDevice);
+       MM_ACQUIRE_UNDI_LOCK (pDevice);

 #ifdef BIG_ENDIAN_HOST
 #ifdef BIG_ENDIAN_HOST

-    MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
-    Value32 = REG_RD(pDevice, PciCfg.MemWindowData);
-    /*    Value32 = REG_RD(pDevice,uIntMem.Mbuf[(MemAddr & 0x7fff)/4]); */
+       MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
+       Value32 = REG_RD (pDevice, PciCfg.MemWindowData);
+       /*    Value32 = REG_RD(pDevice,uIntMem.Mbuf[(MemAddr & 0x7fff)/4]); */

 #else
 #else

-    MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
-    MM_ReadConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, &Value32);
+       MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
+       MM_ReadConfig32 (pDevice, T3_PCI_MEM_WIN_DATA_REG, &Value32);

 #endif
 #endif

-    MM_RELEASE_UNDI_LOCK(pDevice);
-
-    return Value32;
-} /* LM_MemRdInd */
+       MM_RELEASE_UNDI_LOCK (pDevice);

 
 

+       return Value32;
+}                              /* LM_MemRdInd */

 
 /******************************************************************************/
 /* Description:                                                               */
 
 /******************************************************************************/
 /* Description:                                                               */


@@ -144,168 +139,161 @@ LM_UINT32 MemAddr) {
 /* Return:                                                                    */
 /******************************************************************************/
 LM_VOID
 /* Return:                                                                    */
 /******************************************************************************/
 LM_VOID

-LM_MemWrInd(
-PLM_DEVICE_BLOCK pDevice,
-LM_UINT32 MemAddr,
-LM_UINT32 Value32) {
-    MM_ACQUIRE_UNDI_LOCK(pDevice);
+LM_MemWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr, LM_UINT32 Value32)
+{
+       MM_ACQUIRE_UNDI_LOCK (pDevice);

 #ifdef BIG_ENDIAN_HOST
 #ifdef BIG_ENDIAN_HOST

-    REG_WR(pDevice,PciCfg.MemWindowBaseAddr,MemAddr);
-    REG_WR(pDevice,uIntMem.Mbuf[(MemAddr & 0x7fff)/4],Value32);
+       REG_WR (pDevice, PciCfg.MemWindowBaseAddr, MemAddr);
+       REG_WR (pDevice, uIntMem.Mbuf[(MemAddr & 0x7fff) / 4], Value32);

 #else
 #else

-    MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
-    MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, Value32);
+       MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, MemAddr);
+       MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_DATA_REG, Value32);

 #endif
 #endif

-    MM_RELEASE_UNDI_LOCK(pDevice);
-} /* LM_MemWrInd */
-
+       MM_RELEASE_UNDI_LOCK (pDevice);
+}                              /* LM_MemWrInd */

 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-LM_STATUS
-LM_QueueRxPackets(
-PLM_DEVICE_BLOCK pDevice) {
-    LM_STATUS Lmstatus;
-    PLM_PACKET pPacket;
-    PT3_RCV_BD pRcvBd;
-    LM_UINT32 StdBdAdded = 0;
+LM_STATUS LM_QueueRxPackets (PLM_DEVICE_BLOCK pDevice)
+{
+       LM_STATUS Lmstatus;
+       PLM_PACKET pPacket;
+       PT3_RCV_BD pRcvBd;
+       LM_UINT32 StdBdAdded = 0;

 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT

-    LM_UINT32 JumboBdAdded = 0;
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+       LM_UINT32 JumboBdAdded = 0;
+#endif                         /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */

 
 

-    Lmstatus = LM_STATUS_SUCCESS;
+       Lmstatus = LM_STATUS_SUCCESS;

 
 

-    pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
-    while(pPacket) {
-       switch(pPacket->u.Rx.RcvProdRing) {
+       pPacket = (PLM_PACKET) QQ_PopHead (&pDevice->RxPacketFreeQ.Container);
+       while (pPacket) {
+               switch (pPacket->u.Rx.RcvProdRing) {

 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT

-           case T3_JUMBO_RCV_PROD_RING:        /* Jumbo Receive Ring. */
-               /* Initialize the buffer descriptor. */
-               pRcvBd =
-                   &pDevice->pRxJumboBdVirt[pDevice->RxJumboProdIdx];
-               pRcvBd->Flags = RCV_BD_FLAG_END | RCV_BD_FLAG_JUMBO_RING;
-               pRcvBd->Len = (LM_UINT16) pDevice->RxJumboBufferSize;
-
-               /* Initialize the receive buffer pointer */
-#if 0 /* Jimmy, deleted in new */
-               pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low;
-               pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High;
+               case T3_JUMBO_RCV_PROD_RING:    /* Jumbo Receive Ring. */
+                       /* Initialize the buffer descriptor. */
+                       pRcvBd =
+                           &pDevice->pRxJumboBdVirt[pDevice->RxJumboProdIdx];
+                       pRcvBd->Flags =
+                           RCV_BD_FLAG_END | RCV_BD_FLAG_JUMBO_RING;
+                       pRcvBd->Len = (LM_UINT16) pDevice->RxJumboBufferSize;
+
+                       /* Initialize the receive buffer pointer */
+#if 0                          /* Jimmy, deleted in new */
+                       pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low;
+                       pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High;

 #endif
 #endif

-               MM_MapRxDma(pDevice, pPacket, &pRcvBd->HostAddr);
+                       MM_MapRxDma (pDevice, pPacket, &pRcvBd->HostAddr);

 
 

-               /* The opaque field may point to an offset from a fix addr. */
-               pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR(pPacket) -
-                   MM_UINT_PTR(pDevice->pPacketDescBase));
+                       /* The opaque field may point to an offset from a fix addr. */
+                       pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR (pPacket) -
+                                                     MM_UINT_PTR (pDevice->
+                                                                  pPacketDescBase));

 
 

-               /* Update the producer index. */
-               pDevice->RxJumboProdIdx = (pDevice->RxJumboProdIdx + 1) &
-                   T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK;
+                       /* Update the producer index. */
+                       pDevice->RxJumboProdIdx =
+                           (pDevice->RxJumboProdIdx +
+                            1) & T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK;

 
 

-               JumboBdAdded++;
-               break;
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
-           case T3_STD_RCV_PROD_RING:      /* Standard Receive Ring. */
-               /* Initialize the buffer descriptor. */
-               pRcvBd = &pDevice->pRxStdBdVirt[pDevice->RxStdProdIdx];
-               pRcvBd->Flags = RCV_BD_FLAG_END;
-               pRcvBd->Len = MAX_STD_RCV_BUFFER_SIZE;
-
-               /* Initialize the receive buffer pointer */
-#if 0  /* Jimmy, deleted in new replaced with MM_MapRxDma */
-               pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low;
-               pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High;
+                       JumboBdAdded++;
+                       break;
+#endif                         /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+
+               case T3_STD_RCV_PROD_RING:      /* Standard Receive Ring. */
+                       /* Initialize the buffer descriptor. */
+                       pRcvBd = &pDevice->pRxStdBdVirt[pDevice->RxStdProdIdx];
+                       pRcvBd->Flags = RCV_BD_FLAG_END;
+                       pRcvBd->Len = MAX_STD_RCV_BUFFER_SIZE;
+
+                       /* Initialize the receive buffer pointer */
+#if 0                          /* Jimmy, deleted in new replaced with MM_MapRxDma */
+                       pRcvBd->HostAddr.Low = pPacket->u.Rx.RxBufferPhy.Low;
+                       pRcvBd->HostAddr.High = pPacket->u.Rx.RxBufferPhy.High;

 #endif
 #endif

-               MM_MapRxDma(pDevice, pPacket, &pRcvBd->HostAddr);
+                       MM_MapRxDma (pDevice, pPacket, &pRcvBd->HostAddr);

 
 

-               /* The opaque field may point to an offset from a fix addr. */
-               pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR(pPacket) -
-                   MM_UINT_PTR(pDevice->pPacketDescBase));
+                       /* The opaque field may point to an offset from a fix addr. */
+                       pRcvBd->Opaque = (LM_UINT32) (MM_UINT_PTR (pPacket) -
+                                                     MM_UINT_PTR (pDevice->
+                                                                  pPacketDescBase));

 
 

-               /* Update the producer index. */
-               pDevice->RxStdProdIdx = (pDevice->RxStdProdIdx + 1) &
-                   T3_STD_RCV_RCB_ENTRY_COUNT_MASK;
+                       /* Update the producer index. */
+                       pDevice->RxStdProdIdx = (pDevice->RxStdProdIdx + 1) &
+                           T3_STD_RCV_RCB_ENTRY_COUNT_MASK;

 
 

-               StdBdAdded++;
-               break;
+                       StdBdAdded++;
+                       break;

 
 

-           case T3_UNKNOWN_RCV_PROD_RING:
-           default:
-               Lmstatus = LM_STATUS_FAILURE;
-               break;
-       } /* switch */
+               case T3_UNKNOWN_RCV_PROD_RING:
+               default:
+                       Lmstatus = LM_STATUS_FAILURE;
+                       break;
+               }               /* switch */

 
 

-       /* Bail out if there is any error. */
-       if(Lmstatus != LM_STATUS_SUCCESS)
-       {
-           break;
-       }
+               /* Bail out if there is any error. */
+               if (Lmstatus != LM_STATUS_SUCCESS) {
+                       break;
+               }

 
 

-       pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
-    } /* while */
+               pPacket =
+                   (PLM_PACKET) QQ_PopHead (&pDevice->RxPacketFreeQ.Container);
+       }                       /* while */

 
 

-    wmb();
-    /* Update the procedure index. */
-    if(StdBdAdded)
-    {
-       MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low, pDevice->RxStdProdIdx);
-    }
+       wmb ();
+       /* Update the procedure index. */
+       if (StdBdAdded) {
+               MB_REG_WR (pDevice, Mailbox.RcvStdProdIdx.Low,
+                          pDevice->RxStdProdIdx);
+       }

 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT

-    if(JumboBdAdded)
-    {
-       MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low,
-           pDevice->RxJumboProdIdx);
-    }
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
-    return Lmstatus;
-} /* LM_QueueRxPackets */
+       if (JumboBdAdded) {
+               MB_REG_WR (pDevice, Mailbox.RcvJumboProdIdx.Low,
+                          pDevice->RxJumboProdIdx);
+       }
+#endif                         /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */

 
 

+       return Lmstatus;
+}                              /* LM_QueueRxPackets */

 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-STATIC LM_VOID
-LM_NvramInit(
-    PLM_DEVICE_BLOCK pDevice)
+STATIC LM_VOID LM_NvramInit (PLM_DEVICE_BLOCK pDevice)

 {
 {

-    LM_UINT32 Value32;
-    LM_UINT32 j;
-
-    /* Intialize clock period and state machine. */
-    Value32 = SEEPROM_ADDR_CLK_PERD(SEEPROM_CLOCK_PERIOD) |
-       SEEPROM_ADDR_FSM_RESET;
-    REG_WR(pDevice, Grc.EepromAddr, Value32);
-
-    for(j = 0; j < 100; j++)
-    {
-       MM_Wait(10);
-    }
-
-    /* Serial eeprom access using the Grc.EepromAddr/EepromData registers. */
-    Value32 = REG_RD(pDevice, Grc.LocalCtrl);
-    REG_WR(pDevice, Grc.LocalCtrl, Value32 | GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM);
-
-    /* Set the 5701 compatibility mode if we are using EEPROM. */
-    if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
-       T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701)
-    {
-       Value32 = REG_RD(pDevice, Nvram.Config1);
-       if((Value32 & FLASH_INTERFACE_ENABLE) == 0)
-       {
-           /* Use the new interface to read EEPROM. */
-           Value32 &= ~FLASH_COMPAT_BYPASS;
+       LM_UINT32 Value32;
+       LM_UINT32 j;

 
 

-           REG_WR(pDevice, Nvram.Config1, Value32);
+       /* Intialize clock period and state machine. */
+       Value32 = SEEPROM_ADDR_CLK_PERD (SEEPROM_CLOCK_PERIOD) |
+           SEEPROM_ADDR_FSM_RESET;
+       REG_WR (pDevice, Grc.EepromAddr, Value32);
+
+       for (j = 0; j < 100; j++) {
+               MM_Wait (10);

        }
        }

-    }
-} /* LM_NvRamInit */

 
 

+       /* Serial eeprom access using the Grc.EepromAddr/EepromData registers. */
+       Value32 = REG_RD (pDevice, Grc.LocalCtrl);
+       REG_WR (pDevice, Grc.LocalCtrl,
+               Value32 | GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM);
+
+       /* Set the 5701 compatibility mode if we are using EEPROM. */
+       if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
+           T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5701) {
+               Value32 = REG_RD (pDevice, Nvram.Config1);
+               if ((Value32 & FLASH_INTERFACE_ENABLE) == 0) {
+                       /* Use the new interface to read EEPROM. */
+                       Value32 &= ~FLASH_COMPAT_BYPASS;
+
+                       REG_WR (pDevice, Nvram.Config1, Value32);
+               }
+       }
+}                              /* LM_NvRamInit */

 
 /******************************************************************************/
 /* Description:                                                               */
 
 /******************************************************************************/
 /* Description:                                                               */


@@ -313,51 +301,44 @@ LM_NvramInit(
 /* Return:                                                                    */
 /******************************************************************************/
 STATIC LM_STATUS
 /* Return:                                                                    */
 /******************************************************************************/
 STATIC LM_STATUS

-LM_EepromRead(
-    PLM_DEVICE_BLOCK pDevice,
-    LM_UINT32 Offset,
-    LM_UINT32 *pData)
+LM_EepromRead (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT32 * pData)

 {
 {

-    LM_UINT32 Value32;
-    LM_UINT32 Addr;
-    LM_UINT32 Dev;
-    LM_UINT32 j;
+       LM_UINT32 Value32;
+       LM_UINT32 Addr;
+       LM_UINT32 Dev;
+       LM_UINT32 j;

 
 

-    if(Offset > SEEPROM_CHIP_SIZE)
-    {
-       return LM_STATUS_FAILURE;
-    }
+       if (Offset > SEEPROM_CHIP_SIZE) {
+               return LM_STATUS_FAILURE;
+       }

 
 

-    Dev = Offset / SEEPROM_CHIP_SIZE;
-    Addr = Offset % SEEPROM_CHIP_SIZE;
+       Dev = Offset / SEEPROM_CHIP_SIZE;
+       Addr = Offset % SEEPROM_CHIP_SIZE;

 
 

-    Value32 = REG_RD(pDevice, Grc.EepromAddr);
-    Value32 &= ~(SEEPROM_ADDR_ADDRESS_MASK | SEEPROM_ADDR_DEV_ID_MASK |
-       SEEPROM_ADDR_RW_MASK);
-    REG_WR(pDevice, Grc.EepromAddr, Value32 | SEEPROM_ADDR_DEV_ID(Dev) |
-       SEEPROM_ADDR_ADDRESS(Addr) | SEEPROM_ADDR_START | SEEPROM_ADDR_READ);
+       Value32 = REG_RD (pDevice, Grc.EepromAddr);
+       Value32 &= ~(SEEPROM_ADDR_ADDRESS_MASK | SEEPROM_ADDR_DEV_ID_MASK |
+                    SEEPROM_ADDR_RW_MASK);
+       REG_WR (pDevice, Grc.EepromAddr, Value32 | SEEPROM_ADDR_DEV_ID (Dev) |
+               SEEPROM_ADDR_ADDRESS (Addr) | SEEPROM_ADDR_START |
+               SEEPROM_ADDR_READ);

 
 

-    for(j = 0; j < 1000; j++)
-    {
-       Value32 = REG_RD(pDevice, Grc.EepromAddr);
-       if(Value32 & SEEPROM_ADDR_COMPLETE)
-       {
-           break;
+       for (j = 0; j < 1000; j++) {
+               Value32 = REG_RD (pDevice, Grc.EepromAddr);
+               if (Value32 & SEEPROM_ADDR_COMPLETE) {
+                       break;
+               }
+               MM_Wait (10);

        }
        }

-       MM_Wait(10);
-    }
-
-    if(Value32 & SEEPROM_ADDR_COMPLETE)
-    {
-       Value32 = REG_RD(pDevice, Grc.EepromData);
-       *pData = Value32;

 
 

-       return LM_STATUS_SUCCESS;
-    }
+       if (Value32 & SEEPROM_ADDR_COMPLETE) {
+               Value32 = REG_RD (pDevice, Grc.EepromData);
+               *pData = Value32;

 
 

-    return LM_STATUS_FAILURE;
-} /* LM_EepromRead */
+               return LM_STATUS_SUCCESS;
+       }

 
 

+       return LM_STATUS_FAILURE;
+}                              /* LM_EepromRead */

 
 /******************************************************************************/
 /* Description:                                                               */
 
 /******************************************************************************/
 /* Description:                                                               */


@@ -365,291 +346,248 @@ LM_EepromRead(
 /* Return:                                                                    */
 /******************************************************************************/
 STATIC LM_STATUS
 /* Return:                                                                    */
 /******************************************************************************/
 STATIC LM_STATUS

-LM_NvramRead(
-    PLM_DEVICE_BLOCK pDevice,
-    LM_UINT32 Offset,
-    LM_UINT32 *pData)
+LM_NvramRead (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Offset, LM_UINT32 * pData)

 {
 {

-    LM_UINT32 Value32;
-    LM_STATUS Status;
-    LM_UINT32 j;
-
-    if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
-       T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
-    {
-       Status = LM_EepromRead(pDevice, Offset, pData);
-    }
-    else
-    {
-       /* Determine if we have flash or EEPROM. */
-       Value32 = REG_RD(pDevice, Nvram.Config1);
-       if(Value32 & FLASH_INTERFACE_ENABLE)
-       {
-           if(Value32 & FLASH_SSRAM_BUFFERRED_MODE)
-           {
-               Offset = ((Offset/BUFFERED_FLASH_PAGE_SIZE) <<
-                   BUFFERED_FLASH_PAGE_POS) +
-                   (Offset % BUFFERED_FLASH_PAGE_SIZE);
-           }
-       }
+       LM_UINT32 Value32;
+       LM_STATUS Status;
+       LM_UINT32 j;
+
+       if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+           T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+               Status = LM_EepromRead (pDevice, Offset, pData);
+       } else {
+               /* Determine if we have flash or EEPROM. */
+               Value32 = REG_RD (pDevice, Nvram.Config1);
+               if (Value32 & FLASH_INTERFACE_ENABLE) {
+                       if (Value32 & FLASH_SSRAM_BUFFERRED_MODE) {
+                               Offset = ((Offset / BUFFERED_FLASH_PAGE_SIZE) <<
+                                         BUFFERED_FLASH_PAGE_POS) +
+                                   (Offset % BUFFERED_FLASH_PAGE_SIZE);
+                       }
+               }

 
 

-       REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_SET1);
-       for (j = 0; j < 1000; j++)
-       {
-           if (REG_RD(pDevice, Nvram.SwArb) & SW_ARB_GNT1)
-           {
-               break;
-           }
-           MM_Wait(20);
-       }
-       if (j == 1000)
-       {
-           return LM_STATUS_FAILURE;
-       }
+               REG_WR (pDevice, Nvram.SwArb, SW_ARB_REQ_SET1);
+               for (j = 0; j < 1000; j++) {
+                       if (REG_RD (pDevice, Nvram.SwArb) & SW_ARB_GNT1) {
+                               break;
+                       }
+                       MM_Wait (20);
+               }
+               if (j == 1000) {
+                       return LM_STATUS_FAILURE;
+               }

 
 

-       /* Read from flash or EEPROM with the new 5703/02 interface. */
-       REG_WR(pDevice, Nvram.Addr, Offset & NVRAM_ADDRESS_MASK);
+               /* Read from flash or EEPROM with the new 5703/02 interface. */
+               REG_WR (pDevice, Nvram.Addr, Offset & NVRAM_ADDRESS_MASK);

 
 

-       REG_WR(pDevice, Nvram.Cmd, NVRAM_CMD_RD | NVRAM_CMD_DO_IT |
-           NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
+               REG_WR (pDevice, Nvram.Cmd, NVRAM_CMD_RD | NVRAM_CMD_DO_IT |
+                       NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);

 
 

-       /* Wait for the done bit to clear. */
-       for(j = 0; j < 500; j++)
-       {
-           MM_Wait(10);
+               /* Wait for the done bit to clear. */
+               for (j = 0; j < 500; j++) {
+                       MM_Wait (10);

 
 

-           Value32 = REG_RD(pDevice, Nvram.Cmd);
-           if(!(Value32 & NVRAM_CMD_DONE))
-           {
-               break;
-           }
-       }
+                       Value32 = REG_RD (pDevice, Nvram.Cmd);
+                       if (!(Value32 & NVRAM_CMD_DONE)) {
+                               break;
+                       }
+               }

 
 

-       /* Wait for the done bit. */
-       if(!(Value32 & NVRAM_CMD_DONE))
-       {
-           for(j = 0; j < 500; j++)
-           {
-               MM_Wait(10);
+               /* Wait for the done bit. */
+               if (!(Value32 & NVRAM_CMD_DONE)) {
+                       for (j = 0; j < 500; j++) {
+                               MM_Wait (10);

 
 

-               Value32 = REG_RD(pDevice, Nvram.Cmd);
-               if(Value32 & NVRAM_CMD_DONE)
-               {
-                   MM_Wait(10);
+                               Value32 = REG_RD (pDevice, Nvram.Cmd);
+                               if (Value32 & NVRAM_CMD_DONE) {
+                                       MM_Wait (10);

 
 

-                   *pData = REG_RD(pDevice, Nvram.ReadData);
+                                       *pData =
+                                           REG_RD (pDevice, Nvram.ReadData);

 
 

-                   /* Change the endianess. */
-                   *pData = ((*pData & 0xff) << 24)| ((*pData & 0xff00) << 8)|
-                       ((*pData & 0xff0000) >> 8) | ((*pData >> 24) & 0xff);
+                                       /* Change the endianess. */
+                                       *pData =
+                                           ((*pData & 0xff) << 24) |
+                                           ((*pData & 0xff00) << 8) |
+                                           ((*pData & 0xff0000) >> 8) |
+                                           ((*pData >> 24) & 0xff);

 
 

-                   break;
+                                       break;
+                               }
+                       }

                }
                }

-           }
-       }

 
 

-       REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1);
-       if(Value32 & NVRAM_CMD_DONE)
-       {
-           Status = LM_STATUS_SUCCESS;
-       }
-       else
-       {
-           Status = LM_STATUS_FAILURE;
+               REG_WR (pDevice, Nvram.SwArb, SW_ARB_REQ_CLR1);
+               if (Value32 & NVRAM_CMD_DONE) {
+                       Status = LM_STATUS_SUCCESS;
+               } else {
+                       Status = LM_STATUS_FAILURE;
+               }

        }
        }

-    }
-
-    return Status;
-} /* LM_NvramRead */

 
 

+       return Status;
+}                              /* LM_NvramRead */

 
 

-STATIC void
-LM_ReadVPD(PLM_DEVICE_BLOCK pDevice)
+STATIC void LM_ReadVPD (PLM_DEVICE_BLOCK pDevice)

 {
 {

-    LM_UINT32 Vpd_arr[256/4];
-    LM_UINT8 *Vpd = (LM_UINT8 *) &Vpd_arr[0];
-    LM_UINT32 *Vpd_dptr = &Vpd_arr[0];
-    LM_UINT32 Value32;
-    unsigned int j;
-
-    /* Read PN from VPD */
-    for (j = 0; j < 256; j += 4, Vpd_dptr++ )
-    {
-       if (LM_NvramRead(pDevice, 0x100 + j, &Value32) != LM_STATUS_SUCCESS) {
-           printf("BCM570x: LM_ReadVPD: VPD read failed"
-                  " (no EEPROM onboard)\n");
-           return;
-       }
-       *Vpd_dptr = cpu_to_le32(Value32);
-    }
-    for (j = 0; j < 256; )
-    {
-       unsigned int Vpd_r_len;
-       unsigned int Vpd_r_end;
-
-       if ((Vpd[j] == 0x82) || (Vpd[j] == 0x91))
-       {
-           j = j + 3 + Vpd[j + 1] + (Vpd[j + 2] << 8);
-       }
-       else if (Vpd[j] == 0x90)
-       {
-           Vpd_r_len =  Vpd[j + 1] + (Vpd[j + 2] << 8);
-           j += 3;
-           Vpd_r_end = Vpd_r_len + j;
-           while (j < Vpd_r_end)
-           {
-               if ((Vpd[j] == 'P') && (Vpd[j + 1] == 'N'))
-               {
-                   unsigned int len = Vpd[j + 2];
-
-                   if (len <= 24)
-                   {
-                       memcpy(pDevice->PartNo, &Vpd[j + 3], len);
-                   }
-                   break;
+       LM_UINT32 Vpd_arr[256 / 4];
+       LM_UINT8 *Vpd = (LM_UINT8 *) & Vpd_arr[0];
+       LM_UINT32 *Vpd_dptr = &Vpd_arr[0];
+       LM_UINT32 Value32;
+       unsigned int j;
+
+       /* Read PN from VPD */
+       for (j = 0; j < 256; j += 4, Vpd_dptr++) {
+               if (LM_NvramRead (pDevice, 0x100 + j, &Value32) !=
+                   LM_STATUS_SUCCESS) {
+                       printf ("BCM570x: LM_ReadVPD: VPD read failed"
+                               " (no EEPROM onboard)\n");
+                       return;

                }
                }

-               else
-               {
-                   if (Vpd[j + 2] == 0)
-                   {
+               *Vpd_dptr = cpu_to_le32 (Value32);
+       }
+       for (j = 0; j < 256;) {
+               unsigned int Vpd_r_len;
+               unsigned int Vpd_r_end;
+
+               if ((Vpd[j] == 0x82) || (Vpd[j] == 0x91)) {
+                       j = j + 3 + Vpd[j + 1] + (Vpd[j + 2] << 8);
+               } else if (Vpd[j] == 0x90) {
+                       Vpd_r_len = Vpd[j + 1] + (Vpd[j + 2] << 8);
+                       j += 3;
+                       Vpd_r_end = Vpd_r_len + j;
+                       while (j < Vpd_r_end) {
+                               if ((Vpd[j] == 'P') && (Vpd[j + 1] == 'N')) {
+                                       unsigned int len = Vpd[j + 2];
+
+                                       if (len <= 24) {
+                                               memcpy (pDevice->PartNo,
+                                                       &Vpd[j + 3], len);
+                                       }
+                                       break;
+                               } else {
+                                       if (Vpd[j + 2] == 0) {
+                                               break;
+                                       }
+                                       j = j + Vpd[j + 2];
+                               }
+                       }
+                       break;
+               } else {

                        break;
                        break;

-                   }
-                   j = j + Vpd[j + 2];

                }
                }

-           }
-           break;

        }
        }

-       else {
-           break;
-       }
-    }

 }
 
 }
 

-STATIC void
-LM_ReadBootCodeVersion(PLM_DEVICE_BLOCK pDevice)
+STATIC void LM_ReadBootCodeVersion (PLM_DEVICE_BLOCK pDevice)

 {
 {

-    LM_UINT32 Value32, offset, ver_offset;
-    int i;
-
-    if (LM_NvramRead(pDevice, 0x0, &Value32) != LM_STATUS_SUCCESS)
-       return;
-    if (Value32 != 0xaa559966)
-       return;
-    if (LM_NvramRead(pDevice, 0xc, &offset) != LM_STATUS_SUCCESS)
-       return;
-
-    offset = ((offset & 0xff) << 24)| ((offset & 0xff00) << 8)|
-       ((offset & 0xff0000) >> 8) | ((offset >> 24) & 0xff);
-    if (LM_NvramRead(pDevice, offset, &Value32) != LM_STATUS_SUCCESS)
-       return;
-    if ((Value32 == 0x0300000e) &&
-       (LM_NvramRead(pDevice, offset + 4, &Value32) == LM_STATUS_SUCCESS) &&
-       (Value32 == 0)) {
-
-       if (LM_NvramRead(pDevice, offset + 8, &ver_offset) != LM_STATUS_SUCCESS)
-           return;
-       ver_offset = ((ver_offset & 0xff0000) >> 8) |
-           ((ver_offset >> 24) & 0xff);
-       for (i = 0; i < 16; i += 4) {
-           if (LM_NvramRead(pDevice, offset + ver_offset + i, &Value32) !=
-               LM_STATUS_SUCCESS)
-           {
+       LM_UINT32 Value32, offset, ver_offset;
+       int i;
+
+       if (LM_NvramRead (pDevice, 0x0, &Value32) != LM_STATUS_SUCCESS)

                return;
                return;

-           }
-           *((LM_UINT32 *) &pDevice->BootCodeVer[i]) = cpu_to_le32(Value32);
-       }
-    }
-    else {
-       char c;
+       if (Value32 != 0xaa559966)
+               return;
+       if (LM_NvramRead (pDevice, 0xc, &offset) != LM_STATUS_SUCCESS)
+               return;
+
+       offset = ((offset & 0xff) << 24) | ((offset & 0xff00) << 8) |
+           ((offset & 0xff0000) >> 8) | ((offset >> 24) & 0xff);
+       if (LM_NvramRead (pDevice, offset, &Value32) != LM_STATUS_SUCCESS)
+               return;
+       if ((Value32 == 0x0300000e) &&
+           (LM_NvramRead (pDevice, offset + 4, &Value32) == LM_STATUS_SUCCESS)
+           && (Value32 == 0)) {
+
+               if (LM_NvramRead (pDevice, offset + 8, &ver_offset) !=
+                   LM_STATUS_SUCCESS)
+                       return;
+               ver_offset = ((ver_offset & 0xff0000) >> 8) |
+                   ((ver_offset >> 24) & 0xff);
+               for (i = 0; i < 16; i += 4) {
+                       if (LM_NvramRead
+                           (pDevice, offset + ver_offset + i,
+                            &Value32) != LM_STATUS_SUCCESS) {
+                               return;
+                       }
+                       *((LM_UINT32 *) & pDevice->BootCodeVer[i]) =
+                           cpu_to_le32 (Value32);
+               }
+       } else {
+               char c;

 
 

-       if (LM_NvramRead(pDevice, 0x94, &Value32) != LM_STATUS_SUCCESS)
-           return;
+               if (LM_NvramRead (pDevice, 0x94, &Value32) != LM_STATUS_SUCCESS)
+                       return;

 
 

-       i = 0;
-       c = ((Value32 & 0xff0000) >> 16);
+               i = 0;
+               c = ((Value32 & 0xff0000) >> 16);

 
 

-       if (c < 10) {
-           pDevice->BootCodeVer[i++] = c + '0';
-       }
-       else {
-           pDevice->BootCodeVer[i++] = (c / 10) + '0';
-           pDevice->BootCodeVer[i++] = (c % 10) + '0';
-       }
-       pDevice->BootCodeVer[i++] = '.';
-       c = (Value32 & 0xff000000) >> 24;
-       if (c < 10) {
-           pDevice->BootCodeVer[i++] = c + '0';
-       }
-       else {
-           pDevice->BootCodeVer[i++] = (c / 10) + '0';
-           pDevice->BootCodeVer[i++] = (c % 10) + '0';
+               if (c < 10) {
+                       pDevice->BootCodeVer[i++] = c + '0';
+               } else {
+                       pDevice->BootCodeVer[i++] = (c / 10) + '0';
+                       pDevice->BootCodeVer[i++] = (c % 10) + '0';
+               }
+               pDevice->BootCodeVer[i++] = '.';
+               c = (Value32 & 0xff000000) >> 24;
+               if (c < 10) {
+                       pDevice->BootCodeVer[i++] = c + '0';
+               } else {
+                       pDevice->BootCodeVer[i++] = (c / 10) + '0';
+                       pDevice->BootCodeVer[i++] = (c % 10) + '0';
+               }
+               pDevice->BootCodeVer[i] = 0;

        }
        }

-       pDevice->BootCodeVer[i] = 0;
-    }

 }
 
 }
 

-STATIC void
-LM_GetBusSpeed(PLM_DEVICE_BLOCK pDevice)
+STATIC void LM_GetBusSpeed (PLM_DEVICE_BLOCK pDevice)

 {
 {

-    LM_UINT32 PciState = pDevice->PciState;
-    LM_UINT32 ClockCtrl;
-    char *SpeedStr = "";
-
-    if (PciState & T3_PCI_STATE_32BIT_PCI_BUS)
-    {
-       strcpy(pDevice->BusSpeedStr, "32-bit ");
-    }
-    else
-    {
-       strcpy(pDevice->BusSpeedStr, "64-bit ");
-    }
-    if (PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)
-    {
-       strcat(pDevice->BusSpeedStr, "PCI ");
-       if (PciState & T3_PCI_STATE_HIGH_BUS_SPEED)
-       {
-           SpeedStr = "66MHz";
-       }
-       else
-       {
-           SpeedStr = "33MHz";
-       }
-    }
-    else
-    {
-       strcat(pDevice->BusSpeedStr, "PCIX ");
-       if (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE)
-       {
-           SpeedStr = "133MHz";
-       }
-       else
-       {
-           ClockCtrl = REG_RD(pDevice, PciCfg.ClockCtrl) & 0x1f;
-           switch (ClockCtrl)
-           {
-           case 0:
-               SpeedStr = "33MHz";
-               break;
-
-           case 2:
-               SpeedStr = "50MHz";
-               break;
-
-           case 4:
-               SpeedStr = "66MHz";
-               break;
-
-           case 6:
-               SpeedStr = "100MHz";
-               break;
-
-           case 7:
-               SpeedStr = "133MHz";
-               break;
-           }
+       LM_UINT32 PciState = pDevice->PciState;
+       LM_UINT32 ClockCtrl;
+       char *SpeedStr = "";
+
+       if (PciState & T3_PCI_STATE_32BIT_PCI_BUS) {
+               strcpy (pDevice->BusSpeedStr, "32-bit ");
+       } else {
+               strcpy (pDevice->BusSpeedStr, "64-bit ");
+       }
+       if (PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) {
+               strcat (pDevice->BusSpeedStr, "PCI ");
+               if (PciState & T3_PCI_STATE_HIGH_BUS_SPEED) {
+                       SpeedStr = "66MHz";
+               } else {
+                       SpeedStr = "33MHz";
+               }
+       } else {
+               strcat (pDevice->BusSpeedStr, "PCIX ");
+               if (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE) {
+                       SpeedStr = "133MHz";
+               } else {
+                       ClockCtrl = REG_RD (pDevice, PciCfg.ClockCtrl) & 0x1f;
+                       switch (ClockCtrl) {
+                       case 0:
+                               SpeedStr = "33MHz";
+                               break;
+
+                       case 2:
+                               SpeedStr = "50MHz";
+                               break;
+
+                       case 4:
+                               SpeedStr = "66MHz";
+                               break;
+
+                       case 6:
+                               SpeedStr = "100MHz";
+                               break;
+
+                       case 7:
+                               SpeedStr = "133MHz";
+                               break;
+                       }
+               }

        }
        }

-    }
-    strcat(pDevice->BusSpeedStr, SpeedStr);
+       strcat (pDevice->BusSpeedStr, SpeedStr);

 }
 
 /******************************************************************************/
 }
 
 /******************************************************************************/


@@ -660,977 +598,890 @@ LM_GetBusSpeed(PLM_DEVICE_BLOCK pDevice)
 /* Return:                                                                    */
 /*    LM_STATUS_SUCCESS                                                       */
 /******************************************************************************/
 /* Return:                                                                    */
 /*    LM_STATUS_SUCCESS                                                       */
 /******************************************************************************/

-LM_STATUS
-LM_GetAdapterInfo(
-PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_GetAdapterInfo (PLM_DEVICE_BLOCK pDevice)

 {
 {

-    PLM_ADAPTER_INFO pAdapterInfo;
-    LM_UINT32 Value32;
-    LM_STATUS Status;
-    LM_UINT32 j;
-    LM_UINT32 EeSigFound;
-    LM_UINT32 EePhyTypeSerdes = 0;
-    LM_UINT32 EePhyLedMode = 0;
-    LM_UINT32 EePhyId = 0;
-
-    /* Get Device Id and Vendor Id */
-    Status = MM_ReadConfig32(pDevice, PCI_VENDOR_ID_REG, &Value32);
-    if(Status != LM_STATUS_SUCCESS)
-    {
-       return Status;
-    }
-    pDevice->PciVendorId = (LM_UINT16) Value32;
-    pDevice->PciDeviceId = (LM_UINT16) (Value32 >> 16);
-
-    /* If we are not getting the write adapter, exit. */
-    if((Value32 != T3_PCI_ID_BCM5700) &&
-       (Value32 != T3_PCI_ID_BCM5701) &&
-       (Value32 != T3_PCI_ID_BCM5702) &&
-       (Value32 != T3_PCI_ID_BCM5702x) &&
-       (Value32 != T3_PCI_ID_BCM5702FE) &&
-       (Value32 != T3_PCI_ID_BCM5703) &&
-       (Value32 != T3_PCI_ID_BCM5703x) &&
-       (Value32 != T3_PCI_ID_BCM5704))
-    {
-       return LM_STATUS_FAILURE;
-    }
+       PLM_ADAPTER_INFO pAdapterInfo;
+       LM_UINT32 Value32;
+       LM_STATUS Status;
+       LM_UINT32 j;
+       LM_UINT32 EeSigFound;
+       LM_UINT32 EePhyTypeSerdes = 0;
+       LM_UINT32 EePhyLedMode = 0;
+       LM_UINT32 EePhyId = 0;
+
+       /* Get Device Id and Vendor Id */
+       Status = MM_ReadConfig32 (pDevice, PCI_VENDOR_ID_REG, &Value32);
+       if (Status != LM_STATUS_SUCCESS) {
+               return Status;
+       }
+       pDevice->PciVendorId = (LM_UINT16) Value32;
+       pDevice->PciDeviceId = (LM_UINT16) (Value32 >> 16);
+
+       /* If we are not getting the write adapter, exit. */
+       if ((Value32 != T3_PCI_ID_BCM5700) &&
+           (Value32 != T3_PCI_ID_BCM5701) &&
+           (Value32 != T3_PCI_ID_BCM5702) &&
+           (Value32 != T3_PCI_ID_BCM5702x) &&
+           (Value32 != T3_PCI_ID_BCM5702FE) &&
+           (Value32 != T3_PCI_ID_BCM5703) &&
+           (Value32 != T3_PCI_ID_BCM5703x) && (Value32 != T3_PCI_ID_BCM5704)) {
+               return LM_STATUS_FAILURE;
+       }

 
 

-    Status = MM_ReadConfig32(pDevice, PCI_REV_ID_REG, &Value32);
-    if(Status != LM_STATUS_SUCCESS)
-    {
-       return Status;
-    }
-    pDevice->PciRevId = (LM_UINT8) Value32;
+       Status = MM_ReadConfig32 (pDevice, PCI_REV_ID_REG, &Value32);
+       if (Status != LM_STATUS_SUCCESS) {
+               return Status;
+       }
+       pDevice->PciRevId = (LM_UINT8) Value32;

 
 

-    /* Get IRQ. */
-    Status = MM_ReadConfig32(pDevice, PCI_INT_LINE_REG, &Value32);
-    if(Status != LM_STATUS_SUCCESS)
-    {
-       return Status;
-    }
-    pDevice->Irq = (LM_UINT8) Value32;
+       /* Get IRQ. */
+       Status = MM_ReadConfig32 (pDevice, PCI_INT_LINE_REG, &Value32);
+       if (Status != LM_STATUS_SUCCESS) {
+               return Status;
+       }
+       pDevice->Irq = (LM_UINT8) Value32;

 
 

-    /* Get interrupt pin. */
-    pDevice->IntPin = (LM_UINT8) (Value32 >> 8);
+       /* Get interrupt pin. */
+       pDevice->IntPin = (LM_UINT8) (Value32 >> 8);

 
 

-    /* Get chip revision id. */
-    Status = MM_ReadConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, &Value32);
-    pDevice->ChipRevId = Value32 >> 16;
+       /* Get chip revision id. */
+       Status = MM_ReadConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG, &Value32);
+       pDevice->ChipRevId = Value32 >> 16;

 
 

-    /* Get subsystem vendor. */
-    Status = MM_ReadConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, &Value32);
-    if(Status != LM_STATUS_SUCCESS)
-    {
-       return Status;
-    }
-    pDevice->SubsystemVendorId = (LM_UINT16) Value32;
+       /* Get subsystem vendor. */
+       Status =
+           MM_ReadConfig32 (pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG, &Value32);
+       if (Status != LM_STATUS_SUCCESS) {
+               return Status;
+       }
+       pDevice->SubsystemVendorId = (LM_UINT16) Value32;

 
 

-    /* Get PCI subsystem id. */
-    pDevice->SubsystemId = (LM_UINT16) (Value32 >> 16);
+       /* Get PCI subsystem id. */
+       pDevice->SubsystemId = (LM_UINT16) (Value32 >> 16);

 
 

-    /* Get the cache line size. */
-    MM_ReadConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG, &Value32);
-    pDevice->CacheLineSize = (LM_UINT8) Value32;
-    pDevice->SavedCacheLineReg = Value32;
+       /* Get the cache line size. */
+       MM_ReadConfig32 (pDevice, PCI_CACHE_LINE_SIZE_REG, &Value32);
+       pDevice->CacheLineSize = (LM_UINT8) Value32;
+       pDevice->SavedCacheLineReg = Value32;

 
 

-    if(pDevice->ChipRevId != T3_CHIP_ID_5703_A1 &&
-       pDevice->ChipRevId != T3_CHIP_ID_5703_A2 &&
-       pDevice->ChipRevId != T3_CHIP_ID_5704_A0)
-    {
-       pDevice->UndiFix = FALSE;
-    }
+       if (pDevice->ChipRevId != T3_CHIP_ID_5703_A1 &&
+           pDevice->ChipRevId != T3_CHIP_ID_5703_A2 &&
+           pDevice->ChipRevId != T3_CHIP_ID_5704_A0) {
+               pDevice->UndiFix = FALSE;
+       }

 #if !PCIX_TARGET_WORKAROUND
 #if !PCIX_TARGET_WORKAROUND

-    pDevice->UndiFix = FALSE;
+       pDevice->UndiFix = FALSE;

 #endif
 #endif

-    /* Map the memory base to system address space. */
-    if (!pDevice->UndiFix)
-    {
-       Status = MM_MapMemBase(pDevice);
-       if(Status != LM_STATUS_SUCCESS)
-       {
-           return Status;
+       /* Map the memory base to system address space. */
+       if (!pDevice->UndiFix) {
+               Status = MM_MapMemBase (pDevice);
+               if (Status != LM_STATUS_SUCCESS) {
+                       return Status;
+               }
+               /* Initialize the memory view pointer. */
+               pDevice->pMemView = (PT3_STD_MEM_MAP) pDevice->pMappedMemBase;

        }
        }

-       /* Initialize the memory view pointer. */
-       pDevice->pMemView = (PT3_STD_MEM_MAP) pDevice->pMappedMemBase;
-    }
-

 #if PCIX_TARGET_WORKAROUND
 #if PCIX_TARGET_WORKAROUND

-    /* store whether we are in PCI are PCI-X mode */
-    pDevice->EnablePciXFix = FALSE;
-
-    MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32);
-    if((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0)
-    {
-       /* Enable PCI-X workaround only if we are running on 5700 BX. */
-       if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX)
-       {
-           pDevice->EnablePciXFix = TRUE;
+       /* store whether we are in PCI are PCI-X mode */
+       pDevice->EnablePciXFix = FALSE;
+
+       MM_ReadConfig32 (pDevice, T3_PCI_STATE_REG, &Value32);
+       if ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0) {
+               /* Enable PCI-X workaround only if we are running on 5700 BX. */
+               if (T3_CHIP_REV (pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) {
+                       pDevice->EnablePciXFix = TRUE;
+               }
+       }
+       if (pDevice->UndiFix) {
+               pDevice->EnablePciXFix = TRUE;

        }
        }

-    }
-    if (pDevice->UndiFix)
-    {
-       pDevice->EnablePciXFix = TRUE;
-    }

 #endif
 #endif

-    /* Bx bug: due to the "byte_enable bug" in PCI-X mode, the power */
-    /* management register may be clobbered which may cause the */
-    /* BCM5700 to go into D3 state.  While in this state, we will */
-    /* not have memory mapped register access.  As a workaround, we */
-    /* need to restore the device to D0 state. */
-    MM_ReadConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, &Value32);
-    Value32 |= T3_PM_PME_ASSERTED;
-    Value32 &= ~T3_PM_POWER_STATE_MASK;
-    Value32 |= T3_PM_POWER_STATE_D0;
-    MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, Value32);
-
-    /* read the current PCI command word */
-    MM_ReadConfig32(pDevice, PCI_COMMAND_REG, &Value32);
-
-    /* Make sure bus-mastering is enabled. */
-    Value32 |= PCI_BUSMASTER_ENABLE;
+       /* Bx bug: due to the "byte_enable bug" in PCI-X mode, the power */
+       /* management register may be clobbered which may cause the */
+       /* BCM5700 to go into D3 state.  While in this state, we will */
+       /* not have memory mapped register access.  As a workaround, we */
+       /* need to restore the device to D0 state. */
+       MM_ReadConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, &Value32);
+       Value32 |= T3_PM_PME_ASSERTED;
+       Value32 &= ~T3_PM_POWER_STATE_MASK;
+       Value32 |= T3_PM_POWER_STATE_D0;
+       MM_WriteConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, Value32);
+
+       /* read the current PCI command word */
+       MM_ReadConfig32 (pDevice, PCI_COMMAND_REG, &Value32);
+
+       /* Make sure bus-mastering is enabled. */
+       Value32 |= PCI_BUSMASTER_ENABLE;

 
 #if PCIX_TARGET_WORKAROUND
 
 #if PCIX_TARGET_WORKAROUND

-    /* if we are in PCI-X mode, also make sure mem-mapping and SERR#/PERR#
-       are enabled */
-    if (pDevice->EnablePciXFix == TRUE) {
-       Value32 |= (PCI_MEM_SPACE_ENABLE | PCI_SYSTEM_ERROR_ENABLE |
-                   PCI_PARITY_ERROR_ENABLE);
-    }
-    if (pDevice->UndiFix)
-    {
-       Value32 &= ~PCI_MEM_SPACE_ENABLE;
-    }
-
+       /* if we are in PCI-X mode, also make sure mem-mapping and SERR#/PERR#
+          are enabled */
+       if (pDevice->EnablePciXFix == TRUE) {
+               Value32 |= (PCI_MEM_SPACE_ENABLE | PCI_SYSTEM_ERROR_ENABLE |
+                           PCI_PARITY_ERROR_ENABLE);
+       }
+       if (pDevice->UndiFix) {
+               Value32 &= ~PCI_MEM_SPACE_ENABLE;
+       }

 #endif
 
 #endif
 

-    if(pDevice->EnableMWI)
-    {
-       Value32 |= PCI_MEMORY_WRITE_INVALIDATE;
-    }
-    else {
-       Value32 &= (~PCI_MEMORY_WRITE_INVALIDATE);
-    }
-
-    /* Error out if mem-mapping is NOT enabled for PCI systems */
-    if (!(Value32 | PCI_MEM_SPACE_ENABLE))
-    {
-       return LM_STATUS_FAILURE;
-    }
+       if (pDevice->EnableMWI) {
+               Value32 |= PCI_MEMORY_WRITE_INVALIDATE;
+       } else {
+               Value32 &= (~PCI_MEMORY_WRITE_INVALIDATE);
+       }
+
+       /* Error out if mem-mapping is NOT enabled for PCI systems */
+       if (!(Value32 | PCI_MEM_SPACE_ENABLE)) {
+               return LM_STATUS_FAILURE;
+       }

 
 

-    /* save the value we are going to write into the PCI command word */
-    pDevice->PciCommandStatusWords = Value32;
+       /* save the value we are going to write into the PCI command word */
+       pDevice->PciCommandStatusWords = Value32;

 
 

-    Status = MM_WriteConfig32(pDevice, PCI_COMMAND_REG, Value32);
-    if(Status != LM_STATUS_SUCCESS)
-    {
-       return Status;
-    }
+       Status = MM_WriteConfig32 (pDevice, PCI_COMMAND_REG, Value32);
+       if (Status != LM_STATUS_SUCCESS) {
+               return Status;
+       }

 
 

-    /* Set power state to D0. */
-    LM_SetPowerState(pDevice, LM_POWER_STATE_D0);
+       /* Set power state to D0. */
+       LM_SetPowerState (pDevice, LM_POWER_STATE_D0);

 
 #ifdef BIG_ENDIAN_PCI
 
 #ifdef BIG_ENDIAN_PCI

-    pDevice->MiscHostCtrl =
-       MISC_HOST_CTRL_MASK_PCI_INT |
-       MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
-       MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP |
-       MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
-#else /* No CPU Swap modes for PCI IO */
-
-    /* Setup the mode registers. */
-    pDevice->MiscHostCtrl =
-       MISC_HOST_CTRL_MASK_PCI_INT |
-       MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP |
+       pDevice->MiscHostCtrl =
+           MISC_HOST_CTRL_MASK_PCI_INT |
+           MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
+           MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP |
+           MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
+#else                          /* No CPU Swap modes for PCI IO */
+
+       /* Setup the mode registers. */
+       pDevice->MiscHostCtrl =
+           MISC_HOST_CTRL_MASK_PCI_INT |
+           MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP |

 #ifdef BIG_ENDIAN_HOST
 #ifdef BIG_ENDIAN_HOST

-       MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP |
-#endif /* BIG_ENDIAN_HOST */
-       MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
-       MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
-#endif /* !BIG_ENDIAN_PCI */
+           MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP |
+#endif                         /* BIG_ENDIAN_HOST */
+           MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS |
+           MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW;
+#endif                         /* !BIG_ENDIAN_PCI */

 
 

-    /* write to PCI misc host ctr first in order to enable indirect accesses */
-    MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl);
+       /* write to PCI misc host ctr first in order to enable indirect accesses */
+       MM_WriteConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG,
+                         pDevice->MiscHostCtrl);

 
 

-    REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl);
+       REG_WR (pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl);

 
 #ifdef BIG_ENDIAN_PCI
 
 #ifdef BIG_ENDIAN_PCI

-    Value32 = GRC_MODE_WORD_SWAP_DATA|
-             GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
+       Value32 = GRC_MODE_WORD_SWAP_DATA | GRC_MODE_WORD_SWAP_NON_FRAME_DATA;

 #else
 /* No CPU Swap modes for PCI IO */
 #ifdef BIG_ENDIAN_HOST
 #else
 /* No CPU Swap modes for PCI IO */
 #ifdef BIG_ENDIAN_HOST

-    Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
-             GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
+       Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
+           GRC_MODE_WORD_SWAP_NON_FRAME_DATA;

 #else
 #else

-    Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;
+       Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;

 #endif
 #endif

-#endif /* !BIG_ENDIAN_PCI */
-
-    REG_WR(pDevice, Grc.Mode, Value32);
-
-    if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
-    {
-       REG_WR(pDevice, Grc.LocalCtrl, GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
-           GRC_MISC_LOCAL_CTRL_GPIO_OE1);
-    }
-    MM_Wait(40);
-
-    /* Enable indirect memory access */
-    REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);
-
-    if (REG_RD(pDevice, PciCfg.ClockCtrl) & T3_PCI_44MHZ_CORE_CLOCK)
-    {
-       REG_WR(pDevice, PciCfg.ClockCtrl, T3_PCI_44MHZ_CORE_CLOCK |
-               T3_PCI_SELECT_ALTERNATE_CLOCK);
-       REG_WR(pDevice, PciCfg.ClockCtrl, T3_PCI_SELECT_ALTERNATE_CLOCK);
-       MM_Wait(40);  /* required delay is 27usec */
-    }
-    REG_WR(pDevice, PciCfg.ClockCtrl, 0);
-    REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0);
+#endif                         /* !BIG_ENDIAN_PCI */
+
+       REG_WR (pDevice, Grc.Mode, Value32);
+
+       if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+               REG_WR (pDevice, Grc.LocalCtrl,
+                       GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
+                       GRC_MISC_LOCAL_CTRL_GPIO_OE1);
+       }
+       MM_Wait (40);
+
+       /* Enable indirect memory access */
+       REG_WR (pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);
+
+       if (REG_RD (pDevice, PciCfg.ClockCtrl) & T3_PCI_44MHZ_CORE_CLOCK) {
+               REG_WR (pDevice, PciCfg.ClockCtrl, T3_PCI_44MHZ_CORE_CLOCK |
+                       T3_PCI_SELECT_ALTERNATE_CLOCK);
+               REG_WR (pDevice, PciCfg.ClockCtrl,
+                       T3_PCI_SELECT_ALTERNATE_CLOCK);
+               MM_Wait (40);   /* required delay is 27usec */
+       }
+       REG_WR (pDevice, PciCfg.ClockCtrl, 0);
+       REG_WR (pDevice, PciCfg.MemWindowBaseAddr, 0);

 
 #if PCIX_TARGET_WORKAROUND
 
 #if PCIX_TARGET_WORKAROUND

-    MM_ReadConfig32(pDevice, T3_PCI_STATE_REG, &Value32);
-    if ((pDevice->EnablePciXFix == FALSE) &&
-       ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0))
-    {
-       if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
-           pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
-           pDevice->ChipRevId == T3_CHIP_ID_5701_B2 ||
-           pDevice->ChipRevId == T3_CHIP_ID_5701_B5)
-       {
-           __raw_writel(0, &(pDevice->pMemView->uIntMem.MemBlock32K[0x300]));
-           __raw_writel(0, &(pDevice->pMemView->uIntMem.MemBlock32K[0x301]));
-           __raw_writel(0xffffffff, &(pDevice->pMemView->uIntMem.MemBlock32K[0x301]));
-           if (__raw_readl(&(pDevice->pMemView->uIntMem.MemBlock32K[0x300])))
-           {
-               pDevice->EnablePciXFix = TRUE;
-           }
+       MM_ReadConfig32 (pDevice, T3_PCI_STATE_REG, &Value32);
+       if ((pDevice->EnablePciXFix == FALSE) &&
+           ((Value32 & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) == 0)) {
+               if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
+                   pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
+                   pDevice->ChipRevId == T3_CHIP_ID_5701_B2 ||
+                   pDevice->ChipRevId == T3_CHIP_ID_5701_B5) {
+                       __raw_writel (0,
+                                     &(pDevice->pMemView->uIntMem.
+                                       MemBlock32K[0x300]));
+                       __raw_writel (0,
+                                     &(pDevice->pMemView->uIntMem.
+                                       MemBlock32K[0x301]));
+                       __raw_writel (0xffffffff,
+                                     &(pDevice->pMemView->uIntMem.
+                                       MemBlock32K[0x301]));
+                       if (__raw_readl
+                           (&(pDevice->pMemView->uIntMem.MemBlock32K[0x300])))
+                       {
+                               pDevice->EnablePciXFix = TRUE;
+                       }
+               }

        }
        }

-    }

 #endif
 #if 1
 #endif
 #if 1

-    /*
-    *  This code was at the beginning of else block below, but that's
-    *  a bug if node address in shared memory.
-    */
-    MM_Wait(50);
-    LM_NvramInit(pDevice);
+       /*
+        *  This code was at the beginning of else block below, but that's
+        *  a bug if node address in shared memory.
+        */
+       MM_Wait (50);
+       LM_NvramInit (pDevice);

 #endif
 #endif

-    /* Get the node address.  First try to get in from the shared memory. */
-    /* If the signature is not present, then get it from the NVRAM. */
-    Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_HIGH_MAILBOX);
-    if((Value32 >> 16) == 0x484b)
-    {
-
-       pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 8);
-       pDevice->NodeAddress[1] = (LM_UINT8) Value32;
-
-       Value32 = MEM_RD_OFFSET(pDevice, T3_MAC_ADDR_LOW_MAILBOX);
-
-       pDevice->NodeAddress[2] = (LM_UINT8) (Value32 >> 24);
-       pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 16);
-       pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 8);
-       pDevice->NodeAddress[5] = (LM_UINT8) Value32;
-
-       Status = LM_STATUS_SUCCESS;
-    }
-    else
-    {
-       Status = LM_NvramRead(pDevice, 0x7c, &Value32);
-       if(Status == LM_STATUS_SUCCESS)
-       {
-           pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 16);
-           pDevice->NodeAddress[1] = (LM_UINT8) (Value32 >> 24);
-
-           Status = LM_NvramRead(pDevice, 0x80, &Value32);
-
-           pDevice->NodeAddress[2] = (LM_UINT8) Value32;
-           pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 8);
-           pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 16);
-           pDevice->NodeAddress[5] = (LM_UINT8) (Value32 >> 24);
+       /* Get the node address.  First try to get in from the shared memory. */
+       /* If the signature is not present, then get it from the NVRAM. */
+       Value32 = MEM_RD_OFFSET (pDevice, T3_MAC_ADDR_HIGH_MAILBOX);
+       if ((Value32 >> 16) == 0x484b) {
+
+               pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 8);
+               pDevice->NodeAddress[1] = (LM_UINT8) Value32;
+
+               Value32 = MEM_RD_OFFSET (pDevice, T3_MAC_ADDR_LOW_MAILBOX);
+
+               pDevice->NodeAddress[2] = (LM_UINT8) (Value32 >> 24);
+               pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 16);
+               pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 8);
+               pDevice->NodeAddress[5] = (LM_UINT8) Value32;
+
+               Status = LM_STATUS_SUCCESS;
+       } else {
+               Status = LM_NvramRead (pDevice, 0x7c, &Value32);
+               if (Status == LM_STATUS_SUCCESS) {
+                       pDevice->NodeAddress[0] = (LM_UINT8) (Value32 >> 16);
+                       pDevice->NodeAddress[1] = (LM_UINT8) (Value32 >> 24);
+
+                       Status = LM_NvramRead (pDevice, 0x80, &Value32);
+
+                       pDevice->NodeAddress[2] = (LM_UINT8) Value32;
+                       pDevice->NodeAddress[3] = (LM_UINT8) (Value32 >> 8);
+                       pDevice->NodeAddress[4] = (LM_UINT8) (Value32 >> 16);
+                       pDevice->NodeAddress[5] = (LM_UINT8) (Value32 >> 24);
+               }

        }
        }

-    }

 
 

-    /* Assign a default address. */
-    if(Status != LM_STATUS_SUCCESS)
-    {
+       /* Assign a default address. */
+       if (Status != LM_STATUS_SUCCESS) {

 #ifndef EMBEDDED
 #ifndef EMBEDDED

-       printk(KERN_ERR "Cannot get MAC addr from NVRAM. Using default.\n");
-#endif
-       pDevice->NodeAddress[0] = 0x00; pDevice->NodeAddress[1] = 0x10;
-       pDevice->NodeAddress[2] = 0x18; pDevice->NodeAddress[3] = 0x68;
-       pDevice->NodeAddress[4] = 0x61; pDevice->NodeAddress[5] = 0x76;
-    }
-
-    pDevice->PermanentNodeAddress[0] = pDevice->NodeAddress[0];
-    pDevice->PermanentNodeAddress[1] = pDevice->NodeAddress[1];
-    pDevice->PermanentNodeAddress[2] = pDevice->NodeAddress[2];
-    pDevice->PermanentNodeAddress[3] = pDevice->NodeAddress[3];
-    pDevice->PermanentNodeAddress[4] = pDevice->NodeAddress[4];
-    pDevice->PermanentNodeAddress[5] = pDevice->NodeAddress[5];
-
-    /* Initialize the default values. */
-    pDevice->NoTxPseudoHdrChksum = FALSE;
-    pDevice->NoRxPseudoHdrChksum = FALSE;
-    pDevice->NicSendBd = FALSE;
-    pDevice->TxPacketDescCnt = DEFAULT_TX_PACKET_DESC_COUNT;
-    pDevice->RxStdDescCnt = DEFAULT_STD_RCV_DESC_COUNT;
-    pDevice->RxCoalescingTicks = DEFAULT_RX_COALESCING_TICKS;
-    pDevice->TxCoalescingTicks = DEFAULT_TX_COALESCING_TICKS;
-    pDevice->RxMaxCoalescedFrames = DEFAULT_RX_MAX_COALESCED_FRAMES;
-    pDevice->TxMaxCoalescedFrames = DEFAULT_TX_MAX_COALESCED_FRAMES;
-    pDevice->RxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
-    pDevice->TxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
-    pDevice->RxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
-    pDevice->TxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
-    pDevice->StatsCoalescingTicks = DEFAULT_STATS_COALESCING_TICKS;
-    pDevice->EnableMWI = FALSE;
-    pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
-    pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
-    pDevice->DisableAutoNeg = FALSE;
-    pDevice->PhyIntMode = T3_PHY_INT_MODE_AUTO;
-    pDevice->LinkChngMode = T3_LINK_CHNG_MODE_AUTO;
-    pDevice->LedMode = LED_MODE_AUTO;
-    pDevice->ResetPhyOnInit = TRUE;
-    pDevice->DelayPciGrant = TRUE;
-    pDevice->UseTaggedStatus = FALSE;
-    pDevice->OneDmaAtOnce = BAD_DEFAULT_VALUE;
-
-    pDevice->DmaMbufLowMark = T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO;
-    pDevice->RxMacMbufLowMark = T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO;
-    pDevice->MbufHighMark = T3_DEF_MBUF_HIGH_WMARK_JUMBO;
-
-    pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_AUTO;
-    pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_NONE;
-    pDevice->FlowControlCap = LM_FLOW_CONTROL_AUTO_PAUSE;
-    pDevice->EnableTbi = FALSE;
-#if INCLUDE_TBI_SUPPORT
-    pDevice->PollTbiLink = BAD_DEFAULT_VALUE;
+               printk (KERN_ERR
+                       "Cannot get MAC addr from NVRAM. Using default.\n");

 #endif
 #endif

+               pDevice->NodeAddress[0] = 0x00;
+               pDevice->NodeAddress[1] = 0x10;
+               pDevice->NodeAddress[2] = 0x18;
+               pDevice->NodeAddress[3] = 0x68;
+               pDevice->NodeAddress[4] = 0x61;
+               pDevice->NodeAddress[5] = 0x76;
+       }
+
+       pDevice->PermanentNodeAddress[0] = pDevice->NodeAddress[0];
+       pDevice->PermanentNodeAddress[1] = pDevice->NodeAddress[1];
+       pDevice->PermanentNodeAddress[2] = pDevice->NodeAddress[2];
+       pDevice->PermanentNodeAddress[3] = pDevice->NodeAddress[3];
+       pDevice->PermanentNodeAddress[4] = pDevice->NodeAddress[4];
+       pDevice->PermanentNodeAddress[5] = pDevice->NodeAddress[5];
+
+       /* Initialize the default values. */
+       pDevice->NoTxPseudoHdrChksum = FALSE;
+       pDevice->NoRxPseudoHdrChksum = FALSE;
+       pDevice->NicSendBd = FALSE;
+       pDevice->TxPacketDescCnt = DEFAULT_TX_PACKET_DESC_COUNT;
+       pDevice->RxStdDescCnt = DEFAULT_STD_RCV_DESC_COUNT;
+       pDevice->RxCoalescingTicks = DEFAULT_RX_COALESCING_TICKS;
+       pDevice->TxCoalescingTicks = DEFAULT_TX_COALESCING_TICKS;
+       pDevice->RxMaxCoalescedFrames = DEFAULT_RX_MAX_COALESCED_FRAMES;
+       pDevice->TxMaxCoalescedFrames = DEFAULT_TX_MAX_COALESCED_FRAMES;
+       pDevice->RxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
+       pDevice->TxCoalescingTicksDuringInt = BAD_DEFAULT_VALUE;
+       pDevice->RxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
+       pDevice->TxMaxCoalescedFramesDuringInt = BAD_DEFAULT_VALUE;
+       pDevice->StatsCoalescingTicks = DEFAULT_STATS_COALESCING_TICKS;
+       pDevice->EnableMWI = FALSE;
+       pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
+       pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
+       pDevice->DisableAutoNeg = FALSE;
+       pDevice->PhyIntMode = T3_PHY_INT_MODE_AUTO;
+       pDevice->LinkChngMode = T3_LINK_CHNG_MODE_AUTO;
+       pDevice->LedMode = LED_MODE_AUTO;
+       pDevice->ResetPhyOnInit = TRUE;
+       pDevice->DelayPciGrant = TRUE;
+       pDevice->UseTaggedStatus = FALSE;
+       pDevice->OneDmaAtOnce = BAD_DEFAULT_VALUE;

 
 

-    switch (T3_ASIC_REV(pDevice->ChipRevId))
-    {
-    case T3_ASIC_REV_5704:
-       pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
-       pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE64;
-       break;
-    default:
-       pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
-       pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE96;
-       break;
-    }
-
-    pDevice->LinkStatus = LM_STATUS_LINK_DOWN;
-    pDevice->QueueRxPackets = TRUE;
-
-    pDevice->EnableWireSpeed = TRUE;
+       pDevice->DmaMbufLowMark = T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO;
+       pDevice->RxMacMbufLowMark = T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO;
+       pDevice->MbufHighMark = T3_DEF_MBUF_HIGH_WMARK_JUMBO;

 
 

-#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
-    pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT;
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
-    /* Make this is a known adapter. */
-    pAdapterInfo = LM_GetAdapterInfoBySsid(pDevice->SubsystemVendorId,
-       pDevice->SubsystemId);
-
-    pDevice->BondId = REG_RD(pDevice, Grc.MiscCfg) & GRC_MISC_BD_ID_MASK;
-    if (pDevice->BondId != GRC_MISC_BD_ID_5700 &&
-       pDevice->BondId != GRC_MISC_BD_ID_5701 &&
-       pDevice->BondId != GRC_MISC_BD_ID_5702FE &&
-       pDevice->BondId != GRC_MISC_BD_ID_5703 &&
-       pDevice->BondId != GRC_MISC_BD_ID_5703S &&
-       pDevice->BondId != GRC_MISC_BD_ID_5704 &&
-       pDevice->BondId != GRC_MISC_BD_ID_5704CIOBE)
-    {
-       return LM_STATUS_UNKNOWN_ADAPTER;
-    }
-
-    pDevice->SplitModeEnable = SPLIT_MODE_DISABLE;
-    if ((pDevice->ChipRevId == T3_CHIP_ID_5704_A0) &&
-       (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE))
-    {
-       pDevice->SplitModeEnable = SPLIT_MODE_ENABLE;
-       pDevice->SplitModeMaxReq = SPLIT_MODE_5704_MAX_REQ;
-    }
-
-    /* Get Eeprom info. */
-    Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_SIG_ADDR);
-    if (Value32 == T3_NIC_DATA_SIG)
-    {
-       EeSigFound = TRUE;
-       Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_NIC_CFG_ADDR);
-
-       /* Determine PHY type. */
-       switch (Value32 & T3_NIC_CFG_PHY_TYPE_MASK)
-       {
-           case T3_NIC_CFG_PHY_TYPE_COPPER:
-               EePhyTypeSerdes = FALSE;
-               break;
+       pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_AUTO;
+       pDevice->TaskOffloadCap = LM_TASK_OFFLOAD_NONE;
+       pDevice->FlowControlCap = LM_FLOW_CONTROL_AUTO_PAUSE;
+       pDevice->EnableTbi = FALSE;
+#if INCLUDE_TBI_SUPPORT
+       pDevice->PollTbiLink = BAD_DEFAULT_VALUE;
+#endif

 
 

-           case T3_NIC_CFG_PHY_TYPE_FIBER:
-               EePhyTypeSerdes = TRUE;
+       switch (T3_ASIC_REV (pDevice->ChipRevId)) {
+       case T3_ASIC_REV_5704:
+               pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
+               pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE64;

                break;
                break;

-
-           default:
-               EePhyTypeSerdes = FALSE;
+       default:
+               pDevice->MbufBase = T3_NIC_MBUF_POOL_ADDR;
+               pDevice->MbufSize = T3_NIC_MBUF_POOL_SIZE96;

                break;
        }
 
                break;
        }
 

-       /* Determine PHY led mode. */
-       if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
-           T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
-       {
-           switch(Value32 & T3_NIC_CFG_LED_MODE_MASK)
-           {
-               case T3_NIC_CFG_LED_MODE_TRIPLE_SPEED:
-                   EePhyLedMode = LED_MODE_THREE_LINK;
-                   break;
+       pDevice->LinkStatus = LM_STATUS_LINK_DOWN;
+       pDevice->QueueRxPackets = TRUE;

 
 

-               case T3_NIC_CFG_LED_MODE_LINK_SPEED:
-                   EePhyLedMode = LED_MODE_LINK10;
-                   break;
+       pDevice->EnableWireSpeed = TRUE;

 
 

-               default:
-                   EePhyLedMode = LED_MODE_AUTO;
-                   break;
-           }
-       }
-       else
-       {
-           switch(Value32 & T3_NIC_CFG_LED_MODE_MASK)
-           {
-               case T3_NIC_CFG_LED_MODE_OPEN_DRAIN:
-                   EePhyLedMode = LED_MODE_OPEN_DRAIN;
-                   break;
+#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
+       pDevice->RxJumboDescCnt = DEFAULT_JUMBO_RCV_DESC_COUNT;
+#endif                         /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+
+       /* Make this is a known adapter. */
+       pAdapterInfo = LM_GetAdapterInfoBySsid (pDevice->SubsystemVendorId,
+                                               pDevice->SubsystemId);
+
+       pDevice->BondId = REG_RD (pDevice, Grc.MiscCfg) & GRC_MISC_BD_ID_MASK;
+       if (pDevice->BondId != GRC_MISC_BD_ID_5700 &&
+           pDevice->BondId != GRC_MISC_BD_ID_5701 &&
+           pDevice->BondId != GRC_MISC_BD_ID_5702FE &&
+           pDevice->BondId != GRC_MISC_BD_ID_5703 &&
+           pDevice->BondId != GRC_MISC_BD_ID_5703S &&
+           pDevice->BondId != GRC_MISC_BD_ID_5704 &&
+           pDevice->BondId != GRC_MISC_BD_ID_5704CIOBE) {
+               return LM_STATUS_UNKNOWN_ADAPTER;
+       }
+
+       pDevice->SplitModeEnable = SPLIT_MODE_DISABLE;
+       if ((pDevice->ChipRevId == T3_CHIP_ID_5704_A0) &&
+           (pDevice->BondId == GRC_MISC_BD_ID_5704CIOBE)) {
+               pDevice->SplitModeEnable = SPLIT_MODE_ENABLE;
+               pDevice->SplitModeMaxReq = SPLIT_MODE_5704_MAX_REQ;
+       }
+
+       /* Get Eeprom info. */
+       Value32 = MEM_RD_OFFSET (pDevice, T3_NIC_DATA_SIG_ADDR);
+       if (Value32 == T3_NIC_DATA_SIG) {
+               EeSigFound = TRUE;
+               Value32 = MEM_RD_OFFSET (pDevice, T3_NIC_DATA_NIC_CFG_ADDR);
+
+               /* Determine PHY type. */
+               switch (Value32 & T3_NIC_CFG_PHY_TYPE_MASK) {
+               case T3_NIC_CFG_PHY_TYPE_COPPER:
+                       EePhyTypeSerdes = FALSE;
+                       break;

 
 

-               case T3_NIC_CFG_LED_MODE_OUTPUT:
-                   EePhyLedMode = LED_MODE_OUTPUT;
-                   break;
+               case T3_NIC_CFG_PHY_TYPE_FIBER:
+                       EePhyTypeSerdes = TRUE;
+                       break;

 
                default:
 
                default:

-                   EePhyLedMode = LED_MODE_AUTO;
-                   break;
-           }
-       }
-       if(pDevice->ChipRevId == T3_CHIP_ID_5703_A1 ||
-           pDevice->ChipRevId == T3_CHIP_ID_5703_A2)
-       {
-           /* Enable EEPROM write protection. */
-           if(Value32 & T3_NIC_EEPROM_WP)
-           {
-               pDevice->EepromWp = TRUE;
-           }
-       }
+                       EePhyTypeSerdes = FALSE;
+                       break;
+               }

 
 

-       /* Get the PHY Id. */
-       Value32 = MEM_RD_OFFSET(pDevice, T3_NIC_DATA_PHY_ID_ADDR);
-       if (Value32)
-       {
-           EePhyId = (((Value32 & T3_NIC_PHY_ID1_MASK) >> 16) &
-               PHY_ID1_OUI_MASK) << 10;
+               /* Determine PHY led mode. */
+               if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+                   T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+                       switch (Value32 & T3_NIC_CFG_LED_MODE_MASK) {
+                       case T3_NIC_CFG_LED_MODE_TRIPLE_SPEED:
+                               EePhyLedMode = LED_MODE_THREE_LINK;
+                               break;
+
+                       case T3_NIC_CFG_LED_MODE_LINK_SPEED:
+                               EePhyLedMode = LED_MODE_LINK10;
+                               break;
+
+                       default:
+                               EePhyLedMode = LED_MODE_AUTO;
+                               break;
+                       }
+               } else {
+                       switch (Value32 & T3_NIC_CFG_LED_MODE_MASK) {
+                       case T3_NIC_CFG_LED_MODE_OPEN_DRAIN:
+                               EePhyLedMode = LED_MODE_OPEN_DRAIN;
+                               break;
+
+                       case T3_NIC_CFG_LED_MODE_OUTPUT:
+                               EePhyLedMode = LED_MODE_OUTPUT;
+                               break;
+
+                       default:
+                               EePhyLedMode = LED_MODE_AUTO;
+                               break;
+                       }
+               }
+               if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1 ||
+                   pDevice->ChipRevId == T3_CHIP_ID_5703_A2) {
+                       /* Enable EEPROM write protection. */
+                       if (Value32 & T3_NIC_EEPROM_WP) {
+                               pDevice->EepromWp = TRUE;
+                       }
+               }

 
 

-           Value32 = Value32 & T3_NIC_PHY_ID2_MASK;
+               /* Get the PHY Id. */
+               Value32 = MEM_RD_OFFSET (pDevice, T3_NIC_DATA_PHY_ID_ADDR);
+               if (Value32) {
+                       EePhyId = (((Value32 & T3_NIC_PHY_ID1_MASK) >> 16) &
+                                  PHY_ID1_OUI_MASK) << 10;

 
 

-           EePhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
-             (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK);
-       }
-       else
-       {
-           EePhyId = 0;
+                       Value32 = Value32 & T3_NIC_PHY_ID2_MASK;
+
+                       EePhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
+                           (Value32 & PHY_ID2_MODEL_MASK) | (Value32 &
+                                                             PHY_ID2_REV_MASK);
+               } else {
+                       EePhyId = 0;
+               }
+       } else {
+               EeSigFound = FALSE;

        }
        }

-    }
-    else
-    {
-       EeSigFound = FALSE;
-    }

 
 

-    /* Set the PHY address. */
-    pDevice->PhyAddr = PHY_DEVICE_ID;
+       /* Set the PHY address. */
+       pDevice->PhyAddr = PHY_DEVICE_ID;

 
 

-    /* Disable auto polling. */
-    pDevice->MiMode = 0xc0000;
-    REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
-    MM_Wait(40);
+       /* Disable auto polling. */
+       pDevice->MiMode = 0xc0000;
+       REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
+       MM_Wait (40);

 
 

-    /* Get the PHY id. */
-    LM_ReadPhy(pDevice, PHY_ID1_REG, &Value32);
-    pDevice->PhyId = (Value32 & PHY_ID1_OUI_MASK) << 10;
+       /* Get the PHY id. */
+       LM_ReadPhy (pDevice, PHY_ID1_REG, &Value32);
+       pDevice->PhyId = (Value32 & PHY_ID1_OUI_MASK) << 10;

 
 

-    LM_ReadPhy(pDevice, PHY_ID2_REG, &Value32);
-    pDevice->PhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
-      (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK);
+       LM_ReadPhy (pDevice, PHY_ID2_REG, &Value32);
+       pDevice->PhyId |= ((Value32 & PHY_ID2_OUI_MASK) << 16) |
+           (Value32 & PHY_ID2_MODEL_MASK) | (Value32 & PHY_ID2_REV_MASK);

 
 

-    /* Set the EnableTbi flag to false if we have a copper PHY. */
-    switch(pDevice->PhyId & PHY_ID_MASK)
-    {
+       /* Set the EnableTbi flag to false if we have a copper PHY. */
+       switch (pDevice->PhyId & PHY_ID_MASK) {

        case PHY_BCM5400_PHY_ID:
        case PHY_BCM5400_PHY_ID:

-           pDevice->EnableTbi = FALSE;
-           break;
+               pDevice->EnableTbi = FALSE;
+               break;

 
        case PHY_BCM5401_PHY_ID:
 
        case PHY_BCM5401_PHY_ID:

-           pDevice->EnableTbi = FALSE;
-           break;
+               pDevice->EnableTbi = FALSE;
+               break;

 
        case PHY_BCM5411_PHY_ID:
 
        case PHY_BCM5411_PHY_ID:

-           pDevice->EnableTbi = FALSE;
-           break;
+               pDevice->EnableTbi = FALSE;
+               break;

 
        case PHY_BCM5701_PHY_ID:
 
        case PHY_BCM5701_PHY_ID:

-           pDevice->EnableTbi = FALSE;
-           break;
+               pDevice->EnableTbi = FALSE;
+               break;

 
        case PHY_BCM5703_PHY_ID:
 
        case PHY_BCM5703_PHY_ID:

-           pDevice->EnableTbi = FALSE;
-           break;
+               pDevice->EnableTbi = FALSE;
+               break;

 
        case PHY_BCM5704_PHY_ID:
 
        case PHY_BCM5704_PHY_ID:

-           pDevice->EnableTbi = FALSE;
-           break;
+               pDevice->EnableTbi = FALSE;
+               break;

 
        case PHY_BCM8002_PHY_ID:
 
        case PHY_BCM8002_PHY_ID:

-           pDevice->EnableTbi = TRUE;
-           break;
+               pDevice->EnableTbi = TRUE;
+               break;

 
        default:
 
 
        default:
 

-           if (pAdapterInfo)
-           {
-               pDevice->PhyId = pAdapterInfo->PhyId;
-               pDevice->EnableTbi = pAdapterInfo->Serdes;
-           }
-           else if (EeSigFound)
-           {
-               pDevice->PhyId = EePhyId;
-               pDevice->EnableTbi = EePhyTypeSerdes;
-           }
-           break;
-    }
-
-    /* Bail out if we don't know the copper PHY id. */
-    if(UNKNOWN_PHY_ID(pDevice->PhyId) && !pDevice->EnableTbi)
-    {
-       return LM_STATUS_FAILURE;
-    }
+               if (pAdapterInfo) {
+                       pDevice->PhyId = pAdapterInfo->PhyId;
+                       pDevice->EnableTbi = pAdapterInfo->Serdes;
+               } else if (EeSigFound) {
+                       pDevice->PhyId = EePhyId;
+                       pDevice->EnableTbi = EePhyTypeSerdes;
+               }
+               break;
+       }

 
 

-    if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
-    {
-       if((pDevice->SavedCacheLineReg & 0xff00) < 0x4000)
-       {
-           pDevice->SavedCacheLineReg &= 0xffff00ff;
-           pDevice->SavedCacheLineReg |= 0x4000;
-       }
-    }
-    /* Change driver parameters. */
-    Status = MM_GetConfig(pDevice);
-    if(Status != LM_STATUS_SUCCESS)
-    {
-       return Status;
-    }
+       /* Bail out if we don't know the copper PHY id. */
+       if (UNKNOWN_PHY_ID (pDevice->PhyId) && !pDevice->EnableTbi) {
+               return LM_STATUS_FAILURE;
+       }

 
 

+       if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5703) {
+               if ((pDevice->SavedCacheLineReg & 0xff00) < 0x4000) {
+                       pDevice->SavedCacheLineReg &= 0xffff00ff;
+                       pDevice->SavedCacheLineReg |= 0x4000;
+               }
+       }
+       /* Change driver parameters. */
+       Status = MM_GetConfig (pDevice);
+       if (Status != LM_STATUS_SUCCESS) {
+               return Status;
+       }

 #if INCLUDE_5701_AX_FIX
 #if INCLUDE_5701_AX_FIX

-    if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
-       pDevice->ChipRevId == T3_CHIP_ID_5701_B0)
-    {
-       pDevice->ResetPhyOnInit = TRUE;
-    }
+       if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
+           pDevice->ChipRevId == T3_CHIP_ID_5701_B0) {
+               pDevice->ResetPhyOnInit = TRUE;
+       }

 #endif
 
 #endif
 

-    /* Save the current phy link status. */
-    if(!pDevice->EnableTbi)
-    {
-       LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
-       LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
-
-       /* If we don't have link reset the PHY. */
-       if(!(Value32 & PHY_STATUS_LINK_PASS) || pDevice->ResetPhyOnInit)
-       {
+       /* Save the current phy link status. */
+       if (!pDevice->EnableTbi) {
+               LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
+               LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);

 
 

-           LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET);
+               /* If we don't have link reset the PHY. */
+               if (!(Value32 & PHY_STATUS_LINK_PASS)
+                   || pDevice->ResetPhyOnInit) {

 
 

-           for(j = 0; j < 100; j++)
-           {
-               MM_Wait(10);
+                       LM_WritePhy (pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET);

 
 

-               LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
-               if(Value32 && !(Value32 & PHY_CTRL_PHY_RESET))
-               {
-                   MM_Wait(40);
-                   break;
-               }
-           }
+                       for (j = 0; j < 100; j++) {
+                               MM_Wait (10);

 
 

+                               LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32);
+                               if (Value32 && !(Value32 & PHY_CTRL_PHY_RESET)) {
+                                       MM_Wait (40);
+                                       break;
+                               }
+                       }

 
 #if INCLUDE_5701_AX_FIX
 
 #if INCLUDE_5701_AX_FIX

-           /* 5701_AX_BX bug:  only advertises 10mb speed. */
-           if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
-               pDevice->ChipRevId == T3_CHIP_ID_5701_B0)
-           {
-
-               Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD |
-                   PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL |
-                   PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF;
-               Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
-               LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
-               pDevice->advertising = Value32;
-
-               Value32 = BCM540X_AN_AD_1000BASET_HALF |
-                   BCM540X_AN_AD_1000BASET_FULL | BCM540X_CONFIG_AS_MASTER |
-                   BCM540X_ENABLE_CONFIG_AS_MASTER;
-               LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
-               pDevice->advertising1000 = Value32;
-
-               LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE |
-                   PHY_CTRL_RESTART_AUTO_NEG);
-           }
+                       /* 5701_AX_BX bug:  only advertises 10mb speed. */
+                       if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
+                           pDevice->ChipRevId == T3_CHIP_ID_5701_B0) {
+
+                               Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD |
+                                   PHY_AN_AD_10BASET_HALF |
+                                   PHY_AN_AD_10BASET_FULL |
+                                   PHY_AN_AD_100BASETX_FULL |
+                                   PHY_AN_AD_100BASETX_HALF;
+                               Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
+                               LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
+                               pDevice->advertising = Value32;
+
+                               Value32 = BCM540X_AN_AD_1000BASET_HALF |
+                                   BCM540X_AN_AD_1000BASET_FULL |
+                                   BCM540X_CONFIG_AS_MASTER |
+                                   BCM540X_ENABLE_CONFIG_AS_MASTER;
+                               LM_WritePhy (pDevice,
+                                            BCM540X_1000BASET_CTRL_REG,
+                                            Value32);
+                               pDevice->advertising1000 = Value32;
+
+                               LM_WritePhy (pDevice, PHY_CTRL_REG,
+                                            PHY_CTRL_AUTO_NEG_ENABLE |
+                                            PHY_CTRL_RESTART_AUTO_NEG);
+                       }

 #endif
 #endif

-           if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
-           {
-               LM_WritePhy(pDevice, 0x18, 0x0c00);
-               LM_WritePhy(pDevice, 0x17, 0x201f);
-               LM_WritePhy(pDevice, 0x15, 0x2aaa);
-           }
-           if(pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
-           {
-               LM_WritePhy(pDevice, 0x1c, 0x8d68);
-               LM_WritePhy(pDevice, 0x1c, 0x8d68);
-           }
-           /* Enable Ethernet@WireSpeed. */
-           if(pDevice->EnableWireSpeed)
-           {
-               LM_WritePhy(pDevice, 0x18, 0x7007);
-               LM_ReadPhy(pDevice, 0x18, &Value32);
-               LM_WritePhy(pDevice, 0x18, Value32 | BIT_15 | BIT_4);
-           }
-       }
-    }
-
-    /* Turn off tap power management. */
-    if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
-    {
-       LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x0c20);
-       LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012);
-       LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804);
-       LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013);
-       LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204);
-       LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
-       LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132);
-       LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
-       LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232);
-       LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f);
-       LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20);
-
-       MM_Wait(40);
-    }
+                       if (T3_ASIC_REV (pDevice->ChipRevId) ==
+                           T3_ASIC_REV_5703) {
+                               LM_WritePhy (pDevice, 0x18, 0x0c00);
+                               LM_WritePhy (pDevice, 0x17, 0x201f);
+                               LM_WritePhy (pDevice, 0x15, 0x2aaa);
+                       }
+                       if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
+                               LM_WritePhy (pDevice, 0x1c, 0x8d68);
+                               LM_WritePhy (pDevice, 0x1c, 0x8d68);
+                       }
+                       /* Enable Ethernet@WireSpeed. */
+                       if (pDevice->EnableWireSpeed) {
+                               LM_WritePhy (pDevice, 0x18, 0x7007);
+                               LM_ReadPhy (pDevice, 0x18, &Value32);
+                               LM_WritePhy (pDevice, 0x18,
+                                            Value32 | BIT_15 | BIT_4);
+                       }
+               }
+       }

 
 

-#if INCLUDE_TBI_SUPPORT
-    pDevice->IgnoreTbiLinkChange = FALSE;
-
-    if(pDevice->EnableTbi)
-    {
-       pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_NONE;
-       pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
-       if ((pDevice->PollTbiLink == BAD_DEFAULT_VALUE) ||
-           pDevice->DisableAutoNeg)
-       {
-           pDevice->PollTbiLink = FALSE;
-       }
-    }
-    else
-    {
-       pDevice->PollTbiLink = FALSE;
-    }
-#endif /* INCLUDE_TBI_SUPPORT */
-
-    /* UseTaggedStatus is only valid for 5701 and later. */
-    if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
-    {
-       pDevice->UseTaggedStatus = FALSE;
+       /* Turn off tap power management. */
+       if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) {
+               LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x0c20);
+               LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012);
+               LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1804);
+               LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013);
+               LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1204);
+               LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
+               LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0132);
+               LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
+               LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0232);
+               LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f);
+               LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0a20);

 
 

-       pDevice->CoalesceMode = 0;
-    }
-    else
-    {
-       pDevice->CoalesceMode = HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT |
-           HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT;
-    }
-
-    /* Set the status block size. */
-    if(T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_AX &&
-       T3_CHIP_REV(pDevice->ChipRevId) != T3_CHIP_REV_5700_BX)
-    {
-       pDevice->CoalesceMode |= HOST_COALESCE_32_BYTE_STATUS_MODE;
-    }
-
-    /* Check the DURING_INT coalescing ticks parameters. */
-    if(pDevice->UseTaggedStatus)
-    {
-       if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
-       {
-           pDevice->RxCoalescingTicksDuringInt =
-               DEFAULT_RX_COALESCING_TICKS_DURING_INT;
+               MM_Wait (40);

        }
        }

-
-       if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
-       {
-           pDevice->TxCoalescingTicksDuringInt =
-               DEFAULT_TX_COALESCING_TICKS_DURING_INT;
+#if INCLUDE_TBI_SUPPORT
+       pDevice->IgnoreTbiLinkChange = FALSE;
+
+       if (pDevice->EnableTbi) {
+               pDevice->WakeUpModeCap = LM_WAKE_UP_MODE_NONE;
+               pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
+               if ((pDevice->PollTbiLink == BAD_DEFAULT_VALUE) ||
+                   pDevice->DisableAutoNeg) {
+                       pDevice->PollTbiLink = FALSE;
+               }
+       } else {
+               pDevice->PollTbiLink = FALSE;

        }
        }

+#endif                         /* INCLUDE_TBI_SUPPORT */

 
 

-       if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
-       {
-           pDevice->RxMaxCoalescedFramesDuringInt =
-               DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT;
-       }
+       /* UseTaggedStatus is only valid for 5701 and later. */
+       if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+               pDevice->UseTaggedStatus = FALSE;

 
 

-       if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
-       {
-           pDevice->TxMaxCoalescedFramesDuringInt =
-               DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT;
-       }
-    }
-    else
-    {
-       if(pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
-       {
-           pDevice->RxCoalescingTicksDuringInt = 0;
+               pDevice->CoalesceMode = 0;
+       } else {
+               pDevice->CoalesceMode =
+                   HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT |
+                   HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT;

        }
 
        }
 

-       if(pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE)
-       {
-           pDevice->TxCoalescingTicksDuringInt = 0;
+       /* Set the status block size. */
+       if (T3_CHIP_REV (pDevice->ChipRevId) != T3_CHIP_REV_5700_AX &&
+           T3_CHIP_REV (pDevice->ChipRevId) != T3_CHIP_REV_5700_BX) {
+               pDevice->CoalesceMode |= HOST_COALESCE_32_BYTE_STATUS_MODE;

        }
 
        }
 

-       if(pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
-       {
-           pDevice->RxMaxCoalescedFramesDuringInt = 0;
-       }
+       /* Check the DURING_INT coalescing ticks parameters. */
+       if (pDevice->UseTaggedStatus) {
+               if (pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) {
+                       pDevice->RxCoalescingTicksDuringInt =
+                           DEFAULT_RX_COALESCING_TICKS_DURING_INT;
+               }

 
 

-       if(pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE)
-       {
-           pDevice->TxMaxCoalescedFramesDuringInt = 0;
-       }
-    }
+               if (pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) {
+                       pDevice->TxCoalescingTicksDuringInt =
+                           DEFAULT_TX_COALESCING_TICKS_DURING_INT;
+               }

 
 

-#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
-    if(pDevice->RxMtu <= (MAX_STD_RCV_BUFFER_SIZE - 8 /* CRC */))
-    {
-       pDevice->RxJumboDescCnt = 0;
-       if(pDevice->RxMtu <= MAX_ETHERNET_PACKET_SIZE_NO_CRC)
-       {
-           pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
-       }
-    }
-    else
-    {
-       pDevice->RxJumboBufferSize = (pDevice->RxMtu + 8 /* CRC + VLAN */ +
-           COMMON_CACHE_LINE_SIZE-1) & ~COMMON_CACHE_LINE_MASK;
+               if (pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) {
+                       pDevice->RxMaxCoalescedFramesDuringInt =
+                           DEFAULT_RX_MAX_COALESCED_FRAMES_DURING_INT;
+               }

 
 

-       if(pDevice->RxJumboBufferSize > MAX_JUMBO_RCV_BUFFER_SIZE)
-       {
-           pDevice->RxJumboBufferSize = DEFAULT_JUMBO_RCV_BUFFER_SIZE;
-           pDevice->RxMtu = pDevice->RxJumboBufferSize - 8 /* CRC + VLAN */;
-       }
-       pDevice->TxMtu = pDevice->RxMtu;
+               if (pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) {
+                       pDevice->TxMaxCoalescedFramesDuringInt =
+                           DEFAULT_TX_MAX_COALESCED_FRAMES_DURING_INT;
+               }
+       } else {
+               if (pDevice->RxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) {
+                       pDevice->RxCoalescingTicksDuringInt = 0;
+               }

 
 

-    }
-#else
-    pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+               if (pDevice->TxCoalescingTicksDuringInt == BAD_DEFAULT_VALUE) {
+                       pDevice->TxCoalescingTicksDuringInt = 0;
+               }
+
+               if (pDevice->RxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) {
+                       pDevice->RxMaxCoalescedFramesDuringInt = 0;
+               }
+
+               if (pDevice->TxMaxCoalescedFramesDuringInt == BAD_DEFAULT_VALUE) {
+                       pDevice->TxMaxCoalescedFramesDuringInt = 0;
+               }
+       }

 
 

-    pDevice->RxPacketDescCnt =

 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT

-       pDevice->RxJumboDescCnt +
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-       pDevice->RxStdDescCnt;
+       if (pDevice->RxMtu <= (MAX_STD_RCV_BUFFER_SIZE - 8 /* CRC */ )) {
+               pDevice->RxJumboDescCnt = 0;
+               if (pDevice->RxMtu <= MAX_ETHERNET_PACKET_SIZE_NO_CRC) {
+                       pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
+               }
+       } else {
+               pDevice->RxJumboBufferSize =
+                   (pDevice->RxMtu + 8 /* CRC + VLAN */  +
+                    COMMON_CACHE_LINE_SIZE - 1) & ~COMMON_CACHE_LINE_MASK;
+
+               if (pDevice->RxJumboBufferSize > MAX_JUMBO_RCV_BUFFER_SIZE) {
+                       pDevice->RxJumboBufferSize =
+                           DEFAULT_JUMBO_RCV_BUFFER_SIZE;
+                       pDevice->RxMtu =
+                           pDevice->RxJumboBufferSize - 8 /* CRC + VLAN */ ;
+               }
+               pDevice->TxMtu = pDevice->RxMtu;

 
 

-    if(pDevice->TxMtu < MAX_ETHERNET_PACKET_SIZE_NO_CRC)
-    {
-       pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
-    }
+       }
+#else
+       pDevice->RxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;
+#endif                         /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */

 
 

-    if(pDevice->TxMtu > MAX_JUMBO_TX_BUFFER_SIZE)
-    {
-       pDevice->TxMtu = MAX_JUMBO_TX_BUFFER_SIZE;
-    }
+       pDevice->RxPacketDescCnt =
+#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
+           pDevice->RxJumboDescCnt +
+#endif                         /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+           pDevice->RxStdDescCnt;

 
 

-    /* Configure the proper ways to get link change interrupt. */
-    if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO)
-    {
-       if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
-       {
-           pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
+       if (pDevice->TxMtu < MAX_ETHERNET_PACKET_SIZE_NO_CRC) {
+               pDevice->TxMtu = MAX_ETHERNET_PACKET_SIZE_NO_CRC;

        }
        }

-       else
-       {
-           pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
+
+       if (pDevice->TxMtu > MAX_JUMBO_TX_BUFFER_SIZE) {
+               pDevice->TxMtu = MAX_JUMBO_TX_BUFFER_SIZE;

        }
        }

-    }
-    else if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
-    {
-       /* Auto-polling does not work on 5700_AX and 5700_BX. */
-       if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
-       {
-           pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
+
+       /* Configure the proper ways to get link change interrupt. */
+       if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO) {
+               if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+                       pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
+               } else {
+                       pDevice->PhyIntMode = T3_PHY_INT_MODE_LINK_READY;
+               }
+       } else if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
+               /* Auto-polling does not work on 5700_AX and 5700_BX. */
+               if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+                       pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
+               }

        }
        }

-    }

 
 

-    /* Determine the method to get link change status. */
-    if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_AUTO)
-    {
-       /* The link status bit in the status block does not work on 5700_AX */
-       /* and 5700_BX chips. */
-       if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
-       {
-           pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
+       /* Determine the method to get link change status. */
+       if (pDevice->LinkChngMode == T3_LINK_CHNG_MODE_AUTO) {
+               /* The link status bit in the status block does not work on 5700_AX */
+               /* and 5700_BX chips. */
+               if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+                       pDevice->LinkChngMode =
+                           T3_LINK_CHNG_MODE_USE_STATUS_REG;
+               } else {
+                       pDevice->LinkChngMode =
+                           T3_LINK_CHNG_MODE_USE_STATUS_BLOCK;
+               }

        }
        }

-       else
-       {
-           pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_BLOCK;
+
+       if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT ||
+           T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+               pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;

        }
        }

-    }

 
 

-    if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT ||
-       T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
-    {
-       pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
-    }
+       /* Configure PHY led mode. */
+       if (pDevice->LedMode == LED_MODE_AUTO) {
+               if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+                   T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+                       if (pDevice->SubsystemVendorId == T3_SVID_DELL) {
+                               pDevice->LedMode = LED_MODE_LINK10;
+                       } else {
+                               pDevice->LedMode = LED_MODE_THREE_LINK;

 
 

-    /* Configure PHY led mode. */
-    if(pDevice->LedMode == LED_MODE_AUTO)
-    {
-       if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
-           T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
-       {
-           if(pDevice->SubsystemVendorId == T3_SVID_DELL)
-           {
-               pDevice->LedMode = LED_MODE_LINK10;
-           }
-           else
-           {
-               pDevice->LedMode = LED_MODE_THREE_LINK;
-
-               if(EeSigFound && EePhyLedMode != LED_MODE_AUTO)
-               {
-                   pDevice->LedMode = EePhyLedMode;
-               }
-           }
-
-           /* bug? 5701 in LINK10 mode does not seem to work when */
-           /* PhyIntMode is LINK_READY. */
-           if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
+                               if (EeSigFound && EePhyLedMode != LED_MODE_AUTO) {
+                                       pDevice->LedMode = EePhyLedMode;
+                               }
+                       }
+
+                       /* bug? 5701 in LINK10 mode does not seem to work when */
+                       /* PhyIntMode is LINK_READY. */
+                       if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700
+                           &&

 #if INCLUDE_TBI_SUPPORT
 #if INCLUDE_TBI_SUPPORT

-               pDevice->EnableTbi == FALSE &&
+                           pDevice->EnableTbi == FALSE &&

 #endif
 #endif

-               pDevice->LedMode == LED_MODE_LINK10)
-           {
-               pDevice->PhyIntMode = T3_PHY_INT_MODE_MI_INTERRUPT;
-               pDevice->LinkChngMode = T3_LINK_CHNG_MODE_USE_STATUS_REG;
-           }
+                           pDevice->LedMode == LED_MODE_LINK10) {
+                               pDevice->PhyIntMode =
+                                   T3_PHY_INT_MODE_MI_INTERRUPT;
+                               pDevice->LinkChngMode =
+                                   T3_LINK_CHNG_MODE_USE_STATUS_REG;
+                       }
+
+                       if (pDevice->EnableTbi) {
+                               pDevice->LedMode = LED_MODE_THREE_LINK;
+                       }
+               } else {
+                       if (EeSigFound && EePhyLedMode != LED_MODE_AUTO) {
+                               pDevice->LedMode = EePhyLedMode;
+                       } else {
+                               pDevice->LedMode = LED_MODE_OPEN_DRAIN;
+                       }
+               }
+       }

 
 

-           if(pDevice->EnableTbi)
-           {
-               pDevice->LedMode = LED_MODE_THREE_LINK;
-           }
+       /* Enable OneDmaAtOnce. */
+       if (pDevice->OneDmaAtOnce == BAD_DEFAULT_VALUE) {
+               pDevice->OneDmaAtOnce = FALSE;

        }
        }

-       else
-       {
-           if(EeSigFound && EePhyLedMode != LED_MODE_AUTO)
-           {
-               pDevice->LedMode = EePhyLedMode;
-           }
-           else
-           {
-               pDevice->LedMode = LED_MODE_OPEN_DRAIN;
-           }
-       }
-    }
-
-    /* Enable OneDmaAtOnce. */
-    if(pDevice->OneDmaAtOnce == BAD_DEFAULT_VALUE)
-    {
-       pDevice->OneDmaAtOnce = FALSE;
-    }
-
-    if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
-       pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
-       pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
-       pDevice->ChipRevId == T3_CHIP_ID_5701_B2)
-    {
-       pDevice->WolSpeed = WOL_SPEED_10MB;
-    }
-    else
-    {
-       pDevice->WolSpeed = WOL_SPEED_100MB;
-    }
-
-    /* Offloadings. */
-    pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
-
-    /* Turn off task offloading on Ax. */
-    if(pDevice->ChipRevId == T3_CHIP_ID_5700_B0)
-    {
-       pDevice->TaskOffloadCap &= ~(LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
-           LM_TASK_OFFLOAD_TX_UDP_CHECKSUM);
-    }
-    pDevice->PciState = REG_RD(pDevice, PciCfg.PciState);
-    LM_ReadVPD(pDevice);
-    LM_ReadBootCodeVersion(pDevice);
-    LM_GetBusSpeed(pDevice);
-
-    return LM_STATUS_SUCCESS;
-} /* LM_GetAdapterInfo */
-
-STATIC PLM_ADAPTER_INFO
-LM_GetAdapterInfoBySsid(
-    LM_UINT16 Svid,
-    LM_UINT16 Ssid)
+
+       if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+           pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
+           pDevice->ChipRevId == T3_CHIP_ID_5701_B0 ||
+           pDevice->ChipRevId == T3_CHIP_ID_5701_B2) {
+               pDevice->WolSpeed = WOL_SPEED_10MB;
+       } else {
+               pDevice->WolSpeed = WOL_SPEED_100MB;
+       }
+
+       /* Offloadings. */
+       pDevice->TaskToOffload = LM_TASK_OFFLOAD_NONE;
+
+       /* Turn off task offloading on Ax. */
+       if (pDevice->ChipRevId == T3_CHIP_ID_5700_B0) {
+               pDevice->TaskOffloadCap &= ~(LM_TASK_OFFLOAD_TX_TCP_CHECKSUM |
+                                            LM_TASK_OFFLOAD_TX_UDP_CHECKSUM);
+       }
+       pDevice->PciState = REG_RD (pDevice, PciCfg.PciState);
+       LM_ReadVPD (pDevice);
+       LM_ReadBootCodeVersion (pDevice);
+       LM_GetBusSpeed (pDevice);
+
+       return LM_STATUS_SUCCESS;
+}                              /* LM_GetAdapterInfo */
+
+STATIC PLM_ADAPTER_INFO LM_GetAdapterInfoBySsid (LM_UINT16 Svid, LM_UINT16 Ssid)

 {
 {

-    static LM_ADAPTER_INFO AdapterArr[] =
-    {
-       { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A6, PHY_BCM5401_PHY_ID, 0},
-       { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A5, PHY_BCM5701_PHY_ID, 0},
-       { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700T6, PHY_BCM8002_PHY_ID, 1},
-       { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A9, 0, 1 },
-       { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T1, PHY_BCM5701_PHY_ID, 0},
-       { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T8, PHY_BCM5701_PHY_ID, 0},
-       { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A7, 0, 1},
-       { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A10, PHY_BCM5701_PHY_ID, 0},
-       { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A12, PHY_BCM5701_PHY_ID, 0},
-       { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax1, PHY_BCM5701_PHY_ID, 0},
-       { T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax2, PHY_BCM5701_PHY_ID, 0},
-
-       { T3_SVID_3COM, T3_SSID_3COM_3C996T, PHY_BCM5401_PHY_ID, 0 },
-       { T3_SVID_3COM, T3_SSID_3COM_3C996BT, PHY_BCM5701_PHY_ID, 0 },
-       { T3_SVID_3COM, T3_SSID_3COM_3C996SX, 0, 1 },
-       { T3_SVID_3COM, T3_SSID_3COM_3C1000T, PHY_BCM5701_PHY_ID, 0 },
-       { T3_SVID_3COM, T3_SSID_3COM_3C940BR01, PHY_BCM5701_PHY_ID, 0 },
-
-       { T3_SVID_DELL, T3_SSID_DELL_VIPER, PHY_BCM5401_PHY_ID, 0 },
-       { T3_SVID_DELL, T3_SSID_DELL_JAGUAR, PHY_BCM5401_PHY_ID, 0 },
-       { T3_SVID_DELL, T3_SSID_DELL_MERLOT, PHY_BCM5411_PHY_ID, 0 },
-       { T3_SVID_DELL, T3_SSID_DELL_SLIM_MERLOT, PHY_BCM5411_PHY_ID, 0 },
-
-       { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE, PHY_BCM5701_PHY_ID, 0 },
-       { T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE_2, PHY_BCM5701_PHY_ID, 0 },
-       { T3_SVID_COMPAQ, T3_SSID_COMPAQ_CHANGELING, 0, 1 },
-       { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780, PHY_BCM5701_PHY_ID, 0 },
-       { T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780_2, PHY_BCM5701_PHY_ID, 0 },
-
-    };
-    LM_UINT32 j;
-
-    for(j = 0; j < sizeof(AdapterArr)/sizeof(LM_ADAPTER_INFO); j++)
-    {
-       if(AdapterArr[j].Svid == Svid && AdapterArr[j].Ssid == Ssid)
-       {
-           return &AdapterArr[j];
+       static LM_ADAPTER_INFO AdapterArr[] = {
+               {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A6,
+                PHY_BCM5401_PHY_ID, 0},
+               {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A5,
+                PHY_BCM5701_PHY_ID, 0},
+               {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700T6,
+                PHY_BCM8002_PHY_ID, 1},
+               {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95700A9, 0, 1},
+               {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T1,
+                PHY_BCM5701_PHY_ID, 0},
+               {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701T8,
+                PHY_BCM5701_PHY_ID, 0},
+               {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A7, 0, 1},
+               {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A10,
+                PHY_BCM5701_PHY_ID, 0},
+               {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95701A12,
+                PHY_BCM5701_PHY_ID, 0},
+               {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax1,
+                PHY_BCM5701_PHY_ID, 0},
+               {T3_SVID_BROADCOM, T3_SSID_BROADCOM_BCM95703Ax2,
+                PHY_BCM5701_PHY_ID, 0},
+
+               {T3_SVID_3COM, T3_SSID_3COM_3C996T, PHY_BCM5401_PHY_ID, 0},
+               {T3_SVID_3COM, T3_SSID_3COM_3C996BT, PHY_BCM5701_PHY_ID, 0},
+               {T3_SVID_3COM, T3_SSID_3COM_3C996SX, 0, 1},
+               {T3_SVID_3COM, T3_SSID_3COM_3C1000T, PHY_BCM5701_PHY_ID, 0},
+               {T3_SVID_3COM, T3_SSID_3COM_3C940BR01, PHY_BCM5701_PHY_ID, 0},
+
+               {T3_SVID_DELL, T3_SSID_DELL_VIPER, PHY_BCM5401_PHY_ID, 0},
+               {T3_SVID_DELL, T3_SSID_DELL_JAGUAR, PHY_BCM5401_PHY_ID, 0},
+               {T3_SVID_DELL, T3_SSID_DELL_MERLOT, PHY_BCM5411_PHY_ID, 0},
+               {T3_SVID_DELL, T3_SSID_DELL_SLIM_MERLOT, PHY_BCM5411_PHY_ID, 0},
+
+               {T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE, PHY_BCM5701_PHY_ID, 0},
+               {T3_SVID_COMPAQ, T3_SSID_COMPAQ_BANSHEE_2, PHY_BCM5701_PHY_ID,
+                0},
+               {T3_SVID_COMPAQ, T3_SSID_COMPAQ_CHANGELING, 0, 1},
+               {T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780, PHY_BCM5701_PHY_ID, 0},
+               {T3_SVID_COMPAQ, T3_SSID_COMPAQ_NC7780_2, PHY_BCM5701_PHY_ID,
+                0},
+
+       };
+       LM_UINT32 j;
+
+       for (j = 0; j < sizeof (AdapterArr) / sizeof (LM_ADAPTER_INFO); j++) {
+               if (AdapterArr[j].Svid == Svid && AdapterArr[j].Ssid == Ssid) {
+                       return &AdapterArr[j];
+               }

        }
        }

-    }

 
 

-    return NULL;
+       return NULL;

 }
 
 }
 

-

 /******************************************************************************/
 /* Description:                                                               */
 /*    This routine sets up receive/transmit buffer descriptions queues.       */
 /******************************************************************************/
 /* Description:                                                               */
 /*    This routine sets up receive/transmit buffer descriptions queues.       */


@@ -1638,237 +1489,226 @@ LM_GetAdapterInfoBySsid(
 /* Return:                                                                    */
 /*    LM_STATUS_SUCCESS                                                       */
 /******************************************************************************/
 /* Return:                                                                    */
 /*    LM_STATUS_SUCCESS                                                       */
 /******************************************************************************/

-LM_STATUS
-LM_InitializeAdapter(
-PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_InitializeAdapter (PLM_DEVICE_BLOCK pDevice)

 {
 {

-    LM_PHYSICAL_ADDRESS MemPhy;
-    PLM_UINT8 pMemVirt;
-    PLM_PACKET pPacket;
-    LM_STATUS Status;
-    LM_UINT32 Size;
-    LM_UINT32 j;
-
-    /* Set power state to D0. */
-    LM_SetPowerState(pDevice, LM_POWER_STATE_D0);
-
-    /* Intialize the queues. */
-    QQ_InitQueue(&pDevice->RxPacketReceivedQ.Container,
-       MAX_RX_PACKET_DESC_COUNT);
-    QQ_InitQueue(&pDevice->RxPacketFreeQ.Container,
-       MAX_RX_PACKET_DESC_COUNT);
-
-    QQ_InitQueue(&pDevice->TxPacketFreeQ.Container,MAX_TX_PACKET_DESC_COUNT);
-    QQ_InitQueue(&pDevice->TxPacketActiveQ.Container,MAX_TX_PACKET_DESC_COUNT);
-    QQ_InitQueue(&pDevice->TxPacketXmittedQ.Container,MAX_TX_PACKET_DESC_COUNT);
-
-    /* Allocate shared memory for: status block, the buffers for receive */
-    /* rings -- standard, mini, jumbo, and return rings. */
-    Size = T3_STATUS_BLOCK_SIZE + sizeof(T3_STATS_BLOCK) +
-       T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) +
+       LM_PHYSICAL_ADDRESS MemPhy;
+       PLM_UINT8 pMemVirt;
+       PLM_PACKET pPacket;
+       LM_STATUS Status;
+       LM_UINT32 Size;
+       LM_UINT32 j;
+
+       /* Set power state to D0. */
+       LM_SetPowerState (pDevice, LM_POWER_STATE_D0);
+
+       /* Intialize the queues. */
+       QQ_InitQueue (&pDevice->RxPacketReceivedQ.Container,
+                     MAX_RX_PACKET_DESC_COUNT);
+       QQ_InitQueue (&pDevice->RxPacketFreeQ.Container,
+                     MAX_RX_PACKET_DESC_COUNT);
+
+       QQ_InitQueue (&pDevice->TxPacketFreeQ.Container,
+                     MAX_TX_PACKET_DESC_COUNT);
+       QQ_InitQueue (&pDevice->TxPacketActiveQ.Container,
+                     MAX_TX_PACKET_DESC_COUNT);
+       QQ_InitQueue (&pDevice->TxPacketXmittedQ.Container,
+                     MAX_TX_PACKET_DESC_COUNT);
+
+       /* Allocate shared memory for: status block, the buffers for receive */
+       /* rings -- standard, mini, jumbo, and return rings. */
+       Size = T3_STATUS_BLOCK_SIZE + sizeof (T3_STATS_BLOCK) +
+           T3_STD_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD) +

 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT

-       T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD) +
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-       T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD);
-
-    /* Memory for host based Send BD. */
-    if(pDevice->NicSendBd == FALSE)
-    {
-       Size += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
-    }
-
-    /* Allocate the memory block. */
-    Status = MM_AllocateSharedMemory(pDevice, Size, (PLM_VOID) &pMemVirt, &MemPhy, FALSE);
-    if(Status != LM_STATUS_SUCCESS)
-    {
-       return Status;
-    }
-
-    /* Program DMA Read/Write */
-    if (pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS)
-    {
-       pDevice->DmaReadWriteCtrl = 0x763f000f;
-    }
-    else
-    {
-       if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5704)
-       {
-           pDevice->DmaReadWriteCtrl = 0x761f0000;
+           T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD) +
+#endif                         /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+           T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD);
+
+       /* Memory for host based Send BD. */
+       if (pDevice->NicSendBd == FALSE) {
+               Size += sizeof (T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
+       }
+
+       /* Allocate the memory block. */
+       Status =
+           MM_AllocateSharedMemory (pDevice, Size, (PLM_VOID) & pMemVirt,
+                                    &MemPhy, FALSE);
+       if (Status != LM_STATUS_SUCCESS) {
+               return Status;
+       }
+
+       /* Program DMA Read/Write */
+       if (pDevice->PciState & T3_PCI_STATE_NOT_PCI_X_BUS) {
+               pDevice->DmaReadWriteCtrl = 0x763f000f;
+       } else {
+               if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5704) {
+                       pDevice->DmaReadWriteCtrl = 0x761f0000;
+               } else {
+                       pDevice->DmaReadWriteCtrl = 0x761b000f;
+               }
+               if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1 ||
+                   pDevice->ChipRevId == T3_CHIP_ID_5703_A2) {
+                       pDevice->OneDmaAtOnce = TRUE;
+               }

        }
        }

-       else
-       {
-           pDevice->DmaReadWriteCtrl = 0x761b000f;
+       if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5703) {
+               pDevice->DmaReadWriteCtrl &= 0xfffffff0;
+       }
+
+       if (pDevice->OneDmaAtOnce) {
+               pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_ONE_DMA_AT_ONCE;
+       }
+       REG_WR (pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);
+
+       if (LM_DmaTest (pDevice, pMemVirt, MemPhy, 0x400) != LM_STATUS_SUCCESS) {
+               return LM_STATUS_FAILURE;

        }
        }

-       if(pDevice->ChipRevId == T3_CHIP_ID_5703_A1 ||
-           pDevice->ChipRevId == T3_CHIP_ID_5703_A2)
-       {
-           pDevice->OneDmaAtOnce = TRUE;
-       }
-    }
-    if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5703)
-    {
-       pDevice->DmaReadWriteCtrl &= 0xfffffff0;
-    }
-
-    if(pDevice->OneDmaAtOnce)
-    {
-       pDevice->DmaReadWriteCtrl |= DMA_CTRL_WRITE_ONE_DMA_AT_ONCE;
-    }
-    REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);
-
-    if (LM_DmaTest(pDevice, pMemVirt, MemPhy, 0x400) != LM_STATUS_SUCCESS)
-    {
-       return LM_STATUS_FAILURE;
-    }

 
 

-    /* Status block. */
-    pDevice->pStatusBlkVirt = (PT3_STATUS_BLOCK) pMemVirt;
-    pDevice->StatusBlkPhy = MemPhy;
-    pMemVirt += T3_STATUS_BLOCK_SIZE;
-    LM_INC_PHYSICAL_ADDRESS(&MemPhy, T3_STATUS_BLOCK_SIZE);
+       /* Status block. */
+       pDevice->pStatusBlkVirt = (PT3_STATUS_BLOCK) pMemVirt;
+       pDevice->StatusBlkPhy = MemPhy;
+       pMemVirt += T3_STATUS_BLOCK_SIZE;
+       LM_INC_PHYSICAL_ADDRESS (&MemPhy, T3_STATUS_BLOCK_SIZE);

 
 

-    /* Statistics block. */
-    pDevice->pStatsBlkVirt = (PT3_STATS_BLOCK) pMemVirt;
-    pDevice->StatsBlkPhy = MemPhy;
-    pMemVirt += sizeof(T3_STATS_BLOCK);
-    LM_INC_PHYSICAL_ADDRESS(&MemPhy, sizeof(T3_STATS_BLOCK));
+       /* Statistics block. */
+       pDevice->pStatsBlkVirt = (PT3_STATS_BLOCK) pMemVirt;
+       pDevice->StatsBlkPhy = MemPhy;
+       pMemVirt += sizeof (T3_STATS_BLOCK);
+       LM_INC_PHYSICAL_ADDRESS (&MemPhy, sizeof (T3_STATS_BLOCK));

 
 

-    /* Receive standard BD buffer. */
-    pDevice->pRxStdBdVirt = (PT3_RCV_BD) pMemVirt;
-    pDevice->RxStdBdPhy = MemPhy;
+       /* Receive standard BD buffer. */
+       pDevice->pRxStdBdVirt = (PT3_RCV_BD) pMemVirt;
+       pDevice->RxStdBdPhy = MemPhy;

 
 

-    pMemVirt += T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD);
-    LM_INC_PHYSICAL_ADDRESS(&MemPhy,
-       T3_STD_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD));
+       pMemVirt += T3_STD_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD);
+       LM_INC_PHYSICAL_ADDRESS (&MemPhy,
+                                T3_STD_RCV_RCB_ENTRY_COUNT *
+                                sizeof (T3_RCV_BD));

 
 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
 
 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT

-    /* Receive jumbo BD buffer. */
-    pDevice->pRxJumboBdVirt = (PT3_RCV_BD) pMemVirt;
-    pDevice->RxJumboBdPhy = MemPhy;
-
-    pMemVirt += T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD);
-    LM_INC_PHYSICAL_ADDRESS(&MemPhy,
-       T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD));
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
-    /* Receive return BD buffer. */
-    pDevice->pRcvRetBdVirt = (PT3_RCV_BD) pMemVirt;
-    pDevice->RcvRetBdPhy = MemPhy;
-
-    pMemVirt += T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD);
-    LM_INC_PHYSICAL_ADDRESS(&MemPhy,
-       T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof(T3_RCV_BD));
-
-    /* Set up Send BD. */
-    if(pDevice->NicSendBd == FALSE)
-    {
-       pDevice->pSendBdVirt = (PT3_SND_BD) pMemVirt;
-       pDevice->SendBdPhy = MemPhy;
-
-       pMemVirt += sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
-       LM_INC_PHYSICAL_ADDRESS(&MemPhy,
-           sizeof(T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT);
-    }
-    else
-    {
-       pDevice->pSendBdVirt = (PT3_SND_BD)
-           pDevice->pMemView->uIntMem.First32k.BufferDesc;
-       pDevice->SendBdPhy.High = 0;
-       pDevice->SendBdPhy.Low = T3_NIC_SND_BUFFER_DESC_ADDR;
-    }
-
-    /* Allocate memory for packet descriptors. */
-    Size = (pDevice->RxPacketDescCnt +
-       pDevice->TxPacketDescCnt) * MM_PACKET_DESC_SIZE;
-    Status = MM_AllocateMemory(pDevice, Size, (PLM_VOID *) &pPacket);
-    if(Status != LM_STATUS_SUCCESS)
-    {
-       return Status;
-    }
-    pDevice->pPacketDescBase = (PLM_VOID) pPacket;
-
-    /* Create transmit packet descriptors from the memory block and add them */
-    /* to the TxPacketFreeQ for each send ring. */
-    for(j = 0; j < pDevice->TxPacketDescCnt; j++)
-    {
-       /* Ring index. */
-       pPacket->Flags = 0;
-
-       /* Queue the descriptor in the TxPacketFreeQ of the 'k' ring. */
-       QQ_PushTail(&pDevice->TxPacketFreeQ.Container, pPacket);
-
-       /* Get the pointer to the next descriptor.  MM_PACKET_DESC_SIZE */
-       /* is the total size of the packet descriptor including the */
-       /* os-specific extensions in the UM_PACKET structure. */
-       pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
-    } /* for(j.. */
-
-    /* Create receive packet descriptors from the memory block and add them */
-    /* to the RxPacketFreeQ.  Create the Standard packet descriptors. */
-    for(j = 0; j < pDevice->RxStdDescCnt; j++)
-    {
-       /* Receive producer ring. */
-       pPacket->u.Rx.RcvProdRing = T3_STD_RCV_PROD_RING;
-
-       /* Receive buffer size. */
-       pPacket->u.Rx.RxBufferSize = MAX_STD_RCV_BUFFER_SIZE;
-
-       /* Add the descriptor to RxPacketFreeQ. */
-       QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
-
-       /* Get the pointer to the next descriptor.  MM_PACKET_DESC_SIZE */
-       /* is the total size of the packet descriptor including the */
-       /* os-specific extensions in the UM_PACKET structure. */
-       pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
-    } /* for */
+       /* Receive jumbo BD buffer. */
+       pDevice->pRxJumboBdVirt = (PT3_RCV_BD) pMemVirt;
+       pDevice->RxJumboBdPhy = MemPhy;
+
+       pMemVirt += T3_JUMBO_RCV_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD);
+       LM_INC_PHYSICAL_ADDRESS (&MemPhy,
+                                T3_JUMBO_RCV_RCB_ENTRY_COUNT *
+                                sizeof (T3_RCV_BD));
+#endif                         /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+
+       /* Receive return BD buffer. */
+       pDevice->pRcvRetBdVirt = (PT3_RCV_BD) pMemVirt;
+       pDevice->RcvRetBdPhy = MemPhy;
+
+       pMemVirt += T3_RCV_RETURN_RCB_ENTRY_COUNT * sizeof (T3_RCV_BD);
+       LM_INC_PHYSICAL_ADDRESS (&MemPhy,
+                                T3_RCV_RETURN_RCB_ENTRY_COUNT *
+                                sizeof (T3_RCV_BD));
+
+       /* Set up Send BD. */
+       if (pDevice->NicSendBd == FALSE) {
+               pDevice->pSendBdVirt = (PT3_SND_BD) pMemVirt;
+               pDevice->SendBdPhy = MemPhy;
+
+               pMemVirt += sizeof (T3_SND_BD) * T3_SEND_RCB_ENTRY_COUNT;
+               LM_INC_PHYSICAL_ADDRESS (&MemPhy,
+                                        sizeof (T3_SND_BD) *
+                                        T3_SEND_RCB_ENTRY_COUNT);
+       } else {
+               pDevice->pSendBdVirt = (PT3_SND_BD)
+                   pDevice->pMemView->uIntMem.First32k.BufferDesc;
+               pDevice->SendBdPhy.High = 0;
+               pDevice->SendBdPhy.Low = T3_NIC_SND_BUFFER_DESC_ADDR;
+       }
+
+       /* Allocate memory for packet descriptors. */
+       Size = (pDevice->RxPacketDescCnt +
+               pDevice->TxPacketDescCnt) * MM_PACKET_DESC_SIZE;
+       Status = MM_AllocateMemory (pDevice, Size, (PLM_VOID *) & pPacket);
+       if (Status != LM_STATUS_SUCCESS) {
+               return Status;
+       }
+       pDevice->pPacketDescBase = (PLM_VOID) pPacket;
+
+       /* Create transmit packet descriptors from the memory block and add them */
+       /* to the TxPacketFreeQ for each send ring. */
+       for (j = 0; j < pDevice->TxPacketDescCnt; j++) {
+               /* Ring index. */
+               pPacket->Flags = 0;
+
+               /* Queue the descriptor in the TxPacketFreeQ of the 'k' ring. */
+               QQ_PushTail (&pDevice->TxPacketFreeQ.Container, pPacket);
+
+               /* Get the pointer to the next descriptor.  MM_PACKET_DESC_SIZE */
+               /* is the total size of the packet descriptor including the */
+               /* os-specific extensions in the UM_PACKET structure. */
+               pPacket =
+                   (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
+       }                       /* for(j.. */
+
+       /* Create receive packet descriptors from the memory block and add them */
+       /* to the RxPacketFreeQ.  Create the Standard packet descriptors. */
+       for (j = 0; j < pDevice->RxStdDescCnt; j++) {
+               /* Receive producer ring. */
+               pPacket->u.Rx.RcvProdRing = T3_STD_RCV_PROD_RING;
+
+               /* Receive buffer size. */
+               pPacket->u.Rx.RxBufferSize = MAX_STD_RCV_BUFFER_SIZE;
+
+               /* Add the descriptor to RxPacketFreeQ. */
+               QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
+
+               /* Get the pointer to the next descriptor.  MM_PACKET_DESC_SIZE */
+               /* is the total size of the packet descriptor including the */
+               /* os-specific extensions in the UM_PACKET structure. */
+               pPacket =
+                   (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
+       }                       /* for */

 
 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
 
 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT

-    /* Create the Jumbo packet descriptors. */
-    for(j = 0; j < pDevice->RxJumboDescCnt; j++)
-    {
-       /* Receive producer ring. */
-       pPacket->u.Rx.RcvProdRing = T3_JUMBO_RCV_PROD_RING;
-
-       /* Receive buffer size. */
-       pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize;
-
-       /* Add the descriptor to RxPacketFreeQ. */
-       QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
-
-       /* Get the pointer to the next descriptor.  MM_PACKET_DESC_SIZE */
-       /* is the total size of the packet descriptor including the */
-       /* os-specific extensions in the UM_PACKET structure. */
-       pPacket = (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
-    } /* for */
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
-
-    /* Initialize the rest of the packet descriptors. */
-    Status = MM_InitializeUmPackets(pDevice);
-    if(Status != LM_STATUS_SUCCESS)
-    {
-       return Status;
-    } /* if */
+       /* Create the Jumbo packet descriptors. */
+       for (j = 0; j < pDevice->RxJumboDescCnt; j++) {
+               /* Receive producer ring. */
+               pPacket->u.Rx.RcvProdRing = T3_JUMBO_RCV_PROD_RING;

 
 

-    /* Default receive mask. */
-    pDevice->ReceiveMask = LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST |
-       LM_ACCEPT_UNICAST;
+               /* Receive buffer size. */
+               pPacket->u.Rx.RxBufferSize = pDevice->RxJumboBufferSize;

 
 

-    /* Make sure we are in the first 32k memory window or NicSendBd. */
-    REG_WR(pDevice, PciCfg.MemWindowBaseAddr, 0);
+               /* Add the descriptor to RxPacketFreeQ. */
+               QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);

 
 

-    /* Initialize the hardware. */
-    Status = LM_ResetAdapter(pDevice);
-    if(Status != LM_STATUS_SUCCESS)
-    {
-       return Status;
-    }
+               /* Get the pointer to the next descriptor.  MM_PACKET_DESC_SIZE */
+               /* is the total size of the packet descriptor including the */
+               /* os-specific extensions in the UM_PACKET structure. */
+               pPacket =
+                   (PLM_PACKET) ((PLM_UINT8) pPacket + MM_PACKET_DESC_SIZE);
+       }                       /* for */
+#endif                         /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+
+       /* Initialize the rest of the packet descriptors. */
+       Status = MM_InitializeUmPackets (pDevice);
+       if (Status != LM_STATUS_SUCCESS) {
+               return Status;
+       }

 
 

-    /* We are done with initialization. */
-    pDevice->InitDone = TRUE;
+       /* if */
+       /* Default receive mask. */
+       pDevice->ReceiveMask = LM_ACCEPT_MULTICAST | LM_ACCEPT_BROADCAST |
+           LM_ACCEPT_UNICAST;

 
 

-    return LM_STATUS_SUCCESS;
-} /* LM_InitializeAdapter */
+       /* Make sure we are in the first 32k memory window or NicSendBd. */
+       REG_WR (pDevice, PciCfg.MemWindowBaseAddr, 0);

 
 

+       /* Initialize the hardware. */
+       Status = LM_ResetAdapter (pDevice);
+       if (Status != LM_STATUS_SUCCESS) {
+               return Status;
+       }
+
+       /* We are done with initialization. */
+       pDevice->InitDone = TRUE;
+
+       return LM_STATUS_SUCCESS;
+}                              /* LM_InitializeAdapter */

 
 /******************************************************************************/
 /* Description:                                                               */
 
 /******************************************************************************/
 /* Description:                                                               */


@@ -1878,414 +1718,408 @@ PLM_DEVICE_BLOCK pDevice)
 /*    LM_STATUS_SUCCESS                                                       */
 /******************************************************************************/
 LM_STATUS
 /*    LM_STATUS_SUCCESS                                                       */
 /******************************************************************************/
 LM_STATUS

-LM_CntrlBlock(
-PLM_DEVICE_BLOCK pDevice,
-LM_UINT32 mask,LM_UINT32 cntrl)
+LM_CntrlBlock (PLM_DEVICE_BLOCK pDevice, LM_UINT32 mask, LM_UINT32 cntrl)

 {
 {

-    LM_UINT32 j,i,data;
-    LM_UINT32 MaxWaitCnt;
-
-    MaxWaitCnt = 2;
-    j = 0;
-
-    for(i = 0 ; i < 32; i++)
-    {
-       if(!(mask & (1 << i)))
-           continue;
-
-       switch (1 << i)
-       {
-           case T3_BLOCK_DMA_RD:
-               data = REG_RD(pDevice, DmaRead.Mode);
-               if (cntrl == LM_DISABLE)
-               {
-                   data &= ~DMA_READ_MODE_ENABLE;
-                   REG_WR(pDevice, DmaRead.Mode, data);
-                   for(j = 0; j < MaxWaitCnt; j++)
-                   {
-                       if(!(REG_RD(pDevice, DmaRead.Mode) & DMA_READ_MODE_ENABLE))
-                           break;
-                       MM_Wait(10);
-                   }
-               }
-               else
-                   REG_WR(pDevice, DmaRead.Mode, data | DMA_READ_MODE_ENABLE);
-               break;
-
-           case T3_BLOCK_DMA_COMP:
-               data = REG_RD(pDevice,DmaComp.Mode);
-               if (cntrl == LM_DISABLE)
-               {
-                   data &= ~DMA_COMP_MODE_ENABLE;
-                   REG_WR(pDevice, DmaComp.Mode, data);
-                   for(j = 0; j < MaxWaitCnt; j++)
-                   {
-                       if(!(REG_RD(pDevice, DmaComp.Mode) & DMA_COMP_MODE_ENABLE))
-                           break;
-                       MM_Wait(10);
-                   }
-               }
-               else
-                   REG_WR(pDevice, DmaComp.Mode, data | DMA_COMP_MODE_ENABLE);
-               break;
+       LM_UINT32 j, i, data;
+       LM_UINT32 MaxWaitCnt;
+
+       MaxWaitCnt = 2;
+       j = 0;
+
+       for (i = 0; i < 32; i++) {
+               if (!(mask & (1 << i)))
+                       continue;
+
+               switch (1 << i) {
+               case T3_BLOCK_DMA_RD:
+                       data = REG_RD (pDevice, DmaRead.Mode);
+                       if (cntrl == LM_DISABLE) {
+                               data &= ~DMA_READ_MODE_ENABLE;
+                               REG_WR (pDevice, DmaRead.Mode, data);
+                               for (j = 0; j < MaxWaitCnt; j++) {
+                                       if (!
+                                           (REG_RD (pDevice, DmaRead.Mode) &
+                                            DMA_READ_MODE_ENABLE))
+                                               break;
+                                       MM_Wait (10);
+                               }
+                       } else
+                               REG_WR (pDevice, DmaRead.Mode,
+                                       data | DMA_READ_MODE_ENABLE);
+                       break;

 
 

-           case T3_BLOCK_RX_BD_INITIATOR:
-               data = REG_RD(pDevice, RcvBdIn.Mode);
-               if (cntrl == LM_DISABLE)
-               {
-                   data &= ~RCV_BD_IN_MODE_ENABLE;
-                   REG_WR(pDevice, RcvBdIn.Mode,data);
-                   for(j = 0; j < MaxWaitCnt; j++)
-                   {
-                       if(!(REG_RD(pDevice, RcvBdIn.Mode) & RCV_BD_IN_MODE_ENABLE))
-                           break;
-                       MM_Wait(10);
-                   }
-               }
-               else
-                   REG_WR(pDevice, RcvBdIn.Mode,data | RCV_BD_IN_MODE_ENABLE);
-               break;
+               case T3_BLOCK_DMA_COMP:
+                       data = REG_RD (pDevice, DmaComp.Mode);
+                       if (cntrl == LM_DISABLE) {
+                               data &= ~DMA_COMP_MODE_ENABLE;
+                               REG_WR (pDevice, DmaComp.Mode, data);
+                               for (j = 0; j < MaxWaitCnt; j++) {
+                                       if (!
+                                           (REG_RD (pDevice, DmaComp.Mode) &
+                                            DMA_COMP_MODE_ENABLE))
+                                               break;
+                                       MM_Wait (10);
+                               }
+                       } else
+                               REG_WR (pDevice, DmaComp.Mode,
+                                       data | DMA_COMP_MODE_ENABLE);
+                       break;

 
 

-           case T3_BLOCK_RX_BD_COMP:
-               data = REG_RD(pDevice, RcvBdComp.Mode);
-               if (cntrl == LM_DISABLE)
-               {
-                   data &= ~RCV_BD_COMP_MODE_ENABLE;
-                   REG_WR(pDevice, RcvBdComp.Mode,data);
-                   for(j = 0; j < MaxWaitCnt; j++)
-                   {
-                       if(!(REG_RD(pDevice, RcvBdComp.Mode) & RCV_BD_COMP_MODE_ENABLE))
-                           break;
-                       MM_Wait(10);
-                   }
-               }
-               else
-                   REG_WR(pDevice, RcvBdComp.Mode,data | RCV_BD_COMP_MODE_ENABLE);
-               break;
+               case T3_BLOCK_RX_BD_INITIATOR:
+                       data = REG_RD (pDevice, RcvBdIn.Mode);
+                       if (cntrl == LM_DISABLE) {
+                               data &= ~RCV_BD_IN_MODE_ENABLE;
+                               REG_WR (pDevice, RcvBdIn.Mode, data);
+                               for (j = 0; j < MaxWaitCnt; j++) {
+                                       if (!
+                                           (REG_RD (pDevice, RcvBdIn.Mode) &
+                                            RCV_BD_IN_MODE_ENABLE))
+                                               break;
+                                       MM_Wait (10);
+                               }
+                       } else
+                               REG_WR (pDevice, RcvBdIn.Mode,
+                                       data | RCV_BD_IN_MODE_ENABLE);
+                       break;

 
 

-           case T3_BLOCK_DMA_WR:
-               data = REG_RD(pDevice, DmaWrite.Mode);
-               if (cntrl == LM_DISABLE)
-               {
-                   data &= ~DMA_WRITE_MODE_ENABLE;
-                   REG_WR(pDevice, DmaWrite.Mode,data);
+               case T3_BLOCK_RX_BD_COMP:
+                       data = REG_RD (pDevice, RcvBdComp.Mode);
+                       if (cntrl == LM_DISABLE) {
+                               data &= ~RCV_BD_COMP_MODE_ENABLE;
+                               REG_WR (pDevice, RcvBdComp.Mode, data);
+                               for (j = 0; j < MaxWaitCnt; j++) {
+                                       if (!
+                                           (REG_RD (pDevice, RcvBdComp.Mode) &
+                                            RCV_BD_COMP_MODE_ENABLE))
+                                               break;
+                                       MM_Wait (10);
+                               }
+                       } else
+                               REG_WR (pDevice, RcvBdComp.Mode,
+                                       data | RCV_BD_COMP_MODE_ENABLE);
+                       break;

 
 

-                   for(j = 0; j < MaxWaitCnt; j++)
-                   {
-                       if(!(REG_RD(pDevice, DmaWrite.Mode) & DMA_WRITE_MODE_ENABLE))
-                           break;
-                       MM_Wait(10);
-                   }
-               }
-               else
-                   REG_WR(pDevice, DmaWrite.Mode,data | DMA_WRITE_MODE_ENABLE);
-               break;
+               case T3_BLOCK_DMA_WR:
+                       data = REG_RD (pDevice, DmaWrite.Mode);
+                       if (cntrl == LM_DISABLE) {
+                               data &= ~DMA_WRITE_MODE_ENABLE;
+                               REG_WR (pDevice, DmaWrite.Mode, data);
+
+                               for (j = 0; j < MaxWaitCnt; j++) {
+                                       if (!
+                                           (REG_RD (pDevice, DmaWrite.Mode) &
+                                            DMA_WRITE_MODE_ENABLE))
+                                               break;
+                                       MM_Wait (10);
+                               }
+                       } else
+                               REG_WR (pDevice, DmaWrite.Mode,
+                                       data | DMA_WRITE_MODE_ENABLE);
+                       break;

 
 

-           case T3_BLOCK_MSI_HANDLER:
-               data = REG_RD(pDevice, Msi.Mode);
-               if (cntrl == LM_DISABLE)
-               {
-                   data &= ~MSI_MODE_ENABLE;
-                   REG_WR(pDevice, Msi.Mode, data);
-                   for(j = 0; j < MaxWaitCnt; j++)
-                   {
-                       if(!(REG_RD(pDevice, Msi.Mode) & MSI_MODE_ENABLE))
-                           break;
-                       MM_Wait(10);
-                   }
-               }
-               else
-                   REG_WR(pDevice, Msi.Mode, data |MSI_MODE_ENABLE);
-               break;
+               case T3_BLOCK_MSI_HANDLER:
+                       data = REG_RD (pDevice, Msi.Mode);
+                       if (cntrl == LM_DISABLE) {
+                               data &= ~MSI_MODE_ENABLE;
+                               REG_WR (pDevice, Msi.Mode, data);
+                               for (j = 0; j < MaxWaitCnt; j++) {
+                                       if (!
+                                           (REG_RD (pDevice, Msi.Mode) &
+                                            MSI_MODE_ENABLE))
+                                               break;
+                                       MM_Wait (10);
+                               }
+                       } else
+                               REG_WR (pDevice, Msi.Mode,
+                                       data | MSI_MODE_ENABLE);
+                       break;

 
 

-           case T3_BLOCK_RX_LIST_PLMT:
-               data = REG_RD(pDevice, RcvListPlmt.Mode);
-               if (cntrl == LM_DISABLE)
-               {
-                   data &= ~RCV_LIST_PLMT_MODE_ENABLE;
-                   REG_WR(pDevice, RcvListPlmt.Mode,data);
-                   for(j = 0; j < MaxWaitCnt; j++)
-                   {
-                       if(!(REG_RD(pDevice, RcvListPlmt.Mode) & RCV_LIST_PLMT_MODE_ENABLE))
-                           break;
-                       MM_Wait(10);
-                   }
-               }
-               else
-                   REG_WR(pDevice, RcvListPlmt.Mode,data | RCV_LIST_PLMT_MODE_ENABLE);
-               break;
+               case T3_BLOCK_RX_LIST_PLMT:
+                       data = REG_RD (pDevice, RcvListPlmt.Mode);
+                       if (cntrl == LM_DISABLE) {
+                               data &= ~RCV_LIST_PLMT_MODE_ENABLE;
+                               REG_WR (pDevice, RcvListPlmt.Mode, data);
+                               for (j = 0; j < MaxWaitCnt; j++) {
+                                       if (!
+                                           (REG_RD (pDevice, RcvListPlmt.Mode)
+                                            & RCV_LIST_PLMT_MODE_ENABLE))
+                                               break;
+                                       MM_Wait (10);
+                               }
+                       } else
+                               REG_WR (pDevice, RcvListPlmt.Mode,
+                                       data | RCV_LIST_PLMT_MODE_ENABLE);
+                       break;

 
 

-           case T3_BLOCK_RX_LIST_SELECTOR:
-               data = REG_RD(pDevice, RcvListSel.Mode);
-               if (cntrl == LM_DISABLE)
-               {
-                   data &= ~RCV_LIST_SEL_MODE_ENABLE;
-                   REG_WR(pDevice, RcvListSel.Mode,data);
-                   for(j = 0; j < MaxWaitCnt; j++)
-                   {
-                       if(!(REG_RD(pDevice, RcvListSel.Mode) & RCV_LIST_SEL_MODE_ENABLE))
-                           break;
-                       MM_Wait(10);
-                   }
-               }
-               else
-                   REG_WR(pDevice, RcvListSel.Mode,data |RCV_LIST_SEL_MODE_ENABLE);
-               break;
+               case T3_BLOCK_RX_LIST_SELECTOR:
+                       data = REG_RD (pDevice, RcvListSel.Mode);
+                       if (cntrl == LM_DISABLE) {
+                               data &= ~RCV_LIST_SEL_MODE_ENABLE;
+                               REG_WR (pDevice, RcvListSel.Mode, data);
+                               for (j = 0; j < MaxWaitCnt; j++) {
+                                       if (!
+                                           (REG_RD (pDevice, RcvListSel.Mode) &
+                                            RCV_LIST_SEL_MODE_ENABLE))
+                                               break;
+                                       MM_Wait (10);
+                               }
+                       } else
+                               REG_WR (pDevice, RcvListSel.Mode,
+                                       data | RCV_LIST_SEL_MODE_ENABLE);
+                       break;

 
 

-           case T3_BLOCK_RX_DATA_INITIATOR:
-               data = REG_RD(pDevice, RcvDataBdIn.Mode);
-               if (cntrl == LM_DISABLE)
-               {
-                   data &= ~RCV_DATA_BD_IN_MODE_ENABLE;
-                   REG_WR(pDevice, RcvDataBdIn.Mode,data);
-                   for(j = 0; j < MaxWaitCnt; j++)
-                   {
-                       if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_BD_IN_MODE_ENABLE))
-                           break;
-                       MM_Wait(10);
-                   }
-               }
-               else
-                   REG_WR(pDevice, RcvDataBdIn.Mode, data | RCV_DATA_BD_IN_MODE_ENABLE);
-               break;
+               case T3_BLOCK_RX_DATA_INITIATOR:
+                       data = REG_RD (pDevice, RcvDataBdIn.Mode);
+                       if (cntrl == LM_DISABLE) {
+                               data &= ~RCV_DATA_BD_IN_MODE_ENABLE;
+                               REG_WR (pDevice, RcvDataBdIn.Mode, data);
+                               for (j = 0; j < MaxWaitCnt; j++) {
+                                       if (!
+                                           (REG_RD (pDevice, RcvDataBdIn.Mode)
+                                            & RCV_DATA_BD_IN_MODE_ENABLE))
+                                               break;
+                                       MM_Wait (10);
+                               }
+                       } else
+                               REG_WR (pDevice, RcvDataBdIn.Mode,
+                                       data | RCV_DATA_BD_IN_MODE_ENABLE);
+                       break;

 
 

-           case T3_BLOCK_RX_DATA_COMP:
-               data = REG_RD(pDevice, RcvDataComp.Mode);
-               if (cntrl == LM_DISABLE)
-               {
-                   data &= ~RCV_DATA_COMP_MODE_ENABLE;
-                   REG_WR(pDevice, RcvDataComp.Mode,data);
-                   for(j = 0; j < MaxWaitCnt; j++)
-                   {
-                       if(!(REG_RD(pDevice, RcvDataBdIn.Mode) & RCV_DATA_COMP_MODE_ENABLE))
-                           break;
-                       MM_Wait(10);
-                   }
-               }
-               else
-                   REG_WR(pDevice, RcvDataComp.Mode,data | RCV_DATA_COMP_MODE_ENABLE);
-               break;
+               case T3_BLOCK_RX_DATA_COMP:
+                       data = REG_RD (pDevice, RcvDataComp.Mode);
+                       if (cntrl == LM_DISABLE) {
+                               data &= ~RCV_DATA_COMP_MODE_ENABLE;
+                               REG_WR (pDevice, RcvDataComp.Mode, data);
+                               for (j = 0; j < MaxWaitCnt; j++) {
+                                       if (!
+                                           (REG_RD (pDevice, RcvDataBdIn.Mode)
+                                            & RCV_DATA_COMP_MODE_ENABLE))
+                                               break;
+                                       MM_Wait (10);
+                               }
+                       } else
+                               REG_WR (pDevice, RcvDataComp.Mode,
+                                       data | RCV_DATA_COMP_MODE_ENABLE);
+                       break;

 
 

-           case T3_BLOCK_HOST_COALESING:
-               data = REG_RD(pDevice, HostCoalesce.Mode);
-               if (cntrl == LM_DISABLE)
-               {
-                   data &= ~HOST_COALESCE_ENABLE;
-                   REG_WR(pDevice, HostCoalesce.Mode, data);
-                   for(j = 0; j < MaxWaitCnt; j++)
-                   {
-                       if(!(REG_RD(pDevice, SndBdIn.Mode) & HOST_COALESCE_ENABLE))
-                           break;
-                       MM_Wait(10);
-                   }
-               }
-               else
-                   REG_WR(pDevice, HostCoalesce.Mode, data | HOST_COALESCE_ENABLE);
-               break;
+               case T3_BLOCK_HOST_COALESING:
+                       data = REG_RD (pDevice, HostCoalesce.Mode);
+                       if (cntrl == LM_DISABLE) {
+                               data &= ~HOST_COALESCE_ENABLE;
+                               REG_WR (pDevice, HostCoalesce.Mode, data);
+                               for (j = 0; j < MaxWaitCnt; j++) {
+                                       if (!
+                                           (REG_RD (pDevice, SndBdIn.Mode) &
+                                            HOST_COALESCE_ENABLE))
+                                               break;
+                                       MM_Wait (10);
+                               }
+                       } else
+                               REG_WR (pDevice, HostCoalesce.Mode,
+                                       data | HOST_COALESCE_ENABLE);
+                       break;

 
 

-           case T3_BLOCK_MAC_RX_ENGINE:
-               if(cntrl == LM_DISABLE)
-               {
-                   pDevice->RxMode &= ~RX_MODE_ENABLE;
-                   REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
-                   for(j = 0; j < MaxWaitCnt; j++)
-                   {
-                       if(!(REG_RD(pDevice, MacCtrl.RxMode) & RX_MODE_ENABLE))
-                       {
-                           break;
+               case T3_BLOCK_MAC_RX_ENGINE:
+                       if (cntrl == LM_DISABLE) {
+                               pDevice->RxMode &= ~RX_MODE_ENABLE;
+                               REG_WR (pDevice, MacCtrl.RxMode,
+                                       pDevice->RxMode);
+                               for (j = 0; j < MaxWaitCnt; j++) {
+                                       if (!
+                                           (REG_RD (pDevice, MacCtrl.RxMode) &
+                                            RX_MODE_ENABLE)) {
+                                               break;
+                                       }
+                                       MM_Wait (10);
+                               }
+                       } else {
+                               pDevice->RxMode |= RX_MODE_ENABLE;
+                               REG_WR (pDevice, MacCtrl.RxMode,
+                                       pDevice->RxMode);

                        }
                        }

-                       MM_Wait(10);
-                   }
-               }
-               else
-               {
-                   pDevice->RxMode |= RX_MODE_ENABLE;
-                   REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
-               }
-               break;
+                       break;

 
 

-           case T3_BLOCK_MBUF_CLUSTER_FREE:
-               data = REG_RD(pDevice, MbufClusterFree.Mode);
-               if (cntrl == LM_DISABLE)
-               {
-                   data &= ~MBUF_CLUSTER_FREE_MODE_ENABLE;
-                   REG_WR(pDevice, MbufClusterFree.Mode,data);
-                   for(j = 0; j < MaxWaitCnt; j++)
-                   {
-                       if(!(REG_RD(pDevice, MbufClusterFree.Mode) & MBUF_CLUSTER_FREE_MODE_ENABLE))
-                           break;
-                       MM_Wait(10);
-                   }
-               }
-               else
-                   REG_WR(pDevice, MbufClusterFree.Mode, data | MBUF_CLUSTER_FREE_MODE_ENABLE);
-               break;
+               case T3_BLOCK_MBUF_CLUSTER_FREE:
+                       data = REG_RD (pDevice, MbufClusterFree.Mode);
+                       if (cntrl == LM_DISABLE) {
+                               data &= ~MBUF_CLUSTER_FREE_MODE_ENABLE;
+                               REG_WR (pDevice, MbufClusterFree.Mode, data);
+                               for (j = 0; j < MaxWaitCnt; j++) {
+                                       if (!
+                                           (REG_RD
+                                            (pDevice,
+                                             MbufClusterFree.
+                                             Mode) &
+                                            MBUF_CLUSTER_FREE_MODE_ENABLE))
+                                               break;
+                                       MM_Wait (10);
+                               }
+                       } else
+                               REG_WR (pDevice, MbufClusterFree.Mode,
+                                       data | MBUF_CLUSTER_FREE_MODE_ENABLE);
+                       break;

 
 

-           case T3_BLOCK_SEND_BD_INITIATOR:
-               data = REG_RD(pDevice, SndBdIn.Mode);
-               if (cntrl == LM_DISABLE)
-               {
-                   data &= ~SND_BD_IN_MODE_ENABLE;
-                   REG_WR(pDevice, SndBdIn.Mode, data);
-                   for(j = 0; j < MaxWaitCnt; j++)
-                   {
-                       if(!(REG_RD(pDevice, SndBdIn.Mode) & SND_BD_IN_MODE_ENABLE))
-                           break;
-                       MM_Wait(10);
-                   }
-               }
-               else
-                   REG_WR(pDevice, SndBdIn.Mode, data  | SND_BD_IN_MODE_ENABLE);
-               break;
+               case T3_BLOCK_SEND_BD_INITIATOR:
+                       data = REG_RD (pDevice, SndBdIn.Mode);
+                       if (cntrl == LM_DISABLE) {
+                               data &= ~SND_BD_IN_MODE_ENABLE;
+                               REG_WR (pDevice, SndBdIn.Mode, data);
+                               for (j = 0; j < MaxWaitCnt; j++) {
+                                       if (!
+                                           (REG_RD (pDevice, SndBdIn.Mode) &
+                                            SND_BD_IN_MODE_ENABLE))
+                                               break;
+                                       MM_Wait (10);
+                               }
+                       } else
+                               REG_WR (pDevice, SndBdIn.Mode,
+                                       data | SND_BD_IN_MODE_ENABLE);
+                       break;

 
 

-           case T3_BLOCK_SEND_BD_COMP:
-               data = REG_RD(pDevice, SndBdComp.Mode);
-               if (cntrl == LM_DISABLE)
-               {
-                   data &= ~SND_BD_COMP_MODE_ENABLE;
-                   REG_WR(pDevice, SndBdComp.Mode, data);
-                   for(j = 0; j < MaxWaitCnt; j++)
-                   {
-                       if(!(REG_RD(pDevice, SndBdComp.Mode) & SND_BD_COMP_MODE_ENABLE))
-                           break;
-                       MM_Wait(10);
-                   }
-               }
-               else
-                   REG_WR(pDevice, SndBdComp.Mode, data | SND_BD_COMP_MODE_ENABLE);
-               break;
+               case T3_BLOCK_SEND_BD_COMP:
+                       data = REG_RD (pDevice, SndBdComp.Mode);
+                       if (cntrl == LM_DISABLE) {
+                               data &= ~SND_BD_COMP_MODE_ENABLE;
+                               REG_WR (pDevice, SndBdComp.Mode, data);
+                               for (j = 0; j < MaxWaitCnt; j++) {
+                                       if (!
+                                           (REG_RD (pDevice, SndBdComp.Mode) &
+                                            SND_BD_COMP_MODE_ENABLE))
+                                               break;
+                                       MM_Wait (10);
+                               }
+                       } else
+                               REG_WR (pDevice, SndBdComp.Mode,
+                                       data | SND_BD_COMP_MODE_ENABLE);
+                       break;

 
 

-           case T3_BLOCK_SEND_BD_SELECTOR:
-               data = REG_RD(pDevice, SndBdSel.Mode);
-               if (cntrl == LM_DISABLE)
-               {
-                   data &= ~SND_BD_SEL_MODE_ENABLE;
-                   REG_WR(pDevice, SndBdSel.Mode, data);
-                   for(j = 0; j < MaxWaitCnt; j++)
-                   {
-                       if(!(REG_RD(pDevice, SndBdSel.Mode) & SND_BD_SEL_MODE_ENABLE))
-                           break;
-                       MM_Wait(10);
-                   }
-               }
-               else
-                   REG_WR(pDevice, SndBdSel.Mode, data | SND_BD_SEL_MODE_ENABLE);
-               break;
+               case T3_BLOCK_SEND_BD_SELECTOR:
+                       data = REG_RD (pDevice, SndBdSel.Mode);
+                       if (cntrl == LM_DISABLE) {
+                               data &= ~SND_BD_SEL_MODE_ENABLE;
+                               REG_WR (pDevice, SndBdSel.Mode, data);
+                               for (j = 0; j < MaxWaitCnt; j++) {
+                                       if (!
+                                           (REG_RD (pDevice, SndBdSel.Mode) &
+                                            SND_BD_SEL_MODE_ENABLE))
+                                               break;
+                                       MM_Wait (10);
+                               }
+                       } else
+                               REG_WR (pDevice, SndBdSel.Mode,
+                                       data | SND_BD_SEL_MODE_ENABLE);
+                       break;

 
 

-           case T3_BLOCK_SEND_DATA_INITIATOR:
-               data = REG_RD(pDevice, SndDataIn.Mode);
-               if (cntrl == LM_DISABLE)
-               {
-                   data &= ~T3_SND_DATA_IN_MODE_ENABLE;
-                   REG_WR(pDevice, SndDataIn.Mode,data);
-                   for(j = 0; j < MaxWaitCnt; j++)
-                   {
-                       if(!(REG_RD(pDevice, SndDataIn.Mode) & T3_SND_DATA_IN_MODE_ENABLE))
-                           break;
-                       MM_Wait(10);
-                   }
-               }
-               else
-                   REG_WR(pDevice, SndDataIn.Mode,data | T3_SND_DATA_IN_MODE_ENABLE);
-               break;
+               case T3_BLOCK_SEND_DATA_INITIATOR:
+                       data = REG_RD (pDevice, SndDataIn.Mode);
+                       if (cntrl == LM_DISABLE) {
+                               data &= ~T3_SND_DATA_IN_MODE_ENABLE;
+                               REG_WR (pDevice, SndDataIn.Mode, data);
+                               for (j = 0; j < MaxWaitCnt; j++) {
+                                       if (!
+                                           (REG_RD (pDevice, SndDataIn.Mode) &
+                                            T3_SND_DATA_IN_MODE_ENABLE))
+                                               break;
+                                       MM_Wait (10);
+                               }
+                       } else
+                               REG_WR (pDevice, SndDataIn.Mode,
+                                       data | T3_SND_DATA_IN_MODE_ENABLE);
+                       break;

 
 

-           case T3_BLOCK_SEND_DATA_COMP:
-               data = REG_RD(pDevice, SndDataComp.Mode);
-               if (cntrl == LM_DISABLE)
-               {
-                   data &= ~SND_DATA_COMP_MODE_ENABLE;
-                   REG_WR(pDevice, SndDataComp.Mode, data);
-                   for(j = 0; j < MaxWaitCnt; j++)
-                   {
-                       if(!(REG_RD(pDevice, SndDataComp.Mode) & SND_DATA_COMP_MODE_ENABLE))
-                           break;
-                       MM_Wait(10);
-                   }
-               }
-               else
-                   REG_WR(pDevice, SndDataComp.Mode,data | SND_DATA_COMP_MODE_ENABLE);
-               break;
+               case T3_BLOCK_SEND_DATA_COMP:
+                       data = REG_RD (pDevice, SndDataComp.Mode);
+                       if (cntrl == LM_DISABLE) {
+                               data &= ~SND_DATA_COMP_MODE_ENABLE;
+                               REG_WR (pDevice, SndDataComp.Mode, data);
+                               for (j = 0; j < MaxWaitCnt; j++) {
+                                       if (!
+                                           (REG_RD (pDevice, SndDataComp.Mode)
+                                            & SND_DATA_COMP_MODE_ENABLE))
+                                               break;
+                                       MM_Wait (10);
+                               }
+                       } else
+                               REG_WR (pDevice, SndDataComp.Mode,
+                                       data | SND_DATA_COMP_MODE_ENABLE);
+                       break;

 
 

-           case T3_BLOCK_MAC_TX_ENGINE:
-               if(cntrl == LM_DISABLE)
-               {
-                   pDevice->TxMode &= ~TX_MODE_ENABLE;
-                   REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
-                   for(j = 0; j < MaxWaitCnt; j++)
-                   {
-                       if(!(REG_RD(pDevice, MacCtrl.TxMode) & TX_MODE_ENABLE))
-                           break;
-                       MM_Wait(10);
-                   }
-               }
-               else
-               {
-                   pDevice->TxMode |= TX_MODE_ENABLE;
-                   REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
-               }
-               break;
+               case T3_BLOCK_MAC_TX_ENGINE:
+                       if (cntrl == LM_DISABLE) {
+                               pDevice->TxMode &= ~TX_MODE_ENABLE;
+                               REG_WR (pDevice, MacCtrl.TxMode,
+                                       pDevice->TxMode);
+                               for (j = 0; j < MaxWaitCnt; j++) {
+                                       if (!
+                                           (REG_RD (pDevice, MacCtrl.TxMode) &
+                                            TX_MODE_ENABLE))
+                                               break;
+                                       MM_Wait (10);
+                               }
+                       } else {
+                               pDevice->TxMode |= TX_MODE_ENABLE;
+                               REG_WR (pDevice, MacCtrl.TxMode,
+                                       pDevice->TxMode);
+                       }
+                       break;

 
 

-           case T3_BLOCK_MEM_ARBITOR:
-               data = REG_RD(pDevice, MemArbiter.Mode);
-               if (cntrl == LM_DISABLE)
-               {
-                   data &= ~T3_MEM_ARBITER_MODE_ENABLE;
-                   REG_WR(pDevice, MemArbiter.Mode, data);
-                   for(j = 0; j < MaxWaitCnt; j++)
-                   {
-                       if(!(REG_RD(pDevice, MemArbiter.Mode) & T3_MEM_ARBITER_MODE_ENABLE))
-                           break;
-                       MM_Wait(10);
-                   }
-               }
-               else
-                   REG_WR(pDevice, MemArbiter.Mode,data|T3_MEM_ARBITER_MODE_ENABLE);
-               break;
+               case T3_BLOCK_MEM_ARBITOR:
+                       data = REG_RD (pDevice, MemArbiter.Mode);
+                       if (cntrl == LM_DISABLE) {
+                               data &= ~T3_MEM_ARBITER_MODE_ENABLE;
+                               REG_WR (pDevice, MemArbiter.Mode, data);
+                               for (j = 0; j < MaxWaitCnt; j++) {
+                                       if (!
+                                           (REG_RD (pDevice, MemArbiter.Mode) &
+                                            T3_MEM_ARBITER_MODE_ENABLE))
+                                               break;
+                                       MM_Wait (10);
+                               }
+                       } else
+                               REG_WR (pDevice, MemArbiter.Mode,
+                                       data | T3_MEM_ARBITER_MODE_ENABLE);
+                       break;

 
 

-           case T3_BLOCK_MBUF_MANAGER:
-               data = REG_RD(pDevice, BufMgr.Mode);
-               if (cntrl == LM_DISABLE)
-               {
-                   data &= ~BUFMGR_MODE_ENABLE;
-                   REG_WR(pDevice, BufMgr.Mode,data);
-                   for(j = 0; j < MaxWaitCnt; j++)
-                   {
-                       if(!(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE))
-                           break;
-                       MM_Wait(10);
-                   }
-               }
-               else
-                   REG_WR(pDevice, BufMgr.Mode,data |  BUFMGR_MODE_ENABLE);
-               break;
+               case T3_BLOCK_MBUF_MANAGER:
+                       data = REG_RD (pDevice, BufMgr.Mode);
+                       if (cntrl == LM_DISABLE) {
+                               data &= ~BUFMGR_MODE_ENABLE;
+                               REG_WR (pDevice, BufMgr.Mode, data);
+                               for (j = 0; j < MaxWaitCnt; j++) {
+                                       if (!
+                                           (REG_RD (pDevice, BufMgr.Mode) &
+                                            BUFMGR_MODE_ENABLE))
+                                               break;
+                                       MM_Wait (10);
+                               }
+                       } else
+                               REG_WR (pDevice, BufMgr.Mode,
+                                       data | BUFMGR_MODE_ENABLE);
+                       break;

 
 

-           case T3_BLOCK_MAC_GLOBAL:
-               if(cntrl == LM_DISABLE)
-               {
-                   pDevice->MacMode &= ~(MAC_MODE_ENABLE_TDE |
-                       MAC_MODE_ENABLE_RDE |
-                       MAC_MODE_ENABLE_FHDE);
-               }
-               else
-               {
-                   pDevice->MacMode |= (MAC_MODE_ENABLE_TDE |
-                       MAC_MODE_ENABLE_RDE |
-                       MAC_MODE_ENABLE_FHDE);
-               }
-               REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
-               break;
+               case T3_BLOCK_MAC_GLOBAL:
+                       if (cntrl == LM_DISABLE) {
+                               pDevice->MacMode &= ~(MAC_MODE_ENABLE_TDE |
+                                                     MAC_MODE_ENABLE_RDE |
+                                                     MAC_MODE_ENABLE_FHDE);
+                       } else {
+                               pDevice->MacMode |= (MAC_MODE_ENABLE_TDE |
+                                                    MAC_MODE_ENABLE_RDE |
+                                                    MAC_MODE_ENABLE_FHDE);
+                       }
+                       REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
+                       break;

 
 

-           default:
-               return LM_STATUS_FAILURE;
-       } /* switch */
+               default:
+                       return LM_STATUS_FAILURE;
+               }               /* switch */

 
 

-       if(j >= MaxWaitCnt)
-       {
-           return LM_STATUS_FAILURE;
+               if (j >= MaxWaitCnt) {
+                       return LM_STATUS_FAILURE;
+               }

        }
        }

-    }

 
 

-    return LM_STATUS_SUCCESS;
+       return LM_STATUS_SUCCESS;

 }
 
 /******************************************************************************/
 }
 
 /******************************************************************************/


@@ -2295,682 +2129,631 @@ LM_UINT32 mask,LM_UINT32 cntrl)
 /* Return:                                                                    */
 /*    LM_STATUS_SUCCESS                                                       */
 /******************************************************************************/
 /* Return:                                                                    */
 /*    LM_STATUS_SUCCESS                                                       */
 /******************************************************************************/

-LM_STATUS
-LM_ResetAdapter(
-PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_ResetAdapter (PLM_DEVICE_BLOCK pDevice)

 {
 {

-    LM_UINT32 Value32;
-    LM_UINT16 Value16;
-    LM_UINT32 j, k;
+       LM_UINT32 Value32;
+       LM_UINT16 Value16;
+       LM_UINT32 j, k;

 
 

-    /* Disable interrupt. */
-    LM_DisableInterrupt(pDevice);
+       /* Disable interrupt. */
+       LM_DisableInterrupt (pDevice);

 
 

-    /* May get a spurious interrupt */
-    pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED;
+       /* May get a spurious interrupt */
+       pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED;

 
 

-    /* Disable transmit and receive DMA engines.  Abort all pending requests. */
-    if(pDevice->InitDone)
-    {
-       LM_Abort(pDevice);
-    }
+       /* Disable transmit and receive DMA engines.  Abort all pending requests. */
+       if (pDevice->InitDone) {
+               LM_Abort (pDevice);
+       }

 
 

-    pDevice->ShuttingDown = FALSE;
+       pDevice->ShuttingDown = FALSE;

 
 

-    LM_ResetChip(pDevice);
+       LM_ResetChip (pDevice);

 
 

-    /* Bug: Athlon fix for B3 silicon only.  This bit does not do anything */
-    /* in other chip revisions. */
-    if(pDevice->DelayPciGrant)
-    {
-       Value32 = REG_RD(pDevice, PciCfg.ClockCtrl);
-       REG_WR(pDevice, PciCfg.ClockCtrl, Value32 | BIT_31);
-    }
+       /* Bug: Athlon fix for B3 silicon only.  This bit does not do anything */
+       /* in other chip revisions. */
+       if (pDevice->DelayPciGrant) {
+               Value32 = REG_RD (pDevice, PciCfg.ClockCtrl);
+               REG_WR (pDevice, PciCfg.ClockCtrl, Value32 | BIT_31);
+       }

 
 

-    if(pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
-    {
-       if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
-       {
-           Value32 = REG_RD(pDevice, PciCfg.PciState);
-           Value32 |= T3_PCI_STATE_RETRY_SAME_DMA;
-           REG_WR(pDevice, PciCfg.PciState, Value32);
-       }
-    }
-
-    /* Enable TaggedStatus mode. */
-    if(pDevice->UseTaggedStatus)
-    {
-       pDevice->MiscHostCtrl |= MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE;
-    }
-
-    /* Restore PCI configuration registers. */
-    MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG,
-       pDevice->SavedCacheLineReg);
-    MM_WriteConfig32(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG,
-       (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId);
-
-    /* Clear the statistics block. */
-    for(j = 0x0300; j < 0x0b00; j++)
-    {
-       MEM_WR_OFFSET(pDevice, j, 0);
-    }
-
-    /* Initialize the statistis Block */
-    pDevice->pStatusBlkVirt->Status = 0;
-    pDevice->pStatusBlkVirt->RcvStdConIdx = 0;
-    pDevice->pStatusBlkVirt->RcvJumboConIdx = 0;
-    pDevice->pStatusBlkVirt->RcvMiniConIdx = 0;
-
-    for(j = 0; j < 16; j++)
-    {
-       pDevice->pStatusBlkVirt->Idx[j].RcvProdIdx = 0;
-       pDevice->pStatusBlkVirt->Idx[j].SendConIdx = 0;
-    }
-
-    for(k = 0; k < T3_STD_RCV_RCB_ENTRY_COUNT ;k++)
-    {
-       pDevice->pRxStdBdVirt[k].HostAddr.High = 0;
-       pDevice->pRxStdBdVirt[k].HostAddr.Low = 0;
-    }
+       if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
+               if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) {
+                       Value32 = REG_RD (pDevice, PciCfg.PciState);
+                       Value32 |= T3_PCI_STATE_RETRY_SAME_DMA;
+                       REG_WR (pDevice, PciCfg.PciState, Value32);
+               }
+       }
+
+       /* Enable TaggedStatus mode. */
+       if (pDevice->UseTaggedStatus) {
+               pDevice->MiscHostCtrl |=
+                   MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE;
+       }
+
+       /* Restore PCI configuration registers. */
+       MM_WriteConfig32 (pDevice, PCI_CACHE_LINE_SIZE_REG,
+                         pDevice->SavedCacheLineReg);
+       MM_WriteConfig32 (pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG,
+                         (pDevice->SubsystemId << 16) | pDevice->
+                         SubsystemVendorId);
+
+       /* Clear the statistics block. */
+       for (j = 0x0300; j < 0x0b00; j++) {
+               MEM_WR_OFFSET (pDevice, j, 0);
+       }
+
+       /* Initialize the statistis Block */
+       pDevice->pStatusBlkVirt->Status = 0;
+       pDevice->pStatusBlkVirt->RcvStdConIdx = 0;
+       pDevice->pStatusBlkVirt->RcvJumboConIdx = 0;
+       pDevice->pStatusBlkVirt->RcvMiniConIdx = 0;
+
+       for (j = 0; j < 16; j++) {
+               pDevice->pStatusBlkVirt->Idx[j].RcvProdIdx = 0;
+               pDevice->pStatusBlkVirt->Idx[j].SendConIdx = 0;
+       }
+
+       for (k = 0; k < T3_STD_RCV_RCB_ENTRY_COUNT; k++) {
+               pDevice->pRxStdBdVirt[k].HostAddr.High = 0;
+               pDevice->pRxStdBdVirt[k].HostAddr.Low = 0;
+       }

 
 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
 
 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT

-    /* Receive jumbo BD buffer. */
-    for(k = 0; k < T3_JUMBO_RCV_RCB_ENTRY_COUNT; k++)
-    {
-       pDevice->pRxJumboBdVirt[k].HostAddr.High = 0;
-       pDevice->pRxJumboBdVirt[k].HostAddr.Low = 0;
-    }
+       /* Receive jumbo BD buffer. */
+       for (k = 0; k < T3_JUMBO_RCV_RCB_ENTRY_COUNT; k++) {
+               pDevice->pRxJumboBdVirt[k].HostAddr.High = 0;
+               pDevice->pRxJumboBdVirt[k].HostAddr.Low = 0;
+       }

 #endif
 
 #endif
 

-    REG_WR(pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);
+       REG_WR (pDevice, PciCfg.DmaReadWriteCtrl, pDevice->DmaReadWriteCtrl);

 
 

-    /* GRC mode control register. */
-#ifdef BIG_ENDIAN_PCI    /* Jimmy, this ifdef block deleted in new code! */
-    Value32 =
-       GRC_MODE_WORD_SWAP_DATA |
-       GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
-       GRC_MODE_INT_ON_MAC_ATTN |
-       GRC_MODE_HOST_STACK_UP;
+       /* GRC mode control register. */
+#ifdef BIG_ENDIAN_PCI          /* Jimmy, this ifdef block deleted in new code! */
+       Value32 =
+           GRC_MODE_WORD_SWAP_DATA |
+           GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
+           GRC_MODE_INT_ON_MAC_ATTN | GRC_MODE_HOST_STACK_UP;

 #else
 #else

-    /* No CPU Swap modes for PCI IO */
-    Value32 =
+       /* No CPU Swap modes for PCI IO */
+       Value32 =

 #ifdef BIG_ENDIAN_HOST
 #ifdef BIG_ENDIAN_HOST

-       GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
-       GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
-       GRC_MODE_BYTE_SWAP_DATA |
-       GRC_MODE_WORD_SWAP_DATA |
+           GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
+           GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
+           GRC_MODE_BYTE_SWAP_DATA | GRC_MODE_WORD_SWAP_DATA |

 #else
 #else

-       GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
-       GRC_MODE_BYTE_SWAP_DATA |
-       GRC_MODE_WORD_SWAP_DATA |
+           GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
+           GRC_MODE_BYTE_SWAP_DATA | GRC_MODE_WORD_SWAP_DATA |

 #endif
 #endif

-       GRC_MODE_INT_ON_MAC_ATTN |
-       GRC_MODE_HOST_STACK_UP;
-#endif /* !BIG_ENDIAN_PCI */
-
-    /* Configure send BD mode. */
-    if(pDevice->NicSendBd == FALSE)
-    {
-       Value32 |= GRC_MODE_HOST_SEND_BDS;
-    }
-    else
-    {
-       Value32 |= GRC_MODE_4X_NIC_BASED_SEND_RINGS;
-    }
-
-    /* Configure pseudo checksum mode. */
-    if(pDevice->NoTxPseudoHdrChksum)
-    {
-       Value32 |= GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM;
-    }
-
-    if(pDevice->NoRxPseudoHdrChksum)
-    {
-       Value32 |= GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM;
-    }
-
-    REG_WR(pDevice, Grc.Mode, Value32);
-
-    /* Setup the timer prescalar register. */
-    REG_WR(pDevice, Grc.MiscCfg, 65 << 1);      /* Clock is alwasy 66Mhz. */
-
-    /* Set up the MBUF pool base address and size. */
-    REG_WR(pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase);
-    REG_WR(pDevice, BufMgr.MbufPoolSize, pDevice->MbufSize);
-
-    /* Set up the DMA descriptor pool base address and size. */
-    REG_WR(pDevice, BufMgr.DmaDescPoolAddr, T3_NIC_DMA_DESC_POOL_ADDR);
-    REG_WR(pDevice, BufMgr.DmaDescPoolSize, T3_NIC_DMA_DESC_POOL_SIZE);
-
-    /* Configure MBUF and Threshold watermarks */
-    /* Configure the DMA read MBUF low water mark. */
-    if(pDevice->DmaMbufLowMark)
-    {
-       REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark,
-           pDevice->DmaMbufLowMark);
-    }
-    else
-    {
-       if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE)
-       {
-           REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark,
-               T3_DEF_DMA_MBUF_LOW_WMARK);
+           GRC_MODE_INT_ON_MAC_ATTN | GRC_MODE_HOST_STACK_UP;
+#endif                         /* !BIG_ENDIAN_PCI */
+
+       /* Configure send BD mode. */
+       if (pDevice->NicSendBd == FALSE) {
+               Value32 |= GRC_MODE_HOST_SEND_BDS;
+       } else {
+               Value32 |= GRC_MODE_4X_NIC_BASED_SEND_RINGS;

        }
        }

-       else
-       {
-           REG_WR(pDevice, BufMgr.MbufReadDmaLowWaterMark,
-               T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO);
-       }
-    }
-
-    /* Configure the MAC Rx MBUF low water mark. */
-    if(pDevice->RxMacMbufLowMark)
-    {
-       REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark,
-           pDevice->RxMacMbufLowMark);
-    }
-    else
-    {
-       if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE)
-       {
-           REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark,
-               T3_DEF_RX_MAC_MBUF_LOW_WMARK);
+
+       /* Configure pseudo checksum mode. */
+       if (pDevice->NoTxPseudoHdrChksum) {
+               Value32 |= GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM;

        }
        }

-       else
-       {
-           REG_WR(pDevice, BufMgr.MbufMacRxLowWaterMark,
-               T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO);
-       }
-    }
-
-    /* Configure the MBUF high water mark. */
-    if(pDevice->MbufHighMark)
-    {
-       REG_WR(pDevice, BufMgr.MbufHighWaterMark, pDevice->MbufHighMark);
-    }
-    else
-    {
-       if(pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE)
-       {
-           REG_WR(pDevice, BufMgr.MbufHighWaterMark,
-               T3_DEF_MBUF_HIGH_WMARK);
+
+       if (pDevice->NoRxPseudoHdrChksum) {
+               Value32 |= GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM;

        }
        }

-       else
-       {
-           REG_WR(pDevice, BufMgr.MbufHighWaterMark,
-               T3_DEF_MBUF_HIGH_WMARK_JUMBO);
+
+       REG_WR (pDevice, Grc.Mode, Value32);
+
+       /* Setup the timer prescalar register. */
+       REG_WR (pDevice, Grc.MiscCfg, 65 << 1); /* Clock is alwasy 66Mhz. */
+
+       /* Set up the MBUF pool base address and size. */
+       REG_WR (pDevice, BufMgr.MbufPoolAddr, pDevice->MbufBase);
+       REG_WR (pDevice, BufMgr.MbufPoolSize, pDevice->MbufSize);
+
+       /* Set up the DMA descriptor pool base address and size. */
+       REG_WR (pDevice, BufMgr.DmaDescPoolAddr, T3_NIC_DMA_DESC_POOL_ADDR);
+       REG_WR (pDevice, BufMgr.DmaDescPoolSize, T3_NIC_DMA_DESC_POOL_SIZE);
+
+       /* Configure MBUF and Threshold watermarks */
+       /* Configure the DMA read MBUF low water mark. */
+       if (pDevice->DmaMbufLowMark) {
+               REG_WR (pDevice, BufMgr.MbufReadDmaLowWaterMark,
+                       pDevice->DmaMbufLowMark);
+       } else {
+               if (pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) {
+                       REG_WR (pDevice, BufMgr.MbufReadDmaLowWaterMark,
+                               T3_DEF_DMA_MBUF_LOW_WMARK);
+               } else {
+                       REG_WR (pDevice, BufMgr.MbufReadDmaLowWaterMark,
+                               T3_DEF_DMA_MBUF_LOW_WMARK_JUMBO);
+               }

        }
        }

-    }

 
 

-    REG_WR(pDevice, BufMgr.DmaLowWaterMark, T3_DEF_DMA_DESC_LOW_WMARK);
-    REG_WR(pDevice, BufMgr.DmaHighWaterMark, T3_DEF_DMA_DESC_HIGH_WMARK);
+       /* Configure the MAC Rx MBUF low water mark. */
+       if (pDevice->RxMacMbufLowMark) {
+               REG_WR (pDevice, BufMgr.MbufMacRxLowWaterMark,
+                       pDevice->RxMacMbufLowMark);
+       } else {
+               if (pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) {
+                       REG_WR (pDevice, BufMgr.MbufMacRxLowWaterMark,
+                               T3_DEF_RX_MAC_MBUF_LOW_WMARK);
+               } else {
+                       REG_WR (pDevice, BufMgr.MbufMacRxLowWaterMark,
+                               T3_DEF_RX_MAC_MBUF_LOW_WMARK_JUMBO);
+               }
+       }

 
 

-    /* Enable buffer manager. */
-    REG_WR(pDevice, BufMgr.Mode, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
+       /* Configure the MBUF high water mark. */
+       if (pDevice->MbufHighMark) {
+               REG_WR (pDevice, BufMgr.MbufHighWaterMark,
+                       pDevice->MbufHighMark);
+       } else {
+               if (pDevice->TxMtu < MAX_ETHERNET_PACKET_BUFFER_SIZE) {
+                       REG_WR (pDevice, BufMgr.MbufHighWaterMark,
+                               T3_DEF_MBUF_HIGH_WMARK);
+               } else {
+                       REG_WR (pDevice, BufMgr.MbufHighWaterMark,
+                               T3_DEF_MBUF_HIGH_WMARK_JUMBO);
+               }
+       }

 
 

-    for(j = 0 ;j < 2000; j++)
-    {
-       if(REG_RD(pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE)
-           break;
-       MM_Wait(10);
-    }
+       REG_WR (pDevice, BufMgr.DmaLowWaterMark, T3_DEF_DMA_DESC_LOW_WMARK);
+       REG_WR (pDevice, BufMgr.DmaHighWaterMark, T3_DEF_DMA_DESC_HIGH_WMARK);

 
 

-    if(j >= 2000)
-    {
-       return LM_STATUS_FAILURE;
-    }
-
-    /* Enable the FTQs. */
-    REG_WR(pDevice, Ftq.Reset, 0xffffffff);
-    REG_WR(pDevice, Ftq.Reset, 0);
-
-    /* Wait until FTQ is ready */
-    for(j = 0; j < 2000; j++)
-    {
-       if(REG_RD(pDevice, Ftq.Reset) == 0)
-           break;
-       MM_Wait(10);
-    }
-
-    if(j >= 2000)
-    {
-       return LM_STATUS_FAILURE;
-    }
-
-    /* Initialize the Standard Receive RCB. */
-    REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.High,
-       pDevice->RxStdBdPhy.High);
-    REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.Low,
-       pDevice->RxStdBdPhy.Low);
-    REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags,
-       MAX_STD_RCV_BUFFER_SIZE << 16);
-
-    /* Initialize the Jumbo Receive RCB. */
-    REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags,
-       T3_RCB_FLAG_RING_DISABLED);
-#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
-    REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.High,
-       pDevice->RxJumboBdPhy.High);
-    REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.Low,
-       pDevice->RxJumboBdPhy.Low);
+       /* Enable buffer manager. */
+       REG_WR (pDevice, BufMgr.Mode,
+               BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
+
+       for (j = 0; j < 2000; j++) {
+               if (REG_RD (pDevice, BufMgr.Mode) & BUFMGR_MODE_ENABLE)
+                       break;
+               MM_Wait (10);
+       }
+
+       if (j >= 2000) {
+               return LM_STATUS_FAILURE;
+       }

 
 

-    REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, 0);
+       /* Enable the FTQs. */
+       REG_WR (pDevice, Ftq.Reset, 0xffffffff);
+       REG_WR (pDevice, Ftq.Reset, 0);

 
 

-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+       /* Wait until FTQ is ready */
+       for (j = 0; j < 2000; j++) {
+               if (REG_RD (pDevice, Ftq.Reset) == 0)
+                       break;
+               MM_Wait (10);
+       }

 
 

-    /* Initialize the Mini Receive RCB. */
-    REG_WR(pDevice, RcvDataBdIn.MiniRcvRcb.u.MaxLen_Flags,
-       T3_RCB_FLAG_RING_DISABLED);
+       if (j >= 2000) {
+               return LM_STATUS_FAILURE;
+       }

 
 

-    {
-       REG_WR(pDevice, RcvDataBdIn.StdRcvRcb.NicRingAddr,
-           (LM_UINT32) T3_NIC_STD_RCV_BUFFER_DESC_ADDR);
-       REG_WR(pDevice, RcvDataBdIn.JumboRcvRcb.NicRingAddr,
-           (LM_UINT32) T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR);
-    }
+       /* Initialize the Standard Receive RCB. */
+       REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.High,
+               pDevice->RxStdBdPhy.High);
+       REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.HostRingAddr.Low,
+               pDevice->RxStdBdPhy.Low);
+       REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.u.MaxLen_Flags,
+               MAX_STD_RCV_BUFFER_SIZE << 16);

 
 

-    /* Receive BD Ring replenish threshold. */
-    REG_WR(pDevice, RcvBdIn.StdRcvThreshold, pDevice->RxStdDescCnt/8);
+       /* Initialize the Jumbo Receive RCB. */
+       REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags,
+               T3_RCB_FLAG_RING_DISABLED);

 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT

-    REG_WR(pDevice, RcvBdIn.JumboRcvThreshold, pDevice->RxJumboDescCnt/8);
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+       REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.High,
+               pDevice->RxJumboBdPhy.High);
+       REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.HostRingAddr.Low,
+               pDevice->RxJumboBdPhy.Low);

 
 

-    /* Disable all the unused rings. */
-    for(j = 0; j < T3_MAX_SEND_RCB_COUNT; j++) {
-       MEM_WR(pDevice, SendRcb[j].u.MaxLen_Flags, T3_RCB_FLAG_RING_DISABLED);
-    } /* for */
+       REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.u.MaxLen_Flags, 0);

 
 

-    /* Initialize the indices. */
-    pDevice->SendProdIdx = 0;
-    pDevice->SendConIdx = 0;
+#endif                         /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */

 
 

-    MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, 0);
-    MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, 0);
+       /* Initialize the Mini Receive RCB. */
+       REG_WR (pDevice, RcvDataBdIn.MiniRcvRcb.u.MaxLen_Flags,
+               T3_RCB_FLAG_RING_DISABLED);

 
 

-    /* Set up host or NIC based send RCB. */
-    if(pDevice->NicSendBd == FALSE)
-    {
-       MEM_WR(pDevice, SendRcb[0].HostRingAddr.High,
-           pDevice->SendBdPhy.High);
-       MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low,
-           pDevice->SendBdPhy.Low);
+       {
+               REG_WR (pDevice, RcvDataBdIn.StdRcvRcb.NicRingAddr,
+                       (LM_UINT32) T3_NIC_STD_RCV_BUFFER_DESC_ADDR);
+               REG_WR (pDevice, RcvDataBdIn.JumboRcvRcb.NicRingAddr,
+                       (LM_UINT32) T3_NIC_JUMBO_RCV_BUFFER_DESC_ADDR);
+       }
+
+       /* Receive BD Ring replenish threshold. */
+       REG_WR (pDevice, RcvBdIn.StdRcvThreshold, pDevice->RxStdDescCnt / 8);
+#if T3_JUMBO_RCV_RCB_ENTRY_COUNT
+       REG_WR (pDevice, RcvBdIn.JumboRcvThreshold,
+               pDevice->RxJumboDescCnt / 8);
+#endif                         /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+
+       /* Disable all the unused rings. */
+       for (j = 0; j < T3_MAX_SEND_RCB_COUNT; j++) {
+               MEM_WR (pDevice, SendRcb[j].u.MaxLen_Flags,
+                       T3_RCB_FLAG_RING_DISABLED);
+       }                       /* for */
+
+       /* Initialize the indices. */
+       pDevice->SendProdIdx = 0;
+       pDevice->SendConIdx = 0;
+
+       MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low, 0);
+       MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, 0);
+
+       /* Set up host or NIC based send RCB. */
+       if (pDevice->NicSendBd == FALSE) {
+               MEM_WR (pDevice, SendRcb[0].HostRingAddr.High,
+                       pDevice->SendBdPhy.High);
+               MEM_WR (pDevice, SendRcb[0].HostRingAddr.Low,
+                       pDevice->SendBdPhy.Low);
+
+               /* Set up the NIC ring address in the RCB. */
+               MEM_WR (pDevice, SendRcb[0].NicRingAddr,
+                       T3_NIC_SND_BUFFER_DESC_ADDR);
+
+               /* Setup the RCB. */
+               MEM_WR (pDevice, SendRcb[0].u.MaxLen_Flags,
+                       T3_SEND_RCB_ENTRY_COUNT << 16);
+
+               for (k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) {
+                       pDevice->pSendBdVirt[k].HostAddr.High = 0;
+                       pDevice->pSendBdVirt[k].HostAddr.Low = 0;
+               }
+       } else {
+               MEM_WR (pDevice, SendRcb[0].HostRingAddr.High, 0);
+               MEM_WR (pDevice, SendRcb[0].HostRingAddr.Low, 0);
+               MEM_WR (pDevice, SendRcb[0].NicRingAddr,
+                       pDevice->SendBdPhy.Low);
+
+               for (k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++) {
+                       __raw_writel (0,
+                                     &(pDevice->pSendBdVirt[k].HostAddr.High));
+                       __raw_writel (0,
+                                     &(pDevice->pSendBdVirt[k].HostAddr.Low));
+                       __raw_writel (0,
+                                     &(pDevice->pSendBdVirt[k].u1.Len_Flags));
+                       pDevice->ShadowSendBd[k].HostAddr.High = 0;
+                       pDevice->ShadowSendBd[k].u1.Len_Flags = 0;
+               }
+       }
+       atomic_set (&pDevice->SendBdLeft, T3_SEND_RCB_ENTRY_COUNT - 1);
+
+       /* Configure the receive return rings. */
+       for (j = 0; j < T3_MAX_RCV_RETURN_RCB_COUNT; j++) {
+               MEM_WR (pDevice, RcvRetRcb[j].u.MaxLen_Flags,
+                       T3_RCB_FLAG_RING_DISABLED);
+       }
+
+       pDevice->RcvRetConIdx = 0;
+
+       MEM_WR (pDevice, RcvRetRcb[0].HostRingAddr.High,
+               pDevice->RcvRetBdPhy.High);
+       MEM_WR (pDevice, RcvRetRcb[0].HostRingAddr.Low,
+               pDevice->RcvRetBdPhy.Low);

 
        /* Set up the NIC ring address in the RCB. */
 
        /* Set up the NIC ring address in the RCB. */

-       MEM_WR(pDevice, SendRcb[0].NicRingAddr,T3_NIC_SND_BUFFER_DESC_ADDR);
+       /* Not very clear from the spec.  I am guessing that for Receive */
+       /* Return Ring, NicRingAddr is not used. */
+       MEM_WR (pDevice, RcvRetRcb[0].NicRingAddr, 0);

 
        /* Setup the RCB. */
 
        /* Setup the RCB. */

-       MEM_WR(pDevice, SendRcb[0].u.MaxLen_Flags,
-           T3_SEND_RCB_ENTRY_COUNT << 16);
+       MEM_WR (pDevice, RcvRetRcb[0].u.MaxLen_Flags,
+               T3_RCV_RETURN_RCB_ENTRY_COUNT << 16);

 
 

-       for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++)
-       {
-           pDevice->pSendBdVirt[k].HostAddr.High = 0;
-           pDevice->pSendBdVirt[k].HostAddr.Low = 0;
-       }
-    }
-    else
-    {
-       MEM_WR(pDevice, SendRcb[0].HostRingAddr.High, 0);
-       MEM_WR(pDevice, SendRcb[0].HostRingAddr.Low, 0);
-       MEM_WR(pDevice, SendRcb[0].NicRingAddr,
-           pDevice->SendBdPhy.Low);
-
-       for(k = 0; k < T3_SEND_RCB_ENTRY_COUNT; k++)
-       {
-           __raw_writel(0, &(pDevice->pSendBdVirt[k].HostAddr.High));
-           __raw_writel(0, &(pDevice->pSendBdVirt[k].HostAddr.Low));
-           __raw_writel(0, &(pDevice->pSendBdVirt[k].u1.Len_Flags));
-           pDevice->ShadowSendBd[k].HostAddr.High = 0;
-           pDevice->ShadowSendBd[k].u1.Len_Flags = 0;
-       }
-    }
-    atomic_set(&pDevice->SendBdLeft, T3_SEND_RCB_ENTRY_COUNT-1);
-
-    /* Configure the receive return rings. */
-    for(j = 0; j < T3_MAX_RCV_RETURN_RCB_COUNT; j++)
-    {
-       MEM_WR(pDevice, RcvRetRcb[j].u.MaxLen_Flags, T3_RCB_FLAG_RING_DISABLED);
-    }
-
-    pDevice->RcvRetConIdx = 0;
-
-    MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.High,
-       pDevice->RcvRetBdPhy.High);
-    MEM_WR(pDevice, RcvRetRcb[0].HostRingAddr.Low,
-       pDevice->RcvRetBdPhy.Low);
-
-    /* Set up the NIC ring address in the RCB. */
-    /* Not very clear from the spec.  I am guessing that for Receive */
-    /* Return Ring, NicRingAddr is not used. */
-    MEM_WR(pDevice, RcvRetRcb[0].NicRingAddr, 0);
-
-    /* Setup the RCB. */
-    MEM_WR(pDevice, RcvRetRcb[0].u.MaxLen_Flags,
-       T3_RCV_RETURN_RCB_ENTRY_COUNT << 16);
-
-    /* Reinitialize RX ring producer index */
-    MB_REG_WR(pDevice, Mailbox.RcvStdProdIdx.Low, 0);
-    MB_REG_WR(pDevice, Mailbox.RcvJumboProdIdx.Low, 0);
-    MB_REG_WR(pDevice, Mailbox.RcvMiniProdIdx.Low, 0);
+       /* Reinitialize RX ring producer index */
+       MB_REG_WR (pDevice, Mailbox.RcvStdProdIdx.Low, 0);
+       MB_REG_WR (pDevice, Mailbox.RcvJumboProdIdx.Low, 0);
+       MB_REG_WR (pDevice, Mailbox.RcvMiniProdIdx.Low, 0);

 
 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
 
 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT

-    pDevice->RxJumboProdIdx = 0;
-    pDevice->RxJumboQueuedCnt = 0;
+       pDevice->RxJumboProdIdx = 0;
+       pDevice->RxJumboQueuedCnt = 0;

 #endif
 
 #endif
 

-    /* Reinitialize our copy of the indices. */
-    pDevice->RxStdProdIdx = 0;
-    pDevice->RxStdQueuedCnt = 0;
+       /* Reinitialize our copy of the indices. */
+       pDevice->RxStdProdIdx = 0;
+       pDevice->RxStdQueuedCnt = 0;

 
 #if T3_JUMBO_RCV_ENTRY_COUNT
 
 #if T3_JUMBO_RCV_ENTRY_COUNT

-    pDevice->RxJumboProdIdx = 0;
-#endif /* T3_JUMBO_RCV_ENTRY_COUNT */
-
-    /* Configure the MAC address. */
-    LM_SetMacAddress(pDevice, pDevice->NodeAddress);
-
-    /* Initialize the transmit random backoff seed. */
-    Value32 = (pDevice->NodeAddress[0] + pDevice->NodeAddress[1] +
-       pDevice->NodeAddress[2] + pDevice->NodeAddress[3] +
-       pDevice->NodeAddress[4] + pDevice->NodeAddress[5]) &
-       MAC_TX_BACKOFF_SEED_MASK;
-    REG_WR(pDevice, MacCtrl.TxBackoffSeed, Value32);
-
-    /* Receive MTU.  Frames larger than the MTU is marked as oversized. */
-    REG_WR(pDevice, MacCtrl.MtuSize, pDevice->RxMtu + 8);   /* CRC + VLAN. */
-
-    /* Configure Time slot/IPG per 802.3 */
-    REG_WR(pDevice, MacCtrl.TxLengths, 0x2620);
-
-    /*
-     * Configure Receive Rules so that packets don't match
-     * Programmble rule will be queued to Return Ring 1
-     */
-    REG_WR(pDevice, MacCtrl.RcvRuleCfg, RX_RULE_DEFAULT_CLASS);
-
-    /*
-     * Configure to have 16 Classes of Services (COS) and one
-     * queue per class.  Bad frames are queued to RRR#1.
-     * And frames don't match rules are also queued to COS#1.
-     */
-    REG_WR(pDevice, RcvListPlmt.Config, 0x181);
-
-    /* Enable Receive Placement Statistics */
-    REG_WR(pDevice, RcvListPlmt.StatsEnableMask,0xffffff);
-    REG_WR(pDevice, RcvListPlmt.StatsCtrl, RCV_LIST_STATS_ENABLE);
-
-    /* Enable Send Data Initator Statistics */
-    REG_WR(pDevice, SndDataIn.StatsEnableMask,0xffffff);
-    REG_WR(pDevice, SndDataIn.StatsCtrl,
-       T3_SND_DATA_IN_STATS_CTRL_ENABLE | \
-       T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE);
-
-    /* Disable the host coalescing state machine before configuring it's */
-    /* parameters. */
-    REG_WR(pDevice, HostCoalesce.Mode, 0);
-    for(j = 0; j < 2000; j++)
-    {
-       Value32 = REG_RD(pDevice, HostCoalesce.Mode);
-       if(!(Value32 & HOST_COALESCE_ENABLE))
-       {
-           break;
-       }
-       MM_Wait(10);
-    }
-
-    /* Host coalescing configurations. */
-    REG_WR(pDevice, HostCoalesce.RxCoalescingTicks, pDevice->RxCoalescingTicks);
-    REG_WR(pDevice, HostCoalesce.TxCoalescingTicks, pDevice->TxCoalescingTicks);
-    REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFrames,
-       pDevice->RxMaxCoalescedFrames);
-    REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFrames,
-       pDevice->TxMaxCoalescedFrames);
-    REG_WR(pDevice, HostCoalesce.RxCoalescedTickDuringInt,
-       pDevice->RxCoalescingTicksDuringInt);
-    REG_WR(pDevice, HostCoalesce.TxCoalescedTickDuringInt,
-       pDevice->TxCoalescingTicksDuringInt);
-    REG_WR(pDevice, HostCoalesce.RxMaxCoalescedFramesDuringInt,
-       pDevice->RxMaxCoalescedFramesDuringInt);
-    REG_WR(pDevice, HostCoalesce.TxMaxCoalescedFramesDuringInt,
-       pDevice->TxMaxCoalescedFramesDuringInt);
-
-    /* Initialize the address of the status block.  The NIC will DMA */
-    /* the status block to this memory which resides on the host. */
-    REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.High,
-       pDevice->StatusBlkPhy.High);
-    REG_WR(pDevice, HostCoalesce.StatusBlkHostAddr.Low,
-       pDevice->StatusBlkPhy.Low);
-
-    /* Initialize the address of the statistics block.  The NIC will DMA */
-    /* the statistics to this block of memory. */
-    REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.High,
-       pDevice->StatsBlkPhy.High);
-    REG_WR(pDevice, HostCoalesce.StatsBlkHostAddr.Low,
-       pDevice->StatsBlkPhy.Low);
-
-    REG_WR(pDevice, HostCoalesce.StatsCoalescingTicks,
-       pDevice->StatsCoalescingTicks);
-
-    REG_WR(pDevice, HostCoalesce.StatsBlkNicAddr, 0x300);
-    REG_WR(pDevice, HostCoalesce.StatusBlkNicAddr,0xb00);
-
-    /* Enable Host Coalesing state machine */
-    REG_WR(pDevice, HostCoalesce.Mode, HOST_COALESCE_ENABLE |
-       pDevice->CoalesceMode);
-
-    /* Enable the Receive BD Completion state machine. */
-    REG_WR(pDevice, RcvBdComp.Mode, RCV_BD_COMP_MODE_ENABLE |
-       RCV_BD_COMP_MODE_ATTN_ENABLE);
-
-    /* Enable the Receive List Placement state machine. */
-    REG_WR(pDevice, RcvListPlmt.Mode, RCV_LIST_PLMT_MODE_ENABLE);
-
-    /* Enable the Receive List Selector state machine. */
-    REG_WR(pDevice, RcvListSel.Mode, RCV_LIST_SEL_MODE_ENABLE |
-       RCV_LIST_SEL_MODE_ATTN_ENABLE);
-
-    /* Enable transmit DMA, clear statistics. */
-    pDevice->MacMode =  MAC_MODE_ENABLE_TX_STATISTICS |
-       MAC_MODE_ENABLE_RX_STATISTICS | MAC_MODE_ENABLE_TDE |
-       MAC_MODE_ENABLE_RDE | MAC_MODE_ENABLE_FHDE;
-    REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
-       MAC_MODE_CLEAR_RX_STATISTICS | MAC_MODE_CLEAR_TX_STATISTICS);
-
-    /* GRC miscellaneous local control register. */
-    pDevice->GrcLocalCtrl = GRC_MISC_LOCAL_CTRL_INT_ON_ATTN |
-       GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM;
-
-    if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
-    {
-       pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
-           GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1;
-    }
-
-    REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl);
-    MM_Wait(40);
-
-    /* Reset RX counters. */
-    for(j = 0; j < sizeof(LM_RX_COUNTERS); j++)
-    {
-       ((PLM_UINT8) &pDevice->RxCounters)[j] = 0;
-    }
-
-    /* Reset TX counters. */
-    for(j = 0; j < sizeof(LM_TX_COUNTERS); j++)
-    {
-       ((PLM_UINT8) &pDevice->TxCounters)[j] = 0;
-    }
-
-    MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 0);
-
-    /* Enable the DMA Completion state machine. */
-    REG_WR(pDevice, DmaComp.Mode, DMA_COMP_MODE_ENABLE);
-
-    /* Enable the DMA Write state machine. */
-    Value32 = DMA_WRITE_MODE_ENABLE |
-       DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE |
-       DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE |
-       DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE |
-       DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
-       DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE |
-       DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
-       DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE |
-       DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE;
-    REG_WR(pDevice, DmaWrite.Mode, Value32);
-
-    if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
-    {
-       if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
-       {
-           Value16 = REG_RD(pDevice, PciCfg.PciXCommand);
-           Value16 &= ~(PCIX_CMD_MAX_SPLIT_MASK | PCIX_CMD_MAX_BURST_MASK);
-           Value16 |= ((PCIX_CMD_MAX_BURST_CPIOB << PCIX_CMD_MAX_BURST_SHL) &
-               PCIX_CMD_MAX_BURST_MASK);
-           if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE)
-           {
-               Value16 |= (pDevice->SplitModeMaxReq << PCIX_CMD_MAX_SPLIT_SHL)
-                  & PCIX_CMD_MAX_SPLIT_MASK;
-           }
-           REG_WR(pDevice, PciCfg.PciXCommand, Value16);
-       }
-    }
-
-    /* Enable the Read DMA state machine. */
-    Value32 = DMA_READ_MODE_ENABLE |
-       DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE |
-       DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE |
-       DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE |
-       DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
-       DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE |
-       DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
-       DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE |
-       DMA_READ_MODE_LONG_READ_ATTN_ENABLE;
-
-    if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE)
-    {
-       Value32 |= DMA_READ_MODE_SPLIT_ENABLE;
-    }
-    REG_WR(pDevice, DmaRead.Mode, Value32);
-
-    /* Enable the Receive Data Completion state machine. */
-    REG_WR(pDevice, RcvDataComp.Mode, RCV_DATA_COMP_MODE_ENABLE |
-       RCV_DATA_COMP_MODE_ATTN_ENABLE);
-
-    /* Enable the Mbuf Cluster Free state machine. */
-    REG_WR(pDevice, MbufClusterFree.Mode, MBUF_CLUSTER_FREE_MODE_ENABLE);
-
-    /* Enable the Send Data Completion state machine. */
-    REG_WR(pDevice, SndDataComp.Mode, SND_DATA_COMP_MODE_ENABLE);
-
-    /* Enable the Send BD Completion state machine. */
-    REG_WR(pDevice, SndBdComp.Mode, SND_BD_COMP_MODE_ENABLE |
-       SND_BD_COMP_MODE_ATTN_ENABLE);
-
-    /* Enable the Receive BD Initiator state machine. */
-    REG_WR(pDevice, RcvBdIn.Mode, RCV_BD_IN_MODE_ENABLE |
-       RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE);
-
-    /* Enable the Receive Data and Receive BD Initiator state machine. */
-    REG_WR(pDevice, RcvDataBdIn.Mode, RCV_DATA_BD_IN_MODE_ENABLE |
-       RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE);
-
-    /* Enable the Send Data Initiator state machine. */
-    REG_WR(pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE);
-
-    /* Enable the Send BD Initiator state machine. */
-    REG_WR(pDevice, SndBdIn.Mode, SND_BD_IN_MODE_ENABLE |
-       SND_BD_IN_MODE_ATTN_ENABLE);
-
-    /* Enable the Send BD Selector state machine. */
-    REG_WR(pDevice, SndBdSel.Mode, SND_BD_SEL_MODE_ENABLE |
-       SND_BD_SEL_MODE_ATTN_ENABLE);
+       pDevice->RxJumboProdIdx = 0;
+#endif                         /* T3_JUMBO_RCV_ENTRY_COUNT */
+
+       /* Configure the MAC address. */
+       LM_SetMacAddress (pDevice, pDevice->NodeAddress);
+
+       /* Initialize the transmit random backoff seed. */
+       Value32 = (pDevice->NodeAddress[0] + pDevice->NodeAddress[1] +
+                  pDevice->NodeAddress[2] + pDevice->NodeAddress[3] +
+                  pDevice->NodeAddress[4] + pDevice->NodeAddress[5]) &
+           MAC_TX_BACKOFF_SEED_MASK;
+       REG_WR (pDevice, MacCtrl.TxBackoffSeed, Value32);
+
+       /* Receive MTU.  Frames larger than the MTU is marked as oversized. */
+       REG_WR (pDevice, MacCtrl.MtuSize, pDevice->RxMtu + 8);  /* CRC + VLAN. */
+
+       /* Configure Time slot/IPG per 802.3 */
+       REG_WR (pDevice, MacCtrl.TxLengths, 0x2620);
+
+       /*
+        * Configure Receive Rules so that packets don't match
+        * Programmble rule will be queued to Return Ring 1
+        */
+       REG_WR (pDevice, MacCtrl.RcvRuleCfg, RX_RULE_DEFAULT_CLASS);
+
+       /*
+        * Configure to have 16 Classes of Services (COS) and one
+        * queue per class.  Bad frames are queued to RRR#1.
+        * And frames don't match rules are also queued to COS#1.
+        */
+       REG_WR (pDevice, RcvListPlmt.Config, 0x181);
+
+       /* Enable Receive Placement Statistics */
+       REG_WR (pDevice, RcvListPlmt.StatsEnableMask, 0xffffff);
+       REG_WR (pDevice, RcvListPlmt.StatsCtrl, RCV_LIST_STATS_ENABLE);
+
+       /* Enable Send Data Initator Statistics */
+       REG_WR (pDevice, SndDataIn.StatsEnableMask, 0xffffff);
+       REG_WR (pDevice, SndDataIn.StatsCtrl,
+               T3_SND_DATA_IN_STATS_CTRL_ENABLE |
+               T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE);
+
+       /* Disable the host coalescing state machine before configuring it's */
+       /* parameters. */
+       REG_WR (pDevice, HostCoalesce.Mode, 0);
+       for (j = 0; j < 2000; j++) {
+               Value32 = REG_RD (pDevice, HostCoalesce.Mode);
+               if (!(Value32 & HOST_COALESCE_ENABLE)) {
+                       break;
+               }
+               MM_Wait (10);
+       }
+
+       /* Host coalescing configurations. */
+       REG_WR (pDevice, HostCoalesce.RxCoalescingTicks,
+               pDevice->RxCoalescingTicks);
+       REG_WR (pDevice, HostCoalesce.TxCoalescingTicks,
+               pDevice->TxCoalescingTicks);
+       REG_WR (pDevice, HostCoalesce.RxMaxCoalescedFrames,
+               pDevice->RxMaxCoalescedFrames);
+       REG_WR (pDevice, HostCoalesce.TxMaxCoalescedFrames,
+               pDevice->TxMaxCoalescedFrames);
+       REG_WR (pDevice, HostCoalesce.RxCoalescedTickDuringInt,
+               pDevice->RxCoalescingTicksDuringInt);
+       REG_WR (pDevice, HostCoalesce.TxCoalescedTickDuringInt,
+               pDevice->TxCoalescingTicksDuringInt);
+       REG_WR (pDevice, HostCoalesce.RxMaxCoalescedFramesDuringInt,
+               pDevice->RxMaxCoalescedFramesDuringInt);
+       REG_WR (pDevice, HostCoalesce.TxMaxCoalescedFramesDuringInt,
+               pDevice->TxMaxCoalescedFramesDuringInt);
+
+       /* Initialize the address of the status block.  The NIC will DMA */
+       /* the status block to this memory which resides on the host. */
+       REG_WR (pDevice, HostCoalesce.StatusBlkHostAddr.High,
+               pDevice->StatusBlkPhy.High);
+       REG_WR (pDevice, HostCoalesce.StatusBlkHostAddr.Low,
+               pDevice->StatusBlkPhy.Low);
+
+       /* Initialize the address of the statistics block.  The NIC will DMA */
+       /* the statistics to this block of memory. */
+       REG_WR (pDevice, HostCoalesce.StatsBlkHostAddr.High,
+               pDevice->StatsBlkPhy.High);
+       REG_WR (pDevice, HostCoalesce.StatsBlkHostAddr.Low,
+               pDevice->StatsBlkPhy.Low);
+
+       REG_WR (pDevice, HostCoalesce.StatsCoalescingTicks,
+               pDevice->StatsCoalescingTicks);
+
+       REG_WR (pDevice, HostCoalesce.StatsBlkNicAddr, 0x300);
+       REG_WR (pDevice, HostCoalesce.StatusBlkNicAddr, 0xb00);
+
+       /* Enable Host Coalesing state machine */
+       REG_WR (pDevice, HostCoalesce.Mode, HOST_COALESCE_ENABLE |
+               pDevice->CoalesceMode);
+
+       /* Enable the Receive BD Completion state machine. */
+       REG_WR (pDevice, RcvBdComp.Mode, RCV_BD_COMP_MODE_ENABLE |
+               RCV_BD_COMP_MODE_ATTN_ENABLE);
+
+       /* Enable the Receive List Placement state machine. */
+       REG_WR (pDevice, RcvListPlmt.Mode, RCV_LIST_PLMT_MODE_ENABLE);
+
+       /* Enable the Receive List Selector state machine. */
+       REG_WR (pDevice, RcvListSel.Mode, RCV_LIST_SEL_MODE_ENABLE |
+               RCV_LIST_SEL_MODE_ATTN_ENABLE);
+
+       /* Enable transmit DMA, clear statistics. */
+       pDevice->MacMode = MAC_MODE_ENABLE_TX_STATISTICS |
+           MAC_MODE_ENABLE_RX_STATISTICS | MAC_MODE_ENABLE_TDE |
+           MAC_MODE_ENABLE_RDE | MAC_MODE_ENABLE_FHDE;
+       REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode |
+               MAC_MODE_CLEAR_RX_STATISTICS | MAC_MODE_CLEAR_TX_STATISTICS);
+
+       /* GRC miscellaneous local control register. */
+       pDevice->GrcLocalCtrl = GRC_MISC_LOCAL_CTRL_INT_ON_ATTN |
+           GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM;
+
+       if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+               pDevice->GrcLocalCtrl |= GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
+                   GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1;
+       }
+
+       REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl);
+       MM_Wait (40);
+
+       /* Reset RX counters. */
+       for (j = 0; j < sizeof (LM_RX_COUNTERS); j++) {
+               ((PLM_UINT8) & pDevice->RxCounters)[j] = 0;
+       }
+
+       /* Reset TX counters. */
+       for (j = 0; j < sizeof (LM_TX_COUNTERS); j++) {
+               ((PLM_UINT8) & pDevice->TxCounters)[j] = 0;
+       }
+
+       MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 0);
+
+       /* Enable the DMA Completion state machine. */
+       REG_WR (pDevice, DmaComp.Mode, DMA_COMP_MODE_ENABLE);
+
+       /* Enable the DMA Write state machine. */
+       Value32 = DMA_WRITE_MODE_ENABLE |
+           DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE |
+           DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE |
+           DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE |
+           DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
+           DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE |
+           DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
+           DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE |
+           DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE;
+       REG_WR (pDevice, DmaWrite.Mode, Value32);
+
+       if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) {
+               if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
+                       Value16 = REG_RD (pDevice, PciCfg.PciXCommand);
+                       Value16 &=
+                           ~(PCIX_CMD_MAX_SPLIT_MASK |
+                             PCIX_CMD_MAX_BURST_MASK);
+                       Value16 |=
+                           ((PCIX_CMD_MAX_BURST_CPIOB <<
+                             PCIX_CMD_MAX_BURST_SHL) &
+                            PCIX_CMD_MAX_BURST_MASK);
+                       if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) {
+                               Value16 |=
+                                   (pDevice->
+                                    SplitModeMaxReq << PCIX_CMD_MAX_SPLIT_SHL)
+                                   & PCIX_CMD_MAX_SPLIT_MASK;
+                       }
+                       REG_WR (pDevice, PciCfg.PciXCommand, Value16);
+               }
+       }
+
+       /* Enable the Read DMA state machine. */
+       Value32 = DMA_READ_MODE_ENABLE |
+           DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE |
+           DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE |
+           DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE |
+           DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE |
+           DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE |
+           DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE |
+           DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE |
+           DMA_READ_MODE_LONG_READ_ATTN_ENABLE;
+
+       if (pDevice->SplitModeEnable == SPLIT_MODE_ENABLE) {
+               Value32 |= DMA_READ_MODE_SPLIT_ENABLE;
+       }
+       REG_WR (pDevice, DmaRead.Mode, Value32);
+
+       /* Enable the Receive Data Completion state machine. */
+       REG_WR (pDevice, RcvDataComp.Mode, RCV_DATA_COMP_MODE_ENABLE |
+               RCV_DATA_COMP_MODE_ATTN_ENABLE);
+
+       /* Enable the Mbuf Cluster Free state machine. */
+       REG_WR (pDevice, MbufClusterFree.Mode, MBUF_CLUSTER_FREE_MODE_ENABLE);
+
+       /* Enable the Send Data Completion state machine. */
+       REG_WR (pDevice, SndDataComp.Mode, SND_DATA_COMP_MODE_ENABLE);
+
+       /* Enable the Send BD Completion state machine. */
+       REG_WR (pDevice, SndBdComp.Mode, SND_BD_COMP_MODE_ENABLE |
+               SND_BD_COMP_MODE_ATTN_ENABLE);
+
+       /* Enable the Receive BD Initiator state machine. */
+       REG_WR (pDevice, RcvBdIn.Mode, RCV_BD_IN_MODE_ENABLE |
+               RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE);
+
+       /* Enable the Receive Data and Receive BD Initiator state machine. */
+       REG_WR (pDevice, RcvDataBdIn.Mode, RCV_DATA_BD_IN_MODE_ENABLE |
+               RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE);
+
+       /* Enable the Send Data Initiator state machine. */
+       REG_WR (pDevice, SndDataIn.Mode, T3_SND_DATA_IN_MODE_ENABLE);
+
+       /* Enable the Send BD Initiator state machine. */
+       REG_WR (pDevice, SndBdIn.Mode, SND_BD_IN_MODE_ENABLE |
+               SND_BD_IN_MODE_ATTN_ENABLE);
+
+       /* Enable the Send BD Selector state machine. */
+       REG_WR (pDevice, SndBdSel.Mode, SND_BD_SEL_MODE_ENABLE |
+               SND_BD_SEL_MODE_ATTN_ENABLE);

 
 #if INCLUDE_5701_AX_FIX
 
 #if INCLUDE_5701_AX_FIX

-    /* Load the firmware for the 5701_A0 workaround. */
-    if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0)
-    {
-       LM_LoadRlsFirmware(pDevice);
-    }
+       /* Load the firmware for the 5701_A0 workaround. */
+       if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0) {
+               LM_LoadRlsFirmware (pDevice);
+       }

 #endif
 
 #endif
 

-    /* Enable the transmitter. */
-    pDevice->TxMode = TX_MODE_ENABLE;
-    REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
-
-    /* Enable the receiver. */
-    pDevice->RxMode = RX_MODE_ENABLE;
-    REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
-
-    if (pDevice->RestoreOnWakeUp)
-    {
-       pDevice->RestoreOnWakeUp = FALSE;
-       pDevice->DisableAutoNeg = pDevice->WakeUpDisableAutoNeg;
-       pDevice->RequestedMediaType = pDevice->WakeUpRequestedMediaType;
-    }
-
-    /* Disable auto polling. */
-    pDevice->MiMode = 0xc0000;
-    REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
-
-    if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
-       T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
-    {
-       Value32 = LED_CTRL_PHY_MODE_1;
-    }
-    else
-    {
-       if(pDevice->LedMode == LED_MODE_OUTPUT)
-       {
-           Value32 = LED_CTRL_PHY_MODE_2;
-       }
-       else
-       {
-           Value32 = LED_CTRL_PHY_MODE_1;
+       /* Enable the transmitter. */
+       pDevice->TxMode = TX_MODE_ENABLE;
+       REG_WR (pDevice, MacCtrl.TxMode, pDevice->TxMode);
+
+       /* Enable the receiver. */
+       pDevice->RxMode = RX_MODE_ENABLE;
+       REG_WR (pDevice, MacCtrl.RxMode, pDevice->RxMode);
+
+       if (pDevice->RestoreOnWakeUp) {
+               pDevice->RestoreOnWakeUp = FALSE;
+               pDevice->DisableAutoNeg = pDevice->WakeUpDisableAutoNeg;
+               pDevice->RequestedMediaType = pDevice->WakeUpRequestedMediaType;

        }
        }

-    }
-    REG_WR(pDevice, MacCtrl.LedCtrl, Value32);

 
 

-    /* Activate Link to enable MAC state machine */
-    REG_WR(pDevice, MacCtrl.MiStatus, MI_STATUS_ENABLE_LINK_STATUS_ATTN);
+       /* Disable auto polling. */
+       pDevice->MiMode = 0xc0000;
+       REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);

 
 

-    if (pDevice->EnableTbi)
-    {
-       REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_RESET);
-       MM_Wait(10);
-       REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
-       if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1)
-       {
-           REG_WR(pDevice, MacCtrl.SerdesCfg, 0x616000);
+       if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+           T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+               Value32 = LED_CTRL_PHY_MODE_1;
+       } else {
+               if (pDevice->LedMode == LED_MODE_OUTPUT) {
+                       Value32 = LED_CTRL_PHY_MODE_2;
+               } else {
+                       Value32 = LED_CTRL_PHY_MODE_1;
+               }

        }
        }

-    }
-    /* Setup the phy chip. */
-    LM_SetupPhy(pDevice);
+       REG_WR (pDevice, MacCtrl.LedCtrl, Value32);
+
+       /* Activate Link to enable MAC state machine */
+       REG_WR (pDevice, MacCtrl.MiStatus, MI_STATUS_ENABLE_LINK_STATUS_ATTN);

 
 

-    if (!pDevice->EnableTbi) {
-       /* Clear CRC stats */
-       LM_ReadPhy(pDevice, 0x1e, &Value32);
-       LM_WritePhy(pDevice, 0x1e, Value32 | 0x8000);
-       LM_ReadPhy(pDevice, 0x14, &Value32);
-    }
+       if (pDevice->EnableTbi) {
+               REG_WR (pDevice, MacCtrl.RxMode, RX_MODE_RESET);
+               MM_Wait (10);
+               REG_WR (pDevice, MacCtrl.RxMode, pDevice->RxMode);
+               if (pDevice->ChipRevId == T3_CHIP_ID_5703_A1) {
+                       REG_WR (pDevice, MacCtrl.SerdesCfg, 0x616000);
+               }
+       }
+       /* Setup the phy chip. */
+       LM_SetupPhy (pDevice);

 
 

-    /* Set up the receive mask. */
-    LM_SetReceiveMask(pDevice, pDevice->ReceiveMask);
+       if (!pDevice->EnableTbi) {
+               /* Clear CRC stats */
+               LM_ReadPhy (pDevice, 0x1e, &Value32);
+               LM_WritePhy (pDevice, 0x1e, Value32 | 0x8000);
+               LM_ReadPhy (pDevice, 0x14, &Value32);
+       }

 
 

-    /* Queue Rx packet buffers. */
-    if(pDevice->QueueRxPackets)
-    {
-       LM_QueueRxPackets(pDevice);
-    }
+       /* Set up the receive mask. */
+       LM_SetReceiveMask (pDevice, pDevice->ReceiveMask);

 
 

-    /* Enable interrupt to the host. */
-    if(pDevice->InitDone)
-    {
-       LM_EnableInterrupt(pDevice);
-    }
+       /* Queue Rx packet buffers. */
+       if (pDevice->QueueRxPackets) {
+               LM_QueueRxPackets (pDevice);
+       }

 
 

-    return LM_STATUS_SUCCESS;
-} /* LM_ResetAdapter */
+       /* Enable interrupt to the host. */
+       if (pDevice->InitDone) {
+               LM_EnableInterrupt (pDevice);
+       }

 
 

+       return LM_STATUS_SUCCESS;
+}                              /* LM_ResetAdapter */

 
 /******************************************************************************/
 /* Description:                                                               */
 
 /******************************************************************************/
 /* Description:                                                               */


@@ -2979,18 +2762,15 @@ PLM_DEVICE_BLOCK pDevice)
 /* Return:                                                                    */
 /*    LM_STATUS_SUCCESS                                                       */
 /******************************************************************************/
 /* Return:                                                                    */
 /*    LM_STATUS_SUCCESS                                                       */
 /******************************************************************************/

-LM_STATUS
-LM_DisableInterrupt(
-    PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_DisableInterrupt (PLM_DEVICE_BLOCK pDevice)

 {
 {

-    REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl |
-       MISC_HOST_CTRL_MASK_PCI_INT);
-    MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 1);
+       REG_WR (pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl |
+               MISC_HOST_CTRL_MASK_PCI_INT);
+       MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 1);

 
 

-    return LM_STATUS_SUCCESS;
+       return LM_STATUS_SUCCESS;

 }
 
 }
 

-

 /******************************************************************************/
 /* Description:                                                               */
 /*    This routine enables the adapter to generate interrupts.                */
 /******************************************************************************/
 /* Description:                                                               */
 /*    This routine enables the adapter to generate interrupts.                */


@@ -2998,24 +2778,20 @@ LM_DisableInterrupt(
 /* Return:                                                                    */
 /*    LM_STATUS_SUCCESS                                                       */
 /******************************************************************************/
 /* Return:                                                                    */
 /*    LM_STATUS_SUCCESS                                                       */
 /******************************************************************************/

-LM_STATUS
-LM_EnableInterrupt(
-    PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_EnableInterrupt (PLM_DEVICE_BLOCK pDevice)

 {
 {

-    REG_WR(pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl &
-       ~MISC_HOST_CTRL_MASK_PCI_INT);
-    MB_REG_WR(pDevice, Mailbox.Interrupt[0].Low, 0);
+       REG_WR (pDevice, PciCfg.MiscHostCtrl, pDevice->MiscHostCtrl &
+               ~MISC_HOST_CTRL_MASK_PCI_INT);
+       MB_REG_WR (pDevice, Mailbox.Interrupt[0].Low, 0);

 
 

-    if(pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED)
-    {
-       REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
-           GRC_MISC_LOCAL_CTRL_SET_INT);
-    }
+       if (pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_UPDATED) {
+               REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
+                       GRC_MISC_LOCAL_CTRL_SET_INT);
+       }

 
 

-    return LM_STATUS_SUCCESS;
+       return LM_STATUS_SUCCESS;

 }
 
 }
 

-

 /******************************************************************************/
 /* Description:                                                               */
 /*    This routine puts a packet on the wire if there is a transmit DMA       */
 /******************************************************************************/
 /* Description:                                                               */
 /*    This routine puts a packet on the wire if there is a transmit DMA       */


@@ -3027,306 +2803,279 @@ LM_EnableInterrupt(
 /*    LM_STATUS_SUCCESS                                                       */
 /******************************************************************************/
 #if 0
 /*    LM_STATUS_SUCCESS                                                       */
 /******************************************************************************/
 #if 0

-LM_STATUS
-LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
+LM_STATUS LM_SendPacket (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)

 {
 {

-    LM_UINT32 FragCount;
-    PT3_SND_BD pSendBd;
-    PT3_SND_BD pShadowSendBd;
-    LM_UINT32 Value32, Len;
-    LM_UINT32 Idx;
+       LM_UINT32 FragCount;
+       PT3_SND_BD pSendBd;
+       PT3_SND_BD pShadowSendBd;
+       LM_UINT32 Value32, Len;
+       LM_UINT32 Idx;

 
 

-    if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) {
-       return LM_5700SendPacket(pDevice, pPacket);
-    }
+       if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+               return LM_5700SendPacket (pDevice, pPacket);
+       }

 
 

-    /* Update the SendBdLeft count. */
-    atomic_sub(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
+       /* Update the SendBdLeft count. */
+       atomic_sub (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);

 
 

-    /* Initalize the send buffer descriptors. */
-    Idx = pDevice->SendProdIdx;
+       /* Initalize the send buffer descriptors. */
+       Idx = pDevice->SendProdIdx;

 
 

-    pSendBd = &pDevice->pSendBdVirt[Idx];
+       pSendBd = &pDevice->pSendBdVirt[Idx];

 
 

-    /* Next producer index. */
-    if (pDevice->NicSendBd == TRUE)
-    {
-       T3_64BIT_HOST_ADDR paddr;
+       /* Next producer index. */
+       if (pDevice->NicSendBd == TRUE) {
+               T3_64BIT_HOST_ADDR paddr;
+
+               pShadowSendBd = &pDevice->ShadowSendBd[Idx];
+               for (FragCount = 0;;) {
+                       MM_MapTxDma (pDevice, pPacket, &paddr, &Len, FragCount);
+                       /* Initialize the pointer to the send buffer fragment. */
+                       if (paddr.High != pShadowSendBd->HostAddr.High) {
+                               __raw_writel (paddr.High,
+                                             &(pSendBd->HostAddr.High));
+                               pShadowSendBd->HostAddr.High = paddr.High;
+                       }
+                       __raw_writel (paddr.Low, &(pSendBd->HostAddr.Low));
+
+                       /* Setup the control flags and send buffer size. */
+                       Value32 = (Len << 16) | pPacket->Flags;
+
+                       Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
+
+                       FragCount++;
+                       if (FragCount >= pPacket->u.Tx.FragCount) {
+                               Value32 |= SND_BD_FLAG_END;
+                               if (Value32 != pShadowSendBd->u1.Len_Flags) {
+                                       __raw_writel (Value32,
+                                                     &(pSendBd->u1.Len_Flags));
+                                       pShadowSendBd->u1.Len_Flags = Value32;
+                               }
+                               if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) {
+                                       __raw_writel (pPacket->VlanTag,
+                                                     &(pSendBd->u2.VlanTag));
+                               }
+                               break;
+                       } else {
+                               if (Value32 != pShadowSendBd->u1.Len_Flags) {
+                                       __raw_writel (Value32,
+                                                     &(pSendBd->u1.Len_Flags));
+                                       pShadowSendBd->u1.Len_Flags = Value32;
+                               }
+                               if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) {
+                                       __raw_writel (pPacket->VlanTag,
+                                                     &(pSendBd->u2.VlanTag));
+                               }
+                       }

 
 

-       pShadowSendBd = &pDevice->ShadowSendBd[Idx];
-       for(FragCount = 0; ; )
-       {
-           MM_MapTxDma(pDevice, pPacket, &paddr, &Len, FragCount);
-           /* Initialize the pointer to the send buffer fragment. */
-           if (paddr.High != pShadowSendBd->HostAddr.High)
-           {
-               __raw_writel(paddr.High, &(pSendBd->HostAddr.High));
-               pShadowSendBd->HostAddr.High = paddr.High;
-           }
-           __raw_writel(paddr.Low, &(pSendBd->HostAddr.Low));
-
-           /* Setup the control flags and send buffer size. */
-           Value32 = (Len << 16) | pPacket->Flags;
-
-           Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
-
-           FragCount++;
-           if (FragCount >= pPacket->u.Tx.FragCount)
-           {
-               Value32 |= SND_BD_FLAG_END;
-               if (Value32 != pShadowSendBd->u1.Len_Flags)
-               {
-                   __raw_writel(Value32, &(pSendBd->u1.Len_Flags));
-                   pShadowSendBd->u1.Len_Flags = Value32;
-               }
-               if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) {
-                   __raw_writel(pPacket->VlanTag, &(pSendBd->u2.VlanTag));
-               }
-               break;
-           }
-           else
-           {
-               if (Value32 != pShadowSendBd->u1.Len_Flags)
-               {
-                   __raw_writel(Value32, &(pSendBd->u1.Len_Flags));
-                   pShadowSendBd->u1.Len_Flags = Value32;
-               }
-               if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) {
-                   __raw_writel(pPacket->VlanTag, &(pSendBd->u2.VlanTag));
-               }
-           }
-
-           pSendBd++;
-           pShadowSendBd++;
-           if (Idx == 0)
-           {
-               pSendBd = &pDevice->pSendBdVirt[0];
-               pShadowSendBd = &pDevice->ShadowSendBd[0];
-           }
-       } /* for */
+                       pSendBd++;
+                       pShadowSendBd++;
+                       if (Idx == 0) {
+                               pSendBd = &pDevice->pSendBdVirt[0];
+                               pShadowSendBd = &pDevice->ShadowSendBd[0];
+                       }
+               }               /* for */

 
 

-       /* Put the packet descriptor in the ActiveQ. */
-       QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket);
+               /* Put the packet descriptor in the ActiveQ. */
+               QQ_PushTail (&pDevice->TxPacketActiveQ.Container, pPacket);

 
 

-       wmb();
-       MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
+               wmb ();
+               MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);

 
 

-    }
-    else
-    {
-       for(FragCount = 0; ; )
-       {
-           /* Initialize the pointer to the send buffer fragment. */
-           MM_MapTxDma(pDevice, pPacket, &pSendBd->HostAddr, &Len, FragCount);
+       } else {
+               for (FragCount = 0;;) {
+                       /* Initialize the pointer to the send buffer fragment. */
+                       MM_MapTxDma (pDevice, pPacket, &pSendBd->HostAddr, &Len,
+                                    FragCount);

 
 

-           pSendBd->u2.VlanTag = pPacket->VlanTag;
+                       pSendBd->u2.VlanTag = pPacket->VlanTag;

 
 

-           /* Setup the control flags and send buffer size. */
-           Value32 = (Len << 16) | pPacket->Flags;
+                       /* Setup the control flags and send buffer size. */
+                       Value32 = (Len << 16) | pPacket->Flags;

 
 

-           Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
+                       Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;

 
 

-           FragCount++;
-           if (FragCount >= pPacket->u.Tx.FragCount)
-           {
-               pSendBd->u1.Len_Flags = Value32 | SND_BD_FLAG_END;
-               break;
-           }
-           else
-           {
-               pSendBd->u1.Len_Flags = Value32;
-           }
-           pSendBd++;
-           if (Idx == 0)
-           {
-               pSendBd = &pDevice->pSendBdVirt[0];
-           }
-       } /* for */
+                       FragCount++;
+                       if (FragCount >= pPacket->u.Tx.FragCount) {
+                               pSendBd->u1.Len_Flags =
+                                   Value32 | SND_BD_FLAG_END;
+                               break;
+                       } else {
+                               pSendBd->u1.Len_Flags = Value32;
+                       }
+                       pSendBd++;
+                       if (Idx == 0) {
+                               pSendBd = &pDevice->pSendBdVirt[0];
+                       }
+               }               /* for */

 
 

-       /* Put the packet descriptor in the ActiveQ. */
-       QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket);
+               /* Put the packet descriptor in the ActiveQ. */
+               QQ_PushTail (&pDevice->TxPacketActiveQ.Container, pPacket);

 
 

-       wmb();
-       MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
+               wmb ();
+               MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);

 
 

-    }
+       }

 
 

-    /* Update the producer index. */
-    pDevice->SendProdIdx = Idx;
+       /* Update the producer index. */
+       pDevice->SendProdIdx = Idx;

 
 

-    return LM_STATUS_SUCCESS;
+       return LM_STATUS_SUCCESS;

 }
 #endif
 
 }
 #endif
 

-LM_STATUS
-LM_SendPacket(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)
+LM_STATUS LM_SendPacket (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket)

 {
 {

-    LM_UINT32 FragCount;
-    PT3_SND_BD pSendBd, pTmpSendBd, pShadowSendBd;
-    T3_SND_BD NicSendBdArr[MAX_FRAGMENT_COUNT];
-    LM_UINT32 StartIdx, Idx;
+       LM_UINT32 FragCount;
+       PT3_SND_BD pSendBd, pTmpSendBd, pShadowSendBd;
+       T3_SND_BD NicSendBdArr[MAX_FRAGMENT_COUNT];
+       LM_UINT32 StartIdx, Idx;
+
+       while (1) {
+               /* Initalize the send buffer descriptors. */
+               StartIdx = Idx = pDevice->SendProdIdx;
+
+               if (pDevice->NicSendBd) {
+                       pTmpSendBd = pSendBd = &NicSendBdArr[0];
+               } else {
+                       pTmpSendBd = pSendBd = &pDevice->pSendBdVirt[Idx];
+               }

 
 

-    while (1)
-    {
-       /* Initalize the send buffer descriptors. */
-       StartIdx = Idx = pDevice->SendProdIdx;
+               /* Next producer index. */
+               for (FragCount = 0;;) {
+                       LM_UINT32 Value32, Len;

 
 

-       if (pDevice->NicSendBd)
-       {
-           pTmpSendBd = pSendBd = &NicSendBdArr[0];
-       }
-       else
-       {
-           pTmpSendBd = pSendBd = &pDevice->pSendBdVirt[Idx];
+                       /* Initialize the pointer to the send buffer fragment. */
+                       MM_MapTxDma (pDevice, pPacket, &pSendBd->HostAddr, &Len,
+                                    FragCount);
+
+                       pSendBd->u2.VlanTag = pPacket->VlanTag;
+
+                       /* Setup the control flags and send buffer size. */
+                       Value32 = (Len << 16) | pPacket->Flags;
+
+                       Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
+
+                       FragCount++;
+                       if (FragCount >= pPacket->u.Tx.FragCount) {
+                               pSendBd->u1.Len_Flags =
+                                   Value32 | SND_BD_FLAG_END;
+                               break;
+                       } else {
+                               pSendBd->u1.Len_Flags = Value32;
+                       }
+                       pSendBd++;
+                       if ((Idx == 0) && !pDevice->NicSendBd) {
+                               pSendBd = &pDevice->pSendBdVirt[0];
+                       }
+               }               /* for */
+               if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+                       if (LM_Test4GBoundary (pDevice, pPacket, pTmpSendBd) ==
+                           LM_STATUS_SUCCESS) {
+                               if (MM_CoalesceTxBuffer (pDevice, pPacket) !=
+                                   LM_STATUS_SUCCESS) {
+                                       QQ_PushHead (&pDevice->TxPacketFreeQ.
+                                                    Container, pPacket);
+                                       return LM_STATUS_FAILURE;
+                               }
+                               continue;
+                       }
+               }
+               break;

        }
        }

+       /* Put the packet descriptor in the ActiveQ. */
+       QQ_PushTail (&pDevice->TxPacketActiveQ.Container, pPacket);

 
 

-       /* Next producer index. */
-       for(FragCount = 0; ; )
-       {
-           LM_UINT32 Value32, Len;
+       if (pDevice->NicSendBd) {
+               pSendBd = &pDevice->pSendBdVirt[StartIdx];
+               pShadowSendBd = &pDevice->ShadowSendBd[StartIdx];

 
 

-           /* Initialize the pointer to the send buffer fragment. */
-           MM_MapTxDma(pDevice, pPacket, &pSendBd->HostAddr, &Len, FragCount);
+               while (StartIdx != Idx) {
+                       LM_UINT32 Value32;

 
 

-           pSendBd->u2.VlanTag = pPacket->VlanTag;
+                       if ((Value32 = pTmpSendBd->HostAddr.High) !=
+                           pShadowSendBd->HostAddr.High) {
+                               __raw_writel (Value32,
+                                             &(pSendBd->HostAddr.High));
+                               pShadowSendBd->HostAddr.High = Value32;
+                       }

 
 

-           /* Setup the control flags and send buffer size. */
-           Value32 = (Len << 16) | pPacket->Flags;
+                       __raw_writel (pTmpSendBd->HostAddr.Low,
+                                     &(pSendBd->HostAddr.Low));

 
 

-           Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
+                       if ((Value32 = pTmpSendBd->u1.Len_Flags) !=
+                           pShadowSendBd->u1.Len_Flags) {
+                               __raw_writel (Value32,
+                                             &(pSendBd->u1.Len_Flags));
+                               pShadowSendBd->u1.Len_Flags = Value32;
+                       }

 
 

-           FragCount++;
-           if (FragCount >= pPacket->u.Tx.FragCount)
-           {
-               pSendBd->u1.Len_Flags = Value32 | SND_BD_FLAG_END;
-               break;
-           }
-           else
-           {
-               pSendBd->u1.Len_Flags = Value32;
-           }
-           pSendBd++;
-           if ((Idx == 0) && !pDevice->NicSendBd)
-           {
-               pSendBd = &pDevice->pSendBdVirt[0];
-           }
-       } /* for */
-       if (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
-       {
-           if (LM_Test4GBoundary(pDevice, pPacket, pTmpSendBd) ==
-               LM_STATUS_SUCCESS)
-           {
-               if (MM_CoalesceTxBuffer(pDevice, pPacket) != LM_STATUS_SUCCESS)
-               {
-                   QQ_PushHead(&pDevice->TxPacketFreeQ.Container, pPacket);
-                   return LM_STATUS_FAILURE;
-               }
-               continue;
-           }
-       }
-       break;
-    }
-    /* Put the packet descriptor in the ActiveQ. */
-    QQ_PushTail(&pDevice->TxPacketActiveQ.Container, pPacket);
-
-    if (pDevice->NicSendBd)
-    {
-       pSendBd = &pDevice->pSendBdVirt[StartIdx];
-       pShadowSendBd = &pDevice->ShadowSendBd[StartIdx];
-
-       while (StartIdx != Idx)
-       {
-           LM_UINT32 Value32;
-
-           if ((Value32 = pTmpSendBd->HostAddr.High) !=
-               pShadowSendBd->HostAddr.High)
-           {
-               __raw_writel(Value32, &(pSendBd->HostAddr.High));
-               pShadowSendBd->HostAddr.High = Value32;
-           }
-
-           __raw_writel(pTmpSendBd->HostAddr.Low, &(pSendBd->HostAddr.Low));
-
-           if ((Value32 = pTmpSendBd->u1.Len_Flags) !=
-               pShadowSendBd->u1.Len_Flags)
-           {
-               __raw_writel(Value32, &(pSendBd->u1.Len_Flags));
-               pShadowSendBd->u1.Len_Flags = Value32;
-           }
-
-           if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG)
-           {
-               __raw_writel(pTmpSendBd->u2.VlanTag, &(pSendBd->u2.VlanTag));
-           }
-
-           StartIdx = (StartIdx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
-           if (StartIdx == 0)
-               pSendBd = &pDevice->pSendBdVirt[0];
-           else
-               pSendBd++;
-           pTmpSendBd++;
-       }
-       wmb();
-       MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
+                       if (pPacket->Flags & SND_BD_FLAG_VLAN_TAG) {
+                               __raw_writel (pTmpSendBd->u2.VlanTag,
+                                             &(pSendBd->u2.VlanTag));
+                       }

 
 

-       if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX)
-       {
-           MB_REG_WR(pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
-       }
-    }
-    else
-    {
-       wmb();
-       MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
+                       StartIdx =
+                           (StartIdx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
+                       if (StartIdx == 0)
+                               pSendBd = &pDevice->pSendBdVirt[0];
+                       else
+                               pSendBd++;
+                       pTmpSendBd++;
+               }
+               wmb ();
+               MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);

 
 

-       if(T3_CHIP_REV(pDevice->ChipRevId) == T3_CHIP_REV_5700_BX)
-       {
-           MB_REG_WR(pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
+               if (T3_CHIP_REV (pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) {
+                       MB_REG_WR (pDevice, Mailbox.SendNicProdIdx[0].Low, Idx);
+               }
+       } else {
+               wmb ();
+               MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low, Idx);
+
+               if (T3_CHIP_REV (pDevice->ChipRevId) == T3_CHIP_REV_5700_BX) {
+                       MB_REG_WR (pDevice, Mailbox.SendHostProdIdx[0].Low,
+                                  Idx);
+               }

        }
        }

-    }

 
 

-    /* Update the SendBdLeft count. */
-    atomic_sub(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
+       /* Update the SendBdLeft count. */
+       atomic_sub (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);

 
 

-    /* Update the producer index. */
-    pDevice->SendProdIdx = Idx;
+       /* Update the producer index. */
+       pDevice->SendProdIdx = Idx;

 
 

-    return LM_STATUS_SUCCESS;
+       return LM_STATUS_SUCCESS;

 }
 
 STATIC LM_STATUS
 }
 
 STATIC LM_STATUS

-LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket,
-    PT3_SND_BD pSendBd)
+LM_Test4GBoundary (PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket,
+                  PT3_SND_BD pSendBd)

 {
 {

-    int FragCount;
-    LM_UINT32 Idx, Base, Len;
-
-    Idx = pDevice->SendProdIdx;
-    for(FragCount = 0; ; )
-    {
-       Len = pSendBd->u1.Len_Flags >> 16;
-       if (((Base = pSendBd->HostAddr.Low) > 0xffffdcc0) &&
-           (pSendBd->HostAddr.High == 0) &&
-           ((Base + 8 + Len) < Base))
-       {
-           return LM_STATUS_SUCCESS;
-       }
-       FragCount++;
-       if (FragCount >= pPacket->u.Tx.FragCount)
-       {
-           break;
+       int FragCount;
+       LM_UINT32 Idx, Base, Len;
+
+       Idx = pDevice->SendProdIdx;
+       for (FragCount = 0;;) {
+               Len = pSendBd->u1.Len_Flags >> 16;
+               if (((Base = pSendBd->HostAddr.Low) > 0xffffdcc0) &&
+                   (pSendBd->HostAddr.High == 0) &&
+                   ((Base + 8 + Len) < Base)) {
+                       return LM_STATUS_SUCCESS;
+               }
+               FragCount++;
+               if (FragCount >= pPacket->u.Tx.FragCount) {
+                       break;
+               }
+               pSendBd++;
+               if (!pDevice->NicSendBd) {
+                       Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
+                       if (Idx == 0) {
+                               pSendBd = &pDevice->pSendBdVirt[0];
+                       }
+               }

        }
        }

-       pSendBd++;
-       if (!pDevice->NicSendBd)
-       {
-           Idx = (Idx + 1) & T3_SEND_RCB_ENTRY_COUNT_MASK;
-           if (Idx == 0)
-           {
-               pSendBd = &pDevice->pSendBdVirt[0];
-           }
-       }
-    }
-    return LM_STATUS_FAILURE;
+       return LM_STATUS_FAILURE;

 }
 
 /******************************************************************************/
 }
 
 /******************************************************************************/


@@ -3335,35 +3084,30 @@ LM_Test4GBoundary(PLM_DEVICE_BLOCK pDevice, PLM_PACKET pPacket,
 /* Return:                                                                    */
 /******************************************************************************/
 __inline static unsigned long
 /* Return:                                                                    */
 /******************************************************************************/
 __inline static unsigned long

-ComputeCrc32(
-unsigned char *pBuffer,
-unsigned long BufferSize) {
-    unsigned long Reg;
-    unsigned long Tmp;
-    unsigned long j, k;
+ComputeCrc32 (unsigned char *pBuffer, unsigned long BufferSize)
+{
+       unsigned long Reg;
+       unsigned long Tmp;
+       unsigned long j, k;

 
 

-    Reg = 0xffffffff;
+       Reg = 0xffffffff;

 
 

-    for(j = 0; j < BufferSize; j++)
-    {
-       Reg ^= pBuffer[j];
+       for (j = 0; j < BufferSize; j++) {
+               Reg ^= pBuffer[j];

 
 

-       for(k = 0; k < 8; k++)
-       {
-           Tmp = Reg & 0x01;
+               for (k = 0; k < 8; k++) {
+                       Tmp = Reg & 0x01;

 
 

-           Reg >>= 1;
+                       Reg >>= 1;

 
 

-           if(Tmp)
-           {
-               Reg ^= 0xedb88320;
-           }
+                       if (Tmp) {
+                               Reg ^= 0xedb88320;
+                       }
+               }

        }
        }

-    }
-
-    return ~Reg;
-} /* ComputeCrc32 */

 
 

+       return ~Reg;
+}                              /* ComputeCrc32 */

 
 /******************************************************************************/
 /* Description:                                                               */
 
 /******************************************************************************/
 /* Description:                                                               */


@@ -3372,149 +3116,139 @@ unsigned long BufferSize) {
 /* Return:                                                                    */
 /*    LM_STATUS_SUCCESS                                                       */
 /******************************************************************************/
 /* Return:                                                                    */
 /*    LM_STATUS_SUCCESS                                                       */
 /******************************************************************************/

-LM_STATUS
-LM_SetReceiveMask(
-PLM_DEVICE_BLOCK pDevice,
-LM_UINT32 Mask) {
-    LM_UINT32 ReceiveMask;
-    LM_UINT32 RxMode;
-    LM_UINT32 j, k;
-
-    ReceiveMask = Mask;
-
-    RxMode = pDevice->RxMode;
-
-    if(Mask & LM_ACCEPT_UNICAST)
-    {
-       Mask &= ~LM_ACCEPT_UNICAST;
-    }
-
-    if(Mask & LM_ACCEPT_MULTICAST)
-    {
-       Mask &= ~LM_ACCEPT_MULTICAST;
-    }
-
-    if(Mask & LM_ACCEPT_ALL_MULTICAST)
-    {
-       Mask &= ~LM_ACCEPT_ALL_MULTICAST;
-    }
-
-    if(Mask & LM_ACCEPT_BROADCAST)
-    {
-       Mask &= ~LM_ACCEPT_BROADCAST;
-    }
-
-    RxMode &= ~RX_MODE_PROMISCUOUS_MODE;
-    if(Mask & LM_PROMISCUOUS_MODE)
-    {
-       RxMode |= RX_MODE_PROMISCUOUS_MODE;
-       Mask &= ~LM_PROMISCUOUS_MODE;
-    }
-
-    RxMode &= ~(RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED);
-    if(Mask & LM_ACCEPT_ERROR_PACKET)
-    {
-       RxMode |= RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED;
-       Mask &= ~LM_ACCEPT_ERROR_PACKET;
-    }
-
-    /* Make sure all the bits are valid before committing changes. */
-    if(Mask)
-    {
-       return LM_STATUS_FAILURE;
-    }
+LM_STATUS LM_SetReceiveMask (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Mask)
+{
+       LM_UINT32 ReceiveMask;
+       LM_UINT32 RxMode;
+       LM_UINT32 j, k;

 
 

-    /* Commit the new filter. */
-    pDevice->RxMode = RxMode;
-    REG_WR(pDevice, MacCtrl.RxMode, RxMode);
+       ReceiveMask = Mask;

 
 

-    pDevice->ReceiveMask = ReceiveMask;
+       RxMode = pDevice->RxMode;

 
 

-    /* Set up the MC hash table. */
-    if(ReceiveMask & LM_ACCEPT_ALL_MULTICAST)
-    {
-       for(k = 0; k < 4; k++)
-       {
-           REG_WR(pDevice, MacCtrl.HashReg[k], 0xffffffff);
+       if (Mask & LM_ACCEPT_UNICAST) {
+               Mask &= ~LM_ACCEPT_UNICAST;

        }
        }

-    }
-    else if(ReceiveMask & LM_ACCEPT_MULTICAST)
-    {
-       LM_UINT32 HashReg[4];

 
 

-       HashReg[0] = 0; HashReg[1] = 0; HashReg[2] = 0; HashReg[3] = 0;
-       for(j = 0; j < pDevice->McEntryCount; j++)
-       {
-           LM_UINT32 RegIndex;
-           LM_UINT32 Bitpos;
-           LM_UINT32 Crc32;
+       if (Mask & LM_ACCEPT_MULTICAST) {
+               Mask &= ~LM_ACCEPT_MULTICAST;
+       }
+
+       if (Mask & LM_ACCEPT_ALL_MULTICAST) {
+               Mask &= ~LM_ACCEPT_ALL_MULTICAST;
+       }
+
+       if (Mask & LM_ACCEPT_BROADCAST) {
+               Mask &= ~LM_ACCEPT_BROADCAST;
+       }

 
 

-           Crc32 = ComputeCrc32(pDevice->McTable[j], ETHERNET_ADDRESS_SIZE);
+       RxMode &= ~RX_MODE_PROMISCUOUS_MODE;
+       if (Mask & LM_PROMISCUOUS_MODE) {
+               RxMode |= RX_MODE_PROMISCUOUS_MODE;
+               Mask &= ~LM_PROMISCUOUS_MODE;
+       }
+
+       RxMode &= ~(RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED);
+       if (Mask & LM_ACCEPT_ERROR_PACKET) {
+               RxMode |= RX_MODE_ACCEPT_RUNTS | RX_MODE_ACCEPT_OVERSIZED;
+               Mask &= ~LM_ACCEPT_ERROR_PACKET;
+       }
+
+       /* Make sure all the bits are valid before committing changes. */
+       if (Mask) {
+               return LM_STATUS_FAILURE;
+       }

 
 

-           /* The most significant 7 bits of the CRC32 (no inversion), */
-           /* are used to index into one of the possible 128 bit positions. */
-           Bitpos = ~Crc32 & 0x7f;
+       /* Commit the new filter. */
+       pDevice->RxMode = RxMode;
+       REG_WR (pDevice, MacCtrl.RxMode, RxMode);

 
 

-           /* Hash register index. */
-           RegIndex = (Bitpos & 0x60) >> 5;
+       pDevice->ReceiveMask = ReceiveMask;

 
 

-           /* Bit to turn on within a hash register. */
-           Bitpos &= 0x1f;
+       /* Set up the MC hash table. */
+       if (ReceiveMask & LM_ACCEPT_ALL_MULTICAST) {
+               for (k = 0; k < 4; k++) {
+                       REG_WR (pDevice, MacCtrl.HashReg[k], 0xffffffff);
+               }
+       } else if (ReceiveMask & LM_ACCEPT_MULTICAST) {
+               LM_UINT32 HashReg[4];
+
+               HashReg[0] = 0;
+               HashReg[1] = 0;
+               HashReg[2] = 0;
+               HashReg[3] = 0;
+               for (j = 0; j < pDevice->McEntryCount; j++) {
+                       LM_UINT32 RegIndex;
+                       LM_UINT32 Bitpos;
+                       LM_UINT32 Crc32;
+
+                       Crc32 =
+                           ComputeCrc32 (pDevice->McTable[j],
+                                         ETHERNET_ADDRESS_SIZE);
+
+                       /* The most significant 7 bits of the CRC32 (no inversion), */
+                       /* are used to index into one of the possible 128 bit positions. */
+                       Bitpos = ~Crc32 & 0x7f;
+
+                       /* Hash register index. */
+                       RegIndex = (Bitpos & 0x60) >> 5;
+
+                       /* Bit to turn on within a hash register. */
+                       Bitpos &= 0x1f;
+
+                       /* Enable the multicast bit. */
+                       HashReg[RegIndex] |= (1 << Bitpos);
+               }

 
 

-           /* Enable the multicast bit. */
-           HashReg[RegIndex] |= (1 << Bitpos);
+               /* REV_AX has problem with multicast filtering where it uses both */
+               /* DA and SA to perform hashing. */
+               for (k = 0; k < 4; k++) {
+                       REG_WR (pDevice, MacCtrl.HashReg[k], HashReg[k]);
+               }
+       } else {
+               /* Reject all multicast frames. */
+               for (j = 0; j < 4; j++) {
+                       REG_WR (pDevice, MacCtrl.HashReg[j], 0);
+               }

        }
 
        }
 

-       /* REV_AX has problem with multicast filtering where it uses both */
-       /* DA and SA to perform hashing. */
-       for(k = 0; k < 4; k++)
-       {
-           REG_WR(pDevice, MacCtrl.HashReg[k], HashReg[k]);
+       /* By default, Tigon3 will accept broadcast frames.  We need to setup */
+       if (ReceiveMask & LM_ACCEPT_BROADCAST) {
+               REG_WR (pDevice,
+                       MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule,
+                       REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK);
+               REG_WR (pDevice,
+                       MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value,
+                       REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK);
+               REG_WR (pDevice,
+                       MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule,
+                       REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK);
+               REG_WR (pDevice,
+                       MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value,
+                       REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK);
+       } else {
+               REG_WR (pDevice,
+                       MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule,
+                       REJECT_BROADCAST_RULE1_RULE);
+               REG_WR (pDevice,
+                       MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value,
+                       REJECT_BROADCAST_RULE1_VALUE);
+               REG_WR (pDevice,
+                       MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule,
+                       REJECT_BROADCAST_RULE2_RULE);
+               REG_WR (pDevice,
+                       MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value,
+                       REJECT_BROADCAST_RULE2_VALUE);
+       }
+
+       /* disable the rest of the rules. */
+       for (j = RCV_LAST_RULE_IDX; j < 16; j++) {
+               REG_WR (pDevice, MacCtrl.RcvRules[j].Rule, 0);
+               REG_WR (pDevice, MacCtrl.RcvRules[j].Value, 0);

        }
        }

-    }
-    else
-    {
-       /* Reject all multicast frames. */
-       for(j = 0; j < 4; j++)
-       {
-           REG_WR(pDevice, MacCtrl.HashReg[j], 0);
-       }
-    }
-
-    /* By default, Tigon3 will accept broadcast frames.  We need to setup */
-    if(ReceiveMask & LM_ACCEPT_BROADCAST)
-    {
-       REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule,
-           REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK);
-       REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value,
-           REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK);
-       REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule,
-           REJECT_BROADCAST_RULE1_RULE & RCV_DISABLE_RULE_MASK);
-       REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value,
-           REJECT_BROADCAST_RULE1_VALUE & RCV_DISABLE_RULE_MASK);
-    }
-    else
-    {
-       REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Rule,
-           REJECT_BROADCAST_RULE1_RULE);
-       REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE1_REJECT_BROADCAST_IDX].Value,
-           REJECT_BROADCAST_RULE1_VALUE);
-       REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Rule,
-           REJECT_BROADCAST_RULE2_RULE);
-       REG_WR(pDevice, MacCtrl.RcvRules[RCV_RULE2_REJECT_BROADCAST_IDX].Value,
-           REJECT_BROADCAST_RULE2_VALUE);
-    }
-
-    /* disable the rest of the rules. */
-    for(j = RCV_LAST_RULE_IDX; j < 16; j++)
-    {
-       REG_WR(pDevice, MacCtrl.RcvRules[j].Rule, 0);
-       REG_WR(pDevice, MacCtrl.RcvRules[j].Value, 0);
-    }
-
-    return LM_STATUS_SUCCESS;
-} /* LM_SetReceiveMask */

 
 

+       return LM_STATUS_SUCCESS;
+}                              /* LM_SetReceiveMask */

 
 /******************************************************************************/
 /* Description:                                                               */
 
 /******************************************************************************/
 /* Description:                                                               */


@@ -3525,138 +3259,135 @@ LM_UINT32 Mask) {
 /* Return:                                                                    */
 /*    LM_STATUS_SUCCESS                                                       */
 /******************************************************************************/
 /* Return:                                                                    */
 /*    LM_STATUS_SUCCESS                                                       */
 /******************************************************************************/

-LM_STATUS
-LM_Abort(
-PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_Abort (PLM_DEVICE_BLOCK pDevice)

 {
 {

-    PLM_PACKET pPacket;
-    LM_UINT Idx;
-
-    LM_DisableInterrupt(pDevice);
-
-    /* Disable all the state machines. */
-    LM_CntrlBlock(pDevice,T3_BLOCK_MAC_RX_ENGINE,LM_DISABLE);
-    LM_CntrlBlock(pDevice,T3_BLOCK_RX_BD_INITIATOR,LM_DISABLE);
-    LM_CntrlBlock(pDevice,T3_BLOCK_RX_LIST_PLMT,LM_DISABLE);
-    LM_CntrlBlock(pDevice,T3_BLOCK_RX_LIST_SELECTOR,LM_DISABLE);
-    LM_CntrlBlock(pDevice,T3_BLOCK_RX_DATA_INITIATOR,LM_DISABLE);
-    LM_CntrlBlock(pDevice,T3_BLOCK_RX_DATA_COMP,LM_DISABLE);
-    LM_CntrlBlock(pDevice,T3_BLOCK_RX_BD_COMP,LM_DISABLE);
-
-    LM_CntrlBlock(pDevice,T3_BLOCK_SEND_BD_SELECTOR,LM_DISABLE);
-    LM_CntrlBlock(pDevice,T3_BLOCK_SEND_BD_INITIATOR,LM_DISABLE);
-    LM_CntrlBlock(pDevice,T3_BLOCK_SEND_DATA_INITIATOR,LM_DISABLE);
-    LM_CntrlBlock(pDevice,T3_BLOCK_DMA_RD,LM_DISABLE);
-    LM_CntrlBlock(pDevice,T3_BLOCK_SEND_DATA_COMP,LM_DISABLE);
-    LM_CntrlBlock(pDevice,T3_BLOCK_DMA_COMP,LM_DISABLE);
-    LM_CntrlBlock(pDevice,T3_BLOCK_SEND_BD_COMP,LM_DISABLE);
-
-    /* Clear TDE bit */
-    pDevice->MacMode &= ~MAC_MODE_ENABLE_TDE;
-    REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
-
-    LM_CntrlBlock(pDevice,T3_BLOCK_MAC_TX_ENGINE,LM_DISABLE);
-    LM_CntrlBlock(pDevice,T3_BLOCK_HOST_COALESING,LM_DISABLE);
-    LM_CntrlBlock(pDevice,T3_BLOCK_DMA_WR,LM_DISABLE);
-    LM_CntrlBlock(pDevice,T3_BLOCK_MBUF_CLUSTER_FREE,LM_DISABLE);
-
-    /* Reset all FTQs */
-    REG_WR(pDevice, Ftq.Reset, 0xffffffff);
-    REG_WR(pDevice, Ftq.Reset, 0x0);
-
-    LM_CntrlBlock(pDevice,T3_BLOCK_MBUF_MANAGER,LM_DISABLE);
-    LM_CntrlBlock(pDevice,T3_BLOCK_MEM_ARBITOR,LM_DISABLE);
-
-    MM_ACQUIRE_INT_LOCK(pDevice);
-
-    /* Abort packets that have already queued to go out. */
-    pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->TxPacketActiveQ.Container);
-    while(pPacket)
-    {
-
-       pPacket->PacketStatus = LM_STATUS_TRANSMIT_ABORTED;
-       pDevice->TxCounters.TxPacketAbortedCnt++;
-
-       atomic_add(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
-
-       QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket);
-
-       pPacket = (PLM_PACKET)
-           QQ_PopHead(&pDevice->TxPacketActiveQ.Container);
-    }
-
-    /* Cleanup the receive return rings. */
-    LM_ServiceRxInterrupt(pDevice);
-
-    /* Don't want to indicate rx packets in Ndis miniport shutdown context. */
-    /* Doing so may cause system crash. */
-    if(!pDevice->ShuttingDown)
-    {
-       /* Indicate packets to the protocol. */
-       MM_IndicateTxPackets(pDevice);
-
-       /* Indicate received packets to the protocols. */
-       MM_IndicateRxPackets(pDevice);
-    }
-    else
-    {
-       /* Move the receive packet descriptors in the ReceivedQ to the */
-       /* free queue. */
-       for(; ;)
-       {
-           pPacket = (PLM_PACKET) QQ_PopHead(
-               &pDevice->RxPacketReceivedQ.Container);
-           if(pPacket == NULL)
-           {
-               break;
-           }
-           QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
+       PLM_PACKET pPacket;
+       LM_UINT Idx;
+
+       LM_DisableInterrupt (pDevice);
+
+       /* Disable all the state machines. */
+       LM_CntrlBlock (pDevice, T3_BLOCK_MAC_RX_ENGINE, LM_DISABLE);
+       LM_CntrlBlock (pDevice, T3_BLOCK_RX_BD_INITIATOR, LM_DISABLE);
+       LM_CntrlBlock (pDevice, T3_BLOCK_RX_LIST_PLMT, LM_DISABLE);
+       LM_CntrlBlock (pDevice, T3_BLOCK_RX_LIST_SELECTOR, LM_DISABLE);
+       LM_CntrlBlock (pDevice, T3_BLOCK_RX_DATA_INITIATOR, LM_DISABLE);
+       LM_CntrlBlock (pDevice, T3_BLOCK_RX_DATA_COMP, LM_DISABLE);
+       LM_CntrlBlock (pDevice, T3_BLOCK_RX_BD_COMP, LM_DISABLE);
+
+       LM_CntrlBlock (pDevice, T3_BLOCK_SEND_BD_SELECTOR, LM_DISABLE);
+       LM_CntrlBlock (pDevice, T3_BLOCK_SEND_BD_INITIATOR, LM_DISABLE);
+       LM_CntrlBlock (pDevice, T3_BLOCK_SEND_DATA_INITIATOR, LM_DISABLE);
+       LM_CntrlBlock (pDevice, T3_BLOCK_DMA_RD, LM_DISABLE);
+       LM_CntrlBlock (pDevice, T3_BLOCK_SEND_DATA_COMP, LM_DISABLE);
+       LM_CntrlBlock (pDevice, T3_BLOCK_DMA_COMP, LM_DISABLE);
+       LM_CntrlBlock (pDevice, T3_BLOCK_SEND_BD_COMP, LM_DISABLE);
+
+       /* Clear TDE bit */
+       pDevice->MacMode &= ~MAC_MODE_ENABLE_TDE;
+       REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);
+
+       LM_CntrlBlock (pDevice, T3_BLOCK_MAC_TX_ENGINE, LM_DISABLE);
+       LM_CntrlBlock (pDevice, T3_BLOCK_HOST_COALESING, LM_DISABLE);
+       LM_CntrlBlock (pDevice, T3_BLOCK_DMA_WR, LM_DISABLE);
+       LM_CntrlBlock (pDevice, T3_BLOCK_MBUF_CLUSTER_FREE, LM_DISABLE);
+
+       /* Reset all FTQs */
+       REG_WR (pDevice, Ftq.Reset, 0xffffffff);
+       REG_WR (pDevice, Ftq.Reset, 0x0);
+
+       LM_CntrlBlock (pDevice, T3_BLOCK_MBUF_MANAGER, LM_DISABLE);
+       LM_CntrlBlock (pDevice, T3_BLOCK_MEM_ARBITOR, LM_DISABLE);
+
+       MM_ACQUIRE_INT_LOCK (pDevice);
+
+       /* Abort packets that have already queued to go out. */
+       pPacket = (PLM_PACKET) QQ_PopHead (&pDevice->TxPacketActiveQ.Container);
+       while (pPacket) {
+
+               pPacket->PacketStatus = LM_STATUS_TRANSMIT_ABORTED;
+               pDevice->TxCounters.TxPacketAbortedCnt++;
+
+               atomic_add (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
+
+               QQ_PushTail (&pDevice->TxPacketXmittedQ.Container, pPacket);
+
+               pPacket = (PLM_PACKET)
+                   QQ_PopHead (&pDevice->TxPacketActiveQ.Container);
+       }
+
+       /* Cleanup the receive return rings. */
+       LM_ServiceRxInterrupt (pDevice);
+
+       /* Don't want to indicate rx packets in Ndis miniport shutdown context. */
+       /* Doing so may cause system crash. */
+       if (!pDevice->ShuttingDown) {
+               /* Indicate packets to the protocol. */
+               MM_IndicateTxPackets (pDevice);
+
+               /* Indicate received packets to the protocols. */
+               MM_IndicateRxPackets (pDevice);
+       } else {
+               /* Move the receive packet descriptors in the ReceivedQ to the */
+               /* free queue. */
+               for (;;) {
+                       pPacket =
+                           (PLM_PACKET) QQ_PopHead (&pDevice->
+                                                    RxPacketReceivedQ.
+                                                    Container);
+                       if (pPacket == NULL) {
+                               break;
+                       }
+                       QQ_PushTail (&pDevice->RxPacketFreeQ.Container,
+                                    pPacket);
+               }

        }
        }

-    }

 
 

-    /* Clean up the Std Receive Producer ring. */
-    Idx = pDevice->pStatusBlkVirt->RcvStdConIdx;
+       /* Clean up the Std Receive Producer ring. */
+       Idx = pDevice->pStatusBlkVirt->RcvStdConIdx;

 
 

-    while(Idx != pDevice->RxStdProdIdx) {
-       pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) +
-           MM_UINT_PTR(pDevice->pRxStdBdVirt[Idx].Opaque));
+       while (Idx != pDevice->RxStdProdIdx) {
+               pPacket = (PLM_PACKET) (MM_UINT_PTR (pDevice->pPacketDescBase) +
+                                       MM_UINT_PTR (pDevice->pRxStdBdVirt[Idx].
+                                                    Opaque));

 
 

-       QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
+               QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);

 
 

-       Idx = (Idx + 1) & T3_STD_RCV_RCB_ENTRY_COUNT_MASK;
-    } /* while */
+               Idx = (Idx + 1) & T3_STD_RCV_RCB_ENTRY_COUNT_MASK;
+       }                       /* while */

 
 

-    /* Reinitialize our copy of the indices. */
-    pDevice->RxStdProdIdx = 0;
+       /* Reinitialize our copy of the indices. */
+       pDevice->RxStdProdIdx = 0;

 
 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
 
 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT

-    /* Clean up the Jumbo Receive Producer ring. */
-    Idx = pDevice->pStatusBlkVirt->RcvJumboConIdx;
-
-    while(Idx != pDevice->RxJumboProdIdx) {
-       pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) +
-           MM_UINT_PTR(pDevice->pRxJumboBdVirt[Idx].Opaque));
+       /* Clean up the Jumbo Receive Producer ring. */
+       Idx = pDevice->pStatusBlkVirt->RcvJumboConIdx;

 
 

-       QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
+       while (Idx != pDevice->RxJumboProdIdx) {
+               pPacket = (PLM_PACKET) (MM_UINT_PTR (pDevice->pPacketDescBase) +
+                                       MM_UINT_PTR (pDevice->
+                                                    pRxJumboBdVirt[Idx].
+                                                    Opaque));

 
 

-       Idx = (Idx + 1) & T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK;
-    } /* while */
+               QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);

 
 

-    /* Reinitialize our copy of the indices. */
-    pDevice->RxJumboProdIdx = 0;
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+               Idx = (Idx + 1) & T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK;
+       }                       /* while */

 
 

-    MM_RELEASE_INT_LOCK(pDevice);
+       /* Reinitialize our copy of the indices. */
+       pDevice->RxJumboProdIdx = 0;
+#endif                         /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */

 
 

-    /* Initialize the statistis Block */
-    pDevice->pStatusBlkVirt->Status = 0;
-    pDevice->pStatusBlkVirt->RcvStdConIdx = 0;
-    pDevice->pStatusBlkVirt->RcvJumboConIdx = 0;
-    pDevice->pStatusBlkVirt->RcvMiniConIdx = 0;
+       MM_RELEASE_INT_LOCK (pDevice);

 
 

-    return LM_STATUS_SUCCESS;
-} /* LM_Abort */
+       /* Initialize the statistis Block */
+       pDevice->pStatusBlkVirt->Status = 0;
+       pDevice->pStatusBlkVirt->RcvStdConIdx = 0;
+       pDevice->pStatusBlkVirt->RcvJumboConIdx = 0;
+       pDevice->pStatusBlkVirt->RcvMiniConIdx = 0;

 
 

+       return LM_STATUS_SUCCESS;
+}                              /* LM_Abort */

 
 /******************************************************************************/
 /* Description:                                                               */
 
 /******************************************************************************/
 /* Description:                                                               */


@@ -3667,140 +3398,130 @@ PLM_DEVICE_BLOCK pDevice)
 /* Return:                                                                    */
 /*    LM_STATUS_SUCCESS                                                       */
 /******************************************************************************/
 /* Return:                                                                    */
 /*    LM_STATUS_SUCCESS                                                       */
 /******************************************************************************/

-LM_STATUS
-LM_Halt(
-PLM_DEVICE_BLOCK pDevice) {
-    PLM_PACKET pPacket;
-    LM_UINT32 EntryCnt;
-
-    LM_Abort(pDevice);
+LM_STATUS LM_Halt (PLM_DEVICE_BLOCK pDevice)
+{
+       PLM_PACKET pPacket;
+       LM_UINT32 EntryCnt;

 
 

-    /* Get the number of entries in the queue. */
-    EntryCnt = QQ_GetEntryCnt(&pDevice->RxPacketFreeQ.Container);
+       LM_Abort (pDevice);

 
 

-    /* Make sure all the packets have been accounted for. */
-    for(EntryCnt = 0; EntryCnt < pDevice->RxPacketDescCnt; EntryCnt++)
-    {
-       pPacket = (PLM_PACKET) QQ_PopHead(&pDevice->RxPacketFreeQ.Container);
-       if (pPacket == 0)
-           break;
+       /* Get the number of entries in the queue. */
+       EntryCnt = QQ_GetEntryCnt (&pDevice->RxPacketFreeQ.Container);

 
 

-       MM_FreeRxBuffer(pDevice, pPacket);
+       /* Make sure all the packets have been accounted for. */
+       for (EntryCnt = 0; EntryCnt < pDevice->RxPacketDescCnt; EntryCnt++) {
+               pPacket =
+                   (PLM_PACKET) QQ_PopHead (&pDevice->RxPacketFreeQ.Container);
+               if (pPacket == 0)
+                       break;

 
 

-       QQ_PushTail(&pDevice->RxPacketFreeQ.Container, pPacket);
-    }
+               MM_FreeRxBuffer (pDevice, pPacket);

 
 

-    LM_ResetChip(pDevice);
+               QQ_PushTail (&pDevice->RxPacketFreeQ.Container, pPacket);
+       }

 
 

-    /* Restore PCI configuration registers. */
-    MM_WriteConfig32(pDevice, PCI_CACHE_LINE_SIZE_REG,
-       pDevice->SavedCacheLineReg);
-    LM_RegWrInd(pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG,
-       (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId);
+       LM_ResetChip (pDevice);

 
 

-    /* Reprogram the MAC address. */
-    LM_SetMacAddress(pDevice, pDevice->NodeAddress);
+       /* Restore PCI configuration registers. */
+       MM_WriteConfig32 (pDevice, PCI_CACHE_LINE_SIZE_REG,
+                         pDevice->SavedCacheLineReg);
+       LM_RegWrInd (pDevice, PCI_SUBSYSTEM_VENDOR_ID_REG,
+                    (pDevice->SubsystemId << 16) | pDevice->SubsystemVendorId);

 
 

-    return LM_STATUS_SUCCESS;
-} /* LM_Halt */
+       /* Reprogram the MAC address. */
+       LM_SetMacAddress (pDevice, pDevice->NodeAddress);

 
 

+       return LM_STATUS_SUCCESS;
+}                              /* LM_Halt */

 
 

-STATIC LM_STATUS
-LM_ResetChip(PLM_DEVICE_BLOCK pDevice)
+STATIC LM_STATUS LM_ResetChip (PLM_DEVICE_BLOCK pDevice)

 {
 {

-    LM_UINT32 Value32;
-    LM_UINT32 j;
-
-    /* Wait for access to the nvram interface before resetting.  This is */
-    /* a workaround to prevent EEPROM corruption. */
-    if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
-       T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701)
-    {
-       /* Request access to the flash interface. */
-       REG_WR(pDevice, Nvram.SwArb, SW_ARB_REQ_SET1);
-
-       for(j = 0; j < 100000; j++)
-       {
-           Value32 = REG_RD(pDevice, Nvram.SwArb);
-           if(Value32 & SW_ARB_GNT1)
-           {
-               break;
-           }
-           MM_Wait(10);
+       LM_UINT32 Value32;
+       LM_UINT32 j;
+
+       /* Wait for access to the nvram interface before resetting.  This is */
+       /* a workaround to prevent EEPROM corruption. */
+       if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
+           T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5701) {
+               /* Request access to the flash interface. */
+               REG_WR (pDevice, Nvram.SwArb, SW_ARB_REQ_SET1);
+
+               for (j = 0; j < 100000; j++) {
+                       Value32 = REG_RD (pDevice, Nvram.SwArb);
+                       if (Value32 & SW_ARB_GNT1) {
+                               break;
+                       }
+                       MM_Wait (10);
+               }

        }
        }

-    }

 
 

-    /* Global reset. */
-    REG_WR(pDevice, Grc.MiscCfg, GRC_MISC_CFG_CORE_CLOCK_RESET);
-    MM_Wait(40); MM_Wait(40); MM_Wait(40);
+       /* Global reset. */
+       REG_WR (pDevice, Grc.MiscCfg, GRC_MISC_CFG_CORE_CLOCK_RESET);
+       MM_Wait (40);
+       MM_Wait (40);
+       MM_Wait (40);

 
 

-    /* make sure we re-enable indirect accesses */
-    MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG,
-       pDevice->MiscHostCtrl);
+       /* make sure we re-enable indirect accesses */
+       MM_WriteConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG,
+                         pDevice->MiscHostCtrl);

 
 

-    /* Set MAX PCI retry to zero. */
-    Value32 = T3_PCI_STATE_PCI_ROM_ENABLE | T3_PCI_STATE_PCI_ROM_RETRY_ENABLE;
-    if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
-    {
-       if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
-       {
-           Value32 |= T3_PCI_STATE_RETRY_SAME_DMA;
+       /* Set MAX PCI retry to zero. */
+       Value32 =
+           T3_PCI_STATE_PCI_ROM_ENABLE | T3_PCI_STATE_PCI_ROM_RETRY_ENABLE;
+       if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
+               if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) {
+                       Value32 |= T3_PCI_STATE_RETRY_SAME_DMA;
+               }

        }
        }

-    }
-    MM_WriteConfig32(pDevice, T3_PCI_STATE_REG, Value32);
+       MM_WriteConfig32 (pDevice, T3_PCI_STATE_REG, Value32);

 
 

-    /* Restore PCI command register. */
-    MM_WriteConfig32(pDevice, PCI_COMMAND_REG,
-       pDevice->PciCommandStatusWords);
+       /* Restore PCI command register. */
+       MM_WriteConfig32 (pDevice, PCI_COMMAND_REG,
+                         pDevice->PciCommandStatusWords);

 
 

-    /* Disable PCI-X relaxed ordering bit. */
-    MM_ReadConfig32(pDevice, PCIX_CAP_REG, &Value32);
-    Value32 &= ~PCIX_ENABLE_RELAXED_ORDERING;
-    MM_WriteConfig32(pDevice, PCIX_CAP_REG, Value32);
+       /* Disable PCI-X relaxed ordering bit. */
+       MM_ReadConfig32 (pDevice, PCIX_CAP_REG, &Value32);
+       Value32 &= ~PCIX_ENABLE_RELAXED_ORDERING;
+       MM_WriteConfig32 (pDevice, PCIX_CAP_REG, Value32);

 
 

-    /* Enable memory arbiter. */
-    REG_WR(pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);
+       /* Enable memory arbiter. */
+       REG_WR (pDevice, MemArbiter.Mode, T3_MEM_ARBITER_MODE_ENABLE);

 
 

-#ifdef BIG_ENDIAN_PCI      /* This from jfd */
-       Value32 = GRC_MODE_WORD_SWAP_DATA|
-                 GRC_MODE_WORD_SWAP_NON_FRAME_DATA;
+#ifdef BIG_ENDIAN_PCI          /* This from jfd */
+       Value32 = GRC_MODE_WORD_SWAP_DATA | GRC_MODE_WORD_SWAP_NON_FRAME_DATA;

 #else
 #ifdef BIG_ENDIAN_HOST
 #else
 #ifdef BIG_ENDIAN_HOST

-    /* Reconfigure the mode register. */
-    Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
-             GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
-             GRC_MODE_BYTE_SWAP_DATA |
-             GRC_MODE_WORD_SWAP_DATA;
+       /* Reconfigure the mode register. */
+       Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA |
+           GRC_MODE_WORD_SWAP_NON_FRAME_DATA |
+           GRC_MODE_BYTE_SWAP_DATA | GRC_MODE_WORD_SWAP_DATA;

 #else
 #else

-    /* Reconfigure the mode register. */
-    Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;
+       /* Reconfigure the mode register. */
+       Value32 = GRC_MODE_BYTE_SWAP_NON_FRAME_DATA | GRC_MODE_BYTE_SWAP_DATA;

 #endif
 #endif
 #endif
 #endif

-    REG_WR(pDevice, Grc.Mode, Value32);
-
-    /* Prevent PXE from restarting. */
-    MEM_WR_OFFSET(pDevice, 0x0b50, T3_MAGIC_NUM);
-
-    if(pDevice->EnableTbi) {
-       pDevice->MacMode = MAC_MODE_PORT_MODE_TBI;
-       REG_WR(pDevice, MacCtrl.Mode, MAC_MODE_PORT_MODE_TBI);
-    }
-    else {
-       REG_WR(pDevice, MacCtrl.Mode, 0);
-    }
-
-    /* Wait for the firmware to finish initialization. */
-    for(j = 0; j < 100000; j++)
-    {
-       MM_Wait(10);
-
-       Value32 = MEM_RD_OFFSET(pDevice, 0x0b50);
-       if(Value32 == ~T3_MAGIC_NUM)
-       {
-           break;
+       REG_WR (pDevice, Grc.Mode, Value32);
+
+       /* Prevent PXE from restarting. */
+       MEM_WR_OFFSET (pDevice, 0x0b50, T3_MAGIC_NUM);
+
+       if (pDevice->EnableTbi) {
+               pDevice->MacMode = MAC_MODE_PORT_MODE_TBI;
+               REG_WR (pDevice, MacCtrl.Mode, MAC_MODE_PORT_MODE_TBI);
+       } else {
+               REG_WR (pDevice, MacCtrl.Mode, 0);
+       }
+
+       /* Wait for the firmware to finish initialization. */
+       for (j = 0; j < 100000; j++) {
+               MM_Wait (10);
+
+               Value32 = MEM_RD_OFFSET (pDevice, 0x0b50);
+               if (Value32 == ~T3_MAGIC_NUM) {
+                       break;
+               }

        }
        }

-    }
-    return LM_STATUS_SUCCESS;
+       return LM_STATUS_SUCCESS;

 }
 
 /******************************************************************************/
 }
 
 /******************************************************************************/


@@ -3808,161 +3529,143 @@ LM_ResetChip(PLM_DEVICE_BLOCK pDevice)
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-__inline static void
-LM_ServiceTxInterrupt(
-PLM_DEVICE_BLOCK pDevice) {
-    PLM_PACKET pPacket;
-    LM_UINT32 HwConIdx;
-    LM_UINT32 SwConIdx;
-
-    HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx;
-
-    /* Get our copy of the consumer index.  The buffer descriptors */
-    /* that are in between the consumer indices are freed. */
-    SwConIdx = pDevice->SendConIdx;
-
-    /* Move the packets from the TxPacketActiveQ that are sent out to */
-    /* the TxPacketXmittedQ.  Packets that are sent use the */
-    /* descriptors that are between SwConIdx and HwConIdx. */
-    while(SwConIdx != HwConIdx)
-    {
-       /* Get the packet that was sent from the TxPacketActiveQ. */
-       pPacket = (PLM_PACKET) QQ_PopHead(
-           &pDevice->TxPacketActiveQ.Container);
-
-       /* Set the return status. */
-       pPacket->PacketStatus = LM_STATUS_SUCCESS;
-
-       /* Put the packet in the TxPacketXmittedQ for indication later. */
-       QQ_PushTail(&pDevice->TxPacketXmittedQ.Container, pPacket);
-
-       /* Move to the next packet's BD. */
-       SwConIdx = (SwConIdx + pPacket->u.Tx.FragCount) &
-           T3_SEND_RCB_ENTRY_COUNT_MASK;
-
-       /* Update the number of unused BDs. */
-       atomic_add(pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
-
-       /* Get the new updated HwConIdx. */
+__inline static void LM_ServiceTxInterrupt (PLM_DEVICE_BLOCK pDevice)
+{
+       PLM_PACKET pPacket;
+       LM_UINT32 HwConIdx;
+       LM_UINT32 SwConIdx;
+

        HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx;
        HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx;

-    } /* while */

 
 

-    /* Save the new SwConIdx. */
-    pDevice->SendConIdx = SwConIdx;
+       /* Get our copy of the consumer index.  The buffer descriptors */
+       /* that are in between the consumer indices are freed. */
+       SwConIdx = pDevice->SendConIdx;
+
+       /* Move the packets from the TxPacketActiveQ that are sent out to */
+       /* the TxPacketXmittedQ.  Packets that are sent use the */
+       /* descriptors that are between SwConIdx and HwConIdx. */
+       while (SwConIdx != HwConIdx) {
+               /* Get the packet that was sent from the TxPacketActiveQ. */
+               pPacket =
+                   (PLM_PACKET) QQ_PopHead (&pDevice->TxPacketActiveQ.
+                                            Container);
+
+               /* Set the return status. */
+               pPacket->PacketStatus = LM_STATUS_SUCCESS;
+
+               /* Put the packet in the TxPacketXmittedQ for indication later. */
+               QQ_PushTail (&pDevice->TxPacketXmittedQ.Container, pPacket);
+
+               /* Move to the next packet's BD. */
+               SwConIdx = (SwConIdx + pPacket->u.Tx.FragCount) &
+                   T3_SEND_RCB_ENTRY_COUNT_MASK;
+
+               /* Update the number of unused BDs. */
+               atomic_add (pPacket->u.Tx.FragCount, &pDevice->SendBdLeft);
+
+               /* Get the new updated HwConIdx. */
+               HwConIdx = pDevice->pStatusBlkVirt->Idx[0].SendConIdx;
+       }                       /* while */

 
 

-} /* LM_ServiceTxInterrupt */
+       /* Save the new SwConIdx. */
+       pDevice->SendConIdx = SwConIdx;

 
 

+}                              /* LM_ServiceTxInterrupt */

 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-__inline static void
-LM_ServiceRxInterrupt(
-PLM_DEVICE_BLOCK pDevice) {
-    PLM_PACKET pPacket;
-    PT3_RCV_BD pRcvBd;
-    LM_UINT32 HwRcvRetProdIdx;
-    LM_UINT32 SwRcvRetConIdx;
-
-    /* Loop thru the receive return rings for received packets. */
-    HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx;
-
-    SwRcvRetConIdx = pDevice->RcvRetConIdx;
-    while(SwRcvRetConIdx != HwRcvRetProdIdx)
-    {
-       pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx];
-
-       /* Get the received packet descriptor. */
-       pPacket = (PLM_PACKET) (MM_UINT_PTR(pDevice->pPacketDescBase) +
-           MM_UINT_PTR(pRcvBd->Opaque));
-
-       /* Check the error flag. */
-       if(pRcvBd->ErrorFlag &&
-           pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII)
-       {
-           pPacket->PacketStatus = LM_STATUS_FAILURE;
-
-           pDevice->RxCounters.RxPacketErrCnt++;
-
-           if(pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC)
-           {
-               pDevice->RxCounters.RxErrCrcCnt++;
-           }
-
-           if(pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT)
-           {
-               pDevice->RxCounters.RxErrCollCnt++;
-           }
-
-           if(pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT)
-           {
-               pDevice->RxCounters.RxErrLinkLostCnt++;
-           }
-
-           if(pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR)
-           {
-               pDevice->RxCounters.RxErrPhyDecodeCnt++;
-           }
-
-           if(pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII)
-           {
-               pDevice->RxCounters.RxErrOddNibbleCnt++;
-           }
-
-           if(pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT)
-           {
-               pDevice->RxCounters.RxErrMacAbortCnt++;
-           }
-
-           if(pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64)
-           {
-               pDevice->RxCounters.RxErrShortPacketCnt++;
-           }
-
-           if(pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES)
-           {
-               pDevice->RxCounters.RxErrNoResourceCnt++;
-           }
-
-           if(pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD)
-           {
-               pDevice->RxCounters.RxErrLargePacketCnt++;
-           }
-       }
-       else
-       {
-           pPacket->PacketStatus = LM_STATUS_SUCCESS;
-           pPacket->PacketSize = pRcvBd->Len - 4;
+__inline static void LM_ServiceRxInterrupt (PLM_DEVICE_BLOCK pDevice)
+{
+       PLM_PACKET pPacket;
+       PT3_RCV_BD pRcvBd;
+       LM_UINT32 HwRcvRetProdIdx;
+       LM_UINT32 SwRcvRetConIdx;

 
 

-           pPacket->Flags = pRcvBd->Flags;
-           if(pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG)
-           {
-               pPacket->VlanTag = pRcvBd->VlanTag;
-           }
+       /* Loop thru the receive return rings for received packets. */
+       HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx;

 
 

-           pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum;
-       }
+       SwRcvRetConIdx = pDevice->RcvRetConIdx;
+       while (SwRcvRetConIdx != HwRcvRetProdIdx) {
+               pRcvBd = &pDevice->pRcvRetBdVirt[SwRcvRetConIdx];

 
 

-       /* Put the packet descriptor containing the received packet */
-       /* buffer in the RxPacketReceivedQ for indication later. */
-       QQ_PushTail(&pDevice->RxPacketReceivedQ.Container, pPacket);
+               /* Get the received packet descriptor. */
+               pPacket = (PLM_PACKET) (MM_UINT_PTR (pDevice->pPacketDescBase) +
+                                       MM_UINT_PTR (pRcvBd->Opaque));

 
 

-       /* Go to the next buffer descriptor. */
-       SwRcvRetConIdx = (SwRcvRetConIdx + 1) &
-           T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK;
+               /* Check the error flag. */
+               if (pRcvBd->ErrorFlag &&
+                   pRcvBd->ErrorFlag != RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) {
+                       pPacket->PacketStatus = LM_STATUS_FAILURE;

 
 

-       /* Get the updated HwRcvRetProdIdx. */
-       HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx;
-    } /* while */
+                       pDevice->RxCounters.RxPacketErrCnt++;
+
+                       if (pRcvBd->ErrorFlag & RCV_BD_ERR_BAD_CRC) {
+                               pDevice->RxCounters.RxErrCrcCnt++;
+                       }
+
+                       if (pRcvBd->ErrorFlag & RCV_BD_ERR_COLL_DETECT) {
+                               pDevice->RxCounters.RxErrCollCnt++;
+                       }
+
+                       if (pRcvBd->ErrorFlag & RCV_BD_ERR_LINK_LOST_DURING_PKT) {
+                               pDevice->RxCounters.RxErrLinkLostCnt++;
+                       }
+
+                       if (pRcvBd->ErrorFlag & RCV_BD_ERR_PHY_DECODE_ERR) {
+                               pDevice->RxCounters.RxErrPhyDecodeCnt++;
+                       }

 
 

-    pDevice->RcvRetConIdx = SwRcvRetConIdx;
+                       if (pRcvBd->ErrorFlag & RCV_BD_ERR_ODD_NIBBLED_RCVD_MII) {
+                               pDevice->RxCounters.RxErrOddNibbleCnt++;
+                       }
+
+                       if (pRcvBd->ErrorFlag & RCV_BD_ERR_MAC_ABORT) {
+                               pDevice->RxCounters.RxErrMacAbortCnt++;
+                       }
+
+                       if (pRcvBd->ErrorFlag & RCV_BD_ERR_LEN_LT_64) {
+                               pDevice->RxCounters.RxErrShortPacketCnt++;
+                       }
+
+                       if (pRcvBd->ErrorFlag & RCV_BD_ERR_TRUNC_NO_RESOURCES) {
+                               pDevice->RxCounters.RxErrNoResourceCnt++;
+                       }
+
+                       if (pRcvBd->ErrorFlag & RCV_BD_ERR_GIANT_FRAME_RCVD) {
+                               pDevice->RxCounters.RxErrLargePacketCnt++;
+                       }
+               } else {
+                       pPacket->PacketStatus = LM_STATUS_SUCCESS;
+                       pPacket->PacketSize = pRcvBd->Len - 4;
+
+                       pPacket->Flags = pRcvBd->Flags;
+                       if (pRcvBd->Flags & RCV_BD_FLAG_VLAN_TAG) {
+                               pPacket->VlanTag = pRcvBd->VlanTag;
+                       }
+
+                       pPacket->u.Rx.TcpUdpChecksum = pRcvBd->TcpUdpCksum;
+               }
+
+               /* Put the packet descriptor containing the received packet */
+               /* buffer in the RxPacketReceivedQ for indication later. */
+               QQ_PushTail (&pDevice->RxPacketReceivedQ.Container, pPacket);
+
+               /* Go to the next buffer descriptor. */
+               SwRcvRetConIdx = (SwRcvRetConIdx + 1) &
+                   T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK;
+
+               /* Get the updated HwRcvRetProdIdx. */
+               HwRcvRetProdIdx = pDevice->pStatusBlkVirt->Idx[0].RcvProdIdx;
+       }                       /* while */

 
 

-    /* Update the receive return ring consumer index. */
-    MB_REG_WR(pDevice, Mailbox.RcvRetConIdx[0].Low, SwRcvRetConIdx);
-} /* LM_ServiceRxInterrupt */
+       pDevice->RcvRetConIdx = SwRcvRetConIdx;

 
 

+       /* Update the receive return ring consumer index. */
+       MB_REG_WR (pDevice, Mailbox.RcvRetConIdx[0].Low, SwRcvRetConIdx);
+}                              /* LM_ServiceRxInterrupt */

 
 /******************************************************************************/
 /* Description:                                                               */
 
 /******************************************************************************/
 /* Description:                                                               */


@@ -3972,206 +3675,179 @@ PLM_DEVICE_BLOCK pDevice) {
 /* Return:                                                                    */
 /*    LM_STATUS_SUCCESS                                                       */
 /******************************************************************************/
 /* Return:                                                                    */
 /*    LM_STATUS_SUCCESS                                                       */
 /******************************************************************************/

-LM_STATUS
-LM_ServiceInterrupts(
-    PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_ServiceInterrupts (PLM_DEVICE_BLOCK pDevice)

 {
 {

-    LM_UINT32 Value32;
-    int ServicePhyInt = FALSE;
-
-    /* Setup the phy chip whenever the link status changes. */
-    if(pDevice->LinkChngMode == T3_LINK_CHNG_MODE_USE_STATUS_REG)
-    {
-       Value32 = REG_RD(pDevice, MacCtrl.Status);
-       if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT)
-       {
-           if (Value32 & MAC_STATUS_MI_INTERRUPT)
-           {
-               ServicePhyInt = TRUE;
-           }
-       }
-       else if(Value32 & MAC_STATUS_LINK_STATE_CHANGED)
-       {
-           ServicePhyInt = TRUE;
-       }
-    }
-    else
-    {
-       if(pDevice->pStatusBlkVirt->Status & STATUS_BLOCK_LINK_CHANGED_STATUS)
-       {
-           pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
-               (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS);
-           ServicePhyInt = TRUE;
+       LM_UINT32 Value32;
+       int ServicePhyInt = FALSE;
+
+       /* Setup the phy chip whenever the link status changes. */
+       if (pDevice->LinkChngMode == T3_LINK_CHNG_MODE_USE_STATUS_REG) {
+               Value32 = REG_RD (pDevice, MacCtrl.Status);
+               if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) {
+                       if (Value32 & MAC_STATUS_MI_INTERRUPT) {
+                               ServicePhyInt = TRUE;
+                       }
+               } else if (Value32 & MAC_STATUS_LINK_STATE_CHANGED) {
+                       ServicePhyInt = TRUE;
+               }
+       } else {
+               if (pDevice->pStatusBlkVirt->
+                   Status & STATUS_BLOCK_LINK_CHANGED_STATUS) {
+                       pDevice->pStatusBlkVirt->Status =
+                           STATUS_BLOCK_UPDATED | (pDevice->pStatusBlkVirt->
+                                                   Status &
+                                                   ~STATUS_BLOCK_LINK_CHANGED_STATUS);
+                       ServicePhyInt = TRUE;
+               }

        }
        }

-    }

 #if INCLUDE_TBI_SUPPORT
 #if INCLUDE_TBI_SUPPORT

-    if (pDevice->IgnoreTbiLinkChange == TRUE)
-    {
-       ServicePhyInt = FALSE;
-    }
+       if (pDevice->IgnoreTbiLinkChange == TRUE) {
+               ServicePhyInt = FALSE;
+       }

 #endif
 #endif

-    if (ServicePhyInt == TRUE)
-    {
-       LM_SetupPhy(pDevice);
-    }
-
-    /* Service receive and transmit interrupts. */
-    LM_ServiceRxInterrupt(pDevice);
-    LM_ServiceTxInterrupt(pDevice);
+       if (ServicePhyInt == TRUE) {
+               LM_SetupPhy (pDevice);
+       }

 
 

-    /* No spinlock for this queue since this routine is serialized. */
-    if(!QQ_Empty(&pDevice->RxPacketReceivedQ.Container))
-    {
-       /* Indicate receive packets. */
-       MM_IndicateRxPackets(pDevice);
-       /*       LM_QueueRxPackets(pDevice); */
-    }
+       /* Service receive and transmit interrupts. */
+       LM_ServiceRxInterrupt (pDevice);
+       LM_ServiceTxInterrupt (pDevice);

 
 

-    /* No spinlock for this queue since this routine is serialized. */
-    if(!QQ_Empty(&pDevice->TxPacketXmittedQ.Container))
-    {
-       MM_IndicateTxPackets(pDevice);
-    }
+       /* No spinlock for this queue since this routine is serialized. */
+       if (!QQ_Empty (&pDevice->RxPacketReceivedQ.Container)) {
+               /* Indicate receive packets. */
+               MM_IndicateRxPackets (pDevice);
+               /*       LM_QueueRxPackets(pDevice); */
+       }

 
 

-    return LM_STATUS_SUCCESS;
-} /* LM_ServiceInterrupts */
+       /* No spinlock for this queue since this routine is serialized. */
+       if (!QQ_Empty (&pDevice->TxPacketXmittedQ.Container)) {
+               MM_IndicateTxPackets (pDevice);
+       }

 
 

+       return LM_STATUS_SUCCESS;
+}                              /* LM_ServiceInterrupts */

 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-LM_STATUS
-LM_MulticastAdd(
-PLM_DEVICE_BLOCK pDevice,
-PLM_UINT8 pMcAddress) {
-    PLM_UINT8 pEntry;
-    LM_UINT32 j;
-
-    pEntry = pDevice->McTable[0];
-    for(j = 0; j < pDevice->McEntryCount; j++)
-    {
-       if(IS_ETH_ADDRESS_EQUAL(pEntry, pMcAddress))
-       {
-           /* Found a match, increment the instance count. */
-           pEntry[LM_MC_INSTANCE_COUNT_INDEX] += 1;
+LM_STATUS LM_MulticastAdd (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress)
+{
+       PLM_UINT8 pEntry;
+       LM_UINT32 j;

 
 

-           return LM_STATUS_SUCCESS;
-       }
+       pEntry = pDevice->McTable[0];
+       for (j = 0; j < pDevice->McEntryCount; j++) {
+               if (IS_ETH_ADDRESS_EQUAL (pEntry, pMcAddress)) {
+                       /* Found a match, increment the instance count. */
+                       pEntry[LM_MC_INSTANCE_COUNT_INDEX] += 1;

 
 

-       pEntry += LM_MC_ENTRY_SIZE;
-    }
+                       return LM_STATUS_SUCCESS;
+               }

 
 

-    if(pDevice->McEntryCount >= LM_MAX_MC_TABLE_SIZE)
-    {
-       return LM_STATUS_FAILURE;
-    }
+               pEntry += LM_MC_ENTRY_SIZE;
+       }

 
 

-    pEntry = pDevice->McTable[pDevice->McEntryCount];
+       if (pDevice->McEntryCount >= LM_MAX_MC_TABLE_SIZE) {
+               return LM_STATUS_FAILURE;
+       }

 
 

-    COPY_ETH_ADDRESS(pMcAddress, pEntry);
-    pEntry[LM_MC_INSTANCE_COUNT_INDEX] = 1;
+       pEntry = pDevice->McTable[pDevice->McEntryCount];

 
 

-    pDevice->McEntryCount++;
+       COPY_ETH_ADDRESS (pMcAddress, pEntry);
+       pEntry[LM_MC_INSTANCE_COUNT_INDEX] = 1;

 
 

-    LM_SetReceiveMask(pDevice, pDevice->ReceiveMask | LM_ACCEPT_MULTICAST);
+       pDevice->McEntryCount++;

 
 

-    return LM_STATUS_SUCCESS;
-} /* LM_MulticastAdd */
+       LM_SetReceiveMask (pDevice, pDevice->ReceiveMask | LM_ACCEPT_MULTICAST);

 
 

+       return LM_STATUS_SUCCESS;
+}                              /* LM_MulticastAdd */

 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-LM_STATUS
-LM_MulticastDel(
-PLM_DEVICE_BLOCK pDevice,
-PLM_UINT8 pMcAddress) {
-    PLM_UINT8 pEntry;
-    LM_UINT32 j;
-
-    pEntry = pDevice->McTable[0];
-    for(j = 0; j < pDevice->McEntryCount; j++)
-    {
-       if(IS_ETH_ADDRESS_EQUAL(pEntry, pMcAddress))
-       {
-           /* Found a match, decrement the instance count. */
-           pEntry[LM_MC_INSTANCE_COUNT_INDEX] -= 1;
-
-           /* No more instance left, remove the address from the table. */
-           /* Move the last entry in the table to the delete slot. */
-           if(pEntry[LM_MC_INSTANCE_COUNT_INDEX] == 0 &&
-               pDevice->McEntryCount > 1)
-           {
-
-               COPY_ETH_ADDRESS(
-                   pDevice->McTable[pDevice->McEntryCount-1], pEntry);
-               pEntry[LM_MC_INSTANCE_COUNT_INDEX] =
-                   pDevice->McTable[pDevice->McEntryCount-1]
-                   [LM_MC_INSTANCE_COUNT_INDEX];
-           }
-           pDevice->McEntryCount--;
+LM_STATUS LM_MulticastDel (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMcAddress)
+{
+       PLM_UINT8 pEntry;
+       LM_UINT32 j;
+
+       pEntry = pDevice->McTable[0];
+       for (j = 0; j < pDevice->McEntryCount; j++) {
+               if (IS_ETH_ADDRESS_EQUAL (pEntry, pMcAddress)) {
+                       /* Found a match, decrement the instance count. */
+                       pEntry[LM_MC_INSTANCE_COUNT_INDEX] -= 1;
+
+                       /* No more instance left, remove the address from the table. */
+                       /* Move the last entry in the table to the delete slot. */
+                       if (pEntry[LM_MC_INSTANCE_COUNT_INDEX] == 0 &&
+                           pDevice->McEntryCount > 1) {
+
+                               COPY_ETH_ADDRESS (pDevice->
+                                                 McTable[pDevice->
+                                                         McEntryCount - 1],
+                                                 pEntry);
+                               pEntry[LM_MC_INSTANCE_COUNT_INDEX] =
+                                   pDevice->McTable[pDevice->McEntryCount - 1]
+                                   [LM_MC_INSTANCE_COUNT_INDEX];
+                       }
+                       pDevice->McEntryCount--;
+
+                       /* Update the receive mask if the table is empty. */
+                       if (pDevice->McEntryCount == 0) {
+                               LM_SetReceiveMask (pDevice,
+                                                  pDevice->
+                                                  ReceiveMask &
+                                                  ~LM_ACCEPT_MULTICAST);
+                       }

 
 

-           /* Update the receive mask if the table is empty. */
-           if(pDevice->McEntryCount == 0)
-           {
-               LM_SetReceiveMask(pDevice,
-                   pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST);
-           }
+                       return LM_STATUS_SUCCESS;
+               }

 
 

-           return LM_STATUS_SUCCESS;
+               pEntry += LM_MC_ENTRY_SIZE;

        }
 
        }
 

-       pEntry += LM_MC_ENTRY_SIZE;
-    }
-
-    return LM_STATUS_FAILURE;
-} /* LM_MulticastDel */
-
+       return LM_STATUS_FAILURE;
+}                              /* LM_MulticastDel */

 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-LM_STATUS
-LM_MulticastClear(
-PLM_DEVICE_BLOCK pDevice) {
-    pDevice->McEntryCount = 0;
-
-    LM_SetReceiveMask(pDevice, pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST);
+LM_STATUS LM_MulticastClear (PLM_DEVICE_BLOCK pDevice)
+{
+       pDevice->McEntryCount = 0;

 
 

-    return LM_STATUS_SUCCESS;
-} /* LM_MulticastClear */
+       LM_SetReceiveMask (pDevice,
+                          pDevice->ReceiveMask & ~LM_ACCEPT_MULTICAST);

 
 

+       return LM_STATUS_SUCCESS;
+}                              /* LM_MulticastClear */

 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-LM_STATUS
-LM_SetMacAddress(
-    PLM_DEVICE_BLOCK pDevice,
-    PLM_UINT8 pMacAddress)
+LM_STATUS LM_SetMacAddress (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pMacAddress)

 {
 {

-    LM_UINT32 j;
-
-    for(j = 0; j < 4; j++)
-    {
-       REG_WR(pDevice, MacCtrl.MacAddr[j].High,
-           (pMacAddress[0] << 8) | pMacAddress[1]);
-       REG_WR(pDevice, MacCtrl.MacAddr[j].Low,
-           (pMacAddress[2] << 24) | (pMacAddress[3] << 16) |
-           (pMacAddress[4] << 8) | pMacAddress[5]);
-    }
-
-    return LM_STATUS_SUCCESS;
-}
+       LM_UINT32 j;
+
+       for (j = 0; j < 4; j++) {
+               REG_WR (pDevice, MacCtrl.MacAddr[j].High,
+                       (pMacAddress[0] << 8) | pMacAddress[1]);
+               REG_WR (pDevice, MacCtrl.MacAddr[j].Low,
+                       (pMacAddress[2] << 24) | (pMacAddress[3] << 16) |
+                       (pMacAddress[4] << 8) | pMacAddress[5]);
+       }

 
 

+       return LM_STATUS_SUCCESS;
+}

 
 /******************************************************************************/
 /* Description:                                                               */
 
 /******************************************************************************/
 /* Description:                                                               */


@@ -4182,93 +3858,93 @@ LM_SetMacAddress(
 /*    None.                                                                   */
 /******************************************************************************/
 static LM_STATUS
 /*    None.                                                                   */
 /******************************************************************************/
 static LM_STATUS

-LM_TranslateRequestedMediaType(
-LM_REQUESTED_MEDIA_TYPE RequestedMediaType,
-PLM_MEDIA_TYPE pMediaType,
-PLM_LINE_SPEED pLineSpeed,
-PLM_DUPLEX_MODE pDuplexMode) {
-    *pMediaType = LM_MEDIA_TYPE_AUTO;
-    *pLineSpeed = LM_LINE_SPEED_UNKNOWN;
-    *pDuplexMode = LM_DUPLEX_MODE_UNKNOWN;
-
-    /* determine media type */
-    switch(RequestedMediaType) {
+LM_TranslateRequestedMediaType (LM_REQUESTED_MEDIA_TYPE RequestedMediaType,
+                               PLM_MEDIA_TYPE pMediaType,
+                               PLM_LINE_SPEED pLineSpeed,
+                               PLM_DUPLEX_MODE pDuplexMode)
+{
+       *pMediaType = LM_MEDIA_TYPE_AUTO;
+       *pLineSpeed = LM_LINE_SPEED_UNKNOWN;
+       *pDuplexMode = LM_DUPLEX_MODE_UNKNOWN;
+
+       /* determine media type */
+       switch (RequestedMediaType) {

        case LM_REQUESTED_MEDIA_TYPE_BNC:
        case LM_REQUESTED_MEDIA_TYPE_BNC:

-           *pMediaType = LM_MEDIA_TYPE_BNC;
-           *pLineSpeed = LM_LINE_SPEED_10MBPS;
-           *pDuplexMode = LM_DUPLEX_MODE_HALF;
-           break;
+               *pMediaType = LM_MEDIA_TYPE_BNC;
+               *pLineSpeed = LM_LINE_SPEED_10MBPS;
+               *pDuplexMode = LM_DUPLEX_MODE_HALF;
+               break;

 
        case LM_REQUESTED_MEDIA_TYPE_UTP_AUTO:
 
        case LM_REQUESTED_MEDIA_TYPE_UTP_AUTO:

-           *pMediaType = LM_MEDIA_TYPE_UTP;
-           break;
+               *pMediaType = LM_MEDIA_TYPE_UTP;
+               break;

 
        case LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS:
 
        case LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS:

-           *pMediaType = LM_MEDIA_TYPE_UTP;
-           *pLineSpeed = LM_LINE_SPEED_10MBPS;
-           *pDuplexMode = LM_DUPLEX_MODE_HALF;
-           break;
+               *pMediaType = LM_MEDIA_TYPE_UTP;
+               *pLineSpeed = LM_LINE_SPEED_10MBPS;
+               *pDuplexMode = LM_DUPLEX_MODE_HALF;
+               break;

 
        case LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX:
 
        case LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS_FULL_DUPLEX:

-           *pMediaType = LM_MEDIA_TYPE_UTP;
-           *pLineSpeed = LM_LINE_SPEED_10MBPS;
-           *pDuplexMode = LM_DUPLEX_MODE_FULL;
-           break;
+               *pMediaType = LM_MEDIA_TYPE_UTP;
+               *pLineSpeed = LM_LINE_SPEED_10MBPS;
+               *pDuplexMode = LM_DUPLEX_MODE_FULL;
+               break;

 
        case LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS:
 
        case LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS:

-           *pMediaType = LM_MEDIA_TYPE_UTP;
-           *pLineSpeed = LM_LINE_SPEED_100MBPS;
-           *pDuplexMode = LM_DUPLEX_MODE_HALF;
-           break;
+               *pMediaType = LM_MEDIA_TYPE_UTP;
+               *pLineSpeed = LM_LINE_SPEED_100MBPS;
+               *pDuplexMode = LM_DUPLEX_MODE_HALF;
+               break;

 
        case LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX:
 
        case LM_REQUESTED_MEDIA_TYPE_UTP_100MBPS_FULL_DUPLEX:

-           *pMediaType = LM_MEDIA_TYPE_UTP;
-           *pLineSpeed = LM_LINE_SPEED_100MBPS;
-           *pDuplexMode = LM_DUPLEX_MODE_FULL;
-           break;
+               *pMediaType = LM_MEDIA_TYPE_UTP;
+               *pLineSpeed = LM_LINE_SPEED_100MBPS;
+               *pDuplexMode = LM_DUPLEX_MODE_FULL;
+               break;

 
        case LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS:
 
        case LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS:

-           *pMediaType = LM_MEDIA_TYPE_UTP;
-           *pLineSpeed = LM_LINE_SPEED_1000MBPS;
-           *pDuplexMode = LM_DUPLEX_MODE_HALF;
-           break;
+               *pMediaType = LM_MEDIA_TYPE_UTP;
+               *pLineSpeed = LM_LINE_SPEED_1000MBPS;
+               *pDuplexMode = LM_DUPLEX_MODE_HALF;
+               break;

 
        case LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX:
 
        case LM_REQUESTED_MEDIA_TYPE_UTP_1000MBPS_FULL_DUPLEX:

-           *pMediaType = LM_MEDIA_TYPE_UTP;
-           *pLineSpeed = LM_LINE_SPEED_1000MBPS;
-           *pDuplexMode = LM_DUPLEX_MODE_FULL;
-           break;
+               *pMediaType = LM_MEDIA_TYPE_UTP;
+               *pLineSpeed = LM_LINE_SPEED_1000MBPS;
+               *pDuplexMode = LM_DUPLEX_MODE_FULL;
+               break;

 
        case LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS:
 
        case LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS:

-           *pMediaType = LM_MEDIA_TYPE_FIBER;
-           *pLineSpeed = LM_LINE_SPEED_100MBPS;
-           *pDuplexMode = LM_DUPLEX_MODE_HALF;
-           break;
+               *pMediaType = LM_MEDIA_TYPE_FIBER;
+               *pLineSpeed = LM_LINE_SPEED_100MBPS;
+               *pDuplexMode = LM_DUPLEX_MODE_HALF;
+               break;

 
        case LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS_FULL_DUPLEX:
 
        case LM_REQUESTED_MEDIA_TYPE_FIBER_100MBPS_FULL_DUPLEX:

-           *pMediaType = LM_MEDIA_TYPE_FIBER;
-           *pLineSpeed = LM_LINE_SPEED_100MBPS;
-           *pDuplexMode = LM_DUPLEX_MODE_FULL;
-           break;
+               *pMediaType = LM_MEDIA_TYPE_FIBER;
+               *pLineSpeed = LM_LINE_SPEED_100MBPS;
+               *pDuplexMode = LM_DUPLEX_MODE_FULL;
+               break;

 
        case LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS:
 
        case LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS:

-           *pMediaType = LM_MEDIA_TYPE_FIBER;
-           *pLineSpeed = LM_LINE_SPEED_1000MBPS;
-           *pDuplexMode = LM_DUPLEX_MODE_HALF;
-           break;
+               *pMediaType = LM_MEDIA_TYPE_FIBER;
+               *pLineSpeed = LM_LINE_SPEED_1000MBPS;
+               *pDuplexMode = LM_DUPLEX_MODE_HALF;
+               break;

 
        case LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX:
 
        case LM_REQUESTED_MEDIA_TYPE_FIBER_1000MBPS_FULL_DUPLEX:

-           *pMediaType = LM_MEDIA_TYPE_FIBER;
-           *pLineSpeed = LM_LINE_SPEED_1000MBPS;
-           *pDuplexMode = LM_DUPLEX_MODE_FULL;
-           break;
+               *pMediaType = LM_MEDIA_TYPE_FIBER;
+               *pLineSpeed = LM_LINE_SPEED_1000MBPS;
+               *pDuplexMode = LM_DUPLEX_MODE_FULL;
+               break;

 
        default:
 
        default:

-           break;
-    } /* switch */
+               break;
+       }                       /* switch */

 
 

-    return LM_STATUS_SUCCESS;
-} /* LM_TranslateRequestedMediaType */
+       return LM_STATUS_SUCCESS;
+}                              /* LM_TranslateRequestedMediaType */

 
 /******************************************************************************/
 /* Description:                                                               */
 
 /******************************************************************************/
 /* Description:                                                               */


@@ -4277,285 +3953,284 @@ PLM_DUPLEX_MODE pDuplexMode) {
 /*    LM_STATUS_LINK_ACTIVE                                                   */
 /*    LM_STATUS_LINK_DOWN                                                     */
 /******************************************************************************/
 /*    LM_STATUS_LINK_ACTIVE                                                   */
 /*    LM_STATUS_LINK_DOWN                                                     */
 /******************************************************************************/

-static LM_STATUS
-LM_InitBcm540xPhy(
-PLM_DEVICE_BLOCK pDevice)
+static LM_STATUS LM_InitBcm540xPhy (PLM_DEVICE_BLOCK pDevice)

 {
 {

-    LM_LINE_SPEED CurrentLineSpeed;
-    LM_DUPLEX_MODE CurrentDuplexMode;
-    LM_STATUS CurrentLinkStatus;
-    LM_UINT32 Value32;
-    LM_UINT32 j;
-
-#if 1  /* jmb: bugfix -- moved here, out of code that sets initial pwr state */
-    LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x2);
+       LM_LINE_SPEED CurrentLineSpeed;
+       LM_DUPLEX_MODE CurrentDuplexMode;
+       LM_STATUS CurrentLinkStatus;
+       LM_UINT32 Value32;
+       LM_UINT32 j;
+
+#if 1                          /* jmb: bugfix -- moved here, out of code that sets initial pwr state */
+       LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x2);

 #endif
 #endif

-    if((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID)
-    {
-       LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
-       LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
-
-       if(!pDevice->InitDone)
-       {
-           Value32 = 0;
-       }
-
-       if(!(Value32 & PHY_STATUS_LINK_PASS))
-       {
-           LM_WritePhy(pDevice, BCM5401_AUX_CTRL,  0x0c20);
+       if ((pDevice->PhyId & PHY_ID_MASK) == PHY_BCM5401_PHY_ID) {
+               LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
+               LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);

 
 

-           LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012);
-           LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804);
+               if (!pDevice->InitDone) {
+                       Value32 = 0;
+               }

 
 

-           LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013);
-           LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204);
+               if (!(Value32 & PHY_STATUS_LINK_PASS)) {
+                       LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x0c20);

 
 

-           LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
-           LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132);
+                       LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012);
+                       LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1804);

 
 

-           LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
-           LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232);
+                       LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013);
+                       LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x1204);

 
 

-           LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f);
-           LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20);
+                       LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
+                       LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0132);

 
 

-           LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
-           for(j = 0; j < 1000; j++)
-           {
-               MM_Wait(10);
+                       LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
+                       LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0232);

 
 

-               LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
-               if(Value32 & PHY_STATUS_LINK_PASS)
-               {
-                   MM_Wait(40);
-                   break;
-               }
-           }
+                       LM_WritePhy (pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f);
+                       LM_WritePhy (pDevice, BCM540X_DSP_RW_PORT, 0x0a20);

 
 

-           if((pDevice->PhyId & PHY_ID_REV_MASK) == PHY_BCM5401_B0_REV)
-           {
-               if(!(Value32 & PHY_STATUS_LINK_PASS) &&
-                   (pDevice->OldLineSpeed == LM_LINE_SPEED_1000MBPS))
-               {
-                   LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_PHY_RESET);
-                   for(j = 0; j < 100; j++)
-                   {
-                       MM_Wait(10);
+                       LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
+                       for (j = 0; j < 1000; j++) {
+                               MM_Wait (10);

 
 

-                       LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
-                       if(!(Value32 & PHY_CTRL_PHY_RESET))
-                       {
-                           MM_Wait(40);
-                           break;
+                               LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
+                               if (Value32 & PHY_STATUS_LINK_PASS) {
+                                       MM_Wait (40);
+                                       break;
+                               }

                        }
                        }

-                   }
-
-                   LM_WritePhy(pDevice, BCM5401_AUX_CTRL,  0x0c20);

 
 

-                   LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0012);
-                   LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1804);
-
-                   LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x0013);
-                   LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x1204);
-
-                   LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
-                   LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0132);
-
-                   LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x8006);
-                   LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0232);
-
-                   LM_WritePhy(pDevice, BCM540X_DSP_ADDRESS_REG, 0x201f);
-                   LM_WritePhy(pDevice, BCM540X_DSP_RW_PORT, 0x0a20);
+                       if ((pDevice->PhyId & PHY_ID_REV_MASK) ==
+                           PHY_BCM5401_B0_REV) {
+                               if (!(Value32 & PHY_STATUS_LINK_PASS)
+                                   && (pDevice->OldLineSpeed ==
+                                       LM_LINE_SPEED_1000MBPS)) {
+                                       LM_WritePhy (pDevice, PHY_CTRL_REG,
+                                                    PHY_CTRL_PHY_RESET);
+                                       for (j = 0; j < 100; j++) {
+                                               MM_Wait (10);
+
+                                               LM_ReadPhy (pDevice,
+                                                           PHY_CTRL_REG,
+                                                           &Value32);
+                                               if (!
+                                                   (Value32 &
+                                                    PHY_CTRL_PHY_RESET)) {
+                                                       MM_Wait (40);
+                                                       break;
+                                               }
+                                       }
+
+                                       LM_WritePhy (pDevice, BCM5401_AUX_CTRL,
+                                                    0x0c20);
+
+                                       LM_WritePhy (pDevice,
+                                                    BCM540X_DSP_ADDRESS_REG,
+                                                    0x0012);
+                                       LM_WritePhy (pDevice,
+                                                    BCM540X_DSP_RW_PORT,
+                                                    0x1804);
+
+                                       LM_WritePhy (pDevice,
+                                                    BCM540X_DSP_ADDRESS_REG,
+                                                    0x0013);
+                                       LM_WritePhy (pDevice,
+                                                    BCM540X_DSP_RW_PORT,
+                                                    0x1204);
+
+                                       LM_WritePhy (pDevice,
+                                                    BCM540X_DSP_ADDRESS_REG,
+                                                    0x8006);
+                                       LM_WritePhy (pDevice,
+                                                    BCM540X_DSP_RW_PORT,
+                                                    0x0132);
+
+                                       LM_WritePhy (pDevice,
+                                                    BCM540X_DSP_ADDRESS_REG,
+                                                    0x8006);
+                                       LM_WritePhy (pDevice,
+                                                    BCM540X_DSP_RW_PORT,
+                                                    0x0232);
+
+                                       LM_WritePhy (pDevice,
+                                                    BCM540X_DSP_ADDRESS_REG,
+                                                    0x201f);
+                                       LM_WritePhy (pDevice,
+                                                    BCM540X_DSP_RW_PORT,
+                                                    0x0a20);
+                               }
+                       }
+               }
+       } else if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
+                  pDevice->ChipRevId == T3_CHIP_ID_5701_B0) {
+               /* Bug: 5701 A0, B0 TX CRC workaround. */
+               LM_WritePhy (pDevice, 0x15, 0x0a75);
+               LM_WritePhy (pDevice, 0x1c, 0x8c68);
+               LM_WritePhy (pDevice, 0x1c, 0x8d68);
+               LM_WritePhy (pDevice, 0x1c, 0x8c68);
+       }
+
+       /* Acknowledge interrupts. */
+       LM_ReadPhy (pDevice, BCM540X_INT_STATUS_REG, &Value32);
+       LM_ReadPhy (pDevice, BCM540X_INT_STATUS_REG, &Value32);
+
+       /* Configure the interrupt mask. */
+       if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) {
+               LM_WritePhy (pDevice, BCM540X_INT_MASK_REG,
+                            ~BCM540X_INT_LINK_CHANGE);
+       }
+
+       /* Configure PHY led mode. */
+       if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701 ||
+           (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700)) {
+               if (pDevice->LedMode == LED_MODE_THREE_LINK) {
+                       LM_WritePhy (pDevice, BCM540X_EXT_CTRL_REG,
+                                    BCM540X_EXT_CTRL_LINK3_LED_MODE);
+               } else {
+                       LM_WritePhy (pDevice, BCM540X_EXT_CTRL_REG, 0);

                }
                }

-           }
-       }
-    }
-    else if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
-       pDevice->ChipRevId == T3_CHIP_ID_5701_B0)
-    {
-       /* Bug: 5701 A0, B0 TX CRC workaround. */
-       LM_WritePhy(pDevice, 0x15, 0x0a75);
-       LM_WritePhy(pDevice, 0x1c, 0x8c68);
-       LM_WritePhy(pDevice, 0x1c, 0x8d68);
-       LM_WritePhy(pDevice, 0x1c, 0x8c68);
-    }
-
-    /* Acknowledge interrupts. */
-    LM_ReadPhy(pDevice, BCM540X_INT_STATUS_REG, &Value32);
-    LM_ReadPhy(pDevice, BCM540X_INT_STATUS_REG, &Value32);
-
-    /* Configure the interrupt mask. */
-    if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT)
-    {
-       LM_WritePhy(pDevice, BCM540X_INT_MASK_REG, ~BCM540X_INT_LINK_CHANGE);
-    }
-
-    /* Configure PHY led mode. */
-    if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701 ||
-       (T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700))
-    {
-       if(pDevice->LedMode == LED_MODE_THREE_LINK)
-       {
-           LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG,
-               BCM540X_EXT_CTRL_LINK3_LED_MODE);
-       }
-       else
-       {
-           LM_WritePhy(pDevice, BCM540X_EXT_CTRL_REG, 0);

        }
        }

-    }

 
 

-    CurrentLinkStatus = LM_STATUS_LINK_DOWN;
+       CurrentLinkStatus = LM_STATUS_LINK_DOWN;

 
 

-    /* Get current link and duplex mode. */
-    for(j = 0; j < 100; j++)
-    {
-       LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
-       LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
+       /* Get current link and duplex mode. */
+       for (j = 0; j < 100; j++) {
+               LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
+               LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);

 
 

-       if(Value32 & PHY_STATUS_LINK_PASS)
-       {
-           break;
+               if (Value32 & PHY_STATUS_LINK_PASS) {
+                       break;
+               }
+               MM_Wait (40);

        }
        }

-       MM_Wait(40);
-    }
-
-    if(Value32 & PHY_STATUS_LINK_PASS)
-    {
-
-       /* Determine the current line and duplex settings. */
-       LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32);
-       for(j = 0; j < 2000; j++)
-       {
-           MM_Wait(10);

 
 

-           LM_ReadPhy(pDevice, BCM540X_AUX_STATUS_REG, &Value32);
-           if(Value32)
-           {
-               break;
-           }
-       }
+       if (Value32 & PHY_STATUS_LINK_PASS) {

 
 

-       switch(Value32 & BCM540X_AUX_SPEED_MASK)
-       {
-           case BCM540X_AUX_10BASET_HD:
-               CurrentLineSpeed = LM_LINE_SPEED_10MBPS;
-               CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
-               break;
+               /* Determine the current line and duplex settings. */
+               LM_ReadPhy (pDevice, BCM540X_AUX_STATUS_REG, &Value32);
+               for (j = 0; j < 2000; j++) {
+                       MM_Wait (10);

 
 

-           case BCM540X_AUX_10BASET_FD:
-               CurrentLineSpeed = LM_LINE_SPEED_10MBPS;
-               CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
-               break;
+                       LM_ReadPhy (pDevice, BCM540X_AUX_STATUS_REG, &Value32);
+                       if (Value32) {
+                               break;
+                       }
+               }

 
 

-           case BCM540X_AUX_100BASETX_HD:
-               CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
-               CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
-               break;
+               switch (Value32 & BCM540X_AUX_SPEED_MASK) {
+               case BCM540X_AUX_10BASET_HD:
+                       CurrentLineSpeed = LM_LINE_SPEED_10MBPS;
+                       CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
+                       break;

 
 

-           case BCM540X_AUX_100BASETX_FD:
-               CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
-               CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
-               break;
+               case BCM540X_AUX_10BASET_FD:
+                       CurrentLineSpeed = LM_LINE_SPEED_10MBPS;
+                       CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
+                       break;

 
 

-           case BCM540X_AUX_100BASET_HD:
-               CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
-               CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
-               break;
+               case BCM540X_AUX_100BASETX_HD:
+                       CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
+                       CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
+                       break;

 
 

-           case BCM540X_AUX_100BASET_FD:
-               CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
-               CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
-               break;
+               case BCM540X_AUX_100BASETX_FD:
+                       CurrentLineSpeed = LM_LINE_SPEED_100MBPS;
+                       CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
+                       break;

 
 

-           default:
+               case BCM540X_AUX_100BASET_HD:
+                       CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
+                       CurrentDuplexMode = LM_DUPLEX_MODE_HALF;
+                       break;

 
 

-               CurrentLineSpeed = LM_LINE_SPEED_UNKNOWN;
-               CurrentDuplexMode = LM_DUPLEX_MODE_UNKNOWN;
-               break;
-       }
+               case BCM540X_AUX_100BASET_FD:
+                       CurrentLineSpeed = LM_LINE_SPEED_1000MBPS;
+                       CurrentDuplexMode = LM_DUPLEX_MODE_FULL;
+                       break;

 
 

-       /* Make sure we are in auto-neg mode. */
-       for (j = 0; j < 200; j++)
-       {
-           LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
-           if(Value32 && Value32 != 0x7fff)
-           {
-               break;
-           }
+               default:

 
 

-           if(Value32 == 0 && pDevice->RequestedMediaType ==
-               LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS)
-           {
-               break;
-           }
+                       CurrentLineSpeed = LM_LINE_SPEED_UNKNOWN;
+                       CurrentDuplexMode = LM_DUPLEX_MODE_UNKNOWN;
+                       break;
+               }

 
 

-           MM_Wait(10);
-       }
+               /* Make sure we are in auto-neg mode. */
+               for (j = 0; j < 200; j++) {
+                       LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32);
+                       if (Value32 && Value32 != 0x7fff) {
+                               break;
+                       }

 
 

-       /* Use the current line settings for "auto" mode. */
-       if(pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO ||
-           pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO)
-       {
-           if(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)
-           {
-               CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
+                       if (Value32 == 0 && pDevice->RequestedMediaType ==
+                           LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS) {
+                               break;
+                       }

 
 

-               /* We may be exiting low power mode and the link is in */
-               /* 10mb.  In this case, we need to restart autoneg. */
-               LM_ReadPhy(pDevice, BCM540X_1000BASET_CTRL_REG, &Value32);
-               pDevice->advertising1000 = Value32;
-               /* 5702FE supports 10/100Mb only. */
-               if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5703 ||
-                   pDevice->BondId != GRC_MISC_BD_ID_5702FE)
-               {
-                   if(!(Value32 & (BCM540X_AN_AD_1000BASET_HALF |
-                       BCM540X_AN_AD_1000BASET_FULL)))
-                   {
-                       CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
-                   }
-               }
-           }
-           else
-           {
-               CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
-           }
-       }
-       else
-       {
-           /* Force line settings. */
-           /* Use the current setting if it matches the user's requested */
-           /* setting. */
-           LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
-           if((pDevice->LineSpeed == CurrentLineSpeed) &&
-               (pDevice->DuplexMode == CurrentDuplexMode))
-           {
-               if ((pDevice->DisableAutoNeg &&
-                   !(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)) ||
-                   (!pDevice->DisableAutoNeg &&
-                   (Value32 & PHY_CTRL_AUTO_NEG_ENABLE)))
-               {
-                   CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
+                       MM_Wait (10);

                }
                }

-               else
-               {
-                   CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
+
+               /* Use the current line settings for "auto" mode. */
+               if (pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO
+                   || pDevice->RequestedMediaType ==
+                   LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) {
+                       if (Value32 & PHY_CTRL_AUTO_NEG_ENABLE) {
+                               CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
+
+                               /* We may be exiting low power mode and the link is in */
+                               /* 10mb.  In this case, we need to restart autoneg. */
+                               LM_ReadPhy (pDevice, BCM540X_1000BASET_CTRL_REG,
+                                           &Value32);
+                               pDevice->advertising1000 = Value32;
+                               /* 5702FE supports 10/100Mb only. */
+                               if (T3_ASIC_REV (pDevice->ChipRevId) !=
+                                   T3_ASIC_REV_5703
+                                   || pDevice->BondId !=
+                                   GRC_MISC_BD_ID_5702FE) {
+                                       if (!
+                                           (Value32 &
+                                            (BCM540X_AN_AD_1000BASET_HALF |
+                                             BCM540X_AN_AD_1000BASET_FULL))) {
+                                               CurrentLinkStatus =
+                                                   LM_STATUS_LINK_SETTING_MISMATCH;
+                                       }
+                               }
+                       } else {
+                               CurrentLinkStatus =
+                                   LM_STATUS_LINK_SETTING_MISMATCH;
+                       }
+               } else {
+                       /* Force line settings. */
+                       /* Use the current setting if it matches the user's requested */
+                       /* setting. */
+                       LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32);
+                       if ((pDevice->LineSpeed == CurrentLineSpeed) &&
+                           (pDevice->DuplexMode == CurrentDuplexMode)) {
+                               if ((pDevice->DisableAutoNeg &&
+                                    !(Value32 & PHY_CTRL_AUTO_NEG_ENABLE)) ||
+                                   (!pDevice->DisableAutoNeg &&
+                                    (Value32 & PHY_CTRL_AUTO_NEG_ENABLE))) {
+                                       CurrentLinkStatus =
+                                           LM_STATUS_LINK_ACTIVE;
+                               } else {
+                                       CurrentLinkStatus =
+                                           LM_STATUS_LINK_SETTING_MISMATCH;
+                               }
+                       } else {
+                               CurrentLinkStatus =
+                                   LM_STATUS_LINK_SETTING_MISMATCH;
+                       }

                }
                }

-           }
-           else
-           {
-               CurrentLinkStatus = LM_STATUS_LINK_SETTING_MISMATCH;
-           }
-       }

 
 

-       /* Save line settings. */
-       pDevice->LineSpeed = CurrentLineSpeed;
-       pDevice->DuplexMode = CurrentDuplexMode;
-       pDevice->MediaType = LM_MEDIA_TYPE_UTP;
-    }
+               /* Save line settings. */
+               pDevice->LineSpeed = CurrentLineSpeed;
+               pDevice->DuplexMode = CurrentDuplexMode;
+               pDevice->MediaType = LM_MEDIA_TYPE_UTP;
+       }

 
 

-    return CurrentLinkStatus;
-} /* LM_InitBcm540xPhy */
+       return CurrentLinkStatus;
+}                              /* LM_InitBcm540xPhy */

 
 /******************************************************************************/
 /* Description:                                                               */
 
 /******************************************************************************/
 /* Description:                                                               */


@@ -4563,83 +4238,69 @@ PLM_DEVICE_BLOCK pDevice)
 /* Return:                                                                    */
 /******************************************************************************/
 LM_STATUS
 /* Return:                                                                    */
 /******************************************************************************/
 LM_STATUS

-LM_SetFlowControl(
-    PLM_DEVICE_BLOCK pDevice,
-    LM_UINT32 LocalPhyAd,
-    LM_UINT32 RemotePhyAd)
+LM_SetFlowControl (PLM_DEVICE_BLOCK pDevice,
+                  LM_UINT32 LocalPhyAd, LM_UINT32 RemotePhyAd)

 {
 {

-    LM_FLOW_CONTROL FlowCap;
+       LM_FLOW_CONTROL FlowCap;

 
 

-    /* Resolve flow control. */
-    FlowCap = LM_FLOW_CONTROL_NONE;
+       /* Resolve flow control. */
+       FlowCap = LM_FLOW_CONTROL_NONE;

 
 

-    /* See Table 28B-3 of 802.3ab-1999 spec. */
-    if(pDevice->FlowControlCap & LM_FLOW_CONTROL_AUTO_PAUSE)
-    {
-       if(LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE)
-       {
-           if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE)
-           {
-               if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE)
-               {
-                   FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE |
-                       LM_FLOW_CONTROL_RECEIVE_PAUSE;
-               }
-               else if(RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE)
-               {
-                   FlowCap = LM_FLOW_CONTROL_RECEIVE_PAUSE;
-               }
-           }
-           else
-           {
-               if(RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE)
-               {
-                   FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE |
-                       LM_FLOW_CONTROL_RECEIVE_PAUSE;
-               }
-           }
-       }
-       else if(LocalPhyAd & PHY_AN_AD_ASYM_PAUSE)
-       {
-           if((RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) &&
-               (RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE))
-           {
-               FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE;
-           }
-       }
-    }
-    else
-    {
-       FlowCap = pDevice->FlowControlCap;
-    }
-
-    /* Enable/disable rx PAUSE. */
-    pDevice->RxMode &= ~RX_MODE_ENABLE_FLOW_CONTROL;
-    if(FlowCap & LM_FLOW_CONTROL_RECEIVE_PAUSE &&
-       (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE ||
-       pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE))
-    {
-       pDevice->FlowControl |= LM_FLOW_CONTROL_RECEIVE_PAUSE;
-       pDevice->RxMode |= RX_MODE_ENABLE_FLOW_CONTROL;
-
-    }
-    REG_WR(pDevice, MacCtrl.RxMode, pDevice->RxMode);
-
-    /* Enable/disable tx PAUSE. */
-    pDevice->TxMode &= ~TX_MODE_ENABLE_FLOW_CONTROL;
-    if(FlowCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE &&
-       (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE ||
-       pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE))
-    {
-       pDevice->FlowControl |= LM_FLOW_CONTROL_TRANSMIT_PAUSE;
-       pDevice->TxMode |= TX_MODE_ENABLE_FLOW_CONTROL;
-
-    }
-    REG_WR(pDevice, MacCtrl.TxMode, pDevice->TxMode);
-
-    return LM_STATUS_SUCCESS;
-}
+       /* See Table 28B-3 of 802.3ab-1999 spec. */
+       if (pDevice->FlowControlCap & LM_FLOW_CONTROL_AUTO_PAUSE) {
+               if (LocalPhyAd & PHY_AN_AD_PAUSE_CAPABLE) {
+                       if (LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) {
+                               if (RemotePhyAd &
+                                   PHY_LINK_PARTNER_PAUSE_CAPABLE) {
+                                       FlowCap =
+                                           LM_FLOW_CONTROL_TRANSMIT_PAUSE |
+                                           LM_FLOW_CONTROL_RECEIVE_PAUSE;
+                               } else if (RemotePhyAd &
+                                          PHY_LINK_PARTNER_ASYM_PAUSE) {
+                                       FlowCap = LM_FLOW_CONTROL_RECEIVE_PAUSE;
+                               }
+                       } else {
+                               if (RemotePhyAd &
+                                   PHY_LINK_PARTNER_PAUSE_CAPABLE) {
+                                       FlowCap =
+                                           LM_FLOW_CONTROL_TRANSMIT_PAUSE |
+                                           LM_FLOW_CONTROL_RECEIVE_PAUSE;
+                               }
+                       }
+               } else if (LocalPhyAd & PHY_AN_AD_ASYM_PAUSE) {
+                       if ((RemotePhyAd & PHY_LINK_PARTNER_PAUSE_CAPABLE) &&
+                           (RemotePhyAd & PHY_LINK_PARTNER_ASYM_PAUSE)) {
+                               FlowCap = LM_FLOW_CONTROL_TRANSMIT_PAUSE;
+                       }
+               }
+       } else {
+               FlowCap = pDevice->FlowControlCap;
+       }
+
+       /* Enable/disable rx PAUSE. */
+       pDevice->RxMode &= ~RX_MODE_ENABLE_FLOW_CONTROL;
+       if (FlowCap & LM_FLOW_CONTROL_RECEIVE_PAUSE &&
+           (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE ||
+            pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)) {
+               pDevice->FlowControl |= LM_FLOW_CONTROL_RECEIVE_PAUSE;
+               pDevice->RxMode |= RX_MODE_ENABLE_FLOW_CONTROL;
+
+       }
+       REG_WR (pDevice, MacCtrl.RxMode, pDevice->RxMode);
+
+       /* Enable/disable tx PAUSE. */
+       pDevice->TxMode &= ~TX_MODE_ENABLE_FLOW_CONTROL;
+       if (FlowCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE &&
+           (pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE ||
+            pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)) {
+               pDevice->FlowControl |= LM_FLOW_CONTROL_TRANSMIT_PAUSE;
+               pDevice->TxMode |= TX_MODE_ENABLE_FLOW_CONTROL;

 
 

+       }
+       REG_WR (pDevice, MacCtrl.TxMode, pDevice->TxMode);
+
+       return LM_STATUS_SUCCESS;
+}

 
 #if INCLUDE_TBI_SUPPORT
 /******************************************************************************/
 
 #if INCLUDE_TBI_SUPPORT
 /******************************************************************************/


@@ -4647,583 +4308,520 @@ LM_SetFlowControl(
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-STATIC LM_STATUS
-LM_InitBcm800xPhy(
-    PLM_DEVICE_BLOCK pDevice)
+STATIC LM_STATUS LM_InitBcm800xPhy (PLM_DEVICE_BLOCK pDevice)

 {
 {

-    LM_UINT32 Value32;
-    LM_UINT32 j;
+       LM_UINT32 Value32;
+       LM_UINT32 j;

 
 

-    Value32 = REG_RD(pDevice, MacCtrl.Status);
+       Value32 = REG_RD (pDevice, MacCtrl.Status);

 
 

-    /* Reset the SERDES during init and when we have link. */
-    if(!pDevice->InitDone || Value32 & MAC_STATUS_PCS_SYNCED)
-    {
-       /* Set PLL lock range. */
-       LM_WritePhy(pDevice, 0x16, 0x8007);
+       /* Reset the SERDES during init and when we have link. */
+       if (!pDevice->InitDone || Value32 & MAC_STATUS_PCS_SYNCED) {
+               /* Set PLL lock range. */
+               LM_WritePhy (pDevice, 0x16, 0x8007);

 
 

-       /* Software reset. */
-       LM_WritePhy(pDevice, 0x00, 0x8000);
+               /* Software reset. */
+               LM_WritePhy (pDevice, 0x00, 0x8000);

 
 

-       /* Wait for reset to complete. */
-       for(j = 0; j < 500; j++)
-       {
-           MM_Wait(10);
-       }
+               /* Wait for reset to complete. */
+               for (j = 0; j < 500; j++) {
+                       MM_Wait (10);
+               }

 
 

-       /* Config mode; seletct PMA/Ch 1 regs. */
-       LM_WritePhy(pDevice, 0x10, 0x8411);
+               /* Config mode; seletct PMA/Ch 1 regs. */
+               LM_WritePhy (pDevice, 0x10, 0x8411);

 
 

-       /* Enable auto-lock and comdet, select txclk for tx. */
-       LM_WritePhy(pDevice, 0x11, 0x0a10);
+               /* Enable auto-lock and comdet, select txclk for tx. */
+               LM_WritePhy (pDevice, 0x11, 0x0a10);

 
 

-       LM_WritePhy(pDevice, 0x18, 0x00a0);
-       LM_WritePhy(pDevice, 0x16, 0x41ff);
+               LM_WritePhy (pDevice, 0x18, 0x00a0);
+               LM_WritePhy (pDevice, 0x16, 0x41ff);

 
 

-       /* Assert and deassert POR. */
-       LM_WritePhy(pDevice, 0x13, 0x0400);
-       MM_Wait(40);
-       LM_WritePhy(pDevice, 0x13, 0x0000);
+               /* Assert and deassert POR. */
+               LM_WritePhy (pDevice, 0x13, 0x0400);
+               MM_Wait (40);
+               LM_WritePhy (pDevice, 0x13, 0x0000);

 
 

-       LM_WritePhy(pDevice, 0x11, 0x0a50);
-       MM_Wait(40);
-       LM_WritePhy(pDevice, 0x11, 0x0a10);
+               LM_WritePhy (pDevice, 0x11, 0x0a50);
+               MM_Wait (40);
+               LM_WritePhy (pDevice, 0x11, 0x0a10);

 
 

-       /* Delay for signal to stabilize. */
-       for(j = 0; j < 15000; j++)
-       {
-           MM_Wait(10);
-       }
+               /* Delay for signal to stabilize. */
+               for (j = 0; j < 15000; j++) {
+                       MM_Wait (10);
+               }

 
 

-       /* Deselect the channel register so we can read the PHY id later. */
-       LM_WritePhy(pDevice, 0x10, 0x8011);
-    }
+               /* Deselect the channel register so we can read the PHY id later. */
+               LM_WritePhy (pDevice, 0x10, 0x8011);
+       }

 
 

-    return LM_STATUS_SUCCESS;
+       return LM_STATUS_SUCCESS;

 }
 
 }
 

-

 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-STATIC LM_STATUS
-LM_SetupFiberPhy(
-    PLM_DEVICE_BLOCK pDevice)
+STATIC LM_STATUS LM_SetupFiberPhy (PLM_DEVICE_BLOCK pDevice)

 {
 {

-    LM_STATUS CurrentLinkStatus;
-    AUTONEG_STATUS AnStatus = 0;
-    LM_UINT32 Value32;
-    LM_UINT32 Cnt;
-    LM_UINT32 j, k;
+       LM_STATUS CurrentLinkStatus;
+       AUTONEG_STATUS AnStatus = 0;
+       LM_UINT32 Value32;
+       LM_UINT32 Cnt;
+       LM_UINT32 j, k;

 
 

-    pDevice->MacMode &= ~(MAC_MODE_HALF_DUPLEX | MAC_MODE_PORT_MODE_MASK);
+       pDevice->MacMode &= ~(MAC_MODE_HALF_DUPLEX | MAC_MODE_PORT_MODE_MASK);

 
 

-    /* Initialize the send_config register. */
-    REG_WR(pDevice, MacCtrl.TxAutoNeg, 0);
+       /* Initialize the send_config register. */
+       REG_WR (pDevice, MacCtrl.TxAutoNeg, 0);

 
 

-    /* Enable TBI and full duplex mode. */
-    pDevice->MacMode |= MAC_MODE_PORT_MODE_TBI;
-    REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
+       /* Enable TBI and full duplex mode. */
+       pDevice->MacMode |= MAC_MODE_PORT_MODE_TBI;
+       REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);

 
 

-    /* Initialize the BCM8002 SERDES PHY. */
-    switch(pDevice->PhyId & PHY_ID_MASK)
-    {
+       /* Initialize the BCM8002 SERDES PHY. */
+       switch (pDevice->PhyId & PHY_ID_MASK) {

        case PHY_BCM8002_PHY_ID:
        case PHY_BCM8002_PHY_ID:

-           LM_InitBcm800xPhy(pDevice);
-           break;
+               LM_InitBcm800xPhy (pDevice);
+               break;

 
        default:
 
        default:

-           break;
-    }
-
-    /* Enable link change interrupt. */
-    REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
-
-    /* Default to link down. */
-    CurrentLinkStatus = LM_STATUS_LINK_DOWN;
+               break;
+       }

 
 

-    /* Get the link status. */
-    Value32 = REG_RD(pDevice, MacCtrl.Status);
-    if(Value32 & MAC_STATUS_PCS_SYNCED)
-    {
-       if((pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO) ||
-           (pDevice->DisableAutoNeg == FALSE))
-       {
-           /* auto-negotiation mode. */
-           /* Initialize the autoneg default capaiblities. */
-           AutonegInit(&pDevice->AnInfo);
-
-           /* Set the context pointer to point to the main device structure. */
-           pDevice->AnInfo.pContext = pDevice;
-
-           /* Setup flow control advertisement register. */
-           Value32 = GetPhyAdFlowCntrlSettings(pDevice);
-           if(Value32 & PHY_AN_AD_PAUSE_CAPABLE)
-           {
-               pDevice->AnInfo.mr_adv_sym_pause = 1;
-           }
-           else
-           {
-               pDevice->AnInfo.mr_adv_sym_pause = 0;
-           }
-
-           if(Value32 & PHY_AN_AD_ASYM_PAUSE)
-           {
-               pDevice->AnInfo.mr_adv_asym_pause = 1;
-           }
-           else
-           {
-               pDevice->AnInfo.mr_adv_asym_pause = 0;
-           }
-
-           /* Try to autoneg up to six times. */
-           if (pDevice->IgnoreTbiLinkChange)
-           {
-               Cnt = 1;
-           }
-           else
-           {
-               Cnt = 6;
-           }
-           for (j = 0; j < Cnt; j++)
-           {
-               REG_WR(pDevice, MacCtrl.TxAutoNeg, 0);
-
-               Value32 = pDevice->MacMode & ~MAC_MODE_PORT_MODE_MASK;
-               REG_WR(pDevice, MacCtrl.Mode, Value32);
-               MM_Wait(20);
-
-               REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
-                   MAC_MODE_SEND_CONFIGS);
-
-               MM_Wait(20);
-
-               pDevice->AnInfo.State = AN_STATE_UNKNOWN;
-               pDevice->AnInfo.CurrentTime_us = 0;
-
-               REG_WR(pDevice, Grc.Timer, 0);
-               for(k = 0; (pDevice->AnInfo.CurrentTime_us < 75000) &&
-                   (k < 75000); k++)
-               {
-                   AnStatus = Autoneg8023z(&pDevice->AnInfo);
-
-                   if((AnStatus == AUTONEG_STATUS_DONE) ||
-                       (AnStatus == AUTONEG_STATUS_FAILED))
-                   {
-                       break;
-                   }
+       /* Enable link change interrupt. */
+       REG_WR (pDevice, MacCtrl.MacEvent,
+               MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);

 
 

-                   pDevice->AnInfo.CurrentTime_us = REG_RD(pDevice, Grc.Timer);
+       /* Default to link down. */
+       CurrentLinkStatus = LM_STATUS_LINK_DOWN;

 
 

-               }
-               if((AnStatus == AUTONEG_STATUS_DONE) ||
-                   (AnStatus == AUTONEG_STATUS_FAILED))
-               {
-                   break;
-               }
-               if (j >= 1)
-               {
-                   if (!(REG_RD(pDevice, MacCtrl.Status) &
-                       MAC_STATUS_PCS_SYNCED)) {
-                       break;
-                   }
-               }
-           }
+       /* Get the link status. */
+       Value32 = REG_RD (pDevice, MacCtrl.Status);
+       if (Value32 & MAC_STATUS_PCS_SYNCED) {
+               if ((pDevice->RequestedMediaType ==
+                    LM_REQUESTED_MEDIA_TYPE_AUTO)
+                   || (pDevice->DisableAutoNeg == FALSE)) {
+                       /* auto-negotiation mode. */
+                       /* Initialize the autoneg default capaiblities. */
+                       AutonegInit (&pDevice->AnInfo);
+
+                       /* Set the context pointer to point to the main device structure. */
+                       pDevice->AnInfo.pContext = pDevice;
+
+                       /* Setup flow control advertisement register. */
+                       Value32 = GetPhyAdFlowCntrlSettings (pDevice);
+                       if (Value32 & PHY_AN_AD_PAUSE_CAPABLE) {
+                               pDevice->AnInfo.mr_adv_sym_pause = 1;
+                       } else {
+                               pDevice->AnInfo.mr_adv_sym_pause = 0;
+                       }

 
 

-           /* Stop sending configs. */
-           MM_AnTxIdle(&pDevice->AnInfo);
+                       if (Value32 & PHY_AN_AD_ASYM_PAUSE) {
+                               pDevice->AnInfo.mr_adv_asym_pause = 1;
+                       } else {
+                               pDevice->AnInfo.mr_adv_asym_pause = 0;
+                       }

 
 

-           /* Resolve flow control settings. */
-           if((AnStatus == AUTONEG_STATUS_DONE) &&
-               pDevice->AnInfo.mr_an_complete && pDevice->AnInfo.mr_link_ok &&
-               pDevice->AnInfo.mr_lp_adv_full_duplex)
-               {
-               LM_UINT32 RemotePhyAd;
-               LM_UINT32 LocalPhyAd;
+                       /* Try to autoneg up to six times. */
+                       if (pDevice->IgnoreTbiLinkChange) {
+                               Cnt = 1;
+                       } else {
+                               Cnt = 6;
+                       }
+                       for (j = 0; j < Cnt; j++) {
+                               REG_WR (pDevice, MacCtrl.TxAutoNeg, 0);
+
+                               Value32 =
+                                   pDevice->MacMode & ~MAC_MODE_PORT_MODE_MASK;
+                               REG_WR (pDevice, MacCtrl.Mode, Value32);
+                               MM_Wait (20);
+
+                               REG_WR (pDevice, MacCtrl.Mode,
+                                       pDevice->
+                                       MacMode | MAC_MODE_SEND_CONFIGS);
+
+                               MM_Wait (20);
+
+                               pDevice->AnInfo.State = AN_STATE_UNKNOWN;
+                               pDevice->AnInfo.CurrentTime_us = 0;
+
+                               REG_WR (pDevice, Grc.Timer, 0);
+                               for (k = 0;
+                                    (pDevice->AnInfo.CurrentTime_us < 75000)
+                                    && (k < 75000); k++) {
+                                       AnStatus =
+                                           Autoneg8023z (&pDevice->AnInfo);
+
+                                       if ((AnStatus == AUTONEG_STATUS_DONE) ||
+                                           (AnStatus == AUTONEG_STATUS_FAILED))
+                                       {
+                                               break;
+                                       }
+
+                                       pDevice->AnInfo.CurrentTime_us =
+                                           REG_RD (pDevice, Grc.Timer);
+
+                               }
+                               if ((AnStatus == AUTONEG_STATUS_DONE) ||
+                                   (AnStatus == AUTONEG_STATUS_FAILED)) {
+                                       break;
+                               }
+                               if (j >= 1) {
+                                       if (!(REG_RD (pDevice, MacCtrl.Status) &
+                                             MAC_STATUS_PCS_SYNCED)) {
+                                               break;
+                                       }
+                               }
+                       }

 
 

-               LocalPhyAd = 0;
-               if(pDevice->AnInfo.mr_adv_sym_pause)
-               {
-                   LocalPhyAd |= PHY_AN_AD_PAUSE_CAPABLE;
+                       /* Stop sending configs. */
+                       MM_AnTxIdle (&pDevice->AnInfo);
+
+                       /* Resolve flow control settings. */
+                       if ((AnStatus == AUTONEG_STATUS_DONE) &&
+                           pDevice->AnInfo.mr_an_complete
+                           && pDevice->AnInfo.mr_link_ok
+                           && pDevice->AnInfo.mr_lp_adv_full_duplex) {
+                               LM_UINT32 RemotePhyAd;
+                               LM_UINT32 LocalPhyAd;
+
+                               LocalPhyAd = 0;
+                               if (pDevice->AnInfo.mr_adv_sym_pause) {
+                                       LocalPhyAd |= PHY_AN_AD_PAUSE_CAPABLE;
+                               }
+
+                               if (pDevice->AnInfo.mr_adv_asym_pause) {
+                                       LocalPhyAd |= PHY_AN_AD_ASYM_PAUSE;
+                               }
+
+                               RemotePhyAd = 0;
+                               if (pDevice->AnInfo.mr_lp_adv_sym_pause) {
+                                       RemotePhyAd |=
+                                           PHY_LINK_PARTNER_PAUSE_CAPABLE;
+                               }
+
+                               if (pDevice->AnInfo.mr_lp_adv_asym_pause) {
+                                       RemotePhyAd |=
+                                           PHY_LINK_PARTNER_ASYM_PAUSE;
+                               }
+
+                               LM_SetFlowControl (pDevice, LocalPhyAd,
+                                                  RemotePhyAd);
+
+                               CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
+                       }
+                       for (j = 0; j < 30; j++) {
+                               MM_Wait (20);
+                               REG_WR (pDevice, MacCtrl.Status,
+                                       MAC_STATUS_SYNC_CHANGED |
+                                       MAC_STATUS_CFG_CHANGED);
+                               MM_Wait (20);
+                               if ((REG_RD (pDevice, MacCtrl.Status) &
+                                    (MAC_STATUS_SYNC_CHANGED |
+                                     MAC_STATUS_CFG_CHANGED)) == 0)
+                                       break;
+                       }
+                       if (pDevice->PollTbiLink) {
+                               Value32 = REG_RD (pDevice, MacCtrl.Status);
+                               if (Value32 & MAC_STATUS_RECEIVING_CFG) {
+                                       pDevice->IgnoreTbiLinkChange = TRUE;
+                               } else {
+                                       pDevice->IgnoreTbiLinkChange = FALSE;
+                               }
+                       }
+                       Value32 = REG_RD (pDevice, MacCtrl.Status);
+                       if (CurrentLinkStatus == LM_STATUS_LINK_DOWN &&
+                           (Value32 & MAC_STATUS_PCS_SYNCED) &&
+                           ((Value32 & MAC_STATUS_RECEIVING_CFG) == 0)) {
+                               CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
+                       }
+               } else {
+                       /* We are forcing line speed. */
+                       pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE;
+                       LM_SetFlowControl (pDevice, 0, 0);
+
+                       CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
+                       REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode |
+                               MAC_MODE_SEND_CONFIGS);

                }
                }

+       }
+       /* Set the link polarity bit. */
+       pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
+       REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);

 
 

-               if(pDevice->AnInfo.mr_adv_asym_pause)
-               {
-                   LocalPhyAd |= PHY_AN_AD_ASYM_PAUSE;
-               }
+       pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
+           (pDevice->pStatusBlkVirt->
+            Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS);

 
 

-               RemotePhyAd = 0;
-               if(pDevice->AnInfo.mr_lp_adv_sym_pause)
-               {
-                   RemotePhyAd |= PHY_LINK_PARTNER_PAUSE_CAPABLE;
-               }
+       for (j = 0; j < 100; j++) {
+               REG_WR (pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
+                       MAC_STATUS_CFG_CHANGED);
+               MM_Wait (5);
+               if ((REG_RD (pDevice, MacCtrl.Status) &
+                    (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0)
+                       break;
+       }

 
 

-               if(pDevice->AnInfo.mr_lp_adv_asym_pause)
-               {
-                   RemotePhyAd |= PHY_LINK_PARTNER_ASYM_PAUSE;
+       Value32 = REG_RD (pDevice, MacCtrl.Status);
+       if ((Value32 & MAC_STATUS_PCS_SYNCED) == 0) {
+               CurrentLinkStatus = LM_STATUS_LINK_DOWN;
+               if (pDevice->DisableAutoNeg == FALSE) {
+                       REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode |
+                               MAC_MODE_SEND_CONFIGS);
+                       MM_Wait (1);
+                       REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);

                }
                }

+       }

 
 

-               LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd);
+       /* Initialize the current link status. */
+       if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) {
+               pDevice->LineSpeed = LM_LINE_SPEED_1000MBPS;
+               pDevice->DuplexMode = LM_DUPLEX_MODE_FULL;
+               REG_WR (pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED |
+                       LED_CTRL_1000MBPS_LED_ON);
+       } else {
+               pDevice->LineSpeed = LM_LINE_SPEED_UNKNOWN;
+               pDevice->DuplexMode = LM_DUPLEX_MODE_UNKNOWN;
+               REG_WR (pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED |
+                       LED_CTRL_OVERRIDE_TRAFFIC_LED);
+       }

 
 

-               CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
-           }
-           for (j = 0; j < 30; j++)
-           {
-               MM_Wait(20);
-               REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
-                   MAC_STATUS_CFG_CHANGED);
-               MM_Wait(20);
-               if ((REG_RD(pDevice, MacCtrl.Status) &
-                   (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0)
-                   break;
-           }
-           if (pDevice->PollTbiLink)
-           {
-               Value32 = REG_RD(pDevice, MacCtrl.Status);
-               if (Value32 & MAC_STATUS_RECEIVING_CFG)
-               {
-                   pDevice->IgnoreTbiLinkChange = TRUE;
-               }
-               else
-               {
-                   pDevice->IgnoreTbiLinkChange = FALSE;
-               }
-           }
-           Value32 = REG_RD(pDevice, MacCtrl.Status);
-           if (CurrentLinkStatus == LM_STATUS_LINK_DOWN &&
-                (Value32 & MAC_STATUS_PCS_SYNCED) &&
-                ((Value32 & MAC_STATUS_RECEIVING_CFG) == 0))
-           {
-               CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
-           }
+       /* Indicate link status. */
+       if (pDevice->LinkStatus != CurrentLinkStatus) {
+               pDevice->LinkStatus = CurrentLinkStatus;
+               MM_IndicateStatus (pDevice, CurrentLinkStatus);

        }
        }

-       else
-       {
-           /* We are forcing line speed. */
-           pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE;
-           LM_SetFlowControl(pDevice, 0, 0);
-
-           CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
-           REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
-               MAC_MODE_SEND_CONFIGS);
-       }
-    }
-    /* Set the link polarity bit. */
-    pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
-    REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
-
-    pDevice->pStatusBlkVirt->Status = STATUS_BLOCK_UPDATED |
-       (pDevice->pStatusBlkVirt->Status & ~STATUS_BLOCK_LINK_CHANGED_STATUS);
-
-    for (j = 0; j < 100; j++)
-    {
-       REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
-           MAC_STATUS_CFG_CHANGED);
-       MM_Wait(5);
-       if ((REG_RD(pDevice, MacCtrl.Status) &
-           (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED)) == 0)
-           break;
-    }
-
-    Value32 = REG_RD(pDevice, MacCtrl.Status);
-    if((Value32 & MAC_STATUS_PCS_SYNCED) == 0)
-    {
-       CurrentLinkStatus = LM_STATUS_LINK_DOWN;
-       if (pDevice->DisableAutoNeg == FALSE)
-       {
-           REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode |
-               MAC_MODE_SEND_CONFIGS);
-           MM_Wait(1);
-           REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
-       }
-    }
-
-    /* Initialize the current link status. */
-    if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
-    {
-       pDevice->LineSpeed = LM_LINE_SPEED_1000MBPS;
-       pDevice->DuplexMode = LM_DUPLEX_MODE_FULL;
-       REG_WR(pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED |
-           LED_CTRL_1000MBPS_LED_ON);
-    }
-    else
-    {
-       pDevice->LineSpeed = LM_LINE_SPEED_UNKNOWN;
-       pDevice->DuplexMode = LM_DUPLEX_MODE_UNKNOWN;
-       REG_WR(pDevice, MacCtrl.LedCtrl, LED_CTRL_OVERRIDE_LINK_LED |
-           LED_CTRL_OVERRIDE_TRAFFIC_LED);
-    }
-
-    /* Indicate link status. */
-    if (pDevice->LinkStatus != CurrentLinkStatus) {
-       pDevice->LinkStatus = CurrentLinkStatus;
-       MM_IndicateStatus(pDevice, CurrentLinkStatus);
-    }
-
-    return LM_STATUS_SUCCESS;
-}
-#endif /* INCLUDE_TBI_SUPPORT */

 
 

+       return LM_STATUS_SUCCESS;
+}
+#endif                         /* INCLUDE_TBI_SUPPORT */

 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-LM_STATUS
-LM_SetupCopperPhy(
-    PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_SetupCopperPhy (PLM_DEVICE_BLOCK pDevice)

 {
 {

-    LM_STATUS CurrentLinkStatus;
-    LM_UINT32 Value32;
+       LM_STATUS CurrentLinkStatus;
+       LM_UINT32 Value32;

 
 

-    /* Assume there is not link first. */
-    CurrentLinkStatus = LM_STATUS_LINK_DOWN;
+       /* Assume there is not link first. */
+       CurrentLinkStatus = LM_STATUS_LINK_DOWN;

 
 

-    /* Disable phy link change attention. */
-    REG_WR(pDevice, MacCtrl.MacEvent, 0);
+       /* Disable phy link change attention. */
+       REG_WR (pDevice, MacCtrl.MacEvent, 0);

 
 

-    /* Clear link change attention. */
-    REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
-       MAC_STATUS_CFG_CHANGED);
+       /* Clear link change attention. */
+       REG_WR (pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
+               MAC_STATUS_CFG_CHANGED);

 
 

-    /* Disable auto-polling for the moment. */
-    pDevice->MiMode = 0xc0000;
-    REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
-    MM_Wait(40);
+       /* Disable auto-polling for the moment. */
+       pDevice->MiMode = 0xc0000;
+       REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
+       MM_Wait (40);

 
 

-    /* Determine the requested line speed and duplex. */
-    pDevice->OldLineSpeed = pDevice->LineSpeed;
-    LM_TranslateRequestedMediaType(pDevice->RequestedMediaType,
-       &pDevice->MediaType, &pDevice->LineSpeed, &pDevice->DuplexMode);
+       /* Determine the requested line speed and duplex. */
+       pDevice->OldLineSpeed = pDevice->LineSpeed;
+       LM_TranslateRequestedMediaType (pDevice->RequestedMediaType,
+                                       &pDevice->MediaType,
+                                       &pDevice->LineSpeed,
+                                       &pDevice->DuplexMode);

 
 

-    /* Initialize the phy chip. */
-    switch(pDevice->PhyId & PHY_ID_MASK)
-    {
+       /* Initialize the phy chip. */
+       switch (pDevice->PhyId & PHY_ID_MASK) {

        case PHY_BCM5400_PHY_ID:
        case PHY_BCM5401_PHY_ID:
        case PHY_BCM5411_PHY_ID:
        case PHY_BCM5701_PHY_ID:
        case PHY_BCM5703_PHY_ID:
        case PHY_BCM5704_PHY_ID:
        case PHY_BCM5400_PHY_ID:
        case PHY_BCM5401_PHY_ID:
        case PHY_BCM5411_PHY_ID:
        case PHY_BCM5701_PHY_ID:
        case PHY_BCM5703_PHY_ID:
        case PHY_BCM5704_PHY_ID:

-           CurrentLinkStatus = LM_InitBcm540xPhy(pDevice);
-           break;
+               CurrentLinkStatus = LM_InitBcm540xPhy (pDevice);
+               break;

 
        default:
 
        default:

-           break;
-    }
-
-    if(CurrentLinkStatus == LM_STATUS_LINK_SETTING_MISMATCH)
-    {
-       CurrentLinkStatus = LM_STATUS_LINK_DOWN;
-    }
+               break;
+       }

 
 

-    /* Setup flow control. */
-    pDevice->FlowControl = LM_FLOW_CONTROL_NONE;
-    if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
-    {
-       LM_FLOW_CONTROL FlowCap;     /* Flow control capability. */
+       if (CurrentLinkStatus == LM_STATUS_LINK_SETTING_MISMATCH) {
+               CurrentLinkStatus = LM_STATUS_LINK_DOWN;
+       }
+
+       /* Setup flow control. */
+       pDevice->FlowControl = LM_FLOW_CONTROL_NONE;
+       if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) {
+               LM_FLOW_CONTROL FlowCap;        /* Flow control capability. */
+
+               FlowCap = LM_FLOW_CONTROL_NONE;
+
+               if (pDevice->DuplexMode == LM_DUPLEX_MODE_FULL) {
+                       if (pDevice->DisableAutoNeg == FALSE ||
+                           pDevice->RequestedMediaType ==
+                           LM_REQUESTED_MEDIA_TYPE_AUTO
+                           || pDevice->RequestedMediaType ==
+                           LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) {
+                               LM_UINT32 ExpectedPhyAd;
+                               LM_UINT32 LocalPhyAd;
+                               LM_UINT32 RemotePhyAd;
+
+                               LM_ReadPhy (pDevice, PHY_AN_AD_REG,
+                                           &LocalPhyAd);
+                               pDevice->advertising = LocalPhyAd;
+                               LocalPhyAd &=
+                                   (PHY_AN_AD_ASYM_PAUSE |
+                                    PHY_AN_AD_PAUSE_CAPABLE);
+
+                               ExpectedPhyAd =
+                                   GetPhyAdFlowCntrlSettings (pDevice);
+
+                               if (LocalPhyAd != ExpectedPhyAd) {
+                                       CurrentLinkStatus = LM_STATUS_LINK_DOWN;
+                               } else {
+                                       LM_ReadPhy (pDevice,
+                                                   PHY_LINK_PARTNER_ABILITY_REG,
+                                                   &RemotePhyAd);
+
+                                       LM_SetFlowControl (pDevice, LocalPhyAd,
+                                                          RemotePhyAd);
+                               }
+                       } else {
+                               pDevice->FlowControlCap &=
+                                   ~LM_FLOW_CONTROL_AUTO_PAUSE;
+                               LM_SetFlowControl (pDevice, 0, 0);
+                       }
+               }
+       }

 
 

-       FlowCap = LM_FLOW_CONTROL_NONE;
+       if (CurrentLinkStatus == LM_STATUS_LINK_DOWN) {
+               LM_ForceAutoNeg (pDevice, pDevice->RequestedMediaType);

 
 

-       if(pDevice->DuplexMode == LM_DUPLEX_MODE_FULL)
-       {
-           if(pDevice->DisableAutoNeg == FALSE ||
-               pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO ||
-               pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO)
-           {
-               LM_UINT32 ExpectedPhyAd;
-               LM_UINT32 LocalPhyAd;
-               LM_UINT32 RemotePhyAd;
+               /* If we force line speed, we make get link right away. */
+               LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
+               LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
+               if (Value32 & PHY_STATUS_LINK_PASS) {
+                       CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
+               }
+       }

 
 

-               LM_ReadPhy(pDevice, PHY_AN_AD_REG, &LocalPhyAd);
-               pDevice->advertising = LocalPhyAd;
-               LocalPhyAd &= (PHY_AN_AD_ASYM_PAUSE | PHY_AN_AD_PAUSE_CAPABLE);
+       /* GMII interface. */
+       pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK;
+       if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) {
+               if (pDevice->LineSpeed == LM_LINE_SPEED_100MBPS ||
+                   pDevice->LineSpeed == LM_LINE_SPEED_10MBPS) {
+                       pDevice->MacMode |= MAC_MODE_PORT_MODE_MII;
+               } else {
+                       pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
+               }
+       } else {
+               pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
+       }

 
 

-               ExpectedPhyAd = GetPhyAdFlowCntrlSettings(pDevice);
+       /* Set the MAC to operate in the appropriate duplex mode. */
+       pDevice->MacMode &= ~MAC_MODE_HALF_DUPLEX;
+       if (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF) {
+               pDevice->MacMode |= MAC_MODE_HALF_DUPLEX;
+       }

 
 

-               if(LocalPhyAd != ExpectedPhyAd)
-               {
-                   CurrentLinkStatus = LM_STATUS_LINK_DOWN;
+       /* Set the link polarity bit. */
+       pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
+       if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+               if ((pDevice->LedMode == LED_MODE_LINK10) ||
+                   (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE &&
+                    pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)) {
+                       pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
+               }
+       } else {
+               if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) {
+                       pDevice->MacMode |= MAC_MODE_LINK_POLARITY;

                }
                }

-               else
-               {
-                   LM_ReadPhy(pDevice, PHY_LINK_PARTNER_ABILITY_REG,
-                       &RemotePhyAd);

 
 

-                   LM_SetFlowControl(pDevice, LocalPhyAd, RemotePhyAd);
+               /* Set LED mode. */
+               if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+                   T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+                       Value32 = LED_CTRL_PHY_MODE_1;
+               } else {
+                       if (pDevice->LedMode == LED_MODE_OUTPUT) {
+                               Value32 = LED_CTRL_PHY_MODE_2;
+                       } else {
+                               Value32 = LED_CTRL_PHY_MODE_1;
+                       }

                }
                }

-           }
-           else
-           {
-               pDevice->FlowControlCap &= ~LM_FLOW_CONTROL_AUTO_PAUSE;
-               LM_SetFlowControl(pDevice, 0, 0);
-           }
+               REG_WR (pDevice, MacCtrl.LedCtrl, Value32);

        }
        }

-    }

 
 

-    if(CurrentLinkStatus == LM_STATUS_LINK_DOWN)
-    {
-       LM_ForceAutoNeg(pDevice, pDevice->RequestedMediaType);
+       REG_WR (pDevice, MacCtrl.Mode, pDevice->MacMode);

 
 

-       /* If we force line speed, we make get link right away. */
-       LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
-       LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
-       if(Value32 & PHY_STATUS_LINK_PASS)
-       {
-           CurrentLinkStatus = LM_STATUS_LINK_ACTIVE;
+       /* Enable auto polling. */
+       if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
+               pDevice->MiMode |= MI_MODE_AUTO_POLLING_ENABLE;
+               REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);

        }
        }

-    }

 
 

-    /* GMII interface. */
-    pDevice->MacMode &= ~MAC_MODE_PORT_MODE_MASK;
-    if(CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
-    {
-       if(pDevice->LineSpeed == LM_LINE_SPEED_100MBPS ||
-           pDevice->LineSpeed == LM_LINE_SPEED_10MBPS)
-       {
-           pDevice->MacMode |= MAC_MODE_PORT_MODE_MII;
-       }
-       else
-       {
-           pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
-       }
-    }
-    else {
-       pDevice->MacMode |= MAC_MODE_PORT_MODE_GMII;
-    }
-
-    /* Set the MAC to operate in the appropriate duplex mode. */
-    pDevice->MacMode &= ~MAC_MODE_HALF_DUPLEX;
-    if(pDevice->DuplexMode == LM_DUPLEX_MODE_HALF)
-    {
-       pDevice->MacMode |= MAC_MODE_HALF_DUPLEX;
-    }
-
-    /* Set the link polarity bit. */
-    pDevice->MacMode &= ~MAC_MODE_LINK_POLARITY;
-    if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
-    {
-       if((pDevice->LedMode == LED_MODE_LINK10) ||
-            (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE &&
-            pDevice->LineSpeed == LM_LINE_SPEED_10MBPS))
-       {
-           pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
+       /* Enable phy link change attention. */
+       if (pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT) {
+               REG_WR (pDevice, MacCtrl.MacEvent,
+                       MAC_EVENT_ENABLE_MI_INTERRUPT);
+       } else {
+               REG_WR (pDevice, MacCtrl.MacEvent,
+                       MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);

        }
        }

-    }
-    else
-    {
-       if (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE)
-       {
-           pDevice->MacMode |= MAC_MODE_LINK_POLARITY;
+       if ((T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) &&
+           (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) &&
+           (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) &&
+           (((pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) &&
+             (pDevice->PciState & T3_PCI_STATE_BUS_SPEED_HIGH)) ||
+            !(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))) {
+               MM_Wait (120);
+               REG_WR (pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
+                       MAC_STATUS_CFG_CHANGED);
+               MEM_WR_OFFSET (pDevice, T3_FIRMWARE_MAILBOX,
+                              T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE);

        }
 
        }
 

-       /* Set LED mode. */
-       if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
-           T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
-       {
-           Value32 = LED_CTRL_PHY_MODE_1;
+       /* Indicate link status. */
+       if (pDevice->LinkStatus != CurrentLinkStatus) {
+               pDevice->LinkStatus = CurrentLinkStatus;
+               MM_IndicateStatus (pDevice, CurrentLinkStatus);

        }
        }

-       else
-       {
-           if(pDevice->LedMode == LED_MODE_OUTPUT)
-           {
-               Value32 = LED_CTRL_PHY_MODE_2;
-           }
-           else
-           {
-               Value32 = LED_CTRL_PHY_MODE_1;
-           }
-       }
-       REG_WR(pDevice, MacCtrl.LedCtrl, Value32);
-    }
-
-    REG_WR(pDevice, MacCtrl.Mode, pDevice->MacMode);
-
-    /* Enable auto polling. */
-    if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
-    {
-       pDevice->MiMode |= MI_MODE_AUTO_POLLING_ENABLE;
-       REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
-    }
-
-    /* Enable phy link change attention. */
-    if(pDevice->PhyIntMode == T3_PHY_INT_MODE_MI_INTERRUPT)
-    {
-       REG_WR(pDevice, MacCtrl.MacEvent, MAC_EVENT_ENABLE_MI_INTERRUPT);
-    }
-    else
-    {
-       REG_WR(pDevice, MacCtrl.MacEvent,
-           MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN);
-    }
-    if ((T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700) &&
-       (CurrentLinkStatus == LM_STATUS_LINK_ACTIVE) &&
-       (pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) &&
-       (((pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE) &&
-         (pDevice->PciState & T3_PCI_STATE_BUS_SPEED_HIGH)) ||
-        !(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)))
-    {
-       MM_Wait(120);
-       REG_WR(pDevice, MacCtrl.Status, MAC_STATUS_SYNC_CHANGED |
-           MAC_STATUS_CFG_CHANGED);
-       MEM_WR_OFFSET(pDevice, T3_FIRMWARE_MAILBOX,
-           T3_MAGIC_NUM_DISABLE_DMAW_ON_LINK_CHANGE);
-    }
-
-    /* Indicate link status. */
-    if (pDevice->LinkStatus != CurrentLinkStatus) {
-       pDevice->LinkStatus = CurrentLinkStatus;
-       MM_IndicateStatus(pDevice, CurrentLinkStatus);
-    }
-
-    return LM_STATUS_SUCCESS;
-} /* LM_SetupCopperPhy */
+
+       return LM_STATUS_SUCCESS;
+}                              /* LM_SetupCopperPhy */

 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-LM_STATUS
-LM_SetupPhy(
-    PLM_DEVICE_BLOCK pDevice)
+LM_STATUS LM_SetupPhy (PLM_DEVICE_BLOCK pDevice)

 {
 {

-    LM_STATUS LmStatus;
-    LM_UINT32 Value32;
+       LM_STATUS LmStatus;
+       LM_UINT32 Value32;

 
 #if INCLUDE_TBI_SUPPORT
 
 #if INCLUDE_TBI_SUPPORT

-    if(pDevice->EnableTbi)
-    {
-       LmStatus = LM_SetupFiberPhy(pDevice);
-    }
-    else
-#endif /* INCLUDE_TBI_SUPPORT */
-    {
-       LmStatus = LM_SetupCopperPhy(pDevice);
-    }
-    if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0)
-    {
-       if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE))
-       {
-           Value32 = REG_RD(pDevice, PciCfg.PciState);
-           REG_WR(pDevice, PciCfg.PciState,
-               Value32 | T3_PCI_STATE_RETRY_SAME_DMA);
-       }
-    }
-    if ((pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) &&
-       (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF))
-    {
-       REG_WR(pDevice, MacCtrl.TxLengths, 0x26ff);
-    }
-    else
-    {
-       REG_WR(pDevice, MacCtrl.TxLengths, 0x2620);
-    }
-
-    return LmStatus;
+       if (pDevice->EnableTbi) {
+               LmStatus = LM_SetupFiberPhy (pDevice);
+       } else
+#endif                         /* INCLUDE_TBI_SUPPORT */
+       {
+               LmStatus = LM_SetupCopperPhy (pDevice);
+       }
+       if (pDevice->ChipRevId == T3_CHIP_ID_5704_A0) {
+               if (!(pDevice->PciState & T3_PCI_STATE_CONVENTIONAL_PCI_MODE)) {
+                       Value32 = REG_RD (pDevice, PciCfg.PciState);
+                       REG_WR (pDevice, PciCfg.PciState,
+                               Value32 | T3_PCI_STATE_RETRY_SAME_DMA);
+               }
+       }
+       if ((pDevice->LineSpeed == LM_LINE_SPEED_1000MBPS) &&
+           (pDevice->DuplexMode == LM_DUPLEX_MODE_HALF)) {
+               REG_WR (pDevice, MacCtrl.TxLengths, 0x26ff);
+       } else {
+               REG_WR (pDevice, MacCtrl.TxLengths, 0x2620);
+       }
+
+       return LmStatus;

 }
 
 /******************************************************************************/
 }
 
 /******************************************************************************/


@@ -5232,55 +4830,47 @@ LM_SetupPhy(
 /* Return:                                                                    */
 /******************************************************************************/
 LM_VOID
 /* Return:                                                                    */
 /******************************************************************************/
 LM_VOID

-LM_ReadPhy(
-PLM_DEVICE_BLOCK pDevice,
-LM_UINT32 PhyReg,
-PLM_UINT32 pData32) {
-    LM_UINT32 Value32;
-    LM_UINT32 j;
+LM_ReadPhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, PLM_UINT32 pData32)
+{
+       LM_UINT32 Value32;
+       LM_UINT32 j;

 
 

-    if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
-    {
-       REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode &
-           ~MI_MODE_AUTO_POLLING_ENABLE);
-       MM_Wait(40);
-    }
+       if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
+               REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode &
+                       ~MI_MODE_AUTO_POLLING_ENABLE);
+               MM_Wait (40);
+       }

 
 

-    Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) |
-       ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) |
-       MI_COM_CMD_READ | MI_COM_START;
+       Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) |
+           ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) <<
+            MI_COM_FIRST_PHY_REG_ADDR_BIT) | MI_COM_CMD_READ | MI_COM_START;

 
 

-    REG_WR(pDevice, MacCtrl.MiCom, Value32);
+       REG_WR (pDevice, MacCtrl.MiCom, Value32);

 
 

-    for(j = 0; j < 20; j++)
-    {
-       MM_Wait(25);
+       for (j = 0; j < 20; j++) {
+               MM_Wait (25);

 
 

-       Value32 = REG_RD(pDevice, MacCtrl.MiCom);
+               Value32 = REG_RD (pDevice, MacCtrl.MiCom);

 
 

-       if(!(Value32 & MI_COM_BUSY))
-       {
-           MM_Wait(5);
-           Value32 = REG_RD(pDevice, MacCtrl.MiCom);
-           Value32 &= MI_COM_PHY_DATA_MASK;
-           break;
+               if (!(Value32 & MI_COM_BUSY)) {
+                       MM_Wait (5);
+                       Value32 = REG_RD (pDevice, MacCtrl.MiCom);
+                       Value32 &= MI_COM_PHY_DATA_MASK;
+                       break;
+               }

        }
        }

-    }

 
 

-    if(Value32 & MI_COM_BUSY)
-    {
-       Value32 = 0;
-    }
-
-    *pData32 = Value32;
+       if (Value32 & MI_COM_BUSY) {
+               Value32 = 0;
+       }

 
 

-    if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
-    {
-       REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
-       MM_Wait(40);
-    }
-} /* LM_ReadPhy */
+       *pData32 = Value32;

 
 

+       if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
+               REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
+               MM_Wait (40);
+       }
+}                              /* LM_ReadPhy */

 
 /******************************************************************************/
 /* Description:                                                               */
 
 /******************************************************************************/
 /* Description:                                                               */


@@ -5288,341 +4878,296 @@ PLM_UINT32 pData32) {
 /* Return:                                                                    */
 /******************************************************************************/
 LM_VOID
 /* Return:                                                                    */
 /******************************************************************************/
 LM_VOID

-LM_WritePhy(
-PLM_DEVICE_BLOCK pDevice,
-LM_UINT32 PhyReg,
-LM_UINT32 Data32) {
-    LM_UINT32 Value32;
-    LM_UINT32 j;
+LM_WritePhy (PLM_DEVICE_BLOCK pDevice, LM_UINT32 PhyReg, LM_UINT32 Data32)
+{
+       LM_UINT32 Value32;
+       LM_UINT32 j;

 
 

-    if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
-    {
-       REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode &
-           ~MI_MODE_AUTO_POLLING_ENABLE);
-       MM_Wait(40);
-    }
+       if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
+               REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode &
+                       ~MI_MODE_AUTO_POLLING_ENABLE);
+               MM_Wait (40);
+       }

 
 

-    Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) |
-       ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) << MI_COM_FIRST_PHY_REG_ADDR_BIT) |
-       (Data32 & MI_COM_PHY_DATA_MASK) | MI_COM_CMD_WRITE | MI_COM_START;
+       Value32 = (pDevice->PhyAddr << MI_COM_FIRST_PHY_ADDR_BIT) |
+           ((PhyReg & MI_COM_PHY_REG_ADDR_MASK) <<
+            MI_COM_FIRST_PHY_REG_ADDR_BIT) | (Data32 & MI_COM_PHY_DATA_MASK) |
+           MI_COM_CMD_WRITE | MI_COM_START;

 
 

-    REG_WR(pDevice, MacCtrl.MiCom, Value32);
+       REG_WR (pDevice, MacCtrl.MiCom, Value32);

 
 

-    for(j = 0; j < 20; j++)
-    {
-       MM_Wait(25);
+       for (j = 0; j < 20; j++) {
+               MM_Wait (25);

 
 

-       Value32 = REG_RD(pDevice, MacCtrl.MiCom);
+               Value32 = REG_RD (pDevice, MacCtrl.MiCom);

 
 

-       if(!(Value32 & MI_COM_BUSY))
-       {
-           MM_Wait(5);
-           break;
+               if (!(Value32 & MI_COM_BUSY)) {
+                       MM_Wait (5);
+                       break;
+               }

        }
        }

-    }
-
-    if(pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING)
-    {
-       REG_WR(pDevice, MacCtrl.MiMode, pDevice->MiMode);
-       MM_Wait(40);
-    }
-} /* LM_WritePhy */

 
 

+       if (pDevice->PhyIntMode == T3_PHY_INT_MODE_AUTO_POLLING) {
+               REG_WR (pDevice, MacCtrl.MiMode, pDevice->MiMode);
+               MM_Wait (40);
+       }
+}                              /* LM_WritePhy */

 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-LM_STATUS
-LM_SetPowerState(
-PLM_DEVICE_BLOCK pDevice,
-LM_POWER_STATE PowerLevel) {
-    LM_UINT32 PmeSupport;
-    LM_UINT32 Value32;
-    LM_UINT32 PmCtrl;
+LM_STATUS LM_SetPowerState (PLM_DEVICE_BLOCK pDevice, LM_POWER_STATE PowerLevel)
+{
+       LM_UINT32 PmeSupport;
+       LM_UINT32 Value32;
+       LM_UINT32 PmCtrl;

 
 

-    /* make sureindirect accesses are enabled*/
-    MM_WriteConfig32(pDevice, T3_PCI_MISC_HOST_CTRL_REG, pDevice->MiscHostCtrl);
+       /* make sureindirect accesses are enabled */
+       MM_WriteConfig32 (pDevice, T3_PCI_MISC_HOST_CTRL_REG,
+                         pDevice->MiscHostCtrl);

 
 

-    /* Clear the PME_ASSERT bit and the power state bits.  Also enable */
-    /* the PME bit. */
-    MM_ReadConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, &PmCtrl);
+       /* Clear the PME_ASSERT bit and the power state bits.  Also enable */
+       /* the PME bit. */
+       MM_ReadConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, &PmCtrl);

 
 

-    PmCtrl |= T3_PM_PME_ASSERTED;
-    PmCtrl &= ~T3_PM_POWER_STATE_MASK;
+       PmCtrl |= T3_PM_PME_ASSERTED;
+       PmCtrl &= ~T3_PM_POWER_STATE_MASK;

 
 

-    /* Set the appropriate power state. */
-    if(PowerLevel == LM_POWER_STATE_D0)
-    {
+       /* Set the appropriate power state. */
+       if (PowerLevel == LM_POWER_STATE_D0) {

 
 

-       /* Bring the card out of low power mode. */
-       PmCtrl |= T3_PM_POWER_STATE_D0;
-       MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl);
+               /* Bring the card out of low power mode. */
+               PmCtrl |= T3_PM_POWER_STATE_D0;
+               MM_WriteConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl);

 
 

-       REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl);
-       MM_Wait (40);
-#if 0   /* Bugfix by jmb...can't call WritePhy here because pDevice not fully initialized */
-       LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x02);
+               REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl);
+               MM_Wait (40);
+#if 0                          /* Bugfix by jmb...can't call WritePhy here because pDevice not fully initialized */
+               LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x02);

 #endif
 
 #endif
 

-       return LM_STATUS_SUCCESS;
-    }
-    else if(PowerLevel == LM_POWER_STATE_D1)
-    {
-       PmCtrl |= T3_PM_POWER_STATE_D1;
-    }
-    else if(PowerLevel == LM_POWER_STATE_D2)
-    {
-       PmCtrl |= T3_PM_POWER_STATE_D2;
-    }
-    else if(PowerLevel == LM_POWER_STATE_D3)
-    {
-       PmCtrl |= T3_PM_POWER_STATE_D3;
-    }
-    else
-    {
-       return LM_STATUS_FAILURE;
-    }
-    PmCtrl |= T3_PM_PME_ENABLE;
-
-    /* Mask out all interrupts so LM_SetupPhy won't be called while we are */
-    /* setting new line speed. */
-    Value32 = REG_RD(pDevice, PciCfg.MiscHostCtrl);
-    REG_WR(pDevice, PciCfg.MiscHostCtrl, Value32 | MISC_HOST_CTRL_MASK_PCI_INT);
-
-    if(!pDevice->RestoreOnWakeUp)
-    {
-       pDevice->RestoreOnWakeUp = TRUE;
-       pDevice->WakeUpDisableAutoNeg = pDevice->DisableAutoNeg;
-       pDevice->WakeUpRequestedMediaType = pDevice->RequestedMediaType;
-    }
-
-    /* Force auto-negotiation to 10 line speed. */
-    pDevice->DisableAutoNeg = FALSE;
-    pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS;
-    LM_SetupPhy(pDevice);
-
-    /* Put the driver in the initial state, and go through the power down */
-    /* sequence. */
-    LM_Halt(pDevice);
-
-    MM_ReadConfig32(pDevice, T3_PCI_PM_CAP_REG, &PmeSupport);
-
-    if (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE)
-    {
-
-       /* Enable WOL. */
-       LM_WritePhy(pDevice, BCM5401_AUX_CTRL, 0x5a);
-       MM_Wait(40);
-
-       /* Set LED mode. */
-       if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
-           T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
-       {
-           Value32 = LED_CTRL_PHY_MODE_1;
-       }
-       else
-       {
-           if(pDevice->LedMode == LED_MODE_OUTPUT)
-           {
-               Value32 = LED_CTRL_PHY_MODE_2;
-           }
-           else
-           {
-               Value32 = LED_CTRL_PHY_MODE_1;
-           }
+               return LM_STATUS_SUCCESS;
+       } else if (PowerLevel == LM_POWER_STATE_D1) {
+               PmCtrl |= T3_PM_POWER_STATE_D1;
+       } else if (PowerLevel == LM_POWER_STATE_D2) {
+               PmCtrl |= T3_PM_POWER_STATE_D2;
+       } else if (PowerLevel == LM_POWER_STATE_D3) {
+               PmCtrl |= T3_PM_POWER_STATE_D3;
+       } else {
+               return LM_STATUS_FAILURE;

        }
        }

+       PmCtrl |= T3_PM_PME_ENABLE;

 
 

-       Value32 = MAC_MODE_PORT_MODE_MII;
-       if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700)
-       {
-           if(pDevice->LedMode == LED_MODE_LINK10 ||
-               pDevice->WolSpeed == WOL_SPEED_10MB)
-           {
-               Value32 |= MAC_MODE_LINK_POLARITY;
-           }
-       }
-       else
-       {
-           Value32 |= MAC_MODE_LINK_POLARITY;
-       }
-       REG_WR(pDevice, MacCtrl.Mode, Value32);
-       MM_Wait(40); MM_Wait(40); MM_Wait(40);
+       /* Mask out all interrupts so LM_SetupPhy won't be called while we are */
+       /* setting new line speed. */
+       Value32 = REG_RD (pDevice, PciCfg.MiscHostCtrl);
+       REG_WR (pDevice, PciCfg.MiscHostCtrl,
+               Value32 | MISC_HOST_CTRL_MASK_PCI_INT);

 
 

-       /* Always enable magic packet wake-up if we have vaux. */
-       if((PmeSupport & T3_PCI_PM_CAP_PME_D3COLD) &&
-           (pDevice->WakeUpModeCap & LM_WAKE_UP_MODE_MAGIC_PACKET))
-       {
-           Value32 |= MAC_MODE_DETECT_MAGIC_PACKET_ENABLE;
+       if (!pDevice->RestoreOnWakeUp) {
+               pDevice->RestoreOnWakeUp = TRUE;
+               pDevice->WakeUpDisableAutoNeg = pDevice->DisableAutoNeg;
+               pDevice->WakeUpRequestedMediaType = pDevice->RequestedMediaType;

        }
 
        }
 

-       REG_WR(pDevice, MacCtrl.Mode, Value32);
+       /* Force auto-negotiation to 10 line speed. */
+       pDevice->DisableAutoNeg = FALSE;
+       pDevice->RequestedMediaType = LM_REQUESTED_MEDIA_TYPE_UTP_10MBPS;
+       LM_SetupPhy (pDevice);

 
 

-       /* Enable the receiver. */
-       REG_WR(pDevice, MacCtrl.RxMode, RX_MODE_ENABLE);
-    }
-
-    /* Disable tx/rx clocks, and seletect an alternate clock. */
-    if(pDevice->WolSpeed == WOL_SPEED_100MB)
-    {
-       if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
-           T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
-       {
-           Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
-               T3_PCI_SELECT_ALTERNATE_CLOCK;
-       }
-       else
-       {
-           Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK;
-       }
-       REG_WR(pDevice, PciCfg.ClockCtrl, Value32);
+       /* Put the driver in the initial state, and go through the power down */
+       /* sequence. */
+       LM_Halt (pDevice);

 
 

-       MM_Wait(40);
+       MM_ReadConfig32 (pDevice, T3_PCI_PM_CAP_REG, &PmeSupport);

 
 

-       if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
-           T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
-       {
-           Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
-               T3_PCI_SELECT_ALTERNATE_CLOCK | T3_PCI_44MHZ_CORE_CLOCK;
-       }
-       else
-       {
-           Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK |
-               T3_PCI_44MHZ_CORE_CLOCK;
-       }
+       if (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE) {

 
 

-       REG_WR(pDevice, PciCfg.ClockCtrl, Value32);
+               /* Enable WOL. */
+               LM_WritePhy (pDevice, BCM5401_AUX_CTRL, 0x5a);
+               MM_Wait (40);

 
 

-       MM_Wait(40);
+               /* Set LED mode. */
+               if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+                   T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+                       Value32 = LED_CTRL_PHY_MODE_1;
+               } else {
+                       if (pDevice->LedMode == LED_MODE_OUTPUT) {
+                               Value32 = LED_CTRL_PHY_MODE_2;
+                       } else {
+                               Value32 = LED_CTRL_PHY_MODE_1;
+                       }
+               }

 
 

-       if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
-           T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
-       {
-           Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
-               T3_PCI_44MHZ_CORE_CLOCK;
-       }
-       else
-       {
-           Value32 = T3_PCI_44MHZ_CORE_CLOCK;
-       }
+               Value32 = MAC_MODE_PORT_MODE_MII;
+               if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700) {
+                       if (pDevice->LedMode == LED_MODE_LINK10 ||
+                           pDevice->WolSpeed == WOL_SPEED_10MB) {
+                               Value32 |= MAC_MODE_LINK_POLARITY;
+                       }
+               } else {
+                       Value32 |= MAC_MODE_LINK_POLARITY;
+               }
+               REG_WR (pDevice, MacCtrl.Mode, Value32);
+               MM_Wait (40);
+               MM_Wait (40);
+               MM_Wait (40);
+
+               /* Always enable magic packet wake-up if we have vaux. */
+               if ((PmeSupport & T3_PCI_PM_CAP_PME_D3COLD) &&
+                   (pDevice->WakeUpModeCap & LM_WAKE_UP_MODE_MAGIC_PACKET)) {
+                       Value32 |= MAC_MODE_DETECT_MAGIC_PACKET_ENABLE;
+               }

 
 

-       REG_WR(pDevice, PciCfg.ClockCtrl, Value32);
-    }
-    else
-    {
-       if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
-           T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
-       {
-           Value32 = T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
-               T3_PCI_SELECT_ALTERNATE_CLOCK |
-               T3_PCI_POWER_DOWN_PCI_PLL133;
-       }
-       else
-       {
-           Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK |
-               T3_PCI_POWER_DOWN_PCI_PLL133;
+               REG_WR (pDevice, MacCtrl.Mode, Value32);
+
+               /* Enable the receiver. */
+               REG_WR (pDevice, MacCtrl.RxMode, RX_MODE_ENABLE);

        }
 
        }
 

-       REG_WR(pDevice, PciCfg.ClockCtrl, Value32);
-    }
+       /* Disable tx/rx clocks, and seletect an alternate clock. */
+       if (pDevice->WolSpeed == WOL_SPEED_100MB) {
+               if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+                   T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+                       Value32 =
+                           T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
+                           T3_PCI_SELECT_ALTERNATE_CLOCK;
+               } else {
+                       Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK;
+               }
+               REG_WR (pDevice, PciCfg.ClockCtrl, Value32);
+
+               MM_Wait (40);
+
+               if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+                   T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+                       Value32 =
+                           T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
+                           T3_PCI_SELECT_ALTERNATE_CLOCK |
+                           T3_PCI_44MHZ_CORE_CLOCK;
+               } else {
+                       Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK |
+                           T3_PCI_44MHZ_CORE_CLOCK;
+               }
+
+               REG_WR (pDevice, PciCfg.ClockCtrl, Value32);

 
 

-    MM_Wait(40);
+               MM_Wait (40);

 
 

-    if(!pDevice->EepromWp && (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE))
-    {
-       /* Switch adapter to auxilliary power. */
-       if(T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
-           T3_ASIC_REV(pDevice->ChipRevId) == T3_ASIC_REV_5701)
-       {
-           /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */
-           REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
-               GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
-               GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
-               GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
-               GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
-               GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
-               MM_Wait(40);
+               if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+                   T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+                       Value32 =
+                           T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
+                           T3_PCI_44MHZ_CORE_CLOCK;
+               } else {
+                       Value32 = T3_PCI_44MHZ_CORE_CLOCK;
+               }
+
+               REG_WR (pDevice, PciCfg.ClockCtrl, Value32);
+       } else {
+               if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+                   T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+                       Value32 =
+                           T3_PCI_DISABLE_RX_CLOCK | T3_PCI_DISABLE_TX_CLOCK |
+                           T3_PCI_SELECT_ALTERNATE_CLOCK |
+                           T3_PCI_POWER_DOWN_PCI_PLL133;
+               } else {
+                       Value32 = T3_PCI_SELECT_ALTERNATE_CLOCK |
+                           T3_PCI_POWER_DOWN_PCI_PLL133;
+               }
+
+               REG_WR (pDevice, PciCfg.ClockCtrl, Value32);

        }
        }

-       else
-       {
-           /* GPIO0 = 0, GPIO1 = 1, GPIO2 = 1. */
-           REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
-               GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
-               GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
-               GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
-               GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
-               GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
-               MM_Wait(40);
-
-           /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 1. */
-           REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
-               GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
-               GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
-               GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
-               GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
-               GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
-               GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
-               MM_Wait(40);
-
-           /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */
-           REG_WR(pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
-               GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
-               GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
-               GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
-               GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
-               GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
-               MM_Wait(40);
-       }
-    }
-
-    /* Set the phy to low power mode. */
-    /* Put the the hardware in low power mode. */
-    MM_WriteConfig32(pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl);
-
-    return LM_STATUS_SUCCESS;
-} /* LM_SetPowerState */

 
 

+       MM_Wait (40);
+
+       if (!pDevice->EepromWp
+           && (pDevice->WakeUpModeCap != LM_WAKE_UP_MODE_NONE)) {
+               /* Switch adapter to auxilliary power. */
+               if (T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5700 ||
+                   T3_ASIC_REV (pDevice->ChipRevId) == T3_ASIC_REV_5701) {
+                       /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */
+                       REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
+                               GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
+                               GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
+                               GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
+                               GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
+                               GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
+                       MM_Wait (40);
+               } else {
+                       /* GPIO0 = 0, GPIO1 = 1, GPIO2 = 1. */
+                       REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
+                               GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
+                               GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
+                               GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
+                               GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
+                               GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
+                       MM_Wait (40);
+
+                       /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 1. */
+                       REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
+                               GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
+                               GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
+                               GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
+                               GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
+                               GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1 |
+                               GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2);
+                       MM_Wait (40);
+
+                       /* GPIO0 = 1, GPIO1 = 1, GPIO2 = 0. */
+                       REG_WR (pDevice, Grc.LocalCtrl, pDevice->GrcLocalCtrl |
+                               GRC_MISC_LOCAL_CTRL_GPIO_OE0 |
+                               GRC_MISC_LOCAL_CTRL_GPIO_OE1 |
+                               GRC_MISC_LOCAL_CTRL_GPIO_OE2 |
+                               GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0 |
+                               GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1);
+                       MM_Wait (40);
+               }
+       }
+
+       /* Set the phy to low power mode. */
+       /* Put the the hardware in low power mode. */
+       MM_WriteConfig32 (pDevice, T3_PCI_PM_STATUS_CTRL_REG, PmCtrl);
+
+       return LM_STATUS_SUCCESS;
+}                              /* LM_SetPowerState */

 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-static LM_UINT32
-GetPhyAdFlowCntrlSettings(
-    PLM_DEVICE_BLOCK pDevice)
+static LM_UINT32 GetPhyAdFlowCntrlSettings (PLM_DEVICE_BLOCK pDevice)

 {
 {

-    LM_UINT32 Value32;
-
-    Value32 = 0;
-
-    /* Auto negotiation flow control only when autonegotiation is enabled. */
-    if(pDevice->DisableAutoNeg == FALSE ||
-       pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO ||
-       pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO)
-    {
-       /* Please refer to Table 28B-3 of the 802.3ab-1999 spec. */
-       if((pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE) ||
-           ((pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) &&
-           (pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)))
-       {
-           Value32 |= PHY_AN_AD_PAUSE_CAPABLE;
-       }
-       else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE)
-       {
-           Value32 |= PHY_AN_AD_ASYM_PAUSE;
-       }
-       else if(pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)
-       {
-           Value32 |= PHY_AN_AD_PAUSE_CAPABLE | PHY_AN_AD_ASYM_PAUSE;
+       LM_UINT32 Value32;
+
+       Value32 = 0;
+
+       /* Auto negotiation flow control only when autonegotiation is enabled. */
+       if (pDevice->DisableAutoNeg == FALSE ||
+           pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_AUTO ||
+           pDevice->RequestedMediaType == LM_REQUESTED_MEDIA_TYPE_UTP_AUTO) {
+               /* Please refer to Table 28B-3 of the 802.3ab-1999 spec. */
+               if ((pDevice->FlowControlCap == LM_FLOW_CONTROL_AUTO_PAUSE) ||
+                   ((pDevice->FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE)
+                    && (pDevice->
+                        FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE))) {
+                       Value32 |= PHY_AN_AD_PAUSE_CAPABLE;
+               } else if (pDevice->
+                          FlowControlCap & LM_FLOW_CONTROL_TRANSMIT_PAUSE) {
+                       Value32 |= PHY_AN_AD_ASYM_PAUSE;
+               } else if (pDevice->
+                          FlowControlCap & LM_FLOW_CONTROL_RECEIVE_PAUSE) {
+                       Value32 |=
+                           PHY_AN_AD_PAUSE_CAPABLE | PHY_AN_AD_ASYM_PAUSE;
+               }

        }
        }

-    }

 
 

-    return Value32;
+       return Value32;

 }
 
 }
 

-

 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */


@@ -5632,195 +5177,169 @@ GetPhyAdFlowCntrlSettings(
 /*                                                                            */
 /******************************************************************************/
 static LM_STATUS
 /*                                                                            */
 /******************************************************************************/
 static LM_STATUS

-LM_ForceAutoNegBcm540xPhy(
-PLM_DEVICE_BLOCK pDevice,
-LM_REQUESTED_MEDIA_TYPE RequestedMediaType)
+LM_ForceAutoNegBcm540xPhy (PLM_DEVICE_BLOCK pDevice,
+                          LM_REQUESTED_MEDIA_TYPE RequestedMediaType)

 {
 {

-    LM_MEDIA_TYPE MediaType;
-    LM_LINE_SPEED LineSpeed;
-    LM_DUPLEX_MODE DuplexMode;
-    LM_UINT32 NewPhyCtrl;
-    LM_UINT32 Value32;
-    LM_UINT32 Cnt;
-
-    /* Get the interface type, line speed, and duplex mode. */
-    LM_TranslateRequestedMediaType(RequestedMediaType, &MediaType, &LineSpeed,
-       &DuplexMode);
-
-    if (pDevice->RestoreOnWakeUp)
-    {
-       LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0);
-       pDevice->advertising1000 = 0;
-       Value32 = PHY_AN_AD_10BASET_FULL | PHY_AN_AD_10BASET_HALF;
-       if (pDevice->WolSpeed == WOL_SPEED_100MB)
-       {
-           Value32 |= PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF;
-       }
-       Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
-       Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
-       LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
-       pDevice->advertising = Value32;
-    }
-    /* Setup the auto-negotiation advertisement register. */
-    else if(LineSpeed == LM_LINE_SPEED_UNKNOWN)
-    {
-       /* Setup the 10/100 Mbps auto-negotiation advertisement register. */
-       Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD |
-           PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL |
-           PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF;
-       Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
-
-       LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
-       pDevice->advertising = Value32;
-
-       /* Advertise 1000Mbps */
-       Value32 = BCM540X_AN_AD_1000BASET_HALF | BCM540X_AN_AD_1000BASET_FULL;
+       LM_MEDIA_TYPE MediaType;
+       LM_LINE_SPEED LineSpeed;
+       LM_DUPLEX_MODE DuplexMode;
+       LM_UINT32 NewPhyCtrl;
+       LM_UINT32 Value32;
+       LM_UINT32 Cnt;
+
+       /* Get the interface type, line speed, and duplex mode. */
+       LM_TranslateRequestedMediaType (RequestedMediaType, &MediaType,
+                                       &LineSpeed, &DuplexMode);
+
+       if (pDevice->RestoreOnWakeUp) {
+               LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, 0);
+               pDevice->advertising1000 = 0;
+               Value32 = PHY_AN_AD_10BASET_FULL | PHY_AN_AD_10BASET_HALF;
+               if (pDevice->WolSpeed == WOL_SPEED_100MB) {
+                       Value32 |=
+                           PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF;
+               }
+               Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
+               Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
+               LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
+               pDevice->advertising = Value32;
+       }
+       /* Setup the auto-negotiation advertisement register. */
+       else if (LineSpeed == LM_LINE_SPEED_UNKNOWN) {
+               /* Setup the 10/100 Mbps auto-negotiation advertisement register. */
+               Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD |
+                   PHY_AN_AD_10BASET_HALF | PHY_AN_AD_10BASET_FULL |
+                   PHY_AN_AD_100BASETX_FULL | PHY_AN_AD_100BASETX_HALF;
+               Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
+
+               LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
+               pDevice->advertising = Value32;
+
+               /* Advertise 1000Mbps */
+               Value32 =
+                   BCM540X_AN_AD_1000BASET_HALF | BCM540X_AN_AD_1000BASET_FULL;

 
 #if INCLUDE_5701_AX_FIX
 
 #if INCLUDE_5701_AX_FIX

-       /* Bug: workaround for CRC error in gigabit mode when we are in */
-       /* slave mode.  This will force the PHY to operate in */
-       /* master mode. */
-       if(pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
-           pDevice->ChipRevId == T3_CHIP_ID_5701_B0)
-       {
-           Value32 |= BCM540X_CONFIG_AS_MASTER |
-               BCM540X_ENABLE_CONFIG_AS_MASTER;
-       }
+               /* Bug: workaround for CRC error in gigabit mode when we are in */
+               /* slave mode.  This will force the PHY to operate in */
+               /* master mode. */
+               if (pDevice->ChipRevId == T3_CHIP_ID_5701_A0 ||
+                   pDevice->ChipRevId == T3_CHIP_ID_5701_B0) {
+                       Value32 |= BCM540X_CONFIG_AS_MASTER |
+                           BCM540X_ENABLE_CONFIG_AS_MASTER;
+               }

 #endif
 
 #endif
 

-       LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
-       pDevice->advertising1000 = Value32;
-    }
-    else
-    {
-       if(LineSpeed == LM_LINE_SPEED_1000MBPS)
-       {
-           Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
-           Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
+               LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
+               pDevice->advertising1000 = Value32;
+       } else {
+               if (LineSpeed == LM_LINE_SPEED_1000MBPS) {
+                       Value32 = PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
+                       Value32 |= GetPhyAdFlowCntrlSettings (pDevice);
+
+                       LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
+                       pDevice->advertising = Value32;
+
+                       if (DuplexMode != LM_DUPLEX_MODE_FULL) {
+                               Value32 = BCM540X_AN_AD_1000BASET_HALF;
+                       } else {
+                               Value32 = BCM540X_AN_AD_1000BASET_FULL;
+                       }

 
 

-           LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
-           pDevice->advertising = Value32;
+                       LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG,
+                                    Value32);
+                       pDevice->advertising1000 = Value32;
+               } else if (LineSpeed == LM_LINE_SPEED_100MBPS) {
+                       LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, 0);
+                       pDevice->advertising1000 = 0;
+
+                       if (DuplexMode != LM_DUPLEX_MODE_FULL) {
+                               Value32 = PHY_AN_AD_100BASETX_HALF;
+                       } else {
+                               Value32 = PHY_AN_AD_100BASETX_FULL;
+                       }

 
 

-           if(DuplexMode != LM_DUPLEX_MODE_FULL)
-           {
-               Value32 = BCM540X_AN_AD_1000BASET_HALF;
-           }
-           else
-           {
-               Value32 = BCM540X_AN_AD_1000BASET_FULL;
-           }
+                       Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
+                       Value32 |= GetPhyAdFlowCntrlSettings (pDevice);

 
 

-           LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, Value32);
-           pDevice->advertising1000 = Value32;
-       }
-       else if(LineSpeed == LM_LINE_SPEED_100MBPS)
-       {
-           LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0);
-           pDevice->advertising1000 = 0;
+                       LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
+                       pDevice->advertising = Value32;
+               } else if (LineSpeed == LM_LINE_SPEED_10MBPS) {
+                       LM_WritePhy (pDevice, BCM540X_1000BASET_CTRL_REG, 0);
+                       pDevice->advertising1000 = 0;

 
 

-           if(DuplexMode != LM_DUPLEX_MODE_FULL)
-           {
-               Value32 = PHY_AN_AD_100BASETX_HALF;
-           }
-           else
-           {
-               Value32 = PHY_AN_AD_100BASETX_FULL;
-           }
+                       if (DuplexMode != LM_DUPLEX_MODE_FULL) {
+                               Value32 = PHY_AN_AD_10BASET_HALF;
+                       } else {
+                               Value32 = PHY_AN_AD_10BASET_FULL;
+                       }

 
 

-           Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
-           Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
+                       Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
+                       Value32 |= GetPhyAdFlowCntrlSettings (pDevice);

 
 

-           LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
-           pDevice->advertising = Value32;
-       }
-       else if(LineSpeed == LM_LINE_SPEED_10MBPS)
-       {
-           LM_WritePhy(pDevice, BCM540X_1000BASET_CTRL_REG, 0);
-           pDevice->advertising1000 = 0;
-
-           if(DuplexMode != LM_DUPLEX_MODE_FULL)
-           {
-               Value32 = PHY_AN_AD_10BASET_HALF;
-           }
-           else
-           {
-               Value32 = PHY_AN_AD_10BASET_FULL;
-           }
-
-           Value32 |= PHY_AN_AD_PROTOCOL_802_3_CSMA_CD;
-           Value32 |= GetPhyAdFlowCntrlSettings(pDevice);
-
-           LM_WritePhy(pDevice, PHY_AN_AD_REG, Value32);
-           pDevice->advertising = Value32;
-       }
-    }
-
-    /* Force line speed if auto-negotiation is disabled. */
-    if(pDevice->DisableAutoNeg && LineSpeed != LM_LINE_SPEED_UNKNOWN)
-    {
-       /* This code path is executed only when there is link. */
-       pDevice->MediaType = MediaType;
-       pDevice->LineSpeed = LineSpeed;
-       pDevice->DuplexMode = DuplexMode;
-
-       /* Force line seepd. */
-       NewPhyCtrl = 0;
-       switch(LineSpeed)
-       {
-           case LM_LINE_SPEED_10MBPS:
-               NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_10MBPS;
-               break;
-           case LM_LINE_SPEED_100MBPS:
-               NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_100MBPS;
-               break;
-           case LM_LINE_SPEED_1000MBPS:
-               NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS;
-               break;
-           default:
-               NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS;
-               break;
+                       LM_WritePhy (pDevice, PHY_AN_AD_REG, Value32);
+                       pDevice->advertising = Value32;
+               }

        }
 
        }
 

-       if(DuplexMode == LM_DUPLEX_MODE_FULL)
-       {
-           NewPhyCtrl |= PHY_CTRL_FULL_DUPLEX_MODE;
-       }
+       /* Force line speed if auto-negotiation is disabled. */
+       if (pDevice->DisableAutoNeg && LineSpeed != LM_LINE_SPEED_UNKNOWN) {
+               /* This code path is executed only when there is link. */
+               pDevice->MediaType = MediaType;
+               pDevice->LineSpeed = LineSpeed;
+               pDevice->DuplexMode = DuplexMode;

 
 

-       /* Don't do anything if the PHY_CTRL is already what we wanted. */
-       LM_ReadPhy(pDevice, PHY_CTRL_REG, &Value32);
-       if(Value32 != NewPhyCtrl)
-       {
-           /* Temporary bring the link down before forcing line speed. */
-           LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_LOOPBACK_MODE);
+               /* Force line seepd. */
+               NewPhyCtrl = 0;
+               switch (LineSpeed) {
+               case LM_LINE_SPEED_10MBPS:
+                       NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_10MBPS;
+                       break;
+               case LM_LINE_SPEED_100MBPS:
+                       NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_100MBPS;
+                       break;
+               case LM_LINE_SPEED_1000MBPS:
+                       NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS;
+                       break;
+               default:
+                       NewPhyCtrl |= PHY_CTRL_SPEED_SELECT_1000MBPS;
+                       break;
+               }

 
 

-           /* Wait for link to go down. */
-           for(Cnt = 0; Cnt < 15000; Cnt++)
-           {
-               MM_Wait(10);
+               if (DuplexMode == LM_DUPLEX_MODE_FULL) {
+                       NewPhyCtrl |= PHY_CTRL_FULL_DUPLEX_MODE;
+               }

 
 

-               LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
-               LM_ReadPhy(pDevice, PHY_STATUS_REG, &Value32);
+               /* Don't do anything if the PHY_CTRL is already what we wanted. */
+               LM_ReadPhy (pDevice, PHY_CTRL_REG, &Value32);
+               if (Value32 != NewPhyCtrl) {
+                       /* Temporary bring the link down before forcing line speed. */
+                       LM_WritePhy (pDevice, PHY_CTRL_REG,
+                                    PHY_CTRL_LOOPBACK_MODE);

 
 

-               if(!(Value32 & PHY_STATUS_LINK_PASS))
-               {
-                   MM_Wait(40);
-                   break;
-               }
-           }
+                       /* Wait for link to go down. */
+                       for (Cnt = 0; Cnt < 15000; Cnt++) {
+                               MM_Wait (10);

 
 

-           LM_WritePhy(pDevice, PHY_CTRL_REG, NewPhyCtrl);
-           MM_Wait(40);
-       }
-    }
-    else
-    {
-       LM_WritePhy(pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE |
-           PHY_CTRL_RESTART_AUTO_NEG);
-    }
+                               LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
+                               LM_ReadPhy (pDevice, PHY_STATUS_REG, &Value32);
+
+                               if (!(Value32 & PHY_STATUS_LINK_PASS)) {
+                                       MM_Wait (40);
+                                       break;
+                               }
+                       }

 
 

-    return LM_STATUS_SUCCESS;
-} /* LM_ForceAutoNegBcm540xPhy */
+                       LM_WritePhy (pDevice, PHY_CTRL_REG, NewPhyCtrl);
+                       MM_Wait (40);
+               }
+       } else {
+               LM_WritePhy (pDevice, PHY_CTRL_REG, PHY_CTRL_AUTO_NEG_ENABLE |
+                            PHY_CTRL_RESTART_AUTO_NEG);
+       }

 
 

+       return LM_STATUS_SUCCESS;
+}                              /* LM_ForceAutoNegBcm540xPhy */

 
 /******************************************************************************/
 /* Description:                                                               */
 
 /******************************************************************************/
 /* Description:                                                               */


@@ -5828,218 +5347,199 @@ LM_REQUESTED_MEDIA_TYPE RequestedMediaType)
 /* Return:                                                                    */
 /******************************************************************************/
 static LM_STATUS
 /* Return:                                                                    */
 /******************************************************************************/
 static LM_STATUS

-LM_ForceAutoNeg(
-PLM_DEVICE_BLOCK pDevice,
-LM_REQUESTED_MEDIA_TYPE RequestedMediaType)
+LM_ForceAutoNeg (PLM_DEVICE_BLOCK pDevice,
+                LM_REQUESTED_MEDIA_TYPE RequestedMediaType)

 {
 {

-    LM_STATUS LmStatus;
+       LM_STATUS LmStatus;

 
 

-    /* Initialize the phy chip. */
-    switch(pDevice->PhyId & PHY_ID_MASK)
-    {
+       /* Initialize the phy chip. */
+       switch (pDevice->PhyId & PHY_ID_MASK) {

        case PHY_BCM5400_PHY_ID:
        case PHY_BCM5401_PHY_ID:
        case PHY_BCM5411_PHY_ID:
        case PHY_BCM5701_PHY_ID:
        case PHY_BCM5703_PHY_ID:
        case PHY_BCM5704_PHY_ID:
        case PHY_BCM5400_PHY_ID:
        case PHY_BCM5401_PHY_ID:
        case PHY_BCM5411_PHY_ID:
        case PHY_BCM5701_PHY_ID:
        case PHY_BCM5703_PHY_ID:
        case PHY_BCM5704_PHY_ID:

-           LmStatus = LM_ForceAutoNegBcm540xPhy(pDevice, RequestedMediaType);
-           break;
+               LmStatus =
+                   LM_ForceAutoNegBcm540xPhy (pDevice, RequestedMediaType);
+               break;

 
        default:
 
        default:

-           LmStatus = LM_STATUS_FAILURE;
-           break;
-    }
+               LmStatus = LM_STATUS_FAILURE;
+               break;
+       }

 
 

-    return LmStatus;
-} /* LM_ForceAutoNeg */
+       return LmStatus;
+}                              /* LM_ForceAutoNeg */

 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Description:                                                               */
 /*                                                                            */
 /* Return:                                                                    */
 /******************************************************************************/

-LM_STATUS LM_LoadFirmware(PLM_DEVICE_BLOCK pDevice,
-                         PT3_FWIMG_INFO pFwImg,
-                         LM_UINT32 LoadCpu,
-                         LM_UINT32 StartCpu)
+LM_STATUS LM_LoadFirmware (PLM_DEVICE_BLOCK pDevice,
+                          PT3_FWIMG_INFO pFwImg,
+                          LM_UINT32 LoadCpu, LM_UINT32 StartCpu)

 {
 {

-    LM_UINT32 i;
-    LM_UINT32 address;
+       LM_UINT32 i;
+       LM_UINT32 address;

 
 

-    if (LoadCpu & T3_RX_CPU_ID)
-    {
-       if (LM_HaltCpu(pDevice,T3_RX_CPU_ID) != LM_STATUS_SUCCESS)
-       {
-           return LM_STATUS_FAILURE;
-       }
+       if (LoadCpu & T3_RX_CPU_ID) {
+               if (LM_HaltCpu (pDevice, T3_RX_CPU_ID) != LM_STATUS_SUCCESS) {
+                       return LM_STATUS_FAILURE;
+               }

 
 

-       /* First of all clear scrach pad memory */
-       for (i = 0; i < T3_RX_CPU_SPAD_SIZE; i+=4)
-       {
-           LM_RegWrInd(pDevice,T3_RX_CPU_SPAD_ADDR+i,0);
-       }
+               /* First of all clear scrach pad memory */
+               for (i = 0; i < T3_RX_CPU_SPAD_SIZE; i += 4) {
+                       LM_RegWrInd (pDevice, T3_RX_CPU_SPAD_ADDR + i, 0);
+               }

 
 

-       /* Copy code first */
-       address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff);
-       for (i = 0; i <= pFwImg->Text.Length; i+=4)
-       {
-           LM_RegWrInd(pDevice,address+i,
-                       ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]);
-       }
+               /* Copy code first */
+               address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff);
+               for (i = 0; i <= pFwImg->Text.Length; i += 4) {
+                       LM_RegWrInd (pDevice, address + i,
+                                    ((LM_UINT32 *) pFwImg->Text.Buffer)[i /
+                                                                        4]);
+               }

 
 

-       address = T3_RX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff);
-       for (i = 0; i <= pFwImg->ROnlyData.Length; i+=4)
-       {
-           LM_RegWrInd(pDevice,address+i,
-                       ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]);
-       }
+               address =
+                   T3_RX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff);
+               for (i = 0; i <= pFwImg->ROnlyData.Length; i += 4) {
+                       LM_RegWrInd (pDevice, address + i,
+                                    ((LM_UINT32 *) pFwImg->ROnlyData.
+                                     Buffer)[i / 4]);
+               }

 
 

-       address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff);
-       for (i= 0; i <= pFwImg->Data.Length; i+=4)
-       {
-           LM_RegWrInd(pDevice,address+i,
-                       ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]);
+               address = T3_RX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff);
+               for (i = 0; i <= pFwImg->Data.Length; i += 4) {
+                       LM_RegWrInd (pDevice, address + i,
+                                    ((LM_UINT32 *) pFwImg->Data.Buffer)[i /
+                                                                        4]);
+               }

        }
        }

-    }

 
 

-    if (LoadCpu & T3_TX_CPU_ID)
-    {
-       if (LM_HaltCpu(pDevice,T3_TX_CPU_ID) != LM_STATUS_SUCCESS)
-       {
-           return LM_STATUS_FAILURE;
-       }
+       if (LoadCpu & T3_TX_CPU_ID) {
+               if (LM_HaltCpu (pDevice, T3_TX_CPU_ID) != LM_STATUS_SUCCESS) {
+                       return LM_STATUS_FAILURE;
+               }

 
 

-       /* First of all clear scrach pad memory */
-       for (i = 0; i < T3_TX_CPU_SPAD_SIZE; i+=4)
-       {
-           LM_RegWrInd(pDevice,T3_TX_CPU_SPAD_ADDR+i,0);
-       }
+               /* First of all clear scrach pad memory */
+               for (i = 0; i < T3_TX_CPU_SPAD_SIZE; i += 4) {
+                       LM_RegWrInd (pDevice, T3_TX_CPU_SPAD_ADDR + i, 0);
+               }

 
 

-       /* Copy code first */
-       address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff);
-       for (i= 0; i <= pFwImg->Text.Length; i+=4)
-       {
-           LM_RegWrInd(pDevice,address+i,
-                       ((LM_UINT32 *)pFwImg->Text.Buffer)[i/4]);
-       }
+               /* Copy code first */
+               address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Text.Offset & 0xffff);
+               for (i = 0; i <= pFwImg->Text.Length; i += 4) {
+                       LM_RegWrInd (pDevice, address + i,
+                                    ((LM_UINT32 *) pFwImg->Text.Buffer)[i /
+                                                                        4]);
+               }

 
 

-       address = T3_TX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff);
-       for (i= 0; i <= pFwImg->ROnlyData.Length; i+=4)
-       {
-           LM_RegWrInd(pDevice,address+i,
-                       ((LM_UINT32 *)pFwImg->ROnlyData.Buffer)[i/4]);
-       }
+               address =
+                   T3_TX_CPU_SPAD_ADDR + (pFwImg->ROnlyData.Offset & 0xffff);
+               for (i = 0; i <= pFwImg->ROnlyData.Length; i += 4) {
+                       LM_RegWrInd (pDevice, address + i,
+                                    ((LM_UINT32 *) pFwImg->ROnlyData.
+                                     Buffer)[i / 4]);
+               }

 
 

-       address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff);
-       for (i= 0; i <= pFwImg->Data.Length; i+=4)
-       {
-           LM_RegWrInd(pDevice,address+i,
-                       ((LM_UINT32 *)pFwImg->Data.Buffer)[i/4]);
+               address = T3_TX_CPU_SPAD_ADDR + (pFwImg->Data.Offset & 0xffff);
+               for (i = 0; i <= pFwImg->Data.Length; i += 4) {
+                       LM_RegWrInd (pDevice, address + i,
+                                    ((LM_UINT32 *) pFwImg->Data.Buffer)[i /
+                                                                        4]);
+               }

        }
        }

-    }

 
 

-    if (StartCpu & T3_RX_CPU_ID)
-    {
-       /* Start Rx CPU */
-       REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
-       REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress);
-       for (i = 0 ; i < 5; i++)
-       {
-         if (pFwImg->StartAddress == REG_RD(pDevice,rxCpu.reg.PC))
-            break;
+       if (StartCpu & T3_RX_CPU_ID) {
+               /* Start Rx CPU */
+               REG_WR (pDevice, rxCpu.reg.state, 0xffffffff);
+               REG_WR (pDevice, rxCpu.reg.PC, pFwImg->StartAddress);
+               for (i = 0; i < 5; i++) {
+                       if (pFwImg->StartAddress ==
+                           REG_RD (pDevice, rxCpu.reg.PC))
+                               break;
+
+                       REG_WR (pDevice, rxCpu.reg.state, 0xffffffff);
+                       REG_WR (pDevice, rxCpu.reg.mode, CPU_MODE_HALT);
+                       REG_WR (pDevice, rxCpu.reg.PC, pFwImg->StartAddress);
+                       MM_Wait (1000);
+               }

 
 

-         REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
-         REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT);
-         REG_WR(pDevice,rxCpu.reg.PC,pFwImg->StartAddress);
-         MM_Wait(1000);
+               REG_WR (pDevice, rxCpu.reg.state, 0xffffffff);
+               REG_WR (pDevice, rxCpu.reg.mode, 0);

        }
 
        }
 

-       REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
-       REG_WR(pDevice,rxCpu.reg.mode, 0);
-    }
+       if (StartCpu & T3_TX_CPU_ID) {
+               /* Start Tx CPU */
+               REG_WR (pDevice, txCpu.reg.state, 0xffffffff);
+               REG_WR (pDevice, txCpu.reg.PC, pFwImg->StartAddress);
+               for (i = 0; i < 5; i++) {
+                       if (pFwImg->StartAddress ==
+                           REG_RD (pDevice, txCpu.reg.PC))
+                               break;

 
 

-    if (StartCpu & T3_TX_CPU_ID)
-    {
-       /* Start Tx CPU */
-       REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
-       REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress);
-       for (i = 0 ; i < 5; i++)
-       {
-         if (pFwImg->StartAddress == REG_RD(pDevice,txCpu.reg.PC))
-            break;
+                       REG_WR (pDevice, txCpu.reg.state, 0xffffffff);
+                       REG_WR (pDevice, txCpu.reg.mode, CPU_MODE_HALT);
+                       REG_WR (pDevice, txCpu.reg.PC, pFwImg->StartAddress);
+                       MM_Wait (1000);
+               }

 
 

-         REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
-         REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT);
-         REG_WR(pDevice,txCpu.reg.PC,pFwImg->StartAddress);
-         MM_Wait(1000);
+               REG_WR (pDevice, txCpu.reg.state, 0xffffffff);
+               REG_WR (pDevice, txCpu.reg.mode, 0);

        }
 
        }
 

-       REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
-       REG_WR(pDevice,txCpu.reg.mode, 0);
-    }
-
-    return LM_STATUS_SUCCESS;
+       return LM_STATUS_SUCCESS;

 }
 
 }
 

-STATIC LM_STATUS LM_HaltCpu(PLM_DEVICE_BLOCK pDevice,LM_UINT32 cpu_number)
+STATIC LM_STATUS LM_HaltCpu (PLM_DEVICE_BLOCK pDevice, LM_UINT32 cpu_number)

 {
 {

-    LM_UINT32 i;
+       LM_UINT32 i;

 
 

-    if (cpu_number == T3_RX_CPU_ID)
-    {
-       for (i = 0 ; i < 10000; i++)
-       {
-           REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
-           REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT);
+       if (cpu_number == T3_RX_CPU_ID) {
+               for (i = 0; i < 10000; i++) {
+                       REG_WR (pDevice, rxCpu.reg.state, 0xffffffff);
+                       REG_WR (pDevice, rxCpu.reg.mode, CPU_MODE_HALT);

 
 

-           if (REG_RD(pDevice,rxCpu.reg.mode) & CPU_MODE_HALT)
-             break;
-       }
+                       if (REG_RD (pDevice, rxCpu.reg.mode) & CPU_MODE_HALT)
+                               break;
+               }

 
 

-       REG_WR(pDevice,rxCpu.reg.state, 0xffffffff);
-       REG_WR(pDevice,rxCpu.reg.mode,CPU_MODE_HALT);
-       MM_Wait(10);
-    }
-    else
-    {
-       for (i = 0 ; i < 10000; i++)
-       {
-           REG_WR(pDevice,txCpu.reg.state, 0xffffffff);
-           REG_WR(pDevice,txCpu.reg.mode,CPU_MODE_HALT);
+               REG_WR (pDevice, rxCpu.reg.state, 0xffffffff);
+               REG_WR (pDevice, rxCpu.reg.mode, CPU_MODE_HALT);
+               MM_Wait (10);
+       } else {
+               for (i = 0; i < 10000; i++) {
+                       REG_WR (pDevice, txCpu.reg.state, 0xffffffff);
+                       REG_WR (pDevice, txCpu.reg.mode, CPU_MODE_HALT);

 
 

-           if (REG_RD(pDevice,txCpu.reg.mode) & CPU_MODE_HALT)
-              break;
+                       if (REG_RD (pDevice, txCpu.reg.mode) & CPU_MODE_HALT)
+                               break;
+               }

        }
        }

-    }

 
 

-  return (( i == 10000) ? LM_STATUS_FAILURE : LM_STATUS_SUCCESS);
+       return ((i == 10000) ? LM_STATUS_FAILURE : LM_STATUS_SUCCESS);

 }
 
 }
 

-
-int
-LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec)
+int LM_BlinkLED (PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec)

 {
        LM_UINT32 Oldcfg;
        int j;
        int ret = 0;
 
 {
        LM_UINT32 Oldcfg;
        int j;
        int ret = 0;
 

-       if(BlinkDurationSec == 0)
-       {
+       if (BlinkDurationSec == 0) {

                return 0;
        }
                return 0;
        }

-       if(BlinkDurationSec > 120)
-       {
+       if (BlinkDurationSec > 120) {

                BlinkDurationSec = 120;
        }
 
                BlinkDurationSec = 120;
        }
 

-       Oldcfg = REG_RD(pDevice, MacCtrl.LedCtrl);
-       for(j = 0; j < BlinkDurationSec * 2; j++)
-       {
-               if(j % 2)
-               {
+       Oldcfg = REG_RD (pDevice, MacCtrl.LedCtrl);
+       for (j = 0; j < BlinkDurationSec * 2; j++) {
+               if (j % 2) {

                        /* Turn on the LEDs. */
                        /* Turn on the LEDs. */

-                       REG_WR(pDevice, MacCtrl.LedCtrl,
+                       REG_WR (pDevice, MacCtrl.LedCtrl,

                                LED_CTRL_OVERRIDE_LINK_LED |
                                LED_CTRL_1000MBPS_LED_ON |
                                LED_CTRL_100MBPS_LED_ON |
                                LED_CTRL_OVERRIDE_LINK_LED |
                                LED_CTRL_1000MBPS_LED_ON |
                                LED_CTRL_100MBPS_LED_ON |


@@ -6047,154 +5547,152 @@ LM_BlinkLED(PLM_DEVICE_BLOCK pDevice, LM_UINT32 BlinkDurationSec)
                                LED_CTRL_OVERRIDE_TRAFFIC_LED |
                                LED_CTRL_BLINK_TRAFFIC_LED |
                                LED_CTRL_TRAFFIC_LED);
                                LED_CTRL_OVERRIDE_TRAFFIC_LED |
                                LED_CTRL_BLINK_TRAFFIC_LED |
                                LED_CTRL_TRAFFIC_LED);

-               }
-               else
-               {
+               } else {

                        /* Turn off the LEDs. */
                        /* Turn off the LEDs. */

-                       REG_WR(pDevice, MacCtrl.LedCtrl,
+                       REG_WR (pDevice, MacCtrl.LedCtrl,

                                LED_CTRL_OVERRIDE_LINK_LED |
                                LED_CTRL_OVERRIDE_TRAFFIC_LED);
                }
 
 #ifndef EMBEDDED
                current->state = TASK_INTERRUPTIBLE;
                                LED_CTRL_OVERRIDE_LINK_LED |
                                LED_CTRL_OVERRIDE_TRAFFIC_LED);
                }
 
 #ifndef EMBEDDED
                current->state = TASK_INTERRUPTIBLE;

-               if (schedule_timeout(HZ/2) != 0) {
+               if (schedule_timeout (HZ / 2) != 0) {

                        ret = -EINTR;
                        break;
                }
 #else
                        ret = -EINTR;
                        break;
                }
 #else

-               udelay(100000);  /* 1s sleep */
+               udelay (100000);        /* 1s sleep */

 #endif
        }
 #endif
        }

-       REG_WR(pDevice, MacCtrl.LedCtrl, Oldcfg);
+       REG_WR (pDevice, MacCtrl.LedCtrl, Oldcfg);

        return ret;
 }
 
        return ret;
 }
 

-int t3_do_dma(PLM_DEVICE_BLOCK pDevice,
-                  LM_PHYSICAL_ADDRESS host_addr_phy, int length,
-                  int dma_read)
+int t3_do_dma (PLM_DEVICE_BLOCK pDevice,
+              LM_PHYSICAL_ADDRESS host_addr_phy, int length, int dma_read)

 {
 {

-    T3_DMA_DESC dma_desc;
-    int i;
-    LM_UINT32 dma_desc_addr;
-    LM_UINT32 value32;
-
-    REG_WR(pDevice, BufMgr.Mode, 0);
-    REG_WR(pDevice, Ftq.Reset, 0);
-
-    dma_desc.host_addr.High = host_addr_phy.High;
-    dma_desc.host_addr.Low = host_addr_phy.Low;
-    dma_desc.nic_mbuf = 0x2100;
-    dma_desc.len = length;
-    dma_desc.flags = 0x00000004; /* Generate Rx-CPU event */
-
-    if (dma_read)
-    {
-       dma_desc.cqid_sqid = (T3_QID_RX_BD_COMP << 8) |
-           T3_QID_DMA_HIGH_PRI_READ;
-       REG_WR(pDevice, DmaRead.Mode, DMA_READ_MODE_ENABLE);
-    }
-    else
-    {
-       dma_desc.cqid_sqid = (T3_QID_RX_DATA_COMP << 8) |
-           T3_QID_DMA_HIGH_PRI_WRITE;
-       REG_WR(pDevice, DmaWrite.Mode, DMA_WRITE_MODE_ENABLE);
-    }
-
-    dma_desc_addr = T3_NIC_DMA_DESC_POOL_ADDR;
-
-    /* Writing this DMA descriptor to DMA memory */
-    for (i = 0; i < sizeof(T3_DMA_DESC); i += 4)
-    {
-       value32 = *((PLM_UINT32) (((PLM_UINT8) &dma_desc) + i));
-       MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, dma_desc_addr+i);
-       MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_DATA_REG, cpu_to_le32(value32));
-    }
-    MM_WriteConfig32(pDevice, T3_PCI_MEM_WIN_ADDR_REG, 0);
-
-    if (dma_read)
-       REG_WR(pDevice, Ftq.DmaHighReadFtqFifoEnqueueDequeue, dma_desc_addr);
-    else
-       REG_WR(pDevice, Ftq.DmaHighWriteFtqFifoEnqueueDequeue, dma_desc_addr);
-
-    for (i = 0; i < 40; i++)
-    {
+       T3_DMA_DESC dma_desc;
+       int i;
+       LM_UINT32 dma_desc_addr;
+       LM_UINT32 value32;
+
+       REG_WR (pDevice, BufMgr.Mode, 0);
+       REG_WR (pDevice, Ftq.Reset, 0);
+
+       dma_desc.host_addr.High = host_addr_phy.High;
+       dma_desc.host_addr.Low = host_addr_phy.Low;
+       dma_desc.nic_mbuf = 0x2100;
+       dma_desc.len = length;
+       dma_desc.flags = 0x00000004;    /* Generate Rx-CPU event */
+
+       if (dma_read) {
+               dma_desc.cqid_sqid = (T3_QID_RX_BD_COMP << 8) |
+                   T3_QID_DMA_HIGH_PRI_READ;
+               REG_WR (pDevice, DmaRead.Mode, DMA_READ_MODE_ENABLE);
+       } else {
+               dma_desc.cqid_sqid = (T3_QID_RX_DATA_COMP << 8) |
+                   T3_QID_DMA_HIGH_PRI_WRITE;
+               REG_WR (pDevice, DmaWrite.Mode, DMA_WRITE_MODE_ENABLE);
+       }
+
+       dma_desc_addr = T3_NIC_DMA_DESC_POOL_ADDR;
+
+       /* Writing this DMA descriptor to DMA memory */
+       for (i = 0; i < sizeof (T3_DMA_DESC); i += 4) {
+               value32 = *((PLM_UINT32) (((PLM_UINT8) & dma_desc) + i));
+               MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG,
+                                 dma_desc_addr + i);
+               MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_DATA_REG,
+                                 cpu_to_le32 (value32));
+       }
+       MM_WriteConfig32 (pDevice, T3_PCI_MEM_WIN_ADDR_REG, 0);
+

        if (dma_read)
        if (dma_read)

-           value32 = REG_RD(pDevice, Ftq.RcvBdCompFtqFifoEnqueueDequeue);
+               REG_WR (pDevice, Ftq.DmaHighReadFtqFifoEnqueueDequeue,
+                       dma_desc_addr);

        else
        else

-           value32 = REG_RD(pDevice, Ftq.RcvDataCompFtqFifoEnqueueDequeue);
+               REG_WR (pDevice, Ftq.DmaHighWriteFtqFifoEnqueueDequeue,
+                       dma_desc_addr);
+
+       for (i = 0; i < 40; i++) {
+               if (dma_read)
+                       value32 =
+                           REG_RD (pDevice,
+                                   Ftq.RcvBdCompFtqFifoEnqueueDequeue);
+               else
+                       value32 =
+                           REG_RD (pDevice,
+                                   Ftq.RcvDataCompFtqFifoEnqueueDequeue);

 
 

-       if ((value32 & 0xffff) == dma_desc_addr)
-           break;
+               if ((value32 & 0xffff) == dma_desc_addr)
+                       break;

 
 

-       MM_Wait(10);
-    }
+               MM_Wait (10);
+       }

 
 

-    return LM_STATUS_SUCCESS;
+       return LM_STATUS_SUCCESS;

 }
 
 STATIC LM_STATUS
 }
 
 STATIC LM_STATUS

-LM_DmaTest(PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
-          LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize)
+LM_DmaTest (PLM_DEVICE_BLOCK pDevice, PLM_UINT8 pBufferVirt,
+           LM_PHYSICAL_ADDRESS BufferPhy, LM_UINT32 BufferSize)

 {
 {

-    int j;
-    LM_UINT32 *ptr;
-    int dma_success = 0;
+       int j;
+       LM_UINT32 *ptr;
+       int dma_success = 0;
+
+       if (T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
+           T3_ASIC_REV (pDevice->ChipRevId) != T3_ASIC_REV_5701) {
+               return LM_STATUS_SUCCESS;
+       }
+       while (!dma_success) {
+               /* Fill data with incremental patterns */
+               ptr = (LM_UINT32 *) pBufferVirt;
+               for (j = 0; j < BufferSize / 4; j++)
+                       *ptr++ = j;
+
+               if (t3_do_dma (pDevice, BufferPhy, BufferSize, 1) ==
+                   LM_STATUS_FAILURE) {
+                       return LM_STATUS_FAILURE;
+               }

 
 

-    if(T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5700 &&
-       T3_ASIC_REV(pDevice->ChipRevId) != T3_ASIC_REV_5701)
-    {
-       return LM_STATUS_SUCCESS;
-    }
-    while (!dma_success)
-    {
-       /* Fill data with incremental patterns */
-       ptr = (LM_UINT32 *)pBufferVirt;
-       for (j = 0; j < BufferSize/4; j++)
-           *ptr++ = j;
-
-       if (t3_do_dma(pDevice,BufferPhy,BufferSize, 1) == LM_STATUS_FAILURE)
-       {
-           return LM_STATUS_FAILURE;
-       }
+               MM_Wait (40);
+               ptr = (LM_UINT32 *) pBufferVirt;
+               /* Fill data with zero */
+               for (j = 0; j < BufferSize / 4; j++)
+                       *ptr++ = 0;

 
 

-       MM_Wait(40);
-       ptr = (LM_UINT32 *)pBufferVirt;
-       /* Fill data with zero */
-       for (j = 0; j < BufferSize/4; j++)
-           *ptr++ = 0;
+               if (t3_do_dma (pDevice, BufferPhy, BufferSize, 0) ==
+                   LM_STATUS_FAILURE) {
+                       return LM_STATUS_FAILURE;
+               }

 
 

-       if (t3_do_dma(pDevice,BufferPhy,BufferSize, 0) == LM_STATUS_FAILURE)
-       {
-           return LM_STATUS_FAILURE;
+               MM_Wait (40);
+               /* Check for data */
+               ptr = (LM_UINT32 *) pBufferVirt;
+               for (j = 0; j < BufferSize / 4; j++) {
+                       if (*ptr++ != j) {
+                               if ((pDevice->
+                                    DmaReadWriteCtrl &
+                                    DMA_CTRL_WRITE_BOUNDARY_MASK)
+                                   == DMA_CTRL_WRITE_BOUNDARY_DISABLE) {
+                                       pDevice->DmaReadWriteCtrl =
+                                           (pDevice->
+                                            DmaReadWriteCtrl &
+                                            ~DMA_CTRL_WRITE_BOUNDARY_MASK) |
+                                           DMA_CTRL_WRITE_BOUNDARY_16;
+                                       REG_WR (pDevice,
+                                               PciCfg.DmaReadWriteCtrl,
+                                               pDevice->DmaReadWriteCtrl);
+                                       break;
+                               } else {
+                                       return LM_STATUS_FAILURE;
+                               }
+                       }
+               }
+               if (j == (BufferSize / 4))
+                       dma_success = 1;

        }
        }

-
-       MM_Wait(40);
-       /* Check for data */
-       ptr = (LM_UINT32 *)pBufferVirt;
-       for (j = 0; j < BufferSize/4; j++)
-       {
-           if (*ptr++ != j)
-           {
-               if ((pDevice->DmaReadWriteCtrl & DMA_CTRL_WRITE_BOUNDARY_MASK)
-                   == DMA_CTRL_WRITE_BOUNDARY_DISABLE)
-               {
-                   pDevice->DmaReadWriteCtrl = (pDevice->DmaReadWriteCtrl &
-                        ~DMA_CTRL_WRITE_BOUNDARY_MASK) |
-                         DMA_CTRL_WRITE_BOUNDARY_16;
-                   REG_WR(pDevice, PciCfg.DmaReadWriteCtrl,
-                          pDevice->DmaReadWriteCtrl);
-                   break;
-                }
-                else
-                {
-                    return LM_STATUS_FAILURE;
-                }
-           }
-       }
-       if (j == (BufferSize/4))
-           dma_success = 1;
-    }
-    return LM_STATUS_SUCCESS;
+       return LM_STATUS_SUCCESS;

 }
 }

-#endif /* CFG_CMD_NET, !CONFIG_NET_MULTI, CONFIG_TIGON3 */
+#endif                         /* CFG_CMD_NET, !CONFIG_NET_MULTI, CONFIG_TIGON3 */

diff --git a/drivers/tigon3.h b/drivers/tigon3.h
index ea4367d61d227a0c2e90f44c3a206ec5ee257c90..c03347fdc9bccc454d67bc82ab55329b501f0f9f 100644 (file)
--- a/drivers/tigon3.h
+++ b/drivers/tigon3.h
@@ -21,7 +21,6 @@
 #include "bcm570x_autoneg.h"
 #endif
 
 #include "bcm570x_autoneg.h"
 #endif
 

-

 /* io defines */
 #if !defined(BIG_ENDIAN_HOST)
 #define readl(addr) \
 /* io defines */
 #if !defined(BIG_ENDIAN_HOST)
 #define readl(addr) \


@@ -29,7 +28,7 @@
 #define writel(b,addr) \
              ((*(volatile unsigned int *)(addr)) = (LONGSWAP(b)))
 #else
 #define writel(b,addr) \
              ((*(volatile unsigned int *)(addr)) = (LONGSWAP(b)))
 #else

-#if 0 /* !defined(PPC603) */
+#if 0                          /* !defined(PPC603) */

 #define readl(addr) (*(volatile unsigned int*)(0xa0000000 + (unsigned long)(addr)))
 #define writel(b,addr) ((*(volatile unsigned int *) ((unsigned long)(addr) + 0xa0000000)) = (b))
 #else
 #define readl(addr) (*(volatile unsigned int*)(0xa0000000 + (unsigned long)(addr)))
 #define writel(b,addr) ((*(volatile unsigned int *) ((unsigned long)(addr) + 0xa0000000)) = (b))
 #else


@@ -37,25 +36,28 @@
 #define readl(addr) (*(volatile unsigned int*)(addr))
 #define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b))
 #else
 #define readl(addr) (*(volatile unsigned int*)(addr))
 #define writel(b,addr) ((*(volatile unsigned int *) (addr)) = (b))
 #else

-extern int sprintf(char* buf, const char* f, ...);
-static __inline unsigned int readl(void* addr){
-    char buf[128];
-    unsigned int tmp = (*(volatile unsigned int*)(addr));
-    sprintf(buf,"%s:%s: read 0x%x from 0x%x\n",__FILE__,__LINE__,tmp,addr,0,0);
-    sysSerialPrintString(buf);
-    return tmp;
+extern int sprintf (char *buf, const char *f, ...);
+static __inline unsigned int readl (void *addr)
+{
+       char buf[128];
+       unsigned int tmp = (*(volatile unsigned int *)(addr));
+       sprintf (buf, "%s:%s: read 0x%x from 0x%x\n", __FILE__, __LINE__, tmp,
+                addr, 0, 0);
+       sysSerialPrintString (buf);
+       return tmp;

 }
 }

-static __inline void writel(unsigned int b, unsigned int addr){
-    char buf[128];
-    ((*(volatile unsigned int *) (addr)) = (b));
-    sprintf(buf,"%s:%s: write 0x%x to 0x%x\n",__FILE__,__LINE__,b,addr,0,0);
-    sysSerialPrintString(buf);
+static __inline void writel (unsigned int b, unsigned int addr)
+{
+       char buf[128];
+       ((*(volatile unsigned int *)(addr)) = (b));
+       sprintf (buf, "%s:%s: write 0x%x to 0x%x\n", __FILE__, __LINE__, b,
+                addr, 0, 0);
+       sysSerialPrintString (buf);

 }
 #endif
 }
 #endif

-#endif /* PPC603 */
+#endif                         /* PPC603 */

 #endif
 
 #endif
 

-

 /******************************************************************************/
 /* Constants. */
 /******************************************************************************/
 /******************************************************************************/
 /* Constants. */
 /******************************************************************************/


@@ -90,7 +92,7 @@ static __inline void writel(unsigned int b, unsigned int addr){
 
 /* B0 bug. */
 #define BCM5700_BX_MIN_FRAG_SIZE            10
 
 /* B0 bug. */
 #define BCM5700_BX_MIN_FRAG_SIZE            10

-#define BCM5700_BX_MIN_FRAG_BUF_SIZE        16  /* nice aligned size. */
+#define BCM5700_BX_MIN_FRAG_BUF_SIZE        16 /* nice aligned size. */

 #define BCM5700_BX_MIN_FRAG_BUF_SIZE_MASK   (BCM5700_BX_MIN_FRAG_BUF_SIZE-1)
 #define BCM5700_BX_TX_COPY_BUF_SIZE         (BCM5700_BX_MIN_FRAG_BUF_SIZE * \
                                            MAX_FRAGMENT_COUNT)
 #define BCM5700_BX_MIN_FRAG_BUF_SIZE_MASK   (BCM5700_BX_MIN_FRAG_BUF_SIZE-1)
 #define BCM5700_BX_TX_COPY_BUF_SIZE         (BCM5700_BX_MIN_FRAG_BUF_SIZE * \
                                            MAX_FRAGMENT_COUNT)


@@ -161,32 +163,32 @@ static __inline void writel(unsigned int b, unsigned int addr){
 /* Number of entries in the Standard Receive RCB.  Must be 512 entries. */
 #define T3_STD_RCV_RCB_ENTRY_COUNT          512
 #define T3_STD_RCV_RCB_ENTRY_COUNT_MASK     (T3_STD_RCV_RCB_ENTRY_COUNT-1)
 /* Number of entries in the Standard Receive RCB.  Must be 512 entries. */
 #define T3_STD_RCV_RCB_ENTRY_COUNT          512
 #define T3_STD_RCV_RCB_ENTRY_COUNT_MASK     (T3_STD_RCV_RCB_ENTRY_COUNT-1)

-#define DEFAULT_STD_RCV_DESC_COUNT          200    /* Must be < 512. */
+#define DEFAULT_STD_RCV_DESC_COUNT          200        /* Must be < 512. */

 #define MAX_STD_RCV_BUFFER_SIZE             0x600
 
 /* Number of entries in the Mini Receive RCB.  This value can either be */
 /* 0, 1024.  Currently Mini Receive RCB is disabled. */
 #ifndef T3_MINI_RCV_RCB_ENTRY_COUNT
 #define T3_MINI_RCV_RCB_ENTRY_COUNT         0
 #define MAX_STD_RCV_BUFFER_SIZE             0x600
 
 /* Number of entries in the Mini Receive RCB.  This value can either be */
 /* 0, 1024.  Currently Mini Receive RCB is disabled. */
 #ifndef T3_MINI_RCV_RCB_ENTRY_COUNT
 #define T3_MINI_RCV_RCB_ENTRY_COUNT         0

-#endif /* T3_MINI_RCV_RCB_ENTRY_COUNT */
+#endif                         /* T3_MINI_RCV_RCB_ENTRY_COUNT */

 #define T3_MINI_RCV_RCB_ENTRY_COUNT_MASK    (T3_MINI_RCV_RCB_ENTRY_COUNT-1)
 #define MAX_MINI_RCV_BUFFER_SIZE            512
 #define DEFAULT_MINI_RCV_BUFFER_SIZE        64
 #define T3_MINI_RCV_RCB_ENTRY_COUNT_MASK    (T3_MINI_RCV_RCB_ENTRY_COUNT-1)
 #define MAX_MINI_RCV_BUFFER_SIZE            512
 #define DEFAULT_MINI_RCV_BUFFER_SIZE        64

-#define DEFAULT_MINI_RCV_DESC_COUNT         100    /* Must be < 1024. */
+#define DEFAULT_MINI_RCV_DESC_COUNT         100        /* Must be < 1024. */

 
 /* Number of entries in the Jumbo Receive RCB.  This value must 256 or 0. */
 /* Currently, Jumbo Receive RCB is disabled. */
 #ifndef T3_JUMBO_RCV_RCB_ENTRY_COUNT
 #define T3_JUMBO_RCV_RCB_ENTRY_COUNT        0
 
 /* Number of entries in the Jumbo Receive RCB.  This value must 256 or 0. */
 /* Currently, Jumbo Receive RCB is disabled. */
 #ifndef T3_JUMBO_RCV_RCB_ENTRY_COUNT
 #define T3_JUMBO_RCV_RCB_ENTRY_COUNT        0

-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+#endif                         /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */

 #define T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK   (T3_JUMBO_RCV_RCB_ENTRY_COUNT-1)
 
 #define T3_JUMBO_RCV_RCB_ENTRY_COUNT_MASK   (T3_JUMBO_RCV_RCB_ENTRY_COUNT-1)
 

-#define MAX_JUMBO_RCV_BUFFER_SIZE           (10 * 1024) /* > 1514 */
-#define DEFAULT_JUMBO_RCV_BUFFER_SIZE       (4 * 1024) /* > 1514 */
-#define DEFAULT_JUMBO_RCV_DESC_COUNT        128     /* Must be < 256. */
+#define MAX_JUMBO_RCV_BUFFER_SIZE           (10 * 1024)        /* > 1514 */
+#define DEFAULT_JUMBO_RCV_BUFFER_SIZE       (4 * 1024) /* > 1514 */
+#define DEFAULT_JUMBO_RCV_DESC_COUNT        128        /* Must be < 256. */

 
 

-#define MAX_JUMBO_TX_BUFFER_SIZE            (8 * 1024) /* > 1514 */
-#define DEFAULT_JUMBO_TX_BUFFER_SIZE        (4 * 1024) /* > 1514 */
+#define MAX_JUMBO_TX_BUFFER_SIZE            (8 * 1024) /* > 1514 */
+#define DEFAULT_JUMBO_TX_BUFFER_SIZE        (4 * 1024) /* > 1514 */

 
 /* Number of receive return RCBs.  Maybe 1-16 but for now, only support one. */
 #define T3_MAX_RCV_RETURN_RCB_COUNT         16
 
 /* Number of receive return RCBs.  Maybe 1-16 but for now, only support one. */
 #define T3_MAX_RCV_RETURN_RCB_COUNT         16


@@ -195,10 +197,9 @@ static __inline void writel(unsigned int b, unsigned int addr){
 /* or 2048. */
 #ifndef T3_RCV_RETURN_RCB_ENTRY_COUNT
 #define T3_RCV_RETURN_RCB_ENTRY_COUNT       1024
 /* or 2048. */
 #ifndef T3_RCV_RETURN_RCB_ENTRY_COUNT
 #define T3_RCV_RETURN_RCB_ENTRY_COUNT       1024

-#endif /* T3_RCV_RETURN_RCB_ENTRY_COUNT */
+#endif                         /* T3_RCV_RETURN_RCB_ENTRY_COUNT */

 #define T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK  (T3_RCV_RETURN_RCB_ENTRY_COUNT-1)
 
 #define T3_RCV_RETURN_RCB_ENTRY_COUNT_MASK  (T3_RCV_RETURN_RCB_ENTRY_COUNT-1)
 

-

 /* Default coalescing parameters. */
 #define DEFAULT_RX_COALESCING_TICKS         100
 #define MAX_RX_COALESCING_TICKS             500
 /* Default coalescing parameters. */
 #define DEFAULT_RX_COALESCING_TICKS         100
 #define MAX_RX_COALESCING_TICKS             500


@@ -227,7 +228,6 @@ static __inline void writel(unsigned int b, unsigned int addr){
 #define DEFAULT_STATS_COALESCING_TICKS      1000000
 #define MAX_STATS_COALESCING_TICKS          3600000000U
 
 #define DEFAULT_STATS_COALESCING_TICKS      1000000
 #define MAX_STATS_COALESCING_TICKS          3600000000U
 

-

 /* Receive BD Replenish thresholds. */
 #define DEFAULT_RCV_STD_BD_REPLENISH_THRESHOLD      4
 #define DEFAULT_RCV_JUMBO_BD_REPLENISH_THRESHOLD    4
 /* Receive BD Replenish thresholds. */
 #define DEFAULT_RCV_STD_BD_REPLENISH_THRESHOLD      4
 #define DEFAULT_RCV_JUMBO_BD_REPLENISH_THRESHOLD    4


@@ -240,12 +240,10 @@ static __inline void writel(unsigned int b, unsigned int addr){
 /* Maximum physical fragment size. */
 #define MAX_FRAGMENT_SIZE                   (64 * 1024)
 
 /* Maximum physical fragment size. */
 #define MAX_FRAGMENT_SIZE                   (64 * 1024)
 

-

 /* Standard view. */
 #define T3_STD_VIEW_SIZE                    (64 * 1024)
 #define T3_FLAT_VIEW_SIZE                   (32 * 1024 * 1024)
 
 /* Standard view. */
 #define T3_STD_VIEW_SIZE                    (64 * 1024)
 #define T3_FLAT_VIEW_SIZE                   (32 * 1024 * 1024)
 

-

 /* Buffer descriptor base address on the NIC's memory. */
 
 #define T3_NIC_SND_BUFFER_DESC_ADDR         0x4000
 /* Buffer descriptor base address on the NIC's memory. */
 
 #define T3_NIC_SND_BUFFER_DESC_ADDR         0x4000


@@ -265,19 +263,17 @@ static __inline void writel(unsigned int b, unsigned int addr){
 #define T3_NIC_JUMBO_RCV_BUFFER_DESC_SIZE   (T3_JUMBO_RCV_RCB_ENTRY_COUNT * \
                                            sizeof(T3_EXT_RCV_BD) / 4)
 
 #define T3_NIC_JUMBO_RCV_BUFFER_DESC_SIZE   (T3_JUMBO_RCV_RCB_ENTRY_COUNT * \
                                            sizeof(T3_EXT_RCV_BD) / 4)
 

-

 /* MBUF pool. */
 #define T3_NIC_MBUF_POOL_ADDR               0x8000
 /* #define T3_NIC_MBUF_POOL_SIZE               0x18000 */
 #define T3_NIC_MBUF_POOL_SIZE96             0x18000
 #define T3_NIC_MBUF_POOL_SIZE64             0x10000
 
 /* MBUF pool. */
 #define T3_NIC_MBUF_POOL_ADDR               0x8000
 /* #define T3_NIC_MBUF_POOL_SIZE               0x18000 */
 #define T3_NIC_MBUF_POOL_SIZE96             0x18000
 #define T3_NIC_MBUF_POOL_SIZE64             0x10000
 

-

 #define T3_NIC_MBUF_POOL_ADDR_EXT_MEM       0x20000
 
 /* DMA descriptor pool */
 #define T3_NIC_DMA_DESC_POOL_ADDR           0x2000
 #define T3_NIC_MBUF_POOL_ADDR_EXT_MEM       0x20000
 
 /* DMA descriptor pool */
 #define T3_NIC_DMA_DESC_POOL_ADDR           0x2000

-#define T3_NIC_DMA_DESC_POOL_SIZE           0x2000      /* 8KB. */
+#define T3_NIC_DMA_DESC_POOL_SIZE           0x2000     /* 8KB. */

 
 #define T3_DEF_DMA_MBUF_LOW_WMARK           0x40
 #define T3_DEF_RX_MAC_MBUF_LOW_WMARK        0x20
 
 #define T3_DEF_DMA_MBUF_LOW_WMARK           0x40
 #define T3_DEF_RX_MAC_MBUF_LOW_WMARK        0x20


@@ -301,24 +297,21 @@ static __inline void writel(unsigned int b, unsigned int addr){
 #define T3_TX_CPU_SPAD_ADDR  0x34000
 #define T3_TX_CPU_SPAD_SIZE  0x4000
 
 #define T3_TX_CPU_SPAD_ADDR  0x34000
 #define T3_TX_CPU_SPAD_SIZE  0x4000
 

-typedef struct T3_DIR_ENTRY
-{
-  PLM_UINT8 Buffer;
-  LM_UINT32 Offset;
-  LM_UINT32 Length;
-} T3_DIR_ENTRY,*PT3_DIR_ENTRY;
-
-typedef struct T3_FWIMG_INFO
-{
-  LM_UINT32 StartAddress;
-  T3_DIR_ENTRY Text;
-  T3_DIR_ENTRY ROnlyData;
-  T3_DIR_ENTRY Data;
-  T3_DIR_ENTRY Sbss;
-  T3_DIR_ENTRY Bss;
+typedef struct T3_DIR_ENTRY {
+       PLM_UINT8 Buffer;
+       LM_UINT32 Offset;
+       LM_UINT32 Length;
+} T3_DIR_ENTRY, *PT3_DIR_ENTRY;
+
+typedef struct T3_FWIMG_INFO {
+       LM_UINT32 StartAddress;
+       T3_DIR_ENTRY Text;
+       T3_DIR_ENTRY ROnlyData;
+       T3_DIR_ENTRY Data;
+       T3_DIR_ENTRY Sbss;
+       T3_DIR_ENTRY Bss;

 } T3_FWIMG_INFO, *PT3_FWIMG_INFO;
 
 } T3_FWIMG_INFO, *PT3_FWIMG_INFO;
 

-

 /******************************************************************************/
 /* Tigon3 PCI Registers. */
 /******************************************************************************/
 /******************************************************************************/
 /* Tigon3 PCI Registers. */
 /******************************************************************************/


@@ -362,7 +355,6 @@ typedef struct T3_FWIMG_INFO
 #define T3_ASIC_REV_5703                    0x01
 #define T3_ASIC_REV_5704                    0x02
 
 #define T3_ASIC_REV_5703                    0x01
 #define T3_ASIC_REV_5704                    0x02
 

-

 /* Chip id and revision. */
 #define T3_CHIP_REV(_ChipRevId)             ((_ChipRevId) >> 8)
 #define T3_CHIP_REV_5700_AX                 0x70
 /* Chip id and revision. */
 #define T3_CHIP_REV(_ChipRevId)             ((_ChipRevId) >> 8)
 #define T3_CHIP_REV_5700_AX                 0x70


@@ -386,7 +378,6 @@ typedef struct T3_FWIMG_INFO
 #define T3_PCI_POWER_DOWN_PCI_PLL133        BIT_15
 #define T3_PCI_44MHZ_CORE_CLOCK             BIT_18
 
 #define T3_PCI_POWER_DOWN_PCI_PLL133        BIT_15
 #define T3_PCI_44MHZ_CORE_CLOCK             BIT_18
 

-

 #define T3_PCI_REG_ADDR_REG                 0x78
 #define T3_PCI_REG_DATA_REG                 0x80
 
 #define T3_PCI_REG_ADDR_REG                 0x78
 #define T3_PCI_REG_DATA_REG                 0x80
 


@@ -409,7 +400,6 @@ typedef struct T3_FWIMG_INFO
 #define T3_PM_PME_ENABLE                    BIT_8
 #define T3_PM_PME_ASSERTED                  BIT_15
 
 #define T3_PM_PME_ENABLE                    BIT_8
 #define T3_PM_PME_ASSERTED                  BIT_15
 

-

 /* PCI state register. */
 #define T3_PCI_STATE_REG                    0x70
 
 /* PCI state register. */
 #define T3_PCI_STATE_REG                    0x70
 


@@ -419,17 +409,16 @@ typedef struct T3_FWIMG_INFO
 #define T3_PCI_STATE_BUS_SPEED_HIGH         BIT_3
 #define T3_PCI_STATE_32BIT_PCI_BUS          BIT_4
 
 #define T3_PCI_STATE_BUS_SPEED_HIGH         BIT_3
 #define T3_PCI_STATE_32BIT_PCI_BUS          BIT_4
 

-

 /* Broadcom subsystem/subvendor IDs. */
 #define T3_SVID_BROADCOM                            0x14e4
 
 #define T3_SSID_BROADCOM_BCM95700A6                 0x1644
 #define T3_SSID_BROADCOM_BCM95701A5                 0x0001
 /* Broadcom subsystem/subvendor IDs. */
 #define T3_SVID_BROADCOM                            0x14e4
 
 #define T3_SSID_BROADCOM_BCM95700A6                 0x1644
 #define T3_SSID_BROADCOM_BCM95701A5                 0x0001

-#define T3_SSID_BROADCOM_BCM95700T6                 0x0002  /* BCM8002 */
-#define T3_SSID_BROADCOM_BCM95700A9                 0x0003  /* Agilent */
+#define T3_SSID_BROADCOM_BCM95700T6                 0x0002     /* BCM8002 */
+#define T3_SSID_BROADCOM_BCM95700A9                 0x0003     /* Agilent */

 #define T3_SSID_BROADCOM_BCM95701T1                 0x0005
 #define T3_SSID_BROADCOM_BCM95701T8                 0x0006
 #define T3_SSID_BROADCOM_BCM95701T1                 0x0005
 #define T3_SSID_BROADCOM_BCM95701T8                 0x0006

-#define T3_SSID_BROADCOM_BCM95701A7                 0x0007  /* Agilent */
+#define T3_SSID_BROADCOM_BCM95701A7                 0x0007     /* Agilent */

 #define T3_SSID_BROADCOM_BCM95701A10                0x0008
 #define T3_SSID_BROADCOM_BCM95701A12                0x8008
 #define T3_SSID_BROADCOM_BCM95703Ax1                0x0009
 #define T3_SSID_BROADCOM_BCM95701A10                0x0008
 #define T3_SSID_BROADCOM_BCM95701A12                0x8008
 #define T3_SSID_BROADCOM_BCM95703Ax1                0x0009


@@ -449,7 +438,6 @@ typedef struct T3_FWIMG_INFO
 #define T3_SSID_3COM_3C996SX                        0x1004
 #define T3_SSID_3COM_3C997SX                        0x1005
 
 #define T3_SSID_3COM_3C996SX                        0x1004
 #define T3_SSID_3COM_3C997SX                        0x1005
 

-

 /* Dell subsystem/subvendor IDs. */
 
 #define T3_SVID_DELL                                0x1028
 /* Dell subsystem/subvendor IDs. */
 
 #define T3_SVID_DELL                                0x1028


@@ -469,7 +457,6 @@ typedef struct T3_FWIMG_INFO
 #define T3_SSID_COMPAQ_NC7780                       0x0085
 #define T3_SSID_COMPAQ_NC7780_2                     0x0099
 
 #define T3_SSID_COMPAQ_NC7780                       0x0085
 #define T3_SSID_COMPAQ_NC7780_2                     0x0099
 

-

 /******************************************************************************/
 /* MII registers. */
 /******************************************************************************/
 /******************************************************************************/
 /* MII registers. */
 /******************************************************************************/


@@ -490,14 +477,12 @@ typedef struct T3_FWIMG_INFO
 #define PHY_CTRL_LOOPBACK_MODE                      BIT_14
 #define PHY_CTRL_PHY_RESET                          BIT_15
 
 #define PHY_CTRL_LOOPBACK_MODE                      BIT_14
 #define PHY_CTRL_PHY_RESET                          BIT_15
 

-

 /* Status register. */
 #define PHY_STATUS_REG                              0x01
 
 #define PHY_STATUS_LINK_PASS                        BIT_2
 #define PHY_STATUS_AUTO_NEG_COMPLETE                BIT_5
 
 /* Status register. */
 #define PHY_STATUS_REG                              0x01
 
 #define PHY_STATUS_LINK_PASS                        BIT_2
 #define PHY_STATUS_AUTO_NEG_COMPLETE                BIT_5
 

-

 /* Phy Id registers. */
 #define PHY_ID1_REG                                 0x02
 #define PHY_ID1_OUI_MASK                            0xffff
 /* Phy Id registers. */
 #define PHY_ID1_REG                                 0x02
 #define PHY_ID1_OUI_MASK                            0xffff


@@ -507,7 +492,6 @@ typedef struct T3_FWIMG_INFO
 #define PHY_ID2_MODEL_MASK                          0x03f0
 #define PHY_ID2_OUI_MASK                            0xfc00
 
 #define PHY_ID2_MODEL_MASK                          0x03f0
 #define PHY_ID2_OUI_MASK                            0xfc00
 

-

 /* Auto-negotiation advertisement register. */
 #define PHY_AN_AD_REG                               0x04
 
 /* Auto-negotiation advertisement register. */
 #define PHY_AN_AD_REG                               0x04
 


@@ -519,18 +503,15 @@ typedef struct T3_FWIMG_INFO
 #define PHY_AN_AD_100BASETX_FULL                    BIT_8
 #define PHY_AN_AD_PROTOCOL_802_3_CSMA_CD            0x01
 
 #define PHY_AN_AD_100BASETX_FULL                    BIT_8
 #define PHY_AN_AD_PROTOCOL_802_3_CSMA_CD            0x01
 

-

 /* Auto-negotiation Link Partner Ability register. */
 #define PHY_LINK_PARTNER_ABILITY_REG                0x05
 
 #define PHY_LINK_PARTNER_ASYM_PAUSE                 BIT_11
 #define PHY_LINK_PARTNER_PAUSE_CAPABLE              BIT_10
 
 /* Auto-negotiation Link Partner Ability register. */
 #define PHY_LINK_PARTNER_ABILITY_REG                0x05
 
 #define PHY_LINK_PARTNER_ASYM_PAUSE                 BIT_11
 #define PHY_LINK_PARTNER_PAUSE_CAPABLE              BIT_10
 

-

 /* Auto-negotiation expansion register. */
 #define PHY_AN_EXPANSION_REG                        0x06
 
 /* Auto-negotiation expansion register. */
 #define PHY_AN_EXPANSION_REG                        0x06
 

-

 /******************************************************************************/
 /* BCM5400 and BCM5401 phy info. */
 /******************************************************************************/
 /******************************************************************************/
 /* BCM5400 and BCM5401 phy info. */
 /******************************************************************************/


@@ -557,7 +538,6 @@ typedef struct T3_FWIMG_INFO
 #define PHY_ID_MASK                                 (PHY_ID_OUI_MASK |      \
                                                    PHY_ID_MODEL_MASK)
 
 #define PHY_ID_MASK                                 (PHY_ID_OUI_MASK |      \
                                                    PHY_ID_MODEL_MASK)
 

-

 #define UNKNOWN_PHY_ID(x)   ((((x) & PHY_ID_MASK) != PHY_BCM5400_PHY_ID) && \
                            (((x) & PHY_ID_MASK) != PHY_BCM5401_PHY_ID) && \
                            (((x) & PHY_ID_MASK) != PHY_BCM5411_PHY_ID) && \
 #define UNKNOWN_PHY_ID(x)   ((((x) & PHY_ID_MASK) != PHY_BCM5400_PHY_ID) && \
                            (((x) & PHY_ID_MASK) != PHY_BCM5401_PHY_ID) && \
                            (((x) & PHY_ID_MASK) != PHY_BCM5411_PHY_ID) && \


@@ -566,7 +546,6 @@ typedef struct T3_FWIMG_INFO
                            (((x) & PHY_ID_MASK) != PHY_BCM5704_PHY_ID) && \
                            (((x) & PHY_ID_MASK) != PHY_BCM8002_PHY_ID))
 
                            (((x) & PHY_ID_MASK) != PHY_BCM5704_PHY_ID) && \
                            (((x) & PHY_ID_MASK) != PHY_BCM8002_PHY_ID))
 

-

 /* 1000Base-T control register. */
 #define BCM540X_1000BASET_CTRL_REG                  0x09
 
 /* 1000Base-T control register. */
 #define BCM540X_1000BASET_CTRL_REG                  0x09
 


@@ -575,7 +554,6 @@ typedef struct T3_FWIMG_INFO
 #define BCM540X_CONFIG_AS_MASTER                    BIT_11
 #define BCM540X_ENABLE_CONFIG_AS_MASTER             BIT_12
 
 #define BCM540X_CONFIG_AS_MASTER                    BIT_11
 #define BCM540X_ENABLE_CONFIG_AS_MASTER             BIT_12
 

-

 /* Extended control register. */
 #define BCM540X_EXT_CTRL_REG                        0x10
 
 /* Extended control register. */
 #define BCM540X_EXT_CTRL_REG                        0x10
 


@@ -587,11 +565,9 @@ typedef struct T3_FWIMG_INFO
 
 #define BCM540X_EXT_STATUS_LINK_PASS                BIT_8
 
 
 #define BCM540X_EXT_STATUS_LINK_PASS                BIT_8
 

-

 /* DSP Coefficient Read/Write Port. */
 #define BCM540X_DSP_RW_PORT                         0x15
 
 /* DSP Coefficient Read/Write Port. */
 #define BCM540X_DSP_RW_PORT                         0x15
 

-

 /* DSP Coeficient Address Register. */
 #define BCM540X_DSP_ADDRESS_REG                     0x17
 
 /* DSP Coeficient Address Register. */
 #define BCM540X_DSP_ADDRESS_REG                     0x17
 


@@ -631,7 +607,6 @@ typedef struct T3_FWIMG_INFO
 
 #define BCM540X_CONTROL_ALL_CHANNELS                BIT_15
 
 
 #define BCM540X_CONTROL_ALL_CHANNELS                BIT_15
 

-

 /* Auxilliary Control Register (Shadow Register) */
 #define BCM5401_AUX_CTRL                            0x18
 
 /* Auxilliary Control Register (Shadow Register) */
 #define BCM5401_AUX_CTRL                            0x18
 


@@ -644,7 +619,6 @@ typedef struct T3_FWIMG_INFO
 #define BCM5401_SHADOW_SEL_MISC_TEST2               0x05
 #define BCM5401_SHADOW_SEL_IP_PHONE_SEED            0x06
 
 #define BCM5401_SHADOW_SEL_MISC_TEST2               0x05
 #define BCM5401_SHADOW_SEL_IP_PHONE_SEED            0x06
 

-

 /* Shadow register selector == '000' */
 #define BCM5401_SHDW_NORMAL_DIAG_MODE               BIT_3
 #define BCM5401_SHDW_NORMAL_DISABLE_MBP             BIT_4
 /* Shadow register selector == '000' */
 #define BCM5401_SHDW_NORMAL_DIAG_MODE               BIT_3
 #define BCM5401_SHDW_NORMAL_DISABLE_MBP             BIT_4


@@ -664,7 +638,6 @@ typedef struct T3_FWIMG_INFO
 #define BCM5401_SHDW_NORMAL_EXT_PACKET_LENGTH       BIT_14
 #define BCM5401_SHDW_NORMAL_EXTERNAL_LOOPBACK       BIT_15
 
 #define BCM5401_SHDW_NORMAL_EXT_PACKET_LENGTH       BIT_14
 #define BCM5401_SHDW_NORMAL_EXTERNAL_LOOPBACK       BIT_15
 

-

 /* Auxilliary status summary. */
 #define BCM540X_AUX_STATUS_REG                      0x19
 
 /* Auxilliary status summary. */
 #define BCM540X_AUX_STATUS_REG                      0x19
 


@@ -678,7 +651,6 @@ typedef struct T3_FWIMG_INFO
 #define BCM540X_AUX_100BASET_HD                     (BIT_9 | BIT_10)
 #define BCM540X_AUX_100BASET_FD                     (BIT_8 | BIT_9 | BIT_10)
 
 #define BCM540X_AUX_100BASET_HD                     (BIT_9 | BIT_10)
 #define BCM540X_AUX_100BASET_FD                     (BIT_8 | BIT_9 | BIT_10)
 

-

 /* Interrupt status. */
 #define BCM540X_INT_STATUS_REG                      0x1a
 
 /* Interrupt status. */
 #define BCM540X_INT_STATUS_REG                      0x1a
 


@@ -687,11 +659,9 @@ typedef struct T3_FWIMG_INFO
 #define BCM540X_INT_DUPLEX_CHANGE                   BIT_3
 #define BCM540X_INT_AUTO_NEG_PAGE_RX                BIT_10
 
 #define BCM540X_INT_DUPLEX_CHANGE                   BIT_3
 #define BCM540X_INT_AUTO_NEG_PAGE_RX                BIT_10
 

-

 /* Interrupt mask register. */
 #define BCM540X_INT_MASK_REG                        0x1b
 
 /* Interrupt mask register. */
 #define BCM540X_INT_MASK_REG                        0x1b
 

-

 /******************************************************************************/
 /* Register definitions. */
 /******************************************************************************/
 /******************************************************************************/
 /* Register definitions. */
 /******************************************************************************/


@@ -701,9 +671,9 @@ typedef volatile LM_UINT16 T3_16BIT_REGISTER, *PT3_16BIT_REGISTER;
 typedef volatile LM_UINT32 T3_32BIT_REGISTER, *PT3_32BIT_REGISTER;
 
 typedef struct {
 typedef volatile LM_UINT32 T3_32BIT_REGISTER, *PT3_32BIT_REGISTER;
 
 typedef struct {

-    /* Big endian format. */
-    T3_32BIT_REGISTER High;
-    T3_32BIT_REGISTER Low;
+       /* Big endian format. */
+       T3_32BIT_REGISTER High;
+       T3_32BIT_REGISTER Low;

 } T3_64BIT_REGISTER, *PT3_64BIT_REGISTER;
 
 typedef T3_64BIT_REGISTER T3_64BIT_HOST_ADDR, *PT3_64BIT_HOST_ADDR;
 } T3_64BIT_REGISTER, *PT3_64BIT_REGISTER;
 
 typedef T3_64BIT_REGISTER T3_64BIT_HOST_ADDR, *PT3_64BIT_HOST_ADDR;


@@ -711,47 +681,44 @@ typedef T3_64BIT_REGISTER T3_64BIT_HOST_ADDR, *PT3_64BIT_HOST_ADDR;
 #define T3_NUM_OF_DMA_DESC    256
 #define T3_NUM_OF_MBUF        768
 
 #define T3_NUM_OF_DMA_DESC    256
 #define T3_NUM_OF_MBUF        768
 

-typedef struct
-{
-  T3_64BIT_REGISTER host_addr;
-  T3_32BIT_REGISTER nic_mbuf;
-  T3_16BIT_REGISTER len;
-  T3_16BIT_REGISTER cqid_sqid;
-  T3_32BIT_REGISTER flags;
-  T3_32BIT_REGISTER opaque1;
-  T3_32BIT_REGISTER opaque2;
-  T3_32BIT_REGISTER opaque3;
-}T3_DMA_DESC, *PT3_DMA_DESC;
-
+typedef struct {
+       T3_64BIT_REGISTER host_addr;
+       T3_32BIT_REGISTER nic_mbuf;
+       T3_16BIT_REGISTER len;
+       T3_16BIT_REGISTER cqid_sqid;
+       T3_32BIT_REGISTER flags;
+       T3_32BIT_REGISTER opaque1;
+       T3_32BIT_REGISTER opaque2;
+       T3_32BIT_REGISTER opaque3;
+} T3_DMA_DESC, *PT3_DMA_DESC;

 
 /******************************************************************************/
 /* Ring control block. */
 /******************************************************************************/
 
 typedef struct {
 
 /******************************************************************************/
 /* Ring control block. */
 /******************************************************************************/
 
 typedef struct {

-    T3_64BIT_REGISTER HostRingAddr;
+       T3_64BIT_REGISTER HostRingAddr;

 
 

-    union {
-       struct {
+       union {
+               struct {

 #ifdef BIG_ENDIAN_HOST
 #ifdef BIG_ENDIAN_HOST

-           T3_16BIT_REGISTER MaxLen;
-           T3_16BIT_REGISTER Flags;
-#else /* BIG_ENDIAN_HOST */
-           T3_16BIT_REGISTER Flags;
-           T3_16BIT_REGISTER MaxLen;
+                       T3_16BIT_REGISTER MaxLen;
+                       T3_16BIT_REGISTER Flags;
+#else                          /* BIG_ENDIAN_HOST */
+                       T3_16BIT_REGISTER Flags;
+                       T3_16BIT_REGISTER MaxLen;

 #endif
 #endif

-       } s;
+               } s;

 
 

-       T3_32BIT_REGISTER MaxLen_Flags;
-    } u;
+               T3_32BIT_REGISTER MaxLen_Flags;
+       } u;

 
 

-    T3_32BIT_REGISTER NicRingAddr;
+       T3_32BIT_REGISTER NicRingAddr;

 } T3_RCB, *PT3_RCB;
 
 #define T3_RCB_FLAG_USE_EXT_RECV_BD                     BIT_0
 #define T3_RCB_FLAG_RING_DISABLED                       BIT_1
 
 } T3_RCB, *PT3_RCB;
 
 #define T3_RCB_FLAG_USE_EXT_RECV_BD                     BIT_0
 #define T3_RCB_FLAG_RING_DISABLED                       BIT_1
 

-

 /******************************************************************************/
 /* Status block. */
 /******************************************************************************/
 /******************************************************************************/
 /* Status block. */
 /******************************************************************************/


@@ -763,98 +730,95 @@ typedef struct {
 #define T3_STATUS_BLOCK_SIZE                                    0x80
 
 typedef struct {
 #define T3_STATUS_BLOCK_SIZE                                    0x80
 
 typedef struct {

-    volatile LM_UINT32 Status;
-    #define STATUS_BLOCK_UPDATED                                BIT_0
-    #define STATUS_BLOCK_LINK_CHANGED_STATUS                    BIT_1
-    #define STATUS_BLOCK_ERROR                                  BIT_2
+       volatile LM_UINT32 Status;
+#define STATUS_BLOCK_UPDATED                                BIT_0
+#define STATUS_BLOCK_LINK_CHANGED_STATUS                    BIT_1
+#define STATUS_BLOCK_ERROR                                  BIT_2

 
 

-    volatile LM_UINT32 StatusTag;
+       volatile LM_UINT32 StatusTag;

 
 #ifdef BIG_ENDIAN_HOST
 
 #ifdef BIG_ENDIAN_HOST

-    volatile LM_UINT16 RcvStdConIdx;
-    volatile LM_UINT16 RcvJumboConIdx;
-
-    volatile LM_UINT16 Reserved2;
-    volatile LM_UINT16 RcvMiniConIdx;
-
-    struct {
-       volatile LM_UINT16 SendConIdx;   /* Send consumer index. */
-       volatile LM_UINT16 RcvProdIdx;   /* Receive producer index. */
-    } Idx[16];
-#else /* BIG_ENDIAN_HOST */
-    volatile LM_UINT16 RcvJumboConIdx;
-    volatile LM_UINT16 RcvStdConIdx;
-
-    volatile LM_UINT16 RcvMiniConIdx;
-    volatile LM_UINT16 Reserved2;
-
-    struct {
-       volatile LM_UINT16 RcvProdIdx;   /* Receive producer index. */
-       volatile LM_UINT16 SendConIdx;   /* Send consumer index. */
-    } Idx[16];
+       volatile LM_UINT16 RcvStdConIdx;
+       volatile LM_UINT16 RcvJumboConIdx;
+
+       volatile LM_UINT16 Reserved2;
+       volatile LM_UINT16 RcvMiniConIdx;
+
+       struct {
+               volatile LM_UINT16 SendConIdx;  /* Send consumer index. */
+               volatile LM_UINT16 RcvProdIdx;  /* Receive producer index. */
+       } Idx[16];
+#else                          /* BIG_ENDIAN_HOST */
+       volatile LM_UINT16 RcvJumboConIdx;
+       volatile LM_UINT16 RcvStdConIdx;
+
+       volatile LM_UINT16 RcvMiniConIdx;
+       volatile LM_UINT16 Reserved2;
+
+       struct {
+               volatile LM_UINT16 RcvProdIdx;  /* Receive producer index. */
+               volatile LM_UINT16 SendConIdx;  /* Send consumer index. */
+       } Idx[16];

 #endif
 } T3_STATUS_BLOCK, *PT3_STATUS_BLOCK;
 
 #endif
 } T3_STATUS_BLOCK, *PT3_STATUS_BLOCK;
 

-

 /******************************************************************************/
 /* Receive buffer descriptors. */
 /******************************************************************************/
 
 typedef struct {
 /******************************************************************************/
 /* Receive buffer descriptors. */
 /******************************************************************************/
 
 typedef struct {

-    T3_64BIT_HOST_ADDR HostAddr;
+       T3_64BIT_HOST_ADDR HostAddr;

 
 #ifdef BIG_ENDIAN_HOST
 
 #ifdef BIG_ENDIAN_HOST

-    volatile LM_UINT16 Index;
-    volatile LM_UINT16 Len;
+       volatile LM_UINT16 Index;
+       volatile LM_UINT16 Len;

 
 

-    volatile LM_UINT16 Type;
-    volatile LM_UINT16 Flags;
+       volatile LM_UINT16 Type;
+       volatile LM_UINT16 Flags;

 
 

-    volatile LM_UINT16 IpCksum;
-    volatile LM_UINT16 TcpUdpCksum;
+       volatile LM_UINT16 IpCksum;
+       volatile LM_UINT16 TcpUdpCksum;

 
 

-    volatile LM_UINT16 ErrorFlag;
-    volatile LM_UINT16 VlanTag;
-#else /* BIG_ENDIAN_HOST */
-    volatile LM_UINT16 Len;
-    volatile LM_UINT16 Index;
+       volatile LM_UINT16 ErrorFlag;
+       volatile LM_UINT16 VlanTag;
+#else                          /* BIG_ENDIAN_HOST */
+       volatile LM_UINT16 Len;
+       volatile LM_UINT16 Index;

 
 

-    volatile LM_UINT16 Flags;
-    volatile LM_UINT16 Type;
+       volatile LM_UINT16 Flags;
+       volatile LM_UINT16 Type;

 
 

-    volatile LM_UINT16 TcpUdpCksum;
-    volatile LM_UINT16 IpCksum;
+       volatile LM_UINT16 TcpUdpCksum;
+       volatile LM_UINT16 IpCksum;

 
 

-    volatile LM_UINT16 VlanTag;
-    volatile LM_UINT16 ErrorFlag;
+       volatile LM_UINT16 VlanTag;
+       volatile LM_UINT16 ErrorFlag;

 #endif
 
 #endif
 

-    volatile LM_UINT32 Reserved;
-    volatile LM_UINT32 Opaque;
+       volatile LM_UINT32 Reserved;
+       volatile LM_UINT32 Opaque;

 } T3_RCV_BD, *PT3_RCV_BD;
 
 } T3_RCV_BD, *PT3_RCV_BD;
 

-

 typedef struct {
 typedef struct {

-    T3_64BIT_HOST_ADDR HostAddr[3];
+       T3_64BIT_HOST_ADDR HostAddr[3];

 
 #ifdef BIG_ENDIAN_HOST
 
 #ifdef BIG_ENDIAN_HOST

-    LM_UINT16 Len1;
-    LM_UINT16 Len2;
+       LM_UINT16 Len1;
+       LM_UINT16 Len2;

 
 

-    LM_UINT16 Len3;
-    LM_UINT16 Reserved1;
-#else /* BIG_ENDIAN_HOST */
-    LM_UINT16 Len2;
-    LM_UINT16 Len1;
+       LM_UINT16 Len3;
+       LM_UINT16 Reserved1;
+#else                          /* BIG_ENDIAN_HOST */
+       LM_UINT16 Len2;
+       LM_UINT16 Len1;

 
 

-    LM_UINT16 Reserved1;
-    LM_UINT16 Len3;
+       LM_UINT16 Reserved1;
+       LM_UINT16 Len3;

 #endif
 
 #endif
 

-    T3_RCV_BD StdRcvBd;
+       T3_RCV_BD StdRcvBd;

 } T3_EXT_RCV_BD, *PT3_EXT_RCV_BD;
 
 } T3_EXT_RCV_BD, *PT3_EXT_RCV_BD;
 

-

 /* Error flags. */
 #define RCV_BD_ERR_BAD_CRC                          0x0001
 #define RCV_BD_ERR_COLL_DETECT                      0x0002
 /* Error flags. */
 #define RCV_BD_ERR_BAD_CRC                          0x0001
 #define RCV_BD_ERR_COLL_DETECT                      0x0002


@@ -866,7 +830,6 @@ typedef struct {
 #define RCV_BD_ERR_TRUNC_NO_RESOURCES               0x0080
 #define RCV_BD_ERR_GIANT_FRAME_RCVD                 0x0100
 
 #define RCV_BD_ERR_TRUNC_NO_RESOURCES               0x0080
 #define RCV_BD_ERR_GIANT_FRAME_RCVD                 0x0100
 

-

 /* Buffer descriptor flags. */
 #define RCV_BD_FLAG_END                             0x0004
 #define RCV_BD_FLAG_JUMBO_RING                      0x0020
 /* Buffer descriptor flags. */
 #define RCV_BD_FLAG_END                             0x0004
 #define RCV_BD_FLAG_JUMBO_RING                      0x0020


@@ -877,44 +840,42 @@ typedef struct {
 #define RCV_BD_FLAG_TCP_UDP_CHKSUM_FIELD            0x2000
 #define RCV_BD_FLAG_TCP_PACKET                      0x4000
 
 #define RCV_BD_FLAG_TCP_UDP_CHKSUM_FIELD            0x2000
 #define RCV_BD_FLAG_TCP_PACKET                      0x4000
 

-

 /******************************************************************************/
 /* Send buffer descriptor. */
 /******************************************************************************/
 
 typedef struct {
 /******************************************************************************/
 /* Send buffer descriptor. */
 /******************************************************************************/
 
 typedef struct {

-    T3_64BIT_HOST_ADDR HostAddr;
+       T3_64BIT_HOST_ADDR HostAddr;

 
 

-    union {
-       struct {
+       union {
+               struct {

 #ifdef BIG_ENDIAN_HOST
 #ifdef BIG_ENDIAN_HOST

-           LM_UINT16 Len;
-           LM_UINT16 Flags;
-#else /* BIG_ENDIAN_HOST */
-           LM_UINT16 Flags;
-           LM_UINT16 Len;
+                       LM_UINT16 Len;
+                       LM_UINT16 Flags;
+#else                          /* BIG_ENDIAN_HOST */
+                       LM_UINT16 Flags;
+                       LM_UINT16 Len;

 #endif
 #endif

-       } s1;
+               } s1;

 
 

-       LM_UINT32 Len_Flags;
-    } u1;
+               LM_UINT32 Len_Flags;
+       } u1;

 
 

-    union {
-       struct {
+       union {
+               struct {

 #ifdef BIG_ENDIAN_HOST
 #ifdef BIG_ENDIAN_HOST

-           LM_UINT16 Reserved;
-           LM_UINT16 VlanTag;
-#else /* BIG_ENDIAN_HOST */
-           LM_UINT16 VlanTag;
-           LM_UINT16 Reserved;
+                       LM_UINT16 Reserved;
+                       LM_UINT16 VlanTag;
+#else                          /* BIG_ENDIAN_HOST */
+                       LM_UINT16 VlanTag;
+                       LM_UINT16 Reserved;

 #endif
 #endif

-       } s2;
+               } s2;

 
 

-       LM_UINT32 VlanTag;
-    } u2;
+               LM_UINT32 VlanTag;
+       } u2;

 } T3_SND_BD, *PT3_SND_BD;
 
 } T3_SND_BD, *PT3_SND_BD;
 

-

 /* Send buffer descriptor flags. */
 #define SND_BD_FLAG_TCP_UDP_CKSUM                   0x0001
 #define SND_BD_FLAG_IP_CKSUM                        0x0002
 /* Send buffer descriptor flags. */
 #define SND_BD_FLAG_TCP_UDP_CKSUM                   0x0001
 #define SND_BD_FLAG_IP_CKSUM                        0x0002


@@ -932,435 +893,426 @@ typedef struct {
 /* MBUFs */
 typedef struct T3_MBUF_FRAME_DESC {
 #ifdef BIG_ENDIAN_HOST
 /* MBUFs */
 typedef struct T3_MBUF_FRAME_DESC {
 #ifdef BIG_ENDIAN_HOST

-  LM_UINT32 status_control;
-  union {
-    struct {
-      LM_UINT8 cqid;
-      LM_UINT8 reserved1;
-      LM_UINT16 length;
-    }s1;
-    LM_UINT32 word;
-  }u1;
-  union {
-    struct
-    {
-      LM_UINT16 ip_hdr_start;
-      LM_UINT16 tcp_udp_hdr_start;
-    }s2;
-
-    LM_UINT32 word;
-  }u2;
-
-  union {
-    struct {
-      LM_UINT16 data_start;
-      LM_UINT16 vlan_id;
-    }s3;
-
-    LM_UINT32 word;
-  }u3;
-
-  union {
-    struct {
-      LM_UINT16 ip_checksum;
-      LM_UINT16 tcp_udp_checksum;
-    }s4;
-
-    LM_UINT32 word;
-  }u4;
-
-  union {
-    struct {
-      LM_UINT16 pseudo_checksum;
-      LM_UINT16 checksum_status;
-    }s5;
-
-    LM_UINT32 word;
-  }u5;
-
-  union {
-    struct {
-      LM_UINT16 rule_match;
-      LM_UINT8 class;
-      LM_UINT8 rupt;
-    }s6;
-
-    LM_UINT32 word;
-  }u6;
-
-  union {
-    struct {
-      LM_UINT16 reserved2;
-      LM_UINT16 mbuf_num;
-    }s7;
-
-    LM_UINT32 word;
-  }u7;
-
-  LM_UINT32 reserved3;
-  LM_UINT32 reserved4;
+       LM_UINT32 status_control;
+       union {
+               struct {
+                       LM_UINT8 cqid;
+                       LM_UINT8 reserved1;
+                       LM_UINT16 length;
+               } s1;
+               LM_UINT32 word;
+       } u1;
+       union {
+               struct {
+                       LM_UINT16 ip_hdr_start;
+                       LM_UINT16 tcp_udp_hdr_start;
+               } s2;
+
+               LM_UINT32 word;
+       } u2;
+
+       union {
+               struct {
+                       LM_UINT16 data_start;
+                       LM_UINT16 vlan_id;
+               } s3;
+
+               LM_UINT32 word;
+       } u3;
+
+       union {
+               struct {
+                       LM_UINT16 ip_checksum;
+                       LM_UINT16 tcp_udp_checksum;
+               } s4;
+
+               LM_UINT32 word;
+       } u4;
+
+       union {
+               struct {
+                       LM_UINT16 pseudo_checksum;
+                       LM_UINT16 checksum_status;
+               } s5;
+
+               LM_UINT32 word;
+       } u5;
+
+       union {
+               struct {
+                       LM_UINT16 rule_match;
+                       LM_UINT8 class;
+                       LM_UINT8 rupt;
+               } s6;
+
+               LM_UINT32 word;
+       } u6;
+
+       union {
+               struct {
+                       LM_UINT16 reserved2;
+                       LM_UINT16 mbuf_num;
+               } s7;
+
+               LM_UINT32 word;
+       } u7;
+
+       LM_UINT32 reserved3;
+       LM_UINT32 reserved4;

 #else
 #else

-  LM_UINT32 status_control;
-  union {
-    struct {
-      LM_UINT16 length;
-      LM_UINT8  reserved1;
-      LM_UINT8  cqid;
-    }s1;
-    LM_UINT32 word;
-  }u1;
-  union {
-    struct
-    {
-      LM_UINT16 tcp_udp_hdr_start;
-      LM_UINT16 ip_hdr_start;
-    }s2;
-
-    LM_UINT32 word;
-  }u2;
-
-  union {
-    struct {
-      LM_UINT16 vlan_id;
-      LM_UINT16 data_start;
-    }s3;
-
-    LM_UINT32 word;
-  }u3;
-
-  union {
-    struct {
-      LM_UINT16 tcp_udp_checksum;
-      LM_UINT16 ip_checksum;
-    }s4;
-
-    LM_UINT32 word;
-  }u4;
-
-  union {
-    struct {
-      LM_UINT16 checksum_status;
-      LM_UINT16 pseudo_checksum;
-    }s5;
-
-    LM_UINT32 word;
-  }u5;
-
-  union {
-    struct {
-      LM_UINT8 rupt;
-      LM_UINT8 class;
-      LM_UINT16 rule_match;
-    }s6;
-
-    LM_UINT32 word;
-  }u6;
-
-  union {
-    struct {
-      LM_UINT16 mbuf_num;
-      LM_UINT16 reserved2;
-    }s7;
-
-    LM_UINT32 word;
-  }u7;
-
-  LM_UINT32 reserved3;
-  LM_UINT32 reserved4;
+       LM_UINT32 status_control;
+       union {
+               struct {
+                       LM_UINT16 length;
+                       LM_UINT8 reserved1;
+                       LM_UINT8 cqid;
+               } s1;
+               LM_UINT32 word;
+       } u1;
+       union {
+               struct {
+                       LM_UINT16 tcp_udp_hdr_start;
+                       LM_UINT16 ip_hdr_start;
+               } s2;
+
+               LM_UINT32 word;
+       } u2;
+
+       union {
+               struct {
+                       LM_UINT16 vlan_id;
+                       LM_UINT16 data_start;
+               } s3;
+
+               LM_UINT32 word;
+       } u3;
+
+       union {
+               struct {
+                       LM_UINT16 tcp_udp_checksum;
+                       LM_UINT16 ip_checksum;
+               } s4;
+
+               LM_UINT32 word;
+       } u4;
+
+       union {
+               struct {
+                       LM_UINT16 checksum_status;
+                       LM_UINT16 pseudo_checksum;
+               } s5;
+
+               LM_UINT32 word;
+       } u5;
+
+       union {
+               struct {
+                       LM_UINT8 rupt;
+                       LM_UINT8 class;
+                       LM_UINT16 rule_match;
+               } s6;
+
+               LM_UINT32 word;
+       } u6;
+
+       union {
+               struct {
+                       LM_UINT16 mbuf_num;
+                       LM_UINT16 reserved2;
+               } s7;
+
+               LM_UINT32 word;
+       } u7;
+
+       LM_UINT32 reserved3;
+       LM_UINT32 reserved4;

 #endif
 #endif

-}T3_MBUF_FRAME_DESC,*PT3_MBUF_FRAME_DESC;
+} T3_MBUF_FRAME_DESC, *PT3_MBUF_FRAME_DESC;

 
 typedef struct T3_MBUF_HDR {
 
 typedef struct T3_MBUF_HDR {

-  union {
-    struct {
-      unsigned int C:1;
-      unsigned int F:1;
-      unsigned int reserved1:7;
-      unsigned int next_mbuf:16;
-      unsigned int length:7;
-    }s1;
-
-    LM_UINT32 word;
-  }u1;
-
-  LM_UINT32 next_frame_ptr;
-}T3_MBUF_HDR, *PT3_MBUF_HDR;
-
-typedef struct T3_MBUF
-{
-  T3_MBUF_HDR hdr;
-  union
-  {
-    struct {
-      T3_MBUF_FRAME_DESC frame_hdr;
-      LM_UINT32 data[20];
-    }s1;
-
-    struct {
-      LM_UINT32 data[30];
-    }s2;
-  }body;
-}T3_MBUF, *PT3_MBUF;
+       union {
+               struct {
+                       unsigned int C:1;
+                       unsigned int F:1;
+                       unsigned int reserved1:7;
+                       unsigned int next_mbuf:16;
+                       unsigned int length:7;
+               } s1;
+
+               LM_UINT32 word;
+       } u1;
+
+       LM_UINT32 next_frame_ptr;
+} T3_MBUF_HDR, *PT3_MBUF_HDR;
+
+typedef struct T3_MBUF {
+       T3_MBUF_HDR hdr;
+       union {
+               struct {
+                       T3_MBUF_FRAME_DESC frame_hdr;
+                       LM_UINT32 data[20];
+               } s1;
+
+               struct {
+                       LM_UINT32 data[30];
+               } s2;
+       } body;
+} T3_MBUF, *PT3_MBUF;

 
 #define T3_MBUF_BASE   (T3_NIC_MBUF_POOL_ADDR >> 7)
 #define T3_MBUF_END    ((T3_NIC_MBUF_POOL_ADDR + T3_NIC_MBUF_POOL_SIZE) >> 7)
 
 
 #define T3_MBUF_BASE   (T3_NIC_MBUF_POOL_ADDR >> 7)
 #define T3_MBUF_END    ((T3_NIC_MBUF_POOL_ADDR + T3_NIC_MBUF_POOL_SIZE) >> 7)
 

-

 /******************************************************************************/
 /* Statistics block. */
 /******************************************************************************/
 
 typedef struct {
 /******************************************************************************/
 /* Statistics block. */
 /******************************************************************************/
 
 typedef struct {

-    LM_UINT8 Reserved0[0x400-0x300];
-
-    /* Statistics maintained by Receive MAC. */
-    T3_64BIT_REGISTER ifHCInOctets;
-    T3_64BIT_REGISTER Reserved1;
-    T3_64BIT_REGISTER etherStatsFragments;
-    T3_64BIT_REGISTER ifHCInUcastPkts;
-    T3_64BIT_REGISTER ifHCInMulticastPkts;
-    T3_64BIT_REGISTER ifHCInBroadcastPkts;
-    T3_64BIT_REGISTER dot3StatsFCSErrors;
-    T3_64BIT_REGISTER dot3StatsAlignmentErrors;
-    T3_64BIT_REGISTER xonPauseFramesReceived;
-    T3_64BIT_REGISTER xoffPauseFramesReceived;
-    T3_64BIT_REGISTER macControlFramesReceived;
-    T3_64BIT_REGISTER xoffStateEntered;
-    T3_64BIT_REGISTER dot3StatsFramesTooLong;
-    T3_64BIT_REGISTER etherStatsJabbers;
-    T3_64BIT_REGISTER etherStatsUndersizePkts;
-    T3_64BIT_REGISTER inRangeLengthError;
-    T3_64BIT_REGISTER outRangeLengthError;
-    T3_64BIT_REGISTER etherStatsPkts64Octets;
-    T3_64BIT_REGISTER etherStatsPkts65Octetsto127Octets;
-    T3_64BIT_REGISTER etherStatsPkts128Octetsto255Octets;
-    T3_64BIT_REGISTER etherStatsPkts256Octetsto511Octets;
-    T3_64BIT_REGISTER etherStatsPkts512Octetsto1023Octets;
-    T3_64BIT_REGISTER etherStatsPkts1024Octetsto1522Octets;
-    T3_64BIT_REGISTER etherStatsPkts1523Octetsto2047Octets;
-    T3_64BIT_REGISTER etherStatsPkts2048Octetsto4095Octets;
-    T3_64BIT_REGISTER etherStatsPkts4096Octetsto8191Octets;
-    T3_64BIT_REGISTER etherStatsPkts8192Octetsto9022Octets;
-
-    T3_64BIT_REGISTER Unused1[37];
-
-    /* Statistics maintained by Transmit MAC. */
-    T3_64BIT_REGISTER ifHCOutOctets;
-    T3_64BIT_REGISTER Reserved2;
-    T3_64BIT_REGISTER etherStatsCollisions;
-    T3_64BIT_REGISTER outXonSent;
-    T3_64BIT_REGISTER outXoffSent;
-    T3_64BIT_REGISTER flowControlDone;
-    T3_64BIT_REGISTER dot3StatsInternalMacTransmitErrors;
-    T3_64BIT_REGISTER dot3StatsSingleCollisionFrames;
-    T3_64BIT_REGISTER dot3StatsMultipleCollisionFrames;
-    T3_64BIT_REGISTER dot3StatsDeferredTransmissions;
-    T3_64BIT_REGISTER Reserved3;
-    T3_64BIT_REGISTER dot3StatsExcessiveCollisions;
-    T3_64BIT_REGISTER dot3StatsLateCollisions;
-    T3_64BIT_REGISTER dot3Collided2Times;
-    T3_64BIT_REGISTER dot3Collided3Times;
-    T3_64BIT_REGISTER dot3Collided4Times;
-    T3_64BIT_REGISTER dot3Collided5Times;
-    T3_64BIT_REGISTER dot3Collided6Times;
-    T3_64BIT_REGISTER dot3Collided7Times;
-    T3_64BIT_REGISTER dot3Collided8Times;
-    T3_64BIT_REGISTER dot3Collided9Times;
-    T3_64BIT_REGISTER dot3Collided10Times;
-    T3_64BIT_REGISTER dot3Collided11Times;
-    T3_64BIT_REGISTER dot3Collided12Times;
-    T3_64BIT_REGISTER dot3Collided13Times;
-    T3_64BIT_REGISTER dot3Collided14Times;
-    T3_64BIT_REGISTER dot3Collided15Times;
-    T3_64BIT_REGISTER ifHCOutUcastPkts;
-    T3_64BIT_REGISTER ifHCOutMulticastPkts;
-    T3_64BIT_REGISTER ifHCOutBroadcastPkts;
-    T3_64BIT_REGISTER dot3StatsCarrierSenseErrors;
-    T3_64BIT_REGISTER ifOutDiscards;
-    T3_64BIT_REGISTER ifOutErrors;
-
-    T3_64BIT_REGISTER Unused2[31];
-
-    /* Statistics maintained by Receive List Placement. */
-    T3_64BIT_REGISTER COSIfHCInPkts[16];
-    T3_64BIT_REGISTER COSFramesDroppedDueToFilters;
-    T3_64BIT_REGISTER nicDmaWriteQueueFull;
-    T3_64BIT_REGISTER nicDmaWriteHighPriQueueFull;
-    T3_64BIT_REGISTER nicNoMoreRxBDs;
-    T3_64BIT_REGISTER ifInDiscards;
-    T3_64BIT_REGISTER ifInErrors;
-    T3_64BIT_REGISTER nicRecvThresholdHit;
-
-    T3_64BIT_REGISTER Unused3[9];
-
-    /* Statistics maintained by Send Data Initiator. */
-    T3_64BIT_REGISTER COSIfHCOutPkts[16];
-    T3_64BIT_REGISTER nicDmaReadQueueFull;
-    T3_64BIT_REGISTER nicDmaReadHighPriQueueFull;
-    T3_64BIT_REGISTER nicSendDataCompQueueFull;
-
-    /* Statistics maintained by Host Coalescing. */
-    T3_64BIT_REGISTER nicRingSetSendProdIndex;
-    T3_64BIT_REGISTER nicRingStatusUpdate;
-    T3_64BIT_REGISTER nicInterrupts;
-    T3_64BIT_REGISTER nicAvoidedInterrupts;
-    T3_64BIT_REGISTER nicSendThresholdHit;
-
-    LM_UINT8 Reserved4[0xb00-0x9c0];
+       LM_UINT8 Reserved0[0x400 - 0x300];
+
+       /* Statistics maintained by Receive MAC. */
+       T3_64BIT_REGISTER ifHCInOctets;
+       T3_64BIT_REGISTER Reserved1;
+       T3_64BIT_REGISTER etherStatsFragments;
+       T3_64BIT_REGISTER ifHCInUcastPkts;
+       T3_64BIT_REGISTER ifHCInMulticastPkts;
+       T3_64BIT_REGISTER ifHCInBroadcastPkts;
+       T3_64BIT_REGISTER dot3StatsFCSErrors;
+       T3_64BIT_REGISTER dot3StatsAlignmentErrors;
+       T3_64BIT_REGISTER xonPauseFramesReceived;
+       T3_64BIT_REGISTER xoffPauseFramesReceived;
+       T3_64BIT_REGISTER macControlFramesReceived;
+       T3_64BIT_REGISTER xoffStateEntered;
+       T3_64BIT_REGISTER dot3StatsFramesTooLong;
+       T3_64BIT_REGISTER etherStatsJabbers;
+       T3_64BIT_REGISTER etherStatsUndersizePkts;
+       T3_64BIT_REGISTER inRangeLengthError;
+       T3_64BIT_REGISTER outRangeLengthError;
+       T3_64BIT_REGISTER etherStatsPkts64Octets;
+       T3_64BIT_REGISTER etherStatsPkts65Octetsto127Octets;
+       T3_64BIT_REGISTER etherStatsPkts128Octetsto255Octets;
+       T3_64BIT_REGISTER etherStatsPkts256Octetsto511Octets;
+       T3_64BIT_REGISTER etherStatsPkts512Octetsto1023Octets;
+       T3_64BIT_REGISTER etherStatsPkts1024Octetsto1522Octets;
+       T3_64BIT_REGISTER etherStatsPkts1523Octetsto2047Octets;
+       T3_64BIT_REGISTER etherStatsPkts2048Octetsto4095Octets;
+       T3_64BIT_REGISTER etherStatsPkts4096Octetsto8191Octets;
+       T3_64BIT_REGISTER etherStatsPkts8192Octetsto9022Octets;
+
+       T3_64BIT_REGISTER Unused1[37];
+
+       /* Statistics maintained by Transmit MAC. */
+       T3_64BIT_REGISTER ifHCOutOctets;
+       T3_64BIT_REGISTER Reserved2;
+       T3_64BIT_REGISTER etherStatsCollisions;
+       T3_64BIT_REGISTER outXonSent;
+       T3_64BIT_REGISTER outXoffSent;
+       T3_64BIT_REGISTER flowControlDone;
+       T3_64BIT_REGISTER dot3StatsInternalMacTransmitErrors;
+       T3_64BIT_REGISTER dot3StatsSingleCollisionFrames;
+       T3_64BIT_REGISTER dot3StatsMultipleCollisionFrames;
+       T3_64BIT_REGISTER dot3StatsDeferredTransmissions;
+       T3_64BIT_REGISTER Reserved3;
+       T3_64BIT_REGISTER dot3StatsExcessiveCollisions;
+       T3_64BIT_REGISTER dot3StatsLateCollisions;
+       T3_64BIT_REGISTER dot3Collided2Times;
+       T3_64BIT_REGISTER dot3Collided3Times;
+       T3_64BIT_REGISTER dot3Collided4Times;
+       T3_64BIT_REGISTER dot3Collided5Times;
+       T3_64BIT_REGISTER dot3Collided6Times;
+       T3_64BIT_REGISTER dot3Collided7Times;
+       T3_64BIT_REGISTER dot3Collided8Times;
+       T3_64BIT_REGISTER dot3Collided9Times;
+       T3_64BIT_REGISTER dot3Collided10Times;
+       T3_64BIT_REGISTER dot3Collided11Times;
+       T3_64BIT_REGISTER dot3Collided12Times;
+       T3_64BIT_REGISTER dot3Collided13Times;
+       T3_64BIT_REGISTER dot3Collided14Times;
+       T3_64BIT_REGISTER dot3Collided15Times;
+       T3_64BIT_REGISTER ifHCOutUcastPkts;
+       T3_64BIT_REGISTER ifHCOutMulticastPkts;
+       T3_64BIT_REGISTER ifHCOutBroadcastPkts;
+       T3_64BIT_REGISTER dot3StatsCarrierSenseErrors;
+       T3_64BIT_REGISTER ifOutDiscards;
+       T3_64BIT_REGISTER ifOutErrors;
+
+       T3_64BIT_REGISTER Unused2[31];
+
+       /* Statistics maintained by Receive List Placement. */
+       T3_64BIT_REGISTER COSIfHCInPkts[16];
+       T3_64BIT_REGISTER COSFramesDroppedDueToFilters;
+       T3_64BIT_REGISTER nicDmaWriteQueueFull;
+       T3_64BIT_REGISTER nicDmaWriteHighPriQueueFull;
+       T3_64BIT_REGISTER nicNoMoreRxBDs;
+       T3_64BIT_REGISTER ifInDiscards;
+       T3_64BIT_REGISTER ifInErrors;
+       T3_64BIT_REGISTER nicRecvThresholdHit;
+
+       T3_64BIT_REGISTER Unused3[9];
+
+       /* Statistics maintained by Send Data Initiator. */
+       T3_64BIT_REGISTER COSIfHCOutPkts[16];
+       T3_64BIT_REGISTER nicDmaReadQueueFull;
+       T3_64BIT_REGISTER nicDmaReadHighPriQueueFull;
+       T3_64BIT_REGISTER nicSendDataCompQueueFull;
+
+       /* Statistics maintained by Host Coalescing. */
+       T3_64BIT_REGISTER nicRingSetSendProdIndex;
+       T3_64BIT_REGISTER nicRingStatusUpdate;
+       T3_64BIT_REGISTER nicInterrupts;
+       T3_64BIT_REGISTER nicAvoidedInterrupts;
+       T3_64BIT_REGISTER nicSendThresholdHit;
+
+       LM_UINT8 Reserved4[0xb00 - 0x9c0];

 } T3_STATS_BLOCK, *PT3_STATS_BLOCK;
 
 } T3_STATS_BLOCK, *PT3_STATS_BLOCK;
 

-

 /******************************************************************************/
 /* PCI configuration registers. */
 /******************************************************************************/
 
 typedef struct {
 /******************************************************************************/
 /* PCI configuration registers. */
 /******************************************************************************/
 
 typedef struct {

-    T3_16BIT_REGISTER VendorId;
-    T3_16BIT_REGISTER DeviceId;
-
-    T3_16BIT_REGISTER Command;
-    T3_16BIT_REGISTER Status;
-
-    T3_32BIT_REGISTER ClassCodeRevId;
-
-    T3_8BIT_REGISTER CacheLineSize;
-    T3_8BIT_REGISTER LatencyTimer;
-    T3_8BIT_REGISTER HeaderType;
-    T3_8BIT_REGISTER Bist;
-
-    T3_32BIT_REGISTER MemBaseAddrLow;
-    T3_32BIT_REGISTER MemBaseAddrHigh;
-
-    LM_UINT8 Unused1[20];
-
-    T3_16BIT_REGISTER SubsystemVendorId;
-    T3_16BIT_REGISTER SubsystemId;
-
-    T3_32BIT_REGISTER RomBaseAddr;
-
-    T3_8BIT_REGISTER PciXCapiblityPtr;
-    LM_UINT8 Unused2[7];
-
-    T3_8BIT_REGISTER IntLine;
-    T3_8BIT_REGISTER IntPin;
-    T3_8BIT_REGISTER MinGnt;
-    T3_8BIT_REGISTER MaxLat;
-
-    T3_8BIT_REGISTER PciXCapabilities;
-    T3_8BIT_REGISTER PmCapabilityPtr;
-    T3_16BIT_REGISTER PciXCommand;
-
-    T3_32BIT_REGISTER PciXStatus;
-
-    T3_8BIT_REGISTER PmCapabilityId;
-    T3_8BIT_REGISTER VpdCapabilityPtr;
-    T3_16BIT_REGISTER PmCapabilities;
-
-    T3_16BIT_REGISTER PmCtrlStatus;
-    #define PM_CTRL_PME_STATUS            BIT_15
-    #define PM_CTRL_PME_ENABLE            BIT_8
-    #define PM_CTRL_PME_POWER_STATE_D0    0
-    #define PM_CTRL_PME_POWER_STATE_D1    1
-    #define PM_CTRL_PME_POWER_STATE_D2    2
-    #define PM_CTRL_PME_POWER_STATE_D3H   3
-
-    T3_8BIT_REGISTER BridgeSupportExt;
-    T3_8BIT_REGISTER PmData;
-
-    T3_8BIT_REGISTER VpdCapabilityId;
-    T3_8BIT_REGISTER MsiCapabilityPtr;
-    T3_16BIT_REGISTER VpdAddrFlag;
-    #define VPD_FLAG_WRITE      (1 << 15)
-    #define VPD_FLAG_RW_MASK    (1 << 15)
-    #define VPD_FLAG_READ       0
-
-
-    T3_32BIT_REGISTER VpdData;
-
-    T3_8BIT_REGISTER MsiCapabilityId;
-    T3_8BIT_REGISTER NextCapabilityPtr;
-    T3_16BIT_REGISTER MsiCtrl;
-    #define MSI_CTRL_64BIT_CAP     (1 << 7)
-    #define MSI_CTRL_MSG_ENABLE(x) (x << 4)
-    #define MSI_CTRL_MSG_CAP(x)    (x << 1)
-    #define MSI_CTRL_ENABLE        (1 << 0)
-
-
-    T3_32BIT_REGISTER MsiAddrLow;
-    T3_32BIT_REGISTER MsiAddrHigh;
-
-    T3_16BIT_REGISTER MsiData;
-    T3_16BIT_REGISTER Unused3;
-
-    T3_32BIT_REGISTER MiscHostCtrl;
-    #define MISC_HOST_CTRL_CLEAR_INT                        BIT_0
-    #define MISC_HOST_CTRL_MASK_PCI_INT                     BIT_1
-    #define MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP          BIT_2
-    #define MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP          BIT_3
-    #define MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW          BIT_4
-    #define MISC_HOST_CTRL_ENABLE_CLK_REG_RW                BIT_5
-    #define MISC_HOST_CTRL_ENABLE_REG_WORD_SWAP             BIT_6
-    #define MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS           BIT_7
-    #define MISC_HOST_CTRL_ENABLE_INT_MASK_MODE             BIT_8
-    #define MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE        BIT_9
-
-    T3_32BIT_REGISTER DmaReadWriteCtrl;
-    #define DMA_CTRL_WRITE_BOUNDARY_MASK            (BIT_11 | BIT_12 | BIT_13)
-    #define DMA_CTRL_WRITE_BOUNDARY_DISABLE         0
-    #define DMA_CTRL_WRITE_BOUNDARY_16              BIT_11
-    #define DMA_CTRL_WRITE_BOUNDARY_32              BIT_12
-    #define DMA_CTRL_WRITE_BOUNDARY_64              (BIT_12 | BIT_11)
-    #define DMA_CTRL_WRITE_BOUNDARY_128             BIT_13
-    #define DMA_CTRL_WRITE_BOUNDARY_256             (BIT_13 | BIT_11)
-    #define DMA_CTRL_WRITE_BOUNDARY_512             (BIT_13 | BIT_12)
-    #define DMA_CTRL_WRITE_BOUNDARY_1024            (BIT_13 | BIT_12 | BIT_11)
-    #define DMA_CTRL_WRITE_ONE_DMA_AT_ONCE          BIT_14
-
-
-    T3_32BIT_REGISTER PciState;
-    #define T3_PCI_STATE_FORCE_PCI_RESET                    BIT_0
-    #define T3_PCI_STATE_INTERRUPT_NOT_ACTIVE               BIT_1
-    #define T3_PCI_STATE_NOT_PCI_X_BUS                      BIT_2
-    #define T3_PCI_STATE_HIGH_BUS_SPEED                     BIT_3
-    #define T3_PCI_STATE_32BIT_PCI_BUS                      BIT_4
-    #define T3_PCI_STATE_PCI_ROM_ENABLE                     BIT_5
-    #define T3_PCI_STATE_PCI_ROM_RETRY_ENABLE               BIT_6
-    #define T3_PCI_STATE_FLAT_VIEW                          BIT_8
-    #define T3_PCI_STATE_RETRY_SAME_DMA                     BIT_13
-
-    T3_32BIT_REGISTER ClockCtrl;
-    #define T3_PCI_CLKCTRL_TXCPU_CLK_DISABLE                BIT_11
-    #define T3_PCI_CLKCTRL_RXCPU_CLK_DISABLE                BIT_10
-    #define T3_PCI_CLKCTRL_CORE_CLK_DISABLE                 BIT_9
-
-    T3_32BIT_REGISTER RegBaseAddr;
-
-    T3_32BIT_REGISTER MemWindowBaseAddr;
+       T3_16BIT_REGISTER VendorId;
+       T3_16BIT_REGISTER DeviceId;
+
+       T3_16BIT_REGISTER Command;
+       T3_16BIT_REGISTER Status;
+
+       T3_32BIT_REGISTER ClassCodeRevId;
+
+       T3_8BIT_REGISTER CacheLineSize;
+       T3_8BIT_REGISTER LatencyTimer;
+       T3_8BIT_REGISTER HeaderType;
+       T3_8BIT_REGISTER Bist;
+
+       T3_32BIT_REGISTER MemBaseAddrLow;
+       T3_32BIT_REGISTER MemBaseAddrHigh;
+
+       LM_UINT8 Unused1[20];
+
+       T3_16BIT_REGISTER SubsystemVendorId;
+       T3_16BIT_REGISTER SubsystemId;
+
+       T3_32BIT_REGISTER RomBaseAddr;
+
+       T3_8BIT_REGISTER PciXCapiblityPtr;
+       LM_UINT8 Unused2[7];
+
+       T3_8BIT_REGISTER IntLine;
+       T3_8BIT_REGISTER IntPin;
+       T3_8BIT_REGISTER MinGnt;
+       T3_8BIT_REGISTER MaxLat;
+
+       T3_8BIT_REGISTER PciXCapabilities;
+       T3_8BIT_REGISTER PmCapabilityPtr;
+       T3_16BIT_REGISTER PciXCommand;
+
+       T3_32BIT_REGISTER PciXStatus;
+
+       T3_8BIT_REGISTER PmCapabilityId;
+       T3_8BIT_REGISTER VpdCapabilityPtr;
+       T3_16BIT_REGISTER PmCapabilities;
+
+       T3_16BIT_REGISTER PmCtrlStatus;
+#define PM_CTRL_PME_STATUS            BIT_15
+#define PM_CTRL_PME_ENABLE            BIT_8
+#define PM_CTRL_PME_POWER_STATE_D0    0
+#define PM_CTRL_PME_POWER_STATE_D1    1
+#define PM_CTRL_PME_POWER_STATE_D2    2
+#define PM_CTRL_PME_POWER_STATE_D3H   3
+
+       T3_8BIT_REGISTER BridgeSupportExt;
+       T3_8BIT_REGISTER PmData;
+
+       T3_8BIT_REGISTER VpdCapabilityId;
+       T3_8BIT_REGISTER MsiCapabilityPtr;
+       T3_16BIT_REGISTER VpdAddrFlag;
+#define VPD_FLAG_WRITE      (1 << 15)
+#define VPD_FLAG_RW_MASK    (1 << 15)
+#define VPD_FLAG_READ       0
+
+       T3_32BIT_REGISTER VpdData;
+
+       T3_8BIT_REGISTER MsiCapabilityId;
+       T3_8BIT_REGISTER NextCapabilityPtr;
+       T3_16BIT_REGISTER MsiCtrl;
+#define MSI_CTRL_64BIT_CAP     (1 << 7)
+#define MSI_CTRL_MSG_ENABLE(x) (x << 4)
+#define MSI_CTRL_MSG_CAP(x)    (x << 1)
+#define MSI_CTRL_ENABLE        (1 << 0)
+
+       T3_32BIT_REGISTER MsiAddrLow;
+       T3_32BIT_REGISTER MsiAddrHigh;
+
+       T3_16BIT_REGISTER MsiData;
+       T3_16BIT_REGISTER Unused3;
+
+       T3_32BIT_REGISTER MiscHostCtrl;
+#define MISC_HOST_CTRL_CLEAR_INT                        BIT_0
+#define MISC_HOST_CTRL_MASK_PCI_INT                     BIT_1
+#define MISC_HOST_CTRL_ENABLE_ENDIAN_BYTE_SWAP          BIT_2
+#define MISC_HOST_CTRL_ENABLE_ENDIAN_WORD_SWAP          BIT_3
+#define MISC_HOST_CTRL_ENABLE_PCI_STATE_REG_RW          BIT_4
+#define MISC_HOST_CTRL_ENABLE_CLK_REG_RW                BIT_5
+#define MISC_HOST_CTRL_ENABLE_REG_WORD_SWAP             BIT_6
+#define MISC_HOST_CTRL_ENABLE_INDIRECT_ACCESS           BIT_7
+#define MISC_HOST_CTRL_ENABLE_INT_MASK_MODE             BIT_8
+#define MISC_HOST_CTRL_ENABLE_TAGGED_STATUS_MODE        BIT_9
+
+       T3_32BIT_REGISTER DmaReadWriteCtrl;
+#define DMA_CTRL_WRITE_BOUNDARY_MASK            (BIT_11 | BIT_12 | BIT_13)
+#define DMA_CTRL_WRITE_BOUNDARY_DISABLE         0
+#define DMA_CTRL_WRITE_BOUNDARY_16              BIT_11
+#define DMA_CTRL_WRITE_BOUNDARY_32              BIT_12
+#define DMA_CTRL_WRITE_BOUNDARY_64              (BIT_12 | BIT_11)
+#define DMA_CTRL_WRITE_BOUNDARY_128             BIT_13
+#define DMA_CTRL_WRITE_BOUNDARY_256             (BIT_13 | BIT_11)
+#define DMA_CTRL_WRITE_BOUNDARY_512             (BIT_13 | BIT_12)
+#define DMA_CTRL_WRITE_BOUNDARY_1024            (BIT_13 | BIT_12 | BIT_11)
+#define DMA_CTRL_WRITE_ONE_DMA_AT_ONCE          BIT_14
+
+       T3_32BIT_REGISTER PciState;
+#define T3_PCI_STATE_FORCE_PCI_RESET                    BIT_0
+#define T3_PCI_STATE_INTERRUPT_NOT_ACTIVE               BIT_1
+#define T3_PCI_STATE_NOT_PCI_X_BUS                      BIT_2
+#define T3_PCI_STATE_HIGH_BUS_SPEED                     BIT_3
+#define T3_PCI_STATE_32BIT_PCI_BUS                      BIT_4
+#define T3_PCI_STATE_PCI_ROM_ENABLE                     BIT_5
+#define T3_PCI_STATE_PCI_ROM_RETRY_ENABLE               BIT_6
+#define T3_PCI_STATE_FLAT_VIEW                          BIT_8
+#define T3_PCI_STATE_RETRY_SAME_DMA                     BIT_13
+
+       T3_32BIT_REGISTER ClockCtrl;
+#define T3_PCI_CLKCTRL_TXCPU_CLK_DISABLE                BIT_11
+#define T3_PCI_CLKCTRL_RXCPU_CLK_DISABLE                BIT_10
+#define T3_PCI_CLKCTRL_CORE_CLK_DISABLE                 BIT_9
+
+       T3_32BIT_REGISTER RegBaseAddr;
+
+       T3_32BIT_REGISTER MemWindowBaseAddr;

 
 #ifdef NIC_CPU_VIEW
 
 #ifdef NIC_CPU_VIEW

-  /* These registers are ONLY visible to NIC CPU */
-    T3_32BIT_REGISTER PowerConsumed;
-    T3_32BIT_REGISTER PowerDissipated;
-#else /* NIC_CPU_VIEW */
-    T3_32BIT_REGISTER RegData;
-    T3_32BIT_REGISTER MemWindowData;
-#endif /* !NIC_CPU_VIEW */
+       /* These registers are ONLY visible to NIC CPU */
+       T3_32BIT_REGISTER PowerConsumed;
+       T3_32BIT_REGISTER PowerDissipated;
+#else                          /* NIC_CPU_VIEW */
+       T3_32BIT_REGISTER RegData;
+       T3_32BIT_REGISTER MemWindowData;
+#endif                         /* !NIC_CPU_VIEW */

 
 

-    T3_32BIT_REGISTER ModeCtrl;
+       T3_32BIT_REGISTER ModeCtrl;

 
 

-    T3_32BIT_REGISTER MiscCfg;
+       T3_32BIT_REGISTER MiscCfg;

 
 

-    T3_32BIT_REGISTER MiscLocalCtrl;
+       T3_32BIT_REGISTER MiscLocalCtrl;

 
 

-    T3_32BIT_REGISTER Unused4;
+       T3_32BIT_REGISTER Unused4;

 
 

-    /* NOTE: Big/Little-endian clarification needed.  Are these register */
-    /* in big or little endian formate. */
-    T3_64BIT_REGISTER StdRingProdIdx;
-    T3_64BIT_REGISTER RcvRetRingConIdx;
-    T3_64BIT_REGISTER SndProdIdx;
+       /* NOTE: Big/Little-endian clarification needed.  Are these register */
+       /* in big or little endian formate. */
+       T3_64BIT_REGISTER StdRingProdIdx;
+       T3_64BIT_REGISTER RcvRetRingConIdx;
+       T3_64BIT_REGISTER SndProdIdx;

 
 

-    LM_UINT8 Unused5[80];
+       LM_UINT8 Unused5[80];

 } T3_PCI_CONFIGURATION, *PT3_PCI_CONFIGURATION;
 
 #define PCIX_CMD_MAX_SPLIT_MASK                         0x0070
 } T3_PCI_CONFIGURATION, *PT3_PCI_CONFIGURATION;
 
 #define PCIX_CMD_MAX_SPLIT_MASK                         0x0070


@@ -1374,1382 +1326,1347 @@ typedef struct {
 /******************************************************************************/
 
 typedef struct {
 /******************************************************************************/
 
 typedef struct {

-    /* MAC mode control. */
-    T3_32BIT_REGISTER Mode;
-    #define MAC_MODE_GLOBAL_RESET                       BIT_0
-    #define MAC_MODE_HALF_DUPLEX                        BIT_1
-    #define MAC_MODE_PORT_MODE_MASK                     (BIT_2 | BIT_3)
-    #define MAC_MODE_PORT_MODE_TBI                      (BIT_2 | BIT_3)
-    #define MAC_MODE_PORT_MODE_GMII                     BIT_3
-    #define MAC_MODE_PORT_MODE_MII                      BIT_2
-    #define MAC_MODE_PORT_MODE_NONE                     BIT_NONE
-    #define MAC_MODE_PORT_INTERNAL_LOOPBACK             BIT_4
-    #define MAC_MODE_TAGGED_MAC_CONTROL                 BIT_7
-    #define MAC_MODE_TX_BURSTING                        BIT_8
-    #define MAC_MODE_MAX_DEFER                          BIT_9
-    #define MAC_MODE_LINK_POLARITY                      BIT_10
-    #define MAC_MODE_ENABLE_RX_STATISTICS               BIT_11
-    #define MAC_MODE_CLEAR_RX_STATISTICS                BIT_12
-    #define MAC_MODE_FLUSH_RX_STATISTICS                BIT_13
-    #define MAC_MODE_ENABLE_TX_STATISTICS               BIT_14
-    #define MAC_MODE_CLEAR_TX_STATISTICS                BIT_15
-    #define MAC_MODE_FLUSH_TX_STATISTICS                BIT_16
-    #define MAC_MODE_SEND_CONFIGS                       BIT_17
-    #define MAC_MODE_DETECT_MAGIC_PACKET_ENABLE         BIT_18
-    #define MAC_MODE_ACPI_POWER_ON_ENABLE               BIT_19
-    #define MAC_MODE_ENABLE_MIP                         BIT_20
-    #define MAC_MODE_ENABLE_TDE                         BIT_21
-    #define MAC_MODE_ENABLE_RDE                         BIT_22
-    #define MAC_MODE_ENABLE_FHDE                        BIT_23
-
-    /* MAC status */
-    T3_32BIT_REGISTER Status;
-    #define MAC_STATUS_PCS_SYNCED                       BIT_0
-    #define MAC_STATUS_SIGNAL_DETECTED                  BIT_1
-    #define MAC_STATUS_RECEIVING_CFG                    BIT_2
-    #define MAC_STATUS_CFG_CHANGED                      BIT_3
-    #define MAC_STATUS_SYNC_CHANGED                     BIT_4
-    #define MAC_STATUS_PORT_DECODE_ERROR                BIT_10
-    #define MAC_STATUS_LINK_STATE_CHANGED               BIT_12
-    #define MAC_STATUS_MI_COMPLETION                    BIT_22
-    #define MAC_STATUS_MI_INTERRUPT                     BIT_23
-    #define MAC_STATUS_AP_ERROR                         BIT_24
-    #define MAC_STATUS_ODI_ERROR                        BIT_25
-    #define MAC_STATUS_RX_STATS_OVERRUN                 BIT_26
-    #define MAC_STATUS_TX_STATS_OVERRUN                 BIT_27
-
-    /* Event Enable */
-    T3_32BIT_REGISTER MacEvent;
-    #define MAC_EVENT_ENABLE_PORT_DECODE_ERR            BIT_10
-    #define MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN    BIT_12
-    #define MAC_EVENT_ENABLE_MI_COMPLETION              BIT_22
-    #define MAC_EVENT_ENABLE_MI_INTERRUPT               BIT_23
-    #define MAC_EVENT_ENABLE_AP_ERROR                   BIT_24
-    #define MAC_EVENT_ENABLE_ODI_ERROR                  BIT_25
-    #define MAC_EVENT_ENABLE_RX_STATS_OVERRUN           BIT_26
-    #define MAC_EVENT_ENABLE_TX_STATS_OVERRUN           BIT_27
-
-    /* Led control. */
-    T3_32BIT_REGISTER LedCtrl;
-    #define LED_CTRL_OVERRIDE_LINK_LED                  BIT_0
-    #define LED_CTRL_1000MBPS_LED_ON                    BIT_1
-    #define LED_CTRL_100MBPS_LED_ON                     BIT_2
-    #define LED_CTRL_10MBPS_LED_ON                      BIT_3
-    #define LED_CTRL_OVERRIDE_TRAFFIC_LED               BIT_4
-    #define LED_CTRL_BLINK_TRAFFIC_LED                  BIT_5
-    #define LED_CTRL_TRAFFIC_LED                        BIT_6
-    #define LED_CTRL_1000MBPS_LED_STATUS                BIT_7
-    #define LED_CTRL_100MBPS_LED_STATUS                 BIT_8
-    #define LED_CTRL_10MBPS_LED_STATUS                  BIT_9
-    #define LED_CTRL_TRAFFIC_LED_STATUS                 BIT_10
-    #define LED_CTRL_MAC_MODE                           BIT_NONE
-    #define LED_CTRL_PHY_MODE_1                         BIT_11
-    #define LED_CTRL_PHY_MODE_2                         BIT_12
-    #define LED_CTRL_BLINK_RATE_MASK                    0x7ff80000
-    #define LED_CTRL_OVERRIDE_BLINK_PERIOD              BIT_19
-    #define LED_CTRL_OVERRIDE_BLINK_RATE                BIT_31
-
-    /* MAC addresses. */
-    struct {
-       T3_32BIT_REGISTER High;             /* Upper 2 bytes. */
-       T3_32BIT_REGISTER Low;              /* Lower 4 bytes. */
-    } MacAddr[4];
-
-    /* ACPI Mbuf pointer. */
-    T3_32BIT_REGISTER AcpiMbufPtr;
-
-    /* ACPI Length and Offset. */
-    T3_32BIT_REGISTER AcpiLengthOffset;
-    #define ACPI_LENGTH_MASK                            0xffff
-    #define ACPI_OFFSET_MASK                            0x0fff0000
-    #define ACPI_LENGTH(x)                              x
-    #define ACPI_OFFSET(x)                              ((x) << 16)
-
-    /* Transmit random backoff. */
-    T3_32BIT_REGISTER TxBackoffSeed;
-    #define MAC_TX_BACKOFF_SEED_MASK                    0x3ff
-
-    /* Receive MTU */
-    T3_32BIT_REGISTER MtuSize;
-    #define MAC_RX_MTU_MASK                             0xffff
-
-    /* Gigabit PCS Test. */
-    T3_32BIT_REGISTER PcsTest;
-    #define MAC_PCS_TEST_DATA_PATTERN_MASK              0x0fffff
-    #define MAC_PCS_TEST_ENABLE                         BIT_20
-
-    /* Transmit Gigabit Auto-Negotiation. */
-    T3_32BIT_REGISTER TxAutoNeg;
-    #define MAC_AN_TX_AN_DATA_MASK                      0xffff
-
-    /* Receive Gigabit Auto-Negotiation. */
-    T3_32BIT_REGISTER RxAutoNeg;
-    #define MAC_AN_RX_AN_DATA_MASK                      0xffff
-
-    /* MI Communication. */
-    T3_32BIT_REGISTER MiCom;
-    #define MI_COM_CMD_MASK                             (BIT_26 | BIT_27)
-    #define MI_COM_CMD_WRITE                            BIT_26
-    #define MI_COM_CMD_READ                             BIT_27
-    #define MI_COM_READ_FAILED                          BIT_28
-    #define MI_COM_START                                BIT_29
-    #define MI_COM_BUSY                                 BIT_29
-
-    #define MI_COM_PHY_ADDR_MASK                        0x1f
-    #define MI_COM_FIRST_PHY_ADDR_BIT                   21
-
-    #define MI_COM_PHY_REG_ADDR_MASK                    0x1f
-    #define MI_COM_FIRST_PHY_REG_ADDR_BIT               16
-
-    #define MI_COM_PHY_DATA_MASK                        0xffff
-
-    /* MI Status. */
-    T3_32BIT_REGISTER MiStatus;
-    #define MI_STATUS_ENABLE_LINK_STATUS_ATTN           BIT_0
-
-    /* MI Mode. */
-    T3_32BIT_REGISTER MiMode;
-    #define MI_MODE_CLOCK_SPEED_10MHZ                   BIT_0
-    #define MI_MODE_USE_SHORT_PREAMBLE                  BIT_1
-    #define MI_MODE_AUTO_POLLING_ENABLE                 BIT_4
-    #define MI_MODE_CORE_CLOCK_SPEED_62MHZ              BIT_15
-
-    /* Auto-polling status. */
-    T3_32BIT_REGISTER AutoPollStatus;
-    #define AUTO_POLL_ERROR                             BIT_0
-
-    /* Transmit MAC mode. */
-    T3_32BIT_REGISTER TxMode;
-    #define TX_MODE_RESET                               BIT_0
-    #define TX_MODE_ENABLE                              BIT_1
-    #define TX_MODE_ENABLE_FLOW_CONTROL                 BIT_4
-    #define TX_MODE_ENABLE_BIG_BACKOFF                  BIT_5
-    #define TX_MODE_ENABLE_LONG_PAUSE                   BIT_6
-
-    /* Transmit MAC status. */
-    T3_32BIT_REGISTER TxStatus;
-    #define TX_STATUS_RX_CURRENTLY_XOFFED               BIT_0
-    #define TX_STATUS_SENT_XOFF                         BIT_1
-    #define TX_STATUS_SENT_XON                          BIT_2
-    #define TX_STATUS_LINK_UP                           BIT_3
-    #define TX_STATUS_ODI_UNDERRUN                      BIT_4
-    #define TX_STATUS_ODI_OVERRUN                       BIT_5
-
-    /* Transmit MAC length. */
-    T3_32BIT_REGISTER TxLengths;
-    #define TX_LEN_SLOT_TIME_MASK                       0xff
-    #define TX_LEN_IPG_MASK                             0x0f00
-    #define TX_LEN_IPG_CRS_MASK                         (BIT_12 | BIT_13)
-
-    /* Receive MAC mode. */
-    T3_32BIT_REGISTER RxMode;
-    #define RX_MODE_RESET                               BIT_0
-    #define RX_MODE_ENABLE                              BIT_1
-    #define RX_MODE_ENABLE_FLOW_CONTROL                 BIT_2
-    #define RX_MODE_KEEP_MAC_CONTROL                    BIT_3
-    #define RX_MODE_KEEP_PAUSE                          BIT_4
-    #define RX_MODE_ACCEPT_OVERSIZED                    BIT_5
-    #define RX_MODE_ACCEPT_RUNTS                        BIT_6
-    #define RX_MODE_LENGTH_CHECK                        BIT_7
-    #define RX_MODE_PROMISCUOUS_MODE                    BIT_8
-    #define RX_MODE_NO_CRC_CHECK                        BIT_9
-    #define RX_MODE_KEEP_VLAN_TAG                       BIT_10
-
-    /* Receive MAC status. */
-    T3_32BIT_REGISTER RxStatus;
-    #define RX_STATUS_REMOTE_TRANSMITTER_XOFFED         BIT_0
-    #define RX_STATUS_XOFF_RECEIVED                     BIT_1
-    #define RX_STATUS_XON_RECEIVED                      BIT_2
-
-    /* Hash registers. */
-    T3_32BIT_REGISTER HashReg[4];
-
-    /* Receive placement rules registers. */
-    struct {
-       T3_32BIT_REGISTER Rule;
-       T3_32BIT_REGISTER Value;
-    } RcvRules[16];
-
-    #define RCV_DISABLE_RULE_MASK                       0x7fffffff
-
-    #define RCV_RULE1_REJECT_BROADCAST_IDX              0x00
-    #define REJECT_BROADCAST_RULE1_RULE                 0xc2000000
-    #define REJECT_BROADCAST_RULE1_VALUE                0xffffffff
-
-    #define RCV_RULE2_REJECT_BROADCAST_IDX              0x01
-    #define REJECT_BROADCAST_RULE2_RULE                 0x86000004
-    #define REJECT_BROADCAST_RULE2_VALUE                0xffffffff
+       /* MAC mode control. */
+       T3_32BIT_REGISTER Mode;
+#define MAC_MODE_GLOBAL_RESET                       BIT_0
+#define MAC_MODE_HALF_DUPLEX                        BIT_1
+#define MAC_MODE_PORT_MODE_MASK                     (BIT_2 | BIT_3)
+#define MAC_MODE_PORT_MODE_TBI                      (BIT_2 | BIT_3)
+#define MAC_MODE_PORT_MODE_GMII                     BIT_3
+#define MAC_MODE_PORT_MODE_MII                      BIT_2
+#define MAC_MODE_PORT_MODE_NONE                     BIT_NONE
+#define MAC_MODE_PORT_INTERNAL_LOOPBACK             BIT_4
+#define MAC_MODE_TAGGED_MAC_CONTROL                 BIT_7
+#define MAC_MODE_TX_BURSTING                        BIT_8
+#define MAC_MODE_MAX_DEFER                          BIT_9
+#define MAC_MODE_LINK_POLARITY                      BIT_10
+#define MAC_MODE_ENABLE_RX_STATISTICS               BIT_11
+#define MAC_MODE_CLEAR_RX_STATISTICS                BIT_12
+#define MAC_MODE_FLUSH_RX_STATISTICS                BIT_13
+#define MAC_MODE_ENABLE_TX_STATISTICS               BIT_14
+#define MAC_MODE_CLEAR_TX_STATISTICS                BIT_15
+#define MAC_MODE_FLUSH_TX_STATISTICS                BIT_16
+#define MAC_MODE_SEND_CONFIGS                       BIT_17
+#define MAC_MODE_DETECT_MAGIC_PACKET_ENABLE         BIT_18
+#define MAC_MODE_ACPI_POWER_ON_ENABLE               BIT_19
+#define MAC_MODE_ENABLE_MIP                         BIT_20
+#define MAC_MODE_ENABLE_TDE                         BIT_21
+#define MAC_MODE_ENABLE_RDE                         BIT_22
+#define MAC_MODE_ENABLE_FHDE                        BIT_23
+
+       /* MAC status */
+       T3_32BIT_REGISTER Status;
+#define MAC_STATUS_PCS_SYNCED                       BIT_0
+#define MAC_STATUS_SIGNAL_DETECTED                  BIT_1
+#define MAC_STATUS_RECEIVING_CFG                    BIT_2
+#define MAC_STATUS_CFG_CHANGED                      BIT_3
+#define MAC_STATUS_SYNC_CHANGED                     BIT_4
+#define MAC_STATUS_PORT_DECODE_ERROR                BIT_10
+#define MAC_STATUS_LINK_STATE_CHANGED               BIT_12
+#define MAC_STATUS_MI_COMPLETION                    BIT_22
+#define MAC_STATUS_MI_INTERRUPT                     BIT_23
+#define MAC_STATUS_AP_ERROR                         BIT_24
+#define MAC_STATUS_ODI_ERROR                        BIT_25
+#define MAC_STATUS_RX_STATS_OVERRUN                 BIT_26
+#define MAC_STATUS_TX_STATS_OVERRUN                 BIT_27
+
+       /* Event Enable */
+       T3_32BIT_REGISTER MacEvent;
+#define MAC_EVENT_ENABLE_PORT_DECODE_ERR            BIT_10
+#define MAC_EVENT_ENABLE_LINK_STATE_CHANGED_ATTN    BIT_12
+#define MAC_EVENT_ENABLE_MI_COMPLETION              BIT_22
+#define MAC_EVENT_ENABLE_MI_INTERRUPT               BIT_23
+#define MAC_EVENT_ENABLE_AP_ERROR                   BIT_24
+#define MAC_EVENT_ENABLE_ODI_ERROR                  BIT_25
+#define MAC_EVENT_ENABLE_RX_STATS_OVERRUN           BIT_26
+#define MAC_EVENT_ENABLE_TX_STATS_OVERRUN           BIT_27
+
+       /* Led control. */
+       T3_32BIT_REGISTER LedCtrl;
+#define LED_CTRL_OVERRIDE_LINK_LED                  BIT_0
+#define LED_CTRL_1000MBPS_LED_ON                    BIT_1
+#define LED_CTRL_100MBPS_LED_ON                     BIT_2
+#define LED_CTRL_10MBPS_LED_ON                      BIT_3
+#define LED_CTRL_OVERRIDE_TRAFFIC_LED               BIT_4
+#define LED_CTRL_BLINK_TRAFFIC_LED                  BIT_5
+#define LED_CTRL_TRAFFIC_LED                        BIT_6
+#define LED_CTRL_1000MBPS_LED_STATUS                BIT_7
+#define LED_CTRL_100MBPS_LED_STATUS                 BIT_8
+#define LED_CTRL_10MBPS_LED_STATUS                  BIT_9
+#define LED_CTRL_TRAFFIC_LED_STATUS                 BIT_10
+#define LED_CTRL_MAC_MODE                           BIT_NONE
+#define LED_CTRL_PHY_MODE_1                         BIT_11
+#define LED_CTRL_PHY_MODE_2                         BIT_12
+#define LED_CTRL_BLINK_RATE_MASK                    0x7ff80000
+#define LED_CTRL_OVERRIDE_BLINK_PERIOD              BIT_19
+#define LED_CTRL_OVERRIDE_BLINK_RATE                BIT_31
+
+       /* MAC addresses. */
+       struct {
+               T3_32BIT_REGISTER High; /* Upper 2 bytes. */
+               T3_32BIT_REGISTER Low;  /* Lower 4 bytes. */
+       } MacAddr[4];
+
+       /* ACPI Mbuf pointer. */
+       T3_32BIT_REGISTER AcpiMbufPtr;
+
+       /* ACPI Length and Offset. */
+       T3_32BIT_REGISTER AcpiLengthOffset;
+#define ACPI_LENGTH_MASK                            0xffff
+#define ACPI_OFFSET_MASK                            0x0fff0000
+#define ACPI_LENGTH(x)                              x
+#define ACPI_OFFSET(x)                              ((x) << 16)
+
+       /* Transmit random backoff. */
+       T3_32BIT_REGISTER TxBackoffSeed;
+#define MAC_TX_BACKOFF_SEED_MASK                    0x3ff
+
+       /* Receive MTU */
+       T3_32BIT_REGISTER MtuSize;
+#define MAC_RX_MTU_MASK                             0xffff
+
+       /* Gigabit PCS Test. */
+       T3_32BIT_REGISTER PcsTest;
+#define MAC_PCS_TEST_DATA_PATTERN_MASK              0x0fffff
+#define MAC_PCS_TEST_ENABLE                         BIT_20
+
+       /* Transmit Gigabit Auto-Negotiation. */
+       T3_32BIT_REGISTER TxAutoNeg;
+#define MAC_AN_TX_AN_DATA_MASK                      0xffff
+
+       /* Receive Gigabit Auto-Negotiation. */
+       T3_32BIT_REGISTER RxAutoNeg;
+#define MAC_AN_RX_AN_DATA_MASK                      0xffff
+
+       /* MI Communication. */
+       T3_32BIT_REGISTER MiCom;
+#define MI_COM_CMD_MASK                             (BIT_26 | BIT_27)
+#define MI_COM_CMD_WRITE                            BIT_26
+#define MI_COM_CMD_READ                             BIT_27
+#define MI_COM_READ_FAILED                          BIT_28
+#define MI_COM_START                                BIT_29
+#define MI_COM_BUSY                                 BIT_29
+
+#define MI_COM_PHY_ADDR_MASK                        0x1f
+#define MI_COM_FIRST_PHY_ADDR_BIT                   21
+
+#define MI_COM_PHY_REG_ADDR_MASK                    0x1f
+#define MI_COM_FIRST_PHY_REG_ADDR_BIT               16
+
+#define MI_COM_PHY_DATA_MASK                        0xffff
+
+       /* MI Status. */
+       T3_32BIT_REGISTER MiStatus;
+#define MI_STATUS_ENABLE_LINK_STATUS_ATTN           BIT_0
+
+       /* MI Mode. */
+       T3_32BIT_REGISTER MiMode;
+#define MI_MODE_CLOCK_SPEED_10MHZ                   BIT_0
+#define MI_MODE_USE_SHORT_PREAMBLE                  BIT_1
+#define MI_MODE_AUTO_POLLING_ENABLE                 BIT_4
+#define MI_MODE_CORE_CLOCK_SPEED_62MHZ              BIT_15
+
+       /* Auto-polling status. */
+       T3_32BIT_REGISTER AutoPollStatus;
+#define AUTO_POLL_ERROR                             BIT_0
+
+       /* Transmit MAC mode. */
+       T3_32BIT_REGISTER TxMode;
+#define TX_MODE_RESET                               BIT_0
+#define TX_MODE_ENABLE                              BIT_1
+#define TX_MODE_ENABLE_FLOW_CONTROL                 BIT_4
+#define TX_MODE_ENABLE_BIG_BACKOFF                  BIT_5
+#define TX_MODE_ENABLE_LONG_PAUSE                   BIT_6
+
+       /* Transmit MAC status. */
+       T3_32BIT_REGISTER TxStatus;
+#define TX_STATUS_RX_CURRENTLY_XOFFED               BIT_0
+#define TX_STATUS_SENT_XOFF                         BIT_1
+#define TX_STATUS_SENT_XON                          BIT_2
+#define TX_STATUS_LINK_UP                           BIT_3
+#define TX_STATUS_ODI_UNDERRUN                      BIT_4
+#define TX_STATUS_ODI_OVERRUN                       BIT_5
+
+       /* Transmit MAC length. */
+       T3_32BIT_REGISTER TxLengths;
+#define TX_LEN_SLOT_TIME_MASK                       0xff
+#define TX_LEN_IPG_MASK                             0x0f00
+#define TX_LEN_IPG_CRS_MASK                         (BIT_12 | BIT_13)
+
+       /* Receive MAC mode. */
+       T3_32BIT_REGISTER RxMode;
+#define RX_MODE_RESET                               BIT_0
+#define RX_MODE_ENABLE                              BIT_1
+#define RX_MODE_ENABLE_FLOW_CONTROL                 BIT_2
+#define RX_MODE_KEEP_MAC_CONTROL                    BIT_3
+#define RX_MODE_KEEP_PAUSE                          BIT_4
+#define RX_MODE_ACCEPT_OVERSIZED                    BIT_5
+#define RX_MODE_ACCEPT_RUNTS                        BIT_6
+#define RX_MODE_LENGTH_CHECK                        BIT_7
+#define RX_MODE_PROMISCUOUS_MODE                    BIT_8
+#define RX_MODE_NO_CRC_CHECK                        BIT_9
+#define RX_MODE_KEEP_VLAN_TAG                       BIT_10
+
+       /* Receive MAC status. */
+       T3_32BIT_REGISTER RxStatus;
+#define RX_STATUS_REMOTE_TRANSMITTER_XOFFED         BIT_0
+#define RX_STATUS_XOFF_RECEIVED                     BIT_1
+#define RX_STATUS_XON_RECEIVED                      BIT_2
+
+       /* Hash registers. */
+       T3_32BIT_REGISTER HashReg[4];
+
+       /* Receive placement rules registers. */
+       struct {
+               T3_32BIT_REGISTER Rule;
+               T3_32BIT_REGISTER Value;
+       } RcvRules[16];
+
+#define RCV_DISABLE_RULE_MASK                       0x7fffffff
+
+#define RCV_RULE1_REJECT_BROADCAST_IDX              0x00
+#define REJECT_BROADCAST_RULE1_RULE                 0xc2000000
+#define REJECT_BROADCAST_RULE1_VALUE                0xffffffff
+
+#define RCV_RULE2_REJECT_BROADCAST_IDX              0x01
+#define REJECT_BROADCAST_RULE2_RULE                 0x86000004
+#define REJECT_BROADCAST_RULE2_VALUE                0xffffffff

 
 #if INCLUDE_5701_AX_FIX
 
 #if INCLUDE_5701_AX_FIX

-    #define RCV_LAST_RULE_IDX                           0x04
+#define RCV_LAST_RULE_IDX                           0x04

 #else
 #else

-    #define RCV_LAST_RULE_IDX                           0x02
+#define RCV_LAST_RULE_IDX                           0x02

 #endif
 
 #endif
 

-    T3_32BIT_REGISTER RcvRuleCfg;
-    #define RX_RULE_DEFAULT_CLASS                       (1 << 3)
+       T3_32BIT_REGISTER RcvRuleCfg;
+#define RX_RULE_DEFAULT_CLASS                       (1 << 3)

 
 

-    LM_UINT8 Reserved1[140];
+       LM_UINT8 Reserved1[140];

 
 

-    T3_32BIT_REGISTER SerdesCfg;
-    T3_32BIT_REGISTER SerdesStatus;
+       T3_32BIT_REGISTER SerdesCfg;
+       T3_32BIT_REGISTER SerdesStatus;

 
 

-    LM_UINT8 Reserved2[104];
+       LM_UINT8 Reserved2[104];

 
 

-    volatile LM_UINT8 TxMacState[16];
-    volatile LM_UINT8 RxMacState[20];
+       volatile LM_UINT8 TxMacState[16];
+       volatile LM_UINT8 RxMacState[20];

 
 

-    LM_UINT8 Reserved3[476];
+       LM_UINT8 Reserved3[476];

 
 

-    T3_32BIT_REGISTER RxStats[26];
+       T3_32BIT_REGISTER RxStats[26];

 
 

-    LM_UINT8 Reserved4[24];
+       LM_UINT8 Reserved4[24];

 
 

-    T3_32BIT_REGISTER TxStats[28];
+       T3_32BIT_REGISTER TxStats[28];

 
 

-    LM_UINT8 Reserved5[784];
+       LM_UINT8 Reserved5[784];

 } T3_MAC_CONTROL, *PT3_MAC_CONTROL;
 
 } T3_MAC_CONTROL, *PT3_MAC_CONTROL;
 

-

 /******************************************************************************/
 /* Send data initiator control registers. */
 /******************************************************************************/
 
 typedef struct {
 /******************************************************************************/
 /* Send data initiator control registers. */
 /******************************************************************************/
 
 typedef struct {

-    T3_32BIT_REGISTER Mode;
-    #define T3_SND_DATA_IN_MODE_RESET                       BIT_0
-    #define T3_SND_DATA_IN_MODE_ENABLE                      BIT_1
-    #define T3_SND_DATA_IN_MODE_STATS_OFLW_ATTN_ENABLE      BIT_2
-
-    T3_32BIT_REGISTER Status;
-    #define T3_SND_DATA_IN_STATUS_STATS_OFLW_ATTN           BIT_2
-
-    T3_32BIT_REGISTER StatsCtrl;
-    #define T3_SND_DATA_IN_STATS_CTRL_ENABLE                BIT_0
-    #define T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE         BIT_1
-    #define T3_SND_DATA_IN_STATS_CTRL_CLEAR                 BIT_2
-    #define T3_SND_DATA_IN_STATS_CTRL_FLUSH                 BIT_3
-    #define T3_SND_DATA_IN_STATS_CTRL_FORCE_ZERO            BIT_4
-
-    T3_32BIT_REGISTER StatsEnableMask;
-    T3_32BIT_REGISTER StatsIncMask;
-
-    LM_UINT8 Reserved[108];
-
-    T3_32BIT_REGISTER ClassOfServCnt[16];
-    T3_32BIT_REGISTER DmaReadQFullCnt;
-    T3_32BIT_REGISTER DmaPriorityReadQFullCnt;
-    T3_32BIT_REGISTER SdcQFullCnt;
-
-    T3_32BIT_REGISTER NicRingSetSendProdIdxCnt;
-    T3_32BIT_REGISTER StatusUpdatedCnt;
-    T3_32BIT_REGISTER InterruptsCnt;
-    T3_32BIT_REGISTER AvoidInterruptsCnt;
-    T3_32BIT_REGISTER SendThresholdHitCnt;
-
-    /* Unused space. */
-    LM_UINT8 Unused[800];
-} T3_SEND_DATA_INITIATOR, *PT3_SEND_DATA_INITIATOR;
+       T3_32BIT_REGISTER Mode;
+#define T3_SND_DATA_IN_MODE_RESET                       BIT_0
+#define T3_SND_DATA_IN_MODE_ENABLE                      BIT_1
+#define T3_SND_DATA_IN_MODE_STATS_OFLW_ATTN_ENABLE      BIT_2
+
+       T3_32BIT_REGISTER Status;
+#define T3_SND_DATA_IN_STATUS_STATS_OFLW_ATTN           BIT_2
+
+       T3_32BIT_REGISTER StatsCtrl;
+#define T3_SND_DATA_IN_STATS_CTRL_ENABLE                BIT_0
+#define T3_SND_DATA_IN_STATS_CTRL_FASTER_UPDATE         BIT_1
+#define T3_SND_DATA_IN_STATS_CTRL_CLEAR                 BIT_2
+#define T3_SND_DATA_IN_STATS_CTRL_FLUSH                 BIT_3
+#define T3_SND_DATA_IN_STATS_CTRL_FORCE_ZERO            BIT_4
+
+       T3_32BIT_REGISTER StatsEnableMask;
+       T3_32BIT_REGISTER StatsIncMask;
+
+       LM_UINT8 Reserved[108];

 
 

+       T3_32BIT_REGISTER ClassOfServCnt[16];
+       T3_32BIT_REGISTER DmaReadQFullCnt;
+       T3_32BIT_REGISTER DmaPriorityReadQFullCnt;
+       T3_32BIT_REGISTER SdcQFullCnt;
+
+       T3_32BIT_REGISTER NicRingSetSendProdIdxCnt;
+       T3_32BIT_REGISTER StatusUpdatedCnt;
+       T3_32BIT_REGISTER InterruptsCnt;
+       T3_32BIT_REGISTER AvoidInterruptsCnt;
+       T3_32BIT_REGISTER SendThresholdHitCnt;
+
+       /* Unused space. */
+       LM_UINT8 Unused[800];
+} T3_SEND_DATA_INITIATOR, *PT3_SEND_DATA_INITIATOR;

 
 /******************************************************************************/
 /* Send data completion control registers. */
 /******************************************************************************/
 
 typedef struct {
 
 /******************************************************************************/
 /* Send data completion control registers. */
 /******************************************************************************/
 
 typedef struct {

-    T3_32BIT_REGISTER Mode;
-    #define SND_DATA_COMP_MODE_RESET                        BIT_0
-    #define SND_DATA_COMP_MODE_ENABLE                       BIT_1
+       T3_32BIT_REGISTER Mode;
+#define SND_DATA_COMP_MODE_RESET                        BIT_0
+#define SND_DATA_COMP_MODE_ENABLE                       BIT_1

 
 

-    /* Unused space. */
-    LM_UINT8 Unused[1020];
+       /* Unused space. */
+       LM_UINT8 Unused[1020];

 } T3_SEND_DATA_COMPLETION, *PT3_SEND_DATA_COMPLETION;
 
 } T3_SEND_DATA_COMPLETION, *PT3_SEND_DATA_COMPLETION;
 

-

 /******************************************************************************/
 /* Send BD Ring Selector Control Registers. */
 /******************************************************************************/
 
 typedef struct {
 /******************************************************************************/
 /* Send BD Ring Selector Control Registers. */
 /******************************************************************************/
 
 typedef struct {

-    T3_32BIT_REGISTER Mode;
-    #define SND_BD_SEL_MODE_RESET                           BIT_0
-    #define SND_BD_SEL_MODE_ENABLE                          BIT_1
-    #define SND_BD_SEL_MODE_ATTN_ENABLE                     BIT_2
+       T3_32BIT_REGISTER Mode;
+#define SND_BD_SEL_MODE_RESET                           BIT_0
+#define SND_BD_SEL_MODE_ENABLE                          BIT_1
+#define SND_BD_SEL_MODE_ATTN_ENABLE                     BIT_2

 
 

-    T3_32BIT_REGISTER Status;
-    #define SND_BD_SEL_STATUS_ERROR_ATTN                    BIT_2
+       T3_32BIT_REGISTER Status;
+#define SND_BD_SEL_STATUS_ERROR_ATTN                    BIT_2

 
 

-    T3_32BIT_REGISTER HwDiag;
+       T3_32BIT_REGISTER HwDiag;

 
 

-    /* Unused space. */
-    LM_UINT8 Unused1[52];
+       /* Unused space. */
+       LM_UINT8 Unused1[52];

 
 

-    /* Send BD Ring Selector Local NIC Send BD Consumer Index. */
-    T3_32BIT_REGISTER NicSendBdSelConIdx[16];
+       /* Send BD Ring Selector Local NIC Send BD Consumer Index. */
+       T3_32BIT_REGISTER NicSendBdSelConIdx[16];

 
 

-    /* Unused space. */
-    LM_UINT8 Unused2[896];
+       /* Unused space. */
+       LM_UINT8 Unused2[896];

 } T3_SEND_BD_SELECTOR, *PT3_SEND_BD_SELECTOR;
 
 } T3_SEND_BD_SELECTOR, *PT3_SEND_BD_SELECTOR;
 

-

 /******************************************************************************/
 /* Send BD initiator control registers. */
 /******************************************************************************/
 
 typedef struct {
 /******************************************************************************/
 /* Send BD initiator control registers. */
 /******************************************************************************/
 
 typedef struct {

-    T3_32BIT_REGISTER Mode;
-    #define SND_BD_IN_MODE_RESET                            BIT_0
-    #define SND_BD_IN_MODE_ENABLE                           BIT_1
-    #define SND_BD_IN_MODE_ATTN_ENABLE                      BIT_2
+       T3_32BIT_REGISTER Mode;
+#define SND_BD_IN_MODE_RESET                            BIT_0
+#define SND_BD_IN_MODE_ENABLE                           BIT_1
+#define SND_BD_IN_MODE_ATTN_ENABLE                      BIT_2

 
 

-    T3_32BIT_REGISTER Status;
-    #define SND_BD_IN_STATUS_ERROR_ATTN                     BIT_2
+       T3_32BIT_REGISTER Status;
+#define SND_BD_IN_STATUS_ERROR_ATTN                     BIT_2

 
 

-    /* Send BD initiator local NIC send BD producer index. */
-    T3_32BIT_REGISTER NicSendBdInProdIdx[16];
+       /* Send BD initiator local NIC send BD producer index. */
+       T3_32BIT_REGISTER NicSendBdInProdIdx[16];

 
 

-    /* Unused space. */
-    LM_UINT8 Unused2[952];
+       /* Unused space. */
+       LM_UINT8 Unused2[952];

 } T3_SEND_BD_INITIATOR, *PT3_SEND_BD_INITIATOR;
 
 } T3_SEND_BD_INITIATOR, *PT3_SEND_BD_INITIATOR;
 

-

 /******************************************************************************/
 /* Send BD Completion Control. */
 /******************************************************************************/
 
 typedef struct {
 /******************************************************************************/
 /* Send BD Completion Control. */
 /******************************************************************************/
 
 typedef struct {

-    T3_32BIT_REGISTER Mode;
-    #define SND_BD_COMP_MODE_RESET                          BIT_0
-    #define SND_BD_COMP_MODE_ENABLE                         BIT_1
-    #define SND_BD_COMP_MODE_ATTN_ENABLE                    BIT_2
+       T3_32BIT_REGISTER Mode;
+#define SND_BD_COMP_MODE_RESET                          BIT_0
+#define SND_BD_COMP_MODE_ENABLE                         BIT_1
+#define SND_BD_COMP_MODE_ATTN_ENABLE                    BIT_2

 
 

-    /* Unused space. */
-    LM_UINT8 Unused2[1020];
+       /* Unused space. */
+       LM_UINT8 Unused2[1020];

 } T3_SEND_BD_COMPLETION, *PT3_SEND_BD_COMPLETION;
 
 } T3_SEND_BD_COMPLETION, *PT3_SEND_BD_COMPLETION;
 

-

 /******************************************************************************/
 /* Receive list placement control registers. */
 /******************************************************************************/
 
 typedef struct {
 /******************************************************************************/
 /* Receive list placement control registers. */
 /******************************************************************************/
 
 typedef struct {

-    /* Mode. */
-    T3_32BIT_REGISTER Mode;
-    #define RCV_LIST_PLMT_MODE_RESET                        BIT_0
-    #define RCV_LIST_PLMT_MODE_ENABLE                       BIT_1
-    #define RCV_LIST_PLMT_MODE_CLASS0_ATTN_ENABLE           BIT_2
-    #define RCV_LIST_PLMT_MODE_MAPPING_OOR_ATTN_ENABLE      BIT_3
-    #define RCV_LIST_PLMT_MODE_STATS_OFLOW_ATTN_ENABLE      BIT_4
-
-    /* Status. */
-    T3_32BIT_REGISTER Status;
-    #define RCV_LIST_PLMT_STATUS_CLASS0_ATTN                BIT_2
-    #define RCV_LIST_PLMT_STATUS_MAPPING_ATTN               BIT_3
-    #define RCV_LIST_PLMT_STATUS_STATS_OFLOW_ATTN           BIT_4
-
-    /* Receive selector list lock register. */
-    T3_32BIT_REGISTER Lock;
-    #define RCV_LIST_SEL_LOCK_REQUEST_MASK                  0xffff
-    #define RCV_LIST_SEL_LOCK_GRANT_MASK                    0xffff0000
-
-    /* Selector non-empty bits. */
-    T3_32BIT_REGISTER NonEmptyBits;
-    #define RCV_LIST_SEL_NON_EMPTY_MASK                     0xffff
-
-    /* Receive list placement configuration register. */
-    T3_32BIT_REGISTER Config;
-
-    /* Receive List Placement statistics Control. */
-    T3_32BIT_REGISTER StatsCtrl;
+       /* Mode. */
+       T3_32BIT_REGISTER Mode;
+#define RCV_LIST_PLMT_MODE_RESET                        BIT_0
+#define RCV_LIST_PLMT_MODE_ENABLE                       BIT_1
+#define RCV_LIST_PLMT_MODE_CLASS0_ATTN_ENABLE           BIT_2
+#define RCV_LIST_PLMT_MODE_MAPPING_OOR_ATTN_ENABLE      BIT_3
+#define RCV_LIST_PLMT_MODE_STATS_OFLOW_ATTN_ENABLE      BIT_4
+
+       /* Status. */
+       T3_32BIT_REGISTER Status;
+#define RCV_LIST_PLMT_STATUS_CLASS0_ATTN                BIT_2
+#define RCV_LIST_PLMT_STATUS_MAPPING_ATTN               BIT_3
+#define RCV_LIST_PLMT_STATUS_STATS_OFLOW_ATTN           BIT_4
+
+       /* Receive selector list lock register. */
+       T3_32BIT_REGISTER Lock;
+#define RCV_LIST_SEL_LOCK_REQUEST_MASK                  0xffff
+#define RCV_LIST_SEL_LOCK_GRANT_MASK                    0xffff0000
+
+       /* Selector non-empty bits. */
+       T3_32BIT_REGISTER NonEmptyBits;
+#define RCV_LIST_SEL_NON_EMPTY_MASK                     0xffff
+
+       /* Receive list placement configuration register. */
+       T3_32BIT_REGISTER Config;
+
+       /* Receive List Placement statistics Control. */
+       T3_32BIT_REGISTER StatsCtrl;

 #define RCV_LIST_STATS_ENABLE                               BIT_0
 #define RCV_LIST_STATS_FAST_UPDATE                          BIT_1
 
 #define RCV_LIST_STATS_ENABLE                               BIT_0
 #define RCV_LIST_STATS_FAST_UPDATE                          BIT_1
 

-    /* Receive List Placement statistics Enable Mask. */
-    T3_32BIT_REGISTER StatsEnableMask;
-
-    /* Receive List Placement statistics Increment Mask. */
-    T3_32BIT_REGISTER StatsIncMask;
-
-    /* Unused space. */
-    LM_UINT8 Unused1[224];
+       /* Receive List Placement statistics Enable Mask. */
+       T3_32BIT_REGISTER StatsEnableMask;

 
 

-    struct {
-       T3_32BIT_REGISTER Head;
-       T3_32BIT_REGISTER Tail;
-       T3_32BIT_REGISTER Count;
+       /* Receive List Placement statistics Increment Mask. */
+       T3_32BIT_REGISTER StatsIncMask;

 
        /* Unused space. */
 
        /* Unused space. */

-       LM_UINT8 Unused[4];
-    } RcvSelectorList[16];
-
-    /* Local statistics counter. */
-    T3_32BIT_REGISTER ClassOfServCnt[16];
-
-    T3_32BIT_REGISTER DropDueToFilterCnt;
-    T3_32BIT_REGISTER DmaWriteQFullCnt;
-    T3_32BIT_REGISTER DmaHighPriorityWriteQFullCnt;
-    T3_32BIT_REGISTER NoMoreReceiveBdCnt;
-    T3_32BIT_REGISTER IfInDiscardsCnt;
-    T3_32BIT_REGISTER IfInErrorsCnt;
-    T3_32BIT_REGISTER RcvThresholdHitCnt;
-
-    /* Another unused space. */
-    LM_UINT8 Unused2[420];
-} T3_RCV_LIST_PLACEMENT, *PT3_RCV_LIST_PLACEMENT;
+       LM_UINT8 Unused1[224];

 
 

+       struct {
+               T3_32BIT_REGISTER Head;
+               T3_32BIT_REGISTER Tail;
+               T3_32BIT_REGISTER Count;
+
+               /* Unused space. */
+               LM_UINT8 Unused[4];
+       } RcvSelectorList[16];
+
+       /* Local statistics counter. */
+       T3_32BIT_REGISTER ClassOfServCnt[16];
+
+       T3_32BIT_REGISTER DropDueToFilterCnt;
+       T3_32BIT_REGISTER DmaWriteQFullCnt;
+       T3_32BIT_REGISTER DmaHighPriorityWriteQFullCnt;
+       T3_32BIT_REGISTER NoMoreReceiveBdCnt;
+       T3_32BIT_REGISTER IfInDiscardsCnt;
+       T3_32BIT_REGISTER IfInErrorsCnt;
+       T3_32BIT_REGISTER RcvThresholdHitCnt;
+
+       /* Another unused space. */
+       LM_UINT8 Unused2[420];
+} T3_RCV_LIST_PLACEMENT, *PT3_RCV_LIST_PLACEMENT;

 
 /******************************************************************************/
 /* Receive Data and Receive BD Initiator Control. */
 /******************************************************************************/
 
 typedef struct {
 
 /******************************************************************************/
 /* Receive Data and Receive BD Initiator Control. */
 /******************************************************************************/
 
 typedef struct {

-    /* Mode. */
-    T3_32BIT_REGISTER Mode;
-    #define RCV_DATA_BD_IN_MODE_RESET                   BIT_0
-    #define RCV_DATA_BD_IN_MODE_ENABLE                  BIT_1
-    #define RCV_DATA_BD_IN_MODE_JUMBO_BD_NEEDED         BIT_2
-    #define RCV_DATA_BD_IN_MODE_FRAME_TOO_BIG           BIT_3
-    #define RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE       BIT_4
-
-    /* Status. */
-    T3_32BIT_REGISTER Status;
-    #define RCV_DATA_BD_IN_STATUS_JUMBO_BD_NEEDED       BIT_2
-    #define RCV_DATA_BD_IN_STATUS_FRAME_TOO_BIG         BIT_3
-    #define RCV_DATA_BD_IN_STATUS_INVALID_RING_SIZE     BIT_4
-
-    /* Split frame minium size. */
-    T3_32BIT_REGISTER SplitFrameMinSize;
-
-    /* Unused space. */
-    LM_UINT8 Unused1[0x2440-0x240c];
-
-    /* Receive RCBs. */
-    T3_RCB JumboRcvRcb;
-    T3_RCB StdRcvRcb;
-    T3_RCB MiniRcvRcb;
-
-    /* Receive Data and Receive BD Ring Initiator Local NIC Receive */
-    /* BD Consumber Index. */
-    T3_32BIT_REGISTER NicJumboConIdx;
-    T3_32BIT_REGISTER NicStdConIdx;
-    T3_32BIT_REGISTER NicMiniConIdx;
-
-    /* Unused space. */
-    LM_UINT8 Unused2[4];
-
-    /* Receive Data and Receive BD Initiator Local Receive Return ProdIdx. */
-    T3_32BIT_REGISTER RcvDataBdProdIdx[16];
-
-    /* Receive Data and Receive BD Initiator Hardware Diagnostic. */
-    T3_32BIT_REGISTER HwDiag;
-
-    /* Unused space. */
-    LM_UINT8 Unused3[828];
-} T3_RCV_DATA_BD_INITIATOR, *PT3_RCV_DATA_BD_INITIATOR;
+       /* Mode. */
+       T3_32BIT_REGISTER Mode;
+#define RCV_DATA_BD_IN_MODE_RESET                   BIT_0
+#define RCV_DATA_BD_IN_MODE_ENABLE                  BIT_1
+#define RCV_DATA_BD_IN_MODE_JUMBO_BD_NEEDED         BIT_2
+#define RCV_DATA_BD_IN_MODE_FRAME_TOO_BIG           BIT_3
+#define RCV_DATA_BD_IN_MODE_INVALID_RING_SIZE       BIT_4
+
+       /* Status. */
+       T3_32BIT_REGISTER Status;
+#define RCV_DATA_BD_IN_STATUS_JUMBO_BD_NEEDED       BIT_2
+#define RCV_DATA_BD_IN_STATUS_FRAME_TOO_BIG         BIT_3
+#define RCV_DATA_BD_IN_STATUS_INVALID_RING_SIZE     BIT_4
+
+       /* Split frame minium size. */
+       T3_32BIT_REGISTER SplitFrameMinSize;
+
+       /* Unused space. */
+       LM_UINT8 Unused1[0x2440 - 0x240c];
+
+       /* Receive RCBs. */
+       T3_RCB JumboRcvRcb;
+       T3_RCB StdRcvRcb;
+       T3_RCB MiniRcvRcb;
+
+       /* Receive Data and Receive BD Ring Initiator Local NIC Receive */
+       /* BD Consumber Index. */
+       T3_32BIT_REGISTER NicJumboConIdx;
+       T3_32BIT_REGISTER NicStdConIdx;
+       T3_32BIT_REGISTER NicMiniConIdx;
+
+       /* Unused space. */
+       LM_UINT8 Unused2[4];
+
+       /* Receive Data and Receive BD Initiator Local Receive Return ProdIdx. */
+       T3_32BIT_REGISTER RcvDataBdProdIdx[16];

 
 

+       /* Receive Data and Receive BD Initiator Hardware Diagnostic. */
+       T3_32BIT_REGISTER HwDiag;
+
+       /* Unused space. */
+       LM_UINT8 Unused3[828];
+} T3_RCV_DATA_BD_INITIATOR, *PT3_RCV_DATA_BD_INITIATOR;

 
 /******************************************************************************/
 /* Receive Data Completion Control Registes. */
 /******************************************************************************/
 
 typedef struct {
 
 /******************************************************************************/
 /* Receive Data Completion Control Registes. */
 /******************************************************************************/
 
 typedef struct {

-    T3_32BIT_REGISTER Mode;
-    #define RCV_DATA_COMP_MODE_RESET                        BIT_0
-    #define RCV_DATA_COMP_MODE_ENABLE                       BIT_1
-    #define RCV_DATA_COMP_MODE_ATTN_ENABLE                  BIT_2
+       T3_32BIT_REGISTER Mode;
+#define RCV_DATA_COMP_MODE_RESET                        BIT_0
+#define RCV_DATA_COMP_MODE_ENABLE                       BIT_1
+#define RCV_DATA_COMP_MODE_ATTN_ENABLE                  BIT_2

 
 

-    /* Unused spaced. */
-    LM_UINT8 Unused[1020];
+       /* Unused spaced. */
+       LM_UINT8 Unused[1020];

 } T3_RCV_DATA_COMPLETION, *PT3_RCV_DATA_COMPLETION;
 
 } T3_RCV_DATA_COMPLETION, *PT3_RCV_DATA_COMPLETION;
 

-

 /******************************************************************************/
 /* Receive BD Initiator Control. */
 /******************************************************************************/
 
 typedef struct {
 /******************************************************************************/
 /* Receive BD Initiator Control. */
 /******************************************************************************/
 
 typedef struct {

-    T3_32BIT_REGISTER Mode;
-    #define RCV_BD_IN_MODE_RESET                            BIT_0
-    #define RCV_BD_IN_MODE_ENABLE                           BIT_1
-    #define RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE    BIT_2
+       T3_32BIT_REGISTER Mode;
+#define RCV_BD_IN_MODE_RESET                            BIT_0
+#define RCV_BD_IN_MODE_ENABLE                           BIT_1
+#define RCV_BD_IN_MODE_BD_IN_DIABLED_RCB_ATTN_ENABLE    BIT_2

 
 

-    T3_32BIT_REGISTER Status;
-    #define RCV_BD_IN_STATUS_BD_IN_DIABLED_RCB_ATTN         BIT_2
+       T3_32BIT_REGISTER Status;
+#define RCV_BD_IN_STATUS_BD_IN_DIABLED_RCB_ATTN         BIT_2

 
 

-    T3_32BIT_REGISTER NicJumboRcvProdIdx;
-    T3_32BIT_REGISTER NicStdRcvProdIdx;
-    T3_32BIT_REGISTER NicMiniRcvProdIdx;
+       T3_32BIT_REGISTER NicJumboRcvProdIdx;
+       T3_32BIT_REGISTER NicStdRcvProdIdx;
+       T3_32BIT_REGISTER NicMiniRcvProdIdx;

 
 

-    T3_32BIT_REGISTER MiniRcvThreshold;
-    T3_32BIT_REGISTER StdRcvThreshold;
-    T3_32BIT_REGISTER JumboRcvThreshold;
+       T3_32BIT_REGISTER MiniRcvThreshold;
+       T3_32BIT_REGISTER StdRcvThreshold;
+       T3_32BIT_REGISTER JumboRcvThreshold;

 
 

-    /* Unused space. */
-    LM_UINT8 Unused[992];
+       /* Unused space. */
+       LM_UINT8 Unused[992];

 } T3_RCV_BD_INITIATOR, *PT3_RCV_BD_INITIATOR;
 
 } T3_RCV_BD_INITIATOR, *PT3_RCV_BD_INITIATOR;
 

-

 /******************************************************************************/
 /* Receive BD Completion Control Registers. */
 /******************************************************************************/
 
 typedef struct {
 /******************************************************************************/
 /* Receive BD Completion Control Registers. */
 /******************************************************************************/
 
 typedef struct {

-    T3_32BIT_REGISTER Mode;
-    #define RCV_BD_COMP_MODE_RESET                          BIT_0
-    #define RCV_BD_COMP_MODE_ENABLE                         BIT_1
-    #define RCV_BD_COMP_MODE_ATTN_ENABLE                    BIT_2
+       T3_32BIT_REGISTER Mode;
+#define RCV_BD_COMP_MODE_RESET                          BIT_0
+#define RCV_BD_COMP_MODE_ENABLE                         BIT_1
+#define RCV_BD_COMP_MODE_ATTN_ENABLE                    BIT_2

 
 

-    T3_32BIT_REGISTER Status;
-    #define RCV_BD_COMP_STATUS_ERROR_ATTN                   BIT_2
+       T3_32BIT_REGISTER Status;
+#define RCV_BD_COMP_STATUS_ERROR_ATTN                   BIT_2

 
 

-    T3_32BIT_REGISTER  NicJumboRcvBdProdIdx;
-    T3_32BIT_REGISTER  NicStdRcvBdProdIdx;
-    T3_32BIT_REGISTER  NicMiniRcvBdProdIdx;
+       T3_32BIT_REGISTER NicJumboRcvBdProdIdx;
+       T3_32BIT_REGISTER NicStdRcvBdProdIdx;
+       T3_32BIT_REGISTER NicMiniRcvBdProdIdx;

 
 

-    /* Unused space. */
-    LM_UINT8 Unused[1004];
+       /* Unused space. */
+       LM_UINT8 Unused[1004];

 } T3_RCV_BD_COMPLETION, *PT3_RCV_BD_COMPLETION;
 
 } T3_RCV_BD_COMPLETION, *PT3_RCV_BD_COMPLETION;
 

-

 /******************************************************************************/
 /* Receive list selector control register. */
 /******************************************************************************/
 
 typedef struct {
 /******************************************************************************/
 /* Receive list selector control register. */
 /******************************************************************************/
 
 typedef struct {

-    T3_32BIT_REGISTER Mode;
-    #define RCV_LIST_SEL_MODE_RESET                         BIT_0
-    #define RCV_LIST_SEL_MODE_ENABLE                        BIT_1
-    #define RCV_LIST_SEL_MODE_ATTN_ENABLE                   BIT_2
+       T3_32BIT_REGISTER Mode;
+#define RCV_LIST_SEL_MODE_RESET                         BIT_0
+#define RCV_LIST_SEL_MODE_ENABLE                        BIT_1
+#define RCV_LIST_SEL_MODE_ATTN_ENABLE                   BIT_2

 
 

-    T3_32BIT_REGISTER Status;
-    #define RCV_LIST_SEL_STATUS_ERROR_ATTN                  BIT_2
+       T3_32BIT_REGISTER Status;
+#define RCV_LIST_SEL_STATUS_ERROR_ATTN                  BIT_2

 
 

-    /* Unused space. */
-    LM_UINT8 Unused[1016];
+       /* Unused space. */
+       LM_UINT8 Unused[1016];

 } T3_RCV_LIST_SELECTOR, *PT3_RCV_LIST_SELECTOR;
 
 } T3_RCV_LIST_SELECTOR, *PT3_RCV_LIST_SELECTOR;
 

-

 /******************************************************************************/
 /* Mbuf cluster free registers. */
 /******************************************************************************/
 
 typedef struct {
 /******************************************************************************/
 /* Mbuf cluster free registers. */
 /******************************************************************************/
 
 typedef struct {

-    T3_32BIT_REGISTER Mode;
+       T3_32BIT_REGISTER Mode;

 #define MBUF_CLUSTER_FREE_MODE_RESET    BIT_0
 #define MBUF_CLUSTER_FREE_MODE_ENABLE   BIT_1
 
 #define MBUF_CLUSTER_FREE_MODE_RESET    BIT_0
 #define MBUF_CLUSTER_FREE_MODE_ENABLE   BIT_1
 

-    T3_32BIT_REGISTER Status;
+       T3_32BIT_REGISTER Status;

 
 

-    /* Unused space. */
-    LM_UINT8 Unused[1016];
+       /* Unused space. */
+       LM_UINT8 Unused[1016];

 } T3_MBUF_CLUSTER_FREE, *PT3_MBUF_CLUSTER_FREE;
 
 } T3_MBUF_CLUSTER_FREE, *PT3_MBUF_CLUSTER_FREE;
 

-

 /******************************************************************************/
 /* Host coalescing control registers. */
 /******************************************************************************/
 
 typedef struct {
 /******************************************************************************/
 /* Host coalescing control registers. */
 /******************************************************************************/
 
 typedef struct {

-    /* Mode. */
-    T3_32BIT_REGISTER Mode;
-    #define HOST_COALESCE_RESET                         BIT_0
-    #define HOST_COALESCE_ENABLE                        BIT_1
-    #define HOST_COALESCE_ATTN                          BIT_2
-    #define HOST_COALESCE_NOW                           BIT_3
-    #define HOST_COALESCE_FULL_STATUS_MODE              BIT_NONE
-    #define HOST_COALESCE_64_BYTE_STATUS_MODE           BIT_7
-    #define HOST_COALESCE_32_BYTE_STATUS_MODE           BIT_8
-    #define HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT    BIT_9
-    #define HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT    BIT_10
-    #define HOST_COALESCE_NO_INT_ON_COALESCE_NOW_MODE   BIT_11
-    #define HOST_COALESCE_NO_INT_ON_FORCE_DMAD_MODE     BIT_12
+       /* Mode. */
+       T3_32BIT_REGISTER Mode;
+#define HOST_COALESCE_RESET                         BIT_0
+#define HOST_COALESCE_ENABLE                        BIT_1
+#define HOST_COALESCE_ATTN                          BIT_2
+#define HOST_COALESCE_NOW                           BIT_3
+#define HOST_COALESCE_FULL_STATUS_MODE              BIT_NONE
+#define HOST_COALESCE_64_BYTE_STATUS_MODE           BIT_7
+#define HOST_COALESCE_32_BYTE_STATUS_MODE           BIT_8
+#define HOST_COALESCE_CLEAR_TICKS_ON_RX_BD_EVENT    BIT_9
+#define HOST_COALESCE_CLEAR_TICKS_ON_TX_BD_EVENT    BIT_10
+#define HOST_COALESCE_NO_INT_ON_COALESCE_NOW_MODE   BIT_11
+#define HOST_COALESCE_NO_INT_ON_FORCE_DMAD_MODE     BIT_12

 
 

-    /* Status. */
-    T3_32BIT_REGISTER Status;
-    #define HOST_COALESCE_ERROR_ATTN                    BIT_2
+       /* Status. */
+       T3_32BIT_REGISTER Status;
+#define HOST_COALESCE_ERROR_ATTN                    BIT_2

 
 

-    /* Receive coalescing ticks. */
-    T3_32BIT_REGISTER RxCoalescingTicks;
+       /* Receive coalescing ticks. */
+       T3_32BIT_REGISTER RxCoalescingTicks;

 
 

-    /* Send coalescing ticks. */
-    T3_32BIT_REGISTER TxCoalescingTicks;
+       /* Send coalescing ticks. */
+       T3_32BIT_REGISTER TxCoalescingTicks;

 
 

-    /* Receive max coalesced frames. */
-    T3_32BIT_REGISTER RxMaxCoalescedFrames;
+       /* Receive max coalesced frames. */
+       T3_32BIT_REGISTER RxMaxCoalescedFrames;

 
 

-    /* Send max coalesced frames. */
-    T3_32BIT_REGISTER TxMaxCoalescedFrames;
+       /* Send max coalesced frames. */
+       T3_32BIT_REGISTER TxMaxCoalescedFrames;

 
 

-    /* Receive coalescing ticks during interrupt. */
-    T3_32BIT_REGISTER RxCoalescedTickDuringInt;
+       /* Receive coalescing ticks during interrupt. */
+       T3_32BIT_REGISTER RxCoalescedTickDuringInt;

 
 

-    /* Send coalescing ticks during interrupt. */
-    T3_32BIT_REGISTER TxCoalescedTickDuringInt;
+       /* Send coalescing ticks during interrupt. */
+       T3_32BIT_REGISTER TxCoalescedTickDuringInt;

 
 

-    /* Receive max coalesced frames during interrupt. */
-    T3_32BIT_REGISTER RxMaxCoalescedFramesDuringInt;
+       /* Receive max coalesced frames during interrupt. */
+       T3_32BIT_REGISTER RxMaxCoalescedFramesDuringInt;

 
 

-    /* Send max coalesced frames during interrupt. */
-    T3_32BIT_REGISTER TxMaxCoalescedFramesDuringInt;
+       /* Send max coalesced frames during interrupt. */
+       T3_32BIT_REGISTER TxMaxCoalescedFramesDuringInt;

 
 

-    /* Statistics tick. */
-    T3_32BIT_REGISTER StatsCoalescingTicks;
+       /* Statistics tick. */
+       T3_32BIT_REGISTER StatsCoalescingTicks;

 
 

-    /* Unused space. */
-    LM_UINT8 Unused2[4];
+       /* Unused space. */
+       LM_UINT8 Unused2[4];

 
 

-    /* Statistics host address. */
-    T3_64BIT_REGISTER StatsBlkHostAddr;
+       /* Statistics host address. */
+       T3_64BIT_REGISTER StatsBlkHostAddr;

 
 

-    /* Status block host address.*/
-    T3_64BIT_REGISTER StatusBlkHostAddr;
+       /* Status block host address. */
+       T3_64BIT_REGISTER StatusBlkHostAddr;

 
 

-    /* Statistics NIC address. */
-    T3_32BIT_REGISTER StatsBlkNicAddr;
+       /* Statistics NIC address. */
+       T3_32BIT_REGISTER StatsBlkNicAddr;

 
 

-    /* Statust block NIC address. */
-    T3_32BIT_REGISTER StatusBlkNicAddr;
+       /* Statust block NIC address. */
+       T3_32BIT_REGISTER StatusBlkNicAddr;

 
 

-    /* Flow attention registers. */
-    T3_32BIT_REGISTER FlowAttn;
+       /* Flow attention registers. */
+       T3_32BIT_REGISTER FlowAttn;

 
 

-    /* Unused space. */
-    LM_UINT8 Unused3[4];
+       /* Unused space. */
+       LM_UINT8 Unused3[4];

 
 

-    T3_32BIT_REGISTER NicJumboRcvBdConIdx;
-    T3_32BIT_REGISTER NicStdRcvBdConIdx;
-    T3_32BIT_REGISTER NicMiniRcvBdConIdx;
+       T3_32BIT_REGISTER NicJumboRcvBdConIdx;
+       T3_32BIT_REGISTER NicStdRcvBdConIdx;
+       T3_32BIT_REGISTER NicMiniRcvBdConIdx;

 
 

-    /* Unused space. */
-    LM_UINT8 Unused4[36];
+       /* Unused space. */
+       LM_UINT8 Unused4[36];

 
 

-    T3_32BIT_REGISTER NicRetProdIdx[16];
-    T3_32BIT_REGISTER NicSndBdConIdx[16];
+       T3_32BIT_REGISTER NicRetProdIdx[16];
+       T3_32BIT_REGISTER NicSndBdConIdx[16];

 
 

-    /* Unused space. */
-    LM_UINT8 Unused5[768];
+       /* Unused space. */
+       LM_UINT8 Unused5[768];

 } T3_HOST_COALESCING, *PT3_HOST_COALESCING;
 
 } T3_HOST_COALESCING, *PT3_HOST_COALESCING;
 

-

 /******************************************************************************/
 /* Memory arbiter registers. */
 /******************************************************************************/
 
 typedef struct {
 /******************************************************************************/
 /* Memory arbiter registers. */
 /******************************************************************************/
 
 typedef struct {

-    T3_32BIT_REGISTER Mode;
+       T3_32BIT_REGISTER Mode;

 #define T3_MEM_ARBITER_MODE_RESET       BIT_0
 #define T3_MEM_ARBITER_MODE_ENABLE      BIT_1
 
 #define T3_MEM_ARBITER_MODE_RESET       BIT_0
 #define T3_MEM_ARBITER_MODE_ENABLE      BIT_1
 

-    T3_32BIT_REGISTER Status;
+       T3_32BIT_REGISTER Status;

 
 

-    T3_32BIT_REGISTER ArbTrapAddrLow;
-    T3_32BIT_REGISTER ArbTrapAddrHigh;
+       T3_32BIT_REGISTER ArbTrapAddrLow;
+       T3_32BIT_REGISTER ArbTrapAddrHigh;

 
 

-    /* Unused space. */
-    LM_UINT8 Unused[1008];
+       /* Unused space. */
+       LM_UINT8 Unused[1008];

 } T3_MEM_ARBITER, *PT3_MEM_ARBITER;
 
 } T3_MEM_ARBITER, *PT3_MEM_ARBITER;
 

-

 /******************************************************************************/
 /* Buffer manager control register. */
 /******************************************************************************/
 
 typedef struct {
 /******************************************************************************/
 /* Buffer manager control register. */
 /******************************************************************************/
 
 typedef struct {

-    T3_32BIT_REGISTER Mode;
-    #define BUFMGR_MODE_RESET                           BIT_0
-    #define BUFMGR_MODE_ENABLE                          BIT_1
-    #define BUFMGR_MODE_ATTN_ENABLE                     BIT_2
-    #define BUFMGR_MODE_BM_TEST                         BIT_3
-    #define BUFMGR_MODE_MBUF_LOW_ATTN_ENABLE            BIT_4
-
-    T3_32BIT_REGISTER Status;
-    #define BUFMGR_STATUS_ERROR                         BIT_2
-    #define BUFMGR_STATUS_MBUF_LOW                      BIT_4
-
-    T3_32BIT_REGISTER MbufPoolAddr;
-    T3_32BIT_REGISTER MbufPoolSize;
-    T3_32BIT_REGISTER MbufReadDmaLowWaterMark;
-    T3_32BIT_REGISTER MbufMacRxLowWaterMark;
-    T3_32BIT_REGISTER MbufHighWaterMark;
-
-    T3_32BIT_REGISTER RxCpuMbufAllocReq;
-    #define BUFMGR_MBUF_ALLOC_BIT                     BIT_31
-    T3_32BIT_REGISTER RxCpuMbufAllocResp;
-    T3_32BIT_REGISTER TxCpuMbufAllocReq;
-    T3_32BIT_REGISTER TxCpuMbufAllocResp;
-
-    T3_32BIT_REGISTER DmaDescPoolAddr;
-    T3_32BIT_REGISTER DmaDescPoolSize;
-    T3_32BIT_REGISTER DmaLowWaterMark;
-    T3_32BIT_REGISTER DmaHighWaterMark;
-
-    T3_32BIT_REGISTER RxCpuDmaAllocReq;
-    T3_32BIT_REGISTER RxCpuDmaAllocResp;
-    T3_32BIT_REGISTER TxCpuDmaAllocReq;
-    T3_32BIT_REGISTER TxCpuDmaAllocResp;
-
-    T3_32BIT_REGISTER Hwdiag[3];
-
-    /* Unused space. */
-    LM_UINT8 Unused[936];
-} T3_BUFFER_MANAGER, *PT3_BUFFER_MANAGER;
+       T3_32BIT_REGISTER Mode;
+#define BUFMGR_MODE_RESET                           BIT_0
+#define BUFMGR_MODE_ENABLE                          BIT_1
+#define BUFMGR_MODE_ATTN_ENABLE                     BIT_2
+#define BUFMGR_MODE_BM_TEST                         BIT_3
+#define BUFMGR_MODE_MBUF_LOW_ATTN_ENABLE            BIT_4
+
+       T3_32BIT_REGISTER Status;
+#define BUFMGR_STATUS_ERROR                         BIT_2
+#define BUFMGR_STATUS_MBUF_LOW                      BIT_4
+
+       T3_32BIT_REGISTER MbufPoolAddr;
+       T3_32BIT_REGISTER MbufPoolSize;
+       T3_32BIT_REGISTER MbufReadDmaLowWaterMark;
+       T3_32BIT_REGISTER MbufMacRxLowWaterMark;
+       T3_32BIT_REGISTER MbufHighWaterMark;
+
+       T3_32BIT_REGISTER RxCpuMbufAllocReq;
+#define BUFMGR_MBUF_ALLOC_BIT                     BIT_31
+       T3_32BIT_REGISTER RxCpuMbufAllocResp;
+       T3_32BIT_REGISTER TxCpuMbufAllocReq;
+       T3_32BIT_REGISTER TxCpuMbufAllocResp;
+
+       T3_32BIT_REGISTER DmaDescPoolAddr;
+       T3_32BIT_REGISTER DmaDescPoolSize;
+       T3_32BIT_REGISTER DmaLowWaterMark;
+       T3_32BIT_REGISTER DmaHighWaterMark;
+
+       T3_32BIT_REGISTER RxCpuDmaAllocReq;
+       T3_32BIT_REGISTER RxCpuDmaAllocResp;
+       T3_32BIT_REGISTER TxCpuDmaAllocReq;
+       T3_32BIT_REGISTER TxCpuDmaAllocResp;
+
+       T3_32BIT_REGISTER Hwdiag[3];

 
 

+       /* Unused space. */
+       LM_UINT8 Unused[936];
+} T3_BUFFER_MANAGER, *PT3_BUFFER_MANAGER;

 
 /******************************************************************************/
 /* Read DMA control registers. */
 /******************************************************************************/
 
 typedef struct {
 
 /******************************************************************************/
 /* Read DMA control registers. */
 /******************************************************************************/
 
 typedef struct {

-    T3_32BIT_REGISTER Mode;
-    #define DMA_READ_MODE_RESET                         BIT_0
-    #define DMA_READ_MODE_ENABLE                        BIT_1
-    #define DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE      BIT_2
-    #define DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE      BIT_3
-    #define DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE      BIT_4
-    #define DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE     BIT_5
-    #define DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE      BIT_6
-    #define DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE     BIT_7
-    #define DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE     BIT_8
-    #define DMA_READ_MODE_LONG_READ_ATTN_ENABLE         BIT_9
-    #define DMA_READ_MODE_SPLIT_ENABLE                  BIT_11
-    #define DMA_READ_MODE_SPLIT_RESET                   BIT_12
-
-    T3_32BIT_REGISTER Status;
-    #define DMA_READ_STATUS_TARGET_ABORT_ATTN           BIT_2
-    #define DMA_READ_STATUS_MASTER_ABORT_ATTN           BIT_3
-    #define DMA_READ_STATUS_PARITY_ERROR_ATTN           BIT_4
-    #define DMA_READ_STATUS_ADDR_OVERFLOW_ATTN          BIT_5
-    #define DMA_READ_STATUS_FIFO_OVERRUN_ATTN           BIT_6
-    #define DMA_READ_STATUS_FIFO_UNDERRUN_ATTN          BIT_7
-    #define DMA_READ_STATUS_FIFO_OVERREAD_ATTN          BIT_8
-    #define DMA_READ_STATUS_LONG_READ_ATTN              BIT_9
-
-    /* Unused space. */
-    LM_UINT8 Unused[1016];
+       T3_32BIT_REGISTER Mode;
+#define DMA_READ_MODE_RESET                         BIT_0
+#define DMA_READ_MODE_ENABLE                        BIT_1
+#define DMA_READ_MODE_TARGET_ABORT_ATTN_ENABLE      BIT_2
+#define DMA_READ_MODE_MASTER_ABORT_ATTN_ENABLE      BIT_3
+#define DMA_READ_MODE_PARITY_ERROR_ATTN_ENABLE      BIT_4
+#define DMA_READ_MODE_ADDR_OVERFLOW_ATTN_ENABLE     BIT_5
+#define DMA_READ_MODE_FIFO_OVERRUN_ATTN_ENABLE      BIT_6
+#define DMA_READ_MODE_FIFO_UNDERRUN_ATTN_ENABLE     BIT_7
+#define DMA_READ_MODE_FIFO_OVERREAD_ATTN_ENABLE     BIT_8
+#define DMA_READ_MODE_LONG_READ_ATTN_ENABLE         BIT_9
+#define DMA_READ_MODE_SPLIT_ENABLE                  BIT_11
+#define DMA_READ_MODE_SPLIT_RESET                   BIT_12
+
+       T3_32BIT_REGISTER Status;
+#define DMA_READ_STATUS_TARGET_ABORT_ATTN           BIT_2
+#define DMA_READ_STATUS_MASTER_ABORT_ATTN           BIT_3
+#define DMA_READ_STATUS_PARITY_ERROR_ATTN           BIT_4
+#define DMA_READ_STATUS_ADDR_OVERFLOW_ATTN          BIT_5
+#define DMA_READ_STATUS_FIFO_OVERRUN_ATTN           BIT_6
+#define DMA_READ_STATUS_FIFO_UNDERRUN_ATTN          BIT_7
+#define DMA_READ_STATUS_FIFO_OVERREAD_ATTN          BIT_8
+#define DMA_READ_STATUS_LONG_READ_ATTN              BIT_9
+
+       /* Unused space. */
+       LM_UINT8 Unused[1016];

 } T3_DMA_READ, *PT3_DMA_READ;
 
 } T3_DMA_READ, *PT3_DMA_READ;
 

-typedef union T3_CPU
-{
-  struct
-  {
-    T3_32BIT_REGISTER mode;
-    #define CPU_MODE_HALT   BIT_10
-    #define CPU_MODE_RESET  BIT_0
-    T3_32BIT_REGISTER state;
-    T3_32BIT_REGISTER EventMask;
-    T3_32BIT_REGISTER reserved1[4];
-    T3_32BIT_REGISTER PC;
-    T3_32BIT_REGISTER Instruction;
-    T3_32BIT_REGISTER SpadUnderflow;
-    T3_32BIT_REGISTER WatchdogClear;
-    T3_32BIT_REGISTER WatchdogVector;
-    T3_32BIT_REGISTER WatchdogSavedPC;
-    T3_32BIT_REGISTER HardwareBp;
-    T3_32BIT_REGISTER reserved2[3];
-    T3_32BIT_REGISTER WatchdogSavedState;
-    T3_32BIT_REGISTER LastBrchAddr;
-    T3_32BIT_REGISTER SpadUnderflowSet;
-    T3_32BIT_REGISTER reserved3[(0x200-0x50)/4];
-    T3_32BIT_REGISTER Regs[32];
-    T3_32BIT_REGISTER reserved4[(0x400-0x280)/4];
-  }reg;
-}T3_CPU, *PT3_CPU;
+typedef union T3_CPU {
+       struct {
+               T3_32BIT_REGISTER mode;
+#define CPU_MODE_HALT   BIT_10
+#define CPU_MODE_RESET  BIT_0
+               T3_32BIT_REGISTER state;
+               T3_32BIT_REGISTER EventMask;
+               T3_32BIT_REGISTER reserved1[4];
+               T3_32BIT_REGISTER PC;
+               T3_32BIT_REGISTER Instruction;
+               T3_32BIT_REGISTER SpadUnderflow;
+               T3_32BIT_REGISTER WatchdogClear;
+               T3_32BIT_REGISTER WatchdogVector;
+               T3_32BIT_REGISTER WatchdogSavedPC;
+               T3_32BIT_REGISTER HardwareBp;
+               T3_32BIT_REGISTER reserved2[3];
+               T3_32BIT_REGISTER WatchdogSavedState;
+               T3_32BIT_REGISTER LastBrchAddr;
+               T3_32BIT_REGISTER SpadUnderflowSet;
+               T3_32BIT_REGISTER reserved3[(0x200 - 0x50) / 4];
+               T3_32BIT_REGISTER Regs[32];
+               T3_32BIT_REGISTER reserved4[(0x400 - 0x280) / 4];
+       } reg;
+} T3_CPU, *PT3_CPU;

 
 /******************************************************************************/
 /* Write DMA control registers. */
 /******************************************************************************/
 
 typedef struct {
 
 /******************************************************************************/
 /* Write DMA control registers. */
 /******************************************************************************/
 
 typedef struct {

-    T3_32BIT_REGISTER Mode;
-    #define DMA_WRITE_MODE_RESET                        BIT_0
-    #define DMA_WRITE_MODE_ENABLE                       BIT_1
-    #define DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE     BIT_2
-    #define DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE     BIT_3
-    #define DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE     BIT_4
-    #define DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE    BIT_5
-    #define DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE     BIT_6
-    #define DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE    BIT_7
-    #define DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE    BIT_8
-    #define DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE        BIT_9
-
-    T3_32BIT_REGISTER Status;
-    #define DMA_WRITE_STATUS_TARGET_ABORT_ATTN          BIT_2
-    #define DMA_WRITE_STATUS_MASTER_ABORT_ATTN          BIT_3
-    #define DMA_WRITE_STATUS_PARITY_ERROR_ATTN          BIT_4
-    #define DMA_WRITE_STATUS_ADDR_OVERFLOW_ATTN         BIT_5
-    #define DMA_WRITE_STATUS_FIFO_OVERRUN_ATTN          BIT_6
-    #define DMA_WRITE_STATUS_FIFO_UNDERRUN_ATTN         BIT_7
-    #define DMA_WRITE_STATUS_FIFO_OVERREAD_ATTN         BIT_8
-    #define DMA_WRITE_STATUS_LONG_READ_ATTN             BIT_9
-
-    /* Unused space. */
-    LM_UINT8 Unused[1016];
-} T3_DMA_WRITE, *PT3_DMA_WRITE;
+       T3_32BIT_REGISTER Mode;
+#define DMA_WRITE_MODE_RESET                        BIT_0
+#define DMA_WRITE_MODE_ENABLE                       BIT_1
+#define DMA_WRITE_MODE_TARGET_ABORT_ATTN_ENABLE     BIT_2
+#define DMA_WRITE_MODE_MASTER_ABORT_ATTN_ENABLE     BIT_3
+#define DMA_WRITE_MODE_PARITY_ERROR_ATTN_ENABLE     BIT_4
+#define DMA_WRITE_MODE_ADDR_OVERFLOW_ATTN_ENABLE    BIT_5
+#define DMA_WRITE_MODE_FIFO_OVERRUN_ATTN_ENABLE     BIT_6
+#define DMA_WRITE_MODE_FIFO_UNDERRUN_ATTN_ENABLE    BIT_7
+#define DMA_WRITE_MODE_FIFO_OVERREAD_ATTN_ENABLE    BIT_8
+#define DMA_WRITE_MODE_LONG_READ_ATTN_ENABLE        BIT_9
+
+       T3_32BIT_REGISTER Status;
+#define DMA_WRITE_STATUS_TARGET_ABORT_ATTN          BIT_2
+#define DMA_WRITE_STATUS_MASTER_ABORT_ATTN          BIT_3
+#define DMA_WRITE_STATUS_PARITY_ERROR_ATTN          BIT_4
+#define DMA_WRITE_STATUS_ADDR_OVERFLOW_ATTN         BIT_5
+#define DMA_WRITE_STATUS_FIFO_OVERRUN_ATTN          BIT_6
+#define DMA_WRITE_STATUS_FIFO_UNDERRUN_ATTN         BIT_7
+#define DMA_WRITE_STATUS_FIFO_OVERREAD_ATTN         BIT_8
+#define DMA_WRITE_STATUS_LONG_READ_ATTN             BIT_9

 
 

+       /* Unused space. */
+       LM_UINT8 Unused[1016];
+} T3_DMA_WRITE, *PT3_DMA_WRITE;

 
 /******************************************************************************/
 /* Mailbox registers. */
 /******************************************************************************/
 
 typedef struct {
 
 /******************************************************************************/
 /* Mailbox registers. */
 /******************************************************************************/
 
 typedef struct {

-    /* Interrupt mailbox registers. */
-    T3_64BIT_REGISTER Interrupt[4];
+       /* Interrupt mailbox registers. */
+       T3_64BIT_REGISTER Interrupt[4];

 
 

-    /* General mailbox registers. */
-    T3_64BIT_REGISTER General[8];
+       /* General mailbox registers. */
+       T3_64BIT_REGISTER General[8];

 
 

-    /* Reload statistics mailbox. */
-    T3_64BIT_REGISTER ReloadStat;
+       /* Reload statistics mailbox. */
+       T3_64BIT_REGISTER ReloadStat;

 
 

-    /* Receive BD ring producer index registers. */
-    T3_64BIT_REGISTER RcvStdProdIdx;
-    T3_64BIT_REGISTER RcvJumboProdIdx;
-    T3_64BIT_REGISTER RcvMiniProdIdx;
+       /* Receive BD ring producer index registers. */
+       T3_64BIT_REGISTER RcvStdProdIdx;
+       T3_64BIT_REGISTER RcvJumboProdIdx;
+       T3_64BIT_REGISTER RcvMiniProdIdx;

 
 

-    /* Receive return ring consumer index registers. */
-    T3_64BIT_REGISTER RcvRetConIdx[16];
+       /* Receive return ring consumer index registers. */
+       T3_64BIT_REGISTER RcvRetConIdx[16];

 
 

-    /* Send BD ring host producer index registers. */
-    T3_64BIT_REGISTER SendHostProdIdx[16];
+       /* Send BD ring host producer index registers. */
+       T3_64BIT_REGISTER SendHostProdIdx[16];

 
 

-    /* Send BD ring nic producer index registers. */
-    T3_64BIT_REGISTER SendNicProdIdx[16];
-}T3_MAILBOX, *PT3_MAILBOX;
+       /* Send BD ring nic producer index registers. */
+       T3_64BIT_REGISTER SendNicProdIdx[16];
+} T3_MAILBOX, *PT3_MAILBOX;

 
 typedef struct {
 
 typedef struct {

-    T3_MAILBOX Mailbox;
+       T3_MAILBOX Mailbox;

 
 

-    /* Priority mailbox registers. */
-    T3_32BIT_REGISTER HighPriorityEventVector;
-    T3_32BIT_REGISTER HighPriorityEventMask;
-    T3_32BIT_REGISTER LowPriorityEventVector;
-    T3_32BIT_REGISTER LowPriorityEventMask;
+       /* Priority mailbox registers. */
+       T3_32BIT_REGISTER HighPriorityEventVector;
+       T3_32BIT_REGISTER HighPriorityEventMask;
+       T3_32BIT_REGISTER LowPriorityEventVector;
+       T3_32BIT_REGISTER LowPriorityEventMask;

 
 

-    /* Unused space. */
-    LM_UINT8 Unused[496];
+       /* Unused space. */
+       LM_UINT8 Unused[496];

 } T3_GRC_MAILBOX, *PT3_GRC_MAILBOX;
 
 } T3_GRC_MAILBOX, *PT3_GRC_MAILBOX;
 

-

 /******************************************************************************/
 /* Flow through queues. */
 /******************************************************************************/
 
 typedef struct {
 /******************************************************************************/
 /* Flow through queues. */
 /******************************************************************************/
 
 typedef struct {

-    T3_32BIT_REGISTER Reset;
-
-    LM_UINT8 Unused[12];
-
-    T3_32BIT_REGISTER DmaNormalReadFtqCtrl;
-    T3_32BIT_REGISTER DmaNormalReadFtqFullCnt;
-    T3_32BIT_REGISTER DmaNormalReadFtqFifoEnqueueDequeue;
-    T3_32BIT_REGISTER DmaNormalReadFtqFifoWritePeek;
-
-    T3_32BIT_REGISTER DmaHighReadFtqCtrl;
-    T3_32BIT_REGISTER DmaHighReadFtqFullCnt;
-    T3_32BIT_REGISTER DmaHighReadFtqFifoEnqueueDequeue;
-    T3_32BIT_REGISTER DmaHighReadFtqFifoWritePeek;
-
-    T3_32BIT_REGISTER DmaCompDiscardFtqCtrl;
-    T3_32BIT_REGISTER DmaCompDiscardFtqFullCnt;
-    T3_32BIT_REGISTER DmaCompDiscardFtqFifoEnqueueDequeue;
-    T3_32BIT_REGISTER DmaCompDiscardFtqFifoWritePeek;
-
-    T3_32BIT_REGISTER SendBdCompFtqCtrl;
-    T3_32BIT_REGISTER SendBdCompFtqFullCnt;
-    T3_32BIT_REGISTER SendBdCompFtqFifoEnqueueDequeue;
-    T3_32BIT_REGISTER SendBdCompFtqFifoWritePeek;
-
-    T3_32BIT_REGISTER SendDataInitiatorFtqCtrl;
-    T3_32BIT_REGISTER SendDataInitiatorFtqFullCnt;
-    T3_32BIT_REGISTER SendDataInitiatorFtqFifoEnqueueDequeue;
-    T3_32BIT_REGISTER SendDataInitiatorFtqFifoWritePeek;
-
-    T3_32BIT_REGISTER DmaNormalWriteFtqCtrl;
-    T3_32BIT_REGISTER DmaNormalWriteFtqFullCnt;
-    T3_32BIT_REGISTER DmaNormalWriteFtqFifoEnqueueDequeue;
-    T3_32BIT_REGISTER DmaNormalWriteFtqFifoWritePeek;
-
-    T3_32BIT_REGISTER DmaHighWriteFtqCtrl;
-    T3_32BIT_REGISTER DmaHighWriteFtqFullCnt;
-    T3_32BIT_REGISTER DmaHighWriteFtqFifoEnqueueDequeue;
-    T3_32BIT_REGISTER DmaHighWriteFtqFifoWritePeek;
-
-    T3_32BIT_REGISTER SwType1FtqCtrl;
-    T3_32BIT_REGISTER SwType1FtqFullCnt;
-    T3_32BIT_REGISTER SwType1FtqFifoEnqueueDequeue;
-    T3_32BIT_REGISTER SwType1FtqFifoWritePeek;
-
-    T3_32BIT_REGISTER SendDataCompFtqCtrl;
-    T3_32BIT_REGISTER SendDataCompFtqFullCnt;
-    T3_32BIT_REGISTER SendDataCompFtqFifoEnqueueDequeue;
-    T3_32BIT_REGISTER SendDataCompFtqFifoWritePeek;
-
-    T3_32BIT_REGISTER HostCoalesceFtqCtrl;
-    T3_32BIT_REGISTER HostCoalesceFtqFullCnt;
-    T3_32BIT_REGISTER HostCoalesceFtqFifoEnqueueDequeue;
-    T3_32BIT_REGISTER HostCoalesceFtqFifoWritePeek;
-
-    T3_32BIT_REGISTER MacTxFtqCtrl;
-    T3_32BIT_REGISTER MacTxFtqFullCnt;
-    T3_32BIT_REGISTER MacTxFtqFifoEnqueueDequeue;
-    T3_32BIT_REGISTER MacTxFtqFifoWritePeek;
-
-    T3_32BIT_REGISTER MbufClustFreeFtqCtrl;
-    T3_32BIT_REGISTER MbufClustFreeFtqFullCnt;
-    T3_32BIT_REGISTER MbufClustFreeFtqFifoEnqueueDequeue;
-    T3_32BIT_REGISTER MbufClustFreeFtqFifoWritePeek;
-
-    T3_32BIT_REGISTER RcvBdCompFtqCtrl;
-    T3_32BIT_REGISTER RcvBdCompFtqFullCnt;
-    T3_32BIT_REGISTER RcvBdCompFtqFifoEnqueueDequeue;
-    T3_32BIT_REGISTER RcvBdCompFtqFifoWritePeek;
-
-    T3_32BIT_REGISTER RcvListPlmtFtqCtrl;
-    T3_32BIT_REGISTER RcvListPlmtFtqFullCnt;
-    T3_32BIT_REGISTER RcvListPlmtFtqFifoEnqueueDequeue;
-    T3_32BIT_REGISTER RcvListPlmtFtqFifoWritePeek;
-
-    T3_32BIT_REGISTER RcvDataBdInitiatorFtqCtrl;
-    T3_32BIT_REGISTER RcvDataBdInitiatorFtqFullCnt;
-    T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoEnqueueDequeue;
-    T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoWritePeek;
-
-    T3_32BIT_REGISTER RcvDataCompFtqCtrl;
-    T3_32BIT_REGISTER RcvDataCompFtqFullCnt;
-    T3_32BIT_REGISTER RcvDataCompFtqFifoEnqueueDequeue;
-    T3_32BIT_REGISTER RcvDataCompFtqFifoWritePeek;
-
-    T3_32BIT_REGISTER SwType2FtqCtrl;
-    T3_32BIT_REGISTER SwType2FtqFullCnt;
-    T3_32BIT_REGISTER SwType2FtqFifoEnqueueDequeue;
-    T3_32BIT_REGISTER SwType2FtqFifoWritePeek;
-
-    /* Unused space. */
-    LM_UINT8 Unused2[736];
-} T3_FTQ, *PT3_FTQ;
+       T3_32BIT_REGISTER Reset;
+
+       LM_UINT8 Unused[12];
+
+       T3_32BIT_REGISTER DmaNormalReadFtqCtrl;
+       T3_32BIT_REGISTER DmaNormalReadFtqFullCnt;
+       T3_32BIT_REGISTER DmaNormalReadFtqFifoEnqueueDequeue;
+       T3_32BIT_REGISTER DmaNormalReadFtqFifoWritePeek;
+
+       T3_32BIT_REGISTER DmaHighReadFtqCtrl;
+       T3_32BIT_REGISTER DmaHighReadFtqFullCnt;
+       T3_32BIT_REGISTER DmaHighReadFtqFifoEnqueueDequeue;
+       T3_32BIT_REGISTER DmaHighReadFtqFifoWritePeek;
+
+       T3_32BIT_REGISTER DmaCompDiscardFtqCtrl;
+       T3_32BIT_REGISTER DmaCompDiscardFtqFullCnt;
+       T3_32BIT_REGISTER DmaCompDiscardFtqFifoEnqueueDequeue;
+       T3_32BIT_REGISTER DmaCompDiscardFtqFifoWritePeek;
+
+       T3_32BIT_REGISTER SendBdCompFtqCtrl;
+       T3_32BIT_REGISTER SendBdCompFtqFullCnt;
+       T3_32BIT_REGISTER SendBdCompFtqFifoEnqueueDequeue;
+       T3_32BIT_REGISTER SendBdCompFtqFifoWritePeek;
+
+       T3_32BIT_REGISTER SendDataInitiatorFtqCtrl;
+       T3_32BIT_REGISTER SendDataInitiatorFtqFullCnt;
+       T3_32BIT_REGISTER SendDataInitiatorFtqFifoEnqueueDequeue;
+       T3_32BIT_REGISTER SendDataInitiatorFtqFifoWritePeek;
+
+       T3_32BIT_REGISTER DmaNormalWriteFtqCtrl;
+       T3_32BIT_REGISTER DmaNormalWriteFtqFullCnt;
+       T3_32BIT_REGISTER DmaNormalWriteFtqFifoEnqueueDequeue;
+       T3_32BIT_REGISTER DmaNormalWriteFtqFifoWritePeek;
+
+       T3_32BIT_REGISTER DmaHighWriteFtqCtrl;
+       T3_32BIT_REGISTER DmaHighWriteFtqFullCnt;
+       T3_32BIT_REGISTER DmaHighWriteFtqFifoEnqueueDequeue;
+       T3_32BIT_REGISTER DmaHighWriteFtqFifoWritePeek;
+
+       T3_32BIT_REGISTER SwType1FtqCtrl;
+       T3_32BIT_REGISTER SwType1FtqFullCnt;
+       T3_32BIT_REGISTER SwType1FtqFifoEnqueueDequeue;
+       T3_32BIT_REGISTER SwType1FtqFifoWritePeek;
+
+       T3_32BIT_REGISTER SendDataCompFtqCtrl;
+       T3_32BIT_REGISTER SendDataCompFtqFullCnt;
+       T3_32BIT_REGISTER SendDataCompFtqFifoEnqueueDequeue;
+       T3_32BIT_REGISTER SendDataCompFtqFifoWritePeek;
+
+       T3_32BIT_REGISTER HostCoalesceFtqCtrl;
+       T3_32BIT_REGISTER HostCoalesceFtqFullCnt;
+       T3_32BIT_REGISTER HostCoalesceFtqFifoEnqueueDequeue;
+       T3_32BIT_REGISTER HostCoalesceFtqFifoWritePeek;
+
+       T3_32BIT_REGISTER MacTxFtqCtrl;
+       T3_32BIT_REGISTER MacTxFtqFullCnt;
+       T3_32BIT_REGISTER MacTxFtqFifoEnqueueDequeue;
+       T3_32BIT_REGISTER MacTxFtqFifoWritePeek;
+
+       T3_32BIT_REGISTER MbufClustFreeFtqCtrl;
+       T3_32BIT_REGISTER MbufClustFreeFtqFullCnt;
+       T3_32BIT_REGISTER MbufClustFreeFtqFifoEnqueueDequeue;
+       T3_32BIT_REGISTER MbufClustFreeFtqFifoWritePeek;
+
+       T3_32BIT_REGISTER RcvBdCompFtqCtrl;
+       T3_32BIT_REGISTER RcvBdCompFtqFullCnt;
+       T3_32BIT_REGISTER RcvBdCompFtqFifoEnqueueDequeue;
+       T3_32BIT_REGISTER RcvBdCompFtqFifoWritePeek;
+
+       T3_32BIT_REGISTER RcvListPlmtFtqCtrl;
+       T3_32BIT_REGISTER RcvListPlmtFtqFullCnt;
+       T3_32BIT_REGISTER RcvListPlmtFtqFifoEnqueueDequeue;
+       T3_32BIT_REGISTER RcvListPlmtFtqFifoWritePeek;
+
+       T3_32BIT_REGISTER RcvDataBdInitiatorFtqCtrl;
+       T3_32BIT_REGISTER RcvDataBdInitiatorFtqFullCnt;
+       T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoEnqueueDequeue;
+       T3_32BIT_REGISTER RcvDataBdInitiatorFtqFifoWritePeek;
+
+       T3_32BIT_REGISTER RcvDataCompFtqCtrl;
+       T3_32BIT_REGISTER RcvDataCompFtqFullCnt;
+       T3_32BIT_REGISTER RcvDataCompFtqFifoEnqueueDequeue;
+       T3_32BIT_REGISTER RcvDataCompFtqFifoWritePeek;
+
+       T3_32BIT_REGISTER SwType2FtqCtrl;
+       T3_32BIT_REGISTER SwType2FtqFullCnt;
+       T3_32BIT_REGISTER SwType2FtqFifoEnqueueDequeue;
+       T3_32BIT_REGISTER SwType2FtqFifoWritePeek;

 
 

+       /* Unused space. */
+       LM_UINT8 Unused2[736];
+} T3_FTQ, *PT3_FTQ;

 
 /******************************************************************************/
 /* Message signaled interrupt registers. */
 /******************************************************************************/
 
 typedef struct {
 
 /******************************************************************************/
 /* Message signaled interrupt registers. */
 /******************************************************************************/
 
 typedef struct {

-    T3_32BIT_REGISTER Mode;
+       T3_32BIT_REGISTER Mode;

 #define MSI_MODE_RESET       BIT_0
 #define MSI_MODE_ENABLE      BIT_1
 #define MSI_MODE_RESET       BIT_0
 #define MSI_MODE_ENABLE      BIT_1

-    T3_32BIT_REGISTER Status;
+       T3_32BIT_REGISTER Status;

 
 

-    T3_32BIT_REGISTER MsiFifoAccess;
+       T3_32BIT_REGISTER MsiFifoAccess;

 
 

-    /* Unused space. */
-    LM_UINT8 Unused[1012];
+       /* Unused space. */
+       LM_UINT8 Unused[1012];

 } T3_MSG_SIGNALED_INT, *PT3_MSG_SIGNALED_INT;
 
 } T3_MSG_SIGNALED_INT, *PT3_MSG_SIGNALED_INT;
 

-

 /******************************************************************************/
 /* DMA Completion registes. */
 /******************************************************************************/
 
 typedef struct {
 /******************************************************************************/
 /* DMA Completion registes. */
 /******************************************************************************/
 
 typedef struct {

-    T3_32BIT_REGISTER Mode;
-    #define DMA_COMP_MODE_RESET                         BIT_0
-    #define DMA_COMP_MODE_ENABLE                        BIT_1
+       T3_32BIT_REGISTER Mode;
+#define DMA_COMP_MODE_RESET                         BIT_0
+#define DMA_COMP_MODE_ENABLE                        BIT_1

 
 

-    /* Unused space. */
-    LM_UINT8 Unused[1020];
+       /* Unused space. */
+       LM_UINT8 Unused[1020];

 } T3_DMA_COMPLETION, *PT3_DMA_COMPLETION;
 
 } T3_DMA_COMPLETION, *PT3_DMA_COMPLETION;
 

-

 /******************************************************************************/
 /* GRC registers. */
 /******************************************************************************/
 
 typedef struct {
 /******************************************************************************/
 /* GRC registers. */
 /******************************************************************************/
 
 typedef struct {

-    /* Mode control register. */
-    T3_32BIT_REGISTER Mode;
-    #define GRC_MODE_UPDATE_ON_COALESCING               BIT_0
-    #define GRC_MODE_BYTE_SWAP_NON_FRAME_DATA           BIT_1
-    #define GRC_MODE_WORD_SWAP_NON_FRAME_DATA           BIT_2
-    #define GRC_MODE_BYTE_SWAP_DATA                     BIT_4
-    #define GRC_MODE_WORD_SWAP_DATA                     BIT_5
-    #define GRC_MODE_SPLIT_HEADER_MODE                  BIT_8
-    #define GRC_MODE_NO_FRAME_CRACKING                  BIT_9
-    #define GRC_MODE_INCLUDE_CRC                        BIT_10
-    #define GRC_MODE_ALLOW_BAD_FRAMES                   BIT_11
-    #define GRC_MODE_NO_INTERRUPT_ON_SENDS              BIT_13
-    #define GRC_MODE_NO_INTERRUPT_ON_RECEIVE            BIT_14
-    #define GRC_MODE_FORCE_32BIT_PCI_BUS_MODE           BIT_15
-    #define GRC_MODE_HOST_STACK_UP                      BIT_16
-    #define GRC_MODE_HOST_SEND_BDS                      BIT_17
-    #define GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM         BIT_20
-    #define GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM         BIT_23
-    #define GRC_MODE_INT_ON_TX_CPU_ATTN                 BIT_24
-    #define GRC_MODE_INT_ON_RX_CPU_ATTN                 BIT_25
-    #define GRC_MODE_INT_ON_MAC_ATTN                    BIT_26
-    #define GRC_MODE_INT_ON_DMA_ATTN                    BIT_27
-    #define GRC_MODE_INT_ON_FLOW_ATTN                   BIT_28
-    #define GRC_MODE_4X_NIC_BASED_SEND_RINGS            BIT_29
-    #define GRC_MODE_MULTICAST_FRAME_ENABLE             BIT_30
-
-    /* Misc configuration register. */
-    T3_32BIT_REGISTER MiscCfg;
-    #define GRC_MISC_CFG_CORE_CLOCK_RESET               BIT_0
-    #define GRC_MISC_PRESCALAR_TIMER_MASK               0xfe
-    #define GRC_MISC_BD_ID_MASK                         0x0001e000
-    #define GRC_MISC_BD_ID_5700                         0x0001e000
-    #define GRC_MISC_BD_ID_5701                         0x00000000
-    #define GRC_MISC_BD_ID_5703                         0x00000000
-    #define GRC_MISC_BD_ID_5703S                        0x00002000
-    #define GRC_MISC_BD_ID_5702FE                       0x00004000
-    #define GRC_MISC_BD_ID_5704                         0x00000000
-    #define GRC_MISC_BD_ID_5704CIOBE                    0x00004000
-
-    /* Miscellaneous local control register. */
-    T3_32BIT_REGISTER LocalCtrl;
-    #define GRC_MISC_LOCAL_CTRL_INT_ACTIVE              BIT_0
-    #define GRC_MISC_LOCAL_CTRL_CLEAR_INT               BIT_1
-    #define GRC_MISC_LOCAL_CTRL_SET_INT                 BIT_2
-    #define GRC_MISC_LOCAL_CTRL_INT_ON_ATTN             BIT_3
-    #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT0             BIT_8
-    #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT1             BIT_9
-    #define GRC_MISC_LOCAL_CTRL_GPIO_INPUT2             BIT_10
-    #define GRC_MISC_LOCAL_CTRL_GPIO_OE0                BIT_11
-    #define GRC_MISC_LOCAL_CTRL_GPIO_OE1                BIT_12
-    #define GRC_MISC_LOCAL_CTRL_GPIO_OE2                BIT_13
-    #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0            BIT_14
-    #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1            BIT_15
-    #define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2            BIT_16
-    #define GRC_MISC_LOCAL_CTRL_ENABLE_EXT_MEMORY       BIT_17
-    #define GRC_MISC_LOCAL_CTRL_BANK_SELECT             BIT_21
-    #define GRC_MISC_LOCAL_CTRL_SSRAM_TYPE              BIT_22
-
-    #define GRC_MISC_MEMSIZE_256K     0
-    #define GRC_MISC_MEMSIZE_512K     (1 << 18)
-    #define GRC_MISC_MEMSIZE_1024K    (2 << 18)
-    #define GRC_MISC_MEMSIZE_2048K    (3 << 18)
-    #define GRC_MISC_MEMSIZE_4096K    (4 << 18)
-    #define GRC_MISC_MEMSIZE_8192K    (5 << 18)
-    #define GRC_MISC_MEMSIZE_16M      (6 << 18)
-    #define GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM            BIT_24
-
-
-    T3_32BIT_REGISTER Timer;
-
-    T3_32BIT_REGISTER RxCpuEvent;
-    T3_32BIT_REGISTER RxTimerRef;
-    T3_32BIT_REGISTER RxCpuSemaphore;
-    T3_32BIT_REGISTER RemoteRxCpuAttn;
-
-    T3_32BIT_REGISTER TxCpuEvent;
-    T3_32BIT_REGISTER TxTimerRef;
-    T3_32BIT_REGISTER TxCpuSemaphore;
-    T3_32BIT_REGISTER RemoteTxCpuAttn;
-
-    T3_64BIT_REGISTER MemoryPowerUp;
-
-    T3_32BIT_REGISTER EepromAddr;
-    #define SEEPROM_ADDR_WRITE       0
-    #define SEEPROM_ADDR_READ        (1 << 31)
-    #define SEEPROM_ADDR_RW_MASK     0x80000000
-    #define SEEPROM_ADDR_COMPLETE    (1 << 30)
-    #define SEEPROM_ADDR_FSM_RESET   (1 << 29)
-    #define SEEPROM_ADDR_DEV_ID(x)   (x << 26)
-    #define SEEPROM_ADDR_DEV_ID_MASK 0x1c000000
-    #define SEEPROM_ADDR_START       (1 << 25)
-    #define SEEPROM_ADDR_CLK_PERD(x) (x << 16)
-    #define SEEPROM_ADDR_ADDRESS(x)  (x & 0xfffc)
-    #define SEEPROM_ADDR_ADDRESS_MASK 0x0000ffff
-
-    #define SEEPROM_CLOCK_PERIOD        60
-    #define SEEPROM_CHIP_SIZE           (64 * 1024)
-
-    T3_32BIT_REGISTER EepromData;
-    T3_32BIT_REGISTER EepromCtrl;
-
-    T3_32BIT_REGISTER MdiCtrl;
-    T3_32BIT_REGISTER SepromDelay;
-
-    /* Unused space. */
-    LM_UINT8 Unused[948];
-} T3_GRC, *PT3_GRC;
+       /* Mode control register. */
+       T3_32BIT_REGISTER Mode;
+#define GRC_MODE_UPDATE_ON_COALESCING               BIT_0
+#define GRC_MODE_BYTE_SWAP_NON_FRAME_DATA           BIT_1
+#define GRC_MODE_WORD_SWAP_NON_FRAME_DATA           BIT_2
+#define GRC_MODE_BYTE_SWAP_DATA                     BIT_4
+#define GRC_MODE_WORD_SWAP_DATA                     BIT_5
+#define GRC_MODE_SPLIT_HEADER_MODE                  BIT_8
+#define GRC_MODE_NO_FRAME_CRACKING                  BIT_9
+#define GRC_MODE_INCLUDE_CRC                        BIT_10
+#define GRC_MODE_ALLOW_BAD_FRAMES                   BIT_11
+#define GRC_MODE_NO_INTERRUPT_ON_SENDS              BIT_13
+#define GRC_MODE_NO_INTERRUPT_ON_RECEIVE            BIT_14
+#define GRC_MODE_FORCE_32BIT_PCI_BUS_MODE           BIT_15
+#define GRC_MODE_HOST_STACK_UP                      BIT_16
+#define GRC_MODE_HOST_SEND_BDS                      BIT_17
+#define GRC_MODE_TX_NO_PSEUDO_HEADER_CHKSUM         BIT_20
+#define GRC_MODE_RX_NO_PSEUDO_HEADER_CHKSUM         BIT_23
+#define GRC_MODE_INT_ON_TX_CPU_ATTN                 BIT_24
+#define GRC_MODE_INT_ON_RX_CPU_ATTN                 BIT_25
+#define GRC_MODE_INT_ON_MAC_ATTN                    BIT_26
+#define GRC_MODE_INT_ON_DMA_ATTN                    BIT_27
+#define GRC_MODE_INT_ON_FLOW_ATTN                   BIT_28
+#define GRC_MODE_4X_NIC_BASED_SEND_RINGS            BIT_29
+#define GRC_MODE_MULTICAST_FRAME_ENABLE             BIT_30
+
+       /* Misc configuration register. */
+       T3_32BIT_REGISTER MiscCfg;
+#define GRC_MISC_CFG_CORE_CLOCK_RESET               BIT_0
+#define GRC_MISC_PRESCALAR_TIMER_MASK               0xfe
+#define GRC_MISC_BD_ID_MASK                         0x0001e000
+#define GRC_MISC_BD_ID_5700                         0x0001e000
+#define GRC_MISC_BD_ID_5701                         0x00000000
+#define GRC_MISC_BD_ID_5703                         0x00000000
+#define GRC_MISC_BD_ID_5703S                        0x00002000
+#define GRC_MISC_BD_ID_5702FE                       0x00004000
+#define GRC_MISC_BD_ID_5704                         0x00000000
+#define GRC_MISC_BD_ID_5704CIOBE                    0x00004000
+
+       /* Miscellaneous local control register. */
+       T3_32BIT_REGISTER LocalCtrl;
+#define GRC_MISC_LOCAL_CTRL_INT_ACTIVE              BIT_0
+#define GRC_MISC_LOCAL_CTRL_CLEAR_INT               BIT_1
+#define GRC_MISC_LOCAL_CTRL_SET_INT                 BIT_2
+#define GRC_MISC_LOCAL_CTRL_INT_ON_ATTN             BIT_3
+#define GRC_MISC_LOCAL_CTRL_GPIO_INPUT0             BIT_8
+#define GRC_MISC_LOCAL_CTRL_GPIO_INPUT1             BIT_9
+#define GRC_MISC_LOCAL_CTRL_GPIO_INPUT2             BIT_10
+#define GRC_MISC_LOCAL_CTRL_GPIO_OE0                BIT_11
+#define GRC_MISC_LOCAL_CTRL_GPIO_OE1                BIT_12
+#define GRC_MISC_LOCAL_CTRL_GPIO_OE2                BIT_13
+#define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT0            BIT_14
+#define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT1            BIT_15
+#define GRC_MISC_LOCAL_CTRL_GPIO_OUTPUT2            BIT_16
+#define GRC_MISC_LOCAL_CTRL_ENABLE_EXT_MEMORY       BIT_17
+#define GRC_MISC_LOCAL_CTRL_BANK_SELECT             BIT_21
+#define GRC_MISC_LOCAL_CTRL_SSRAM_TYPE              BIT_22
+
+#define GRC_MISC_MEMSIZE_256K     0
+#define GRC_MISC_MEMSIZE_512K     (1 << 18)
+#define GRC_MISC_MEMSIZE_1024K    (2 << 18)
+#define GRC_MISC_MEMSIZE_2048K    (3 << 18)
+#define GRC_MISC_MEMSIZE_4096K    (4 << 18)
+#define GRC_MISC_MEMSIZE_8192K    (5 << 18)
+#define GRC_MISC_MEMSIZE_16M      (6 << 18)
+#define GRC_MISC_LOCAL_CTRL_AUTO_SEEPROM            BIT_24
+
+       T3_32BIT_REGISTER Timer;
+
+       T3_32BIT_REGISTER RxCpuEvent;
+       T3_32BIT_REGISTER RxTimerRef;
+       T3_32BIT_REGISTER RxCpuSemaphore;
+       T3_32BIT_REGISTER RemoteRxCpuAttn;
+
+       T3_32BIT_REGISTER TxCpuEvent;
+       T3_32BIT_REGISTER TxTimerRef;
+       T3_32BIT_REGISTER TxCpuSemaphore;
+       T3_32BIT_REGISTER RemoteTxCpuAttn;
+
+       T3_64BIT_REGISTER MemoryPowerUp;
+
+       T3_32BIT_REGISTER EepromAddr;
+#define SEEPROM_ADDR_WRITE       0
+#define SEEPROM_ADDR_READ        (1 << 31)
+#define SEEPROM_ADDR_RW_MASK     0x80000000
+#define SEEPROM_ADDR_COMPLETE    (1 << 30)
+#define SEEPROM_ADDR_FSM_RESET   (1 << 29)
+#define SEEPROM_ADDR_DEV_ID(x)   (x << 26)
+#define SEEPROM_ADDR_DEV_ID_MASK 0x1c000000
+#define SEEPROM_ADDR_START       (1 << 25)
+#define SEEPROM_ADDR_CLK_PERD(x) (x << 16)
+#define SEEPROM_ADDR_ADDRESS(x)  (x & 0xfffc)
+#define SEEPROM_ADDR_ADDRESS_MASK 0x0000ffff
+
+#define SEEPROM_CLOCK_PERIOD        60
+#define SEEPROM_CHIP_SIZE           (64 * 1024)
+
+       T3_32BIT_REGISTER EepromData;
+       T3_32BIT_REGISTER EepromCtrl;
+
+       T3_32BIT_REGISTER MdiCtrl;
+       T3_32BIT_REGISTER SepromDelay;

 
 

+       /* Unused space. */
+       LM_UINT8 Unused[948];
+} T3_GRC, *PT3_GRC;

 
 /******************************************************************************/
 /* NVRAM control registers. */
 /******************************************************************************/
 
 
 /******************************************************************************/
 /* NVRAM control registers. */
 /******************************************************************************/
 

-typedef struct
-{
-    T3_32BIT_REGISTER Cmd;
-    #define NVRAM_CMD_RESET                             BIT_0
-    #define NVRAM_CMD_DONE                              BIT_3
-    #define NVRAM_CMD_DO_IT                             BIT_4
-    #define NVRAM_CMD_WR                                BIT_5
-    #define NVRAM_CMD_RD                                BIT_NONE
-    #define NVRAM_CMD_ERASE                             BIT_6
-    #define NVRAM_CMD_FIRST                             BIT_7
-    #define NVRAM_CMD_LAST                              BIT_8
-
-    T3_32BIT_REGISTER Status;
-    T3_32BIT_REGISTER WriteData;
-
-    T3_32BIT_REGISTER Addr;
-    #define NVRAM_ADDRESS_MASK                          0xffffff
-
-    T3_32BIT_REGISTER ReadData;
-
-    /* Flash config 1 register. */
-    T3_32BIT_REGISTER Config1;
-    #define FLASH_INTERFACE_ENABLE                      BIT_0
-    #define FLASH_SSRAM_BUFFERRED_MODE                  BIT_1
-    #define FLASH_PASS_THRU_MODE                        BIT_2
-    #define FLASH_BIT_BANG_MODE                         BIT_3
-    #define FLASH_COMPAT_BYPASS                         BIT_31
-
-    /* Buffered flash (Atmel: AT45DB011B) specific information */
-    #define BUFFERED_FLASH_PAGE_POS         9
-    #define BUFFERED_FLASH_BYTE_ADDR_MASK   ((1<<BUFFERED_FLASH_PAGE_POS) - 1)
-    #define BUFFERED_FLASH_PAGE_SIZE        264
-    #define BUFFERED_FLASH_PHY_PAGE_SIZE    512
-
-    T3_32BIT_REGISTER Config2;
-    T3_32BIT_REGISTER Config3;
-    T3_32BIT_REGISTER SwArb;
-    #define SW_ARB_REQ_SET0                             BIT_0
-    #define SW_ARB_REQ_SET1                             BIT_1
-    #define SW_ARB_REQ_SET2                             BIT_2
-    #define SW_ARB_REQ_SET3                             BIT_3
-    #define SW_ARB_REQ_CLR0                             BIT_4
-    #define SW_ARB_REQ_CLR1                             BIT_5
-    #define SW_ARB_REQ_CLR2                             BIT_6
-    #define SW_ARB_REQ_CLR3                             BIT_7
-    #define SW_ARB_GNT0                                 BIT_8
-    #define SW_ARB_GNT1                                 BIT_9
-    #define SW_ARB_GNT2                                 BIT_10
-    #define SW_ARB_GNT3                                 BIT_11
-    #define SW_ARB_REQ0                                 BIT_12
-    #define SW_ARB_REQ1                                 BIT_13
-    #define SW_ARB_REQ2                                 BIT_14
-    #define SW_ARB_REQ3                                 BIT_15
-
-    /* Unused space. */
-    LM_UINT8 Unused[988];
-} T3_NVRAM, *PT3_NVRAM;
+typedef struct {
+       T3_32BIT_REGISTER Cmd;
+#define NVRAM_CMD_RESET                             BIT_0
+#define NVRAM_CMD_DONE                              BIT_3
+#define NVRAM_CMD_DO_IT                             BIT_4
+#define NVRAM_CMD_WR                                BIT_5
+#define NVRAM_CMD_RD                                BIT_NONE
+#define NVRAM_CMD_ERASE                             BIT_6
+#define NVRAM_CMD_FIRST                             BIT_7
+#define NVRAM_CMD_LAST                              BIT_8
+
+       T3_32BIT_REGISTER Status;
+       T3_32BIT_REGISTER WriteData;
+
+       T3_32BIT_REGISTER Addr;
+#define NVRAM_ADDRESS_MASK                          0xffffff
+
+       T3_32BIT_REGISTER ReadData;
+
+       /* Flash config 1 register. */
+       T3_32BIT_REGISTER Config1;
+#define FLASH_INTERFACE_ENABLE                      BIT_0
+#define FLASH_SSRAM_BUFFERRED_MODE                  BIT_1
+#define FLASH_PASS_THRU_MODE                        BIT_2
+#define FLASH_BIT_BANG_MODE                         BIT_3
+#define FLASH_COMPAT_BYPASS                         BIT_31
+
+       /* Buffered flash (Atmel: AT45DB011B) specific information */
+#define BUFFERED_FLASH_PAGE_POS         9
+#define BUFFERED_FLASH_BYTE_ADDR_MASK   ((1<<BUFFERED_FLASH_PAGE_POS) - 1)
+#define BUFFERED_FLASH_PAGE_SIZE        264
+#define BUFFERED_FLASH_PHY_PAGE_SIZE    512
+
+       T3_32BIT_REGISTER Config2;
+       T3_32BIT_REGISTER Config3;
+       T3_32BIT_REGISTER SwArb;
+#define SW_ARB_REQ_SET0                             BIT_0
+#define SW_ARB_REQ_SET1                             BIT_1
+#define SW_ARB_REQ_SET2                             BIT_2
+#define SW_ARB_REQ_SET3                             BIT_3
+#define SW_ARB_REQ_CLR0                             BIT_4
+#define SW_ARB_REQ_CLR1                             BIT_5
+#define SW_ARB_REQ_CLR2                             BIT_6
+#define SW_ARB_REQ_CLR3                             BIT_7
+#define SW_ARB_GNT0                                 BIT_8
+#define SW_ARB_GNT1                                 BIT_9
+#define SW_ARB_GNT2                                 BIT_10
+#define SW_ARB_GNT3                                 BIT_11
+#define SW_ARB_REQ0                                 BIT_12
+#define SW_ARB_REQ1                                 BIT_13
+#define SW_ARB_REQ2                                 BIT_14
+#define SW_ARB_REQ3                                 BIT_15

 
 

+       /* Unused space. */
+       LM_UINT8 Unused[988];
+} T3_NVRAM, *PT3_NVRAM;

 
 /******************************************************************************/
 /* NIC's internal memory. */
 /******************************************************************************/
 
 typedef struct {
 
 /******************************************************************************/
 /* NIC's internal memory. */
 /******************************************************************************/
 
 typedef struct {

-    /* Page zero for the internal CPUs. */
-    LM_UINT8 PageZero[0x100];               /* 0x0000 */
+       /* Page zero for the internal CPUs. */
+       LM_UINT8 PageZero[0x100];       /* 0x0000 */

 
 

-    /* Send RCBs. */
-    T3_RCB SendRcb[16];                     /* 0x0100 */
+       /* Send RCBs. */
+       T3_RCB SendRcb[16];     /* 0x0100 */

 
 

-    /* Receive Return RCBs. */
-    T3_RCB RcvRetRcb[16];                   /* 0x0200 */
+       /* Receive Return RCBs. */
+       T3_RCB RcvRetRcb[16];   /* 0x0200 */

 
 

-    /* Statistics block. */
-    T3_STATS_BLOCK StatsBlk;                /* 0x0300 */
+       /* Statistics block. */
+       T3_STATS_BLOCK StatsBlk;        /* 0x0300 */

 
 

-    /* Status block. */
-    T3_STATUS_BLOCK StatusBlk;              /* 0x0b00 */
+       /* Status block. */
+       T3_STATUS_BLOCK StatusBlk;      /* 0x0b00 */

 
 

-    /* Reserved for software. */
-    LM_UINT8 Reserved[1200];                /* 0x0b50 */
+       /* Reserved for software. */
+       LM_UINT8 Reserved[1200];        /* 0x0b50 */

 
 

-    /* Unmapped region. */
-    LM_UINT8 Unmapped[4096];                /* 0x1000 */
+       /* Unmapped region. */
+       LM_UINT8 Unmapped[4096];        /* 0x1000 */

 
 

-    /* DMA descriptors. */
-    LM_UINT8 DmaDesc[8192];                 /* 0x2000 */
+       /* DMA descriptors. */
+       LM_UINT8 DmaDesc[8192]; /* 0x2000 */

 
 

-    /* Buffer descriptors. */
-    LM_UINT8 BufferDesc[16384];             /* 0x4000 */
+       /* Buffer descriptors. */
+       LM_UINT8 BufferDesc[16384];     /* 0x4000 */

 } T3_FIRST_32K_SRAM, *PT3_FIRST_32K_SRAM;
 
 } T3_FIRST_32K_SRAM, *PT3_FIRST_32K_SRAM;
 

-

 /******************************************************************************/
 /* Memory layout. */
 /******************************************************************************/
 
 typedef struct {
 /******************************************************************************/
 /* Memory layout. */
 /******************************************************************************/
 
 typedef struct {

-    /* PCI configuration registers. */
-    T3_PCI_CONFIGURATION PciCfg;
-
-    /* Unused. */
-    LM_UINT8 Unused1[0x100];                            /* 0x0100 */
+       /* PCI configuration registers. */
+       T3_PCI_CONFIGURATION PciCfg;

 
 

-    /* Mailbox . */
-    T3_MAILBOX Mailbox;                                 /* 0x0200 */
+       /* Unused. */
+       LM_UINT8 Unused1[0x100];        /* 0x0100 */

 
 

-    /* MAC control registers. */
-    T3_MAC_CONTROL MacCtrl;                             /* 0x0400 */
+       /* Mailbox . */
+       T3_MAILBOX Mailbox;     /* 0x0200 */

 
 

-    /* Send data initiator control registers. */
-    T3_SEND_DATA_INITIATOR SndDataIn;                   /* 0x0c00 */
+       /* MAC control registers. */
+       T3_MAC_CONTROL MacCtrl; /* 0x0400 */

 
 

-    /* Send data completion Control registers. */
-    T3_SEND_DATA_COMPLETION SndDataComp;                /* 0x1000 */
+       /* Send data initiator control registers. */
+       T3_SEND_DATA_INITIATOR SndDataIn;       /* 0x0c00 */

 
 

-    /* Send BD ring selector. */
-    T3_SEND_BD_SELECTOR SndBdSel;                       /* 0x1400 */
+       /* Send data completion Control registers. */
+       T3_SEND_DATA_COMPLETION SndDataComp;    /* 0x1000 */

 
 

-    /* Send BD initiator control registers. */
-    T3_SEND_BD_INITIATOR SndBdIn;                       /* 0x1800 */
+       /* Send BD ring selector. */
+       T3_SEND_BD_SELECTOR SndBdSel;   /* 0x1400 */

 
 

-    /* Send BD completion control registers. */
-    T3_SEND_BD_COMPLETION SndBdComp;                    /* 0x1c00 */
+       /* Send BD initiator control registers. */
+       T3_SEND_BD_INITIATOR SndBdIn;   /* 0x1800 */

 
 

-    /* Receive list placement control registers. */
-    T3_RCV_LIST_PLACEMENT RcvListPlmt;                  /* 0x2000 */
+       /* Send BD completion control registers. */
+       T3_SEND_BD_COMPLETION SndBdComp;        /* 0x1c00 */

 
 

-    /* Receive Data and Receive BD Initiator Control. */
-    T3_RCV_DATA_BD_INITIATOR RcvDataBdIn;               /* 0x2400 */
+       /* Receive list placement control registers. */
+       T3_RCV_LIST_PLACEMENT RcvListPlmt;      /* 0x2000 */

 
 

-    /* Receive Data Completion Control */
-    T3_RCV_DATA_COMPLETION RcvDataComp;                 /* 0x2800 */
+       /* Receive Data and Receive BD Initiator Control. */
+       T3_RCV_DATA_BD_INITIATOR RcvDataBdIn;   /* 0x2400 */

 
 

-    /* Receive BD Initiator Control Registers. */
-    T3_RCV_BD_INITIATOR RcvBdIn;                        /* 0x2c00 */
+       /* Receive Data Completion Control */
+       T3_RCV_DATA_COMPLETION RcvDataComp;     /* 0x2800 */

 
 

-    /* Receive BD Completion Control Registers. */
-    T3_RCV_BD_COMPLETION RcvBdComp;                     /* 0x3000 */
+       /* Receive BD Initiator Control Registers. */
+       T3_RCV_BD_INITIATOR RcvBdIn;    /* 0x2c00 */

 
 

-    /* Receive list selector control registers. */
-    T3_RCV_LIST_SELECTOR RcvListSel;                    /* 0x3400 */
+       /* Receive BD Completion Control Registers. */
+       T3_RCV_BD_COMPLETION RcvBdComp; /* 0x3000 */

 
 

-    /* Mbuf cluster free registers. */
-    T3_MBUF_CLUSTER_FREE MbufClusterFree;               /* 0x3800 */
+       /* Receive list selector control registers. */
+       T3_RCV_LIST_SELECTOR RcvListSel;        /* 0x3400 */

 
 

-    /* Host coalescing control registers. */
-    T3_HOST_COALESCING HostCoalesce;                    /* 0x3c00 */
+       /* Mbuf cluster free registers. */
+       T3_MBUF_CLUSTER_FREE MbufClusterFree;   /* 0x3800 */

 
 

-    /* Memory arbiter control registers. */
-    T3_MEM_ARBITER MemArbiter;                          /* 0x4000 */
+       /* Host coalescing control registers. */
+       T3_HOST_COALESCING HostCoalesce;        /* 0x3c00 */

 
 

-    /* Buffer manger control registers. */
-    T3_BUFFER_MANAGER BufMgr;                           /* 0x4400 */
+       /* Memory arbiter control registers. */
+       T3_MEM_ARBITER MemArbiter;      /* 0x4000 */

 
 

-    /* Read DMA control registers. */
-    T3_DMA_READ DmaRead;                                /* 0x4800 */
+       /* Buffer manger control registers. */
+       T3_BUFFER_MANAGER BufMgr;       /* 0x4400 */

 
 

-    /* Write DMA control registers. */
-    T3_DMA_WRITE DmaWrite;                              /* 0x4c00 */
+       /* Read DMA control registers. */
+       T3_DMA_READ DmaRead;    /* 0x4800 */

 
 

-    T3_CPU rxCpu;                                       /* 0x5000 */
-    T3_CPU txCpu;                                       /* 0x5400 */
+       /* Write DMA control registers. */
+       T3_DMA_WRITE DmaWrite;  /* 0x4c00 */

 
 

-    /* Mailboxes. */
-    T3_GRC_MAILBOX GrcMailbox;                          /* 0x5800 */
+       T3_CPU rxCpu;           /* 0x5000 */
+       T3_CPU txCpu;           /* 0x5400 */

 
 

-    /* Flow Through queues. */
-    T3_FTQ Ftq;                                         /* 0x5c00 */
+       /* Mailboxes. */
+       T3_GRC_MAILBOX GrcMailbox;      /* 0x5800 */

 
 

-    /* Message signaled interrupt registes. */
-    T3_MSG_SIGNALED_INT Msi;                            /* 0x6000 */
+       /* Flow Through queues. */
+       T3_FTQ Ftq;             /* 0x5c00 */

 
 

-    /* DMA completion registers. */
-    T3_DMA_COMPLETION DmaComp;                          /* 0x6400 */
+       /* Message signaled interrupt registes. */
+       T3_MSG_SIGNALED_INT Msi;        /* 0x6000 */

 
 

-    /* GRC registers. */
-    T3_GRC Grc;                                         /* 0x6800 */
+       /* DMA completion registers. */
+       T3_DMA_COMPLETION DmaComp;      /* 0x6400 */

 
 

-    /* Unused space. */
-    LM_UINT8 Unused2[1024];                             /* 0x6c00 */
+       /* GRC registers. */
+       T3_GRC Grc;             /* 0x6800 */

 
 

-    /* NVRAM registers. */
-    T3_NVRAM Nvram;                                     /* 0x7000 */
-
-    /* Unused space. */
-    LM_UINT8 Unused3[3072];                             /* 0x7400 */
+       /* Unused space. */
+       LM_UINT8 Unused2[1024]; /* 0x6c00 */

 
 

-    /* The 32k memory window into the NIC's */
-    /* internal memory.  The memory window is */
-    /* controlled by the Memory Window Base */
-    /* Address register.  This register is located */
-    /* in the PCI configuration space. */
-    union {                                             /* 0x8000 */
-       T3_FIRST_32K_SRAM First32k;
+       /* NVRAM registers. */
+       T3_NVRAM Nvram;         /* 0x7000 */

 
 

-       /* Use the memory window base address register to determine the */
-       /* MBUF segment. */
-       LM_UINT32 Mbuf[32768/4];
-       LM_UINT32 MemBlock32K[32768/4];
-    } uIntMem;
+       /* Unused space. */
+       LM_UINT8 Unused3[3072]; /* 0x7400 */
+
+       /* The 32k memory window into the NIC's */
+       /* internal memory.  The memory window is */
+       /* controlled by the Memory Window Base */
+       /* Address register.  This register is located */
+       /* in the PCI configuration space. */
+       union {                 /* 0x8000 */
+               T3_FIRST_32K_SRAM First32k;
+
+               /* Use the memory window base address register to determine the */
+               /* MBUF segment. */
+               LM_UINT32 Mbuf[32768 / 4];
+               LM_UINT32 MemBlock32K[32768 / 4];
+       } uIntMem;

 } T3_STD_MEM_MAP, *PT3_STD_MEM_MAP;
 
 } T3_STD_MEM_MAP, *PT3_STD_MEM_MAP;
 

-

 /******************************************************************************/
 /* Adapter info. */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Adapter info. */
 /******************************************************************************/
 

-typedef struct
-{
-    LM_UINT16 Svid;
-    LM_UINT16 Ssid;
-    LM_UINT32 PhyId;
-    LM_UINT32 Serdes;   /* 0 = copper PHY, 1 = Serdes */
+typedef struct {
+       LM_UINT16 Svid;
+       LM_UINT16 Ssid;
+       LM_UINT32 PhyId;
+       LM_UINT32 Serdes;       /* 0 = copper PHY, 1 = Serdes */

 } LM_ADAPTER_INFO, *PLM_ADAPTER_INFO;
 
 } LM_ADAPTER_INFO, *PLM_ADAPTER_INFO;
 

-

 /******************************************************************************/
 /* Packet queues. */
 /******************************************************************************/
 
 /******************************************************************************/
 /* Packet queues. */
 /******************************************************************************/
 

-DECLARE_QUEUE_TYPE(LM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT);
-DECLARE_QUEUE_TYPE(LM_TX_PACKET_Q, MAX_TX_PACKET_DESC_COUNT);
-
+DECLARE_QUEUE_TYPE (LM_RX_PACKET_Q, MAX_RX_PACKET_DESC_COUNT);
+DECLARE_QUEUE_TYPE (LM_TX_PACKET_Q, MAX_TX_PACKET_DESC_COUNT);

 
 /******************************************************************************/
 /* Tx counters. */
 /******************************************************************************/
 
 typedef struct {
 
 /******************************************************************************/
 /* Tx counters. */
 /******************************************************************************/
 
 typedef struct {

-    LM_COUNTER TxPacketGoodCnt;
-    LM_COUNTER TxBytesGoodCnt;
-    LM_COUNTER TxPacketAbortedCnt;
-    LM_COUNTER NoSendBdLeftCnt;
-    LM_COUNTER NoMapRegisterLeftCnt;
-    LM_COUNTER TooManyFragmentsCnt;
-    LM_COUNTER NoTxPacketDescCnt;
+       LM_COUNTER TxPacketGoodCnt;
+       LM_COUNTER TxBytesGoodCnt;
+       LM_COUNTER TxPacketAbortedCnt;
+       LM_COUNTER NoSendBdLeftCnt;
+       LM_COUNTER NoMapRegisterLeftCnt;
+       LM_COUNTER TooManyFragmentsCnt;
+       LM_COUNTER NoTxPacketDescCnt;

 } LM_TX_COUNTERS, *PLM_TX_COUNTERS;
 
 } LM_TX_COUNTERS, *PLM_TX_COUNTERS;
 

-

 /******************************************************************************/
 /* Rx counters. */
 /******************************************************************************/
 
 typedef struct {
 /******************************************************************************/
 /* Rx counters. */
 /******************************************************************************/
 
 typedef struct {

-    LM_COUNTER RxPacketGoodCnt;
-    LM_COUNTER RxBytesGoodCnt;
-    LM_COUNTER RxPacketErrCnt;
-    LM_COUNTER RxErrCrcCnt;
-    LM_COUNTER RxErrCollCnt;
-    LM_COUNTER RxErrLinkLostCnt;
-    LM_COUNTER RxErrPhyDecodeCnt;
-    LM_COUNTER RxErrOddNibbleCnt;
-    LM_COUNTER RxErrMacAbortCnt;
-    LM_COUNTER RxErrShortPacketCnt;
-    LM_COUNTER RxErrNoResourceCnt;
-    LM_COUNTER RxErrLargePacketCnt;
+       LM_COUNTER RxPacketGoodCnt;
+       LM_COUNTER RxBytesGoodCnt;
+       LM_COUNTER RxPacketErrCnt;
+       LM_COUNTER RxErrCrcCnt;
+       LM_COUNTER RxErrCollCnt;
+       LM_COUNTER RxErrLinkLostCnt;
+       LM_COUNTER RxErrPhyDecodeCnt;
+       LM_COUNTER RxErrOddNibbleCnt;
+       LM_COUNTER RxErrMacAbortCnt;
+       LM_COUNTER RxErrShortPacketCnt;
+       LM_COUNTER RxErrNoResourceCnt;
+       LM_COUNTER RxErrLargePacketCnt;

 } LM_RX_COUNTERS, *PLM_RX_COUNTERS;
 
 } LM_RX_COUNTERS, *PLM_RX_COUNTERS;
 

-

 /******************************************************************************/
 /* Receive producer rings. */
 /******************************************************************************/
 
 typedef enum {
 /******************************************************************************/
 /* Receive producer rings. */
 /******************************************************************************/
 
 typedef enum {

-    T3_UNKNOWN_RCV_PROD_RING    = 0,
-    T3_STD_RCV_PROD_RING        = 1,
-    T3_MINI_RCV_PROD_RING       = 2,
-    T3_JUMBO_RCV_PROD_RING      = 3
+       T3_UNKNOWN_RCV_PROD_RING = 0,
+       T3_STD_RCV_PROD_RING = 1,
+       T3_MINI_RCV_PROD_RING = 2,
+       T3_JUMBO_RCV_PROD_RING = 3

 } T3_RCV_PROD_RING, *PT3_RCV_PROD_RING;
 
 } T3_RCV_PROD_RING, *PT3_RCV_PROD_RING;
 

-

 /******************************************************************************/
 /* Packet descriptor. */
 /******************************************************************************/
 /******************************************************************************/
 /* Packet descriptor. */
 /******************************************************************************/


@@ -2758,331 +2675,328 @@ typedef enum {
 #define LM_PACKET_SIGNATURE_RX              0x6b766168
 
 typedef struct _LM_PACKET {
 #define LM_PACKET_SIGNATURE_RX              0x6b766168
 
 typedef struct _LM_PACKET {

-    /* Set in LM. */
-    LM_STATUS PacketStatus;
+       /* Set in LM. */
+       LM_STATUS PacketStatus;

 
 

-    /* Set in LM for Rx, in UM for Tx. */
-    LM_UINT32 PacketSize;
+       /* Set in LM for Rx, in UM for Tx. */
+       LM_UINT32 PacketSize;

 
 

-    LM_UINT16 Flags;
+       LM_UINT16 Flags;

 
 

-    LM_UINT16 VlanTag;
+       LM_UINT16 VlanTag;

 
 

-    union {
-       /* Send info. */
-       struct {
-           /* Set up by UM. */
-           LM_UINT32 FragCount;
+       union {
+               /* Send info. */
+               struct {
+                       /* Set up by UM. */
+                       LM_UINT32 FragCount;

 
 

-       } Tx;
+               } Tx;

 
 

-       /* Receive info. */
-       struct {
-           /* This descriptor belongs to either Std, Mini, or Jumbo ring. */
-           T3_RCV_PROD_RING RcvProdRing;
+               /* Receive info. */
+               struct {
+                       /* This descriptor belongs to either Std, Mini, or Jumbo ring. */
+                       T3_RCV_PROD_RING RcvProdRing;

 
 

-           /* Receive buffer size */
-           LM_UINT32 RxBufferSize;
+                       /* Receive buffer size */
+                       LM_UINT32 RxBufferSize;

 
 

-           /* Checksum information. */
-           LM_UINT16 IpChecksum;
-           LM_UINT16 TcpUdpChecksum;
+                       /* Checksum information. */
+                       LM_UINT16 IpChecksum;
+                       LM_UINT16 TcpUdpChecksum;

 
 

-       } Rx;
-    } u;
+               } Rx;
+       } u;

 } LM_PACKET;
 
 } LM_PACKET;
 

-

 /******************************************************************************/
 /* Tigon3 device block. */
 /******************************************************************************/
 
 typedef struct _LM_DEVICE_BLOCK {
 /******************************************************************************/
 /* Tigon3 device block. */
 /******************************************************************************/
 
 typedef struct _LM_DEVICE_BLOCK {

-    int index; /* Device ID */
-    /* Memory view. */
-    PT3_STD_MEM_MAP pMemView;
+       int index;              /* Device ID */
+       /* Memory view. */
+       PT3_STD_MEM_MAP pMemView;

 
 

-    /* Base address of the block of memory in which the LM_PACKET descriptors */
-    /* are allocated from. */
-    PLM_VOID pPacketDescBase;
+       /* Base address of the block of memory in which the LM_PACKET descriptors */
+       /* are allocated from. */
+       PLM_VOID pPacketDescBase;

 
 

-    LM_UINT32 MiscHostCtrl;
-    LM_UINT32 GrcLocalCtrl;
-    LM_UINT32 DmaReadWriteCtrl;
-    LM_UINT32 PciState;
+       LM_UINT32 MiscHostCtrl;
+       LM_UINT32 GrcLocalCtrl;
+       LM_UINT32 DmaReadWriteCtrl;
+       LM_UINT32 PciState;

 
 

-    /* Rx info */
-    LM_UINT32 RxStdDescCnt;
-    LM_UINT32 RxStdQueuedCnt;
-    LM_UINT32 RxStdProdIdx;
+       /* Rx info */
+       LM_UINT32 RxStdDescCnt;
+       LM_UINT32 RxStdQueuedCnt;
+       LM_UINT32 RxStdProdIdx;

 
 

-    PT3_RCV_BD pRxStdBdVirt;
-    LM_PHYSICAL_ADDRESS RxStdBdPhy;
+       PT3_RCV_BD pRxStdBdVirt;
+       LM_PHYSICAL_ADDRESS RxStdBdPhy;

 
 

-    LM_UINT32 RxPacketDescCnt;
-    LM_RX_PACKET_Q RxPacketFreeQ;
-    LM_RX_PACKET_Q RxPacketReceivedQ;
+       LM_UINT32 RxPacketDescCnt;
+       LM_RX_PACKET_Q RxPacketFreeQ;
+       LM_RX_PACKET_Q RxPacketReceivedQ;

 
 

-    /* Receive info. */
-    PT3_RCV_BD pRcvRetBdVirt;
-    LM_PHYSICAL_ADDRESS RcvRetBdPhy;
-    LM_UINT32 RcvRetConIdx;
+       /* Receive info. */
+       PT3_RCV_BD pRcvRetBdVirt;
+       LM_PHYSICAL_ADDRESS RcvRetBdPhy;
+       LM_UINT32 RcvRetConIdx;

 
 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT
 
 #if T3_JUMBO_RCV_RCB_ENTRY_COUNT

-    LM_UINT32 RxJumboDescCnt;
-    LM_UINT32 RxJumboBufferSize;
-    LM_UINT32 RxJumboQueuedCnt;
+       LM_UINT32 RxJumboDescCnt;
+       LM_UINT32 RxJumboBufferSize;
+       LM_UINT32 RxJumboQueuedCnt;
+
+       LM_UINT32 RxJumboProdIdx;
+
+       PT3_RCV_BD pRxJumboBdVirt;
+       LM_PHYSICAL_ADDRESS RxJumboBdPhy;
+#endif                         /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */

 
 

-    LM_UINT32 RxJumboProdIdx;
+       /* These values are used by the upper module to inform the protocol */
+       /* of the maximum transmit/receive packet size. */
+       LM_UINT32 TxMtu;        /* Does not include CRC. */
+       LM_UINT32 RxMtu;        /* Does not include CRC. */

 
 

-    PT3_RCV_BD pRxJumboBdVirt;
-    LM_PHYSICAL_ADDRESS RxJumboBdPhy;
-#endif /* T3_JUMBO_RCV_RCB_ENTRY_COUNT */
+       /* We need to shadow the EMAC, Rx, Tx mode registers.  With B0 silicon, */
+       /* we may have problems reading any MAC registers in 10mb mode. */
+       LM_UINT32 MacMode;
+       LM_UINT32 RxMode;
+       LM_UINT32 TxMode;

 
 

-    /* These values are used by the upper module to inform the protocol */
-    /* of the maximum transmit/receive packet size. */
-    LM_UINT32 TxMtu;    /* Does not include CRC. */
-    LM_UINT32 RxMtu;    /* Does not include CRC. */
+       /* MiMode register. */
+       LM_UINT32 MiMode;

 
 

-    /* We need to shadow the EMAC, Rx, Tx mode registers.  With B0 silicon, */
-    /* we may have problems reading any MAC registers in 10mb mode. */
-    LM_UINT32 MacMode;
-    LM_UINT32 RxMode;
-    LM_UINT32 TxMode;
+       /* Host coalesce mode register. */
+       LM_UINT32 CoalesceMode;

 
 

-    /* MiMode register. */
-    LM_UINT32 MiMode;
-
-    /* Host coalesce mode register. */
-    LM_UINT32 CoalesceMode;
-
-    /* Send info. */
-    LM_UINT32 TxPacketDescCnt;
-
-    /* Tx info. */
-    LM_TX_PACKET_Q TxPacketFreeQ;
-    LM_TX_PACKET_Q TxPacketActiveQ;
-    LM_TX_PACKET_Q TxPacketXmittedQ;
-
-    /* Pointers to SendBd. */
-    PT3_SND_BD pSendBdVirt;
-    LM_PHYSICAL_ADDRESS SendBdPhy;  /* Only valid for Host based Send BD. */
-
-    /* Send producer and consumer indices. */
-    LM_UINT32 SendProdIdx;
-    LM_UINT32 SendConIdx;
-
-    /* Number of BD left. */
-    atomic_t SendBdLeft;
-
-    T3_SND_BD ShadowSendBd[T3_SEND_RCB_ENTRY_COUNT];
-
-    /* Counters. */
-    LM_RX_COUNTERS RxCounters;
-    LM_TX_COUNTERS TxCounters;
-
-    /* Host coalescing parameters. */
-    LM_UINT32 RxCoalescingTicks;
-    LM_UINT32 TxCoalescingTicks;
-    LM_UINT32 RxMaxCoalescedFrames;
-    LM_UINT32 TxMaxCoalescedFrames;
-    LM_UINT32 StatsCoalescingTicks;
-    LM_UINT32 RxCoalescingTicksDuringInt;
-    LM_UINT32 TxCoalescingTicksDuringInt;
-    LM_UINT32 RxMaxCoalescedFramesDuringInt;
-    LM_UINT32 TxMaxCoalescedFramesDuringInt;
-
-    /* DMA water marks. */
-    LM_UINT32 DmaMbufLowMark;
-    LM_UINT32 RxMacMbufLowMark;
-    LM_UINT32 MbufHighMark;
-
-    /* Status block. */
-    PT3_STATUS_BLOCK pStatusBlkVirt;
-    LM_PHYSICAL_ADDRESS StatusBlkPhy;
-
-    /* Statistics block. */
-    PT3_STATS_BLOCK pStatsBlkVirt;
-    LM_PHYSICAL_ADDRESS StatsBlkPhy;
-
-    /* Current receive mask. */
-    LM_UINT32 ReceiveMask;
-
-    /* Task offload capabilities. */
-    LM_TASK_OFFLOAD TaskOffloadCap;
-
-    /* Task offload selected. */
-    LM_TASK_OFFLOAD TaskToOffload;
-
-    /* Wake up capability. */
-    LM_WAKE_UP_MODE WakeUpModeCap;
-
-    /* Wake up capability. */
-    LM_WAKE_UP_MODE WakeUpMode;
-
-    /* Flow control. */
-    LM_FLOW_CONTROL FlowControlCap;
-    LM_FLOW_CONTROL FlowControl;
-
-    /* Enable or disable PCI MWI. */
-    LM_UINT32 EnableMWI;
-
-    /* Enable 5701 tagged status mode. */
-    LM_UINT32 UseTaggedStatus;
-
-    /* NIC will not compute the pseudo header checksum.  The driver or OS */
-    /* must seed the checksum field with the pseudo checksum. */
-    LM_UINT32 NoTxPseudoHdrChksum;
-
-    /* The receive checksum in the BD does not include the pseudo checksum. */
-    /* The OS or the driver must calculate the pseudo checksum and add it to */
-    /* the checksum in the BD. */
-    LM_UINT32 NoRxPseudoHdrChksum;
-
-    /* Current node address. */
-    LM_UINT8 NodeAddress[8];
-
-    /* The adapter's node address. */
-    LM_UINT8 PermanentNodeAddress[8];
-
-    /* Adapter info. */
-    LM_UINT16 BusNum;
-    LM_UINT8 DevNum;
-    LM_UINT8 FunctNum;
-    LM_UINT16 PciVendorId;
-    LM_UINT16 PciDeviceId;
-    LM_UINT32 BondId;
-    LM_UINT8 Irq;
-    LM_UINT8 IntPin;
-    LM_UINT8 CacheLineSize;
-    LM_UINT8 PciRevId;
+       /* Send info. */
+       LM_UINT32 TxPacketDescCnt;
+
+       /* Tx info. */
+       LM_TX_PACKET_Q TxPacketFreeQ;
+       LM_TX_PACKET_Q TxPacketActiveQ;
+       LM_TX_PACKET_Q TxPacketXmittedQ;
+
+       /* Pointers to SendBd. */
+       PT3_SND_BD pSendBdVirt;
+       LM_PHYSICAL_ADDRESS SendBdPhy;  /* Only valid for Host based Send BD. */
+
+       /* Send producer and consumer indices. */
+       LM_UINT32 SendProdIdx;
+       LM_UINT32 SendConIdx;
+
+       /* Number of BD left. */
+       atomic_t SendBdLeft;
+
+       T3_SND_BD ShadowSendBd[T3_SEND_RCB_ENTRY_COUNT];
+
+       /* Counters. */
+       LM_RX_COUNTERS RxCounters;
+       LM_TX_COUNTERS TxCounters;
+
+       /* Host coalescing parameters. */
+       LM_UINT32 RxCoalescingTicks;
+       LM_UINT32 TxCoalescingTicks;
+       LM_UINT32 RxMaxCoalescedFrames;
+       LM_UINT32 TxMaxCoalescedFrames;
+       LM_UINT32 StatsCoalescingTicks;
+       LM_UINT32 RxCoalescingTicksDuringInt;
+       LM_UINT32 TxCoalescingTicksDuringInt;
+       LM_UINT32 RxMaxCoalescedFramesDuringInt;
+       LM_UINT32 TxMaxCoalescedFramesDuringInt;
+
+       /* DMA water marks. */
+       LM_UINT32 DmaMbufLowMark;
+       LM_UINT32 RxMacMbufLowMark;
+       LM_UINT32 MbufHighMark;
+
+       /* Status block. */
+       PT3_STATUS_BLOCK pStatusBlkVirt;
+       LM_PHYSICAL_ADDRESS StatusBlkPhy;
+
+       /* Statistics block. */
+       PT3_STATS_BLOCK pStatsBlkVirt;
+       LM_PHYSICAL_ADDRESS StatsBlkPhy;
+
+       /* Current receive mask. */
+       LM_UINT32 ReceiveMask;
+
+       /* Task offload capabilities. */
+       LM_TASK_OFFLOAD TaskOffloadCap;
+
+       /* Task offload selected. */
+       LM_TASK_OFFLOAD TaskToOffload;
+
+       /* Wake up capability. */
+       LM_WAKE_UP_MODE WakeUpModeCap;
+
+       /* Wake up capability. */
+       LM_WAKE_UP_MODE WakeUpMode;
+
+       /* Flow control. */
+       LM_FLOW_CONTROL FlowControlCap;
+       LM_FLOW_CONTROL FlowControl;
+
+       /* Enable or disable PCI MWI. */
+       LM_UINT32 EnableMWI;
+
+       /* Enable 5701 tagged status mode. */
+       LM_UINT32 UseTaggedStatus;
+
+       /* NIC will not compute the pseudo header checksum.  The driver or OS */
+       /* must seed the checksum field with the pseudo checksum. */
+       LM_UINT32 NoTxPseudoHdrChksum;
+
+       /* The receive checksum in the BD does not include the pseudo checksum. */
+       /* The OS or the driver must calculate the pseudo checksum and add it to */
+       /* the checksum in the BD. */
+       LM_UINT32 NoRxPseudoHdrChksum;
+
+       /* Current node address. */
+       LM_UINT8 NodeAddress[8];
+
+       /* The adapter's node address. */
+       LM_UINT8 PermanentNodeAddress[8];
+
+       /* Adapter info. */
+       LM_UINT16 BusNum;
+       LM_UINT8 DevNum;
+       LM_UINT8 FunctNum;
+       LM_UINT16 PciVendorId;
+       LM_UINT16 PciDeviceId;
+       LM_UINT32 BondId;
+       LM_UINT8 Irq;
+       LM_UINT8 IntPin;
+       LM_UINT8 CacheLineSize;
+       LM_UINT8 PciRevId;

 #if PCIX_TARGET_WORKAROUND
        LM_UINT32 EnablePciXFix;
 #endif
 #if PCIX_TARGET_WORKAROUND
        LM_UINT32 EnablePciXFix;
 #endif

-    LM_UINT32 UndiFix;   /* new, jimmy */
-    LM_UINT32 PciCommandStatusWords;
-    LM_UINT32 ChipRevId;
-    LM_UINT16 SubsystemVendorId;
-    LM_UINT16 SubsystemId;
-#if 0  /* Jimmy, deleted in new driver */
-    LM_UINT32 MemBaseLow;
-    LM_UINT32 MemBaseHigh;
-    LM_UINT32 MemBaseSize;
+       LM_UINT32 UndiFix;      /* new, jimmy */
+       LM_UINT32 PciCommandStatusWords;
+       LM_UINT32 ChipRevId;
+       LM_UINT16 SubsystemVendorId;
+       LM_UINT16 SubsystemId;
+#if 0                          /* Jimmy, deleted in new driver */
+       LM_UINT32 MemBaseLow;
+       LM_UINT32 MemBaseHigh;
+       LM_UINT32 MemBaseSize;

 #endif
 #endif

-    PLM_UINT8 pMappedMemBase;
-
-    /* Saved PCI configuration registers for restoring after a reset. */
-    LM_UINT32 SavedCacheLineReg;
+       PLM_UINT8 pMappedMemBase;

 
 

-    /* Phy info. */
-    LM_UINT32 PhyAddr;
-    LM_UINT32 PhyId;
+       /* Saved PCI configuration registers for restoring after a reset. */
+       LM_UINT32 SavedCacheLineReg;

 
 

-    /* Requested phy settings. */
-    LM_REQUESTED_MEDIA_TYPE RequestedMediaType;
+       /* Phy info. */
+       LM_UINT32 PhyAddr;
+       LM_UINT32 PhyId;

 
 

-    /* Disable auto-negotiation. */
-    LM_UINT32 DisableAutoNeg;
+       /* Requested phy settings. */
+       LM_REQUESTED_MEDIA_TYPE RequestedMediaType;

 
 

-    /* Ways for the MAC to get link change interrupt. */
-    LM_UINT32 PhyIntMode;
-    #define T3_PHY_INT_MODE_AUTO                        0
-    #define T3_PHY_INT_MODE_MI_INTERRUPT                1
-    #define T3_PHY_INT_MODE_LINK_READY                  2
-    #define T3_PHY_INT_MODE_AUTO_POLLING                3
+       /* Disable auto-negotiation. */
+       LM_UINT32 DisableAutoNeg;

 
 

-    /* Ways to determine link change status. */
-    LM_UINT32 LinkChngMode;
-    #define T3_LINK_CHNG_MODE_AUTO                      0
-    #define T3_LINK_CHNG_MODE_USE_STATUS_REG            1
-    #define T3_LINK_CHNG_MODE_USE_STATUS_BLOCK          2
+       /* Ways for the MAC to get link change interrupt. */
+       LM_UINT32 PhyIntMode;
+#define T3_PHY_INT_MODE_AUTO                        0
+#define T3_PHY_INT_MODE_MI_INTERRUPT                1
+#define T3_PHY_INT_MODE_LINK_READY                  2
+#define T3_PHY_INT_MODE_AUTO_POLLING                3

 
 

+       /* Ways to determine link change status. */
+       LM_UINT32 LinkChngMode;
+#define T3_LINK_CHNG_MODE_AUTO                      0
+#define T3_LINK_CHNG_MODE_USE_STATUS_REG            1
+#define T3_LINK_CHNG_MODE_USE_STATUS_BLOCK          2

 
 

-    /* LED mode. */
-    LM_UINT32 LedMode;
+       /* LED mode. */
+       LM_UINT32 LedMode;

 
 

-    #define LED_MODE_AUTO                               0
+#define LED_MODE_AUTO                               0

 
 

-    /* 5700/01 LED mode. */
-    #define LED_MODE_THREE_LINK                         1
-    #define LED_MODE_LINK10                             2
+       /* 5700/01 LED mode. */
+#define LED_MODE_THREE_LINK                         1
+#define LED_MODE_LINK10                             2

 
 

-    /* 5703/02/04 LED mode. */
-    #define LED_MODE_OPEN_DRAIN                         1
-    #define LED_MODE_OUTPUT                             2
+       /* 5703/02/04 LED mode. */
+#define LED_MODE_OPEN_DRAIN                         1
+#define LED_MODE_OUTPUT                             2

 
 

-    /* WOL Speed */
-    LM_UINT32 WolSpeed;
-    #define WOL_SPEED_10MB                              1
-    #define WOL_SPEED_100MB                             2
+       /* WOL Speed */
+       LM_UINT32 WolSpeed;
+#define WOL_SPEED_10MB                              1
+#define WOL_SPEED_100MB                             2

 
 

-    /* Reset the PHY on initialization. */
-    LM_UINT32 ResetPhyOnInit;
+       /* Reset the PHY on initialization. */
+       LM_UINT32 ResetPhyOnInit;

 
 

-    LM_UINT32 RestoreOnWakeUp;
-    LM_REQUESTED_MEDIA_TYPE WakeUpRequestedMediaType;
-    LM_UINT32 WakeUpDisableAutoNeg;
+       LM_UINT32 RestoreOnWakeUp;
+       LM_REQUESTED_MEDIA_TYPE WakeUpRequestedMediaType;
+       LM_UINT32 WakeUpDisableAutoNeg;

 
 

-    /* Current phy settings. */
-    LM_MEDIA_TYPE MediaType;
-    LM_LINE_SPEED LineSpeed;
-    LM_LINE_SPEED OldLineSpeed;
-    LM_DUPLEX_MODE DuplexMode;
-    LM_STATUS LinkStatus;
-    LM_UINT32 advertising;     /* Jimmy, new! */
-    LM_UINT32 advertising1000; /* Jimmy, new! */
+       /* Current phy settings. */
+       LM_MEDIA_TYPE MediaType;
+       LM_LINE_SPEED LineSpeed;
+       LM_LINE_SPEED OldLineSpeed;
+       LM_DUPLEX_MODE DuplexMode;
+       LM_STATUS LinkStatus;
+       LM_UINT32 advertising;  /* Jimmy, new! */
+       LM_UINT32 advertising1000;      /* Jimmy, new! */

 
 

-    /* Multicast address list. */
-    LM_UINT32 McEntryCount;
-    LM_UINT8 McTable[LM_MAX_MC_TABLE_SIZE][LM_MC_ENTRY_SIZE];
+       /* Multicast address list. */
+       LM_UINT32 McEntryCount;
+       LM_UINT8 McTable[LM_MAX_MC_TABLE_SIZE][LM_MC_ENTRY_SIZE];

 
 

-    /* Use NIC or Host based send BD. */
-    LM_UINT32 NicSendBd;
+       /* Use NIC or Host based send BD. */
+       LM_UINT32 NicSendBd;

 
 

-    /* Athlon fix. */
-    LM_UINT32 DelayPciGrant;
+       /* Athlon fix. */
+       LM_UINT32 DelayPciGrant;

 
 

-    /* Enable OneDmaAtOnce */
-    LM_UINT32 OneDmaAtOnce;
+       /* Enable OneDmaAtOnce */
+       LM_UINT32 OneDmaAtOnce;

 
 

-    /* Split Mode flags, Jimmy new */
-    LM_UINT32 SplitModeEnable;
-    LM_UINT32 SplitModeMaxReq;
+       /* Split Mode flags, Jimmy new */
+       LM_UINT32 SplitModeEnable;
+       LM_UINT32 SplitModeMaxReq;

 
 

-    /* Init flag. */
-    LM_BOOL InitDone;
+       /* Init flag. */
+       LM_BOOL InitDone;

 
 

-    /* Shutdown flag.  Set by the upper module. */
-    LM_BOOL ShuttingDown;
+       /* Shutdown flag.  Set by the upper module. */
+       LM_BOOL ShuttingDown;

 
 

-    /* Flag to determine whether to call LM_QueueRxPackets or not in */
-    /* LM_ResetAdapter routine. */
-    LM_BOOL QueueRxPackets;
+       /* Flag to determine whether to call LM_QueueRxPackets or not in */
+       /* LM_ResetAdapter routine. */
+       LM_BOOL QueueRxPackets;

 
 

-    LM_UINT32 MbufBase;
-    LM_UINT32 MbufSize;
+       LM_UINT32 MbufBase;
+       LM_UINT32 MbufSize;

 
 

-    /* TRUE if we have a SERDES PHY. */
-    LM_UINT32 EnableTbi;
+       /* TRUE if we have a SERDES PHY. */
+       LM_UINT32 EnableTbi;

 
 

-    /* Ethernet@WireSpeed. */
-    LM_UINT32 EnableWireSpeed;
+       /* Ethernet@WireSpeed. */
+       LM_UINT32 EnableWireSpeed;

 
 

-    LM_UINT32 EepromWp;
+       LM_UINT32 EepromWp;

 
 #if INCLUDE_TBI_SUPPORT
 
 #if INCLUDE_TBI_SUPPORT

-    /* Autoneg state info. */
-    AN_STATE_INFO AnInfo;
-    LM_UINT32 PollTbiLink;
-    LM_UINT32 IgnoreTbiLinkChange;
+       /* Autoneg state info. */
+       AN_STATE_INFO AnInfo;
+       LM_UINT32 PollTbiLink;
+       LM_UINT32 IgnoreTbiLinkChange;

 #endif
 #endif

-    char PartNo[24];
-    char BootCodeVer[16];
-    char BusSpeedStr[24]; /* Jimmy, new! */
-    LM_UINT32 PhyCrcCount;
+       char PartNo[24];
+       char BootCodeVer[16];
+       char BusSpeedStr[24];   /* Jimmy, new! */
+       LM_UINT32 PhyCrcCount;

 } LM_DEVICE_BLOCK;
 
 } LM_DEVICE_BLOCK;
 

-

 #define T3_REG_CPU_VIEW               0xc0000000
 
 #define T3_BLOCK_DMA_RD               (1 << 0)
 #define T3_REG_CPU_VIEW               0xc0000000
 
 #define T3_BLOCK_DMA_RD               (1 << 0)


@@ -3216,7 +3130,6 @@ typedef struct _LM_DEVICE_BLOCK {
 #define TX_CPU_EVT_SW12             30
 #define TX_CPU_EVT_SW13             31
 
 #define TX_CPU_EVT_SW12             30
 #define TX_CPU_EVT_SW13             31
 

-

 /* TX-CPU event */
 #define TX_CPU_EVENT_SW_EVENT0      (1 << TX_CPU_EVT_SW0)
 #define TX_CPU_EVENT_SW_EVENT1      (1 << TX_CPU_EVT_SW1)
 /* TX-CPU event */
 #define TX_CPU_EVENT_SW_EVENT0      (1 << TX_CPU_EVT_SW0)
 #define TX_CPU_EVENT_SW_EVENT1      (1 << TX_CPU_EVT_SW1)


@@ -3251,12 +3164,10 @@ typedef struct _LM_DEVICE_BLOCK {
 #define TX_CPU_EVENT_SW_EVENT12     (1 << TX_CPU_EVT_SW12)
 #define TX_CPU_EVENT_SW_EVENT13     (1 << TX_CPU_EVT_SW13)
 
 #define TX_CPU_EVENT_SW_EVENT12     (1 << TX_CPU_EVT_SW12)
 #define TX_CPU_EVENT_SW_EVENT13     (1 << TX_CPU_EVT_SW13)
 

-

 #define TX_CPU_MASK (TX_CPU_EVENT_SW_EVENT0 | \
                     TX_CPU_EVENT_SDI  | \
                     TX_CPU_EVENT_SDC)
 
 #define TX_CPU_MASK (TX_CPU_EVENT_SW_EVENT0 | \
                     TX_CPU_EVENT_SDI  | \
                     TX_CPU_EVENT_SDC)
 

-

 #define T3_FTQ_TYPE1_UNDERFLOW_BIT   (1 << 29)
 #define T3_FTQ_TYPE1_PASS_BIT        (1 << 30)
 #define T3_FTQ_TYPE1_SKIP_BIT        (1 << 31)
 #define T3_FTQ_TYPE1_UNDERFLOW_BIT   (1 << 29)
 #define T3_FTQ_TYPE1_PASS_BIT        (1 << 30)
 #define T3_FTQ_TYPE1_SKIP_BIT        (1 << 31)


@@ -3283,25 +3194,24 @@ typedef struct _LM_DEVICE_BLOCK {
 #define T3_QID_RX_DATA_COMP           16
 #define T3_QID_SW_TYPE2               17
 
 #define T3_QID_RX_DATA_COMP           16
 #define T3_QID_SW_TYPE2               17
 

-LM_STATUS LM_LoadFirmware(PLM_DEVICE_BLOCK pDevice,
-                         PT3_FWIMG_INFO pFwImg,
-                         LM_UINT32 LoadCpu,
-                         LM_UINT32 StartCpu);
+LM_STATUS LM_LoadFirmware (PLM_DEVICE_BLOCK pDevice,
+                          PT3_FWIMG_INFO pFwImg,
+                          LM_UINT32 LoadCpu, LM_UINT32 StartCpu);

 
 /******************************************************************************/
 /* NIC register read/write macros. */
 /******************************************************************************/
 
 
 /******************************************************************************/
 /* NIC register read/write macros. */
 /******************************************************************************/
 

-#if 0  /* Jimmy */
+#if 0                          /* Jimmy */

 /* MAC register access. */
 /* MAC register access. */

-LM_UINT32 LM_RegRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register);
-LM_VOID LM_RegWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register,
-    LM_UINT32 Value32);
+LM_UINT32 LM_RegRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register);
+LM_VOID LM_RegWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register,
+                    LM_UINT32 Value32);

 
 /* MAC memory access. */
 
 /* MAC memory access. */

-LM_UINT32 LM_MemRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr);
-LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
-    LM_UINT32 Value32);
+LM_UINT32 LM_MemRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr);
+LM_VOID LM_MemWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
+                    LM_UINT32 Value32);

 
 #if PCIX_TARGET_WORKAROUND
 
 
 #if PCIX_TARGET_WORKAROUND
 


@@ -3342,7 +3252,7 @@ LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
 #define MEM_WR_OFFSET(pDevice, Offset, Value32)                  \
     LM_MemWrInd(pDevice, Offset, Value32)
 
 #define MEM_WR_OFFSET(pDevice, Offset, Value32)                  \
     LM_MemWrInd(pDevice, Offset, Value32)
 

-#else /* normal target access path below */
+#else                          /* normal target access path below */

 
 /* Register access. */
 #define REG_RD(pDevice, OffsetName)                                         \
 
 /* Register access. */
 #define REG_RD(pDevice, OffsetName)                                         \


@@ -3355,7 +3265,6 @@ LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
 #define REG_WR_OFFSET(pDevice, Offset, Value32)                             \
     writel(Value32, ((LM_UINT8 *) (pDevice)->pMemView + Offset))
 
 #define REG_WR_OFFSET(pDevice, Offset, Value32)                             \
     writel(Value32, ((LM_UINT8 *) (pDevice)->pMemView + Offset))
 

-

 /* There could be problem access the memory window directly.  For now, */
 /* we have to go through the PCI configuration register. */
 #define MEM_RD(pDevice, AddrName)                                           \
 /* There could be problem access the memory window directly.  For now, */
 /* we have to go through the PCI configuration register. */
 #define MEM_RD(pDevice, AddrName)                                           \


@@ -3368,9 +3277,9 @@ LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
 #define MEM_WR_OFFSET(pDevice, Offset, Value32)                             \
     LM_MemWrInd(pDevice, Offset, Value32)
 
 #define MEM_WR_OFFSET(pDevice, Offset, Value32)                             \
     LM_MemWrInd(pDevice, Offset, Value32)
 

-#endif  /* PCIX_TARGET_WORKAROUND */
+#endif                         /* PCIX_TARGET_WORKAROUND */

 
 

-#endif  /* Jimmy, merging */
+#endif                         /* Jimmy, merging */

 
   /* Jimmy...rest of file is new stuff! */
 /******************************************************************************/
 
   /* Jimmy...rest of file is new stuff! */
 /******************************************************************************/


@@ -3378,14 +3287,14 @@ LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
 /******************************************************************************/
 
 /* MAC register access. */
 /******************************************************************************/
 
 /* MAC register access. */

-LM_UINT32 LM_RegRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register);
-LM_VOID LM_RegWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register,
-    LM_UINT32 Value32);
+LM_UINT32 LM_RegRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register);
+LM_VOID LM_RegWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 Register,
+                    LM_UINT32 Value32);

 
 /* MAC memory access. */
 
 /* MAC memory access. */

-LM_UINT32 LM_MemRdInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr);
-LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
-    LM_UINT32 Value32);
+LM_UINT32 LM_MemRdInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr);
+LM_VOID LM_MemWrInd (PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
+                    LM_UINT32 Value32);

 
 #define MB_REG_WR(pDevice, OffsetName, Value32)                               \
     ((pDevice)->UndiFix) ?                                                    \
 
 #define MB_REG_WR(pDevice, OffsetName, Value32)                               \
     ((pDevice)->UndiFix) ?                                                    \


@@ -3427,4 +3336,4 @@ LM_VOID LM_MemWrInd(PLM_DEVICE_BLOCK pDevice, LM_UINT32 MemAddr,
 #define MEM_WR_OFFSET(pDevice, Offset, Value32)                             \
     LM_MemWrInd(pDevice, Offset, Value32)
 
 #define MEM_WR_OFFSET(pDevice, Offset, Value32)                             \
     LM_MemWrInd(pDevice, Offset, Value32)
 

-#endif /* TIGON3_H */
+#endif                         /* TIGON3_H */