fpga: zynqpl: Add support for zc7100 device.

- Add support for zc7100 device.
- FPGA programming on few of the SOC(zc7100) takes more
  than 1sec, hence increased the program time by 4sec to
  sync' all soc's.

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>

diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c
index 4bb140e29ec0cb5f72c512db0dc8d74e7c3d2e3a..c173f0cc51f498b1c1c9cf7514f28b0ec1d8223d 100644 (file)
--- a/board/xilinx/zynq/board.c
+++ b/board/xilinx/zynq/board.c
@@ -20,6 +20,7 @@ Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
 Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
 Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
 Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
+Xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
 #endif
 
 int board_init(void)
@@ -42,6 +43,9 @@ int board_init(void)
        case XILINX_ZYNQ_7045:
                fpga = fpga045;
                break;
+       case XILINX_ZYNQ_7100:
+               fpga = fpga100;
+               break;
        }
 #endif
 

diff --git a/drivers/fpga/zynqpl.c b/drivers/fpga/zynqpl.c
index 8cc16fd2c2db3da9c77dabbd1e2ad89cd9bb36eb..aa49e82483fda7f2f0671f02fdeb0a274ad7763e 100644 (file)
--- a/drivers/fpga/zynqpl.c
+++ b/drivers/fpga/zynqpl.c
@@ -31,7 +31,7 @@
 #endif
 
 #ifndef CONFIG_SYS_FPGA_PROG_TIME
-#define CONFIG_SYS_FPGA_PROG_TIME CONFIG_SYS_HZ        /* 1 s */
+#define CONFIG_SYS_FPGA_PROG_TIME      (CONFIG_SYS_HZ * 4) /* 4 s */
 #endif
 
 int zynq_info(Xilinx_desc *desc)

diff --git a/include/zynqpl.h b/include/zynqpl.h
index f8211cdba29e7a31b9e6b0e83f44101fc49278fd..6107cbf3a5a9c98c44951b013adee0cab949e3d8 100644 (file)
--- a/include/zynqpl.h
+++ b/include/zynqpl.h
@@ -20,12 +20,14 @@ extern int zynq_info(Xilinx_desc *desc);
 #define XILINX_ZYNQ_7020       0x7
 #define XILINX_ZYNQ_7030       0xc
 #define XILINX_ZYNQ_7045       0x11
+#define XILINX_ZYNQ_7100       0x16
 
 /* Device Image Sizes */
 #define XILINX_XC7Z010_SIZE    16669920/8
 #define XILINX_XC7Z020_SIZE    32364512/8
 #define XILINX_XC7Z030_SIZE    47839328/8
 #define XILINX_XC7Z045_SIZE    106571232/8
+#define XILINX_XC7Z100_SIZE    139330784/8
 
 /* Descriptor Macros */
 #define XILINX_XC7Z010_DESC(cookie) \
@@ -40,4 +42,7 @@ extern int zynq_info(Xilinx_desc *desc);
 #define XILINX_XC7Z045_DESC(cookie) \
 { xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, "7z045" }
 
+#define XILINX_XC7Z100_DESC(cookie) \
+{ xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, "7z100" }
+
 #endif /* _ZYNQPL_H_ */