]> git.kernelconcepts.de Git - karo-tx-uboot.git/commitdiff
ls2085a: esdhc: Add esdhc support for ls2085a
authorYangbo Lu <yangbo.lu@freescale.com>
Sat, 21 Mar 2015 02:28:31 +0000 (19:28 -0700)
committerLothar Waßmann <LW@KARO-electronics.de>
Tue, 8 Sep 2015 20:31:32 +0000 (22:31 +0200)
This patch adds esdhc support for ls2085a.

Signed-off-by: Yangbo Lu <yangbo.lu@freescale.com>
Signed-off-by: York Sun <yorksun@freescale.com>
arch/arm/cpu/armv8/fsl-lsch3/cpu.c
arch/arm/cpu/armv8/fsl-lsch3/fdt.c
arch/arm/include/asm/arch-fsl-lsch3/config.h
drivers/mmc/fsl_esdhc.c
include/configs/ls2085a_common.h
include/configs/ls2085aqds.h
include/configs/ls2085ardb.h

index 07064a32b93c17e11eda0d48323a08b4c4d5d4b6..67145778b97fba9e2aba03b3328b0bee397c2068 100644 (file)
@@ -13,6 +13,9 @@
 #include <fsl_debug_server.h>
 #include <fsl-mc/fsl_mc.h>
 #include <asm/arch/fsl_serdes.h>
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
 #include "cpu.h"
 #include "mp.h"
 #include "speed.h"
@@ -412,6 +415,13 @@ int print_cpuinfo(void)
 }
 #endif
 
+#ifdef CONFIG_FSL_ESDHC
+int cpu_mmc_init(bd_t *bis)
+{
+       return fsl_esdhc_mmc_init(bis);
+}
+#endif
+
 int cpu_eth_init(bd_t *bis)
 {
        int error = 0;
index 42c5b58d9a016f38aa57c74b1214946cc5a4c7f2..d37002333c92d441b39e875d1bacfc6292eabaed 100644 (file)
@@ -7,6 +7,9 @@
 #include <common.h>
 #include <libfdt.h>
 #include <fdt_support.h>
+#ifdef CONFIG_FSL_ESDHC
+#include <fsl_esdhc.h>
+#endif
 #include "mp.h"
 
 #ifdef CONFIG_MP
@@ -65,4 +68,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
        do_fixup_by_compat_u32(blob, "fsl,ns16550",
                               "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 #endif
+
+#if defined(CONFIG_FSL_ESDHC)
+       fdt_fixup_esdhc(blob, bd);
+#endif
 }
index 77c20ab4ad0b4715ddc68dd71545527dfe9d6044..ca8d38cf78b720b02f04996a57c2ace698a5fc58 100644 (file)
@@ -31,6 +31,7 @@
 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR       (CONFIG_SYS_IMMR + 0x00300000)
 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR       (CONFIG_SYS_IMMR + 0x00310000)
 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR       (CONFIG_SYS_IMMR + 0x00370000)
+#define CONFIG_SYS_FSL_ESDHC_ADDR              (CONFIG_SYS_IMMR + 0x01140000)
 #define CONFIG_SYS_IFC_ADDR                    (CONFIG_SYS_IMMR + 0x01240000)
 #define CONFIG_SYS_NS16550_COM1                        (CONFIG_SYS_IMMR + 0x011C0500)
 #define CONFIG_SYS_NS16550_COM2                        (CONFIG_SYS_IMMR + 0x011C0600)
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
 #define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_5_0
 
+#define CONFIG_SYS_FSL_ESDHC_LE
 /* IFC */
 #define CONFIG_SYS_FSL_IFC_LE
 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
index b4935c759248f5f02db88ea49f0c029133a26340..f5212e7699a21e0a220bf10fa27078ea1d269c15 100644 (file)
@@ -105,7 +105,8 @@ static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
        else if (cmd->resp_type & MMC_RSP_PRESENT)
                xfertyp |= XFERTYP_RSPTYP_48;
 
-#if defined(CONFIG_SOC_MX53) || defined(CONFIG_PPC_T4240) || defined(CONFIG_SOC_LS102XA)
+#if defined(CONFIG_SOC_MX53) || defined(CONFIG_PPC_T4240) || \
+       defined(CONFIG_SOC_LS102XA) || defined(CONFIG_LS2085A)
        if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
                xfertyp |= XFERTYP_CMDTYP_ABORT;
 #endif
@@ -195,6 +196,9 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
        int timeout;
        struct fsl_esdhc_cfg *cfg = mmc->priv;
        struct fsl_esdhc *regs = cfg->esdhc_base;
+#ifdef CONFIG_LS2085A
+       dma_addr_t addr;
+#endif
        uint wml_value;
 
        wml_value = data->blocksize / 4;
@@ -205,7 +209,15 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 
                esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+#ifdef CONFIG_LS2085A
+               addr = virt_to_phys((void *)(data->dest));
+               if (upper_32_bits(addr))
+                       printf("Error found for upper 32 bits\n");
+               else
+                       esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
+#else
                esdhc_write32(&regs->dsaddr, (u32)data->dest);
+#endif
 #endif
        } else {
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
@@ -225,7 +237,15 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
                esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
                                        wml_value << 16);
 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+#ifdef CONFIG_LS2085A
+               addr = virt_to_phys((void *)(data->src));
+               if (upper_32_bits(addr))
+                       printf("Error found for upper 32 bits\n");
+               else
+                       esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
+#else
                esdhc_write32(&regs->dsaddr, (u32)data->src);
+#endif
 #endif
        }
 
@@ -271,10 +291,23 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 static void check_and_invalidate_dcache_range
        (struct mmc_cmd *cmd,
         struct mmc_data *data) {
+#ifdef CONFIG_LS2085A
+       unsigned start = 0;
+#else
        unsigned start = (unsigned)data->dest ;
+#endif
        unsigned size = roundup(ARCH_DMA_MINALIGN,
                                data->blocks*data->blocksize);
        unsigned end = start+size ;
+#ifdef CONFIG_LS2085A
+       dma_addr_t addr;
+
+       addr = virt_to_phys((void *)(data->dest));
+       if (upper_32_bits(addr))
+               printf("Error found for upper 32 bits\n");
+       else
+               start = lower_32_bits(addr);
+#endif
        invalidate_dcache_range(start, end);
 }
 #endif
index 2fa07d48a09de4390bcc86632761c70323f6b8f8..e270fc8c195ab1f12890629f7081c3a4c34fdb4f 100644 (file)
@@ -155,6 +155,9 @@ unsigned long long get_qixis_addr(void);
 #define QIXIS_BASE                             get_qixis_addr()
 #define QIXIS_BASE_PHYS                                0x20000000
 #define QIXIS_BASE_PHYS_EARLY                  0xC000000
+#define QIXIS_STAT_PRES1                       0xb
+#define QIXIS_SDID_MASK                                0x07
+#define QIXIS_ESDHC_NO_ADAPTER                 0x7
 
 #define CONFIG_SYS_NAND_BASE                   0x530000000ULL
 #define CONFIG_SYS_NAND_BASE_PHYS              0x30000000
@@ -217,8 +220,6 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_CMD_BOOTD
 #define CONFIG_CMD_ECHO
 #define CONFIG_CMD_SOURCE
-#define CONFIG_CMD_FAT
-#define CONFIG_DOS_PARTITION
 
 /* Miscellaneous configurable options */
 #define CONFIG_SYS_LOAD_ADDR   (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
index 3d3e3aed96fc9ea963f4404eef3a8dd57d53b4b8..711d529624d16ffa13a6a40de545471a11a40e03 100644 (file)
@@ -274,6 +274,14 @@ unsigned long get_board_ddr_clk(void);
 /* I2C bus multiplexer */
 #define I2C_MUX_CH_DEFAULT      0x8
 
+/*
+ * MMC
+ */
+#ifdef CONFIG_MMC
+#define CONFIG_ESDHC_DETECT_QUIRK ((readb(QIXIS_BASE + QIXIS_STAT_PRES1) & \
+       QIXIS_SDID_MASK) != QIXIS_ESDHC_NO_ADAPTER)
+#endif
+
 /*
  * RTC configuration
  */
@@ -304,7 +312,16 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_CMD_NET
 #endif
 
-
+/*  MMC  */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
 
 /* Initial environment variables */
 #undef CONFIG_EXTRA_ENV_SETTINGS
index 89dbf63d458895459f620bdcafc27589f963ce79..d1c2548a238df9a8eee61ad8807fcd813b9313fa 100644 (file)
@@ -277,7 +277,16 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_CMD_NET
 #endif
 
-
+/*  MMC  */
+#define CONFIG_MMC
+#ifdef CONFIG_MMC
+#define CONFIG_CMD_MMC
+#define CONFIG_FSL_ESDHC
+#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
+#define CONFIG_GENERIC_MMC
+#define CONFIG_CMD_FAT
+#define CONFIG_DOS_PARTITION
+#endif
 
 /* Initial environment variables */
 #undef CONFIG_EXTRA_ENV_SETTINGS