From: Minkyu Kang Date: Fri, 30 Oct 2009 03:14:40 +0000 (+0900) Subject: Merge branch 'master' of git://git.denx.de/u-boot-arm X-Git-Tag: v2010.09-rc1~28^2~7^2~41 X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=commitdiff_plain;h=0bf7de838096e804f0cece8f2d94905477381b6e;hp=d43bc3d2d09022bcffa1302b8f51e7fabe2dc68a Merge branch 'master' of git://git.denx.de/u-boot-arm Conflicts: board/eukrea/cpu9260/cpu9260.c drivers/serial/serial_s5pc1xx.c include/asm-arm/arch-s5pc1xx/clock.h include/asm-arm/arch-s5pc1xx/gpio.h include/asm-arm/arch-s5pc1xx/pwm.h include/asm-arm/arch-s5pc1xx/uart.h include/configs/cpu9260.h include/configs/cpuat91.h include/configs/davinci_dm355evm.h include/linux/mtd/samsung_onenand.h --- diff --git a/MAINTAINERS b/MAINTAINERS index 1bb2521867..d70a9d22d8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -612,6 +612,13 @@ Sergey Kubushyn SONATA ARM926EJS SCHMOOGIE ARM926EJS +Sandeep Paulraj + + davinci_dm355evm ARM926EJS + davinci_dm355leopard ARM926EJS + davinci_dm365evm ARM926EJS + davinci_dm6467evm ARM926EJS + Prakash Kumar cerf250 xscale @@ -628,6 +635,7 @@ Guennadi Liakhovetski Nishanth Menon + omap3_sdp3430 ARM CORTEX-A8 (OMAP3xx SoC) omap3_zoom1 ARM CORTEX-A8 (OMAP3xx SoC) David Müller diff --git a/MAKEALL b/MAKEALL index 6122e9f52e..5492d8f8df 100755 --- a/MAKEALL +++ b/MAKEALL @@ -567,6 +567,8 @@ LIST_ARM9=" \ davinci_sffsdr \ davinci_sonata \ davinci_dm355evm \ + davinci_dm355leopard \ + davinci_dm6467evm \ " ######################################################################### @@ -603,6 +605,7 @@ LIST_ARM_CORTEX_A8=" \ omap3_overo \ omap3_evm \ omap3_pandora \ + omap3_sdp3430 \ omap3_zoom1 \ omap3_zoom2 \ smdkc100 \ diff --git a/Makefile b/Makefile index 1df7e9d8ec..b91b1c0394 100644 --- a/Makefile +++ b/Makefile @@ -2927,9 +2927,15 @@ davinci_sonata_config : unconfig davinci_dm355evm_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs dm355evm davinci davinci +davinci_dm355leopard_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs dm355leopard davinci davinci + davinci_dm365evm_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs dm365evm davinci davinci +davinci_dm6467evm_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs dm6467evm davinci davinci + imx27lite_config: unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs imx27lite logicpd mx27 @@ -3138,6 +3144,9 @@ omap3_evm_config : unconfig omap3_pandora_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 pandora NULL omap3 +omap3_sdp3430_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 sdp3430 ti omap3 + omap3_zoom1_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 zoom1 logicpd omap3 diff --git a/board/LEOX/elpt860/u-boot.lds b/board/LEOX/elpt860/u-boot.lds index c6b1f94ebd..3c44b3ef29 100644 --- a/board/LEOX/elpt860/u-boot.lds +++ b/board/LEOX/elpt860/u-boot.lds @@ -80,7 +80,6 @@ SECTIONS common/env_embedded.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/LEOX/elpt860/u-boot.lds.debug b/board/LEOX/elpt860/u-boot.lds.debug index 434c9b71d3..5126083425 100644 --- a/board/LEOX/elpt860/u-boot.lds.debug +++ b/board/LEOX/elpt860/u-boot.lds.debug @@ -73,7 +73,6 @@ SECTIONS common/env_embedded.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/MAI/AmigaOneG3SE/u-boot.lds b/board/MAI/AmigaOneG3SE/u-boot.lds index 66440dacad..18510a8e7e 100644 --- a/board/MAI/AmigaOneG3SE/u-boot.lds +++ b/board/MAI/AmigaOneG3SE/u-boot.lds @@ -65,7 +65,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/Marvell/db64360/u-boot.lds b/board/Marvell/db64360/u-boot.lds index 632921ae53..d021331148 100644 --- a/board/Marvell/db64360/u-boot.lds +++ b/board/Marvell/db64360/u-boot.lds @@ -63,7 +63,6 @@ SECTIONS /* common/env_embedded.o(.text) */ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/Marvell/db64460/u-boot.lds b/board/Marvell/db64460/u-boot.lds index 632921ae53..d021331148 100644 --- a/board/Marvell/db64460/u-boot.lds +++ b/board/Marvell/db64460/u-boot.lds @@ -63,7 +63,6 @@ SECTIONS /* common/env_embedded.o(.text) */ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/RPXClassic/u-boot.lds b/board/RPXClassic/u-boot.lds index faa1c6ccad..47247ec813 100644 --- a/board/RPXClassic/u-boot.lds +++ b/board/RPXClassic/u-boot.lds @@ -67,7 +67,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/RPXClassic/u-boot.lds.debug b/board/RPXClassic/u-boot.lds.debug index ea8538900c..a2d940f048 100644 --- a/board/RPXClassic/u-boot.lds.debug +++ b/board/RPXClassic/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/RPXlite/u-boot.lds b/board/RPXlite/u-boot.lds index faa1c6ccad..47247ec813 100644 --- a/board/RPXlite/u-boot.lds +++ b/board/RPXlite/u-boot.lds @@ -67,7 +67,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/RPXlite/u-boot.lds.debug b/board/RPXlite/u-boot.lds.debug index ea8538900c..a2d940f048 100644 --- a/board/RPXlite/u-boot.lds.debug +++ b/board/RPXlite/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/RPXlite_dw/u-boot.lds b/board/RPXlite_dw/u-boot.lds index 7b7b83ba2c..7ae7be0c02 100644 --- a/board/RPXlite_dw/u-boot.lds +++ b/board/RPXlite_dw/u-boot.lds @@ -67,7 +67,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/RPXlite_dw/u-boot.lds.debug b/board/RPXlite_dw/u-boot.lds.debug index 0f6ae696d8..83fdc15011 100644 --- a/board/RPXlite_dw/u-boot.lds.debug +++ b/board/RPXlite_dw/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/RRvision/u-boot.lds b/board/RRvision/u-boot.lds index 17e6fa0e1e..f22b25fc3d 100644 --- a/board/RRvision/u-boot.lds +++ b/board/RRvision/u-boot.lds @@ -69,7 +69,6 @@ SECTIONS common/env_embedded.o (.ppcenv) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/adder/u-boot.lds b/board/adder/u-boot.lds index 186dfe666a..397ee2f053 100644 --- a/board/adder/u-boot.lds +++ b/board/adder/u-boot.lds @@ -54,7 +54,6 @@ SECTIONS { cpu/mpc8xx/start.o (.text) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.eh_frame) diff --git a/board/altera/ep1c20/ep1c20.c b/board/altera/ep1c20/ep1c20.c index c5bfb85a71..82900f7170 100644 --- a/board/altera/ep1c20/ep1c20.c +++ b/board/altera/ep1c20/ep1c20.c @@ -22,6 +22,7 @@ */ #include +#include int board_early_init_f (void) { @@ -38,3 +39,14 @@ phys_size_t initdram (int board_type) { return (0); } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} +#endif diff --git a/board/altera/ep1s10/ep1s10.c b/board/altera/ep1s10/ep1s10.c index de9bf42bdc..cf886da64a 100644 --- a/board/altera/ep1s10/ep1s10.c +++ b/board/altera/ep1s10/ep1s10.c @@ -22,6 +22,7 @@ */ #include +#include int board_early_init_f (void) { @@ -38,3 +39,14 @@ phys_size_t initdram (int board_type) { return (0); } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} +#endif diff --git a/board/altera/ep1s40/ep1s40.c b/board/altera/ep1s40/ep1s40.c index c0eca17b92..6395de7293 100644 --- a/board/altera/ep1s40/ep1s40.c +++ b/board/altera/ep1s40/ep1s40.c @@ -22,6 +22,7 @@ */ #include +#include int checkboard (void) { @@ -33,3 +34,14 @@ phys_size_t initdram (int board_type) { return (0); } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} +#endif diff --git a/board/amcc/acadia/u-boot-nand.lds b/board/amcc/acadia/u-boot-nand.lds index b769e9411f..738caa0c5f 100644 --- a/board/amcc/acadia/u-boot-nand.lds +++ b/board/amcc/acadia/u-boot-nand.lds @@ -62,7 +62,6 @@ SECTIONS . = ALIGN(0x10000); *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/amcc/acadia/u-boot.lds b/board/amcc/acadia/u-boot.lds index b7aa160a58..d37200d8bd 100644 --- a/board/amcc/acadia/u-boot.lds +++ b/board/amcc/acadia/u-boot.lds @@ -63,7 +63,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index 38186a5d37..2598f2cf41 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -542,22 +542,22 @@ void pci_target_init(struct pci_controller *hose) | Use byte reversed out routines to handle endianess. | Make this region non-prefetchable. +--------------------------------------------------------------------------*/ - out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ /*--------------------------------------------------------------------------+ * Set up Configuration registers diff --git a/board/amcc/bamboo/u-boot-nand.lds b/board/amcc/bamboo/u-boot-nand.lds index b769e9411f..738caa0c5f 100644 --- a/board/amcc/bamboo/u-boot-nand.lds +++ b/board/amcc/bamboo/u-boot-nand.lds @@ -62,7 +62,6 @@ SECTIONS . = ALIGN(0x10000); *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/amcc/bamboo/u-boot.lds b/board/amcc/bamboo/u-boot.lds index 997d844859..bcde534dfd 100644 --- a/board/amcc/bamboo/u-boot.lds +++ b/board/amcc/bamboo/u-boot.lds @@ -70,7 +70,6 @@ SECTIONS board/amcc/bamboo/bamboo.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/amcc/bubinga/u-boot.lds b/board/amcc/bubinga/u-boot.lds index b7aa160a58..d37200d8bd 100644 --- a/board/amcc/bubinga/u-boot.lds +++ b/board/amcc/bubinga/u-boot.lds @@ -63,7 +63,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index f359d2377a..91fae1917d 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -28,6 +28,7 @@ #include #include #include +#include extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ @@ -338,27 +339,27 @@ void pci_target_init(struct pci_controller * hose ) /* * Disable everything */ - out_le32((void *)PCIX0_PIM0SA, 0); /* disable */ - out_le32((void *)PCIX0_PIM1SA, 0); /* disable */ - out_le32((void *)PCIX0_PIM2SA, 0); /* disable */ - out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */ + out_le32((void *)PCIL0_PIM0SA, 0); /* disable */ + out_le32((void *)PCIL0_PIM1SA, 0); /* disable */ + out_le32((void *)PCIL0_PIM2SA, 0); /* disable */ + out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */ /* * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 * strapping options to not support sizes such as 128/256 MB. */ - out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); - out_le32((void *)PCIX0_PIM0LAH, 0); - out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1); - out_le32((void *)PCIX0_BAR0, 0); + out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); + out_le32((void *)PCIL0_PIM0LAH, 0); + out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1); + out_le32((void *)PCIL0_BAR0, 0); /* * Program the board's subsystem id/vendor id */ - out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); - out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); + out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); + out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); - out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY); + out_le16((void *)PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY); } #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ @@ -414,6 +415,8 @@ void pcie_setup_hoses(int busno) ret = ppc4xx_init_pcie_endport(i); else ret = ppc4xx_init_pcie_rootport(i); + if (ret == -ENODEV) + continue; if (ret) { printf("PCIE%d: initialization as %s failed\n", i, is_end_point(i) ? "endpoint" : "root-complex"); diff --git a/board/amcc/canyonlands/u-boot-nand.lds b/board/amcc/canyonlands/u-boot-nand.lds index d18c536158..47c6bd9211 100644 --- a/board/amcc/canyonlands/u-boot-nand.lds +++ b/board/amcc/canyonlands/u-boot-nand.lds @@ -62,7 +62,6 @@ SECTIONS . = ALIGN(0x80000); *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/amcc/canyonlands/u-boot.lds b/board/amcc/canyonlands/u-boot.lds index b768532e2b..22fb8b8d49 100644 --- a/board/amcc/canyonlands/u-boot.lds +++ b/board/amcc/canyonlands/u-boot.lds @@ -69,7 +69,6 @@ SECTIONS board/amcc/canyonlands/init.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c index e61b5de2d8..0ca1accec8 100644 --- a/board/amcc/ebony/ebony.c +++ b/board/amcc/ebony/ebony.c @@ -210,28 +210,28 @@ void pci_target_init(struct pci_controller *hose) /*--------------------------------------------------------------------------+ * Disable everything *--------------------------------------------------------------------------*/ - out32r(PCIX0_PIM0SA, 0); /* disable */ - out32r(PCIX0_PIM1SA, 0); /* disable */ - out32r(PCIX0_PIM2SA, 0); /* disable */ - out32r(PCIX0_EROMBA, 0); /* disable expansion rom */ + out32r(PCIL0_PIM0SA, 0); /* disable */ + out32r(PCIL0_PIM1SA, 0); /* disable */ + out32r(PCIL0_PIM2SA, 0); /* disable */ + out32r(PCIL0_EROMBA, 0); /* disable expansion rom */ /*--------------------------------------------------------------------------+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); - out32r(PCIX0_PIM0LAH, 0); - out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1); + out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); + out32r(PCIL0_PIM0LAH, 0); + out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1); - out32r(PCIX0_BAR0, 0); + out32r(PCIL0_BAR0, 0); /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); - out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); + out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); + out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); - out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY); + out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY); } #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ diff --git a/board/amcc/ebony/u-boot.lds b/board/amcc/ebony/u-boot.lds index d569a14cf2..4cb2e6c929 100644 --- a/board/amcc/ebony/u-boot.lds +++ b/board/amcc/ebony/u-boot.lds @@ -69,7 +69,6 @@ SECTIONS board/amcc/ebony/init.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index bcef707403..908f1a5953 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -32,6 +32,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -304,27 +305,27 @@ void pci_target_init(struct pci_controller * hose ) /*-------------------------------------------------------------------+ * Disable everything *-------------------------------------------------------------------*/ - out32r( PCIX0_PIM0SA, 0 ); /* disable */ - out32r( PCIX0_PIM1SA, 0 ); /* disable */ - out32r( PCIX0_PIM2SA, 0 ); /* disable */ - out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + out32r( PCIL0_PIM0SA, 0 ); /* disable */ + out32r( PCIL0_PIM1SA, 0 ); /* disable */ + out32r( PCIL0_PIM2SA, 0 ); /* disable */ + out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ /*-------------------------------------------------------------------+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 * strapping options to not support sizes such as 128/256 MB. *-------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIX0_PIM0LAH, 0 ); - out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - out32r( PCIX0_BAR0, 0 ); + out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); + out32r( PCIL0_PIM0LAH, 0 ); + out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + out32r( PCIL0_BAR0, 0 ); /*-------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *-------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); + out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); + out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); } #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ @@ -391,6 +392,8 @@ void pcie_setup_hoses(int busno) ret = ppc4xx_init_pcie_endport(i); else ret = ppc4xx_init_pcie_rootport(i); + if (ret == -ENODEV) + continue; if (ret) { printf("PCIE%d: initialization as %s failed\n", i, is_end_point(i) ? "endpoint" : "root-complex"); diff --git a/board/amcc/katmai/u-boot.lds b/board/amcc/katmai/u-boot.lds index 71a8b69616..f2231c28ea 100644 --- a/board/amcc/katmai/u-boot.lds +++ b/board/amcc/katmai/u-boot.lds @@ -66,7 +66,6 @@ SECTIONS board/amcc/katmai/init.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c index 5ebe69272c..5cd822a7fa 100644 --- a/board/amcc/kilauea/kilauea.c +++ b/board/amcc/kilauea/kilauea.c @@ -28,6 +28,7 @@ #include #include #include +#include #if defined(CONFIG_PCI) #include @@ -317,6 +318,8 @@ void pcie_setup_hoses(int busno) ret = ppc4xx_init_pcie_endport(i); else ret = ppc4xx_init_pcie_rootport(i); + if (ret == -ENODEV) + continue; if (ret) { printf("PCIE%d: initialization as %s failed\n", i, is_end_point(i) ? "endpoint" : "root-complex"); diff --git a/board/amcc/kilauea/u-boot-nand.lds b/board/amcc/kilauea/u-boot-nand.lds index b769e9411f..738caa0c5f 100644 --- a/board/amcc/kilauea/u-boot-nand.lds +++ b/board/amcc/kilauea/u-boot-nand.lds @@ -62,7 +62,6 @@ SECTIONS . = ALIGN(0x10000); *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/amcc/kilauea/u-boot.lds b/board/amcc/kilauea/u-boot.lds index a44613dc6e..bebb2b236a 100644 --- a/board/amcc/kilauea/u-boot.lds +++ b/board/amcc/kilauea/u-boot.lds @@ -64,7 +64,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/amcc/luan/epld.h b/board/amcc/luan/epld.h index 05362e06d7..569d78c462 100644 --- a/board/amcc/luan/epld.h +++ b/board/amcc/luan/epld.h @@ -8,8 +8,8 @@ #define EPLD0_FLASH_SRAM_SEL_N 0x01 /* 0 SRAM at mem top, 1 small flash at mem top */ #define EPLD1_CLK_CNTL0 0x80 /* FSEL-FB1 of MPC9772 */ -#define EPLD1_PCIX0_CNTL1 0x40 /* S*0 of 9531 */ -#define EPLD1_PCIX0_CNTL2 0x20 /* S*1 of 9531 */ +#define EPLD1_PCIL0_CNTL1 0x40 /* S*0 of 9531 */ +#define EPLD1_PCIL0_CNTL2 0x20 /* S*1 of 9531 */ #define EPLD1_CLK_CNTL3 0x10 /* FSEL-B1 of MPC9772 */ #define EPLD1_CLK_CNTL4 0x08 /* FSEL-B0 of MPC9772 */ #define EPLD1_MASTER_CLOCK6 0x04 /* clock source select 6 */ @@ -29,25 +29,25 @@ #define EPLD3_STATUS_LED2 0x02 /* status LED 2 (1 = LED on) */ #define EPLD3_STATUS_LED1 0x01 /* status LED 1 (1 = LED on) */ -#define EPLD4_PCIX0_VTH1 0x80 /* PCI-X 0 VTH1 status */ -#define EPLD4_PCIX0_VTH2 0x40 /* PCI-X 0 VTH2 status */ -#define EPLD4_PCIX0_VTH3 0x20 /* PCI-X 0 VTH3 status */ -#define EPLD4_PCIX0_VTH4 0x10 /* PCI-X 0 VTH4 status */ +#define EPLD4_PCIL0_VTH1 0x80 /* PCI-X 0 VTH1 status */ +#define EPLD4_PCIL0_VTH2 0x40 /* PCI-X 0 VTH2 status */ +#define EPLD4_PCIL0_VTH3 0x20 /* PCI-X 0 VTH3 status */ +#define EPLD4_PCIL0_VTH4 0x10 /* PCI-X 0 VTH4 status */ #define EPLD4_PCIX1_VTH1 0x08 /* PCI-X 1 VTH1 status */ #define EPLD4_PCIX1_VTH2 0x04 /* PCI-X 1 VTH2 status */ #define EPLD4_PCIX1_VTH3 0x02 /* PCI-X 1 VTH3 status */ #define EPLD4_PCIX1_VTH4 0x01 /* PCI-X 1 VTH4 status */ -#define EPLD5_PCIX0_INT0 0x80 /* PCIX0 INT0 status, write 0 to reset */ -#define EPLD5_PCIX0_INT1 0x40 /* PCIX0 INT1 status, write 0 to reset */ -#define EPLD5_PCIX0_INT2 0x20 /* PCIX0 INT2 status, write 0 to reset */ -#define EPLD5_PCIX0_INT3 0x10 /* PCIX0 INT3 status, write 0 to reset */ +#define EPLD5_PCIL0_INT0 0x80 /* PCIX0 INT0 status, write 0 to reset */ +#define EPLD5_PCIL0_INT1 0x40 /* PCIX0 INT1 status, write 0 to reset */ +#define EPLD5_PCIL0_INT2 0x20 /* PCIX0 INT2 status, write 0 to reset */ +#define EPLD5_PCIL0_INT3 0x10 /* PCIX0 INT3 status, write 0 to reset */ #define EPLD5_PCIX1_INT0 0x08 /* PCIX1 INT0 status, write 0 to reset */ #define EPLD5_PCIX1_INT1 0x04 /* PCIX1 INT1 status, write 0 to reset */ #define EPLD5_PCIX1_INT2 0x02 /* PCIX1 INT2 status, write 0 to reset */ #define EPLD5_PCIX1_INT3 0x01 /* PCIX1 INT3 status, write 0 to reset */ -#define EPLD6_PCIX0_RESET_CTL 0x80 /* 0=enable slot reset, 1=disable slot reset */ +#define EPLD6_PCIL0_RESET_CTL 0x80 /* 0=enable slot reset, 1=disable slot reset */ #define EPLD6_PCIX1_RESET_CTL 0x40 /* 0=enable slot reset, 1=disable slot reset */ #define EPLD6_ETH_INT_MODE 0x20 /* 0=IRQ5 recv's external eth int */ #define EPLD6_PCIX2_RESET_CTL 0x10 /* 0=enable slot reset, 1=disable slot reset */ diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index 5f76672fb5..a04f2af3b8 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -173,28 +173,28 @@ void pci_target_init(struct pci_controller *hose) /*--------------------------------------------------------------------------+ * Disable everything *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0SA, 0 ); /* disable */ - out32r( PCIX0_PIM1SA, 0 ); /* disable */ - out32r( PCIX0_PIM2SA, 0 ); /* disable */ - out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + out32r( PCIL0_PIM0SA, 0 ); /* disable */ + out32r( PCIL0_PIM1SA, 0 ); /* disable */ + out32r( PCIL0_PIM2SA, 0 ); /* disable */ + out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ /*--------------------------------------------------------------------------+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIX0_PIM0LAH, 0 ); - out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); + out32r( PCIL0_PIM0LAH, 0 ); + out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - out32r( PCIX0_BAR0, 0 ); + out32r( PCIL0_BAR0, 0 ); /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); + out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); + out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); } #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ diff --git a/board/amcc/luan/u-boot.lds b/board/amcc/luan/u-boot.lds index 7c1bc82d73..12c5b60fc7 100644 --- a/board/amcc/luan/u-boot.lds +++ b/board/amcc/luan/u-boot.lds @@ -69,7 +69,6 @@ SECTIONS board/amcc/luan/init.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c index fb0e7b75eb..d4277dda99 100644 --- a/board/amcc/makalu/makalu.c +++ b/board/amcc/makalu/makalu.c @@ -29,6 +29,7 @@ #include #include #include +#include #if defined(CONFIG_PCI) #include @@ -273,6 +274,8 @@ void pcie_setup_hoses(int busno) ret = ppc4xx_init_pcie_endport(i); else ret = ppc4xx_init_pcie_rootport(i); + if (ret == -ENODEV) + continue; if (ret) { printf("PCIE%d: initialization as %s failed\n", i, is_end_point(i) ? "endpoint" : "root-complex"); diff --git a/board/amcc/makalu/u-boot.lds b/board/amcc/makalu/u-boot.lds index a44613dc6e..bebb2b236a 100644 --- a/board/amcc/makalu/u-boot.lds +++ b/board/amcc/makalu/u-boot.lds @@ -64,7 +64,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c index d776edabcd..0aa317ec0e 100644 --- a/board/amcc/ocotea/ocotea.c +++ b/board/amcc/ocotea/ocotea.c @@ -321,28 +321,28 @@ void pci_target_init(struct pci_controller * hose ) /*--------------------------------------------------------------------------+ * Disable everything *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0SA, 0 ); /* disable */ - out32r( PCIX0_PIM1SA, 0 ); /* disable */ - out32r( PCIX0_PIM2SA, 0 ); /* disable */ - out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + out32r( PCIL0_PIM0SA, 0 ); /* disable */ + out32r( PCIL0_PIM1SA, 0 ); /* disable */ + out32r( PCIL0_PIM2SA, 0 ); /* disable */ + out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ /*--------------------------------------------------------------------------+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIX0_PIM0LAH, 0 ); - out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); + out32r( PCIL0_PIM0LAH, 0 ); + out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - out32r( PCIX0_BAR0, 0 ); + out32r( PCIL0_BAR0, 0 ); /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); + out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); + out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); } #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ diff --git a/board/amcc/ocotea/u-boot.lds b/board/amcc/ocotea/u-boot.lds index 95cac85c96..b0b4c00fd3 100644 --- a/board/amcc/ocotea/u-boot.lds +++ b/board/amcc/ocotea/u-boot.lds @@ -69,7 +69,6 @@ SECTIONS board/amcc/ocotea/init.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/amcc/redwood/u-boot.lds b/board/amcc/redwood/u-boot.lds index 32eff525d6..7bda06eb03 100644 --- a/board/amcc/redwood/u-boot.lds +++ b/board/amcc/redwood/u-boot.lds @@ -73,7 +73,6 @@ SECTIONS /* common/env_embedded.o(.text)*/ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index 17f831c3f4..d42c802538 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -428,26 +428,26 @@ void pci_target_init(struct pci_controller *hose) * Use byte reversed out routines to handle endianess. * Make this region non-prefetchable. */ - out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ + out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */ + out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */ /* and enable region */ - out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */ + out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */ + out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */ /* and enable region */ - out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ /* * Set up Configuration registers diff --git a/board/amcc/sequoia/u-boot-nand.lds b/board/amcc/sequoia/u-boot-nand.lds index b580e0bd10..fb629e0c5e 100644 --- a/board/amcc/sequoia/u-boot-nand.lds +++ b/board/amcc/sequoia/u-boot-nand.lds @@ -62,7 +62,6 @@ SECTIONS . = ALIGN(0x10000); *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/amcc/sequoia/u-boot-ram.lds b/board/amcc/sequoia/u-boot-ram.lds index 9393b65178..e22dbecbf7 100644 --- a/board/amcc/sequoia/u-boot-ram.lds +++ b/board/amcc/sequoia/u-boot-ram.lds @@ -53,7 +53,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/amcc/sequoia/u-boot.lds b/board/amcc/sequoia/u-boot.lds index 7798722eb9..b9ec56bb20 100644 --- a/board/amcc/sequoia/u-boot.lds +++ b/board/amcc/sequoia/u-boot.lds @@ -68,7 +68,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/amcc/taihu/u-boot.lds b/board/amcc/taihu/u-boot.lds index b7aa160a58..d37200d8bd 100644 --- a/board/amcc/taihu/u-boot.lds +++ b/board/amcc/taihu/u-boot.lds @@ -63,7 +63,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/amcc/taishan/showinfo.c b/board/amcc/taishan/showinfo.c index e4e441b319..a9a80e5b6e 100644 --- a/board/amcc/taishan/showinfo.c +++ b/board/amcc/taishan/showinfo.c @@ -39,13 +39,13 @@ void show_reset_reg(void) mfcpr(CPR0_PLLD,reg); printf("cpr_plld = %#010lx\n",reg); - mfcpr(CPR0_PRIMAD,reg); + mfcpr(CPR0_PRIMAD0,reg); printf("cpr_primad = %#010lx\n",reg); - mfcpr(CPR0_PRIMBD,reg); + mfcpr(CPR0_PRIMBD0,reg); printf("cpr_primbd = %#010lx\n",reg); - mfcpr(CPR0_OPBD,reg); + mfcpr(CPR0_OPBD0,reg); printf("cpr_opbd = %#010lx\n",reg); mfcpr(CPR0_PERD,reg); @@ -106,59 +106,59 @@ void show_xbridge_info(void) printf("SDR0_XPLLD = %#010lx\n", reg); printf("PCI-X Bridge Configure registers\n"); - printf("PCIX0_VENDID = %#06x\n", in16r(PCIX0_VENDID)); - printf("PCIX0_DEVID = %#06x\n", in16r(PCIX0_DEVID)); - printf("PCIX0_CMD = %#06x\n", in16r(PCIX0_CMD)); - printf("PCIX0_STATUS = %#06x\n", in16r(PCIX0_STATUS)); - printf("PCIX0_REVID = %#04x\n", in8(PCIX0_REVID)); - printf("PCIX0_CACHELS = %#04x\n", in8(PCIX0_CACHELS)); - printf("PCIX0_LATTIM = %#04x\n", in8(PCIX0_LATTIM)); - printf("PCIX0_HDTYPE = %#04x\n", in8(PCIX0_HDTYPE)); - printf("PCIX0_BIST = %#04x\n", in8(PCIX0_BIST)); - - printf("PCIX0_BAR0 = %#010lx\n", in32r(PCIX0_BAR0)); - printf("PCIX0_BAR1 = %#010lx\n", in32r(PCIX0_BAR1)); - printf("PCIX0_BAR2 = %#010lx\n", in32r(PCIX0_BAR2)); - printf("PCIX0_BAR3 = %#010lx\n", in32r(PCIX0_BAR3)); - printf("PCIX0_BAR4 = %#010lx\n", in32r(PCIX0_BAR4)); - printf("PCIX0_BAR5 = %#010lx\n", in32r(PCIX0_BAR5)); - - printf("PCIX0_CISPTR = %#010lx\n", in32r(PCIX0_CISPTR)); - printf("PCIX0_SBSSYSVID = %#010x\n", in16r(PCIX0_SBSYSVID)); - printf("PCIX0_SBSSYSID = %#010x\n", in16r(PCIX0_SBSYSID)); - printf("PCIX0_EROMBA = %#010lx\n", in32r(PCIX0_EROMBA)); - printf("PCIX0_CAP = %#04x\n", in8(PCIX0_CAP)); - printf("PCIX0_INTLN = %#04x\n", in8(PCIX0_INTLN)); - printf("PCIX0_INTPN = %#04x\n", in8(PCIX0_INTPN)); - printf("PCIX0_MINGNT = %#04x\n", in8(PCIX0_MINGNT)); - printf("PCIX0_MAXLTNCY = %#04x\n", in8(PCIX0_MAXLTNCY)); - - printf("PCIX0_BRDGOPT1 = %#010lx\n", in32r(PCIX0_BRDGOPT1)); - printf("PCIX0_BRDGOPT2 = %#010lx\n", in32r(PCIX0_BRDGOPT2)); - - printf("PCIX0_POM0LAL = %#010lx\n", in32r(PCIX0_POM0LAL)); - printf("PCIX0_POM0LAH = %#010lx\n", in32r(PCIX0_POM0LAH)); - printf("PCIX0_POM0SA = %#010lx\n", in32r(PCIX0_POM0SA)); - printf("PCIX0_POM0PCILAL = %#010lx\n", in32r(PCIX0_POM0PCIAL)); - printf("PCIX0_POM0PCILAH = %#010lx\n", in32r(PCIX0_POM0PCIAH)); - printf("PCIX0_POM1LAL = %#010lx\n", in32r(PCIX0_POM1LAL)); - printf("PCIX0_POM1LAH = %#010lx\n", in32r(PCIX0_POM1LAH)); - printf("PCIX0_POM1SA = %#010lx\n", in32r(PCIX0_POM1SA)); - printf("PCIX0_POM1PCILAL = %#010lx\n", in32r(PCIX0_POM1PCIAL)); - printf("PCIX0_POM1PCILAH = %#010lx\n", in32r(PCIX0_POM1PCIAH)); - printf("PCIX0_POM2SA = %#010lx\n", in32r(PCIX0_POM2SA)); - - printf("PCIX0_PIM0SA = %#010lx\n", in32r(PCIX0_PIM0SA)); - printf("PCIX0_PIM0LAL = %#010lx\n", in32r(PCIX0_PIM0LAL)); - printf("PCIX0_PIM0LAH = %#010lx\n", in32r(PCIX0_PIM0LAH)); - printf("PCIX0_PIM1SA = %#010lx\n", in32r(PCIX0_PIM1SA)); - printf("PCIX0_PIM1LAL = %#010lx\n", in32r(PCIX0_PIM1LAL)); - printf("PCIX0_PIM1LAH = %#010lx\n", in32r(PCIX0_PIM1LAH)); - printf("PCIX0_PIM2SA = %#010lx\n", in32r(PCIX0_PIM1SA)); - printf("PCIX0_PIM2LAL = %#010lx\n", in32r(PCIX0_PIM1LAL)); - printf("PCIX0_PIM2LAH = %#010lx\n", in32r(PCIX0_PIM1LAH)); - - printf("PCIX0_XSTS = %#010lx\n", in32r(PCIX0_STS)); + printf("PCIL0_VENDID = %#06x\n", in16r(PCIL0_VENDID)); + printf("PCIL0_DEVID = %#06x\n", in16r(PCIL0_DEVID)); + printf("PCIL0_CMD = %#06x\n", in16r(PCIL0_CMD)); + printf("PCIL0_STATUS = %#06x\n", in16r(PCIL0_STATUS)); + printf("PCIL0_REVID = %#04x\n", in8(PCIL0_REVID)); + printf("PCIL0_CACHELS = %#04x\n", in8(PCIL0_CACHELS)); + printf("PCIL0_LATTIM = %#04x\n", in8(PCIL0_LATTIM)); + printf("PCIL0_HDTYPE = %#04x\n", in8(PCIL0_HDTYPE)); + printf("PCIL0_BIST = %#04x\n", in8(PCIL0_BIST)); + + printf("PCIL0_BAR0 = %#010lx\n", in32r(PCIL0_BAR0)); + printf("PCIL0_BAR1 = %#010lx\n", in32r(PCIL0_BAR1)); + printf("PCIL0_BAR2 = %#010lx\n", in32r(PCIL0_BAR2)); + printf("PCIL0_BAR3 = %#010lx\n", in32r(PCIL0_BAR3)); + printf("PCIL0_BAR4 = %#010lx\n", in32r(PCIL0_BAR4)); + printf("PCIL0_BAR5 = %#010lx\n", in32r(PCIL0_BAR5)); + + printf("PCIL0_CISPTR = %#010lx\n", in32r(PCIL0_CISPTR)); + printf("PCIL0_SBSSYSVID = %#010x\n", in16r(PCIL0_SBSYSVID)); + printf("PCIL0_SBSSYSID = %#010x\n", in16r(PCIL0_SBSYSID)); + printf("PCIL0_EROMBA = %#010lx\n", in32r(PCIL0_EROMBA)); + printf("PCIL0_CAP = %#04x\n", in8(PCIL0_CAP)); + printf("PCIL0_INTLN = %#04x\n", in8(PCIL0_INTLN)); + printf("PCIL0_INTPN = %#04x\n", in8(PCIL0_INTPN)); + printf("PCIL0_MINGNT = %#04x\n", in8(PCIL0_MINGNT)); + printf("PCIL0_MAXLTNCY = %#04x\n", in8(PCIL0_MAXLTNCY)); + + printf("PCIL0_BRDGOPT1 = %#010lx\n", in32r(PCIL0_BRDGOPT1)); + printf("PCIL0_BRDGOPT2 = %#010lx\n", in32r(PCIL0_BRDGOPT2)); + + printf("PCIL0_POM0LAL = %#010lx\n", in32r(PCIL0_POM0LAL)); + printf("PCIL0_POM0LAH = %#010lx\n", in32r(PCIL0_POM0LAH)); + printf("PCIL0_POM0SA = %#010lx\n", in32r(PCIL0_POM0SA)); + printf("PCIL0_POM0PCILAL = %#010lx\n", in32r(PCIL0_POM0PCIAL)); + printf("PCIL0_POM0PCILAH = %#010lx\n", in32r(PCIL0_POM0PCIAH)); + printf("PCIL0_POM1LAL = %#010lx\n", in32r(PCIL0_POM1LAL)); + printf("PCIL0_POM1LAH = %#010lx\n", in32r(PCIL0_POM1LAH)); + printf("PCIL0_POM1SA = %#010lx\n", in32r(PCIL0_POM1SA)); + printf("PCIL0_POM1PCILAL = %#010lx\n", in32r(PCIL0_POM1PCIAL)); + printf("PCIL0_POM1PCILAH = %#010lx\n", in32r(PCIL0_POM1PCIAH)); + printf("PCIL0_POM2SA = %#010lx\n", in32r(PCIL0_POM2SA)); + + printf("PCIL0_PIM0SA = %#010lx\n", in32r(PCIL0_PIM0SA)); + printf("PCIL0_PIM0LAL = %#010lx\n", in32r(PCIL0_PIM0LAL)); + printf("PCIL0_PIM0LAH = %#010lx\n", in32r(PCIL0_PIM0LAH)); + printf("PCIL0_PIM1SA = %#010lx\n", in32r(PCIL0_PIM1SA)); + printf("PCIL0_PIM1LAL = %#010lx\n", in32r(PCIL0_PIM1LAL)); + printf("PCIL0_PIM1LAH = %#010lx\n", in32r(PCIL0_PIM1LAH)); + printf("PCIL0_PIM2SA = %#010lx\n", in32r(PCIL0_PIM1SA)); + printf("PCIL0_PIM2LAL = %#010lx\n", in32r(PCIL0_PIM1LAL)); + printf("PCIL0_PIM2LAH = %#010lx\n", in32r(PCIL0_PIM1LAH)); + + printf("PCIL0_XSTS = %#010lx\n", in32r(PCIL0_STS)); } int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c index 4a0573eb38..0c20faf9ab 100644 --- a/board/amcc/taishan/taishan.c +++ b/board/amcc/taishan/taishan.c @@ -254,28 +254,28 @@ void pci_target_init(struct pci_controller * hose ) /*--------------------------------------------------------------------------+ * Disable everything *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0SA, 0 ); /* disable */ - out32r( PCIX0_PIM1SA, 0 ); /* disable */ - out32r( PCIX0_PIM2SA, 0 ); /* disable */ - out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + out32r( PCIL0_PIM0SA, 0 ); /* disable */ + out32r( PCIL0_PIM1SA, 0 ); /* disable */ + out32r( PCIL0_PIM2SA, 0 ); /* disable */ + out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ /*--------------------------------------------------------------------------+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIX0_PIM0LAH, 0 ); - out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); + out32r( PCIL0_PIM0LAH, 0 ); + out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - out32r( PCIX0_BAR0, 0 ); + out32r( PCIL0_BAR0, 0 ); /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); + out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); + out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); } #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ diff --git a/board/amcc/taishan/u-boot.lds b/board/amcc/taishan/u-boot.lds index 75b7fc9a24..c043f69ee7 100644 --- a/board/amcc/taishan/u-boot.lds +++ b/board/amcc/taishan/u-boot.lds @@ -69,7 +69,6 @@ SECTIONS board/amcc/taishan/init.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/amcc/walnut/u-boot.lds b/board/amcc/walnut/u-boot.lds index f6cbe137ca..d7a78570e3 100644 --- a/board/amcc/walnut/u-boot.lds +++ b/board/amcc/walnut/u-boot.lds @@ -63,7 +63,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/amcc/yosemite/u-boot.lds b/board/amcc/yosemite/u-boot.lds index e31f071184..b8646d539e 100644 --- a/board/amcc/yosemite/u-boot.lds +++ b/board/amcc/yosemite/u-boot.lds @@ -69,7 +69,6 @@ SECTIONS board/amcc/yosemite/init.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 1ec13eb6b5..7ceccfa9b9 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -408,22 +408,22 @@ void pci_target_init(struct pci_controller *hose) | Use byte reversed out routines to handle endianess. | Make this region non-prefetchable. +--------------------------------------------------------------------------*/ - out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ /*--------------------------------------------------------------------------+ * Set up Configuration registers diff --git a/board/amcc/yucca/u-boot.lds b/board/amcc/yucca/u-boot.lds index 60135b9b72..2d44c6478f 100644 --- a/board/amcc/yucca/u-boot.lds +++ b/board/amcc/yucca/u-boot.lds @@ -69,7 +69,6 @@ SECTIONS board/amcc/yucca/init.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 033bdd20fa..d8f4bcbb17 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -32,6 +32,7 @@ #include #include #include +#include #include "yucca.h" @@ -632,27 +633,27 @@ void pci_target_init(struct pci_controller * hose ) /*-------------------------------------------------------------------+ * Disable everything *-------------------------------------------------------------------*/ - out32r( PCIX0_PIM0SA, 0 ); /* disable */ - out32r( PCIX0_PIM1SA, 0 ); /* disable */ - out32r( PCIX0_PIM2SA, 0 ); /* disable */ - out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + out32r( PCIL0_PIM0SA, 0 ); /* disable */ + out32r( PCIL0_PIM1SA, 0 ); /* disable */ + out32r( PCIL0_PIM2SA, 0 ); /* disable */ + out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ /*-------------------------------------------------------------------+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 * strapping options to not support sizes such as 128/256 MB. *-------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIX0_PIM0LAH, 0 ); - out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - out32r( PCIX0_BAR0, 0 ); + out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); + out32r( PCIL0_PIM0LAH, 0 ); + out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + out32r( PCIL0_BAR0, 0 ); /*-------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *-------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); + out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); + out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); } #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ @@ -830,6 +831,8 @@ void pcie_setup_hoses(int busno) yucca_setup_pcie_fpga_rootpoint(i); ret = ppc4xx_init_pcie_rootport(i); } + if (ret == -ENODEV) + continue; if (ret) { printf("PCIE%d: initialization as %s failed\n", i, is_end_point(i) ? "endpoint" : "root-complex"); diff --git a/board/amirix/ap1000/u-boot.lds b/board/amirix/ap1000/u-boot.lds index a4c48d6cac..707203d60f 100644 --- a/board/amirix/ap1000/u-boot.lds +++ b/board/amirix/ap1000/u-boot.lds @@ -72,7 +72,6 @@ SECTIONS /* common/env_embedded.o(.text)*/ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/armltd/integrator/integrator.c b/board/armltd/integrator/integrator.c index a46deea448..518944e077 100644 --- a/board/armltd/integrator/integrator.c +++ b/board/armltd/integrator/integrator.c @@ -34,9 +34,7 @@ */ #include -#ifdef CONFIG_PCI #include -#endif DECLARE_GLOBAL_DATA_PTR; @@ -127,9 +125,16 @@ extern void dram_query(void); return 0; } -#ifdef CONFIG_PCI +#ifdef CONFIG_CMD_NET int board_eth_init(bd_t *bis) { - return pci_eth_init(bis); + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif +#ifdef CONFIG_PCI + rc += pci_eth_init(bis); +#endif + return rc; } #endif diff --git a/board/armltd/versatile/versatile.c b/board/armltd/versatile/versatile.c index 197bc896ac..6e836dd1f9 100644 --- a/board/armltd/versatile/versatile.c +++ b/board/armltd/versatile/versatile.c @@ -34,6 +34,7 @@ */ #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -89,3 +90,14 @@ int dram_init (void) { return 0; } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} +#endif diff --git a/board/bf533-ezkit/bf533-ezkit.c b/board/bf533-ezkit/bf533-ezkit.c index d5f0b7c689..8727dee6d9 100644 --- a/board/bf533-ezkit/bf533-ezkit.c +++ b/board/bf533-ezkit/bf533-ezkit.c @@ -26,6 +26,7 @@ */ #include +#include #include "psd4256.h" #include "flash-defines.h" @@ -57,3 +58,10 @@ int misc_init_r(void) return 0; } + +#ifdef CONFIG_SMC91111 +int board_eth_init(bd_t *bis) +{ + return smc91111_initialize(0, CONFIG_SMC91111_BASE); +} +#endif diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c index 7108ddae45..a2269105be 100644 --- a/board/bf533-stamp/bf533-stamp.c +++ b/board/bf533-stamp/bf533-stamp.c @@ -26,6 +26,7 @@ */ #include +#include #include #include "bf533-stamp.h" @@ -283,3 +284,10 @@ void __led_toggle(led_id_t mask) } #endif + +#ifdef CONFIG_SMC91111 +int board_eth_init(bd_t *bis) +{ + return smc91111_initialize(0, CONFIG_SMC91111_BASE); +} +#endif diff --git a/board/bf538f-ezkit/bf538f-ezkit.c b/board/bf538f-ezkit/bf538f-ezkit.c index bbee989675..15916fad64 100644 --- a/board/bf538f-ezkit/bf538f-ezkit.c +++ b/board/bf538f-ezkit/bf538f-ezkit.c @@ -7,6 +7,7 @@ */ #include +#include #include #include @@ -25,3 +26,10 @@ phys_size_t initdram(int board_type) gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; return gd->bd->bi_memsize; } + +#ifdef CONFIG_SMC91111 +int board_eth_init(bd_t *bis) +{ + return smc91111_initialize(0, CONFIG_SMC91111_BASE); +} +#endif diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c index 5aede174d8..e5d7eb3388 100644 --- a/board/bf561-ezkit/bf561-ezkit.c +++ b/board/bf561-ezkit/bf561-ezkit.c @@ -26,6 +26,7 @@ */ #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -43,3 +44,10 @@ phys_size_t initdram(int board_type) gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; return gd->bd->bi_memsize; } + +#ifdef CONFIG_SMC91111 +int board_eth_init(bd_t *bis) +{ + return smc91111_initialize(0, CONFIG_SMC91111_BASE); +} +#endif diff --git a/board/blackstamp/blackstamp.c b/board/blackstamp/blackstamp.c index b671899e06..f55ab975e4 100644 --- a/board/blackstamp/blackstamp.c +++ b/board/blackstamp/blackstamp.c @@ -12,6 +12,7 @@ */ #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -44,3 +45,10 @@ void swap_to(int device_id) SSYNC(); } #endif + +#ifdef CONFIG_SMC91111 +int board_eth_init(bd_t *bis) +{ + return smc91111_initialize(0, CONFIG_SMC91111_BASE); +} +#endif diff --git a/board/c2mon/u-boot.lds b/board/c2mon/u-boot.lds index 61650a85fa..2d0efb3161 100644 --- a/board/c2mon/u-boot.lds +++ b/board/c2mon/u-boot.lds @@ -66,7 +66,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/c2mon/u-boot.lds.debug b/board/c2mon/u-boot.lds.debug index dbec9860a9..ad36953915 100644 --- a/board/c2mon/u-boot.lds.debug +++ b/board/c2mon/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/cerf250/cerf250.c b/board/cerf250/cerf250.c index 307894fd61..59346bc6d4 100644 --- a/board/cerf250/cerf250.c +++ b/board/cerf250/cerf250.c @@ -26,6 +26,7 @@ */ #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -71,3 +72,14 @@ int dram_init (void) return 0; } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} +#endif diff --git a/board/cm-bf533/cm-bf533.c b/board/cm-bf533/cm-bf533.c index 7eb761dcc8..ab0bf3bf65 100644 --- a/board/cm-bf533/cm-bf533.c +++ b/board/cm-bf533/cm-bf533.c @@ -7,6 +7,7 @@ */ #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -23,3 +24,10 @@ phys_size_t initdram(int board_type) gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; return gd->bd->bi_memsize; } + +#ifdef CONFIG_SMC91111 +int board_eth_init(bd_t *bis) +{ + return smc91111_initialize(0, CONFIG_SMC91111_BASE); +} +#endif diff --git a/board/cm-bf561/cm-bf561.c b/board/cm-bf561/cm-bf561.c index 5bce9eb59d..f21a015e42 100644 --- a/board/cm-bf561/cm-bf561.c +++ b/board/cm-bf561/cm-bf561.c @@ -7,6 +7,7 @@ */ #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -23,3 +24,10 @@ phys_size_t initdram(int board_type) gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE; return gd->bd->bi_memsize; } + +#ifdef CONFIG_SMC91111 +int board_eth_init(bd_t *bis) +{ + return smc91111_initialize(0, CONFIG_SMC91111_BASE); +} +#endif diff --git a/board/cm5200/u-boot.lds b/board/cm5200/u-boot.lds index 3a72bd32f2..5887f774e9 100644 --- a/board/cm5200/u-boot.lds +++ b/board/cm5200/u-boot.lds @@ -52,7 +52,6 @@ SECTIONS { cpu/mpc5xxx/start.o (.text) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.eh_frame) diff --git a/board/cogent/u-boot.lds b/board/cogent/u-boot.lds index 3ea6f1c4dd..2fecb0fcf6 100644 --- a/board/cogent/u-boot.lds +++ b/board/cogent/u-boot.lds @@ -54,7 +54,6 @@ SECTIONS { *(.text) common/env_embedded.o(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/cogent/u-boot.lds.debug b/board/cogent/u-boot.lds.debug index ea8538900c..a2d940f048 100644 --- a/board/cogent/u-boot.lds.debug +++ b/board/cogent/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/cradle/cradle.c b/board/cradle/cradle.c index 6d8d55570f..21eb6550db 100644 --- a/board/cradle/cradle.c +++ b/board/cradle/cradle.c @@ -27,6 +27,7 @@ #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -223,3 +224,14 @@ dram_init (void) PHYS_SDRAM_3_SIZE + PHYS_SDRAM_4_SIZE ); } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} +#endif diff --git a/board/cray/L1/u-boot.lds b/board/cray/L1/u-boot.lds index 86c8ecbb83..bd80df6102 100644 --- a/board/cray/L1/u-boot.lds +++ b/board/cray/L1/u-boot.lds @@ -78,7 +78,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/cray/L1/u-boot.lds.debug b/board/cray/L1/u-boot.lds.debug index 338392a075..970628d556 100644 --- a/board/cray/L1/u-boot.lds.debug +++ b/board/cray/L1/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/csb272/u-boot.lds b/board/csb272/u-boot.lds index 0aa6f8f9c1..b58ccc5f82 100644 --- a/board/csb272/u-boot.lds +++ b/board/csb272/u-boot.lds @@ -79,7 +79,6 @@ SECTIONS /* common/env_embedded.o(.text)*/ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/csb472/u-boot.lds b/board/csb472/u-boot.lds index 565e021187..ba37c1b79e 100644 --- a/board/csb472/u-boot.lds +++ b/board/csb472/u-boot.lds @@ -79,7 +79,6 @@ SECTIONS /* common/env_embedded.o(.text)*/ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/dave/PPChameleonEVB/u-boot.lds b/board/dave/PPChameleonEVB/u-boot.lds index b36827d0ef..ee7f59ec85 100644 --- a/board/dave/PPChameleonEVB/u-boot.lds +++ b/board/dave/PPChameleonEVB/u-boot.lds @@ -73,7 +73,6 @@ SECTIONS lib_generic/zlib.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/davinci/dm355evm/dm355evm.c b/board/davinci/dm355evm/dm355evm.c index 0a44748320..87f284c4ce 100644 --- a/board/davinci/dm355evm/dm355evm.c +++ b/board/davinci/dm355evm/dm355evm.c @@ -92,8 +92,8 @@ int board_eth_init(bd_t *bis) static void nand_dm355evm_select_chip(struct mtd_info *mtd, int chip) { struct nand_chip *this = mtd->priv; - u32 wbase = (u32) this->IO_ADDR_W; - u32 rbase = (u32) this->IO_ADDR_R; + unsigned long wbase = (unsigned long) this->IO_ADDR_W; + unsigned long rbase = (unsigned long) this->IO_ADDR_R; if (chip == 1) { __set_bit(14, &wbase); diff --git a/board/davinci/dm355leopard/Makefile b/board/davinci/dm355leopard/Makefile new file mode 100644 index 0000000000..26b0705465 --- /dev/null +++ b/board/davinci/dm355leopard/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o +SOBJS := + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/davinci/dm355leopard/config.mk b/board/davinci/dm355leopard/config.mk new file mode 100644 index 0000000000..d67df02ccf --- /dev/null +++ b/board/davinci/dm355leopard/config.mk @@ -0,0 +1,6 @@ +# Linux Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) +# + +#Provide at least 16MB spacing between us and the Linux Kernel image +TEXT_BASE = 0x81080000 diff --git a/board/davinci/dm355leopard/dm355leopard.c b/board/davinci/dm355leopard/dm355leopard.c new file mode 100644 index 0000000000..e89786ed1a --- /dev/null +++ b/board/davinci/dm355leopard/dm355leopard.c @@ -0,0 +1,98 @@ +/* + * Copyright (C) 2009 Texas Instruments Incorporated + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include +#include "../common/misc.h" +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + struct davinci_gpio *gpio01_base = + (struct davinci_gpio *)DAVINCI_GPIO_BANK01; + struct davinci_gpio *gpio23_base = + (struct davinci_gpio *)DAVINCI_GPIO_BANK23; + struct davinci_gpio *gpio67_base = + (struct davinci_gpio *)DAVINCI_GPIO_BANK67; + + gd->bd->bi_arch_number = MACH_TYPE_DM355_LEOPARD; + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + /* GIO 9 & 10 are used for IO */ + writel((readl(PINMUX3) & 0XF8FFFFFF), PINMUX3); + + /* Interrupt set GIO 9 */ + writel((readl(DAVINCI_GPIO_BINTEN) | 0x1), DAVINCI_GPIO_BINTEN); + + /* set GIO 9 input */ + writel((readl(&gpio01_base->dir) | (1 << 9)), &gpio01_base->dir); + + /* Both edge trigger GIO 9 */ + writel((readl(&gpio01_base->set_rising) | (1 << 9)), + &gpio01_base->set_rising); + writel((readl(&gpio01_base->dir) & ~(1 << 5)), &gpio01_base->dir); + + /* output low */ + writel((readl(&gpio01_base->set_data) & ~(1 << 5)), + &gpio01_base->set_data); + + /* set GIO 10 output */ + writel((readl(&gpio01_base->dir) & ~(1 << 10)), &gpio01_base->dir); + + /* output high */ + writel((readl(&gpio01_base->set_data) | (1 << 10)), + &gpio01_base->set_data); + + /* set GIO 32 output */ + writel((readl(&gpio23_base->dir) & ~(1 << 0)), &gpio23_base->dir); + + /* output High */ + writel((readl(&gpio23_base->set_data) | (1 << 0)), + &gpio23_base->set_data); + + /* Enable UART1 MUX Lines */ + writel((readl(PINMUX0) & ~3), PINMUX0); + writel((readl(&gpio67_base->dir) & ~(1 << 6)), &gpio67_base->dir); + writel((readl(&gpio67_base->set_data) | (1 << 6)), + &gpio67_base->set_data); + + return 0; +} + +#ifdef CONFIG_DRIVER_DM9000 +int board_eth_init(bd_t *bis) +{ + return dm9000_initialize(bis); +} +#endif + +#ifdef CONFIG_NAND_DAVINCI +int board_nand_init(struct nand_chip *nand) +{ + davinci_nand_init(nand); + + return 0; +} +#endif diff --git a/board/davinci/dm365evm/dm365evm.c b/board/davinci/dm365evm/dm365evm.c index 5b97060539..290eb99749 100644 --- a/board/davinci/dm365evm/dm365evm.c +++ b/board/davinci/dm365evm/dm365evm.c @@ -1,4 +1,5 @@ /* + * Copyright (C) 2009 Texas Instruments Incorporated * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -79,8 +80,8 @@ int board_eth_init(bd_t *bis) static void nand_dm365evm_select_chip(struct mtd_info *mtd, int chip) { struct nand_chip *this = mtd->priv; - u32 wbase = (u32) this->IO_ADDR_W; - u32 rbase = (u32) this->IO_ADDR_R; + unsigned long wbase = (unsigned long) this->IO_ADDR_W; + unsigned long rbase = (unsigned long) this->IO_ADDR_R; if (chip == 1) { __set_bit(14, &wbase); diff --git a/board/davinci/dm6467evm/Makefile b/board/davinci/dm6467evm/Makefile new file mode 100644 index 0000000000..26b0705465 --- /dev/null +++ b/board/davinci/dm6467evm/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o +SOBJS := + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/davinci/dm6467evm/config.mk b/board/davinci/dm6467evm/config.mk new file mode 100644 index 0000000000..ca801c2737 --- /dev/null +++ b/board/davinci/dm6467evm/config.mk @@ -0,0 +1,2 @@ +#Provide at least 16MB spacing between us and the Linux Kernel image +TEXT_BASE = 0x81080000 diff --git a/board/davinci/dm6467evm/dm6467evm.c b/board/davinci/dm6467evm/dm6467evm.c new file mode 100644 index 0000000000..960581824c --- /dev/null +++ b/board/davinci/dm6467evm/dm6467evm.c @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2009 Texas Instruments Incorporated + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_DAVINCI_DM6467_EVM; + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + diff --git a/board/delta/delta.c b/board/delta/delta.c index 84ff47e53c..a2942135fd 100644 --- a/board/delta/delta.c +++ b/board/delta/delta.c @@ -22,6 +22,7 @@ */ #include +#include #include #include #include @@ -363,3 +364,14 @@ void hw_watchdog_reset(void) i2c_reg_write(addr, SYS_CONTROL_A, val); } #endif + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} +#endif diff --git a/board/digsy_mtc/cmd_mtc.c b/board/digsy_mtc/cmd_mtc.c index aa3961153b..ecea5b3c54 100644 --- a/board/digsy_mtc/cmd_mtc.c +++ b/board/digsy_mtc/cmd_mtc.c @@ -320,36 +320,6 @@ static int do_mtc_help(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ARRAY_SIZE(cmd_mtc_sub), cmdtp, flag, argc, argv); } -/* Relocate the command table function pointers when running in RAM */ -int mtc_cmd_init_r(void) -{ - cmd_tbl_t *cmdtp; - - for (cmdtp = &cmd_mtc_sub[0]; cmdtp != - &cmd_mtc_sub[ARRAY_SIZE(cmd_mtc_sub)]; cmdtp++) { - ulong addr; - - addr = (ulong)(cmdtp->cmd) + gd->reloc_off; - cmdtp->cmd = - (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr; - - addr = (ulong)(cmdtp->name) + gd->reloc_off; - cmdtp->name = (char *)addr; - - if (cmdtp->usage) { - addr = (ulong)(cmdtp->usage) + gd->reloc_off; - cmdtp->usage = (char *)addr; - } -#ifdef CONFIG_SYS_LONGHELP - if (cmdtp->help) { - addr = (ulong)(cmdtp->help) + gd->reloc_off; - cmdtp->help = (char *)addr; - } -#endif - } - return 0; -} - int cmd_mtc(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { cmd_tbl_t *c; diff --git a/board/digsy_mtc/digsy_mtc.c b/board/digsy_mtc/digsy_mtc.c index 9d77e5485b..cc6087b339 100644 --- a/board/digsy_mtc/digsy_mtc.c +++ b/board/digsy_mtc/digsy_mtc.c @@ -240,7 +240,6 @@ void board_get_enetaddr (uchar * enet) int misc_init_r(void) { - extern int mtc_cmd_init_r (void); uchar enetaddr[6]; if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { @@ -248,7 +247,6 @@ int misc_init_r(void) eth_setenv_enetaddr("ethaddr", enetaddr); } - mtc_cmd_init_r(); return 0; } diff --git a/board/dnp1110/dnp1110.c b/board/dnp1110/dnp1110.c index ab8e7beb99..c215f5f49b 100644 --- a/board/dnp1110/dnp1110.c +++ b/board/dnp1110/dnp1110.c @@ -23,6 +23,7 @@ */ #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -53,3 +54,14 @@ int dram_init (void) return (0); } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} +#endif diff --git a/board/eltec/bab7xx/u-boot.lds b/board/eltec/bab7xx/u-boot.lds index 632921ae53..d021331148 100644 --- a/board/eltec/bab7xx/u-boot.lds +++ b/board/eltec/bab7xx/u-boot.lds @@ -63,7 +63,6 @@ SECTIONS /* common/env_embedded.o(.text) */ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/eltec/elppc/u-boot.lds b/board/eltec/elppc/u-boot.lds index 632921ae53..d021331148 100644 --- a/board/eltec/elppc/u-boot.lds +++ b/board/eltec/elppc/u-boot.lds @@ -63,7 +63,6 @@ SECTIONS /* common/env_embedded.o(.text) */ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/eltec/mhpc/u-boot.lds b/board/eltec/mhpc/u-boot.lds index ee74eb950a..5c847fbf84 100644 --- a/board/eltec/mhpc/u-boot.lds +++ b/board/eltec/mhpc/u-boot.lds @@ -56,7 +56,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/eltec/mhpc/u-boot.lds.debug b/board/eltec/mhpc/u-boot.lds.debug index dbec9860a9..ad36953915 100644 --- a/board/eltec/mhpc/u-boot.lds.debug +++ b/board/eltec/mhpc/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/emk/top860/u-boot.lds b/board/emk/top860/u-boot.lds index b4e093ca70..46dca96e60 100644 --- a/board/emk/top860/u-boot.lds +++ b/board/emk/top860/u-boot.lds @@ -55,7 +55,6 @@ SECTIONS cpu/mpc8xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/emk/top860/u-boot.lds.debug b/board/emk/top860/u-boot.lds.debug index 82e8dce830..bfe85134e5 100644 --- a/board/emk/top860/u-boot.lds.debug +++ b/board/emk/top860/u-boot.lds.debug @@ -65,7 +65,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/ep88x/u-boot.lds b/board/ep88x/u-boot.lds index b3849deda2..70b84e4c8a 100644 --- a/board/ep88x/u-boot.lds +++ b/board/ep88x/u-boot.lds @@ -54,7 +54,6 @@ SECTIONS { cpu/mpc8xx/start.o (.text) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) diff --git a/board/eric/u-boot.lds b/board/eric/u-boot.lds index e62896f12f..261ccfbc1f 100644 --- a/board/eric/u-boot.lds +++ b/board/eric/u-boot.lds @@ -78,7 +78,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/adciop/u-boot.lds b/board/esd/adciop/u-boot.lds index 2645e84c38..9207fe0bf5 100644 --- a/board/esd/adciop/u-boot.lds +++ b/board/esd/adciop/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/apc405/u-boot.lds b/board/esd/apc405/u-boot.lds index 8c010162f0..0799275fde 100644 --- a/board/esd/apc405/u-boot.lds +++ b/board/esd/apc405/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/ar405/u-boot.lds b/board/esd/ar405/u-boot.lds index 0221e3091b..2247109cb6 100644 --- a/board/esd/ar405/u-boot.lds +++ b/board/esd/ar405/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/ash405/u-boot.lds b/board/esd/ash405/u-boot.lds index 005957eedb..285c901fe6 100644 --- a/board/esd/ash405/u-boot.lds +++ b/board/esd/ash405/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/canbt/u-boot.lds b/board/esd/canbt/u-boot.lds index 0221e3091b..2247109cb6 100644 --- a/board/esd/canbt/u-boot.lds +++ b/board/esd/canbt/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/cms700/u-boot.lds b/board/esd/cms700/u-boot.lds index 8c010162f0..0799275fde 100644 --- a/board/esd/cms700/u-boot.lds +++ b/board/esd/cms700/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/common/cmd_loadpci.c b/board/esd/common/cmd_loadpci.c index 47e946f116..eecae0a7fd 100644 --- a/board/esd/common/cmd_loadpci.c +++ b/board/esd/common/cmd_loadpci.c @@ -48,7 +48,7 @@ int do_loadpci(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) u32 la, ptm1la; #if defined(CONFIG_440) - ptm1la = in32r(PCIX0_PTM1LA); + ptm1la = in32r(PCIL0_PTM1LA); #else ptm1la = in32r(PTM1LA); #endif diff --git a/board/esd/cpci2dp/u-boot.lds b/board/esd/cpci2dp/u-boot.lds index 8c010162f0..0799275fde 100644 --- a/board/esd/cpci2dp/u-boot.lds +++ b/board/esd/cpci2dp/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/cpci405/u-boot.lds b/board/esd/cpci405/u-boot.lds index 8c010162f0..0799275fde 100644 --- a/board/esd/cpci405/u-boot.lds +++ b/board/esd/cpci405/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/cpci750/u-boot.lds b/board/esd/cpci750/u-boot.lds index 632921ae53..d021331148 100644 --- a/board/esd/cpci750/u-boot.lds +++ b/board/esd/cpci750/u-boot.lds @@ -63,7 +63,6 @@ SECTIONS /* common/env_embedded.o(.text) */ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/cpciiser4/u-boot.lds b/board/esd/cpciiser4/u-boot.lds index 8c010162f0..0799275fde 100644 --- a/board/esd/cpciiser4/u-boot.lds +++ b/board/esd/cpciiser4/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/dasa_sim/u-boot.lds b/board/esd/dasa_sim/u-boot.lds index 77674b514e..b044649ebf 100644 --- a/board/esd/dasa_sim/u-boot.lds +++ b/board/esd/dasa_sim/u-boot.lds @@ -63,7 +63,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/dp405/u-boot.lds b/board/esd/dp405/u-boot.lds index 8c010162f0..0799275fde 100644 --- a/board/esd/dp405/u-boot.lds +++ b/board/esd/dp405/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/du405/u-boot.lds b/board/esd/du405/u-boot.lds index 166d0d1cda..65ad2f23be 100644 --- a/board/esd/du405/u-boot.lds +++ b/board/esd/du405/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c index 056f455d68..d0e52cbab3 100644 --- a/board/esd/du440/du440.c +++ b/board/esd/du440/du440.c @@ -435,26 +435,26 @@ void pci_target_init(struct pci_controller *hose) * Use byte reversed out routines to handle endianess. * Make this region non-prefetchable. */ - out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ + out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */ + out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */ /* and enable region */ - out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */ + out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */ + out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */ /* and enable region */ - out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ /* * Set up Configuration registers diff --git a/board/esd/du440/u-boot.lds b/board/esd/du440/u-boot.lds index 7360349dfb..3b6c09687a 100644 --- a/board/esd/du440/u-boot.lds +++ b/board/esd/du440/u-boot.lds @@ -65,7 +65,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/hh405/u-boot.lds b/board/esd/hh405/u-boot.lds index 8c010162f0..0799275fde 100644 --- a/board/esd/hh405/u-boot.lds +++ b/board/esd/hh405/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/hub405/u-boot.lds b/board/esd/hub405/u-boot.lds index 005957eedb..285c901fe6 100644 --- a/board/esd/hub405/u-boot.lds +++ b/board/esd/hub405/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/ocrtc/u-boot.lds b/board/esd/ocrtc/u-boot.lds index 1b50b6d4da..34884b69b0 100644 --- a/board/esd/ocrtc/u-boot.lds +++ b/board/esd/ocrtc/u-boot.lds @@ -75,7 +75,6 @@ SECTIONS /* common/env_embedded.o(.text)*/ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/pci405/u-boot.lds b/board/esd/pci405/u-boot.lds index 8c010162f0..0799275fde 100644 --- a/board/esd/pci405/u-boot.lds +++ b/board/esd/pci405/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/plu405/u-boot.lds b/board/esd/plu405/u-boot.lds index 005957eedb..285c901fe6 100644 --- a/board/esd/plu405/u-boot.lds +++ b/board/esd/plu405/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/pmc405/u-boot.lds b/board/esd/pmc405/u-boot.lds index 74f1d870c8..178a755ef7 100644 --- a/board/esd/pmc405/u-boot.lds +++ b/board/esd/pmc405/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/pmc405de/u-boot.lds b/board/esd/pmc405de/u-boot.lds index 8c010162f0..0799275fde 100644 --- a/board/esd/pmc405de/u-boot.lds +++ b/board/esd/pmc405de/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c index 1af431bd7d..476e940962 100644 --- a/board/esd/pmc440/cmd_pmc440.c +++ b/board/esd/pmc440/cmd_pmc440.c @@ -497,15 +497,15 @@ int do_pmm(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /* map PCI address at 0xc0000000 in PLB space */ /* PMM1 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM1MA, 0x00000000); + out32r(PCIL0_PMM1MA, 0x00000000); /* PMM1 Local Address */ - out32r(PCIX0_PMM1LA, 0xc0000000); + out32r(PCIL0_PMM1LA, 0xc0000000); /* PMM1 PCI Low Address */ - out32r(PCIX0_PMM1PCILA, pciaddr); + out32r(PCIL0_PMM1PCILA, pciaddr); /* PMM1 PCI High Address */ - out32r(PCIX0_PMM1PCIHA, 0x00000000); + out32r(PCIL0_PMM1PCIHA, 0x00000000); /* 256MB + No prefetching, and enable region */ - out32r(PCIX0_PMM1MA, 0xf0000001); + out32r(PCIL0_PMM1MA, 0xf0000001); } else { printf("Usage:\npmm %s\n", cmdtp->help); } diff --git a/board/esd/pmc440/fpga.c b/board/esd/pmc440/fpga.c index a2eda32ac8..f92bbff291 100644 --- a/board/esd/pmc440/fpga.c +++ b/board/esd/pmc440/fpga.c @@ -442,9 +442,9 @@ int pmc440_init_fpga(void) { char *s; - debug("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", - __FUNCTION__, __LINE__, gd->reloc_off); - fpga_init(gd->reloc_off); + debug("%s:%d: Initialize FPGA interface\n", + __FUNCTION__, __LINE__); + fpga_init(); fpga_serialslave_init (); debug("%s:%d: Adding fpga 0\n", __FUNCTION__, __LINE__); diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S index 26a8282cec..6585fed664 100644 --- a/board/esd/pmc440/init.S +++ b/board/esd/pmc440/init.S @@ -23,7 +23,7 @@ #include #include -/************************************************************************** +/* * TLB TABLE * * This table is used by the cpu boot code to setup the initial tlb @@ -32,7 +32,7 @@ * * Pointer to the table is returned in r1 * - *************************************************************************/ + */ .section .bootpg,"ax" .globl tlbtab @@ -49,12 +49,7 @@ tlbtab: tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G ) #endif - /* TLB-entry for DDR SDRAM (Up to 2GB) */ -#ifdef CONFIG_4xx_DCACHE - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G) -#else - tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I ) -#endif + /* TLB entries for DDR2 SDRAM are generated dynamically */ #ifdef CONFIG_SYS_INIT_RAM_DCACHE /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index f0f9bff3eb..ec9255243c 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -208,7 +208,7 @@ int misc_init_f(void) if (getenv("pciearly") && (!is_monarch())) { printf("PCI: early target init\n"); - pci_setup_indirect(&hose, PCIX0_CFGADR, PCIX0_CFGDATA); + pci_setup_indirect(&hose, PCIL0_CFGADR, PCIL0_CFGDATA); pci_target_init(&hose); } return 0; @@ -568,42 +568,42 @@ void pci_target_init(struct pci_controller *hose) * Use byte reversed out routines to handle endianess. * Make this region non-prefetchable. */ - out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ + out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */ + out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM0MA, 0xc0000001); /* 1G + No prefetching, */ /* and enable region */ if (!is_monarch()) { ptmla_str = getenv("ptm1la"); ptmms_str = getenv("ptm1ms"); if(NULL != ptmla_str && NULL != ptmms_str ) { - out32r(PCIX0_PTM1MS, + out32r(PCIL0_PTM1MS, simple_strtoul(ptmms_str, NULL, 16)); - out32r(PCIX0_PTM1LA, + out32r(PCIL0_PTM1LA, simple_strtoul(ptmla_str, NULL, 16)); } else { /* BAR1: default top 64MB of RAM */ - out32r(PCIX0_PTM1MS, 0xfc000001); - out32r(PCIX0_PTM1LA, 0x0c000000); + out32r(PCIL0_PTM1MS, 0xfc000001); + out32r(PCIL0_PTM1LA, 0x0c000000); } } else { /* BAR1: default: complete 256MB RAM */ - out32r(PCIX0_PTM1MS, 0xf0000001); - out32r(PCIX0_PTM1LA, 0x00000000); + out32r(PCIL0_PTM1MS, 0xf0000001); + out32r(PCIL0_PTM1LA, 0x00000000); } ptmla_str = getenv("ptm2la"); /* Local Addr. Reg */ ptmms_str = getenv("ptm2ms"); /* Memory Size/Attribute */ if(NULL != ptmla_str && NULL != ptmms_str ) { - out32r(PCIX0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16)); - out32r(PCIX0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16)); + out32r(PCIL0_PTM2MS, simple_strtoul(ptmms_str, NULL, 16)); + out32r(PCIL0_PTM2LA, simple_strtoul(ptmla_str, NULL, 16)); } else { /* BAR2: default: 4MB FPGA */ - out32r(PCIX0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */ - out32r(PCIX0_PTM2LA, 0xef000000); /* Local Addr. Reg */ + out32r(PCIL0_PTM2MS, 0xffc00001); /* Memory Size/Attribute */ + out32r(PCIL0_PTM2LA, 0xef000000); /* Local Addr. Reg */ } if (is_monarch()) { diff --git a/board/esd/pmc440/sdram.c b/board/esd/pmc440/sdram.c index bb46ecce2e..c3528bca4b 100644 --- a/board/esd/pmc440/sdram.c +++ b/board/esd/pmc440/sdram.c @@ -1,4 +1,7 @@ /* + * (C) Copyright 2009 + * Matthias Fuchs, esd gmbh, matthias.fuchs@esd.eu + * * (C) Copyright 2006 * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com @@ -31,33 +34,30 @@ #include #include #include +#include #include extern int denali_wait_for_dlllock(void); extern void denali_core_search_data_eye(void); +struct sdram_conf_s { + ulong size; + int rows; + int banks; +}; -#if defined(CONFIG_NAND_SPL) -/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big - * for the 4k NAND boot image so define bus_frequency to 133MHz here - * which is save for the refresh counter setup. - */ -#define get_bus_freq(val) 133000000 -#endif +struct sdram_conf_s sdram_conf[] = { + {(1024 << 20), 14, 8}, /* 1GByte: 4x2GBit, 14x10, 8 banks */ + {(512 << 20), 13, 8}, /* 512MByte: 4x1GBit, 13x10, 8 banks */ + {(256 << 20), 13, 4}, /* 256MByte: 4x512MBit, 13x10, 4 banks */ +}; -/************************************************************************* - * +/* * initdram -- 440EPx's DDR controller is a DENALI Core - * - ************************************************************************/ -phys_size_t initdram (int board_type) + */ +int initdram_by_rb(int rows, int banks) { -#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) -#if !defined(CONFIG_NAND_SPL) ulong speed = get_bus_freq(0); -#else - ulong speed = 133333333; /* 133MHz is on the safe side */ -#endif mtsdram(DDR0_02, 0x00000000); @@ -89,21 +89,25 @@ phys_size_t initdram (int board_type) mtsdram(DDR0_27, 0x0000682B); mtsdram(DDR0_28, 0x00000000); mtsdram(DDR0_31, 0x00000000); - mtsdram(DDR0_42, 0x01000006); - mtsdram(DDR0_43, 0x030A0200); + + mtsdram(DDR0_42, + DDR0_42_ADDR_PINS_DECODE(14 - rows) | + 0x00000006); + mtsdram(DDR0_43, + DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0) | + 0x030A0200); + mtsdram(DDR0_44, 0x00000003); mtsdram(DDR0_02, 0x00000001); denali_wait_for_dlllock(); -#endif /* #ifndef CONFIG_NAND_U_BOOT */ #ifdef CONFIG_DDR_DATA_EYE - /* -----------------------------------------------------------+ + /* * Perform data eye search if requested. - * ----------------------------------------------------------*/ + */ denali_core_search_data_eye(); #endif - /* * Clear possible errors resulting from data-eye-search. * If not done, then we could get an interrupt later on when @@ -111,5 +115,35 @@ phys_size_t initdram (int board_type) */ set_mcsr(get_mcsr()); - return (CONFIG_SYS_MBYTES_SDRAM << 20); + return 0; +} + +phys_size_t initdram(int board_type) +{ + phys_size_t size; + int n; + + /* go through supported memory configurations */ + for (n = 0; n < ARRAY_SIZE(sdram_conf); n++) { + size = sdram_conf[n].size; + + /* program TLB entries */ + program_tlb(0, CONFIG_SYS_SDRAM_BASE, size, + TLB_WORD2_I_ENABLE); + + /* + * setup denali core + */ + initdram_by_rb(sdram_conf[n].rows, + sdram_conf[n].banks); + + /* check for suitable configuration */ + if (get_ram_size(CONFIG_SYS_SDRAM_BASE, size) == size) + return size; + + /* delete TLB entries */ + remove_tlb(CONFIG_SYS_SDRAM_BASE, size); + } + + return 0; } diff --git a/board/esd/pmc440/u-boot-nand.lds b/board/esd/pmc440/u-boot-nand.lds index b580e0bd10..fb629e0c5e 100644 --- a/board/esd/pmc440/u-boot-nand.lds +++ b/board/esd/pmc440/u-boot-nand.lds @@ -62,7 +62,6 @@ SECTIONS . = ALIGN(0x10000); *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/pmc440/u-boot.lds b/board/esd/pmc440/u-boot.lds index 7360349dfb..3b6c09687a 100644 --- a/board/esd/pmc440/u-boot.lds +++ b/board/esd/pmc440/u-boot.lds @@ -65,7 +65,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/voh405/u-boot.lds b/board/esd/voh405/u-boot.lds index 8c010162f0..0799275fde 100644 --- a/board/esd/voh405/u-boot.lds +++ b/board/esd/voh405/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/vom405/u-boot.lds b/board/esd/vom405/u-boot.lds index 8c010162f0..0799275fde 100644 --- a/board/esd/vom405/u-boot.lds +++ b/board/esd/vom405/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esd/wuh405/u-boot.lds b/board/esd/wuh405/u-boot.lds index 005957eedb..285c901fe6 100644 --- a/board/esd/wuh405/u-boot.lds +++ b/board/esd/wuh405/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/esteem192e/u-boot.lds b/board/esteem192e/u-boot.lds index 57aabed7c5..3e4490ec49 100644 --- a/board/esteem192e/u-boot.lds +++ b/board/esteem192e/u-boot.lds @@ -66,7 +66,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/etx094/u-boot.lds b/board/etx094/u-boot.lds index eb3d487526..1d34e68fd7 100644 --- a/board/etx094/u-boot.lds +++ b/board/etx094/u-boot.lds @@ -68,7 +68,6 @@ SECTIONS . = env_offset; common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/etx094/u-boot.lds.debug b/board/etx094/u-boot.lds.debug index 28f8804dcc..1af61fb2b5 100644 --- a/board/etx094/u-boot.lds.debug +++ b/board/etx094/u-boot.lds.debug @@ -71,7 +71,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/eukrea/cpu9260/cpu9260.c b/board/eukrea/cpu9260/cpu9260.c index 0b4f0d450d..af8a4a2f89 100644 --- a/board/eukrea/cpu9260/cpu9260.c +++ b/board/eukrea/cpu9260/cpu9260.c @@ -165,7 +165,7 @@ int board_init(void) /* arch number of the board */ #if defined(CONFIG_CPU9G20) - gd->bd->bi_arch_number = MACH_TYPE_CPUAT9260; + gd->bd->bi_arch_number = MACH_TYPE_CPUAT9G20; #elif defined(CONFIG_CPU9260) gd->bd->bi_arch_number = MACH_TYPE_CPUAT9260; #endif diff --git a/board/evb64260/u-boot.lds b/board/evb64260/u-boot.lds index 632921ae53..d021331148 100644 --- a/board/evb64260/u-boot.lds +++ b/board/evb64260/u-boot.lds @@ -63,7 +63,6 @@ SECTIONS /* common/env_embedded.o(.text) */ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/exbitgen/init.S b/board/exbitgen/init.S index 7a9726fe78..721aaac3e7 100644 --- a/board/exbitgen/init.S +++ b/board/exbitgen/init.S @@ -52,7 +52,7 @@ #define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS) #define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR) #define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR) -#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV) +#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IIC0_CLKDIV) #define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK) #define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT) #define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS) @@ -537,7 +537,7 @@ read_spd: WRITE_I2C(IICHSADR, 0x00) /* clear hi slave address */ WRITE_I2C(IICSTS, 0x08) /* update status register */ WRITE_I2C(IICEXTSTS, 0x8f) - WRITE_I2C(IICCLKDIV, 0x05) + WRITE_I2C(IIC0_CLKDIV, 0x05) WRITE_I2C(IICINTRMSK, 0x00) /* no interrupts */ WRITE_I2C(IICXFRCNT, 0x00) /* clear transfer count */ WRITE_I2C(IICXTCNTLSS, 0xf0) /* clear extended control & stat */ diff --git a/board/exbitgen/u-boot.lds b/board/exbitgen/u-boot.lds index 2798dc8819..d2b28e11b6 100644 --- a/board/exbitgen/u-boot.lds +++ b/board/exbitgen/u-boot.lds @@ -77,7 +77,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/fads/u-boot.lds b/board/fads/u-boot.lds index b39ef1479a..ce3e32e0d5 100644 --- a/board/fads/u-boot.lds +++ b/board/fads/u-boot.lds @@ -56,7 +56,6 @@ SECTIONS common/env_embedded.o (.ppcenv) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/fads/u-boot.lds.debug b/board/fads/u-boot.lds.debug index 67d37ae334..0a3b958fad 100644 --- a/board/fads/u-boot.lds.debug +++ b/board/fads/u-boot.lds.debug @@ -65,7 +65,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/flagadm/u-boot.lds b/board/flagadm/u-boot.lds index 1c8180a019..877e82c84c 100644 --- a/board/flagadm/u-boot.lds +++ b/board/flagadm/u-boot.lds @@ -55,7 +55,6 @@ SECTIONS cpu/mpc8xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/flagadm/u-boot.lds.debug b/board/flagadm/u-boot.lds.debug index dbec9860a9..ad36953915 100644 --- a/board/flagadm/u-boot.lds.debug +++ b/board/flagadm/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c index 13bd73c81e..2fa3650092 100644 --- a/board/freescale/mpc5121ads/mpc5121ads.c +++ b/board/freescale/mpc5121ads/mpc5121ads.c @@ -169,11 +169,11 @@ phys_size_t initdram(int board_type) * Elpida MDDRC and initialization settings are an alternative * to the Default Micron ones for all but the earliest Rev 4 boards */ - u32 elpida_mddrc_config[4] = { - CONFIG_SYS_MDDRC_TIME_CFG0, - CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA, - CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA, - CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA, + ddr512x_config_t elpida_mddrc_config = { + .ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA, + .ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0, + .ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA, + .ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA, }; u32 elpida_init_sequence[] = { @@ -229,7 +229,7 @@ phys_size_t initdram(int board_type) if (is_micron()) { msize = fixed_sdram(NULL, NULL, 0); } else { - msize = fixed_sdram(elpida_mddrc_config, + msize = fixed_sdram(&elpida_mddrc_config, elpida_init_sequence, sizeof(elpida_init_sequence)/sizeof(u32)); } diff --git a/board/freescale/mpc7448hpc2/u-boot.lds b/board/freescale/mpc7448hpc2/u-boot.lds index cd11f3939c..247779f6c2 100644 --- a/board/freescale/mpc7448hpc2/u-boot.lds +++ b/board/freescale/mpc7448hpc2/u-boot.lds @@ -63,7 +63,6 @@ SECTIONS /* common/env_embedded.o(.text) */ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 80de6f8762..73e7c21093 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -276,7 +276,6 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; - struct pci_config_table *table; struct pci_region *r = hose->regions; uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ @@ -312,12 +311,6 @@ pci_init_board(void) PCI_REGION_IO); hose->region_count = r - hose->regions; - /* relocate config table pointers */ - hose->config_table = \ - (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off); - for (table = hose->config_table; table && table->vendor; table++) - table->config_device += gd->reloc_off; - hose->first_busno=first_free_busno; fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); diff --git a/board/freescale/mpc8610hpcd/u-boot.lds b/board/freescale/mpc8610hpcd/u-boot.lds index 5cc88aeea5..b573807fe9 100644 --- a/board/freescale/mpc8610hpcd/u-boot.lds +++ b/board/freescale/mpc8610hpcd/u-boot.lds @@ -61,7 +61,6 @@ SECTIONS lib_ppc/extable.o (.text) lib_generic/zlib.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/freescale/mpc8641hpcn/u-boot.lds b/board/freescale/mpc8641hpcn/u-boot.lds index e18872202a..2b98b5a9cc 100644 --- a/board/freescale/mpc8641hpcn/u-boot.lds +++ b/board/freescale/mpc8641hpcn/u-boot.lds @@ -62,7 +62,6 @@ SECTIONS lib_generic/zlib.o (.text) drivers/bios_emulator/atibios.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/g2000/u-boot.lds b/board/g2000/u-boot.lds index 8c010162f0..0799275fde 100644 --- a/board/g2000/u-boot.lds +++ b/board/g2000/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c b/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c index 105a74714b..7fe85b85ad 100644 --- a/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c +++ b/board/gaisler/gr_cpci_ax2000/gr_cpci_ax2000.c @@ -19,6 +19,7 @@ */ #include +#include #include #include @@ -37,3 +38,14 @@ int misc_init_r(void) { return 0; } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} +#endif diff --git a/board/gaisler/gr_ep2s60/gr_ep2s60.c b/board/gaisler/gr_ep2s60/gr_ep2s60.c index 2904d32586..7241c6d1a4 100644 --- a/board/gaisler/gr_ep2s60/gr_ep2s60.c +++ b/board/gaisler/gr_ep2s60/gr_ep2s60.c @@ -19,6 +19,7 @@ */ #include +#include #include #include @@ -37,3 +38,14 @@ int misc_init_r(void) { return 0; } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} +#endif diff --git a/board/gdsys/dlvision/u-boot.lds b/board/gdsys/dlvision/u-boot.lds index d803625b5a..689c808b8a 100644 --- a/board/gdsys/dlvision/u-boot.lds +++ b/board/gdsys/dlvision/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c index 7cc1bf2678..90dbe52aa2 100644 --- a/board/gdsys/gdppc440etx/gdppc440etx.c +++ b/board/gdsys/gdppc440etx/gdppc440etx.c @@ -239,22 +239,22 @@ void pci_target_init(struct pci_controller *hose) * Use byte reversed out routines to handle endianess. * Make this region non-prefetchable. */ - out32r(PCIX0_PMM0MA, 0x00000000); /* disabled b4 setting */ - out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); - out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); - out32r(PCIX0_PMM0PCIHA, 0x00000000); - out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */ - - out32r(PCIX0_PMM1MA, 0x00000000); /* disabled b4 setting */ - out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); - out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); - out32r(PCIX0_PMM1PCIHA, 0x00000000); - out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */ - - out32r(PCIX0_PTM1MS, 0x00000001); - out32r(PCIX0_PTM1LA, 0); - out32r(PCIX0_PTM2MS, 0); - out32r(PCIX0_PTM2LA, 0); + out32r(PCIL0_PMM0MA, 0x00000000); /* disabled b4 setting */ + out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); + out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); + out32r(PCIL0_PMM0PCIHA, 0x00000000); + out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M, no prefetch, enable region */ + + out32r(PCIL0_PMM1MA, 0x00000000); /* disabled b4 setting */ + out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); + out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); + out32r(PCIL0_PMM1PCIHA, 0x00000000); + out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M, no prefetch, enable region */ + + out32r(PCIL0_PTM1MS, 0x00000001); + out32r(PCIL0_PTM1LA, 0); + out32r(PCIL0_PTM2MS, 0); + out32r(PCIL0_PTM2LA, 0); /* * Set up Configuration registers diff --git a/board/gdsys/gdppc440etx/u-boot.lds b/board/gdsys/gdppc440etx/u-boot.lds index 77f0aae700..6ab36ee855 100644 --- a/board/gdsys/gdppc440etx/u-boot.lds +++ b/board/gdsys/gdppc440etx/u-boot.lds @@ -69,7 +69,6 @@ SECTIONS board/gdsys/gdppc440etx/init.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c index 2cd2e6d450..b42e90853f 100644 --- a/board/gdsys/intip/intip.c +++ b/board/gdsys/intip/intip.c @@ -154,27 +154,27 @@ void pci_target_init(struct pci_controller *hose) /* * Disable everything */ - out_le32((void *)PCIX0_PIM0SA, 0); /* disable */ - out_le32((void *)PCIX0_PIM1SA, 0); /* disable */ - out_le32((void *)PCIX0_PIM2SA, 0); /* disable */ - out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */ + out_le32((void *)PCIL0_PIM0SA, 0); /* disable */ + out_le32((void *)PCIL0_PIM1SA, 0); /* disable */ + out_le32((void *)PCIL0_PIM2SA, 0); /* disable */ + out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */ /* * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 * strapping options to not support sizes such as 128/256 MB. */ - out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); - out_le32((void *)PCIX0_PIM0LAH, 0); - out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1); - out_le32((void *)PCIX0_BAR0, 0); + out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); + out_le32((void *)PCIL0_PIM0LAH, 0); + out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1); + out_le32((void *)PCIL0_BAR0, 0); /* * Program the board's subsystem id/vendor id */ - out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); - out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); + out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); + out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); - out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY); + out_le16((void *)PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY); } #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ diff --git a/board/gdsys/intip/u-boot.lds b/board/gdsys/intip/u-boot.lds index c1cbd1c4ac..624c4c1bef 100644 --- a/board/gdsys/intip/u-boot.lds +++ b/board/gdsys/intip/u-boot.lds @@ -69,7 +69,6 @@ SECTIONS board/gdsys/intip/init.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/gdsys/neo/u-boot.lds b/board/gdsys/neo/u-boot.lds index b95eb5ce18..75202caf33 100644 --- a/board/gdsys/neo/u-boot.lds +++ b/board/gdsys/neo/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c index 29cad2ee81..d42c500ca0 100644 --- a/board/gen860t/fpga.c +++ b/board/gen860t/fpga.c @@ -193,8 +193,9 @@ int gen860t_init_fpga (void) { int i; - PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off); - fpga_init (gd->reloc_off); + PRINTF ("%s:%d: Initialize FPGA interface\n", + __FUNCTION__, __LINE__); + fpga_init (); fpga_selectmap_init (); for (i = 0; i < CONFIG_FPGA_COUNT; i++) { diff --git a/board/gen860t/u-boot-flashenv.lds b/board/gen860t/u-boot-flashenv.lds index 9785639c76..7b83b25b65 100644 --- a/board/gen860t/u-boot-flashenv.lds +++ b/board/gen860t/u-boot-flashenv.lds @@ -57,7 +57,6 @@ SECTIONS { cpu/mpc8xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/gen860t/u-boot.lds b/board/gen860t/u-boot.lds index fbe3c7044b..8f40b303bf 100644 --- a/board/gen860t/u-boot.lds +++ b/board/gen860t/u-boot.lds @@ -56,7 +56,6 @@ SECTIONS { cpu/mpc8xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/genietv/u-boot.lds b/board/genietv/u-boot.lds index ee0b7195c6..716efcdd0b 100644 --- a/board/genietv/u-boot.lds +++ b/board/genietv/u-boot.lds @@ -65,7 +65,6 @@ SECTIONS . = env_offset; common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/genietv/u-boot.lds.debug b/board/genietv/u-boot.lds.debug index 61fdfe53ec..3568e6de69 100644 --- a/board/genietv/u-boot.lds.debug +++ b/board/genietv/u-boot.lds.debug @@ -65,7 +65,6 @@ SECTIONS . = env_offset; common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/gth/u-boot.lds b/board/gth/u-boot.lds index 88265508f8..f6175d9d57 100644 --- a/board/gth/u-boot.lds +++ b/board/gth/u-boot.lds @@ -55,7 +55,6 @@ SECTIONS cpu/mpc8xx/start.o(.text) *(.text) common/env_embedded.o(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/hermes/u-boot.lds b/board/hermes/u-boot.lds index 02216fb849..7b74cb7d5f 100644 --- a/board/hermes/u-boot.lds +++ b/board/hermes/u-boot.lds @@ -66,7 +66,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/hermes/u-boot.lds.debug b/board/hermes/u-boot.lds.debug index 78456e6d8f..3801206931 100644 --- a/board/hermes/u-boot.lds.debug +++ b/board/hermes/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/hymod/u-boot.lds b/board/hymod/u-boot.lds index 03fefecefb..52d66a2df3 100644 --- a/board/hymod/u-boot.lds +++ b/board/hymod/u-boot.lds @@ -68,7 +68,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/hymod/u-boot.lds.debug b/board/hymod/u-boot.lds.debug index ea8538900c..a2d940f048 100644 --- a/board/hymod/u-boot.lds.debug +++ b/board/hymod/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/icu862/u-boot.lds b/board/icu862/u-boot.lds index 9a28cfd303..b43be81b69 100644 --- a/board/icu862/u-boot.lds +++ b/board/icu862/u-boot.lds @@ -69,7 +69,6 @@ SECTIONS */ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/icu862/u-boot.lds.debug b/board/icu862/u-boot.lds.debug index dbd1f9d106..653e0be45c 100644 --- a/board/icu862/u-boot.lds.debug +++ b/board/icu862/u-boot.lds.debug @@ -65,7 +65,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c index c645b05b5c..27b79ec7f4 100644 --- a/board/inka4x0/inka4x0.c +++ b/board/inka4x0/inka4x0.c @@ -177,16 +177,6 @@ void flash_preinit(void) clrbits_be32(&lpb->cs0_cfg, 0x1); /* clear RO */ } -int misc_init_r (void) { - extern int inkadiag_init_r (void); - - /* - * The command table used for the subcommands of inkadiag - * needs to be relocated manually. - */ - return inkadiag_init_r(); -} - int misc_init_f (void) { volatile struct mpc5xxx_gpio *gpio = diff --git a/board/inka4x0/inkadiag.c b/board/inka4x0/inkadiag.c index 3761ef66d4..0a75abde3f 100644 --- a/board/inka4x0/inkadiag.c +++ b/board/inka4x0/inkadiag.c @@ -484,31 +484,3 @@ U_BOOT_CMD(inkadiag, 6, 1, do_inkadiag, "[inkadiag what ...]\n" " - perform a diagnosis on inka hardware\n" "'inkadiag' performs hardware tests."); - -/* Relocate the command table function pointers when running in RAM */ -int inkadiag_init_r (void) { - cmd_tbl_t *cmdtp; - - for (cmdtp = &cmd_inkadiag_sub[0]; cmdtp != - &cmd_inkadiag_sub[ARRAY_SIZE(cmd_inkadiag_sub)]; cmdtp++) { - ulong addr; - - addr = (ulong) (cmdtp->cmd) + gd->reloc_off; - cmdtp->cmd = (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr; - - addr = (ulong)(cmdtp->name) + gd->reloc_off; - cmdtp->name = (char *)addr; - - if (cmdtp->usage) { - addr = (ulong)(cmdtp->usage) + gd->reloc_off; - cmdtp->usage = (char *)addr; - } -#ifdef CONFIG_SYS_LONGHELP - if (cmdtp->help) { - addr = (ulong)(cmdtp->help) + gd->reloc_off; - cmdtp->help = (char *)addr; - } -#endif - } - return 0; -} diff --git a/board/innokom/innokom.c b/board/innokom/innokom.c index c2b88ae16a..3412f10d3f 100644 --- a/board/innokom/innokom.c +++ b/board/innokom/innokom.c @@ -24,6 +24,7 @@ */ #include +#include #include #include @@ -182,3 +183,14 @@ void show_boot_progress (int status) return; } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} +#endif diff --git a/board/ip860/u-boot.lds b/board/ip860/u-boot.lds index b47ae8e530..a786bf23e1 100644 --- a/board/ip860/u-boot.lds +++ b/board/ip860/u-boot.lds @@ -66,7 +66,6 @@ SECTIONS common/env_embedded.o(.text) **/ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/ip860/u-boot.lds.debug b/board/ip860/u-boot.lds.debug index e8a47f7a0b..dc2f6e12f5 100644 --- a/board/ip860/u-boot.lds.debug +++ b/board/ip860/u-boot.lds.debug @@ -65,7 +65,6 @@ SECTIONS common/env_embedded.o(.text) **/ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/ivm/u-boot.lds b/board/ivm/u-boot.lds index ab51bd8352..8d7ff70117 100644 --- a/board/ivm/u-boot.lds +++ b/board/ivm/u-boot.lds @@ -55,7 +55,6 @@ SECTIONS cpu/mpc8xx/start.o (.text) common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/ivm/u-boot.lds.debug b/board/ivm/u-boot.lds.debug index 4d49f1bbef..b5206c50fd 100644 --- a/board/ivm/u-boot.lds.debug +++ b/board/ivm/u-boot.lds.debug @@ -65,7 +65,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/jse/u-boot.lds b/board/jse/u-boot.lds index 12d3938fc1..6d0a21cdc4 100644 --- a/board/jse/u-boot.lds +++ b/board/jse/u-boot.lds @@ -68,7 +68,6 @@ SECTIONS /* common/env_embedded.o(.text)*/ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/keymile/km8xx/u-boot.lds b/board/keymile/km8xx/u-boot.lds index 5af36c97ac..a8057f225b 100644 --- a/board/keymile/km8xx/u-boot.lds +++ b/board/keymile/km8xx/u-boot.lds @@ -69,7 +69,6 @@ SECTIONS common/env_embedded.o (.ppcenv) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/korat/korat.c b/board/korat/korat.c index 40a097cef5..8c674a2095 100644 --- a/board/korat/korat.c +++ b/board/korat/korat.c @@ -679,29 +679,29 @@ void pci_target_init(struct pci_controller *hose) * Use byte reversed out routines to handle endianess. * Make this region non-prefetchable. */ - out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ + out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, + out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */ + out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, */ /* and enable region */ - out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */ + out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute */ /* - disabled b4 setting */ - out32r(PCIX0_PMM1LA, + out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE + 0x20000000); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, + out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE + 0x20000000); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */ + out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, */ /* and enable region */ - out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ /* * Set up Configuration registers diff --git a/board/korat/u-boot-F7FC.lds b/board/korat/u-boot-F7FC.lds index c175f91fd4..cbad8668e3 100644 --- a/board/korat/u-boot-F7FC.lds +++ b/board/korat/u-boot-F7FC.lds @@ -68,7 +68,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/korat/u-boot.lds b/board/korat/u-boot.lds index 7798722eb9..b9ec56bb20 100644 --- a/board/korat/u-boot.lds +++ b/board/korat/u-boot.lds @@ -68,7 +68,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/kup/kup4k/u-boot.lds b/board/kup/kup4k/u-boot.lds index f2b6650028..79b886af21 100644 --- a/board/kup/kup4k/u-boot.lds +++ b/board/kup/kup4k/u-boot.lds @@ -69,7 +69,6 @@ SECTIONS */ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/kup/kup4k/u-boot.lds.debug b/board/kup/kup4k/u-boot.lds.debug index 0f6ae696d8..83fdc15011 100644 --- a/board/kup/kup4k/u-boot.lds.debug +++ b/board/kup/kup4k/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/kup/kup4x/u-boot.lds b/board/kup/kup4x/u-boot.lds index f2b6650028..79b886af21 100644 --- a/board/kup/kup4x/u-boot.lds +++ b/board/kup/kup4x/u-boot.lds @@ -69,7 +69,6 @@ SECTIONS */ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/kup/kup4x/u-boot.lds.debug b/board/kup/kup4x/u-boot.lds.debug index 0f6ae696d8..83fdc15011 100644 --- a/board/kup/kup4x/u-boot.lds.debug +++ b/board/kup/kup4x/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/lantec/u-boot.lds b/board/lantec/u-boot.lds index b9fa2d6d94..854ed68932 100644 --- a/board/lantec/u-boot.lds +++ b/board/lantec/u-boot.lds @@ -66,7 +66,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/lantec/u-boot.lds.debug b/board/lantec/u-boot.lds.debug index d5e2c1d579..3b4799e1ef 100644 --- a/board/lantec/u-boot.lds.debug +++ b/board/lantec/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/logicpd/zoom2/zoom2.c b/board/logicpd/zoom2/zoom2.c index d9e2ae5021..dadbeb6730 100644 --- a/board/logicpd/zoom2/zoom2.c +++ b/board/logicpd/zoom2/zoom2.c @@ -50,9 +50,6 @@ * The details of the setting of the serial gpmc setup are not available. * The values were provided by another party. */ -void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base, - u32 size); - static u32 gpmc_serial_TL16CP754C[GPMC_MAX_REG] = { 0x00011000, 0x001F1F01, @@ -129,7 +126,7 @@ int board_init (void) /* Configure console support on zoom2 */ gpmc_config = gpmc_serial_TL16CP754C; - enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[4], + enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[3], SERIAL_TL16CP754C_BASE, GPMC_SIZE_16M); /* board id for Linux */ diff --git a/board/logodl/logodl.c b/board/logodl/logodl.c index c57210a95f..2562ecca35 100644 --- a/board/logodl/logodl.c +++ b/board/logodl/logodl.c @@ -23,6 +23,7 @@ */ #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -120,3 +121,14 @@ void show_boot_progress (int status) return; } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} +#endif diff --git a/board/lpd7a40x/lpd7a40x.c b/board/lpd7a40x/lpd7a40x.c index 7edb65e6d8..437dad0388 100644 --- a/board/lpd7a40x/lpd7a40x.c +++ b/board/lpd7a40x/lpd7a40x.c @@ -26,6 +26,7 @@ */ #include +#include #if defined(CONFIG_LH7A400) #include #elif defined(CONFIG_LH7A404) @@ -79,3 +80,14 @@ int dram_init (void) return 0; } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} +#endif diff --git a/board/lwmon/u-boot.lds b/board/lwmon/u-boot.lds index 9e46f9d8bf..cc8ad7d3db 100644 --- a/board/lwmon/u-boot.lds +++ b/board/lwmon/u-boot.lds @@ -55,7 +55,6 @@ SECTIONS cpu/mpc8xx/start.o (.text) common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/lwmon/u-boot.lds.debug b/board/lwmon/u-boot.lds.debug index bd9d76ce20..987c4ddb9b 100644 --- a/board/lwmon/u-boot.lds.debug +++ b/board/lwmon/u-boot.lds.debug @@ -65,7 +65,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index f4090f40dd..ef7f2e8dc5 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -351,22 +351,22 @@ void pci_target_init(struct pci_controller *hose) | Use byte reversed out routines to handle endianess. | Make this region non-prefetchable. +--------------------------------------------------------------------------*/ - out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ /*--------------------------------------------------------------------------+ * Set up Configuration registers diff --git a/board/lwmon5/u-boot.lds b/board/lwmon5/u-boot.lds index 7798722eb9..b9ec56bb20 100644 --- a/board/lwmon5/u-boot.lds +++ b/board/lwmon5/u-boot.lds @@ -68,7 +68,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/matrix_vision/mvbc_p/fpga.c b/board/matrix_vision/mvbc_p/fpga.c index 356af1aa54..3ed46fe802 100644 --- a/board/matrix_vision/mvbc_p/fpga.c +++ b/board/matrix_vision/mvbc_p/fpga.c @@ -46,7 +46,6 @@ Altera_CYC2_Passive_Serial_fns altera_fns = { fpga_wr_fn, fpga_null_fn, fpga_null_fn, - 0 }; Altera_desc cyclone2 = { @@ -55,16 +54,14 @@ Altera_desc cyclone2 = { Altera_EP2C8_SIZE, (void *) &altera_fns, NULL, - 0 }; DECLARE_GLOBAL_DATA_PTR; int mvbc_p_init_fpga(void) { - fpga_debug("Initialize FPGA interface (reloc 0x%.8lx)\n", - gd->reloc_off); - fpga_init(gd->reloc_off); + fpga_debug("Initialize FPGA interface\n"); + fpga_init(); fpga_add(fpga_altera, &cyclone2); fpga_config_fn(0, 1, 0); udelay(60); diff --git a/board/matrix_vision/mvblm7/fpga.c b/board/matrix_vision/mvblm7/fpga.c index 7527d161ad..7b03d6f507 100644 --- a/board/matrix_vision/mvblm7/fpga.c +++ b/board/matrix_vision/mvblm7/fpga.c @@ -46,7 +46,6 @@ Altera_CYC2_Passive_Serial_fns altera_fns = { fpga_wr_fn, fpga_null_fn, fpga_null_fn, - 0 }; Altera_desc cyclone2 = { @@ -62,9 +61,8 @@ DECLARE_GLOBAL_DATA_PTR; int mvblm7_init_fpga(void) { - fpga_debug("Initialize FPGA interface (reloc 0x%.8lx)\n", - gd->reloc_off); - fpga_init(gd->reloc_off); + fpga_debug("Initialize FPGA interface\n"); + fpga_init(); fpga_add(fpga_altera, &cyclone2); fpga_config_fn(0, 1, 0); udelay(60); diff --git a/board/mbx8xx/u-boot.lds b/board/mbx8xx/u-boot.lds index ca35e88482..dc3e580fb1 100644 --- a/board/mbx8xx/u-boot.lds +++ b/board/mbx8xx/u-boot.lds @@ -55,7 +55,6 @@ SECTIONS cpu/mpc8xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/mbx8xx/u-boot.lds.debug b/board/mbx8xx/u-boot.lds.debug index 67d37ae334..0a3b958fad 100644 --- a/board/mbx8xx/u-boot.lds.debug +++ b/board/mbx8xx/u-boot.lds.debug @@ -65,7 +65,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/ml2/u-boot.lds b/board/ml2/u-boot.lds index a6b67487f1..8fea3be41b 100644 --- a/board/ml2/u-boot.lds +++ b/board/ml2/u-boot.lds @@ -72,7 +72,6 @@ SECTIONS /* common/env_embedded.o(.text)*/ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/ml2/u-boot.lds.debug b/board/ml2/u-boot.lds.debug index 338392a075..970628d556 100644 --- a/board/ml2/u-boot.lds.debug +++ b/board/ml2/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/mousse/u-boot.lds b/board/mousse/u-boot.lds index 44144e23c2..5100542e73 100644 --- a/board/mousse/u-boot.lds +++ b/board/mousse/u-boot.lds @@ -59,7 +59,6 @@ SECTIONS lib_generic/crc32.o (.text) lib_generic/zlib.o (.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.eh_frame) diff --git a/board/mousse/u-boot.lds.rom b/board/mousse/u-boot.lds.rom index 27d10b6d6a..f79c39f716 100644 --- a/board/mousse/u-boot.lds.rom +++ b/board/mousse/u-boot.lds.rom @@ -64,7 +64,6 @@ SECTIONS *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.rodata) diff --git a/board/mpl/common/memtst.c b/board/mpl/common/memtst.c index 1393ea15af..92c33bac16 100644 --- a/board/mpl/common/memtst.c +++ b/board/mpl/common/memtst.c @@ -468,32 +468,6 @@ static RAM_MEMTEST_FUNC test_stage[TEST_STAGES] = { RAM_MemTest_CheckRandomPattern, NULL} }; -void mem_test_reloc(void) -{ - unsigned long addr; - int i; - for (i=0; i< TEST_STAGES; i++) { - addr = (ulong) (test_stage[i].test_write) + gd->reloc_off; - test_stage[i].test_write= - (void (*) (unsigned long startaddr, unsigned long size, - unsigned long *pat))addr; - addr = (ulong) (test_stage[i].test_write_desc) + gd->reloc_off; - test_stage[i].test_write_desc=(char *)addr; - if(test_stage[i].test_check1) { - addr = (ulong) (test_stage[i].test_check1) + gd->reloc_off; - test_stage[i].test_check1= - (void *(*) (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat))addr; - } - if(test_stage[i].test_check2) { - addr = (ulong) (test_stage[i].test_check2) + gd->reloc_off; - test_stage[i].test_check2= - (void *(*) (int mode, unsigned long startaddr, - unsigned long size, unsigned long *pat))addr; - } - } -} - int mem_test (unsigned long start, unsigned long ramsize, int quiet) { diff --git a/board/mpl/common/pci.c b/board/mpl/common/pci.c index e0ba620d1f..f9bb6ab2bc 100644 --- a/board/mpl/common/pci.c +++ b/board/mpl/common/pci.c @@ -94,29 +94,11 @@ static struct pci_controller hose = { }; -static void reloc_pci_cfg_table(struct pci_config_table *table) -{ - unsigned long addr; - - for (; table && table->vendor; table++) { - addr = (ulong) (table->config_device) + gd->reloc_off; -#ifdef DEBUG - printf ("device \"%d\": 0x%08lx => 0x%08lx\n", - table->device, (ulong) (table->config_device), addr); -#endif - table->config_device = - (void (*)(struct pci_controller* hose, pci_dev_t dev, - struct pci_config_table *))addr; - table->priv[0]+=gd->reloc_off; - } -} - void pci_init_board(void) { /*we want the ptrs to RAM not flash (ie don't use init list)*/ hose.fixup_irq = pci_pip405_fixup_irq; hose.config_table = pci_pip405_config_table; - reloc_pci_cfg_table(hose.config_table); #ifdef DEBUG printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",pci_pip405_fixup_irq,pci_pip405_config_table,hose); #endif diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c index ae8eade64a..495e9bd88a 100644 --- a/board/mpl/mip405/mip405.c +++ b/board/mpl/mip405/mip405.c @@ -717,7 +717,6 @@ int post_hotkeys_pressed(void) } #endif -extern void mem_test_reloc(void); extern int mk_date (char *, struct rtc_time *); int last_stage_init (void) @@ -725,7 +724,7 @@ int last_stage_init (void) unsigned long stop; struct rtc_time newtm; char *s; - mem_test_reloc(); + /* write correct LED configuration */ if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) { printf ("Error writing to the PHY\n"); diff --git a/board/mpl/mip405/u-boot.lds b/board/mpl/mip405/u-boot.lds index d71a299785..cc8bed071d 100644 --- a/board/mpl/mip405/u-boot.lds +++ b/board/mpl/mip405/u-boot.lds @@ -82,7 +82,6 @@ SECTIONS /* common/env_embedded.o(.text)*/ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c index 1b3b698ed9..e12bc423f4 100644 --- a/board/mpl/pati/pati.c +++ b/board/mpl/pati/pati.c @@ -144,7 +144,6 @@ const sdram_t sdram_table[] = { extern int mem_test (unsigned long start, unsigned long ramsize, int quiet); -extern void mem_test_reloc(void); /* * Get RAM size. @@ -334,7 +333,6 @@ void user_led1(int led_on) ****************************************************************/ int last_stage_init (void) { - mem_test_reloc(); init_ios(); return 0; } diff --git a/board/mpl/pip405/u-boot.lds b/board/mpl/pip405/u-boot.lds index f6f88a7ec2..92290d8b34 100644 --- a/board/mpl/pip405/u-boot.lds +++ b/board/mpl/pip405/u-boot.lds @@ -77,7 +77,6 @@ SECTIONS /* common/env_embedded.o(.text)*/ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/mpl/pip405/u-boot.lds.debug b/board/mpl/pip405/u-boot.lds.debug index 338392a075..970628d556 100644 --- a/board/mpl/pip405/u-boot.lds.debug +++ b/board/mpl/pip405/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index ed4df17763..4d8b579caa 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -313,11 +313,8 @@ int checkboard(void) } -extern void mem_test_reloc(void); - int last_stage_init(void) { - mem_test_reloc(); checkboard(); stdio_print_current_devices(); check_env(); diff --git a/board/ms7722se/ms7722se.c b/board/ms7722se/ms7722se.c index 32234d3e08..4e40b17343 100644 --- a/board/ms7722se/ms7722se.c +++ b/board/ms7722se/ms7722se.c @@ -24,6 +24,7 @@ */ #include +#include #include #include @@ -57,3 +58,14 @@ void led_set_state(unsigned short value) { writew(value & 0xFF, LED_BASE); } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} +#endif diff --git a/board/munices/u-boot.lds b/board/munices/u-boot.lds index 5fe8707fb5..8db7f26a52 100644 --- a/board/munices/u-boot.lds +++ b/board/munices/u-boot.lds @@ -54,7 +54,6 @@ SECTIONS { cpu/mpc5xxx/start.o (.text) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) diff --git a/board/nc650/u-boot.lds b/board/nc650/u-boot.lds index dd040f0551..21fed6262c 100644 --- a/board/nc650/u-boot.lds +++ b/board/nc650/u-boot.lds @@ -54,7 +54,6 @@ SECTIONS { cpu/mpc8xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/nc650/u-boot.lds.debug b/board/nc650/u-boot.lds.debug index 079a55abeb..5f8dc9d2c6 100644 --- a/board/nc650/u-boot.lds.debug +++ b/board/nc650/u-boot.lds.debug @@ -54,7 +54,6 @@ SECTIONS { cpu/mpc8xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/netphone/u-boot.lds b/board/netphone/u-boot.lds index 68fe165e58..d64274b683 100644 --- a/board/netphone/u-boot.lds +++ b/board/netphone/u-boot.lds @@ -66,7 +66,6 @@ SECTIONS common/env_embedded.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/netphone/u-boot.lds.debug b/board/netphone/u-boot.lds.debug index d47c4082aa..4ef16f1ffe 100644 --- a/board/netphone/u-boot.lds.debug +++ b/board/netphone/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/netstal/hcu4/u-boot.lds b/board/netstal/hcu4/u-boot.lds index 0c38ea299f..f748ec30bb 100644 --- a/board/netstal/hcu4/u-boot.lds +++ b/board/netstal/hcu4/u-boot.lds @@ -65,7 +65,6 @@ SECTIONS /* common/env_embedded.o(.text)*/ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c index 4522612dae..946c3f3a4d 100644 --- a/board/netstal/hcu5/hcu5.c +++ b/board/netstal/hcu5/hcu5.c @@ -398,27 +398,27 @@ void pci_target_init(struct pci_controller *hose) * Make this region non-prefetchable. */ /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM0MA, 0x00000000); - out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIL0_PMM0MA, 0x00000000); + out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); - out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); + out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ /* 512M + No prefetching, and enable region */ - out32r(PCIX0_PMM0MA, 0xE0000001); + out32r(PCIL0_PMM0MA, 0xE0000001); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM1MA, 0x00000000); - out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIL0_PMM1MA, 0x00000000); + out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); - out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); + out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ /* 512M + No prefetching, and enable region */ - out32r(PCIX0_PMM1MA, 0xE0000001); + out32r(PCIL0_PMM1MA, 0xE0000001); - out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ /* * Set up Configuration registers diff --git a/board/netstal/hcu5/u-boot.lds b/board/netstal/hcu5/u-boot.lds index 21a2be2f4f..bdc6e705cb 100644 --- a/board/netstal/hcu5/u-boot.lds +++ b/board/netstal/hcu5/u-boot.lds @@ -67,7 +67,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/netstal/mcu25/u-boot.lds b/board/netstal/mcu25/u-boot.lds index b589956459..2cf3361c4e 100644 --- a/board/netstal/mcu25/u-boot.lds +++ b/board/netstal/mcu25/u-boot.lds @@ -65,7 +65,6 @@ SECTIONS /* common/env_embedded.o(.text)*/ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/netstar/eeprom.c b/board/netstar/eeprom.c index 5806128cf1..1366457b9b 100644 --- a/board/netstar/eeprom.c +++ b/board/netstar/eeprom.c @@ -27,43 +27,42 @@ #include #include #include +#include #include "../drivers/net/smc91111.h" -#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE - -static u16 read_eeprom_reg(u16 reg) +static u16 read_eeprom_reg(struct eth_device *dev, u16 reg) { int timeout; - SMC_SELECT_BANK(2); - SMC_outw(reg, PTR_REG); + SMC_SELECT_BANK(dev, 2); + SMC_outw(dev, reg, PTR_REG); - SMC_SELECT_BANK(1); - SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD, + SMC_SELECT_BANK(dev, 1); + SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD, CTL_REG); timeout = 100; - while((SMC_inw (CTL_REG) & CTL_RELOAD) && --timeout) + while((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --timeout) udelay(100); if (timeout == 0) { printf("Timeout Reading EEPROM register %02x\n", reg); return 0; } - return SMC_inw (GP_REG); + return SMC_inw (dev, GP_REG); } -static int write_eeprom_reg(u16 value, u16 reg) +static int write_eeprom_reg(struct eth_device *dev, u16 value, u16 reg) { int timeout; - SMC_SELECT_BANK(2); - SMC_outw(reg, PTR_REG); + SMC_SELECT_BANK(dev, 2); + SMC_outw(dev, reg, PTR_REG); - SMC_SELECT_BANK(1); - SMC_outw(value, GP_REG); - SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG); + SMC_SELECT_BANK(dev, 1); + SMC_outw(dev, value, GP_REG); + SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG); timeout = 100; - while ((SMC_inw(CTL_REG) & CTL_STORE) && --timeout) + while ((SMC_inw(dev, CTL_REG) & CTL_STORE) && --timeout) udelay (100); if (timeout == 0) { printf("Timeout Writing EEPROM register %02x\n", reg); @@ -73,17 +72,17 @@ static int write_eeprom_reg(u16 value, u16 reg) return 1; } -static int write_data(u16 *buf, int len) +static int write_data(struct eth_device *dev, u16 *buf, int len) { u16 reg = 0x23; while (len--) - write_eeprom_reg(*buf++, reg++); + write_eeprom_reg(dev, *buf++, reg++); return 0; } -static int verify_macaddr(char *s) +static int verify_macaddr(struct eth_device *dev, char *s) { u16 reg; int i, err = 0; @@ -91,7 +90,7 @@ static int verify_macaddr(char *s) printf("MAC Address: "); err = i = 0; for (i = 0; i < 3; i++) { - reg = read_eeprom_reg(0x20 + i); + reg = read_eeprom_reg(dev, 0x20 + i); printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n'); if (s) err |= reg != ((u16 *)s)[i]; @@ -100,7 +99,7 @@ static int verify_macaddr(char *s) return err ? 0 : 1; } -static int set_mac(char *s) +static int set_mac(struct eth_device *dev, char *s) { int i; char *e, eaddr[6]; @@ -112,7 +111,7 @@ static int set_mac(char *s) } for (i = 0; i < 3; i++) - write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i); + write_eeprom_reg(dev, *(((u16 *)eaddr) + i), 0x20 + i); return 0; } @@ -150,6 +149,10 @@ int eeprom(int argc, char *argv[]) int i, len, ret; unsigned char buf[58], *p; + struct eth_device dev = { + .iobase = CONFIG_SMC91111_BASE + }; + app_startup(argv); if (get_version() != XF_VERSION) { printf("Wrong XF_VERSION.\n"); @@ -160,14 +163,14 @@ int eeprom(int argc, char *argv[]) return crcek(); - if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) { + if ((SMC_inw (&dev, BANK_SELECT) & 0xFF00) != 0x3300) { printf("SMSC91111 not found.\n"); return 2; } /* Called without parameters - print MAC address */ if (argc < 2) { - verify_macaddr(NULL); + verify_macaddr(&dev, NULL); return 0; } @@ -201,8 +204,8 @@ int eeprom(int argc, char *argv[]) } /* First argument (MAC) is mandatory */ - set_mac(argv[1]); - if (verify_macaddr(argv[1])) { + set_mac(&dev, argv[1]); + if (verify_macaddr(&dev, argv[1])) { printf("*** MAC address does not match! ***\n"); return 4; } @@ -210,7 +213,7 @@ int eeprom(int argc, char *argv[]) while (len--) *p++ = 0; - write_data((u16 *)buf, sizeof(buf) >> 1); + write_data(&dev, (u16 *)buf, sizeof(buf) >> 1); return 0; } diff --git a/board/netstar/netstar.c b/board/netstar/netstar.c index ffd60bfae0..df1704be35 100644 --- a/board/netstar/netstar.c +++ b/board/netstar/netstar.c @@ -21,6 +21,7 @@ */ #include +#include #include #include #include @@ -115,3 +116,14 @@ int board_nand_init(struct nand_chip *nand) return 0; } #endif + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} +#endif diff --git a/board/netta/u-boot.lds b/board/netta/u-boot.lds index 14201acce1..860c887c25 100644 --- a/board/netta/u-boot.lds +++ b/board/netta/u-boot.lds @@ -66,7 +66,6 @@ SECTIONS common/env_embedded.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/netta/u-boot.lds.debug b/board/netta/u-boot.lds.debug index d47c4082aa..4ef16f1ffe 100644 --- a/board/netta/u-boot.lds.debug +++ b/board/netta/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/netta2/u-boot.lds b/board/netta2/u-boot.lds index 14201acce1..860c887c25 100644 --- a/board/netta2/u-boot.lds +++ b/board/netta2/u-boot.lds @@ -66,7 +66,6 @@ SECTIONS common/env_embedded.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/netta2/u-boot.lds.debug b/board/netta2/u-boot.lds.debug index d47c4082aa..4ef16f1ffe 100644 --- a/board/netta2/u-boot.lds.debug +++ b/board/netta2/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/netvia/u-boot.lds b/board/netvia/u-boot.lds index 8c48f1f345..a7d290ae88 100644 --- a/board/netvia/u-boot.lds +++ b/board/netvia/u-boot.lds @@ -66,7 +66,6 @@ SECTIONS common/env_embedded.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/netvia/u-boot.lds.debug b/board/netvia/u-boot.lds.debug index 9210c43d52..c3c99b35c2 100644 --- a/board/netvia/u-boot.lds.debug +++ b/board/netvia/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/nx823/u-boot.lds b/board/nx823/u-boot.lds index ee74eb950a..5c847fbf84 100644 --- a/board/nx823/u-boot.lds +++ b/board/nx823/u-boot.lds @@ -56,7 +56,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/nx823/u-boot.lds.debug b/board/nx823/u-boot.lds.debug index dbec9860a9..ad36953915 100644 --- a/board/nx823/u-boot.lds.debug +++ b/board/nx823/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/pcippc2/u-boot.lds b/board/pcippc2/u-boot.lds index 4bb582dd37..d11bb056fb 100644 --- a/board/pcippc2/u-boot.lds +++ b/board/pcippc2/u-boot.lds @@ -66,7 +66,6 @@ SECTIONS /* common/env_embedded.o(.text) */ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index ac059a903b..b70827e0cc 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -626,22 +626,22 @@ void pci_target_init(struct pci_controller *hose) | Use byte reversed out routines to handle endianess. | Make this region non-prefetchable. +--------------------------------------------------------------------------*/ - out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ - out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ - - out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ - out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */ - out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */ - out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */ + out32r(PCIL0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIL0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIL0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */ + out32r(PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIL0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */ + + out32r(PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ + out32r(PCIL0_PTM1LA, 0); /* Local Addr. Reg */ + out32r(PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ + out32r(PCIL0_PTM2LA, 0); /* Local Addr. Reg */ /*--------------------------------------------------------------------------+ * Set up Configuration registers diff --git a/board/pcs440ep/u-boot.lds b/board/pcs440ep/u-boot.lds index a4c537ec0a..2f6109117d 100644 --- a/board/pcs440ep/u-boot.lds +++ b/board/pcs440ep/u-boot.lds @@ -67,7 +67,6 @@ SECTIONS lib_generic/sha1.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/ppmc7xx/u-boot.lds b/board/ppmc7xx/u-boot.lds index b0da216a5c..30e8972afa 100644 --- a/board/ppmc7xx/u-boot.lds +++ b/board/ppmc7xx/u-boot.lds @@ -63,7 +63,6 @@ SECTIONS /* common/env_embedded.o(.text) */ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c index cdb91ac36b..51335c4d9c 100644 --- a/board/prodrive/alpr/alpr.c +++ b/board/prodrive/alpr/alpr.c @@ -192,28 +192,28 @@ void pci_target_init(struct pci_controller * hose ) /*--------------------------------------------------------------------------+ * Disable everything *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0SA, 0 ); /* disable */ - out32r( PCIX0_PIM1SA, 0 ); /* disable */ - out32r( PCIX0_PIM2SA, 0 ); /* disable */ - out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + out32r( PCIL0_PIM0SA, 0 ); /* disable */ + out32r( PCIL0_PIM1SA, 0 ); /* disable */ + out32r( PCIL0_PIM2SA, 0 ); /* disable */ + out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ /*--------------------------------------------------------------------------+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIX0_PIM0LAH, 0 ); - out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); + out32r( PCIL0_PIM0LAH, 0 ); + out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - out32r( PCIX0_BAR0, 0 ); + out32r( PCIL0_BAR0, 0 ); /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); + out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); } #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ @@ -270,21 +270,21 @@ void pci_master_init(struct pci_controller *hose) | Use byte reversed out routines to handle endianess. | Make this region non-prefetchable. +--------------------------------------------------------------------------*/ - out32r( PCIX0_POM0SA, 0 ); /* disable */ - out32r( PCIX0_POM1SA, 0 ); /* disable */ - out32r( PCIX0_POM2SA, 0 ); /* disable */ - - out32r(PCIX0_POM0LAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ - out32r(PCIX0_POM0LAH, 0x00000003); /* PMM0 Local Address */ - out32r(PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ - out32r(PCIX0_POM0PCIAH, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_POM0SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ - - out32r(PCIX0_POM1LAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ - out32r(PCIX0_POM1LAH, 0x00000003); /* PMM0 Local Address */ - out32r(PCIX0_POM1PCIAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ - out32r(PCIX0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */ - out32r(PCIX0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ + out32r( PCIL0_POM0SA, 0 ); /* disable */ + out32r( PCIL0_POM1SA, 0 ); /* disable */ + out32r( PCIL0_POM2SA, 0 ); /* disable */ + + out32r(PCIL0_POM0LAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 Local Address */ + out32r(PCIL0_POM0LAH, 0x00000003); /* PMM0 Local Address */ + out32r(PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */ + out32r(PCIL0_POM0PCIAH, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_POM0SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ + + out32r(PCIL0_POM1LAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */ + out32r(PCIL0_POM1LAH, 0x00000003); /* PMM0 Local Address */ + out32r(PCIL0_POM1PCIAL, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */ + out32r(PCIL0_POM1PCIAH, 0x00000000); /* PMM0 PCI High Address */ + out32r(PCIL0_POM1SA, ~(0x10000000 - 1) | 1); /* 256MB + enable region */ } #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */ diff --git a/board/prodrive/alpr/fpga.c b/board/prodrive/alpr/fpga.c index 0ecebc943a..7571cd950c 100644 --- a/board/prodrive/alpr/fpga.c +++ b/board/prodrive/alpr/fpga.c @@ -244,8 +244,8 @@ int alpr_fpga_init (void) { int i; - PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off); - fpga_init (gd->reloc_off); + PRINTF ("%s:%d: Initialize FPGA interface\n", __FUNCTION__, __LINE__); + fpga_init (); for (i = 0; i < CONFIG_FPGA_COUNT; i++) { PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i); diff --git a/board/prodrive/alpr/u-boot.lds b/board/prodrive/alpr/u-boot.lds index e7c5fe61f7..6633f91c44 100644 --- a/board/prodrive/alpr/u-boot.lds +++ b/board/prodrive/alpr/u-boot.lds @@ -69,7 +69,6 @@ SECTIONS board/prodrive/alpr/init.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/prodrive/p3mx/p3mx.c b/board/prodrive/p3mx/p3mx.c index 0247bb80a4..05eca52e0e 100644 --- a/board/prodrive/p3mx/p3mx.c +++ b/board/prodrive/p3mx/p3mx.c @@ -316,16 +316,6 @@ int misc_init_r () return 0; } -int board_early_init_r(void) -{ - /* now relocate the debug serial driver */ - mpsc_putchar += gd->reloc_off; - mpsc_getchar += gd->reloc_off; - mpsc_test_char += gd->reloc_off; - - return 0; -} - void after_reloc (ulong dest_addr, gd_t * gd) { memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE, CONFIG_SYS_BOOT_SIZE); diff --git a/board/prodrive/p3mx/u-boot.lds b/board/prodrive/p3mx/u-boot.lds index 632921ae53..d021331148 100644 --- a/board/prodrive/p3mx/u-boot.lds +++ b/board/prodrive/p3mx/u-boot.lds @@ -63,7 +63,6 @@ SECTIONS /* common/env_embedded.o(.text) */ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c index 20fd4dc276..9a07852760 100644 --- a/board/prodrive/p3p440/p3p440.c +++ b/board/prodrive/p3p440/p3p440.c @@ -209,28 +209,28 @@ void pci_target_init(struct pci_controller *hose) /*--------------------------------------------------------------------------+ * Disable everything *--------------------------------------------------------------------------*/ - out32r(PCIX0_PIM0SA, 0); /* disable */ - out32r(PCIX0_PIM1SA, 0); /* disable */ - out32r(PCIX0_PIM2SA, 0); /* disable */ - out32r(PCIX0_EROMBA, 0); /* disable expansion rom */ + out32r(PCIL0_PIM0SA, 0); /* disable */ + out32r(PCIL0_PIM1SA, 0); /* disable */ + out32r(PCIL0_PIM2SA, 0); /* disable */ + out32r(PCIL0_EROMBA, 0); /* disable expansion rom */ /*--------------------------------------------------------------------------+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); - out32r(PCIX0_PIM0LAH, 0); - out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1); + out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); + out32r(PCIL0_PIM0LAH, 0); + out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1); - out32r(PCIX0_BAR0, 0); + out32r(PCIL0_BAR0, 0); /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); - out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); + out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); + out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); - out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY); + out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY); } #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ diff --git a/board/prodrive/p3p440/u-boot.lds b/board/prodrive/p3p440/u-boot.lds index 93279709a8..b1c2dfffe9 100644 --- a/board/prodrive/p3p440/u-boot.lds +++ b/board/prodrive/p3p440/u-boot.lds @@ -69,7 +69,6 @@ SECTIONS board/prodrive/p3p440/init.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/psyent/pk1c20/pk1c20.c b/board/psyent/pk1c20/pk1c20.c index 95b48bc57b..0a24866960 100644 --- a/board/psyent/pk1c20/pk1c20.c +++ b/board/psyent/pk1c20/pk1c20.c @@ -22,6 +22,7 @@ */ #include +#include int board_early_init_f (void) { @@ -38,3 +39,14 @@ phys_size_t initdram (int board_type) { return (0); } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} +#endif diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c index e9e479c4ba..05e30ecf00 100644 --- a/board/pxa255_idp/pxa_idp.c +++ b/board/pxa255_idp/pxa_idp.c @@ -31,6 +31,7 @@ */ #include +#include #include DECLARE_GLOBAL_DATA_PTR; @@ -133,3 +134,14 @@ U_BOOT_CMD(idpcmd, CONFIG_SYS_MAXARGS, 0, do_idpcmd, ); #endif + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} +#endif diff --git a/board/quad100hd/u-boot.lds b/board/quad100hd/u-boot.lds index 24d31a112b..4f359b72d7 100644 --- a/board/quad100hd/u-boot.lds +++ b/board/quad100hd/u-boot.lds @@ -61,7 +61,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/quantum/u-boot.lds b/board/quantum/u-boot.lds index faa1c6ccad..47247ec813 100644 --- a/board/quantum/u-boot.lds +++ b/board/quantum/u-boot.lds @@ -67,7 +67,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/quantum/u-boot.lds.debug b/board/quantum/u-boot.lds.debug index 016048dae2..ec01fe256b 100644 --- a/board/quantum/u-boot.lds.debug +++ b/board/quantum/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/r360mpi/u-boot.lds b/board/r360mpi/u-boot.lds index 61d4b11900..9089f7d6b6 100644 --- a/board/r360mpi/u-boot.lds +++ b/board/r360mpi/u-boot.lds @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o (.text) ***/ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/rbc823/u-boot.lds b/board/rbc823/u-boot.lds index 552f15d276..e0ea600d28 100644 --- a/board/rbc823/u-boot.lds +++ b/board/rbc823/u-boot.lds @@ -66,7 +66,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/renesas/MigoR/migo_r.c b/board/renesas/MigoR/migo_r.c index 204ca78fa4..c0f26ac1ea 100644 --- a/board/renesas/MigoR/migo_r.c +++ b/board/renesas/MigoR/migo_r.c @@ -24,6 +24,7 @@ */ #include +#include #include #include @@ -51,3 +52,14 @@ int dram_init (void) void led_set_state (unsigned short value) { } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} +#endif diff --git a/board/rmu/u-boot.lds b/board/rmu/u-boot.lds index faa1c6ccad..47247ec813 100644 --- a/board/rmu/u-boot.lds +++ b/board/rmu/u-boot.lds @@ -67,7 +67,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/rmu/u-boot.lds.debug b/board/rmu/u-boot.lds.debug index 016048dae2..ec01fe256b 100644 --- a/board/rmu/u-boot.lds.debug +++ b/board/rmu/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/rsdproto/u-boot.lds b/board/rsdproto/u-boot.lds index 771f7de657..0d4a9efb79 100644 --- a/board/rsdproto/u-boot.lds +++ b/board/rsdproto/u-boot.lds @@ -54,7 +54,6 @@ SECTIONS { cpu/mpc8260/start.o (.text) *(.text) - *(.fixup) *(.got1) /*. = env_offset; */ } diff --git a/board/sandburst/common/ppc440gx_i2c.h b/board/sandburst/common/ppc440gx_i2c.h index 328abd64b8..90f27caa0d 100644 --- a/board/sandburst/common/ppc440gx_i2c.h +++ b/board/sandburst/common/ppc440gx_i2c.h @@ -44,7 +44,7 @@ #define IIC_EXTSTS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICEXTSTS) #define IIC_LSADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICLSADR) #define IIC_HSADR1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICHSADR) -#define IIC_CLKDIV1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICCLKDIV) +#define IIC_CLKDIV1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IIC0_CLKDIV) #define IIC_INTRMSK1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICINTRMSK) #define IIC_XFRCNT1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXFRCNT) #define IIC_XTCNTLSS1 (I2C_REGISTERS_BUS1_BASE_ADDRESS+IICXTCNTLSS) diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c index e1c61463dd..a484874ea3 100644 --- a/board/sandburst/common/sb_common.c +++ b/board/sandburst/common/sb_common.c @@ -346,28 +346,28 @@ void pci_target_init(struct pci_controller * hose ) /*--------------------------------------------------------------------------+ * Disable everything *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0SA, 0 ); /* disable */ - out32r( PCIX0_PIM1SA, 0 ); /* disable */ - out32r( PCIX0_PIM2SA, 0 ); /* disable */ - out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ + out32r( PCIL0_PIM0SA, 0 ); /* disable */ + out32r( PCIL0_PIM1SA, 0 ); /* disable */ + out32r( PCIL0_PIM2SA, 0 ); /* disable */ + out32r( PCIL0_EROMBA, 0 ); /* disable expansion rom */ /*--------------------------------------------------------------------------+ * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. *--------------------------------------------------------------------------*/ - out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); - out32r( PCIX0_PIM0LAH, 0 ); - out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); + out32r( PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); + out32r( PCIL0_PIM0LAH, 0 ); + out32r( PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1 ); - out32r( PCIX0_BAR0, 0 ); + out32r( PCIL0_BAR0, 0 ); /*--------------------------------------------------------------------------+ * Program the board's subsystem id/vendor id *--------------------------------------------------------------------------*/ - out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); + out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); - out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); + out16r( PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY ); } #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ diff --git a/board/sandburst/karef/u-boot.lds b/board/sandburst/karef/u-boot.lds index f509100dc2..f22ece2647 100644 --- a/board/sandburst/karef/u-boot.lds +++ b/board/sandburst/karef/u-boot.lds @@ -84,7 +84,6 @@ SECTIONS /* common/env_embedded.o(.text)*/ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/sandburst/karef/u-boot.lds.debug b/board/sandburst/karef/u-boot.lds.debug index d00e252716..48fd579162 100644 --- a/board/sandburst/karef/u-boot.lds.debug +++ b/board/sandburst/karef/u-boot.lds.debug @@ -73,7 +73,6 @@ SECTIONS /* common/env_embedded.o(.text) */ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/sandburst/metrobox/u-boot.lds b/board/sandburst/metrobox/u-boot.lds index f1bc4a0ddf..c5851f22f0 100644 --- a/board/sandburst/metrobox/u-boot.lds +++ b/board/sandburst/metrobox/u-boot.lds @@ -84,7 +84,6 @@ SECTIONS /* common/env_embedded.o(.text)*/ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/sandburst/metrobox/u-boot.lds.debug b/board/sandburst/metrobox/u-boot.lds.debug index a3350f2792..4bc5ceac02 100644 --- a/board/sandburst/metrobox/u-boot.lds.debug +++ b/board/sandburst/metrobox/u-boot.lds.debug @@ -73,7 +73,6 @@ SECTIONS /* common/env_embedded.o(.text) */ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/sbc405/u-boot.lds b/board/sbc405/u-boot.lds index d9410fafb1..89edd67aa6 100644 --- a/board/sbc405/u-boot.lds +++ b/board/sbc405/u-boot.lds @@ -76,7 +76,6 @@ SECTIONS /* common/env_embedded.o(.text)*/ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/sbc8641d/u-boot.lds b/board/sbc8641d/u-boot.lds index f156d4fc11..b71a7d6e58 100644 --- a/board/sbc8641d/u-boot.lds +++ b/board/sbc8641d/u-boot.lds @@ -61,7 +61,6 @@ SECTIONS lib_ppc/extable.o (.text) lib_generic/zlib.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/sc3/u-boot.lds b/board/sc3/u-boot.lds index 75174e1b5d..16dc384015 100644 --- a/board/sc3/u-boot.lds +++ b/board/sc3/u-boot.lds @@ -77,7 +77,6 @@ SECTIONS /* common/env_embedded.o(.text)*/ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/siemens/CCM/u-boot.lds b/board/siemens/CCM/u-boot.lds index 61650a85fa..2d0efb3161 100644 --- a/board/siemens/CCM/u-boot.lds +++ b/board/siemens/CCM/u-boot.lds @@ -66,7 +66,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/siemens/CCM/u-boot.lds.debug b/board/siemens/CCM/u-boot.lds.debug index 88dbd3810f..29657e93ef 100644 --- a/board/siemens/CCM/u-boot.lds.debug +++ b/board/siemens/CCM/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) */ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/siemens/IAD210/u-boot.lds b/board/siemens/IAD210/u-boot.lds index 12a53ba70b..104b44ccff 100644 --- a/board/siemens/IAD210/u-boot.lds +++ b/board/siemens/IAD210/u-boot.lds @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/siemens/pcu_e/u-boot.lds b/board/siemens/pcu_e/u-boot.lds index 9e46f9d8bf..cc8ad7d3db 100644 --- a/board/siemens/pcu_e/u-boot.lds +++ b/board/siemens/pcu_e/u-boot.lds @@ -55,7 +55,6 @@ SECTIONS cpu/mpc8xx/start.o (.text) common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/siemens/pcu_e/u-boot.lds.debug b/board/siemens/pcu_e/u-boot.lds.debug index bd9d76ce20..987c4ddb9b 100644 --- a/board/siemens/pcu_e/u-boot.lds.debug +++ b/board/siemens/pcu_e/u-boot.lds.debug @@ -65,7 +65,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/sixnet/u-boot.lds b/board/sixnet/u-boot.lds index bde981b389..dd632a44ce 100644 --- a/board/sixnet/u-boot.lds +++ b/board/sixnet/u-boot.lds @@ -55,7 +55,6 @@ SECTIONS cpu/mpc8xx/start.o (.text) common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/snmc/qs850/u-boot.lds b/board/snmc/qs850/u-boot.lds index 7de0de8d9d..9ef2c201a2 100644 --- a/board/snmc/qs850/u-boot.lds +++ b/board/snmc/qs850/u-boot.lds @@ -69,7 +69,6 @@ SECTIONS common/env_embedded.o (.ppcenv) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/snmc/qs860t/u-boot.lds b/board/snmc/qs860t/u-boot.lds index 7de0de8d9d..9ef2c201a2 100644 --- a/board/snmc/qs860t/u-boot.lds +++ b/board/snmc/qs860t/u-boot.lds @@ -69,7 +69,6 @@ SECTIONS common/env_embedded.o (.ppcenv) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/spc1920/u-boot.lds b/board/spc1920/u-boot.lds index 4e221bc57e..d6711b5bf2 100644 --- a/board/spc1920/u-boot.lds +++ b/board/spc1920/u-boot.lds @@ -69,7 +69,6 @@ SECTIONS common/env_embedded.o (.ppcenv) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/spd8xx/u-boot.lds b/board/spd8xx/u-boot.lds index a06d8c6564..7b9455b252 100644 --- a/board/spd8xx/u-boot.lds +++ b/board/spd8xx/u-boot.lds @@ -55,7 +55,6 @@ SECTIONS cpu/mpc8xx/start.o (.text) common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/spd8xx/u-boot.lds.debug b/board/spd8xx/u-boot.lds.debug index 67d37ae334..0a3b958fad 100644 --- a/board/spd8xx/u-boot.lds.debug +++ b/board/spd8xx/u-boot.lds.debug @@ -65,7 +65,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/st/nhk8815/nhk8815.c b/board/st/nhk8815/nhk8815.c index 1fa506a889..faef8109db 100644 --- a/board/st/nhk8815/nhk8815.c +++ b/board/st/nhk8815/nhk8815.c @@ -26,6 +26,7 @@ */ #include +#include #include #include @@ -89,3 +90,14 @@ int dram_init(void) gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; return 0; } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} +#endif diff --git a/board/stx/stxxtc/u-boot.lds b/board/stx/stxxtc/u-boot.lds index 14201acce1..860c887c25 100644 --- a/board/stx/stxxtc/u-boot.lds +++ b/board/stx/stxxtc/u-boot.lds @@ -66,7 +66,6 @@ SECTIONS common/env_embedded.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/stx/stxxtc/u-boot.lds.debug b/board/stx/stxxtc/u-boot.lds.debug index d47c4082aa..4ef16f1ffe 100644 --- a/board/stx/stxxtc/u-boot.lds.debug +++ b/board/stx/stxxtc/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/svm_sc8xx/u-boot.lds b/board/svm_sc8xx/u-boot.lds index 11a819a03f..02aa9dd987 100644 --- a/board/svm_sc8xx/u-boot.lds +++ b/board/svm_sc8xx/u-boot.lds @@ -69,7 +69,6 @@ SECTIONS common/env_embedded.o (.ppcenv) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/svm_sc8xx/u-boot.lds.debug b/board/svm_sc8xx/u-boot.lds.debug index 016048dae2..ec01fe256b 100644 --- a/board/svm_sc8xx/u-boot.lds.debug +++ b/board/svm_sc8xx/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/ti/sdp3430/Makefile b/board/ti/sdp3430/Makefile new file mode 100644 index 0000000000..2554c7b081 --- /dev/null +++ b/board/ti/sdp3430/Makefile @@ -0,0 +1,49 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := sdp.o + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/ti/sdp3430/config.mk b/board/ti/sdp3430/config.mk new file mode 100644 index 0000000000..18e4761abd --- /dev/null +++ b/board/ti/sdp3430/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2006-2009 +# Texas Instruments Incorporated, +# +# OMAP 3430 SDP uses OMAP3 (ARM-CortexA8) cpu +# see http://www.ti.com/ for more information on Texas Instruments +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# Physical Address: +# 8000'0000 (bank0) +# A000/0000 (bank1) +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) + +# For use with external or internal boots. +TEXT_BASE = 0x80e80000 diff --git a/board/ti/sdp3430/sdp.c b/board/ti/sdp3430/sdp.c new file mode 100644 index 0000000000..40cf26f42a --- /dev/null +++ b/board/ti/sdp3430/sdp.c @@ -0,0 +1,204 @@ +/* + * (C) Copyright 2004-2009 + * Texas Instruments Incorporated, + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include "sdp.h" + +const omap3_sysinfo sysinfo = { + DDR_DISCRETE, + "OMAP3 SDP3430 board", +#if defined(CONFIG_ENV_IS_IN_ONENAND) + "OneNAND", +#elif defined(CONFIG_ENV_IS_IN_NAND) + "NAND", +#else + "NOR", +#endif +}; + +/* Timing definitions for GPMC controller for Sibley NOR */ +static const u32 gpmc_sdp_nor[] = { + SDP3430_NOR_GPMC_CONF1, + SDP3430_NOR_GPMC_CONF2, + SDP3430_NOR_GPMC_CONF3, + SDP3430_NOR_GPMC_CONF4, + SDP3430_NOR_GPMC_CONF5, + SDP3430_NOR_GPMC_CONF6, + /*CONF7- computed as params */ +}; + +/* + * Timing definitions for GPMC controller for Debug Board + * Debug board contains access to ethernet and DIP Switch setting + * information etc. + */ +static const u32 gpmc_sdp_debug[] = { + SDP3430_DEBUG_GPMC_CONF1, + SDP3430_DEBUG_GPMC_CONF2, + SDP3430_DEBUG_GPMC_CONF3, + SDP3430_DEBUG_GPMC_CONF4, + SDP3430_DEBUG_GPMC_CONF5, + SDP3430_DEBUG_GPMC_CONF6, + /*CONF7- computed as params */ +}; + +/* Timing defintions for GPMC OneNAND */ +static const u32 gpmc_sdp_onenand[] = { + SDP3430_ONENAND_GPMC_CONF1, + SDP3430_ONENAND_GPMC_CONF2, + SDP3430_ONENAND_GPMC_CONF3, + SDP3430_ONENAND_GPMC_CONF4, + SDP3430_ONENAND_GPMC_CONF5, + SDP3430_ONENAND_GPMC_CONF6, + /*CONF7- computed as params */ +}; + +/* GPMC definitions for GPMC NAND */ +static const u32 gpmc_sdp_nand[] = { + SDP3430_NAND_GPMC_CONF1, + SDP3430_NAND_GPMC_CONF2, + SDP3430_NAND_GPMC_CONF3, + SDP3430_NAND_GPMC_CONF4, + SDP3430_NAND_GPMC_CONF5, + SDP3430_NAND_GPMC_CONF6, + /*CONF7- computed as params */ +}; + +/* gpmc_cfg is initialized by gpmc_init and we use it here */ +extern struct gpmc *gpmc_cfg; + +/** + * @brief board_init - gpmc and basic setup as phase1 of boot sequence + * + * @return 0 + */ +int board_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* TODO: Dynamically pop out CS mapping and program accordingly */ + /* Configure devices for default ON ON ON settings */ + enable_gpmc_cs_config(gpmc_sdp_nor, &gpmc_cfg->cs[0], + CONFIG_SYS_FLASH_BASE, GPMC_SIZE_128M); + enable_gpmc_cs_config(gpmc_sdp_nand, &gpmc_cfg->cs[1], 0x28000000, + GPMC_SIZE_16M); + enable_gpmc_cs_config(gpmc_sdp_onenand, &gpmc_cfg->cs[2], 0x20000000, + GPMC_SIZE_16M); + enable_gpmc_cs_config(gpmc_sdp_debug, &gpmc_cfg->cs[3], DEBUG_BASE, + GPMC_SIZE_16M); + /* board id for Linux */ + gd->bd->bi_arch_number = MACH_TYPE_OMAP_3430SDP; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + + return 0; +} + +#define LAN_RESET_REGISTER (CONFIG_LAN91C96_BASE + 0x01c) +#define ETH_CONTROL_REG (CONFIG_LAN91C96_BASE + 0x30b) + +/** + * @brief ether_init Take the Ethernet controller out of reset and wait + * for the EEPROM load to complete. + */ +static void ether_init(void) +{ +#ifdef CONFIG_DRIVER_LAN91C96 + int cnt = 20; + + writew(0x0, LAN_RESET_REGISTER); + do { + writew(0x1, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) + goto reset_err_out; + --cnt; + } while (readw(LAN_RESET_REGISTER) != 0x1); + + cnt = 20; + + do { + writew(0x0, LAN_RESET_REGISTER); + udelay(100); + if (cnt == 0) + goto reset_err_out; + --cnt; + } while (readw(LAN_RESET_REGISTER) != 0x0000); + udelay(1000); + + writeb(readb(ETH_CONTROL_REG) & ~0x1, ETH_CONTROL_REG); + udelay(1000); +reset_err_out: + return; + +#endif +} + +/** + * @brief misc_init_r - Configure SDP board specific configurations + * such as power configurations, ethernet initialization as phase2 of + * boot sequence + * + * @return 0 + */ +int misc_init_r(void) +{ + /* Partial setup: + * VAUX3 - 2.8V for DVI + * VPLL1 - 1.8V + * VDAC - 1.8V + * and turns on LEDA/LEDB (not needed ... NOP?) + */ + twl4030_power_init(); + + /* FIXME finish setup: + * VAUX1 - 2.8V for mainboard I/O + * VAUX2 - 2.8V for camera + * VAUX4 - 1.8V for OMAP3 CSI + * VMMC1 - 3.15V (init, variable) for MMC1 + * VMMC2 - 1.85V for MMC2 + * VSIM - off (init, variable) for MMC1.DAT[3..7], SIM + * VPLL2 - 1.8V + */ + ether_init(); + + return 0; +} + +/** + * @brief set_muxconf_regs Setting up the configuration Mux registers + * specific to the hardware. Many pins need to be moved from protect + * to primary mode. + */ +void set_muxconf_regs(void) +{ + /* platform specific muxes */ + MUX_SDP3430(); +} diff --git a/board/ti/sdp3430/sdp.h b/board/ti/sdp3430/sdp.h new file mode 100644 index 0000000000..3526e94672 --- /dev/null +++ b/board/ti/sdp3430/sdp.h @@ -0,0 +1,417 @@ +/* + * (C) Copyright 2004-2009 + * Texas Instruments Incorporated + * Richard Woodruff + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _BOARD_SDP_H_ +#define _BOARD_SDP_H_ + +#define OFF_IN_PD 0 +#define OFF_OUT_PD 0 + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_SDP3430()\ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0))\ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_A2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_A3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_A4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_A5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_A6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_A7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_A8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_A9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_A10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D0), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D1), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D12), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D13), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D14), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_D15), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_NCS0), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_NCS1), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_NCS2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_NCS3), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_NCS4), (OFF_IN_PD | IEN | PTU | EN | M4)) /*G55-F_DIS*/\ + MUX_VAL(CP(GPMC_NCS5), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G56T_EN*/\ + MUX_VAL(CP(GPMC_NCS6), (OFF_IN_PD | IEN | PTD | DIS | M4))/*G57-AGPSP*/\ + MUX_VAL(CP(GPMC_NCS7), (OFF_IN_PD | IEN | PTU | EN | M4))/*G58-WLNIQ*/\ + MUX_VAL(CP(GPMC_CLK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_NADV_ALE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_NOE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_NWE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_NBE0_CLE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_NBE1), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*G61-BTST*/\ + MUX_VAL(CP(GPMC_NWP), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(GPMC_WAIT0), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_WAIT1), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(GPMC_WAIT2), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_64*/\ + MUX_VAL(CP(GPMC_WAIT3), (OFF_IN_PD | IEN | PTU | EN | M4)) /*GPIO_65*/\ + /*DSS*/\ + MUX_VAL(CP(DSS_PCLK), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_HSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_VSYNC), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_ACBIAS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA0), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA1), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA3), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA4), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA5), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA6), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA7), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA8), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA9), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA10), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA11), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA12), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA13), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA14), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA15), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA16), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA17), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA18), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA19), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA20), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA21), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA22), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(DSS_DATA23), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + /*CAMERA*/\ + MUX_VAL(CP(CAM_HS), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(CAM_VS), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(CAM_XCLKA), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(CAM_PCLK), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(CAM_FLD), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G98-C_RST*/\ + MUX_VAL(CP(CAM_D0), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D0 */\ + MUX_VAL(CP(CAM_D1), (OFF_IN_PD | IEN | PTD | DIS | M2)) /*CAM_D1 */\ + MUX_VAL(CP(CAM_D2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CAM_D3), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CAM_D4), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CAM_D5), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CAM_D6), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CAM_D7), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CAM_D8), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CAM_D9), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CAM_D10), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CAM_D11), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CAM_XCLKB), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(CAM_WEN), (OFF_IN_PD | IEN | PTD | DIS | M4)) /*GPIO_167*/\ + MUX_VAL(CP(CAM_STROBE), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(CSI2_DX0), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CSI2_DY0), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CSI2_DX1), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(CSI2_DY1), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + /*Audio InterfACe */\ + MUX_VAL(CP(MCBSP2_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP2_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP2_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP2_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + /*Expansion Card */\ + MUX_VAL(CP(MMC1_CLK), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ + MUX_VAL(CP(MMC1_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC1_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC1_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC1_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC1_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC1_DAT4), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC1_DAT5), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC1_DAT6), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC1_DAT7), (OFF_IN_PD | IEN | PTU | EN | M0))\ + /*Wireless LAN */\ + MUX_VAL(CP(MMC2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MMC2_CMD), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC2_DAT0), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC2_DAT1), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC2_DAT2), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC2_DAT3), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MMC2_DAT4), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD0*/\ + MUX_VAL(CP(MMC2_DAT5), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DRD1*/\ + MUX_VAL(CP(MMC2_DAT6), (OFF_OUT_PD | IDIS | PTD | DIS | M1))/*DCMD*/\ + MUX_VAL(CP(MMC2_DAT7), (OFF_IN_PD | IEN | PTU | EN | M1))/*CLKIN*/\ + /*Bluetooth*/\ + MUX_VAL(CP(MCBSP3_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP3_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP3_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP3_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(UART2_CTS), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(UART2_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(UART2_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(UART2_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + /*Modem Interface */\ + MUX_VAL(CP(UART1_TX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(UART1_RTS), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(UART1_CTS), (OFF_IN_PD | IEN | PTU | DIS | M0))\ + MUX_VAL(CP(UART1_RX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP4_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1DRX*/\ + MUX_VAL(CP(MCBSP4_DR), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1FLGRX*/\ + MUX_VAL(CP(MCBSP4_DX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1RDYRX*/\ + MUX_VAL(CP(MCBSP4_FSX), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SSI1WAKE*/\ + MUX_VAL(CP(MCBSP1_CLKR), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP1_FSR), (OFF_OUT_PD | IDIS | PTU | EN | M4))/*G157BWP*/\ + MUX_VAL(CP(MCBSP1_DX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP1_DR), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP_CLKS), (OFF_IN_PD | IEN | PTU | DIS | M0))\ + MUX_VAL(CP(MCBSP1_FSX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCBSP1_CLKX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + /*Serial Interface*/\ + MUX_VAL(CP(UART3_CTS_RCTX), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(UART3_RTS_SD), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(UART3_RX_IRRX), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(UART3_TX_IRTX), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(HSUSB0_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(HSUSB0_STP), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ + MUX_VAL(CP(HSUSB0_DIR), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(HSUSB0_NXT), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(HSUSB0_DATA0), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(HSUSB0_DATA1), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(HSUSB0_DATA2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(HSUSB0_DATA3), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(HSUSB0_DATA4), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(HSUSB0_DATA5), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(HSUSB0_DATA6), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(HSUSB0_DATA7), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + /* NOTE db: removed off-mode from I2C 1/2/3 ... external pullups!! */\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | EN | M0))\ + MUX_VAL(CP(HDQ_SIO), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(MCSPI1_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCSPI1_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCSPI1_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCSPI1_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(MCSPI1_CS1), (OFF_OUT_PD | IDIS | PTD | EN | M0))\ + MUX_VAL(CP(MCSPI1_CS2), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G176*/\ + MUX_VAL(CP(MCSPI1_CS3), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(MCSPI2_CLK), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCSPI2_SIMO), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCSPI2_SOMI), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(MCSPI2_CS0), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(MCSPI2_CS1), (OFF_IN_PD | IEN | PTD | EN | M0))\ + /*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SYS_CLKREQ), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SYS_NIRQ), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(SYS_BOOT0), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G2PENIRQ*/\ + MUX_VAL(CP(SYS_BOOT1), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*GPIO_3 */\ + MUX_VAL(CP(SYS_BOOT2), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G4MMC1WP*/\ + MUX_VAL(CP(SYS_BOOT3), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G5LCDENV*/\ + MUX_VAL(CP(SYS_BOOT4), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G6LANINT*/\ + MUX_VAL(CP(SYS_BOOT5), (OFF_OUT_PD | IEN | PTD | DIS | M4))/*G7MMC2WP*/\ + MUX_VAL(CP(SYS_BOOT6), (OFF_OUT_PD | IDIS | PTD | DIS | M4))/*G8ENBKL*/\ + MUX_VAL(CP(SYS_OFF_MODE), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SYS_CLKOUT1), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SYS_CLKOUT2), (OFF_IN_PD | IEN | PTU | EN | M4))/*GPIO_186*/\ + MUX_VAL(CP(JTAG_nTRST), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(JTAG_TCK), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(JTAG_TMS), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(JTAG_TDI), (IEN | PTD | DIS | M0))\ + MUX_VAL(CP(JTAG_EMU0), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(JTAG_EMU1), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_CLK_ES2), (OFF_OUT_PD | IDIS | PTU | EN | M0))\ + MUX_VAL(CP(ETK_CTL_ES2), (OFF_OUT_PD | IDIS | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_D0_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD0*/\ + MUX_VAL(CP(ETK_D1_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*SPI3_CS0*/\ + MUX_VAL(CP(ETK_D2_ES2), (OFF_IN_PD | IEN | PTD | EN | M1))/*USB1TLD2*/\ + MUX_VAL(CP(ETK_D3_ES2), (OFF_IN_PD | IEN | PTD | DIS | M1))/*USB1TLD7*/\ + MUX_VAL(CP(ETK_D4_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_D5_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_D6_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_D7_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_D8_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_D9_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_D10_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_D11_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_D12_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_D13_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_D14_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(ETK_D15_ES2), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + /*Die to Die */\ + MUX_VAL(CP(D2D_MCAD0), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD1), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD2), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD3), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD4), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD5), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD6), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD7), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD8), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD9), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD10), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD11), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD12), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD13), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD14), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD15), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD16), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD17), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD18), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD19), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD20), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD21), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD22), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD23), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD24), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD25), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD26), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD27), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD28), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD29), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD30), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD31), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD32), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD33), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD34), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD35), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_MCAD36), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_CLK26MI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_NRESPWRON), (OFF_OUT_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_NRESWARM), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(D2D_ARM9NIRQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_UMA2P6FIQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_SPINT), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_FRINT), (OFF_IN_PD | IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_DMAREQ0), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_DMAREQ1), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_DMAREQ2), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_DMAREQ3), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_N3GTRST), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_N3GTDI), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_N3GTDO), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_N3GTMS), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_N3GTCK), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_N3GRTCK), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_MSTDBY), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(D2D_SWAKEUP), (IEN | PTD | EN | M0))\ + MUX_VAL(CP(D2D_IDLEREQ), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_IDLEACK), (OFF_IN_PD | IEN | PTU | EN | M0))\ + MUX_VAL(CP(D2D_MWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_SWRITE), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_MREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_SREAD), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_MBUSFLAG), (OFF_IN_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(D2D_SBUSFLAG), (OFF_OUT_PD | IEN | PTD | DIS | M0))\ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0))\ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7)) /*SDRC_CKE1 NOT USED*/ + +/* + * GPMC Timing definitions for SDP3430 + * at L3 = 166Mhz + */ + +/* Timing definitions for GPMC controller for Sibley NOR */ +#define SDP3430_NOR_GPMC_CONF1 0x00001200 +#define SDP3430_NOR_GPMC_CONF2 0x001F1F00 +#define SDP3430_NOR_GPMC_CONF3 0x00080802 +#define SDP3430_NOR_GPMC_CONF4 0x1C091C09 +#define SDP3430_NOR_GPMC_CONF5 0x01131F1F +#define SDP3430_NOR_GPMC_CONF6 0x1F0F03C2 + +/* + * Timing definitions for GPMC controller for Debug Board + * Debug board contains access to ethernet and DIP Switch setting + * information etc. + */ +#define SDP3430_DEBUG_GPMC_CONF1 0x00611200 +#define SDP3430_DEBUG_GPMC_CONF2 0x001F1F01 +#define SDP3430_DEBUG_GPMC_CONF3 0x00080803 +#define SDP3430_DEBUG_GPMC_CONF4 0x1D091D09 +#define SDP3430_DEBUG_GPMC_CONF5 0x041D1F1F +#define SDP3430_DEBUG_GPMC_CONF6 0x1D0904C4 + +/* Timing defintions for GPMC OneNAND */ +#define SDP3430_ONENAND_GPMC_CONF1 0x00001200 +#define SDP3430_ONENAND_GPMC_CONF2 0x000F0F01 +#define SDP3430_ONENAND_GPMC_CONF3 0x00030301 +#define SDP3430_ONENAND_GPMC_CONF4 0x0F040F04 +#define SDP3430_ONENAND_GPMC_CONF5 0x010F1010 +#define SDP3430_ONENAND_GPMC_CONF6 0x1F060000 + +/* GPMC definitions for GPMC NAND */ +#define SDP3430_NAND_GPMC_CONF1 0x00000800 +#define SDP3430_NAND_GPMC_CONF2 0x00141400 +#define SDP3430_NAND_GPMC_CONF3 0x00141400 +#define SDP3430_NAND_GPMC_CONF4 0x0F010F01 +#define SDP3430_NAND_GPMC_CONF5 0x010C1414 +#define SDP3430_NAND_GPMC_CONF6 0x1F040A80 + +#endif /* _BOARD_SDP_H_ */ diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c index faa2e02191..5a091c40d7 100644 --- a/board/tqc/tqm5200/tqm5200.c +++ b/board/tqc/tqm5200/tqm5200.c @@ -358,11 +358,9 @@ int post_hotkeys_pressed(void) gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO; /* - * Configure PSC6_1 and PSC6_3 as GPIO. PSC6 then couldn't be used in - * CODEC or UART mode. Consumer IrDA should still be possible. + * Configure PSC6_0 through PSC6_3 as GPIO. */ - gpio->port_config &= ~(0x07000000); - gpio->port_config |= 0x03000000; + gpio->port_config &= ~(0x00700000); /* Enable GPIO for GPIO_IRDA_1 (IR_USB_CLK pin) = PSC6_3 */ gpio->simple_gpioe |= 0x20000000; diff --git a/board/tqc/tqm8xx/u-boot.lds b/board/tqc/tqm8xx/u-boot.lds index 19c1541fe2..2df8d8459c 100644 --- a/board/tqc/tqm8xx/u-boot.lds +++ b/board/tqc/tqm8xx/u-boot.lds @@ -68,7 +68,6 @@ SECTIONS common/env_embedded.o (.ppcenv) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/tqc/tqm8xx/u-boot.lds.debug b/board/tqc/tqm8xx/u-boot.lds.debug index ea8538900c..a2d940f048 100644 --- a/board/tqc/tqm8xx/u-boot.lds.debug +++ b/board/tqc/tqm8xx/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/uc100/u-boot.lds b/board/uc100/u-boot.lds index 1450d37bd4..e3ea52aede 100644 --- a/board/uc100/u-boot.lds +++ b/board/uc100/u-boot.lds @@ -68,7 +68,6 @@ SECTIONS common/env_embedded.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/uc100/u-boot.lds.debug b/board/uc100/u-boot.lds.debug index 5750657111..edaa4020a9 100644 --- a/board/uc100/u-boot.lds.debug +++ b/board/uc100/u-boot.lds.debug @@ -63,7 +63,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/v37/u-boot.lds b/board/v37/u-boot.lds index d24289c25d..6f2ea9a613 100644 --- a/board/v37/u-boot.lds +++ b/board/v37/u-boot.lds @@ -71,7 +71,6 @@ SECTIONS common/env_embedded.o (.ppcenv) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/voiceblue/eeprom.c b/board/voiceblue/eeprom.c index f01597ad10..2ae46d10cd 100644 --- a/board/voiceblue/eeprom.c +++ b/board/voiceblue/eeprom.c @@ -27,43 +27,42 @@ #include #include #include +#include #include "../drivers/net/smc91111.h" -#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE - -static u16 read_eeprom_reg(u16 reg) +static u16 read_eeprom_reg(struct eth_device *dev, u16 reg) { int timeout; - SMC_SELECT_BANK(2); - SMC_outw(reg, PTR_REG); + SMC_SELECT_BANK(dev, 2); + SMC_outw(dev, reg, PTR_REG); - SMC_SELECT_BANK(1); - SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD, + SMC_SELECT_BANK(dev, 1); + SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD, CTL_REG); timeout = 100; - while((SMC_inw (CTL_REG) & CTL_RELOAD) && --timeout) + while((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --timeout) udelay(100); if (timeout == 0) { printf("Timeout Reading EEPROM register %02x\n", reg); return 0; } - return SMC_inw (GP_REG); + return SMC_inw (dev, GP_REG); } -static int write_eeprom_reg(u16 value, u16 reg) +static int write_eeprom_reg(struct eth_device *dev, u16 value, u16 reg) { int timeout; - SMC_SELECT_BANK(2); - SMC_outw(reg, PTR_REG); + SMC_SELECT_BANK(dev, 2); + SMC_outw(dev, reg, PTR_REG); - SMC_SELECT_BANK(1); - SMC_outw(value, GP_REG); - SMC_outw(SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG); + SMC_SELECT_BANK(dev, 1); + SMC_outw(dev, value, GP_REG); + SMC_outw(dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG); timeout = 100; - while ((SMC_inw(CTL_REG) & CTL_STORE) && --timeout) + while ((SMC_inw(dev, CTL_REG) & CTL_STORE) && --timeout) udelay (100); if (timeout == 0) { printf("Timeout Writing EEPROM register %02x\n", reg); @@ -73,17 +72,17 @@ static int write_eeprom_reg(u16 value, u16 reg) return 1; } -static int write_data(u16 *buf, int len) +static int write_data(struct eth_device *dev, u16 *buf, int len) { u16 reg = 0x23; while (len--) - write_eeprom_reg(*buf++, reg++); + write_eeprom_reg(dev, *buf++, reg++); return 0; } -static int verify_macaddr(char *s) +static int verify_macaddr(struct eth_device *dev, char *s) { u16 reg; int i, err = 0; @@ -91,7 +90,7 @@ static int verify_macaddr(char *s) printf("MAC Address: "); err = i = 0; for (i = 0; i < 3; i++) { - reg = read_eeprom_reg(0x20 + i); + reg = read_eeprom_reg(dev, 0x20 + i); printf("%02x:%02x%c", reg & 0xff, reg >> 8, i != 2 ? ':' : '\n'); if (s) err |= reg != ((u16 *)s)[i]; @@ -100,7 +99,7 @@ static int verify_macaddr(char *s) return err ? 0 : 1; } -static int set_mac(char *s) +static int set_mac(struct eth_device *dev, char *s) { int i; char *e, eaddr[6]; @@ -112,7 +111,7 @@ static int set_mac(char *s) } for (i = 0; i < 3; i++) - write_eeprom_reg(*(((u16 *)eaddr) + i), 0x20 + i); + write_eeprom_reg(dev, *(((u16 *)eaddr) + i), 0x20 + i); return 0; } @@ -148,6 +147,10 @@ int eeprom(int argc, char *argv[]) int i, len, ret; unsigned char buf[58], *p; + struct eth_device dev = { + .iobase = CONFIG_SMC91111_BASE + }; + app_startup(argv); if (get_version() != XF_VERSION) { printf("Wrong XF_VERSION.\n"); @@ -156,14 +159,14 @@ int eeprom(int argc, char *argv[]) return 1; } - if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) { + if ((SMC_inw (&dev, BANK_SELECT) & 0xFF00) != 0x3300) { printf("SMSC91111 not found.\n"); return 2; } /* Called without parameters - print MAC address */ if (argc < 2) { - verify_macaddr(NULL); + verify_macaddr(&dev, NULL); return 0; } @@ -197,8 +200,8 @@ int eeprom(int argc, char *argv[]) } /* First argument (MAC) is mandatory */ - set_mac(argv[1]); - if (verify_macaddr(argv[1])) { + set_mac(&dev, argv[1]); + if (verify_macaddr(&dev, argv[1])) { printf("*** MAC address does not match! ***\n"); return 4; } @@ -206,7 +209,7 @@ int eeprom(int argc, char *argv[]) while (len--) *p++ = 0; - write_data((u16 *)buf, sizeof(buf) >> 1); + write_data(&dev, (u16 *)buf, sizeof(buf) >> 1); return 0; } diff --git a/board/voiceblue/voiceblue.c b/board/voiceblue/voiceblue.c index 59b3310ae8..5f8af2bd24 100644 --- a/board/voiceblue/voiceblue.c +++ b/board/voiceblue/voiceblue.c @@ -20,6 +20,7 @@ */ #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -66,3 +67,14 @@ int board_late_init(void) return 0; } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} +#endif diff --git a/board/w7o/u-boot.lds b/board/w7o/u-boot.lds index 191a17920a..d953fd4bd6 100644 --- a/board/w7o/u-boot.lds +++ b/board/w7o/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) board/w7o/init.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/w7o/u-boot.lds.debug b/board/w7o/u-boot.lds.debug index d2089de9d4..8bb4929a46 100644 --- a/board/w7o/u-boot.lds.debug +++ b/board/w7o/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/westel/amx860/u-boot.lds b/board/westel/amx860/u-boot.lds index 61650a85fa..2d0efb3161 100644 --- a/board/westel/amx860/u-boot.lds +++ b/board/westel/amx860/u-boot.lds @@ -66,7 +66,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/westel/amx860/u-boot.lds.debug b/board/westel/amx860/u-boot.lds.debug index dbd1f9d106..653e0be45c 100644 --- a/board/westel/amx860/u-boot.lds.debug +++ b/board/westel/amx860/u-boot.lds.debug @@ -65,7 +65,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/xaeniax/xaeniax.c b/board/xaeniax/xaeniax.c index 9baa457c04..4c19c4dd4e 100644 --- a/board/xaeniax/xaeniax.c +++ b/board/xaeniax/xaeniax.c @@ -29,6 +29,7 @@ */ #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -71,3 +72,14 @@ int dram_init (void) return 0; } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} +#endif diff --git a/board/xes/xpedite1000/u-boot.lds b/board/xes/xpedite1000/u-boot.lds index 46b52fc535..73f65d61b3 100644 --- a/board/xes/xpedite1000/u-boot.lds +++ b/board/xes/xpedite1000/u-boot.lds @@ -79,7 +79,6 @@ SECTIONS lib_generic/zlib.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/xes/xpedite1000/u-boot.lds.debug b/board/xes/xpedite1000/u-boot.lds.debug index 68cd72d12d..d00834eef3 100644 --- a/board/xes/xpedite1000/u-boot.lds.debug +++ b/board/xes/xpedite1000/u-boot.lds.debug @@ -71,7 +71,6 @@ SECTIONS /* common/env_embedded.o(.text) */ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/xes/xpedite1000/xpedite1000.c b/board/xes/xpedite1000/xpedite1000.c index 011fb94bb6..04949bb2d4 100644 --- a/board/xes/xpedite1000/xpedite1000.c +++ b/board/xes/xpedite1000/xpedite1000.c @@ -156,7 +156,7 @@ int pci_pre_init(struct pci_controller * hose) return 0; #if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV) - /* Setup System Device Register PCIX0_XCR */ + /* Setup System Device Register PCIL0_XCR */ mfsdr(SDR0_XCR, strap); strap &= 0x0f000000; mtsdr(SDR0_XCR, strap); @@ -175,26 +175,26 @@ int pci_pre_init(struct pci_controller * hose) void pci_target_init(struct pci_controller * hose) { /* Disable everything */ - out32r(PCIX0_PIM0SA, 0); - out32r(PCIX0_PIM1SA, 0); - out32r(PCIX0_PIM2SA, 0); - out32r(PCIX0_EROMBA, 0); /* disable expansion rom */ + out32r(PCIL0_PIM0SA, 0); + out32r(PCIL0_PIM1SA, 0); + out32r(PCIL0_PIM2SA, 0); + out32r(PCIL0_EROMBA, 0); /* disable expansion rom */ /* * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * options to not support sizes such as 128/256 MB. */ - out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); - out32r(PCIX0_PIM0LAH, 0); - out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1); + out32r(PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); + out32r(PCIL0_PIM0LAH, 0); + out32r(PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1); - out32r(PCIX0_BAR0, 0); + out32r(PCIL0_BAR0, 0); /* Program the board's subsystem id/vendor id */ - out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); - out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); + out16r(PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); + out16r(PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); - out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY); + out16r(PCIL0_CMD, in16r(PCIL0_CMD) | PCI_COMMAND_MEMORY); } #endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ diff --git a/board/xes/xpedite5170/config.mk b/board/xes/xpedite5170/config.mk index 77c5785bb7..1abae973f0 100644 --- a/board/xes/xpedite5170/config.mk +++ b/board/xes/xpedite5170/config.mk @@ -25,5 +25,3 @@ # XPedite5170 # TEXT_BASE = 0xfff00000 - -PLATFORM_RELFLAGS += -mrelocatable diff --git a/board/xes/xpedite5200/config.mk b/board/xes/xpedite5200/config.mk index fbfbc2b5a7..0761579d9d 100644 --- a/board/xes/xpedite5200/config.mk +++ b/board/xes/xpedite5200/config.mk @@ -27,5 +27,3 @@ ifndef TEXT_BASE TEXT_BASE = 0xfff80000 endif - -PLATFORM_CPPFLAGS += -mrelocatable diff --git a/board/xes/xpedite5370/config.mk b/board/xes/xpedite5370/config.mk index 7b8d06b157..995def8759 100644 --- a/board/xes/xpedite5370/config.mk +++ b/board/xes/xpedite5370/config.mk @@ -27,5 +27,3 @@ ifndef TEXT_BASE TEXT_BASE = 0xfff80000 endif - -PLATFORM_RELFLAGS += -mrelocatable diff --git a/board/xilinx/ml300/u-boot.lds b/board/xilinx/ml300/u-boot.lds index fa60e6b053..b9899408d8 100644 --- a/board/xilinx/ml300/u-boot.lds +++ b/board/xilinx/ml300/u-boot.lds @@ -74,7 +74,6 @@ SECTIONS /* common/env_embedded.o(.text)*/ *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/xilinx/ml300/u-boot.lds.debug b/board/xilinx/ml300/u-boot.lds.debug index 338392a075..970628d556 100644 --- a/board/xilinx/ml300/u-boot.lds.debug +++ b/board/xilinx/ml300/u-boot.lds.debug @@ -64,7 +64,6 @@ SECTIONS common/env_embedded.o(.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/xilinx/ppc405-generic/u-boot-ram.lds b/board/xilinx/ppc405-generic/u-boot-ram.lds index 908d84b0c0..2543c9b060 100644 --- a/board/xilinx/ppc405-generic/u-boot-ram.lds +++ b/board/xilinx/ppc405-generic/u-boot-ram.lds @@ -57,7 +57,6 @@ SECTIONS *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/xilinx/ppc405-generic/u-boot-rom.lds b/board/xilinx/ppc405-generic/u-boot-rom.lds index 592976a45b..02044e43d5 100644 --- a/board/xilinx/ppc405-generic/u-boot-rom.lds +++ b/board/xilinx/ppc405-generic/u-boot-rom.lds @@ -67,7 +67,6 @@ SECTIONS *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/xilinx/ppc440-generic/u-boot-ram.lds b/board/xilinx/ppc440-generic/u-boot-ram.lds index 3ab9a3167a..94f6fafa17 100644 --- a/board/xilinx/ppc440-generic/u-boot-ram.lds +++ b/board/xilinx/ppc440-generic/u-boot-ram.lds @@ -57,7 +57,6 @@ SECTIONS *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/xilinx/ppc440-generic/u-boot-rom.lds b/board/xilinx/ppc440-generic/u-boot-rom.lds index 74202807d8..57c809e4cb 100644 --- a/board/xilinx/ppc440-generic/u-boot-rom.lds +++ b/board/xilinx/ppc440-generic/u-boot-rom.lds @@ -67,7 +67,6 @@ SECTIONS *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/xm250/xm250.c b/board/xm250/xm250.c index 56b1cd4f46..246bdde750 100644 --- a/board/xm250/xm250.c +++ b/board/xm250/xm250.c @@ -27,6 +27,7 @@ #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -80,3 +81,14 @@ dram_init (void) return (0); } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} +#endif diff --git a/board/xsengine/xsengine.c b/board/xsengine/xsengine.c index 65923e92c5..4464fd4a0a 100644 --- a/board/xsengine/xsengine.c +++ b/board/xsengine/xsengine.c @@ -26,6 +26,7 @@ */ #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -61,3 +62,14 @@ int dram_init (void) return 0; } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} +#endif diff --git a/board/zeus/u-boot.lds b/board/zeus/u-boot.lds index f86570d17e..f3ccd33e7c 100644 --- a/board/zeus/u-boot.lds +++ b/board/zeus/u-boot.lds @@ -60,7 +60,6 @@ SECTIONS cpu/ppc4xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/board/zylonite/zylonite.c b/board/zylonite/zylonite.c index 58291706c0..749a40f529 100644 --- a/board/zylonite/zylonite.c +++ b/board/zylonite/zylonite.c @@ -26,6 +26,7 @@ */ #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -68,3 +69,14 @@ int dram_init (void) return 0; } + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + int rc = 0; +#ifdef CONFIG_SMC91111 + rc = smc91111_initialize(0, CONFIG_SMC91111_BASE); +#endif + return rc; +} +#endif diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 365ceebdf0..8f83598561 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -561,7 +561,6 @@ int do_bootm_subcommand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) /*******************************************************************/ /* bootm - boot application image from image in memory */ /*******************************************************************/ -static int relocated = 0; int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { @@ -569,6 +568,8 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) ulong load_end = 0; int ret; boot_os_fn *boot_fn; +#ifndef CONFIG_RELOC_FIXUP_WORKS + static int relocated = 0; /* relocate boot function table */ if (!relocated) { @@ -578,6 +579,7 @@ int do_bootm (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) boot_os[i] += gd->reloc_off; relocated = 1; } +#endif /* determine if we have a sub command */ if (argc > 1) { diff --git a/common/cmd_date.c b/common/cmd_date.c index b69e935085..9f50f8956e 100644 --- a/common/cmd_date.c +++ b/common/cmd_date.c @@ -35,7 +35,11 @@ const char *weekdays[] = { "Sun", "Mon", "Tues", "Wednes", "Thurs", "Fri", "Satur", }; +#ifdef CONFIG_RELOC_FIXUP_WORKS +#define RELOC(a) a +#else #define RELOC(a) ((typeof(a))((unsigned long)(a) + gd->reloc_off)) +#endif int mk_date (char *, struct rtc_time *); diff --git a/common/cmd_reginfo.c b/common/cmd_reginfo.c index d0ebd0fd60..89fd9ec4e9 100644 --- a/common/cmd_reginfo.c +++ b/common/cmd_reginfo.c @@ -25,8 +25,8 @@ #include #if defined(CONFIG_8xx) #include -#elif defined (CONFIG_405GP) || defined(CONFIG_405EP) -#include +#elif defined (CONFIG_4xx) +extern void ppc4xx_reginfo(void); #elif defined (CONFIG_5xx) #include #elif defined (CONFIG_MPC5200) @@ -90,158 +90,8 @@ int do_reginfo (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) * May be some CPM info here? */ -#elif defined (CONFIG_405GP) - printf ("\n405GP registers; MSR=%08x\n",mfmsr()); - printf ("\nUniversal Interrupt Controller Regs\n" - "UIC0SR UIC0ER UIC0CR UIC0PR UIC0TR UIC0MSR UIC0VR UIC0VCR" - "\n" - "%08x %08x %08x %08x %08x %08x %08x %08x\n", - mfdcr(UIC0SR), - mfdcr(UIC0ER), - mfdcr(UIC0CR), - mfdcr(UIC0PR), - mfdcr(UIC0TR), - mfdcr(UIC0MSR), - mfdcr(UIC0VR), - mfdcr(UIC0VCR)); - - puts ("\nMemory (SDRAM) Configuration\n" - "besra besrsa besrb besrsb bear mcopt1 rtr pmit\n"); - - mtdcr(SDRAM0_CFGADDR,SDRAM0_BESR0); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,SDRAM0_BESRS0); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,SDRAM0_BESR1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,SDRAM0_BESRS1); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,SDRAM0_BEAR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,SDRAM0_CFG); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,SDRAM0_RTR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,SDRAM0_PMIT); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - - puts ("\n" - "mb0cf mb1cf mb2cf mb3cf sdtr1 ecccf eccerr\n"); - mtdcr(SDRAM0_CFGADDR,SDRAM0_B0CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,SDRAM0_B1CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,SDRAM0_B2CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,SDRAM0_B3CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,SDRAM0_TR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,SDRAM0_ECCCFG); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,SDRAM0_ECCESR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - - printf ("\n\n" - "DMA Channels\n" - "DMASR DMASGC DMAADR\n" - "%08x %08x %08x\n" - "dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n" - "%08x %08x %08x %08x %08x\n" - "dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n" - "%08x %08x %08x %08x %08x\n", - mfdcr(DMASR), mfdcr(DMASGC),mfdcr(DMAADR), - mfdcr(DMACR0), mfdcr(DMACT0),mfdcr(DMADA0), mfdcr(DMASA0), mfdcr(DMASB0), - mfdcr(DMACR1), mfdcr(DMACT1),mfdcr(DMADA1), mfdcr(DMASA1), mfdcr(DMASB1)); - - printf ( - "dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n" - "dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n", - mfdcr(DMACR2), mfdcr(DMACT2),mfdcr(DMADA2), mfdcr(DMASA2), mfdcr(DMASB2), - mfdcr(DMACR3), mfdcr(DMACT3),mfdcr(DMADA3), mfdcr(DMASA3), mfdcr(DMASB3) ); - - puts ("\n" - "External Bus\n" - "PBEAR PBESR0 PBESR1 EBC0_CFG\n"); - mtdcr(EBC0_CFGADDR,PBEAR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PBESR0); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PBESR1); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,EBC0_CFG); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - - puts ("\n" - "PB0CR PB0AP PB1CR PB1AP PB2CR PB2AP PB3CR PB3AP\n"); - mtdcr(EBC0_CFGADDR,PB0CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PB0AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PB1CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PB1AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PB2CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PB2AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PB3CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PB3AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - - puts ("\n" - "PB4CR PB4AP PB5CR bp5ap PB6CR PB6AP PB7CR PB7AP\n"); - mtdcr(EBC0_CFGADDR,PB4CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PB4AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PB5CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PB5AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PB6CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PB6AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PB7CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PB7AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - - puts ("\n\n"); - -#elif defined(CONFIG_405EP) - printf ("\n405EP registers; MSR=%08x\n",mfmsr()); - printf ("\nUniversal Interrupt Controller Regs\n" - "UIC0SR UIC0ER UIC0CR UIC0PR UIC0TR UIC0MSR UIC0VR UIC0VCR" - "\n" - "%08x %08x %08x %08x %08x %08x %08x %08x\n", - mfdcr(UIC0SR), - mfdcr(UIC0ER), - mfdcr(UIC0CR), - mfdcr(UIC0PR), - mfdcr(UIC0TR), - mfdcr(UIC0MSR), - mfdcr(UIC0VR), - mfdcr(UIC0VCR)); - - puts ("\nMemory (SDRAM) Configuration\n" - "mcopt1 rtr pmit mb0cf mb1cf sdtr1\n"); - - mtdcr(SDRAM0_CFGADDR,SDRAM0_CFG); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,SDRAM0_RTR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,SDRAM0_PMIT); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,SDRAM0_B0CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,SDRAM0_B1CR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - mtdcr(SDRAM0_CFGADDR,SDRAM0_TR); printf ("%08x ", mfdcr(SDRAM0_CFGDATA)); - - printf ("\n\n" - "DMA Channels\n" - "DMASR DMASGC DMAADR\n" "%08x %08x %08x\n" - "dmacr_0 dmact_0 dmada_0 dmasa_0 dmasb_0\n" "%08x %08x %08x %08x %08x\n" - "dmacr_1 dmact_1 dmada_1 dmasa_1 dmasb_1\n" "%08x %08x %08x %08x %08x\n", - mfdcr(DMASR), mfdcr(DMASGC),mfdcr(DMAADR), - mfdcr(DMACR0), mfdcr(DMACT0),mfdcr(DMADA0), mfdcr(DMASA0), mfdcr(DMASB0), - mfdcr(DMACR1), mfdcr(DMACT1),mfdcr(DMADA1), mfdcr(DMASA1), mfdcr(DMASB1)); - - printf ( - "dmacr_2 dmact_2 dmada_2 dmasa_2 dmasb_2\n" "%08x %08x %08x %08x %08x\n" - "dmacr_3 dmact_3 dmada_3 dmasa_3 dmasb_3\n" "%08x %08x %08x %08x %08x\n", - mfdcr(DMACR2), mfdcr(DMACT2),mfdcr(DMADA2), mfdcr(DMASA2), mfdcr(DMASB2), - mfdcr(DMACR3), mfdcr(DMACT3),mfdcr(DMADA3), mfdcr(DMASA3), mfdcr(DMASB3) ); - - puts ("\n" - "External Bus\n" - "PBEAR PBESR0 PBESR1 EBC0_CFG\n"); - mtdcr(EBC0_CFGADDR,PBEAR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PBESR0); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PBESR1); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,EBC0_CFG); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - - puts ("\n" - "PB0CR PB0AP PB1CR PB1AP PB2CR PB2AP PB3CR PB3AP\n"); - mtdcr(EBC0_CFGADDR,PB0CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PB0AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PB1CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PB1AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PB2CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PB2AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PB3CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PB3AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - - puts ("\n" - "PB4CR PB4AP\n"); - mtdcr(EBC0_CFGADDR,PB4CR); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - mtdcr(EBC0_CFGADDR,PB4AP); printf ("%08x ", mfdcr(EBC0_CFGDATA)); - - puts ("\n\n"); +#elif defined (CONFIG_4xx) + ppc4xx_reginfo(); #elif defined(CONFIG_5xx) volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; diff --git a/common/dlmalloc.c b/common/dlmalloc.c index 241db8cd3e..ca088a17d1 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -1494,6 +1494,7 @@ static mbinptr av_[NAV * 2 + 2] = { IAV(120), IAV(121), IAV(122), IAV(123), IAV(124), IAV(125), IAV(126), IAV(127) }; +#ifndef CONFIG_RELOC_FIXUP_WORKS void malloc_bin_reloc (void) { unsigned long *p = (unsigned long *)(&av_[2]); @@ -1502,6 +1503,7 @@ void malloc_bin_reloc (void) *p++ += gd->reloc_off; } } +#endif ulong mem_malloc_start = 0; ulong mem_malloc_end = 0; diff --git a/common/env_common.c b/common/env_common.c index be64d1307b..439a4a905b 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -224,8 +224,10 @@ void set_default_env(void) void env_relocate (void) { +#ifndef CONFIG_RELOC_FIXUP_WORKS DEBUGF ("%s[%d] offset = 0x%lx\n", __FUNCTION__,__LINE__, gd->reloc_off); +#endif #ifdef CONFIG_AMIGAONEG3SE enable_nvram(); @@ -236,7 +238,9 @@ void env_relocate (void) * The environment buffer is embedded with the text segment, * just relocate the environment pointer */ +#ifndef CONFIG_RELOC_FIXUP_WORKS env_ptr = (env_t *)((ulong)env_ptr + gd->reloc_off); +#endif DEBUGF ("%s[%d] embedded ENV at %p\n", __FUNCTION__,__LINE__,env_ptr); #else /* diff --git a/common/hush.c b/common/hush.c index 528dd254a5..06c5ff8df4 100644 --- a/common/hush.c +++ b/common/hush.c @@ -3270,6 +3270,7 @@ int parse_file_outer(void) } #ifdef __U_BOOT__ +#ifndef CONFIG_RELOC_FIXUP_WORKS static void u_boot_hush_reloc(void) { unsigned long addr; @@ -3280,6 +3281,7 @@ static void u_boot_hush_reloc(void) r->literal = (char *)addr; } } +#endif int u_boot_hush_start(void) { @@ -3290,7 +3292,9 @@ int u_boot_hush_start(void) top_vars->next = 0; top_vars->flg_export = 0; top_vars->flg_read_only = 1; +#ifndef CONFIG_RELOC_FIXUP_WORKS u_boot_hush_reloc(); +#endif } return 0; } diff --git a/common/image.c b/common/image.c index d0f169d660..6eaf41eb13 100644 --- a/common/image.c +++ b/common/image.c @@ -513,7 +513,7 @@ char *get_table_entry_name (table_entry_t *table, char *msg, int id) { for (; table->id >= 0; ++table) { if (table->id == id) -#ifdef USE_HOSTCC +#if defined(USE_HOSTCC) || defined(CONFIG_RELOC_FIXUP_WORKS) return table->lname; #else return table->lname + gd->reloc_off; @@ -578,7 +578,11 @@ int get_table_entry_id (table_entry_t *table, fprintf (stderr, "\n"); #else for (t = table; t->id >= 0; ++t) { +#ifdef CONFIG_RELOC_FIXUP_WORKS + if (t->sname && strcmp(t->sname, name) == 0) +#else if (t->sname && strcmp(t->sname + gd->reloc_off, name) == 0) +#endif return (t->id); } debug ("Invalid %s Type: %s\n", table_name, name); diff --git a/common/serial.c b/common/serial.c index e5ce9fdff2..5f9ffd7e45 100644 --- a/common/serial.c +++ b/common/serial.c @@ -93,12 +93,14 @@ struct serial_device *default_serial_console(void) __attribute__((weak, alias("_ int serial_register (struct serial_device *dev) { +#ifndef CONFIG_RELOC_FIXUP_WORKS dev->init += gd->reloc_off; dev->setbrg += gd->reloc_off; dev->getc += gd->reloc_off; dev->tstc += gd->reloc_off; dev->putc += gd->reloc_off; dev->puts += gd->reloc_off; +#endif dev->next = serial_devices; serial_devices = dev; diff --git a/common/stdio.c b/common/stdio.c index 697df5a495..870ddfd5ef 100644 --- a/common/stdio.c +++ b/common/stdio.c @@ -201,7 +201,8 @@ int stdio_deregister(char *devname) int stdio_init (void) { -#ifndef CONFIG_ARM /* already relocated for current ARM implementation */ +#if !defined(CONFIG_RELOC_FIXUP_WORKS) + /* already relocated for current ARM implementation */ ulong relocation_offset = gd->reloc_off; int i; @@ -210,7 +211,7 @@ int stdio_init (void) stdio_names[i] = (char *) (((ulong) stdio_names[i]) + relocation_offset); } -#endif +#endif /* !CONFIG_RELOC_FIXUP_WORKS */ /* Initialize the list */ INIT_LIST_HEAD(&(devs.list)); diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S index 792cd30856..23381a35cd 100644 --- a/cpu/74xx_7xx/start.S +++ b/cpu/74xx_7xx/start.S @@ -716,15 +716,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/arm926ejs/start.S b/cpu/arm926ejs/start.S index 8043322583..4421b6a990 100644 --- a/cpu/arm926ejs/start.S +++ b/cpu/arm926ejs/start.S @@ -172,6 +172,7 @@ stack_setup: sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ + bic sp, r0, #7 /* 8-byte align stack for ABI compliance */ clear_bss: ldr r0, _bss_start /* find start of bss segment */ diff --git a/cpu/arm_cortexa8/omap3/mem.c b/cpu/arm_cortexa8/omap3/mem.c index 079c848701..8b8cd6d617 100644 --- a/cpu/arm_cortexa8/omap3/mem.c +++ b/cpu/arm_cortexa8/omap3/mem.c @@ -44,7 +44,7 @@ volatile unsigned int boot_flash_env_addr; struct gpmc *gpmc_cfg; #if defined(CONFIG_CMD_NAND) -static u32 gpmc_m_nand[GPMC_MAX_REG] = { +static const u32 gpmc_m_nand[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, M_NAND_GPMC_CONFIG2, M_NAND_GPMC_CONFIG3, @@ -62,7 +62,7 @@ static u32 gpmc_m_nand[GPMC_MAX_REG] = { #endif #if defined(CONFIG_CMD_ONENAND) -static u32 gpmc_onenand[GPMC_MAX_REG] = { +static const u32 gpmc_onenand[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG1, ONENAND_GPMC_CONFIG2, ONENAND_GPMC_CONFIG3, @@ -92,7 +92,7 @@ void make_cs1_contiguous(void) u32 size, a_add_low, a_add_high; size = get_sdr_cs_size(CS0); - size /= SZ_32M; /* find size to offset CS1 */ + size >>= 25; /* divide by 32 MiB to find size to offset CS1 */ a_add_high = (size & 3) << 8; /* set up low field */ a_add_low = (size & 0x3C) >> 2; /* set up high field */ writel((a_add_high | a_add_low), &sdrc_base->cs_cfg); @@ -192,7 +192,7 @@ void do_sdrc_init(u32 cs, u32 early) writel(0, &sdrc_base->cs[cs].mcfg); } -void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base, +void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, u32 size) { writel(0, &cs->config7); @@ -218,12 +218,16 @@ void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base, void gpmc_init(void) { /* putting a blanket check on GPMC based on ZeBu for now */ - u32 *gpmc_config = NULL; gpmc_cfg = (struct gpmc *)GPMC_BASE; +#if defined(CONFIG_CMD_NAND) || defined(CONFIG_CMD_ONENAND) + const u32 *gpmc_config = NULL; u32 base = 0; u32 size = 0; +#if defined(CONFIG_ENV_IS_IN_NAND) || defined(CONFIG_ENV_IS_IN_ONENAND) u32 f_off = CONFIG_SYS_MONITOR_LEN; u32 f_sec = 0; +#endif +#endif u32 config = 0; /* global settings */ @@ -249,7 +253,7 @@ void gpmc_init(void) enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); #if defined(CONFIG_ENV_IS_IN_NAND) f_off = SMNAND_ENV_OFFSET; - f_sec = SZ_128K; + f_sec = (128 << 10); /* 128 KiB */ /* env setup */ boot_flash_base = base; boot_flash_off = f_off; @@ -265,7 +269,7 @@ void gpmc_init(void) enable_gpmc_cs_config(gpmc_config, &gpmc_cfg->cs[0], base, size); #if defined(CONFIG_ENV_IS_IN_ONENAND) f_off = ONENAND_ENV_OFFSET; - f_sec = SZ_128K; + f_sec = (128 << 10); /* 128 KiB */ /* env setup */ boot_flash_base = base; boot_flash_off = f_off; diff --git a/cpu/arm_cortexa8/omap3/sys_info.c b/cpu/arm_cortexa8/omap3/sys_info.c index 765aaf2b37..31b20033cc 100644 --- a/cpu/arm_cortexa8/omap3/sys_info.c +++ b/cpu/arm_cortexa8/omap3/sys_info.c @@ -124,7 +124,7 @@ u32 get_sdr_cs_size(u32 cs) /* get ram size field */ size = readl(&sdrc_base->cs[cs].mcfg) >> 8; size &= 0x3FF; /* remove unwanted bits */ - size *= SZ_2M; /* find size in MB */ + size <<= 21; /* multiply by 2 MiB to find size in MB */ return size; } diff --git a/cpu/mpc512x/fixed_sdram.c b/cpu/mpc512x/fixed_sdram.c index 673d61ee10..442b5fc918 100644 --- a/cpu/mpc512x/fixed_sdram.c +++ b/cpu/mpc512x/fixed_sdram.c @@ -26,13 +26,13 @@ #include /* - * MDDRC Config Runtime Settings in order of the 4 MDDRC cfg registers + * MDDRC Config Runtime Settings */ -u32 default_mddrc_config[4] = { - CONFIG_SYS_MDDRC_TIME_CFG0, /* time_config0 */ - CONFIG_SYS_MDDRC_TIME_CFG1, /* time_config1 */ - CONFIG_SYS_MDDRC_TIME_CFG2, /* time_config2 */ - CONFIG_SYS_MDDRC_SYS_CFG, /* sys_config */ +ddr512x_config_t default_mddrc_config = { + .ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG, + .ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0, + .ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1, + .ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2, }; u32 default_init_seq[] = { @@ -74,7 +74,8 @@ u32 default_init_seq[] = { * The board doesn't use memory modules that have serial presence * detect or similar mechanism for discovery of the DRAM settings */ -long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz) +long int fixed_sdram(ddr512x_config_t *mddrc_config, + u32 *dram_init_seq, int seq_sz) { volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; @@ -83,7 +84,7 @@ long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz) /* take default settings and init sequence if necessary */ if (mddrc_config == NULL) - mddrc_config = default_mddrc_config; + mddrc_config = &default_mddrc_config; if (dram_init_seq == NULL) { dram_init_seq = default_init_seq; seq_sz = sizeof(default_init_seq)/sizeof(u32); @@ -130,18 +131,22 @@ long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz) * put MDDRC in CMD mode and * set the max time between refreshes to 0 during init process */ - out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3] | MDDRC_SYS_CFG_CMD_MASK); - out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0] & MDDRC_REFRESH_ZERO_MASK); - out_be32(&im->mddrc.ddr_time_config1, mddrc_config[1]); - out_be32(&im->mddrc.ddr_time_config2, mddrc_config[2]); + out_be32(&im->mddrc.ddr_sys_config, + mddrc_config->ddr_sys_config | MDDRC_SYS_CFG_CMD_MASK); + out_be32(&im->mddrc.ddr_time_config0, + mddrc_config->ddr_time_config0 & MDDRC_REFRESH_ZERO_MASK); + out_be32(&im->mddrc.ddr_time_config1, + mddrc_config->ddr_time_config1); + out_be32(&im->mddrc.ddr_time_config2, + mddrc_config->ddr_time_config2); /* Initialize DDR with either default or supplied init sequence */ for (i = 0; i < seq_sz; i++) out_be32(&im->mddrc.ddr_command, dram_init_seq[i]); /* Start MDDRC */ - out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0]); - out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3]); + out_be32(&im->mddrc.ddr_time_config0, mddrc_config->ddr_time_config0); + out_be32(&im->mddrc.ddr_sys_config, mddrc_config->ddr_sys_config); return msize; } diff --git a/cpu/mpc512x/start.S b/cpu/mpc512x/start.S index 2e3f645afb..4edc8e94d9 100644 --- a/cpu/mpc512x/start.S +++ b/cpu/mpc512x/start.S @@ -611,15 +611,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc512x/u-boot.lds b/cpu/mpc512x/u-boot.lds index dae32697e3..2e260eb2af 100644 --- a/cpu/mpc512x/u-boot.lds +++ b/cpu/mpc512x/u-boot.lds @@ -51,7 +51,6 @@ SECTIONS { cpu/mpc512x/start.o (.text) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.eh_frame) diff --git a/cpu/mpc5xx/start.S b/cpu/mpc5xx/start.S index 106935cb63..85ea7a8827 100644 --- a/cpu/mpc5xx/start.S +++ b/cpu/mpc5xx/start.S @@ -458,15 +458,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc5xx/u-boot.lds b/cpu/mpc5xx/u-boot.lds index cb17ca5d74..deeb06ae26 100644 --- a/cpu/mpc5xx/u-boot.lds +++ b/cpu/mpc5xx/u-boot.lds @@ -58,7 +58,6 @@ SECTIONS cpu/mpc5xx/start.o (.text) *(.text) - *(.fixup) *(.got1) } _etext = .; diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S index 6b1162aa5e..eb42939b7b 100644 --- a/cpu/mpc5xxx/start.S +++ b/cpu/mpc5xxx/start.S @@ -684,15 +684,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc5xxx/u-boot-customlayout.lds b/cpu/mpc5xxx/u-boot-customlayout.lds index 9563690321..c340086619 100644 --- a/cpu/mpc5xxx/u-boot-customlayout.lds +++ b/cpu/mpc5xxx/u-boot-customlayout.lds @@ -65,7 +65,6 @@ SECTIONS common/env_embedded.o (.ppcenv) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.eh_frame) diff --git a/cpu/mpc5xxx/u-boot.lds b/cpu/mpc5xxx/u-boot.lds index a6d4ff3888..7fe1e95129 100644 --- a/cpu/mpc5xxx/u-boot.lds +++ b/cpu/mpc5xxx/u-boot.lds @@ -54,7 +54,6 @@ SECTIONS { cpu/mpc5xxx/start.o (.text) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.eh_frame) diff --git a/cpu/mpc8220/start.S b/cpu/mpc8220/start.S index 3abc619269..af9472d6b3 100644 --- a/cpu/mpc8220/start.S +++ b/cpu/mpc8220/start.S @@ -649,15 +649,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc8220/u-boot.lds b/cpu/mpc8220/u-boot.lds index 436423c3bb..4400e60c8f 100644 --- a/cpu/mpc8220/u-boot.lds +++ b/cpu/mpc8220/u-boot.lds @@ -54,7 +54,6 @@ SECTIONS { cpu/mpc8220/start.o (.text) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.eh_frame) diff --git a/cpu/mpc824x/start.S b/cpu/mpc824x/start.S index 39325cda5b..750457b02a 100644 --- a/cpu/mpc824x/start.S +++ b/cpu/mpc824x/start.S @@ -589,15 +589,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc824x/u-boot.lds b/cpu/mpc824x/u-boot.lds index 46f708738e..0eac48f2cd 100644 --- a/cpu/mpc824x/u-boot.lds +++ b/cpu/mpc824x/u-boot.lds @@ -54,7 +54,6 @@ SECTIONS { cpu/mpc824x/start.o (.text) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.eh_frame) diff --git a/cpu/mpc8260/start.S b/cpu/mpc8260/start.S index 379f2fb175..edb95e6a62 100644 --- a/cpu/mpc8260/start.S +++ b/cpu/mpc8260/start.S @@ -909,15 +909,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc8260/u-boot.lds b/cpu/mpc8260/u-boot.lds index b3a103dbcb..c777cf9da9 100644 --- a/cpu/mpc8260/u-boot.lds +++ b/cpu/mpc8260/u-boot.lds @@ -54,7 +54,6 @@ SECTIONS { cpu/mpc8260/start.o (.text) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.eh_frame) diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 26e31061f4..ee4b8624aa 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -957,16 +957,18 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b #ifndef CONFIG_NAND_SPL /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc83xx/u-boot.lds b/cpu/mpc83xx/u-boot.lds index 7d57ee4160..c84d4b0222 100644 --- a/cpu/mpc83xx/u-boot.lds +++ b/cpu/mpc83xx/u-boot.lds @@ -52,7 +52,6 @@ SECTIONS { cpu/mpc83xx/start.o (.text) *(.text) - *(.fixup) *(.got1) . = ALIGN(16); *(.eh_frame) diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S index c9e91a90da..6a865283d4 100644 --- a/cpu/mpc85xx/start.S +++ b/cpu/mpc85xx/start.S @@ -977,15 +977,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc85xx/u-boot.lds b/cpu/mpc85xx/u-boot.lds index ec4787157c..183dce9514 100644 --- a/cpu/mpc85xx/u-boot.lds +++ b/cpu/mpc85xx/u-boot.lds @@ -62,7 +62,6 @@ SECTIONS .text : { *(.text) - *(.fixup) *(.got1) } :text _etext = .; @@ -132,6 +131,17 @@ SECTIONS . = RESET_VECTOR_ADDRESS + 0x4; + /* + * Make sure that the bss segment isn't linked at 0x0, otherwise its + * address won't be updated during relocation fixups. Note that + * this is a temporary fix. Code to dynamically the fixup the bss + * location will be added in the future. When the bss relocation + * fixup code is present this workaround should be removed. + */ +#if (RESET_VECTOR_ADDRESS == 0xfffffffc) + . |= 0x10; +#endif + __bss_start = .; .bss (NOLOAD) : { diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index 63cc8dbcda..e65f1c0649 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -733,15 +733,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/mpc8xx/start.S b/cpu/mpc8xx/start.S index 8864c37cf6..e84326ebdc 100644 --- a/cpu/mpc8xx/start.S +++ b/cpu/mpc8xx/start.S @@ -589,15 +589,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 2ab23365a5..3975306400 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -9,7 +9,7 @@ * Copyright (c) 2008 Nuovation System Designs, LLC * Grant Erickson - * (C) Copyright 2007-2008 + * (C) Copyright 2007-2009 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * COPYRIGHT AMCC CORPORATION 2004 @@ -86,8 +86,133 @@ /* disable caching on SDRAM */ #define MY_TLB_WORD2_I_ENABLE TLB_WORD2_I_ENABLE #endif /* CONFIG_4xx_DCACHE */ + +void dcbz_area(u32 start_address, u32 num_bytes); #endif /* CONFIG_440 */ +#define MAXRANKS 4 +#define MAXBXCF 4 + +#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d)) + +#if !defined(CONFIG_NAND_SPL) +/*-----------------------------------------------------------------------------+ + * sdram_memsize + *-----------------------------------------------------------------------------*/ +phys_size_t sdram_memsize(void) +{ + phys_size_t mem_size; + unsigned long mcopt2; + unsigned long mcstat; + unsigned long mb0cf; + unsigned long sdsz; + unsigned long i; + + mem_size = 0; + + mfsdram(SDRAM_MCOPT2, mcopt2); + mfsdram(SDRAM_MCSTAT, mcstat); + + /* DDR controller must be enabled and not in self-refresh. */ + /* Otherwise memsize is zero. */ + if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE) + && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT) + && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK)) + == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) { + for (i = 0; i < MAXBXCF; i++) { + mfsdram(SDRAM_MB0CF + (i << 2), mb0cf); + /* Banks enabled */ + if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) { +#if defined(CONFIG_440) + sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK; +#else + sdsz = mb0cf & SDRAM_RXBAS_SDSZ_MASK; +#endif + switch(sdsz) { + case SDRAM_RXBAS_SDSZ_8: + mem_size+=8; + break; + case SDRAM_RXBAS_SDSZ_16: + mem_size+=16; + break; + case SDRAM_RXBAS_SDSZ_32: + mem_size+=32; + break; + case SDRAM_RXBAS_SDSZ_64: + mem_size+=64; + break; + case SDRAM_RXBAS_SDSZ_128: + mem_size+=128; + break; + case SDRAM_RXBAS_SDSZ_256: + mem_size+=256; + break; + case SDRAM_RXBAS_SDSZ_512: + mem_size+=512; + break; + case SDRAM_RXBAS_SDSZ_1024: + mem_size+=1024; + break; + case SDRAM_RXBAS_SDSZ_2048: + mem_size+=2048; + break; + case SDRAM_RXBAS_SDSZ_4096: + mem_size+=4096; + break; + default: + printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n" + , sdsz); + mem_size=0; + break; + } + } + } + } + + return mem_size << 20; +} + +/*-----------------------------------------------------------------------------+ + * is_ecc_enabled + *-----------------------------------------------------------------------------*/ +static unsigned long is_ecc_enabled(void) +{ + unsigned long val; + + mfsdram(SDRAM_MCOPT1, val); + + return SDRAM_MCOPT1_MCHK_CHK_DECODE(val); +} + +/*-----------------------------------------------------------------------------+ + * board_add_ram_info + *-----------------------------------------------------------------------------*/ +void board_add_ram_info(int use_default) +{ + PPC4xx_SYS_INFO board_cfg; + u32 val; + + if (is_ecc_enabled()) + puts(" (ECC"); + else + puts(" (ECC not"); + + get_sys_info(&board_cfg); + +#if defined(CONFIG_405EX) + val = board_cfg.freqPLB; +#else + mfsdr(SDR0_DDR0, val); + val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1); +#endif + printf(" enabled, %d MHz", (val * 2) / 1000000); + + mfsdram(SDRAM_MMODE, val); + val = (val & SDRAM_MMODE_DCL_MASK) >> 4; + printf(", CL%d)", val); +} +#endif /* !CONFIG_NAND_SPL */ + #if defined(CONFIG_SPD_EEPROM) /*-----------------------------------------------------------------------------+ @@ -105,14 +230,10 @@ #define SDRAM_NONE 0 #define MAXDIMMS 2 -#define MAXRANKS 4 -#define MAXBXCF 4 #define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */ #define ONE_BILLION 1000000000 -#define MULDIV64(m1, m2, d) (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d)) - #define CMD_NOP (7 << 19) #define CMD_PRECHARGE (2 << 19) #define CMD_REFRESH (1 << 19) @@ -213,7 +334,6 @@ typedef enum ddr_cas_id { /*-----------------------------------------------------------------------------+ * Prototypes *-----------------------------------------------------------------------------*/ -static phys_size_t sdram_memsize(void); static void get_spd_info(unsigned long *dimm_populated, unsigned char *iic0_dimm_addr, unsigned long num_dimm_banks); @@ -257,15 +377,11 @@ static void program_initplr(unsigned long *dimm_populated, unsigned long num_dimm_banks, ddr_cas_id_t selected_cas, int write_recovery); -static unsigned long is_ecc_enabled(void); #ifdef CONFIG_DDR_ECC static void program_ecc(unsigned long *dimm_populated, unsigned char *iic0_dimm_addr, unsigned long num_dimm_banks, unsigned long tlb_word2_i_value); -static void program_ecc_addr(unsigned long start_address, - unsigned long num_bytes, - unsigned long tlb_word2_i_value); #endif #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) static void program_DQS_calibration(unsigned long *dimm_populated, @@ -278,7 +394,6 @@ static void DQS_calibration_process(void); #endif #endif int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); -void dcbz_area(u32 start_address, u32 num_bytes); static unsigned char spd_read(uchar chip, uint addr) { @@ -291,79 +406,6 @@ static unsigned char spd_read(uchar chip, uint addr) return 0; } -/*-----------------------------------------------------------------------------+ - * sdram_memsize - *-----------------------------------------------------------------------------*/ -static phys_size_t sdram_memsize(void) -{ - phys_size_t mem_size; - unsigned long mcopt2; - unsigned long mcstat; - unsigned long mb0cf; - unsigned long sdsz; - unsigned long i; - - mem_size = 0; - - mfsdram(SDRAM_MCOPT2, mcopt2); - mfsdram(SDRAM_MCSTAT, mcstat); - - /* DDR controller must be enabled and not in self-refresh. */ - /* Otherwise memsize is zero. */ - if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE) - && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT) - && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK)) - == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) { - for (i = 0; i < MAXBXCF; i++) { - mfsdram(SDRAM_MB0CF + (i << 2), mb0cf); - /* Banks enabled */ - if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) { - sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK; - - switch(sdsz) { - case SDRAM_RXBAS_SDSZ_8: - mem_size+=8; - break; - case SDRAM_RXBAS_SDSZ_16: - mem_size+=16; - break; - case SDRAM_RXBAS_SDSZ_32: - mem_size+=32; - break; - case SDRAM_RXBAS_SDSZ_64: - mem_size+=64; - break; - case SDRAM_RXBAS_SDSZ_128: - mem_size+=128; - break; - case SDRAM_RXBAS_SDSZ_256: - mem_size+=256; - break; - case SDRAM_RXBAS_SDSZ_512: - mem_size+=512; - break; - case SDRAM_RXBAS_SDSZ_1024: - mem_size+=1024; - break; - case SDRAM_RXBAS_SDSZ_2048: - mem_size+=2048; - break; - case SDRAM_RXBAS_SDSZ_4096: - mem_size+=4096; - break; - default: - printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n" - , sdsz); - mem_size=0; - break; - } - } - } - } - - return mem_size << 20; -} - /*-----------------------------------------------------------------------------+ * initdram. Initializes the 440SP Memory Queue and DDR SDRAM controller. * Note: This routine runs from flash with a stack set up in the chip's @@ -643,26 +685,6 @@ static void get_spd_info(unsigned long *dimm_populated, } } -void board_add_ram_info(int use_default) -{ - PPC4xx_SYS_INFO board_cfg; - u32 val; - - if (is_ecc_enabled()) - puts(" (ECC"); - else - puts(" (ECC not"); - - get_sys_info(&board_cfg); - - mfsdr(SDR0_DDR0, val); - val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1); - printf(" enabled, %d MHz", (val * 2) / 1000000); - - mfsdram(SDRAM_MMODE, val); - val = (val & SDRAM_MMODE_DCL_MASK) >> 4; - printf(", CL%d)", val); -} /*------------------------------------------------------------------ * For the memory DIMMs installed, this routine verifies that they @@ -2277,25 +2299,6 @@ static void program_memory_queue(unsigned long *dimm_populated, #endif } -/*-----------------------------------------------------------------------------+ - * is_ecc_enabled. - *-----------------------------------------------------------------------------*/ -static unsigned long is_ecc_enabled(void) -{ - unsigned long dimm_num; - unsigned long ecc; - unsigned long val; - - ecc = 0; - /* loop through all the DIMM slots on the board */ - for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) { - mfsdram(SDRAM_MCOPT1, val); - ecc = max(ecc, SDRAM_MCOPT1_MCHK_CHK_DECODE(val)); - } - - return ecc; -} - #ifdef CONFIG_DDR_ECC /*-----------------------------------------------------------------------------+ * program_ecc. @@ -2305,9 +2308,6 @@ static void program_ecc(unsigned long *dimm_populated, unsigned long num_dimm_banks, unsigned long tlb_word2_i_value) { - unsigned long mcopt1; - unsigned long mcopt2; - unsigned long mcstat; unsigned long dimm_num; unsigned long ecc; @@ -2321,105 +2321,7 @@ static void program_ecc(unsigned long *dimm_populated, if (ecc == 0) return; - if (sdram_memsize() > CONFIG_MAX_MEM_MAPPED) { - printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n"); - return; - } - - mfsdram(SDRAM_MCOPT1, mcopt1); - mfsdram(SDRAM_MCOPT2, mcopt2); - - if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) { - /* DDR controller must be enabled and not in self-refresh. */ - mfsdram(SDRAM_MCSTAT, mcstat); - if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE) - && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT) - && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK)) - == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) { - - program_ecc_addr(0, sdram_memsize(), tlb_word2_i_value); - } - } - - return; -} - -static void wait_ddr_idle(void) -{ - u32 val; - - do { - mfsdram(SDRAM_MCSTAT, val); - } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT); -} - -/*-----------------------------------------------------------------------------+ - * program_ecc_addr. - *-----------------------------------------------------------------------------*/ -static void program_ecc_addr(unsigned long start_address, - unsigned long num_bytes, - unsigned long tlb_word2_i_value) -{ - unsigned long current_address; - unsigned long end_address; - unsigned long address_increment; - unsigned long mcopt1; - char str[] = "ECC generation -"; - char slash[] = "\\|/-\\|/-"; - int loop = 0; - int loopi = 0; - - current_address = start_address; - mfsdram(SDRAM_MCOPT1, mcopt1); - if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) { - mtsdram(SDRAM_MCOPT1, - (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN); - sync(); - eieio(); - wait_ddr_idle(); - - puts(str); - if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) { - /* ECC bit set method for non-cached memory */ - if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32) - address_increment = 4; - else - address_increment = 8; - end_address = current_address + num_bytes; - - while (current_address < end_address) { - *((unsigned long *)current_address) = 0x00000000; - current_address += address_increment; - - if ((loop++ % (2 << 20)) == 0) { - putc('\b'); - putc(slash[loopi++ % 8]); - } - } - - } else { - /* ECC bit set method for cached memory */ - dcbz_area(start_address, num_bytes); - /* Write modified dcache lines back to memory */ - clean_dcache_range(start_address, start_address + num_bytes); - } - - blank_string(strlen(str)); - - sync(); - eieio(); - wait_ddr_idle(); - - /* clear ECC error repoting registers */ - mtsdram(SDRAM_ECCCR, 0xffffffff); - mtdcr(0x4c, 0xffffffff); - - mtsdram(SDRAM_MCOPT1, - (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP); - sync(); - eieio(); - wait_ddr_idle(); - } + do_program_ecc(tlb_word2_i_value); } #endif @@ -3106,7 +3008,7 @@ phys_size_t initdram(int board_type) #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */ #if defined(CONFIG_DDR_ECC) - ecc_init(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20); + do_program_ecc(0); #endif /* defined(CONFIG_DDR_ECC) */ #if defined(CONFIG_440) @@ -3183,18 +3085,6 @@ void mtdcr_any(u32 dcr, u32 val) } } #endif /* defined(CONFIG_440) */ - -void blank_string(int size) -{ - int i; - - for (i = 0; i < size; i++) - putc('\b'); - for (i = 0; i < size; i++) - putc(' '); - for (i = 0; i < size; i++) - putc('\b'); -} #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */ inline void ppc4xx_ibm_ddr2_register_dump(void) diff --git a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c index 91bf582d6e..0283c91d84 100644 --- a/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c +++ b/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c @@ -42,6 +42,8 @@ #include #include +#include "ecc.h" + #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) /* @@ -177,7 +179,7 @@ static u32 *get_membase(int bxcr_num) static inline void ecc_clear_status_reg(void) { - mtsdram(SDRAM_ECCCR, 0xffffffff); + mtsdram(SDRAM_ECCES, 0xffffffff); #if defined(SDRAM_R0BAS) mtdcr(SDRAM_ERRSTATLL, 0xffffffff); #endif @@ -210,7 +212,7 @@ static int ecc_check_status_reg(void) * ecc error, then don't count * this as a passing value */ - mfsdram(SDRAM_ECCCR, ecc_status); + mfsdram(SDRAM_ECCES, ecc_status); if (ecc_status != 0x00000000) { /* clear on error */ ecc_clear_status_reg(); diff --git a/cpu/ppc4xx/4xx_pci.c b/cpu/ppc4xx/4xx_pci.c index e97f32c7b0..fa521f0415 100644 --- a/cpu/ppc4xx/4xx_pci.c +++ b/cpu/ppc4xx/4xx_pci.c @@ -518,7 +518,7 @@ int pci_440_init (struct pci_controller *hose) /* PCI I/O space */ pci_set_region(hose->regions + reg_num++, 0x00000000, - PCIX0_IOBASE, + PCIL0_IOBASE, 0x10000, PCI_REGION_IO); @@ -545,7 +545,7 @@ int pci_440_init (struct pci_controller *hose) hose->region_count = reg_num; - pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA); + pci_setup_indirect(hose, PCIL0_CFGADR, PCIL0_CFGDATA); /* Let board change/modify hose & do initial checks */ if (pci_pre_init (hose) == 0) { @@ -562,18 +562,18 @@ int pci_440_init (struct pci_controller *hose) #if defined(CONFIG_SYS_PCI_TARGET_INIT) pci_target_init(hose); /* Let board setup pci target */ #else - out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); - out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID ); - out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */ + out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); + out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID ); + out16r( PCIL0_CLS, 0x00060000 ); /* Bridge, host bridge */ #endif #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) - out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */ - out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */ -#elif defined(PCIX0_BRDGOPT1) - out32r( PCIX0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */ - out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 1 ); /* Enable host config */ + out32r( PCIL0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */ + out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */ +#elif defined(PCIL0_BRDGOPT1) + out32r( PCIL0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */ + out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 1 ); /* Enable host config */ #endif /*--------------------------------------------------------------------------+ @@ -583,23 +583,23 @@ int pci_440_init (struct pci_controller *hose) #if defined(CONFIG_SYS_PCI_MASTER_INIT) pci_master_init(hose); /* Let board setup pci master */ #else - out32r( PCIX0_POM0SA, 0 ); /* disable */ - out32r( PCIX0_POM1SA, 0 ); /* disable */ - out32r( PCIX0_POM2SA, 0 ); /* disable */ + out32r( PCIL0_POM0SA, 0 ); /* disable */ + out32r( PCIL0_POM1SA, 0 ); /* disable */ + out32r( PCIL0_POM2SA, 0 ); /* disable */ #if defined(CONFIG_440SPE) - out32r( PCIX0_POM0LAL, 0x10000000 ); - out32r( PCIX0_POM0LAH, 0x0000000c ); + out32r( PCIL0_POM0LAL, 0x10000000 ); + out32r( PCIL0_POM0LAH, 0x0000000c ); #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) - out32r( PCIX0_POM0LAL, 0x20000000 ); - out32r( PCIX0_POM0LAH, 0x0000000c ); + out32r( PCIL0_POM0LAL, 0x20000000 ); + out32r( PCIL0_POM0LAH, 0x0000000c ); #else - out32r( PCIX0_POM0LAL, 0x00000000 ); - out32r( PCIX0_POM0LAH, 0x00000003 ); + out32r( PCIL0_POM0LAL, 0x00000000 ); + out32r( PCIL0_POM0LAH, 0x00000003 ); #endif - out32r( PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE ); - out32r( PCIX0_POM0PCIAH, 0x00000000 ); - out32r( PCIX0_POM0SA, 0xf0000001 ); /* 256MB, enabled */ - out32r( PCIX0_STS, in32r( PCIX0_STS ) & ~0x0000fff8 ); + out32r( PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE ); + out32r( PCIL0_POM0PCIAH, 0x00000000 ); + out32r( PCIL0_POM0SA, 0xf0000001 ); /* 256MB, enabled */ + out32r( PCIL0_STS, in32r( PCIL0_STS ) & ~0x0000fff8 ); #endif /*--------------------------------------------------------------------------+ @@ -614,7 +614,7 @@ int pci_440_init (struct pci_controller *hose) #endif #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \ !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) - out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER); + out16r( PCIL0_CMD, in16r( PCIL0_CMD ) | PCI_COMMAND_MASTER); #endif hose->last_busno = pci_hose_scan(hose); } diff --git a/cpu/ppc4xx/4xx_pcie.c b/cpu/ppc4xx/4xx_pcie.c index e880c288e1..19d2c7dd2f 100644 --- a/cpu/ppc4xx/4xx_pcie.c +++ b/cpu/ppc4xx/4xx_pcie.c @@ -30,6 +30,7 @@ #include #include #include +#include #if (defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \ @@ -874,7 +875,7 @@ int ppc4xx_init_pcie_port(int port, int rootport) val = SDR_READ(SDRN_PESDR_LOOP(port)); if (!(val & 0x00001000)) { printf("PCIE%d: link is not up.\n", port); - return -1; + return -ENODEV; } /* diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index 2050b17d81..365f966fed 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -33,6 +33,7 @@ SOBJS += dcr.o SOBJS += kgdb.o COBJS := 40x_spd_sdram.o + COBJS += 44x_spd_ddr.o COBJS += 44x_spd_ddr2.o ifdef CONFIG_PPC4xx_DDR_AUTOCALIBRATION @@ -54,6 +55,9 @@ COBJS += fdt.o COBJS += i2c.o COBJS += interrupts.o COBJS += iop480_uart.o +ifdef CONFIG_CMD_REGINFO +COBJS += reginfo.o +endif COBJS += sdram.o COBJS += speed.o COBJS += tlb.o diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index 2287904669..a9a0ac3454 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -371,16 +371,6 @@ int checkcpu (void) strcpy(addstr, "Security support"); break; - case PVR_405EX2_RA: - puts("EX Rev. A"); - strcpy(addstr, "No Security support"); - break; - - case PVR_405EXR1_RA: - puts("EXr Rev. A"); - strcpy(addstr, "Security support"); - break; - case PVR_405EXR2_RA: puts("EXr Rev. A"); strcpy(addstr, "No Security support"); @@ -406,6 +396,26 @@ int checkcpu (void) strcpy(addstr, "No Security support"); break; + case PVR_405EX1_RD: + puts("EX Rev. D"); + strcpy(addstr, "Security support"); + break; + + case PVR_405EX2_RD: + puts("EX Rev. D"); + strcpy(addstr, "No Security support"); + break; + + case PVR_405EXR1_RD: + puts("EXr Rev. D"); + strcpy(addstr, "Security support"); + break; + + case PVR_405EXR2_RD: + puts("EXr Rev. D"); + strcpy(addstr, "No Security support"); + break; + #if defined(CONFIG_440) case PVR_440GP_RB: puts("GP Rev. B"); diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index bd06b9bc22..a00da408c9 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -58,13 +58,13 @@ void reconfigure_pll(u32 new_cpu_freq) target_perdv0 = 4; target_spcid0 = 4; - mfcpr(CPR0_PRIMBD, reg); + mfcpr(CPR0_PRIMBD0, reg); temp = (reg & PRBDV_MASK) >> 24; prbdv0 = temp ? temp : 8; if (prbdv0 != target_prbdv0) { reg &= ~PRBDV_MASK; reg |= ((target_prbdv0 == 8 ? 0 : target_prbdv0) << 24); - mtcpr(CPR0_PRIMBD, reg); + mtcpr(CPR0_PRIMBD0, reg); reset_needed = 1; } diff --git a/cpu/ppc4xx/denali_spd_ddr2.c b/cpu/ppc4xx/denali_spd_ddr2.c index 4705e21b57..5858cb36a5 100644 --- a/cpu/ppc4xx/denali_spd_ddr2.c +++ b/cpu/ppc4xx/denali_spd_ddr2.c @@ -1159,7 +1159,7 @@ phys_size_t initdram(int board_type) mtsdram(DDR0_31, DDR0_31_XOR_CHECK_BITS_ENCODE(0x0000)); - mtsdram(DDR0_42, DDR0_42_ADDR_PINS_DECODE(14 - rows) | + mtsdram(DDR0_42, DDR0_42_ADDR_PINS_ENCODE(14 - rows) | DDR0_42_CASLAT_LIN_GATE_ENCODE(2 * cas_latency)); program_ddr0_43(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq, diff --git a/cpu/ppc4xx/ecc.c b/cpu/ppc4xx/ecc.c index 3f989e7f59..f105605459 100644 --- a/cpu/ppc4xx/ecc.c +++ b/cpu/ppc4xx/ecc.c @@ -2,7 +2,7 @@ * Copyright (c) 2008 Nuovation System Designs, LLC * Grant Erickson * - * (C) Copyright 2005-2007 + * (C) Copyright 2005-2009 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * (C) Copyright 2002 @@ -42,81 +42,144 @@ #include #include #include +#include +#include #include "ecc.h" #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) || \ defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) #if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) + +#if defined(CONFIG_405EX) /* - * void ecc_init() - * - * Description: - * This routine initializes a range of DRAM ECC memory with known - * data and enables ECC checking. - * - * TO DO: - * - Improve performance by utilizing cache. - * - Further generalize to make usable by other 4xx variants (e.g. - * 440EPx, et al). - * - * Input(s): - * start - A pointer to the start of memory covered by ECC requiring - * initialization. - * size - The size, in bytes, of the memory covered by ECC requiring - * initialization. - * - * Output(s): - * start - A pointer to the start of memory covered by ECC with - * CONFIG_SYS_ECC_PATTERN written to all locations and ECC data - * primed. - * - * Returns: - * N/A + * Currently only 405EX uses 16bit data bus width as an alternative + * option to 32bit data width (SDRAM0_MCOPT1_WDTH) */ -void ecc_init(unsigned long * const start, unsigned long size) +#define SDRAM_DATA_ALT_WIDTH 2 +#else +#define SDRAM_DATA_ALT_WIDTH 8 +#endif + +static void wait_ddr_idle(void) { - const unsigned long pattern = CONFIG_SYS_ECC_PATTERN; - unsigned long * const end = (unsigned long * const)((long)start + size); - unsigned long * current = start; + u32 val; + + do { + mfsdram(SDRAM_MCSTAT, val); + } while ((val & SDRAM_MCSTAT_IDLE_MASK) == SDRAM_MCSTAT_IDLE_NOT); +} + +static void program_ecc_addr(unsigned long start_address, + unsigned long num_bytes, + unsigned long tlb_word2_i_value) +{ + unsigned long current_address; + unsigned long end_address; + unsigned long address_increment; unsigned long mcopt1; - long increment; + char str[] = "ECC generation -"; + char slash[] = "\\|/-\\|/-"; + int loop = 0; + int loopi = 0; - if (start >= end) - return; + current_address = start_address; + mfsdram(SDRAM_MCOPT1, mcopt1); + if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) { + mtsdram(SDRAM_MCOPT1, + (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_GEN); + sync(); + eieio(); + wait_ddr_idle(); + + puts(str); - mfsdram(SDRAM_ECC_CFG, mcopt1); +#ifdef CONFIG_440 + if (tlb_word2_i_value == TLB_WORD2_I_ENABLE) { +#endif + /* ECC bit set method for non-cached memory */ + if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) == SDRAM_MCOPT1_DMWD_32) + address_increment = 4; + else + address_increment = SDRAM_DATA_ALT_WIDTH; + end_address = current_address + num_bytes; - /* Enable ECC generation without checking or reporting */ + while (current_address < end_address) { + *((unsigned long *)current_address) = 0; + current_address += address_increment; - mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) | - SDRAM_ECC_CFG_MCHK_GEN)); + if ((loop++ % (2 << 20)) == 0) { + putc('\b'); + putc(slash[loopi++ % 8]); + } + } +#ifdef CONFIG_440 + } else { + /* ECC bit set method for cached memory */ + dcbz_area(start_address, num_bytes); + /* Write modified dcache lines back to memory */ + clean_dcache_range(start_address, start_address + num_bytes); + } +#endif /* CONFIG_440 */ - increment = sizeof(u32); + blank_string(strlen(str)); -#if defined(CONFIG_440) + sync(); + eieio(); + wait_ddr_idle(); + + /* clear ECC error repoting registers */ + mtsdram(SDRAM_ECCES, 0xffffffff); + mtdcr(0x4c, 0xffffffff); + + mtsdram(SDRAM_MCOPT1, + (mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | SDRAM_MCOPT1_MCHK_CHK_REP); + sync(); + eieio(); + wait_ddr_idle(); + } +} + +#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) +void ecc_init(unsigned long * const start, unsigned long size) +{ /* - * Look at the geometry of SDRAM (data width) to determine whether we - * can skip words when writing. + * Init ECC with cache disabled (on PPC's with IBM DDR + * controller (non DDR2), not tested with cache enabled yet */ + program_ecc_addr((u32)start, size, TLB_WORD2_I_ENABLE); +} +#endif - if ((mcopt1 & SDRAM_ECC_CFG_DMWD_MASK) != SDRAM_ECC_CFG_DMWD_32) - increment = sizeof(u64); -#endif /* defined(CONFIG_440) */ +#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) +void do_program_ecc(unsigned long tlb_word2_i_value) +{ + unsigned long mcopt1; + unsigned long mcopt2; + unsigned long mcstat; + phys_size_t memsize = sdram_memsize(); - while (current < end) { - *current = pattern; - current = (unsigned long *)((long)current + increment); + if (memsize > CONFIG_MAX_MEM_MAPPED) { + printf("\nWarning: Can't enable ECC on systems with more than 2GB of SDRAM!\n"); + return; } - /* Wait until the writes are finished. */ + mfsdram(SDRAM_MCOPT1, mcopt1); + mfsdram(SDRAM_MCOPT2, mcopt2); - sync(); + if ((mcopt1 & SDRAM_MCOPT1_MCHK_MASK) != SDRAM_MCOPT1_MCHK_NON) { + /* DDR controller must be enabled and not in self-refresh. */ + mfsdram(SDRAM_MCSTAT, mcstat); + if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE) + && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT) + && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK)) + == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) { - /* Enable ECC generation with checking and no reporting */ - - mtsdram(SDRAM_ECC_CFG, ((mcopt1 & ~SDRAM_ECC_CFG_MCHK_MASK) | - SDRAM_ECC_CFG_MCHK_CHK)); + program_ecc_addr(0, memsize, tlb_word2_i_value); + } + } } +#endif + #endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */ #endif /* defined(CONFIG_SDRAM_PPC4xx_IBM_DDR)... */ diff --git a/cpu/ppc4xx/ecc.h b/cpu/ppc4xx/ecc.h index 67c3bff878..b2588919eb 100644 --- a/cpu/ppc4xx/ecc.h +++ b/cpu/ppc4xx/ecc.h @@ -2,7 +2,7 @@ * Copyright (c) 2008 Nuovation System Designs, LLC * Grant Erickson * - * Copyright (c) 2007 DENX Software Engineering, GmbH + * Copyright (c) 2007-2009 DENX Software Engineering, GmbH * Stefan Roese * * See file CREDITS for list of people who contributed to this @@ -25,18 +25,13 @@ * * Description: * This file implements ECC initialization for PowerPC processors - * using the SDRAM DDR2 controller, including the 405EX(r), - * 440SP(E), 460EX and 460GT. + * using the IBM SDRAM DDR1 & DDR2 controller. * */ #ifndef _ECC_H_ #define _ECC_H_ -#if !defined(CONFIG_SYS_ECC_PATTERN) -#define CONFIG_SYS_ECC_PATTERN 0x00000000 -#endif /* !defined(CONFIG_SYS_ECC_PATTERN) */ - /* * Since the IBM DDR controller used on 440GP/GX/EP/GR is not register * compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT @@ -46,24 +41,35 @@ /* For 440GP/GX/EP/GR */ #if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR) -#define SDRAM_ECC_CFG SDRAM_CFG0 -#define SDRAM_ECC_CFG_MCHK_MASK SDRAM_CFG0_MCHK_MASK -#define SDRAM_ECC_CFG_MCHK_GEN SDRAM_CFG0_MCHK_GEN -#define SDRAM_ECC_CFG_MCHK_CHK SDRAM_CFG0_MCHK_CHK -#define SDRAM_ECC_CFG_DMWD_MASK SDRAM_CFG0_DMWD_MASK -#define SDRAM_ECC_CFG_DMWD_32 SDRAM_CFG0_DMWD_32 -#endif +#define SDRAM_MCOPT1 SDRAM_CFG0 +#define SDRAM_MCOPT1_MCHK_MASK SDRAM_CFG0_MCHK_MASK +#define SDRAM_MCOPT1_MCHK_NON SDRAM_CFG0_MCHK_NON +#define SDRAM_MCOPT1_MCHK_GEN SDRAM_CFG0_MCHK_GEN +#define SDRAM_MCOPT1_MCHK_CHK SDRAM_CFG0_MCHK_CHK +#define SDRAM_MCOPT1_MCHK_CHK_REP SDRAM_CFG0_MCHK_CHK +#define SDRAM_MCOPT1_DMWD_MASK SDRAM_CFG0_DMWD_MASK +#define SDRAM_MCOPT1_DMWD_32 SDRAM_CFG0_DMWD_32 + +#define SDRAM_MCSTAT SDRAM0_MCSTS +#define SDRAM_MCSTAT_IDLE_MASK SDRAM_MCSTS_CIS +#define SDRAM_MCSTAT_IDLE_NOT SDRAM_MCSTS_IDLE_NOT -/* For 405EX/440SP/SPe/460EX/GT */ -#if defined(CONFIG_SDRAM_PPC4xx_IBM_DDR2) -#define SDRAM_ECC_CFG SDRAM_MCOPT1 -#define SDRAM_ECC_CFG_MCHK_MASK SDRAM_MCOPT1_MCHK_MASK -#define SDRAM_ECC_CFG_MCHK_GEN SDRAM_MCOPT1_MCHK_GEN -#define SDRAM_ECC_CFG_MCHK_CHK SDRAM_MCOPT1_MCHK_CHK -#define SDRAM_ECC_CFG_DMWD_MASK SDRAM_MCOPT1_DMWD_MASK -#define SDRAM_ECC_CFG_DMWD_32 SDRAM_MCOPT1_DMWD_32 +#define SDRAM_ECCES SDRAM0_ECCESR #endif -extern void ecc_init(unsigned long * const start, unsigned long size); +void ecc_init(unsigned long * const start, unsigned long size); +void do_program_ecc(unsigned long tlb_word2_i_value); + +static void inline blank_string(int size) +{ + int i; + + for (i = 0; i < size; i++) + putc('\b'); + for (i = 0; i < size; i++) + putc(' '); + for (i = 0; i < size; i++) + putc('\b'); +} #endif /* _ECC_H_ */ diff --git a/cpu/ppc4xx/miiphy.c b/cpu/ppc4xx/miiphy.c index fa3bfc8d9f..22ed5c25ea 100644 --- a/cpu/ppc4xx/miiphy.c +++ b/cpu/ppc4xx/miiphy.c @@ -195,7 +195,7 @@ unsigned int miiphy_getemac_offset(u8 addr) unsigned long eoffset; /* Need to find out which mdi port we're using */ - zmii = in_be32((void *)ZMII_FER); + zmii = in_be32((void *)ZMII0_FER); if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) /* using port 0 */ @@ -217,12 +217,12 @@ unsigned int miiphy_getemac_offset(u8 addr) /* None of the mdi ports are enabled! */ /* enable port 0 */ zmii |= ZMII_FER_MDI << ZMII_FER_V (0); - out_be32((void *)ZMII_FER, zmii); + out_be32((void *)ZMII0_FER, zmii); eoffset = 0; /* need to soft reset port 0 */ - zmii = in_be32((void *)EMAC_M0); - zmii |= EMAC_M0_SRST; - out_be32((void *)EMAC_M0, zmii); + zmii = in_be32((void *)EMAC0_MR0); + zmii |= EMAC_MR0_SRST; + out_be32((void *)EMAC0_MR0, zmii); } return (eoffset); @@ -243,19 +243,19 @@ unsigned int miiphy_getemac_offset(u8 addr) switch (addr) { #if defined(CONFIG_HAS_ETH1) && defined(CONFIG_GPCS_PHY1_ADDR) case CONFIG_GPCS_PHY1_ADDR: - if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x100))) + if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x100))) eoffset = 0x100; break; #endif #if defined(CONFIG_HAS_ETH2) && defined(CONFIG_GPCS_PHY2_ADDR) case CONFIG_GPCS_PHY2_ADDR: - if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x300))) + if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x300))) eoffset = 0x300; break; #endif #if defined(CONFIG_HAS_ETH3) && defined(CONFIG_GPCS_PHY3_ADDR) case CONFIG_GPCS_PHY3_ADDR: - if (addr == EMAC_M1_IPPA_GET(in_be32((void *)EMAC_M1 + 0x400))) + if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x400))) eoffset = 0x400; break; #endif @@ -278,9 +278,9 @@ static int emac_miiphy_wait(u32 emac_reg) /* wait for completion */ i = 0; do { - sta_reg = in_be32((void *)EMAC_STACR + emac_reg); + sta_reg = in_be32((void *)EMAC0_STACR + emac_reg); if (i++ > 5) { - debug("%s [%d]: Timeout! EMAC_STACR=0x%0x\n", __func__, + debug("%s [%d]: Timeout! EMAC0_STACR=0x%0x\n", __func__, __LINE__, sta_reg); return -1; } @@ -324,7 +324,7 @@ static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value) if (cmd == EMAC_STACR_WRITE) memcpy(&sta_reg, &value, 2); /* put in data */ - out_be32((void *)EMAC_STACR + emac_reg, sta_reg); + out_be32((void *)EMAC0_STACR + emac_reg, sta_reg); debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg); /* wait for completion */ @@ -349,7 +349,7 @@ int emac4xx_miiphy_read (char *devname, unsigned char addr, unsigned char reg, if (emac_miiphy_command(addr, reg, EMAC_STACR_READ, 0) != 0) return -1; - sta_reg = in_be32((void *)EMAC_STACR + emac_reg); + sta_reg = in_be32((void *)EMAC0_STACR + emac_reg); *value = sta_reg >> 16; return 0; diff --git a/cpu/ppc4xx/reginfo.c b/cpu/ppc4xx/reginfo.c new file mode 100644 index 0000000000..a9756672c1 --- /dev/null +++ b/cpu/ppc4xx/reginfo.c @@ -0,0 +1,370 @@ +/* + *(C) Copyright 2005-2009 Netstal Maschinen AG + * Bruno Hars (Bruno.Hars@netstal.com) + * Niklaus Giger (Niklaus.Giger@netstal.com) + * + * This source code is free software; you can redistribute it + * and/or modify it in source code form under the terms of the GNU + * General Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA + */ + +/* + * reginfo.c - register dump of HW-configuratin register for PPC4xx based board + */ + +#include +#include +#include +#include +#include +#include + +enum REGISTER_TYPE { + IDCR1, /* Indirectly Accessed DCR via SDRAM0_CFGADDR/SDRAM0_CFGDATA */ + IDCR2, /* Indirectly Accessed DCR via EBC0_CFGADDR/EBC0_CFGDATA */ + IDCR3, /* Indirectly Accessed DCR via EBM0_CFGADDR/EBM0_CFGDATA */ + IDCR4, /* Indirectly Accessed DCR via PPM0_CFGADDR/PPM0_CFGDATA */ + IDCR5, /* Indirectly Accessed DCR via CPR0_CFGADDR/CPR0_CFGDATA */ + IDCR6, /* Indirectly Accessed DCR via SDR0_CFGADDR/SDR0_CFGDATA */ + MM /* Directly Accessed MMIO Register */ +}; + +struct cpu_register { + char *name; + enum REGISTER_TYPE type; + u32 address; +}; + +/* + * PPC440EPx registers ordered for output + * name type addr size + * ------------------------------------------- + */ + +const struct cpu_register ppc4xx_reg[] = { + {"PB0CR", IDCR2, PB0CR}, + {"PB0AP", IDCR2, PB0AP}, + {"PB1CR", IDCR2, PB1CR}, + {"PB1AP", IDCR2, PB1AP}, + {"PB2CR", IDCR2, PB2CR}, + {"PB2AP", IDCR2, PB2AP}, + {"PB3CR", IDCR2, PB3CR}, + {"PB3AP", IDCR2, PB3AP}, + + {"PB4CR", IDCR2, PB4CR}, + {"PB4AP", IDCR2, PB4AP}, +#if !defined(CONFIG_405EP) + {"PB5CR", IDCR2, PB5CR}, + {"PB5AP", IDCR2, PB5AP}, + {"PB6CR", IDCR2, PB6CR}, + {"PB6AP", IDCR2, PB6AP}, + {"PB7CR", IDCR2, PB7CR}, + {"PB7AP", IDCR2, PB7AP}, +#endif + + {"PBEAR", IDCR2, PBEAR}, +#if defined(CONFIG_405EP) || defined (CONFIG_405GP) + {"PBESR0", IDCR2, PBESR0}, + {"PBESR1", IDCR2, PBESR1}, +#endif + {"EBC0_CFG", IDCR2, EBC0_CFG}, + +#ifdef CONFIG_405GP + {"SDRAM0_BESR0", IDCR1, SDRAM0_BESR0}, + {"SDRAM0_BESRS0", IDCR1, SDRAM0_BESRS0}, + {"SDRAM0_BESR1", IDCR1, SDRAM0_BESR1}, + {"SDRAM0_BESRS1", IDCR1, SDRAM0_BESRS1}, + {"SDRAM0_BEAR", IDCR1, SDRAM0_BEAR}, + {"SDRAM0_CFG", IDCR1, SDRAM0_CFG}, + {"SDRAM0_RTR", IDCR1, SDRAM0_RTR}, + {"SDRAM0_PMIT", IDCR1, SDRAM0_PMIT}, + + {"SDRAM0_B0CR", IDCR1, SDRAM0_B0CR}, + {"SDRAM0_B1CR", IDCR1, SDRAM0_B1CR}, + {"SDRAM0_B2CR", IDCR1, SDRAM0_B2CR}, + {"SDRAM0_B3CR", IDCR1, SDRAM0_B1CR}, + {"SDRAM0_TR", IDCR1, SDRAM0_TR}, + {"SDRAM0_ECCCFG", IDCR1, SDRAM0_B1CR}, + {"SDRAM0_ECCESR", IDCR1, SDRAM0_ECCESR}, + + +#endif + +#ifdef CONFIG_440EPX + {"SDR0_SDSTP0", IDCR6, SDR0_SDSTP0}, + {"SDR0_SDSTP1", IDCR6, SDR0_SDSTP1}, + {"SDR0_SDSTP2", IDCR6, SDR0_SDSTP2}, + {"SDR0_SDSTP3", IDCR6, SDR0_SDSTP3}, + {"SDR0_CUST0", IDCR6, SDR0_CUST0}, + {"SDR0_CUST1", IDCR6, SDR0_CUST1}, + {"SDR0_EBC0", IDCR6, SDR0_EBC0}, + {"SDR0_AMP0", IDCR6, SD0_AMP0}, + {"SDR0_AMP1", IDCR6, SD0_AMP1}, + {"SDR0_CP440", IDCR6, SDR0_CP440}, + {"SDR0_CRYP0", IDCR6, SDR0_CRYP0}, + {"SDR0_DDRCFG", IDCR6, SDR0_DDRCFG}, + {"SDR0_EMAC0RXST", IDCR6, SDR0_EMAC0RXST}, + {"SDR0_EMAC0TXST", IDCR6, SDR0_EMAC0TXST}, + {"SDR0_MFR", IDCR6, SDR0_MFR}, + {"SDR0_PCI0", IDCR6, SDR0_PCI0}, + {"SDR0_PFC0", IDCR6, SDR0_PFC0}, + {"SDR0_PFC1", IDCR6, SDR0_PFC1}, + {"SDR0_PFC2", IDCR6, SDR0_PFC2}, + {"SDR0_PFC4", IDCR6, SDR0_PFC4}, + {"SDR0_UART0", IDCR6, SDR0_UART0}, + {"SDR0_UART1", IDCR6, SDR0_UART1}, + {"SDR0_UART2", IDCR6, SDR0_UART2}, + {"SDR0_UART3", IDCR6, SDR0_UART3}, + {"DDR0_02", IDCR1, DDR0_02}, + {"DDR0_00", IDCR1, DDR0_00}, + {"DDR0_01", IDCR1, DDR0_01}, + {"DDR0_03", IDCR1, DDR0_03}, + {"DDR0_04", IDCR1, DDR0_04}, + {"DDR0_05", IDCR1, DDR0_05}, + {"DDR0_06", IDCR1, DDR0_06}, + {"DDR0_07", IDCR1, DDR0_07}, + {"DDR0_08", IDCR1, DDR0_08}, + {"DDR0_09", IDCR1, DDR0_09}, + {"DDR0_10", IDCR1, DDR0_10}, + {"DDR0_11", IDCR1, DDR0_11}, + {"DDR0_12", IDCR1, DDR0_12}, + {"DDR0_14", IDCR1, DDR0_14}, + {"DDR0_17", IDCR1, DDR0_17}, + {"DDR0_18", IDCR1, DDR0_18}, + {"DDR0_19", IDCR1, DDR0_19}, + {"DDR0_20", IDCR1, DDR0_20}, + {"DDR0_21", IDCR1, DDR0_21}, + {"DDR0_22", IDCR1, DDR0_22}, + {"DDR0_23", IDCR1, DDR0_23}, + {"DDR0_24", IDCR1, DDR0_24}, + {"DDR0_25", IDCR1, DDR0_25}, + {"DDR0_26", IDCR1, DDR0_26}, + {"DDR0_27", IDCR1, DDR0_27}, + {"DDR0_28", IDCR1, DDR0_28}, + {"DDR0_31", IDCR1, DDR0_31}, + {"DDR0_32", IDCR1, DDR0_32}, + {"DDR0_33", IDCR1, DDR0_33}, + {"DDR0_34", IDCR1, DDR0_34}, + {"DDR0_35", IDCR1, DDR0_35}, + {"DDR0_36", IDCR1, DDR0_36}, + {"DDR0_37", IDCR1, DDR0_37}, + {"DDR0_38", IDCR1, DDR0_38}, + {"DDR0_39", IDCR1, DDR0_39}, + {"DDR0_40", IDCR1, DDR0_40}, + {"DDR0_41", IDCR1, DDR0_41}, + {"DDR0_42", IDCR1, DDR0_42}, + {"DDR0_43", IDCR1, DDR0_43}, + {"DDR0_44", IDCR1, DDR0_44}, + {"CPR0_ICFG", IDCR5, CPR0_ICFG}, + {"CPR0_MALD", IDCR5, CPR0_MALD}, + {"CPR0_OPBD00", IDCR5, CPR0_OPBD0}, + {"CPR0_PERD0", IDCR5, CPR0_PERD}, + {"CPR0_PLLC0", IDCR5, CPR0_PLLC}, + {"CPR0_PLLD0", IDCR5, CPR0_PLLD}, + {"CPR0_PRIMAD0", IDCR5, CPR0_PRIMAD0}, + {"CPR0_PRIMBD0", IDCR5, CPR0_PRIMBD0}, + {"CPR0_SPCID", IDCR5, CPR0_SPCID}, + {"SPI0_MODE", MM, SPI0_MODE}, + {"IIC0_CLKDIV", MM, PCIL0_PMM1MA}, + {"PCIL0_PMM0MA", MM, PCIL0_PMM0MA}, + {"PCIL0_PMM1MA", MM, PCIL0_PMM1MA}, + {"PCIL0_PTM1LA", MM, PCIL0_PMM1MA}, + {"PCIL0_PTM1MS", MM, PCIL0_PTM1MS}, + {"PCIL0_PTM2LA", MM, PCIL0_PMM1MA}, + {"PCIL0_PTM2MS", MM, PCIL0_PTM2MS}, + {"ZMII0_FER", MM, ZMII0_FER}, + {"ZMII0_SSR", MM, ZMII0_SSR}, + {"EMAC0_IPGVR", MM, EMAC0_IPGVR}, + {"EMAC0_MR1", MM, EMAC0_MR1}, + {"EMAC0_PTR", MM, EMAC0_PTR}, + {"EMAC0_RWMR", MM, EMAC0_RWMR}, + {"EMAC0_STACR", MM, EMAC0_STACR}, + {"EMAC0_TMR0", MM, EMAC0_TMR0}, + {"EMAC0_TMR1", MM, EMAC0_TMR1}, + {"EMAC0_TRTR", MM, EMAC0_TRTR}, + {"EMAC1_MR1", MM, EMAC1_MR1}, + {"GPIO0_OR", MM, GPIO0_OR}, + {"GPIO1_OR", MM, GPIO1_OR}, + {"GPIO0_TCR", MM, GPIO0_TCR}, + {"GPIO1_TCR", MM, GPIO1_TCR}, + {"GPIO0_ODR", MM, GPIO0_ODR}, + {"GPIO1_ODR", MM, GPIO1_ODR}, + {"GPIO0_OSRL", MM, GPIO0_OSRL}, + {"GPIO0_OSRH", MM, GPIO0_OSRH}, + {"GPIO1_OSRL", MM, GPIO1_OSRL}, + {"GPIO1_OSRH", MM, GPIO1_OSRH}, + {"GPIO0_TSRL", MM, GPIO0_TSRL}, + {"GPIO0_TSRH", MM, GPIO0_TSRH}, + {"GPIO1_TSRL", MM, GPIO1_TSRL}, + {"GPIO1_TSRH", MM, GPIO1_TSRH}, + {"GPIO0_IR", MM, GPIO0_IR}, + {"GPIO1_IR", MM, GPIO1_IR}, + {"GPIO0_ISR1L", MM, GPIO0_ISR1L}, + {"GPIO0_ISR1H", MM, GPIO0_ISR1H}, + {"GPIO1_ISR1L", MM, GPIO1_ISR1L}, + {"GPIO1_ISR1H", MM, GPIO1_ISR1H}, + {"GPIO0_ISR2L", MM, GPIO0_ISR2L}, + {"GPIO0_ISR2H", MM, GPIO0_ISR2H}, + {"GPIO1_ISR2L", MM, GPIO1_ISR2L}, + {"GPIO1_ISR2H", MM, GPIO1_ISR2H}, + {"GPIO0_ISR3L", MM, GPIO0_ISR3L}, + {"GPIO0_ISR3H", MM, GPIO0_ISR3H}, + {"GPIO1_ISR3L", MM, GPIO1_ISR3L}, + {"GPIO1_ISR3H", MM, GPIO1_ISR3H}, + {"SDR0_USB2PHY0CR", IDCR6, SDR0_USB2PHY0CR}, + {"SDR0_USB2H0CR", IDCR6, SDR0_USB2H0CR}, + {"SDR0_USB2D0CR", IDCR6, SDR0_USB2D0CR}, +#endif +}; + +/* + * CPU Register dump of PPC4xx HW configuration registers + * Output: first all DCR-registers, then in order of struct ppc4xx_reg + */ +#define PRINT_DCR(dcr) printf("0x%08x %-16s: 0x%08x\n", dcr,#dcr, mfdcr(dcr)); + +void ppc4xx_reginfo(void) +{ + unsigned int i; + unsigned int n; + u32 value; + enum REGISTER_TYPE type; +#if defined (CONFIG_405EP) + printf("Dump PPC405EP HW configuration registers\n\n"); +#elif CONFIG_405GP + printf ("Dump 405GP HW configuration registers\n\n"); +#elif CONFIG_440EPX + printf("Dump PPC440EPx HW configuration registers\n\n"); +#endif + printf("MSR: 0x%08x\n", mfmsr()); + + printf ("\nUniversal Interrupt Controller Regs\n"); + PRINT_DCR(UIC0SR); + PRINT_DCR(UIC0ER); + PRINT_DCR(UIC0CR); + PRINT_DCR(UIC0PR); + PRINT_DCR(UIC0TR); + PRINT_DCR(UIC0MSR); + PRINT_DCR(UIC0VR); + PRINT_DCR(UIC0VCR); + +#if (UIC_MAX > 1) + PRINT_DCR(UIC2SR); + PRINT_DCR(UIC2ER); + PRINT_DCR(UIC2CR); + PRINT_DCR(UIC2PR); + PRINT_DCR(UIC2TR); + PRINT_DCR(UIC2MSR); + PRINT_DCR(UIC2VR); + PRINT_DCR(UIC2VCR); +#endif + +#if (UIC_MAX > 2) + PRINT_DCR(UIC2SR); + PRINT_DCR(UIC2ER); + PRINT_DCR(UIC2CR); + PRINT_DCR(UIC2PR); + PRINT_DCR(UIC2TR); + PRINT_DCR(UIC2MSR); + PRINT_DCR(UIC2VR); + PRINT_DCR(UIC2VCR); +#endif + +#if (UIC_MAX > 3) + PRINT_DCR(UIC3SR); + PRINT_DCR(UIC3ER); + PRINT_DCR(UIC3CR); + PRINT_DCR(UIC3PR); + PRINT_DCR(UIC3TR); + PRINT_DCR(UIC3MSR); + PRINT_DCR(UIC3VR); + PRINT_DCR(UIC3VCR); +#endif + +#if defined (CONFIG_405EP) || defined (CONFIG_405GP) + printf ("\n\nDMA Channels\n"); + PRINT_DCR(DMASR); + PRINT_DCR(DMASGC); + PRINT_DCR(DMAADR); + + PRINT_DCR(DMACR0); + PRINT_DCR(DMACT0); + PRINT_DCR(DMADA0); + PRINT_DCR(DMASA0); + PRINT_DCR(DMASB0); + + PRINT_DCR(DMACR1); + PRINT_DCR(DMACT1); + PRINT_DCR(DMADA1); + PRINT_DCR(DMASA1); + PRINT_DCR(DMASB1); + + PRINT_DCR(DMACR2); + PRINT_DCR(DMACT2); + PRINT_DCR(DMADA2); + PRINT_DCR(DMASA2); + PRINT_DCR(DMASB2); + + PRINT_DCR(DMACR3); + PRINT_DCR(DMACT3); + PRINT_DCR(DMADA3); + PRINT_DCR(DMASA3); + PRINT_DCR(DMASB3); +#endif + + printf ("\n\nVarious HW-Configuration registers\n"); +#if defined (CONFIG_440EPX) + PRINT_DCR(MAL0_CFG); + PRINT_DCR(CPM0_ER); + PRINT_DCR(CPM1_ER); + PRINT_DCR(PLB4A0_ACR); + PRINT_DCR(PLB4A1_ACR); + PRINT_DCR(PLB3A0_ACR); + PRINT_DCR(OPB2PLB40_BCTRL); + PRINT_DCR(P4P3BO0_CFG); +#endif + n = sizeof(ppc4xx_reg) / sizeof(ppc4xx_reg[0]); + for (i = 0; i < n; i++) { + value = 0; + type = ppc4xx_reg[i].type; + switch (type) { + case IDCR1: /* Indirect via SDRAM0_CFGADDR/DDR0_CFGDATA */ + mtdcr(SDRAM0_CFGADDR, ppc4xx_reg[i].address); + value = mfdcr(SDRAM0_CFGDATA); + break; + case IDCR2: /* Indirect via EBC0_CFGADDR/EBC0_CFGDATA */ + mtdcr(EBC0_CFGADDR, ppc4xx_reg[i].address); + value = mfdcr(EBC0_CFGDATA); + break; + case IDCR5: /* Indirect via CPR0_CFGADDR/CPR0_CFGDATA */ + mtdcr(CPR0_CFGADDR, ppc4xx_reg[i].address); + value = mfdcr(CPR0_CFGDATA); + break; + case IDCR6: /* Indirect via SDR0_CFGADDR/SDR0_CFGDATA */ + mtdcr(SDR0_CFGADDR, ppc4xx_reg[i].address); + value = mfdcr(SDR0_CFGDATA); + break; + case MM: /* Directly Accessed MMIO Register */ + value = in_be32((const volatile unsigned __iomem *) + ppc4xx_reg[i].address); + break; + default: + printf("\nERROR: struct entry %d: unknown register" + "type\n", i); + break; + } + printf("0x%08x %-16s: 0x%08x\n",ppc4xx_reg[i].address, + ppc4xx_reg[i].name, value); + } +} diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index 988ba9742d..906face033 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -334,7 +334,7 @@ void get_sys_info (sys_info_t *sysInfo) sysInfo->pllFbkDiv = temp ? temp : 32; lfdiv = reg & PLLD_LFBDV_MASK; - mfcpr(CPR0_OPBD, reg); + mfcpr(CPR0_OPBD0, reg); temp = (reg & OPBDDV_MASK) >> 24; sysInfo->pllOpbDiv = temp ? temp : 4; @@ -342,7 +342,7 @@ void get_sys_info (sys_info_t *sysInfo) temp = (reg & PERDV_MASK) >> 24; sysInfo->pllExtBusDiv = temp ? temp : 8; - mfcpr(CPR0_PRIMBD, reg); + mfcpr(CPR0_PRIMBD0, reg); temp = (reg & PRBDV_MASK) >> 24; prbdv0 = temp ? temp : 8; @@ -1050,7 +1050,7 @@ void get_sys_info (sys_info_t * sysInfo) /* * Determine OPBDV0 */ - mfcpr(CPR0_OPBD, tmp); + mfcpr(CPR0_OPBD0, tmp); tmp = (tmp >> 24) & 0x03; sysInfo->pllOpbDiv = (tmp == 0) ? 4 : tmp; diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 287a912246..46f65aa779 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -1596,15 +1596,17 @@ in_ram: sub r11,r3,r11 addi r3,r3,-4 1: lwzu r0,4(r3) + cmpwi r0,0 + beq- 2f add r0,r0,r11 stw r0,0(r3) - bdnz 1b +2: bdnz 1b /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ -2: li r0,__fixup_entries@sectoff@l + li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 diff --git a/disk/part.c b/disk/part.c index b92fb45b86..9ced4527f3 100644 --- a/disk/part.c +++ b/disk/part.c @@ -80,7 +80,10 @@ block_dev_desc_t *get_dev(char* ifname, int dev) block_dev_desc_t* (*reloc_get_dev)(int dev); while (drvr->name) { - reloc_get_dev = drvr->get_dev + gd->reloc_off; + reloc_get_dev = drvr->get_dev; +#ifndef CONFIG_RELOC_FIXUP_WORKS + reloc_get_dev += gd->reloc_off; +#endif if (strncmp(ifname, drvr->name, strlen(drvr->name)) == 0) return reloc_get_dev(dev); drvr++; diff --git a/doc/README.bitbangMII b/doc/README.bitbangMII new file mode 100644 index 0000000000..edd085630f --- /dev/null +++ b/doc/README.bitbangMII @@ -0,0 +1,56 @@ +This patch rewrites the miiphybb ( Bit-banged MII bus driver ) in order to +support an arbitrary number of mii buses. This feature is useful when your +board uses different mii buses for different phys and all (or a part) of these +buses are implemented via bit-banging mode. + +The driver requires that the following macros should be defined into the board +configuration file: + +CONFIG_BITBANGMII - Enable the miiphybb driver +CONFIG_BITBANGMII_MULTI - Enable the multi bus support + +If the CONFIG_BITBANGMII_MULTI is not defined, the board's config file needs +to define at least the following macros: + +MII_INIT - Generic code to enable the MII bus (optional) +MDIO_DECLARE - Declaration needed to access to the MDIO pin (optional) +MDIO_ACTIVE - Activate the MDIO pin as out pin +MDIO_TRISTATE - Activate the MDIO pin as input/tristate pin +MDIO_READ - Read the MDIO pin +MDIO(v) - Write v on the MDIO pin +MDC_DECLARE - Declaration needed to access to the MDC pin (optional) +MDC(v) - Write v on the MDC pin + +The previous macros make the driver compatible with the previous version +(that didn't support the multi-bus). + +When the CONFIG_BITBANGMII_MULTI is also defined, the board code needs to fill +the bb_miiphy_buses[] array with a record for each required bus and declare +the bb_miiphy_buses_num variable with the number of mii buses. +The record (struct bb_miiphy_bus) has the following fields/callbacks (see +miiphy.h for details): + +char name[] - The symbolic name that must be equal to the MII bus + registered name +int (*init)() - Initialization function called at startup time (just + before the Ethernet initialization) +int (*mdio_active)() - Activate the MDIO pin as output +int (*mdio_tristate)() - Activate the MDIO pin as input/tristate pin +int (*set_mdio)() - Write the MDIO pin +int (*get_mdio)() - Read the MDIO pin +int (*set_mdc)() - Write the MDC pin +int (*delay)() - Delay function +void *priv - Private data used by board specific code + +The board code will look like: + +struct bb_miiphy_bus bb_miiphy_buses[] = { + { .name = "miibus#1", .init = b1_init, .mdio_active = b1_mdio_active, ... }, + { .name = "miibus#2", .init = b2_init, .mdio_active = b2_mdio_active, ... }, + ... +}; +int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / + sizeof(bb_miiphy_buses[0]); + +2009 Industrie Dial Face S.p.A. + Luigi 'Comio' Mantellini diff --git a/doc/README.drivers.eth b/doc/README.drivers.eth new file mode 100644 index 0000000000..e06d3ad44b --- /dev/null +++ b/doc/README.drivers.eth @@ -0,0 +1,182 @@ +----------------------- + Ethernet Driver Guide +----------------------- + +The networking stack in Das U-Boot is designed for multiple network devices +to be easily added and controlled at runtime. This guide is meant for people +who wish to review the net driver stack with an eye towards implementing your +own ethernet device driver. Here we will describe a new pseudo 'APE' driver. + +------------------ + Driver Functions +------------------ + +All functions you will be implementing in this document have the return value +meaning of 0 for success and non-zero for failure. + + ---------- + Register + ---------- + +When U-Boot initializes, it will call the common function eth_initialize(). +This will in turn call the board-specific board_eth_init() (or if that fails, +the cpu-specific cpu_eth_init()). These board-specific functions can do random +system handling, but ultimately they will call the driver-specific register +function which in turn takes care of initializing that particular instance. + +Keep in mind that you should code the driver to avoid storing state in global +data as someone might want to hook up two of the same devices to one board. +Any such information that is specific to an interface should be stored in a +private, driver-defined data structure and pointed to by eth->priv (see below). + +So the call graph at this stage would look something like: +board_init() + eth_initialize() + board_eth_init() / cpu_eth_init() + driver_register() + initialize eth_device + eth_register() + +At this point in time, the only thing you need to worry about is the driver's +register function. The pseudo code would look something like: +int ape_register(bd_t *bis, int iobase) +{ + struct ape_priv *priv; + struct eth_device *dev; + + priv = malloc(sizeof(*priv)); + if (priv == NULL) + return 1; + + dev = malloc(sizeof(*dev)); + if (dev == NULL) { + free(priv); + return 1; + } + + /* setup whatever private state you need */ + + memset(dev, 0, sizeof(*dev)); + sprintf(dev->name, "APE"); + + /* if your device has dedicated hardware storage for the + * MAC, read it and initialize dev->enetaddr with it + */ + ape_mac_read(dev->enetaddr); + + dev->iobase = iobase; + dev->priv = priv; + dev->init = ape_init; + dev->halt = ape_halt; + dev->send = ape_send; + dev->recv = ape_recv; + + eth_register(dev); + +#ifdef CONFIG_CMD_MII) + miiphy_register(dev->name, ape_mii_read, ape_mii_write); +#endif + + return 1; +} + +The exact arguments needed to initialize your device are up to you. If you +need to pass more/less arguments, that's fine. You should also add the +prototype for your new register function to include/netdev.h. + +The return value for this function should be as follows: +< 0 - failure (hardware failure, not probe failure) +>=0 - number of interfaces detected + +You might notice that many drivers seem to use xxx_initialize() rather than +xxx_register(). This is the old naming convention and should be avoided as it +causes confusion with the driver-specific init function. + +Other than locating the MAC address in dedicated hardware storage, you should +not touch the hardware in anyway. That step is handled in the driver-specific +init function. Remember that we are only registering the device here, we are +not checking its state or doing random probing. + + ----------- + Callbacks + ----------- + +Now that we've registered with the ethernet layer, we can start getting some +real work done. You will need four functions: + int ape_init(struct eth_device *dev, bd_t *bis); + int ape_send(struct eth_device *dev, volatile void *packet, int length); + int ape_recv(struct eth_device *dev); + int ape_halt(struct eth_device *dev); + +The init function checks the hardware (probing/identifying) and gets it ready +for send/recv operations. You often do things here such as resetting the MAC +and/or PHY, and waiting for the link to autonegotiate. You should also take +the opportunity to program the device's MAC address with the dev->enetaddr +member. This allows the rest of U-Boot to dynamically change the MAC address +and have the new settings be respected. + +The send function does what you think -- transmit the specified packet whose +size is specified by length (in bytes). You should not return until the +transmission is complete, and you should leave the state such that the send +function can be called multiple times in a row. + +The recv function should process packets as long as the hardware has them +readily available before returning. i.e. you should drain the hardware fifo. +The common code sets up packet buffers for you already (NetRxPackets), so there +is no need to allocate your own. For each packet you receive, you should call +the NetReceive() function on it with the packet length. So the pseudo code +here would look something like: +int ape_recv(struct eth_device *dev) +{ + int length, i = 0; + ... + while (packets_are_available()) { + ... + length = ape_get_packet(&NetRxPackets[i]); + ... + NetReceive(&NetRxPackets[i], length); + ... + if (++i >= PKTBUFSRX) + i = 0; + ... + } + ... + return 0; +} + +The halt function should turn off / disable the hardware and place it back in +its reset state. + +So the call graph at this stage would look something like: +some net operation (ping / tftp / whatever...) + eth_init() + dev->init() + eth_send() + dev->send() + eth_rx() + dev->recv() + eth_halt() + dev->halt() + +----------------------------- + CONFIG_MII / CONFIG_CMD_MII +----------------------------- + +If your device supports banging arbitrary values on the MII bus (pretty much +every device does), you should add support for the mii command. Doing so is +fairly trivial and makes debugging mii issues a lot easier at runtime. + +After you have called eth_register() in your driver's register function, add +a call to miiphy_register() like so: +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + miiphy_register(dev->name, mii_read, mii_write); +#endif + +And then define the mii_read and mii_write functions if you haven't already. +Their syntax is straightforward: + int mii_read(char *devname, uchar addr, uchar reg, ushort *val); + int mii_write(char *devname, uchar addr, uchar reg, ushort val); + +The read function should read the register 'reg' from the phy at address 'addr' +and store the result in the pointer 'val'. The implementation for the write +function should logically follow. diff --git a/drivers/bios_emulator/x86emu/ops.c b/drivers/bios_emulator/x86emu/ops.c index f884e9b03c..c836a20b15 100644 --- a/drivers/bios_emulator/x86emu/ops.c +++ b/drivers/bios_emulator/x86emu/ops.c @@ -70,9 +70,6 @@ * calls is especially important; otherwise mistakes in coding an * "add" would represent a nightmare in maintenance. * -* Jason ported this file to u-boot. place all the function pointer in -* the got2 sector. Removed some opcode. -* ****************************************************************************/ #include @@ -88,7 +85,7 @@ static char *x86emu_GenOpName[8] = { #endif /* used by several opcodes */ -static u8 (*genop_byte_operation[])(u8 d, u8 s) __attribute__ ((section(GOT2_TYPE))) = +static u8 (*genop_byte_operation[])(u8 d, u8 s) = { add_byte, /* 00 */ or_byte, /* 01 */ @@ -100,7 +97,7 @@ static u8 (*genop_byte_operation[])(u8 d, u8 s) __attribute__ ((section(GOT2_TYP cmp_byte, /* 07 */ }; -static u16 (*genop_word_operation[])(u16 d, u16 s) __attribute__ ((section(GOT2_TYPE))) = +static u16 (*genop_word_operation[])(u16 d, u16 s) = { add_word, /*00 */ or_word, /*01 */ @@ -112,7 +109,7 @@ static u16 (*genop_word_operation[])(u16 d, u16 s) __attribute__ ((section(GOT2_ cmp_word, /*07 */ }; -static u32 (*genop_long_operation[])(u32 d, u32 s) __attribute__ ((section(GOT2_TYPE))) = +static u32 (*genop_long_operation[])(u32 d, u32 s) = { add_long, /*00 */ or_long, /*01 */ @@ -125,7 +122,7 @@ static u32 (*genop_long_operation[])(u32 d, u32 s) __attribute__ ((section(GOT2_ }; /* used by opcodes 80, c0, d0, and d2. */ -static u8(*opcD0_byte_operation[])(u8 d, u8 s) __attribute__ ((section(GOT2_TYPE))) = +static u8(*opcD0_byte_operation[])(u8 d, u8 s) = { rol_byte, ror_byte, @@ -138,7 +135,7 @@ static u8(*opcD0_byte_operation[])(u8 d, u8 s) __attribute__ ((section(GOT2_TYPE }; /* used by opcodes c1, d1, and d3. */ -static u16(*opcD1_word_operation[])(u16 s, u8 d) __attribute__ ((section(GOT2_TYPE))) = +static u16(*opcD1_word_operation[])(u16 s, u8 d) = { rol_word, ror_word, @@ -151,7 +148,7 @@ static u16(*opcD1_word_operation[])(u16 s, u8 d) __attribute__ ((section(GOT2_TY }; /* used by opcodes c1, d1, and d3. */ -static u32 (*opcD1_long_operation[])(u32 s, u8 d) __attribute__ ((section(GOT2_TYPE))) = +static u32 (*opcD1_long_operation[])(u32 s, u8 d) = { rol_long, ror_long, @@ -5144,7 +5141,7 @@ void x86emuOp_opcFF_word_RM(u8 X86EMU_UNUSED(op1)) /*************************************************************************** * Single byte operation code table: **************************************************************************/ -void (*x86emu_optab[256])(u8) __attribute__ ((section(GOT2_TYPE))) = +void (*x86emu_optab[256])(u8) = { /* 0x00 */ x86emuOp_genop_byte_RM_R, /* 0x01 */ x86emuOp_genop_word_RM_R, diff --git a/drivers/bios_emulator/x86emu/ops2.c b/drivers/bios_emulator/x86emu/ops2.c index ee7258e758..937bf4ce07 100644 --- a/drivers/bios_emulator/x86emu/ops2.c +++ b/drivers/bios_emulator/x86emu/ops2.c @@ -39,9 +39,6 @@ * and emulation of all the x86 extended two-byte processor * instructions. * -* Jason port this file to u-boot. Put the function pointer into -* got2 sector. -* ****************************************************************************/ #include @@ -1495,7 +1492,7 @@ void x86emuOp2_movsx_word_R_RM(u8 X86EMU_UNUSED(op2)) /*************************************************************************** * Double byte operation code table: **************************************************************************/ -void (*x86emu_optab2[256])(u8) __attribute__((section(GOT2_TYPE))) = +void (*x86emu_optab2[256])(u8) = { /* 0x00 */ x86emuOp2_illegal_op, /* Group F (ring 0 PM) */ /* 0x01 */ x86emuOp2_illegal_op, /* Group G (ring 0 PM) */ diff --git a/drivers/fpga/ACEX1K.c b/drivers/fpga/ACEX1K.c index 3f7967782b..06b4247d87 100644 --- a/drivers/fpga/ACEX1K.c +++ b/drivers/fpga/ACEX1K.c @@ -51,7 +51,6 @@ static int ACEX1K_ps_load( Altera_desc *desc, void *buf, size_t bsize ); static int ACEX1K_ps_dump( Altera_desc *desc, void *buf, size_t bsize ); /* static int ACEX1K_ps_info( Altera_desc *desc ); */ -static int ACEX1K_ps_reloc( Altera_desc *desc, ulong reloc_offset ); /* ------------------------------------------------------------------------- */ /* ACEX1K Generic Implementation */ @@ -101,31 +100,6 @@ int ACEX1K_info( Altera_desc *desc ) } -int ACEX1K_reloc (Altera_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume a failure */ - - if (desc->family != Altera_ACEX1K) { - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - return FPGA_FAIL; - } else - switch (desc->iface) { - case passive_serial: - ret_val = ACEX1K_ps_reloc (desc, reloc_offset); - break; - - /* Add new interface types here */ - - default: - printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); - } - - return ret_val; -} - - /* ------------------------------------------------------------------------- */ /* ACEX1K Passive Serial Generic Implementation */ @@ -290,73 +264,3 @@ static int ACEX1K_ps_dump (Altera_desc * desc, void *buf, size_t bsize) __FUNCTION__); return FPGA_FAIL; } - -static int ACEX1K_ps_reloc (Altera_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume the worst */ - Altera_ACEX1K_Passive_Serial_fns *fn_r, *fn = - (Altera_ACEX1K_Passive_Serial_fns *) (desc->iface_fns); - - if (fn) { - ulong addr; - - /* Get the relocated table address */ - addr = (ulong) fn + reloc_offset; - fn_r = (Altera_ACEX1K_Passive_Serial_fns *) addr; - - if (!fn_r->relocated) { - - if (memcmp (fn_r, fn, - sizeof (Altera_ACEX1K_Passive_Serial_fns)) - == 0) { - /* good copy of the table, fix the descriptor pointer */ - desc->iface_fns = fn_r; - } else { - PRINTF ("%s: Invalid function table at 0x%p\n", - __FUNCTION__, fn_r); - return FPGA_FAIL; - } - - PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, - desc); - - addr = (ulong) (fn->pre) + reloc_offset; - fn_r->pre = (Altera_pre_fn) addr; - - addr = (ulong) (fn->config) + reloc_offset; - fn_r->config = (Altera_config_fn) addr; - - addr = (ulong) (fn->status) + reloc_offset; - fn_r->status = (Altera_status_fn) addr; - - addr = (ulong) (fn->done) + reloc_offset; - fn_r->done = (Altera_done_fn) addr; - - addr = (ulong) (fn->clk) + reloc_offset; - fn_r->clk = (Altera_clk_fn) addr; - - addr = (ulong) (fn->data) + reloc_offset; - fn_r->data = (Altera_data_fn) addr; - - addr = (ulong) (fn->abort) + reloc_offset; - fn_r->abort = (Altera_abort_fn) addr; - - addr = (ulong) (fn->post) + reloc_offset; - fn_r->post = (Altera_post_fn) addr; - - fn_r->relocated = TRUE; - - } else { - /* this table has already been moved */ - /* XXX - should check to see if the descriptor is correct */ - desc->iface_fns = fn_r; - } - - ret_val = FPGA_SUCCESS; - } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); - } - - return ret_val; - -} diff --git a/drivers/fpga/altera.c b/drivers/fpga/altera.c index 09dc0b22e1..650f2ec734 100644 --- a/drivers/fpga/altera.c +++ b/drivers/fpga/altera.c @@ -211,45 +211,6 @@ int altera_info( Altera_desc *desc ) return ret_val; } -int altera_reloc( Altera_desc *desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume a failure */ - - if (!altera_validate (desc, (char *)__FUNCTION__)) { - printf ("%s: Invalid device descriptor\n", __FUNCTION__); - } else { - switch (desc->family) { - case Altera_ACEX1K: -#if defined(CONFIG_FPGA_ACEX1K) - ret_val = ACEX1K_reloc (desc, reloc_offset); -#else - printf ("%s: No support for ACEX devices.\n", - __FUNCTION__); -#endif - break; -#if defined(CONFIG_FPGA_STRATIX_II) - case Altera_StratixII: - ret_val = StratixII_reloc (desc, reloc_offset); - break; -#endif - case Altera_CYC2: -#if defined(CONFIG_FPGA_CYCLON2) - ret_val = CYC2_reloc (desc, reloc_offset); -#else - printf ("%s: No support for CYCLON II devices.\n", - __FUNCTION__); -#endif - break; - /* Add new family types here */ - default: - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - } - } - - return ret_val; -} - /* ------------------------------------------------------------------------- */ static int altera_validate (Altera_desc * desc, const char *fn) diff --git a/drivers/fpga/cyclon2.c b/drivers/fpga/cyclon2.c index 3ed64b2793..4622b4e455 100644 --- a/drivers/fpga/cyclon2.c +++ b/drivers/fpga/cyclon2.c @@ -50,7 +50,6 @@ static int CYC2_ps_load( Altera_desc *desc, void *buf, size_t bsize ); static int CYC2_ps_dump( Altera_desc *desc, void *buf, size_t bsize ); /* static int CYC2_ps_info( Altera_desc *desc ); */ -static int CYC2_ps_reloc( Altera_desc *desc, ulong reloc_offset ); /* ------------------------------------------------------------------------- */ /* CYCLON2 Generic Implementation */ @@ -99,30 +98,6 @@ int CYC2_info( Altera_desc *desc ) return FPGA_SUCCESS; } -int CYC2_reloc (Altera_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume a failure */ - - if (desc->family != Altera_CYC2) { - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - return FPGA_FAIL; - } else - switch (desc->iface) { - case passive_serial: - ret_val = CYC2_ps_reloc (desc, reloc_offset); - break; - - /* Add new interface types here */ - - default: - printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); - } - - return ret_val; -} - /* ------------------------------------------------------------------------- */ /* CYCLON2 Passive Serial Generic Implementation */ static int CYC2_ps_load (Altera_desc * desc, void *buf, size_t bsize) @@ -233,69 +208,3 @@ static int CYC2_ps_dump (Altera_desc * desc, void *buf, size_t bsize) __FUNCTION__); return FPGA_FAIL; } - -static int CYC2_ps_reloc (Altera_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume the worst */ - Altera_CYC2_Passive_Serial_fns *fn_r, *fn = - (Altera_CYC2_Passive_Serial_fns *) (desc->iface_fns); - - if (fn) { - ulong addr; - - /* Get the relocated table address */ - addr = (ulong) fn + reloc_offset; - fn_r = (Altera_CYC2_Passive_Serial_fns *) addr; - - if (!fn_r->relocated) { - - if (memcmp (fn_r, fn, - sizeof (Altera_CYC2_Passive_Serial_fns)) - == 0) { - /* good copy of the table, fix the descriptor pointer */ - desc->iface_fns = fn_r; - } else { - PRINTF ("%s: Invalid function table at 0x%p\n", - __FUNCTION__, fn_r); - return FPGA_FAIL; - } - - PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, - desc); - - addr = (ulong) (fn->pre) + reloc_offset; - fn_r->pre = (Altera_pre_fn) addr; - - addr = (ulong) (fn->config) + reloc_offset; - fn_r->config = (Altera_config_fn) addr; - - addr = (ulong) (fn->status) + reloc_offset; - fn_r->status = (Altera_status_fn) addr; - - addr = (ulong) (fn->done) + reloc_offset; - fn_r->done = (Altera_done_fn) addr; - - addr = (ulong) (fn->write) + reloc_offset; - fn_r->write = (Altera_write_fn) addr; - - addr = (ulong) (fn->abort) + reloc_offset; - fn_r->abort = (Altera_abort_fn) addr; - - addr = (ulong) (fn->post) + reloc_offset; - fn_r->post = (Altera_post_fn) addr; - - fn_r->relocated = TRUE; - - } else { - /* this table has already been moved */ - /* XXX - should check to see if the descriptor is correct */ - desc->iface_fns = fn_r; - } - - ret_val = FPGA_SUCCESS; - } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); - } - - return ret_val; -} diff --git a/drivers/fpga/fpga.c b/drivers/fpga/fpga.c index 67a6c300c7..5659517793 100644 --- a/drivers/fpga/fpga.c +++ b/drivers/fpga/fpga.c @@ -46,7 +46,6 @@ #endif /* Local static data */ -static ulong relocation_offset = 0; static int next_desc = FPGA_INVALID_DEVICE; static fpga_desc desc_table[CONFIG_MAX_FPGA_DEVICES]; @@ -153,46 +152,12 @@ static int fpga_dev_info( int devnum ) } -/* fpga_reloc - * generic multiplexing code - */ -int fpga_reloc( fpga_type devtype, void *desc, ulong reloc_off ) -{ - int ret_val = FPGA_FAIL; - - PRINTF( "%s: Relocating Device of type %d @ 0x%p with offset %lx\n", - __FUNCTION__, devtype, desc, reloc_off ); - - switch ( devtype ) { - case fpga_xilinx: -#if defined(CONFIG_FPGA_XILINX) - ret_val = xilinx_reloc( desc, reloc_off ); -#else - fpga_no_sup( (char *)__FUNCTION__, "Xilinx devices" ); -#endif - break; - case fpga_altera: -#if defined(CONFIG_FPGA_ALTERA) - ret_val = altera_reloc( desc, reloc_off ); -#else - fpga_no_sup( (char *)__FUNCTION__, "Altera devices" ); -#endif - break; - default: - printf( "%s: Invalid or unsupported device type %d\n", - __FUNCTION__, devtype ); - } - - return ret_val; -} - /* ------------------------------------------------------------------------- */ /* fgpa_init is usually called from misc_init_r() and MUST be called * before any of the other fpga functions are used. */ -void fpga_init( ulong reloc_off ) +void fpga_init(void) { - relocation_offset = reloc_off; next_desc = 0; memset( desc_table, 0, sizeof(desc_table)); @@ -208,9 +173,7 @@ int fpga_count( void ) } /* fpga_add - * Attempts to relocate the device/board specific interface code - * to the proper RAM locations and adds the device descriptor to - * the device table. + * Add the device descriptor to the device table. */ int fpga_add( fpga_type devtype, void *desc ) { @@ -221,15 +184,9 @@ int fpga_add( fpga_type devtype, void *desc ) } else if (( devtype > fpga_min_type ) && ( devtype < fpga_undefined )) { if ( desc ) { if ( next_desc < CONFIG_MAX_FPGA_DEVICES ) { - if ( fpga_reloc( devtype, desc, relocation_offset ) - == FPGA_SUCCESS ) { - devnum = next_desc; - desc_table[next_desc].devtype = devtype; - desc_table[next_desc++].devdesc = desc; - } else { - printf( "%s: Unable to relocate device interface table!\n", - __FUNCTION__ ); - } + devnum = next_desc; + desc_table[next_desc].devtype = devtype; + desc_table[next_desc++].devdesc = desc; } else { printf( "%s: Exceeded Max FPGA device count\n", __FUNCTION__ ); } diff --git a/drivers/fpga/spartan2.c b/drivers/fpga/spartan2.c index d745334e92..cd16a9c44c 100644 --- a/drivers/fpga/spartan2.c +++ b/drivers/fpga/spartan2.c @@ -51,12 +51,10 @@ static int Spartan2_sp_load( Xilinx_desc *desc, void *buf, size_t bsize ); static int Spartan2_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize ); /* static int Spartan2_sp_info( Xilinx_desc *desc ); */ -static int Spartan2_sp_reloc( Xilinx_desc *desc, ulong reloc_offset ); static int Spartan2_ss_load( Xilinx_desc *desc, void *buf, size_t bsize ); static int Spartan2_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize ); /* static int Spartan2_ss_info( Xilinx_desc *desc ); */ -static int Spartan2_ss_reloc( Xilinx_desc *desc, ulong reloc_offset ); /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ @@ -112,33 +110,6 @@ int Spartan2_info( Xilinx_desc *desc ) } -int Spartan2_reloc (Xilinx_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume a failure */ - - if (desc->family != Xilinx_Spartan2) { - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - return FPGA_FAIL; - } else - switch (desc->iface) { - case slave_serial: - ret_val = Spartan2_ss_reloc (desc, reloc_offset); - break; - - case slave_parallel: - ret_val = Spartan2_sp_reloc (desc, reloc_offset); - break; - - default: - printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); - } - - return ret_val; -} - - /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ @@ -340,93 +311,6 @@ static int Spartan2_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize) } -static int Spartan2_sp_reloc (Xilinx_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan2_Slave_Parallel_fns *fn_r, *fn = - (Xilinx_Spartan2_Slave_Parallel_fns *) (desc->iface_fns); - - if (fn) { - ulong addr; - - /* Get the relocated table address */ - addr = (ulong) fn + reloc_offset; - fn_r = (Xilinx_Spartan2_Slave_Parallel_fns *) addr; - - if (!fn_r->relocated) { - - if (memcmp (fn_r, fn, - sizeof (Xilinx_Spartan2_Slave_Parallel_fns)) - == 0) { - /* good copy of the table, fix the descriptor pointer */ - desc->iface_fns = fn_r; - } else { - PRINTF ("%s: Invalid function table at 0x%p\n", - __FUNCTION__, fn_r); - return FPGA_FAIL; - } - - PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, - desc); - - addr = (ulong) (fn->pre) + reloc_offset; - fn_r->pre = (Xilinx_pre_fn) addr; - - addr = (ulong) (fn->pgm) + reloc_offset; - fn_r->pgm = (Xilinx_pgm_fn) addr; - - addr = (ulong) (fn->init) + reloc_offset; - fn_r->init = (Xilinx_init_fn) addr; - - addr = (ulong) (fn->done) + reloc_offset; - fn_r->done = (Xilinx_done_fn) addr; - - addr = (ulong) (fn->clk) + reloc_offset; - fn_r->clk = (Xilinx_clk_fn) addr; - - addr = (ulong) (fn->err) + reloc_offset; - fn_r->err = (Xilinx_err_fn) addr; - - addr = (ulong) (fn->cs) + reloc_offset; - fn_r->cs = (Xilinx_cs_fn) addr; - - addr = (ulong) (fn->wr) + reloc_offset; - fn_r->wr = (Xilinx_wr_fn) addr; - - addr = (ulong) (fn->rdata) + reloc_offset; - fn_r->rdata = (Xilinx_rdata_fn) addr; - - addr = (ulong) (fn->wdata) + reloc_offset; - fn_r->wdata = (Xilinx_wdata_fn) addr; - - addr = (ulong) (fn->busy) + reloc_offset; - fn_r->busy = (Xilinx_busy_fn) addr; - - addr = (ulong) (fn->abort) + reloc_offset; - fn_r->abort = (Xilinx_abort_fn) addr; - - if (fn->post) { - addr = (ulong) (fn->post) + reloc_offset; - fn_r->post = (Xilinx_post_fn) addr; - } - - fn_r->relocated = TRUE; - - } else { - /* this table has already been moved */ - /* XXX - should check to see if the descriptor is correct */ - desc->iface_fns = fn_r; - } - - ret_val = FPGA_SUCCESS; - } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); - } - - return ret_val; - -} - /* ------------------------------------------------------------------------- */ static int Spartan2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) @@ -580,74 +464,3 @@ static int Spartan2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize) __FUNCTION__); return FPGA_FAIL; } - -static int Spartan2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan2_Slave_Serial_fns *fn_r, *fn = - (Xilinx_Spartan2_Slave_Serial_fns *) (desc->iface_fns); - - if (fn) { - ulong addr; - - /* Get the relocated table address */ - addr = (ulong) fn + reloc_offset; - fn_r = (Xilinx_Spartan2_Slave_Serial_fns *) addr; - - if (!fn_r->relocated) { - - if (memcmp (fn_r, fn, - sizeof (Xilinx_Spartan2_Slave_Serial_fns)) - == 0) { - /* good copy of the table, fix the descriptor pointer */ - desc->iface_fns = fn_r; - } else { - PRINTF ("%s: Invalid function table at 0x%p\n", - __FUNCTION__, fn_r); - return FPGA_FAIL; - } - - PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, - desc); - - if (fn->pre) { - addr = (ulong) (fn->pre) + reloc_offset; - fn_r->pre = (Xilinx_pre_fn) addr; - } - - addr = (ulong) (fn->pgm) + reloc_offset; - fn_r->pgm = (Xilinx_pgm_fn) addr; - - addr = (ulong) (fn->init) + reloc_offset; - fn_r->init = (Xilinx_init_fn) addr; - - addr = (ulong) (fn->done) + reloc_offset; - fn_r->done = (Xilinx_done_fn) addr; - - addr = (ulong) (fn->clk) + reloc_offset; - fn_r->clk = (Xilinx_clk_fn) addr; - - addr = (ulong) (fn->wr) + reloc_offset; - fn_r->wr = (Xilinx_wr_fn) addr; - - if (fn->post) { - addr = (ulong) (fn->post) + reloc_offset; - fn_r->post = (Xilinx_post_fn) addr; - } - - fn_r->relocated = TRUE; - - } else { - /* this table has already been moved */ - /* XXX - should check to see if the descriptor is correct */ - desc->iface_fns = fn_r; - } - - ret_val = FPGA_SUCCESS; - } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); - } - - return ret_val; - -} diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 8bb244971f..0fe30410a6 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -56,12 +56,10 @@ static int Spartan3_sp_load( Xilinx_desc *desc, void *buf, size_t bsize ); static int Spartan3_sp_dump( Xilinx_desc *desc, void *buf, size_t bsize ); /* static int Spartan3_sp_info( Xilinx_desc *desc ); */ -static int Spartan3_sp_reloc( Xilinx_desc *desc, ulong reloc_offset ); static int Spartan3_ss_load( Xilinx_desc *desc, void *buf, size_t bsize ); static int Spartan3_ss_dump( Xilinx_desc *desc, void *buf, size_t bsize ); /* static int Spartan3_ss_info( Xilinx_desc *desc ); */ -static int Spartan3_ss_reloc( Xilinx_desc *desc, ulong reloc_offset ); /* ------------------------------------------------------------------------- */ /* Spartan-II Generic Implementation */ @@ -117,33 +115,6 @@ int Spartan3_info( Xilinx_desc *desc ) } -int Spartan3_reloc (Xilinx_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume a failure */ - - if (desc->family != Xilinx_Spartan3) { - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - return FPGA_FAIL; - } else - switch (desc->iface) { - case slave_serial: - ret_val = Spartan3_ss_reloc (desc, reloc_offset); - break; - - case slave_parallel: - ret_val = Spartan3_sp_reloc (desc, reloc_offset); - break; - - default: - printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); - } - - return ret_val; -} - - /* ------------------------------------------------------------------------- */ /* Spartan-II Slave Parallel Generic Implementation */ @@ -347,91 +318,6 @@ static int Spartan3_sp_dump (Xilinx_desc * desc, void *buf, size_t bsize) } -static int Spartan3_sp_reloc (Xilinx_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan3_Slave_Parallel_fns *fn_r, *fn = - (Xilinx_Spartan3_Slave_Parallel_fns *) (desc->iface_fns); - - if (fn) { - ulong addr; - - /* Get the relocated table address */ - addr = (ulong) fn + reloc_offset; - fn_r = (Xilinx_Spartan3_Slave_Parallel_fns *) addr; - - if (!fn_r->relocated) { - - if (memcmp (fn_r, fn, - sizeof (Xilinx_Spartan3_Slave_Parallel_fns)) - == 0) { - /* good copy of the table, fix the descriptor pointer */ - desc->iface_fns = fn_r; - } else { - PRINTF ("%s: Invalid function table at 0x%p\n", - __FUNCTION__, fn_r); - return FPGA_FAIL; - } - - PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, - desc); - - addr = (ulong) (fn->pre) + reloc_offset; - fn_r->pre = (Xilinx_pre_fn) addr; - - addr = (ulong) (fn->pgm) + reloc_offset; - fn_r->pgm = (Xilinx_pgm_fn) addr; - - addr = (ulong) (fn->init) + reloc_offset; - fn_r->init = (Xilinx_init_fn) addr; - - addr = (ulong) (fn->done) + reloc_offset; - fn_r->done = (Xilinx_done_fn) addr; - - addr = (ulong) (fn->clk) + reloc_offset; - fn_r->clk = (Xilinx_clk_fn) addr; - - addr = (ulong) (fn->err) + reloc_offset; - fn_r->err = (Xilinx_err_fn) addr; - - addr = (ulong) (fn->cs) + reloc_offset; - fn_r->cs = (Xilinx_cs_fn) addr; - - addr = (ulong) (fn->wr) + reloc_offset; - fn_r->wr = (Xilinx_wr_fn) addr; - - addr = (ulong) (fn->rdata) + reloc_offset; - fn_r->rdata = (Xilinx_rdata_fn) addr; - - addr = (ulong) (fn->wdata) + reloc_offset; - fn_r->wdata = (Xilinx_wdata_fn) addr; - - addr = (ulong) (fn->busy) + reloc_offset; - fn_r->busy = (Xilinx_busy_fn) addr; - - addr = (ulong) (fn->abort) + reloc_offset; - fn_r->abort = (Xilinx_abort_fn) addr; - - addr = (ulong) (fn->post) + reloc_offset; - fn_r->post = (Xilinx_post_fn) addr; - - fn_r->relocated = TRUE; - - } else { - /* this table has already been moved */ - /* XXX - should check to see if the descriptor is correct */ - desc->iface_fns = fn_r; - } - - ret_val = FPGA_SUCCESS; - } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); - } - - return ret_val; - -} - /* ------------------------------------------------------------------------- */ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) @@ -587,74 +473,3 @@ static int Spartan3_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize) __FUNCTION__); return FPGA_FAIL; } - -static int Spartan3_ss_reloc (Xilinx_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume the worst */ - Xilinx_Spartan3_Slave_Serial_fns *fn_r, *fn = - (Xilinx_Spartan3_Slave_Serial_fns *) (desc->iface_fns); - - if (fn) { - ulong addr; - - /* Get the relocated table address */ - addr = (ulong) fn + reloc_offset; - fn_r = (Xilinx_Spartan3_Slave_Serial_fns *) addr; - - if (!fn_r->relocated) { - - if (memcmp (fn_r, fn, - sizeof (Xilinx_Spartan3_Slave_Serial_fns)) - == 0) { - /* good copy of the table, fix the descriptor pointer */ - desc->iface_fns = fn_r; - } else { - PRINTF ("%s: Invalid function table at 0x%p\n", - __FUNCTION__, fn_r); - return FPGA_FAIL; - } - - PRINTF ("%s: Relocating descriptor at 0x%p\n", __FUNCTION__, - desc); - - if (fn->pre) { - addr = (ulong) (fn->pre) + reloc_offset; - fn_r->pre = (Xilinx_pre_fn) addr; - } - - addr = (ulong) (fn->pgm) + reloc_offset; - fn_r->pgm = (Xilinx_pgm_fn) addr; - - addr = (ulong) (fn->init) + reloc_offset; - fn_r->init = (Xilinx_init_fn) addr; - - addr = (ulong) (fn->done) + reloc_offset; - fn_r->done = (Xilinx_done_fn) addr; - - addr = (ulong) (fn->clk) + reloc_offset; - fn_r->clk = (Xilinx_clk_fn) addr; - - addr = (ulong) (fn->wr) + reloc_offset; - fn_r->wr = (Xilinx_wr_fn) addr; - - if (fn->post) { - addr = (ulong) (fn->post) + reloc_offset; - fn_r->post = (Xilinx_post_fn) addr; - } - - fn_r->relocated = TRUE; - - } else { - /* this table has already been moved */ - /* XXX - should check to see if the descriptor is correct */ - desc->iface_fns = fn_r; - } - - ret_val = FPGA_SUCCESS; - } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); - } - - return ret_val; - -} diff --git a/drivers/fpga/stratixII.c b/drivers/fpga/stratixII.c index 7556dbfb3d..8a3a7d872e 100644 --- a/drivers/fpga/stratixII.c +++ b/drivers/fpga/stratixII.c @@ -77,30 +77,6 @@ int StratixII_info (Altera_desc * desc) return FPGA_SUCCESS; } -int StratixII_reloc (Altera_desc * desc, ulong reloc_offset) -{ - int i; - uint32_t dest = (uint32_t) desc & 0xff000000; - - /* we assume a relocated code and non relocated code has different upper 8 bits */ - if (dest != ((uint32_t) desc->iface_fns & 0xff000000)) { - desc->iface_fns = - (void *)((uint32_t) (desc->iface_fns) + reloc_offset); - } - for (i = 0; i < sizeof (altera_board_specific_func) / sizeof (void *); - i++) { - if (dest != - ((uint32_t) (((void **)(desc->iface_fns))[i]) & 0xff000000)) - { - ((void **)(desc->iface_fns))[i] = - (void - *)(((uint32_t) (((void **)(desc->iface_fns))[i])) + - reloc_offset); - } - } - return FPGA_SUCCESS; -} - int StratixII_ps_fpp_dump (Altera_desc * desc, void *buf, size_t bsize) { printf ("Stratix II Fast Passive Parallel dump is not implemented\n"); diff --git a/drivers/fpga/virtex2.c b/drivers/fpga/virtex2.c index 50d0921844..d1b4d15b71 100644 --- a/drivers/fpga/virtex2.c +++ b/drivers/fpga/virtex2.c @@ -103,11 +103,9 @@ static int Virtex2_ssm_load (Xilinx_desc * desc, void *buf, size_t bsize); static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize); -static int Virtex2_ssm_reloc (Xilinx_desc * desc, ulong reloc_offset); static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize); static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize); -static int Virtex2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset); int Virtex2_load (Xilinx_desc * desc, void *buf, size_t bsize) { @@ -158,31 +156,6 @@ int Virtex2_info (Xilinx_desc * desc) return FPGA_SUCCESS; } -int Virtex2_reloc (Xilinx_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; - - if (desc->family != Xilinx_Virtex2) { - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - return FPGA_FAIL; - } else - switch (desc->iface) { - case slave_serial: - ret_val = Virtex2_ss_reloc (desc, reloc_offset); - break; - - case slave_selectmap: - ret_val = Virtex2_ssm_reloc (desc, reloc_offset); - break; - - default: - printf ("%s: Unsupported interface type, %d\n", - __FUNCTION__, desc->iface); - } - return ret_val; -} - /* * Virtex-II Slave SelectMap configuration loader. Configuration via * SelectMap is as follows: @@ -448,81 +421,6 @@ static int Virtex2_ssm_dump (Xilinx_desc * desc, void *buf, size_t bsize) return ret_val; } -/* - * Relocate the addresses in the function table from FLASH (or ROM, - * or whatever) to RAM. - */ -static int Virtex2_ssm_reloc (Xilinx_desc * desc, ulong reloc_offset) -{ - ulong addr; - int ret_val = FPGA_FAIL; - Xilinx_Virtex2_Slave_SelectMap_fns *fn_r, *fn = - (Xilinx_Virtex2_Slave_SelectMap_fns *) (desc->iface_fns); - - if (fn) { - /* - * Get the relocated table address - */ - addr = (ulong) fn + reloc_offset; - fn_r = (Xilinx_Virtex2_Slave_SelectMap_fns *) addr; - - /* - * Check to see if the table has already been relocated. If not, do - * a sanity check to make sure there is a faithful copy of the - * FLASH based function table in RAM, then adjust the table. - */ - if (!fn_r->relocated) { - if (memcmp - (fn_r, fn, sizeof (Xilinx_Virtex2_Slave_SelectMap_fns)) - == 0) { - desc->iface_fns = fn_r; - } else { - PRINTF ("%s:%d: Invalid function table at 0x%p\n", - __FUNCTION__, __LINE__, fn_r); - return FPGA_FAIL; - } - - PRINTF ("%s:%d: Relocating descriptor at 0x%p\n", - __FUNCTION__, __LINE__, desc); - - addr = (ulong) (fn->pre) + reloc_offset; - fn_r->pre = (Xilinx_pre_fn) addr; - addr = (ulong) (fn->pgm) + reloc_offset; - fn_r->pgm = (Xilinx_pgm_fn) addr; - addr = (ulong) (fn->init) + reloc_offset; - fn_r->init = (Xilinx_init_fn) addr; - addr = (ulong) (fn->done) + reloc_offset; - fn_r->done = (Xilinx_done_fn) addr; - addr = (ulong) (fn->err) + reloc_offset; - fn_r->err = (Xilinx_err_fn) addr; - addr = (ulong) (fn->clk) + reloc_offset; - fn_r->clk = (Xilinx_clk_fn) addr; - addr = (ulong) (fn->cs) + reloc_offset; - fn_r->cs = (Xilinx_cs_fn) addr; - addr = (ulong) (fn->wr) + reloc_offset; - fn_r->wr = (Xilinx_wr_fn) addr; - addr = (ulong) (fn->rdata) + reloc_offset; - fn_r->rdata = (Xilinx_rdata_fn) addr; - addr = (ulong) (fn->wdata) + reloc_offset; - fn_r->wdata = (Xilinx_wdata_fn) addr; - addr = (ulong) (fn->busy) + reloc_offset; - fn_r->busy = (Xilinx_busy_fn) addr; - addr = (ulong) (fn->abort) + reloc_offset; - fn_r->abort = (Xilinx_abort_fn) addr; - addr = (ulong) (fn->post) + reloc_offset; - fn_r->post = (Xilinx_post_fn) addr; - fn_r->relocated = TRUE; - } else { - printf ("%s:%d: Function table @0x%p has already been relocated\n", __FUNCTION__, __LINE__, fn_r); - desc->iface_fns = fn_r; - } - ret_val = FPGA_SUCCESS; - } else { - printf ("%s: NULL Interface function table!\n", __FUNCTION__); - } - return ret_val; -} - static int Virtex2_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) { printf ("%s: Slave Serial Loading is unsupported\n", __FUNCTION__); @@ -535,20 +433,4 @@ static int Virtex2_ss_dump (Xilinx_desc * desc, void *buf, size_t bsize) return FPGA_FAIL; } -static int Virtex2_ss_reloc (Xilinx_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; - Xilinx_Virtex2_Slave_Serial_fns *fn = - (Xilinx_Virtex2_Slave_Serial_fns *) (desc->iface_fns); - - if (fn) { - printf ("%s:%d: Slave Serial Loading is unsupported\n", - __FUNCTION__, __LINE__); - } else { - printf ("%s:%d: NULL Interface function table!\n", - __FUNCTION__, __LINE__); - } - return ret_val; -} - /* vim: set ts=4 tw=78: */ diff --git a/drivers/fpga/xilinx.c b/drivers/fpga/xilinx.c index 7b5e8c5bbd..08dfdecdee 100644 --- a/drivers/fpga/xilinx.c +++ b/drivers/fpga/xilinx.c @@ -238,48 +238,6 @@ int xilinx_info (Xilinx_desc * desc) return ret_val; } -int xilinx_reloc (Xilinx_desc * desc, ulong reloc_offset) -{ - int ret_val = FPGA_FAIL; /* assume a failure */ - - if (!xilinx_validate (desc, (char *)__FUNCTION__)) { - printf ("%s: Invalid device descriptor\n", __FUNCTION__); - } else - switch (desc->family) { - case Xilinx_Spartan2: -#if defined(CONFIG_FPGA_SPARTAN2) - ret_val = Spartan2_reloc (desc, reloc_offset); -#else - printf ("%s: No support for Spartan-II devices.\n", - __FUNCTION__); -#endif - break; - case Xilinx_Spartan3: -#if defined(CONFIG_FPGA_SPARTAN3) - ret_val = Spartan3_reloc (desc, reloc_offset); -#else - printf ("%s: No support for Spartan-III devices.\n", - __FUNCTION__); -#endif - break; - case Xilinx_Virtex2: -#if defined(CONFIG_FPGA_VIRTEX2) - ret_val = Virtex2_reloc (desc, reloc_offset); -#else - printf ("%s: No support for Virtex-II devices.\n", - __FUNCTION__); -#endif - break; - /* Add new family types here */ - default: - printf ("%s: Unsupported family type, %d\n", - __FUNCTION__, desc->family); - } - - return ret_val; -} - - /* ------------------------------------------------------------------------- */ static int xilinx_validate (Xilinx_desc * desc, char *fn) diff --git a/drivers/mtd/nand/nand.c b/drivers/mtd/nand/nand.c index 9065fa91c6..47d6872fd0 100644 --- a/drivers/mtd/nand/nand.c +++ b/drivers/mtd/nand/nand.c @@ -54,8 +54,10 @@ static void nand_init_chip(struct mtd_info *mtd, struct nand_chip *nand, if (nand_scan(mtd, maxchips) == 0) { if (!mtd->name) mtd->name = (char *)default_nand_name; +#ifndef CONFIG_RELOC_FIXUP_WORKS else mtd->name += gd->reloc_off; +#endif #ifdef CONFIG_MTD_DEVICE /* diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c index afd108415b..2fac64167b 100644 --- a/drivers/net/4xx_enet.c +++ b/drivers/net/4xx_enet.c @@ -44,7 +44,7 @@ * RX descriptor address up to the next cache line boundary. * 16-Jan-00 Added support for booting with IP of 0x0 MKW * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the - * EMAC_RXM register. JWB + * EMAC0_RXM register. JWB * 12-Mar-01 anne-sophie.harnois@nextream.fr * - Variables are compatible with those already defined in * include/net.h @@ -58,7 +58,7 @@ * 08-May-01 stefan.roese@esd-electronics.com * - MAL error handling added (eth_init called again) * 13-Nov-01 stefan.roese@esd-electronics.com - * - Set IST bit in EMAC_M1 reg upon 100MBit or full duplex + * - Set IST bit in EMAC0_MR1 reg upon 100MBit or full duplex * 04-Jan-02 stefan.roese@esd-electronics.com * - Wait for PHY auto negotiation to complete added * 06-Feb-02 stefan.roese@esd-electronics.com @@ -359,7 +359,7 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) EMAC_4XX_HW_PST hw_p = dev->priv; u32 val = 10000; - out_be32((void *)EMAC_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ + out_be32((void *)EMAC0_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ /* 1st reset MAL channel */ /* Note: writing a 0 to a channel has no effect */ @@ -382,7 +382,7 @@ static void ppc_4xx_eth_halt (struct eth_device *dev) emac_loopback_enable(hw_p); /* EMAC RESET */ - out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); + out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST); /* remove clocks for EMAC internal loopback */ emac_loopback_disable(hw_p); @@ -485,7 +485,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) /* Ensure we setup mdio for this devnum and ONLY this devnum */ zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); - out_be32((void *)ZMII_FER, zmiifer); + out_be32((void *)ZMII0_FER, zmiifer); out_be32((void *)RGMII_FER, rmiifer); return ((int)pfc1); @@ -504,21 +504,21 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) switch (pfc1) { case SDR0_PFC1_SELECT_CONFIG_2: /* 1 x GMII port */ - out_be32((void *)ZMII_FER, 0x00); + out_be32((void *)ZMII0_FER, 0x00); out_be32((void *)RGMII_FER, 0x00000037); bis->bi_phymode[0] = BI_PHYMODE_GMII; bis->bi_phymode[1] = BI_PHYMODE_NONE; break; case SDR0_PFC1_SELECT_CONFIG_4: /* 2 x RGMII ports */ - out_be32((void *)ZMII_FER, 0x00); + out_be32((void *)ZMII0_FER, 0x00); out_be32((void *)RGMII_FER, 0x00000055); bis->bi_phymode[0] = BI_PHYMODE_RGMII; bis->bi_phymode[1] = BI_PHYMODE_RGMII; break; case SDR0_PFC1_SELECT_CONFIG_6: /* 2 x SMII ports */ - out_be32((void *)ZMII_FER, + out_be32((void *)ZMII0_FER, ((ZMII_FER_SMII) << ZMII_FER_V(0)) | ((ZMII_FER_SMII) << ZMII_FER_V(1))); out_be32((void *)RGMII_FER, 0x00000000); @@ -527,7 +527,7 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) break; case SDR0_PFC1_SELECT_CONFIG_1_2: /* only 1 x MII supported */ - out_be32((void *)ZMII_FER, (ZMII_FER_MII) << ZMII_FER_V(0)); + out_be32((void *)ZMII0_FER, (ZMII_FER_MII) << ZMII_FER_V(0)); out_be32((void *)RGMII_FER, 0x00000000); bis->bi_phymode[0] = BI_PHYMODE_MII; bis->bi_phymode[1] = BI_PHYMODE_NONE; @@ -537,9 +537,9 @@ int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) } /* Ensure we setup mdio for this devnum and ONLY this devnum */ - zmiifer = in_be32((void *)ZMII_FER); + zmiifer = in_be32((void *)ZMII0_FER); zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); - out_be32((void *)ZMII_FER, zmiifer); + out_be32((void *)ZMII0_FER, zmiifer); return ((int)0x0); } @@ -953,18 +953,18 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) /* NOTE: Therefore, disable all other EMACS, since we handle */ /* NOTE: only one emac at a time */ reg = 0; - out_be32((void *)ZMII_FER, 0); + out_be32((void *)ZMII0_FER, 0); udelay (100); #if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) - out_be32((void *)ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); + out_be32((void *)ZMII0_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); #elif defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); #endif - out_be32((void *)ZMII_SSR, ZMII_SSR_SP << ZMII_SSR_V(devnum)); + out_be32((void *)ZMII0_SSR, ZMII0_SSR_SP << ZMII0_SSR_V(devnum)); #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ #if defined(CONFIG_405EX) ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); @@ -976,13 +976,13 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) emac_loopback_enable(hw_p); /* EMAC RESET */ - out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_SRST); + out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST); /* remove clocks for EMAC internal loopback */ emac_loopback_disable(hw_p); failsafe = 1000; - while ((in_be32((void *)EMAC_M0 + hw_p->hw_addr) & (EMAC_M0_SRST)) && failsafe) { + while ((in_be32((void *)EMAC0_MR0 + hw_p->hw_addr) & (EMAC_MR0_SRST)) && failsafe) { udelay (1000); failsafe--; } @@ -1000,15 +1000,15 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) opbfreq = sysinfo.freqOPB / 1000000; if (opbfreq <= 50); else if (opbfreq <= 66) - mode_reg |= EMAC_M1_OBCI_66; + mode_reg |= EMAC_MR1_OBCI_66; else if (opbfreq <= 83) - mode_reg |= EMAC_M1_OBCI_83; + mode_reg |= EMAC_MR1_OBCI_83; else if (opbfreq <= 100) - mode_reg |= EMAC_M1_OBCI_100; + mode_reg |= EMAC_MR1_OBCI_100; else - mode_reg |= EMAC_M1_OBCI_GT100; + mode_reg |= EMAC_MR1_OBCI_GT100; - out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); + out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg); #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ #if defined(CONFIG_GPCS_PHY_ADDR) || defined(CONFIG_GPCS_PHY1_ADDR) || \ @@ -1041,9 +1041,9 @@ static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) #endif } - mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr); - mode_reg |= EMAC_M1_MF_1000GPCS | EMAC_M1_IPPA_SET(reg); - out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); + mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr); + mode_reg |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_IPPA_SET(reg); + out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg); /* Configure GPCS interface to recommended setting for SGMII */ miiphy_reset(dev->name, reg); @@ -1250,11 +1250,11 @@ get_speed: #endif /* Set ZMII/RGMII speed according to the phy link speed */ - reg = in_be32((void *)ZMII_SSR); + reg = in_be32((void *)ZMII0_SSR); if ( (speed == 100) || (speed == 1000) ) - out_be32((void *)ZMII_SSR, reg | (ZMII_SSR_SP << ZMII_SSR_V (devnum))); + out_be32((void *)ZMII0_SSR, reg | (ZMII0_SSR_SP << ZMII0_SSR_V (devnum))); else - out_be32((void *)ZMII_SSR, reg & (~(ZMII_SSR_SP << ZMII_SSR_V (devnum)))); + out_be32((void *)ZMII0_SSR, reg & (~(ZMII0_SSR_SP << ZMII0_SSR_V (devnum)))); if ((devnum == 2) || (devnum == 3)) { if (speed == 1000) @@ -1381,7 +1381,7 @@ get_speed: reg = reg << 8; reg |= dev->enetaddr[1]; - out_be32((void *)EMAC_IAH + hw_p->hw_addr, reg); + out_be32((void *)EMAC0_IAH + hw_p->hw_addr, reg); reg = 0x00000000; reg |= dev->enetaddr[2]; /* set low address */ @@ -1392,7 +1392,7 @@ get_speed: reg = reg << 8; reg |= dev->enetaddr[5]; - out_be32((void *)EMAC_IAL + hw_p->hw_addr, reg); + out_be32((void *)EMAC0_IAL + hw_p->hw_addr, reg); switch (devnum) { case 1: @@ -1480,9 +1480,9 @@ get_speed: mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> hw_p->devnum)); /* set transmit enable & receive enable */ - out_be32((void *)EMAC_M0 + hw_p->hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); + out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_TXE | EMAC_MR0_RXE); - mode_reg = in_be32((void *)EMAC_M1 + hw_p->hw_addr); + mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr); /* set rx-/tx-fifo size */ mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE; @@ -1497,47 +1497,47 @@ get_speed: pfc1 |= SDR0_PFC1_EM_1000; mtsdr (SDR0_PFC1, pfc1); #endif - mode_reg = mode_reg | EMAC_M1_MF_1000MBPS | EMAC_M1_IST; + mode_reg = mode_reg | EMAC_MR1_MF_1000MBPS | EMAC_MR1_IST; } else if (speed == _100BASET) - mode_reg = mode_reg | EMAC_M1_MF_100MBPS | EMAC_M1_IST; + mode_reg = mode_reg | EMAC_MR1_MF_100MBPS | EMAC_MR1_IST; else mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */ if (duplex == FULL) - mode_reg = mode_reg | 0x80000000 | EMAC_M1_IST; + mode_reg = mode_reg | 0x80000000 | EMAC_MR1_IST; - out_be32((void *)EMAC_M1 + hw_p->hw_addr, mode_reg); + out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg); /* Enable broadcast and indvidual address */ /* TBS: enabling runts as some misbehaved nics will send runts */ - out_be32((void *)EMAC_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); + out_be32((void *)EMAC0_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); /* we probably need to set the tx mode1 reg? maybe at tx time */ /* set transmit request threshold register */ - out_be32((void *)EMAC_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ + out_be32((void *)EMAC0_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ /* set receive low/high water mark register */ #if defined(CONFIG_440) /* 440s has a 64 byte burst length */ - out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); + out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); #else /* 405s have a 16 byte burst length */ - out_be32((void *)EMAC_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); + out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); #endif /* defined(CONFIG_440) */ - out_be32((void *)EMAC_TXM1 + hw_p->hw_addr, 0xf8640000); + out_be32((void *)EMAC0_TMR1 + hw_p->hw_addr, 0xf8640000); /* Set fifo limit entry in tx mode 0 */ - out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, 0x00000003); + out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr, 0x00000003); /* Frame gap set */ - out_be32((void *)EMAC_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); + out_be32((void *)EMAC0_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); /* Set EMAC IER */ hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE; if (speed == _100BASET) hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE; - out_be32((void *)EMAC_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ - out_be32((void *)EMAC_IER + hw_p->hw_addr, hw_p->emac_ier); + out_be32((void *)EMAC0_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ + out_be32((void *)EMAC0_IER + hw_p->hw_addr, hw_p->emac_ier); if (hw_p->first_init == 0) { /* @@ -1596,8 +1596,8 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, sync(); - out_be32((void *)EMAC_TXM0 + hw_p->hw_addr, - in_be32((void *)EMAC_TXM0 + hw_p->hw_addr) | EMAC_TXM0_GNP0); + out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr, + in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr) | EMAC_TMR0_GNP0); #ifdef INFO_4XX_ENET hw_p->stats.pkts_tx++; #endif @@ -1607,9 +1607,9 @@ static int ppc_4xx_eth_send (struct eth_device *dev, volatile void *ptr, *-----------------------------------------------------------------------*/ time_start = get_timer (0); while (1) { - temp_txm0 = in_be32((void *)EMAC_TXM0 + hw_p->hw_addr); + temp_txm0 = in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr); /* loop until either TINT turns on or 3 seconds elapse */ - if ((temp_txm0 & EMAC_TXM0_GNP0) != 0) { + if ((temp_txm0 & EMAC_TMR0_GNP0) != 0) { /* transmit is done, so now check for errors * If there is an error, an interrupt should * happen when we return @@ -1678,7 +1678,7 @@ int enetInt (struct eth_device *dev) /* look for EMAC errors */ if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) { - emac_isr = in_be32((void *)EMAC_ISR + hw_p->hw_addr); + emac_isr = in_be32((void *)EMAC0_ISR + hw_p->hw_addr); emac_err(dev, emac_isr); /* clear EMAC error interrupt status bits */ @@ -1717,6 +1717,15 @@ int enetInt (struct eth_device *dev) rc = 0; } } +#if defined(CONFIG_405EZ) + /* + * On 405EZ the RX-/TX-interrupts are coalesced into + * one IRQ bit in the UIC. We need to acknowledge the + * RX-/TX-interrupts in the SDR0_ICINTSTAT reg as well. + */ + mtsdr(SDR0_ICINTSTAT, + SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT); +#endif /* defined(CONFIG_405EZ) */ } while (serviced); return (rc); @@ -1752,7 +1761,7 @@ static void emac_err (struct eth_device *dev, unsigned long isr) EMAC_4XX_HW_PST hw_p = dev->priv; printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr); - out_be32((void *)EMAC_ISR + hw_p->hw_addr, isr); + out_be32((void *)EMAC0_ISR + hw_p->hw_addr, isr); } /*-----------------------------------------------------------------------------+ diff --git a/drivers/net/Makefile b/drivers/net/Makefile index be5c484d18..fc9887b51d 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -64,7 +64,7 @@ COBJS-$(CONFIG_RTL8139) += rtl8139.o COBJS-$(CONFIG_RTL8169) += rtl8169.o COBJS-$(CONFIG_DRIVER_S3C4510_ETH) += s3c4510b_eth.o COBJS-$(CONFIG_SH_ETHER) += sh_eth.o -COBJS-$(CONFIG_DRIVER_SMC91111) += smc91111.o +COBJS-$(CONFIG_SMC91111) += smc91111.o COBJS-$(CONFIG_SMC911X) += smc911x.o COBJS-$(CONFIG_TIGON3) += tigon3.o bcm570x_autoneg.o 5701rls.o COBJS-$(CONFIG_DRIVER_TI_EMAC) += davinci_emac.o diff --git a/drivers/net/kirkwood_egiga.c b/drivers/net/kirkwood_egiga.c index 479035d552..07a86cd6f7 100644 --- a/drivers/net/kirkwood_egiga.c +++ b/drivers/net/kirkwood_egiga.c @@ -400,8 +400,10 @@ static int kwgbe_init(struct eth_device *dev) { struct kwgbe_device *dkwgbe = to_dkwgbe(dev); struct kwgbe_registers *regs = dkwgbe->regs; +#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \ + && defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN) int i; - +#endif /* setup RX rings */ kwgbe_init_rx_desc_ring(dkwgbe); diff --git a/drivers/net/phy/miiphybb.c b/drivers/net/phy/miiphybb.c index b77c917462..44c45fa66b 100644 --- a/drivers/net/phy/miiphybb.c +++ b/drivers/net/phy/miiphybb.c @@ -1,4 +1,7 @@ /* + * (C) Copyright 2009 Industrie Dial Face S.p.A. + * Luigi 'Comio' Mantellini + * * (C) Copyright 2001 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com. * @@ -29,18 +32,144 @@ #include #include #include +#include + +#define BB_MII_RELOCATE(v,off) (v += (v?off:0)) + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_BITBANGMII_MULTI + +/* + * If CONFIG_BITBANGMII_MULTI is not defined we use a + * compatibility layer with the previous miiphybb implementation + * based on macros usage. + * + */ +static int bb_mii_init_wrap(struct bb_miiphy_bus *bus) +{ +#ifdef MII_INIT + MII_INIT; +#endif + return 0; +} + +static int bb_mdio_active_wrap(struct bb_miiphy_bus *bus) +{ +#ifdef MDIO_DECLARE + MDIO_DECLARE; +#endif + MDIO_ACTIVE; + return 0; +} + +static int bb_mdio_tristate_wrap(struct bb_miiphy_bus *bus) +{ +#ifdef MDIO_DECLARE + MDIO_DECLARE; +#endif + MDIO_TRISTATE; + return 0; +} + +static int bb_set_mdio_wrap(struct bb_miiphy_bus *bus, int v) +{ +#ifdef MDIO_DECLARE + MDIO_DECLARE; +#endif + MDIO(v); + return 0; +} + +static int bb_get_mdio_wrap(struct bb_miiphy_bus *bus, int *v) +{ +#ifdef MDIO_DECLARE + MDIO_DECLARE; +#endif + *v = MDIO_READ; + return 0; +} + +static int bb_set_mdc_wrap(struct bb_miiphy_bus *bus, int v) +{ +#ifdef MDC_DECLARE + MDC_DECLARE; +#endif + MDC(v); + return 0; +} + +static int bb_delay_wrap(struct bb_miiphy_bus *bus) +{ + MIIDELAY; + return 0; +} + +struct bb_miiphy_bus bb_miiphy_buses[] = { + { + .name = BB_MII_DEVNAME, + .init = bb_mii_init_wrap, + .mdio_active = bb_mdio_active_wrap, + .mdio_tristate = bb_mdio_tristate_wrap, + .set_mdio = bb_set_mdio_wrap, + .get_mdio = bb_get_mdio_wrap, + .set_mdc = bb_set_mdc_wrap, + .delay = bb_delay_wrap, + } +}; + +int bb_miiphy_buses_num = sizeof(bb_miiphy_buses) / + sizeof(bb_miiphy_buses[0]); +#endif + +void bb_miiphy_init(void) +{ + int i; + + for (i = 0; i < bb_miiphy_buses_num; i++) { +#if !defined(CONFIG_RELOC_FIXUP_WORKS) + /* Relocate the hook pointers*/ + BB_MII_RELOCATE(bb_miiphy_buses[i].init, gd->reloc_off); + BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_active, gd->reloc_off); + BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_tristate, gd->reloc_off); + BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdio, gd->reloc_off); + BB_MII_RELOCATE(bb_miiphy_buses[i].get_mdio, gd->reloc_off); + BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdc, gd->reloc_off); + BB_MII_RELOCATE(bb_miiphy_buses[i].delay, gd->reloc_off); +#endif + if (bb_miiphy_buses[i].init != NULL) { + bb_miiphy_buses[i].init(&bb_miiphy_buses[i]); + } + } +} + +static inline struct bb_miiphy_bus *bb_miiphy_getbus(char *devname) +{ +#ifdef CONFIG_BITBANGMII_MULTI + int i; + + /* Search the correct bus */ + for (i = 0; i < bb_miiphy_buses_num; i++) { + if (!strcmp(bb_miiphy_buses[i].name, devname)) { + return &bb_miiphy_buses[i]; + } + } + return NULL; +#else + /* We have just one bitbanging bus */ + return &bb_miiphy_buses[0]; +#endif +} /***************************************************************************** * * Utility to send the preamble, address, and register (common to read * and write). */ -static void miiphy_pre (char read, unsigned char addr, unsigned char reg) +static void miiphy_pre(struct bb_miiphy_bus *bus, char read, + unsigned char addr, unsigned char reg) { - int j; /* counter */ -#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) - volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT); -#endif + int j; /* * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure. @@ -50,67 +179,66 @@ static void miiphy_pre (char read, unsigned char addr, unsigned char reg) * but it is safer and will be much more robust. */ - MDIO_ACTIVE; - MDIO (1); + bus->mdio_active(bus); + bus->set_mdio(bus, 1); for (j = 0; j < 32; j++) { - MDC (0); - MIIDELAY; - MDC (1); - MIIDELAY; + bus->set_mdc(bus, 0); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); } /* send the start bit (01) and the read opcode (10) or write (10) */ - MDC (0); - MDIO (0); - MIIDELAY; - MDC (1); - MIIDELAY; - MDC (0); - MDIO (1); - MIIDELAY; - MDC (1); - MIIDELAY; - MDC (0); - MDIO (read); - MIIDELAY; - MDC (1); - MIIDELAY; - MDC (0); - MDIO (!read); - MIIDELAY; - MDC (1); - MIIDELAY; + bus->set_mdc(bus, 0); + bus->set_mdio(bus, 0); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 0); + bus->set_mdio(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 0); + bus->set_mdio(bus, read); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 0); + bus->set_mdio(bus, !read); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); /* send the PHY address */ for (j = 0; j < 5; j++) { - MDC (0); + bus->set_mdc(bus, 0); if ((addr & 0x10) == 0) { - MDIO (0); + bus->set_mdio(bus, 0); } else { - MDIO (1); + bus->set_mdio(bus, 1); } - MIIDELAY; - MDC (1); - MIIDELAY; + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); addr <<= 1; } /* send the register address */ for (j = 0; j < 5; j++) { - MDC (0); + bus->set_mdc(bus, 0); if ((reg & 0x10) == 0) { - MDIO (0); + bus->set_mdio(bus, 0); } else { - MDIO (1); + bus->set_mdio(bus, 1); } - MIIDELAY; - MDC (1); - MIIDELAY; + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); reg <<= 1; } } - /***************************************************************************** * * Read a MII PHY register. @@ -118,63 +246,69 @@ static void miiphy_pre (char read, unsigned char addr, unsigned char reg) * Returns: * 0 on success */ -int bb_miiphy_read (char *devname, unsigned char addr, - unsigned char reg, unsigned short *value) +int bb_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value) { - short rdreg; /* register working value */ - int j; /* counter */ -#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) - volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT); -#endif + short rdreg; /* register working value */ + int v; + int j; /* counter */ + struct bb_miiphy_bus *bus; + + bus = bb_miiphy_getbus(devname); + if (bus == NULL) { + return -1; + } if (value == NULL) { puts("NULL value pointer\n"); - return (-1); + return -1; } - miiphy_pre (1, addr, reg); + miiphy_pre (bus, 1, addr, reg); /* tri-state our MDIO I/O pin so we can read */ - MDC (0); - MDIO_TRISTATE; - MIIDELAY; - MDC (1); - MIIDELAY; + bus->set_mdc(bus, 0); + bus->mdio_tristate(bus); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); /* check the turnaround bit: the PHY should be driving it to zero */ - if (MDIO_READ != 0) { + bus->get_mdio(bus, &v); + if (v != 0) { /* puts ("PHY didn't drive TA low\n"); */ for (j = 0; j < 32; j++) { - MDC (0); - MIIDELAY; - MDC (1); - MIIDELAY; + bus->set_mdc(bus, 0); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); } /* There is no PHY, set value to 0xFFFF and return */ *value = 0xFFFF; - return (-1); + return -1; } - MDC (0); - MIIDELAY; + bus->set_mdc(bus, 0); + bus->delay(bus); /* read 16 bits of register data, MSB first */ rdreg = 0; for (j = 0; j < 16; j++) { - MDC (1); - MIIDELAY; + bus->set_mdc(bus, 1); + bus->delay(bus); rdreg <<= 1; - rdreg |= MDIO_READ; - MDC (0); - MIIDELAY; + bus->get_mdio(bus, &v); + rdreg |= (v & 0x1); + bus->set_mdc(bus, 0); + bus->delay(bus); } - MDC (1); - MIIDELAY; - MDC (0); - MIIDELAY; - MDC (1); - MIIDELAY; + bus->set_mdc(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 0); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); *value = rdreg; @@ -194,49 +328,53 @@ int bb_miiphy_read (char *devname, unsigned char addr, * 0 on success */ int bb_miiphy_write (char *devname, unsigned char addr, - unsigned char reg, unsigned short value) + unsigned char reg, unsigned short value) { + struct bb_miiphy_bus *bus; int j; /* counter */ -#if !(defined(CONFIG_EP8248) || defined(CONFIG_EP82XXM)) - volatile ioport_t *iop = ioport_addr ((immap_t *) CONFIG_SYS_IMMR, MDIO_PORT); -#endif - miiphy_pre (0, addr, reg); + bus = bb_miiphy_getbus(devname); + if (bus == NULL) { + /* Bus not found! */ + return -1; + } + + miiphy_pre (bus, 0, addr, reg); /* send the turnaround (10) */ - MDC (0); - MDIO (1); - MIIDELAY; - MDC (1); - MIIDELAY; - MDC (0); - MDIO (0); - MIIDELAY; - MDC (1); - MIIDELAY; + bus->set_mdc(bus, 0); + bus->set_mdio(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); + bus->set_mdc(bus, 0); + bus->set_mdio(bus, 0); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); /* write 16 bits of register data, MSB first */ for (j = 0; j < 16; j++) { - MDC (0); + bus->set_mdc(bus, 0); if ((value & 0x00008000) == 0) { - MDIO (0); + bus->set_mdio(bus, 0); } else { - MDIO (1); + bus->set_mdio(bus, 1); } - MIIDELAY; - MDC (1); - MIIDELAY; + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); value <<= 1; } /* * Tri-state the MDIO line. */ - MDIO_TRISTATE; - MDC (0); - MIIDELAY; - MDC (1); - MIIDELAY; + bus->mdio_tristate(bus); + bus->set_mdc(bus, 0); + bus->delay(bus); + bus->set_mdc(bus, 1); + bus->delay(bus); return 0; -} +} \ No newline at end of file diff --git a/drivers/net/phy/mv88e61xx.c b/drivers/net/phy/mv88e61xx.c index 3754e8bdc4..2d1de02917 100644 --- a/drivers/net/phy/mv88e61xx.c +++ b/drivers/net/phy/mv88e61xx.c @@ -201,11 +201,11 @@ static void mv88e61xx_port_vlan_config(struct mv88e61xx_config *swconfig, */ static int mv88e61xx_busychk(char *name) { - u32 reg = 0; + u16 reg = 0; u32 timeout = MV88E61XX_PHY_TIMEOUT; do { RD_PHY(name, MV88E61XX_GLB2REG_DEVADR, - MV88E61XX_PHY_CMD, (u16 *) & reg); + MV88E61XX_PHY_CMD, ®); if (timeout-- == 0) { printf("SMI busy timeout\n"); return -1; diff --git a/drivers/net/smc91111.c b/drivers/net/smc91111.c index b41e4d2866..54a1bfb2a9 100644 --- a/drivers/net/smc91111.c +++ b/drivers/net/smc91111.c @@ -62,6 +62,7 @@ #include #include #include +#include #include "smc91111.h" #include @@ -122,17 +123,15 @@ static const char version[] = . what you are doing. . -------------------------------------------------------------------------*/ -#define CARDNAME "LAN91C111" /* Memory sizing constant */ #define LAN91C111_MEMORY_MULTIPLIER (1024*2) #ifndef CONFIG_SMC91111_BASE -#define CONFIG_SMC91111_BASE 0x20000300 +#error "SMC91111 Base address must be passed to initialization funciton" +/* #define CONFIG_SMC91111_BASE 0x20000300 */ #endif -#define SMC_BASE_ADDRESS CONFIG_SMC91111_BASE - #define SMC_DEV_NAME "SMC91111" #define SMC_PHY_ADDR 0x0000 #define SMC_ALLOC_MAX_TRY 5 @@ -147,72 +146,17 @@ static const char version[] = #else #undef USE_32_BIT #endif -/*----------------------------------------------------------------- - . - . The driver can be entered at any of the following entry points. - . - .------------------------------------------------------------------ */ - -extern int eth_init(bd_t *bd); -extern void eth_halt(void); -extern int eth_rx(void); -extern int eth_send(volatile void *packet, int length); #ifdef SHARED_RESOURCES - extern void swap_to(int device_id); +extern void swap_to(int device_id); +#else +# define swap_to(x) #endif -/* - . This is called by register_netdev(). It is responsible for - . checking the portlist for the SMC9000 series chipset. If it finds - . one, then it will initialize the device, find the hardware information, - . and sets up the appropriate device parameters. - . NOTE: Interrupts are *OFF* when this procedure is called. - . - . NB:This shouldn't be static since it is referred to externally. -*/ -int smc_init(void); - -/* - . This is called by unregister_netdev(). It is responsible for - . cleaning up before the driver is finally unregistered and discarded. -*/ -void smc_destructor(void); - -/* - . The kernel calls this function when someone wants to use the device, - . typically 'ifconfig ethX up'. -*/ -static int smc_open(bd_t *bd); - - -/* - . This is called by the kernel in response to 'ifconfig ethX down'. It - . is responsible for cleaning up everything that the open routine - . does, and maybe putting the card into a powerdown state. -*/ -static int smc_close(void); - -/* - . Configures the PHY through the MII Management interface -*/ #ifndef CONFIG_SMC91111_EXT_PHY -static void smc_phy_configure(void); +static void smc_phy_configure(struct eth_device *dev); #endif /* !CONFIG_SMC91111_EXT_PHY */ -/* - . This is a separate procedure to handle the receipt of a packet, to - . leave the interrupt code looking slightly cleaner -*/ -static int smc_rcv(void); - -/* See if a MAC address is defined in the current environment. If so use it. If not - . print a warning and set the environment and other globals with the default. - . If an EEPROM is present it really should be consulted. -*/ -int smc_get_ethaddr(bd_t *bd); -int get_rom_mac(uchar *v_rom_mac); - /* ------------------------------------------------------------ . @@ -233,125 +177,69 @@ int get_rom_mac(uchar *v_rom_mac); * packets being corrupt (shifted) on the wire, etc. Switching to the * inx,outx functions fixed this problem. */ -static inline word SMC_inw(dword offset); -static inline void SMC_outw(word value, dword offset); -static inline byte SMC_inb(dword offset); -static inline void SMC_outb(byte value, dword offset); -static inline void SMC_insw(dword offset, volatile uchar* buf, dword len); -static inline void SMC_outsw(dword offset, uchar* buf, dword len); #define barrier() __asm__ __volatile__("": : :"memory") -static inline word SMC_inw(dword offset) +static inline word SMC_inw(struct eth_device *dev, dword offset) { word v; - v = *((volatile word*)(SMC_BASE_ADDRESS+offset)); + v = *((volatile word*)(dev->iobase + offset)); barrier(); *(volatile u32*)(0xc0000000); return v; } -static inline void SMC_outw(word value, dword offset) +static inline void SMC_outw(struct eth_device *dev, word value, dword offset) { - *((volatile word*)(SMC_BASE_ADDRESS+offset)) = value; + *((volatile word*)(dev->iobase + offset)) = value; barrier(); *(volatile u32*)(0xc0000000); } -static inline byte SMC_inb(dword offset) +static inline byte SMC_inb(struct eth_device *dev, dword offset) { word _w; - _w = SMC_inw(offset & ~((dword)1)); + _w = SMC_inw(dev, offset & ~((dword)1)); return (offset & 1) ? (byte)(_w >> 8) : (byte)(_w); } -static inline void SMC_outb(byte value, dword offset) +static inline void SMC_outb(struct eth_device *dev, byte value, dword offset) { word _w; - _w = SMC_inw(offset & ~((dword)1)); + _w = SMC_inw(dev, offset & ~((dword)1)); if (offset & 1) - *((volatile word*)(SMC_BASE_ADDRESS+(offset & ~((dword)1)))) = (value<<8) | (_w & 0x00ff); + *((volatile word*)(dev->iobase + (offset & ~((dword)1)))) = + (value<<8) | (_w & 0x00ff); else - *((volatile word*)(SMC_BASE_ADDRESS+offset)) = value | (_w & 0xff00); + *((volatile word*)(dev->iobase + offset)) = + value | (_w & 0xff00); } -static inline void SMC_insw(dword offset, volatile uchar* buf, dword len) +static inline void SMC_insw(struct eth_device *dev, dword offset, + volatile uchar* buf, dword len) { volatile word *p = (volatile word *)buf; while (len-- > 0) { - *p++ = SMC_inw(offset); + *p++ = SMC_inw(dev, offset); barrier(); *((volatile u32*)(0xc0000000)); } } -static inline void SMC_outsw(dword offset, uchar* buf, dword len) +static inline void SMC_outsw(struct eth_device *dev, dword offset, + uchar* buf, dword len) { volatile word *p = (volatile word *)buf; while (len-- > 0) { - SMC_outw(*p++, offset); + SMC_outw(dev, *p++, offset); barrier(); *(volatile u32*)(0xc0000000); } } #endif /* CONFIG_SMC_USE_IOFUNCS */ -static char unsigned smc_mac_addr[6] = {0x02, 0x80, 0xad, 0x20, 0x31, 0xb8}; - -/* - * This function must be called before smc_open() if you want to override - * the default mac address. - */ - -void smc_set_mac_addr(const unsigned char *addr) { - int i; - - for (i=0; i < sizeof(smc_mac_addr); i++){ - smc_mac_addr[i] = addr[i]; - } -} - -/* - * smc_get_macaddr is no longer used. If you want to override the default - * mac address, call smc_get_mac_addr as a part of the board initialization. - */ - -#if 0 -void smc_get_macaddr( byte *addr ) { - /* MAC ADDRESS AT FLASHBLOCK 1 / OFFSET 0x10 */ - unsigned char *dnp1110_mac = (unsigned char *) (0xE8000000 + 0x20010); - int i; - - - for (i=0; i<6; i++) { - addr[0] = *(dnp1110_mac+0); - addr[1] = *(dnp1110_mac+1); - addr[2] = *(dnp1110_mac+2); - addr[3] = *(dnp1110_mac+3); - addr[4] = *(dnp1110_mac+4); - addr[5] = *(dnp1110_mac+5); - } -} -#endif /* 0 */ - -/*********************************************** - * Show available memory * - ***********************************************/ -void dump_memory_info(void) -{ - word mem_info; - word old_bank; - - old_bank = SMC_inw(BANK_SELECT)&0xF; - - SMC_SELECT_BANK(0); - mem_info = SMC_inw( MIR_REG ); - PRINTK2("Memory: %4d available\n", (mem_info >> 8)*2048); - - SMC_SELECT_BANK(old_bank); -} /* . A rather simple routine to print out a packet for debugging purposes. */ @@ -361,35 +249,15 @@ static void print_packet( byte *, int ); #define tx_done(dev) 1 - -/* this does a soft reset on the device */ -static void smc_reset( void ); - -/* Enable Interrupts, Receive, and Transmit */ -static void smc_enable( void ); - -/* this puts the device in an inactive state */ -static void smc_shutdown( void ); - -/* Routines to Read and Write the PHY Registers across the - MII Management Interface -*/ - -#ifndef CONFIG_SMC91111_EXT_PHY -static word smc_read_phy_register(byte phyreg); -static void smc_write_phy_register(byte phyreg, word phydata); -#endif /* !CONFIG_SMC91111_EXT_PHY */ - - -static int poll4int (byte mask, int timeout) +static int poll4int (struct eth_device *dev, byte mask, int timeout) { int tmo = get_timer (0) + timeout * CONFIG_SYS_HZ; int is_timeout = 0; - word old_bank = SMC_inw (BSR_REG); + word old_bank = SMC_inw (dev, BSR_REG); PRINTK2 ("Polling...\n"); - SMC_SELECT_BANK (2); - while ((SMC_inw (SMC91111_INT_REG) & mask) == 0) { + SMC_SELECT_BANK (dev, 2); + while ((SMC_inw (dev, SMC91111_INT_REG) & mask) == 0) { if (get_timer (0) >= tmo) { is_timeout = 1; break; @@ -397,7 +265,7 @@ static int poll4int (byte mask, int timeout) } /* restore old bank selection */ - SMC_SELECT_BANK (old_bank); + SMC_SELECT_BANK (dev, old_bank); if (is_timeout) return 1; @@ -406,12 +274,12 @@ static int poll4int (byte mask, int timeout) } /* Only one release command at a time, please */ -static inline void smc_wait_mmu_release_complete (void) +static inline void smc_wait_mmu_release_complete (struct eth_device *dev) { int count = 0; /* assume bank 2 selected */ - while (SMC_inw (MMU_CMD_REG) & MC_BUSY) { + while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { udelay (1); /* Wait until not busy */ if (++count > 200) break; @@ -435,49 +303,50 @@ static inline void smc_wait_mmu_release_complete (void) . 5. clear all interrupts . */ -static void smc_reset (void) +static void smc_reset (struct eth_device *dev) { PRINTK2 ("%s: smc_reset\n", SMC_DEV_NAME); /* This resets the registers mostly to defaults, but doesn't affect EEPROM. That seems unnecessary */ - SMC_SELECT_BANK (0); - SMC_outw (RCR_SOFTRST, RCR_REG); + SMC_SELECT_BANK (dev, 0); + SMC_outw (dev, RCR_SOFTRST, RCR_REG); /* Setup the Configuration Register */ /* This is necessary because the CONFIG_REG is not affected */ /* by a soft reset */ - SMC_SELECT_BANK (1); + SMC_SELECT_BANK (dev, 1); #if defined(CONFIG_SMC91111_EXT_PHY) - SMC_outw (CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG); + SMC_outw (dev, CONFIG_DEFAULT | CONFIG_EXT_PHY, CONFIG_REG); #else - SMC_outw (CONFIG_DEFAULT, CONFIG_REG); + SMC_outw (dev, CONFIG_DEFAULT, CONFIG_REG); #endif /* Release from possible power-down state */ /* Configuration register is not affected by Soft Reset */ - SMC_outw (SMC_inw (CONFIG_REG) | CONFIG_EPH_POWER_EN, CONFIG_REG); + SMC_outw (dev, SMC_inw (dev, CONFIG_REG) | CONFIG_EPH_POWER_EN, + CONFIG_REG); - SMC_SELECT_BANK (0); + SMC_SELECT_BANK (dev, 0); /* this should pause enough for the chip to be happy */ udelay (10); /* Disable transmit and receive functionality */ - SMC_outw (RCR_CLEAR, RCR_REG); - SMC_outw (TCR_CLEAR, TCR_REG); + SMC_outw (dev, RCR_CLEAR, RCR_REG); + SMC_outw (dev, TCR_CLEAR, TCR_REG); /* set the control register */ - SMC_SELECT_BANK (1); - SMC_outw (CTL_DEFAULT, CTL_REG); + SMC_SELECT_BANK (dev, 1); + SMC_outw (dev, CTL_DEFAULT, CTL_REG); /* Reset the MMU */ - SMC_SELECT_BANK (2); - smc_wait_mmu_release_complete (); - SMC_outw (MC_RESET, MMU_CMD_REG); - while (SMC_inw (MMU_CMD_REG) & MC_BUSY) + SMC_SELECT_BANK (dev, 2); + smc_wait_mmu_release_complete (dev); + SMC_outw (dev, MC_RESET, MMU_CMD_REG); + while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) udelay (1); /* Wait until not busy */ /* Note: It doesn't seem that waiting for the MMU busy is needed here, @@ -485,7 +354,7 @@ static void smc_reset (void) of issuing another MMU command right after this */ /* Disable all interrupts */ - SMC_outb (0, IM_REG); + SMC_outb (dev, 0, IM_REG); } /* @@ -496,20 +365,20 @@ static void smc_reset (void) . 2. Enable the receiver . 3. Enable interrupts */ -static void smc_enable() +static void smc_enable(struct eth_device *dev) { PRINTK2("%s: smc_enable\n", SMC_DEV_NAME); - SMC_SELECT_BANK( 0 ); + SMC_SELECT_BANK( dev, 0 ); /* see the header file for options in TCR/RCR DEFAULT*/ - SMC_outw( TCR_DEFAULT, TCR_REG ); - SMC_outw( RCR_DEFAULT, RCR_REG ); + SMC_outw( dev, TCR_DEFAULT, TCR_REG ); + SMC_outw( dev, RCR_DEFAULT, RCR_REG ); /* clear MII_DIS */ /* smc_write_phy_register(PHY_CNTL_REG, 0x0000); */ } /* - . Function: smc_shutdown + . Function: smc_halt . Purpose: closes down the SMC91xxx chip. . Method: . 1. zero the interrupt mask @@ -522,26 +391,25 @@ static void smc_enable() . the manual says that it will wake up in response to any I/O requests . in the register space. Empirical results do not show this working. */ -static void smc_shutdown() +static void smc_halt(struct eth_device *dev) { - PRINTK2(CARDNAME ": smc_shutdown\n"); + PRINTK2("%s: smc_halt\n", SMC_DEV_NAME); /* no more interrupts for me */ - SMC_SELECT_BANK( 2 ); - SMC_outb( 0, IM_REG ); + SMC_SELECT_BANK( dev, 2 ); + SMC_outb( dev, 0, IM_REG ); /* and tell the card to stay away from that nasty outside world */ - SMC_SELECT_BANK( 0 ); - SMC_outb( RCR_CLEAR, RCR_REG ); - SMC_outb( TCR_CLEAR, TCR_REG ); -#ifdef SHARED_RESOURCES + SMC_SELECT_BANK( dev, 0 ); + SMC_outb( dev, RCR_CLEAR, RCR_REG ); + SMC_outb( dev, TCR_CLEAR, TCR_REG ); + swap_to(FLASH); -#endif } /* - . Function: smc_hardware_send_packet(struct net_device * ) + . Function: smc_send(struct net_device * ) . Purpose: . This sends the actual packet to the SMC9xxx chip. . @@ -558,10 +426,10 @@ static void smc_shutdown() . Enable the transmit interrupt, so I know if it failed . Free the kernel data if I actually sent it. */ -static int smc_send_packet (volatile void *packet, int packet_length) +static int smc_send(struct eth_device *dev, volatile void *packet, + int packet_length) { byte packet_no; - unsigned long ioaddr; byte *buf; int length; int numPages; @@ -572,9 +440,9 @@ static int smc_send_packet (volatile void *packet, int packet_length) word saved_ptr; /* save PTR and PNR registers before manipulation */ - SMC_SELECT_BANK (2); - saved_pnr = SMC_inb( PN_REG ); - saved_ptr = SMC_inw( PTR_REG ); + SMC_SELECT_BANK (dev, 2); + saved_pnr = SMC_inb( dev, PN_REG ); + saved_ptr = SMC_inw( dev, PTR_REG ); PRINTK3 ("%s: smc_hardware_send_packet\n", SMC_DEV_NAME); @@ -601,8 +469,8 @@ static int smc_send_packet (volatile void *packet, int packet_length) } /* now, try to allocate the memory */ - SMC_SELECT_BANK (2); - SMC_outw (MC_ALLOC | numPages, MMU_CMD_REG); + SMC_SELECT_BANK (dev, 2); + SMC_outw (dev, MC_ALLOC | numPages, MMU_CMD_REG); /* FIXME: the ALLOC_INT bit never gets set * * so the following will always give a * @@ -615,10 +483,10 @@ again: try++; time_out = MEMORY_WAIT_TIME; do { - status = SMC_inb (SMC91111_INT_REG); + status = SMC_inb (dev, SMC91111_INT_REG); if (status & IM_ALLOC_INT) { /* acknowledge the interrupt */ - SMC_outb (IM_ALLOC_INT, SMC91111_INT_REG); + SMC_outb (dev, IM_ALLOC_INT, SMC91111_INT_REG); break; } } while (--time_out); @@ -635,14 +503,10 @@ again: PRINTK2 ("%s: memory allocation, try %d succeeded ...\n", SMC_DEV_NAME, try); - /* I can send the packet now.. */ - - ioaddr = SMC_BASE_ADDRESS; - buf = (byte *) packet; /* If I get here, I _know_ there is a packet slot waiting for me */ - packet_no = SMC_inb (AR_REG); + packet_no = SMC_inb (dev, AR_REG); if (packet_no & AR_FAILED) { /* or isn't there? BAD CHIP! */ printf ("%s: Memory allocation failed. \n", SMC_DEV_NAME); @@ -651,20 +515,20 @@ again: /* we have a packet address, so tell the card to use it */ #ifndef CONFIG_XAENIAX - SMC_outb (packet_no, PN_REG); + SMC_outb (dev, packet_no, PN_REG); #else /* On Xaeniax board, we can't use SMC_outb here because that way * the Allocate MMU command will end up written to the command register * as well, which will lead to a problem. */ - SMC_outl (packet_no << 16, 0); + SMC_outl (dev, packet_no << 16, 0); #endif /* do not write new ptr value if Write data fifo not empty */ while ( saved_ptr & PTR_NOTEMPTY ) printf ("Write data fifo not empty!\n"); /* point to the beginning of the packet */ - SMC_outw (PTR_AUTOINC, PTR_REG); + SMC_outw (dev, PTR_AUTOINC, PTR_REG); PRINTK3 ("%s: Trying to xmit packet of length %x\n", SMC_DEV_NAME, length); @@ -677,11 +541,11 @@ again: /* send the packet length ( +6 for status, length and ctl byte ) and the status word ( set to zeros ) */ #ifdef USE_32_BIT - SMC_outl ((length + 6) << 16, SMC91111_DATA_REG); + SMC_outl (dev, (length + 6) << 16, SMC91111_DATA_REG); #else - SMC_outw (0, SMC91111_DATA_REG); + SMC_outw (dev, 0, SMC91111_DATA_REG); /* send the packet length ( +6 for status words, length, and ctl */ - SMC_outw ((length + 6), SMC91111_DATA_REG); + SMC_outw (dev, (length + 6), SMC91111_DATA_REG); #endif /* send the actual data @@ -692,10 +556,10 @@ again: . almost as much time as is saved? */ #ifdef USE_32_BIT - SMC_outsl (SMC91111_DATA_REG, buf, length >> 2); + SMC_outsl (dev, SMC91111_DATA_REG, buf, length >> 2); #ifndef CONFIG_XAENIAX if (length & 0x2) - SMC_outw (*((word *) (buf + (length & 0xFFFFFFFC))), + SMC_outw (dev, *((word *) (buf + (length & 0xFFFFFFFC))), SMC91111_DATA_REG); #else /* On XANEIAX, we can only use 32-bit writes, so we need to handle @@ -703,48 +567,48 @@ again: */ if ((length & 3) == 3) { u16 * ptr = (u16*) &buf[length-3]; - SMC_outl((*ptr) | ((0x2000 | buf[length-1]) << 16), + SMC_outl(dev, (*ptr) | ((0x2000 | buf[length-1]) << 16), SMC91111_DATA_REG); } else if ((length & 2) == 2) { u16 * ptr = (u16*) &buf[length-2]; - SMC_outl(*ptr, SMC91111_DATA_REG); + SMC_outl(dev, *ptr, SMC91111_DATA_REG); } else if (length & 1) { - SMC_outl((0x2000 | buf[length-1]), SMC91111_DATA_REG); + SMC_outl(dev, (0x2000 | buf[length-1]), SMC91111_DATA_REG); } else { - SMC_outl(0, SMC91111_DATA_REG); + SMC_outl(dev, 0, SMC91111_DATA_REG); } #endif #else - SMC_outsw (SMC91111_DATA_REG, buf, (length) >> 1); + SMC_outsw (dev, SMC91111_DATA_REG, buf, (length) >> 1); #endif /* USE_32_BIT */ #ifndef CONFIG_XAENIAX /* Send the last byte, if there is one. */ if ((length & 1) == 0) { - SMC_outw (0, SMC91111_DATA_REG); + SMC_outw (dev, 0, SMC91111_DATA_REG); } else { - SMC_outw (buf[length - 1] | 0x2000, SMC91111_DATA_REG); + SMC_outw (dev, buf[length - 1] | 0x2000, SMC91111_DATA_REG); } #endif /* and let the chipset deal with it */ - SMC_outw (MC_ENQUEUE, MMU_CMD_REG); + SMC_outw (dev, MC_ENQUEUE, MMU_CMD_REG); /* poll for TX INT */ - /* if (poll4int (IM_TX_INT, SMC_TX_TIMEOUT)) { */ + /* if (poll4int (dev, IM_TX_INT, SMC_TX_TIMEOUT)) { */ /* poll for TX_EMPTY INT - autorelease enabled */ - if (poll4int(IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) { + if (poll4int(dev, IM_TX_EMPTY_INT, SMC_TX_TIMEOUT)) { /* sending failed */ PRINTK2 ("%s: TX timeout, sending failed...\n", SMC_DEV_NAME); /* release packet */ /* no need to release, MMU does that now */ #ifdef CONFIG_XAENIAX - SMC_outw (MC_FREEPKT, MMU_CMD_REG); + SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG); #endif /* wait for MMU getting ready (low) */ - while (SMC_inw (MMU_CMD_REG) & MC_BUSY) { + while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { udelay (10); } @@ -754,7 +618,7 @@ again: return 0; } else { /* ack. int */ - SMC_outb (IM_TX_EMPTY_INT, SMC91111_INT_REG); + SMC_outb (dev, IM_TX_EMPTY_INT, SMC91111_INT_REG); /* SMC_outb (IM_TX_INT, SMC91111_INT_REG); */ PRINTK2 ("%s: Sent packet of length %d \n", SMC_DEV_NAME, length); @@ -762,11 +626,11 @@ again: /* release packet */ /* no need to release, MMU does that now */ #ifdef CONFIG_XAENIAX - SMC_outw (MC_FREEPKT, MMU_CMD_REG); + SMC_outw (dev, MC_FREEPKT, MMU_CMD_REG); #endif /* wait for MMU getting ready (low) */ - while (SMC_inw (MMU_CMD_REG) & MC_BUSY) { + while (SMC_inw (dev, MMU_CMD_REG) & MC_BUSY) { udelay (10); } @@ -777,78 +641,62 @@ again: /* restore previously saved registers */ #ifndef CONFIG_XAENIAX - SMC_outb( saved_pnr, PN_REG ); + SMC_outb( dev, saved_pnr, PN_REG ); #else /* On Xaeniax board, we can't use SMC_outb here because that way * the Allocate MMU command will end up written to the command register * as well, which will lead to a problem. */ - SMC_outl(saved_pnr << 16, 0); + SMC_outl(dev, saved_pnr << 16, 0); #endif - SMC_outw( saved_ptr, PTR_REG ); + SMC_outw( dev, saved_ptr, PTR_REG ); return length; } -/*------------------------------------------------------------------------- - | - | smc_destructor( struct net_device * dev ) - | Input parameters: - | dev, pointer to the device structure - | - | Output: - | None. - | - --------------------------------------------------------------------------- -*/ -void smc_destructor() -{ - PRINTK2(CARDNAME ": smc_destructor\n"); -} - - /* * Open and Initialize the board * * Set up everything, reset the card, etc .. * */ -static int smc_open (bd_t * bd) +static int smc_init(struct eth_device *dev, bd_t *bd) { - int i, err; + int i; - PRINTK2 ("%s: smc_open\n", SMC_DEV_NAME); + swap_to(ETHERNET); + + PRINTK2 ("%s: smc_init\n", SMC_DEV_NAME); /* reset the hardware */ - smc_reset (); - smc_enable (); + smc_reset (dev); + smc_enable (dev); /* Configure the PHY */ #ifndef CONFIG_SMC91111_EXT_PHY - smc_phy_configure (); + smc_phy_configure (dev); #endif /* conservative setting (10Mbps, HalfDuplex, no AutoNeg.) */ -/* SMC_SELECT_BANK(0); */ -/* SMC_outw(0, RPC_REG); */ - SMC_SELECT_BANK (1); +/* SMC_SELECT_BANK(dev, 0); */ +/* SMC_outw(dev, 0, RPC_REG); */ + SMC_SELECT_BANK (dev, 1); - err = smc_get_ethaddr (bd); /* set smc_mac_addr, and sync it with u-boot globals */ - if (err < 0) - return -1; #ifdef USE_32_BIT for (i = 0; i < 6; i += 2) { word address; - address = smc_mac_addr[i + 1] << 8; - address |= smc_mac_addr[i]; - SMC_outw (address, (ADDR0_REG + i)); + address = dev->enetaddr[i + 1] << 8; + address |= dev->enetaddr[i]; + SMC_outw(dev, address, (ADDR0_REG + i)); } #else for (i = 0; i < 6; i++) - SMC_outb (smc_mac_addr[i], (ADDR0_REG + i)); + SMC_outb(dev, dev->enetaddr[i], (ADDR0_REG + i)); #endif + printf(SMC_DEV_NAME ": MAC %pM\n", dev->enetaddr); + return 0; } @@ -864,7 +712,7 @@ static int smc_open (bd_t * bd) . o otherwise, read in the packet -------------------------------------------------------------- */ -static int smc_rcv() +static int smc_rcv(struct eth_device *dev) { int packet_number; word status; @@ -876,12 +724,12 @@ static int smc_rcv() byte saved_pnr; word saved_ptr; - SMC_SELECT_BANK(2); + SMC_SELECT_BANK(dev, 2); /* save PTR and PTR registers */ - saved_pnr = SMC_inb( PN_REG ); - saved_ptr = SMC_inw( PTR_REG ); + saved_pnr = SMC_inb( dev, PN_REG ); + saved_ptr = SMC_inw( dev, PTR_REG ); - packet_number = SMC_inw( RXFIFO_REG ); + packet_number = SMC_inw( dev, RXFIFO_REG ); if ( packet_number & RXFIFO_REMPTY ) { @@ -890,16 +738,16 @@ static int smc_rcv() PRINTK3("%s: smc_rcv\n", SMC_DEV_NAME); /* start reading from the start of the packet */ - SMC_outw( PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG ); + SMC_outw( dev, PTR_READ | PTR_RCV | PTR_AUTOINC, PTR_REG ); /* First two words are status and packet_length */ #ifdef USE_32_BIT - stat_len = SMC_inl(SMC91111_DATA_REG); + stat_len = SMC_inl(dev, SMC91111_DATA_REG); status = stat_len & 0xffff; packet_length = stat_len >> 16; #else - status = SMC_inw( SMC91111_DATA_REG ); - packet_length = SMC_inw( SMC91111_DATA_REG ); + status = SMC_inw( dev, SMC91111_DATA_REG ); + packet_length = SMC_inw( dev, SMC91111_DATA_REG ); #endif packet_length &= 0x07ff; /* mask off top bits */ @@ -923,20 +771,23 @@ static int smc_rcv() to send the DWORDs or the bytes first, or some mixture. A mixture might improve already slow PIO performance */ - SMC_insl( SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 2 ); + SMC_insl( dev, SMC91111_DATA_REG, NetRxPackets[0], + packet_length >> 2 ); /* read the left over bytes */ if (packet_length & 3) { int i; - byte *tail = (byte *)(NetRxPackets[0] + (packet_length & ~3)); - dword leftover = SMC_inl(SMC91111_DATA_REG); + byte *tail = (byte *)(NetRxPackets[0] + + (packet_length & ~3)); + dword leftover = SMC_inl(dev, SMC91111_DATA_REG); for (i=0; i<(packet_length & 3); i++) *tail++ = (byte) (leftover >> (8*i)) & 0xff; } #else PRINTK3(" Reading %d words and %d byte(s) \n", (packet_length >> 1 ), packet_length & 1 ); - SMC_insw(SMC91111_DATA_REG , NetRxPackets[0], packet_length >> 1); + SMC_insw(dev, SMC91111_DATA_REG , NetRxPackets[0], + packet_length >> 1); #endif /* USE_32_BIT */ @@ -950,26 +801,26 @@ static int smc_rcv() is_error = 1; } - while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY ) + while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY ) udelay(1); /* Wait until not busy */ /* error or good, tell the card to get rid of this packet */ - SMC_outw( MC_RELEASE, MMU_CMD_REG ); + SMC_outw( dev, MC_RELEASE, MMU_CMD_REG ); - while ( SMC_inw( MMU_CMD_REG ) & MC_BUSY ) + while ( SMC_inw( dev, MMU_CMD_REG ) & MC_BUSY ) udelay(1); /* Wait until not busy */ /* restore saved registers */ #ifndef CONFIG_XAENIAX - SMC_outb( saved_pnr, PN_REG ); + SMC_outb( dev, saved_pnr, PN_REG ); #else /* On Xaeniax board, we can't use SMC_outb here because that way * the Allocate MMU command will end up written to the command register * as well, which will lead to a problem. */ - SMC_outl( saved_pnr << 16, 0); + SMC_outl( dev, saved_pnr << 16, 0); #endif - SMC_outw( saved_ptr, PTR_REG ); + SMC_outw( dev, saved_ptr, PTR_REG ); if (!is_error) { /* Pass the packet up to the protocol layers. */ @@ -982,43 +833,24 @@ static int smc_rcv() } -/*---------------------------------------------------- - . smc_close - . - . this makes the board clean up everything that it can - . and not talk to the outside world. Caused by - . an 'ifconfig ethX down' - . - -----------------------------------------------------*/ -static int smc_close() -{ - PRINTK2("%s: smc_close\n", SMC_DEV_NAME); - - /* clear everything */ - smc_shutdown(); - - return 0; -} - - #if 0 /*------------------------------------------------------------ . Modify a bit in the LAN91C111 register set .-------------------------------------------------------------*/ -static word smc_modify_regbit(int bank, int ioaddr, int reg, +static word smc_modify_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit, int val) { word regval; - SMC_SELECT_BANK( bank ); + SMC_SELECT_BANK( dev, bank ); - regval = SMC_inw( reg ); + regval = SMC_inw( dev, reg ); if (val) regval |= bit; else regval &= ~bit; - SMC_outw( regval, 0 ); + SMC_outw( dev, regval, 0 ); return(regval); } @@ -1026,10 +858,10 @@ static word smc_modify_regbit(int bank, int ioaddr, int reg, /*------------------------------------------------------------ . Retrieve a bit in the LAN91C111 register set .-------------------------------------------------------------*/ -static int smc_get_regbit(int bank, int ioaddr, int reg, unsigned int bit) +static int smc_get_regbit(struct eth_device *dev, int bank, int ioaddr, int reg, unsigned int bit) { - SMC_SELECT_BANK( bank ); - if ( SMC_inw( reg ) & bit) + SMC_SELECT_BANK( dev, bank ); + if ( SMC_inw( dev, reg ) & bit) return(1); else return(0); @@ -1039,20 +871,20 @@ static int smc_get_regbit(int bank, int ioaddr, int reg, unsigned int bit) /*------------------------------------------------------------ . Modify a LAN91C111 register (word access only) .-------------------------------------------------------------*/ -static void smc_modify_reg(int bank, int ioaddr, int reg, word val) +static void smc_modify_reg(struct eth_device *dev, int bank, int ioaddr, int reg, word val) { - SMC_SELECT_BANK( bank ); - SMC_outw( val, reg ); + SMC_SELECT_BANK( dev, bank ); + SMC_outw( dev, val, reg ); } /*------------------------------------------------------------ . Retrieve a LAN91C111 register (word access only) .-------------------------------------------------------------*/ -static int smc_get_reg(int bank, int ioaddr, int reg) +static int smc_get_reg(struct eth_device *dev, int bank, int ioaddr, int reg) { - SMC_SELECT_BANK( bank ); - return(SMC_inw( reg )); + SMC_SELECT_BANK( dev, bank ); + return(SMC_inw( dev, reg )); } #endif /* 0 */ @@ -1105,7 +937,7 @@ static void smc_dump_mii_stream (byte * bits, int size) . Reads a register from the MII Management serial interface .-------------------------------------------------------------*/ #ifndef CONFIG_SMC91111_EXT_PHY -static word smc_read_phy_register (byte phyreg) +static word smc_read_phy_register (struct eth_device *dev, byte phyreg) { int oldBank; int i; @@ -1168,13 +1000,13 @@ static word smc_read_phy_register (byte phyreg) bits[clk_idx++] = 0; /* Save the current bank */ - oldBank = SMC_inw (BANK_SELECT); + oldBank = SMC_inw (dev, BANK_SELECT); /* Select bank 3 */ - SMC_SELECT_BANK (3); + SMC_SELECT_BANK (dev, 3); /* Get the current MII register value */ - mii_reg = SMC_inw (MII_REG); + mii_reg = SMC_inw (dev, MII_REG); /* Turn off all MII Interface bits */ mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); @@ -1182,23 +1014,23 @@ static word smc_read_phy_register (byte phyreg) /* Clock all 64 cycles */ for (i = 0; i < sizeof bits; ++i) { /* Clock Low - output data */ - SMC_outw (mii_reg | bits[i], MII_REG); + SMC_outw (dev, mii_reg | bits[i], MII_REG); udelay (SMC_PHY_CLOCK_DELAY); /* Clock Hi - input data */ - SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG); + SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG); udelay (SMC_PHY_CLOCK_DELAY); - bits[i] |= SMC_inw (MII_REG) & MII_MDI; + bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI; } /* Return to idle state */ /* Set clock to low, data to low, and output tristated */ - SMC_outw (mii_reg, MII_REG); + SMC_outw (dev, mii_reg, MII_REG); udelay (SMC_PHY_CLOCK_DELAY); /* Restore original bank select */ - SMC_SELECT_BANK (oldBank); + SMC_SELECT_BANK (dev, oldBank); /* Recover input data */ phydata = 0; @@ -1222,7 +1054,8 @@ static word smc_read_phy_register (byte phyreg) /*------------------------------------------------------------ . Writes a register to the MII Management serial interface .-------------------------------------------------------------*/ -static void smc_write_phy_register (byte phyreg, word phydata) +static void smc_write_phy_register (struct eth_device *dev, byte phyreg, + word phydata) { int oldBank; int i; @@ -1288,13 +1121,13 @@ static void smc_write_phy_register (byte phyreg, word phydata) bits[clk_idx++] = 0; /* Save the current bank */ - oldBank = SMC_inw (BANK_SELECT); + oldBank = SMC_inw (dev, BANK_SELECT); /* Select bank 3 */ - SMC_SELECT_BANK (3); + SMC_SELECT_BANK (dev, 3); /* Get the current MII register value */ - mii_reg = SMC_inw (MII_REG); + mii_reg = SMC_inw (dev, MII_REG); /* Turn off all MII Interface bits */ mii_reg &= ~(MII_MDOE | MII_MCLK | MII_MDI | MII_MDO); @@ -1302,23 +1135,23 @@ static void smc_write_phy_register (byte phyreg, word phydata) /* Clock all cycles */ for (i = 0; i < sizeof bits; ++i) { /* Clock Low - output data */ - SMC_outw (mii_reg | bits[i], MII_REG); + SMC_outw (dev, mii_reg | bits[i], MII_REG); udelay (SMC_PHY_CLOCK_DELAY); /* Clock Hi - input data */ - SMC_outw (mii_reg | bits[i] | MII_MCLK, MII_REG); + SMC_outw (dev, mii_reg | bits[i] | MII_MCLK, MII_REG); udelay (SMC_PHY_CLOCK_DELAY); - bits[i] |= SMC_inw (MII_REG) & MII_MDI; + bits[i] |= SMC_inw (dev, MII_REG) & MII_MDI; } /* Return to idle state */ /* Set clock to low, data to low, and output tristated */ - SMC_outw (mii_reg, MII_REG); + SMC_outw (dev, mii_reg, MII_REG); udelay (SMC_PHY_CLOCK_DELAY); /* Restore original bank select */ - SMC_SELECT_BANK (oldBank); + SMC_SELECT_BANK (dev, oldBank); #if (SMC_DEBUG > 2 ) printf ("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n", @@ -1345,7 +1178,7 @@ static void smc_wait_ms(unsigned int ms) . smc_phy_fixed() if the user has requested a certain config. .-------------------------------------------------------------*/ #ifndef CONFIG_SMC91111_EXT_PHY -static void smc_phy_configure () +static void smc_phy_configure (struct eth_device *dev) { int timeout; byte phyaddr; @@ -1361,12 +1194,12 @@ static void smc_phy_configure () phyaddr = SMC_PHY_ADDR; /* Reset the PHY, setting all other bits to zero */ - smc_write_phy_register (PHY_CNTL_REG, PHY_CNTL_RST); + smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_RST); /* Wait for the reset to complete, or time out */ timeout = 6; /* Wait up to 3 seconds */ while (timeout--) { - if (!(smc_read_phy_register (PHY_CNTL_REG) + if (!(smc_read_phy_register (dev, PHY_CNTL_REG) & PHY_CNTL_RST)) { /* reset complete */ break; @@ -1385,14 +1218,14 @@ static void smc_phy_configure () /* Enable PHY Interrupts (for register 18) */ /* Interrupts listed here are disabled */ - smc_write_phy_register (PHY_MASK_REG, 0xffff); + smc_write_phy_register (dev, PHY_MASK_REG, 0xffff); /* Configure the Receive/Phy Control register */ - SMC_SELECT_BANK (0); - SMC_outw (RPC_DEFAULT, RPC_REG); + SMC_SELECT_BANK (dev, 0); + SMC_outw (dev, RPC_DEFAULT, RPC_REG); /* Copy our capabilities from PHY_STAT_REG to PHY_AD_REG */ - my_phy_caps = smc_read_phy_register (PHY_STAT_REG); + my_phy_caps = smc_read_phy_register (dev, PHY_STAT_REG); my_ad_caps = PHY_AD_CSMA; /* I am CSMA capable */ if (my_phy_caps & PHY_STAT_CAP_T4) @@ -1411,18 +1244,18 @@ static void smc_phy_configure () my_ad_caps |= PHY_AD_10_HDX; /* Update our Auto-Neg Advertisement Register */ - smc_write_phy_register (PHY_AD_REG, my_ad_caps); + smc_write_phy_register (dev, PHY_AD_REG, my_ad_caps); /* Read the register back. Without this, it appears that when */ /* auto-negotiation is restarted, sometimes it isn't ready and */ /* the link does not come up. */ - smc_read_phy_register(PHY_AD_REG); + smc_read_phy_register(dev, PHY_AD_REG); PRINTK2 ("%s: phy caps=%x\n", SMC_DEV_NAME, my_phy_caps); PRINTK2 ("%s: phy advertised caps=%x\n", SMC_DEV_NAME, my_ad_caps); /* Restart auto-negotiation process in order to advertise my caps */ - smc_write_phy_register (PHY_CNTL_REG, + smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST); /* Wait for the auto-negotiation to complete. This may take from */ @@ -1431,7 +1264,7 @@ static void smc_phy_configure () timeout = CONFIG_SMC_AUTONEG_TIMEOUT * 2; while (timeout--) { - status = smc_read_phy_register (PHY_STAT_REG); + status = smc_read_phy_register (dev, PHY_STAT_REG); if (status & PHY_STAT_ANEG_ACK) { /* auto-negotiate complete */ break; @@ -1447,7 +1280,7 @@ static void smc_phy_configure () /* Restart auto-negotiation */ printf ("%s: PHY restarting auto-negotiation\n", SMC_DEV_NAME); - smc_write_phy_register (PHY_CNTL_REG, + smc_write_phy_register (dev, PHY_CNTL_REG, PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST | PHY_CNTL_SPEED | @@ -1467,7 +1300,7 @@ static void smc_phy_configure () } /* Re-Configure the Receive/Phy Control register */ - SMC_outw (RPC_DEFAULT, RPC_REG); + SMC_outw (dev, RPC_DEFAULT, RPC_REG); smc_phy_configure_exit: ; @@ -1512,61 +1345,37 @@ static void print_packet( byte * buf, int length ) } #endif -int eth_init(bd_t *bd) { -#ifdef SHARED_RESOURCES - swap_to(ETHERNET); -#endif - return (smc_open(bd)); -} - -void eth_halt() { - smc_close(); -} - -int eth_rx() { - return smc_rcv(); -} - -int eth_send(volatile void *packet, int length) { - return smc_send_packet(packet, length); -} - -int smc_get_ethaddr (bd_t * bd) +int smc91111_initialize(u8 dev_num, int base_addr) { - uchar v_mac[6]; + struct smc91111_priv *priv; + struct eth_device *dev; + int i; - if (!eth_getenv_enetaddr("ethaddr", v_mac)) { - /* get ROM mac value if any */ - if (!get_rom_mac(v_mac)) { - printf("\n*** ERROR: ethaddr is NOT set !!\n"); - return -1; - } - eth_setenv_enetaddr("ethaddr", v_mac); + priv = malloc(sizeof(*priv)); + if (!priv) + return 0; + dev = malloc(sizeof(*dev)); + if (!dev) { + free(priv); + return 0; } - smc_set_mac_addr(v_mac); /* use old function to update smc default */ - PRINTK("Using MAC Address %pM\n", v_mac); - return 0; -} + priv->dev_num = dev_num; + dev->priv = priv; + dev->iobase = base_addr; -int get_rom_mac (uchar *v_rom_mac) -{ -#ifdef HARDCODE_MAC /* used for testing or to supress run time warnings */ - char hw_mac_addr[] = { 0x02, 0x80, 0xad, 0x20, 0x31, 0xb8 }; - - memcpy (v_rom_mac, hw_mac_addr, 6); - return (1); -#else - int i; - int valid_mac = 0; + swap_to(ETHERNET); + SMC_SELECT_BANK(dev, 1); + for (i = 0; i < 6; ++i) + dev->enetaddr[i] = SMC_inb(dev, (ADDR0_REG + i)); + swap_to(FLASH); - SMC_SELECT_BANK (1); - for (i=0; i<6; i++) - { - v_rom_mac[i] = SMC_inb ((ADDR0_REG + i)); - valid_mac |= v_rom_mac[i]; - } + dev->init = smc_init; + dev->halt = smc_halt; + dev->send = smc_send; + dev->recv = smc_rcv; + sprintf(dev->name, "%s-%hu", SMC_DEV_NAME, dev_num); - return (valid_mac ? 1 : 0); -#endif + eth_register(dev); + return 0; } diff --git a/drivers/net/smc91111.h b/drivers/net/smc91111.h index 967adddd74..bb4524106f 100644 --- a/drivers/net/smc91111.h +++ b/drivers/net/smc91111.h @@ -58,6 +58,10 @@ typedef unsigned char byte; typedef unsigned short word; typedef unsigned long int dword; +struct smc91111_priv{ + u8 dev_num; +}; + /* . DEBUGGING LEVELS . @@ -77,32 +81,32 @@ typedef unsigned long int dword; #ifdef CONFIG_PXA250 #ifdef CONFIG_XSENGINE -#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1)))) -#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r<<1)))) -#define SMC_inb(p) ({ \ - unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p<<1)); \ +#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r<<1)))) +#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r<<1)))) +#define SMC_inb(a,p) ({ \ + unsigned int __p = (unsigned int)((a)->iobase + (p<<1)); \ unsigned int __v = *(volatile unsigned short *)((__p) & ~2); \ if (__p & 2) __v >>= 8; \ else __v &= 0xff; \ __v; }) #elif defined(CONFIG_XAENIAX) -#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) -#define SMC_inw(z) ({ \ - unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (z)); \ +#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) +#define SMC_inw(a,z) ({ \ + unsigned int __p = (unsigned int)((a)->iobase + (z)); \ unsigned int __v = *(volatile unsigned int *)((__p) & ~3); \ if (__p & 3) __v >>= 16; \ else __v &= 0xffff; \ __v; }) -#define SMC_inb(p) ({ \ - unsigned int ___v = SMC_inw((p) & ~1); \ +#define SMC_inb(a,p) ({ \ + unsigned int ___v = SMC_inw((a),(p) & ~1); \ if (p & 1) ___v >>= 8; \ else ___v &= 0xff; \ ___v; }) #else -#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) -#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) -#define SMC_inb(p) ({ \ - unsigned int __p = (unsigned int)(SMC_BASE_ADDRESS + (p)); \ +#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) +#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r)))) +#define SMC_inb(a,p) ({ \ + unsigned int __p = (unsigned int)((a)->iobase + (p)); \ unsigned int __v = *(volatile unsigned short *)((__p) & ~1); \ if (__p & 1) __v >>= 8; \ else __v &= 0xff; \ @@ -110,69 +114,69 @@ typedef unsigned long int dword; #endif #ifdef CONFIG_XSENGINE -#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d) -#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r<<1))) = d) +#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d) +#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r<<1))) = d) #elif defined (CONFIG_XAENIAX) -#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d) -#define SMC_outw(d,p) ({ \ - dword __dwo = SMC_inl((p) & ~3); \ +#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) +#define SMC_outw(a,d,p) ({ \ + dword __dwo = SMC_inl((a),(p) & ~3); \ dword __dwn = (word)(d); \ __dwo &= ((p) & 3) ? 0x0000ffff : 0xffff0000; \ __dwo |= ((p) & 3) ? __dwn << 16 : __dwn; \ - SMC_outl(__dwo, (p) & ~3); \ + SMC_outl((a), __dwo, (p) & ~3); \ }) #else -#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d) -#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d) +#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) +#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d) #endif -#define SMC_outb(d,r) ({ word __d = (byte)(d); \ - word __w = SMC_inw((r)&~1); \ +#define SMC_outb(a,d,r) ({ word __d = (byte)(d); \ + word __w = SMC_inw((a),(r)&~1); \ __w &= ((r)&1) ? 0x00FF : 0xFF00; \ __w |= ((r)&1) ? __d<<8 : __d; \ - SMC_outw(__w,(r)&~1); \ + SMC_outw((a),__w,(r)&~1); \ }) -#define SMC_outsl(r,b,l) ({ int __i; \ +#define SMC_outsl(a,r,b,l) ({ int __i; \ dword *__b2; \ __b2 = (dword *) b; \ for (__i = 0; __i < l; __i++) { \ - SMC_outl( *(__b2 + __i), r); \ + SMC_outl((a), *(__b2 + __i), r); \ } \ }) -#define SMC_outsw(r,b,l) ({ int __i; \ +#define SMC_outsw(a,r,b,l) ({ int __i; \ word *__b2; \ __b2 = (word *) b; \ for (__i = 0; __i < l; __i++) { \ - SMC_outw( *(__b2 + __i), r); \ + SMC_outw((a), *(__b2 + __i), r); \ } \ }) -#define SMC_insl(r,b,l) ({ int __i ; \ +#define SMC_insl(a,r,b,l) ({ int __i ; \ dword *__b2; \ __b2 = (dword *) b; \ for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inl(r); \ - SMC_inl(0); \ + *(__b2 + __i) = SMC_inl((a),(r)); \ + SMC_inl((a),0); \ }; \ }) -#define SMC_insw(r,b,l) ({ int __i ; \ +#define SMC_insw(a,r,b,l) ({ int __i ; \ word *__b2; \ __b2 = (word *) b; \ for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inw(r); \ - SMC_inw(0); \ + *(__b2 + __i) = SMC_inw((a),(r)); \ + SMC_inw((a),0); \ }; \ }) -#define SMC_insb(r,b,l) ({ int __i ; \ +#define SMC_insb(a,r,b,l) ({ int __i ; \ byte *__b2; \ __b2 = (byte *) b; \ for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inb(r); \ - SMC_inb(0); \ + *(__b2 + __i) = SMC_inb((a),(r)); \ + SMC_inb((a),0); \ }; \ }) @@ -187,61 +191,61 @@ typedef unsigned long int dword; ((0x00FF0000UL & _x) >> 8) | \ (_x >> 24)); }) -#define SMC_inl(r) (SMC_LEON_SWAP32((*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0))))) -#define SMC_inl_nosw(r) ((*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0)))) -#define SMC_inw(r) (SMC_LEON_SWAP16((*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0))))) -#define SMC_inw_nosw(r) ((*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0)))) -#define SMC_inb(p) ({ \ - word ___v = SMC_inw((p) & ~1); \ +#define SMC_inl(a,r) (SMC_LEON_SWAP32((*(volatile dword *)((a)->iobase+((r)<<0))))) +#define SMC_inl_nosw(a,r) ((*(volatile dword *)((a)->iobase+((r)<<0)))) +#define SMC_inw(a,r) (SMC_LEON_SWAP16((*(volatile word *)((a)->iobase+((r)<<0))))) +#define SMC_inw_nosw(a,r) ((*(volatile word *)((a)->iobase+((r)<<0)))) +#define SMC_inb(a,p) ({ \ + word ___v = SMC_inw((a),(p) & ~1); \ if ((p) & 1) ___v >>= 8; \ else ___v &= 0xff; \ ___v; }) -#define SMC_outl(d,r) (*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0))=SMC_LEON_SWAP32(d)) -#define SMC_outl_nosw(d,r) (*(volatile dword *)(SMC_BASE_ADDRESS+((r)<<0))=(d)) -#define SMC_outw(d,r) (*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0))=SMC_LEON_SWAP16(d)) -#define SMC_outw_nosw(d,r) (*(volatile word *)(SMC_BASE_ADDRESS+((r)<<0))=(d)) -#define SMC_outb(d,r) do{ word __d = (byte)(d); \ - word __w = SMC_inw((r)&~1); \ +#define SMC_outl(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP32(d)) +#define SMC_outl_nosw(a,d,r) (*(volatile dword *)((a)->iobase+((r)<<0))=(d)) +#define SMC_outw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=SMC_LEON_SWAP16(d)) +#define SMC_outw_nosw(a,d,r) (*(volatile word *)((a)->iobase+((r)<<0))=(d)) +#define SMC_outb(a,d,r) do{ word __d = (byte)(d); \ + word __w = SMC_inw((a),(r)&~1); \ __w &= ((r)&1) ? 0x00FF : 0xFF00; \ __w |= ((r)&1) ? __d<<8 : __d; \ - SMC_outw(__w,(r)&~1); \ + SMC_outw((a),__w,(r)&~1); \ }while(0) -#define SMC_outsl(r,b,l) do{ int __i; \ +#define SMC_outsl(a,r,b,l) do{ int __i; \ dword *__b2; \ __b2 = (dword *) b; \ for (__i = 0; __i < l; __i++) { \ - SMC_outl_nosw( *(__b2 + __i), r); \ + SMC_outl_nosw((a), *(__b2 + __i), r); \ } \ }while(0) -#define SMC_outsw(r,b,l) do{ int __i; \ +#define SMC_outsw(a,r,b,l) do{ int __i; \ word *__b2; \ __b2 = (word *) b; \ for (__i = 0; __i < l; __i++) { \ - SMC_outw_nosw( *(__b2 + __i), r); \ + SMC_outw_nosw((a), *(__b2 + __i), r); \ } \ }while(0) -#define SMC_insl(r,b,l) do{ int __i ; \ +#define SMC_insl(a,r,b,l) do{ int __i ; \ dword *__b2; \ __b2 = (dword *) b; \ for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inl_nosw(r); \ + *(__b2 + __i) = SMC_inl_nosw((a),(r)); \ }; \ }while(0) -#define SMC_insw(r,b,l) do{ int __i ; \ +#define SMC_insw(a,r,b,l) do{ int __i ; \ word *__b2; \ __b2 = (word *) b; \ for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inw_nosw(r); \ + *(__b2 + __i) = SMC_inw_nosw((a),(r)); \ }; \ }while(0) -#define SMC_insb(r,b,l) do{ int __i ; \ +#define SMC_insb(a,r,b,l) do{ int __i ; \ byte *__b2; \ __b2 = (byte *) b; \ for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inb(r); \ + *(__b2 + __i) = SMC_inb((a),(r)); \ }; \ }while(0) @@ -253,48 +257,48 @@ typedef unsigned long int dword; */ #ifdef CONFIG_ADNPESC1 -#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1)))) +#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+((r)<<1)))) #elif CONFIG_BLACKFIN -#define SMC_inw(r) ({ word __v = (*((volatile word *)(SMC_BASE_ADDRESS+(r)))); SSYNC(); __v;}) +#define SMC_inw(a,r) ({ word __v = (*((volatile word *)((a)->iobase+(r)))); SSYNC(); __v;}) #else -#define SMC_inw(r) (*((volatile word *)(SMC_BASE_ADDRESS+(r)))) +#define SMC_inw(a,r) (*((volatile word *)((a)->iobase+(r)))) #endif -#define SMC_inb(r) (((r)&1) ? SMC_inw((r)&~1)>>8 : SMC_inw(r)&0xFF) +#define SMC_inb(a,r) (((r)&1) ? SMC_inw((a),(r)&~1)>>8 : SMC_inw((a),(r)&0xFF)) #ifdef CONFIG_ADNPESC1 -#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+((r)<<1))) = d) +#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+((r)<<1))) = d) #elif CONFIG_BLACKFIN -#define SMC_outw(d,r) {(*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d); SSYNC();} +#define SMC_outw(a,d,r) {(*((volatile word *)((a)->iobase+(r))) = d); SSYNC();} #else -#define SMC_outw(d,r) (*((volatile word *)(SMC_BASE_ADDRESS+(r))) = d) +#define SMC_outw(a,d,r) (*((volatile word *)((a)->iobase+(r))) = d) #endif -#define SMC_outb(d,r) ({ word __d = (byte)(d); \ - word __w = SMC_inw((r)&~1); \ +#define SMC_outb(a,d,r) ({ word __d = (byte)(d); \ + word __w = SMC_inw((a),(r)&~1); \ __w &= ((r)&1) ? 0x00FF : 0xFF00; \ __w |= ((r)&1) ? __d<<8 : __d; \ - SMC_outw(__w,(r)&~1); \ + SMC_outw((a),__w,(r)&~1); \ }) #if 0 -#define SMC_outsw(r,b,l) outsw(SMC_BASE_ADDRESS+(r), (b), (l)) +#define SMC_outsw(a,r,b,l) outsw((a)->iobase+(r), (b), (l)) #else -#define SMC_outsw(r,b,l) ({ int __i; \ +#define SMC_outsw(a,r,b,l) ({ int __i; \ word *__b2; \ __b2 = (word *) b; \ for (__i = 0; __i < l; __i++) { \ - SMC_outw( *(__b2 + __i), r); \ + SMC_outw((a), *(__b2 + __i), r); \ } \ }) #endif #if 0 -#define SMC_insw(r,b,l) insw(SMC_BASE_ADDRESS+(r), (b), (l)) +#define SMC_insw(a,r,b,l) insw((a)->iobase+(r), (b), (l)) #else -#define SMC_insw(r,b,l) ({ int __i ; \ +#define SMC_insw(a,r,b,l) ({ int __i ; \ word *__b2; \ __b2 = (word *) b; \ for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inw(r); \ - SMC_inw(0); \ + *(__b2 + __i) = SMC_inw((a),(r)); \ + SMC_inw((a),0); \ }; \ }) #endif @@ -304,30 +308,30 @@ typedef unsigned long int dword; #if defined(CONFIG_SMC_USE_32_BIT) #ifdef CONFIG_XSENGINE -#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1)))) +#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r<<1)))) #else -#define SMC_inl(r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r)))) +#define SMC_inl(a,r) (*((volatile dword *)((a)->iobase+(r)))) #endif -#define SMC_insl(r,b,l) ({ int __i ; \ +#define SMC_insl(a,r,b,l) ({ int __i ; \ dword *__b2; \ __b2 = (dword *) b; \ for (__i = 0; __i < l; __i++) { \ - *(__b2 + __i) = SMC_inl(r); \ - SMC_inl(0); \ + *(__b2 + __i) = SMC_inl((a),(r)); \ + SMC_inl((a),0); \ }; \ }) #ifdef CONFIG_XSENGINE -#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r<<1))) = d) +#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r<<1))) = d) #else -#define SMC_outl(d,r) (*((volatile dword *)(SMC_BASE_ADDRESS+(r))) = d) +#define SMC_outl(a,d,r) (*((volatile dword *)((a)->iobase+(r))) = d) #endif -#define SMC_outsl(r,b,l) ({ int __i; \ +#define SMC_outsl(a,r,b,l) ({ int __i; \ dword *__b2; \ __b2 = (dword *) b; \ for (__i = 0; __i < l; __i++) { \ - SMC_outl( *(__b2 + __i), r); \ + SMC_outl((a), *(__b2 + __i), r); \ } \ }) @@ -752,25 +756,25 @@ enum { /* select a register bank, 0 to 3 */ -#define SMC_SELECT_BANK(x) { SMC_outw( x, BANK_SELECT ); } +#define SMC_SELECT_BANK(a,x) { SMC_outw((a), (x), BANK_SELECT ); } /* this enables an interrupt in the interrupt mask register */ -#define SMC_ENABLE_INT(x) {\ +#define SMC_ENABLE_INT(a,x) {\ unsigned char mask;\ - SMC_SELECT_BANK(2);\ - mask = SMC_inb( IM_REG );\ + SMC_SELECT_BANK((a),2);\ + mask = SMC_inb((a), IM_REG );\ mask |= (x);\ - SMC_outb( mask, IM_REG ); \ + SMC_outb( (a), mask, IM_REG ); \ } /* this disables an interrupt from the interrupt mask register */ -#define SMC_DISABLE_INT(x) {\ +#define SMC_DISABLE_INT(a,x) {\ unsigned char mask;\ SMC_SELECT_BANK(2);\ - mask = SMC_inb( IM_REG );\ + mask = SMC_inb( (a), IM_REG );\ mask &= ~(x);\ - SMC_outb( mask, IM_REG ); \ + SMC_outb( (a), mask, IM_REG ); \ } /*---------------------------------------------------------------------- diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index b106ec9732..48e08c06c9 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -249,6 +249,12 @@ int smc911x_initialize(u8 dev_num, int base_addr) dev->iobase = base_addr; + /* Try to detect chip. Will fail if not present. */ + if (smc911x_detect_chip(dev)) { + free(dev); + return 0; + } + addrh = smc911x_get_mac_csr(dev, ADDRH); addrl = smc911x_get_mac_csr(dev, ADDRL); dev->enetaddr[0] = addrl; diff --git a/drivers/net/tsec.c b/drivers/net/tsec.c index 5c3d261ecd..3f74118dbe 100644 --- a/drivers/net/tsec.c +++ b/drivers/net/tsec.c @@ -35,8 +35,6 @@ typedef volatile struct rtxbd { #define MAXCONTROLLERS (8) -static int relocated = 0; - static struct tsec_private *privlist[MAXCONTROLLERS]; static int num_tsecs = 0; @@ -59,7 +57,6 @@ uint read_phy_reg(struct tsec_private *priv, uint regnum); struct phy_info *get_phy_info(struct eth_device *dev); void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd); static void adjust_link(struct eth_device *dev); -static void relocate_cmds(void); #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ && !defined(BITBANGMII) static int tsec_miiphy_write(char *devname, unsigned char addr, @@ -321,9 +318,6 @@ static int init_phy(struct eth_device *dev) asm("sync"); while (priv->phyregs->miimind & MIIMIND_BUSY) ; - if (0 == relocated) - relocate_cmds(); - /* Get the cmd structure corresponding to the attached * PHY */ curphy = get_phy_info(dev); @@ -1800,49 +1794,6 @@ void phy_run_commands(struct tsec_private *priv, struct phy_cmd *cmd) } } -/* Relocate the function pointers in the phy cmd lists */ -static void relocate_cmds(void) -{ - struct phy_cmd **cmdlistptr; - struct phy_cmd *cmd; - int i, j, k; - - for (i = 0; phy_info[i]; i++) { - /* First thing's first: relocate the pointers to the - * PHY command structures (the structs were done) */ - phy_info[i] = (struct phy_info *)((uint) phy_info[i] - + gd->reloc_off); - phy_info[i]->name += gd->reloc_off; - phy_info[i]->config = - (struct phy_cmd *)((uint) phy_info[i]->config - + gd->reloc_off); - phy_info[i]->startup = - (struct phy_cmd *)((uint) phy_info[i]->startup - + gd->reloc_off); - phy_info[i]->shutdown = - (struct phy_cmd *)((uint) phy_info[i]->shutdown - + gd->reloc_off); - - cmdlistptr = &phy_info[i]->config; - j = 0; - for (; cmdlistptr <= &phy_info[i]->shutdown; cmdlistptr++) { - k = 0; - for (cmd = *cmdlistptr; - cmd->mii_reg != miim_end; - cmd++) { - /* Only relocate non-NULL pointers */ - if (cmd->funct) - cmd->funct += gd->reloc_off; - - k++; - } - j++; - } - } - - relocated = 1; -} - #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) \ && !defined(BITBANGMII) diff --git a/drivers/serial/serial_s5pc1xx.c b/drivers/serial/serial_s5pc1xx.c index 64c1dcc8ff..68c06a9190 100644 --- a/drivers/serial/serial_s5pc1xx.c +++ b/drivers/serial/serial_s5pc1xx.c @@ -74,7 +74,7 @@ void serial_setbrg_dev(const int dev_index) val = pclk / baudrate; writel(val / 16 - 1, &uart->ubrdiv); - writel(udivslot[val % 16], &uart->udivslot); + writew(udivslot[val % 16], &uart->udivslot); } /* diff --git a/examples/standalone/smc91111_eeprom.c b/examples/standalone/smc91111_eeprom.c index 39e530648d..89afc871fa 100644 --- a/examples/standalone/smc91111_eeprom.c +++ b/examples/standalone/smc91111_eeprom.c @@ -29,9 +29,11 @@ #include #include +/* the smc91111.h gets base addr through eth_device' iobase */ +struct eth_device { unsigned long iobase; }; #include "../drivers/net/smc91111.h" -#ifdef CONFIG_DRIVER_SMC91111 +#ifdef CONFIG_SMC91111 #ifndef SMC91111_EEPROM_INIT # define SMC91111_EEPROM_INIT() @@ -42,19 +44,23 @@ #define MAC 0x2 #define UNKNOWN 0x4 -void dump_reg (void); -void dump_eeprom (void); -int write_eeprom_reg (int, int); -void copy_from_eeprom (void); -void print_MAC (void); -int read_eeprom_reg (int); -void print_macaddr (void); +void dump_reg (struct eth_device *dev); +void dump_eeprom (struct eth_device *dev); +int write_eeprom_reg (struct eth_device *dev, int value, int reg); +void copy_from_eeprom (struct eth_device *dev); +void print_MAC (struct eth_device *dev); +int read_eeprom_reg (struct eth_device *dev, int reg); +void print_macaddr (struct eth_device *dev); int smc91111_eeprom (int argc, char *argv[]) { int c, i, j, done, line, reg, value, start, what; char input[50]; + struct eth_device dev = { + .iobase = CONFIG_SMC91111_BASE + }; + /* Print the ABI version */ app_startup (argv); if (XF_VERSION != (int) get_version ()) { @@ -67,7 +73,7 @@ int smc91111_eeprom (int argc, char *argv[]) SMC91111_EEPROM_INIT(); - if ((SMC_inw (BANK_SELECT) & 0xFF00) != 0x3300) { + if ((SMC_inw (&dev, BANK_SELECT) & 0xFF00) != 0x3300) { printf ("Can't find SMSC91111\n"); return (0); } @@ -211,12 +217,12 @@ int smc91111_eeprom (int argc, char *argv[]) switch (what) { case 1: printf ("Writing EEPROM register %02x with %04x\n", reg, value); - write_eeprom_reg (value, reg); + write_eeprom_reg (&dev, value, reg); break; case 2: printf ("Writing MAC register bank %i, reg %02x with %04x\n", reg >> 4, reg & 0xE, value); - SMC_SELECT_BANK (reg >> 4); - SMC_outw (value, reg & 0xE); + SMC_SELECT_BANK (&dev, reg >> 4); + SMC_outw (&dev, value, reg & 0xE); break; default: printf ("Wrong\n"); @@ -224,16 +230,16 @@ int smc91111_eeprom (int argc, char *argv[]) } break; case ('D'): - dump_eeprom (); + dump_eeprom (&dev); break; case ('M'): - dump_reg (); + dump_reg (&dev); break; case ('C'): - copy_from_eeprom (); + copy_from_eeprom (&dev); break; case ('P'): - print_macaddr (); + print_macaddr (&dev); break; default: break; @@ -244,15 +250,15 @@ int smc91111_eeprom (int argc, char *argv[]) return (0); } -void copy_from_eeprom (void) +void copy_from_eeprom (struct eth_device *dev) { int i; - SMC_SELECT_BANK (1); - SMC_outw ((SMC_inw (CTL_REG) & !CTL_EEPROM_SELECT) | CTL_RELOAD, - CTL_REG); + SMC_SELECT_BANK (dev, 1); + SMC_outw (dev, (SMC_inw (dev, CTL_REG) & !CTL_EEPROM_SELECT) | + CTL_RELOAD, CTL_REG); i = 100; - while ((SMC_inw (CTL_REG) & CTL_RELOAD) && --i) + while ((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --i) udelay (100); if (i == 0) { printf ("Timeout Refreshing EEPROM registers\n"); @@ -262,21 +268,21 @@ void copy_from_eeprom (void) } -void print_macaddr (void) +void print_macaddr (struct eth_device *dev) { int i, j, k, mac[6]; printf ("Current MAC Address in SMSC91111 "); - SMC_SELECT_BANK (1); + SMC_SELECT_BANK (dev, 1); for (i = 0; i < 5; i++) { - printf ("%02x:", SMC_inb (ADDR0_REG + i)); + printf ("%02x:", SMC_inb (dev, ADDR0_REG + i)); } - printf ("%02x\n", SMC_inb (ADDR0_REG + 5)); + printf ("%02x\n", SMC_inb (dev, ADDR0_REG + 5)); i = 0; for (j = 0x20; j < 0x23; j++) { - k = read_eeprom_reg (j); + k = read_eeprom_reg (dev, j); mac[i] = k & 0xFF; i++; mac[i] = k >> 8; @@ -289,7 +295,7 @@ void print_macaddr (void) printf ("%02x\n", mac[5]); } -void dump_eeprom (void) +void dump_eeprom (struct eth_device *dev) { int j, k; @@ -307,7 +313,8 @@ void dump_eeprom (void) if ((k == 2) || (k == 3)) printf (" "); for (j = 0; j < 0x20; j += 4) { - printf ("%02x:%04x ", j + k, read_eeprom_reg (j + k)); + printf ("%02x:%04x ", j + k, + read_eeprom_reg (dev, j + k)); } printf ("\n"); } @@ -315,46 +322,47 @@ void dump_eeprom (void) for (j = 0x20; j < 0x40; j++) { if ((j & 0x07) == 0) printf ("\n"); - printf ("%02x:%04x ", j, read_eeprom_reg (j)); + printf ("%02x:%04x ", j, read_eeprom_reg (dev, j)); } printf ("\n"); } -int read_eeprom_reg (int reg) +int read_eeprom_reg (struct eth_device *dev, int reg) { int timeout; - SMC_SELECT_BANK (2); - SMC_outw (reg, PTR_REG); + SMC_SELECT_BANK (dev, 2); + SMC_outw (dev, reg, PTR_REG); - SMC_SELECT_BANK (1); - SMC_outw (SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_RELOAD, - CTL_REG); + SMC_SELECT_BANK (dev, 1); + SMC_outw (dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | + CTL_RELOAD, CTL_REG); timeout = 100; - while ((SMC_inw (CTL_REG) & CTL_RELOAD) && --timeout) + while ((SMC_inw (dev, CTL_REG) & CTL_RELOAD) && --timeout) udelay (100); if (timeout == 0) { printf ("Timeout Reading EEPROM register %02x\n", reg); return 0; } - return SMC_inw (GP_REG); + return SMC_inw (dev, GP_REG); } -int write_eeprom_reg (int value, int reg) +int write_eeprom_reg (struct eth_device *dev, int value, int reg) { int timeout; - SMC_SELECT_BANK (2); - SMC_outw (reg, PTR_REG); + SMC_SELECT_BANK (dev, 2); + SMC_outw (dev, reg, PTR_REG); - SMC_SELECT_BANK (1); - SMC_outw (value, GP_REG); - SMC_outw (SMC_inw (CTL_REG) | CTL_EEPROM_SELECT | CTL_STORE, CTL_REG); + SMC_SELECT_BANK (dev, 1); + SMC_outw (dev, value, GP_REG); + SMC_outw (dev, SMC_inw (dev, CTL_REG) | CTL_EEPROM_SELECT | + CTL_STORE, CTL_REG); timeout = 100; - while ((SMC_inw (CTL_REG) & CTL_STORE) && --timeout) + while ((SMC_inw (dev, CTL_REG) & CTL_STORE) && --timeout) udelay (100); if (timeout == 0) { printf ("Timeout Writing EEPROM register %02x\n", reg); @@ -365,7 +373,7 @@ int write_eeprom_reg (int value, int reg) } -void dump_reg (void) +void dump_reg (struct eth_device *dev) { int i, j; @@ -377,8 +385,8 @@ void dump_reg (void) for (i = 0; i < 0xF; i += 2) { printf ("%02x ", i); for (j = 0; j < 4; j++) { - SMC_SELECT_BANK (j); - printf ("%04x ", SMC_inw (i)); + SMC_SELECT_BANK (dev, j); + printf ("%04x ", SMC_inw (dev, i)); } printf ("\n"); } diff --git a/fs/ubifs/ubifs.c b/fs/ubifs/ubifs.c index 286739c368..82f1c547da 100644 --- a/fs/ubifs/ubifs.c +++ b/fs/ubifs/ubifs.c @@ -124,9 +124,13 @@ int ubifs_decompress(const void *in_buf, int in_len, void *out_buf, static int __init compr_init(struct ubifs_compressor *compr) { ubifs_compressors[compr->compr_type] = compr; + +#ifndef CONFIG_RELOC_FIXUP_WORKS ubifs_compressors[compr->compr_type]->name += gd->reloc_off; ubifs_compressors[compr->compr_type]->capi_name += gd->reloc_off; ubifs_compressors[compr->compr_type]->decompress += gd->reloc_off; +#endif + return 0; } diff --git a/include/4xx_i2c.h b/include/4xx_i2c.h index f0e772c050..070657fbb6 100644 --- a/include/4xx_i2c.h +++ b/include/4xx_i2c.h @@ -63,7 +63,7 @@ #define IIC_EXTSTS (I2C_REGISTERS_BASE_ADDRESS+IICEXTSTS) #define IIC_LSADR (I2C_REGISTERS_BASE_ADDRESS+IICLSADR) #define IIC_HSADR (I2C_REGISTERS_BASE_ADDRESS+IICHSADR) -#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IICCLKDIV) +#define IIC_CLKDIV (I2C_REGISTERS_BASE_ADDRESS+IIC0_CLKDIV) #define IIC_INTRMSK (I2C_REGISTERS_BASE_ADDRESS+IICINTRMSK) #define IIC_XFRCNT (I2C_REGISTERS_BASE_ADDRESS+IICXFRCNT) #define IIC_XTCNTLSS (I2C_REGISTERS_BASE_ADDRESS+IICXTCNTLSS) diff --git a/include/ACEX1K.h b/include/ACEX1K.h index 354e0f0e47..ae201647be 100644 --- a/include/ACEX1K.h +++ b/include/ACEX1K.h @@ -33,12 +33,10 @@ extern int ACEX1K_load( Altera_desc *desc, void *image, size_t size ); extern int ACEX1K_dump( Altera_desc *desc, void *buf, size_t bsize ); extern int ACEX1K_info( Altera_desc *desc ); -extern int ACEX1K_reloc( Altera_desc *desc, ulong reloc_off ); extern int CYC2_load( Altera_desc *desc, void *image, size_t size ); extern int CYC2_dump( Altera_desc *desc, void *buf, size_t bsize ); extern int CYC2_info( Altera_desc *desc ); -extern int CYC2_reloc( Altera_desc *desc, ulong reloc_off ); /* Slave Serial Implementation function table */ typedef struct { @@ -50,7 +48,6 @@ typedef struct { Altera_data_fn data; Altera_abort_fn abort; Altera_post_fn post; - int relocated; } Altera_ACEX1K_Passive_Serial_fns; /* Slave Serial Implementation function table */ @@ -62,7 +59,6 @@ typedef struct { Altera_write_fn write; Altera_abort_fn abort; Altera_post_fn post; - int relocated; } Altera_CYC2_Passive_Serial_fns; /* Device Image Sizes diff --git a/include/altera.h b/include/altera.h index 44a1ee5635..bc21ddfff9 100644 --- a/include/altera.h +++ b/include/altera.h @@ -79,7 +79,6 @@ typedef struct { /* typedef Altera_desc */ extern int altera_load( Altera_desc *desc, void *image, size_t size ); extern int altera_dump( Altera_desc *desc, void *buf, size_t bsize ); extern int altera_info( Altera_desc *desc ); -extern int altera_reloc( Altera_desc *desc, ulong reloc_offset ); /* Board specific implementation specific function types *********************************************************************/ diff --git a/include/asm-arm/arch-davinci/hardware.h b/include/asm-arm/arch-davinci/hardware.h index ac32510a30..acf12ea7a2 100644 --- a/include/asm-arm/arch-davinci/hardware.h +++ b/include/asm-arm/arch-davinci/hardware.h @@ -71,10 +71,12 @@ typedef volatile unsigned int * dv_reg_p; #define DAVINCI_SPI_BASE (0x01c66800) #define DAVINCI_GPIO_BASE (0x01c67000) #define DAVINCI_VPSS_REGS_BASE (0x01c70000) +#if !defined(CONFIG_SOC_DM646X) #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE (0x02000000) #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE (0x04000000) #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE (0x06000000) #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE (0x08000000) +#endif #define DAVINCI_DDR_BASE (0x80000000) #ifdef CONFIG_SOC_DM644X diff --git a/include/asm-arm/arch-omap3/sys_proto.h b/include/asm-arm/arch-omap3/sys_proto.h index 2246f801e5..34bd515b05 100644 --- a/include/asm-arm/arch-omap3/sys_proto.h +++ b/include/asm-arm/arch-omap3/sys_proto.h @@ -34,6 +34,8 @@ void memif_init(void); void sdrc_init(void); void do_sdrc_init(u32, u32); void gpmc_init(void); +void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, + u32 size); void watchdog_init(void); void set_muxconf_regs(void); diff --git a/include/asm-arm/arch-s5pc1xx/clock.h b/include/asm-arm/arch-s5pc1xx/clock.h index 0cad9225bd..7b4eb89905 100644 --- a/include/asm-arm/arch-s5pc1xx/clock.h +++ b/include/asm-arm/arch-s5pc1xx/clock.h @@ -25,69 +25,69 @@ #ifndef __ASSEMBLY__ struct s5pc100_clock { - unsigned long apll_lock; - unsigned long mpll_lock; - unsigned long epll_lock; - unsigned long hpll_lock; + unsigned int apll_lock; + unsigned int mpll_lock; + unsigned int epll_lock; + unsigned int hpll_lock; unsigned char res1[0xf0]; - unsigned long apll_con; - unsigned long mpll_con; - unsigned long epll_con; - unsigned long hpll_con; + unsigned int apll_con; + unsigned int mpll_con; + unsigned int epll_con; + unsigned int hpll_con; unsigned char res2[0xf0]; - unsigned long src0; - unsigned long src1; - unsigned long src2; - unsigned long src3; + unsigned int src0; + unsigned int src1; + unsigned int src2; + unsigned int src3; unsigned char res3[0xf0]; - unsigned long div0; - unsigned long div1; - unsigned long div2; - unsigned long div3; - unsigned long div4; + unsigned int div0; + unsigned int div1; + unsigned int div2; + unsigned int div3; + unsigned int div4; unsigned char res4[0x1ec]; - unsigned long gate_d00; - unsigned long gate_d01; - unsigned long gate_d02; + unsigned int gate_d00; + unsigned int gate_d01; + unsigned int gate_d02; unsigned char res5[0x54]; - unsigned long gate_sclk0; - unsigned long gate_sclk1; + unsigned int gate_sclk0; + unsigned int gate_sclk1; }; struct s5pc110_clock { - unsigned long apll_lock; + unsigned int apll_lock; unsigned char res1[0x4]; - unsigned long mpll_lock; + unsigned int mpll_lock; unsigned char res2[0x4]; - unsigned long epll_lock; + unsigned int epll_lock; unsigned char res3[0xc]; - unsigned long vpll_lock; + unsigned int vpll_lock; unsigned char res4[0xdc]; - unsigned long apll_con; + unsigned int apll_con; unsigned char res5[0x4]; - unsigned long mpll_con; + unsigned int mpll_con; unsigned char res6[0x4]; - unsigned long epll_con; + unsigned int epll_con; unsigned char res7[0xc]; - unsigned long vpll_con; + unsigned int vpll_con; unsigned char res8[0xdc]; - unsigned long src0; - unsigned long src1; - unsigned long src2; - unsigned long src3; + unsigned int src0; + unsigned int src1; + unsigned int src2; + unsigned int src3; unsigned char res9[0xf0]; - unsigned long div0; - unsigned long div1; - unsigned long div2; - unsigned long div3; - unsigned long div4; + unsigned int div0; + unsigned int div1; + unsigned int div2; + unsigned int div3; + unsigned int div4; unsigned char res10[0x1ec]; - unsigned long gate_d00; - unsigned long gate_d01; - unsigned long gate_d02; + unsigned int gate_d00; + unsigned int gate_d01; + unsigned int gate_d02; unsigned char res11[0x54]; - unsigned long gate_sclk0; - unsigned long gate_sclk1; + unsigned int gate_sclk0; + unsigned int gate_sclk1; }; #endif diff --git a/include/asm-arm/arch-s5pc1xx/gpio.h b/include/asm-arm/arch-s5pc1xx/gpio.h index 0010405315..afbc7ea5ae 100644 --- a/include/asm-arm/arch-s5pc1xx/gpio.h +++ b/include/asm-arm/arch-s5pc1xx/gpio.h @@ -23,12 +23,12 @@ #ifndef __ASSEMBLY__ struct s5pc1xx_gpio_bank { - unsigned long con; - unsigned long dat; - unsigned long pull; - unsigned long drv; - unsigned long pdn_con; - unsigned long pdn_pull; + unsigned int con; + unsigned int dat; + unsigned int pull; + unsigned int drv; + unsigned int pdn_con; + unsigned int pdn_pull; unsigned char res1[8]; }; diff --git a/include/asm-arm/arch-s5pc1xx/pwm.h b/include/asm-arm/arch-s5pc1xx/pwm.h index 53c23cd146..e02a8d8fb3 100644 --- a/include/asm-arm/arch-s5pc1xx/pwm.h +++ b/include/asm-arm/arch-s5pc1xx/pwm.h @@ -35,24 +35,24 @@ #ifndef __ASSEMBLY__ struct s5pc1xx_timer { - unsigned long tcfg0; - unsigned long tcfg1; - unsigned long tcon; - unsigned long tcntb0; - unsigned long tcmpb0; - unsigned long tcnto0; - unsigned long tcntb1; - unsigned long tcmpb1; - unsigned long tcnto1; - unsigned long tcntb2; - unsigned long tcmpb2; - unsigned long tcnto2; - unsigned long tcntb3; - unsigned long res1; - unsigned long tcnto3; - unsigned long tcntb4; - unsigned long tcnto4; - unsigned long tintcstat; + unsigned int tcfg0; + unsigned int tcfg1; + unsigned int tcon; + unsigned int tcntb0; + unsigned int tcmpb0; + unsigned int tcnto0; + unsigned int tcntb1; + unsigned int tcmpb1; + unsigned int tcnto1; + unsigned int tcntb2; + unsigned int tcmpb2; + unsigned int tcnto2; + unsigned int tcntb3; + unsigned int res1; + unsigned int tcnto3; + unsigned int tcntb4; + unsigned int tcnto4; + unsigned int tintcstat; }; #endif /* __ASSEMBLY__ */ diff --git a/include/asm-arm/arch-s5pc1xx/uart.h b/include/asm-arm/arch-s5pc1xx/uart.h index bd7d6b2dda..140dbdc45f 100644 --- a/include/asm-arm/arch-s5pc1xx/uart.h +++ b/include/asm-arm/arch-s5pc1xx/uart.h @@ -25,19 +25,19 @@ #ifndef __ASSEMBLY__ struct s5pc1xx_uart { - unsigned long ulcon; - unsigned long ucon; - unsigned long ufcon; - unsigned long umcon; - unsigned long utrstat; - unsigned long uerstat; - unsigned long ufstat; - unsigned long umstat; + unsigned int ulcon; + unsigned int ucon; + unsigned int ufcon; + unsigned int umcon; + unsigned int utrstat; + unsigned int uerstat; + unsigned int ufstat; + unsigned int umstat; unsigned char utxh; unsigned char res1[3]; unsigned char urxh; unsigned char res2[3]; - unsigned long ubrdiv; + unsigned int ubrdiv; unsigned short udivslot; unsigned char res3[2]; unsigned char res4[0x3d0]; diff --git a/include/asm-arm/config.h b/include/asm-arm/config.h index 049c44eaf8..b76fd8eb48 100644 --- a/include/asm-arm/config.h +++ b/include/asm-arm/config.h @@ -21,4 +21,7 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +/* Relocation to SDRAM works on all ARM boards */ +#define CONFIG_RELOC_FIXUP_WORKS + #endif diff --git a/include/asm-arm/global_data.h b/include/asm-arm/global_data.h index 5c56ce3282..8115a24b78 100644 --- a/include/asm-arm/global_data.h +++ b/include/asm-arm/global_data.h @@ -38,7 +38,6 @@ typedef struct global_data { unsigned long flags; unsigned long baudrate; unsigned long have_console; /* serial_init() was called */ - unsigned long reloc_off; /* Relocation Offset */ unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid? */ unsigned long fb_base; /* base address of frame buffer */ diff --git a/include/asm-microblaze/config.h b/include/asm-microblaze/config.h index 049c44eaf8..8a9064b3c8 100644 --- a/include/asm-microblaze/config.h +++ b/include/asm-microblaze/config.h @@ -21,4 +21,7 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +/* Relocation to SDRAM works on all Microblaze boards */ +#define CONFIG_RELOC_FIXUP_WORKS + #endif diff --git a/include/asm-microblaze/global_data.h b/include/asm-microblaze/global_data.h index 3f49c349c8..ec7837f6b9 100644 --- a/include/asm-microblaze/global_data.h +++ b/include/asm-microblaze/global_data.h @@ -39,7 +39,6 @@ typedef struct global_data { unsigned long flags; unsigned long baudrate; unsigned long have_console; /* serial_init() was called */ - unsigned long reloc_off; /* Relocation Offset */ unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid? */ unsigned long fb_base; /* base address of frame buffer */ diff --git a/include/asm-nios/config.h b/include/asm-nios/config.h index 049c44eaf8..2efe898b35 100644 --- a/include/asm-nios/config.h +++ b/include/asm-nios/config.h @@ -21,4 +21,7 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +/* Relocation to SDRAM works on all NIOS boards */ +#define CONFIG_RELOC_FIXUP_WORKS + #endif diff --git a/include/asm-nios/global_data.h b/include/asm-nios/global_data.h index 4929a5b872..fa54ee4dd3 100644 --- a/include/asm-nios/global_data.h +++ b/include/asm-nios/global_data.h @@ -31,7 +31,6 @@ typedef struct global_data { unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long have_console; /* serial_init() was called */ phys_size_t ram_size; /* RAM size */ - unsigned long reloc_off; /* Relocation Offset */ unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid */ #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) diff --git a/include/asm-nios2/config.h b/include/asm-nios2/config.h index 049c44eaf8..011d603a4b 100644 --- a/include/asm-nios2/config.h +++ b/include/asm-nios2/config.h @@ -21,4 +21,7 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +/* Relocation to SDRAM works on all NIOS2 boards */ +#define CONFIG_RELOC_FIXUP_WORKS + #endif diff --git a/include/asm-nios2/global_data.h b/include/asm-nios2/global_data.h index db71324d49..34aa96277a 100644 --- a/include/asm-nios2/global_data.h +++ b/include/asm-nios2/global_data.h @@ -30,7 +30,6 @@ typedef struct global_data { unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long have_console; /* serial_init() was called */ phys_size_t ram_size; /* RAM size */ - unsigned long reloc_off; /* Relocation Offset */ unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid */ #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER) diff --git a/include/asm-ppc/config.h b/include/asm-ppc/config.h index e35b0b77fc..eba79010b1 100644 --- a/include/asm-ppc/config.h +++ b/include/asm-ppc/config.h @@ -47,4 +47,7 @@ #define CONFIG_MAX_CPUS 1 #endif +/* Relocation to SDRAM works on all PPC boards */ +#define CONFIG_RELOC_FIXUP_WORKS + #endif /* _ASM_CONFIG_H_ */ diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index db4b1eaa1e..55e7e2066d 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -24,6 +24,7 @@ #ifndef __ASM_GBL_DATA_H #define __ASM_GBL_DATA_H +#include "config.h" #include "asm/types.h" /* @@ -124,7 +125,6 @@ typedef struct global_data { unsigned long flb_clk; #endif phys_size_t ram_size; /* RAM size */ - unsigned long reloc_off; /* Relocation Offset */ unsigned long reset_status; /* reset status register at boot */ #if defined(CONFIG_MPC83xx) unsigned long arbiter_event_attributes; diff --git a/include/asm-ppc/immap_512x.h b/include/asm-ppc/immap_512x.h index 79cdd80298..bdc6ff2845 100644 --- a/include/asm-ppc/immap_512x.h +++ b/include/asm-ppc/immap_512x.h @@ -346,6 +346,16 @@ typedef struct ddr512x { #define MDDRC_SYS_CFG_CMD_MASK 0x10000000 #define MDDRC_REFRESH_ZERO_MASK 0x0000FFFF +/* + * DDR Memory Controller Configuration settings + */ +typedef struct ddr512x_config { + u32 ddr_sys_config; /* System Configuration Register */ + u32 ddr_time_config0; /* Timing Configuration Register */ + u32 ddr_time_config1; /* Timing Configuration Register */ + u32 ddr_time_config2; /* Timing Configuration Register */ +} ddr512x_config_t; + /* * DMA/Messaging Unit */ diff --git a/include/asm-ppc/mpc512x.h b/include/asm-ppc/mpc512x.h index 8ef0d9ca6d..960e229294 100644 --- a/include/asm-ppc/mpc512x.h +++ b/include/asm-ppc/mpc512x.h @@ -50,7 +50,8 @@ static inline void sync_law(volatile void *addr) /* * Prototypes */ -extern long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz); +extern long int fixed_sdram(ddr512x_config_t *mddrc_config, + u32 *dram_init_seq, int seq_sz); extern int mpc5121_diu_init(void); extern void ide_set_reset(int idereset); diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index b6182d4f21..92be514b40 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -117,6 +117,7 @@ #define SDRAM_MCSTS_MRSC 0x80000000 #define SDRAM_MCSTS_SRMS 0x40000000 #define SDRAM_MCSTS_CIS 0x20000000 +#define SDRAM_MCSTS_IDLE_NOT 0x00000000 /* Mem contr not idle */ /* * SDRAM Refresh Timer Register @@ -416,8 +417,7 @@ #define SDRAM_SDTR3 0x87 /* DDR SDRAM timing 3 */ #define SDRAM_MMODE 0x88 /* memory mode */ #define SDRAM_MEMODE 0x89 /* memory extended mode */ -#define SDRAM_ECCCR 0x98 /* ECC error status */ -#define SDRAM_ECCES SDRAM_ECCCR +#define SDRAM_ECCES 0x98 /* ECC error status */ #define SDRAM_CID 0xA4 /* core ID */ #ifndef CONFIG_405EX #define SDRAM_RID 0xA8 /* revision ID */ @@ -1397,7 +1397,6 @@ /* * Prototypes */ -void inline blank_string(int size); inline void ppc4xx_ibm_ddr2_register_dump(void); u32 mfdcr_any(u32); void mtdcr_any(u32, u32); @@ -1405,6 +1404,8 @@ u32 ddr_wrdtr(u32); u32 ddr_clktr(u32); void spd_ddr_init_hang(void); u32 DQS_autocalibration(void); +phys_size_t sdram_memsize(void); +void dcbz_area(u32 start_address, u32 num_bytes); #endif /* __ASSEMBLY__ */ #endif /* _PPC4xx_SDRAM_H_ */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index d009957d8b..f61778f864 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -863,14 +863,16 @@ #define PVR_405EP_RA 0x51210950 #define PVR_405GPR_RB 0x50910951 #define PVR_405EZ_RA 0x41511460 -#define PVR_405EXR1_RA 0x12911473 /* 405EXr rev A/B with Security */ #define PVR_405EXR2_RA 0x12911471 /* 405EXr rev A/B without Security */ #define PVR_405EX1_RA 0x12911477 /* 405EX rev A/B with Security */ -#define PVR_405EX2_RA 0x12911475 /* 405EX rev A/B without Security */ #define PVR_405EXR1_RC 0x1291147B /* 405EXr rev C with Security */ #define PVR_405EXR2_RC 0x12911479 /* 405EXr rev C without Security */ #define PVR_405EX1_RC 0x1291147F /* 405EX rev C with Security */ #define PVR_405EX2_RC 0x1291147D /* 405EX rev C without Security */ +#define PVR_405EXR1_RD 0x12911472 /* 405EXr rev D with Security */ +#define PVR_405EXR2_RD 0x12911470 /* 405EXr rev D without Security */ +#define PVR_405EX1_RD 0x12911475 /* 405EX rev D with Security */ +#define PVR_405EX2_RD 0x12911473 /* 405EX rev D without Security */ #define PVR_440GP_RB 0x40120440 #define PVR_440GP_RC 0x40120481 #define PVR_440EP_RA 0x42221850 diff --git a/include/asm-sh/config.h b/include/asm-sh/config.h index 049c44eaf8..978cc92f40 100644 --- a/include/asm-sh/config.h +++ b/include/asm-sh/config.h @@ -21,4 +21,7 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +/* Relocation to SDRAM works on all sh boards */ +#define CONFIG_RELOC_FIXUP_WORKS + #endif diff --git a/include/asm-sh/global_data.h b/include/asm-sh/global_data.h index f8ade5ca62..c12b8558ec 100644 --- a/include/asm-sh/global_data.h +++ b/include/asm-sh/global_data.h @@ -35,7 +35,6 @@ typedef struct global_data unsigned long cpu_clk; /* CPU clock in Hz! */ unsigned long have_console; /* serial_init() was called */ phys_size_t ram_size; /* RAM size */ - unsigned long reloc_off; /* Relocation Offset */ unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid */ void **jt; /* Standalone app jump table */ diff --git a/include/configs/EP1C20.h b/include/configs/EP1C20.h index 8941e4df53..61d8e20f9b 100644 --- a/include/configs/EP1C20.h +++ b/include/configs/EP1C20.h @@ -151,7 +151,8 @@ * cache bypass so there's no need to monkey with inx/outx macros. *----------------------------------------------------------------------*/ #define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */ -#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 /* Using SMC91c111 */ #undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ #define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ diff --git a/include/configs/EP1S10.h b/include/configs/EP1S10.h index 53bd0d87c9..41e64e6d1b 100644 --- a/include/configs/EP1S10.h +++ b/include/configs/EP1S10.h @@ -145,7 +145,8 @@ * cache bypass so there's no need to monkey with inx/outx macros. *----------------------------------------------------------------------*/ #define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */ -#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 /* Using SMC91c111 */ #undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ #define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ diff --git a/include/configs/EP1S40.h b/include/configs/EP1S40.h index 9e9a8a4ab0..5b332e40ee 100644 --- a/include/configs/EP1S40.h +++ b/include/configs/EP1S40.h @@ -145,7 +145,8 @@ * cache bypass so there's no need to monkey with inx/outx macros. *----------------------------------------------------------------------*/ #define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */ -#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 /* Using SMC91c111 */ #undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ #define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ diff --git a/include/configs/ISPAN.h b/include/configs/ISPAN.h index 6eb466a725..c0b1d86224 100644 --- a/include/configs/ISPAN.h +++ b/include/configs/ISPAN.h @@ -84,6 +84,10 @@ * GPIO pins used for bit-banged MII communications */ #define MDIO_PORT 3 /* Port D */ +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE + #define CONFIG_SYS_MDIO_PIN 0x00040000 /* PD13 */ #define CONFIG_SYS_MDC_PIN 0x00080000 /* PD12 */ diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index 39b8b8fce4..ffd37fd933 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -150,6 +150,9 @@ * GPIO pins used for bit-banged MII communications */ #define MDIO_PORT 2 /* Port C */ +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS #define CONFIG_SYS_MDIO_PIN 0x00002000 /* PC18 */ diff --git a/include/configs/MPC8266ADS.h b/include/configs/MPC8266ADS.h index b0162c3971..55d77f808b 100644 --- a/include/configs/MPC8266ADS.h +++ b/include/configs/MPC8266ADS.h @@ -96,6 +96,10 @@ * Port pins used for bit-banged MII communictions (if applicable). */ #define MDIO_PORT 2 /* Port C */ +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE + #define MDIO_ACTIVE (iop->pdir |= 0x00400000) #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) #define MDIO_READ ((iop->pdat & 0x00400000) != 0) diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 8ddce5c699..df59acae31 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -363,6 +363,10 @@ * GPIO pins used for bit-banged MII communications */ #define MDIO_PORT 2 /* Port C */ +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE + #define MDIO_ACTIVE (iop->pdir |= 0x00400000) #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) #define MDIO_READ ((iop->pdat & 0x00400000) != 0) diff --git a/include/configs/MigoR.h b/include/configs/MigoR.h index 3853574fcb..60838925d4 100644 --- a/include/configs/MigoR.h +++ b/include/configs/MigoR.h @@ -50,7 +50,8 @@ #undef CONFIG_SHOW_BOOT_PROGRESS /* SMC9111 */ -#define CONFIG_DRIVER_SMC91111 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 #define CONFIG_SMC91111_BASE (0xB0000000) /* MEMORY */ diff --git a/include/configs/PK1C20.h b/include/configs/PK1C20.h index 522349f788..cf6f7a9e8a 100644 --- a/include/configs/PK1C20.h +++ b/include/configs/PK1C20.h @@ -151,7 +151,8 @@ * cache bypass so there's no need to monkey with inx/outx macros. *----------------------------------------------------------------------*/ #define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */ -#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 /* Using SMC91c111 */ #undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ #define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 012ae798d1..d6e2f6bc5e 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -215,7 +215,6 @@ /*----------------------------------------------------------------------- * DDR SDRAM *----------------------------------------------------------------------*/ -#define CONFIG_SYS_MBYTES_SDRAM (256) /* 256MB */ #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ #endif diff --git a/include/configs/Rattler.h b/include/configs/Rattler.h index 5b6f27186b..e630afef01 100644 --- a/include/configs/Rattler.h +++ b/include/configs/Rattler.h @@ -103,6 +103,10 @@ * GPIO pins used for bit-banged MII communications */ #define MDIO_PORT 2 /* Port C */ +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE + #define MDIO_ACTIVE (iop->pdir |= 0x00400000) #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) #define MDIO_READ ((iop->pdat & 0x00400000) != 0) diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 7cde39bf2a..1989e5aea6 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -290,6 +290,10 @@ * GPIO pins used for bit-banged MII communications */ #define MDIO_PORT 2 /* Port C */ + #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) + #define MDC_DECLARE MDIO_DECLARE + #define MDIO_ACTIVE (iop->pdir |= 0x00400000) #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) #define MDIO_READ ((iop->pdat & 0x00400000) != 0) diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index a4336a7500..2154c7870e 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -540,6 +540,8 @@ * 101 -> use PSC6 as UART. Pins PSC6_0 to PSC6_3 are used. * Extended POST test is not available. * Use for STK52xx, FO300 and CAM5200 boards. + * WARNING: When the extended POST is enabled, these bits will + * be overridden by this code as GPIOs! * use PCI_DIS: Bit 16 (mask 0x00008000): * 1 -> disable PCI controller (on CAM5200 board). * use USB: Bits 18-19 (mask 0x00003000): @@ -552,7 +554,7 @@ * 000 -> All PSC2 pins are GPIOs. * 100 -> UART (on CAM5200 board). * 001 -> CAN1/2 on PSC2 pins. - * Use for REV100 STK52xx boards + * Use for REV100 STK52xx boards * 01x -> Use AC97 (on FO300 board). * use PSC1: Bits 29-31 (mask: 0x00000007): * 100 -> UART (on all boards). @@ -711,20 +713,20 @@ #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA -/* Offset for data I/O */ +/* Offset for data I/O */ #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) -/* Offset for normal register accesses */ +/* Offset for normal register accesses */ #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) -/* Offset for alternate registers */ +/* Offset for alternate registers */ #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) -/* Interval between registers */ +/* Interval between registers */ #define CONFIG_SYS_ATA_STRIDE 4 /* Support ATAPI devices */ -#define CONFIG_ATAPI 1 +#define CONFIG_ATAPI 1 /*----------------------------------------------------------------------- * Open firmware flat tree support diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h index 6c462af53c..6eaa61d563 100644 --- a/include/configs/TQM8272.h +++ b/include/configs/TQM8272.h @@ -219,6 +219,9 @@ * GPIO pins used for bit-banged MII communications */ #define MDIO_PORT 2 /* Port C */ +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE #if STK82xx_150 #define CONFIG_SYS_MDIO_PIN 0x00008000 /* PC16 */ diff --git a/include/configs/VoVPN-GW.h b/include/configs/VoVPN-GW.h index b2d75e3c1c..36141843a8 100644 --- a/include/configs/VoVPN-GW.h +++ b/include/configs/VoVPN-GW.h @@ -124,6 +124,11 @@ #define CONFIG_BITBANGMII #define MDIO_PORT 1 /* Port B */ + +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE + #define CONFIG_SYS_MDIO_PIN 0x00002000 /* PB18 */ #define CONFIG_SYS_MDC_PIN 0x00001000 /* PB19 */ #define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN) diff --git a/include/configs/XPEDITE5170.h b/include/configs/XPEDITE5170.h index 30642cdfef..1a810e442f 100644 --- a/include/configs/XPEDITE5170.h +++ b/include/configs/XPEDITE5170.h @@ -36,7 +36,6 @@ #define CONFIG_SYS_BOARD_NAME "XPedite5170" #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ -#define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */ #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ #define CONFIG_ALTIVEC 1 diff --git a/include/configs/XPEDITE5200.h b/include/configs/XPEDITE5200.h index d79231b8b8..3f737803e5 100644 --- a/include/configs/XPEDITE5200.h +++ b/include/configs/XPEDITE5200.h @@ -37,7 +37,6 @@ #define CONFIG_XPEDITE5200 1 #define CONFIG_SYS_BOARD_NAME "XPedite5200" #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ -#define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ diff --git a/include/configs/XPEDITE5370.h b/include/configs/XPEDITE5370.h index 65e1afddc6..26b798b4d8 100644 --- a/include/configs/XPEDITE5370.h +++ b/include/configs/XPEDITE5370.h @@ -37,7 +37,6 @@ #define CONFIG_XPEDITE5370 1 #define CONFIG_SYS_BOARD_NAME "XPedite5370" #define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */ -#define CONFIG_RELOC_FIXUP_WORKS /* Fully relocate to SDRAM */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */ diff --git a/include/configs/ZPC1900.h b/include/configs/ZPC1900.h index 9cda3f9bdf..8ae765c7c3 100644 --- a/include/configs/ZPC1900.h +++ b/include/configs/ZPC1900.h @@ -86,6 +86,10 @@ * GPIO pins used for bit-banged MII communications */ #define MDIO_PORT 2 /* Port C */ +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE + #define MDIO_ACTIVE (iop->pdir |= 0x00400000) #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) #define MDIO_READ ((iop->pdat & 0x00400000) != 0) diff --git a/include/configs/bf533-ezkit.h b/include/configs/bf533-ezkit.h index f896cb07a1..c80ddcabdf 100644 --- a/include/configs/bf533-ezkit.h +++ b/include/configs/bf533-ezkit.h @@ -65,12 +65,14 @@ * Network Settings */ #define ADI_CMDS_NETWORK 1 -#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 1 #define CONFIG_SMC91111_BASE 0x20310300 #define SMC91111_EEPROM_INIT() \ do { \ - *pFIO_DIR |= PF1; \ - *pFIO_FLAG_S = PF1; \ + bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \ + bfin_write_FIO_FLAG_C(PF1); \ + bfin_write_FIO_FLAG_S(PF0); \ SSYNC(); \ } while (0) #define CONFIG_HOSTNAME bf533-ezkit @@ -85,7 +87,7 @@ #define CONFIG_SYS_MAX_FLASH_BANKS 3 #define CONFIG_SYS_MAX_FLASH_SECT 40 #define CONFIG_ENV_IS_IN_FLASH -#define CONFIG_ENV_ADDR 0x20020000 +#define CONFIG_ENV_ADDR 0x20030000 #define CONFIG_ENV_SECT_SIZE 0x10000 #define FLASH_TOT_SECT 40 diff --git a/include/configs/bf533-stamp.h b/include/configs/bf533-stamp.h index 4be2a5cfb8..0006b029e2 100644 --- a/include/configs/bf533-stamp.h +++ b/include/configs/bf533-stamp.h @@ -60,12 +60,14 @@ * Network Settings */ #define ADI_CMDS_NETWORK 1 -#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 1 #define CONFIG_SMC91111_BASE 0x20300300 #define SMC91111_EEPROM_INIT() \ do { \ - *pFIO_DIR |= PF1; \ - *pFIO_FLAG_S = PF1; \ + bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \ + bfin_write_FIO_FLAG_C(PF1); \ + bfin_write_FIO_FLAG_S(PF0); \ SSYNC(); \ } while (0) #define CONFIG_HOSTNAME bf533-stamp diff --git a/include/configs/bf538f-ezkit.h b/include/configs/bf538f-ezkit.h index 535687fdbf..c4d899dca2 100644 --- a/include/configs/bf538f-ezkit.h +++ b/include/configs/bf538f-ezkit.h @@ -60,7 +60,8 @@ * Network Settings */ #define ADI_CMDS_NETWORK 1 -#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 1 #define CONFIG_SMC91111_BASE 0x20310300 #define CONFIG_HOSTNAME bf538f-ezkit /* Uncomment next line to use fixed MAC address */ diff --git a/include/configs/bf561-ezkit.h b/include/configs/bf561-ezkit.h index 4779a97a45..a1fa80bb89 100644 --- a/include/configs/bf561-ezkit.h +++ b/include/configs/bf561-ezkit.h @@ -60,7 +60,8 @@ * Network Settings */ #define ADI_CMDS_NETWORK 1 -#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 1 #define CONFIG_SMC91111_BASE 0x2C010300 #define CONFIG_SMC_USE_32_BIT 1 #define CONFIG_HOSTNAME bf561-ezkit diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h index 00bfc6e90b..0b87418db6 100644 --- a/include/configs/bfin_adi_common.h +++ b/include/configs/bfin_adi_common.h @@ -138,7 +138,7 @@ "uart" MK_STR(CONFIG_UART_CONSOLE) "," \ MK_STR(CONFIG_BAUDRATE) " " \ CONFIG_BOOTARGS_VIDEO \ - "console=ttyBF0," MK_STR(CONFIG_BAUDRATE) + "console=ttyBF" MK_STR(CONFIG_UART_CONSOLE) "," MK_STR(CONFIG_BAUDRATE) #if defined(CONFIG_CMD_NAND) # define NAND_ENV_SETTINGS \ "nandargs=set bootargs " CONFIG_BOOTARGS "\0" \ diff --git a/include/configs/blackstamp.h b/include/configs/blackstamp.h index 887f3fb3a3..aa33933164 100644 --- a/include/configs/blackstamp.h +++ b/include/configs/blackstamp.h @@ -30,7 +30,8 @@ /* * Board settings */ -#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 1 #define CONFIG_SMC91111_BASE 0x20300300 /* FLASH/ETHERNET uses the same address range @@ -69,7 +70,7 @@ * Network settings */ -#ifdef CONFIG_DRIVER_SMC91111 +#ifdef CONFIG_SMC91111 #define CONFIG_IPADDR 192.168.0.15 #define CONFIG_NETMASK 255.255.255.0 #define CONFIG_GATEWAYIP 192.168.0.1 @@ -108,7 +109,7 @@ #include -#ifdef CONFIG_DRIVER_SMC91111 +#ifdef CONFIG_SMC91111 # define CONFIG_CMD_DHCP # define CONFIG_CMD_PING #else diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h index b924758dc2..477b94aa61 100644 --- a/include/configs/cerf250.h +++ b/include/configs/cerf250.h @@ -53,7 +53,8 @@ /* * Hardware drivers */ -#define CONFIG_DRIVER_SMC91111 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 #define CONFIG_SMC91111_BASE 0x04000300 #define CONFIG_SMC_USE_32_BIT diff --git a/include/configs/cm-bf533.h b/include/configs/cm-bf533.h index ea548e9992..06eb2889e3 100644 --- a/include/configs/cm-bf533.h +++ b/include/configs/cm-bf533.h @@ -60,7 +60,8 @@ * Network Settings */ #define ADI_CMDS_NETWORK 1 -#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 1 #define CONFIG_SMC91111_BASE 0x20200300 #define CONFIG_HOSTNAME cm-bf533 /* Uncomment next line to use fixed MAC address */ diff --git a/include/configs/cm-bf561.h b/include/configs/cm-bf561.h index 59dc8d2458..4a77435648 100644 --- a/include/configs/cm-bf561.h +++ b/include/configs/cm-bf561.h @@ -61,7 +61,8 @@ */ #define ADI_CMDS_NETWORK 1 /* The next 2 lines are for use with DEV-BF5xx */ -#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 1 #define CONFIG_SMC91111_BASE 0x28000300 /* The next 3 lines are for use with EXT-BF5xx-USB-ETH2 */ /* #define CONFIG_DRIVER_SMC911X 1 */ diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h index 4ef8566ea2..de8cfb7c60 100644 --- a/include/configs/cpu9260.h +++ b/include/configs/cpu9260.h @@ -295,6 +295,7 @@ #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ /* NOR flash */ #define CONFIG_SYS_FLASH_CFI 1 diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h index 0d3acf61ae..8746f702da 100644 --- a/include/configs/cpuat91.h +++ b/include/configs/cpuat91.h @@ -189,8 +189,8 @@ #define CONFIG_SILENT_CONSOLE 1 #define CONFIG_AUTOBOOT_KEYED 1 -#define CONFIG_AUTOBOOT_PROMPT \ - "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_PROMPT \ + "Press SPACE to abort autoboot\n" #define CONFIG_AUTOBOOT_STOP_STR " " #define CONFIG_AUTOBOOT_DELAY_STR "d" diff --git a/include/configs/cradle.h b/include/configs/cradle.h index b150c221a3..200b61e0c7 100644 --- a/include/configs/cradle.h +++ b/include/configs/cradle.h @@ -49,7 +49,8 @@ /* * Hardware drivers */ -#define CONFIG_DRIVER_SMC91111 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 #define CONFIG_SMC91111_BASE 0x10000300 #define CONFIG_SMC91111_EXT_PHY #define CONFIG_SMC_USE_32_BIT diff --git a/include/configs/davinci_dm355evm.h b/include/configs/davinci_dm355evm.h index d092fb8325..ea40df0bed 100644 --- a/include/configs/davinci_dm355evm.h +++ b/include/configs/davinci_dm355evm.h @@ -69,6 +69,7 @@ #define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST #define CONFIG_SYS_NAND_PAGE_2K +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #define CONFIG_SYS_NAND_LARGEPAGE #define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, } diff --git a/include/configs/davinci_dm355leopard.h b/include/configs/davinci_dm355leopard.h new file mode 100644 index 0000000000..5db720e9d6 --- /dev/null +++ b/include/configs/davinci_dm355leopard.h @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2009 Texas Instruments Incorporated + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define DAVINCI_DM355LEOPARD + +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is a 3rd stage loader */ +#define CONFIG_SKIP_RELOCATE_UBOOT +#define CONFIG_SYS_NO_FLASH /* that is, no *NOR* flash */ +#define CONFIG_SYS_CONSOLE_INFO_QUIET +#define CONFIG_DISPLAY_CPUINFO + +/* SoC Configuration */ +#define CONFIG_ARM926EJS /* arm926ejs CPU */ +#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ +#define CONFIG_SYS_HZ_CLOCK 24000000 /* timer0 freq */ +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SOC_DM355 /* DM355 based board */ + +/* Memory Info */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_1_SIZE (128 << 20) /* 128 MiB */ + +/* Serial Driver info: UART0 for console */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE -4 +#define CONFIG_SYS_NS16550_COM1 0x01c20000 +#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_HZ_CLOCK +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Ethernet: external DM9000 */ +#define CONFIG_DRIVER_DM9000 1 +#define CONFIG_DM9000_BASE 0x04000000 +#define DM9000_IO CONFIG_DM9000_BASE +#define DM9000_DATA (CONFIG_DM9000_BASE + 16) +#define CONFIG_NET_MULTI + +/* I2C */ +#define CONFIG_HARD_I2C +#define CONFIG_DRIVER_DAVINCI_I2C +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 0x10 + +/* NAND */ +#define CONFIG_NAND_DAVINCI +#define CONFIG_SYS_NAND_USE_FLASH_BBT +#define CONFIG_SYS_NAND_HW_ECC + +#define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, } +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_MAX_CHIPS 1 + +/* U-Boot command configuration */ +#include + +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES + +#ifdef CONFIG_NAND_DAVINCI +#define CONFIG_CMD_MTDPARTS +#define CONFIG_MTD_PARTITIONS +#define CONFIG_MTD_DEVICE +#define CONFIG_CMD_NAND +#define CONFIG_CMD_UBI +#define CONFIG_RBTREE +#endif + +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC + +/* U-Boot general configuration */ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CONFIG_SYS_PROMPT "DM355 LEOPARD # " +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE /* Print buffer size */ \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_LONGHELP + +#ifdef CONFIG_NAND_DAVINCI +#define CONFIG_ENV_SIZE (256 << 10) /* 256 KiB */ +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_ENV_OFFSET 0x3C0000 +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ +#undef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OVERWRITE +#endif + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTCOMMAND "dhcp;bootm" +#define CONFIG_BOOTARGS \ + "console=ttyS0,115200n8 " \ + "root=/dev/mmcblk0p1 rootwait rootfstype=ext3 ro" + +#define CONFIG_CMDLINE_EDITING +#define CONFIG_VERSION_VARIABLE +#define CONFIG_TIMESTAMP + +#define CONFIG_NET_RETRY_COUNT 10 + +/* U-Boot memory configuration */ +#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */ +#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* for initial data */ +#define CONFIG_SYS_MEMTEST_START 0x87000000 /* physical address */ +#define CONFIG_SYS_MEMTEST_END 0x88000000 /* test 16MB RAM */ + +/* Linux interfacing */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_SYS_BARGSIZE 1024 /* bootarg Size */ +#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */ + +#define MTDIDS_DEFAULT "nand0=davinci_nand.0" + +#ifdef CONFIG_SYS_NAND_LARGEPAGE +#define PART_BOOT "2m(bootloader)ro," +#else +/* Assume 16K erase blocks; allow a few bad ones. */ +#define PART_BOOT "512k(bootloader)ro," +#endif + +#define PART_KERNEL "4m(kernel)," /* kernel + initramfs */ +#define PART_REST "-(filesystem)" + +#define MTDPARTS_DEFAULT \ + "mtdparts=davinci_nand.0:" PART_BOOT PART_KERNEL PART_REST + +#endif /* __CONFIG_H */ diff --git a/include/configs/davinci_dm365evm.h b/include/configs/davinci_dm365evm.h index 2797f827e9..53a105bf6d 100644 --- a/include/configs/davinci_dm365evm.h +++ b/include/configs/davinci_dm365evm.h @@ -1,4 +1,5 @@ /* + * Copyright (C) 2009 Texas Instruments Incorporated * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -76,6 +77,7 @@ #define CONFIG_SYS_NAND_USE_FLASH_BBT #define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST #define CONFIG_SYS_NAND_PAGE_2K +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #define CONFIG_SYS_NAND_LARGEPAGE #define CONFIG_SYS_NAND_BASE_LIST { 0x02000000, } diff --git a/include/configs/davinci_dm6467evm.h b/include/configs/davinci_dm6467evm.h new file mode 100644 index 0000000000..2a4cb79f88 --- /dev/null +++ b/include/configs/davinci_dm6467evm.h @@ -0,0 +1,132 @@ +/* + * Copyright (C) 2009 Texas Instruments Incorporated + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* Spectrum Digital TMS320DM6467 EVM board */ +#define DAVINCI_DM6467EVM + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT + +/* SoC Configuration */ +#define CONFIG_ARM926EJS /* arm926ejs CPU */ +#define CONFIG_SYS_TIMERBASE 0x01c21400 /* use timer 0 */ +#define CONFIG_SYS_HZ_CLOCK 27000000 +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SOC_DM646X + +/* EEPROM definitions for EEPROM */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 + +/* Memory Info */ +#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* 1 MiB */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* initial data */ +#define CONFIG_SYS_MEMTEST_START 0x80000000 +#define CONFIG_SYS_MEMTEST_END 0x81000000 /* 16MB RAM test */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */ +#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ +#define PHYS_SDRAM_1_SIZE (256 << 20) /* DDR size 256MB */ + +/* Linux interfacing */ +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_SYS_BARGSIZE 1024 /* Bootarg Size */ +#define CONFIG_SYS_LOAD_ADDR 0x80700000 /* kernel address */ + +/* Serial Driver info */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 4 +#define CONFIG_SYS_NS16550_COM1 0x01c20000 +#define CONFIG_SYS_NS16550_CLK 24000000 +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* I2C Configuration */ +#define CONFIG_HARD_I2C +#define CONFIG_DRIVER_DAVINCI_I2C +#define CONFIG_SYS_I2C_SPEED 80000 +#define CONFIG_SYS_I2C_SLAVE 10 + +/* Flash & Environment */ +#define CONFIG_SYS_NO_FLASH +#ifdef CONFIG_SYS_USE_NAND +#define CONFIG_NAND_DAVINCI +#undef CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_IS_IN_NAND +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ +#define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ +#define CONFIG_SYS_NAND_BASE_LIST {0x42000000, } +#define CONFIG_SYS_NAND_HW_ECC +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_ENV_OFFSET 0 +#else +#define CONFIG_ENV_IS_NOWHERE +#define CONFIG_ENV_SIZE (4 << 10) /* 4 KiB */ +#endif + +/* U-Boot general configuration */ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CONFIG_SYS_PROMPT "DM6467 EVM > " /* Monitor Command Prompt */ +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC +#define CONFIG_BOOTCOMMAND "source 0x82080000; dhcp; bootm" +#define CONFIG_BOOTARGS \ + "mem=120M console=ttyS0,115200n8 " \ + "root=/dev/hda1 rw noinitrd ip=dhcp" + +/* U-Boot commands */ +#include +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_EEPROM +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#ifdef CONFIG_SYS_USE_NAND +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +#define CONFIG_CMD_NAND +#endif + +#endif /* __CONFIG_H */ + diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index f7d23990c4..b045e80ae6 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -138,6 +138,7 @@ #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #define DEF_BOOTM "" #elif defined(CONFIG_SYS_USE_NOR) #ifdef CONFIG_NOR_UART_BOOT diff --git a/include/configs/davinci_sonata.h b/include/configs/davinci_sonata.h index 5a55c569dd..9138b2b90a 100644 --- a/include/configs/davinci_sonata.h +++ b/include/configs/davinci_sonata.h @@ -125,6 +125,7 @@ #define CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define CONFIG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ +#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */ #define DEF_BOOTM "" #elif defined(CONFIG_SYS_USE_NOR) #ifdef CONFIG_NOR_UART_BOOT diff --git a/include/configs/devkit8000.h b/include/configs/devkit8000.h index a8ac786c64..bd5037e910 100644 --- a/include/configs/devkit8000.h +++ b/include/configs/devkit8000.h @@ -30,7 +30,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include /* High Level Configuration Options */ #define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ @@ -59,9 +58,9 @@ #define CONFIG_REVISION_TAG 1 /* Size of malloc() pool */ -#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ /* initial data */ @@ -271,16 +270,16 @@ #define CONFIG_SYS_HZ 1000 /* The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ #ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ #endif /* Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE SZ_128M /* at least 128 meg */ +#define PHYS_SDRAM_1_SIZE (128 << 20) /* at least 128 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* SDRAM Bank Allocation method */ @@ -289,7 +288,7 @@ /* NAND and environment organization */ #define PISMO1_NAND_SIZE GPMC_SIZE_128M -#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #define CONFIG_ENV_IS_IN_NAND 1 #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ diff --git a/include/configs/dnp1110.h b/include/configs/dnp1110.h index b6cfc6721d..e48e20f685 100644 --- a/include/configs/dnp1110.h +++ b/include/configs/dnp1110.h @@ -54,7 +54,8 @@ /* * Hardware drivers */ -#define CONFIG_DRIVER_SMC91111 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 #define CONFIG_SMC91111_BASE 0x20000300 diff --git a/include/configs/ep8248.h b/include/configs/ep8248.h index cb4185a67b..a738425f4f 100644 --- a/include/configs/ep8248.h +++ b/include/configs/ep8248.h @@ -92,6 +92,7 @@ * GPIO pins used for bit-banged MII communications */ #define MDIO_PORT 0 /* Not used - implemented in BCSR */ + #define MDIO_ACTIVE (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB) #define MDIO_TRISTATE (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04) #define MDIO_READ (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1) diff --git a/include/configs/ep82xxm.h b/include/configs/ep82xxm.h index 239ff67330..c737f10ec9 100644 --- a/include/configs/ep82xxm.h +++ b/include/configs/ep82xxm.h @@ -85,6 +85,7 @@ * GPIO pins used for bit-banged MII communications */ #define MDIO_PORT 0 /* Not used - implemented in BCSR */ + #define MDIO_ACTIVE (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB) #define MDIO_TRISTATE (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04) #define MDIO_READ (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1) diff --git a/include/configs/gr_cpci_ax2000.h b/include/configs/gr_cpci_ax2000.h index bbe635b9fe..d188439db7 100644 --- a/include/configs/gr_cpci_ax2000.h +++ b/include/configs/gr_cpci_ax2000.h @@ -292,7 +292,8 @@ /* * Ethernet configuration uses on board SMC91C111 */ -#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 1 #define CONFIG_SMC91111_BASE 0x20000300 /* chip select 3 */ #define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */ #undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ diff --git a/include/configs/gr_ep2s60.h b/include/configs/gr_ep2s60.h index 7b0a08ff01..3a568ffad2 100644 --- a/include/configs/gr_ep2s60.h +++ b/include/configs/gr_ep2s60.h @@ -267,7 +267,8 @@ #ifndef USE_GRETH /* USE SMC91C111 MAC */ -#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 1 #define CONFIG_SMC91111_BASE 0x20000300 /* chip select 3 */ #define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */ #undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ diff --git a/include/configs/gw8260.h b/include/configs/gw8260.h index 53a001d211..9ed38463cd 100644 --- a/include/configs/gw8260.h +++ b/include/configs/gw8260.h @@ -212,6 +212,11 @@ * Port pins used for bit-banged MII communictions (if applicable). */ #define MDIO_PORT 2 /* Port C */ + +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE + #define MDIO_ACTIVE (iop->pdir |= 0x00400000) #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) #define MDIO_READ ((iop->pdat & 0x00400000) != 0) diff --git a/include/configs/hymod.h b/include/configs/hymod.h index 284672b338..5a282ff941 100644 --- a/include/configs/hymod.h +++ b/include/configs/hymod.h @@ -93,6 +93,10 @@ # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) # define MDIO_PORT 0 /* Port A */ +# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +# define MDC_DECLARE MDIO_DECLARE + # define MDIO_DATA_PINMASK 0x00040000 /* Pin 13 */ # define MDIO_CLCK_PINMASK 0x00080000 /* Pin 12 */ @@ -110,6 +114,10 @@ # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) # define MDIO_PORT 0 /* Port A */ +# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +# define MDC_DECLARE MDIO_DECLARE + # define MDIO_DATA_PINMASK 0x00000040 /* Pin 25 */ # define MDIO_CLCK_PINMASK 0x00000080 /* Pin 24 */ @@ -127,6 +135,10 @@ # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) # define MDIO_PORT 0 /* Port A */ +# define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +# define MDC_DECLARE MDIO_DECLARE + # define MDIO_DATA_PINMASK 0x00000100 /* Pin 23 */ # define MDIO_CLCK_PINMASK 0x00000200 /* Pin 22 */ diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index 46606cace9..14f7826705 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -42,7 +42,6 @@ #define BOOTFLAG_WARM 0x02 /* Software reboot */ #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ -#define CONFIG_MISC_INIT_R 1 /* Use misc_init_r() */ #define CONFIG_HIGH_BATS 1 /* High BATs supported */ diff --git a/include/configs/innokom.h b/include/configs/innokom.h index ed03ad32a0..9cb0d42eac 100644 --- a/include/configs/innokom.h +++ b/include/configs/innokom.h @@ -157,7 +157,8 @@ /* * SMSC91C111 Network Card */ -#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 1 #define CONFIG_SMC91111_BASE 0x14000000 /* chip select 5 */ #undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */ #undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index e38d569108..caafc93116 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -53,7 +53,8 @@ /* * Hardware drivers */ -#define CONFIG_DRIVER_SMC91111 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 #define CONFIG_SMC_USE_32_BIT #define CONFIG_SMC91111_BASE 0xC8000000 #undef CONFIG_SMC91111_EXT_PHY diff --git a/include/configs/logodl.h b/include/configs/logodl.h index 5b903f0dcb..0535ee127f 100644 --- a/include/configs/logodl.h +++ b/include/configs/logodl.h @@ -133,7 +133,8 @@ * SMSC91C111 Network Card */ #if 0 -#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 1 #define CONFIG_SMC91111_BASE 0x10000000 /* chip select 4 */ #undef CONFIG_SMC_USE_32_BIT /* 16 bit bus access */ #undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ diff --git a/include/configs/lpd7a400-10.h b/include/configs/lpd7a400-10.h index 6145c37f78..5f57c3a5a1 100644 --- a/include/configs/lpd7a400-10.h +++ b/include/configs/lpd7a400-10.h @@ -72,7 +72,8 @@ * Default IO base of chip is 0x300, Card Engine has this address lines * (LAN chip) tied to Vcc, so we just care about the chip select */ -#define CONFIG_DRIVER_SMC91111 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 #define CONFIG_SMC91111_BASE (0x70000000) #undef CONFIG_SMC_USE_32_BIT #define CONFIG_SMC_USE_IOFUNCS diff --git a/include/configs/lpd7a404-10.h b/include/configs/lpd7a404-10.h index ce23f3d602..9074e28a04 100644 --- a/include/configs/lpd7a404-10.h +++ b/include/configs/lpd7a404-10.h @@ -72,7 +72,8 @@ * Default IO base of chip is 0x300, Card Engine has this address lines * (LAN chip) tied to Vcc, so we just care about the chip select */ -#define CONFIG_DRIVER_SMC91111 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 #define CONFIG_SMC91111_BASE (0x70000000) #undef CONFIG_SMC_USE_32_BIT #define CONFIG_SMC_USE_IOFUNCS diff --git a/include/configs/ms7722se.h b/include/configs/ms7722se.h index 6755af3d59..02514285cc 100644 --- a/include/configs/ms7722se.h +++ b/include/configs/ms7722se.h @@ -48,7 +48,8 @@ #undef CONFIG_SHOW_BOOT_PROGRESS /* SMC9111 */ -#define CONFIG_DRIVER_SMC91111 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 #define CONFIG_SMC91111_BASE (0xB8000000) /* MEMORY */ diff --git a/include/configs/muas3001.h b/include/configs/muas3001.h index c94daa3d03..43f46bffee 100644 --- a/include/configs/muas3001.h +++ b/include/configs/muas3001.h @@ -101,6 +101,10 @@ * GPIO pins used for bit-banged MII communications */ #define MDIO_PORT 0 /* Port A */ +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE + #define CONFIG_SYS_MDIO_PIN 0x00200000 /* PA10 */ #define CONFIG_SYS_MDC_PIN 0x00400000 /* PA9 */ diff --git a/include/configs/netstar.h b/include/configs/netstar.h index f0b420781e..7bddf2444b 100644 --- a/include/configs/netstar.h +++ b/include/configs/netstar.h @@ -93,7 +93,8 @@ #define CONFIG_SYS_NS16550_CLK (CONFIG_XTAL_FREQ) /* can be 12M/32Khz or 48Mhz */ #define CONFIG_SYS_NS16550_COM1 OMAP1510_UART1_BASE /* uart1 */ -#define CONFIG_DRIVER_SMC91111 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 #define CONFIG_SMC91111_BASE 0x04000300 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 diff --git a/include/configs/nhk8815.h b/include/configs/nhk8815.h index 027e8e16b3..a00c2fb23a 100644 --- a/include/configs/nhk8815.h +++ b/include/configs/nhk8815.h @@ -132,7 +132,8 @@ #define __io(a) ((void __iomem *)(PCI_IO_VADDR + (a))) #define __mem_isa(a) ((a) + PCI_MEMORY_VADDR) -#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111*/ +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 /* Using SMC91c111*/ #define CONFIG_SMC91111_BASE 0x34000300 #undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ #define CONFIG_SMC_USE_32_BIT diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 55eeb947fe..19a5ec92ec 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -27,7 +27,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include /* * High Level Configuration Options @@ -62,9 +61,9 @@ /* * Size of malloc() pool */ -#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ /* initial data */ @@ -165,16 +164,27 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "console=ttyS2,115200n8\0" \ - "videomode=1024x768@60,vxres=1024,vyres=768\0" \ - "videospec=omapfb:vram:2M,vram:4M\0" \ + "vram=12M\0" \ + "dvimode=1024x768MR-16@60\0" \ + "defaultdisplay=dvi\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "nandroot=/dev/mtdblock4 rw\0" \ + "nandrootfstype=jffs2\0" \ "mmcargs=setenv bootargs console=${console} " \ - "video=${videospec},mode:${videomode} " \ - "root=/dev/mmcblk0p2 rw " \ - "rootfstype=ext3 rootwait\0" \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapfb.debug=y " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ "nandargs=setenv bootargs console=${console} " \ - "video=${videospec},mode:${videomode} " \ - "root=/dev/mtdblock4 rw " \ - "rootfstype=jffs2\0" \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapfb.debug=y " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source ${loadaddr}\0" \ @@ -239,10 +249,10 @@ * * The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ #ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ #endif /*----------------------------------------------------------------------- @@ -250,7 +260,7 @@ */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* SDRAM Bank Allocation method */ @@ -269,7 +279,7 @@ #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ /* one chip */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #define CONFIG_SYS_FLASH_BASE boot_flash_base diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index 72e9626963..a5514aeb9b 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -32,7 +32,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include /* * High Level Configuration Options @@ -67,9 +66,9 @@ /* * Size of malloc() pool */ -#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ /* initial data */ /* @@ -231,10 +230,10 @@ * * The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ #ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ #endif /*----------------------------------------------------------------------- @@ -242,7 +241,7 @@ */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* SDRAM Bank Allocation method */ @@ -261,7 +260,7 @@ #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ /* on one chip */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #define CONFIG_SYS_FLASH_BASE boot_flash_base diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 1a9192135e..ffb515d322 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -19,7 +19,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include /* * High Level Configuration Options @@ -54,9 +53,9 @@ /* * Size of malloc() pool */ -#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ /* initial data */ @@ -151,16 +150,27 @@ #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "console=ttyS2,115200n8\0" \ - "videomode=1024x768@60,vxres=1024,vyres=768\0" \ - "videospec=omapfb:vram:2M,vram:4M\0" \ + "vram=12M\0" \ + "dvimode=1024x768MR-16@60\0" \ + "defaultdisplay=dvi\0" \ + "mmcroot=/dev/mmcblk0p2 rw\0" \ + "mmcrootfstype=ext3 rootwait\0" \ + "nandroot=/dev/mtdblock4 rw\0" \ + "nandrootfstype=jffs2\0" \ "mmcargs=setenv bootargs console=${console} " \ - "video=${videospec},mode:${videomode} " \ - "root=/dev/mmcblk0p2 rw " \ - "rootfstype=ext3 rootwait\0" \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapfb.debug=y " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${mmcroot} " \ + "rootfstype=${mmcrootfstype}\0" \ "nandargs=setenv bootargs console=${console} " \ - "video=${videospec},mode:${videomode} " \ - "root=/dev/mtdblock4 rw " \ - "rootfstype=jffs2\0" \ + "vram=${vram} " \ + "omapfb.mode=dvi:${dvimode} " \ + "omapfb.debug=y " \ + "omapdss.def_disp=${defaultdisplay} " \ + "root=${nandroot} " \ + "rootfstype=${nandrootfstype}\0" \ "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source ${loadaddr}\0" \ @@ -224,10 +234,10 @@ * * The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ #ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ #endif /*----------------------------------------------------------------------- @@ -235,7 +245,7 @@ */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* SDRAM Bank Allocation method */ @@ -254,7 +264,7 @@ #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ /* one chip */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #define CONFIG_SYS_FLASH_BASE boot_flash_base diff --git a/include/configs/omap3_pandora.h b/include/configs/omap3_pandora.h index 064c0bc690..6f21af3d13 100644 --- a/include/configs/omap3_pandora.h +++ b/include/configs/omap3_pandora.h @@ -22,7 +22,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include /* * High Level Configuration Options @@ -57,9 +56,9 @@ /* * Size of malloc() pool */ -#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ /* initial data */ @@ -228,10 +227,10 @@ * * The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ #ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ #endif /*----------------------------------------------------------------------- @@ -239,7 +238,7 @@ */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* SDRAM Bank Allocation method */ @@ -258,7 +257,7 @@ #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ /* one chip */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #define CONFIG_SYS_FLASH_BASE boot_flash_base diff --git a/include/configs/omap3_sdp3430.h b/include/configs/omap3_sdp3430.h new file mode 100644 index 0000000000..229dc5e644 --- /dev/null +++ b/include/configs/omap3_sdp3430.h @@ -0,0 +1,369 @@ +/* + * (C) Copyright 2006-2009 + * Texas Instruments Incorporated. + * Richard Woodruff + * Syed Mohammed Khasim + * Nishanth Menon + * + * Configuration settings for the 3430 TI SDP3430 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* TODO: REMOVE THE FOLLOWING + * Retained the following till size.h is removed in u-boot + */ +#include +/* + * High Level Configuration Options + */ +#define CONFIG_ARMCORTEXA8 1 /* This is an ARM V7 CPU core */ +#define CONFIG_OMAP 1 /* in a TI OMAP core */ +#define CONFIG_OMAP34XX 1 /* which is a 34XX */ +#define CONFIG_OMAP3430 1 /* which is in a 3430 */ +#define CONFIG_OMAP3_3430SDP 1 /* working with SDP Rev2 */ + +#include /* get chip and board defs */ +#include + +/* + * NOTE: these #defines presume standard SDP jumper settings. + * In particular: + * - 26 MHz clock (not 19.2 or 38.4 MHz) + * - Boot from 128MB NOR, not NAND or OneNAND + * + * At this writing, OMAP3 U-Boot support doesn't permit concurrent + * support for all the flash types the board supports. + */ +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +/* Clock Defines */ +#define V_OSCK 26000000 /* Clock output from T2 */ +#define V_SCLK (V_OSCK >> 1) + +#undef CONFIG_USE_IRQ /* no support for IRQs */ +#define CONFIG_MISC_INIT_R + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +/* + * Size of malloc() pool + * Total Size Environment - 256k + * Malloc - add 256k + */ +#define CONFIG_ENV_SIZE (256 << 10) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10)) +#define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ + /* initial data */ + +/*--------------------------------------------------------------------------*/ + +/* + * Hardware drivers + */ + +/* + * TWL4030 + */ +#define CONFIG_TWL4030_POWER 1 + +/* + * serial port - NS16550 compatible + */ +#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ + +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE (-4) +#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK + +/* Original SDP u-boot used UART1 and thus J8 (innermost); that can be + * swapped with UART2 via jumpering. Downsides of using J8: it doesn't + * support UART boot (that's only for UART3); it prevents sharing a Linux + * kernel (LL_DEBUG_UART3) or filesystem (getty ttyS2) with most boards. + * + * UART boot uses UART3 on J9, and the SDP user's guide says to use + * that for console. Downsides of using J9: you can't use IRDA too; + * since UART3 isn't in the CORE power domain, it may be a bit less + * usable in certain PM-sensitive debug scenarios. + */ +#undef CONSOLE_J9 /* else J8/UART1 (innermost) */ + +#ifdef CONSOLE_J9 +#define CONFIG_CONS_INDEX 3 +#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 +#define CONFIG_SERIAL3 3 /* UART3 */ +#else +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 +#define CONFIG_SERIAL1 1 /* UART1 */ +#endif + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ + 115200} + +/* + * I2C for power management setup + */ +#define CONFIG_HARD_I2C 1 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 1 +#define CONFIG_SYS_I2C_BUS 0 +#define CONFIG_SYS_I2C_BUS_SELECT 1 +#define CONFIG_DRIVER_OMAP34XX_I2C 1 + +/* OMITTED: single 1 Gbit MT29F1G NAND flash */ + +/* + * NOR boot support - single 1 Gbit PF48F6000M0 Strataflash + */ +#define CONFIG_SYS_FLASH_BASE 0x10000000 +#define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#define CONFIG_SYS_FLASH_CFI 1 /* use CFI geometry data */ +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* ~10x faster writes */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware sector protection */ +#define CONFIG_SYS_FLASH_EMPTY_INFO 1 /* flinfo 'E' for empty */ +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */ + +#define CONFIG_SYS_FLASH_CFI_WIDTH 2 +#define PHYS_FLASH_SIZE (128 << 20) +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors on one chip */ + +/* timeout values are in milliseconds */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) +#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) + +/* OMITTED: single 2 Gbit KFM2G16 OneNAND flash */ + +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_SYS_ENV_SECT_SIZE (256 << 10) +#define CONFIG_ENV_OFFSET CONFIG_SYS_ENV_SECT_SIZE +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_ENV_SECT_SIZE) +/*--------------------------------------------------------------------------*/ + +/* commands to include */ +#include + +/* Enabled commands */ +#define CONFIG_CMD_DHCP /* DHCP Support */ +#define CONFIG_CMD_EXT2 /* EXT2 Support */ +#define CONFIG_CMD_FAT /* FAT support */ +#define CONFIG_CMD_I2C /* I2C serial bus support */ +#define CONFIG_CMD_JFFS2 /* JFFS2 Support */ +#define CONFIG_CMD_MMC /* MMC support */ +#define CONFIG_CMD_NET + +/* Disabled commands */ +#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ +#undef CONFIG_CMD_IMLS /* List all found images */ + +/*--------------------------------------------------------------------------*/ +/* + * MMC boot support + */ + +#if defined(CONFIG_CMD_MMC) +#define CONFIG_MMC 1 +#define CONFIG_OMAP3_MMC 1 +#define CONFIG_DOS_PARTITION 1 +#endif + +/*---------------------------------------------------------------------------- + * SMSC9115 Ethernet from SMSC9118 family + *---------------------------------------------------------------------------- + */ +#if defined(CONFIG_CMD_NET) + +#define CONFIG_DRIVER_LAN91C96 +#define CONFIG_LAN91C96_BASE DEBUG_BASE +#define CONFIG_LAN91C96_EXT_PHY + +#define CONFIG_BOOTP_SEND_HOSTNAME +/* + * BOOTP fields + */ +#define CONFIG_BOOTP_SUBNETMASK 0x00000001 +#define CONFIG_BOOTP_GATEWAY 0x00000002 +#define CONFIG_BOOTP_HOSTNAME 0x00000004 +#define CONFIG_BOOTP_BOOTPATH 0x00000010 +#endif /* (CONFIG_CMD_NET) */ + +/* + * Environment setup + * + * Default boot order: mmc bootscript, MMC uImage, NOR image. + * Network booting environment must be configured at site. + */ + +/* allow overwriting serial config and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loadaddr=0x82000000\0" \ + "console=ttyS0,115200n8\0" \ + "mmcargs=setenv bootargs console=${console} " \ + "root=/dev/mmcblk0p2 rw " \ + "rootfstype=ext3 rootwait\0" \ + "norargs=setenv bootargs console=${console} " \ + "root=/dev/mtdblock3 rw " \ + "rootfstype=jffs2\0" \ + "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \ + "bootscript=echo Running bootscript from MMC/SD ...; " \ + "autoscr ${loadaddr}\0" \ + "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \ + "mmcboot=echo Booting from MMC/SD ...; " \ + "run mmcargs; " \ + "bootm ${loadaddr}\0" \ + "norboot=echo Booting from NOR ...; " \ + "run norargs; " \ + "bootm 0x80000\0" \ + +#define CONFIG_BOOTCOMMAND \ + "if mmcinit; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run norboot; " \ + "fi; " \ + "fi; " \ + "else run norboot; fi" + +#define CONFIG_AUTO_COMPLETE 1 + +/*--------------------------------------------------------------------------*/ + +/* + * Miscellaneous configurable options + */ +#define V_PROMPT "OMAP34XX SDP # " + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_PROMPT V_PROMPT +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) + +/* SDRAM Test range - start at 16 meg boundary -ends at 32Meg - + * a basic sanity check ONLY + * IF you would like to increase coverage, increase the end address + * or run the test with custom options + */ +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x01000000) +#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + (32 << 20)) + +/* Default load address */ +#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) + +/*--------------------------------------------------------------------------*/ + +/* + * 3430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by + * 32KHz clk, or from external sig. This rate is divided by a local divisor. + */ +#define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) +#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ +#define CONFIG_SYS_HZ 1000 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 << 10) /* Regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack */ +#endif + +/* + * SDRAM Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ +#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 meg */ +#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 + +/* SDRAM Bank Allocation method */ +#define SDRC_R_B_C 1 + +/*--------------------------------------------------------------------------*/ + +/* + * NOR FLASH usage ... default nCS0: + * - one 256KB sector for U-Boot + * - one 256KB sector for its parameters (not all used) + * - eight sectors (2 MB) for kernel + * - rest for JFFS2 + */ + +/* Monitor at start of flash */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (256 << 10) + +#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS +#define CONFIG_SYS_JFFS2_NUM_BANKS 1 + +/* + * NAND FLASH usage ... default nCS1: + * - four 128KB sectors for X-Loader + * - four 128KB sectors for U-Boot + * - two 128KB sector for its parameters + * - 32 sectors (4 MB) for kernel + * - rest for filesystem + */ + +/* + * OneNAND FLASH usage ... default nCS2: + * - four 128KB sectors for X-Loader + * - two 128KB sectors for U-Boot + * - one 128KB sector for its parameters + * - sixteen sectors (2 MB) for kernel + * - rest for filesystem + */ + +/*--------------------------------------------------------------------------*/ + +#ifndef __ASSEMBLY__ +extern struct gpmc *gpmc_cfg; +extern unsigned int boot_flash_base; +extern volatile unsigned int boot_flash_env_addr; +extern unsigned int boot_flash_off; +extern unsigned int boot_flash_sec; +extern unsigned int boot_flash_type; +#endif + +#endif /* __CONFIG_H */ diff --git a/include/configs/omap3_zoom1.h b/include/configs/omap3_zoom1.h index b55b8f0222..da4b677f93 100644 --- a/include/configs/omap3_zoom1.h +++ b/include/configs/omap3_zoom1.h @@ -28,7 +28,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include /* * High Level Configuration Options @@ -63,9 +62,9 @@ /* * Size of malloc() pool */ -#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ /* initial data */ @@ -236,10 +235,10 @@ * * The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE SZ_128K /* regular stack */ +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ #ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ SZ_4K /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ SZ_4K /* FIQ stack */ +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ #endif /*----------------------------------------------------------------------- @@ -247,7 +246,7 @@ */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* SDRAM Bank Allocation method */ @@ -266,7 +265,7 @@ #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ /* one chip */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #define CONFIG_SYS_FLASH_BASE boot_flash_base diff --git a/include/configs/omap3_zoom2.h b/include/configs/omap3_zoom2.h index 75ab98098c..32cd6fdb14 100644 --- a/include/configs/omap3_zoom2.h +++ b/include/configs/omap3_zoom2.h @@ -29,7 +29,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#include /* * High Level Configuration Options @@ -64,9 +63,9 @@ /* * Size of malloc() pool */ -#define CONFIG_ENV_SIZE SZ_128K /* Total Size Environment */ +#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ /* Sector */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + SZ_128K) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */ /* initial data */ /* @@ -201,10 +200,10 @@ * * The stack sizes are set up in start.S using these settings */ -#define CONFIG_STACKSIZE SZ_128K +#define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */ #ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ SZ_4K -#define CONFIG_STACKSIZE_FIQ SZ_4K +#define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */ +#define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */ #endif /*----------------------------------------------------------------------- @@ -212,7 +211,7 @@ */ #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 -#define PHYS_SDRAM_1_SIZE SZ_32M /* at least 32 meg */ +#define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 /* SDRAM Bank Allocation method */ @@ -231,7 +230,7 @@ #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */ /* one chip */ #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ -#define CONFIG_SYS_MONITOR_LEN SZ_256K /* Reserve 2 sectors */ +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ #define CONFIG_SYS_FLASH_BASE boot_flash_base diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h index 5e4d30b8a5..0749037163 100644 --- a/include/configs/p3mx.h +++ b/include/configs/p3mx.h @@ -59,7 +59,6 @@ /* which initialization functions to call for this board */ #define CONFIG_SYS_BOARD_ASM_INIT 1 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ -#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ /*----------------------------------------------------------------------- diff --git a/include/configs/ppmc8260.h b/include/configs/ppmc8260.h index ff7d61439b..f387601861 100644 --- a/include/configs/ppmc8260.h +++ b/include/configs/ppmc8260.h @@ -182,6 +182,10 @@ * Port pins used for bit-banged MII communictions (if applicable). */ #define MDIO_PORT 2 /* Port C */ +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE + #define MDIO_ACTIVE (iop->pdir |= 0x00400000) #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) #define MDIO_READ ((iop->pdat & 0x00400000) != 0) diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h index 2cae8ca9b3..6c1defc9ae 100644 --- a/include/configs/pxa255_idp.h +++ b/include/configs/pxa255_idp.h @@ -87,7 +87,8 @@ /* * Hardware drivers */ -#define CONFIG_DRIVER_SMC91111 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 #define CONFIG_SMC91111_BASE (PXA_CS5_PHYS + IDP_CS5_ETH_OFFSET + 0x300) #define CONFIG_SMC_USE_32_BIT 1 /* #define CONFIG_SMC_USE_IOFUNCS */ diff --git a/include/configs/sacsng.h b/include/configs/sacsng.h index 0ab6fc31ea..b0198aa06b 100644 --- a/include/configs/sacsng.h +++ b/include/configs/sacsng.h @@ -179,6 +179,10 @@ */ #define MDIO_PORT 2 /* Port A=0, B=1, C=2, D=3 */ +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE + #define MDIO_ACTIVE (iop->pdir |= 0x40000000) #define MDIO_TRISTATE (iop->pdir &= ~0x40000000) #define MDIO_READ ((iop->pdat & 0x40000000) != 0) diff --git a/include/configs/sbc8260.h b/include/configs/sbc8260.h index 26ed55795e..3fa80a80ec 100644 --- a/include/configs/sbc8260.h +++ b/include/configs/sbc8260.h @@ -201,6 +201,10 @@ * Port pins used for bit-banged MII communictions (if applicable). */ #define MDIO_PORT 2 /* Port C */ +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE + #define MDIO_ACTIVE (iop->pdir |= 0x00400000) #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) #define MDIO_READ ((iop->pdat & 0x00400000) != 0) diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index a6b15f74c9..dab4f801d8 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -293,6 +293,10 @@ * GPIO pins used for bit-banged MII communications */ #define MDIO_PORT 2 /* Port C */ + #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) + #define MDC_DECLARE MDIO_DECLARE + #define MDIO_ACTIVE (iop->pdir |= 0x00400000) #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) #define MDIO_READ ((iop->pdat & 0x00400000) != 0) diff --git a/include/configs/versatile.h b/include/configs/versatile.h index a9b70cc367..4273b84a44 100644 --- a/include/configs/versatile.h +++ b/include/configs/versatile.h @@ -82,7 +82,8 @@ * Hardware drivers */ -#define CONFIG_DRIVER_SMC91111 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 #define CONFIG_SMC_USE_32_BIT #define CONFIG_SMC91111_BASE 0x10010000 #undef CONFIG_SMC91111_EXT_PHY diff --git a/include/configs/voiceblue.h b/include/configs/voiceblue.h index c9c3132355..0dde65d12a 100644 --- a/include/configs/voiceblue.h +++ b/include/configs/voiceblue.h @@ -94,7 +94,8 @@ /* * Hardware drivers */ -#define CONFIG_DRIVER_SMC91111 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 #define CONFIG_SMC91111_BASE 0x08000300 #define CONFIG_HARD_I2C diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h index 83883f6fd5..1329f0f3d8 100644 --- a/include/configs/xaeniax.h +++ b/include/configs/xaeniax.h @@ -196,7 +196,8 @@ /* * SMSC91C111 Network Card */ -#define CONFIG_DRIVER_SMC91111 1 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 1 #define CONFIG_SMC91111_BASE 0x10000300 /* chip select 3 */ #define CONFIG_SMC_USE_32_BIT 1 /* 32 bit bus */ #undef CONFIG_SMC_91111_EXT_PHY /* we use internal phy */ diff --git a/include/configs/xm250.h b/include/configs/xm250.h index f18701abf5..cd56ce72e7 100644 --- a/include/configs/xm250.h +++ b/include/configs/xm250.h @@ -50,7 +50,8 @@ /* * Hardware drivers */ -#define CONFIG_DRIVER_SMC91111 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 #define CONFIG_SMC91111_BASE 0x04000300 #undef CONFIG_SMC91111_EXT_PHY #define CONFIG_SMC_USE_32_BIT diff --git a/include/configs/xsengine.h b/include/configs/xsengine.h index 2697ccaf62..f68461bb22 100644 --- a/include/configs/xsengine.h +++ b/include/configs/xsengine.h @@ -94,7 +94,8 @@ #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ /* Hardware drivers */ -#define CONFIG_DRIVER_SMC91111 +#define CONFIG_NET_MULTI +#define CONFIG_SMC91111 #define CONFIG_SMC91111_BASE 0x04000300 #define CONFIG_SMC_USE_32_BIT 1 diff --git a/include/configs/zylonite.h b/include/configs/zylonite.h index 86b6ea1e18..36c341e7c2 100644 --- a/include/configs/zylonite.h +++ b/include/configs/zylonite.h @@ -62,7 +62,7 @@ #undef TURN_ON_ETHERNET #ifdef TURN_ON_ETHERNET -# define CONFIG_DRIVER_SMC91111 1 +# define CONFIG_SMC91111 1 # define CONFIG_SMC91111_BASE 0x14000300 # define CONFIG_SMC91111_EXT_PHY # define CONFIG_SMC_USE_32_BIT diff --git a/include/exports.h b/include/exports.h index 16ea03a6bd..2e8fd8b8b4 100644 --- a/include/exports.h +++ b/include/exports.h @@ -47,7 +47,7 @@ enum { XF_MAX }; -#define XF_VERSION 5 +#define XF_VERSION 6 #if defined(CONFIG_I386) extern gd_t *global_data; diff --git a/include/fpga.h b/include/fpga.h index a48b89b3c5..84d7b9fc1a 100644 --- a/include/fpga.h +++ b/include/fpga.h @@ -71,7 +71,7 @@ typedef struct { /* typedef fpga_desc */ /* root function definitions */ -extern void fpga_init( ulong reloc_off ); +extern void fpga_init( void ); extern int fpga_add( fpga_type devtype, void *desc ); extern int fpga_count( void ); extern int fpga_load( int devnum, void *buf, size_t bsize ); diff --git a/include/linux/mtd/samsung_onenand.h b/include/linux/mtd/samsung_onenand.h index 9865780d40..021fa27f7d 100644 --- a/include/linux/mtd/samsung_onenand.h +++ b/include/linux/mtd/samsung_onenand.h @@ -31,75 +31,75 @@ #ifndef __ASSEMBLY__ struct samsung_onenand { - unsigned long mem_cfg; /* 0x0000 */ + unsigned int mem_cfg; /* 0x0000 */ unsigned char res1[0xc]; - unsigned long burst_len; /* 0x0010 */ + unsigned int burst_len; /* 0x0010 */ unsigned char res2[0xc]; - unsigned long mem_reset; /* 0x0020 */ + unsigned int mem_reset; /* 0x0020 */ unsigned char res3[0xc]; - unsigned long int_err_stat; /* 0x0030 */ + unsigned int int_err_stat; /* 0x0030 */ unsigned char res4[0xc]; - unsigned long int_err_mask; /* 0x0040 */ + unsigned int int_err_mask; /* 0x0040 */ unsigned char res5[0xc]; - unsigned long int_err_ack; /* 0x0050 */ + unsigned int int_err_ack; /* 0x0050 */ unsigned char res6[0xc]; - unsigned long ecc_err_stat; /* 0x0060 */ + unsigned int ecc_err_stat; /* 0x0060 */ unsigned char res7[0xc]; - unsigned long manufact_id; /* 0x0070 */ + unsigned int manufact_id; /* 0x0070 */ unsigned char res8[0xc]; - unsigned long device_id; /* 0x0080 */ + unsigned int device_id; /* 0x0080 */ unsigned char res9[0xc]; - unsigned long data_buf_size; /* 0x0090 */ + unsigned int data_buf_size; /* 0x0090 */ unsigned char res10[0xc]; - unsigned long boot_buf_size; /* 0x00A0 */ + unsigned int boot_buf_size; /* 0x00A0 */ unsigned char res11[0xc]; - unsigned long buf_amount; /* 0x00B0 */ + unsigned int buf_amount; /* 0x00B0 */ unsigned char res12[0xc]; - unsigned long tech; /* 0x00C0 */ + unsigned int tech; /* 0x00C0 */ unsigned char res13[0xc]; - unsigned long fba; /* 0x00D0 */ + unsigned int fba; /* 0x00D0 */ unsigned char res14[0xc]; - unsigned long fpa; /* 0x00E0 */ + unsigned int fpa; /* 0x00E0 */ unsigned char res15[0xc]; - unsigned long fsa; /* 0x00F0 */ + unsigned int fsa; /* 0x00F0 */ unsigned char res16[0x3c]; - unsigned long sync_mode; /* 0x0130 */ + unsigned int sync_mode; /* 0x0130 */ unsigned char res17[0xc]; - unsigned long trans_spare; /* 0x0140 */ + unsigned int trans_spare; /* 0x0140 */ unsigned char res18[0x3c]; - unsigned long err_page_addr; /* 0x0180 */ + unsigned int err_page_addr; /* 0x0180 */ unsigned char res19[0x1c]; - unsigned long int_pin_en; /* 0x01A0 */ + unsigned int int_pin_en; /* 0x01A0 */ unsigned char res20[0x1c]; - unsigned long acc_clock; /* 0x01C0 */ + unsigned int acc_clock; /* 0x01C0 */ unsigned char res21[0x1c]; - unsigned long err_blk_addr; /* 0x01E0 */ + unsigned int err_blk_addr; /* 0x01E0 */ unsigned char res22[0xc]; - unsigned long flash_ver_id; /* 0x01F0 */ + unsigned int flash_ver_id; /* 0x01F0 */ unsigned char res23[0x6c]; - unsigned long watchdog_cnt_low; /* 0x0260 */ + unsigned int watchdog_cnt_low; /* 0x0260 */ unsigned char res24[0xc]; - unsigned long watchdog_cnt_hi; /* 0x0270 */ + unsigned int watchdog_cnt_hi; /* 0x0270 */ unsigned char res25[0xc]; - unsigned long sync_write; /* 0x0280 */ + unsigned int sync_write; /* 0x0280 */ unsigned char res26[0x1c]; - unsigned long cold_reset; /* 0x02A0 */ + unsigned int cold_reset; /* 0x02A0 */ unsigned char res27[0xc]; - unsigned long ddp_device; /* 0x02B0 */ + unsigned int ddp_device; /* 0x02B0 */ unsigned char res28[0xc]; - unsigned long multi_plane; /* 0x02C0 */ + unsigned int multi_plane; /* 0x02C0 */ unsigned char res29[0x1c]; - unsigned long trans_mode; /* 0x02E0 */ + unsigned int trans_mode; /* 0x02E0 */ unsigned char res30[0x1c]; - unsigned long ecc_err_stat2; /* 0x0300 */ + unsigned int ecc_err_stat2; /* 0x0300 */ unsigned char res31[0xc]; - unsigned long ecc_err_stat3; /* 0x0310 */ + unsigned int ecc_err_stat3; /* 0x0310 */ unsigned char res32[0xc]; - unsigned long ecc_err_stat4; /* 0x0320 */ + unsigned int ecc_err_stat4; /* 0x0320 */ unsigned char res33[0x1c]; - unsigned long dev_page_size; /* 0x0340 */ + unsigned int dev_page_size; /* 0x0340 */ unsigned char res34[0x4c]; - unsigned long int_mon_status; /* 0x0390 */ + unsigned int int_mon_status; /* 0x0390 */ }; #endif diff --git a/include/miiphy.h b/include/miiphy.h index fa33ec7f71..5362125233 100644 --- a/include/miiphy.h +++ b/include/miiphy.h @@ -19,6 +19,8 @@ | | COPYRIGHT I B M CORPORATION 1999 | LICENSED MATERIAL - PROGRAM PROPERTY OF I B M +| +| Additions (C) Copyright 2009 Industrie Dial Face S.p.A. +----------------------------------------------------------------------------*/ /*----------------------------------------------------------------------------+ | @@ -61,12 +63,33 @@ char *miiphy_get_current_dev (void); void miiphy_listdev (void); -#define BB_MII_DEVNAME "bbmii" +#ifdef CONFIG_BITBANGMII + +#define BB_MII_DEVNAME "bb_miiphy" + +struct bb_miiphy_bus { + char name[NAMESIZE]; + int (*init)(struct bb_miiphy_bus *bus); + int (*mdio_active)(struct bb_miiphy_bus *bus); + int (*mdio_tristate)(struct bb_miiphy_bus *bus); + int (*set_mdio)(struct bb_miiphy_bus *bus, int v); + int (*get_mdio)(struct bb_miiphy_bus *bus, int *v); + int (*set_mdc)(struct bb_miiphy_bus *bus, int v); + int (*delay)(struct bb_miiphy_bus *bus); +#ifdef CONFIG_BITBANGMII_MULTI + void *priv; +#endif +}; + +extern struct bb_miiphy_bus bb_miiphy_buses[]; +extern int bb_miiphy_buses_num; +void bb_miiphy_init (void); int bb_miiphy_read (char *devname, unsigned char addr, unsigned char reg, unsigned short *value); int bb_miiphy_write (char *devname, unsigned char addr, unsigned char reg, unsigned short value); +#endif /* phy seed setup */ #define AUTO 99 diff --git a/include/net.h b/include/net.h index 4873000c0d..1c8ab12454 100644 --- a/include/net.h +++ b/include/net.h @@ -517,6 +517,9 @@ extern ushort getenv_VLAN(char *); /* copy a filename (allow for "..." notation, limit length) */ extern void copy_filename (char *dst, char *src, int size); +/* get a random source port */ +extern unsigned int random_port(void); + /**********************************************************************/ #endif /* __NET_H__ */ diff --git a/include/netdev.h b/include/netdev.h index a50ec67d53..a91368e666 100644 --- a/include/netdev.h +++ b/include/netdev.h @@ -75,6 +75,7 @@ int rtl8169_initialize(bd_t *bis); int scc_initialize(bd_t *bis); int skge_initialize(bd_t *bis); int smc911x_initialize(u8 dev_num, int base_addr); +int smc91111_initialize(u8 dev_num, int base_addr); int tsi108_eth_initialize(bd_t *bis); int uec_initialize(int index); int uec_standard_init(bd_t *bis); diff --git a/include/post.h b/include/post.h index fe96312cb0..9fcd3cec2f 100644 --- a/include/post.h +++ b/include/post.h @@ -73,7 +73,9 @@ void post_output_backlog ( void ); int post_run (char *name, int flags); int post_info (char *name); int post_log (char *format, ...); +#ifndef CONFIG_RELOC_FIXUP_WORKS void post_reloc (void); +#endif unsigned long post_time_ms (unsigned long base); extern struct post_test post_list[]; diff --git a/include/ppc405.h b/include/ppc405.h index 5e56897819..508c77b14e 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -29,9 +29,9 @@ #define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1) #ifndef CONFIG_IOP480 -#define CONFIG_SYS_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */ +#define CONFIG_SYS_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */ #else -#define CONFIG_SYS_DCACHE_SIZE (2 << 10) /* For PLX IOP480 (403) */ +#define CONFIG_SYS_DCACHE_SIZE (2 << 10) /* For PLX IOP480(403)*/ #endif /****************************************************************************** @@ -71,10 +71,10 @@ * Decompression Controller ******************************************************************************/ #define DECOMP_DCR_BASE 0x14 -#define KIAR (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */ -#define KIDR (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */ +#define KIAR (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */ +#define KIDR (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */ /* values for kiar register - indirect addressing of these regs */ -#define KCONF 0x40 /* decompression core config register */ +#define KCONF 0x40 /* decompression core config register */ #endif /****************************************************************************** @@ -85,61 +85,61 @@ #else #define POWERMAN_DCR_BASE 0xb8 #endif -#define CPMSR (POWERMAN_DCR_BASE+0x0) /* Power management status */ -#define CPMER (POWERMAN_DCR_BASE+0x1) /* Power management enable */ -#define CPMFR (POWERMAN_DCR_BASE+0x2) /* Power management force */ +#define CPMSR (POWERMAN_DCR_BASE+0x0) /* Power management status */ +#define CPMER (POWERMAN_DCR_BASE+0x1) /* Power management enable */ +#define CPMFR (POWERMAN_DCR_BASE+0x2) /* Power management force */ /****************************************************************************** * Extrnal Bus Controller ******************************************************************************/ /* values for EBC0_CFGADDR register - indirect addressing of these regs */ - #define PB0CR 0x00 /* periph bank 0 config reg */ - #define PB1CR 0x01 /* periph bank 1 config reg */ - #define PB2CR 0x02 /* periph bank 2 config reg */ - #define PB3CR 0x03 /* periph bank 3 config reg */ - #define PB4CR 0x04 /* periph bank 4 config reg */ + #define PB0CR 0x00 /* periph bank 0 config reg */ + #define PB1CR 0x01 /* periph bank 1 config reg */ + #define PB2CR 0x02 /* periph bank 2 config reg */ + #define PB3CR 0x03 /* periph bank 3 config reg */ + #define PB4CR 0x04 /* periph bank 4 config reg */ #ifndef CONFIG_405EP - #define PB5CR 0x05 /* periph bank 5 config reg */ - #define PB6CR 0x06 /* periph bank 6 config reg */ - #define PB7CR 0x07 /* periph bank 7 config reg */ + #define PB5CR 0x05 /* periph bank 5 config reg */ + #define PB6CR 0x06 /* periph bank 6 config reg */ + #define PB7CR 0x07 /* periph bank 7 config reg */ #endif - #define PB0AP 0x10 /* periph bank 0 access parameters */ - #define PB1AP 0x11 /* periph bank 1 access parameters */ - #define PB2AP 0x12 /* periph bank 2 access parameters */ - #define PB3AP 0x13 /* periph bank 3 access parameters */ - #define PB4AP 0x14 /* periph bank 4 access parameters */ + #define PB0AP 0x10 /* periph bank 0 access parameters */ + #define PB1AP 0x11 /* periph bank 1 access parameters */ + #define PB2AP 0x12 /* periph bank 2 access parameters */ + #define PB3AP 0x13 /* periph bank 3 access parameters */ + #define PB4AP 0x14 /* periph bank 4 access parameters */ #ifndef CONFIG_405EP - #define PB5AP 0x15 /* periph bank 5 access parameters */ - #define PB6AP 0x16 /* periph bank 6 access parameters */ - #define PB7AP 0x17 /* periph bank 7 access parameters */ + #define PB5AP 0x15 /* periph bank 5 access parameters */ + #define PB6AP 0x16 /* periph bank 6 access parameters */ + #define PB7AP 0x17 /* periph bank 7 access parameters */ #endif - #define PBEAR 0x20 /* periph bus error addr reg */ - #define PBESR0 0x21 /* periph bus error status reg 0 */ - #define PBESR1 0x22 /* periph bus error status reg 1 */ -#define EBC0_CFG 0x23 /* external bus configuration reg */ + #define PBEAR 0x20 /* periph bus error addr reg */ + #define PBESR0 0x21 /* periph bus error status reg 0 */ + #define PBESR1 0x22 /* periph bus error status reg 1 */ +#define EBC0_CFG 0x23 /* external bus configuration reg */ #ifdef CONFIG_405EP /****************************************************************************** * Control ******************************************************************************/ #define CNTRL_DCR_BASE 0x0f0 -#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ -#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Clock status register */ -#define CPC0_EPCTL (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ -#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ -#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART control register */ -#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI control register */ - -#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ -#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ -#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ -#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/ -#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ -#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ -#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ -#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ -#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ -#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ +#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ +#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Clock status register */ +#define CPC0_EPCTL (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ +#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ +#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART control register */ +#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI control register */ + +#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ +#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ +#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ +#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */ +#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ +#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ +#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ +#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ +#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ +#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ /* Bit definitions */ #define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */ @@ -160,13 +160,13 @@ #define PLLMR0_OPB_PLB_DIV_3 0x00002000 #define PLLMR0_OPB_PLB_DIV_4 0x00003000 -#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */ +#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */ #define PLLMR0_EXB_PLB_DIV_2 0x00000000 #define PLLMR0_EXB_PLB_DIV_3 0x00000100 #define PLLMR0_EXB_PLB_DIV_4 0x00000200 #define PLLMR0_EXB_PLB_DIV_5 0x00000300 -#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */ +#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */ #define PLLMR0_MAL_PLB_DIV_1 0x00000000 #define PLLMR0_MAL_PLB_DIV_2 0x00000010 #define PLLMR0_MAL_PLB_DIV_3 0x00000020 @@ -180,7 +180,7 @@ #define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */ #define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */ -#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */ +#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */ #define PLLMR1_FBMUL_DIV_16 0x00000000 #define PLLMR1_FBMUL_DIV_1 0x00100000 #define PLLMR1_FBMUL_DIV_2 0x00200000 @@ -198,7 +198,7 @@ #define PLLMR1_FBMUL_DIV_14 0x00E00000 #define PLLMR1_FBMUL_DIV_15 0x00F00000 -#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */ +#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */ #define PLLMR1_FWDVA_DIV_8 0x00000000 #define PLLMR1_FWDVA_DIV_7 0x00010000 #define PLLMR1_FWDVA_DIV_6 0x00020000 @@ -207,132 +207,132 @@ #define PLLMR1_FWDVA_DIV_3 0x00050000 #define PLLMR1_FWDVA_DIV_2 0x00060000 #define PLLMR1_FWDVA_DIV_1 0x00070000 -#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */ -#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */ +#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */ +#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */ /* Defines for CPC0_EPRCSR register */ -#define CPC0_EPRCSR_E0NFE 0x80000000 -#define CPC0_EPRCSR_E1NFE 0x40000000 -#define CPC0_EPRCSR_E1RPP 0x00000080 -#define CPC0_EPRCSR_E0RPP 0x00000040 -#define CPC0_EPRCSR_E1ERP 0x00000020 -#define CPC0_EPRCSR_E0ERP 0x00000010 -#define CPC0_EPRCSR_E1PCI 0x00000002 -#define CPC0_EPRCSR_E0PCI 0x00000001 +#define CPC0_EPRCSR_E0NFE 0x80000000 +#define CPC0_EPRCSR_E1NFE 0x40000000 +#define CPC0_EPRCSR_E1RPP 0x00000080 +#define CPC0_EPRCSR_E0RPP 0x00000040 +#define CPC0_EPRCSR_E1ERP 0x00000020 +#define CPC0_EPRCSR_E0ERP 0x00000010 +#define CPC0_EPRCSR_E1PCI 0x00000002 +#define CPC0_EPRCSR_E0PCI 0x00000001 /* Defines for CPC0_PCI Register */ -#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */ -#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */ -#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled*/ +#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */ +#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */ +#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled */ /* Defines for CPC0_BOOR Register */ -#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */ +#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */ /* Defines for CPC0_PLLMR1 Register fields */ -#define PLL_ACTIVE 0x80000000 -#define CPC0_PLLMR1_SSCS 0x80000000 -#define PLL_RESET 0x40000000 -#define CPC0_PLLMR1_PLLR 0x40000000 - /* Feedback multiplier */ -#define PLL_FBKDIV 0x00F00000 -#define CPC0_PLLMR1_FBDV 0x00F00000 -#define PLL_FBKDIV_16 0x00000000 -#define PLL_FBKDIV_1 0x00100000 -#define PLL_FBKDIV_2 0x00200000 -#define PLL_FBKDIV_3 0x00300000 -#define PLL_FBKDIV_4 0x00400000 -#define PLL_FBKDIV_5 0x00500000 -#define PLL_FBKDIV_6 0x00600000 -#define PLL_FBKDIV_7 0x00700000 -#define PLL_FBKDIV_8 0x00800000 -#define PLL_FBKDIV_9 0x00900000 -#define PLL_FBKDIV_10 0x00A00000 -#define PLL_FBKDIV_11 0x00B00000 -#define PLL_FBKDIV_12 0x00C00000 -#define PLL_FBKDIV_13 0x00D00000 -#define PLL_FBKDIV_14 0x00E00000 -#define PLL_FBKDIV_15 0x00F00000 - /* Forward A divisor */ -#define PLL_FWDDIVA 0x00070000 -#define CPC0_PLLMR1_FWDVA 0x00070000 -#define PLL_FWDDIVA_8 0x00000000 -#define PLL_FWDDIVA_7 0x00010000 -#define PLL_FWDDIVA_6 0x00020000 -#define PLL_FWDDIVA_5 0x00030000 -#define PLL_FWDDIVA_4 0x00040000 -#define PLL_FWDDIVA_3 0x00050000 -#define PLL_FWDDIVA_2 0x00060000 -#define PLL_FWDDIVA_1 0x00070000 - /* Forward B divisor */ -#define PLL_FWDDIVB 0x00007000 -#define CPC0_PLLMR1_FWDVB 0x00007000 -#define PLL_FWDDIVB_8 0x00000000 -#define PLL_FWDDIVB_7 0x00001000 -#define PLL_FWDDIVB_6 0x00002000 -#define PLL_FWDDIVB_5 0x00003000 -#define PLL_FWDDIVB_4 0x00004000 -#define PLL_FWDDIVB_3 0x00005000 -#define PLL_FWDDIVB_2 0x00006000 -#define PLL_FWDDIVB_1 0x00007000 - /* PLL tune bits */ +#define PLL_ACTIVE 0x80000000 +#define CPC0_PLLMR1_SSCS 0x80000000 +#define PLL_RESET 0x40000000 +#define CPC0_PLLMR1_PLLR 0x40000000 + /* Feedback multiplier */ +#define PLL_FBKDIV 0x00F00000 +#define CPC0_PLLMR1_FBDV 0x00F00000 +#define PLL_FBKDIV_16 0x00000000 +#define PLL_FBKDIV_1 0x00100000 +#define PLL_FBKDIV_2 0x00200000 +#define PLL_FBKDIV_3 0x00300000 +#define PLL_FBKDIV_4 0x00400000 +#define PLL_FBKDIV_5 0x00500000 +#define PLL_FBKDIV_6 0x00600000 +#define PLL_FBKDIV_7 0x00700000 +#define PLL_FBKDIV_8 0x00800000 +#define PLL_FBKDIV_9 0x00900000 +#define PLL_FBKDIV_10 0x00A00000 +#define PLL_FBKDIV_11 0x00B00000 +#define PLL_FBKDIV_12 0x00C00000 +#define PLL_FBKDIV_13 0x00D00000 +#define PLL_FBKDIV_14 0x00E00000 +#define PLL_FBKDIV_15 0x00F00000 + /* Forward A divisor */ +#define PLL_FWDDIVA 0x00070000 +#define CPC0_PLLMR1_FWDVA 0x00070000 +#define PLL_FWDDIVA_8 0x00000000 +#define PLL_FWDDIVA_7 0x00010000 +#define PLL_FWDDIVA_6 0x00020000 +#define PLL_FWDDIVA_5 0x00030000 +#define PLL_FWDDIVA_4 0x00040000 +#define PLL_FWDDIVA_3 0x00050000 +#define PLL_FWDDIVA_2 0x00060000 +#define PLL_FWDDIVA_1 0x00070000 + /* Forward B divisor */ +#define PLL_FWDDIVB 0x00007000 +#define CPC0_PLLMR1_FWDVB 0x00007000 +#define PLL_FWDDIVB_8 0x00000000 +#define PLL_FWDDIVB_7 0x00001000 +#define PLL_FWDDIVB_6 0x00002000 +#define PLL_FWDDIVB_5 0x00003000 +#define PLL_FWDDIVB_4 0x00004000 +#define PLL_FWDDIVB_3 0x00005000 +#define PLL_FWDDIVB_2 0x00006000 +#define PLL_FWDDIVB_1 0x00007000 + /* PLL tune bits */ #define PLL_TUNE_MASK 0x000003FF -#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ -#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ -#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ -#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ -#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ -#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ -#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ +#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ +#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ +#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ +#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ +#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ +#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ +#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ /* Defines for CPC0_PLLMR0 Register fields */ - /* CPU divisor */ -#define PLL_CPUDIV 0x00300000 -#define CPC0_PLLMR0_CCDV 0x00300000 -#define PLL_CPUDIV_1 0x00000000 -#define PLL_CPUDIV_2 0x00100000 -#define PLL_CPUDIV_3 0x00200000 -#define PLL_CPUDIV_4 0x00300000 - /* PLB divisor */ -#define PLL_PLBDIV 0x00030000 -#define CPC0_PLLMR0_CBDV 0x00030000 -#define PLL_PLBDIV_1 0x00000000 -#define PLL_PLBDIV_2 0x00010000 -#define PLL_PLBDIV_3 0x00020000 -#define PLL_PLBDIV_4 0x00030000 - /* OPB divisor */ -#define PLL_OPBDIV 0x00003000 -#define CPC0_PLLMR0_OPDV 0x00003000 -#define PLL_OPBDIV_1 0x00000000 -#define PLL_OPBDIV_2 0x00001000 -#define PLL_OPBDIV_3 0x00002000 -#define PLL_OPBDIV_4 0x00003000 - /* EBC divisor */ -#define PLL_EXTBUSDIV 0x00000300 -#define CPC0_PLLMR0_EPDV 0x00000300 -#define PLL_EXTBUSDIV_2 0x00000000 -#define PLL_EXTBUSDIV_3 0x00000100 -#define PLL_EXTBUSDIV_4 0x00000200 -#define PLL_EXTBUSDIV_5 0x00000300 - /* MAL divisor */ -#define PLL_MALDIV 0x00000030 -#define CPC0_PLLMR0_MPDV 0x00000030 -#define PLL_MALDIV_1 0x00000000 -#define PLL_MALDIV_2 0x00000010 -#define PLL_MALDIV_3 0x00000020 -#define PLL_MALDIV_4 0x00000030 - /* PCI divisor */ -#define PLL_PCIDIV 0x00000003 -#define CPC0_PLLMR0_PPFD 0x00000003 -#define PLL_PCIDIV_1 0x00000000 -#define PLL_PCIDIV_2 0x00000001 -#define PLL_PCIDIV_3 0x00000002 -#define PLL_PCIDIV_4 0x00000003 + /* CPU divisor */ +#define PLL_CPUDIV 0x00300000 +#define CPC0_PLLMR0_CCDV 0x00300000 +#define PLL_CPUDIV_1 0x00000000 +#define PLL_CPUDIV_2 0x00100000 +#define PLL_CPUDIV_3 0x00200000 +#define PLL_CPUDIV_4 0x00300000 + /* PLB divisor */ +#define PLL_PLBDIV 0x00030000 +#define CPC0_PLLMR0_CBDV 0x00030000 +#define PLL_PLBDIV_1 0x00000000 +#define PLL_PLBDIV_2 0x00010000 +#define PLL_PLBDIV_3 0x00020000 +#define PLL_PLBDIV_4 0x00030000 + /* OPB divisor */ +#define PLL_OPBDIV 0x00003000 +#define CPC0_PLLMR0_OPDV 0x00003000 +#define PLL_OPBDIV_1 0x00000000 +#define PLL_OPBDIV_2 0x00001000 +#define PLL_OPBDIV_3 0x00002000 +#define PLL_OPBDIV_4 0x00003000 + /* EBC divisor */ +#define PLL_EXTBUSDIV 0x00000300 +#define CPC0_PLLMR0_EPDV 0x00000300 +#define PLL_EXTBUSDIV_2 0x00000000 +#define PLL_EXTBUSDIV_3 0x00000100 +#define PLL_EXTBUSDIV_4 0x00000200 +#define PLL_EXTBUSDIV_5 0x00000300 + /* MAL divisor */ +#define PLL_MALDIV 0x00000030 +#define CPC0_PLLMR0_MPDV 0x00000030 +#define PLL_MALDIV_1 0x00000000 +#define PLL_MALDIV_2 0x00000010 +#define PLL_MALDIV_3 0x00000020 +#define PLL_MALDIV_4 0x00000030 + /* PCI divisor */ +#define PLL_PCIDIV 0x00000003 +#define CPC0_PLLMR0_PPFD 0x00000003 +#define PLL_PCIDIV_1 0x00000000 +#define PLL_PCIDIV_2 0x00000001 +#define PLL_PCIDIV_3 0x00000002 +#define PLL_PCIDIV_4 0x00000003 /* - *------------------------------------------------------------------------------- + *------------------------------------------------------------------------------ * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, * assuming a 33.3MHz input clock to the 405EP. - *------------------------------------------------------------------------------- + *------------------------------------------------------------------------------ */ #define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ @@ -427,25 +427,25 @@ #define CPC0_PERD1 0x0e1 /* CPR_PERD1 */ #define CPC0_PERC0 0x180 /* CPR_PERC0 */ -#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */ -#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ -#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */ +#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */ +#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ +#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */ -#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ +#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ -#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */ -#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */ -#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */ +#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */ +#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */ +#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */ -#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */ -#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */ -#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */ -#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */ +#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */ +#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */ +#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */ +#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */ -#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */ -#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */ -#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */ -#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */ +#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */ +#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */ +#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */ +#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */ #else /* #ifdef CONFIG_405EP */ /****************************************************************************** @@ -462,13 +462,13 @@ #define CPC0_ECR 0xaa /* edge conditioner register */ /* Bit definitions */ -#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ +#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ #define PLLMR_FWD_DIV_BYPASS 0xE0000000 #define PLLMR_FWD_DIV_3 0xA0000000 #define PLLMR_FWD_DIV_4 0x80000000 #define PLLMR_FWD_DIV_6 0x40000000 -#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */ +#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */ #define PLLMR_FB_DIV_1 0x02000000 #define PLLMR_FB_DIV_2 0x04000000 #define PLLMR_FB_DIV_3 0x06000000 @@ -476,32 +476,32 @@ #define PLLMR_TUNING_MASK 0x01F80000 -#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */ +#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */ #define PLLMR_CPU_PLB_DIV_1 0x00000000 #define PLLMR_CPU_PLB_DIV_2 0x00020000 #define PLLMR_CPU_PLB_DIV_3 0x00040000 #define PLLMR_CPU_PLB_DIV_4 0x00060000 -#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */ +#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */ #define PLLMR_OPB_PLB_DIV_1 0x00000000 #define PLLMR_OPB_PLB_DIV_2 0x00008000 #define PLLMR_OPB_PLB_DIV_3 0x00010000 #define PLLMR_OPB_PLB_DIV_4 0x00018000 -#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */ +#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */ #define PLLMR_PCI_PLB_DIV_1 0x00000000 #define PLLMR_PCI_PLB_DIV_2 0x00002000 #define PLLMR_PCI_PLB_DIV_3 0x00004000 #define PLLMR_PCI_PLB_DIV_4 0x00006000 -#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */ +#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */ #define PLLMR_EXB_PLB_DIV_2 0x00000000 #define PLLMR_EXB_PLB_DIV_3 0x00000800 #define PLLMR_EXB_PLB_DIV_4 0x00001000 #define PLLMR_EXB_PLB_DIV_5 0x00001800 /* definitions for PPC405GPr (new mode strapping) */ -#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */ +#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */ #define PSR_PLL_FWD_MASK 0xC0000000 #define PSR_PLL_FDBACK_MASK 0x30000000 @@ -513,15 +513,15 @@ #define PSR_ROM_WIDTH_MASK 0x00018000 #define PSR_ROM_LOC 0x00004000 #define PSR_PCI_ASYNC_EN 0x00001000 -#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */ +#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */ #define PSR_PCI_ARBIT_EN 0x00000400 -#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */ +#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */ #ifndef CONFIG_IOP480 /* * PLL Voltage Controlled Oscillator (VCO) definitions * Maximum and minimum values (in MHz) for correct PLL operation. - */ +*/ #define VCO_MIN 400 #define VCO_MAX 800 #endif /* #ifndef CONFIG_IOP480 */ @@ -535,35 +535,35 @@ #else #define MAL_DCR_BASE 0x180 #endif -#define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */ -#define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Err Status (Read/Clear)*/ -#define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */ -#define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set)*/ -#define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset)*/ -#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status*/ -#define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int reg */ -#define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */ -#define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */ -#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status*/ -#define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int reg */ -#define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table ptr */ -#define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table ptr */ -#define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table ptr */ -#define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table ptr */ -#define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table ptr */ -#define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table ptr */ -#define MAL0_RXCTP2R (MAL_DCR_BASE + 0x42) /* RX 2 Channel table ptr */ -#define MAL0_RXCTP3R (MAL_DCR_BASE + 0x43) /* RX 3 Channel table ptr */ -#define MAL0_RXCTP8R (MAL_DCR_BASE + 0x48) /* RX 8 Channel table ptr */ -#define MAL0_RXCTP16R (MAL_DCR_BASE + 0x50) /* RX 16 Channel table ptr */ -#define MAL0_RXCTP24R (MAL_DCR_BASE + 0x58) /* RX 24 Channel table ptr */ -#define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */ -#define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */ -#define MAL0_RCBS2 (MAL_DCR_BASE + 0x62) /* RX 2 Channel buffer size */ -#define MAL0_RCBS3 (MAL_DCR_BASE + 0x63) /* RX 3 Channel buffer size */ -#define MAL0_RCBS8 (MAL_DCR_BASE + 0x68) /* RX 8 Channel buffer size */ -#define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */ -#define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */ +#define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */ +#define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Err Status (Read/Clear) */ +#define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */ +#define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ +#define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset) */ +#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status */ +#define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int reg */ +#define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */ +#define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */ +#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status */ +#define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int reg */ +#define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table ptr */ +#define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table ptr */ +#define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table ptr */ +#define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table ptr */ +#define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table ptr */ +#define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table ptr */ +#define MAL0_RXCTP2R (MAL_DCR_BASE + 0x42) /* RX 2 Channel table ptr */ +#define MAL0_RXCTP3R (MAL_DCR_BASE + 0x43) /* RX 3 Channel table ptr */ +#define MAL0_RXCTP8R (MAL_DCR_BASE + 0x48) /* RX 8 Channel table ptr */ +#define MAL0_RXCTP16R (MAL_DCR_BASE + 0x50) /* RX 16 Channel table ptr */ +#define MAL0_RXCTP24R (MAL_DCR_BASE + 0x58) /* RX 24 Channel table ptr */ +#define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */ +#define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */ +#define MAL0_RCBS2 (MAL_DCR_BASE + 0x62) /* RX 2 Channel buffer size */ +#define MAL0_RCBS3 (MAL_DCR_BASE + 0x63) /* RX 3 Channel buffer size */ +#define MAL0_RCBS8 (MAL_DCR_BASE + 0x68) /* RX 8 Channel buffer size */ +#define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */ +#define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */ /*----------------------------------------------------------------------------- | IIC Register Offsets @@ -578,7 +578,7 @@ #define IICEXTSTS 0x09 #define IICLSADR 0x0A #define IICHSADR 0x0B -#define IICCLKDIV 0x0C +#define IIC0_CLKDIV 0x0C #define IICINTRMSK 0x0D #define IICXFRCNT 0x0E #define IICXTCNTLSS 0x0F @@ -610,7 +610,7 @@ #define OCM0_DSRC2 (OCM_DCR_BASE + 0x09) /* OCM D-side Bank 2 Config */ #define OCM0_ISRC1 (OCM_DCR_BASE + 0x0A) /* OCM I-side Bank 1Config */ #define OCM0_ISRC2 (OCM_DCR_BASE + 0x0B) /* OCM I-side Bank 2 Config */ -#define OCM0_DISDPC (OCM_DCR_BASE + 0x0C) /* OCM D-/I-side Data Par Chk*/ +#define OCM0_DISDPC (OCM_DCR_BASE + 0x0C) /* OCM D-/I-side Data Par Chk */ #else #define OCM_DCR_BASE 0x018 #define OCM0_ISCNTL (OCM_DCR_BASE+0x01) /* OCM I-side control reg */ @@ -746,21 +746,21 @@ #define SDR0_MFR 0x4300 /* SDR0_MFR reg */ /* Defines for CPC0_EPRCSR register */ -#define CPC0_EPRCSR_E0NFE 0x80000000 -#define CPC0_EPRCSR_E1NFE 0x40000000 -#define CPC0_EPRCSR_E1RPP 0x00000080 -#define CPC0_EPRCSR_E0RPP 0x00000040 -#define CPC0_EPRCSR_E1ERP 0x00000020 -#define CPC0_EPRCSR_E0ERP 0x00000010 -#define CPC0_EPRCSR_E1PCI 0x00000002 -#define CPC0_EPRCSR_E0PCI 0x00000001 +#define CPC0_EPRCSR_E0NFE 0x80000000 +#define CPC0_EPRCSR_E1NFE 0x40000000 +#define CPC0_EPRCSR_E1RPP 0x00000080 +#define CPC0_EPRCSR_E0RPP 0x00000040 +#define CPC0_EPRCSR_E1ERP 0x00000020 +#define CPC0_EPRCSR_E0ERP 0x00000010 +#define CPC0_EPRCSR_E1PCI 0x00000002 +#define CPC0_EPRCSR_E0PCI 0x00000001 #define CPR0_CLKUPD 0x020 #define CPR0_PLLC 0x040 #define CPR0_PLLD 0x060 #define CPR0_CPUD 0x080 #define CPR0_PLBD 0x0a0 -#define CPR0_OPBD 0x0c0 +#define CPR0_OPBD0 0x0c0 #define CPR0_PERD 0x0e0 #define SDR0_PINSTP 0x0040 @@ -770,46 +770,46 @@ /* CUST0 Customer Configuration Register0 */ #define SDR0_CUST0 0x4000 -#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ -#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ -#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ -#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ - -#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ -#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ -#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ - -#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ -#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ -#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ - -#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ -#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) -#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) - -#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ -#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22) -#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03) - -#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ -#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ -#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ - -#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ -#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ -#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ - -#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ -#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) -#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF) - -#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ -#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ -#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */ -#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ -#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ -#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ -#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ +#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ +#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ +#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ +#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ + +#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ +#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ +#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ + +#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ +#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width= 16 Bit */ +#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width= 8 Bit */ + +#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ +#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) +#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) + +#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ +#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22) +#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03) + +#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ + +#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ +#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ +#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ + +#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ +#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) +#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF) + +#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Sel Gating Mask */ +#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Sel Gating Disable */ +#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Sel Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Sel0 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Sel1 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Sel2 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Sel3 Gating Enable */ #define SDR0_PFC0 0x4100 #define SDR0_PFC1 0x4101 diff --git a/include/ppc440.h b/include/ppc440.h index 378a9de20a..fe0db93b51 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -48,7 +48,7 @@ #ifndef __PPC440_H__ #define __PPC440_H__ -#define CONFIG_SYS_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */ +#define CONFIG_SYS_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */ /****************************************************************************** * DCRs & Related @@ -60,9 +60,9 @@ /* values for clkcfga register - indirect addressing of these regs */ #define CPR0_PLLC 0x0040 #define CPR0_PLLD 0x0060 -#define CPR0_PRIMAD 0x0080 -#define CPR0_PRIMBD 0x00a0 -#define CPR0_OPBD 0x00c0 +#define CPR0_PRIMAD0 0x0080 +#define CPR0_PRIMBD0 0x00a0 +#define CPR0_OPBD0 0x00c0 #define CPR0_PERD 0x00e0 #define CPR0_MALD 0x0100 #define CPR0_SPCID 0x0120 @@ -86,8 +86,8 @@ #define SDR0_XPLLC 0x01c1 #define SDR0_XPLLD 0x01c2 #define SDR0_SRST 0x0200 -#define SD0_AMP0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */ -#define SD0_AMP1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */ +#define SD0_AMP0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */ +#define SD0_AMP1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */ #if defined(CONFIG_460EX) || defined(CONFIG_460GT) #define SDR0_PCI0 0x01c0 #else @@ -100,7 +100,7 @@ #define SDR0_PFC1 0x4101 /* Pin Function 1 */ #define SDR0_MFR 0x4300 /* SDR0_MFR reg */ -#ifdef CONFIG_440GX +#if defined(CONFIG_440GX) #define SD0_AMP 0x0240 #define SDR0_XPLLC 0x01c1 #define SDR0_XPLLD 0x01c2 @@ -145,10 +145,10 @@ #define SDR0_XCR2 0x01c6 #define SDR0_XPLLC0 0x01c1 #define SDR0_XPLLD0 0x01c2 -#define SDR0_XPLLC1 0x01c4 /*notRCW - SG */ -#define SDR0_XPLLD1 0x01c5 /*notRCW - SG */ -#define SDR0_XPLLC2 0x01c7 /*notRCW - SG */ -#define SDR0_XPLLD2 0x01c8 /*notRCW - SG */ +#define SDR0_XPLLC1 0x01c4 /* notRCW - SG */ +#define SDR0_XPLLD1 0x01c5 /* notRCW - SG */ +#define SDR0_XPLLC2 0x01c7 /* notRCW - SG */ +#define SDR0_XPLLD2 0x01c8 /* dnotRCW - SG */ #define SD0_AMP0 0x0240 #define SD0_AMP1 0x0241 #define SDR0_CUST2 0x4004 @@ -187,80 +187,91 @@ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -/* PLB3 Arbiter */ + /* PLB3 Arbiter */ #define PLB3_DCR_BASE 0x070 #define PLB3_ACR (PLB3_DCR_BASE + 0x7) -/* PLB4 Arbiter - PowerPC440EP Pass1 */ + /* PLB4 Arbiter - PowerPC440EP Pass1 */ #define PLB4_DCR_BASE 0x080 #define PLB4_ACR (PLB4_DCR_BASE + 0x1) #define PLB4_ACR_WRP (0x80000000 >> 7) -/* Pin Function Control Register 1 */ + /* Pin Function Control Register 1 */ #define SDR0_PFC1 0x4101 -#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ -#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ -#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ -#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ -#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ -#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ -#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ -#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ -#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ -#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ -#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ -#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ -#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */ -#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ -#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ -#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */ -#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ -#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ -#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */ -#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */ -#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ -#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */ -#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */ -#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */ - -#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */ -#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */ -#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */ -#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */ - -/* USB Control Register */ +#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ +#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ +#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ +#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ +#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ +#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ +#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ +#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ +#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ +#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ +#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ +#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ +#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold + Req Selection */ +#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ +#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ +#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) + Selection */ +#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ +#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ +#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) + Selection */ +#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. + Selected */ +#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ +#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject + Selection */ +#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject + Disable */ +#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject + Enable */ + +#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor Enable + Selection */ +#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor + Enable */ +#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor + Enable */ +#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation + Gated In */ + + /* USB Control Register */ #define SDR0_USB0 0x0320 -#define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */ -#define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */ -#define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */ -#define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */ -#define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */ -#define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */ - -/* Miscealleneaous Function Reg. */ +#define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */ +#define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */ +#define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */ +#define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */ +#define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */ +#define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */ + + /* Miscealleneaous Function Reg. */ #define SDR0_MFR 0x4300 -#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */ -#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000 -#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */ -#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000 -#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ -#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ -#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ -#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */ -#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */ -#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ -#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ -#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) -#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3) - -#define SDR0_MFR_ERRATA3_EN0 0x00800000 -#define SDR0_MFR_ERRATA3_EN1 0x00400000 -#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */ -#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */ -#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */ -#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */ -#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */ +#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */ +#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000 +#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */ +#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000 +#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ +#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ +#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ +#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */ +#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */ +#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ +#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ +#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) +#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3) + +#define SDR0_MFR_ERRATA3_EN0 0x00800000 +#define SDR0_MFR_ERRATA3_EN1 0x00400000 +#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */ +#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Ena. on both EMAC3 0-1 */ +#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */ +#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */ +#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */ #define GPT0_COMP6 0x00000098 #define GPT0_COMP5 0x00000094 @@ -278,245 +289,296 @@ #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) #define SDR0_USB2D0CR 0x0320 -#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC Master Selection */ -#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection */ -#define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */ - -#define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface Selection */ -#define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */ -#define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */ - -#define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */ -#define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */ -#define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */ - -/* USB2 Host Control Register */ -#define SDR0_USB2H0CR 0x0340 -#define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface */ -#define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */ -#define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */ -#define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length Adjustment */ - -/* Pin Function Control Register 1 */ -#define SDR0_PFC1 0x4101 -#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ -#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ -#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ - -#define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select EMAC 0 */ -#define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII bridge */ -#define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */ -#define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII bridge */ -#define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII bridge */ -#define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII bridge */ -#define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII bridge */ -#define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII bridge */ - -#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ -#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ -#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ -#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ -#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ -#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ -#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ -#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ -#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ -#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */ -#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ -#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ -#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */ -#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ -#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ -#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */ -#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */ -#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ -#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */ -#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */ -#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */ - -#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */ -#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */ -#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */ -#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */ - -/* Ethernet PLL Configuration Register */ -#define SDR0_PFC2 0x4102 -#define SDR0_PFC2_TUNE_MASK 0x01FF8000 /* Loop stability tuning bits */ -#define SDR0_PFC2_MULTI_MASK 0x00007C00 /* Frequency multiplication selector */ -#define SDR0_PFC2_RANGEB_MASK 0x00000380 /* PLLOUTB/C frequency selector */ -#define SDR0_PFC2_RANGEA_MASK 0x00000071 /* PLLOUTA frequency selector */ - -#define SDR0_PFC2_SELECT_MASK 0xE0000000 /* Ethernet Pin select EMAC1 */ -#define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */ -#define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */ -#define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */ -#define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */ -#define SDR0_PFC2_SELECT_CONFIG_4 0xA0000000 /* 2xRGMII using RGMII bridge */ -#define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */ -#define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */ +#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC + Master Selection */ +#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection*/ +#define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */ + +#define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface + Selection */ +#define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */ +#define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */ + +#define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */ +#define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */ +#define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */ + + /* USB2 Host Control Register */ +#define SDR0_USB2H0CR 0x0340 +#define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface*/ +#define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */ +#define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */ +#define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length + Adjustment */ + + /* Pin Function Control Register 1 */ +#define SDR0_PFC1 0x4101 +#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ +#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ +#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ + +#define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select + EMAC 0 */ +#define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII + bridge */ +#define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII + bridge */ +#define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII + bridge */ +#define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII + bridge */ +#define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII + bridge */ +#define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII + bridge */ +#define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII + bridge */ + +#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ +#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ +#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ +#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ +#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ +#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ +#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ +#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ +#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ +#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req + Selection */ +#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ +#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ +#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) + Selection */ +#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ +#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ +#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) + Selection */ +#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */ +#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ +#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject + Selection */ +#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject + Disable */ +#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject + Enable */ + +#define SDR0_PFC1_PLB_PME_MASK 0x00001000 + /* PLB3/PLB4 Perf. Monitor En. Selection */ +#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 + /* PLB3 Performance Monitor Enable */ +#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 + /* PLB3 Performance Monitor Enable */ +#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation + Gated In */ + + /* Ethernet PLL Configuration Register */ +#define SDR0_PFC2 0x4102 +#define SDR0_PFC2_TUNE_MASK 0x01FF8000 /* Loop stability tuning bits */ +#define SDR0_PFC2_MULTI_MASK 0x00007C00 /* Frequency multiplication + selector */ +#define SDR0_PFC2_RANGEB_MASK 0x00000380 /* PLLOUTB/C frequency selector */ +#define SDR0_PFC2_RANGEA_MASK 0x00000071 /* PLLOUTA frequency selector */ + +#define SDR0_PFC2_SELECT_MASK 0xE0000000 /* Ethernet Pin select EMAC1 */ +#define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */ +#define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */ +#define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */ +#define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */ +#define SDR0_PFC2_SELECT_CONFIG_4 0xA0000000 /* 2xRGMII using RGMII bridge */ +#define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */ +#define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */ #define SDR0_PFC4 0x4104 -/* USB2PHY0 Control Register */ -#define SDR0_USB2PHY0CR 0x4103 -#define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 /* PHY UTMI interface connection */ -#define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */ -#define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */ - -#define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */ -#define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */ -#define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */ - -#define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000 /* VBus detect (Device mode only) */ -#define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000 /* Pull-up resistance on D+ is disabled */ -#define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000 /* Pull-up resistance on D+ is enabled */ - -#define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000 /* PHY UTMI data width and clock select */ -#define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */ -#define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */ - -#define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */ -#define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */ -#define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000 /* Loop back enabled (only test purposes) */ - -#define SDR0_USB2PHY0CR_XOON_MASK 0x04000000 /* Force XO block on during a suspend */ -#define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */ -#define SDR0_USB2PHY0CR_XO_OFF 0x04000000 /* PHY XO block is powered-off when all ports are suspended */ - -#define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */ -#define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */ -#define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only for full-speed operation */ - -#define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock source */ -#define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal 48M clock as a reference */ -#define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO block output as a reference */ - -#define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO block */ -#define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external clock */ -#define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock from a crystal */ - -#define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */ -#define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq = 12 MHz*/ -#define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq = 48 MHz*/ -#define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq = 24 MHz*/ - -/* Miscealleneaous Function Reg. */ -#define SDR0_MFR 0x4300 -#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */ -#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000 -#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */ -#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000 -#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ -#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ -#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ -#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ -#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ -#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) -#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3) - -#define SDR0_MFR_ERRATA3_EN0 0x00800000 -#define SDR0_MFR_ERRATA3_EN1 0x00400000 -#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */ -#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Enable on both EMAC3 0-1 */ -#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */ -#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */ -#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */ + /* USB2PHY0 Control Register */ +#define SDR0_USB2PHY0CR 0x4103 +#define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 + + /* PHY UTMI interface connection */ +#define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */ +#define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */ + +#define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */ +#define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */ +#define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */ + +#define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000 + /* VBus detect (Device mode only) */ +#define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000 + /* Pull-up resistance on D+ is disabled */ +#define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000 + /* Pull-up resistance on D+ is enabled */ + +#define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000 + /* PHY UTMI data width and clock select */ +#define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */ +#define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */ + +#define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */ +#define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */ +#define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000 + /* Loop back enabled (only test purposes) */ + +#define SDR0_USB2PHY0CR_XOON_MASK 0x04000000 + /* Force XO block on during a suspend */ +#define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */ +#define SDR0_USB2PHY0CR_XO_OFF 0x04000000 + /* PHY XO block is powered-off when all ports are suspended */ + +#define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */ +#define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */ +#define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only + for full-speed operation */ + +#define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock + source */ +#define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal + 48M clock as a reference */ +#define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO + block output as a reference */ + +#define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO + block*/ +#define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external + clock */ +#define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock + from a crystal */ + +#define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */ +#define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq + = 12 MHz */ +#define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq + = 48 MHz */ +#define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq + = 24 MHz */ + + /* Miscealleneaous Function Reg. */ +#define SDR0_MFR 0x4300 +#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */ +#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000 +#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */ +#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000 +#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ +#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ +#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ +#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ +#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ +#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) +#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3) + +#define SDR0_MFR_ERRATA3_EN0 0x00800000 +#define SDR0_MFR_ERRATA3_EN1 0x00400000 +#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */ +#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Ena. on both EMAC3 0-1 */ +#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */ +#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */ +#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */ #endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */ -/* CUST1 Customer Configuration Register1 */ -#define SDR0_CUST1 0x4002 -#define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */ -#define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) -#define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) - -/* Pin Function Control Register 0 */ -#define SDR0_PFC0 0x4100 -#define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */ -#define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */ -#define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */ -#define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8) -#define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01) - -/* Pin Function Control Register 1 */ -#define SDR0_PFC1 0x4101 -#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ -#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ -#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ -#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ -#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ -#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ -#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ -#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ -#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ -#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ -#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ -#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ -#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req Selection */ -#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ -#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ -#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) Selection */ -#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ -#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ -#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) Selection */ -#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */ -#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ -#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject Selection */ -#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject Disable */ -#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject Enable */ - -#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. Selection */ -#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor Enable */ -#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor Enable */ -#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation Gated In */ + /* CUST1 Customer Configuration Register1 */ +#define SDR0_CUST1 0x4002 +#define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */ +#define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) +#define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) + + /* Pin Function Control Register 0 */ +#define SDR0_PFC0 0x4100 +#define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */ +#define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */ +#define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */ +#define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8) +#define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01) + + /* Pin Function Control Register 1 */ +#define SDR0_PFC1 0x4101 +#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ +#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ +#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ +#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ +#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ +#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ +#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ +#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ +#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ +#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ +#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ +#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ +#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req + Selection */ +#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ +#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ +#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) + Selection */ +#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ +#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ +#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) + Selection */ +#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */ +#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ +#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject + Selection */ +#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject + Disable */ +#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject + Enable */ + +#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. + Selection */ +#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor + Enable */ +#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor + Enable */ +#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation + Gated In */ #endif /* 440EP || 440GR || 440EPX || 440GRX */ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) -/* CUST0 Customer Configuration Register0 */ -#define SDR0_CUST0 0x4000 -#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ -#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ -#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ -#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ - -#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ -#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ -#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ - -#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ -#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ -#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ - -#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ -#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) -#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) - -#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ -#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22) -#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03) - -#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ -#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ -#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ - -#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ -#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ -#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ - -#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ -#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) -#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF) - -#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ -#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ -#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Select Gating Enable */ -#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ -#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ -#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ -#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ + /* CUST0 Customer Configuration Register0 */ +#define SDR0_CUST0 0x4000 +#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ +#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ +#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ +#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ + +#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ +#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ +#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ + +#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ +#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ +#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ + +#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ +#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) +#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) + +#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ +#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22) +#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03) + +#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ + +#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ +#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ +#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ + +#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ +#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) +#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF) + +#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ +#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ +#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /*All Chip Select Gating Enable*/ +#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ #endif /*----------------------------------------------------------------------------- @@ -534,16 +596,16 @@ #define CNTRL_DCR_BASE 0x0b0 #endif -#define CPC0_SYS0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */ -#define CPC0_SYS1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */ +#define CPC0_SYS0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */ +#define CPC0_SYS1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */ -#define CPC0_STRP0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */ -#define CPC0_STRP1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */ +#define CPC0_STRP0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */ +#define CPC0_STRP1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */ -#define CPC0_GPIO (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */ +#define CPC0_GPIO (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */ -#define CPC0_CR0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */ -#define CPC0_CR1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */ +#define CPC0_CR0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */ +#define CPC0_CR1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */ /*----------------------------------------------------------------------------- | DMA @@ -572,12 +634,12 @@ #define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */ #define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ #define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset) */ -#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status */ +#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status*/ #define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int */ #define MAL0_TXBADDR (MAL_DCR_BASE + 0x09) /* TX descriptor base addr*/ #define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */ #define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */ -#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status */ +#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status*/ #define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int */ #define MAL0_RXBADDR (MAL_DCR_BASE + 0x15) /* RX descriptor base addr */ #define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table pointer */ @@ -658,7 +720,7 @@ #define SDR0_SDSTP0_TUNE_DECODE(n) ((((unsigned long)(n))>>17)&0x3FF) #define SDR0_SDSTP0_FBDV_MASK 0x0001F000 #define SDR0_SDSTP0_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12) -#define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1) +#define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1) #define SDR0_SDSTP0_FWDVA_MASK 0x00000F00 #define SDR0_SDSTP0_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<8) #define SDR0_SDSTP0_FWDVA_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x0F)+1) @@ -732,8 +794,8 @@ #define SDR0_SDSTP1_DBGEN_MASK 0x00000030 /* $218C */ #define SDR0_SDSTP1_DBGEN_FUNC 0x00000000 #define SDR0_SDSTP1_DBGEN_TRACE 0x00000010 -#define SDR0_SDSTP1_DBGEN_ENCODE(n) ((((unsigned long)(n))&0x03)<<4) /* $218C */ -#define SDR0_SDSTP1_DBGEN_DECODE(n) ((((unsigned long)(n))>>4)&0x03) /* $218C */ +#define SDR0_SDSTP1_DBGEN_ENCODE(n) ((((unsigned long)(n))&0x03)<<4) /* $218C */ +#define SDR0_SDSTP1_DBGEN_DECODE(n) ((((unsigned long)(n))>>4)&0x03) /* $218C */ #define SDR0_SDSTP1_ETH_MASK 0x00000004 #define SDR0_SDSTP1_ETH_10_100 0x00000000 #define SDR0_SDSTP1_ETH_GIGA 0x00000004 @@ -816,10 +878,14 @@ #define SDR0_PINSTP 0x0040 #define SDR0_PINSTP_BOOTSTRAP_MASK 0xC0000000 /* Strap Bits */ -#define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 (EBC boot) */ -#define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1 (PCI boot) */ -#define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled - Addr = 0x54 */ -#define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled - Addr = 0x50 */ +#define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 + (EBC boot) */ +#define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1 + (PCI boot) */ +#define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled - + Addr = 0x54 */ +#define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled - + Addr = 0x50 */ #define SDR0_SDCS 0x0060 #define SDR0_ECID0 0x0080 #define SDR0_ECID1 0x0081 @@ -960,8 +1026,10 @@ #define SDR0_PFC1_CPU_TRACE_MASK 0x00180000 /* $218C */ #define SDR0_PFC1_CPU_NO_TRACE 0x00000000 #define SDR0_PFC1_CPU_TRACE 0x00080000 -#define SDR0_PFC1_CPU_TRACE_ENCODE(n) ((((unsigned long)(n))&0x3)<<19) /* $218C */ -#define SDR0_PFC1_CPU_TRACE_DECODE(n) ((((unsigned long)(n))>>19)&0x03) /* $218C */ +#define SDR0_PFC1_CPU_TRACE_ENCODE(n) ((((unsigned long)(n))&0x3)<<19) + /* $218C */ +#define SDR0_PFC1_CPU_TRACE_DECODE(n) ((((unsigned long)(n))>>19)&0x03) + /* $218C */ #define SDR0_MFR 0x4300 #endif /* CONFIG_440SPE */ @@ -1023,34 +1091,43 @@ /* Ethernet Configuration Register (SDR0_ETH_CFG) */ #define SDR0_ETH_CFG 0x4103 -#define SDR0_ETH_CFG_SGMII3_LPBK 0x00800000 /* SGMII3 port loopback enable */ -#define SDR0_ETH_CFG_SGMII2_LPBK 0x00400000 /* SGMII2 port loopback enable */ -#define SDR0_ETH_CFG_SGMII1_LPBK 0x00200000 /* SGMII1 port loopback enable */ -#define SDR0_ETH_CFG_SGMII0_LPBK 0x00100000 /* SGMII0 port loopback enable */ -#define SDR0_ETH_CFG_SGMII_MASK 0x00070000 /* SGMII Mask */ -#define SDR0_ETH_CFG_SGMII2_ENABLE 0x00040000 /* SGMII2 port enable */ -#define SDR0_ETH_CFG_SGMII1_ENABLE 0x00020000 /* SGMII1 port enable */ -#define SDR0_ETH_CFG_SGMII0_ENABLE 0x00010000 /* SGMII0 port enable */ -#define SDR0_ETH_CFG_TAHOE1_BYPASS 0x00002000 /* TAHOE1 Bypass selector */ -#define SDR0_ETH_CFG_TAHOE0_BYPASS 0x00001000 /* TAHOE0 Bypass selector */ -#define SDR0_ETH_CFG_EMAC3_PHY_CLK_SEL 0x00000800 /* EMAC 3 PHY clock selector */ -#define SDR0_ETH_CFG_EMAC2_PHY_CLK_SEL 0x00000400 /* EMAC 2 PHY clock selector */ -#define SDR0_ETH_CFG_EMAC1_PHY_CLK_SEL 0x00000200 /* EMAC 1 PHY clock selector */ -#define SDR0_ETH_CFG_EMAC0_PHY_CLK_SEL 0x00000100 /* EMAC 0 PHY clock selector */ -#define SDR0_ETH_CFG_EMAC_2_1_SWAP 0x00000080 /* Swap EMAC2 with EMAC1 */ -#define SDR0_ETH_CFG_EMAC_0_3_SWAP 0x00000040 /* Swap EMAC0 with EMAC3 */ -#define SDR0_ETH_CFG_MDIO_SEL_MASK 0x00000030 /* MDIO source selector mask */ -#define SDR0_ETH_CFG_MDIO_SEL_EMAC0 0x00000000 /* MDIO source - EMAC0 */ -#define SDR0_ETH_CFG_MDIO_SEL_EMAC1 0x00000010 /* MDIO source - EMAC1 */ -#define SDR0_ETH_CFG_MDIO_SEL_EMAC2 0x00000020 /* MDIO source - EMAC2 */ -#define SDR0_ETH_CFG_MDIO_SEL_EMAC3 0x00000030 /* MDIO source - EMAC3 */ -#define SDR0_ETH_CFG_ZMII_MODE_MASK 0x0000000C /* ZMII bridge mode selector mask */ -#define SDR0_ETH_CFG_ZMII_SEL_MII 0x00000000 /* ZMII bridge mode - MII */ -#define SDR0_ETH_CFG_ZMII_SEL_SMII 0x00000004 /* ZMII bridge mode - SMII */ -#define SDR0_ETH_CFG_ZMII_SEL_RMII_10 0x00000008 /* ZMII bridge mode - RMII (10 Mbps) */ -#define SDR0_ETH_CFG_ZMII_SEL_RMII_100 0x0000000C /* ZMII bridge mode - RMII (100 Mbps) */ -#define SDR0_ETH_CFG_GMC1_BRIDGE_SEL 0x00000002 /* GMC Port 1 bridge selector */ -#define SDR0_ETH_CFG_GMC0_BRIDGE_SEL 0x00000001 /* GMC Port 0 bridge selector */ +#define SDR0_ETH_CFG_SGMII3_LPBK 0x00800000 /*SGMII3 port loopback + enable */ +#define SDR0_ETH_CFG_SGMII2_LPBK 0x00400000 /*SGMII2 port loopback + enable */ +#define SDR0_ETH_CFG_SGMII1_LPBK 0x00200000 /*SGMII1 port loopback + enable */ +#define SDR0_ETH_CFG_SGMII0_LPBK 0x00100000 /*SGMII0 port loopback + enable */ +#define SDR0_ETH_CFG_SGMII_MASK 0x00070000 /*SGMII Mask */ +#define SDR0_ETH_CFG_SGMII2_ENABLE 0x00040000 /*SGMII2 port enable */ +#define SDR0_ETH_CFG_SGMII1_ENABLE 0x00020000 /*SGMII1 port enable */ +#define SDR0_ETH_CFG_SGMII0_ENABLE 0x00010000 /*SGMII0 port enable */ +#define SDR0_ETH_CFG_TAHOE1_BYPASS 0x00002000 /*TAHOE1 Bypass selector */ +#define SDR0_ETH_CFG_TAHOE0_BYPASS 0x00001000 /*TAHOE0 Bypass selector */ +#define SDR0_ETH_CFG_EMAC3_PHY_CLK_SEL 0x00000800 /*EMAC 3 PHY clock selector*/ +#define SDR0_ETH_CFG_EMAC2_PHY_CLK_SEL 0x00000400 /*EMAC 2 PHY clock selector*/ +#define SDR0_ETH_CFG_EMAC1_PHY_CLK_SEL 0x00000200 /*EMAC 1 PHY clock selector*/ +#define SDR0_ETH_CFG_EMAC0_PHY_CLK_SEL 0x00000100 /*EMAC 0 PHY clock selector*/ +#define SDR0_ETH_CFG_EMAC_2_1_SWAP 0x00000080 /*Swap EMAC2 with EMAC1 */ +#define SDR0_ETH_CFG_EMAC_0_3_SWAP 0x00000040 /*Swap EMAC0 with EMAC3 */ +#define SDR0_ETH_CFG_MDIO_SEL_MASK 0x00000030 /*MDIO source selector mask*/ +#define SDR0_ETH_CFG_MDIO_SEL_EMAC0 0x00000000 /*MDIO source - EMAC0 */ +#define SDR0_ETH_CFG_MDIO_SEL_EMAC1 0x00000010 /*MDIO source - EMAC1 */ +#define SDR0_ETH_CFG_MDIO_SEL_EMAC2 0x00000020 /*MDIO source - EMAC2 */ +#define SDR0_ETH_CFG_MDIO_SEL_EMAC3 0x00000030 /*MDIO source - EMAC3 */ +#define SDR0_ETH_CFG_ZMII_MODE_MASK 0x0000000C /*ZMII bridge mode selector + mask */ +#define SDR0_ETH_CFG_ZMII_SEL_MII 0x00000000 /*ZMII bridge mode - MII */ +#define SDR0_ETH_CFG_ZMII_SEL_SMII 0x00000004 /*ZMII bridge mode - SMII */ +#define SDR0_ETH_CFG_ZMII_SEL_RMII_10 0x00000008 /*ZMII bridge mode - RMII + (10 Mbps) */ +#define SDR0_ETH_CFG_ZMII_SEL_RMII_100 0x0000000C /*ZMII bridge mode - RMII + (100 Mbps) */ +#define SDR0_ETH_CFG_GMC1_BRIDGE_SEL 0x00000002 /*GMC Port 1 bridge + selector */ +#define SDR0_ETH_CFG_GMC0_BRIDGE_SEL 0x00000001 /*GMC Port 0 bridge + selector */ #define SDR0_ETH_CFG_ZMII_MODE_SHIFT 4 #define SDR0_ETH_CFG_ZMII_MII_MODE 0x00 @@ -1063,26 +1140,46 @@ /* Miscealleneaous Function Reg. (SDR0_MFR) */ #define SDR0_MFR 0x4300 -#define SDR0_MFR_T0TxFL 0x00800000 /* force parity error TAHOE0 Tx FIFO bits 0:63 */ -#define SDR0_MFR_T0TxFH 0x00400000 /* force parity error TAHOE0 Tx FIFO bits 64:127 */ -#define SDR0_MFR_T1TxFL 0x00200000 /* force parity error TAHOE1 Tx FIFO bits 0:63 */ -#define SDR0_MFR_T1TxFH 0x00100000 /* force parity error TAHOE1 Tx FIFO bits 64:127 */ -#define SDR0_MFR_E0TxFL 0x00008000 /* force parity error EMAC0 Tx FIFO bits 0:63 */ -#define SDR0_MFR_E0TxFH 0x00004000 /* force parity error EMAC0 Tx FIFO bits 64:127 */ -#define SDR0_MFR_E0RxFL 0x00002000 /* force parity error EMAC0 Rx FIFO bits 0:63 */ -#define SDR0_MFR_E0RxFH 0x00001000 /* force parity error EMAC0 Rx FIFO bits 64:127 */ -#define SDR0_MFR_E1TxFL 0x00000800 /* force parity error EMAC1 Tx FIFO bits 0:63 */ -#define SDR0_MFR_E1TxFH 0x00000400 /* force parity error EMAC1 Tx FIFO bits 64:127 */ -#define SDR0_MFR_E1RxFL 0x00000200 /* force parity error EMAC1 Rx FIFO bits 0:63 */ -#define SDR0_MFR_E1RxFH 0x00000100 /* force parity error EMAC1 Rx FIFO bits 64:127 */ -#define SDR0_MFR_E2TxFL 0x00000080 /* force parity error EMAC2 Tx FIFO bits 0:63 */ -#define SDR0_MFR_E2TxFH 0x00000040 /* force parity error EMAC2 Tx FIFO bits 64:127 */ -#define SDR0_MFR_E2RxFL 0x00000020 /* force parity error EMAC2 Rx FIFO bits 0:63 */ -#define SDR0_MFR_E2RxFH 0x00000010 /* force parity error EMAC2 Rx FIFO bits 64:127 */ -#define SDR0_MFR_E3TxFL 0x00000008 /* force parity error EMAC3 Tx FIFO bits 0:63 */ -#define SDR0_MFR_E3TxFH 0x00000004 /* force parity error EMAC3 Tx FIFO bits 64:127 */ -#define SDR0_MFR_E3RxFL 0x00000002 /* force parity error EMAC3 Rx FIFO bits 0:63 */ -#define SDR0_MFR_E3RxFH 0x00000001 /* force parity error EMAC3 Rx FIFO bits 64:127 */ +#define SDR0_MFR_T0TxFL 0x00800000 /* force parity error TAHOE0 Tx + FIFO bits 0:63 */ +#define SDR0_MFR_T0TxFH 0x00400000 /* force parity error TAHOE0 Tx + FIFO bits 64:127 */ +#define SDR0_MFR_T1TxFL 0x00200000 /* force parity error TAHOE1 Tx + FIFO bits 0:63 */ +#define SDR0_MFR_T1TxFH 0x00100000 /* force parity error TAHOE1 Tx + FIFO bits 64:127 */ +#define SDR0_MFR_E0TxFL 0x00008000 /* force parity error EMAC0 Tx + FIFO bits 0:63 */ +#define SDR0_MFR_E0TxFH 0x00004000 /* force parity error EMAC0 Tx + FIFO bits 64:127 */ +#define SDR0_MFR_E0RxFL 0x00002000 /* force parity error EMAC0 Rx + FIFO bits 0:63 */ +#define SDR0_MFR_E0RxFH 0x00001000 /* force parity error EMAC0 Rx + FIFO bits 64:127 */ +#define SDR0_MFR_E1TxFL 0x00000800 /* force parity error EMAC1 Tx + FIFO bits 0:63 */ +#define SDR0_MFR_E1TxFH 0x00000400 /* force parity error EMAC1 Tx + FIFO bits 64:127 */ +#define SDR0_MFR_E1RxFL 0x00000200 /* force parity error EMAC1 Rx + FIFO bits 0:63 */ +#define SDR0_MFR_E1RxFH 0x00000100 /* force parity error EMAC1 Rx + FIFO bits 64:127 */ +#define SDR0_MFR_E2TxFL 0x00000080 /* force parity error EMAC2 Tx + FIFO bits 0:63 */ +#define SDR0_MFR_E2TxFH 0x00000040 /* force parity error EMAC2 Tx + FIFO bits 64:127 */ +#define SDR0_MFR_E2RxFL 0x00000020 /* force parity error EMAC2 Rx + FIFO bits 0:63 */ +#define SDR0_MFR_E2RxFH 0x00000010 /* force parity error EMAC2 Rx + FIFO bits 64:127 */ +#define SDR0_MFR_E3TxFL 0x00000008 /* force parity error EMAC3 Tx + FIFO bits 0:63 */ +#define SDR0_MFR_E3TxFH 0x00000004 /* force parity error EMAC3 Tx + FIFO bits 64:127 */ +#define SDR0_MFR_E3RxFL 0x00000002 /* force parity error EMAC3 Rx + FIFO bits 0:63 */ +#define SDR0_MFR_E3RxFH 0x00000001 /* force parity error EMAC3 Rx + FIFO bits 64:127 */ /* EMACx TX Status Register (SDR0_EMACxTXST)*/ #define SDR0_EMAC0TXST 0x4400 @@ -1090,30 +1187,30 @@ #define SDR0_EMAC2TXST 0x4402 #define SDR0_EMAC3TXST 0x4403 -#define SDR0_EMACxTXST_FUR 0x02000000 /* TX FIFO underrun */ -#define SDR0_EMACxTXST_BC 0x01000000 /* broadcase address */ -#define SDR0_EMACxTXST_MC 0x00800000 /* multicast address */ -#define SDR0_EMACxTXST_UC 0x00400000 /* unicast address */ -#define SDR0_EMACxTXST_FP 0x00200000 /* frame paused by control packet */ -#define SDR0_EMACxTXST_BFCS 0x00100000 /* bad FCS in the transmitted frame */ -#define SDR0_EMACxTXST_CPF 0x00080000 /* TX control pause frame */ -#define SDR0_EMACxTXST_CF 0x00040000 /* TX control frame */ -#define SDR0_EMACxTXST_MSIZ 0x00020000 /* 1024-maxsize bytes transmitted */ -#define SDR0_EMACxTXST_1023 0x00010000 /* 512-1023 bytes transmitted */ -#define SDR0_EMACxTXST_511 0x00008000 /* 256-511 bytes transmitted */ -#define SDR0_EMACxTXST_255 0x00004000 /* 128-255 bytes transmitted */ -#define SDR0_EMACxTXST_127 0x00002000 /* 65-127 bytes transmitted */ -#define SDR0_EMACxTXST_64 0x00001000 /* 64 bytes transmitted */ -#define SDR0_EMACxTXST_SQE 0x00000800 /* SQE indication */ -#define SDR0_EMACxTXST_LOC 0x00000400 /* loss of carrier sense */ -#define SDR0_EMACxTXST_IERR 0x00000080 /* EMAC internal error */ -#define SDR0_EMACxTXST_EDF 0x00000040 /* excessive deferral */ -#define SDR0_EMACxTXST_ECOL 0x00000020 /* excessive collisions */ -#define SDR0_EMACxTXST_LCOL 0x00000010 /* late collision */ -#define SDR0_EMACxTXST_DFFR 0x00000008 /* deferred frame */ -#define SDR0_EMACxTXST_MCOL 0x00000004 /* multiple collision frame */ -#define SDR0_EMACxTXST_SCOL 0x00000002 /* single collision frame */ -#define SDR0_EMACxTXST_TXOK 0x00000001 /* transmit OK */ +#define SDR0_EMACxTXST_FUR 0x02000000 /*TX FIFO underrun */ +#define SDR0_EMACxTXST_BC 0x01000000 /*broadcase address */ +#define SDR0_EMACxTXST_MC 0x00800000 /*multicast address */ +#define SDR0_EMACxTXST_UC 0x00400000 /*unicast address */ +#define SDR0_EMACxTXST_FP 0x00200000 /*frame paused by control packet */ +#define SDR0_EMACxTXST_BFCS 0x00100000 /*bad FCS in the transmitted frame */ +#define SDR0_EMACxTXST_CPF 0x00080000 /*TX control pause frame */ +#define SDR0_EMACxTXST_CF 0x00040000 /*TX control frame */ +#define SDR0_EMACxTXST_MSIZ 0x00020000 /* 1024-maxsize bytes transmitted */ +#define SDR0_EMACxTXST_1023 0x00010000 /*512-1023 bytes transmitted */ +#define SDR0_EMACxTXST_511 0x00008000 /*256-511 bytes transmitted */ +#define SDR0_EMACxTXST_255 0x00004000 /*128-255 bytes transmitted */ +#define SDR0_EMACxTXST_127 0x00002000 /*65-127 bytes transmitted */ +#define SDR0_EMACxTXST_64 0x00001000 /*64 bytes transmitted */ +#define SDR0_EMACxTXST_SQE 0x00000800 /*SQE indication */ +#define SDR0_EMACxTXST_LOC 0x00000400 /*loss of carrier sense */ +#define SDR0_EMACxTXST_IERR 0x00000080 /*EMAC internal error */ +#define SDR0_EMACxTXST_EDF 0x00000040 /*excessive deferral */ +#define SDR0_EMACxTXST_ECOL 0x00000020 /*excessive collisions */ +#define SDR0_EMACxTXST_LCOL 0x00000010 /*late collision */ +#define SDR0_EMACxTXST_DFFR 0x00000008 /*deferred frame */ +#define SDR0_EMACxTXST_MCOL 0x00000004 /*multiple collision frame */ +#define SDR0_EMACxTXST_SCOL 0x00000002 /*single collision frame */ +#define SDR0_EMACxTXST_TXOK 0x00000001 /*transmit OK */ /* EMACx RX Status Register (SDR0_EMACxRXST)*/ #define SDR0_EMAC0RXST 0x4404 @@ -1146,8 +1243,9 @@ #define SDR0_EMACxRXST_F2L 0x00000020 /* frame is to long */ #define SDR0_EMACxRXST_OERR 0x00000010 /* out of range length error */ #define SDR0_EMACxRXST_IERR 0x00000008 /* in range length error */ -#define SDR0_EMACxRXST_LOST 0x00000004 /* frame lost due to internal EMAC receive error */ -#define SDR0_EMACxRXST_BFCS 0x00000002 /* bad FCS in the recieved frame */ +#define SDR0_EMACxRXST_LOST 0x00000004 /* frame lost due to internal + EMAC receive error */ +#define SDR0_EMACxRXST_BFCS 0x00000002 /* bad FCS in the recieved frame */ #define SDR0_EMACxRXST_RXOK 0x00000001 /* Recieve OK */ /* EMACx TX Status Register (SDR0_EMACxREJCNT)*/ @@ -1300,23 +1398,37 @@ #define SDR0_MFR_ECS_MASK 0x10000000 #define SDR0_MFR_ECS_INTERNAL 0x10000000 -#define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */ -#define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */ -#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ -#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ -#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ -#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */ -#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */ -#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ -#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ -#define SDR0_MFR_ERRATA3_EN0 0x00800000 -#define SDR0_MFR_ERRATA3_EN1 0x00400000 +#define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */ +#define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */ +#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ +#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ +#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ +#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */ +#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs*/ +#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ +#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ +#define SDR0_MFR_ERRATA3_EN0 0x00800000 +#define SDR0_MFR_ERRATA3_EN1 0x00400000 #if defined(CONFIG_440GX) /* test-only: only 440GX or 440SPE??? */ -#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */ -#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 0-1 */ -#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */ -#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */ -#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */ +#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */ +#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 + 0-1 */ +#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */ +#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */ +#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */ +#endif + + +#if defined(CONFIG_440EPX) +#define CPM0_ER 0x000000B0 +#define CPM1_ER 0x000000F0 +#define PLB4A0_ACR 0x00000081 +#define PLB4A1_ACR 0x00000089 +#define PLB3A0_ACR 0x00000077 +#define OPB2PLB40_BCTRL 0x00000350 +#define P4P3BO0_CFG 0x00000026 +#define SPI0_MODE 0xEF600090 /* SPI Mode Regsgiter */ + #endif #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) @@ -1330,61 +1442,74 @@ #define SDR0_MFR_ECS_INTERNAL 0x10000000 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define SDR0_SRST0 0x200 -#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */ -#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */ -#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */ -#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */ -#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */ -#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */ -#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */ -#define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */ -#define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */ -#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */ -#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */ -#define SDR0_SRST0_PCI 0x00100000 /* PCI */ -#define SDR0_SRST0_EMAC0 0x00080000 /* Ethernet media access controller 0 */ -#define SDR0_SRST0_EMAC1 0x00040000 /* Ethernet media access controller 1 */ -#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */ -#define SDR0_SRST0_ZMII 0x00010000 /* ZMII bridge */ -#define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0 */ -#define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1 */ -#define SDR0_SRST0_IIC1 0x00002000 /* Inter integrated circuit 1 */ -#define SDR0_SRST0_SCP 0x00001000 /* Serial communications port */ -#define SDR0_SRST0_BGI 0x00000800 /* OPB to PLB bridge */ -#define SDR0_SRST0_DMA 0x00000400 /* Direct memory access controller */ -#define SDR0_SRST0_DMAC 0x00000200 /* DMA channel */ -#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */ -#define SDR0_SRST0_USB2D 0x00000080 /* USB2.0 device */ -#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */ -#define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */ -#define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */ -#define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */ -#define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/transmitter 2 */ -#define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/transmitter 3 */ - -#define SDR0_SRST1 0x201 -#define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */ -#define SDR0_SRST1_OPBA1 0x40000000 /* OPB Arbiter attached to PLB4 */ -#define SDR0_SRST1_P4OPB0 0x20000000 /* PLB4 to OPB Bridge0 */ -#define SDR0_SRST1_PLB42OPB0 SDR0_SRST1_P4OPB0 -#define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */ -#define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */ -#define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4 USB 2.0 Host */ -#define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to USB 2.0 Host */ -#define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to USB 2.0 Host */ -#define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */ -#define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2 */ -#define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */ -#define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */ -#define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */ -#define SDR0_SRST1_USB2HPHY 0x00040000 /* USB 2.0 Host Phy Interface */ -#define SDR0_SRST1_SRAM0 0x00020000 /* Internal SRAM Controller */ -#define SDR0_SRST1_RGMII0 0x00010000 /* RGMII Bridge */ -#define SDR0_SRST1_ETHPLL 0x00008000 /* Ethernet PLL */ -#define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */ -#define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */ +#define SDR0_SRST0 0x200 +#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */ +#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */ +#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */ +#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */ +#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/ + transmitter 0 */ +#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/ + transmitter 1 */ +#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */ +#define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */ +#define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */ +#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */ +#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */ +#define SDR0_SRST0_PCI 0x00100000 /* PCI */ +#define SDR0_SRST0_EMAC0 0x00080000 /* Ethernet media access controller 0 */ +#define SDR0_SRST0_EMAC1 0x00040000 /* Ethernet media access controller 1 */ +#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */ +#define SDR0_SRST0_ZMII 0x00010000 /* ZMII bridge */ +#define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0 */ +#define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1 */ +#define SDR0_SRST0_IIC1 0x00002000 /* Inter integrated circuit 1 */ +#define SDR0_SRST0_SCP 0x00001000 /* Serial communications port */ +#define SDR0_SRST0_BGI 0x00000800 /* OPB to PLB bridge */ +#define SDR0_SRST0_DMA 0x00000400 /* Direct memory access controller */ +#define SDR0_SRST0_DMAC 0x00000200 /* DMA channel */ +#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */ +#define SDR0_SRST0_USB2D 0x00000080 /* USB2.0 device */ +#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */ +#define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */ +#define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */ +#define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */ +#define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/ + transmitter 2 */ +#define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/ + transmitter 3 */ +#define SDR0_SRST1 0x201 +#define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */ +#define SDR0_SRST1_OPBA1 0x40000000 /* OPB Arbiter attached to PLB4 */ +#define SDR0_SRST1_P4OPB0 0x20000000 /* PLB4 to OPB Bridge0 */ +#define SDR0_SRST1_PLB42OPB0 SDR0_SRST1_P4OPB0 +#define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */ +#define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */ +#define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4 + USB 2.0 Host */ +#define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to + USB 2.0 Host */ +#define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to + USB 2.0 Host */ +#define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */ +#define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2*/ +#define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */ +#define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */ +#define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */ +#define SDR0_SRST1_USB2HPHY 0x00040000 /* USB 2.0 Host Phy Interface */ +#define SDR0_SRST1_SRAM0 0x00020000 /* Internal SRAM Controller */ +#define SDR0_SRST1_RGMII0 0x00010000 /* RGMII Bridge */ +#define SDR0_SRST1_ETHPLL 0x00008000 /* Ethernet PLL */ +#define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */ +#define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */ + +#define SDR0_EMAC0RXST 0x00004301 /* */ +#define SDR0_EMAC0TXST 0x00004302 /* */ +#define SDR0_CRYP0 0x00004500 +#define SDR0_EBC0 0x00000100 +#define SDR0_SDSTP2 0x00004001 +#define SDR0_SDSTP3 0x00004001 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) #define SDR0_SRST0 SDR0_SRST /* for compatability reasons */ @@ -1392,8 +1517,10 @@ #define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */ #define SDR0_SRST0_EBC 0x20000000 /* External bus controller */ #define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */ -#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/transmitter 0 */ -#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/transmitter 1 */ +#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/ + transmitter 0 */ +#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/ + transmitter 1 */ #define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */ #define SDR0_SRST0_IIC1 0x01000000 /* Inter integrated circuit 1 */ #define SDR0_SRST0_GPIO0 0x00800000 /* General purpose I/O 0 */ @@ -1408,11 +1535,13 @@ #define SDR0_SRST0_UIC2 0x00001000 /* Universal interrupt controller 2*/ #define SDR0_SRST0_UIC3 0x00000800 /* Universal interrupt controller 3*/ #define SDR0_SRST0_OCM 0x00000400 /* Universal interrupt controller 0*/ -#define SDR0_SRST0_UART2 0x00000200 /* Universal asynchronous receiver/transmitter 2 */ +#define SDR0_SRST0_UART2 0x00000200 /* Universal asynchronous receiver/ + transmitter 2 */ #define SDR0_SRST0_MAL 0x00000100 /* Media access layer */ #define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */ #define SDR0_SRST0_L2CACHE 0x00000004 /* L2 Cache */ -#define SDR0_SRST0_UART3 0x00000002 /* Universal asynchronous receiver/transmitter 3 */ +#define SDR0_SRST0_UART3 0x00000002 /* Universal asynchronous receiver/ + transmitter 3 */ #define SDR0_SRST0_GPIO1 0x00000001 /* General purpose I/O 1 */ #define SDR0_SRST1 0x201 @@ -1421,17 +1550,22 @@ #define SDR0_SRST1_PLBARB 0x20000000 /* PLB Arbiter */ #define SDR0_SRST1_EIPPKP 0x10000000 /* EIPPPKP */ #define SDR0_SRST1_EIP94 0x08000000 /* EIP 94 */ -#define SDR0_SRST1_EMAC0 0x04000000 /* Ethernet media access controller 0 */ -#define SDR0_SRST1_EMAC1 0x02000000 /* Ethernet media access controller 1 */ -#define SDR0_SRST1_EMAC2 0x01000000 /* Ethernet media access controller 2 */ -#define SDR0_SRST1_EMAC3 0x00800000 /* Ethernet media access controller 3 */ +#define SDR0_SRST1_EMAC0 0x04000000 /* Ethernet media access + controller 0 */ +#define SDR0_SRST1_EMAC1 0x02000000 /* Ethernet media access + controller 1 */ +#define SDR0_SRST1_EMAC2 0x01000000 /* Ethernet media access + controller 2 */ +#define SDR0_SRST1_EMAC3 0x00800000 /* Ethernet media access + controller 3 */ #define SDR0_SRST1_ZMII 0x00400000 /* Ethernet ZMII/RMII/SMII */ #define SDR0_SRST1_RGMII0 0x00200000 /* Ethernet RGMII/RTBI 0 */ #define SDR0_SRST1_RGMII1 0x00100000 /* Ethernet RGMII/RTBI 1 */ #define SDR0_SRST1_DMA4 0x00080000 /* DMA to PLB4 */ #define SDR0_SRST1_DMA4CH 0x00040000 /* DMA Channel to PLB4 */ #define SDR0_SRST1_SATAPHY 0x00020000 /* Serial ATA PHY */ -#define SDR0_SRST1_SRIODEV 0x00010000 /* Serial Rapid IO core, PCS, and serdes */ +#define SDR0_SRST1_SRIODEV 0x00010000 /* Serial Rapid IO core, PCS, and + serdes */ #define SDR0_SRST1_SRIOPCS 0x00008000 /* Serial Rapid IO core and PCS */ #define SDR0_SRST1_NDFC 0x00004000 /* Nand flash controller */ #define SDR0_SRST1_SRIOPLB 0x00002000 /* Serial Rapid IO PLB */ @@ -1520,7 +1654,7 @@ #else /* !CONFIG_440GX or CONFIG_440EP or CONFIG_440GR */ #define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */ #define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */ -#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */ +#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */ #define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */ #define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */ #define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */ @@ -1528,7 +1662,7 @@ #define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */ #define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */ -#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */ +#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */ #define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ #define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */ #define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */ @@ -1586,7 +1720,7 @@ #define IICEXTSTS 0x09 #define IICLSADR 0x0A #define IICHSADR 0x0B -#define IICCLKDIV 0x0C +#define IIC0_CLKDIV 0x0C #define IICINTRMSK 0x0D #define IICXFRCNT 0x0E #define IICXTCNTLSS 0x0F @@ -1595,95 +1729,123 @@ /*----------------------------------------------------------------------------- | PCI Internal Registers et. al. (accessed via plb) +----------------------------------------------------------------------------*/ -#define PCIX0_CFGADR (CONFIG_SYS_PCI_BASE + 0x0ec00000) -#define PCIX0_CFGDATA (CONFIG_SYS_PCI_BASE + 0x0ec00004) -#define PCIX0_CFGBASE (CONFIG_SYS_PCI_BASE + 0x0ec80000) -#define PCIX0_IOBASE (CONFIG_SYS_PCI_BASE + 0x08000000) +#define PCIL0_CFGADR (CONFIG_SYS_PCI_BASE + 0x0ec00000) +#define PCIL0_CFGDATA (CONFIG_SYS_PCI_BASE + 0x0ec00004) +#define PCIL0_CFGBASE (CONFIG_SYS_PCI_BASE + 0x0ec80000) +#define PCIL0_IOBASE (CONFIG_SYS_PCI_BASE + 0x08000000) #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* PCI Local Configuration Registers --------------------------------- */ -#define PCI_MMIO_LCR_BASE (CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real => 0x0EF400000 */ +#define PCI_MMIO_LCR_BASE (CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real => + 0x0EF400000 */ /* PCI Master Local Configuration Registers */ -#define PCIX0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */ -#define PCIX0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */ -#define PCIX0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */ -#define PCIX0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */ -#define PCIX0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */ -#define PCIX0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */ -#define PCIX0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */ -#define PCIX0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */ -#define PCIX0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */ -#define PCIX0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */ -#define PCIX0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */ -#define PCIX0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */ +#define PCIL0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */ +#define PCIL0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */ +#define PCIL0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */ +#define PCIL0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */ +#define PCIL0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */ +#define PCIL0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */ +#define PCIL0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */ +#define PCIL0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */ +#define PCIL0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */ +#define PCIL0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */ +#define PCIL0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */ +#define PCIL0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */ /* PCI Target Local Configuration Registers */ -#define PCIX0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/Attribute */ -#define PCIX0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */ -#define PCIX0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/Attribute */ -#define PCIX0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */ +#define PCIL0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/ + Attribute */ +#define PCIL0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */ +#define PCIL0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/ + Attribute */ +#define PCIL0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */ #else -#define PCIX0_VENDID (PCIX0_CFGBASE + PCI_VENDOR_ID ) -#define PCIX0_DEVID (PCIX0_CFGBASE + PCI_DEVICE_ID ) -#define PCIX0_CMD (PCIX0_CFGBASE + PCI_COMMAND ) -#define PCIX0_STATUS (PCIX0_CFGBASE + PCI_STATUS ) -#define PCIX0_REVID (PCIX0_CFGBASE + PCI_REVISION_ID ) -#define PCIX0_CLS (PCIX0_CFGBASE + PCI_CLASS_CODE) -#define PCIX0_CACHELS (PCIX0_CFGBASE + PCI_CACHE_LINE_SIZE ) -#define PCIX0_LATTIM (PCIX0_CFGBASE + PCI_LATENCY_TIMER ) -#define PCIX0_HDTYPE (PCIX0_CFGBASE + PCI_HEADER_TYPE ) -#define PCIX0_BIST (PCIX0_CFGBASE + PCI_BIST ) -#define PCIX0_BAR0 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_0 ) -#define PCIX0_BAR1 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_1 ) -#define PCIX0_BAR2 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_2 ) -#define PCIX0_BAR3 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_3 ) -#define PCIX0_BAR4 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_4 ) -#define PCIX0_BAR5 (PCIX0_CFGBASE + PCI_BASE_ADDRESS_5 ) -#define PCIX0_CISPTR (PCIX0_CFGBASE + PCI_CARDBUS_CIS ) -#define PCIX0_SBSYSVID (PCIX0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID ) -#define PCIX0_SBSYSID (PCIX0_CFGBASE + PCI_SUBSYSTEM_ID ) -#define PCIX0_EROMBA (PCIX0_CFGBASE + PCI_ROM_ADDRESS ) -#define PCIX0_CAP (PCIX0_CFGBASE + PCI_CAPABILITY_LIST ) -#define PCIX0_RES0 (PCIX0_CFGBASE + 0x0035 ) -#define PCIX0_RES1 (PCIX0_CFGBASE + 0x0036 ) -#define PCIX0_RES2 (PCIX0_CFGBASE + 0x0038 ) -#define PCIX0_INTLN (PCIX0_CFGBASE + PCI_INTERRUPT_LINE ) -#define PCIX0_INTPN (PCIX0_CFGBASE + PCI_INTERRUPT_PIN ) -#define PCIX0_MINGNT (PCIX0_CFGBASE + PCI_MIN_GNT ) -#define PCIX0_MAXLTNCY (PCIX0_CFGBASE + PCI_MAX_LAT ) - -#define PCIX0_BRDGOPT1 (PCIX0_CFGBASE + 0x0040) -#define PCIX0_BRDGOPT2 (PCIX0_CFGBASE + 0x0044) - -#define PCIX0_POM0LAL (PCIX0_CFGBASE + 0x0068) -#define PCIX0_POM0LAH (PCIX0_CFGBASE + 0x006c) -#define PCIX0_POM0SA (PCIX0_CFGBASE + 0x0070) -#define PCIX0_POM0PCIAL (PCIX0_CFGBASE + 0x0074) -#define PCIX0_POM0PCIAH (PCIX0_CFGBASE + 0x0078) -#define PCIX0_POM1LAL (PCIX0_CFGBASE + 0x007c) -#define PCIX0_POM1LAH (PCIX0_CFGBASE + 0x0080) -#define PCIX0_POM1SA (PCIX0_CFGBASE + 0x0084) -#define PCIX0_POM1PCIAL (PCIX0_CFGBASE + 0x0088) -#define PCIX0_POM1PCIAH (PCIX0_CFGBASE + 0x008c) -#define PCIX0_POM2SA (PCIX0_CFGBASE + 0x0090) - -#define PCIX0_PIM0SA (PCIX0_CFGBASE + 0x0098) -#define PCIX0_PIM0LAL (PCIX0_CFGBASE + 0x009c) -#define PCIX0_PIM0LAH (PCIX0_CFGBASE + 0x00a0) -#define PCIX0_PIM1SA (PCIX0_CFGBASE + 0x00a4) -#define PCIX0_PIM1LAL (PCIX0_CFGBASE + 0x00a8) -#define PCIX0_PIM1LAH (PCIX0_CFGBASE + 0x00ac) -#define PCIX0_PIM2SA (PCIX0_CFGBASE + 0x00b0) -#define PCIX0_PIM2LAL (PCIX0_CFGBASE + 0x00b4) -#define PCIX0_PIM2LAH (PCIX0_CFGBASE + 0x00b8) - -#define PCIX0_STS (PCIX0_CFGBASE + 0x00e0) +#define PCIL0_VENDID (PCIL0_CFGBASE + PCI_VENDOR_ID ) +#define PCIL0_DEVID (PCIL0_CFGBASE + PCI_DEVICE_ID ) +#define PCIL0_CMD (PCIL0_CFGBASE + PCI_COMMAND ) +#define PCIL0_STATUS (PCIL0_CFGBASE + PCI_STATUS ) +#define PCIL0_REVID (PCIL0_CFGBASE + PCI_REVISION_ID ) +#define PCIL0_CLS (PCIL0_CFGBASE + PCI_CLASS_CODE) +#define PCIL0_CACHELS (PCIL0_CFGBASE + PCI_CACHE_LINE_SIZE ) +#define PCIL0_LATTIM (PCIL0_CFGBASE + PCI_LATENCY_TIMER ) +#define PCIL0_HDTYPE (PCIL0_CFGBASE + PCI_HEADER_TYPE ) +#define PCIL0_BIST (PCIL0_CFGBASE + PCI_BIST ) +#define PCIL0_BAR0 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_0 ) +#define PCIL0_BAR1 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_1 ) +#define PCIL0_BAR2 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_2 ) +#define PCIL0_BAR3 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_3 ) +#define PCIL0_BAR4 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_4 ) +#define PCIL0_BAR5 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_5 ) +#define PCIL0_CISPTR (PCIL0_CFGBASE + PCI_CARDBUS_CIS ) +#define PCIL0_SBSYSVID (PCIL0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID ) +#define PCIL0_SBSYSID (PCIL0_CFGBASE + PCI_SUBSYSTEM_ID ) +#define PCIL0_EROMBA (PCIL0_CFGBASE + PCI_ROM_ADDRESS ) +#define PCIL0_CAP (PCIL0_CFGBASE + PCI_CAPABILITY_LIST ) +#define PCIL0_RES0 (PCIL0_CFGBASE + 0x0035 ) +#define PCIL0_RES1 (PCIL0_CFGBASE + 0x0036 ) +#define PCIL0_RES2 (PCIL0_CFGBASE + 0x0038 ) +#define PCIL0_INTLN (PCIL0_CFGBASE + PCI_INTERRUPT_LINE ) +#define PCIL0_INTPN (PCIL0_CFGBASE + PCI_INTERRUPT_PIN ) +#define SDR0_EMACxTXST_FUR 0x02000000 /* TX FIFO underrun */ +#define SDR0_EMACxTXST_BC 0x01000000 /* broadcase address */ +#define SDR0_EMACxTXST_MC 0x00800000 /* multicast address */ +#define SDR0_EMACxTXST_UC 0x00400000 /* unicast address */ +#define SDR0_EMACxTXST_FP 0x00200000 /* frame paused by control packet */ +#define SDR0_EMACxTXST_BFCS 0x00100000 /* bad FCS in the transmitted frame*/ +#define SDR0_EMACxTXST_CPF 0x00080000 /* TX control pause frame */ +#define SDR0_EMACxTXST_CF 0x00040000 /* TX control frame */ +#define SDR0_EMACxTXST_MSIZ 0x00020000 /* 1024-maxsize bytes transmitted */ +#define SDR0_EMACxTXST_1023 0x00010000 /* 512-1023 bytes transmitted */ +#define SDR0_EMACxTXST_511 0x00008000 /* 256-511 bytes transmitted */ +#define SDR0_EMACxTXST_255 0x00004000 /* 128-255 bytes transmitted */ +#define SDR0_EMACxTXST_127 0x00002000 /* 65-127 bytes transmitted */ +#define SDR0_EMACxTXST_64 0x00001000 /* 64 bytes transmitted */ +#define SDR0_EMACxTXST_SQE 0x00000800 /* SQE indication */ +#define SDR0_EMACxTXST_LOC 0x00000400 /* loss of carrier sense */ +#define SDR0_EMACxTXST_IERR 0x00000080 /* EMAC internal error */ +#define SDR0_EMACxTXST_EDF 0x00000040 /* excessive deferral */ +#define SDR0_EMACxTXST_ECOL 0x00000020 /* excessive collisions */ +#define SDR0_EMACxTXST_LCOL 0x00000010 /* late collision */ +#define SDR0_EMACxTXST_DFFR 0x00000008 /* deferred frame */ +#define SDR0_EMACxTXST_MCOL 0x00000004 /* multiple collision frame */ +#define SDR0_EMACxTXST_SCOL 0x00000002 /* single collision frame */ +#define SDR0_EMACxTXST_TXOK 0x00000001 /* transmit OK */ + +#define PCIL0_MINGNT (PCIL0_CFGBASE + PCI_MIN_GNT ) +#define PCIL0_MAXLTNCY (PCIL0_CFGBASE + PCI_MAX_LAT ) + +#define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040) +#define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044) + +#define PCIL0_POM0LAL (PCIL0_CFGBASE + 0x0068) +#define PCIL0_POM0LAH (PCIL0_CFGBASE + 0x006c) +#define PCIL0_POM0SA (PCIL0_CFGBASE + 0x0070) +#define PCIL0_POM0PCIAL (PCIL0_CFGBASE + 0x0074) +#define PCIL0_POM0PCIAH (PCIL0_CFGBASE + 0x0078) +#define PCIL0_POM1LAL (PCIL0_CFGBASE + 0x007c) +#define PCIL0_POM1LAH (PCIL0_CFGBASE + 0x0080) +#define PCIL0_POM1SA (PCIL0_CFGBASE + 0x0084) +#define PCIL0_POM1PCIAL (PCIL0_CFGBASE + 0x0088) +#define PCIL0_POM1PCIAH (PCIL0_CFGBASE + 0x008c) +#define PCIL0_POM2SA (PCIL0_CFGBASE + 0x0090) + +#define PCIL0_PIM0SA (PCIL0_CFGBASE + 0x0098) +#define PCIL0_PIM0LAL (PCIL0_CFGBASE + 0x009c) +#define PCIL0_PIM0LAH (PCIL0_CFGBASE + 0x00a0) +#define PCIL0_PIM1SA (PCIL0_CFGBASE + 0x00a4) +#define PCIL0_PIM1LAL (PCIL0_CFGBASE + 0x00a8) +#define PCIL0_PIM1LAH (PCIL0_CFGBASE + 0x00ac) +#define PCIL0_PIM2SA (PCIL0_CFGBASE + 0x00b0) +#define PCIL0_PIM2LAL (PCIL0_CFGBASE + 0x00b4) +#define PCIL0_PIM2LAH (PCIL0_CFGBASE + 0x00b8) + +#define PCIL0_STS (PCIL0_CFGBASE + 0x00e0) #endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */ @@ -1694,24 +1856,41 @@ #define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) -#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for Endpoint 0 plus IN Endpoints 1 to 3 */ -#define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management register */ -#define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address register */ -#define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRIN */ -#define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for OUT Endpoints 1 to 3 */ -#define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for USB2D0_INTRUSB */ -#define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for common USB interrupts */ -#define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable register for IntrOut */ -#define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 test modes */ -#define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for selecting the Endpoint status/control registers */ +#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for + Endpoint 0 plus IN Endpoints 1 to 3 */ +#define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management + register */ +#define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address + register */ +#define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable + register for USB2D0_INTRIN */ +#define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for + OUT Endpoints 1 to 3 */ +#define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable + register for USB2D0_INTRUSB */ +#define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for + common USB interrupts */ +#define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable + register for IntrOut */ +#define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 + test modes */ +#define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for + selecting the Endpoint status/control registers */ #define USB2D0_FRAME (USB2D0_BASE + 0x00000000) /* Frame number */ -#define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status register for Endpoint 0. (Index register set to select Endpoint 0) */ -#define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status register for IN Endpoint. (Index register set to select Endpoints 13) */ -#define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for IN Endpoint. (Index register set to select Endpoints 13) */ -#define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status register for OUT Endpoint. (Index register set to select Endpoints 13) */ -#define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet size for OUT Endpoint. (Index register set to select Endpoints 13) */ -#define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */ -#define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in OUT Endpoint FIFO. (Index register set to select Endpoints 13) */ +#define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status + register for Endpoint 0. (Index register set to select Endpoint 0) */ +#define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status + register for IN Endpoint. (Index register set to select Endpoints 13) */ +#define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet + size for IN Endpoint. (Index register set to select Endpoints 13) */ +#define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status + register for OUT Endpoint. (Index register set to select Endpoints 13) */ +#define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet + size for OUT Endpoint. (Index register set to select Endpoints 13) */ +#define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received + bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */ +#define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in + OUT Endpoint FIFO. (Index register set to select Endpoints 13) */ #endif /****************************************************************************** @@ -1720,55 +1899,55 @@ #if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ defined(CONFIG_460SX) -#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000700) +#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000700) -#define GPIO0_OR (GPIO0_BASE+0x0) -#define GPIO0_TCR (GPIO0_BASE+0x4) -#define GPIO0_ODR (GPIO0_BASE+0x18) -#define GPIO0_IR (GPIO0_BASE+0x1C) +#define GPIO0_OR (GPIO0_BASE+0x0) +#define GPIO0_TCR (GPIO0_BASE+0x4) +#define GPIO0_ODR (GPIO0_BASE+0x18) +#define GPIO0_IR (GPIO0_BASE+0x1C) #endif /* CONFIG_440GP */ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000B00) -#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000C00) - -#define GPIO0_OR (GPIO0_BASE+0x0) -#define GPIO0_TCR (GPIO0_BASE+0x4) -#define GPIO0_OSRL (GPIO0_BASE+0x8) -#define GPIO0_OSRH (GPIO0_BASE+0xC) -#define GPIO0_TSRL (GPIO0_BASE+0x10) -#define GPIO0_TSRH (GPIO0_BASE+0x14) -#define GPIO0_ODR (GPIO0_BASE+0x18) -#define GPIO0_IR (GPIO0_BASE+0x1C) -#define GPIO0_RR1 (GPIO0_BASE+0x20) -#define GPIO0_RR2 (GPIO0_BASE+0x24) -#define GPIO0_RR3 (GPIO0_BASE+0x28) -#define GPIO0_ISR1L (GPIO0_BASE+0x30) -#define GPIO0_ISR1H (GPIO0_BASE+0x34) -#define GPIO0_ISR2L (GPIO0_BASE+0x38) -#define GPIO0_ISR2H (GPIO0_BASE+0x3C) -#define GPIO0_ISR3L (GPIO0_BASE+0x40) -#define GPIO0_ISR3H (GPIO0_BASE+0x44) - -#define GPIO1_OR (GPIO1_BASE+0x0) -#define GPIO1_TCR (GPIO1_BASE+0x4) -#define GPIO1_OSRL (GPIO1_BASE+0x8) -#define GPIO1_OSRH (GPIO1_BASE+0xC) -#define GPIO1_TSRL (GPIO1_BASE+0x10) -#define GPIO1_TSRH (GPIO1_BASE+0x14) -#define GPIO1_ODR (GPIO1_BASE+0x18) -#define GPIO1_IR (GPIO1_BASE+0x1C) -#define GPIO1_RR1 (GPIO1_BASE+0x20) -#define GPIO1_RR2 (GPIO1_BASE+0x24) -#define GPIO1_RR3 (GPIO1_BASE+0x28) -#define GPIO1_ISR1L (GPIO1_BASE+0x30) -#define GPIO1_ISR1H (GPIO1_BASE+0x34) -#define GPIO1_ISR2L (GPIO1_BASE+0x38) -#define GPIO1_ISR2H (GPIO1_BASE+0x3C) -#define GPIO1_ISR3L (GPIO1_BASE+0x40) -#define GPIO1_ISR3H (GPIO1_BASE+0x44) +#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000B00) +#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000C00) + +#define GPIO0_OR (GPIO0_BASE+0x0) +#define GPIO0_TCR (GPIO0_BASE+0x4) +#define GPIO0_OSRL (GPIO0_BASE+0x8) +#define GPIO0_OSRH (GPIO0_BASE+0xC) +#define GPIO0_TSRL (GPIO0_BASE+0x10) +#define GPIO0_TSRH (GPIO0_BASE+0x14) +#define GPIO0_ODR (GPIO0_BASE+0x18) +#define GPIO0_IR (GPIO0_BASE+0x1C) +#define GPIO0_RR1 (GPIO0_BASE+0x20) +#define GPIO0_RR2 (GPIO0_BASE+0x24) +#define GPIO0_RR3 (GPIO0_BASE+0x28) +#define GPIO0_ISR1L (GPIO0_BASE+0x30) +#define GPIO0_ISR1H (GPIO0_BASE+0x34) +#define GPIO0_ISR2L (GPIO0_BASE+0x38) +#define GPIO0_ISR2H (GPIO0_BASE+0x3C) +#define GPIO0_ISR3L (GPIO0_BASE+0x40) +#define GPIO0_ISR3H (GPIO0_BASE+0x44) + +#define GPIO1_OR (GPIO1_BASE+0x0) +#define GPIO1_TCR (GPIO1_BASE+0x4) +#define GPIO1_OSRL (GPIO1_BASE+0x8) +#define GPIO1_OSRH (GPIO1_BASE+0xC) +#define GPIO1_TSRL (GPIO1_BASE+0x10) +#define GPIO1_TSRH (GPIO1_BASE+0x14) +#define GPIO1_ODR (GPIO1_BASE+0x18) +#define GPIO1_IR (GPIO1_BASE+0x1C) +#define GPIO1_RR1 (GPIO1_BASE+0x20) +#define GPIO1_RR2 (GPIO1_BASE+0x24) +#define GPIO1_RR3 (GPIO1_BASE+0x28) +#define GPIO1_ISR1L (GPIO1_BASE+0x30) +#define GPIO1_ISR1H (GPIO1_BASE+0x34) +#define GPIO1_ISR2L (GPIO1_BASE+0x38) +#define GPIO1_ISR2H (GPIO1_BASE+0x3C) +#define GPIO1_ISR3L (GPIO1_BASE+0x40) +#define GPIO1_ISR3H (GPIO1_BASE+0x44) #endif #ifndef __ASSEMBLY__ diff --git a/include/ppc4xx.h b/include/ppc4xx.h index 086f8fb7ee..3bff00a559 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -136,12 +136,12 @@ * Common stuff for 4xx (405 and 440) */ -#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ +#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ #define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000) #define RESET_VECTOR 0xfffffffc -#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for cache - line aligned data. */ +#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for + cache line aligned data. */ #define CPR0_DCR_BASE 0x0C #define CPR0_CFGADDR (CPR0_DCR_BASE + 0x0) @@ -162,17 +162,25 @@ /* * Macros for indirect DCR access */ -#define mtcpr(reg, d) do { mtdcr(CPR0_CFGADDR,reg);mtdcr(CPR0_CFGDATA,d); } while (0) -#define mfcpr(reg, d) do { mtdcr(CPR0_CFGADDR,reg);d = mfdcr(CPR0_CFGDATA); } while (0) - -#define mtebc(reg, d) do { mtdcr(EBC0_CFGADDR,reg);mtdcr(EBC0_CFGDATA,d); } while (0) -#define mfebc(reg, d) do { mtdcr(EBC0_CFGADDR,reg);d = mfdcr(EBC0_CFGDATA); } while (0) - -#define mtsdram(reg, d) do { mtdcr(SDRAM0_CFGADDR,reg);mtdcr(SDRAM0_CFGDATA,d); } while (0) -#define mfsdram(reg, d) do { mtdcr(SDRAM0_CFGADDR,reg);d = mfdcr(SDRAM0_CFGDATA); } while (0) - -#define mtsdr(reg, d) do { mtdcr(SDR0_CFGADDR,reg);mtdcr(SDR0_CFGDATA,d); } while (0) -#define mfsdr(reg, d) do { mtdcr(SDR0_CFGADDR,reg);d = mfdcr(SDR0_CFGDATA); } while (0) +#define mtcpr(reg, d) \ + do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0) +#define mfcpr(reg, d) \ + do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0) + +#define mtebc(reg, d) \ + do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0) +#define mfebc(reg, d) \ + do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0) + +#define mtsdram(reg, d) \ + do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0) +#define mfsdram(reg, d) \ + do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0) + +#define mtsdr(reg, d) \ + do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0) +#define mfsdr(reg, d) \ + do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0) #ifndef __ASSEMBLY__ diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h index 7588e93ceb..3095aedc38 100644 --- a/include/ppc4xx_enet.h +++ b/include/ppc4xx_enet.h @@ -119,11 +119,11 @@ typedef struct emac_4xx_hw_st { int first_init; int tx_err_index; int rx_err_index; - int rx_slot; /* MAL Receive Slot */ - int rx_i_index; /* Receive Interrupt Queue Index */ - int rx_u_index; /* Receive User Queue Index */ - int tx_slot; /* MAL Transmit Slot */ - int tx_i_index; /* Transmit Interrupt Queue Index */ + int rx_slot; /* MAL Receive Slot */ + int rx_i_index; /* Receive Interrupt Queue Index */ + int rx_u_index; /* Receive User Queue Index */ + int tx_slot; /* MAL Transmit Slot */ + int tx_i_index; /* Transmit Interrupt Queue Index */ int tx_u_index; /* Transmit User Queue Index */ int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */ int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */ @@ -173,13 +173,13 @@ typedef struct emac_4xx_hw_st { #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define ZMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0D00) +#define ZMII0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0D00) #else -#define ZMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0780) +#define ZMII0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0780) #endif -#define ZMII_FER (ZMII_BASE) -#define ZMII_SSR (ZMII_BASE + 4) -#define ZMII_SMIISR (ZMII_BASE + 8) +#define ZMII0_FER (ZMII0_BASE) +#define ZMII0_SSR (ZMII0_BASE + 4) +#define ZMII0_SMIISR (ZMII0_BASE + 8) /* ZMII FER Register Bit Definitions */ #define ZMII_FER_DIS (0x0) @@ -196,25 +196,25 @@ typedef struct emac_4xx_hw_st { /* ZMII Speed Selection Register Bit Definitions */ -#define ZMII_SSR_SCI (0x4) -#define ZMII_SSR_FSS (0x2) -#define ZMII_SSR_SP (0x1) -#define ZMII_SSR_RSVD16_31 (0x0000FFFF) +#define ZMII0_SSR_SCI (0x4) +#define ZMII0_SSR_FSS (0x2) +#define ZMII0_SSR_SP (0x1) +#define ZMII0_SSR_RSVD16_31 (0x0000FFFF) -#define ZMII_SSR_V(__x) (((3 - __x) * 4) + 16) +#define ZMII0_SSR_V(__x) (((3 - __x) * 4) + 16) /* ZMII SMII Status Register Bit Definitions */ -#define ZMII_SMIISR_E1 (0x80) -#define ZMII_SMIISR_EC (0x40) -#define ZMII_SMIISR_EN (0x20) -#define ZMII_SMIISR_EJ (0x10) -#define ZMII_SMIISR_EL (0x08) -#define ZMII_SMIISR_ED (0x04) -#define ZMII_SMIISR_ES (0x02) -#define ZMII_SMIISR_EF (0x01) +#define ZMII0_SMIISR_E1 (0x80) +#define ZMII0_SMIISR_EC (0x40) +#define ZMII0_SMIISR_EN (0x20) +#define ZMII0_SMIISR_EJ (0x10) +#define ZMII0_SMIISR_EL (0x08) +#define ZMII0_SMIISR_ED (0x04) +#define ZMII0_SMIISR_ES (0x02) +#define ZMII0_SMIISR_EF (0x01) -#define ZMII_SMIISR_V(__x) ((3 - __x) * 8) +#define ZMII0_SMIISR_V(__x) ((3 - __x) * 8) /* RGMII Register Addresses */ #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) @@ -262,16 +262,16 @@ typedef struct emac_4xx_hw_st { | TCP/IP Acceleration Hardware (TAH) 440GX Only +---------------------------------------------------------------------------*/ #if defined(CONFIG_440GX) -#define TAH_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0B50) -#define TAH_REVID (TAH_BASE + 0x0) /* Revision ID (RO)*/ -#define TAH_MR (TAH_BASE + 0x10) /* Mode Register (R/W) */ -#define TAH_SSR0 (TAH_BASE + 0x14) /* Segment Size Reg 0 (R/W) */ -#define TAH_SSR1 (TAH_BASE + 0x18) /* Segment Size Reg 1 (R/W) */ -#define TAH_SSR2 (TAH_BASE + 0x1C) /* Segment Size Reg 2 (R/W) */ -#define TAH_SSR3 (TAH_BASE + 0x20) /* Segment Size Reg 3 (R/W) */ -#define TAH_SSR4 (TAH_BASE + 0x24) /* Segment Size Reg 4 (R/W) */ -#define TAH_SSR5 (TAH_BASE + 0x28) /* Segment Size Reg 5 (R/W) */ -#define TAH_TSR (TAH_BASE + 0x2C) /* Transmit Status Register (RO) */ +#define TAH_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0B50) +#define TAH_REVID (TAH_BASE + 0x0) /* Revision ID (RO)*/ +#define TAH_MR (TAH_BASE + 0x10) /* Mode Register (R/W) */ +#define TAH_SSR0 (TAH_BASE + 0x14) /* Segment Size Reg 0 (R/W) */ +#define TAH_SSR1 (TAH_BASE + 0x18) /* Segment Size Reg 1 (R/W) */ +#define TAH_SSR2 (TAH_BASE + 0x1C) /* Segment Size Reg 2 (R/W) */ +#define TAH_SSR3 (TAH_BASE + 0x20) /* Segment Size Reg 3 (R/W) */ +#define TAH_SSR4 (TAH_BASE + 0x24) /* Segment Size Reg 4 (R/W) */ +#define TAH_SSR5 (TAH_BASE + 0x28) /* Segment Size Reg 5 (R/W) */ +#define TAH_TSR (TAH_BASE + 0x2C) /* Transmit Status Register (RO) */ /* TAH Revision */ #define TAH_REV_RN_M (0x000FFF00) /* Revision Number */ @@ -281,45 +281,45 @@ typedef struct emac_4xx_hw_st { #define TAH_REV_BN_V (0) /* TAH Mode Register */ -#define TAH_MR_CVR (0x80000000) /* Checksum verification on RX */ -#define TAH_MR_SR (0x40000000) /* Software reset */ -#define TAH_MR_ST (0x3F000000) /* Send Threshold */ -#define TAH_MR_TFS (0x00E00000) /* Transmit FIFO size */ -#define TAH_MR_DTFP (0x00100000) /* Disable TX FIFO parity */ -#define TAH_MR_DIG (0x00080000) /* Disable interrupt generation */ -#define TAH_MR_RSVD (0x0007FFFF) /* Reserved */ +#define TAH_MR_CVR (0x80000000) /* Checksum verification on RX */ +#define TAH_MR_SR (0x40000000) /* Software reset */ +#define TAH_MR_ST (0x3F000000) /* Send Threshold */ +#define TAH_MR_TFS (0x00E00000) /* Transmit FIFO size */ +#define TAH_MR_DTFP (0x00100000) /* Disable TX FIFO parity */ +#define TAH_MR_DIG (0x00080000) /* Disable interrupt generation */ +#define TAH_MR_RSVD (0x0007FFFF) /* Reserved */ -#define TAH_MR_ST_V (20) -#define TAH_MR_TFS_V (17) +#define TAH_MR_ST_V (20) +#define TAH_MR_TFS_V (17) -#define TAH_MR_TFS_2K (0x1) /* Transmit FIFO size 2Kbyte */ -#define TAH_MR_TFS_4K (0x2) /* Transmit FIFO size 4Kbyte */ -#define TAH_MR_TFS_6K (0x3) /* Transmit FIFO size 6Kbyte */ -#define TAH_MR_TFS_8K (0x4) /* Transmit FIFO size 8Kbyte */ -#define TAH_MR_TFS_10K (0x5) /* Transmit FIFO size 10Kbyte (max)*/ +#define TAH_MR_TFS_2K (0x1) /* Transmit FIFO size 2Kbyte */ +#define TAH_MR_TFS_4K (0x2) /* Transmit FIFO size 4Kbyte */ +#define TAH_MR_TFS_6K (0x3) /* Transmit FIFO size 6Kbyte */ +#define TAH_MR_TFS_8K (0x4) /* Transmit FIFO size 8Kbyte */ +#define TAH_MR_TFS_10K (0x5) /* Transmit FIFO size 10Kbyte (max)*/ /* TAH Segment Size Registers 0:5 */ -#define TAH_SSR_RSVD0 (0xC0000000) /* Reserved */ -#define TAH_SSR_SS (0x3FFE0000) /* Segment size in multiples of 2 */ -#define TAH_SSR_RSVD1 (0x0001FFFF) /* Reserved */ +#define TAH_SSR_RSVD0 (0xC0000000) /* Reserved */ +#define TAH_SSR_SS (0x3FFE0000) /* Segment size in multiples of 2 */ +#define TAH_SSR_RSVD1 (0x0001FFFF) /* Reserved */ /* TAH Transmit Status Register */ -#define TAH_TSR_TFTS (0x80000000) /* Transmit FIFO too small */ -#define TAH_TSR_UH (0x40000000) /* Unrecognized header */ -#define TAH_TSR_NIPF (0x20000000) /* Not IPv4 */ -#define TAH_TSR_IPOP (0x10000000) /* IP option present */ -#define TAH_TSR_NISF (0x08000000) /* No IEEE SNAP format */ -#define TAH_TSR_ILTS (0x04000000) /* IP length too short */ -#define TAH_TSR_IPFP (0x02000000) /* IP fragment present */ -#define TAH_TSR_UP (0x01000000) /* Unsupported protocol */ -#define TAH_TSR_TFP (0x00800000) /* TCP flags present */ -#define TAH_TSR_SUDP (0x00400000) /* Segmentation for UDP */ -#define TAH_TSR_DLM (0x00200000) /* Data length mismatch */ -#define TAH_TSR_SIEEE (0x00100000) /* Segmentation for IEEE */ -#define TAH_TSR_TFPE (0x00080000) /* Transmit FIFO parity error */ -#define TAH_TSR_SSTS (0x00040000) /* Segment size too small */ -#define TAH_TSR_RSVD (0x0003FFFF) /* Reserved */ +#define TAH_TSR_TFTS (0x80000000) /* Transmit FIFO too small */ +#define TAH_TSR_UH (0x40000000) /* Unrecognized header */ +#define TAH_TSR_NIPF (0x20000000) /* Not IPv4 */ +#define TAH_TSR_IPOP (0x10000000) /* IP option present */ +#define TAH_TSR_NISF (0x08000000) /* No IEEE SNAP format */ +#define TAH_TSR_ILTS (0x04000000) /* IP length too short */ +#define TAH_TSR_IPFP (0x02000000) /* IP fragment present */ +#define TAH_TSR_UP (0x01000000) /* Unsupported protocol */ +#define TAH_TSR_TFP (0x00800000) /* TCP flags present */ +#define TAH_TSR_SUDP (0x00400000) /* Segmentation for UDP */ +#define TAH_TSR_DLM (0x00200000) /* Data length mismatch */ +#define TAH_TSR_SIEEE (0x00100000) /* Segmentation for IEEE */ +#define TAH_TSR_TFPE (0x00080000) /* Transmit FIFO parity error */ +#define TAH_TSR_SSTS (0x00040000) /* Segment size too small */ +#define TAH_TSR_RSVD (0x0003FFFF) /* Reserved */ #endif /* CONFIG_440GX */ @@ -328,41 +328,49 @@ typedef struct emac_4xx_hw_st { #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define EMAC_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0E00) +#define EMAC0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0E00) #else -#define EMAC_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800) +#define EMAC0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800) #endif #else #if defined(CONFIG_405EZ) || defined(CONFIG_405EX) -#define EMAC_BASE 0xEF600900 +#define EMAC0_BASE 0xEF600900 #else -#define EMAC_BASE 0xEF600800 +#define EMAC0_BASE 0xEF600800 #endif #endif -#define EMAC_M0 (EMAC_BASE) -#define EMAC_M1 (EMAC_BASE + 4) -#define EMAC_TXM0 (EMAC_BASE + 8) -#define EMAC_TXM1 (EMAC_BASE + 12) -#define EMAC_RXM (EMAC_BASE + 16) -#define EMAC_ISR (EMAC_BASE + 20) -#define EMAC_IER (EMAC_BASE + 24) -#define EMAC_IAH (EMAC_BASE + 28) -#define EMAC_IAL (EMAC_BASE + 32) -#define EMAC_PAUSE_TIME_REG (EMAC_BASE + 44) -#define EMAC_I_FRAME_GAP_REG (EMAC_BASE + 88) -#define EMAC_STACR (EMAC_BASE + 92) -#define EMAC_TRTR (EMAC_BASE + 96) -#define EMAC_RX_HI_LO_WMARK (EMAC_BASE + 100) +#if defined(CONFIG_440EPX) +#define EMAC1_BASE 0xEF600F00 +#define EMAC1_MR1 (EMAC1_BASE + 0x04) +#endif + +#define EMAC0_MR0 (EMAC0_BASE) +#define EMAC0_MR1 (EMAC0_BASE + 0x04) +#define EMAC0_TMR0 (EMAC0_BASE + 0x08) +#define EMAC0_TMR1 (EMAC0_BASE + 0x0c) +#define EMAC0_RXM (EMAC0_BASE + 0x10) +#define EMAC0_ISR (EMAC0_BASE + 0x14) +#define EMAC0_IER (EMAC0_BASE + 0x18) +#define EMAC0_IAH (EMAC0_BASE + 0x1c) +#define EMAC0_IAL (EMAC0_BASE + 0x20) +#define EMAC0_PTR (EMAC0_BASE + 0x2c) +#define EMAC0_PAUSE_TIME_REG EMAC0_PTR +#define EMAC0_IPGVR (EMAC0_BASE + 0x58) +#define EMAC0_I_FRAME_GAP_REG EMAC0_IPGVR +#define EMAC0_STACR (EMAC0_BASE + 0x5c) +#define EMAC0_TRTR (EMAC0_BASE + 0x60) +#define EMAC0_RWMR (EMAC0_BASE + 0x64) +#define EMAC0_RX_HI_LO_WMARK EMAC0_RWMR /* bit definitions */ /* MODE REG 0 */ -#define EMAC_M0_RXI (0x80000000) -#define EMAC_M0_TXI (0x40000000) -#define EMAC_M0_SRST (0x20000000) -#define EMAC_M0_TXE (0x10000000) -#define EMAC_M0_RXE (0x08000000) -#define EMAC_M0_WKE (0x04000000) +#define EMAC_MR0_RXI (0x80000000) +#define EMAC_MR0_TXI (0x40000000) +#define EMAC_MR0_SRST (0x20000000) +#define EMAC_MR0_TXE (0x10000000) +#define EMAC_MR0_RXE (0x08000000) +#define EMAC_MR0_WKE (0x04000000) /* on 440GX EMAC_MR1 has a different layout! */ #if defined(CONFIG_440GX) || \ @@ -371,82 +379,82 @@ typedef struct emac_4xx_hw_st { defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ defined(CONFIG_405EX) /* MODE Reg 1 */ -#define EMAC_M1_FDE (0x80000000) -#define EMAC_M1_ILE (0x40000000) -#define EMAC_M1_VLE (0x20000000) -#define EMAC_M1_EIFC (0x10000000) -#define EMAC_M1_APP (0x08000000) -#define EMAC_M1_RSVD (0x06000000) -#define EMAC_M1_IST (0x01000000) -#define EMAC_M1_MF_1000GPCS (0x00C00000) -#define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */ -#define EMAC_M1_MF_100MBPS (0x00400000) -#define EMAC_M1_RFS_MASK (0x00380000) -#define EMAC_M1_RFS_16K (0x00280000) -#define EMAC_M1_RFS_8K (0x00200000) -#define EMAC_M1_RFS_4K (0x00180000) -#define EMAC_M1_RFS_2K (0x00100000) -#define EMAC_M1_RFS_1K (0x00080000) -#define EMAC_M1_TX_FIFO_MASK (0x00070000) -#define EMAC_M1_TX_FIFO_16K (0x00050000) -#define EMAC_M1_TX_FIFO_8K (0x00040000) -#define EMAC_M1_TX_FIFO_4K (0x00030000) -#define EMAC_M1_TX_FIFO_2K (0x00020000) -#define EMAC_M1_TX_FIFO_1K (0x00010000) -#define EMAC_M1_TR_MULTI (0x00008000) /* 0'x for single packet */ -#define EMAC_M1_MWSW (0x00007000) -#define EMAC_M1_JUMBO_ENABLE (0x00000800) -#define EMAC_M1_IPPA (0x000007c0) -#define EMAC_M1_IPPA_SET(id) (((id) & 0x1f) << 6) -#define EMAC_M1_IPPA_GET(id) (((id) >> 6) & 0x1f) -#define EMAC_M1_OBCI_GT100 (0x00000020) -#define EMAC_M1_OBCI_100 (0x00000018) -#define EMAC_M1_OBCI_83 (0x00000010) -#define EMAC_M1_OBCI_66 (0x00000008) -#define EMAC_M1_RSVD1 (0x00000007) +#define EMAC_MR1_FDE (0x80000000) +#define EMAC_MR1_ILE (0x40000000) +#define EMAC_MR1_VLE (0x20000000) +#define EMAC_MR1_EIFC (0x10000000) +#define EMAC_MR1_APP (0x08000000) +#define EMAC_MR1_RSVD (0x06000000) +#define EMAC_MR1_IST (0x01000000) +#define EMAC_MR1_MF_1000GPCS (0x00C00000) +#define EMAC_MR1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */ +#define EMAC_MR1_MF_100MBPS (0x00400000) +#define EMAC_MR1_RFS_MASK (0x00380000) +#define EMAC_MR1_RFS_16K (0x00280000) +#define EMAC_MR1_RFS_8K (0x00200000) +#define EMAC_MR1_RFS_4K (0x00180000) +#define EMAC_MR1_RFS_2K (0x00100000) +#define EMAC_MR1_RFS_1K (0x00080000) +#define EMAC_MR1_TX_FIFO_MASK (0x00070000) +#define EMAC_MR1_TX_FIFO_16K (0x00050000) +#define EMAC_MR1_TX_FIFO_8K (0x00040000) +#define EMAC_MR1_TX_FIFO_4K (0x00030000) +#define EMAC_MR1_TX_FIFO_2K (0x00020000) +#define EMAC_MR1_TX_FIFO_1K (0x00010000) +#define EMAC_MR1_TR_MULTI (0x00008000) /* 0'x for single packet */ +#define EMAC_MR1_MWSW (0x00007000) +#define EMAC_MR1_JUMBO_ENABLE (0x00000800) +#define EMAC_MR1_IPPA (0x000007c0) +#define EMAC_MR1_IPPA_SET(id) (((id) & 0x1f) << 6) +#define EMAC_MR1_IPPA_GET(id) (((id) >> 6) & 0x1f) +#define EMAC_MR1_OBCI_GT100 (0x00000020) +#define EMAC_MR1_OBCI_100 (0x00000018) +#define EMAC_MR1_OBCI_83 (0x00000010) +#define EMAC_MR1_OBCI_66 (0x00000008) +#define EMAC_MR1_RSVD1 (0x00000007) #else /* defined(CONFIG_440GX) */ /* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */ -#define EMAC_M1_FDE 0x80000000 -#define EMAC_M1_ILE 0x40000000 -#define EMAC_M1_VLE 0x20000000 -#define EMAC_M1_EIFC 0x10000000 -#define EMAC_M1_APP 0x08000000 -#define EMAC_M1_AEMI 0x02000000 -#define EMAC_M1_IST 0x01000000 -#define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */ -#define EMAC_M1_MF_100MBPS 0x00400000 -#define EMAC_M1_RFS_MASK 0x00300000 -#define EMAC_M1_RFS_4K 0x00300000 -#define EMAC_M1_RFS_2K 0x00200000 -#define EMAC_M1_RFS_1K 0x00100000 -#define EMAC_M1_RFS_512 0x00000000 -#define EMAC_M1_TX_FIFO_MASK 0x000c0000 -#define EMAC_M1_TX_FIFO_2K 0x00080000 -#define EMAC_M1_TX_FIFO_1K 0x00040000 -#define EMAC_M1_TX_FIFO_512 0x00000000 -#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */ -#define EMAC_M1_TR0_MULTI 0x00008000 -#define EMAC_M1_TR1_DEPEND 0x00004000 -#define EMAC_M1_TR1_MULTI 0x00002000 +#define EMAC_MR1_FDE 0x80000000 +#define EMAC_MR1_ILE 0x40000000 +#define EMAC_MR1_VLE 0x20000000 +#define EMAC_MR1_EIFC 0x10000000 +#define EMAC_MR1_APP 0x08000000 +#define EMAC_MR1_AEMI 0x02000000 +#define EMAC_MR1_IST 0x01000000 +#define EMAC_MR1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */ +#define EMAC_MR1_MF_100MBPS 0x00400000 +#define EMAC_MR1_RFS_MASK 0x00300000 +#define EMAC_MR1_RFS_4K 0x00300000 +#define EMAC_MR1_RFS_2K 0x00200000 +#define EMAC_MR1_RFS_1K 0x00100000 +#define EMAC_MR1_RFS_512 0x00000000 +#define EMAC_MR1_TX_FIFO_MASK 0x000c0000 +#define EMAC_MR1_TX_FIFO_2K 0x00080000 +#define EMAC_MR1_TX_FIFO_1K 0x00040000 +#define EMAC_MR1_TX_FIFO_512 0x00000000 +#define EMAC_MR1_TR0_DEPEND 0x00010000 /* 0'x for single packet */ +#define EMAC_MR1_TR0_MULTI 0x00008000 +#define EMAC_MR1_TR1_DEPEND 0x00004000 +#define EMAC_MR1_TR1_MULTI 0x00002000 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) -#define EMAC_M1_JUMBO_ENABLE 0x00001000 +#define EMAC_MR1_JUMBO_ENABLE 0x00001000 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */ #endif /* defined(CONFIG_440GX) */ -#define EMAC_MR1_FIFO_MASK (EMAC_M1_RFS_MASK | EMAC_M1_TX_FIFO_MASK) +#define EMAC_MR1_FIFO_MASK (EMAC_MR1_RFS_MASK | EMAC_MR1_TX_FIFO_MASK) #if defined(CONFIG_405EZ) /* 405EZ only supports 512 bytes fifos */ -#define EMAC_MR1_FIFO_SIZE (EMAC_M1_RFS_512 | EMAC_M1_TX_FIFO_512) +#define EMAC_MR1_FIFO_SIZE (EMAC_MR1_RFS_512 | EMAC_MR1_TX_FIFO_512) #else /* Set receive fifo to 4k and tx fifo to 2k */ -#define EMAC_MR1_FIFO_SIZE (EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K) +#define EMAC_MR1_FIFO_SIZE (EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K) #endif /* Transmit Mode Register 0 */ -#define EMAC_TXM0_GNP0 (0x80000000) -#define EMAC_TXM0_GNP1 (0x40000000) -#define EMAC_TXM0_GNPD (0x20000000) -#define EMAC_TXM0_FC (0x10000000) +#define EMAC_TMR0_GNP0 (0x80000000) +#define EMAC_TMR0_GNP1 (0x40000000) +#define EMAC_TMR0_GNPD (0x20000000) +#define EMAC_TMR0_FC (0x10000000) /* Receive Mode Register */ #define EMAC_RMR_SP (0x80000000) diff --git a/include/spartan2.h b/include/spartan2.h index 7327857c12..8959f90f0e 100644 --- a/include/spartan2.h +++ b/include/spartan2.h @@ -30,7 +30,6 @@ extern int Spartan2_load( Xilinx_desc *desc, void *image, size_t size ); extern int Spartan2_dump( Xilinx_desc *desc, void *buf, size_t bsize ); extern int Spartan2_info( Xilinx_desc *desc ); -extern int Spartan2_reloc( Xilinx_desc *desc, ulong reloc_off ); /* Slave Parallel Implementation function table */ typedef struct { @@ -47,7 +46,6 @@ typedef struct { Xilinx_busy_fn busy; Xilinx_abort_fn abort; Xilinx_post_fn post; - int relocated; } Xilinx_Spartan2_Slave_Parallel_fns; /* Slave Serial Implementation function table */ @@ -59,7 +57,6 @@ typedef struct { Xilinx_done_fn done; Xilinx_wr_fn wr; Xilinx_post_fn post; - int relocated; } Xilinx_Spartan2_Slave_Serial_fns; /* Device Image Sizes diff --git a/include/spartan3.h b/include/spartan3.h index b0fa1cdaee..30b1c2d62d 100644 --- a/include/spartan3.h +++ b/include/spartan3.h @@ -30,7 +30,6 @@ extern int Spartan3_load( Xilinx_desc *desc, void *image, size_t size ); extern int Spartan3_dump( Xilinx_desc *desc, void *buf, size_t bsize ); extern int Spartan3_info( Xilinx_desc *desc ); -extern int Spartan3_reloc( Xilinx_desc *desc, ulong reloc_off ); /* Slave Parallel Implementation function table */ typedef struct { @@ -47,7 +46,6 @@ typedef struct { Xilinx_busy_fn busy; Xilinx_abort_fn abort; Xilinx_post_fn post; - int relocated; } Xilinx_Spartan3_Slave_Parallel_fns; /* Slave Serial Implementation function table */ @@ -59,7 +57,6 @@ typedef struct { Xilinx_done_fn done; Xilinx_wr_fn wr; Xilinx_post_fn post; - int relocated; } Xilinx_Spartan3_Slave_Serial_fns; /* Device Image Sizes diff --git a/include/stratixII.h b/include/stratixII.h index 37abd9fa44..b8e84573c7 100644 --- a/include/stratixII.h +++ b/include/stratixII.h @@ -27,6 +27,5 @@ extern int StratixII_load (Altera_desc * desc, void *image, size_t size); extern int StratixII_dump (Altera_desc * desc, void *buf, size_t bsize); extern int StratixII_info (Altera_desc * desc); -extern int StratixII_reloc (Altera_desc * desc, ulong reloc_off); #endif /* _STRATIXII_H_ */ diff --git a/include/virtex2.h b/include/virtex2.h index d1166479c4..89d7d76876 100644 --- a/include/virtex2.h +++ b/include/virtex2.h @@ -31,7 +31,6 @@ extern int Virtex2_load( Xilinx_desc *desc, void *image, size_t size ); extern int Virtex2_dump( Xilinx_desc *desc, void *buf, size_t bsize ); extern int Virtex2_info( Xilinx_desc *desc ); -extern int Virtex2_reloc( Xilinx_desc *desc, ulong reloc_off ); /* * Slave SelectMap Implementation function table. @@ -50,7 +49,6 @@ typedef struct { Xilinx_busy_fn busy; Xilinx_abort_fn abort; Xilinx_post_fn post; - int relocated; } Xilinx_Virtex2_Slave_SelectMap_fns; /* Slave Serial Implementation function table */ @@ -59,7 +57,6 @@ typedef struct { Xilinx_clk_fn clk; Xilinx_rdata_fn rdata; Xilinx_wdata_fn wdata; - int relocated; } Xilinx_Virtex2_Slave_Serial_fns; /* Device Image Sizes (in bytes) diff --git a/include/xilinx.h b/include/xilinx.h index fdc358725c..d0799bc572 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -84,7 +84,6 @@ typedef struct { /* typedef Xilinx_desc */ extern int xilinx_load( Xilinx_desc *desc, void *image, size_t size ); extern int xilinx_dump( Xilinx_desc *desc, void *buf, size_t bsize ); extern int xilinx_info( Xilinx_desc *desc ); -extern int xilinx_reloc( Xilinx_desc *desc, ulong reloc_offset ); /* Board specific implementation specific function types *********************************************************************/ diff --git a/lib_arm/board.c b/lib_arm/board.c index a0e56d5ae8..5e3d7f65b1 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -50,6 +50,10 @@ #include #include +#ifdef CONFIG_BITBANGMII +#include +#endif + #ifdef CONFIG_DRIVER_SMC91111 #include "../drivers/net/smc91111.h" #endif @@ -417,6 +421,9 @@ extern void davinci_eth_set_mac_addr (const u_int8_t *addr); mmc_initialize (gd->bd); #endif +#ifdef CONFIG_BITBANGMII + bb_miiphy_init(); +#endif #if defined(CONFIG_CMD_NET) #if defined(CONFIG_NET_MULTI) puts ("Net: "); diff --git a/lib_avr32/board.c b/lib_avr32/board.c index 29999d8635..917ed6ce75 100644 --- a/lib_avr32/board.c +++ b/lib_avr32/board.c @@ -27,6 +27,10 @@ #include #include +#ifdef CONFIG_BITBANGMII +#include +#endif + #include #include @@ -337,6 +341,9 @@ void board_init_r(gd_t *new_gd, ulong dest_addr) if (s) load_addr = simple_strtoul(s, NULL, 16); +#ifdef CONFIG_BITBANGMII + bb_miiphy_init(); +#endif #if defined(CONFIG_CMD_NET) s = getenv("bootfile"); if (s) diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c index 1053f694cb..3670d2caa4 100644 --- a/lib_blackfin/board.c +++ b/lib_blackfin/board.c @@ -26,6 +26,10 @@ #include /* cannot even include nand.h if it isnt configured */ #endif +#ifdef CONFIG_BITBANGMII +#include +#endif + #if defined(CONFIG_POST) #include int post_flag; @@ -270,6 +274,9 @@ void board_init_f(ulong bootflag) static void board_net_init_r(bd_t *bd) { +#ifdef CONFIG_BITBANGMII + bb_miiphy_init(); +#endif #ifdef CONFIG_CMD_NET uchar enetaddr[6]; char *s; diff --git a/lib_i386/board.c b/lib_i386/board.c index 0262b5e2cb..12ca20f608 100644 --- a/lib_i386/board.c +++ b/lib_i386/board.c @@ -1,6 +1,6 @@ /* * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, daniel@omicron.se + * Daniel Engstr�m, Omicron Ceti AB, daniel@omicron.se * * (C) Copyright 2002 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. @@ -39,6 +39,10 @@ #include #include +#ifdef CONFIG_BITBANGMII +#include +#endif + DECLARE_GLOBAL_DATA_PTR; extern long _i386boot_start; @@ -351,6 +355,9 @@ void start_i386boot (void) doc_init(); #endif +#ifdef CONFIG_BITBANGMII + bb_miiphy_init(); +#endif #if defined(CONFIG_CMD_NET) #if defined(CONFIG_NET_MULTI) WATCHDOG_RESET(); diff --git a/lib_m68k/board.c b/lib_m68k/board.c index 3d885306e2..732023d67c 100644 --- a/lib_m68k/board.c +++ b/lib_m68k/board.c @@ -63,6 +63,10 @@ #include #endif +#ifdef CONFIG_BITBANGMII +#include +#endif + #include DECLARE_GLOBAL_DATA_PTR; @@ -630,6 +634,9 @@ void board_init_r (gd_t *id, ulong dest_addr) nand_init(); /* go init the NAND */ #endif +#ifdef CONFIG_BITBANGMII + bb_miiphy_init(); +#endif #if defined(CONFIG_CMD_NET) WATCHDOG_RESET(); #if defined(FEC_ENET) diff --git a/lib_mips/board.c b/lib_mips/board.c index f62a46a172..b2d113e870 100644 --- a/lib_mips/board.c +++ b/lib_mips/board.c @@ -33,6 +33,10 @@ #include #include +#ifdef CONFIG_BITBANGMII +#include +#endif + DECLARE_GLOBAL_DATA_PTR; #if ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \ @@ -407,6 +411,9 @@ void board_init_r (gd_t *id, ulong dest_addr) misc_init_r (); #endif +#ifdef CONFIG_BITBANGMII + bb_miiphy_init(); +#endif #if defined(CONFIG_CMD_NET) #if defined(CONFIG_NET_MULTI) puts ("Net: "); diff --git a/lib_ppc/Makefile b/lib_ppc/Makefile index 60ea0c9139..399b41e31e 100644 --- a/lib_ppc/Makefile +++ b/lib_ppc/Makefile @@ -42,6 +42,12 @@ SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) $(LIB): $(obj).depend $(OBJS) + @if ! $(CROSS_COMPILE)readelf -S $(OBJS) | grep -q '\.fixup.*PROGBITS';\ + then \ + echo "ERROR: Your compiler doesn't generate .fixup sections!";\ + echo " Upgrade to a recent toolchain."; \ + exit 1; \ + fi; $(AR) $(ARFLAGS) $@ $(OBJS) ######################################################################### diff --git a/lib_ppc/board.c b/lib_ppc/board.c index f9dbdb9a86..796d00242b 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -83,6 +83,10 @@ #include #endif +#ifdef CONFIG_BITBANGMII +#include +#endif + #ifdef CONFIG_SYS_UPDATE_FLASH_SIZE extern int update_flash_size (int flash_size); #endif @@ -627,13 +631,8 @@ void board_init_f (ulong bootflag) */ void board_init_r (gd_t *id, ulong dest_addr) { - cmd_tbl_t *cmdtp; char *s; bd_t *bd; - extern void malloc_bin_reloc (void); -#ifndef CONFIG_ENV_IS_NOWHERE - extern char * env_name_spec; -#endif ulong malloc_start; #ifndef CONFIG_SYS_NO_FLASH @@ -646,18 +645,7 @@ void board_init_r (gd_t *id, ulong dest_addr) gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ /* The Malloc area is immediately below the monitor copy in DRAM */ -#if defined(CONFIG_RELOC_FIXUP_WORKS) - gd->reloc_off = 0; malloc_start = dest_addr - TOTAL_MALLOC_LEN; -#else - gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE; - malloc_start = CONFIG_SYS_MONITOR_BASE + gd->reloc_off - - TOTAL_MALLOC_LEN; -#endif - -#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) - gd->cpu += gd->reloc_off; -#endif #ifdef CONFIG_SERIAL_MULTI serial_initialize(); @@ -682,38 +670,6 @@ void board_init_r (gd_t *id, ulong dest_addr) monitor_flash_len = (ulong)&__init_end - dest_addr; - /* - * We have to relocate the command table manually - */ - for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) { - ulong addr; - addr = (ulong) (cmdtp->cmd) + gd->reloc_off; -#if 0 - printf ("Command \"%s\": 0x%08lx => 0x%08lx\n", - cmdtp->name, (ulong) (cmdtp->cmd), addr); -#endif - cmdtp->cmd = - (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr; - - addr = (ulong)(cmdtp->name) + gd->reloc_off; - cmdtp->name = (char *)addr; - - if (cmdtp->usage) { - addr = (ulong)(cmdtp->usage) + gd->reloc_off; - cmdtp->usage = (char *)addr; - } -#ifdef CONFIG_SYS_LONGHELP - if (cmdtp->help) { - addr = (ulong)(cmdtp->help) + gd->reloc_off; - cmdtp->help = (char *)addr; - } -#endif - } - /* there are some other pointer constants we must deal with */ -#ifndef CONFIG_ENV_IS_NOWHERE - env_name_spec += gd->reloc_off; -#endif - WATCHDOG_RESET (); #ifdef CONFIG_LOGBUFFER @@ -721,7 +677,6 @@ void board_init_r (gd_t *id, ulong dest_addr) #endif #ifdef CONFIG_POST post_output_backlog (); - post_reloc (); #endif WATCHDOG_RESET(); @@ -752,7 +707,6 @@ void board_init_r (gd_t *id, ulong dest_addr) asm ("sync ; isync"); mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN); - malloc_bin_reloc (); #if !defined(CONFIG_SYS_NO_FLASH) puts ("FLASH: "); @@ -992,6 +946,9 @@ void board_init_r (gd_t *id, ulong dest_addr) doc_init (); #endif +#ifdef CONFIG_BITBANGMII + bb_miiphy_init(); +#endif #if defined(CONFIG_CMD_NET) #if defined(CONFIG_NET_MULTI) WATCHDOG_RESET (); diff --git a/lib_ppc/config.mk b/lib_ppc/config.mk index 010d874da6..06a3b107d5 100644 --- a/lib_ppc/config.mk +++ b/lib_ppc/config.mk @@ -25,6 +25,7 @@ CROSS_COMPILE ?= ppc_8xx- STANDALONE_LOAD_ADDR = 0x40000 +PLATFORM_RELFLAGS += -mrelocatable PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__ PLATFORM_LDFLAGS += -n diff --git a/lib_ppc/extable.c b/lib_ppc/extable.c index 91e2b3d246..7408d5c969 100644 --- a/lib_ppc/extable.c +++ b/lib_ppc/extable.c @@ -53,27 +53,13 @@ search_one_table(const struct exception_table_entry *first, unsigned long value) { long diff; - if ((ulong) first > CONFIG_SYS_MONITOR_BASE) { - /* exception occurs in FLASH, before u-boot relocation. - * No relocation offset is needed. - */ - while (first <= last) { - diff = first->insn - value; - if (diff == 0) - return first->fixup; - first++; - } - } else { - /* exception occurs in RAM, after u-boot relocation. - * A relocation offset should be added. - */ - while (first <= last) { - diff = (first->insn + gd->reloc_off) - value; - if (diff == 0) - return (first->fixup + gd->reloc_off); - first++; - } + while (first <= last) { + diff = first->insn - value; + if (diff == 0) + return first->fixup; + first++; } + return 0; } diff --git a/lib_sh/board.c b/lib_sh/board.c index 5d61f0d74f..5ed40e922b 100644 --- a/lib_sh/board.c +++ b/lib_sh/board.c @@ -28,6 +28,10 @@ #include #include +#ifdef CONFIG_BITBANGMII +#include +#endif + extern void malloc_bin_reloc (void); extern int cpu_init(void); extern int board_init(void); @@ -178,6 +182,9 @@ void sh_generic_init(void) #endif /* CONFIG_WATCHDOG*/ +#ifdef CONFIG_BITBANGMII + bb_miiphy_init(); +#endif #if defined(CONFIG_CMD_NET) { char *s; diff --git a/lib_sparc/board.c b/lib_sparc/board.c index 6aadb56f63..11eea603c1 100644 --- a/lib_sparc/board.c +++ b/lib_sparc/board.c @@ -49,6 +49,10 @@ #include #endif +#ifdef CONFIG_BITBANGMII +#include +#endif + DECLARE_GLOBAL_DATA_PTR; /* Debug options @@ -405,6 +409,9 @@ void board_init_f(ulong bootflag) doc_init(); #endif +#ifdef CONFIG_BITBANGMII + bb_miiphy_init(); +#endif #if defined(CONFIG_CMD_NET) #if defined(CONFIG_NET_MULTI) WATCHDOG_RESET(); diff --git a/post/board/lwmon/sysmon.c b/post/board/lwmon/sysmon.c index 79a5151c01..fc828b2e50 100644 --- a/post/board/lwmon/sysmon.c +++ b/post/board/lwmon/sysmon.c @@ -56,8 +56,6 @@ static int sysmon_temp_invalid = 0; /* #define DEBUG */ -#define RELOC(x) if (x != NULL) x = (void *) ((ulong) (x) + gd->reloc_off) - typedef struct sysmon_s sysmon_t; typedef struct sysmon_table_s sysmon_table_t; @@ -159,20 +157,7 @@ int sysmon_init_f (void) void sysmon_reloc (void) { - sysmon_t ** l; - sysmon_table_t * t; - - for (l = sysmon_list; *l; l++) { - RELOC(*l); - RELOC((*l)->init); - RELOC((*l)->read); - } - - for (t = sysmon_table; t < sysmon_table + sysmon_table_size; t ++) { - RELOC(t->exec_before); - RELOC(t->exec_after); - RELOC(t->sysmon); - } + /* Do nothing for now, sysmon_reloc() is required by the sysmon post */ } static char *sysmon_unit_value (sysmon_table_t *s, uint val) diff --git a/post/board/lwmon5/sysmon.c b/post/board/lwmon5/sysmon.c index aef5bd018a..9c49d0e646 100644 --- a/post/board/lwmon5/sysmon.c +++ b/post/board/lwmon5/sysmon.c @@ -58,8 +58,6 @@ DECLARE_GLOBAL_DATA_PTR; /* from dspic.c */ extern int dspic_read(ushort reg); -#define RELOC(x) if (x != NULL) x = (void *) ((ulong) (x) + gd->reloc_off) - #define REG_TEMPERATURE 0x12BC #define REG_VOLTAGE_5V 0x12CA #define REG_VOLTAGE_5V_STANDBY 0x12C6 @@ -160,20 +158,7 @@ int sysmon_init_f (void) void sysmon_reloc (void) { - sysmon_t ** l; - sysmon_table_t * t; - - for (l = sysmon_list; *l; l++) { - RELOC(*l); - RELOC((*l)->init); - RELOC((*l)->read); - } - - for (t = sysmon_table; t < sysmon_table + sysmon_table_size; t ++) { - RELOC(t->exec_before); - RELOC(t->exec_after); - RELOC(t->sysmon); - } + /* Do nothing for now, sysmon_reloc() is required by the sysmon post */ } static char *sysmon_unit_value (sysmon_table_t *s, uint val) diff --git a/post/cpu/ppc4xx/ether.c b/post/cpu/ppc4xx/ether.c index c3665da94a..a58db04e49 100644 --- a/post/cpu/ppc4xx/ether.c +++ b/post/cpu/ppc4xx/ether.c @@ -115,11 +115,11 @@ static void ether_post_init (int devnum, int hw_addr) sync (); #endif /* reset emac */ - out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_SRST); + out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST); sync (); for (i = 0;; i++) { - if (!(in_be32 ((void*)(EMAC_M0 + hw_addr)) & EMAC_M0_SRST)) + if (!(in_be32 ((void*)(EMAC0_MR0 + hw_addr)) & EMAC_MR0_SRST)) break; if (i >= 1000) { printf ("Timeout resetting EMAC\n"); @@ -134,15 +134,15 @@ static void ether_post_init (int devnum, int hw_addr) mode_reg = 0x0; if (sysinfo.freqOPB <= 50000000); else if (sysinfo.freqOPB <= 66666667) - mode_reg |= EMAC_M1_OBCI_66; + mode_reg |= EMAC_MR1_OBCI_66; else if (sysinfo.freqOPB <= 83333333) - mode_reg |= EMAC_M1_OBCI_83; + mode_reg |= EMAC_MR1_OBCI_83; else if (sysinfo.freqOPB <= 100000000) - mode_reg |= EMAC_M1_OBCI_100; + mode_reg |= EMAC_MR1_OBCI_100; else - mode_reg |= EMAC_M1_OBCI_GT100; + mode_reg |= EMAC_MR1_OBCI_GT100; - out_be32 ((void*)(EMAC_M1 + hw_addr), mode_reg); + out_be32 ((void*)(EMAC0_MR1 + hw_addr), mode_reg); #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ @@ -210,40 +210,40 @@ static void ether_post_init (int devnum, int hw_addr) /* set internal loopback mode */ #ifdef CONFIG_SYS_POST_ETHER_EXT_LOOPBACK - out_be32 ((void*)(EMAC_M1 + hw_addr), EMAC_M1_FDE | 0 | - EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K | - EMAC_M1_MF_100MBPS | EMAC_M1_IST | - in_be32 ((void*)(EMAC_M1 + hw_addr))); + out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE | 0 | + EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K | + EMAC_MR1_MF_100MBPS | EMAC_MR1_IST | + in_be32 ((void*)(EMAC0_MR1 + hw_addr))); #else - out_be32 ((void*)(EMAC_M1 + hw_addr), EMAC_M1_FDE | EMAC_M1_ILE | - EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K | - EMAC_M1_MF_100MBPS | EMAC_M1_IST | - in_be32 ((void*)(EMAC_M1 + hw_addr))); + out_be32 ((void*)(EMAC0_MR1 + hw_addr), EMAC_MR1_FDE | EMAC_MR1_ILE | + EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K | + EMAC_MR1_MF_100MBPS | EMAC_MR1_IST | + in_be32 ((void*)(EMAC0_MR1 + hw_addr))); #endif /* set transmit enable & receive enable */ - out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_TXE | EMAC_M0_RXE); + out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_TXE | EMAC_MR0_RXE); /* enable broadcast address */ - out_be32 ((void*)(EMAC_RXM + hw_addr), EMAC_RMR_BAE); + out_be32 ((void*)(EMAC0_RXM + hw_addr), EMAC_RMR_BAE); /* set transmit request threshold register */ - out_be32 ((void*)(EMAC_TRTR + hw_addr), 0x18000000); /* 256 byte threshold */ + out_be32 ((void*)(EMAC0_TRTR + hw_addr), 0x18000000); /* 256 byte threshold */ /* set receive low/high water mark register */ #if defined(CONFIG_440) /* 440s has a 64 byte burst length */ - out_be32 ((void*)(EMAC_RX_HI_LO_WMARK + hw_addr), 0x80009000); + out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x80009000); #else /* 405s have a 16 byte burst length */ - out_be32 ((void*)(EMAC_RX_HI_LO_WMARK + hw_addr), 0x0f002000); + out_be32 ((void*)(EMAC0_RX_HI_LO_WMARK + hw_addr), 0x0f002000); #endif /* defined(CONFIG_440) */ - out_be32 ((void*)(EMAC_TXM1 + hw_addr), 0xf8640000); + out_be32 ((void*)(EMAC0_TMR1 + hw_addr), 0xf8640000); /* Set fifo limit entry in tx mode 0 */ - out_be32 ((void*)(EMAC_TXM0 + hw_addr), 0x00000003); + out_be32 ((void*)(EMAC0_TMR0 + hw_addr), 0x00000003); /* Frame gap set */ - out_be32 ((void*)(EMAC_I_FRAME_GAP_REG + hw_addr), 0x00000008); + out_be32 ((void*)(EMAC0_I_FRAME_GAP_REG + hw_addr), 0x00000008); sync (); } @@ -270,7 +270,7 @@ static void ether_post_halt (int devnum, int hw_addr) udelay (1000); } /* emac reset */ - out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_SRST); + out_be32 ((void*)(EMAC0_MR0 + hw_addr), EMAC_MR0_SRST); #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /* remove clocks for EMAC internal loopback */ @@ -300,7 +300,7 @@ static void ether_post_send (int devnum, int hw_addr, void *packet, int length) flush_dcache_range((u32)tx.data_ptr, (u32)tx.data_ptr + length); sync (); - out_be32 ((void*)(EMAC_TXM0 + hw_addr), in_be32 ((void*)(EMAC_TXM0 + hw_addr)) | EMAC_TXM0_GNP0); + out_be32 ((void*)(EMAC0_TMR0 + hw_addr), in_be32 ((void*)(EMAC0_TMR0 + hw_addr)) | EMAC_TMR0_GNP0); sync (); } diff --git a/post/post.c b/post/post.c index bc8114e511..b74e762316 100644 --- a/post/post.c +++ b/post/post.c @@ -393,6 +393,7 @@ int post_log (char *format, ...) return 0; } +#ifndef CONFIG_RELOC_FIXUP_WORKS void post_reloc (void) { unsigned int i; @@ -437,6 +438,7 @@ void post_reloc (void) } } } +#endif /*