From: Lothar Waßmann Date: Thu, 24 Aug 2017 07:26:22 +0000 (+0200) Subject: Kirkwood: tk71: fix SDRAM timing parameters X-Git-Tag: KARO-TK71-2017-08-24 X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=commitdiff_plain;h=240eaada88b75a084776388fc35b612c13d7c65f;hp=3a085e3e702672bc2867ae8e7bc552dc7af287fd Kirkwood: tk71: fix SDRAM timing parameters The current SDRAM timing setup is broken. Adjust the timing parameters to match the need of the SDRAM in use. --- diff --git a/board/karo/tk71/kwbimage.cfg b/board/karo/tk71/kwbimage.cfg index 0166826e72..46034fff21 100644 --- a/board/karo/tk71/kwbimage.cfg +++ b/board/karo/tk71/kwbimage.cfg @@ -48,7 +48,7 @@ DATA 0xFFD01400 0x43000c30 # DDR Configuration register # bit29-26: zero # bit31-30: 01 -DATA 0xFFD01404 0x36543000 # DDR Controller Control Low +DATA 0xFFD01404 0x37543000 # DDR Controller Control Low # bit 4: 0=addr/cmd in smame cycle # bit 5: 0=clk is driven during self refresh, we don't care for APX # bit 6: 0=use recommended falling edge of clk for addr/cmd @@ -59,7 +59,7 @@ DATA 0xFFD01404 0x36543000 # DDR Controller Control Low # bit30-28: 3 required # bit31: 0=no additional STARTBURST delay -DATA 0xFFD01408 0x1101355b # DDR Timing (Low) (active cycles value +1) +DATA 0xFFD01408 0x33136552 # DDR Timing (Low) (active cycles value +1) # bit3-0: TRAS lsbs # bit7-4: TRCD # bit11- 8: TRP @@ -70,7 +70,7 @@ DATA 0xFFD01408 0x1101355b # DDR Timing (Low) (active cycles value +1) # bit27-24: TRRD # bit31-28: TRTP -DATA 0xFFD0140C 0x00000034 # DDR Timing (High) +DATA 0xFFD0140C 0x0000004e # DDR Timing (High) # bit6-0: TRFC # bit8-7: TR2R # bit10-9: TR2W