From: Simon Glass <sjg@chromium.org>
Date: Mon, 3 Dec 2012 13:56:51 +0000 (+0000)
Subject: x86: fdt: Create basic .dtsi file for coreboot
X-Git-Tag: v2013.01-rc2~73^2~13
X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=commitdiff_plain;h=2712f08898de84a9688b4a7b7752ba27e71d63ef

x86: fdt: Create basic .dtsi file for coreboot

This contains just the minimum information for a coreboot-based board.

Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
---

diff --git a/arch/x86/dts/coreboot.dtsi b/arch/x86/dts/coreboot.dtsi
new file mode 100644
index 0000000000..4862a59704
--- /dev/null
+++ b/arch/x86/dts/coreboot.dtsi
@@ -0,0 +1,16 @@
+/include/ "skeleton.dtsi"
+
+/ {
+	aliases {
+		console = "/serial";
+	};
+
+	serial {
+		compatible = "ns16550";
+		reg-shift = <1>;
+		io-mapped = <1>;
+		multiplier = <1>;
+		baudrate = <115200>;
+		status = "disabled";
+	};
+};
diff --git a/arch/x86/dts/skeleton.dtsi b/arch/x86/dts/skeleton.dtsi
new file mode 100644
index 0000000000..b41d241de2
--- /dev/null
+++ b/arch/x86/dts/skeleton.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Skeleton device tree; the bare minimum needed to boot; just include and
+ * add a compatible value.  The bootloader will typically populate the memory
+ * node.
+ */
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	chosen { };
+	aliases { };
+	memory { device_type = "memory"; reg = <0 0>; };
+};
diff --git a/board/chromebook-x86/dts/x86-alex.dts b/board/chromebook-x86/dts/alex.dts
similarity index 53%
rename from board/chromebook-x86/dts/x86-alex.dts
rename to board/chromebook-x86/dts/alex.dts
index bd90d185f1..cb6a9e41ee 100644
--- a/board/chromebook-x86/dts/x86-alex.dts
+++ b/board/chromebook-x86/dts/alex.dts
@@ -1,5 +1,7 @@
 /dts-v1/;
 
+/include/ "coreboot.dtsi"
+
 / {
         #address-cells = <1>;
         #size-cells = <1>;
@@ -10,19 +12,11 @@
 	       silent_console = <0>;
 	};
 
-	aliases {
-		console = "/serial@e0401000";
-	};
+        gpio: gpio {};
 
-	serial@e0401000 {
-		compatible = "ns16550";
-		reg = <0xe0401000 0x40>;
-		id = <1>;
-		reg-shift = <1>;
-		baudrate = <115200>;
-		clock-frequency = <4000000>;
-		multiplier = <1>;
-		status = "ok";
+	serial {
+		reg = <0x3f8 8>;
+		clock-frequency = <115200>;
 	};
 
         chosen { };
diff --git a/board/chromebook-x86/dts/link.dts b/board/chromebook-x86/dts/link.dts
new file mode 100644
index 0000000000..af60f59de7
--- /dev/null
+++ b/board/chromebook-x86/dts/link.dts
@@ -0,0 +1,24 @@
+/dts-v1/;
+
+/include/ "coreboot.dtsi"
+
+/ {
+        #address-cells = <1>;
+        #size-cells = <1>;
+	model = "Google Link";
+	compatible = "google,link", "intel,celeron-ivybridge";
+
+	config {
+	       silent_console = <0>;
+	};
+
+        gpio: gpio {};
+
+	serial {
+		reg = <0x3f8 8>;
+		clock-frequency = <115200>;
+	};
+
+        chosen { };
+        memory { device_type = "memory"; reg = <0 0>; };
+};