From: Ye.Li <Ye.Li@freescale.com>
Date: Wed, 20 Aug 2014 09:18:24 +0000 (+0800)
Subject: iMX6: Disable the L2 before chaning the PL310 latency
X-Git-Tag: KARO-TXA5-2015-06-26~655^2^2~14
X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=commitdiff_plain;h=4aa7ac30a7173934f32db466bd4592cd292e7cc9

iMX6: Disable the L2 before chaning the PL310 latency

The Latency parameters of PL310 Tag RAM latency control register and
Data RAM Latency control register are set in L2 cache enable. And
setting these registers must have PL310 NOT enabled.

But when using Plugin mode boot, the PL310 is enabled by bootrom.
The patch disables the PL310 before applying this setting.

Signed-off-by: Ye.Li <Ye.Li@freescale.com>
---

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index ac84a1fbfb..be4bf24020 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -430,6 +430,9 @@ void v7_outer_cache_enable(void)
 	}
 #endif
 
+	/* Must disable the L2 before changing the latency parameters */
+	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
 	writel(0x132, &pl310->pl310_tag_latency_ctrl);
 	writel(0x132, &pl310->pl310_data_latency_ctrl);