From: Lothar Waßmann <LW@KARO-electronics.de>
Date: Fri, 21 Aug 2015 14:22:42 +0000 (+0200)
Subject: karo: tx6: configure ENET_OUT pad in DCD for earlier generation of the PHY refclock
X-Git-Tag: KARO-TX6-2015-09-18~4034^2^2~5
X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=commitdiff_plain;h=5991b7ed19f0a899c6eb97533ca0c8bd9a6fcd81

karo: tx6: configure ENET_OUT pad in DCD for earlier generation of the PHY refclock
---

diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S
index 4753c55d00..027db9aa9e 100644
--- a/board/karo/tx6/lowlevel_init.S
+++ b/board/karo/tx6/lowlevel_init.S
@@ -488,13 +488,16 @@ ivt_end:
 
 #ifdef CONFIG_SOC_MX6Q
 #define IOMUXC_GPR1				0x020e0004
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20	0x020e00a0
 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21	0x020e00a4
 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28	0x020e00c4
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO16		0x020e0248
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17		0x020e024c
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7		0x020e02a8
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6		0x020e02ac
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0		0x020e02c0
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1		0x020e02c4
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2		0x020e02c8
 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE		0x020e02d4
 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE		0x020e02d8
 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B		0x020e02dc
@@ -512,6 +515,7 @@ ivt_end:
 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06	0x020e0314
 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07	0x020e0318
 
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20	0x020e03b4
 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21	0x020e03b8
 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28	0x020e03d8
 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P	0x020e050c
@@ -558,6 +562,9 @@ ivt_end:
 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6		0x020e05bc
 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P	0x020e05c0
 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7		0x020e05c4
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO16		0x020e0618
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO17		0x020e061c
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2		0x020e06b0
 #define IOMUXC_SW_PAD_CTL_GRP_B7DS		0x020e0748
 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS		0x020e074c
 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL	0x020e0750
@@ -593,13 +600,16 @@ ivt_end:
 
 #if defined(CONFIG_SOC_MX6DL) || defined(CONFIG_SOC_MX6S)
 #define IOMUXC_GPR1				0x020e0004
+#define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20	0x020e0154
 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA21	0x020e0158
 #define IOMUXC_SW_MUX_CTL_PAD_EIM_DATA28	0x020e0174
+#define IOMUXC_SW_MUX_CTL_PAD_GPIO16		0x020e0214
 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17		0x020e0218
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7		0x020e0330
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6		0x020e032c
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0		0x020e0314
 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1		0x020e0318
+#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2		0x020e031c
 #define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE		0x020e0270
 #define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE		0x020e026c
 #define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B		0x020e02a8
@@ -617,6 +627,7 @@ ivt_end:
 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06	0x020e029c
 #define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07	0x020e02a0
 
+#define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20	0x020e0524
 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA21	0x020e0528
 #define IOMUXC_SW_PAD_CTL_PAD_EIM_DATA28	0x020e0544
 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P	0x020e04d0
@@ -663,6 +674,9 @@ ivt_end:
 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6		0x020e0488
 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P	0x020e04d8
 #define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7		0x020e048c
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO16		0x020e05e4
+#define IOMUXC_SW_PAD_CTL_PAD_GPIO17		0x020e05e8
+#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2		0x020e0704
 #define IOMUXC_SW_PAD_CTL_GRP_B7DS		0x020e0748
 #define IOMUXC_SW_PAD_CTL_GRP_ADDDS		0x020e074c
 #define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL	0x020e0750
@@ -699,8 +713,17 @@ dcd_hdr:
 	MXC_DCD_ITEM(IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA21, TX6_I2C1_SEL_INP_VAL)
 	MXC_DCD_ITEM(IOMUXC_SW_SEL_INPUT_PAD_EIM_DATA28, TX6_I2C1_SEL_INP_VAL)
 
+	/* ENET_REF_CLK */
+	MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO16, 0x00000012)
+	/* ETN PHY nRST */
+	MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2, 0x00000015)
+	MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2, 0x000030b0)
+	/* ETN PHY Power */
+	MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_EIM_DATA20, 0x00000015)
+	MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_EIM_DATA20, 0x000030b0)
 	/* RESET_OUT GPIO_7_12 */
 	MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005)
+	MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_GPIO17, 0x000030b0)
 
 	MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* default: 0x007236c1 */
 	MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CHSCCDR, 0x00012093) /* default: 0x0002a150 */