From: Lothar Waßmann Date: Fri, 23 Aug 2013 15:27:09 +0000 (+0200) Subject: upgrade to upstream version 2013.07 X-Git-Tag: KARO-TX6-2013-08-23 X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=commitdiff_plain;h=778c3cbd857f4abe54773f399204dd86ffe6516c upgrade to upstream version 2013.07 --- 778c3cbd857f4abe54773f399204dd86ffe6516c diff --cc Makefile index 26326e96df,b82feebefa..261bde92ef --- a/Makefile +++ b/Makefile @@@ -512,13 -508,9 +508,9 @@@ $(obj)u-boot.ais: $(obj)spl/u-boo cat $(obj)spl/u-boot-spl-pad.ais $(obj)u-boot.img > \ $(obj)u-boot.ais - # Specify the target for use in elftosb call - ELFTOSB_TARGET-$(CONFIG_MX28) = imx28 -$(obj)u-boot.sb: $(obj)u-boot $(obj)spl/u-boot-spl.bin elftosb +$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin elftosb - cd $(OBJTREE); \ - $(TOPDIR)/$(SUBDIR_TOOLS)/elftosb/bld/linux/elftosb -zdf $(ELFTOSB_TARGET-y) -c $(TOPDIR)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd \ - -o $(obj)u-boot.sb + $(MAKE) -C $(SRCTREE)/$(CPUDIR)/$(SOC)/ $(OBJTREE)/u-boot.sb # On x600 (SPEAr600) U-Boot is appended to U-Boot SPL. # Both images are created using mkimage (crc etc), so that the ROM diff --cc arch/arm/cpu/arm926ejs/mxs/clock.c index 85f219d4d4,e9d8800f8c..8b5ad018ea --- a/arch/arm/cpu/arm926ejs/mxs/clock.c +++ b/arch/arm/cpu/arm926ejs/mxs/clock.c @@@ -41,32 -28,17 +28,38 @@@ #define PLL_FREQ_MHZ (PLL_FREQ_KHZ / 1000) #define XTAL_FREQ_MHZ (XTAL_FREQ_KHZ / 1000) + #if defined(CONFIG_MX23) + #define MXC_SSPCLK_MAX MXC_SSPCLK0 + #elif defined(CONFIG_MX28) + #define MXC_SSPCLK_MAX MXC_SSPCLK3 + #endif + -static uint32_t mxs_get_pclk(void) +static struct mxs_clkctrl_regs *clkctrl_regs = (void *)MXS_CLKCTRL_BASE; + +static uint32_t get_frac_clk(uint32_t refclk, uint32_t div, uint32_t _mask) { - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; + uint32_t mask = (_mask + 1) >> 1; + uint32_t acc = div; + int period = 0; + int mult = 0; + + if (div & mask) + return 0; + + do { + acc += div; + if (acc & mask) { + acc &= ~mask; + mult++; + } + period++; + } while (acc != div); + return refclk * mult / period; +} + - static uint32_t mx28_get_pclk(void) ++static uint32_t mxs_get_pclk(void) +{ uint32_t clkctrl, clkseq, div; uint8_t clkfrac, frac; @@@ -105,23 -63,32 +98,23 @@@ return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; } - static uint32_t mx28_get_hclk(void) + static uint32_t mxs_get_hclk(void) { - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - uint32_t div; uint32_t clkctrl; - uint32_t refclk = mx28_get_pclk(); ++ uint32_t refclk = mxs_get_pclk(); clkctrl = readl(&clkctrl_regs->hw_clkctrl_hbus); + div = clkctrl & CLKCTRL_HBUS_DIV_MASK; - /* No support of fractional divider calculation */ if (clkctrl & CLKCTRL_HBUS_DIV_FRAC_EN) - return 0; + return get_frac_clk(refclk, div, CLKCTRL_HBUS_DIV_MASK); - div = clkctrl & CLKCTRL_HBUS_DIV_MASK; - return mxs_get_pclk() / div; + return refclk / div; } - static uint32_t mx28_get_emiclk(void) + static uint32_t mxs_get_emiclk(void) { - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - uint32_t clkctrl, clkseq, div; uint8_t clkfrac, frac; @@@ -142,8 -109,17 +135,15 @@@ return (PLL_FREQ_MHZ * PLL_FREQ_COEF / frac) / div; } - static uint32_t mx28_get_gpmiclk(void) + static uint32_t mxs_get_gpmiclk(void) { - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; + #if defined(CONFIG_MX23) + uint8_t *reg = + &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]; + #elif defined(CONFIG_MX28) + uint8_t *reg = + &clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_GPMI]; + #endif uint32_t clkctrl, clkseq, div; uint8_t clkfrac, frac; @@@ -166,8 -142,10 +166,8 @@@ /* * Set IO clock frequency, in kHz */ - void mx28_set_ioclk(enum mxs_ioclock io, uint32_t freq) + void mxs_set_ioclk(enum mxs_ioclock io, uint32_t freq) { - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; uint32_t div; int io_reg; @@@ -197,8 -175,10 +197,8 @@@ /* * Get IO clock, returns IO clock in kHz */ - static uint32_t mx28_get_ioclk(enum mxs_ioclock io) + static uint32_t mxs_get_ioclk(enum mxs_ioclock io) { - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; uint8_t ret; int io_reg; @@@ -218,11 -196,13 +218,11 @@@ /* * Configure SSP clock frequency, in kHz */ - void mx28_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal) + void mxs_set_sspclk(enum mxs_sspclock ssp, uint32_t freq, int xtal) { - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; uint32_t clk, clkreg; - if (ssp > MXC_SSPCLK3) + if (ssp > MXC_SSPCLK_MAX) return; clkreg = (uint32_t)(&clkctrl_regs->hw_clkctrl_ssp0) + @@@ -260,12 -240,14 +260,12 @@@ /* * Return SSP frequency, in kHz */ - static uint32_t mx28_get_sspclk(enum mxs_sspclock ssp) + static uint32_t mxs_get_sspclk(enum mxs_sspclock ssp) { - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; - uint32_t clkreg; + uint32_t *clkreg; uint32_t clk, tmp; - if (ssp > MXC_SSPCLK3) + if (ssp > MXC_SSPCLK_MAX) return 0; tmp = readl(&clkctrl_regs->hw_clkctrl_clkseq); @@@ -324,53 -309,127 +326,144 @@@ void mxs_set_ssp_busclock(unsigned int bus, tgtclk, freq); } - static uint32_t mx28_get_xbus_clk(void) + void mxs_set_lcdclk(uint32_t freq) + { - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; + uint32_t fp, x, k_rest, k_best, x_best, tk; + int32_t k_best_l = 999, k_best_t = 0, x_best_l = 0xff, x_best_t = 0xff; + + if (freq == 0) + return; + + #if defined(CONFIG_MX23) + writel(CLKCTRL_CLKSEQ_BYPASS_PIX, &clkctrl_regs->hw_clkctrl_clkseq_clr); + #elif defined(CONFIG_MX28) + writel(CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF, &clkctrl_regs->hw_clkctrl_clkseq_clr); + #endif + + /* + * / 18 \ 1 1 + * freq kHz = | 480000000 Hz * -- | * --- * ------ + * \ x / k 1000 + * + * 480000000 Hz 18 + * ------------ * -- + * freq kHz x + * k = ------------------- + * 1000 + */ + + fp = ((PLL_FREQ_KHZ * 1000) / freq) * 18; + + for (x = 18; x <= 35; x++) { + tk = fp / x; + if ((tk / 1000 == 0) || (tk / 1000 > 255)) + continue; + + k_rest = tk % 1000; + + if (k_rest < (k_best_l % 1000)) { + k_best_l = tk; + x_best_l = x; + } + + if (k_rest > (k_best_t % 1000)) { + k_best_t = tk; + x_best_t = x; + } + } + + if (1000 - (k_best_t % 1000) > (k_best_l % 1000)) { + k_best = k_best_l; + x_best = x_best_l; + } else { + k_best = k_best_t; + x_best = x_best_t; + } + + k_best /= 1000; + + #if defined(CONFIG_MX23) + writeb(CLKCTRL_FRAC_CLKGATE, + &clkctrl_regs->hw_clkctrl_frac0_set[CLKCTRL_FRAC0_PIX]); + writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK), + &clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_PIX]); + writeb(CLKCTRL_FRAC_CLKGATE, + &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_PIX]); + + writel(CLKCTRL_PIX_CLKGATE, + &clkctrl_regs->hw_clkctrl_pix_set); + clrsetbits_le32(&clkctrl_regs->hw_clkctrl_pix, + CLKCTRL_PIX_DIV_MASK | CLKCTRL_PIX_CLKGATE, + k_best << CLKCTRL_PIX_DIV_OFFSET); + + while (readl(&clkctrl_regs->hw_clkctrl_pix) & CLKCTRL_PIX_BUSY) + ; + #elif defined(CONFIG_MX28) + writeb(CLKCTRL_FRAC_CLKGATE, + &clkctrl_regs->hw_clkctrl_frac1_set[CLKCTRL_FRAC1_PIX]); + writeb(CLKCTRL_FRAC_CLKGATE | (x_best & CLKCTRL_FRAC_FRAC_MASK), + &clkctrl_regs->hw_clkctrl_frac1[CLKCTRL_FRAC1_PIX]); + writeb(CLKCTRL_FRAC_CLKGATE, + &clkctrl_regs->hw_clkctrl_frac1_clr[CLKCTRL_FRAC1_PIX]); + + writel(CLKCTRL_DIS_LCDIF_CLKGATE, + &clkctrl_regs->hw_clkctrl_lcdif_set); + clrsetbits_le32(&clkctrl_regs->hw_clkctrl_lcdif, + CLKCTRL_DIS_LCDIF_DIV_MASK | CLKCTRL_DIS_LCDIF_CLKGATE, + k_best << CLKCTRL_DIS_LCDIF_DIV_OFFSET); + + while (readl(&clkctrl_regs->hw_clkctrl_lcdif) & CLKCTRL_DIS_LCDIF_BUSY) + ; + #endif + } + ++static uint32_t mxs_get_xbus_clk(void) +{ - struct mxs_clkctrl_regs *clkctrl_regs = - (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; + uint32_t div; + uint32_t clkctrl; - uint32_t refclk = mx28_get_pclk(); ++ uint32_t refclk = mxs_get_pclk(); + + clkctrl = readl(&clkctrl_regs->hw_clkctrl_xbus); + div = clkctrl & CLKCTRL_XBUS_DIV_MASK; + + if (clkctrl & CLKCTRL_XBUS_DIV_FRAC_EN) + return get_frac_clk(refclk, div, CLKCTRL_XBUS_DIV_MASK); + + return refclk / div; +} + uint32_t mxc_get_clock(enum mxc_clock clk) { switch (clk) { case MXC_ARM_CLK: - return mx28_get_pclk() * 1000000; + return mxs_get_pclk() * 1000000; case MXC_GPMI_CLK: - return mx28_get_gpmiclk() * 1000000; + return mxs_get_gpmiclk() * 1000000; case MXC_AHB_CLK: case MXC_IPG_CLK: - return mx28_get_hclk() * 1000000; + return mxs_get_hclk() * 1000000; case MXC_EMI_CLK: - return mx28_get_emiclk(); + return mxs_get_emiclk(); case MXC_IO0_CLK: - return mx28_get_ioclk(MXC_IOCLK0); + return mxs_get_ioclk(MXC_IOCLK0); case MXC_IO1_CLK: - return mx28_get_ioclk(MXC_IOCLK1); + return mxs_get_ioclk(MXC_IOCLK1); + case MXC_XTAL_CLK: + return XTAL_FREQ_KHZ * 1000; case MXC_SSP0_CLK: - return mx28_get_sspclk(MXC_SSPCLK0); + return mxs_get_sspclk(MXC_SSPCLK0); + #ifdef CONFIG_MX28 case MXC_SSP1_CLK: - return mx28_get_sspclk(MXC_SSPCLK1); + return mxs_get_sspclk(MXC_SSPCLK1); case MXC_SSP2_CLK: - return mx28_get_sspclk(MXC_SSPCLK2); + return mxs_get_sspclk(MXC_SSPCLK2); case MXC_SSP3_CLK: - return mx28_get_sspclk(MXC_SSPCLK3); - case MXC_XTAL_CLK: - return XTAL_FREQ_KHZ * 1000; + return mxs_get_sspclk(MXC_SSPCLK3); + #endif + case MXC_XBUS_CLK: - return mx28_get_xbus_clk() * 1000000; ++ return mxs_get_xbus_clk() * 1000000; + default: + printf("Invalid clock selector %u\n", clk); } return 0; diff --cc arch/arm/cpu/arm926ejs/mxs/timer.c index f2dfc8a6dd,20693e2a94..12789327cc --- a/arch/arm/cpu/arm926ejs/mxs/timer.c +++ b/arch/arm/cpu/arm926ejs/mxs/timer.c @@@ -82,6 -74,13 +74,13 @@@ int timer_init(void TIMROT_TIMCTRLn_SELECT_1KHZ_XTAL, &timrot_regs->hw_timrot_timctrl0); - /* Set fixed_count to maximal value */ ++ /* Set fixed_count to maximum value */ + #if defined(CONFIG_MX23) + writel(TIMER_LOAD_VAL - 1, &timrot_regs->hw_timrot_timcount0); + #elif defined(CONFIG_MX28) + writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0); + #endif + #ifndef DEBUG_TIMER_WRAP /* Set fixed_count to maximum value */ writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0); @@@ -90,8 -89,8 +89,7 @@@ writel(20 * MXS_INCREMENTER_HZ, &timrot_regs->hw_timrot_fixed_count0); gd->arch.lastinc = TIMER_LOAD_VAL - 20 * MXS_INCREMENTER_HZ; --#endif --#ifdef DEBUG_TIMER_WRAP ++ /* Make the usec counter roll over 30 seconds after startup */ writel(-30000000, MXS_HW_DIGCTL_MICROSECONDS); #endif diff --cc arch/arm/cpu/armv7/omap-common/boot-common.c index d5fb40e22e,6b9ce369f5..ad383872c5 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@@ -23,26 -15,51 +15,51 @@@ #include #include - /* - * This is used to verify if the configuration header - * was executed by rom code prior to control of transfer - * to the bootloader. SPL is responsible for saving and - * passing the boot_params pointer to the u-boot. - */ - struct omap_boot_parameters boot_params __attribute__ ((section(".data"))); + DECLARE_GLOBAL_DATA_PTR; - #ifdef CONFIG_SPL_BUILD - /* - * We use static variables because global data is not ready yet. - * Initialized data is available in SPL right from the beginning. - * We would not typically need to save these parameters in regular - * U-Boot. This is needed only in SPL at the moment. - */ - u32 omap_bootmode __attribute__ ((section(".data"))) = MMCSD_MODE_UNDEFINED; + void save_omap_boot_params(void) + { + u32 rom_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS); + u8 boot_device; + u32 dev_desc, dev_data; + + if ((rom_params < NON_SECURE_SRAM_START) || + (rom_params > NON_SECURE_SRAM_END)) + return; + + /* + * rom_params can be type casted to omap_boot_parameters and + * used. But it not correct to assume that romcode structure + * encoding would be same as u-boot. So use the defined offsets. + */ + gd->arch.omap_boot_params.omap_bootdevice = boot_device = + *((u8 *)(rom_params + BOOT_DEVICE_OFFSET)); + + gd->arch.omap_boot_params.ch_flags = + *((u8 *)(rom_params + CH_FLAGS_OFFSET)); + if ((boot_device >= MMC_BOOT_DEVICES_START) && + (boot_device <= MMC_BOOT_DEVICES_END)) { + #if !defined(CONFIG_AM33XX) && !defined(CONFIG_TI81XX) + if ((omap_hw_init_context() == + OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)) { + gd->arch.omap_boot_params.omap_bootmode = + *((u8 *)(rom_params + BOOT_MODE_OFFSET)); + } else + #endif + { + dev_desc = *((u32 *)(rom_params + DEV_DESC_PTR_OFFSET)); + dev_data = *((u32 *)(dev_desc + DEV_DATA_PTR_OFFSET)); + gd->arch.omap_boot_params.omap_bootmode = + *((u32 *)(dev_data + BOOT_MODE_OFFSET)); + } + } + } + + #ifdef CONFIG_SPL_BUILD u32 spl_boot_device(void) { - return boot_params.omap_bootdevice; - return (u32) (gd->arch.omap_boot_params.omap_bootdevice); ++ return gd->arch.omap_boot_params.omap_bootdevice; } u32 spl_boot_mode(void) diff --cc arch/arm/imx-common/timer.c index bf18102641,a4b0137cf3..92712a6de5 --- a/arch/arm/imx-common/timer.c +++ b/arch/arm/imx-common/timer.c @@@ -45,67 -27,25 +27,33 @@@ static struct mxc_gpt *cur_gpt = (struc /* General purpose timers bitfields */ #define GPTCR_SWR (1 << 15) /* Software reset */ #define GPTCR_FRR (1 << 9) /* Freerun / restart */ - #define GPTCR_CLKSOURCE_IPG (1 << 6) /* Clock source */ - #define GPTCR_CLKSOURCE_CKIH (2 << 6) - #define GPTCR_CLKSOURCE_32kHz (4 << 6) - #if defined(CONFIG_MX6Q) - #define GPTCR_CLKSOURCE_OSCDIV8 (5 << 6) - #define GPTCR_CLKSOURCE_OSC (7 << 6) - #elif defined(CONFIG_MX6DL) - #define GPTCR_M24EN (1 << 10) - #define GPTCR_CLKSOURCE_OSC ((5 << 6) | GPTCR_M24EN) - #else - #define GPTCR_CLKSOURCE_OSC (5 << 6) - #endif - #define GPTCR_CLKSOURCE_MASK (7 << 6) + #define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */ #define GPTCR_TEN 1 /* Timer enable */ - #if 1 - #define GPT_CLKSOURCE GPTCR_CLKSOURCE_OSC - #define GPT_REFCLK 24000000 - #define GPT_PRESCALER 24 - #else - #define GPT_CLKSOURCE GPTCR_CLKSOURCE_32kHz - #define GPT_REFCLK 32768 - #define GPT_PRESCALER 1 - #endif - #define GPT_CLK (GPT_REFCLK / GPT_PRESCALER) - - #ifdef DEBUG_TIMER_WRAP - /* - * Let the timer wrap 30 seconds after start to catch misbehaving - * timer related code early - */ - #define TIMER_START (-time_to_tick(30 * CONFIG_SYS_HZ)) - #else - #define TIMER_START 0UL - #endif - DECLARE_GLOBAL_DATA_PTR; - static inline unsigned long tick_to_time(unsigned long tick) + static inline unsigned long long tick_to_time(unsigned long long tick) { - unsigned long long t = (unsigned long long)tick * CONFIG_SYS_HZ; - do_div(t, GPT_CLK); - return t; + tick *= CONFIG_SYS_HZ; + do_div(tick, MXC_CLK32); - + return tick; } +static inline unsigned long time_to_tick(unsigned long time) +{ + unsigned long long ticks = (unsigned long long)time; + - ticks *= GPT_CLK; ++ ticks *= MXC_CLK32; + do_div(ticks, CONFIG_SYS_HZ); + return ticks; +} + - static inline unsigned long us_to_tick(unsigned long usec) + static inline unsigned long long us_to_tick(unsigned long long usec) { - unsigned long long ticks = (unsigned long long)usec; + usec = usec * MXC_CLK32 + 999999; + do_div(usec, 1000000); - ticks *= GPT_CLK; - do_div(ticks, 1000 * CONFIG_SYS_HZ); - return ticks; + return usec; } int timer_init(void) @@@ -164,11 -96,9 +111,9 @@@ ulong get_timer_masked(void ulong get_timer(ulong base) { - return get_timer_masked() - base; + return tick_to_time(get_ticks() - time_to_tick(base)); } - #include - /* delay x useconds AND preserve advance timstamp value */ void __udelay(unsigned long usec) { diff --cc arch/arm/include/asm/arch-mxs/clock.h index 0e145dba75,fc9d75b509..d3bc95b824 --- a/arch/arm/include/asm/arch-mxs/clock.h +++ b/arch/arm/include/asm/arch-mxs/clock.h @@@ -35,8 -24,7 +24,8 @@@ enum mxc_clock MXC_SSP1_CLK, MXC_SSP2_CLK, MXC_SSP3_CLK, - MXC_XTAL_CLK, + #endif + MXC_XBUS_CLK, }; enum mxs_ioclock { diff --cc arch/arm/include/asm/arch-mxs/regs-ssp.h index 51a7037752,be74e4b1cf..464e9e0914 --- a/arch/arm/include/asm/arch-mxs/regs-ssp.h +++ b/arch/arm/include/asm/arch-mxs/regs-ssp.h @@@ -25,9 -12,31 +12,29 @@@ #ifndef __MX28_REGS_SSP_H__ #define __MX28_REGS_SSP_H__ - #include + #include #ifndef __ASSEMBLY__ + #if defined(CONFIG_MX23) + struct mxs_ssp_regs { - mxs_reg_32(hw_ssp_ctrl0) - mxs_reg_32(hw_ssp_cmd0) - mxs_reg_32(hw_ssp_cmd1) - mxs_reg_32(hw_ssp_compref) - mxs_reg_32(hw_ssp_compmask) - mxs_reg_32(hw_ssp_timing) - mxs_reg_32(hw_ssp_ctrl1) - mxs_reg_32(hw_ssp_data) - mxs_reg_32(hw_ssp_sdresp0) - mxs_reg_32(hw_ssp_sdresp1) - mxs_reg_32(hw_ssp_sdresp2) - mxs_reg_32(hw_ssp_sdresp3) - mxs_reg_32(hw_ssp_status) - - uint32_t reserved1[12]; - - mxs_reg_32(hw_ssp_debug) - mxs_reg_32(hw_ssp_version) ++ mxs_reg_32(hw_ssp_ctrl0); ++ mxs_reg_32(hw_ssp_cmd0); ++ mxs_reg_32(hw_ssp_cmd1); ++ mxs_reg_32(hw_ssp_compref); ++ mxs_reg_32(hw_ssp_compmask); ++ mxs_reg_32(hw_ssp_timing); ++ mxs_reg_32(hw_ssp_ctrl1); ++ mxs_reg_32(hw_ssp_data); ++ mxs_reg_32(hw_ssp_sdresp0); ++ mxs_reg_32(hw_ssp_sdresp1); ++ mxs_reg_32(hw_ssp_sdresp2); ++ mxs_reg_32(hw_ssp_sdresp3); ++ mxs_reg_32(hw_ssp_status); ++ reg_32(reserved[3]); ++ mxs_reg_32(hw_ssp_debug); ++ mxs_reg_32(hw_ssp_version); + }; + #elif defined(CONFIG_MX28) struct mxs_ssp_regs { mxs_reg_32(hw_ssp_ctrl0); mxs_reg_32(hw_ssp_cmd0); diff --cc board/karo/tx53/lowlevel_init.S index 5dc4a964d1,85b204df6a..ba8d961aac --- a/board/karo/tx53/lowlevel_init.S +++ b/board/karo/tx53/lowlevel_init.S @@@ -15,13 -15,7 +15,6 @@@ #define SDRAM_SIZE PHYS_SDRAM_1_SIZE #endif - #define REG_ESDCTL0 0x00 - #define REG_ESDCFG0 0x04 - #define REG_ESDCTL1 0x08 - #define REG_ESDCFG1 0x0c - #define REG_ESDMISC 0x10 - #define REG_ESDSCR 0x14 - #define REG_ESDGPR 0x34 -#define REG_CCOSR 0x60 #define REG_CCGR0 0x68 #define REG_CCGR1 0x6c diff --cc common/lcd.c index 77052e696d,8ba13160c4..0a8835e83c --- a/common/lcd.c +++ b/common/lcd.c @@@ -1050,8 -1074,7 +1074,8 @@@ int lcd_display_bitmap(ulong bmp_image fb[2] = *bmap++; /* R */ fb += 4; } + bmap += (padded_width - width) * 4; - fb -= width * 4 + lcd_line_length; + fb -= lcd_line_length + width * (bpix / 8); } break; }; diff --cc drivers/mmc/omap_hsmmc.c index a00e507449,c6dfd3931b..67d6b68625 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@@ -177,7 -215,7 +215,8 @@@ void mmc_init_stream(struct hsmmc *mmc_ static int mmc_init_setup(struct mmc *mmc) { - struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv; - struct hsmmc *mmc_base; ++ struct omap_hsmmc_data *priv_data = mmc->priv; ++ struct hsmmc *mmc_base = priv_data->base_addr; unsigned int reg_val; unsigned int dsor; ulong start; @@@ -262,7 -301,7 +301,8 @@@ static void mmc_reset_controller_fsm(st static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { - struct hsmmc *mmc_base = mmc->priv; - struct hsmmc *mmc_base; ++ struct omap_hsmmc_data *priv_data = mmc->priv; ++ struct hsmmc *mmc_base = priv_data->base_addr; unsigned int flags, mmc_stat; ulong start; @@@ -488,7 -528,7 +528,8 @@@ static int mmc_write_data(struct hsmmc static void mmc_set_ios(struct mmc *mmc) { - struct hsmmc *mmc_base = (struct hsmmc *)mmc->priv; - struct hsmmc *mmc_base; ++ struct omap_hsmmc_data *priv_data = mmc->priv; ++ struct hsmmc *mmc_base = priv_data->base_addr; unsigned int dsor = 0; ulong start; diff --cc drivers/mtd/nand/mxc_nand.c index 0e89828ee6,57f4e79640..f4528f20bd --- a/drivers/mtd/nand/mxc_nand.c +++ b/drivers/mtd/nand/mxc_nand.c @@@ -138,10 -130,10 +130,6 @@@ static int is_16bit_nand(void #define NFC_VERSION "unknown" #endif - #ifndef CONFIG_MXC_NAND_IP_BASE - #define CONFIG_MXC_NAND_IP_BASE 0 -#ifndef CONFIG_MXC_NAND_IP_REGS_BASE -#define CONFIG_MXC_NAND_IP_REGS_BASE 0 --#endif -- /* Addresses for NFC registers */ #define NFC_V1_V2_BUF_SIZE (host->regs + 0x00) #define NFC_V1_V2_BUF_ADDR (host->regs + 0x04) diff --cc drivers/video/mxc_ipuv3_fb.c index cad5db9511,d7232ad1d6..6a147d5186 --- a/drivers/video/mxc_ipuv3_fb.c +++ b/drivers/video/mxc_ipuv3_fb.c @@@ -8,26 -8,9 +8,10 @@@ * * (C) Copyright 2004-2011 Freescale Semiconductor, Inc. * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ +/* #define DEBUG */ #include #include #include diff --cc include/configs/tx48.h index 8ce9efcd3c,0ee481440c..64f42e023b --- a/include/configs/tx48.h +++ b/include/configs/tx48.h @@@ -6,18 -6,12 +6,12 @@@ * based on: am335x_evm * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. + * SPDX-License-Identifier: GPL-2.0 * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ --#ifndef __CONFIGS_TX48_H --#define __CONFIGS_TX48_H ++#ifndef __CONFIG_H ++#define __CONFIG_H #include @@@ -351,4 -347,4 +347,4 @@@ #define CONFIG_SYS_SPL_MALLOC_START (PHYS_SDRAM_1 + SZ_2M + SZ_32K) #define CONFIG_SYS_SPL_MALLOC_SIZE SZ_1M --#endif /* __CONFIGS_TX48_H */ ++#endif /* __CONFIG_H */ diff --cc include/configs/tx51.h index 8ab6ebb3a1,e0fde5cd18..5005a47ebc --- a/include/configs/tx51.h +++ b/include/configs/tx51.h @@@ -1,28 -1,23 +1,24 @@@ /* * Copyright (C) 2012 * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. + * SPDX-License-Identifier: GPL-2.0 * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ --#ifndef __CONFIGS_TX51_H --#define __CONFIGS_TX51_H + -#define CONFIG_MX51 /* must be set before including imx-regs.h */ ++#ifndef __CONFIG_H ++#define __CONFIG_H ++ ++#define CONFIG_MX51 /* must be set before including imx-regs.h */ #include + #include /* * Ka-Ro TX51 board - SoC configuration */ - #define CONFIG_MX51 /* i.MX51 SoC */ #define CONFIG_SYS_MX5_IOMUX_V3 --#define CONFIG_MXC_GPIO /* GPIO control */ ++#define CONFIG_MXC_GPIO /* GPIO control */ #define CONFIG_SYS_MX5_HCLK 24000000 - #define CONFIG_SYS_MX5_CLK32 32768 #define CONFIG_SYS_DDR_CLKSEL 0 #define CONFIG_SYS_HZ 1000 /* Ticks per second */ #define CONFIG_SHOW_ACTIVITY @@@ -168,7 -163,9 +164,6 @@@ */ #include #define CONFIG_CMD_CACHE -#if 0 --#define CONFIG_CMD_IIM -#endif #define CONFIG_CMD_MMC #define CONFIG_CMD_NAND #define CONFIG_CMD_MTDPARTS @@@ -213,8 -211,8 +209,8 @@@ #define CONFIG_MTD_DEVICE #define CONFIG_ENV_IS_IN_NAND #define CONFIG_NAND_MXC - #define CONFIG_MXC_NAND_REGS_BASE 0xcfff0000 - #define CONFIG_MXC_NAND_IP_BASE 0x83fdb000 -#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI // 0xcfff0000 -#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR // 0x83fdb000 ++#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI ++#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR #define CONFIG_MXC_NAND_HWECC #define CONFIG_CMD_NAND_TRIMFFS #define CONFIG_SYS_MAX_FLASH_SECT 1024 @@@ -289,7 -286,7 +284,7 @@@ GENERATED_GBL_DATA_SIZE) #ifdef CONFIG_CMD_IIM - #define CONFIG_IMX_IIM + #define CONFIG_FSL_IIM #endif --#endif /* __CONFIGS_TX51_H */ ++#endif /* __CONFIG_H */ diff --cc include/configs/tx53.h index b7821a88b5,8044fd09b2..3b2eb240f3 --- a/include/configs/tx53.h +++ b/include/configs/tx53.h @@@ -1,29 -1,25 +1,25 @@@ /* * Copyright (C) 2012 * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. + * SPDX-License-Identifier: GPL-2.0 * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ - #ifndef __CONFIGS_TX53_H - #define __CONFIGS_TX53_H + -#ifndef __CONFIGS_TX53_H -#define __CONFIGS_TX53_H ++#ifndef __CONFIG_H ++#define __CONFIG_H + -#define CONFIG_MX53 /* must be set before including imx-regs.h */ ++#define CONFIG_MX53 /* must be set before including imx-regs.h */ #include + #include /* * Ka-Ro TX53 board - SoC configuration */ --#define CONFIG_TX53 /* TX53 SoM */ - #define CONFIG_MX53 /* i.MX53 SoC */ ++#define CONFIG_TX53 /* TX53 SoM */ #define CONFIG_SYS_MX5_IOMUX_V3 --#define CONFIG_MXC_GPIO /* GPIO control */ ++#define CONFIG_MXC_GPIO /* GPIO control */ #define CONFIG_SYS_MX5_HCLK 24000000 - #define CONFIG_SYS_MX5_CLK32 32768 #define CONFIG_SYS_DDR_CLKSEL 0 #define CONFIG_SYS_HZ 1000 /* Ticks per second */ #define CONFIG_SHOW_ACTIVITY @@@ -151,7 -147,9 +147,6 @@@ */ #include #define CONFIG_CMD_CACHE -#if 0 --#define CONFIG_CMD_IIM -#endif #define CONFIG_CMD_MMC #define CONFIG_CMD_NAND #define CONFIG_CMD_MTDPARTS @@@ -196,8 -195,8 +192,8 @@@ #define CONFIG_MTD_DEVICE #define CONFIG_ENV_IS_IN_NAND #define CONFIG_NAND_MXC - #define CONFIG_MXC_NAND_REGS_BASE 0xf7ff0000 - #define CONFIG_MXC_NAND_IP_BASE 0x63fdb000 -#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI // 0xf7ff0000 -#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR // 0x63fdb000 ++#define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI ++#define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR #define CONFIG_MXC_NAND_HWECC #define CONFIG_CMD_NAND_TRIMFFS #define CONFIG_SYS_MAX_FLASH_SECT 1024 @@@ -232,7 -231,9 +228,6 @@@ #define CONFIG_MMC #define CONFIG_GENERIC_MMC #define CONFIG_FSL_ESDHC -#if 0 --#define CONFIG_SYS_FSL_ESDHC_USE_PIO -#endif #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define CONFIG_SYS_FSL_ESDHC_NUM 2 @@@ -272,7 -273,7 +267,7 @@@ GENERATED_GBL_DATA_SIZE) #ifdef CONFIG_CMD_IIM - #define CONFIG_IMX_IIM + #define CONFIG_FSL_IIM #endif --#endif /* __CONFIGS_TX53_H */ ++#endif /* __CONFIG_H */ diff --cc include/configs/tx6.h index 8065accf30,a9a5011387..24058cb259 --- a/include/configs/tx6.h +++ b/include/configs/tx6.h @@@ -1,19 -1,15 +1,15 @@@ /* * Copyright (C) 2012 * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation version 2. + * SPDX-License-Identifier: GPL-2.0 * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. */ - #ifndef __TX6_H - #define __TX6_H + -#ifndef __TX6_H -#define __TX6_H ++#ifndef __CONFIG_H ++#define __CONFIG_H #include + #include /* * Ka-Ro TX6 board - SoC configuration @@@ -353,8 -350,4 +350,4 @@@ #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ GENERATED_GBL_DATA_SIZE) - #ifdef CONFIG_CMD_IIM - #define CONFIG_IMX_IIM - #endif - -#endif /* __CONFIGS_TX6_H */ +#endif /* __CONFIG_H */