From: Shaveta Leekha <shaveta@freescale.com>
Date: Wed, 26 Feb 2014 10:37:51 +0000 (+0530)
Subject: B4860qds: Set SerDes2 refclk2 at to 156.25MHz for XFI to work
X-Git-Tag: v2014.04-rc2~10^2~8
X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=commitdiff_plain;h=c4930b1a0ee5a35c49de10e0289f9c8253e78848;hp=6df82e3c0f3e1b160ff08dbf4a2e36f8c75de68e

B4860qds: Set SerDes2 refclk2 at to 156.25MHz for XFI to work

Change setting of SerDes2 refclk2 to have the default value as it is
coming on board that is 156.25MHz, for XFI to work.
Also change PLL_NUM variable to the one defined in config_mpc85xx.h
for B4860 and B4420.

Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Reviewed-by: York Sun <yorksun@freescale.com>
---

diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
index 25b3be8663..24a709e257 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -29,7 +29,6 @@
 
 #define CLK_MUX_SEL_MASK	0x4
 #define ETH_PHY_CLK_OUT		0x4
-#define PLL_NUM			2
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -386,7 +385,7 @@ int config_serdes1_refclks(void)
 		/* Steps For SerDes PLLs reset and reconfiguration after
 		 * changing SerDes's refclks
 		 */
-		for (i = 0; i < PLL_NUM; i++) {
+		for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
 			debug("For PLL%d reset and reconfiguration after"
 			       " changing refclks\n", i+1);
 			clrbits_be32(&srds_regs->bank[i].rstctl,
@@ -453,7 +452,7 @@ int config_serdes2_refclks(void)
 		if (!ret) {
 			ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2,
 					SERDES_REFCLK_100,
-					SERDES_REFCLK_100, 0);
+					SERDES_REFCLK_156_25, 0);
 			if (ret) {
 				printf("IDT8T49N222A configuration failed.\n");
 				goto out;
@@ -467,7 +466,7 @@ int config_serdes2_refclks(void)
 		/* Steps For SerDes PLLs reset and reconfiguration after
 		 * changing SerDes's refclks
 		 */
-		for (i = 0; i < PLL_NUM; i++) {
+		for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
 			clrbits_be32(&srds2_regs->bank[i].rstctl,
 					SRDS_RSTCTL_SDRST_B);
 			udelay(10);