From: Albert ARIBAUD Date: Fri, 10 Oct 2014 06:56:01 +0000 (+0200) Subject: Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' X-Git-Tag: KARO-TXA5-2015-06-26~541^2~6 X-Git-Url: https://git.kernelconcepts.de/?p=karo-tx-uboot.git;a=commitdiff_plain;h=ebf8644a113a36b163c2e06fe1e081c73f563c3a;hp=7d2f669b94aa42579b5d5775dfb076bce0102e3f Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master' --- diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 7365fca526..72558b8562 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -336,6 +336,9 @@ config TARGET_BCM958622HR config ARCH_EXYNOS bool "Samsung EXYNOS" +config ARCH_S5PC1XX + bool "Samsung S5PC1XX" + config ARCH_HIGHBANK bool "Calxeda Highbank" @@ -432,12 +435,6 @@ config RMOBILE config TARGET_CM_FX6 bool "Support cm_fx6" -config TARGET_S5P_GONI - bool "Support s5p_goni" - -config TARGET_SMDKC100 - bool "Support smdkc100" - config TARGET_SOCFPGA_CYCLONE5 bool "Support socfpga_cyclone5" @@ -553,6 +550,8 @@ source "arch/arm/cpu/arm926ejs/orion5x/Kconfig" source "arch/arm/cpu/armv7/rmobile/Kconfig" +source "arch/arm/cpu/armv7/s5pc1xx/Kconfig" + source "arch/arm/cpu/armv7/tegra-common/Kconfig" source "arch/arm/cpu/armv7/uniphier/Kconfig" @@ -661,9 +660,7 @@ source "board/raspberrypi/rpi_b/Kconfig" source "board/ronetix/pm9261/Kconfig" source "board/ronetix/pm9263/Kconfig" source "board/ronetix/pm9g45/Kconfig" -source "board/samsung/goni/Kconfig" source "board/samsung/smdk2410/Kconfig" -source "board/samsung/smdkc100/Kconfig" source "board/sandisk/sansa_fuze_plus/Kconfig" source "board/scb9328/Kconfig" source "board/schulercontrol/sc_sps_1/Kconfig" diff --git a/arch/arm/cpu/armv7/exynos/Kconfig b/arch/arm/cpu/armv7/exynos/Kconfig index e7c93d8c1f..7a0d182e5f 100644 --- a/arch/arm/cpu/armv7/exynos/Kconfig +++ b/arch/arm/cpu/armv7/exynos/Kconfig @@ -5,6 +5,7 @@ choice config TARGET_SMDKV310 bool "Exynos4210 SMDKV310 board" + select OF_CONTROL if !SPL_BUILD config TARGET_TRATS bool "Exynos4210 Trats board" diff --git a/arch/arm/cpu/armv7/s5pc1xx/Kconfig b/arch/arm/cpu/armv7/s5pc1xx/Kconfig new file mode 100644 index 0000000000..2fbbc18203 --- /dev/null +++ b/arch/arm/cpu/armv7/s5pc1xx/Kconfig @@ -0,0 +1,25 @@ +if ARCH_S5PC1XX + +choice + prompt "S5PC1XX board select" + +config TARGET_S5P_GONI + bool "S5P Goni board" + select OF_CONTROL if !SPL_BUILD + +config TARGET_SMDKC100 + bool "Support smdkc100 board" + select OF_CONTROL if !SPL_BUILD + +endchoice + +config SYS_CPU + default "armv7" + +config SYS_SOC + default "s5pc1xx" + +source "board/samsung/goni/Kconfig" +source "board/samsung/smdkc100/Kconfig" + +endif diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.S b/arch/arm/cpu/armv7/s5pc1xx/cache.S deleted file mode 100644 index 3089592eb1..0000000000 --- a/arch/arm/cpu/armv7/s5pc1xx/cache.S +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2009 Samsung Electronics - * Minkyu Kang - * - * based on arch/arm/cpu/armv7/omap3/cache.S - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -.align 5 - -#include - -#ifndef CONFIG_SYS_L2CACHE_OFF -ENTRY(v7_outer_cache_enable) - push {r0, r1, r2, lr} - mrc 15, 0, r3, cr1, cr0, 1 - orr r3, r3, #2 - mcr 15, 0, r3, cr1, cr0, 1 - pop {r1, r2, r3, pc} -ENDPROC(v7_outer_cache_enable) - -ENTRY(v7_outer_cache_disable) - push {r0, r1, r2, lr} - mrc 15, 0, r3, cr1, cr0, 1 - bic r3, r3, #2 - mcr 15, 0, r3, cr1, cr0, 1 - pop {r1, r2, r3, pc} -ENDPROC(v7_outer_cache_disable) -#endif diff --git a/arch/arm/cpu/armv7/s5pc1xx/cache.c b/arch/arm/cpu/armv7/s5pc1xx/cache.c new file mode 100644 index 0000000000..51af2990c2 --- /dev/null +++ b/arch/arm/cpu/armv7/s5pc1xx/cache.c @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * Minkyu Kang + * Robert Baldyga + * + * based on arch/arm/cpu/armv7/omap3/cache.S + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + dcache_enable(); +} + +void disable_caches(void) +{ + dcache_disable(); +} +#endif + +#ifndef CONFIG_SYS_L2CACHE_OFF +void v7_outer_cache_enable(void) +{ + __asm( + "push {r0, r1, r2, lr}\n\t" + "mrc 15, 0, r3, cr1, cr0, 1\n\t" + "orr r3, r3, #2\n\t" + "mcr 15, 0, r3, cr1, cr0, 1\n\t" + "pop {r1, r2, r3, pc}" + ); +} + +void v7_outer_cache_disable(void) +{ + __asm( + "push {r0, r1, r2, lr}\n\t" + "mrc 15, 0, r3, cr1, cr0, 1\n\t" + "bic r3, r3, #2\n\t" + "mcr 15, 0, r3, cr1, cr0, 1\n\t" + "pop {r1, r2, r3, pc}" + ); +} +#endif diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 5f2b946fdd..c37580ed84 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1,4 +1,7 @@ +dtb-$(CONFIG_S5PC100) += s5pc1xx-smdkc100.dtb +dtb-$(CONFIG_S5PC110) += s5pc1xx-goni.dtb dtb-$(CONFIG_EXYNOS4) += exynos4210-origen.dtb \ + exynos4210-smdkv310.dtb \ exynos4210-universal_c210.dtb \ exynos4210-trats.dtb \ exynos4412-trats2.dtb \ diff --git a/arch/arm/dts/exynos4210-smdkv310.dts b/arch/arm/dts/exynos4210-smdkv310.dts new file mode 100644 index 0000000000..c390c8f0c8 --- /dev/null +++ b/arch/arm/dts/exynos4210-smdkv310.dts @@ -0,0 +1,21 @@ +/* + * Samsung's Exynos4210-based SMDKV310 board device tree source + * + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; +/include/ "exynos4.dtsi" + +/ { + model = "Samsung SMDKV310 on Exynos4210"; + compatible = "samsung,smdkv310", "samsung,exynos4210"; + + aliases { + serial0 = "/serial@13800000"; + console = "/serial@13820000"; + }; + +}; diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts index 3ed70a8a92..995e62b337 100644 --- a/arch/arm/dts/exynos5420-peach-pit.dts +++ b/arch/arm/dts/exynos5420-peach-pit.dts @@ -28,11 +28,66 @@ pmic = "/i2c@12ca0000"; }; + cros-ec-keyb { + compatible = "google,cros-ec-keyb"; + google,key-rows = <8>; + google,key-columns = <13>; + google,repeat-delay-ms = <240>; + google,repeat-rate-ms = <30>; + google,ghost-filter; + /* + * Keymap entries take the form of 0xRRCCKKKK where + * RR=Row CC=Column KKKK=Key Code + * The values below are for a US keyboard layout and + * are taken from the Linux driver. Note that the + * 102ND key is not used for US keyboards. + */ + linux,keymap = < + /* CAPSLCK F1 B F10 */ + 0x0001003a 0x0002003b 0x00030030 0x00040044 + /* N = R_ALT ESC */ + 0x00060031 0x0008000d 0x000a0064 0x01010001 + /* F4 G F7 H */ + 0x0102003e 0x01030022 0x01040041 0x01060023 + /* ' F9 BKSPACE L_CTRL */ + 0x01080028 0x01090043 0x010b000e 0x0200001d + /* TAB F3 T F6 */ + 0x0201000f 0x0202003d 0x02030014 0x02040040 + /* ] Y 102ND [ */ + 0x0205001b 0x02060015 0x02070056 0x0208001a + /* F8 GRAVE F2 5 */ + 0x02090042 0x03010029 0x0302003c 0x03030006 + /* F5 6 - \ */ + 0x0304003f 0x03060007 0x0308000c 0x030b002b + /* R_CTRL A D F */ + 0x04000061 0x0401001e 0x04020020 0x04030021 + /* S K J ; */ + 0x0404001f 0x04050025 0x04060024 0x04080027 + /* L ENTER Z C */ + 0x04090026 0x040b001c 0x0501002c 0x0502002e + /* V X , M */ + 0x0503002f 0x0504002d 0x05050033 0x05060032 + /* L_SHIFT / . SPACE */ + 0x0507002a 0x05080035 0x05090034 0x050B0039 + /* 1 3 4 2 */ + 0x06010002 0x06020004 0x06030005 0x06040003 + /* 8 7 0 9 */ + 0x06050009 0x06060008 0x0608000b 0x0609000a + /* L_ALT DOWN RIGHT Q */ + 0x060a0038 0x060b006c 0x060c006a 0x07010010 + /* E R W I */ + 0x07020012 0x07030013 0x07040011 0x07050017 + /* U R_SHIFT P O */ + 0x07060016 0x07070036 0x07080019 0x07090018 + /* UP LEFT */ + 0x070b0067 0x070c0069>; + }; + dmc { mem-manuf = "samsung"; mem-type = "ddr3"; clock-frequency = <800000000>; - arm-frequency = <1700000000>; + arm-frequency = <900000000>; }; tmu@10060000 { diff --git a/arch/arm/dts/s5pc1xx-goni.dts b/arch/arm/dts/s5pc1xx-goni.dts new file mode 100644 index 0000000000..2e671bbf7e --- /dev/null +++ b/arch/arm/dts/s5pc1xx-goni.dts @@ -0,0 +1,28 @@ +/* + * Samsung's S5PC110-based Goni board device tree source + * + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "skeleton.dtsi" + +/ { + model = "Samsung Goni based on S5PC110"; + compatible = "samsung,goni", "samsung,s5pc110"; + + aliases { + serial2 = "/serial@e2900800"; + console = "/serial@e2900800"; + }; + + serial@e2900800 { + compatible = "samsung,exynos4210-uart"; + reg = <0xe2900800 0x400>; + id = <2>; + }; + +}; diff --git a/arch/arm/dts/s5pc1xx-smdkc100.dts b/arch/arm/dts/s5pc1xx-smdkc100.dts new file mode 100644 index 0000000000..42754ce811 --- /dev/null +++ b/arch/arm/dts/s5pc1xx-smdkc100.dts @@ -0,0 +1,29 @@ +/* + * Samsung's Exynos4210-based SMDKV310 board device tree source + * + * Copyright (c) 2014 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "skeleton.dtsi" + +/ { + model = "Samsung SMDKC100 based on S5PC100"; + compatible = "samsung,smdkc100", "samsung,s5pc100"; + + aliases { + serial0 = "/serial@ec000000"; + console = "/serial@ec000000"; + }; + + serial@ec000000 { + compatible = "samsung,exynos4210-uart"; + reg = <0xec000000 0x100>; + interrupts = <0 51 0>; + id = <0>; + }; + +}; diff --git a/arch/arm/include/asm/arch-s5pc1xx/periph.h b/arch/arm/include/asm/arch-s5pc1xx/periph.h new file mode 100644 index 0000000000..5c1c3d4a93 --- /dev/null +++ b/arch/arm/include/asm/arch-s5pc1xx/periph.h @@ -0,0 +1,61 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Rajeshwari Shinde + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARM_ARCH_PERIPH_H +#define __ASM_ARM_ARCH_PERIPH_H + +/* + * Peripherals required for pinmux configuration. List will + * grow with support for more devices getting added. + * Numbering based on interrupt table. + * + */ +enum periph_id { + PERIPH_ID_UART0 = 51, + PERIPH_ID_UART1, + PERIPH_ID_UART2, + PERIPH_ID_UART3, + PERIPH_ID_I2C0 = 56, + PERIPH_ID_I2C1, + PERIPH_ID_I2C2, + PERIPH_ID_I2C3, + PERIPH_ID_I2C4, + PERIPH_ID_I2C5, + PERIPH_ID_I2C6, + PERIPH_ID_I2C7, + PERIPH_ID_SPI0 = 68, + PERIPH_ID_SPI1, + PERIPH_ID_SPI2, + PERIPH_ID_SDMMC0 = 75, + PERIPH_ID_SDMMC1, + PERIPH_ID_SDMMC2, + PERIPH_ID_SDMMC3, + PERIPH_ID_I2C8 = 87, + PERIPH_ID_I2C9, + PERIPH_ID_I2S0 = 98, + PERIPH_ID_I2S1 = 99, + + /* Since following peripherals do + * not have shared peripheral interrupts (SPIs) + * they are numbered arbitiraly after the maximum + * SPIs Exynos has (128) + */ + PERIPH_ID_SROMC = 128, + PERIPH_ID_SPI3, + PERIPH_ID_SPI4, + PERIPH_ID_SDMMC4, + PERIPH_ID_PWM0, + PERIPH_ID_PWM1, + PERIPH_ID_PWM2, + PERIPH_ID_PWM3, + PERIPH_ID_PWM4, + PERIPH_ID_I2C10 = 203, + + PERIPH_ID_NONE = -1, +}; + +#endif /* __ASM_ARM_ARCH_PERIPH_H */ diff --git a/arch/arm/include/asm/arch-s5pc1xx/pinmux.h b/arch/arm/include/asm/arch-s5pc1xx/pinmux.h new file mode 100644 index 0000000000..0b91ef658c --- /dev/null +++ b/arch/arm/include/asm/arch-s5pc1xx/pinmux.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2012 Samsung Electronics + * Abhilash Kesavan + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARM_ARCH_PINMUX_H +#define __ASM_ARM_ARCH_PINMUX_H + +#include "periph.h" + +/* + * Flags for setting specific configarations of peripherals. + * List will grow with support for more devices getting added. + */ +enum { + PINMUX_FLAG_NONE = 0x00000000, + + /* Flags for eMMC */ + PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */ + + /* Flags for SROM controller */ + PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */ + PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */ +}; + +/** + * Configures the pinmux for a particular peripheral. + * + * Each gpio can be configured in many different ways (4 bits on exynos) + * such as "input", "output", "special function", "external interrupt" + * etc. This function will configure the peripheral pinmux along with + * pull-up/down and drive strength. + * + * @param peripheral peripheral to be configured + * @param flags configure flags + * @return 0 if ok, -1 on error (e.g. unsupported peripheral) + */ +int exynos_pinmux_config(int peripheral, int flags); + +/** + * Decode the peripheral id using the interrpt numbers. + * + * @param blob Device tree blob + * @param node FDT I2C node to find + * @return peripheral id if ok, PERIPH_ID_NONE on error + */ +int pinmux_decode_periph_id(const void *blob, int node); +#endif diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index fd5d2d2ca9..5edb250f06 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -158,10 +158,10 @@ static void board_clock_init(void) * For MOUThpm = 1000 MHz (MOUTapll) * doutcopy = MOUThpm / (ratio + 1) = 200 (4) * sclkhpm = doutcopy / (ratio + 1) = 200 (4) - * cores_out = armclk / (ratio + 1) = 1000 (0) + * cores_out = armclk / (ratio + 1) = 200 (4) */ clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7); - set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(0); + set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(4); clrsetbits_le32(&clk->div_cpu1, clr, set); @@ -195,8 +195,8 @@ static void board_clock_init(void) while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING) continue; - /* Set MPLL to 880MHz */ - set = SDIV(0) | PDIV(3) | MDIV(110) | FSEL(0) | PLL_ENABLE(1); + /* Set MPLL to 800MHz */ + set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1); clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set); @@ -220,15 +220,15 @@ static void board_clock_init(void) DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7); /* * For: - * MOUTdmc = 880 MHz - * MOUTdphy = 880 MHz + * MOUTdmc = 800 MHz + * MOUTdphy = 800 MHz * - * aclk_acp = MOUTdmc / (ratio + 1) = 220 (3) - * pclk_acp = aclk_acp / (ratio + 1) = 110 (1) - * sclk_dphy = MOUTdphy / (ratio + 1) = 440 (1) - * sclk_dmc = MOUTdmc / (ratio + 1) = 440 (1) - * aclk_dmcd = sclk_dmc / (ratio + 1) = 220 (1) - * aclk_dmcp = aclk_dmcd / (ratio + 1) = 110 (1) + * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3) + * pclk_acp = aclk_acp / (ratio + 1) = 100 (1) + * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1) + * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1) + * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1) + * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1) */ set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) | DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1); @@ -244,13 +244,13 @@ static void board_clock_init(void) C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127); /* * For: - * MOUTg2d = 880 MHz - * MOUTc2c = 880 Mhz + * MOUTg2d = 800 MHz + * MOUTc2c = 800 Mhz * MOUTpwi = 108 MHz * - * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 440 (1) - * sclk_c2c = MOUTc2c / (ratio + 1) = 440 (1) - * aclk_c2c = sclk_c2c / (ratio + 1) = 220 (1) + * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1) + * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1) + * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1) * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5) */ set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) | @@ -282,9 +282,9 @@ static void board_clock_init(void) clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) | UART3_RATIO(15) | UART4_RATIO(15); /* - * For MOUTuart0-4: 880MHz + * For MOUTuart0-4: 800MHz * - * SCLK_UARTx = MOUTuartX / (ratio + 1) = 110 (7) + * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7) */ set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) | UART3_RATIO(7) | UART4_RATIO(7); @@ -298,12 +298,12 @@ static void board_clock_init(void) clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) | MMC1_PRE_RATIO(255); /* - * For MOUTmmc0-3 = 880 MHz (MPLL) + * For MOUTmmc0-3 = 800 MHz (MPLL) * - * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 110 (7) - * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 60 (1) - * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 110 (7) - * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 60 (1) + * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7) + * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1) + * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7) + * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1) */ set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) | MMC1_PRE_RATIO(1); @@ -318,12 +318,12 @@ static void board_clock_init(void) clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) | MMC3_PRE_RATIO(255); /* - * For MOUTmmc0-3 = 880 MHz (MPLL) + * For MOUTmmc0-3 = 800 MHz (MPLL) * - * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 110 (7) - * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 60 (1) - * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 110 (7) - * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 60 (1) + * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7) + * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1) + * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7) + * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1) */ set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) | MMC3_PRE_RATIO(1); @@ -337,10 +337,10 @@ static void board_clock_init(void) /* CLK_DIV_FSYS3 */ clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255); /* - * For MOUTmmc4 = 880 MHz (MPLL) + * For MOUTmmc4 = 800 MHz (MPLL) * - * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 110 (7) - * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 110 (0) + * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7) + * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0) */ set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0); diff --git a/board/samsung/smdk5250/MAINTAINERS b/board/samsung/smdk5250/MAINTAINERS index 8a2a4aa63c..070593e266 100644 --- a/board/samsung/smdk5250/MAINTAINERS +++ b/board/samsung/smdk5250/MAINTAINERS @@ -6,7 +6,7 @@ F: include/configs/smdk5250.h F: configs/smdk5250_defconfig SNOW BOARD -M: Rajeshwari Shinde +M: Akshay Saraswat S: Maintained F: include/configs/snow.h F: configs/snow_defconfig diff --git a/board/samsung/smdk5420/MAINTAINERS b/board/samsung/smdk5420/MAINTAINERS index c8241a82f5..e0f5c7a530 100644 --- a/board/samsung/smdk5420/MAINTAINERS +++ b/board/samsung/smdk5420/MAINTAINERS @@ -4,9 +4,5 @@ S: Maintained F: board/samsung/smdk5420/ F: include/configs/peach-pit.h F: configs/peach-pit_defconfig - -SMDK5420 BOARD -M: Rajeshwari Shinde -S: Maintained F: include/configs/smdk5420.h F: configs/smdk5420_defconfig diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig index c0c35090cf..618e590802 100644 --- a/configs/s5p_goni_defconfig +++ b/configs/s5p_goni_defconfig @@ -1,2 +1,4 @@ CONFIG_ARM=y +CONFIG_ARCH_S5PC1XX=y CONFIG_TARGET_S5P_GONI=y +CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-goni" diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig index 7455235f23..041030f942 100644 --- a/configs/smdkc100_defconfig +++ b/configs/smdkc100_defconfig @@ -1,2 +1,4 @@ CONFIG_ARM=y CONFIG_TARGET_SMDKC100=y +CONFIG_ARCH_S5PC1XX=y +CONFIG_DEFAULT_DEVICE_TREE="s5pc1xx-smdkc100" diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig index 44da2732b6..0d1a24f99f 100644 --- a/configs/smdkv310_defconfig +++ b/configs/smdkv310_defconfig @@ -2,3 +2,4 @@ CONFIG_SPL=y +S:CONFIG_ARM=y +S:CONFIG_ARCH_EXYNOS=y +S:CONFIG_TARGET_SMDKV310=y +CONFIG_DEFAULT_DEVICE_TREE="exynos4210-smdkv310" diff --git a/drivers/mmc/s5p_sdhci.c b/drivers/mmc/s5p_sdhci.c index 2ff0ec2a42..637dd972a5 100644 --- a/drivers/mmc/s5p_sdhci.c +++ b/drivers/mmc/s5p_sdhci.c @@ -14,9 +14,7 @@ #include #include #include -#ifdef CONFIG_OF_CONTROL #include -#endif static char *S5P_NAME = "SAMSUNG SDHCI"; static void s5p_sdhci_set_control_reg(struct sdhci_host *host) diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile index a472f61f88..e7b07ebab4 100644 --- a/drivers/power/pmic/Makefile +++ b/drivers/power/pmic/Makefile @@ -11,7 +11,8 @@ obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o -obj-$(CONFIG_POWER_TPS65090) += pmic_tps65090.o +obj-$(CONFIG_POWER_TPS65090_I2C) += pmic_tps65090.o +obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o obj-$(CONFIG_POWER_TPS65218) += pmic_tps65218.o obj-$(CONFIG_POWER_TPS65910) += pmic_tps65910.o diff --git a/drivers/power/pmic/pmic_tps65090_ec.c b/drivers/power/pmic/pmic_tps65090_ec.c new file mode 100644 index 0000000000..ac0d44fec8 --- /dev/null +++ b/drivers/power/pmic/pmic_tps65090_ec.c @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2013 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define TPS65090_ADDR 0x48 + +static struct tps65090 { + struct cros_ec_dev *dev; /* The CROS_EC device */ +} config; + +/* TPS65090 register addresses */ +enum { + REG_IRQ1 = 0, + REG_CG_CTRL0 = 4, + REG_CG_STATUS1 = 0xa, + REG_FET1_CTRL = 0x0f, + REG_FET2_CTRL, + REG_FET3_CTRL, + REG_FET4_CTRL, + REG_FET5_CTRL, + REG_FET6_CTRL, + REG_FET7_CTRL, + TPS65090_NUM_REGS, +}; + +enum { + IRQ1_VBATG = 1 << 3, + CG_CTRL0_ENC_MASK = 0x01, + + MAX_FET_NUM = 7, + MAX_CTRL_READ_TRIES = 5, + + /* TPS65090 FET_CTRL register values */ + FET_CTRL_TOFET = 1 << 7, /* Timeout, startup, overload */ + FET_CTRL_PGFET = 1 << 4, /* Power good for FET status */ + FET_CTRL_WAIT = 3 << 2, /* Overcurrent timeout max */ + FET_CTRL_ADENFET = 1 << 1, /* Enable output auto discharge */ + FET_CTRL_ENFET = 1 << 0, /* Enable FET */ +}; + +/** + * tps65090_read - read a byte from tps6090 + * + * @param reg The register address to read from. + * @param val We'll return value value read here. + * @return 0 if ok; error if EC returns failure. + */ +static int tps65090_read(u32 reg, u8 *val) +{ + return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1, + val, 1, true); +} + +/** + * tps65090_write - write a byte to tps6090 + * + * @param reg The register address to write to. + * @param val The value to write. + * @return 0 if ok; error if EC returns failure. + */ +static int tps65090_write(u32 reg, u8 val) +{ + return cros_ec_i2c_xfer(config.dev, TPS65090_ADDR, reg, 1, + &val, 1, false); +} + +/** + * Checks for a valid FET number + * + * @param fet_id FET number to check + * @return 0 if ok, -EINVAL if FET value is out of range + */ +static int tps65090_check_fet(unsigned int fet_id) +{ + if (fet_id == 0 || fet_id > MAX_FET_NUM) { + debug("parameter fet_id is out of range, %u not in 1 ~ %u\n", + fet_id, MAX_FET_NUM); + return -EINVAL; + } + + return 0; +} + +/** + * Set the power state for a FET + * + * @param fet_id Fet number to set (1..MAX_FET_NUM) + * @param set 1 to power on FET, 0 to power off + * @return -EIO if we got a comms error, -EAGAIN if the FET failed to + * change state. If all is ok, returns 0. + */ +static int tps65090_fet_set(int fet_id, bool set) +{ + int retry; + u8 reg, value; + + value = FET_CTRL_ADENFET | FET_CTRL_WAIT; + if (set) + value |= FET_CTRL_ENFET; + + if (tps65090_write(REG_FET1_CTRL + fet_id - 1, value)) + return -EIO; + + /* Try reading until we get a result */ + for (retry = 0; retry < MAX_CTRL_READ_TRIES; retry++) { + if (tps65090_read(REG_FET1_CTRL + fet_id - 1, ®)) + return -EIO; + + /* Check that the fet went into the expected state */ + if (!!(reg & FET_CTRL_PGFET) == set) + return 0; + + /* If we got a timeout, there is no point in waiting longer */ + if (reg & FET_CTRL_TOFET) + break; + + mdelay(1); + } + + debug("FET %d: Power good should have set to %d but reg=%#02x\n", + fet_id, set, reg); + return -EAGAIN; +} + +int tps65090_fet_enable(unsigned int fet_id) +{ + ulong start; + int loops; + int ret; + + ret = tps65090_check_fet(fet_id); + if (ret) + return ret; + + start = get_timer(0); + for (loops = 0;; loops++) { + ret = tps65090_fet_set(fet_id, true); + if (!ret) + break; + + if (get_timer(start) > 100) + break; + + /* Turn it off and try again until we time out */ + tps65090_fet_set(fet_id, false); + } + + if (ret) { + debug("%s: FET%d failed to power on: time=%lums, loops=%d\n", + __func__, fet_id, get_timer(start), loops); + } else if (loops) { + debug("%s: FET%d powered on after %lums, loops=%d\n", + __func__, fet_id, get_timer(start), loops); + } + /* + * Unfortunately, there are some conditions where the power + * good bit will be 0, but the fet still comes up. One such + * case occurs with the lcd backlight. We'll just return 0 here + * and assume that the fet will eventually come up. + */ + if (ret == -EAGAIN) + ret = 0; + + return ret; +} + +int tps65090_fet_disable(unsigned int fet_id) +{ + int ret; + + ret = tps65090_check_fet(fet_id); + if (ret) + return ret; + + ret = tps65090_fet_set(fet_id, false); + + return ret; +} + +int tps65090_fet_is_enabled(unsigned int fet_id) +{ + u8 reg = 0; + int ret; + + ret = tps65090_check_fet(fet_id); + if (ret) + return ret; + ret = tps65090_read(REG_FET1_CTRL + fet_id - 1, ®); + if (ret) { + debug("fail to read FET%u_CTRL register over I2C", fet_id); + return -EIO; + } + + return reg & FET_CTRL_ENFET; +} + +int tps65090_init(void) +{ + puts("TPS65090 PMIC EC init\n"); + + config.dev = board_get_cros_ec_dev(); + if (!config.dev) { + debug("%s: no cros_ec device: cannot init tps65090\n", + __func__); + return -ENODEV; + } + + return 0; +} diff --git a/include/configs/arndale.h b/include/configs/arndale.h index 43077cf851..f9ee40fa7e 100644 --- a/include/configs/arndale.h +++ b/include/configs/arndale.h @@ -9,109 +9,19 @@ #ifndef __CONFIG_ARNDALE_H #define __CONFIG_ARNDALE_H -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* S5P Family */ -#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ -#define CONFIG_EXYNOS5250 - -#include /* get chip and board defs */ - -#define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - - -/* Allow tracing to be enabled */ -#define CONFIG_TRACE -#define CONFIG_CMD_TRACE -#define CONFIG_TRACE_BUFFER_SIZE (16 << 20) -#define CONFIG_TRACE_EARLY_SIZE (8 << 20) -#define CONFIG_TRACE_EARLY -#define CONFIG_TRACE_EARLY_ADDR 0x50000000 - -/* Keep L2 Cache Disabled */ -#define CONFIG_SYS_DCACHE_OFF - -#define CONFIG_SYS_SDRAM_BASE 0x40000000 -#define CONFIG_SYS_TEXT_BASE 0x43E00000 - -/* input clock of PLL: SMDK5250 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - -/* Power Down Modes */ -#define S5P_CHECK_SLEEP 0x00000BAD -#define S5P_CHECK_DIDLE 0xBAD00000 -#define S5P_CHECK_LPA 0xABAD0000 - -/* Offset for inform registers */ -#define INFORM0_OFFSET 0x800 -#define INFORM1_OFFSET 0x804 - -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) - -/* select serial console configuration */ -#define CONFIG_BAUDRATE 115200 -#define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 -#define CONFIG_SILENT_CONSOLE - -/* Console configuration */ -#define CONFIG_CONSOLE_MUX -#define CONFIG_SYS_CONSOLE_IS_IN_ENV -#define EXYNOS_DEVICE_SETTINGS \ - "stdin=serial\0" \ - "stdout=serial\0" \ - "stderr=serial\0" - -#define CONFIG_EXTRA_ENV_SETTINGS \ - EXYNOS_DEVICE_SETTINGS +#include "exynos5250-common.h" /* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_S5P_SDHCI -#define CONFIG_DWMMC -#define CONFIG_EXYNOS_DWMMC #define CONFIG_SUPPORT_EMMC_BOOT -#define CONFIG_BOUNCE_BUFFER - - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* PWM */ -#define CONFIG_PWM /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -/* Command definition*/ -#include - -#define CONFIG_CMD_PING -#define CONFIG_CMD_ELF -#define CONFIG_CMD_MMC #define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_CMD_NET -#define CONFIG_CMD_HASH - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* USB */ -#define CONFIG_CMD_USB #define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_EXYNOS -#define CONFIG_USB_STORAGE #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 #define CONFIG_USB_HOST_ETHER @@ -119,106 +29,23 @@ /* MMC SPL */ #define CONFIG_EXYNOS_SPL -#define COPY_BL2_FNPTR_ADDR 0x02020030 - -#define CONFIG_SPL_LIBCOMMON_SUPPORT - -/* specific .lds file */ -#define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" -#define CONFIG_SPL_TEXT_BASE 0x02023400 -#define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) - -#define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000" /* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT "ARNDALE # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -/* memtest works on */ -#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) - -#define CONFIG_RD_LVL #define CONFIG_NR_DRAM_BANKS 8 #define SDRAM_BANK_SIZE (256UL << 20UL) /* 256 MB */ -#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE -#define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) -#define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_5 (CONFIG_SYS_SDRAM_BASE + (4 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_5_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_6 (CONFIG_SYS_SDRAM_BASE + (5 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_6_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_7 (CONFIG_SYS_SDRAM_BASE + (6 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_7_SIZE SDRAM_BANK_SIZE -#define PHYS_SDRAM_8 (CONFIG_SYS_SDRAM_BASE + (7 * SDRAM_BANK_SIZE)) -#define PHYS_SDRAM_8_SIZE SDRAM_BANK_SIZE -#define CONFIG_SYS_MONITOR_BASE 0x00000000 - -/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH -#undef CONFIG_CMD_IMLS #define CONFIG_IDENT_STRING " for ARNDALE" -#define CONFIG_SYS_MMC_ENV_DEV 0 - #define CONFIG_ENV_IS_IN_MMC -#define CONFIG_SECURE_BL1_ONLY - -/* Secure FW size configuration */ -#ifdef CONFIG_SECURE_BL1_ONLY -#define CONFIG_SEC_FW_SIZE (8 << 10) /* 8KB */ -#else -#define CONFIG_SEC_FW_SIZE 0 -#endif - -/* Configuration of BL1, BL2, ENV Blocks on mmc */ -#define CONFIG_RES_BLOCK_SIZE (512) -#define CONFIG_BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ -#define CONFIG_BL2_SIZE (512UL << 10UL) /* 512 KB */ -#define CONFIG_ENV_SIZE (16 << 10) /* 16 KB */ - -#define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) -#define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) #define CONFIG_ENV_OFFSET (CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE) -/* U-boot copy size from boot Media to DRAM.*/ -#define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) -#define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) - -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_CMD_PART -#define CONFIG_PARTITION_UUIDS - - #define CONFIG_IRAM_STACK 0x02050000 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK -/* I2C */ -#define CONFIG_SYS_I2C_INIT_BOARD -#define CONFIG_SYS_I2C -#define CONFIG_CMD_I2C -#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 /* 100 Kbps */ -#define CONFIG_SYS_I2C_S3C24X0 -#define CONFIG_MAX_I2C_NUM 8 -#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0x0 -#define CONFIG_I2C_EDID - /* PMIC */ #define CONFIG_PMIC #define CONFIG_POWER_I2C @@ -227,26 +54,6 @@ #define CONFIG_PREBOOT -/* Ethernet Controllor Driver */ -#ifdef CONFIG_CMD_NET -#define CONFIG_SMC911X -#define CONFIG_SMC911X_BASE 0x5000000 -#define CONFIG_SMC911X_16_BIT -#define CONFIG_ENV_SROM_BANK 1 -#endif /*CONFIG_CMD_NET*/ - -/* Enable PXE Support */ -#ifdef CONFIG_CMD_NET -#define CONFIG_CMD_PXE -#define CONFIG_MENU -#endif - -/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT - -/* Enable Time Command */ -#define CONFIG_CMD_TIME - #define CONFIG_S5P_PA_SYSRAM 0x02020000 #define CONFIG_SMP_PEN_ADDR CONFIG_S5P_PA_SYSRAM diff --git a/include/configs/exynos4-dt.h b/include/configs/exynos-common.h similarity index 51% rename from include/configs/exynos4-dt.h rename to include/configs/exynos-common.h index 99472acd0c..371f32d840 100644 --- a/include/configs/exynos4-dt.h +++ b/include/configs/exynos-common.h @@ -1,109 +1,78 @@ /* - * Copyright (C) 2014 Samsung Electronics + * Copyright (C) 2013 Samsung Electronics * - * Configuration settings for the SAMSUNG EXYNOS5 board. + * Common configuration settings for the SAMSUNG EXYNOS boards. * * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_H -#define __CONFIG_H +#ifndef __EXYNOS_COMMON_H +#define __EXYNOS_COMMON_H /* High Level Configuration Options */ #define CONFIG_SAMSUNG /* in a SAMSUNG core */ #define CONFIG_S5P /* S5P Family */ -#define CONFIG_EXYNOS4 /* which is in a Exynos4 Family */ #include /* get chip and board defs */ +#include +#define CONFIG_SYS_GENERIC_BOARD #define CONFIG_ARCH_CPU_INIT #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_COMMON -#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_EARLY_INIT_F + +/* Enable fdt support */ +#define CONFIG_OF_LIBFDT -#define CONFIG_SYS_CACHELINE_SIZE 32 +/* Keep L2 Cache Disabled */ +#define CONFIG_CMD_CACHE -/* input clock of PLL: EXYNOS4 boards have 24MHz input clock */ +/* input clock of PLL: 24MHz input clock */ #define CONFIG_SYS_CLK_FREQ 24000000 #define CONFIG_SETUP_MEMORY_TAGS #define CONFIG_CMDLINE_TAG -#define CONFIG_REVISION_TAG #define CONFIG_INITRD_TAG #define CONFIG_CMDLINE_EDITING +#define CONFIG_ENV_OVERWRITE -#include +/* Size of malloc() pool before and after relocation */ +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) + +/* select serial console configuration */ +#define CONFIG_BAUDRATE 115200 /* SD/MMC configuration */ #define CONFIG_GENERIC_MMC #define CONFIG_MMC #define CONFIG_S5P_SDHCI #define CONFIG_SDHCI -#define CONFIG_MMC_SDMA #define CONFIG_DWMMC #define CONFIG_EXYNOS_DWMMC #define CONFIG_BOUNCE_BUFFER -#define CONFIG_MMC_DEFAULT_DEV 0 + +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK /* PWM */ #define CONFIG_PWM -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - /* Command definition*/ #include -#undef CONFIG_CMD_FPGA -#undef CONFIG_CMD_MISC -#undef CONFIG_CMD_NET -#undef CONFIG_CMD_NFS -#undef CONFIG_CMD_XIMG -#undef CONFIG_CMD_CACHE -#undef CONFIG_CMD_ONENAND -#undef CONFIG_CMD_MTDPARTS -#define CONFIG_CMD_CACHE #define CONFIG_CMD_MMC -#define CONFIG_CMD_DFU -#define CONFIG_CMD_GPT -#define CONFIG_CMD_PMIC -#define CONFIG_CMD_SETEXPR - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK - -/* FAT */ -#define CONFIG_CMD_FAT -#define CONFIG_FAT_WRITE - -/* EXT4 */ #define CONFIG_CMD_EXT4 #define CONFIG_CMD_EXT4_WRITE +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE -/* USB Composite download gadget - g_dnl */ -#define CONFIG_USBDOWNLOAD_GADGET - -/* TIZEN THOR downloader support */ -#define CONFIG_CMD_THOR_DOWNLOAD -#define CONFIG_THOR_FUNCTION - -#define CONFIG_DFU_FUNCTION -#define CONFIG_DFU_MMC -#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M -#define DFU_DEFAULT_POLL_TIMEOUT 300 - -/* USB Samsung's IDs */ -#define CONFIG_G_DNL_VENDOR_NUM 0x04E8 -#define CONFIG_G_DNL_PRODUCT_NUM 0x6601 -#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM -#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D -#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 -#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 -#define CONFIG_G_DNL_MANUFACTURER "Samsung" +#define CONFIG_DOS_PARTITION +#define CONFIG_EFI_PARTITION +#define CONFIG_CMD_PART +#define CONFIG_PARTITION_UUIDS /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ @@ -111,6 +80,7 @@ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ + /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE @@ -118,22 +88,4 @@ #define CONFIG_SYS_NO_FLASH #undef CONFIG_CMD_IMLS -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_CMD_PART -#define CONFIG_PARTITION_UUIDS - -#define CONFIG_USB_GADGET -#define CONFIG_USB_GADGET_S3C_UDC_OTG -#define CONFIG_USB_GADGET_DUALSPEED -#define CONFIG_USB_GADGET_VBUS_DRAW 2 - -#define CONFIG_CMD_USB_MASS_STORAGE -#define CONFIG_USB_GADGET_MASS_STORAGE - -/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT - #endif /* __CONFIG_H */ diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h new file mode 100644 index 0000000000..89ba14e05d --- /dev/null +++ b/include/configs/exynos4-common.h @@ -0,0 +1,68 @@ +/* + * Copyright (C) 2014 Samsung Electronics + * + * Configuration settings for the SAMSUNG EXYNOS5 board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_EXYNOS4_COMMON_H +#define __CONFIG_EXYNOS4_COMMON_H + +#define CONFIG_EXYNOS4 /* Exynos4 Family */ + +#include "exynos-common.h" + +#define CONFIG_BOARD_COMMON + +#define CONFIG_SYS_CACHELINE_SIZE 32 +#define CONFIG_REVISION_TAG + +/* SD/MMC configuration */ +#define CONFIG_MMC_SDMA +#define CONFIG_MMC_DEFAULT_DEV 0 + +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_MISC +#undef CONFIG_CMD_NET +#undef CONFIG_CMD_NFS +#undef CONFIG_CMD_XIMG +#undef CONFIG_CMD_ONENAND +#undef CONFIG_CMD_MTDPARTS +#define CONFIG_CMD_DFU +#define CONFIG_CMD_GPT +#define CONFIG_CMD_PMIC +#define CONFIG_CMD_SETEXPR + +/* USB Composite download gadget - g_dnl */ +#define CONFIG_USBDOWNLOAD_GADGET + +/* TIZEN THOR downloader support */ +#define CONFIG_CMD_THOR_DOWNLOAD +#define CONFIG_THOR_FUNCTION + +#define CONFIG_DFU_FUNCTION +#define CONFIG_DFU_MMC +#define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_32M +#define DFU_DEFAULT_POLL_TIMEOUT 300 + +/* USB Samsung's IDs */ +#define CONFIG_G_DNL_VENDOR_NUM 0x04E8 +#define CONFIG_G_DNL_PRODUCT_NUM 0x6601 +#define CONFIG_G_DNL_THOR_VENDOR_NUM CONFIG_G_DNL_VENDOR_NUM +#define CONFIG_G_DNL_THOR_PRODUCT_NUM 0x685D +#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 +#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 +#define CONFIG_G_DNL_MANUFACTURER "Samsung" + +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ + +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_S3C_UDC_OTG +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_VBUS_DRAW 2 + +#define CONFIG_CMD_USB_MASS_STORAGE +#define CONFIG_USB_GADGET_MASS_STORAGE + +#endif /* __CONFIG_EXYNOS4_COMMON_H */ diff --git a/include/configs/exynos5-dt.h b/include/configs/exynos5-common.h similarity index 64% rename from include/configs/exynos5-dt.h rename to include/configs/exynos5-common.h index 1dc3002523..ba591e7c1e 100644 --- a/include/configs/exynos5-dt.h +++ b/include/configs/exynos5-common.h @@ -6,22 +6,14 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __CONFIG_H -#define __CONFIG_H - -/* High Level Configuration Options */ -#define CONFIG_SAMSUNG /* in a SAMSUNG core */ -#define CONFIG_S5P /* S5P Family */ -#define CONFIG_EXYNOS5 /* which is in a Exynos5 Family */ - -#include /* get chip and board defs */ - -#define CONFIG_SYS_GENERIC_BOARD -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_COMMON -#define CONFIG_ARCH_EARLY_INIT_R +#ifndef __CONFIG_EXYNOS5_COMMON_H +#define __CONFIG_EXYNOS5_COMMON_H + +#define CONFIG_EXYNOS5 /* Exynos5 Family */ + +#include "exynos-common.h" + +#define CONFIG_SYS_CACHELINE_SIZE 64 #define CONFIG_EXYNOS_SPL /* Allow tracing to be enabled */ @@ -32,22 +24,11 @@ #define CONFIG_TRACE_EARLY #define CONFIG_TRACE_EARLY_ADDR 0x50000000 -/* Keep L2 Cache Disabled */ -#define CONFIG_SYS_DCACHE_OFF -#define CONFIG_SYS_CACHELINE_SIZE 64 /* Enable ACE acceleration for SHA1 and SHA256 */ #define CONFIG_EXYNOS_ACE_SHA #define CONFIG_SHA_HW_ACCEL -/* input clock of PLL: SMDK5250 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - /* Power Down Modes */ #define S5P_CHECK_SLEEP 0x00000BAD #define S5P_CHECK_DIDLE 0xBAD00000 @@ -59,66 +40,26 @@ #define INFORM2_OFFSET 0x808 #define INFORM3_OFFSET 0x80c -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20)) - /* select serial console configuration */ #define CONFIG_BAUDRATE 115200 #define EXYNOS5_DEFAULT_UART_OFFSET 0x010000 #define CONFIG_SILENT_CONSOLE - -/* Enable keyboard */ -#define CONFIG_CROS_EC /* CROS_EC protocol */ -#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ -#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ -#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */ -#define CONFIG_CMD_CROS_EC -#define CONFIG_KEYBOARD - -/* Console configuration */ -#define CONFIG_CONSOLE_MUX #define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_CONSOLE_MUX + #define EXYNOS_DEVICE_SETTINGS \ - "stdin=serial,cros-ec-keyb\0" \ - "stdout=serial,lcd\0" \ - "stderr=serial,lcd\0" + "stdin=serial\0" \ + "stdout=serial\0" \ + "stderr=serial\0" #define CONFIG_EXTRA_ENV_SETTINGS \ EXYNOS_DEVICE_SETTINGS -/* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_S5P_SDHCI -#define CONFIG_DWMMC -#define CONFIG_EXYNOS_DWMMC -#define CONFIG_SUPPORT_EMMC_BOOT -#define CONFIG_BOUNCE_BUFFER - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_SKIP_LOWLEVEL_INIT - -/* PWM */ -#define CONFIG_PWM - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -/* Command definition*/ -#include - #define CONFIG_CMD_PING #define CONFIG_CMD_ELF -#define CONFIG_CMD_MMC -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT #define CONFIG_CMD_NET #define CONFIG_CMD_HASH -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK - /* Thermal Management Unit */ #define CONFIG_EXYNOS_TMU #define CONFIG_CMD_DTT @@ -133,6 +74,7 @@ /* MMC SPL */ #define COPY_BL2_FNPTR_ADDR 0x02020030 +#define CONFIG_SUPPORT_EMMC_BOOT #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_GPIO_SUPPORT @@ -140,15 +82,7 @@ /* specific .lds file */ #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" -/* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" /* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* memtest works on */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) @@ -175,10 +109,6 @@ #define CONFIG_SYS_MONITOR_BASE 0x00000000 -/* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH -#undef CONFIG_CMD_IMLS - #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_SECURE_BL1_ONLY @@ -199,23 +129,13 @@ #define CONFIG_BL1_OFFSET (CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE) #define CONFIG_BL2_OFFSET (CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE) -/* Store environment at the end of a 4 MB SPI flash */ -#define FLASH_SIZE (0x4 << 20) -#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) - /* U-boot copy size from boot Media to DRAM.*/ #define BL2_START_OFFSET (CONFIG_BL2_OFFSET/512) #define BL2_SIZE_BLOC_COUNT (CONFIG_BL2_SIZE/512) -#define CONFIG_SPI_BOOTING #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 #define SPI_FLASH_UBOOT_POS (CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) -#define CONFIG_DOS_PARTITION -#define CONFIG_EFI_PARTITION -#define CONFIG_CMD_PART -#define CONFIG_PARTITION_UUIDS - /* I2C */ #define CONFIG_SYS_I2C_INIT_BOARD #define CONFIG_SYS_I2C @@ -227,10 +147,6 @@ #define CONFIG_I2C_EDID /* SPI */ -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_SPI_FLASH -#define CONFIG_ENV_SPI_BASE 0x12D30000 - #ifdef CONFIG_SPI_FLASH #define CONFIG_EXYNOS_SPI #define CONFIG_CMD_SF @@ -250,11 +166,6 @@ #define CONFIG_ENV_SPI_MAX_HZ 50000000 #endif -/* PMIC */ -#define CONFIG_POWER -#define CONFIG_POWER_I2C -#define CONFIG_POWER_TPS65090 - /* Ethernet Controllor Driver */ #ifdef CONFIG_CMD_NET #define CONFIG_SMC911X @@ -269,9 +180,6 @@ #define CONFIG_MENU #endif -/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT - /* SHA hashing */ #define CONFIG_CMD_HASH #define CONFIG_HASH_VERIFY @@ -291,4 +199,8 @@ #define EXYNOS_USB_SECONDARY_BOOT 0xfeed0002 #define EXYNOS_IRAM_SECONDARY_BASE 0x02020018 -#endif /* __CONFIG_H */ +/* Enable FIT support and comparison */ +#define CONFIG_FIT +#define CONFIG_FIT_BEST_MATCH + +#endif /* __CONFIG_EXYNOS5_COMMON_H */ diff --git a/include/configs/exynos5-dt-common.h b/include/configs/exynos5-dt-common.h new file mode 100644 index 0000000000..66547fa34e --- /dev/null +++ b/include/configs/exynos5-dt-common.h @@ -0,0 +1,35 @@ +/* + * Copyright (C) 2014 Google, Inc + * + * Configuration settings for generic Exynos 5 board + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_EXYNOS5_DT_COMMON_H +#define __CONFIG_EXYNOS5_DT_COMMON_H + +#include "exynos5-common.h" + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_TPS65090 + +/* Enable keyboard */ +#define CONFIG_CROS_EC /* CROS_EC protocol */ +#define CONFIG_CROS_EC_KEYB /* CROS_EC keyboard input */ +#define CONFIG_CMD_CROS_EC +#define CONFIG_KEYBOARD + +/* Console configuration */ +#undef EXYNOS_DEVICE_SETTINGS +#define EXYNOS_DEVICE_SETTINGS \ + "stdin=serial,cros-ec-keyb\0" \ + "stdout=serial,lcd\0" \ + "stderr=serial,lcd\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + EXYNOS_DEVICE_SETTINGS + +#endif diff --git a/include/configs/exynos5250-dt.h b/include/configs/exynos5250-common.h similarity index 88% rename from include/configs/exynos5250-dt.h rename to include/configs/exynos5250-common.h index c24984bd2b..713614f3ad 100644 --- a/include/configs/exynos5250-dt.h +++ b/include/configs/exynos5250-common.h @@ -10,7 +10,7 @@ #ifndef __CONFIG_5250_H #define __CONFIG_5250_H -#include +#include #define CONFIG_EXYNOS5250 #define CONFIG_SYS_SDRAM_BASE 0x40000000 @@ -24,8 +24,6 @@ /* USB */ #define CONFIG_CMD_USB -#define CONFIG_USB_XHCI -#define CONFIG_USB_XHCI_EXYNOS #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 #define CONFIG_USB_STORAGE @@ -33,9 +31,6 @@ #define CONFIG_BOOTCOMMAND "mmc read 40007000 451 2000; bootm 40007000" -#define CONFIG_SYS_PROMPT "SMDK5250 # " -#define CONFIG_IDENT_STRING " for SMDK5250" - #define CONFIG_IRAM_STACK 0x02050000 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_IRAM_STACK diff --git a/include/configs/exynos5420.h b/include/configs/exynos5420-common.h similarity index 71% rename from include/configs/exynos5420.h rename to include/configs/exynos5420-common.h index d2a95567a8..b0f940cd16 100644 --- a/include/configs/exynos5420.h +++ b/include/configs/exynos5420-common.h @@ -9,7 +9,18 @@ #ifndef __CONFIG_EXYNOS5420_H #define __CONFIG_EXYNOS5420_H -#define CONFIG_EXYNOS5420 /* which is in a Exynos5 Family */ +#define CONFIG_EXYNOS5420 + +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) +#define CONFIG_SPI_BOOTING + +#include + +#define CONFIG_ARCH_EARLY_INIT_R #define MACH_TYPE_SMDK5420 8002 #define CONFIG_MACH_TYPE MACH_TYPE_SMDK5420 @@ -31,14 +42,12 @@ #define CONFIG_MAX_I2C_NUM 11 -/* Enable FIT support and comparison */ -#define CONFIG_FIT -#define CONFIG_FIT_BEST_MATCH - #define CONFIG_BOARD_REV_GPIO_COUNT 2 #define CONFIG_BOOTCOMMAND "mmc read 20007000 451 2000; bootm 20007000" +#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2 + /* * Put the initial stack pointer 1KB below this to allow room for the * SPL marker. This value is arbitrary, but gd_t is placed starting here. @@ -49,4 +58,7 @@ #define CONFIG_NR_DRAM_BANKS 7 #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ +/* Miscellaneous configurable options */ +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" + #endif /* __CONFIG_EXYNOS5420_H */ diff --git a/include/configs/odroid.h b/include/configs/odroid.h index b616ac2fbd..b928af839e 100644 --- a/include/configs/odroid.h +++ b/include/configs/odroid.h @@ -12,7 +12,7 @@ #ifndef __CONFIG_ODROID_U3_H #define __CONFIG_ODROID_U3_H -#include +#include #define CONFIG_SYS_PROMPT "Odroid # " /* Monitor Command Prompt */ @@ -37,8 +37,6 @@ #define CONFIG_SYS_TEXT_BASE 0x43e00000 #include -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) /* select serial console configuration */ #define CONFIG_SERIAL1 diff --git a/include/configs/origen.h b/include/configs/origen.h index fb1536c62c..da9d6a1ee1 100644 --- a/include/configs/origen.h +++ b/include/configs/origen.h @@ -9,7 +9,7 @@ #ifndef __CONFIG_ORIGEN_H #define __CONFIG_ORIGEN_H -#include +#include #define CONFIG_SYS_PROMPT "ORIGEN # " @@ -35,9 +35,6 @@ #define CONFIG_MACH_TYPE MACH_TYPE_ORIGEN -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) - /* select serial console configuration */ #define CONFIG_SERIAL2 #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/peach-pit.h b/include/configs/peach-pit.h index 987cef504c..ab8ac60df2 100644 --- a/include/configs/peach-pit.h +++ b/include/configs/peach-pit.h @@ -9,10 +9,16 @@ #ifndef __CONFIG_PEACH_PIT_H #define __CONFIG_PEACH_PIT_H -#include +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) -#include +#include +#include +#define CONFIG_BOARD_COMMON /* select serial console configuration */ #define CONFIG_SERIAL3 /* use SERIAL 3 */ @@ -30,4 +36,10 @@ #define LCD_BPP LCD_COLOR16 #endif +#define CONFIG_POWER_TPS65090_EC +#define CONFIG_CROS_EC_SPI /* Support CROS_EC over SPI */ + +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_EXYNOS + #endif /* __CONFIG_PEACH_PIT_H */ diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index a51215d9ae..0c6e9c7878 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -39,8 +39,9 @@ #define CONFIG_INITRD_TAG #define CONFIG_CMDLINE_EDITING -/* Size of malloc() pool.*/ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 80 * SZ_1M) +/* Size of malloc() pool before and after relocation */ +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 << 20)) /* * select serial console configuration @@ -53,6 +54,7 @@ #define CONFIG_MMC #define CONFIG_SDHCI #define CONFIG_S5P_SDHCI +#define SDHCI_MAX_HOSTS 4 /* PWM */ #define CONFIG_PWM 1 @@ -106,7 +108,6 @@ ",12m(modem)"\ ",60m(qboot)\0" -#define CONFIG_BOOTDELAY 1 #define CONFIG_ZERO_BOOTDELAY_CHECK /* partitions definitions */ @@ -283,4 +284,6 @@ #define CONFIG_CMD_USB_MASS_STORAGE #define CONFIG_USB_GADGET_MASS_STORAGE +#define CONFIG_OF_LIBFDT + #endif /* __CONFIG_H */ diff --git a/include/configs/s5pc210_universal.h b/include/configs/s5pc210_universal.h index 082d51c52b..27f3d0af47 100644 --- a/include/configs/s5pc210_universal.h +++ b/include/configs/s5pc210_universal.h @@ -10,7 +10,7 @@ #ifndef __CONFIG_UNIVERSAL_H #define __CONFIG_UNIVERSAL_H -#include +#include #define CONFIG_SYS_PROMPT "Universal # " /* Monitor Command Prompt */ @@ -27,9 +27,6 @@ #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) - /* select serial console configuration */ #define CONFIG_SERIAL2 #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 61170941c1..83953728dd 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -9,11 +9,26 @@ #ifndef __CONFIG_SMDK_H #define __CONFIG_SMDK_H -#include +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) +#define CONFIG_SPI_BOOTING +#include -/* Enable FIT support and comparison */ -#define CONFIG_FIT -#define CONFIG_FIT_BEST_MATCH + +#define CONFIG_BOARD_COMMON +#define CONFIG_ARCH_EARLY_INIT_R + +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_EXYNOS + +#define CONFIG_SYS_PROMPT "SMDK5250 # " +#define CONFIG_IDENT_STRING " for SMDK5250" + +/* Miscellaneous configurable options */ +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" #endif /* __CONFIG_SMDK_H */ diff --git a/include/configs/smdk5420.h b/include/configs/smdk5420.h index 36a156f7a7..fd2d482e4a 100644 --- a/include/configs/smdk5420.h +++ b/include/configs/smdk5420.h @@ -9,9 +9,9 @@ #ifndef __CONFIG_SMDK5420_H #define __CONFIG_SMDK5420_H -#include +#include -#include +#define CONFIG_BOARD_COMMON #define CONFIG_SMDK5420 /* which is in a SMDK5420 */ @@ -21,5 +21,6 @@ #define CONFIG_SYS_PROMPT "SMDK5420 # " #define CONFIG_IDENT_STRING " for SMDK5420" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" #endif /* __CONFIG_SMDK5420_H */ diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index c9a2e1568f..22835ffd64 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -47,6 +47,10 @@ * 1MB = 0x100000, 0x100000 = 1024 * 1024 */ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) + +/* Small malloc pool before relocation */ +#define CONFIG_SYS_MALLOC_F_LEN (1 << 10) + /* * select serial console configuration */ @@ -217,4 +221,6 @@ #define CONFIG_ENV_SROM_BANK 3 /* Select SROM Bank-3 for Ethernet*/ #endif /* CONFIG_CMD_NET */ +#define CONFIG_OF_LIBFDT + #endif /* __CONFIG_H */ diff --git a/include/configs/smdkv310.h b/include/configs/smdkv310.h index 048c178692..a2469eb60c 100644 --- a/include/configs/smdkv310.h +++ b/include/configs/smdkv310.h @@ -9,71 +9,42 @@ #ifndef __CONFIG_H #define __CONFIG_H +#include "exynos4-common.h" + +#undef CONFIG_BOARD_COMMON +#undef CONFIG_USB_GADGET +#undef CONFIG_USB_GADGET_S3C_UDC_OTG +#undef CONFIG_CMD_USB_MASS_STORAGE +#undef CONFIG_REVISION_TAG +#undef CONFIG_CMD_THOR_DOWNLOAD +#undef CONFIG_CMD_DFU + /* High Level Configuration Options */ -#define CONFIG_SAMSUNG 1 /* in a SAMSUNG core */ -#define CONFIG_S5P 1 /* S5P Family */ -#define CONFIG_EXYNOS4 /* EXYNOS4 Family */ #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ #define CONFIG_SMDKV310 1 /* working with SMDKV310*/ -#include /* get chip and board defs */ - -#define CONFIG_ARCH_CPU_INIT -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_BOARD_EARLY_INIT_F - /* Mach Type */ #define CONFIG_MACH_TYPE MACH_TYPE_SMDKV310 #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define CONFIG_SYS_TEXT_BASE 0x43E00000 -/* input clock of PLL: SMDKV310 has 24MHz input clock */ -#define CONFIG_SYS_CLK_FREQ 24000000 - -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_CMDLINE_TAG -#define CONFIG_INITRD_TAG -#define CONFIG_CMDLINE_EDITING - /* Handling Sleep Mode*/ #define S5P_CHECK_SLEEP 0x00000BAD #define S5P_CHECK_DIDLE 0xBAD00000 #define S5P_CHECK_LPA 0xABAD0000 -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) - /* select serial console configuration */ #define CONFIG_SERIAL1 1 /* use SERIAL 1 */ -#define CONFIG_BAUDRATE 115200 #define EXYNOS4_DEFAULT_UART_OFFSET 0x010000 -/* SD/MMC configuration */ -#define CONFIG_GENERIC_MMC -#define CONFIG_MMC -#define CONFIG_SDHCI -#define CONFIG_S5P_SDHCI - -/* PWM */ -#define CONFIG_PWM 1 - /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE -/* Command definition*/ -#include - #define CONFIG_CMD_PING #define CONFIG_CMD_ELF #define CONFIG_CMD_DHCP -#define CONFIG_CMD_MMC #define CONFIG_CMD_NET -#define CONFIG_CMD_FAT - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ZERO_BOOTDELAY_CHECK /* MMC SPL */ #define CONFIG_SKIP_LOWLEVEL_INIT @@ -84,15 +55,8 @@ #define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" /* Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ #define CONFIG_SYS_PROMPT "SMDKV310 # " -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size*/ -#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* memtest works on */ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x6000000) @@ -111,8 +75,6 @@ #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE /* FLASH and environment organization */ -#define CONFIG_SYS_NO_FLASH 1 -#undef CONFIG_CMD_IMLS #define CONFIG_IDENT_STRING " for SMDKC210/V310" #define CONFIG_CLK_1000_400_200 @@ -126,7 +88,6 @@ #define RESERVE_BLOCK_SIZE (512) #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ #define CONFIG_ENV_OFFSET (RESERVE_BLOCK_SIZE + BL1_SIZE) -#define CONFIG_DOS_PARTITION 1 #define CONFIG_SPL_LDSCRIPT "board/samsung/common/exynos-uboot-spl.lds" #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) @@ -146,6 +107,4 @@ #define CONFIG_ENV_SROM_BANK 1 #endif /*CONFIG_CMD_NET*/ -/* Enable devicetree support */ -#define CONFIG_OF_LIBFDT #endif /* __CONFIG_H */ diff --git a/include/configs/snow.h b/include/configs/snow.h index fbaaa593cc..7eaa58697e 100644 --- a/include/configs/snow.h +++ b/include/configs/snow.h @@ -9,11 +9,28 @@ #ifndef __CONFIG_SNOW_H #define __CONFIG_SNOW_H -#include +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SPI_FLASH +#define CONFIG_ENV_SPI_BASE 0x12D30000 +#define FLASH_SIZE (0x4 << 20) +#define CONFIG_ENV_OFFSET (FLASH_SIZE - CONFIG_BL2_SIZE) +#define CONFIG_SPI_BOOTING +#include +#include -/* Enable FIT support and comparison */ -#define CONFIG_FIT -#define CONFIG_FIT_BEST_MATCH + +#define CONFIG_CROS_EC_I2C /* Support CROS_EC over I2C */ +#define CONFIG_POWER_TPS65090_I2C + +#define CONFIG_BOARD_COMMON +#define CONFIG_ARCH_EARLY_INIT_R + +#define CONFIG_USB_XHCI +#define CONFIG_USB_XHCI_EXYNOS + +#define CONFIG_SYS_PROMPT "snow # " +#define CONFIG_IDENT_STRING " for snow" +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" #endif /* __CONFIG_SNOW_H */ diff --git a/include/configs/trats.h b/include/configs/trats.h index 43751e7938..b21ea2de5f 100644 --- a/include/configs/trats.h +++ b/include/configs/trats.h @@ -10,7 +10,7 @@ #ifndef __CONFIG_TRATS_H #define __CONFIG_TRATS_H -#include +#include #define CONFIG_SYS_PROMPT "Trats # " /* Monitor Command Prompt */ @@ -39,10 +39,6 @@ #define CONFIG_SYS_TEXT_BASE 0x63300000 -#include -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) - /* select serial console configuration */ #define CONFIG_SERIAL2 #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/trats2.h b/include/configs/trats2.h index e9a04f7af3..42481ab6e1 100644 --- a/include/configs/trats2.h +++ b/include/configs/trats2.h @@ -11,7 +11,7 @@ #ifndef __CONFIG_TRATS2_H #define __CONFIG_TRATS2_H -#include +#include #define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */ @@ -36,10 +36,6 @@ #define CONFIG_SYS_TEXT_BASE 0x43e00000 -#include -/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) - /* select serial console configuration */ #define CONFIG_SERIAL2 #define CONFIG_BAUDRATE 115200