This patch re-formats the arm920t s3c24x0 header files in preparation for
changes to add support for the Embest SBC2440-II Board.
The changes are as follows:
- re-indent the code using Lindent
- make sure register layouts are defined using a C struct
- replace the upper-case typedef'ed C struct names with lower case
non-typedef'ed ones
- make sure registers are accessed using the proper accessor functions
- run checkpatch.pl and fix any error reports
It assumes the following patch has been applied first:
- [U-Boot][PATCH-ARM] CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards, 05/09/2009
- patch 1/4 of this series
Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have
any s3c2400 or s3c2410 boards but need this patch applying before I can submit
patches for the SBC2440-II Board. Also, temporarily modified sbc2410x, smdk2400,
smdk2410 and trab configs to use the mtd nand driver (which isn't used by any
board at the moment), ran MAKEALL for all ARM9 targets and no new warnings or
errors were found.
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Clean-up of cpu_arm920t and cpu_arm920t_s3c24x0 code
This patch re-formats the code in cpu/arm920t and cpu/arm920t/23c24x0 in
preparation for changes to add support for the Embest SBC2440-II Board.
The changes are as follows:
- re-indent the code using Lindent
- make sure register layouts are defined using a C struct
- replace the upper-case typedef'ed C struct names with lower case
non-typedef'ed ones
- make sure registers are accessed using the proper accessor functions
- run checkpatch.pl and fix any error reports
It assumes the following patch has been applied first:
- [U-Boot][PATCH-ARM] CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards, 05/09/2009
Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have
any s3c2400 or s3c2410 boards but need this patch applying before I can submit
patches for the SBC2440-II Board. Also, ran MAKEALL for all ARM9 targets and no
new warnings or errors were found.
Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This sets CONFIG_SYS_HZ to 1000 for all boards that use the s3c2400 and
s3c2410 cpu's which fixes various problems such as the timeouts in tftp being
too short.
Tested on an Embest SBC2440-II Board with local u-boot patches as I don't
have any s3c2400 or s3c2410 boards but need this patch applying before I can
submit patches for the SBC2440-II Board. Also, ran MAKEALL for all ARM9 targets
and no new warnings or errors were found.
It was originally submitted on 21/06/2009 but didn't get into the 2009.08
release, and Jean-Pierre made one comment on the original patch (see
http://lists.denx.de/pipermail/u-boot/2009-July/055470.html). I've made two
changes to the original patch:
- it's been re-based to the current release
- I've re-named get_timer_raw() to get_ticks() in response to Jean-Pierre's comment
This affects the sbc2410, smdk2400, smdk2410 and trab boards. I've copied it
directly to the maintainers of all except the sbc2410 which doesn't have an
entry in MAINTAINERS.
Signed-off-by: Kevin Morfitt <kmorfitt@aselaptop-1.localdomain> Tested-by: Wolfgang Denk <wd@denx.de> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
Mingkai Hu [Wed, 23 Sep 2009 07:20:38 +0000 (15:20 +0800)]
On-chip ROM boot: MPC8536DS support
The MPC8536E is capable of booting from the on-chip ROM - boot from
eSDHC and boot from eSPI. When power on, the porcessor excutes the
ROM code to initialize the eSPI/eSDHC controller, and loads the mian
U-Boot image from the memory device that interfaced to the controller,
such as the SDCard or SPI EEPROM, to the target memory, e.g. SDRAM or
L2SRAM, then boot from it.
The memory device should contain a specific data structure with control
word and config word at the fixed address. The config word direct the
process how to config the memory device, and the control word direct
the processor where to find the image on the memory device, or where
copy the main image to. The user can use any method to store the data
structure to the memory device, only if store it on the assigned address.
The on-chip ROM code will map the whole 4GB address space by setting
entry0 in the TLB1, so the main image need to switch to Address space 1
to disable this mapping and map the address space again.
This patch implements loading the mian U-Boot image into L2SRAM, so
the image can configure the system memory by using SPD EEPROM.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Mingkai Hu [Wed, 23 Sep 2009 07:20:37 +0000 (15:20 +0800)]
NAND boot: MPC8536DS support
MPC8536E can support booting from NAND flash which uses the
image u-boot-nand.bin. This image contains two parts: a 4K
NAND loader and a main U-Boot image. The former is appended
to the latter to produce u-boot-nand.bin. The 4K NAND loader
includes the corresponding nand_spl directory, along with the
code twisted by CONFIG_NAND_SPL. The main U-Boot image just
like a general U-Boot image except the parts that included by
CONFIG_SYS_RAMBOOT.
When power on, eLBC will automatically load from bank 0 the
4K NAND loader into the FCM buffer RAM where CPU can execute
the boot code directly. In the first stage, the NAND loader
copies itself to RAM or L2SRAM to free up the FCM buffer RAM,
then loads the main image from NAND flash to RAM or L2SRAM
and boot from it.
This patch implements the NAND loader to load the main image
into L2SRAM, so the main image can configure the RAM by using
SPD EEPROM. In the first stage, the NAND loader copies itself
to the second to last 4K address space, and uses the last 4K
address space as the initial RAM for stack.
Obviously, the size of L2SRAM shouldn't be less than the size
of the image used. If so, the workaround is to generate another
image that includes the code to configure the RAM by SPD and
load it to L2SRAM first, then relocate the main image to RAM
to boot up.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker [Fri, 25 Sep 2009 15:14:11 +0000 (11:14 -0400)]
sbc8548: reclaim wasted sector in boot flash
By nature of being based off the MPC8548CDS board, this
board inherited an ENV_SIZE setting of 256k. But since
it has a smaller flash device (8MB soldered on), it has
a native sector size of 128k, and hence the ENV_SIZE was
causing 2 sectors to be used for the environment.
By removing the unused sector, we can push TEXT_BASE up
closer to the end of address space and reclaim that
sector for any other application. This also fixes the
mismatch between TEXT_BASE and MONITOR_LEN reported by
Kumar earlier.
Since this board also supports the ability to boot off
the 64MB SODIMM flash, this change is forward looking
with that in mind; i.e. the settings for MONITOR_LEN
and ENV_SIZE will work when the 512k sectors of the
SODIMM flash are used for alternate boot in the future.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Tue, 29 Sep 2009 02:38:00 +0000 (21:38 -0500)]
ppc/85xx: Clean up immap_85xx.h
* Converted all white space to tabs
* Converted all types to u8/u16/u32
* Reduce lines to fit in 80 columns
* Renamed MPC85xx_{Q,B}MAN -> FSL_CORENET_{Q,B}MAN
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Scott Wood [Mon, 28 Sep 2009 21:33:18 +0000 (16:33 -0500)]
NAND: davinci: Fix warnings when 4-bit ECC not used
I accidentally left v2 of "NAND: DaVinci:Adding 4 BIT ECC support"
applied when I pushed the tree last merge window, and missed these fixes
which were in v3 of that patch.
Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
The commit ecad289fc6bd9d89ef4d5093cc7b6fd712fd0d29 (OneNAND: Remove
unused read_spareram and add unlock_all as kernel does) forgot to remove
a local reference to read_spareram in board/micronas/vct/ebi_onenand.c,
which causes the following build failure when configured with OneNAND:
ebi_onenand.c: In function 'onenand_board_init':
ebi_onenand.c:196: error: 'struct onenand_chip' has no member named 'read_spareram'
make[1]: *** [ebi_onenand.o] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [board/micronas/vct/libvct.a] Error 2
Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com> Acked-by: Stefan Roese <sr@denx.de> Cc: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Stefan Roese [Thu, 24 Sep 2009 11:59:57 +0000 (13:59 +0200)]
ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper case
The latest PPC4xx register cleanup patch missed some SDRAM defines.
This patch now changes lower case UIC defines to upper case. Also
some names are changed to match the naming in the IBM/AMCC users
manuals (e.g. mem_mcopt1 -> SDRAM0_CFG).
__i2c_read always ends with a STOP condition thereby releasing
the bus. It is cleaner to do the STOP magic in i2c_read(), like
i2c_write() does. This may also help future multimaster systems which
wants to hold on to the bus until all transactions are finished.
fsl_i2c: Impl. AN2919, rev 5 to calculate FDR/DFSR
The latest AN2919 has changed the way FDR/DFSR should be calculated.
Update the driver according to spec. However, Condition 2
is not accounted for as it is not clear how to do so.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Acked-by: Wolfgang Grandegger <wg@grandegger.com>
Kim Phillips [Fri, 25 Sep 2009 23:19:44 +0000 (18:19 -0500)]
mpc83xx: retain POR values of non-configured ACR, SPCR, SCCR, and LCRR bitfields
some LCRR bits are not documented throughout the 83xx family RMs.
New board porters copying similar board configurations might omit
setting e.g., DBYP since it was not documented in their SoC's RM.
Prevent them bricking their board by retaining power on reset values
in bit fields that the board porter doesn't explicitly configure
via CONFIG_SYS_<registername>_<bitfield> assignments in the board
config file.
also move LCRR assignment to cpu_init_r[am] to help ensure no
transactions are being executed via the local bus while CLKDIV is being
modified.
also start to use i/o accessors.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Paul Gortmaker [Mon, 21 Sep 2009 21:44:51 +0000 (17:44 -0400)]
sbc8349: tidy up Makefile to use new configuration script.
Commit 804d83a5 allows us to move all the configuration
variation tweaks out of the top level Makefile and down
into the board config header. This takes advantage of
that for the sbc8349 board.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Anton Vorontsov [Wed, 16 Sep 2009 19:21:59 +0000 (23:21 +0400)]
mpc83xx: mpc8360emds: Use RGMII-ID mode, add workarounds for rev. 2.1 CPUs
This patch fixes various ethernet issues with gigabit links handling
in U-Boot. The workarounds originally implemented by Kim Phillips for
Linux kernel.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Though, it appears that QE Ethernet in Gigabit mode can't transmit
large packets when it tries to work with a data in LBC SDRAM (memtest
didn't discover any issues, is LBC SDRAM just too slow?).
With this patch we can still use the board without DDR memory, but
if DDR is available, we don't use LBC SDRAM.
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Ken MacLeod [Fri, 11 Sep 2009 20:16:18 +0000 (15:16 -0500)]
cmd_fdt.c: fix parse of byte streams and strings
Commit 4abd844d8e extended the fdt command parser to handle property
strings which are split across multiple arguments but it was broken for
byte streams and strings.
Byte stream parsing:
* Fixes where it would terminate early or go into an endless loop.
* Fixes a 0x00 being inserted into the data if there is a space after
'[' or a separate argument.
* Fixes dereferencing the argument pointer after the last argument.
* Checks for bad characters.
String parsing:
* Treat multiple arguments as a string list. This fixes an issue where
only the last argument was stored.
mucmc52, uc101: delete ata@3a00 node, if no CF card is detected
U-Boot can detect if an IDE device is present or not.
If not, and this new config option is activated, U-Boot
removes the ATA node from the DTS before booting Linux,
so the Linux IDE driver does not probe the device and
crash. This is needed for buggy hardware (uc101) where
no pull down resistor is connected to the signal IDE5V_DD7.
- As these boards are similiar, collect common config options
in manroland/common.h and manroland/mpc52xx-common.h
for mpc5200 specific common options for this manufacturer.
- add OF support
- update default environment
Signed-off-by: Heiko Schocher <hs@denx.de>
Minor edit of commit message.
Wolfgang Denk [Thu, 24 Sep 2009 22:57:49 +0000 (00:57 +0200)]
Fix "ppc/85xx: Clean up use of LAWAR defines" breakage
Commit 002741ae86 modified include/asm-ppc/mmu.h such that the LAWAR_
defines were only enabled for the 83xx platform, but they are also
needed on MPC512x system. Enabling these for E300 systems seems thus
more appropriate.
Kumar Gala [Thu, 19 Mar 2009 07:46:19 +0000 (02:46 -0500)]
ppc/p4080: Determine various chip frequencies on CoreNet platforms
The means to determine the core, bus, and DDR frequencies are completely
new on CoreNet style platforms. Additionally on p4080 we can have
different frequencies for FMAN and PME IP blocks. We need to keep track
of the FMAN & PME frequencies since they are used for time stamping
capabilities inside each block.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Thu, 17 Sep 2009 06:52:37 +0000 (01:52 -0500)]
ppc/p4080: Handle timebase enabling and frequency reporting
On CoreNet style platforms the timebase frequency is the bus frequency
defined by 16 (on PQ3 it is divide by 8). Also on the CoreNet platforms
the core not longer controls the enabling of the timebase. We now need
to enable the boot core's timebase via CCSR register writes.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Thu, 19 Mar 2009 07:39:17 +0000 (02:39 -0500)]
ppc/p4080: Add various p4080 related defines (and p4040)
There are various locations that we have chip specific info:
* Makefile for which ddr code to build
* Added p4080 & p4040 to cpu_type_list and SVR list
* Added number of LAWs for p4080
* Set CONFIG_MAX_CPUS to 8 for p4080
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The CoreNet platform style of bringing secondary cores out of reset is
a bit different that the PQ3 style. Mostly the registers that we use
to setup boot translation, enable time bases, and boot release the cores
have moved around.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Thu, 19 Mar 2009 07:32:23 +0000 (02:32 -0500)]
ppc/p4080: Add support for CoreNet style platform LAWs
On CoreNet based platforms the LAW address is split between an high &
low register and we no longer shift the address. Also, the target IDs
on CoreNet platforms have been completely re-assigned.
Additionally, added a new find_law() API to which LAW an address hits in.
This is need for the CoreNet style boot release code since it will need
to determine what the target ID should be set to for boot window
translation.
Finally, enamed LAWAR_EN to LAW_EN and moved to header so we can use
it elsewhere.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Wed, 16 Sep 2009 14:43:12 +0000 (09:43 -0500)]
ppc/p4080: Add p4080 platform immap definitions
The p4080 SoC has a significant amount of commonality with the 85xx/PQ3
platform. We reuse the 85xx immap and just add new definitions for
local access and global utils. The global utils is now broken into
global utils, clocking and run control/power management.
The offsets from CCSR for a number of blocks have also changed. We
introduce the CONFIG_FSL_CORENET define to distinquish the PQ3 style of
platform from the new p4080 platform. We don't use QoirQ as there are
products (like p2020) that are PQ3 based platforms but have the QoirQ
name.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Mingkai Hu [Tue, 22 Sep 2009 06:53:10 +0000 (14:53 +0800)]
ppc/85xx: add ld script file for boot from NAND
The first stage 4K image uses a seperate ld script file to
generate 4K image. This patch moves it to the cpu/mpc85xx/*
to make it avaliable for 85xx platform.
Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker [Mon, 21 Sep 2009 21:19:17 +0000 (17:19 -0400)]
sbc85x0: tidy up Makefile to use new configuration script.
Commit 804d83a5 allows us to move all the configuration
variation tweaks out of the top level Makefile and down
into the boards config header. This takes advantage of
that for the sbc8540/sbc8560 boards.
There were a couple of cheezy comments pointing at incorrect
files, or files that don't exist, so I've cleaned those up too.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker [Mon, 21 Sep 2009 00:36:06 +0000 (20:36 -0400)]
sbc8548: allow enabling PCI via a make config option
Prior to this commit, to enable PCI, you had to go manually
edit the board config header, and if you had 33MHz PCI, you
had to manually change CONFIG_SYS_NS16550_CLK too, which was
not real user friendly,
This adds the typical PCI and clock speed make targets to the
toplevel Makefile in accordance with what is being done with
other boards (i.e. using the "-t" to mkconfig).
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker [Mon, 21 Sep 2009 00:36:05 +0000 (20:36 -0400)]
sbc8548: update PCI/PCI-e support code
The PCI/PCI-e support for the sbc8548 was based on an earlier
version of what the MPC8548CDS board was using, and in its
current state it won't even compile. This re-syncs it to match
the latest codebase and makes use of the new shared PCI functions
to reduce board duplication.
It borrows from the MPC8568MDS, in that it pulls the PCI-e I/O
back to 0xe280_0000 (where PCI2 would be on MPC8548CDS), and
similarly it coalesces the PCI and PCI-e mem into one single TLB.
Both PCI-x and PCI-e have been tested with intel e1000 cards
under linux (with an accompanying dts change in place)
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker [Mon, 21 Sep 2009 00:36:04 +0000 (20:36 -0400)]
sbc8548: correct local bus SDRAM size from 64M to 128M
The size of the LB SDRAM on this board is 128MB, spanning CS3
and CS4. It was previously only being configured for 64MB on
CS3, since that was what the original codebase of the MPC8548CDS
had. In addition to setting up BR4/OR4, this also adds the TLB
entry for the second half of the SDRAM.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker [Fri, 18 Sep 2009 23:08:41 +0000 (19:08 -0400)]
sbc8548: enable access to second bank of flash
The sbc8548 has a 64MB SODIMM flash module off of CS6 that
previously wasn't enumerated by u-boot. There were already
BR6/OR6 settings for it [used by cpu_init_f()] but there
was no TLB entry and it wasn't in the list of flash banks
reported to u-boot.
The location of the 64MB flash is "pulled back" 8MB from
a 64MB boundary, in order to allow address space for the
8MB boot flash that is at the end of 32 bit address space.
This means creating two 4MB TLB entries for the 8MB chunk,
and then expanding the original boot flash entry to 64MB
in order to cover the 8MB boot flash and the remainder
(56MB) of the user flash.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker [Fri, 18 Sep 2009 23:08:40 +0000 (19:08 -0400)]
sbc8548: get_clock_freq is not valid for this board
The get_clock_freq() comes from freescale/common/cadmus.c and is
only valid for the CDS based 85xx reference platforms. It would
be nice if we could read the 33 vs. 66MHz status somehow, but in
the meantime, tie it to CONFIG_SYS_CLK_FREQ like all the other
non-CDS boards do.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker [Fri, 18 Sep 2009 23:08:39 +0000 (19:08 -0400)]
sbc8548: delete unused MPC8548CDS info carried over from port
There are a couple defines and PCI bridge quirks related to the PCI
backplane of the MPC8548CDS that have no meaning in the context of
the port to the sbc8548 board, so delete them.
Also, the form factor of the sbc8548 is a standalone board with a
single PCI-X and a single PCI-e slot. That pretty much guarantees
that it will never be a PCI agent itself, so the host/agent and root
complex/end node distinctions have been removed.
Similarly, since there is no physical connector mapping to PCI2, so
all references of PCI2 in the board support files have been removed
as well.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
The P1020/P1011 SOCs support max 32bit DDR width as opposed to P2020/P2010
where max DDR data width supported is 64bit.
As a next step the DDR data width initialization would be made more dynamic
with more flexibility from the board perspective and user choice.
Going forward we would also remove the hardcodings for platforms with onboard
memories and try to use the FSL SPD code for DDR initialization.
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Paul Gortmaker [Fri, 18 Sep 2009 23:08:46 +0000 (19:08 -0400)]
sbc8548: replace README with completely new document
The previous README.sbc8548 was pretty much content-free. Replace
it with something that actually gives the end user some relevant
hardware details, and also lists the u-boot configuration choices.
Also in the cosmetic department, fix the bogus line in the Makefile
that was carried over from the SBC8560 Makefile, and the typo in
the sbc8548.c copyright.
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Sat, 19 Sep 2009 16:20:54 +0000 (11:20 -0500)]
ppc/85xx: Clean up use of LAWAR defines
On 85xx platforms we shouldn't be using any LAWAR_* defines
but using the LAW_* ones provided by fsl-law.h. Rename any such
uses and limit the LAWAR_ to the 83xx platform as the only user so
we will get compile errors in the future.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Peter Tyser [Mon, 21 Sep 2009 17:04:32 +0000 (12:04 -0500)]
MAKEALL: Add summary information
This change adds some basic summary information to the MAKEALL script.
The summary information includes how many boards were compiled, how many
boards had compile warnings or errors, and which specific boards had
compile warnings or errors.
This information is useful when doing compile testing to quickly
determine which boards are broken.
As a side benefit, no empty $BOARD.ERR files are generated by MAKEALL.
Previously, each board had a corresponding $BOARD.ERR file, even if the
board compiled cleanly.
Simon Kagstrom [Tue, 15 Sep 2009 07:53:29 +0000 (09:53 +0200)]
ubifs: Add support for looking up directory and relative symlinks
This patch adds support for resolving symlinks to directories as well as
relative symlinks. Symlinks are now always resolved during file lookup,
so the load stage no longer needs to special-case them.
Signed-off-by: Simon Kagstrom <simon.kagstrom@netinsight.net> Signed-off-by: Stefan Roese <sr@denx.de>
u-boot reports a PCIE PLL lock error at boot time on Yucca board, and
left PCIe nonfunctional. This is fixed by making u-boot function
ppc4xx_init_pcie() to wait 300 uS after negating reset before the
first check of the PLL lock.
Signed-off-by: Rupjyoti Sarmah <rsarmah@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
projects / karo-tx-uboot.git / log