James Hogan [Tue, 4 Mar 2014 14:48:42 +0000 (14:48 +0000)]
malta: correct tcl script path in README.malta
README.malta referred to board/malta, but malta has now been moved
within board/imgtec/, so correct the path.
Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Paul Burton <paul.burton@imgtec.com>
Masahiro Yamada [Mon, 3 Mar 2014 10:03:17 +0000 (19:03 +0900)]
kbuild: allow empty board directories
U-Boot has compelled all boards to have
board/${BOARD}/ or board/${VENDOR}/${BOARD}/ directory.
Sometimes it does not seem suitable for some boards,
for example Sandbox. (Is it a board?)
And arcangel4 board has nothing to compile
under the board directory.
This commit makes the build system more flexible:
If '<none>' is given to the 6th column (=Board name) of boards.cfg,
Kbuild will not descend into the board directory.
Tom Rini [Thu, 27 Feb 2014 13:27:28 +0000 (08:27 -0500)]
scripts: update checkpatch.pl to latest upstream version
Update to v3.14-rc4's version of checkpatch.pl. In doing so we drop the
changes to top_of_kernel_tree() as we pass in --no-tree and drop our
changes about MAINTAINERS as that's for reporting checkpatch.pl problems
itself (and upstream has said they'll reword this section to be
clearer).
Simon Glass [Wed, 26 Feb 2014 22:59:27 +0000 (15:59 -0700)]
dm: Remove old driver model documentation
This documentation pertains to the planned implementation of driver model
in U-Boot for each subsystem, but it has not been superseded. It is
probably better to have this documentation in the source code for each
subsystem where possible, so that docbook will pick it up. Where this does
not make sense, new documentation can be placed in some suitable file in
doc/driver-model.
Simon Glass [Wed, 26 Feb 2014 22:59:26 +0000 (15:59 -0700)]
dm: Enable gpio command to support driver model
Now that named GPIO banks are supported, along with a way of obtaining
the status of a GPIO (input or output), we can provide an enhanced
GPIO command for driver model. Where the driver provides its own operation
for obtaining the GPIO state, this is used, otherwise a generic version
is sufficient.
Simon Glass [Wed, 26 Feb 2014 22:59:24 +0000 (15:59 -0700)]
dm: Add GPIO support and tests
Add driver model support for GPIOs. Since existing GPIO drivers do not use
driver model, this feature must be enabled by CONFIG_DM_GPIO. After all
GPO drivers are converted over we can perhaps remove this config.
Tests are provided for the sandbox implementation, and are a sufficient
sanity check for basic operation.
The GPIO uclass understands the concept of named banks of GPIOs, with each
GPIO device providing a single bank. Within each bank the GPIOs are numbered
using an offset from 0 to n-1. For example a bank named 'b' with 20
offsets will provide GPIOs named b0 to b19.
Anonymous GPIO banks are also supported, and are just numbered without any
prefix.
Each time a GPIO driver is added to the uclass, the GPIOs are renumbered
accordinging, so there is always a global GPIO numbering order.
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Pavel Herrmann <morpheus.ibis@gmail.com> Signed-off-by: Viktor Křivák <viktor.krivak@gmail.com> Signed-off-by: Tomas Hlavacek <tmshlvck@gmail.com>
Simon Glass [Wed, 26 Feb 2014 22:59:23 +0000 (15:59 -0700)]
dm: Add a demonstration/example driver
As an example of how to write a uclass and a driver, provide a demo version
of each, accessible through the 'demo' command.
To use these with driver model, define CONFIG_CMD_DEMO and CONFIG_DM_DEMO.
The two demo drivers are enabled with CONFIG_DM_DEMO_SIMPLE and
CONFIG_DM_DEMO_SHAPE.
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Pavel Herrmann <morpheus.ibis@gmail.com> Signed-off-by: Viktor Křivák <viktor.krivak@gmail.com> Signed-off-by: Tomas Hlavacek <tmshlvck@gmail.com>
Simon Glass [Wed, 26 Feb 2014 22:59:22 +0000 (15:59 -0700)]
dm: Add a 'dm' command for testing
This command is not required for driver model operation, but can be useful
for testing. It provides simple dumps of internal data structures.
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Pavel Herrmann <morpheus.ibis@gmail.com> Signed-off-by: Viktor Křivák <viktor.krivak@gmail.com> Signed-off-by: Tomas Hlavacek <tmshlvck@gmail.com>
Simon Glass [Wed, 26 Feb 2014 22:59:21 +0000 (15:59 -0700)]
dm: Add basic tests
Add some tests of driver model functionality. Coverage includes:
- basic init
- binding of drivers to devices using platform_data
- automatic probing of devices when referenced
- availability of platform data to devices
- lifecycle from bind to probe to remove to unbind
- renumbering within a uclass when devices are probed/removed
- calling driver-defined operations
- deactivation of drivers when removed
- memory leak across creation and destruction of drivers/uclasses
- uclass init/destroy methods
- automatic probe/remove of children/parents when needed
This function is enabled for sandbox, using CONFIG_DM_TEST.
Simon Glass [Wed, 26 Feb 2014 22:59:20 +0000 (15:59 -0700)]
dm: Set up driver model after relocation
Make driver model available after relocation, by setting up data structures
and scanning for devices using compiled-in platform_data and (when available)
the device tree.
Simon Glass [Wed, 26 Feb 2014 22:59:18 +0000 (15:59 -0700)]
dm: Add base driver model support
Add driver model functionality for generic board.
This includes data structures and base code for registering devices and
uclasses (groups of devices with the same purpose, e.g. all I2C ports will
be in the same uclass).
The feature is enabled with CONFIG_DM.
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Pavel Herrmann <morpheus.ibis@gmail.com> Signed-off-by: Viktor Křivák <viktor.krivak@gmail.com> Signed-off-by: Tomas Hlavacek <tmshlvck@gmail.com>
Simon Glass [Wed, 26 Feb 2014 22:59:16 +0000 (15:59 -0700)]
yaffs: Remove private list implementation
U-Boot already has a list implementation, and files which include both
that and the yaffs implementation will get errors:
In file included from ydirectenv.h:80:0,
from yportenv.h:81,
from yaffs_guts.h:19,
from yaffs_allocator.h:19,
from yaffs_allocator.c:14:
yaffs_list.h:32:8: error: redefinition of ‘struct list_head’
struct list_head {
^
Simon Glass [Wed, 26 Feb 2014 22:59:15 +0000 (15:59 -0700)]
Add cmd_process_error() to report and process errors
U-Boot now uses errors defined in include/errno.h which are negative
integers. Commands which fail need to report the error and return 1
to indicate failure. Add this functionality in cmd_process_error().
For now this merely reports the error number. It would be possible
also to produce a helpful error message by storing the error strings
in U-Boot.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Vineet Gupta <vgupta@synopsys.com> Cc: Tom Rini <trini@ti.com> Cc: Stefan Roese <sr@denx.de> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Acked-by: Tom Rini <trini@ti.com> Acked-by: Stefan Roese <sr@denx.de>
[trini: Add bcm Kona platforms to the patch] Signed-off-by: Tom Rini <trini@ti.com>
Stefan Roese [Tue, 25 Feb 2014 10:07:22 +0000 (11:07 +0100)]
arm: am335x: DXR2: Reset SMSC LAN9303 switch via GPIO upon bootup
Since the switch may be re-configured for VLAN usage in Linux (or any
other OS), lets reset the switch to its default register values upon
power-up. Otherwise network might not be available in U-Boot.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Roger Meier <r.meier@siemens.com> Cc: Lukas Stockmann <lukas.stockmann@siemens.com> Cc: Tom Rini <trini@ti.com>
Dave Gerlach [Tue, 18 Feb 2014 12:32:01 +0000 (07:32 -0500)]
ARM: AM43xx: Change DDR3 Reset Value
The bit DDR3_RST_DEF_VAL inside CTRL_DDR_IO represents the default value
of the ddr reset value for DDR3 before the EMIF takes over. We must have
this bit set high so that on exit from DeepSleep0 within the kernel the
reset line has the proper value.
Dave Gerlach [Tue, 18 Feb 2014 12:32:00 +0000 (07:32 -0500)]
ARM: AM43xx: Write sdram_config to secure_emif_sdram_config
The register secure_emif_sdram_config in control module is copied to
the EMIF sdram_config register when it is coming out of DeepSleep0 in
order to ensure that the EMIF comes up for the correct type of DDR.
Without this, resume can hang from within the kernel.
Per a suggestion from the hardware team, program the emif_pwr_mgmt_ctrl
and emif_pwr_mgmt_ctrl_shdw registers within the EMIF to hold the
desired delay in cycles that the EMIF waits without an access to enter
self-refresh, in this case 8192 cycles. With this, code desiring to
enter self refresh only has to toggle one bit to enable it.
Lokesh Vutla [Tue, 18 Feb 2014 12:31:57 +0000 (07:31 -0500)]
ARM: AM4372: Update EMIF registers for DDR3
Updating EMIF_PHY_CTRL and adding EMIF_READ_WRITE_EXECUTION_THRESHOLD
registers.
In EMIF_PHY_CTRL:
Updating [4:0]READ_LATENCY to 8, because at higher frequencies like
400MHz the read latency expected will be CL+3 as per tests from HW
folks.
Clearing [19]PHY_DIS_CALIB_RST bit as this is used onl for debug
purpose. With out this resume is not working(Still waiting for PHY team
to come back for better explanation).
Mugunthan V N [Tue, 18 Feb 2014 12:31:56 +0000 (07:31 -0500)]
ARM: DRA7xx: add support for reading cpsw 2nd mac from efuse
Adding support for reading cpsw 2nd mac address from efuse and pass it
to kernel via dtb which will be used in dual emac mode of cpsw.
Also correct the bit masking of mac id read from the efuse.
Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Mugunthan V N [Tue, 18 Feb 2014 12:31:55 +0000 (07:31 -0500)]
ARM: AM335x: add support for reading cpsw 2nd mac address from efuse
Adding support for reading cpsw 2nd mac address from efuse and pass it
to kernel via dtb which will be used in dual emac mode of cpsw.
Also adding mii command support to am335x common config.
Acked-by: Tom Rini <trini@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Mugunthan V N [Tue, 18 Feb 2014 12:31:52 +0000 (07:31 -0500)]
drivers: net: cpsw: add support to have phy address from cpsw platform data
Some platforms like AM437x have different EVMs with different phy addresses,
so this patch adds support for passing phy address via cpsw plaform data.
Also renamed phy_id to phy_addr so better understanding of the code.
Reviewed-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
[trini: Update BuR am335x_igep0033 pcm051_rev3 pcm051_rev1 cm_t335
pengwyn boards] Signed-off-by: Tom Rini <trini@ti.com>
Masahiro Yamada [Wed, 26 Feb 2014 08:51:11 +0000 (17:51 +0900)]
nand_spl: display warning message to inform the end of nand_spl
Now we have two different frameworks for doing the same thing.
I'd like to propose to drop nand_spl framework.
How about deleting it before v2014.07 release?
In the interim, this commit will display a warning message
when compiling nand_spl board.
They must be ported to SPL before the deadline,
otherwise they will be removed.
Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Dave Liu <daveliu@freescale.com> Cc: Ron Madrid <info@sheldoninst.com> Cc: Roy Zang <tie-fei.zang@freescale.com> Cc: Stefan Roese <sr@denx.de> Acked-by: Stefan Roese <sr@denx.de>
pekon gupta [Tue, 19 Nov 2013 05:32:17 +0000 (11:02 +0530)]
mtd: nand: omap: optimized chip->ecc.correct() for H/W ECC schemes
chip->ecc.correct() is used for detecting and correcting bit-flips during read
operations. In omap-nand driver it implemented as:
(a) omap_correct_data(): for h/w based ECC_HAM1 scheme
(b) omap_correct_data_bch() + CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
for ECC_BCH8 scheme using GPMC and software lib/bch.c
(c) omap_correct_data_bch() + CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW
for ECC_BCH8 scheme using GPMC and ELM
This patch updates (c)
- checks for calc_ecc[]==0x00 so that error_correction is not required for
known good pages.
- adds scalability for other ECC_BCHx scheme by merging following
omap_rotate_ecc_bch() + omap_fix_errors_bch() => omap_correct_data_bch()
- fixing logic for bit-flip correction based on error_loc[count]
pekon gupta [Tue, 19 Nov 2013 05:32:16 +0000 (11:02 +0530)]
mtd: nand: omap: optimize chip->ecc.calculate() for H/W ECC schemes
chip->ecc.calculate() is used for calculating and fetching of ECC syndrome by
processing the data passed during Read/Write accesses.
All H/W based ECC schemes use GPMC controller to calculate ECC syndrome.
But each BCHx_ECC scheme has its own implemetation of post-processing and
fetching ECC syndrome from GPMC controller.
This patch updates OMAP_ECC_BCH8_CODE_HW ECC scheme in following way:
- merges multiple chip->calculate API for different ECC schemes
omap_calculate_ecc() + omap_calculate_ecc_bch() + omap_calculate_ecc_bch_sw()
==> omap_calculate_ecc()
- removes omap_ecc_disable() and instead uses it as inline.
pekon gupta [Tue, 19 Nov 2013 05:32:15 +0000 (11:02 +0530)]
mtd: nand: omap: optimize chip->ecc.hwctl() for H/W ECC schemes
chip->ecc.hwctl() is used for preparing the H/W controller before read/write
NAND accesses (like assigning data-buf, enabling ECC scheme configs, etc.)
Though all ECC schemes in OMAP NAND driver use GPMC controller for generating
ECC syndrome (for both Read/Write accesses). But but in current code
HAM1_ECC and BCHx_ECC schemes implement individual function to achieve this.
This patch
(1) removes omap_hwecc_init() and omap_hwecc_init_bch()
as chip->ecc.hwctl will re-initializeGPMC before every read/write call.
omap_hwecc_init_bch() -> omap_enable_ecc_bch()
(2) merges the GPMC configuration code for all ECC schemes into
single omap_enable_hwecc(), thus adding scalability for future ECC schemes.
omap_enable_hwecc() + omap_enable_ecc_bch() -> omap_enable_hwecc()
Tom Rini [Tue, 25 Feb 2014 15:27:01 +0000 (10:27 -0500)]
arm: Switch to -mno-unaligned-access when supported by the compiler
When we tell the compiler to optimize for ARMv7 (and ARMv6 for that
matter) it assumes a default of SCTRL.A being cleared and unaligned
accesses being allowed and fast at the hardware level. We set this bit
and must pass along -mno-unaligned-access so that the compiler will
still breakdown accesses and not trigger a data abort.
To better help understand the requirements of the project with respect
to unaligned memory access, the
Documentation/unaligned-memory-access.txt file has been added as
doc/README.unaligned-memory-access.txt and is taken from the v3.14-rc1
tag of the kernel.
Cc: Albert ARIBAUD <albert.u.boot@aribaud.net> Cc: Mans Rullgard <mans@mansr.com> Signed-off-by: Tom Rini <trini@ti.com>
Masahiro Yamada [Tue, 25 Feb 2014 10:26:47 +0000 (19:26 +0900)]
kbuild: Fix a false error of generic board support
Before this commit, make terminated with an error
where is shouldn't under some condition.
This bug happened when we built a board unsupporting
generic board right after building with generic board.
For example, the following sequence failed.
(harmony uses generic board but microblaze-generic does not
support it)
$ make harmony_config
Configuring for harmony board...
$ make CROSS_COMPILE=arm-linux-gnueabi-
[ Build succeed ]
$ make microblaze-generic_config
Configuring for microblaze-generic board...
$ make CROSS_COMPILE=microblaze-linux-
Makefile:488: *** Your architecture does not support generic board.
Please undefined CONFIG_SYS_GENERIC_BOARD in your board config file. Stop.
We had to do "make clean" before building the microblaze board.
This commit fixes this unconvenience.
Move generic board sanity check to "prepare1" target,
which is run after generation of include/autoconf.mk.
"help" target has been copied from Linux 3.13 and adjusted
for U-Boot.
Unlike Linux, cleaning is done on 4 levels:
clean, clobber, mrproper, distclean.
Masahiro Yamada [Mon, 24 Feb 2014 02:12:21 +0000 (11:12 +0900)]
kbuild: refactor more IMX image rules
This commit avoids generating ./SPL twice.
- Fist time descending to spl/
- Second time as a prerequisite of u-boot-with-spl.imx,
u-boot-with-nand-spl.imx.
Nikhil Badola [Mon, 17 Feb 2014 11:28:36 +0000 (16:58 +0530)]
fsl/usb: Limit phy_type comparison to first four characters
Use first four characters for phy_type comparison. Strcmp() should not
be used to check the phy_type string which maybe parsed by hwconfig_subarg().
Hwconfig_subarg() returns part of hwconfig string starting from
phy_type value till the end of the string. Since phy_type could be
either "utmi" or "ulpi", strncmp() should be used so that a comparison
of "utmi;fsl_ddr:bank_intlv=auto" with "utmi" will succeed.
Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Haijun.Zhang [Thu, 13 Feb 2014 01:03:02 +0000 (09:03 +0800)]
powerpc/mpc8536DS:Increase binary size for mpc8536DS board
u-boot binary size for Freescale mpc8536DS platforms is 512KB.
This has been reached to upper limit of the platforms and causig
linker error. So increase the u-boot binary size to 768KB.
Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Zhao Qiang [Mon, 23 Dec 2013 07:51:33 +0000 (15:51 +0800)]
ar8031/8033/phy:enable autonegotiation for ar8031/8033
Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before
while "if (phydev->supported & SUPPORTED_Autoneg)" now.
So assign "phydev->supported" to "phydev->drv->features" for ar8031/8033
to enable autonegotiation.
Signed-off-by: Zhao Qiang <B45475@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Ying Zhang [Fri, 24 Jan 2014 07:50:09 +0000 (15:50 +0800)]
powerpc: p1010rdb: Enable p1010rdb to start from NAND/SD/SPI flash with SPL
In the previous patches, we introduced the SPL/TPL fraamework.
For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The
SPL was loaded by the code from the internal on-chip ROM. The SPL initializes
the DDR according to the SPD and loads the final uboot image into DDR, then
jump to the DDR to begin execution.
For NAND booting way, the nand SPL has size limitation on some board(e.g.
P1010RDB), it can not be more than 8KB, we can call it "minimal SPL", So the
dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is
loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD
and loads the final uboot image into DDR,then jump to the DDR to begin execution.
This patch enabled SPL/TPL for P1010RDB to support starting from NAND/SD/SPI
flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL.
Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to
execute, so the section .resetvec is no longer needed.
Signed-off-by: Ying Zhang <b40530@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
Ying Zhang [Fri, 24 Jan 2014 07:50:08 +0000 (15:50 +0800)]
SPL: P1022DS: fix the problem booting from spi flash
There was no enough memory for malloc in SPL booting from spi flash, so
relayout the memory in SPL: reduce the memory for global data from 16K
Bytes to 4K Bytes, save the space for malloc.
Signed-off-by: Ying Zhang <b40530@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
projects / karo-tx-uboot.git / log