Kumar Gala [Tue, 13 Jul 2010 05:39:46 +0000 (00:39 -0500)]
powerpc/p4080: Add workaround for errata SERDES8
Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Tue, 13 Jul 2010 03:51:29 +0000 (22:51 -0500)]
powerpc/p4080: Add support for initializing SERDES
Add support for initializing the SERDES blocks on CoreNet style QoriQ
devices and the p4080 specific SERDES tables to know which actual
componetns are enabled.
Additionally, split out the Frame Manger (FMAN) into its specific ethernet
ports instead of gross level of the full FMAN.
Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Thu, 10 Sep 2009 08:02:13 +0000 (03:02 -0500)]
powerpc/85xx: Add support to initialize LIODN registers and portals
On the new QorIQ/CoreNet based platforms we need to initialize the
"portals" as access into the Data Path subystem as well as Logical IO
Device Numbers (LIODN) that are used for the IOMMU (PAMU).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Fri, 9 Jul 2010 21:18:58 +0000 (16:18 -0500)]
fdt: Add function to alloc phandle values
If we are creating reference (handles) to nodes in a device tree we need
to first create a new phandle in node and this needs a new phandle
value. So we search through the whole dtb to find the max phandle value
and return the next greater value for a new phandle allocation.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
Kumar Gala [Thu, 19 Mar 2009 08:40:08 +0000 (03:40 -0500)]
powerpc/p4080: Add support for CPC(Corenet platform cache) on CoreNet platforms
The CoreNet style platforms can have a L3 cache that fronts the memory
controllers. Enable that cache as well as add information into the
device tree about it.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Mike Frysinger [Fri, 23 Jul 2010 20:51:49 +0000 (16:51 -0400)]
Blackfin: jtag-console: handle newline stuffing
Serial devices currently have to manually stuff \r after every \n found,
but this is a bit more difficult with the jtag console since we process
everything in chunks of 4 bit. So we have to scan & stuff the whole
string rather than what most serial drivers do which is output on a byte
per byte basis.
Mike Frysinger [Fri, 23 Jul 2010 15:34:49 +0000 (11:34 -0400)]
Blackfin: jtag-console: add debug markers
While we're in here, add some useful debug points. We need custom debug
statements because we need the output to only go to the serial port. If
we used the standard debug helpers, the output would also go to the stdout
(which would be the jtag console) and make it hard to figure out what is
going where exactly.
Mike Frysinger [Fri, 23 Jul 2010 15:34:49 +0000 (11:34 -0400)]
Blackfin: jtag-console: robustify against missing peer
If the other side isn't listening, we should reset the state to ignore
the whole message and not just the part we missed. This makes it easier
to connect at any time to the jtag console without worrying about the two
sides getting out of sync and thus sending garbage back and forth.
Wolfgang Denk [Mon, 19 Jul 2010 09:36:58 +0000 (11:36 +0200)]
FAT32: fix broken root directory handling.
On FAT32, instead of fetching the cluster numbers from the FAT, the
code assumed (incorrectly) that the clusters for the root directory
were allocated contiguously. In the result, only the first cluster
could be accessed. At the typical cluster size of 8 sectors this
caused all accesses to files after the first 128 entries to fail -
"fatls" would terminate after 128 files (usually displaying a bogus
file name, occasionally even crashing the system), and "fatload"
would fail to find any files that were not in the first directory
cluster.
Wolfgang Denk [Mon, 19 Jul 2010 09:36:56 +0000 (11:36 +0200)]
usb_storage.c: initialize device type
The device type was left uninitialized which caused later tests
against DEV_TYPE_UNKNOWN to fail. In the result, "usb part" would
attempt to print information about non-existent devices like this:
=> usb part
print_part of 0
Partition Map for USB device 0 -- Partition Type: DOS
Partition Start Sector Num Sectors Type
1 0 2031616 f8
print_part of 1
## Unknown partition table
print_part of 2
## Unknown partition table
print_part of 3
## Unknown partition table
print_part of 4
## Unknown partition table
=>
By initializing the type as DEV_TYPE_UNKNOWN we avoid all the
"Unknown partition table" messages.
[Note: the "print_part of ?" messages is left over debug code that
will be removed in another patch.]
Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Remy Bohmer <linux@bohmer.net>
Stefan Roese [Wed, 21 Jul 2010 17:06:10 +0000 (19:06 +0200)]
ppc4xx: Add "ecctest" command to test/simulate ECC errors
This patch adds the "ecctest" command to test and simulate ECC errors
(single bit and/or double bit) while running from SDRAM. Currently only
the IBM DDR2 controller is supported (405EX, 440SP(e), 460EX/GT).
This is done by copying and calling functions, modifying the SDRAM
controller operation mode, in internal SRAM/OCM.
For correctable ECC errors (single bit) only the status will be printed
since the DDR2 controller doesn't provide the faulting address:
=> ecctest 1000000 1
Using address 01000000 for 1 bit ECC error injection
ECC: Correctable error
Uncorrectable ECC errors (double bit) will also display the faulting
address:
=> ecctest 1000000 2
Using address 01000000 for 2 bit ECC error injection
ECC: Uncorrectable error at 0x0001000000
To enable this "ecctest" function you need to define CONFIG_CMD_ECCTEST
in the board config header.
Stefan Roese [Wed, 21 Jul 2010 09:08:27 +0000 (11:08 +0200)]
ppc4xx: DDR/ECC: Use correct macros to clear error status
Use the correct macro instead of the hardcoded 0x4c to clear the ECC
status in the 440/460 DDR(2) error status register after ECC
initialization.
Also the non-440 parts (405EX(r) right now) and the IBM DDR PPC variants
(440GX) use a different registers to clear this error status. Use the
correct ones.
Stefan Roese [Tue, 20 Jul 2010 05:06:03 +0000 (07:06 +0200)]
ppc4xx: Add CONFIG_DDR_RFDC_FIXED to allow board specific RFDC values
Using this define, a board can define an opimized RFDC value and use
the auto calibration code to "tune" the remaining DDR2 controller
calibration register.
Stefan Roese [Mon, 19 Jul 2010 12:24:22 +0000 (14:24 +0200)]
ppc4xx: T3CORP fixes and updates
This patch fixes some problems for the T3CORP board. Here the list
of the changes:
- Add 600-67 and 677 CPU frequency setting to chip_config
command
- Define CONFIG_DDR_RFDC_FIXED on t3corp:
While using the "normal" auto calibration code, sometimes values for
RFDC were picked (>= T3) that resulted in a non-working U-Boot (hang
upon relocation, while running from SDRAM). With this optimized RFDC
value we can force this register and use the auto-calibration code to
setup the remaining calibration registers.
- Increase sizes of FPGA chips selects
- EBC timing updated OEN=3 for 66 MHz EBC speed
- Change ext. IRQ2 setup to level-low active
- Enable CONFIG_SYS_CFI_FLASH_STATUS_POLL
By defining CONFIG_SYS_CFI_FLASH_STATUS_POLL, DQ7 is polled to detect the
chip busy status. This is now used instead of the data toggle method which
is used historically by default in the common CFI driver. With this change
a problem with not written data is solved on this board, where a 32 byte
block of data is still erased instead of filled with the correct content
after these commands:
=> erase 0xfc100000 +0x1000000
....................................................................
done
Erased 128 sectors
=> cp.b 0x100000 0xfc100000 0x1000000
Copy to Flash... done
=> cmp.b 0x100000 0xfc100000 0x1000000
byte at 0x00d0d6c0 (0x00) != byte at 0xfcd0d6c0 (0xff)
Total of 12637888 bytes were the same
Kumar Gala [Sun, 11 Jul 2010 17:41:46 +0000 (12:41 -0500)]
powerpc/85xx: Rework P1022 SERDES is_serdes_configured support
Move serdes init until after we are in ram so we can keep track of a
global static protocal map for the particular serdes config we are in.
This makes is_serdes_configured() much simplier and not constantly
reading registers to determine if a given device is enabled based on the
protocol.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Sat, 22 May 2010 18:21:39 +0000 (13:21 -0500)]
powerpc/85xx: Rework MPC8536 SERDES is_serdes_configured support
Move serdes init until after we are in ram so we can keep track of a
global static protocal map for the particular serdes config we are in.
This makes is_serdes_configured() much simplier and not constantly
reading registers to determine if a given device is enabled based on the
protocol.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Wed, 27 Jan 2010 16:26:46 +0000 (10:26 -0600)]
powerpc/p3041: Add various p3041 related defines
There are various locations that we have chip specific info:
* Makefile for which ddr code to build
* Added p3041 to cpu_type_list and SVR list
* Added number of LAWs for p3041
* Set CONFIG_MAX_CPUS to 4 for p3041
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Wed, 21 Oct 2009 18:32:58 +0000 (13:32 -0500)]
powerpc/p5020: Add various p5020 related defines (and p5010)
There are various locations that we have chip specific info:
* Makefile for which ddr code to build
* Added p5020 & p5010 to cpu_type_list and SVR list
* Added number of LAWs for p5020
* Set CONFIG_MAX_CPUS to 2 for p5020
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Sat, 10 Jul 2010 11:55:41 +0000 (06:55 -0500)]
powerpc/p4080: Add setting of clock-frequency for clockgen node
On QorIQ CoreNet based devices we have a global clocking block. We want
to keep track of SYSCLK frequency as it is what is used to derive all
other frequencies in the SoC
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Fri, 9 Jul 2010 03:37:44 +0000 (22:37 -0500)]
powerpc/85xx & 86xx: Rework ft_fsl_pci_setup to not require aliases
Previously we used an alias the pci node to determine which node to
fixup or delete. Now we use the new fdt_node_offset_by_compat_reg to
find the node to update.
Additionally, we replace the code in each board with a single macro call
that makes assumes uniform naming and reduces duplication in this area.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Sun, 4 Jul 2010 17:48:21 +0000 (12:48 -0500)]
fdt: Add fdt_node_offset_by_compat_reg helper
Given a compatible string and physical address try and find a node that
matches. This is useful when we want to find a specific device node to
update (for example if we have multiple PCI nodes we can use the
physical address to distinguish them when trying to update the device
tree).
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
Kumar Gala [Wed, 16 Jun 2010 19:27:38 +0000 (14:27 -0500)]
fdt: Add fdt_translate_address to convert reg node to cpu phys addr
This code is extracted out of the Linux Kernel code from
arch/powerpc/kernel/prom_parse.c.
We maintain some of the same structure to support multiple bus types even
though we only have one in the current code. In the future we might want
to translate across a PCI bus and thus it will be easier to add that
functionality back in.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Gerald Van Baren <vanbaren@cideas.com>
Kumar Gala [Fri, 9 Jul 2010 03:35:59 +0000 (22:35 -0500)]
powerpc/86xx: Move PCI/PCIe address defines into common immap_86xx.h
Remove dupliacted setting of PCI/PCIe address and offsets in board
config.h. Renamed CONFIG_SYS_PCI1/2_ADDR to CONFIG_SYS_PCI1/2ADDR on
MPC8641 boards since its really PCIE controllers and not PCI.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Fri, 9 Jul 2010 03:27:30 +0000 (22:27 -0500)]
powerpc/85xx: Move p1022ds slot code into board file
The code to map SERDES configs to slot names is board specific and not
chip specific. Thus it should live in board/freescale/p1022ds/ and not
in arch/powerpc/cpu/.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Timur Tabi [Fri, 28 May 2010 20:05:30 +0000 (15:05 -0500)]
fsl: add LAW target to fsl_pci_info structure
Add the LAW target (enum law_trgt_if) to the fsl_pci_info structure, so that
we can capture the LAW target for a given PCI or PCIE controller. Also update
the SET_STD_PCI_INFO and SET_STD_PCIE_INFO macros to assign the
LAW_TRGT_IF_PCI[E]_x macro to the LAW target field of the structure.
This will allow future PCI[E] code to configure the LAW target automatically,
rather than requiring each board to it for each PCI controller separately.
Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Tue, 30 Mar 2010 02:03:11 +0000 (21:03 -0500)]
powerpc/85xx: Add support for link stack & STAC on e5500
The e5500 has a link register stack and segment target address cache.
Its safe to enable these bits on older e500 cores as the bits are
implemented in the register.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Becky Bruce [Thu, 17 Jun 2010 16:37:26 +0000 (11:37 -0500)]
powerpc 83xx/85xx: Merge lbc upmconfig code
Each platform had its own version of the upmconfig, despite the
init process being identical. Now that we have a spot for common
lbc code, create a common upmconfig() there.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Becky Bruce [Thu, 17 Jun 2010 16:37:21 +0000 (11:37 -0500)]
mpc85xx: tlb.c cleanups
Extract the operation to read a tlb into a function - we will need
this later to print out the tlbs, and there's no point in duplicating
the code. Create a TSIZE_TO_BYTES macro to deal with the conversion
from the MAS field to an actual size instead of duplicating this in code.
There are a few misc other minor cleanups.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Becky Bruce [Thu, 17 Jun 2010 16:37:20 +0000 (11:37 -0500)]
83xx/85xx/86xx: LBC register cleanup
Currently, 83xx, 86xx, and 85xx have a lot of duplicated code
dedicated to defining and manipulating the LBC registers. Merge
this into a single spot.
To do this, we have to decide on a common name for the data structure
that holds the lbc registers - it will now be known as fsl_lbc_t, and we
adopt a common name for the immap layouts that include the lbc - this was
previously known as either im_lbc or lbus; use the former.
In addition, create accessors for the BR/OR regs that use in/out_be32
and use those instead of the mismash of access methods currently in play.
I have done a successful ppc build all and tested a board or two from
each processor family.
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Becky Bruce [Thu, 17 Jun 2010 16:37:18 +0000 (11:37 -0500)]
powerpc: Update configs to properly set FSL_ELBC
Some parts that have an Enhanced Local Bus Controller weren't
setting CONFIG_FSL_ELBC. Fix this so we can use this define
properly going forward (currently it's only used if PHYS_64BIT is
set, which meant not all platforms needed to have it set correctly).
Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala [Sat, 22 May 2010 22:25:47 +0000 (17:25 -0500)]
ppc/85xx: Add a structure defn for PIXIS registers
The various boards that have PIXIS FPGAs have slightly different
register definitions, however there is some common functionality (like
reset, ICS307 clk control, etc) that can be shared.
The struct definition exists for MPC8536DS, MPC8544DS, MPC8572DS,
MPC8610HPCD, and MPC8641HPCN boards.
Also fixed ngpixis to be __packed__ instead of aligned.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kim Phillips [Tue, 1 Jun 2010 17:24:27 +0000 (12:24 -0500)]
powerpc/8xxx: Distinguish between incompatible SEC h/w types
CONFIG_SYS_FSL_SEC_COMPAT is set to 2 for the SEC 2.x and SEC 3.x.
Parts with newer SEC h/w versions will increment the number to
accomodate incompatible code changes.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Fixes below compilation warning
omap3.c: In function 'musb_platform_init':
omap3.c:123: warning: implicit declaration of function
'omap3_evm_need_extvbus'
Existing code returns checkpatch error on pinmux macro definition for
not enclosing the definition in parenthesis. The error can be observed in
the patch generated from commit id bdc9c6c7f77a9a63349ecb9f54b20ad34033a2ae.
So macro implementation is modified to fix the error.
Marek Vasut [Fri, 16 Apr 2010 22:36:48 +0000 (00:36 +0200)]
PXA: Add hardware init helper macros
This patch adds macros for the following purposes:
- GPIO configuration
- SDRAM configuration
- Wakeup
- Clock configuration
- Interrupt controller configuration
These macros are intended to replace numerous copies of the same code.
Signed-off-by: Marek Vasut <marek.vasut@gmail.com>
projects / karo-tx-uboot.git / log