From 1f2979b99ea4206881f280fe3ed12bc67c36ece7 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Lothar=20Wa=C3=9Fmann?= Date: Fri, 9 Jan 2015 11:49:52 +0100 Subject: [PATCH] karo: tx6: add support for TX6 HW Rev. 3 --- board/karo/tx6/Makefile | 1 + board/karo/tx6/config.mk | 10 +- board/karo/tx6/lowlevel_init.S | 65 ++++++------ board/karo/tx6/rn5t567.c | 186 +++++++++++++++++++++++++++++++++ board/karo/tx6/rn5t618.c | 18 ++++ board/karo/tx6/tx6qdl.c | 75 +++++++++++-- boards.cfg | 24 ++++- include/configs/tx6.h | 36 ++++--- 8 files changed, 356 insertions(+), 59 deletions(-) create mode 100644 board/karo/tx6/rn5t567.c diff --git a/board/karo/tx6/Makefile b/board/karo/tx6/Makefile index 87b5f8b8f1..a353e5a6af 100644 --- a/board/karo/tx6/Makefile +++ b/board/karo/tx6/Makefile @@ -11,6 +11,7 @@ LIB = $(obj)lib$(BOARD).o COBJS-y := tx6qdl.o COBJS-$(CONFIG_LTC3676) += ltc3676.o +COBJS-$(CONFIG_RN5T567) += rn5t567.o COBJS-$(CONFIG_RN5T618) += rn5t618.o COBJS-$(CONFIG_CMD_ROMUPDATE) += flash.o diff --git a/board/karo/tx6/config.mk b/board/karo/tx6/config.mk index 3326141157..c8af7c793e 100644 --- a/board/karo/tx6/config.mk +++ b/board/karo/tx6/config.mk @@ -6,7 +6,7 @@ LOGO_BMP = logos/karo.bmp #PLATFORM_CPPFLAGS += -Wno-unused-but-set-variable PLATFORM_CPPFLAGS += -Werror -ifeq ($(CONFIG_TX6_V2),) +ifeq ($(CONFIG_NO_NAND),) # calculate U_BOOT_IMG_SIZE to be at least 3 eraseblocks larger than the maximum expected image size CONFIG_SYS_NAND_BLOCK_SIZE := 131072 ifeq ($(CONFIG_SYS_NAND_BLOCKS),) @@ -33,7 +33,11 @@ PLATFORM_CPPFLAGS += -DCONFIG_SYS_NAND_BBT_SIZE=$(shell printf "%uk" `expr $(CON PLATFORM_CPPFLAGS += -DCONFIG_SYS_NAND_BBT_OFFSET=$(shell printf "0x%x" `expr \( $(CONFIG_SYS_NAND_BLOCKS) - $(CONFIG_SYS_NAND_BBT_BLOCKS) \) \* $(CONFIG_SYS_NAND_BLOCK_SIZE)`) endif # CONFIG_SYS_NAND_BLOCK_SIZE else -CONFIG_SYS_MMC_BOOT_PART_SIZE := $(shell expr 4096 \* 1024) +ifneq ($(CONFIG_MMC_BOOT_SIZE),) + CONFIG_SYS_MMC_BOOT_PART_SIZE := $(shell expr $(CONFIG_MMC_BOOT_SIZE) \* 1024) +else + CONFIG_SYS_MMC_BOOT_PART_SIZE := $(shell expr 4096 \* 1024) +endif CONFIG_U_BOOT_IMG_SIZE := $(shell expr 1 \* 1048576) CONFIG_MAX_DTB_SIZE := $(shell expr 64 \* 1024) CONFIG_ENV_SIZE := $(shell expr 128 \* 1024) @@ -48,4 +52,4 @@ PLATFORM_CPPFLAGS += -DCONFIG_SYS_MMC_BOOT_PART_SIZE=$(CONFIG_SYS_MMC_BOOT_PART_ PLATFORM_CPPFLAGS += -DCONFIG_ENV_OFFSET=$(shell printf "0x%x" $(CONFIG_ENV_OFFSET)) PLATFORM_CPPFLAGS += -DCONFIG_SYS_DTB_OFFSET=$(shell printf "0x%x" $(CONFIG_SYS_DTB_OFFSET)) PLATFORM_CPPFLAGS += -DCONFIG_SYS_DTB_BLKNO=$(shell printf "0x%x" `expr $(CONFIG_SYS_DTB_OFFSET) / 512`) -endif # CONFIG_TX6_V2 +endif # CONFIG_NO_NAND diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S index d6d062a3a7..11189e11c1 100644 --- a/board/karo/tx6/lowlevel_init.S +++ b/board/karo/tx6/lowlevel_init.S @@ -352,18 +352,14 @@ plugin: ivt_end: #define DCD_VERSION 0x40 -#define CLKCTL_CCGR0 0x68 -#define CLKCTL_CCGR1 0x6c -#define CLKCTL_CCGR2 0x70 -#define CLKCTL_CCGR3 0x74 -#define CLKCTL_CCGR4 0x78 -#define CLKCTL_CCGR5 0x7c -#define CLKCTL_CCGR6 0x80 -#define CLKCTL_CCGR7 0x84 -#define CLKCTL_CMEOR 0x88 - -#define DDR_SEL_VAL 3 -#define DSE_VAL 6 +#define DDR_SEL_VAL 3 /* DDR3 */ +#if PHYS_SDRAM_1_WIDTH == 16 +#define DSE1_VAL 6 /* Drive Strength for DATA lines */ +#define DSE2_VAL 6 /* Drive Strength for ADDR/CMD lines */ +#else +#define DSE1_VAL 6 /* Drive Strength for DATA lines */ +#define DSE2_VAL 6 /* Drive Strength for ADDR/CMD lines */ +#endif #define ODT_VAL 2 #define DDR_PKE_VAL 0 @@ -377,18 +373,19 @@ ivt_end: #define PUS_SHIFT 14 #define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT) -#define DDR_MODE_MASK (1 << DDR_MODE_SHIFT) -#define DSE_MASK (DSE_VAL << DSE_SHIFT) +#define DDR_MODE_MASK (1 << DDR_MODE_SHIFT) /* differential input mode */ +#define DSE1_MASK (DSE1_VAL << DSE_SHIFT) +#define DSE2_MASK (DSE2_VAL << DSE_SHIFT) #define ODT_MASK (ODT_VAL << ODT_SHIFT) #define DDR_PKE_MASK (DDR_PKE_VAL << PKE_SHIFT) -#define DQM_MASK (DDR_MODE_MASK | DSE_MASK) -#define SDQS_MASK DSE_MASK -#define SDODT_MASK (DSE_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) -#define SDCLK_MASK (DDR_MODE_MASK | DSE_MASK) +#define DQM_MASK (DDR_MODE_MASK | DSE2_MASK) +#define SDQS_MASK DSE2_MASK +#define SDODT_MASK (DSE2_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) +#define SDCLK_MASK (DDR_MODE_MASK | DSE2_MASK) #define SDCKE_MASK ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) -#define DDR_ADDR_MASK 0 -#define DDR_CTRL_MASK (DDR_MODE_MASK | DSE_MASK) +#define DDR_ADDR_MASK (ODT_MASK | DDR_MODE_MASK) +#define DDR_CTRL_MASK (DDR_MODE_MASK | DSE2_MASK) #define MMDC1_MDCTL 0x021b0000 #define MMDC1_MDPDC 0x021b0004 @@ -568,7 +565,7 @@ ivt_end: #define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0920 #endif -#ifdef CONFIG_MX6DL +#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S) #define IOMUXC_GPR1 0x020e0004 #define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x020e0218 #define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x020e0330 @@ -755,16 +752,16 @@ dcd_hdr: MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, SDODT_MASK) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, SDODT_MASK) /* DRAM_B[0..7]DS */ - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE_MASK) - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE_MASK) - MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE_MASK) - MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE_MASK) - MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B4DS, DSE_MASK) - MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B5DS, DSE_MASK) - MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B6DS, DSE_MASK) - MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B7DS, DSE_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE1_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE1_MASK) + MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE1_MASK) + MXC_DCD_ITEM_32(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE1_MASK) + MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B4DS, DSE1_MASK) + MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B5DS, DSE1_MASK) + MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B6DS, DSE1_MASK) + MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B7DS, DSE1_MASK) /* ADDDS */ - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE2_MASK) /* DDRMODE_CTL */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK) /* DDRPKE */ @@ -772,7 +769,7 @@ dcd_hdr: /* DDRMODE */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK) /* CTLDS */ - MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_CTLDS, DSE_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_CTLDS, DSE2_MASK) /* DDR_TYPE */ MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, DDR_SEL_MASK) /* DDRPK */ @@ -929,7 +926,8 @@ dcd_hdr: MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */ MXC_DCD_ITEM(MMDC1_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */ MXC_DCD_ITEM_64(MMDC2_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */ - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000001f) + MXC_DCD_CMD_CHK_16(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x00000013) + MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000001f) MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000001f) MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) #else /* DO_DDR_CALIB */ @@ -940,7 +938,8 @@ dcd_hdr: /* Write delay calibration */ MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */ MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */ - MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000001f) + MXC_DCD_CMD_CHK_16(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000013) + MXC_DCD_CMD_CHK_32(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000001f) #if PHYS_SDRAM_1_WIDTH == 64 MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) diff --git a/board/karo/tx6/rn5t567.c b/board/karo/tx6/rn5t567.c new file mode 100644 index 0000000000..f089168baf --- /dev/null +++ b/board/karo/tx6/rn5t567.c @@ -0,0 +1,186 @@ +/* + * Copyright (C) 2014 Lothar Waßmann + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include + +#include "pmic.h" + +#define RN5T567_NOETIMSET 0x11 +#define RN5T567_LDORTC1_SLOT 0x2a +#define RN5T567_DC1CTL 0x2c +#define RN5T567_DC1CTL2 0x2d +#define RN5T567_DC2CTL 0x2e +#define RN5T567_DC2CTL2 0x2f +#define RN5T567_DC3CTL 0x30 +#define RN5T567_DC3CTL2 0x31 +#define RN5T567_DC1DAC 0x36 /* CORE */ +#define RN5T567_DC2DAC 0x37 /* SOC */ +#define RN5T567_DC3DAC 0x38 /* DDR */ +#define RN5T567_DC1DAC_SLP 0x3b +#define RN5T567_DC2DAC_SLP 0x3c +#define RN5T567_DC3DAC_SLP 0x3d +#define RN5T567_LDOEN1 0x44 +#define RN5T567_LDODIS 0x46 +#define RN5T567_LDOEN2 0x48 +#define RN5T567_LDO3DAC 0x4e /* IO */ +#define RN5T567_LDORTC1DAC 0x56 /* VBACKUP */ + +#define NOETIMSET_DIS_OFF_NOE_TIM (1 << 3) + +#define VDD_RTC_VAL mV_to_regval_rtc(3000 * 10) +#define VDD_HIGH_VAL mV_to_regval3(3000 * 10) +#define VDD_HIGH_VAL_LP mV_to_regval3(3000 * 10) +#define VDD_CORE_VAL mV_to_regval(1425 * 10) +#define VDD_CORE_VAL_LP mV_to_regval(900 * 10) +#define VDD_SOC_VAL mV_to_regval(1425 * 10) +#define VDD_SOC_VAL_LP mV_to_regval(900 * 10) +#define VDD_DDR_VAL mV_to_regval(1500 * 10) +#define VDD_DDR_VAL_LP mV_to_regval(1500 * 10) + +/* calculate voltages in 10mV */ +/* DCDC1-3 */ +#define mV_to_regval(mV) DIV_ROUND(((((mV) < 6000) ? 6000 : (mV)) - 6000), 125) +#define regval_to_mV(v) (((v) * 125 + 6000)) + +/* LDO1-2 */ +#define mV_to_regval2(mV) DIV_ROUND(((((mV) < 9000) ? 9000 : (mV)) - 9000), 250) +#define regval2_to_mV(v) (((v) * 250 + 9000)) + +/* LDO3 */ +#define mV_to_regval3(mV) DIV_ROUND(((((mV) < 6000) ? 6000 : (mV)) - 6000), 250) +#define regval3_to_mV(v) (((v) * 250 + 6000)) + +/* LDORTC */ +#define mV_to_regval_rtc(mV) DIV_ROUND(((((mV) < 17000) ? 17000 : (mV)) - 17000), 250) +#define regval_rtc_to_mV(v) (((v) * 250 + 17000)) + +static struct rn5t567_regs { + u8 addr; + u8 val; + u8 mask; +} rn5t567_regs[] = { + { RN5T567_NOETIMSET, NOETIMSET_DIS_OFF_NOE_TIM | 0x5, }, +#if 0 + { RN5T567_DC1DAC, VDD_CORE_VAL, }, + { RN5T567_DC2DAC, VDD_SOC_VAL, }, + { RN5T567_DC3DAC, VDD_DDR_VAL, }, + { RN5T567_DC1DAC_SLP, VDD_CORE_VAL_LP, }, + { RN5T567_DC2DAC_SLP, VDD_SOC_VAL_LP, }, + { RN5T567_DC3DAC_SLP, VDD_DDR_VAL_LP, }, + { RN5T567_LDOEN1, 0x01f, ~0x1f, }, + { RN5T567_LDOEN2, 0x10, ~0x30, }, + { RN5T567_LDODIS, 0x00, }, + { RN5T567_LDO3DAC, VDD_HIGH_VAL, }, + { RN5T567_LDORTCDAC, VDD_RTC_VAL, }, + { RN5T567_LDORTC1_SLOT, 0x0f, ~0x3f, }, +#endif +}; + +static struct rn5t567_regs debug_regs[] __maybe_unused = { + { 0x00, 4, }, + { 0x09, 4, }, + { 0x10, 16, }, + { 0x25, 26, }, + { 0x44, 3, }, + { 0x4c, 5, }, + { 0x56, 1, }, + { 0x58, 5, }, + { 0x97, 2, }, + { 0xb0, 1, }, + { 0xbc, 1, }, +}; + +static int rn5t567_setup_regs(struct rn5t567_regs *r, size_t count) +{ + int ret; + int i; + + for (i = 0; i < count; i++, r++) { +#ifdef DEBUG + unsigned char value; + + ret = i2c_read(CONFIG_SYS_I2C_SLAVE, r->addr, 1, &value, 1); + if ((value & ~r->mask) != r->val) { + printf("Changing PMIC reg %02x from %02x to %02x\n", + r->addr, value, r->val); + } + if (ret) { + printf("%s: failed to read PMIC register %02x: %d\n", + __func__, r->addr, ret); + return ret; + } +#endif +// value = (value & ~r->mask) | r->val; + ret = i2c_write(CONFIG_SYS_I2C_SLAVE, + r->addr, 1, &r->val, 1); + if (ret) { + printf("%s: failed to write PMIC register %02x: %d\n", + __func__, r->addr, ret); + return ret; + } +#ifdef DEBUG + ret = i2c_read(CONFIG_SYS_I2C_SLAVE, r->addr, 1, &value, 1); + printf("PMIC reg %02x is %02x\n", r->addr, value); +#endif + } +#if 0 + for (i = 0; i < ARRAY_SIZE(debug_regs); i++) { + int j; + + r = &debug_regs[i]; + for (j = r->addr; j < r->addr + r->val; j++) { + unsigned char value; + + ret = i2c_read(CONFIG_SYS_I2C_SLAVE, j, 1, &value, 1); + printf("PMIC reg %02x = %02x\n", + j, value); + } + } +#endif + debug("%s() complete\n", __func__); + return 0; +} + +int setup_pmic_voltages(void) +{ + int ret; + unsigned char value; + + ret = i2c_probe(CONFIG_SYS_I2C_SLAVE); + if (ret != 0) { + printf("Failed to initialize I2C\n"); + return ret; + } + + ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1); + if (ret) { + printf("%s: i2c_read error: %d\n", __func__, ret); + return ret; + } + + ret = rn5t567_setup_regs(rn5t567_regs, ARRAY_SIZE(rn5t567_regs)); + if (ret) + return ret; + + printf("VDDCORE set to %umV\n", + DIV_ROUND(regval_to_mV(VDD_CORE_VAL), 10)); + printf("VDDSOC set to %umV\n", + DIV_ROUND(regval_to_mV(VDD_SOC_VAL), 10)); + + return ret; +} diff --git a/board/karo/tx6/rn5t618.c b/board/karo/tx6/rn5t618.c index c68fd30713..06dffa8585 100644 --- a/board/karo/tx6/rn5t618.c +++ b/board/karo/tx6/rn5t618.c @@ -72,6 +72,7 @@ static struct rn5t618_regs { u8 val; u8 mask; } rn5t618_regs[] = { +#if CONFIG_TX6_REV == 2 { RN5T618_NOETIMSET, 0, }, { RN5T618_DC1DAC, VDD_CORE_VAL, }, { RN5T618_DC2DAC, VDD_SOC_VAL, }, @@ -85,6 +86,23 @@ static struct rn5t618_regs { { RN5T618_LDO3DAC, VDD_HIGH_VAL, }, { RN5T618_LDORTCDAC, VDD_RTC_VAL, }, { RN5T618_LDORTC1_SLOT, 0x0f, ~0x3f, }, +#elif CONFIG_TX6_REV == 3 + { RN5T618_NOETIMSET, 0, }, + { RN5T618_DC1DAC, VDD_CORE_VAL, }, + { RN5T618_DC2DAC, VDD_SOC_VAL, }, + { RN5T618_DC3DAC, VDD_DDR_VAL, }, + { RN5T618_DC1DAC_SLP, VDD_CORE_VAL_LP, }, + { RN5T618_DC2DAC_SLP, VDD_SOC_VAL_LP, }, + { RN5T618_DC3DAC_SLP, VDD_DDR_VAL_LP, }, + { RN5T618_LDOEN1, 0x01f, ~0x1f, }, + { RN5T618_LDOEN2, 0x10, ~0x30, }, + { RN5T618_LDODIS, 0x00, }, + { RN5T618_LDO3DAC, VDD_HIGH_VAL, }, + { RN5T618_LDORTCDAC, VDD_RTC_VAL, }, + { RN5T618_LDORTC1_SLOT, 0x0f, ~0x3f, }, +#else +#error Unsupported TX6 module revision +#endif }; static int rn5t618_setup_regs(struct rn5t618_regs *r, size_t count) diff --git a/board/karo/tx6/tx6qdl.c b/board/karo/tx6/tx6qdl.c index d94b7ca825..5d2317dde4 100644 --- a/board/karo/tx6/tx6qdl.c +++ b/board/karo/tx6/tx6qdl.c @@ -59,7 +59,7 @@ DECLARE_GLOBAL_DATA_PTR; #define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0) static const iomux_v3_cfg_t tx6qdl_pads[] = { -#ifdef CONFIG_TX6_V2 +#ifndef CONFIG_NO_NAND /* NAND flash pads */ MX6_PAD_NANDF_CLE__RAWNAND_CLE, MX6_PAD_NANDF_ALE__RAWNAND_ALE, @@ -197,6 +197,8 @@ static void print_reset_cause(void) int read_cpu_temperature(void); int check_cpu_temperature(int boot); +static const char *tx6_mod_suffix; + static void tx6qdl_print_cpuinfo(void) { u32 cpurev = get_cpu_rev(); @@ -205,15 +207,19 @@ static void tx6qdl_print_cpuinfo(void) switch ((cpurev >> 12) & 0xff) { case MXC_CPU_MX6SL: cpu_str = "SL"; + tx6_mod_suffix = "?"; break; case MXC_CPU_MX6DL: cpu_str = "DL"; + tx6_mod_suffix = "U"; break; case MXC_CPU_MX6SOLO: cpu_str = "SOLO"; + tx6_mod_suffix = "S"; break; case MXC_CPU_MX6Q: cpu_str = "Q"; + tx6_mod_suffix = "Q"; break; } @@ -1126,12 +1132,65 @@ exit: return ret; } -#ifdef CONFIG_TX6_V2 -#define TX6_FLASH_SZ 0 +#ifdef CONFIG_NO_NAND +#ifdef CONFIG_MMC_BOOT_SIZE +#define TX6_FLASH_SZ (CONFIG_MMC_BOOT_SIZE / 1024 - 1 + 2) +#else +#define TX6_FLASH_SZ 3 +#endif +#else /* CONFIG_NO_NAND */ +#define TX6_FLASH_SZ (CONFIG_SYS_NAND_BLOCKS / 1024 - 1) +#endif /* CONFIG_NO_NAND */ + +#ifdef CONFIG_SYS_SDRAM_BUS_WIDTH +#define TX6_DDR_SZ (ffs(CONFIG_SYS_SDRAM_BUS_WIDTH / 16) - 1) #else -#define TX6_FLASH_SZ (2 * (CONFIG_SYS_NAND_BLOCKS / 1024 - 1)) +#define TX6_DDR_SZ 2 #endif +#if CONFIG_TX6_REV >= 0x3 +static char tx6_mem_table[] = { + '4', /* 256MiB SDRAM; 128MiB NAND */ + '1', /* 512MiB SDRAM; 128MiB NAND */ + '0', /* 1GiB SDRAM; 128MiB NAND */ + '?', /* 256MiB SDRAM; 256MiB NAND */ + '?', /* 512MiB SDRAM; 256MiB NAND */ + '2', /* 1GiB SDRAM; 256MiB NAND */ + '?', /* 256MiB SDRAM; 4GiB eMMC */ + '5', /* 512MiB SDRAM; 4GiB eMMC */ + '3', /* 1GiB SDRAM; 4GiB eMMC */ + '?', /* 256MiB SDRAM; 8GiB eMMC */ + '?', /* 512MiB SDRAM; 8GiB eMMC */ + '?', /* 1GiB SDRAM; 8GiB eMMC */ +}; + +static inline char tx6_mem_suffix(void) +{ + size_t mem_idx = (TX6_FLASH_SZ * 3) + TX6_DDR_SZ; + + debug("TX6_DDR_SZ=%d TX6_FLASH_SZ=%d idx=%d\n", + TX6_DDR_SZ, TX6_FLASH_SZ, mem_idx); + + if (mem_idx >= ARRAY_SIZE(tx6_mem_table)) + return '?'; + + return tx6_mem_table[mem_idx]; +}; +#else /* CONFIG_TX6_REV >= 0x3 */ +static inline char tx6_mem_suffix(void) +{ +#ifdef CONFIG_SYS_SDRAM_BUS_WIDTH + if (CONFIG_SYS_SDRAM_BUS_WIDTH == 32) + return '1'; +#endif +#ifdef CONFIG_SYS_NAND_BLOCKS + if (CONFIG_SYS_NAND_BLOCKS == 2048) + return '2'; +#endif + return '0'; +} +#endif /* CONFIG_TX6_REV >= 0x3 */ + int checkboard(void) { u32 cpurev = get_cpu_rev(); @@ -1139,11 +1198,11 @@ int checkboard(void) tx6qdl_print_cpuinfo(); - printf("Board: Ka-Ro TX6%c-%d%d1%d\n", - cpu_variant == MXC_CPU_MX6Q ? 'Q' : 'U', + printf("Board: Ka-Ro TX6%s-%d%d%d%c\n", + tx6_mod_suffix, cpu_variant == MXC_CPU_MX6Q ? 1 : 8, - is_lvds(), 1 - PHYS_SDRAM_1_WIDTH / 64 + - TX6_FLASH_SZ); + is_lvds(), CONFIG_TX6_REV, + tx6_mem_suffix()); return 0; } diff --git a/boards.cfg b/boards.cfg index 6e3c5d4f69..41740dbd92 100644 --- a/boards.cfg +++ b/boards.cfg @@ -284,12 +284,24 @@ tx53-1232 arm armv7 tx53 karo m tx6q-1010 arm armv7 tx6 karo mx6 tx6:MX6Q tx6q-1010_mfg arm armv7 tx6 karo mx6 tx6:MX6Q,MFG tx6q-1010_noenv arm armv7 tx6 karo mx6 tx6:MX6Q,ENV_IS_NOWHERE -tx6q-1020 arm armv7 tx6 karo mx6 tx6:MX6Q,TX6_V2,ENV_IS_IN_MMC -tx6q-1020_noenv arm armv7 tx6 karo mx6 tx6:MX6Q,TX6_V2,ENV_IS_NOWHERE -tx6q-1020_mfg arm armv7 tx6 karo mx6 tx6:MX6Q,TX6_V2,ENV_IS_IN_MMC,MFG +tx6q-1020 arm armv7 tx6 karo mx6 tx6:MX6Q,ENV_IS_IN_MMC,NO_NAND,TX6_REV=0x2 +tx6q-1020_mfg arm armv7 tx6 karo mx6 tx6:MX6Q,ENV_IS_IN_MMC,NO_NAND,MFG,TX6_REV=0x2 +tx6q-1020_noenv arm armv7 tx6 karo mx6 tx6:MX6Q,ENV_IS_NOWHERE,NO_NAND,TX6_REV=0x2 +tx6q-1030 arm armv7 tx6 karo mx6 tx6:MX6Q,TX6_REV=0x3 +tx6q-1030_mfg arm armv7 tx6 karo mx6 tx6:MX6Q,MFG,TX6_REV=0x3 +tx6q-1030_noenv arm armv7 tx6 karo mx6 tx6:MX6Q,ENV_IS_NOWHERE,TX6_REV=0x3 tx6q-1110 arm armv7 tx6 karo mx6 tx6:MX6Q,SYS_LVDS_IF tx6q-1110_mfg arm armv7 tx6 karo mx6 tx6:MX6Q,MFG,SYS_LVDS_IF tx6q-1110_noenv arm armv7 tx6 karo mx6 tx6:MX6Q,ENV_IS_NOWHERE,SYS_LVDS_IF +tx6q-1130 arm armv7 tx6 karo mx6 tx6:MX6Q,SYS_LVDS_IF,TX6_REV=0x3 +tx6q-1130_mfg arm armv7 tx6 karo mx6 tx6:MX6Q,MFG,SYS_LVDS_IF,TX6_REV=0x3 +tx6q-1130_noenv arm armv7 tx6 karo mx6 tx6:MX6Q,ENV_IS_NOWHERE,SYS_LVDS_IF,TX6_REV=0x3 +tx6s-8034 arm armv7 tx6 karo mx6 tx6:MX6S,SYS_SDRAM_BUS_WIDTH=16,TX6_REV=0x3 +tx6s-8034_mfg arm armv7 tx6 karo mx6 tx6:MX6S,MFG,SYS_SDRAM_BUS_WIDTH=16,TX6_REV=0x3 +tx6s-8034_noenv arm armv7 tx6 karo mx6 tx6:MX6S,ENV_IS_NOWHERE,SYS_SDRAM_BUS_WIDTH=16,TX6_REV=0x3 +tx6s-8035 arm armv7 tx6 karo mx6 tx6:MX6S,ENV_IS_IN_MMC,MMC_BOOT_SIZE=1024,NO_NAND,SYS_SDRAM_BUS_WIDTH=32,TX6_REV=0x3 +tx6s-8035_mfg arm armv7 tx6 karo mx6 tx6:MX6S,ENV_IS_IN_MMC,MFG,MMC_BOOT_SIZE=1024,NO_NAND,SYS_SDRAM_BUS_WIDTH=32,TX6_REV=0x3 +tx6s-8035_noenv arm armv7 tx6 karo mx6 tx6:MX6S,ENV_IS_NOWHERE,MMC_BOOT_SIZE=1024,NO_NAND,SYS_SDRAM_BUS_WIDTH=32,TX6_REV=0x3 tx6u-8010 arm armv7 tx6 karo mx6 tx6:MX6DL tx6u-8010_mfg arm armv7 tx6 karo mx6 tx6:MX6DL,MFG tx6u-8010_noenv arm armv7 tx6 karo mx6 tx6:MX6DL,ENV_IS_NOWHERE @@ -305,6 +317,12 @@ tx6u-8110_noenv arm armv7 tx6 karo m tx6u-8111 arm armv7 tx6 karo mx6 tx6:MX6DL,SYS_SDRAM_BUS_WIDTH=32,SYS_LVDS_IF tx6u-8111_mfg arm armv7 tx6 karo mx6 tx6:MX6DL,SYS_SDRAM_BUS_WIDTH=32,MFG,SYS_LVDS_IF tx6u-8111_noenv arm armv7 tx6 karo mx6 tx6:MX6DL,SYS_SDRAM_BUS_WIDTH=32,ENV_IS_NOWHERE,SYS_LVDS_IF +tx6u-8030 arm armv7 tx6 karo mx6 tx6:MX6DL,TX6_REV=0x3 +tx6u-8030_mfg arm armv7 tx6 karo mx6 tx6:MX6DL,MFG,TX6_REV=0x3 +tx6u-8030_noenv arm armv7 tx6 karo mx6 tx6:MX6DL,ENV_IS_NOWHERE,TX6_REV=0x3 +tx6u-8033 arm armv7 tx6 karo mx6 tx6:MX6DL,ENV_IS_IN_MMC,MMC_BOOT_SIZE=1024,NO_NAND,TX6_REV=0x3 +tx6u-8033_mfg arm armv7 tx6 karo mx6 tx6:MX6DL,ENV_IS_IN_MMC,MFG,MMC_BOOT_SIZE=1024,NO_NAND,TX6_REV=0x3 +tx6u-8033_noenv arm armv7 tx6 karo mx6 tx6:MX6DL,ENV_IS_NOWHERE,MMC_BOOT_SIZE=1024,NO_NAND,TX6_REV=0x3 mx6qarm2 arm armv7 mx6qarm2 freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg diff --git a/include/configs/tx6.h b/include/configs/tx6.h index 0d34a9a703..adf859eec2 100644 --- a/include/configs/tx6.h +++ b/include/configs/tx6.h @@ -14,6 +14,9 @@ /* * Ka-Ro TX6 board - SoC configuration */ +#ifndef CONFIG_TX6_REV +#define CONFIG_TX6_REV 0x1 /* '1' would be converted to 'y' by define2mk.sed */ +#endif #define CONFIG_MX6 #define CONFIG_SYS_MX6_HCLK 24000000 #define CONFIG_SYS_MX6_CLK32 32768 @@ -49,8 +52,7 @@ #else #define PHYS_SDRAM_1_WIDTH 64 #endif -#define PHYS_SDRAM_1_SIZE (SZ_512M * (PHYS_SDRAM_1_WIDTH / 32)) - +#define PHYS_SDRAM_1_SIZE (SZ_512M / 32 * PHYS_SDRAM_1_WIDTH) #ifdef CONFIG_MX6Q #define CONFIG_SYS_SDRAM_CLK 528 #else @@ -65,10 +67,14 @@ * U-Boot general configurations */ #define CONFIG_SYS_LONGHELP -#ifdef CONFIG_MX6Q +#if defined(CONFIG_MX6Q) #define CONFIG_SYS_PROMPT "TX6Q U-Boot > " -#else +#elif defined(CONFIG_MX6DL) #define CONFIG_SYS_PROMPT "TX6DL U-Boot > " +#elif defined(CONFIG_MX6S) +#define CONFIG_SYS_PROMPT "TX6S U-Boot > " +#else +#error Unsupported i.MX6 processor variant #endif #define CONFIG_SYS_CBSIZE 2048 /* Console I/O buffer size */ #define CONFIG_SYS_PBSIZE \ @@ -90,7 +96,7 @@ #ifndef CONFIG_MFG #define CONFIG_OF_LIBFDT #ifdef CONFIG_OF_LIBFDT -#ifndef CONFIG_TX6_V2 +#ifndef CONFIG_NO_NAND #define CONFIG_FDT_FIXUP_PARTITIONS #endif #define CONFIG_OF_BOARD_SETUP @@ -185,7 +191,7 @@ #endif /* CONFIG_ENV_IS_NOWHERE */ #endif /* CONFIG_MFG */ -#ifndef CONFIG_TX6_V2 +#ifndef CONFIG_NO_NAND #define CONFIG_SYS_DEFAULT_BOOT_MODE "nand" #define CONFIG_SYS_BOOT_CMD_NAND \ "bootcmd_nand=set autostart no;run bootargs_ubifs;nboot linux\0" @@ -217,11 +223,12 @@ #include #define CONFIG_CMD_CACHE #define CONFIG_CMD_MMC -#ifndef CONFIG_TX6_V2 +#ifndef CONFIG_NO_NAND #define CONFIG_CMD_NAND #define CONFIG_CMD_MTDPARTS #endif #define CONFIG_CMD_BOOTCE +#define CONFIG_CMD_BOOTZ #define CONFIG_CMD_TIME #define CONFIG_CMD_I2C #define CONFIG_CMD_MEMTEST @@ -274,12 +281,17 @@ #define CONFIG_SYS_I2C_BASE I2C1_BASE_ADDR #define CONFIG_SYS_I2C_MX6_PORT1 #define CONFIG_SYS_I2C_SPEED 400000 -#ifndef CONFIG_TX6_V2 +#if CONFIG_TX6_REV == 0x1 #define CONFIG_SYS_I2C_SLAVE 0x3c #define CONFIG_LTC3676 -#else +#elif CONFIG_TX6_REV == 0x2 #define CONFIG_SYS_I2C_SLAVE 0x32 #define CONFIG_RN5T618 +#elif CONFIG_TX6_REV == 0x3 +#define CONFIG_SYS_I2C_SLAVE 0x33 +#define CONFIG_RN5T567 +#else +#error Unsupported TX6 module revision #endif #endif @@ -295,7 +307,7 @@ /* * NAND flash driver */ -#ifdef CONFIG_CMD_NAND +#ifndef CONFIG_NO_NAND #define CONFIG_MTD_DEVICE #if 0 #define CONFIG_MTD_DEBUG @@ -321,7 +333,7 @@ #define CONFIG_ENV_RANGE (3 * CONFIG_SYS_NAND_BLOCK_SIZE) #else #undef CONFIG_ENV_IS_IN_NAND -#endif /* CONFIG_CMD_NAND */ +#endif /* CONFIG_NO_NAND */ #ifdef CONFIG_ENV_OFFSET_REDUND #define CONFIG_SYS_ENV_PART_STR xstr(CONFIG_SYS_ENV_PART_SIZE) \ @@ -367,7 +379,7 @@ #define CONFIG_ENV_SIZE SZ_4K #endif -#ifndef CONFIG_TX6_V2 +#ifndef CONFIG_NO_NAND #define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \ xstr(CONFIG_SYS_U_BOOT_PART_SIZE) \ "@" xstr(CONFIG_SYS_NAND_U_BOOT_OFFS) \ -- 2.39.2