From 3247b6123a2a20abb831194f33172270092e9b1c Mon Sep 17 00:00:00 2001 From: =?utf8?q?Lothar=20Wa=C3=9Fmann?= Date: Tue, 23 Jun 2015 07:34:51 +0200 Subject: [PATCH] video: atmel_hlcdfb: make pixel clock polarity configurable --- drivers/video/atmel_hlcdfb.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/video/atmel_hlcdfb.c b/drivers/video/atmel_hlcdfb.c index d27928eea4..8e5cc3bd38 100644 --- a/drivers/video/atmel_hlcdfb.c +++ b/drivers/video/atmel_hlcdfb.c @@ -42,11 +42,13 @@ void lcd_ctrl_init(void *lcdbase) unsigned long value; struct lcd_dma_desc *desc; struct atmel_hlcd_regs *regs; + u32 clk_pol; if (!has_lcdc()) return; /* No lcdc */ regs = panel_info.mmio; + clk_pol = panel_info.vl_clk_pol ? LCDC_LCDCFG0_CLKPOL : 0; /* Disable DISP signal */ lcdc_writel(®s->lcdc_lcddis, LCDC_LCDDIS_DISPDIS); @@ -78,8 +80,8 @@ void lcd_ctrl_init(void *lcdbase) | LCDC_LCDCFG0_CGDISHEO | LCDC_LCDCFG0_CGDISOVR1 | LCDC_LCDCFG0_CGDISBASE - | panel_info.vl_clk_pol - | LCDC_LCDCFG0_CLKSEL); + | LCDC_LCDCFG0_CLKSEL + | clk_pol); } else { lcdc_writel(®s->lcdc_lcdcfg0, @@ -88,7 +90,7 @@ void lcd_ctrl_init(void *lcdbase) | LCDC_LCDCFG0_CGDISHEO | LCDC_LCDCFG0_CGDISOVR1 | LCDC_LCDCFG0_CGDISBASE - | panel_info.vl_clk_pol); + | clk_pol); } /* Initialize control register 5 */ -- 2.39.2