From 8ec346e17b5bf6897f038b8ecc3ecd073e097a22 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Lothar=20Wa=C3=9Fmann?= Date: Wed, 21 Aug 2013 16:14:19 +0200 Subject: [PATCH] merged tx6dl-devel into denx master branch --- .gitignore | 1 + Makefile | 11 +- README | 11 + arch/arm/config.mk | 2 +- arch/arm/cpu/arm926ejs/cpu.c | 9 + arch/arm/cpu/arm926ejs/mxs/Makefile | 4 +- arch/arm/cpu/arm926ejs/mxs/mxs.c | 45 +- arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 13 +- arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 56 +- arch/arm/cpu/arm926ejs/mxs/spl_power_init.c | 386 +- arch/arm/cpu/arm926ejs/mxs/timer.c | 122 +- arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd | 12 +- arch/arm/cpu/armv7/am33xx/Makefile | 1 + arch/arm/cpu/armv7/am33xx/board.c | 54 + arch/arm/cpu/armv7/am33xx/clock_am33xx.c | 450 +- arch/arm/cpu/armv7/am33xx/ddr.c | 15 +- arch/arm/cpu/armv7/am33xx/elm.c | 65 +- arch/arm/cpu/armv7/am33xx/mem.c | 5 +- arch/arm/cpu/armv7/am33xx/sys_info.c | 42 +- arch/arm/cpu/armv7/cache_v7.c | 41 +- arch/arm/cpu/armv7/cpu.c | 11 +- arch/arm/cpu/armv7/lowlevel_init.S | 4 + arch/arm/cpu/armv7/mx5/clock.c | 205 +- arch/arm/cpu/armv7/mx5/soc.c | 36 +- arch/arm/cpu/armv7/mx6/asm-offsets.c | 63 + arch/arm/cpu/armv7/mx6/clock.c | 612 +- arch/arm/cpu/armv7/mx6/soc.c | 170 +- arch/arm/cpu/armv7/omap-common/config.mk | 9 - .../arm/cpu/armv7/omap-common/lowlevel_init.S | 8 +- arch/arm/cpu/armv7/omap-common/reset.c | 3 + arch/arm/cpu/armv7/omap-common/timer.c | 106 +- arch/arm/cpu/armv7/start.S | 6 +- arch/arm/dts/am33xx.dtsi | 158 + arch/arm/dts/imx6qdl.dtsi | 800 ++ arch/arm/dts/mx28.dtsi | 872 ++ arch/arm/dts/mx51.dtsi | 476 + arch/arm/dts/mx53.dtsi | 615 + arch/arm/dts/mx6dl.dtsi | 413 + arch/arm/dts/mx6q.dtsi | 428 + arch/arm/imx-common/cpu.c | 9 - arch/arm/imx-common/iomux-v3.c | 22 +- arch/arm/imx-common/timer.c | 3 +- .../include/asm/arch-am33xx/clocks_am33xx.h | 4 + arch/arm/include/asm/arch-am33xx/cpu.h | 45 +- arch/arm/include/asm/arch-am33xx/da8xx-fb.h | 126 + arch/arm/include/asm/arch-am33xx/ddr_defs.h | 5 +- arch/arm/include/asm/arch-am33xx/gpio.h | 2 + .../include/asm/arch-am33xx/mmc_host_def.h | 5 +- arch/arm/include/asm/arch-am33xx/nand.h | 219 + arch/arm/include/asm/arch-exynos/system.h | 6 +- arch/arm/include/asm/arch-mx5/clock.h | 51 +- arch/arm/include/asm/arch-mx5/crm_regs.h | 6 +- arch/arm/include/asm/arch-mx5/imx-regs.h | 94 +- arch/arm/include/asm/arch-mx5/iomux-mx51.h | 123 +- arch/arm/include/asm/arch-mx5/iomux-mx53.h | 4 +- arch/arm/include/asm/arch-mx5/sys_proto.h | 1 + arch/arm/include/asm/arch-mx6/clock.h | 52 + arch/arm/include/asm/arch-mx6/crm_regs.h | 1009 +- arch/arm/include/asm/arch-mx6/imx-regs.h | 573 +- arch/arm/include/asm/arch-mx6/mx6dl_pins.h | 4 +- arch/arm/include/asm/arch-mx6/mx6q_pins.h | 2 +- arch/arm/include/asm/arch-mx6/regs-ocotp.h | 113 + arch/arm/include/asm/arch-mx6/sys_proto.h | 5 +- .../include/asm/arch-mxs/regs-clkctrl-mx28.h | 62 +- arch/arm/include/asm/arch-mxs/regs-digctl.h | 50 +- arch/arm/include/asm/arch-mxs/regs-i2c.h | 28 +- arch/arm/include/asm/arch-mxs/regs-lcdif.h | 88 +- arch/arm/include/asm/arch-mxs/regs-ocotp.h | 86 +- arch/arm/include/asm/arch-mxs/regs-pinctrl.h | 168 +- .../include/asm/arch-mxs/regs-power-mx28.h | 60 +- arch/arm/include/asm/arch-mxs/regs-rtc.h | 44 +- arch/arm/include/asm/arch-mxs/regs-ssp.h | 40 +- arch/arm/include/asm/arch-mxs/regs-timrot.h | 54 +- arch/arm/include/asm/arch-mxs/regs-usbphy.h | 20 +- arch/arm/include/asm/arch-mxs/sys_proto.h | 4 + arch/arm/include/asm/emif.h | 214 +- arch/arm/include/asm/global_data.h | 3 + arch/arm/include/asm/imx-common/iomux-v3.h | 125 +- arch/arm/include/asm/imx-common/regs-apbh.h | 392 +- arch/arm/include/asm/imx-common/regs-bch.h | 46 +- arch/arm/include/asm/imx-common/regs-common.h | 32 +- arch/arm/include/asm/imx-common/regs-gpmi.h | 30 +- arch/arm/include/asm/system.h | 2 +- arch/arm/lib/Makefile | 6 +- arch/arm/lib/cache-cp15.c | 29 +- arch/arm/lib/cache.c | 10 +- arch/arm/lib/crt0.S | 4 +- arch/arm/lib/reset.c | 4 +- board/denx/m28evk/spl_boot.c | 50 + board/freescale/mx6qarm2/mx6qarm2.c | 2 +- board/freescale/mx6qsabreauto/mx6qsabreauto.c | 6 +- board/freescale/mx6qsabrelite/mx6qsabrelite.c | 28 +- board/karo/common/Makefile | 48 + board/karo/common/fdt.c | 539 + board/karo/common/karo.h | 68 + board/karo/common/splashimage.c | 192 + board/karo/dts/tx28.dts | 377 + board/karo/dts/tx48.dts | 117 + board/karo/dts/tx51.dts | 323 + board/karo/dts/tx53.dts | 432 + board/karo/dts/tx6dl.dts | 62 + board/karo/dts/tx6q.dts | 62 + board/karo/tx28/Makefile | 53 + board/karo/tx28/config.mk | 10 + board/karo/tx28/flash.c | 602 + board/karo/tx28/spl_boot.c | 388 + board/karo/tx28/tx28.c | 806 ++ board/karo/tx28/u-boot.bd | 14 + board/karo/tx48/Makefile | 46 + board/karo/tx48/config.mk | 7 + board/karo/tx48/spl.c | 721 + board/karo/tx48/tx48.c | 894 ++ board/karo/tx48/u-boot.lds | 106 + board/karo/tx51/Makefile | 46 + board/karo/tx51/config.mk | 5 + board/karo/tx51/lowlevel_init.S | 177 + board/karo/tx51/tx51.c | 1026 ++ board/karo/tx51/u-boot.lds | 100 + board/karo/tx53/Makefile | 39 + board/karo/tx53/config.mk | 5 + board/karo/tx53/lowlevel_init.S | 586 + board/karo/tx53/tx53.c | 1042 ++ board/karo/tx53/u-boot.lds | 99 + board/karo/tx6/Makefile | 31 + board/karo/tx6/config.mk | 29 + board/karo/tx6/flash.c | 661 + board/karo/tx6/lowlevel_init.S | 955 ++ board/karo/tx6/tx6qdl.c | 1147 ++ board/karo/tx6/u-boot.lds | 100 + board/ti/am335x/board.c | 2 +- boards.cfg | 24 +- common/Makefile | 3 + common/cmd_bootce.c | 1063 ++ common/cmd_nand.c | 47 +- common/env_nand.c | 4 +- common/fdt_support.c | 2 +- common/lcd.c | 151 +- common/main.c | 15 +- common/spl/spl.c | 5 +- common/spl/spl_nand.c | 26 +- common/spl/spl_ymodem.c | 16 +- common/xyzModem.c | 15 +- config.mk | 8 +- disk/part.c | 3 + doc/README.KARO | 39 + doc/README.KARO-FDT | 35 + doc/README.KARO-TX28 | 77 + doc/README.KARO-TX48 | 70 + doc/README.KARO-TX51 | 79 + doc/README.KARO-TX53 | 80 + drivers/dma/apbh_dma.c | 45 +- drivers/gpio/Makefile | 3 + drivers/gpio/am33xx_gpio.c | 106 + drivers/gpio/gpiolib.c | 55 + drivers/mmc/fsl_esdhc.c | 242 +- drivers/mtd/nand/Makefile | 3 + drivers/mtd/nand/am33xx_nand.c | 940 ++ drivers/mtd/nand/mxc_nand.c | 22 +- drivers/mtd/nand/mxs_nand.c | 280 +- drivers/mtd/nand/nand_spl_simple.c | 41 +- drivers/net/cpsw.c | 416 +- drivers/net/fec_mxc.c | 88 +- drivers/net/fec_mxc.h | 2 - drivers/video/Makefile | 2 +- drivers/video/da8xx-fb.c | 423 +- drivers/video/ipu_common.c | 508 +- drivers/video/ipu_disp.c | 144 +- drivers/video/ipu_regs.h | 119 +- drivers/video/mxc_ipuv3_fb.c | 179 +- drivers/watchdog/imx_watchdog.c | 7 +- dts/Makefile | 8 +- include/ahci.h | 8 +- include/asm-generic/gpio.h | 34 + include/common.h | 1 + include/configs/triton320.h | 266 + include/configs/tx28.h | 314 + include/configs/tx48.h | 350 + include/configs/tx51.h | 292 + include/configs/tx53.h | 279 + include/configs/tx6.h | 353 + include/fsl_esdhc.h | 3 +- {drivers/video => include}/ipu.h | 140 +- include/lcd.h | 30 +- include/linux/mtd/bbm.h | 68 +- {drivers/video => include}/mxcfb.h | 0 include/net.h | 5 +- include/netdev.h | 36 + include/spl.h | 2 +- include/wince.h | 449 + lib/Makefile | 1 + net/Makefile | 1 + net/bootme.c | 396 + net/bootp.c | 8 +- net/bootp.h | 1 - net/eth.c | 2 +- net/net.c | 14 +- net/net_rand.h | 2 +- tools/elftosb/COPYING | 28 + tools/elftosb/ReadMe.txt | 45 + tools/elftosb/bdfiles/basic_test_cmd.e | 192 + tools/elftosb/bdfiles/complex.bd | 260 + tools/elftosb/bdfiles/habtest.bd | 36 + tools/elftosb/bdfiles/simple.e | 8 + tools/elftosb/bdfiles/test_cmd.e | 120 + tools/elftosb/common/AESKey.cpp | 78 + tools/elftosb/common/AESKey.h | 144 + tools/elftosb/common/Blob.cpp | 123 + tools/elftosb/common/Blob.h | 70 + tools/elftosb/common/BootImage.h | 54 + tools/elftosb/common/DataSource.cpp | 224 + tools/elftosb/common/DataSource.h | 299 + tools/elftosb/common/DataSourceImager.cpp | 143 + tools/elftosb/common/DataSourceImager.h | 54 + tools/elftosb/common/DataTarget.cpp | 59 + tools/elftosb/common/DataTarget.h | 122 + tools/elftosb/common/ELF.h | 332 + tools/elftosb/common/ELFSourceFile.cpp | 540 + tools/elftosb/common/ELFSourceFile.h | 224 + tools/elftosb/common/EncoreBootImage.cpp | 1372 ++ tools/elftosb/common/EncoreBootImage.h | 967 ++ tools/elftosb/common/EndianUtilities.h | 141 + tools/elftosb/common/EvalContext.cpp | 111 + tools/elftosb/common/EvalContext.h | 99 + tools/elftosb/common/ExcludesListMatcher.cpp | 88 + tools/elftosb/common/ExcludesListMatcher.h | 67 + tools/elftosb/common/GHSSecInfo.cpp | 100 + tools/elftosb/common/GHSSecInfo.h | 72 + tools/elftosb/common/GlobMatcher.cpp | 129 + tools/elftosb/common/GlobMatcher.h | 59 + tools/elftosb/common/HexValues.cpp | 34 + tools/elftosb/common/HexValues.h | 21 + tools/elftosb/common/IVTDataSource.cpp | 113 + tools/elftosb/common/IVTDataSource.h | 296 + tools/elftosb/common/Logging.cpp | 91 + tools/elftosb/common/Logging.h | 226 + tools/elftosb/common/Operation.cpp | 63 + tools/elftosb/common/Operation.h | 168 + tools/elftosb/common/OptionContext.h | 50 + tools/elftosb/common/OptionDictionary.cpp | 170 + tools/elftosb/common/OptionDictionary.h | 107 + tools/elftosb/common/OutputSection.cpp | 9 + tools/elftosb/common/OutputSection.h | 72 + tools/elftosb/common/Random.cpp | 85 + tools/elftosb/common/Random.h | 57 + tools/elftosb/common/RijndaelCBCMAC.cpp | 86 + tools/elftosb/common/RijndaelCBCMAC.h | 62 + tools/elftosb/common/SHA1.cpp | 274 + tools/elftosb/common/SHA1.h | 149 + tools/elftosb/common/SRecordSourceFile.cpp | 176 + tools/elftosb/common/SRecordSourceFile.h | 83 + tools/elftosb/common/SearchPath.cpp | 121 + tools/elftosb/common/SearchPath.h | 58 + tools/elftosb/common/SourceFile.cpp | 178 + tools/elftosb/common/SourceFile.h | 156 + tools/elftosb/common/StELFFile.cpp | 543 + tools/elftosb/common/StELFFile.h | 196 + tools/elftosb/common/StExecutableImage.cpp | 463 + tools/elftosb/common/StExecutableImage.h | 251 + tools/elftosb/common/StSRecordFile.cpp | 235 + tools/elftosb/common/StSRecordFile.h | 119 + tools/elftosb/common/StringMatcher.h | 62 + tools/elftosb/common/Value.cpp | 43 + tools/elftosb/common/Value.h | 138 + tools/elftosb/common/Version.cpp | 143 + tools/elftosb/common/Version.h | 51 + tools/elftosb/common/crc.cpp | 292 + tools/elftosb/common/crc.h | 48 + tools/elftosb/common/format_string.cpp | 79 + tools/elftosb/common/format_string.h | 20 + tools/elftosb/common/int_size.h | 22 + tools/elftosb/common/options.cpp | 1140 ++ tools/elftosb/common/options.h | 488 + tools/elftosb/common/rijndael.cpp | 1604 +++ tools/elftosb/common/rijndael.h | 159 + tools/elftosb/common/smart_ptr.h | 232 + tools/elftosb/common/stdafx.cpp | 8 + tools/elftosb/common/stdafx.h | 83 + tools/elftosb/elftosb.ccscc | 7 + tools/elftosb/elftosb.xcodeproj/creed.mode1 | 1527 +++ tools/elftosb/elftosb.xcodeproj/creed.mode1v3 | 1569 +++ tools/elftosb/elftosb.xcodeproj/creed.pbxuser | 4452 ++++++ .../elftosb/elftosb.xcodeproj/project.pbxproj | 943 ++ tools/elftosb/elftosb2/BootImageGenerator.cpp | 80 + tools/elftosb/elftosb2/BootImageGenerator.h | 69 + .../elftosb/elftosb2/ConversionController.cpp | 1428 ++ tools/elftosb/elftosb2/ConversionController.h | 153 + tools/elftosb/elftosb2/Doxyfile | 250 + tools/elftosb/elftosb2/ElftosbAST.cpp | 1352 ++ tools/elftosb/elftosb2/ElftosbAST.h | 1227 ++ tools/elftosb/elftosb2/ElftosbErrors.h | 29 + tools/elftosb/elftosb2/ElftosbLexer.cpp | 149 + tools/elftosb/elftosb2/ElftosbLexer.h | 97 + .../elftosb2/EncoreBootImageGenerator.cpp | 297 + .../elftosb2/EncoreBootImageGenerator.h | 57 + tools/elftosb/elftosb2/FlexLexer.h | 208 + tools/elftosb/elftosb2/elftosb.cpp | 700 + tools/elftosb/elftosb2/elftosb2.vcproj | 585 + tools/elftosb/elftosb2/elftosb_lexer.cpp | 2241 +++ tools/elftosb/elftosb2/elftosb_lexer.l | 299 + tools/elftosb/elftosb2/elftosb_parser.tab.cpp | 2955 ++++ tools/elftosb/elftosb2/elftosb_parser.tab.hpp | 152 + tools/elftosb/elftosb2/elftosb_parser.y | 978 ++ tools/elftosb/encryptgpk/encryptgpk.cpp | 442 + tools/elftosb/encryptgpk/encryptgpk.vcproj | 349 + tools/elftosb/keygen/Doxyfile | 250 + tools/elftosb/keygen/keygen.cpp | 346 + tools/elftosb/keygen/keygen.vcproj | 478 + tools/elftosb/makefile | 32 + tools/elftosb/makefile.rules | 178 + tools/elftosb/sbtool/Doxyfile | 250 + .../elftosb/sbtool/EncoreBootImageReader.cpp | 370 + tools/elftosb/sbtool/EncoreBootImageReader.h | 117 + tools/elftosb/sbtool/sbtool.cpp | 626 + tools/elftosb/sbtool/sbtool.vcproj | 495 + tools/elftosb/stdafx.h | 66 + tools/elftosb/test_elftosb.bat | 12 + tools/elftosb/test_elftosb.sh | 26 + tools/elftosb/test_files/hello_NOR_arm | Bin 0 -> 2444 bytes tools/elftosb/test_files/hello_NOR_arm.map | 38 + tools/elftosb/test_files/hello_NOR_mixed | Bin 0 -> 2496 bytes tools/elftosb/test_files/hello_NOR_mixed.map | 39 + tools/elftosb/test_files/hello_NOR_thumb | Bin 0 -> 2348 bytes tools/elftosb/test_files/hello_NOR_thumb.map | 38 + tools/elftosb/test_files/hostlink | Bin 0 -> 1292292 bytes tools/elftosb/test_files/player_linfix.elf | Bin 0 -> 1909984 bytes tools/elftosb/test_files/plugin_complex | Bin 0 -> 2884 bytes tools/elftosb/test_files/plugin_hello | Bin 0 -> 2068 bytes tools/elftosb/test_files/redboot_gcc.srec | 3397 +++++ tools/elftosb/test_files/rom_nand_ldr_profile | Bin 0 -> 38496 bytes tools/elftosb/test_files/sd_player_gcc | Bin 0 -> 1451135 bytes tools/elftosb/test_files/sd_player_gcc.srec | 11250 ++++++++++++++++ tools/elftosb/test_files/test0.key | 1 + tools/elftosb/winsupport/unistd.h | 0 tools/gen_eth_addr.c | 2 +- tools/logos/karo.bmp | Bin 0 -> 15414 bytes 335 files changed, 83594 insertions(+), 3573 deletions(-) create mode 100644 arch/arm/cpu/armv7/mx6/asm-offsets.c delete mode 100644 arch/arm/cpu/armv7/omap-common/config.mk create mode 100644 arch/arm/dts/am33xx.dtsi create mode 100644 arch/arm/dts/imx6qdl.dtsi create mode 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tools/elftosb/test_files/player_linfix.elf create mode 100644 tools/elftosb/test_files/plugin_complex create mode 100644 tools/elftosb/test_files/plugin_hello create mode 100644 tools/elftosb/test_files/redboot_gcc.srec create mode 100644 tools/elftosb/test_files/rom_nand_ldr_profile create mode 100644 tools/elftosb/test_files/sd_player_gcc create mode 100644 tools/elftosb/test_files/sd_player_gcc.srec create mode 100644 tools/elftosb/test_files/test0.key create mode 100644 tools/elftosb/winsupport/unistd.h create mode 100644 tools/logos/karo.bmp diff --git a/.gitignore b/.gitignore index 43e957ac0b..7b59233ebd 100644 --- a/.gitignore +++ b/.gitignore @@ -69,6 +69,7 @@ patches-* # quilt's files patches series +.pc # gdb files .gdb_history diff --git a/Makefile b/Makefile index d545d306fd..b82feebefa 100644 --- a/Makefile +++ b/Makefile @@ -14,8 +14,6 @@ U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL).$(SUBLEVEL)$(EXTRAVERSION) else U_BOOT_VERSION = $(VERSION).$(PATCHLEVEL)$(EXTRAVERSION) endif -TIMESTAMP_FILE = $(obj)include/generated/timestamp_autogenerated.h -VERSION_FILE = $(obj)include/generated/version_autogenerated.h HOSTARCH := $(shell uname -m | \ sed -e s/i.86/x86/ \ @@ -92,7 +90,7 @@ export CHECKSRC ifneq ($(BUILD_DIR),) saved-output := $(BUILD_DIR) -# Attempt to create a output directory. +# Attempt to create an output directory. $(shell [ -d ${BUILD_DIR} ] || mkdir -p ${BUILD_DIR}) # Verify if it was successful. @@ -127,6 +125,9 @@ src := endif export obj src +TIMESTAMP_FILE = $(obj)include/generated/timestamp_autogenerated.h +VERSION_FILE = $(obj)include/generated/version_autogenerated.h + # Make sure CDPATH settings don't interfere unexport CDPATH @@ -508,7 +509,7 @@ $(obj)u-boot.ais: $(obj)spl/u-boot-spl.bin $(obj)u-boot.img $(obj)u-boot.ais -$(obj)u-boot.sb: $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin +$(obj)u-boot.sb: $(obj)u-boot $(obj)spl/u-boot-spl.bin elftosb $(MAKE) -C $(SRCTREE)/$(CPUDIR)/$(SOC)/ $(OBJTREE)/u-boot.sb # On x600 (SPEAr600) U-Boot is appended to U-Boot SPL. @@ -609,6 +610,8 @@ $(obj)spl/u-boot-spl.bin: $(SUBDIR_TOOLS) depend updater: $(MAKE) -C tools/updater all +elftosb: + $(MAKE) -C $(SUBDIR_TOOLS)/elftosb all # Explicitly make _depend in subdirs containing multiple targets to prevent # parallel sub-makes creating .depend files simultaneously. diff --git a/README b/README index a5c3e8dcf7..06c09c5c47 100644 --- a/README +++ b/README @@ -1804,6 +1804,17 @@ CBFS (Coreboot Filesystem) support 4th and following BOOTP requests: delay 0 ... 8 sec +- BOOTP Random transaction ID: + CONFIG_BOOTP_RANDOM_ID + + The standard algorithm to generate a DHCP/BOOTP transaction ID + by using the MAC address and the current time stamp may not + quite unlikely produce duplicate transaction IDs from different + clients in the same network. This option creates a transaction + ID using the rand() function. Provided that the RNG has been + seeded well, this should guarantee unique transaction IDs + always. + - DHCP Advanced Options: You can fine tune the DHCP functionality by defining CONFIG_BOOTP_* symbols: diff --git a/arch/arm/config.mk b/arch/arm/config.mk index 540a1192c2..f9908e5ae6 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -39,7 +39,7 @@ ifneq ($(CONFIG_SPL_BUILD),y) ALL-$(CONFIG_SYS_THUMB_BUILD) += checkthumb endif -# Try if EABI is supported, else fall back to old API, +# Try if EABI is supported, else fall back to old ABI, # i. e. for example: # - with ELDK 4.2 (EABI supported), use: # -mabi=aapcs-linux diff --git a/arch/arm/cpu/arm926ejs/cpu.c b/arch/arm/cpu/arm926ejs/cpu.c index e37e87b68d..174c8d36b2 100644 --- a/arch/arm/cpu/arm926ejs/cpu.c +++ b/arch/arm/cpu/arm926ejs/cpu.c @@ -15,6 +15,7 @@ #include #include +#include #include static void cache_flush(void); @@ -30,6 +31,14 @@ int cleanup_before_linux (void) disable_interrupts (); +#ifdef CONFIG_LCD + { + /* switch off LCD panel */ + lcd_panel_disable(); + /* disable LCD controller */ + lcd_disable(); + } +#endif /* turn off I/D-cache */ icache_disable(); diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile index 3d6689252b..b29227e5fe 100644 --- a/arch/arm/cpu/arm926ejs/mxs/Makefile +++ b/arch/arm/cpu/arm926ejs/mxs/Makefile @@ -31,8 +31,8 @@ ELFTOSB_TARGET-$(CONFIG_MX28) = imx28 $(OBJTREE)/u-boot.bd: $(SRCTREE)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd sed "s@OBJTREE@$(OBJTREE)@g" $^ > $@ -$(OBJTREE)/u-boot.sb: $(OBJTREE)/u-boot.bin $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/u-boot.bd - elftosb -zf $(ELFTOSB_TARGET-y) -c $(OBJTREE)/u-boot.bd -o $(OBJTREE)/u-boot.sb +$(OBJTREE)/u-boot.sb: $(OBJTREE)/u-boot $(OBJTREE)/spl/u-boot-spl $(OBJTREE)/u-boot.bd + $(TOPDIR)/tools/elftosb/bld/linux/elftosb -V -zf $(ELFTOSB_TARGET-y) -c $(OBJTREE)/u-boot.bd -o $(OBJTREE)/u-boot.sb ######################################################################### diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c index 365542fe0b..b00e40485f 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxs.c +++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c @@ -26,6 +26,31 @@ DECLARE_GLOBAL_DATA_PTR; /* Lowlevel init isn't used on i.MX28, so just have a dummy here */ inline void lowlevel_init(void) {} +#define BOOT_CAUSE_MASK (RTC_PERSISTENT0_EXTERNAL_RESET | \ + RTC_PERSISTENT0_ALARM_WAKE | \ + RTC_PERSISTENT0_THERMAL_RESET) + +static int wait_rtc_stat(u32 mask) +{ + int timeout = 5000; + u32 val; + struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE; + u32 old_val = readl(&rtc_regs->hw_rtc_stat); + + debug("stat=%x\n", old_val); + + while ((val = readl(&rtc_regs->hw_rtc_stat)) & mask) { + if (val != old_val) { + old_val = val; + debug("stat: %x -> %x\n", old_val, val); + } + udelay(1); + if (timeout-- < 0) + break; + } + return !!(readl(&rtc_regs->hw_rtc_stat) & mask); +} + void reset_cpu(ulong ignored) __attribute__((noreturn)); void reset_cpu(ulong ignored) @@ -34,6 +59,7 @@ void reset_cpu(ulong ignored) (struct mxs_rtc_regs *)MXS_RTC_BASE; struct mxs_lcdif_regs *lcdif_regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE; + u32 reg; /* * Shut down the LCD controller as it interferes with BootROM boot mode @@ -41,7 +67,13 @@ void reset_cpu(ulong ignored) */ writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr); - /* Wait 1 uS before doing the actual watchdog reset */ + reg = readl(&rtc_regs->hw_rtc_persistent0); + if (reg & BOOT_CAUSE_MASK) { + writel(reg & ~BOOT_CAUSE_MASK, &rtc_regs->hw_rtc_persistent0); + wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0); + } + + /* Wait 1 mS before doing the actual watchdog reset */ writel(1, &rtc_regs->hw_rtc_watchdog); writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set); @@ -96,6 +128,7 @@ int arch_misc_init(void) } #endif +#ifdef CONFIG_ARCH_CPU_INIT int arch_cpu_init(void) { struct mxs_clkctrl_regs *clkctrl_regs = @@ -129,6 +162,7 @@ int arch_cpu_init(void) return 0; } +#endif #if defined(CONFIG_DISPLAY_CPUINFO) static const char *get_cpu_type(void) @@ -223,13 +257,16 @@ int cpu_eth_init(bd_t *bis) udelay(10); + /* + * Enable pad output; must be done BEFORE enabling PLL + * according to i.MX28 Ref. Manual Rev. 1, 2010 p. 883 + */ + setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN); + /* Gate on ENET PLL */ writel(CLKCTRL_PLL2CTRL0_CLKGATE, &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr); - /* Enable pad output */ - setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN); - return 0; } #endif diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c index 0392afd9be..74bc009dc5 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c @@ -22,15 +22,18 @@ * takes a few seconds to roll. The boot doesn't take that long, so to keep the * code simple, it doesn't take rolling into consideration. */ +/* + * There's nothing to be taken into consideration for the rollover. + * Two's complement arithmetic used correctly does all that's needed + * automagically. + */ void early_delay(int delay) { struct mxs_digctl_regs *digctl_regs = (struct mxs_digctl_regs *)MXS_DIGCTL_BASE; + u32 start = readl(&digctl_regs->hw_digctl_microseconds); - uint32_t st = readl(&digctl_regs->hw_digctl_microseconds); - st += delay; - while (st > readl(&digctl_regs->hw_digctl_microseconds)) - ; + while (readl(&digctl_regs->hw_digctl_microseconds) - start < delay); } #define MUX_CONFIG_BOOTMODE_PAD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) @@ -120,7 +123,7 @@ void mxs_common_spl_init(const iomux_cfg_t *iomux_setup, mxs_power_wait_pswitch(); } -/* Support aparatus */ +/* Support apparatus */ inline void board_init_f(unsigned long bootflag) { for (;;) diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c index 3baf4ddefc..0dda76030b 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c @@ -158,18 +158,17 @@ static void mxs_mem_init_clock(void) writeb(CLKCTRL_FRAC_CLKGATE, &clkctrl_regs->hw_clkctrl_frac0_clr[CLKCTRL_FRAC0_EMI]); - early_delay(11000); /* Set EMI clock divider for EMI clock to 411 / 2 = 205MHz */ writel((2 << CLKCTRL_EMI_DIV_EMI_OFFSET) | (1 << CLKCTRL_EMI_DIV_XTAL_OFFSET), &clkctrl_regs->hw_clkctrl_emi); + while (readl(&clkctrl_regs->hw_clkctrl_emi) & CLKCTRL_EMI_BUSY_REF_EMI) + ; /* Unbypass EMI */ writel(CLKCTRL_CLKSEQ_BYPASS_EMI, &clkctrl_regs->hw_clkctrl_clkseq_clr); - - early_delay(10000); } static void mxs_mem_setup_cpu_and_hbus(void) @@ -187,51 +186,56 @@ static void mxs_mem_setup_cpu_and_hbus(void) &clkctrl_regs->hw_clkctrl_clkseq_set); /* HBUS = 151MHz */ - writel(CLKCTRL_HBUS_DIV_MASK, &clkctrl_regs->hw_clkctrl_hbus_set); - writel(((~3) << CLKCTRL_HBUS_DIV_OFFSET) & CLKCTRL_HBUS_DIV_MASK, - &clkctrl_regs->hw_clkctrl_hbus_clr); - - early_delay(10000); + clrsetbits_le32(&clkctrl_regs->hw_clkctrl_hbus, + CLKCTRL_HBUS_DIV_MASK, + 3 << CLKCTRL_HBUS_DIV_OFFSET); + while (readl(&clkctrl_regs->hw_clkctrl_hbus) & CLKCTRL_HBUS_ASM_BUSY) + ; /* CPU clock divider = 1 */ clrsetbits_le32(&clkctrl_regs->hw_clkctrl_cpu, - CLKCTRL_CPU_DIV_CPU_MASK, 1); + CLKCTRL_CPU_DIV_CPU_MASK, + 1 << CLKCTRL_CPU_DIV_CPU_OFFSET); + while (readl(&clkctrl_regs->hw_clkctrl_cpu) & CLKCTRL_CPU_BUSY_REF_CPU) + ; /* Disable CPU bypass */ writel(CLKCTRL_CLKSEQ_BYPASS_CPU, &clkctrl_regs->hw_clkctrl_clkseq_clr); - - early_delay(15000); } -static void mxs_mem_setup_vdda(void) -{ - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; +#define MEM_ABORT_FUNC - writel((0xc << POWER_VDDACTRL_TRG_OFFSET) | - (0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) | - POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW, - &power_regs->hw_power_vddactrl); +#ifdef MEM_ABORT_FUNC +static void data_abort_memdetect_handler(void) +{ + asm volatile("subs pc, lr, #4"); } +#endif uint32_t mxs_mem_get_size(void) { uint32_t sz, da; uint32_t *vt = (uint32_t *)0x20; - /* The following is "subs pc, r14, #4", used as return from DABT. */ - const uint32_t data_abort_memdetect_handler = 0xe25ef004; /* Replace the DABT handler. */ da = vt[4]; - vt[4] = data_abort_memdetect_handler; - - sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); +#ifdef MEM_ABORT_FUNC + vt[4] = (uint32_t)data_abort_memdetect_handler; +#else + vt[4] = (uint32_t)&&data_abort_memdetect_handler; +#endif + sz = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE * 2); /* Restore the old DABT handler. */ vt[4] = da; return sz; + +#ifndef MEM_ABORT_FUNC +data_abort_memdetect_handler: + asm volatile("subs pc, lr, #4"); +#endif } #ifdef CONFIG_MX23 @@ -317,15 +321,11 @@ void mxs_mem_init(void) mxs_mem_init_clock(); - mxs_mem_setup_vdda(); - #if defined(CONFIG_MX23) mx23_mem_init(); #elif defined(CONFIG_MX28) mx28_mem_init(); #endif - early_delay(10000); - mxs_mem_setup_cpu_and_hbus(); } diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index e3b6cd95f9..ff4ff13dd9 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -14,6 +14,66 @@ #include "mxs_init.h" +#ifdef CONFIG_SYS_SPL_VDDD_VAL +#define VDDD_VAL CONFIG_SYS_SPL_VDDD_VAL +#else +#define VDDD_VAL 1350 +#endif +#ifdef CONFIG_SYS_SPL_VDDIO_VAL +#define VDDIO_VAL CONFIG_SYS_SPL_VDDIO_VAL +#else +#define VDDIO_VAL 3300 +#endif +#ifdef CONFIG_SYS_SPL_VDDA_VAL +#define VDDA_VAL CONFIG_SYS_SPL_VDDA_VAL +#else +#define VDDA_VAL 1800 +#endif +#ifdef CONFIG_SYS_SPL_VDDMEM_VAL +#define VDDMEM_VAL CONFIG_SYS_SPL_VDDMEM_VAL +#else +#define VDDMEM_VAL 1700 +#endif + +#ifdef CONFIG_SYS_SPL_VDDD_BO_VAL +#define VDDD_BO_VAL CONFIG_SYS_SPL_VDDD_BO_VAL +#else +#define VDDD_BO_VAL 150 +#endif +#ifdef CONFIG_SYS_SPL_VDDIO_BO_VAL +#define VDDIO_BO_VAL CONFIG_SYS_SPL_VDDIO_BO_VAL +#else +#define VDDIO_BO_VAL 150 +#endif +#ifdef CONFIG_SYS_SPL_VDDA_BO_VAL +#define VDDA_BO_VAL CONFIG_SYS_SPL_VDDA_BO_VAL +#else +#define VDDA_BO_VAL 175 +#endif +#ifdef CONFIG_SYS_SPL_VDDMEM_BO_VAL +#define VDDMEM_BO_VAL CONFIG_SYS_SPL_VDDMEM_BO_VAL +#else +#define VDDMEM_BO_VAL 25 +#endif + +#ifdef CONFIG_SYS_SPL_BATT_BO_LEVEL +#if CONFIG_SYS_SPL_BATT_BO_LEVEL < 2400 || CONFIG_SYS_SPL_BATT_BO_LEVEL > 3640 +#error CONFIG_SYS_SPL_BATT_BO_LEVEL out of range +#endif +#define BATT_BO_VAL (((CONFIG_SYS_SPL_BATT_BO_LEVEL) - 2400) / 40) +#else +/* Brownout default at 3V */ +#define BATT_BO_VAL ((3000 - 2400) / 40) +#endif + +#ifdef CONFIG_SYS_SPL_FIXED_BATT_SUPPLY +static const int fixed_batt_supply = 1; +#else +static const int fixed_batt_supply; +#endif + +static struct mxs_power_regs *power_regs = (void *)MXS_POWER_BASE; + static void mxs_power_clock2xtal(void) { struct mxs_clkctrl_regs *clkctrl_regs = @@ -36,44 +96,49 @@ static void mxs_power_clock2pll(void) CLKCTRL_CLKSEQ_BYPASS_CPU); } -static void mxs_power_clear_auto_restart(void) +static int mxs_power_wait_rtc_stat(u32 mask) { - struct mxs_rtc_regs *rtc_regs = - (struct mxs_rtc_regs *)MXS_RTC_BASE; + int timeout = 5000; /* 3 ms according to i.MX28 Ref. Manual */ + u32 val; + struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE; - writel(RTC_CTRL_SFTRST, &rtc_regs->hw_rtc_ctrl_clr); - while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_SFTRST) - ; + while ((val = readl(&rtc_regs->hw_rtc_stat)) & mask) { + early_delay(1); + if (timeout-- < 0) + break; + } + return !!(readl(&rtc_regs->hw_rtc_stat) & mask); +} - writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr); - while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE) - ; +static int mxs_power_set_auto_restart(int on) +{ + struct mxs_rtc_regs *rtc_regs = (void *)MXS_RTC_BASE; /* * Due to the hardware design bug of mx28 EVK-A * we need to set the AUTO_RESTART bit. */ - if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART) - return; + if (mxs_power_wait_rtc_stat(RTC_STAT_STALE_REGS_PERSISTENT0)) + return 1; - while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK) - ; + if ((!(readl(&rtc_regs->hw_rtc_persistent0) & + RTC_PERSISTENT0_AUTO_RESTART) ^ !on) == 0) + return 0; - setbits_le32(&rtc_regs->hw_rtc_persistent0, - RTC_PERSISTENT0_AUTO_RESTART); - writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set); - writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr); - while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK) - ; - while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK) - ; + if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0)) + return 1; + + clrsetbits_le32(&rtc_regs->hw_rtc_persistent0, + !on * RTC_PERSISTENT0_AUTO_RESTART, + !!on * RTC_PERSISTENT0_AUTO_RESTART); + if (mxs_power_wait_rtc_stat(RTC_STAT_NEW_REGS_PERSISTENT0)) + return 1; + + return 0; } static void mxs_power_set_linreg(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - /* Set linear regulator 25mV below switching converter */ clrsetbits_le32(&power_regs->hw_power_vdddctrl, POWER_VDDDCTRL_LINREG_OFFSET_MASK, @@ -90,9 +155,8 @@ static void mxs_power_set_linreg(void) static int mxs_get_batt_volt(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t volt = readl(&power_regs->hw_power_battmonitor); + volt &= POWER_BATTMONITOR_BATT_VAL_MASK; volt >>= POWER_BATTMONITOR_BATT_VAL_OFFSET; volt *= 8; @@ -106,8 +170,6 @@ static int mxs_is_batt_ready(void) static int mxs_is_batt_good(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t volt = mxs_get_batt_volt(); if ((volt >= 2400) && (volt <= 4300)) @@ -146,9 +208,6 @@ static int mxs_is_batt_good(void) static void mxs_power_setup_5v_detect(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - /* Start 5V detection */ clrsetbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_VBUSVALID_TRSH_MASK, @@ -158,9 +217,6 @@ static void mxs_power_setup_5v_detect(void) static void mxs_src_power_init(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - /* Improve efficieny and reduce transient ripple */ writel(POWER_LOOPCTRL_TOGGLE_DIF | POWER_LOOPCTRL_EN_CM_HYST | POWER_LOOPCTRL_EN_DF_HYST, &power_regs->hw_power_loopctrl_set); @@ -169,8 +225,14 @@ static void mxs_src_power_init(void) POWER_DCLIMITS_POSLIMIT_BUCK_MASK, 0x30 << POWER_DCLIMITS_POSLIMIT_BUCK_OFFSET); - setbits_le32(&power_regs->hw_power_battmonitor, + if (!fixed_batt_supply) { + /* FIXME: This requires the LRADC to be set up! */ + setbits_le32(&power_regs->hw_power_battmonitor, POWER_BATTMONITOR_EN_BATADJ); + } else { + clrbits_le32(&power_regs->hw_power_battmonitor, + POWER_BATTMONITOR_EN_BATADJ); + } /* Increase the RCSCALE level for quick DCDC response to dynamic load */ clrsetbits_le32(&power_regs->hw_power_loopctrl, @@ -181,17 +243,16 @@ static void mxs_src_power_init(void) clrsetbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_HALFFETS, POWER_MINPWR_DOUBLE_FETS); - /* 5V to battery handoff ... FIXME */ - setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); - early_delay(30); - clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); + if (!fixed_batt_supply) { + /* 5V to battery handoff ... FIXME */ + setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); + early_delay(30); + clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); + } } static void mxs_power_init_4p2_params(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - /* Setup 4P2 parameters */ clrsetbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_CMPTRIP_MASK | POWER_DCDC4P2_TRG_MASK, @@ -213,8 +274,6 @@ static void mxs_power_init_4p2_params(void) static void mxs_enable_4p2_dcdc_input(int xfer) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo; uint32_t prev_5v_brnout, prev_5v_droop; @@ -309,8 +368,6 @@ static void mxs_enable_4p2_dcdc_input(int xfer) static void mxs_power_init_4p2_regulator(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t tmp, tmp2; setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2); @@ -393,9 +450,6 @@ static void mxs_power_init_4p2_regulator(void) static void mxs_power_init_dcdc_4p2_source(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - if (!(readl(&power_regs->hw_power_dcdc4p2) & POWER_DCDC4P2_ENABLE_DCDC)) { hang(); @@ -415,8 +469,6 @@ static void mxs_power_init_dcdc_4p2_source(void) static void mxs_power_enable_4p2(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t vdddctrl, vddactrl, vddioctrl; uint32_t tmp; @@ -474,9 +526,6 @@ static void mxs_power_enable_4p2(void) static void mxs_boot_valid_5v(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - /* * Use VBUSVALID level instead of VDD5V_GT_VDDIO level to trigger a 5V * disconnect event. FIXME @@ -497,8 +546,6 @@ static void mxs_boot_valid_5v(void) static void mxs_powerdown(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset); writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF, &power_regs->hw_power_reset); @@ -506,9 +553,6 @@ static void mxs_powerdown(void) static void mxs_batt_boot(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT); clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC); @@ -550,8 +594,6 @@ static void mxs_batt_boot(void) static void mxs_handle_5v_conflict(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t tmp; setbits_le32(&power_regs->hw_power_vddioctrl, @@ -586,9 +628,6 @@ static void mxs_handle_5v_conflict(void) static void mxs_5v_boot(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - /* * NOTE: In original IMX-Bootlets, this also checks for VBUSVALID, * but their implementation always returns 1 so we omit it here. @@ -607,15 +646,42 @@ static void mxs_5v_boot(void) mxs_handle_5v_conflict(); } -static void mxs_init_batt_bo(void) +static void mxs_fixed_batt_boot(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; + writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr); + + setbits_le32(&power_regs->hw_power_5vctrl, + POWER_5VCTRL_PWDN_5VBRNOUT | + POWER_5VCTRL_ENABLE_DCDC | + POWER_5VCTRL_ILIMIT_EQ_ZERO | + POWER_5VCTRL_PWDN_5VBRNOUT | + POWER_5VCTRL_PWD_CHARGE_4P2_MASK); + + writel(POWER_CHARGE_PWD_BATTCHRG, &power_regs->hw_power_charge_set); + + clrbits_le32(&power_regs->hw_power_vdddctrl, + POWER_VDDDCTRL_DISABLE_FET | + POWER_VDDDCTRL_ENABLE_LINREG | + POWER_VDDDCTRL_DISABLE_STEPPING); + + clrbits_le32(&power_regs->hw_power_vddactrl, + POWER_VDDACTRL_DISABLE_FET | POWER_VDDACTRL_ENABLE_LINREG | + POWER_VDDACTRL_DISABLE_STEPPING); - /* Brownout at 3V */ + clrbits_le32(&power_regs->hw_power_vddioctrl, + POWER_VDDIOCTRL_DISABLE_FET | + POWER_VDDIOCTRL_DISABLE_STEPPING); + + /* Stop 5V detection */ + writel(POWER_5VCTRL_PWRUP_VBUS_CMPS, + &power_regs->hw_power_5vctrl_clr); +} + +static void mxs_init_batt_bo(void) +{ clrsetbits_le32(&power_regs->hw_power_battmonitor, POWER_BATTMONITOR_BRWNOUT_LVL_MASK, - 15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET); + BATT_BO_VAL << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET); writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr); writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr); @@ -623,9 +689,6 @@ static void mxs_init_batt_bo(void) static void mxs_switch_vddd_to_dcdc_source(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - clrsetbits_le32(&power_regs->hw_power_vdddctrl, POWER_VDDDCTRL_LINREG_OFFSET_MASK, POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW); @@ -637,33 +700,32 @@ static void mxs_switch_vddd_to_dcdc_source(void) static void mxs_power_configure_power_source(void) { - int batt_ready, batt_good; - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; struct mxs_lradc_regs *lradc_regs = (struct mxs_lradc_regs *)MXS_LRADC_BASE; mxs_src_power_init(); - if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { - batt_ready = mxs_is_batt_ready(); - if (batt_ready) { - /* 5V source detected, good battery detected. */ - mxs_batt_boot(); - } else { - batt_good = mxs_is_batt_good(); - if (!batt_good) { - /* 5V source detected, bad battery detected. */ - writel(LRADC_CONVERSION_AUTOMATIC, - &lradc_regs->hw_lradc_conversion_clr); - clrbits_le32(&power_regs->hw_power_battmonitor, - POWER_BATTMONITOR_BATT_VAL_MASK); + if (!fixed_batt_supply) { + if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { + if (mxs_is_batt_ready()) { + /* 5V source detected, good battery detected. */ + mxs_batt_boot(); + } else { + if (!mxs_is_batt_good()) { + /* 5V source detected, bad battery detected. */ + writel(LRADC_CONVERSION_AUTOMATIC, + &lradc_regs->hw_lradc_conversion_clr); + clrbits_le32(&power_regs->hw_power_battmonitor, + POWER_BATTMONITOR_BATT_VAL_MASK); + } + mxs_5v_boot(); } - mxs_5v_boot(); + } else { + /* 5V not detected, booting from battery. */ + mxs_batt_boot(); } } else { - /* 5V not detected, booting from battery. */ - mxs_batt_boot(); + mxs_fixed_batt_boot(); } mxs_power_clock2pll(); @@ -681,9 +743,6 @@ static void mxs_power_configure_power_source(void) static void mxs_enable_output_rail_protection(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ | POWER_CTRL_VDDIO_BO_IRQ, &power_regs->hw_power_ctrl_clr); @@ -699,11 +758,12 @@ static void mxs_enable_output_rail_protection(void) static int mxs_get_vddio_power_source_off(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t tmp; - if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { + if ((readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) && + !(readl(&power_regs->hw_power_5vctrl) & + POWER_5VCTRL_ILIMIT_EQ_ZERO)) { + tmp = readl(&power_regs->hw_power_vddioctrl); if (tmp & POWER_VDDIOCTRL_DISABLE_FET) { if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) == @@ -722,13 +782,10 @@ static int mxs_get_vddio_power_source_off(void) } return 0; - } static int mxs_get_vddd_power_source_off(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t tmp; tmp = readl(&power_regs->hw_power_vdddctrl); @@ -756,10 +813,40 @@ static int mxs_get_vddd_power_source_off(void) return 0; } +static int mxs_get_vdda_power_source_off(void) +{ + uint32_t tmp; + + tmp = readl(&power_regs->hw_power_vddactrl); + if (tmp & POWER_VDDACTRL_DISABLE_FET) { + if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) == + POWER_VDDACTRL_LINREG_OFFSET_0STEPS) { + return 1; + } + } + + if (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO) { + if (!(readl(&power_regs->hw_power_5vctrl) & + POWER_5VCTRL_ENABLE_DCDC)) { + return 1; + } + } + + if (!(tmp & POWER_VDDACTRL_ENABLE_LINREG)) { + if ((tmp & POWER_VDDACTRL_LINREG_OFFSET_MASK) == + POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW) { + return 1; + } + } + + return 0; +} + struct mxs_vddx_cfg { uint32_t *reg; uint8_t step_mV; uint16_t lowest_mV; + uint16_t highest_mV; int (*powered_by_linreg)(void); uint32_t trg_mask; uint32_t bo_irq; @@ -768,15 +855,17 @@ struct mxs_vddx_cfg { uint32_t bo_offset_offset; }; +#define POWER_REG(n) &((struct mxs_power_regs *)MXS_POWER_BASE)->n + static const struct mxs_vddx_cfg mxs_vddio_cfg = { - .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)-> - hw_power_vddioctrl), + .reg = POWER_REG(hw_power_vddioctrl), #if defined(CONFIG_MX23) .step_mV = 25, #else .step_mV = 50, #endif .lowest_mV = 2800, + .highest_mV = 3600, .powered_by_linreg = mxs_get_vddio_power_source_off, .trg_mask = POWER_VDDIOCTRL_TRG_MASK, .bo_irq = POWER_CTRL_VDDIO_BO_IRQ, @@ -786,10 +875,10 @@ static const struct mxs_vddx_cfg mxs_vddio_cfg = { }; static const struct mxs_vddx_cfg mxs_vddd_cfg = { - .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)-> - hw_power_vdddctrl), + .reg = POWER_REG(hw_power_vdddctrl), .step_mV = 25, .lowest_mV = 800, + .highest_mV = 1575, .powered_by_linreg = mxs_get_vddd_power_source_off, .trg_mask = POWER_VDDDCTRL_TRG_MASK, .bo_irq = POWER_CTRL_VDDD_BO_IRQ, @@ -798,12 +887,25 @@ static const struct mxs_vddx_cfg mxs_vddd_cfg = { .bo_offset_offset = POWER_VDDDCTRL_BO_OFFSET_OFFSET, }; +static const struct mxs_vddx_cfg mxs_vdda_cfg = { + .reg = POWER_REG(hw_power_vddactrl), + .step_mV = 50, + .lowest_mV = 2800, + .highest_mV = 3600, + .powered_by_linreg = mxs_get_vdda_power_source_off, + .trg_mask = POWER_VDDACTRL_TRG_MASK, + .bo_irq = POWER_CTRL_VDDA_BO_IRQ, + .bo_enirq = POWER_CTRL_ENIRQ_VDDA_BO, + .bo_offset_mask = POWER_VDDACTRL_BO_OFFSET_MASK, + .bo_offset_offset = POWER_VDDACTRL_BO_OFFSET_OFFSET, +}; + #ifdef CONFIG_MX23 static const struct mxs_vddx_cfg mxs_vddmem_cfg = { - .reg = &(((struct mxs_power_regs *)MXS_POWER_BASE)-> - hw_power_vddmemctrl), + .reg = POWER_REG(hw_power_vddmemctrl), .step_mV = 50, - .lowest_mV = 1700, + .lowest_mV = 1500, + .highest_mV = 1700, .powered_by_linreg = NULL, .trg_mask = POWER_VDDMEMCTRL_TRG_MASK, .bo_irq = 0, @@ -816,11 +918,14 @@ static const struct mxs_vddx_cfg mxs_vddmem_cfg = { static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg, uint32_t new_target, uint32_t new_brownout) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t cur_target, diff, bo_int = 0; - uint32_t powered_by_linreg = 0; - int adjust_up, tmp; + int powered_by_linreg = 0; + int adjust_up; + + if (new_target < cfg->lowest_mV) + new_target = cfg->lowest_mV; + if (new_target > cfg->highest_mV) + new_target = cfg->highest_mV; new_brownout = DIV_ROUND(new_target - new_brownout, cfg->step_mV); @@ -858,13 +963,12 @@ static void mxs_power_set_vddx(const struct mxs_vddx_cfg *cfg, if (powered_by_linreg || (readl(&power_regs->hw_power_sts) & - POWER_STS_VDD5V_GT_VDDIO)) + POWER_STS_VDD5V_GT_VDDIO)) { early_delay(500); - else { - for (;;) { - tmp = readl(&power_regs->hw_power_sts); - if (tmp & POWER_STS_DC_OK) - break; + } else { + while (!(readl(&power_regs->hw_power_sts) & + POWER_STS_DC_OK)) { + } } @@ -896,51 +1000,61 @@ static void mxs_setup_batt_detect(void) static void mxs_ungate_power(void) { #ifdef CONFIG_MX23 - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - writel(POWER_CTRL_CLKGATE, &power_regs->hw_power_ctrl_clr); #endif } +#ifdef CONFIG_CONFIG_MACH_MX28EVK +#define auto_restart 1 +#else +#define auto_restart 0 +#endif + void mxs_power_init(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - mxs_ungate_power(); mxs_power_clock2xtal(); - mxs_power_clear_auto_restart(); + if (mxs_power_set_auto_restart(auto_restart)) { + serial_puts("Inconsistent value in RTC_PERSISTENT0 register; power-on-reset required\n"); + } mxs_power_set_linreg(); - mxs_power_setup_5v_detect(); - mxs_setup_batt_detect(); + if (!fixed_batt_supply) { + mxs_power_setup_5v_detect(); + mxs_setup_batt_detect(); + } mxs_power_configure_power_source(); mxs_enable_output_rail_protection(); - mxs_power_set_vddx(&mxs_vddio_cfg, 3300, 3150); - mxs_power_set_vddx(&mxs_vddd_cfg, 1500, 1000); + mxs_power_set_vddx(&mxs_vddio_cfg, VDDIO_VAL, VDDIO_BO_VAL); + mxs_power_set_vddx(&mxs_vddd_cfg, VDDD_VAL, VDDD_BO_VAL); + mxs_power_set_vddx(&mxs_vdda_cfg, VDDA_VAL, VDDA_BO_VAL); #ifdef CONFIG_MX23 - mxs_power_set_vddx(&mxs_vddmem_cfg, 2500, 1700); + mxs_power_set_vddx(&mxs_vddmem_cfg, VDDMEM_VAL, VDDMEM_BO_VAL); + + setbits_le32(&power_regs->hw_power_vddmemctrl, + POWER_VDDMEMCTRL_ENABLE_LINREG); + early_delay(500); + clrbits_le32(&power_regs->hw_power_vddmemctrl, + POWER_VDDMEMCTRL_ENABLE_ILIMIT); +#else + clrbits_le32(&power_regs->hw_power_vddmemctrl, + POWER_VDDMEMCTRL_ENABLE_LINREG); #endif writel(POWER_CTRL_VDDD_BO_IRQ | POWER_CTRL_VDDA_BO_IRQ | POWER_CTRL_VDDIO_BO_IRQ | POWER_CTRL_VDD5V_DROOP_IRQ | POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ | POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); - - writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set); - - early_delay(1000); + if (!fixed_batt_supply) + writel(POWER_5VCTRL_PWDN_5VBRNOUT, + &power_regs->hw_power_5vctrl_set); } #ifdef CONFIG_SPL_MXS_PSWITCH_WAIT void mxs_power_wait_pswitch(void) { - struct mxs_power_regs *power_regs = - (struct mxs_power_regs *)MXS_POWER_BASE; - while (!(readl(&power_regs->hw_power_sts) & POWER_STS_PSWITCH_MASK)) ; } diff --git a/arch/arm/cpu/arm926ejs/mxs/timer.c b/arch/arm/cpu/arm926ejs/mxs/timer.c index 9b49ef4a91..20693e2a94 100644 --- a/arch/arm/cpu/arm926ejs/mxs/timer.c +++ b/arch/arm/cpu/arm926ejs/mxs/timer.c @@ -24,8 +24,20 @@ DECLARE_GLOBAL_DATA_PTR; -#define timestamp (gd->arch.tbl) -#define lastdec (gd->arch.lastinc) +/* Enable this to verify that the code can correctly + * handle the timer rollover + */ +/* #define DEBUG_TIMER_WRAP */ + +#ifdef DEBUG_TIMER_WRAP +/* + * Let the timer wrap 15 seconds after start to catch misbehaving + * timer related code early + */ +#define TIMER_START (-time_to_tick(15 * CONFIG_SYS_HZ)) +#else +#define TIMER_START 0UL +#endif /* * This driver uses 1kHz clock source. @@ -42,12 +54,6 @@ static inline unsigned long time_to_tick(unsigned long time) return time * (MXS_INCREMENTER_HZ / CONFIG_SYS_HZ); } -/* Calculate how many ticks happen in "us" microseconds */ -static inline unsigned long us_to_tick(unsigned long us) -{ - return (us * MXS_INCREMENTER_HZ) / 1000000; -} - int timer_init(void) { struct mxs_timrot_regs *timrot_regs = @@ -75,38 +81,60 @@ int timer_init(void) writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0); #endif +#ifndef DEBUG_TIMER_WRAP + /* Set fixed_count to maximum value */ + writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0); +#else + /* Set fixed_count so that the counter will wrap after 20 seconds */ + writel(20 * MXS_INCREMENTER_HZ, + &timrot_regs->hw_timrot_fixed_count0); + gd->arch.lastinc = TIMER_LOAD_VAL - 20 * MXS_INCREMENTER_HZ; +#endif +#ifdef DEBUG_TIMER_WRAP + /* Make the usec counter roll over 30 seconds after startup */ + writel(-30000000, MXS_HW_DIGCTL_MICROSECONDS); +#endif + writel(TIMROT_TIMCTRLn_UPDATE, + &timrot_regs->hw_timrot_timctrl0_clr); +#ifdef DEBUG_TIMER_WRAP + /* Set fixed_count to maximal value for subsequent loads */ + writel(TIMER_LOAD_VAL, &timrot_regs->hw_timrot_fixed_count0); +#endif + gd->arch.timer_rate_hz = MXS_INCREMENTER_HZ; + gd->arch.tbl = TIMER_START; + gd->arch.tbu = 0; return 0; } +/* Note: This function works correctly for TIMER_LOAD_VAL == 0xffffffff! + * The rollover is handled automagically due to the properties of + * two's complement arithmetic. + * For any other value of TIMER_LOAD_VAL the calculations would have + * to be done modulus(TIMER_LOAD_VAL + 1). + */ unsigned long long get_ticks(void) { struct mxs_timrot_regs *timrot_regs = (struct mxs_timrot_regs *)MXS_TIMROT_BASE; - uint32_t now; - - /* Current tick value */ + unsigned long now; #if defined(CONFIG_MX23) /* Upper bits are the valid ones. */ now = readl(&timrot_regs->hw_timrot_timcount0) >> TIMROT_RUNNING_COUNTn_RUNNING_COUNT_OFFSET; -#elif defined(CONFIG_MX28) - now = readl(&timrot_regs->hw_timrot_running_count0); +#else + /* The timer is counting down, so subtract the register value from + * the counter period length (implicitly 2^32) to get an incrementing + * timestamp + */ + now = -readl(&timrot_regs->hw_timrot_running_count0); #endif + ulong inc = now - gd->arch.lastinc; - if (lastdec >= now) { - /* - * normal mode (non roll) - * move stamp forward with absolut diff ticks - */ - timestamp += (lastdec - now); - } else { - /* we have rollover of decrementer */ - timestamp += (TIMER_LOAD_VAL - now) + lastdec; - - } - lastdec = now; - - return timestamp; + if (gd->arch.tbl + inc < gd->arch.tbl) + gd->arch.tbu++; + gd->arch.tbl += inc; + gd->arch.lastinc = now; + return ((unsigned long long)gd->arch.tbu << 32) | gd->arch.tbl; } ulong get_timer_masked(void) @@ -116,7 +144,8 @@ ulong get_timer_masked(void) ulong get_timer(ulong base) { - return get_timer_masked() - base; + /* NOTE: time_to_tick(base) is required to correctly handle rollover! */ + return tick_to_time(get_ticks() - time_to_tick(base)); } /* We use the HW_DIGCTL_MICROSECONDS register for sub-millisecond timer. */ @@ -124,36 +153,19 @@ ulong get_timer(ulong base) void __udelay(unsigned long usec) { - uint32_t old, new, incr; - uint32_t counter = 0; - - old = readl(MXS_HW_DIGCTL_MICROSECONDS); - - while (counter < usec) { - new = readl(MXS_HW_DIGCTL_MICROSECONDS); - - /* Check if the timer wrapped. */ - if (new < old) { - incr = 0xffffffff - old; - incr += new; - } else { - incr = new - old; - } - - /* - * Check if we are close to the maximum time and the counter - * would wrap if incremented. If that's the case, break out - * from the loop as the requested delay time passed. + uint32_t start = readl(MXS_HW_DIGCTL_MICROSECONDS); + + while (readl(MXS_HW_DIGCTL_MICROSECONDS) - start <= usec) + /* use '<=' to guarantee a delay of _at least_ + * the given number of microseconds. + * No need for fancy rollover checks + * Two's complement arithmetic applied correctly + * does everything that's needed automagically! */ - if (counter + incr < counter) - break; - - counter += incr; - old = new; - } + ; } ulong get_tbclk(void) { - return MXS_INCREMENTER_HZ; + return gd->arch.timer_rate_hz; } diff --git a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd index a5fa6483a9..ee9cc75cd1 100644 --- a/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd +++ b/arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd @@ -1,14 +1,14 @@ sources { - u_boot_spl="OBJTREE/spl/u-boot-spl.bin"; - u_boot="OBJTREE/u-boot.bin"; + u_boot_spl="OBJTREE/spl/u-boot-spl"; + u_boot="OBJTREE/u-boot"; } section (0) { - load u_boot_spl > 0x0000; - load ivt (entry = 0x0014) > 0x8000; + load u_boot_spl; + load ivt (entry = u_boot_spl:reset) > 0x8000; hab call 0x8000; - load u_boot > 0x40000100; - load ivt (entry = 0x40000100) > 0x8000; + load u_boot; + load ivt (entry = u_boot:reset) > 0x8000; hab call 0x8000; } diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile index dbd1ec3c05..2db1d410c9 100644 --- a/arch/arm/cpu/armv7/am33xx/Makefile +++ b/arch/arm/cpu/armv7/am33xx/Makefile @@ -17,6 +17,7 @@ COBJS += emif4.o COBJS += board.o COBJS += mux.o COBJS-$(CONFIG_NAND_OMAP_GPMC) += elm.o +COBJS-$(CONFIG_NAND_AM33XX) += elm.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS) $(COBJS-y) $(SOBJS)) diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index 07ab91c3ee..5b3cefb62f 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -43,6 +43,60 @@ static const struct gpio_bank gpio_bank_am33xx[4] = { const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx; +#ifdef CONFIG_HW_WATCHDOG +void hw_watchdog_reset(void) +{ + struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; + static int trg __attribute__((section(".data"))); + + switch (trg) { + case 0: + case 1: + if (readl(&wdtimer->wdtwwps) & (1 << 4)) + return; + writel(trg ? 0x5555 : 0xaaaa, &wdtimer->wdtwspr); + break; + case 2: + if (readl(&wdtimer->wdtwwps) & (1 << 2)) + return; + /* 10 sec timeout */ + writel(-32768 * 10, &wdtimer->wdtwldr); + + if (readl(&wdtimer->wdtwwps) & (1 << 0)) + return; + /* prescaler = 1 */ + writel(0, &wdtimer->wdtwclr); + break; + + case 3: + case 4: + /* enable watchdog */ + if (readl(&wdtimer->wdtwwps) & (1 << 4)) + return; + writel((trg & 1) ? 0xBBBB : 0x4444, &wdtimer->wdtwspr); + break; + + default: + /* retrigger watchdog */ + if (readl(&wdtimer->wdtwwps) & (1 << 3)) + return; + + writel(trg, &wdtimer->wdtwtgr); + trg ^= 0x2; + return; + } + trg++; +} +#endif + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif + #if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD) int cpu_mmc_init(bd_t *bis) { diff --git a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c index fb3fb43dcc..5e37af34d6 100644 --- a/arch/arm/cpu/armv7/am33xx/clock_am33xx.c +++ b/arch/arm/cpu/armv7/am33xx/clock_am33xx.c @@ -28,11 +28,10 @@ #define CLK_DIV_MASK 0x1f #define CLK_DIV2_MASK 0x7f #define CLK_SEL_SHIFT 0x8 +#define CLK_MODE_MASK 0x7 #define CLK_MODE_SEL 0x7 -#define CLK_MODE_MASK 0xfffffff8 -#define CLK_DIV_SEL 0xFFFFFFE0 -#define CPGMAC0_IDLE 0x30000 -#define DPLL_CLKDCOLDO_GATE_CTRL 0x300 +#define DPLL_CLKDCOLDO_GATE_CTRL 0x300 + #define OSC (V_OSCK/1000000) @@ -68,36 +67,35 @@ const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP; const struct cm_dpll *cmdpll = (struct cm_dpll *)CM_DPLL; const struct cm_rtc *cmrtc = (struct cm_rtc *)CM_RTC; +#ifdef CONFIG_SPL_BUILD +#define enable_clk(reg, val) __enable_clk(#reg, ®, val) + +static void __enable_clk(const char *name, const void *reg, u32 mask) +{ + unsigned long timeout = 10000000; + + writel(mask, reg); + while (readl(reg) != mask) + /* poor man's timeout, since timers not initialized */ + if (timeout-- == 0) + /* no error message, since console not yet available */ + break; +} + static void enable_interface_clocks(void) { /* Enable all the Interconnect Modules */ - writel(PRCM_MOD_EN, &cmper->l3clkctrl); - while (readl(&cmper->l3clkctrl) != PRCM_MOD_EN) - ; - - writel(PRCM_MOD_EN, &cmper->l4lsclkctrl); - while (readl(&cmper->l4lsclkctrl) != PRCM_MOD_EN) - ; - - writel(PRCM_MOD_EN, &cmper->l4fwclkctrl); - while (readl(&cmper->l4fwclkctrl) != PRCM_MOD_EN) - ; - - writel(PRCM_MOD_EN, &cmwkup->wkl4wkclkctrl); - while (readl(&cmwkup->wkl4wkclkctrl) != PRCM_MOD_EN) - ; - - writel(PRCM_MOD_EN, &cmper->l3instrclkctrl); - while (readl(&cmper->l3instrclkctrl) != PRCM_MOD_EN) - ; - - writel(PRCM_MOD_EN, &cmper->l4hsclkctrl); - while (readl(&cmper->l4hsclkctrl) != PRCM_MOD_EN) - ; - - writel(PRCM_MOD_EN, &cmwkup->wkgpio0clkctrl); - while (readl(&cmwkup->wkgpio0clkctrl) != PRCM_MOD_EN) - ; + enable_clk(cmper->l3clkctrl, PRCM_MOD_EN); + enable_clk(cmper->l4lsclkctrl, PRCM_MOD_EN); + enable_clk(cmper->l4fwclkctrl, PRCM_MOD_EN); + enable_clk(cmwkup->wkl4wkclkctrl, PRCM_MOD_EN); + enable_clk(cmper->l3instrclkctrl, PRCM_MOD_EN); + enable_clk(cmper->l4hsclkctrl, PRCM_MOD_EN); +#ifdef CONFIG_HW_WATCHDOG + enable_clk(cmwkup->wdtimer1ctrl, PRCM_MOD_EN); +#endif + /* GPIO0 */ + enable_clk(cmwkup->wkgpio0clkctrl, PRCM_MOD_EN); } /* @@ -120,72 +118,50 @@ static void power_domain_wkup_transition(void) static void enable_per_clocks(void) { /* Enable the control module though RBL would have done it*/ - writel(PRCM_MOD_EN, &cmwkup->wkctrlclkctrl); - while (readl(&cmwkup->wkctrlclkctrl) != PRCM_MOD_EN) - ; - - /* Enable the module clock */ - writel(PRCM_MOD_EN, &cmper->timer2clkctrl); - while (readl(&cmper->timer2clkctrl) != PRCM_MOD_EN) - ; - + enable_clk(cmwkup->wkctrlclkctrl, PRCM_MOD_EN); + /* Enable the timer2 clock */ + enable_clk(cmper->timer2clkctrl, PRCM_MOD_EN); /* Select the Master osc 24 MHZ as Timer2 clock source */ writel(0x1, &cmdpll->clktimer2clk); +#ifdef CONFIG_SYS_NS16550_COM1 /* UART0 */ - writel(PRCM_MOD_EN, &cmwkup->wkup_uart0ctrl); - while (readl(&cmwkup->wkup_uart0ctrl) != PRCM_MOD_EN) - ; - - /* UART1 */ -#ifdef CONFIG_SERIAL2 - writel(PRCM_MOD_EN, &cmper->uart1clkctrl); - while (readl(&cmper->uart1clkctrl) != PRCM_MOD_EN) - ; -#endif /* CONFIG_SERIAL2 */ - - /* UART2 */ -#ifdef CONFIG_SERIAL3 - writel(PRCM_MOD_EN, &cmper->uart2clkctrl); - while (readl(&cmper->uart2clkctrl) != PRCM_MOD_EN) - ; -#endif /* CONFIG_SERIAL3 */ - - /* UART3 */ -#ifdef CONFIG_SERIAL4 - writel(PRCM_MOD_EN, &cmper->uart3clkctrl); - while (readl(&cmper->uart3clkctrl) != PRCM_MOD_EN) - ; -#endif /* CONFIG_SERIAL4 */ - - /* UART4 */ -#ifdef CONFIG_SERIAL5 - writel(PRCM_MOD_EN, &cmper->uart4clkctrl); - while (readl(&cmper->uart4clkctrl) != PRCM_MOD_EN) - ; -#endif /* CONFIG_SERIAL5 */ - - /* UART5 */ -#ifdef CONFIG_SERIAL6 - writel(PRCM_MOD_EN, &cmper->uart5clkctrl); - while (readl(&cmper->uart5clkctrl) != PRCM_MOD_EN) - ; -#endif /* CONFIG_SERIAL6 */ - + enable_clk(cmwkup->wkup_uart0ctrl, PRCM_MOD_EN); +#endif +#ifdef CONFIG_SYS_NS16550_COM2 + enable_clk(cmper->uart1clkctrl, PRCM_MOD_EN); +#endif +#ifdef CONFIG_SYS_NS16550_COM3 + enable_clk(cmper->uart2clkctrl, PRCM_MOD_EN); +#endif +#ifdef CONFIG_SYS_NS16550_COM4 + enable_clk(cmper->uart3clkctrl, PRCM_MOD_EN); +#endif +#ifdef CONFIG_SYS_NS16550_COM5 + enable_clk(cmper->uart4clkctrl, PRCM_MOD_EN); +#endif +#ifdef CONFIG_SYS_NS16550_COM6 + enable_clk(cmper->uart5clkctrl, PRCM_MOD_EN); +#endif /* GPMC */ - writel(PRCM_MOD_EN, &cmper->gpmcclkctrl); - while (readl(&cmper->gpmcclkctrl) != PRCM_MOD_EN) - ; + enable_clk(cmper->gpmcclkctrl, PRCM_MOD_EN); /* ELM */ - writel(PRCM_MOD_EN, &cmper->elmclkctrl); - while (readl(&cmper->elmclkctrl) != PRCM_MOD_EN) - ; + enable_clk(cmper->elmclkctrl, PRCM_MOD_EN); - /* MMC0*/ - writel(PRCM_MOD_EN, &cmper->mmc0clkctrl); - while (readl(&cmper->mmc0clkctrl) != PRCM_MOD_EN) - ; + /* Ethernet */ + enable_clk(cmper->cpswclkstctrl, PRCM_MOD_EN); + enable_clk(cmper->cpgmac0clkctrl, PRCM_MOD_EN); + + /* MMC */ +#ifndef CONFIG_OMAP_MMC_DEV_0 + enable_clk(cmper->mmc0clkctrl, PRCM_MOD_EN); +#endif +#ifdef CONFIG_OMAP_MMC_DEV_1 + enable_clk(cmper->mmc1clkctrl, PRCM_MOD_EN); +#endif + /* LCD */ + enable_clk(cmper->lcdclkctrl, PRCM_MOD_EN); /* MMC1 */ writel(PRCM_MOD_EN, &cmper->mmc1clkctrl); @@ -193,50 +169,26 @@ static void enable_per_clocks(void) ; /* i2c0 */ - writel(PRCM_MOD_EN, &cmwkup->wkup_i2c0ctrl); - while (readl(&cmwkup->wkup_i2c0ctrl) != PRCM_MOD_EN) - ; + enable_clk(cmwkup->wkup_i2c0ctrl, PRCM_MOD_EN); - /* gpio1 module */ - writel(PRCM_MOD_EN, &cmper->gpio1clkctrl); - while (readl(&cmper->gpio1clkctrl) != PRCM_MOD_EN) - ; - - /* gpio2 module */ - writel(PRCM_MOD_EN, &cmper->gpio2clkctrl); - while (readl(&cmper->gpio2clkctrl) != PRCM_MOD_EN) - ; - - /* gpio3 module */ - writel(PRCM_MOD_EN, &cmper->gpio3clkctrl); - while (readl(&cmper->gpio3clkctrl) != PRCM_MOD_EN) - ; + /* GPIO1-3 */ + enable_clk(cmper->gpio1clkctrl, PRCM_MOD_EN); + enable_clk(cmper->gpio2clkctrl, PRCM_MOD_EN); + enable_clk(cmper->gpio3clkctrl, PRCM_MOD_EN); /* i2c1 */ - writel(PRCM_MOD_EN, &cmper->i2c1clkctrl); - while (readl(&cmper->i2c1clkctrl) != PRCM_MOD_EN) - ; - - /* Ethernet */ - writel(PRCM_MOD_EN, &cmper->cpgmac0clkctrl); - while ((readl(&cmper->cpgmac0clkctrl) & CPGMAC0_IDLE) != PRCM_FUNCTL) - ; + enable_clk(cmper->i2c1clkctrl, PRCM_MOD_EN); /* spi0 */ - writel(PRCM_MOD_EN, &cmper->spi0clkctrl); - while (readl(&cmper->spi0clkctrl) != PRCM_MOD_EN) - ; + enable_clk(cmper->spi0clkctrl, PRCM_MOD_EN); - /* RTC */ - writel(PRCM_MOD_EN, &cmrtc->rtcclkctrl); - while (readl(&cmrtc->rtcclkctrl) != PRCM_MOD_EN) - ; + /* rtc */ + enable_clk(cmrtc->rtcclkctrl, PRCM_MOD_EN); - /* MUSB */ - writel(PRCM_MOD_EN, &cmper->usb0clkctrl); - while (readl(&cmper->usb0clkctrl) != PRCM_MOD_EN) - ; + /* usb0 */ + enable_clk(cmper->usb0clkctrl, PRCM_MOD_EN); } +#endif /* CONFIG_SPL_BUILD */ void mpu_pll_config_val(int mpull_m) { @@ -251,27 +203,28 @@ void mpu_pll_config_val(int mpull_m) while (readl(&cmwkup->idlestdpllmpu) != ST_MN_BYPASS) ; - clksel = clksel & (~CLK_SEL_MASK); - clksel = clksel | ((mpull_m << CLK_SEL_SHIFT) | MPUPLL_N); + clksel &= ~CLK_SEL_MASK; + clksel |= (mpull_m << CLK_SEL_SHIFT) | MPUPLL_N; writel(clksel, &cmwkup->clkseldpllmpu); - div_m2 = div_m2 & ~CLK_DIV_MASK; - div_m2 = div_m2 | MPUPLL_M2; + div_m2 &= ~CLK_DIV_MASK; + div_m2 |= MPUPLL_M2; writel(div_m2, &cmwkup->divm2dpllmpu); - clkmode = clkmode | CLK_MODE_SEL; + clkmode &= ~CLK_MODE_MASK; + clkmode |= CLK_MODE_SEL; writel(clkmode, &cmwkup->clkmoddpllmpu); while (readl(&cmwkup->idlestdpllmpu) != ST_DPLL_CLK) ; } -static void mpu_pll_config(void) +void mpu_pll_config(void) { mpu_pll_config_val(CONFIG_SYS_MPUCLK); } -static void core_pll_config(void) +static void core_pll_config_val(int m) { u32 clkmode, clksel, div_m4, div_m5, div_m6; @@ -287,30 +240,36 @@ static void core_pll_config(void) while (readl(&cmwkup->idlestdpllcore) != ST_MN_BYPASS) ; - clksel = clksel & (~CLK_SEL_MASK); - clksel = clksel | ((COREPLL_M << CLK_SEL_SHIFT) | COREPLL_N); + clksel &= ~CLK_SEL_MASK; + clksel |= ((m << CLK_SEL_SHIFT) | COREPLL_N); writel(clksel, &cmwkup->clkseldpllcore); - div_m4 = div_m4 & ~CLK_DIV_MASK; - div_m4 = div_m4 | COREPLL_M4; + div_m4 &= ~CLK_DIV_MASK; + div_m4 |= COREPLL_M4; writel(div_m4, &cmwkup->divm4dpllcore); - div_m5 = div_m5 & ~CLK_DIV_MASK; - div_m5 = div_m5 | COREPLL_M5; + div_m5 &= ~CLK_DIV_MASK; + div_m5 |= COREPLL_M5; writel(div_m5, &cmwkup->divm5dpllcore); - div_m6 = div_m6 & ~CLK_DIV_MASK; - div_m6 = div_m6 | COREPLL_M6; + div_m6 &= ~CLK_DIV_MASK; + div_m6 |= COREPLL_M6; writel(div_m6, &cmwkup->divm6dpllcore); - clkmode = clkmode | CLK_MODE_SEL; + clkmode &= ~CLK_MODE_MASK; + clkmode |= CLK_MODE_SEL; writel(clkmode, &cmwkup->clkmoddpllcore); while (readl(&cmwkup->idlestdpllcore) != ST_DPLL_CLK) ; } -static void per_pll_config(void) +static inline void core_pll_config(void) +{ + core_pll_config_val(COREPLL_M); +} + +static void per_pll_config_val(int m) { u32 clkmode, clksel, div_m2; @@ -324,15 +283,16 @@ static void per_pll_config(void) while (readl(&cmwkup->idlestdpllper) != ST_MN_BYPASS) ; - clksel = clksel & (~CLK_SEL_MASK); - clksel = clksel | ((PERPLL_M << CLK_SEL_SHIFT) | PERPLL_N); + clksel &= ~CLK_SEL_MASK; + clksel |= (m << CLK_SEL_SHIFT) | PERPLL_N; writel(clksel, &cmwkup->clkseldpllper); - div_m2 = div_m2 & ~CLK_DIV2_MASK; - div_m2 = div_m2 | PERPLL_M2; + div_m2 &= ~CLK_DIV2_MASK; + div_m2 |= PERPLL_M2; writel(div_m2, &cmwkup->divm2dpllper); - clkmode = clkmode | CLK_MODE_SEL; + clkmode &= ~CLK_MODE_MASK; + clkmode |= CLK_MODE_SEL; writel(clkmode, &cmwkup->clkmoddpllper); while (readl(&cmwkup->idlestdpllper) != ST_DPLL_CLK) @@ -341,6 +301,46 @@ static void per_pll_config(void) writel(DPLL_CLKDCOLDO_GATE_CTRL, &cmwkup->clkdcoldodpllper); } +static inline void per_pll_config(void) +{ + per_pll_config_val(PERPLL_M); +} + +static void disp_pll_config_val(int m) +{ + u32 clkmode, clksel, div_m2; + + clkmode = readl(&cmwkup->clkmoddplldisp); + clksel = readl(&cmwkup->clkseldplldisp); + div_m2 = readl(&cmwkup->divm2dplldisp); + + /* Set the PLL to bypass Mode */ + writel(PLL_BYPASS_MODE, &cmwkup->clkmoddplldisp); + + while (!(readl(&cmwkup->idlestdplldisp) & ST_MN_BYPASS)) + ; + + clksel &= ~CLK_SEL_MASK; + clksel |= (m << CLK_SEL_SHIFT) | DISPPLL_N; + writel(clksel, &cmwkup->clkseldplldisp); + + div_m2 &= ~CLK_DIV2_MASK; + div_m2 |= DISPPLL_M2; + writel(div_m2, &cmwkup->divm2dplldisp); + + clkmode &= ~CLK_MODE_MASK; + clkmode |= CLK_MODE_SEL; + writel(clkmode, &cmwkup->clkmoddplldisp); + + while (!(readl(&cmwkup->idlestdplldisp) & ST_DPLL_CLK)) + ; +} + +static inline void disp_pll_config(void) +{ + disp_pll_config_val(DISPPLL_M); +} + void ddr_pll_config(unsigned int ddrpll_m) { u32 clkmode, clksel, div_m2; @@ -350,23 +350,24 @@ void ddr_pll_config(unsigned int ddrpll_m) div_m2 = readl(&cmwkup->divm2dpllddr); /* Set the PLL to bypass Mode */ - clkmode = (clkmode & CLK_MODE_MASK) | PLL_BYPASS_MODE; + clkmode &= ~CLK_MODE_MASK; + clkmode |= PLL_BYPASS_MODE; writel(clkmode, &cmwkup->clkmoddpllddr); /* Wait till bypass mode is enabled */ - while ((readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS) - != ST_MN_BYPASS) + while (!(readl(&cmwkup->idlestdpllddr) & ST_MN_BYPASS)) ; - clksel = clksel & (~CLK_SEL_MASK); - clksel = clksel | ((ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N); + clksel &= ~CLK_SEL_MASK; + clksel |= (ddrpll_m << CLK_SEL_SHIFT) | DDRPLL_N; writel(clksel, &cmwkup->clkseldpllddr); - div_m2 = div_m2 & CLK_DIV_SEL; - div_m2 = div_m2 | DDRPLL_M2; + div_m2 &= ~CLK_DIV_MASK; + div_m2 |= DDRPLL_M2; writel(div_m2, &cmwkup->divm2dpllddr); - clkmode = (clkmode & CLK_MODE_MASK) | CLK_MODE_SEL; + clkmode &= ~CLK_MODE_MASK; + clkmode |= CLK_MODE_SEL; writel(clkmode, &cmwkup->clkmoddpllddr); /* Wait till dpll is locked */ @@ -374,6 +375,7 @@ void ddr_pll_config(unsigned int ddrpll_m) ; } +#ifdef CONFIG_SPL_BUILD void enable_emif_clocks(void) { /* Enable the EMIF_FW Functional clock */ @@ -393,6 +395,7 @@ void pll_init() mpu_pll_config(); core_pll_config(); per_pll_config(); + disp_pll_config(); /* Enable the required interconnect clocks */ enable_interface_clocks(); @@ -403,3 +406,140 @@ void pll_init() /* Enable the required peripherals */ enable_per_clocks(); } +#endif + +#define M(mn) (((mn) & CLK_SEL_MASK) >> CLK_SEL_SHIFT) +#define N(mn) ((mn) & CLK_DIV2_MASK) + +unsigned long __clk_get_rate(u32 m_n, u32 div_m2) +{ + unsigned long rate; + + div_m2 &= CLK_DIV_MASK; + debug("M=%u N=%u M2=%u\n", M(m_n), N(m_n), div_m2); + rate = V_OSCK / 1000 * M(m_n) / (N(m_n) + 1) / div_m2; + debug("CLK = %lu.%03luMHz\n", rate / 1000, rate % 1000); + return rate * 1000; +} + +unsigned long lcdc_clk_rate(void) +{ + return clk_get_rate(cmwkup, disp); +} + +unsigned long mpu_clk_rate(void) +{ + return clk_get_rate(cmwkup, mpu); +} + +enum { + CLK_MPU_PLL, + CLK_CORE_PLL, + CLK_PER_PLL, + CLK_DISP_PLL, + CLK_GPMC, +}; + +static struct clk_lookup { + const char *name; + unsigned int index; +} am33xx_clk_lookup[] = { + { "mpu", CLK_MPU_PLL, }, + { "core", CLK_CORE_PLL, }, + { "per", CLK_PER_PLL, }, + { "lcdc", CLK_DISP_PLL, }, + { "gpmc", CLK_GPMC, }, +}; + +#define print_pll(dom, pll) { \ + u32 __pll = clk_get_rate(dom, pll); \ + printf("%-12s %4d.%03d MHz\n", #pll, \ + __pll / 1000000, __pll / 1000 % 1000); \ + } + +#define print_pll2(dom, n, pll) { \ + u32 __m_n = readl(&(dom)->clkseldpll##pll); \ + u32 __div = readl(&(dom)->divm##n##dpll##pll); \ + u32 __pll = __clk_get_rate(__m_n, __div); \ + printf("%-12s %4d.%03d MHz\n", #pll "_m" #n, \ + __pll / 1000000, __pll / 1000 % 1000); \ + } + +static void do_showclocks(void) +{ + print_pll(cmwkup, mpu); + print_pll2(cmwkup, 4, core); + print_pll2(cmwkup, 5, core); + print_pll2(cmwkup, 6, core); + print_pll(cmwkup, ddr); + print_pll(cmwkup, per); + print_pll(cmwkup, disp); +} + +int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, + char *const argv[]) +{ + int i; + unsigned long freq; + unsigned long __attribute__((unused)) ref = ~0UL; + + if (argc < 2) { + do_showclocks(); + return CMD_RET_SUCCESS; + } else if (argc == 2 || argc > 4) { + return CMD_RET_USAGE; + } + + freq = simple_strtoul(argv[2], NULL, 0); + if (freq < 1000) { + printf("Invalid clock frequency %lu\n", freq); + return CMD_RET_FAILURE; + } + if (argc > 3) { + ref = simple_strtoul(argv[3], NULL, 0); + } + for (i = 0; i < ARRAY_SIZE(am33xx_clk_lookup); i++) { + if (strcasecmp(argv[1], am33xx_clk_lookup[i].name) == 0) { + switch (am33xx_clk_lookup[i].index) { + case CLK_MPU_PLL: + mpu_pll_config_val(freq / 1000000); + break; + case CLK_CORE_PLL: + core_pll_config_val(freq / 1000000); + break; + case CLK_PER_PLL: + per_pll_config_val(freq / 1000000); + break; + case CLK_DISP_PLL: + disp_pll_config_val(freq / 1000000); + break; + default: + printf("Cannot change %s clock\n", + am33xx_clk_lookup[i].name); + return CMD_RET_FAILURE; + } + + printf("%s clock set to %lu.%03lu MHz\n", + am33xx_clk_lookup[i].name, + freq / 1000000, freq / 1000 % 1000); + return CMD_RET_SUCCESS; + } + } + if (i == ARRAY_SIZE(am33xx_clk_lookup)) { + printf("clock %s not found; supported clocks are:\n", argv[1]); + for (i = 0; i < ARRAY_SIZE(am33xx_clk_lookup); i++) { + printf("\t%s\n", am33xx_clk_lookup[i].name); + } + } else { + printf("Failed to set clock %s to %s MHz\n", + argv[1], argv[2]); + } + return CMD_RET_FAILURE; +} + +U_BOOT_CMD( + clocks, 4, 0, do_clocks, + "display/set clocks", + " - display clock settings\n" + "clocks - set clock to Hz" +); diff --git a/arch/arm/cpu/armv7/am33xx/ddr.c b/arch/arm/cpu/armv7/am33xx/ddr.c index fa697c74ab..11cbac441c 100644 --- a/arch/arm/cpu/armv7/am33xx/ddr.c +++ b/arch/arm/cpu/armv7/am33xx/ddr.c @@ -17,24 +17,27 @@ */ static struct emif_reg_struct *emif_reg[2] = { (struct emif_reg_struct *)EMIF4_0_CFG_BASE, - (struct emif_reg_struct *)EMIF4_1_CFG_BASE}; + (struct emif_reg_struct *)EMIF4_1_CFG_BASE, +}; /** * Base addresses for DDR PHY cmd/data regs */ static struct ddr_cmd_regs *ddr_cmd_reg[2] = { (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR, - (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2}; + (struct ddr_cmd_regs *)DDR_PHY_CMD_ADDR2, +}; static struct ddr_data_regs *ddr_data_reg[2] = { (struct ddr_data_regs *)DDR_PHY_DATA_ADDR, - (struct ddr_data_regs *)DDR_PHY_DATA_ADDR2}; + (struct ddr_data_regs *)DDR_PHY_DATA_ADDR2, +}; /** * Base address for ddr io control instances */ -static struct ddr_cmdtctrl *ioctrl_reg = { - (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR}; +static struct ddr_cmdtctrl *ioctrl_reg = + (struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR; /** * Configure SDRAM @@ -49,7 +52,7 @@ void config_sdram(const struct emif_regs *regs, int nr) */ writel(0x2800, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->zq_config, &emif_reg[nr]->emif_zq_config); - writel(regs->sdram_config, &cstat->secure_emif_sdram_config); + writel(regs->sdram_config, &cstat->emif_sdram_config); writel(regs->sdram_config, &emif_reg[nr]->emif_sdram_config); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl); writel(regs->ref_ctrl, &emif_reg[nr]->emif_sdram_ref_ctrl_shdw); diff --git a/arch/arm/cpu/armv7/am33xx/elm.c b/arch/arm/cpu/armv7/am33xx/elm.c index 8f1d6afdd3..b0b05f4c85 100644 --- a/arch/arm/cpu/armv7/am33xx/elm.c +++ b/arch/arm/cpu/armv7/am33xx/elm.c @@ -20,9 +20,13 @@ #include #include -#define ELM_DEFAULT_POLY (0) +#define ELM_DEFAULT_POLY 0 -struct elm *elm_cfg; +/* make sure this variable does not end up in bss + * because that would corrupt the relocation section + * that is overlayed with the bss section + */ +static struct elm *elm_cfg __attribute__((section(".data"))); /** * elm_load_syndromes - Load BCH syndromes based on nibble selection @@ -34,58 +38,53 @@ struct elm *elm_cfg; */ static void elm_load_syndromes(u8 *syndrome, u32 nibbles, u8 poly) { - u32 *ptr; u32 val; + struct syndrome *sf = &elm_cfg->syndrome_fragments[poly]; /* reg 0 */ - ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[0]; val = syndrome[0] | (syndrome[1] << 8) | (syndrome[2] << 16) | (syndrome[3] << 24); - writel(val, ptr); + writel(val, &sf->syndrome_fragment_x[0]); + /* reg 1 */ - ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[1]; val = syndrome[4] | (syndrome[5] << 8) | (syndrome[6] << 16) | (syndrome[7] << 24); - writel(val, ptr); + writel(val, &sf->syndrome_fragment_x[1]); /* BCH 8-bit with 26 nibbles (4*8=32) */ if (nibbles > 13) { /* reg 2 */ - ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[2]; val = syndrome[8] | (syndrome[9] << 8) | (syndrome[10] << 16) | (syndrome[11] << 24); - writel(val, ptr); + writel(val, &sf->syndrome_fragment_x[2]); + /* reg 3 */ - ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[3]; - val = syndrome[12] | (syndrome[13] << 8) | - (syndrome[14] << 16) | (syndrome[15] << 24); - writel(val, ptr); + val = syndrome[12] | (syndrome[13] << 8) | (syndrome[14] << 16) | + (syndrome[15] << 24); + writel(val, &sf->syndrome_fragment_x[3]); } /* BCH 16-bit with 52 nibbles (7*8=56) */ if (nibbles > 26) { /* reg 4 */ - ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[4]; - val = syndrome[16] | (syndrome[17] << 8) | - (syndrome[18] << 16) | (syndrome[19] << 24); - writel(val, ptr); + val = syndrome[16] | (syndrome[17] << 8) | (syndrome[18] << 16) | + (syndrome[19] << 24); + writel(val, &sf->syndrome_fragment_x[4]); /* reg 5 */ - ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[5]; - val = syndrome[20] | (syndrome[21] << 8) | - (syndrome[22] << 16) | (syndrome[23] << 24); - writel(val, ptr); + val = syndrome[20] | (syndrome[21] << 8) | (syndrome[22] << 16) | + (syndrome[23] << 24); + writel(val, &sf->syndrome_fragment_x[5]); /* reg 6 */ - ptr = &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]; - val = syndrome[24] | (syndrome[25] << 8) | - (syndrome[26] << 16) | (syndrome[27] << 24); - writel(val, ptr); + val = syndrome[24] | (syndrome[25] << 8) | (syndrome[26] << 16) | + (syndrome[27] << 24); + writel(val, &sf->syndrome_fragment_x[6]); } } /** - * elm_check_errors - Check for BCH errors and return error locations + * elm_check_error - Check for BCH errors and return error locations * @syndrome: BCH syndrome * @nibbles: * @error_count: Returns number of errrors in the syndrome @@ -107,14 +106,13 @@ int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count, /* start processing */ writel((readl(&elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]) | ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID), - &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]); + &elm_cfg->syndrome_fragments[poly].syndrome_fragment_x[6]); /* wait for processing to complete */ - while ((readl(&elm_cfg->irqstatus) & (0x1 << poly)) != 0x1) - ; + while (!(readl(&elm_cfg->irqstatus) & (0x1 << poly))); /* clear status */ - writel((readl(&elm_cfg->irqstatus) | (0x1 << poly)), - &elm_cfg->irqstatus); + writel((readl(&elm_cfg->irqstatus) & ~(0x1 << poly)), + &elm_cfg->irqstatus); /* check if correctable */ location_status = readl(&elm_cfg->error_location[poly].location_status); @@ -123,12 +121,11 @@ int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count, /* get error count */ *error_count = readl(&elm_cfg->error_location[poly].location_status) & - ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK; + ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK; - for (i = 0; i < *error_count; i++) { + for (i = 0; i < *error_count; i++) error_locations[i] = readl(&elm_cfg->error_location[poly].error_location_x[i]); - } return 0; } diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c index f81c9a8ba8..b1a1329f86 100644 --- a/arch/arm/cpu/armv7/am33xx/mem.c +++ b/arch/arm/cpu/armv7/am33xx/mem.c @@ -20,8 +20,6 @@ #include #include -struct gpmc *gpmc_cfg; - #if defined(CONFIG_CMD_NAND) static const u32 gpmc_m_nand[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, @@ -60,8 +58,7 @@ void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, void gpmc_init(void) { /* putting a blanket check on GPMC based on ZeBu for now */ - gpmc_cfg = (struct gpmc *)GPMC_BASE; - + struct gpmc *gpmc_cfg = (struct gpmc *)GPMC_BASE; #ifdef CONFIG_CMD_NAND const u32 *gpmc_config = NULL; u32 base = 0; diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c index 63afaaa328..3f6d180e40 100644 --- a/arch/arm/cpu/armv7/am33xx/sys_info.c +++ b/arch/arm/cpu/armv7/am33xx/sys_info.c @@ -63,7 +63,7 @@ u32 get_board_rev(void) u32 get_device_type(void) { int mode; - mode = readl(&cstat->statusreg) & (DEVICE_MASK); + mode = readl(&cstat->statusreg) & DEVICE_MASK; return mode >>= 8; } @@ -73,17 +73,36 @@ u32 get_device_type(void) u32 get_sysboot_value(void) { int mode; - mode = readl(&cstat->statusreg) & (SYSBOOT_MASK); + mode = readl(&cstat->statusreg) & SYSBOOT_MASK; return mode; } #ifdef CONFIG_DISPLAY_CPUINFO +#define SYSBOOT_FREQ_SHIFT 22 +#define SYSBOOT_FREQ_MASK (3 << SYSBOOT_FREQ_SHIFT) + +static unsigned long bootfreqs[] = { + 19200000, + 24000000, + 25000000, + 26000000, +}; + +static u32 get_sysboot_freq(void) +{ + int mode; + mode = readl(&cstat->statusreg) & SYSBOOT_FREQ_MASK; + return bootfreqs[mode >> SYSBOOT_FREQ_SHIFT]; +} + /** * Print CPU information */ int print_cpuinfo(void) { char *cpu_s, *sec_s; + unsigned long clk; + const struct cm_wkuppll *cmwkup = (struct cm_wkuppll *)CM_WKUP; switch (get_cpu_type()) { case AM335X: @@ -94,7 +113,6 @@ int print_cpuinfo(void) break; default: cpu_s = "Unknown cpu type"; - break; } switch (get_device_type()) { @@ -116,6 +134,24 @@ int print_cpuinfo(void) printf("%s-%s rev %d\n", cpu_s, sec_s, get_cpu_rev()); + clk = get_sysboot_freq(); + printf("OSC clk: %4lu.%03lu MHz\n", + clk / 1000000, clk / 1000 % 1000); + clk = clk_get_rate(cmwkup, mpu); + printf("MPU clk: %4lu.%03lu MHz\n", + clk / 1000000, clk / 1000 % 1000); + clk = clk_get_rate(cmwkup, ddr); + printf("DDR clk: %4lu.%03lu MHz\n", + clk / 1000000, clk / 1000 % 1000); + clk = clk_get_rate(cmwkup, per); + printf("PER clk: %4lu.%03lu MHz\n", + clk / 1000000, clk / 1000 % 1000); +#ifdef CONFIG_LCD + clk = clk_get_rate(cmwkup, disp); + printf("LCD clk: %4lu.%03lu MHz\n", + clk / 1000000, clk / 1000 % 1000); +#endif + return 0; } #endif /* CONFIG_DISPLAY_CPUINFO */ diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index bc5fc423d6..f7865bc389 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -220,16 +220,18 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op) /* Invalidate TLB */ static void v7_inval_tlb(void) { - /* Invalidate entire unified TLB */ - asm volatile ("mcr p15, 0, %0, c8, c7, 0" : : "r" (0)); - /* Invalidate entire data TLB */ - asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0)); - /* Invalidate entire instruction TLB */ - asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0)); - /* Full system DSB - make sure that the invalidation is complete */ - CP15DSB; - /* Full system ISB - make sure the instruction stream sees it */ - CP15ISB; + asm volatile ( + /* Invalidate entire unified TLB */ + "mcr p15, 0, %0, c8, c7, 0\n" + /* Invalidate entire data TLB */ + "mcr p15, 0, %0, c8, c6, 0\n" + /* Invalidate entire instruction TLB */ + "mcr p15, 0, %0, c8, c5, 0\n" + /* Full system DSB - make sure that the invalidation is complete */ + "mcr p15, 0, %0, c7, c10, 4\n" + /* Full system ISB - make sure the instruction stream sees it */ + "mcr p15, 0, %0, c7, c5, 4\n" + : : "r" (0)); } void invalidate_dcache_all(void) @@ -337,16 +339,15 @@ void invalidate_icache_all(void) * Invalidate all instruction caches to PoU. * Also flushes branch target cache. */ - asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0)); - - /* Invalidate entire branch predictor array */ - asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0)); - - /* Full system DSB - make sure that the invalidation is complete */ - CP15DSB; - - /* ISB - make sure the instruction stream sees it */ - CP15ISB; + asm volatile ( + "mcr p15, 0, %0, c7, c5, 0\n" + /* Invalidate entire branch predictor array */ + "mcr p15, 0, %0, c7, c5, 6\n" + /* Full system DSB - make sure that the invalidation is complete */ + "mcr p15, 0, %0, c7, c10, 4\n" + /* ISB - make sure the instruction stream sees it */ + "mcr p15, 0, %0, c7, c5, 4\n" + : : "r" (0)); } #else void invalidate_icache_all(void) diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c index 01cdb7ee76..a5794c6cdb 100644 --- a/arch/arm/cpu/armv7/cpu.c +++ b/arch/arm/cpu/armv7/cpu.c @@ -17,6 +17,7 @@ #include #include +#include #include #include #include @@ -34,7 +35,15 @@ int cleanup_before_linux(void) */ #ifndef CONFIG_SPL_BUILD disable_interrupts(); -#endif +#ifdef CONFIG_LCD + { + /* switch off LCD panel */ + lcd_panel_disable(); + /* disable LCD controller */ + lcd_disable(); + } +#endif /* CONFIG_LCD */ +#endif /* CONFIG_SPL_BUILD */ /* * Turn off I-cache and invalidate it diff --git a/arch/arm/cpu/armv7/lowlevel_init.S b/arch/arm/cpu/armv7/lowlevel_init.S index 82b2b86520..cf477a978f 100644 --- a/arch/arm/cpu/armv7/lowlevel_init.S +++ b/arch/arm/cpu/armv7/lowlevel_init.S @@ -19,7 +19,11 @@ ENTRY(lowlevel_init) /* * Setup a temporary stack */ +#ifndef CONFIG_SPL_BUILD ldr sp, =CONFIG_SYS_INIT_SP_ADDR +#else + ldr sp, =CONFIG_SPL_STACK +#endif bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ #ifdef CONFIG_SPL_BUILD ldr r8, =gdata diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index fbbb365cb6..21fef9f55d 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -46,9 +46,6 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = { #define EMI_DIV_MAX 8 #define NFC_DIV_MAX 8 -#define MX5_CBCMR 0x00015154 -#define MX5_CBCDR 0x02888945 - struct fixed_pll_mfd { u32 ref_clk_hz; u32 mfd; @@ -73,6 +70,93 @@ struct pll_param { struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; +int clk_enable(struct clk *clk) +{ + int ret = 0; + + if (!clk) + return 0; + if (clk->usecount++ == 0) { + ret = clk->enable(clk); + if (ret) + clk->usecount--; + } + return ret; +} + +void clk_disable(struct clk *clk) +{ + if (!clk) + return; + + if (!(--clk->usecount)) { + if (clk->disable) + clk->disable(clk); + } + if (clk->usecount < 0) { + printf("%s: clk %p underflow\n", __func__, clk); + hang(); + } +} + +int clk_get_usecount(struct clk *clk) +{ + if (clk == NULL) + return 0; + + return clk->usecount; +} + +u32 clk_get_rate(struct clk *clk) +{ + if (!clk) + return 0; + + return clk->rate; +} + +struct clk *clk_get_parent(struct clk *clk) +{ + if (!clk) + return 0; + + return clk->parent; +} + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + if (clk && clk->set_rate) + clk->set_rate(clk, rate); + return clk->rate; +} + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + if (clk == NULL || !clk->round_rate) + return 0; + + return clk->round_rate(clk, rate); +} + +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + debug("Setting parent of clk %p to %p (%p)\n", clk, parent, + clk ? clk->parent : NULL); + + if (!clk || clk == parent) + return 0; + + if (clk->set_parent) { + int ret; + + ret = clk->set_parent(clk, parent); + if (ret) + return ret; + } + clk->parent = parent; + return 0; +} + void set_usboh3_clk(void) { clrsetbits_le32(&mxc_ccm->cscmr1, @@ -94,6 +178,34 @@ void enable_usboh3_clk(unsigned char enable) MXC_CCM_CCGR2_USBOH3_60M(cg)); } +void ipu_clk_enable(void) +{ + /* IPU root clock derived from AXI B */ + clrsetbits_le32(&mxc_ccm->cbcmr, MXC_CCM_CBCMR_IPU_HSP_CLK_SEL_MASK, + MXC_CCM_CBCMR_IPU_HSP_CLK_SEL(1)); + + setbits_le32(&mxc_ccm->CCGR5, + MXC_CCM_CCGR5_IPU(MXC_CCM_CCGR_CG_MASK)); + + /* Handshake with IPU when certain clock rates are changed. */ + clrbits_le32(&mxc_ccm->ccdr, MXC_CCM_CCDR_IPU_HS_MASK); + + /* Handshake with IPU when LPM is entered as its enabled. */ + clrbits_le32(&mxc_ccm->clpcr, MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS); +} + +void ipu_clk_disable(void) +{ + clrbits_le32(&mxc_ccm->CCGR5, + MXC_CCM_CCGR5_IPU(MXC_CCM_CCGR_CG_MASK)); + + /* Handshake with IPU when certain clock rates are changed. */ + setbits_le32(&mxc_ccm->ccdr, MXC_CCM_CCDR_IPU_HS_MASK); + + /* Handshake with IPU when LPM is entered as its enabled. */ + setbits_le32(&mxc_ccm->clpcr, MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS); +} + #ifdef CONFIG_I2C_MXC /* i2c_num can be from 0, to 1 for i.MX51 and 2 for i.MX53 */ int enable_i2c_clk(unsigned char enable, unsigned i2c_num) @@ -561,8 +673,7 @@ static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll) */ if (n_target < PLL_FREQ_MIN(ref) || n_target > PLL_FREQ_MAX(ref)) { - printf("Targeted peripheral clock should be" - "within [%d - %d]\n", + printf("Targeted peripheral clock should be within [%d - %d]\n", PLL_FREQ_MIN(ref) / SZ_DEC_1M, PLL_FREQ_MAX(ref) / SZ_DEC_1M); return -EINVAL; @@ -628,71 +739,63 @@ static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll) #define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \ { \ - writel(0x1232, &pll->ctrl); \ - writel(0x2, &pll->config); \ - writel((((pd) - 1) << 0) | ((fi) << 4), \ - &pll->op); \ - writel(fn, &(pll->mfn)); \ - writel((fd) - 1, &pll->mfd); \ - writel((((pd) - 1) << 0) | ((fi) << 4), \ - &pll->hfs_op); \ - writel(fn, &pll->hfs_mfn); \ - writel((fd) - 1, &pll->hfs_mfd); \ - writel(0x1232, &pll->ctrl); \ - while (!readl(&pll->ctrl) & 0x1) \ + __raw_writel(0x1232, &pll->ctrl); \ + __raw_writel(0x2, &pll->config); \ + __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \ + &pll->op); \ + __raw_writel(fn, &(pll->mfn)); \ + __raw_writel((fd) - 1, &pll->mfd); \ + __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \ + &pll->hfs_op); \ + __raw_writel(fn, &pll->hfs_mfn); \ + __raw_writel((fd) - 1, &pll->hfs_mfd); \ + __raw_writel(0x1232, &pll->ctrl); \ + while (!__raw_readl(&pll->ctrl) & 0x1) \ ;\ } static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param) { - u32 ccsr = readl(&mxc_ccm->ccsr); + u32 ccsr = __raw_readl(&mxc_ccm->ccsr); struct mxc_pll_reg *pll = mxc_plls[index]; switch (index) { case PLL1_CLOCK: /* Switch ARM to PLL2 clock */ - writel(ccsr | MXC_CCM_CCSR_PLL1_SW_CLK_SEL, - &mxc_ccm->ccsr); + __raw_writel(ccsr | 0x4, &mxc_ccm->ccsr); CHANGE_PLL_SETTINGS(pll, pll_param->pd, pll_param->mfi, pll_param->mfn, pll_param->mfd); /* Switch back */ - writel(ccsr & ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL, - &mxc_ccm->ccsr); + __raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr); break; case PLL2_CLOCK: /* Switch to pll2 bypass clock */ - writel(ccsr | MXC_CCM_CCSR_PLL2_SW_CLK_SEL, - &mxc_ccm->ccsr); + __raw_writel(ccsr | 0x2, &mxc_ccm->ccsr); CHANGE_PLL_SETTINGS(pll, pll_param->pd, pll_param->mfi, pll_param->mfn, pll_param->mfd); /* Switch back */ - writel(ccsr & ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL, - &mxc_ccm->ccsr); + __raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr); break; case PLL3_CLOCK: /* Switch to pll3 bypass clock */ - writel(ccsr | MXC_CCM_CCSR_PLL3_SW_CLK_SEL, - &mxc_ccm->ccsr); + __raw_writel(ccsr | 0x1, &mxc_ccm->ccsr); CHANGE_PLL_SETTINGS(pll, pll_param->pd, pll_param->mfi, pll_param->mfn, pll_param->mfd); /* Switch back */ - writel(ccsr & ~MXC_CCM_CCSR_PLL3_SW_CLK_SEL, - &mxc_ccm->ccsr); + __raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr); break; #ifdef CONFIG_MX53 case PLL4_CLOCK: /* Switch to pll4 bypass clock */ - writel(ccsr | MXC_CCM_CCSR_PLL4_SW_CLK_SEL, - &mxc_ccm->ccsr); + __raw_writel(ccsr | 0x20, &mxc_ccm->ccsr); CHANGE_PLL_SETTINGS(pll, pll_param->pd, pll_param->mfi, pll_param->mfn, pll_param->mfd); /* Switch back */ - writel(ccsr & ~MXC_CCM_CCSR_PLL4_SW_CLK_SEL, - &mxc_ccm->ccsr); + __raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr); break; #endif default: @@ -713,7 +816,9 @@ static int config_core_clk(u32 ref, u32 freq) /* The case that periph uses PLL1 is not considered here */ ret = calc_pll_params(ref, freq, &pll_param); if (ret != 0) { - printf("Error:Can't find pll parameters: %d\n", ret); + printf("Error: Can't find pll parameters for %u.%03uMHz ref %u.%03uMHz\n", + freq / 1000000, freq / 1000 % 1000, + ref / 1000000, ref / 1000 % 1000); return ret; } @@ -902,28 +1007,38 @@ void mxc_set_sata_internal_clock(void) /* * Dump some core clockes. */ +#define pr_clk_val(c, v) { \ + printf("%-11s %3lu.%03lu MHz\n", #c, \ + (v) / 1000000, (v) / 1000 % 1000); \ +} + +#define pr_clk(c) { \ + unsigned long __clk = mxc_get_clock(MXC_##c##_CLK); \ + pr_clk_val(c, __clk); \ +} + int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - u32 freq; + unsigned long freq; freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); - printf("PLL1 %8d MHz\n", freq / 1000000); + pr_clk_val(PLL1, freq); freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); - printf("PLL2 %8d MHz\n", freq / 1000000); + pr_clk_val(PLL2, freq); freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); - printf("PLL3 %8d MHz\n", freq / 1000000); + pr_clk_val(PLL3, freq); #ifdef CONFIG_MX53 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); - printf("PLL4 %8d MHz\n", freq / 1000000); + pr_clk_val(PLL4, freq); #endif printf("\n"); - printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); - printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); - printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000); - printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); + pr_clk(AHB); + pr_clk(IPG); + pr_clk(IPG); + pr_clk(DDR); #ifdef CONFIG_MXC_SPI - printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); + pr_clk(CSPI); #endif return 0; } diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c index 2d53669c89..3ccea6738e 100644 --- a/arch/arm/cpu/armv7/mx5/soc.c +++ b/arch/arm/cpu/armv7/mx5/soc.c @@ -20,6 +20,23 @@ #error "CPU_TYPE not defined" #endif +#ifdef CONFIG_HW_WATCHDOG +#define wdog_base ((void *)WDOG1_BASE_ADDR) +#define WDOG_WCR 0x00 +#define WCR_WDE (1 << 2) +#define WDOG_WSR 0x02 + +void hw_watchdog_reset(void) +{ + if (readw(wdog_base + WDOG_WCR) & WCR_WDE) { + static u16 toggle = 0xaaaa; + + writew(toggle, wdog_base + WDOG_WSR); + toggle ^= 0xffff; + } +} +#endif + u32 get_cpu_rev(void) { #ifdef CONFIG_MX51 @@ -72,7 +89,7 @@ void enable_caches(void) #endif #if defined(CONFIG_FEC_MXC) -void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +static void __imx_get_mac_from_fuse(int dev_id, unsigned char *mac) { int i; struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; @@ -83,6 +100,10 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) for (i = 0; i < 6; i++) mac[i] = readl(&fuse->mac_addr[i]) & 0xff; } + +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) + __attribute__((weak, alias("__imx_get_mac_from_fuse"))); + #endif void set_chipselect_size(int const cs_size) @@ -116,6 +137,19 @@ void set_chipselect_size(int const cs_size) writel(reg, &iomuxc_regs->gpr1); } +#if 1 +void cpu_cache_initialization(void) +{ + printf("Enabling L2 cache\n"); + asm volatile( + "mrc 15, 0, r0, c1, c0, 1\n" + "orr r0, r0, #0x2\n" + "mcr 15, 0, r0, c1, c0, 1\n" + : : : "r0", "memory" + ); +} +#endif + #ifdef CONFIG_MX53 void boot_mode_apply(unsigned cfg_val) { diff --git a/arch/arm/cpu/armv7/mx6/asm-offsets.c b/arch/arm/cpu/armv7/mx6/asm-offsets.c new file mode 100644 index 0000000000..77699c2cd0 --- /dev/null +++ b/arch/arm/cpu/armv7/mx6/asm-offsets.c @@ -0,0 +1,63 @@ +/* + * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c + * + * This program is used to generate definitions needed by + * assembly language modules. + * + * We use the technique used in the OSF Mach kernel code: + * generate asm statements containing #defines, + * compile this file to assembler, and then extract the + * #defines from the assembly-language output. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include +#include +#include + +#include + +int main(void) +{ + DEFINE(CCM_CCR, offsetof(struct mxc_ccm_reg, ccr)); + DEFINE(CCM_CCDR, offsetof(struct mxc_ccm_reg, ccdr)); + DEFINE(CCM_CSR, offsetof(struct mxc_ccm_reg, csr)); + DEFINE(CCM_CCSR, offsetof(struct mxc_ccm_reg, ccsr)); + DEFINE(CCM_CACRR, offsetof(struct mxc_ccm_reg, cacrr)); + DEFINE(CCM_CBCDR, offsetof(struct mxc_ccm_reg, cbcdr)); + DEFINE(CCM_CBCMR, offsetof(struct mxc_ccm_reg, cbcmr)); + DEFINE(CCM_CSCMR1, offsetof(struct mxc_ccm_reg, cscmr1)); + DEFINE(CCM_CSCMR2, offsetof(struct mxc_ccm_reg, cscmr2)); + DEFINE(CCM_CSCDR1, offsetof(struct mxc_ccm_reg, cscdr1)); + DEFINE(CCM_CS1CDR, offsetof(struct mxc_ccm_reg, cs1cdr)); + DEFINE(CCM_CS2CDR, offsetof(struct mxc_ccm_reg, cs2cdr)); + DEFINE(CCM_CDCDR, offsetof(struct mxc_ccm_reg, cdcdr)); + DEFINE(CCM_CHSCCDR, offsetof(struct mxc_ccm_reg, chsccdr)); + DEFINE(CCM_CSCDR2, offsetof(struct mxc_ccm_reg, cscdr2)); + DEFINE(CCM_CSCDR3, offsetof(struct mxc_ccm_reg, cscdr3)); + DEFINE(CCM_CSCDR4, offsetof(struct mxc_ccm_reg, cscdr4)); + DEFINE(CCM_CDHIPR, offsetof(struct mxc_ccm_reg, cdhipr)); + DEFINE(CCM_CDCR, offsetof(struct mxc_ccm_reg, cdcr)); + DEFINE(CCM_CTOR, offsetof(struct mxc_ccm_reg, ctor)); + DEFINE(CCM_CLPCR, offsetof(struct mxc_ccm_reg, clpcr)); + DEFINE(CCM_CISR, offsetof(struct mxc_ccm_reg, cisr)); + DEFINE(CCM_CIMR, offsetof(struct mxc_ccm_reg, cimr)); + DEFINE(CCM_CCOSR, offsetof(struct mxc_ccm_reg, ccosr)); + DEFINE(CCM_CGPR, offsetof(struct mxc_ccm_reg, cgpr)); + DEFINE(CCM_CCGR0, offsetof(struct mxc_ccm_reg, CCGR0)); + DEFINE(CCM_CCGR1, offsetof(struct mxc_ccm_reg, CCGR1)); + DEFINE(CCM_CCGR2, offsetof(struct mxc_ccm_reg, CCGR2)); + DEFINE(CCM_CCGR3, offsetof(struct mxc_ccm_reg, CCGR3)); + DEFINE(CCM_CCGR4, offsetof(struct mxc_ccm_reg, CCGR4)); + DEFINE(CCM_CCGR5, offsetof(struct mxc_ccm_reg, CCGR5)); + DEFINE(CCM_CCGR6, offsetof(struct mxc_ccm_reg, CCGR6)); + DEFINE(CCM_CCGR7, offsetof(struct mxc_ccm_reg, CCGR7)); + DEFINE(CCM_CMEOR, offsetof(struct mxc_ccm_reg, cmeor)); + + DEFINE(ANATOP_PLL_ENET, offsetof(struct anatop_regs, pll_enet)); + return 0; +} diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 3bdb553ffb..abe3c05ed2 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -13,13 +13,107 @@ #include enum pll_clocks { - PLL_SYS, /* System PLL */ - PLL_BUS, /* System Bus PLL*/ - PLL_USBOTG, /* OTG USB PLL */ - PLL_ENET, /* ENET PLL */ + PLL_ARM, /* PLL1: ARM PLL */ + PLL_BUS, /* PLL2: System Bus PLL*/ + PLL_USBOTG, /* PLL3: OTG USB PLL */ + PLL_AUDIO, /* PLL4: Audio PLL */ + PLL_VIDEO, /* PLL5: Video PLL */ + PLL_ENET, /* PLL6: ENET PLL */ + PLL_USB2, /* PLL7: USB2 PLL */ + PLL_MLB, /* PLL8: MLB PLL */ }; -struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; +struct mxc_ccm_reg *const imx_ccm = (void *)CCM_BASE_ADDR; +struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR; + +int clk_enable(struct clk *clk) +{ + int ret = 0; + + if (!clk) + return 0; + if (clk->usecount == 0) { +debug("%s: Enabling %s clock\n", __func__, clk->name); + ret = clk->enable(clk); + if (ret) + return ret; + clk->usecount++; + } + assert(clk->usecount > 0); + return ret; +} + +void clk_disable(struct clk *clk) +{ + if (!clk) + return; + + assert(clk->usecount > 0); + if (!(--clk->usecount)) { + if (clk->disable) { +debug("%s: Disabling %s clock\n", __func__, clk->name); + clk->disable(clk); + } + } +} + +int clk_get_usecount(struct clk *clk) +{ + if (clk == NULL) + return 0; + + return clk->usecount; +} + +u32 clk_get_rate(struct clk *clk) +{ + if (!clk) + return 0; + + return clk->rate; +} + +struct clk *clk_get_parent(struct clk *clk) +{ + if (!clk) + return 0; + + return clk->parent; +} + +int clk_set_rate(struct clk *clk, unsigned long rate) +{ + if (clk && clk->set_rate) + clk->set_rate(clk, rate); + return clk->rate; +} + +long clk_round_rate(struct clk *clk, unsigned long rate) +{ + if (clk == NULL || !clk->round_rate) + return 0; + + return clk->round_rate(clk, rate); +} + +int clk_set_parent(struct clk *clk, struct clk *parent) +{ + debug("Setting parent of clk %p to %p (%p)\n", clk, parent, + clk ? clk->parent : NULL); + + if (!clk || clk == parent) + return 0; + + if (clk->set_parent) { + int ret; + + ret = clk->set_parent(clk, parent); + if (ret) + return ret; + } + clk->parent = parent; + return 0; +} #ifdef CONFIG_MXC_OCOTP void enable_ocotp_clk(unsigned char enable) @@ -75,30 +169,64 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq) u32 div; switch (pll) { - case PLL_SYS: - div = __raw_readl(&imx_ccm->analog_pll_sys); - div &= BM_ANADIG_PLL_SYS_DIV_SELECT; - - return infreq * (div >> 1); + case PLL_ARM: + div = __raw_readl(&anatop->pll_arm); + if (div & BM_ANADIG_PLL_ARM_BYPASS) + /* Assume the bypass clock is always derived from OSC */ + return infreq; + div &= BM_ANADIG_PLL_ARM_DIV_SELECT; + + return infreq * div / 2; case PLL_BUS: - div = __raw_readl(&imx_ccm->analog_pll_528); - div &= BM_ANADIG_PLL_528_DIV_SELECT; + div = __raw_readl(&anatop->pll_528); + if (div & BM_ANADIG_PLL_SYS_BYPASS) + return infreq; + div &= BM_ANADIG_PLL_SYS_DIV_SELECT; - return infreq * (20 + (div << 1)); + return infreq * (20 + div * 2); case PLL_USBOTG: - div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl); + div = __raw_readl(&anatop->usb1_pll_480_ctrl); + if (div & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS) + return infreq; div &= BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT; - return infreq * (20 + (div << 1)); + return infreq * (20 + div * 2); + case PLL_AUDIO: + div = __raw_readl(&anatop->pll_audio); + if (div & BM_ANADIG_PLL_AUDIO_BYPASS) + return infreq; + div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT; + + return infreq * div; + case PLL_VIDEO: + div = __raw_readl(&anatop->pll_video); + if (div & BM_ANADIG_PLL_VIDEO_BYPASS) + return infreq; + div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT; + + return infreq * div; case PLL_ENET: - div = __raw_readl(&imx_ccm->analog_pll_enet); + div = __raw_readl(&anatop->pll_enet); + if (div & BM_ANADIG_PLL_ENET_BYPASS) + return infreq; div &= BM_ANADIG_PLL_ENET_DIV_SELECT; - return (div == 3 ? 125000000 : 25000000 * (div << 1)); - default: + return (div == 3 ? 125000000 : 25000000 * div * 2); + case PLL_USB2: + div = __raw_readl(&anatop->usb2_pll_480_ctrl); + if (div & BM_ANADIG_USB2_PLL_480_CTRL_BYPASS) + return infreq; + div &= BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT; + + return infreq * (20 + div * 2); + case PLL_MLB: + div = __raw_readl(&anatop->pll_mlb); + if (div & BM_ANADIG_PLL_MLB_BYPASS) + return infreq; + /* unknown external clock provided on MLB_CLK pin */ return 0; } - /* NOTREACHED */ + return 0; } static u32 get_mcu_main_clk(void) @@ -108,7 +236,7 @@ static u32 get_mcu_main_clk(void) reg = __raw_readl(&imx_ccm->cacrr); reg &= MXC_CCM_CACRR_ARM_PODF_MASK; reg >>= MXC_CCM_CACRR_ARM_PODF_OFFSET; - freq = decode_pll(PLL_SYS, MXC_HCLK); + freq = decode_pll(PLL_ARM, MXC_HCLK); return freq / (reg + 1); } @@ -131,8 +259,6 @@ u32 get_periph_clk(void) case 2: freq = MXC_HCLK; break; - default: - break; } } else { reg = __raw_readl(&imx_ccm->cbcmr); @@ -152,8 +278,6 @@ u32 get_periph_clk(void) case 3: freq = PLL2_PFD2_DIV_FREQ; break; - default: - break; } } @@ -254,6 +378,104 @@ static u32 get_emi_slow_clk(void) return root_freq / (emi_slow_pof + 1); } +static u32 get_nfc_clk(void) +{ + u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr); + u32 podf = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET; + u32 pred = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK) >> MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET; + int nfc_clk_sel = (cs2cdr & MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) >> + MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET; + u32 root_freq; + + switch (nfc_clk_sel) { + case 0: + root_freq = PLL2_PFD0_FREQ; + break; + case 1: + root_freq = decode_pll(PLL_BUS, MXC_HCLK); + break; + case 2: + root_freq = decode_pll(PLL_USBOTG, MXC_HCLK); + break; + case 3: + root_freq = PLL2_PFD2_FREQ; + break; + } + + return root_freq / (pred + 1) / (podf + 1); +} + +#define CS2CDR_ENFC_MASK (MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | \ + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | \ + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK) + +static int set_nfc_clk(u32 ref, u32 freq_khz) +{ + u32 cs2cdr = __raw_readl(&imx_ccm->cs2cdr); + u32 podf; + u32 pred; + int nfc_clk_sel; + u32 root_freq; + u32 min_err = ~0; + u32 nfc_val = ~0; + u32 freq = freq_khz * 1000; + + for (nfc_clk_sel = 0; nfc_clk_sel < 4; nfc_clk_sel++) { + u32 act_freq; + u32 err; + + if (ref < 4 && ref != nfc_clk_sel) + continue; + + switch (nfc_clk_sel) { + case 0: + root_freq = PLL2_PFD0_FREQ; + break; + case 1: + root_freq = decode_pll(PLL_BUS, MXC_HCLK); + break; + case 2: + root_freq = decode_pll(PLL_USBOTG, MXC_HCLK); + break; + case 3: + root_freq = PLL2_PFD2_FREQ; + break; + } + if (root_freq < freq) + continue; + + podf = min(DIV_ROUND_UP(root_freq, freq), 1 << 6); + pred = min(DIV_ROUND_UP(root_freq / podf, freq), 8); + act_freq = root_freq / pred / podf; + err = (freq - act_freq) * 100 / freq; + debug("root=%d[%u] freq=%u pred=%u podf=%u act=%u err=%d\n", + nfc_clk_sel, root_freq, freq, pred, podf, act_freq, err); + if (act_freq > freq) + continue; + if (err < min_err) { + nfc_val = (podf - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET; + nfc_val |= (pred - 1) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET; + nfc_val |= nfc_clk_sel << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET; + min_err = err; + if (err == 0) + break; + } + } + + if (nfc_val == ~0 || min_err > 10) + return -EINVAL; + + if ((cs2cdr & CS2CDR_ENFC_MASK) != nfc_val) { + debug("changing cs2cdr from %08x to %08x\n", cs2cdr, + (cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val); + __raw_writel((cs2cdr & ~CS2CDR_ENFC_MASK) | nfc_val, + &imx_ccm->cs2cdr); + } else { + debug("Leaving cs2cdr unchanged [%08x]\n", cs2cdr); + } + return 0; +} + #ifdef CONFIG_MX6SL static u32 get_mmdc_ch0_clk(void) { @@ -348,10 +570,8 @@ u32 imx_get_fecclk(void) int enable_sata_clock(void) { - u32 reg = 0; + u32 reg; s32 timeout = 100000; - struct mxc_ccm_reg *const imx_ccm - = (struct mxc_ccm_reg *) CCM_BASE_ADDR; /* Enable sata clock */ reg = readl(&imx_ccm->CCGR5); /* CCGR5 */ @@ -359,24 +579,52 @@ int enable_sata_clock(void) writel(reg, &imx_ccm->CCGR5); /* Enable PLLs */ - reg = readl(&imx_ccm->analog_pll_enet); - reg &= ~BM_ANADIG_PLL_SYS_POWERDOWN; - writel(reg, &imx_ccm->analog_pll_enet); - reg |= BM_ANADIG_PLL_SYS_ENABLE; + reg = readl(&anatop->pll_enet); + reg &= ~BM_ANADIG_PLL_ENET_POWERDOWN; + writel(reg, &anatop->pll_enet); + reg |= BM_ANADIG_PLL_ENET_ENABLE; while (timeout--) { - if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK) + if (readl(&anatop->pll_enet) & BM_ANADIG_PLL_ENET_LOCK) break; } if (timeout <= 0) return -EIO; - reg &= ~BM_ANADIG_PLL_SYS_BYPASS; - writel(reg, &imx_ccm->analog_pll_enet); + reg &= ~BM_ANADIG_PLL_ENET_BYPASS; + writel(reg, &anatop->pll_enet); reg |= BM_ANADIG_PLL_ENET_ENABLE_SATA; - writel(reg, &imx_ccm->analog_pll_enet); + writel(reg, &anatop->pll_enet); return 0 ; } +void ipu_clk_enable(void) +{ + u32 reg = readl(&imx_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK; + writel(reg, &imx_ccm->CCGR3); +} + +void ipu_clk_disable(void) +{ + u32 reg = readl(&imx_ccm->CCGR3); + reg &= ~MXC_CCM_CCGR3_IPU1_IPU_MASK; + writel(reg, &imx_ccm->CCGR3); +} + +void ocotp_clk_enable(void) +{ + u32 reg = readl(&imx_ccm->CCGR2); + reg |= MXC_CCM_CCGR2_OCOTP_CTRL_MASK; + writel(reg, &imx_ccm->CCGR2); +} + +void ocotp_clk_disable(void) +{ + u32 reg = readl(&imx_ccm->CCGR2); + reg &= ~MXC_CCM_CCGR2_OCOTP_CTRL_MASK; + writel(reg, &imx_ccm->CCGR2); +} + unsigned int mxc_get_clock(enum mxc_clock clk) { switch (clk) { @@ -411,51 +659,281 @@ unsigned int mxc_get_clock(enum mxc_clock clk) return get_usdhc_clk(3); case MXC_SATA_CLK: return get_ahb_clk(); - default: - break; + case MXC_NFC_CLK: + return get_nfc_clk(); } return -1; } +static inline int gcd(int m, int n) +{ + int t; + while (m > 0) { + if (n > m) { + t = m; + m = n; + n = t; + } /* swap */ + m -= n; + } + return n; +} + +/* Config CPU clock */ +static int set_arm_clk(u32 ref, u32 freq_khz) +{ + int d; + int div = 0; + int mul = 0; + u32 min_err = ~0; + u32 reg; + + if (freq_khz > ref / 1000 * 108 / 2 || freq_khz < ref / 1000 * 54 / 8 / 2) { + printf("Frequency %u.%03uMHz is out of range: %u.%03u..%u.%03u\n", + freq_khz / 1000, freq_khz % 1000, + 54 * ref / 1000000 / 8 / 2, 54 * ref / 1000 / 8 / 2 % 1000, + 108 * ref / 1000000 / 2, 108 * ref / 1000 / 2 % 1000); + return -EINVAL; + } + + for (d = DIV_ROUND_UP(648000, freq_khz); d <= 8; d++) { + int m = freq_khz * 2 * d / (ref / 1000); + u32 f; + u32 err; + + if (m > 108) { + debug("%s@%d: d=%d m=%d\n", __func__, __LINE__, + d, m); + break; + } + + f = ref * m / d / 2; + if (f > freq_khz * 1000) { + debug("%s@%d: d=%d m=%d f=%u freq=%u\n", __func__, __LINE__, + d, m, f, freq_khz); + if (--m < 54) + return -EINVAL; + f = ref * m / d / 2; + } + err = freq_khz * 1000 - f; + debug("%s@%d: d=%d m=%d f=%u freq=%u err=%d\n", __func__, __LINE__, + d, m, f, freq_khz, err); + if (err < min_err) { + mul = m; + div = d; + min_err = err; + if (err == 0) + break; + } + } + if (min_err == ~0) + return -EINVAL; + debug("Setting M=%3u D=%2u for %u.%03uMHz (actual: %u.%03uMHz)\n", + mul, div, freq_khz / 1000, freq_khz % 1000, + ref * mul / 2 / div / 1000000, ref * mul / 2 / div / 1000 % 1000); + + reg = readl(&anatop->pll_arm); + debug("anadig_pll_arm=%08x -> %08x\n", + reg, (reg & ~0x7f) | mul); + + reg |= 1 << 16; + writel(reg, &anatop->pll_arm); /* bypass PLL */ + + reg = (reg & ~0x7f) | mul; + writel(reg, &anatop->pll_arm); + + writel(div - 1, &imx_ccm->cacrr); + + reg &= ~(1 << 16); + writel(reg, &anatop->pll_arm); /* disable PLL bypass */ + + return 0; +} + +/* + * This function assumes the expected core clock has to be changed by + * modifying the PLL. This is NOT true always but for most of the times, + * it is. So it assumes the PLL output freq is the same as the expected + * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN. + * In the latter case, it will try to increase the presc value until + * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to + * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based + * on the targeted PLL and reference input clock to the PLL. Lastly, + * it sets the register based on these values along with the dividers. + * Note 1) There is no value checking for the passed-in divider values + * so the caller has to make sure those values are sensible. + * 2) Also adjust the NFC divider such that the NFC clock doesn't + * exceed NFC_CLK_MAX. + * 3) IPU HSP clock is independent of AHB clock. Even it can go up to + * 177MHz for higher voltage, this function fixes the max to 133MHz. + * 4) This function should not have allowed diag_printf() calls since + * the serial driver has been stoped. But leave then here to allow + * easy debugging by NOT calling the cyg_hal_plf_serial_stop(). + */ +int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk) +{ + int ret; + + freq *= 1000; + + switch (clk) { + case MXC_ARM_CLK: + ret = set_arm_clk(ref, freq); + break; + + case MXC_NFC_CLK: + ret = set_nfc_clk(ref, freq); + break; + + default: + printf("Warning: Unsupported or invalid clock type: %d\n", + clk); + return -EINVAL; + } + + return ret; +} + /* - * Dump some core clockes. + * Dump some core clocks. */ -int do_mx6_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - u32 freq; - freq = decode_pll(PLL_SYS, MXC_HCLK); - printf("PLL_SYS %8d MHz\n", freq / 1000000); - freq = decode_pll(PLL_BUS, MXC_HCLK); - printf("PLL_BUS %8d MHz\n", freq / 1000000); - freq = decode_pll(PLL_USBOTG, MXC_HCLK); - printf("PLL_OTG %8d MHz\n", freq / 1000000); - freq = decode_pll(PLL_ENET, MXC_HCLK); - printf("PLL_NET %8d MHz\n", freq / 1000000); +#define print_pll(pll) { \ + u32 __pll = decode_pll(pll, MXC_HCLK); \ + printf("%-12s %4d.%03d MHz\n", #pll, \ + __pll / 1000000, __pll / 1000 % 1000); \ + } + +#define MXC_IPG_PER_CLK MXC_IPG_PERCLK + +#define print_clk(clk) { \ + u32 __clk = mxc_get_clock(MXC_##clk##_CLK); \ + printf("%-12s %4d.%03d MHz\n", #clk, \ + __clk / 1000000, __clk / 1000 % 1000); \ + } +#define print_pfd(pll, pfd) { \ + u32 __pfd = readl(&anatop->pfd_##pll); \ + if (__pfd & (0x80 << 8 * pfd)) { \ + printf("PFD_%s[%d] OFF\n", #pll, pfd); \ + } else { \ + __pfd = (__pfd >> 8 * pfd) & 0x3f; \ + printf("PFD_%s[%d] %4d.%03d MHz\n", #pll, pfd, \ + pll * 18 / __pfd, \ + pll * 18 * 1000 / __pfd % 1000); \ + } \ +} + +static void do_mx6_showclocks(void) +{ + print_pll(PLL_ARM); + print_pll(PLL_BUS); + print_pll(PLL_USBOTG); + print_pll(PLL_AUDIO); + print_pll(PLL_VIDEO); + print_pll(PLL_ENET); + print_pll(PLL_USB2); printf("\n"); - printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); - printf("UART %8d kHz\n", mxc_get_clock(MXC_UART_CLK) / 1000); -#ifdef CONFIG_MXC_SPI - printf("CSPI %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000); -#endif - printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); - printf("AXI %8d kHz\n", mxc_get_clock(MXC_AXI_CLK) / 1000); - printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); - printf("USDHC1 %8d kHz\n", mxc_get_clock(MXC_ESDHC_CLK) / 1000); - printf("USDHC2 %8d kHz\n", mxc_get_clock(MXC_ESDHC2_CLK) / 1000); - printf("USDHC3 %8d kHz\n", mxc_get_clock(MXC_ESDHC3_CLK) / 1000); - printf("USDHC4 %8d kHz\n", mxc_get_clock(MXC_ESDHC4_CLK) / 1000); - printf("EMI SLOW %8d kHz\n", mxc_get_clock(MXC_EMI_SLOW_CLK) / 1000); - printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000); - return 0; + print_pfd(480, 0); + print_pfd(480, 1); + print_pfd(480, 2); + print_pfd(480, 3); + print_pfd(528, 0); + print_pfd(528, 1); + print_pfd(528, 2); + print_pfd(528, 3); + printf("\n"); + + print_clk(IPG); + print_clk(UART); + print_clk(CSPI); + print_clk(AHB); + print_clk(AXI); + print_clk(DDR); + print_clk(ESDHC); + print_clk(ESDHC2); + print_clk(ESDHC3); + print_clk(ESDHC4); + print_clk(EMI_SLOW); + print_clk(NFC); + print_clk(IPG_PER); + print_clk(ARM); +} + +static struct clk_lookup { + const char *name; + unsigned int index; +} mx6_clk_lookup[] = { + { "arm", MXC_ARM_CLK, }, + { "nfc", MXC_NFC_CLK, }, +}; + +int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + int i; + unsigned long freq; + unsigned long ref = ~0UL; + + if (argc < 2) { + do_mx6_showclocks(); + return CMD_RET_SUCCESS; + } else if (argc == 2 || argc > 4) { + return CMD_RET_USAGE; + } + + freq = simple_strtoul(argv[2], NULL, 0); + if (freq == 0) { + printf("Invalid clock frequency %lu\n", freq); + return CMD_RET_FAILURE; + } + if (argc > 3) { + ref = simple_strtoul(argv[3], NULL, 0); + } + for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) { + if (strcasecmp(argv[1], mx6_clk_lookup[i].name) == 0) { + switch (mx6_clk_lookup[i].index) { + case MXC_ARM_CLK: + if (argc > 3) + return CMD_RET_USAGE; + ref = CONFIG_SYS_MX6_HCLK; + break; + + case MXC_NFC_CLK: + if (argc > 3 && ref > 3) { + printf("Invalid clock selector value: %lu\n", ref); + return CMD_RET_FAILURE; + } + break; + } + printf("Setting %s clock to %lu MHz\n", + mx6_clk_lookup[i].name, freq); + if (mxc_set_clock(ref, freq, mx6_clk_lookup[i].index)) + break; + freq = mxc_get_clock(mx6_clk_lookup[i].index); + printf("%s clock set to %lu.%03lu MHz\n", + mx6_clk_lookup[i].name, + freq / 1000000, freq / 1000 % 1000); + return CMD_RET_SUCCESS; + } + } + if (i == ARRAY_SIZE(mx6_clk_lookup)) { + printf("clock %s not found; supported clocks are:\n", argv[1]); + for (i = 0; i < ARRAY_SIZE(mx6_clk_lookup); i++) { + printf("\t%s\n", mx6_clk_lookup[i].name); + } + } else { + printf("Failed to set clock %s to %s MHz\n", + argv[1], argv[2]); + } + return CMD_RET_FAILURE; } /***************************************************/ U_BOOT_CMD( - clocks, CONFIG_SYS_MAXARGS, 1, do_mx6_showclocks, - "display clocks", - "" + clocks, 4, 0, do_clocks, + "display/set clocks", + " - display clock settings\n" + "clocks - set clock to MHz" ); diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c index 32572eea6a..86b15250c0 100644 --- a/arch/arm/cpu/armv7/mx6/soc.c +++ b/arch/arm/cpu/armv7/mx6/soc.c @@ -11,11 +11,25 @@ #include #include #include +#include +#include #include #include #include #include #include +#ifdef CONFIG_VIDEO_IPUV3 +#include +#endif + +DECLARE_GLOBAL_DATA_PTR; + +#define TEMPERATURE_MIN -40 +#define TEMPERATURE_HOT 80 +#define TEMPERATURE_MAX 125 +#define REG_VALUE_TO_CEL(ratio, raw) ((raw_n40c - raw) * 100 / ratio - 40) + +#define __data __attribute__((section(".data"))) struct scu_regs { u32 ctrl; @@ -25,6 +39,28 @@ struct scu_regs { u32 fpga_rev; }; +#ifdef CONFIG_HW_WATCHDOG +#define wdog_base ((void *)WDOG1_BASE_ADDR) +#define WDOG_WCR 0x00 +#define WCR_WDE (1 << 2) +#define WDOG_WSR 0x02 + +void hw_watchdog_reset(void) +{ + if (readw(wdog_base + WDOG_WCR) & WCR_WDE) { + static u16 toggle = 0xaaaa; + static int first = 1; + + if (first) { + printf("Watchdog active\n"); + first = 0; + } + writew(toggle, wdog_base + WDOG_WSR); + toggle ^= 0xffff; + } +} +#endif + u32 get_cpu_rev(void) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; @@ -99,7 +135,7 @@ void init_aips(void) * Possible values are from 0.725V to 1.450V in steps of * 0.025V (25mV). */ -void set_vddsoc(u32 mv) +static void set_vddsoc(u32 mv) { struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR; u32 val, reg = readl(&anatop->reg_core); @@ -119,6 +155,116 @@ void set_vddsoc(u32 mv) writel(reg, &anatop->reg_core); } +static u32 __data thermal_calib; + +int read_cpu_temperature(void) +{ + unsigned int reg, tmp, i; + unsigned int raw_25c, raw_hot, hot_temp, raw_n40c, ratio; + int temperature; + struct anatop_regs *const anatop = (void *)ANATOP_BASE_ADDR; + struct mx6_ocotp_regs *const ocotp_regs = (void *)OCOTP_BASE_ADDR; + + if (!thermal_calib) { + ocotp_clk_enable(); + writel(1, &ocotp_regs->hw_ocotp_read_ctrl); + thermal_calib = readl(&ocotp_regs->hw_ocotp_ana1); + writel(0, &ocotp_regs->hw_ocotp_read_ctrl); + ocotp_clk_disable(); + } + + if (thermal_calib == 0 || thermal_calib == 0xffffffff) + return TEMPERATURE_MIN; + + /* Fuse data layout: + * [31:20] sensor value @ 25C + * [19:8] sensor value of hot + * [7:0] hot temperature value */ + raw_25c = thermal_calib >> 20; + raw_hot = (thermal_calib & 0xfff00) >> 8; + hot_temp = thermal_calib & 0xff; + + ratio = ((raw_25c - raw_hot) * 100) / (hot_temp - 25); + raw_n40c = raw_25c + (13 * ratio) / 20; + + /* now we only using single measure, every time we measure + the temperature, we will power on/down the anadig module*/ + writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_clr); + writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_set); + + /* write measure freq */ + reg = readl(&anatop->tempsense1); + reg &= ~BM_ANADIG_TEMPSENSE1_MEASURE_FREQ; + reg |= 327; + writel(reg, &anatop->tempsense1); + + writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_clr); + writel(BM_ANADIG_TEMPSENSE0_FINISHED, &anatop->tempsense0_clr); + writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, &anatop->tempsense0_set); + + tmp = 0; + /* read five times of temperature values to get average*/ + for (i = 0; i < 5; i++) { + while ((readl(&anatop->tempsense0) & + BM_ANADIG_TEMPSENSE0_FINISHED) == 0) + udelay(10000); + reg = readl(&anatop->tempsense0); + tmp += (reg & BM_ANADIG_TEMPSENSE0_TEMP_VALUE) >> + BP_ANADIG_TEMPSENSE0_TEMP_VALUE; + writel(BM_ANADIG_TEMPSENSE0_FINISHED, + &anatop->tempsense0_clr); + } + + tmp = tmp / 5; + if (tmp <= raw_n40c) + temperature = REG_VALUE_TO_CEL(ratio, tmp); + else + temperature = TEMPERATURE_MIN; + + /* power down anatop thermal sensor */ + writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, &anatop->tempsense0_set); + writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, &anatop->ana_misc0_clr); + + return temperature; +} + +int check_cpu_temperature(int boot) +{ + static int __data max_temp; + int boot_limit = TEMPERATURE_HOT; + int tmp = read_cpu_temperature(); + + if (tmp < TEMPERATURE_MIN || tmp > TEMPERATURE_MAX) { + printf("Temperature: can't get valid data!\n"); + return tmp; + } + + while (tmp >= boot_limit) { + if (boot) { + printf("CPU is %d C, too hot to boot, waiting...\n", + tmp); + udelay(5000000); + tmp = read_cpu_temperature(); + boot_limit = TEMPERATURE_HOT - 1; + } else { + printf("CPU is %d C, too hot, resetting...\n", + tmp); + udelay(1000000); + reset_cpu(0); + } + } + + if (boot) { + printf("Temperature: %d C, calibration data 0x%x\n", + tmp, thermal_calib); + } else if (tmp > max_temp) { + if (tmp > TEMPERATURE_HOT - 5) + printf("WARNING: CPU temperature %d C\n", tmp); + max_temp = tmp; + } + return tmp; +} + static void imx_set_wdog_powerdown(bool enable) { struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR; @@ -129,6 +275,7 @@ static void imx_set_wdog_powerdown(bool enable) writew(enable, &wdog2->wmcr); } +#ifdef CONFIG_ARCH_CPU_INIT int arch_cpu_init(void) { init_aips(); @@ -137,13 +284,17 @@ int arch_cpu_init(void) imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */ -#ifdef CONFIG_APBH_DMA - /* Start APBH DMA */ +#ifdef CONFIG_VIDEO_IPUV3 + gd->arch.ipu_hw_rev = IPUV3_HW_REV_IPUV3H; +#endif +#ifdef CONFIG_APBH_DMA + /* Timer is required for Initializing APBH DMA */ + timer_init(); mxs_dma_init(); #endif - return 0; } +#endif #ifndef CONFIG_SYS_DCACHE_OFF void enable_caches(void) @@ -163,14 +314,13 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) u32 value = readl(&fuse->mac_addr_high); mac[0] = (value >> 8); - mac[1] = value ; + mac[1] = value; value = readl(&fuse->mac_addr_low); - mac[2] = value >> 24 ; - mac[3] = value >> 16 ; - mac[4] = value >> 8 ; - mac[5] = value ; - + mac[2] = value >> 24; + mac[3] = value >> 16; + mac[4] = value >> 8; + mac[5] = value; } #endif diff --git a/arch/arm/cpu/armv7/omap-common/config.mk b/arch/arm/cpu/armv7/omap-common/config.mk deleted file mode 100644 index 3a36ab65e1..0000000000 --- a/arch/arm/cpu/armv7/omap-common/config.mk +++ /dev/null @@ -1,9 +0,0 @@ -# -# (C) Copyright 2002 -# Gary Jennejohn, DENX Software Engineering, -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# Make ARMv5 to allow more compilers to work, even though its v7a. -PLATFORM_CPPFLAGS += -march=armv5 diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 86c0e42174..9c8cf89aa6 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -26,7 +26,11 @@ ENTRY(set_pl310_ctrl_reg) PUSH {r4-r11, lr} @ save registers - ROM code may pollute @ our registers LDR r12, =0x102 @ Set PL310 control register - value in R0 - .word 0xe1600070 @ SMC #0 - hand assembled because -march=armv5 - @ call ROM Code API to set control register +#if __GNUC__ >= 4 && __GNUC_MINOR__ >= 6 && defined(__ARM_ARCH_7A__) + .arch_extension sec + smc #0 @ call ROM Code API to set control register +#else + .word 0xe1600070 +#endif POP {r4-r11, pc} ENDPROC(set_pl310_ctrl_reg) diff --git a/arch/arm/cpu/armv7/omap-common/reset.c b/arch/arm/cpu/armv7/omap-common/reset.c index 91ad031ddd..4145e37c3f 100644 --- a/arch/arm/cpu/armv7/omap-common/reset.c +++ b/arch/arm/cpu/armv7/omap-common/reset.c @@ -9,6 +9,7 @@ * * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include #include @@ -16,6 +17,8 @@ void __weak reset_cpu(unsigned long ignored) { + /* clear the reset status flags */ + writel(readl(PRM_RSTST), PRM_RSTST); writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL); } diff --git a/arch/arm/cpu/armv7/omap-common/timer.c b/arch/arm/cpu/armv7/omap-common/timer.c index 7c9924dc39..95da274178 100644 --- a/arch/arm/cpu/armv7/omap-common/timer.c +++ b/arch/arm/cpu/armv7/omap-common/timer.c @@ -17,6 +17,7 @@ */ #include +#include #include #include #include @@ -29,22 +30,66 @@ static struct gptimer *timer_base = (struct gptimer *)CONFIG_SYS_TIMERBASE; * Nothing really to do with interrupts, just starts up a counter. */ +#if CONFIG_SYS_PTV > 7 +#error Invalid CONFIG_SYS_PTV value +#elif CONFIG_SYS_PTV >= 0 #define TIMER_CLOCK (V_SCLK / (2 << CONFIG_SYS_PTV)) -#define TIMER_OVERFLOW_VAL 0xffffffff +#define TCLR_VAL ((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST) +#else +#define TIMER_CLOCK V_SCLK +#define TCLR_VAL (TCLR_AR | TCLR_ST) +#endif #define TIMER_LOAD_VAL 0 +#define TIOCP_CFG_SOFTRESET (1 << 0) + +#if TIMER_CLOCK < CONFIG_SYS_HZ +#error TIMER_CLOCK must be >= CONFIG_SYS_HZ +#endif + +/* + * Start timer so that it will overflow 15 sec after boot, + * to catch misbehaving timer code early on! +*/ +#define TIMER_START (-time_to_tick(15 * CONFIG_SYS_HZ)) + +static inline unsigned long tick_to_time(unsigned long tick) +{ + return tick / (TIMER_CLOCK / CONFIG_SYS_HZ); +} + +static inline unsigned long time_to_tick(unsigned long time) +{ + return time * (TIMER_CLOCK / CONFIG_SYS_HZ); +} + +static inline unsigned long us_to_ticks(unsigned long usec) +{ + return usec * (TIMER_CLOCK / CONFIG_SYS_HZ / 1000); +} + int timer_init(void) { +#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) + /* Reset the Timer */ + writel(TIOCP_CFG_SOFTRESET, &timer_base->tiocp_cfg); + + /* Wait until the reset is done */ + while (readl(&timer_base->tiocp_cfg) & TIOCP_CFG_SOFTRESET) + ; + + /* preload the counter to make overflow occur early */ + writel(TIMER_START, &timer_base->tldr); + writel(~0, &timer_base->ttgr); + /* start the counter ticking up, reload value on overflow */ writel(TIMER_LOAD_VAL, &timer_base->tldr); /* enable timer */ - writel((CONFIG_SYS_PTV << 2) | TCLR_PRE | TCLR_AR | TCLR_ST, - &timer_base->tclr); - - /* reset time, capture current incrementer value time */ - gd->arch.lastinc = readl(&timer_base->tcrr) / - (TIMER_CLOCK / CONFIG_SYS_HZ); - gd->arch.tbl = 0; /* start "advancing" time stamp from 0 */ + writel(TCLR_VAL, &timer_base->tclr); +#endif + gd->arch.lastinc = -30 * TIMER_CLOCK; + gd->arch.tbl = TIMER_START; + gd->arch.timer_rate_hz = TIMER_CLOCK; return 0; } @@ -54,39 +99,29 @@ int timer_init(void) */ ulong get_timer(ulong base) { - return get_timer_masked() - base; + return tick_to_time(get_ticks() - time_to_tick(base)); } /* delay x useconds */ void __udelay(unsigned long usec) { - long tmo = usec * (TIMER_CLOCK / 1000) / 1000; - unsigned long now, last = readl(&timer_base->tcrr); - - while (tmo > 0) { - now = readl(&timer_base->tcrr); - if (last > now) /* count up timer overflow */ - tmo -= TIMER_OVERFLOW_VAL - last + now + 1; - else - tmo -= now - last; - last = now; - } + unsigned long start = readl(&timer_base->tcrr); + unsigned long ticks = us_to_ticks(usec); + + if (usec == 0) + return; + + if (ticks == 0) + ticks++; + + while (readl(&timer_base->tcrr) - start < ticks) + /* NOP */ ; } ulong get_timer_masked(void) { /* current tick value */ - ulong now = readl(&timer_base->tcrr) / (TIMER_CLOCK / CONFIG_SYS_HZ); - - if (now >= gd->arch.lastinc) { /* normal mode (non roll) */ - /* move stamp fordward with absoulte diff ticks */ - gd->arch.tbl += (now - gd->arch.lastinc); - } else { /* we have rollover of incrementer */ - gd->arch.tbl += ((TIMER_LOAD_VAL / (TIMER_CLOCK / - CONFIG_SYS_HZ)) - gd->arch.lastinc) + now; - } - gd->arch.lastinc = now; - return gd->arch.tbl; + return tick_to_time(get_ticks()); } /* @@ -95,7 +130,12 @@ ulong get_timer_masked(void) */ unsigned long long get_ticks(void) { - return get_timer(0); + ulong now = readl(&timer_base->tcrr); + ulong inc = now - gd->arch.lastinc; + + gd->arch.tbl += inc; + gd->arch.lastinc = now; + return gd->arch.tbl; } /* @@ -104,5 +144,5 @@ unsigned long long get_ticks(void) */ ulong get_tbclk(void) { - return CONFIG_SYS_HZ; + return gd->arch.timer_rate_hz; } diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index ef62fc8327..364094ed0d 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -65,11 +65,7 @@ _end_vect: .globl _TEXT_BASE _TEXT_BASE: -#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_TEXT_BASE) - .word CONFIG_SPL_TEXT_BASE -#else - .word CONFIG_SYS_TEXT_BASE -#endif + .word _start /* * These are defined in the board-specific linker script. diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/dts/am33xx.dtsi new file mode 100644 index 0000000000..edee62f338 --- /dev/null +++ b/arch/arm/dts/am33xx.dtsi @@ -0,0 +1,158 @@ +/* + * Device Tree Source for AM33XX SoC + * + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This file is licensed under the terms of the GNU General Public License + * version 2. This program is licensed "as is" without any warranty of any + * kind, whether express or implied. + */ + +/include/ "skeleton.dtsi" + +/ { + compatible = "ti,am33xx"; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + serial5 = &uart5; + }; + + cpus { + cpu@0 { + compatible = "arm,cortex-a8"; + }; + }; + + /* + * The soc node represents the soc top level view. It is uses for IPs + * that are not memory mapped in the MPU view or for the MPU itself. + */ + soc { + compatible = "ti,omap-infra"; + mpu { + compatible = "ti,omap3-mpu"; + ti,hwmods = "mpu"; + }; + }; + + /* + * XXX: Use a flat representation of the AM33XX interconnect. + * The real AM33XX interconnect network is quite complex.Since + * that will not bring real advantage to represent that in DT + * for the moment, just use a fake OCP bus entry to represent + * the whole bus hierarchy. + */ + ocp { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + ti,hwmods = "l3_main"; + + intc: interrupt-controller@48200000 { + compatible = "ti,omap2-intc"; + interrupt-controller; + #interrupt-cells = <1>; + ti,intc-size = <128>; + reg = <0x48200000 0x1000>; + }; + + gpio0: gpio@44e07000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio1"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio1: gpio@4804C000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio2"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio2: gpio@481AC000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio3"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio3: gpio@481AE000 { + compatible = "ti,omap4-gpio"; + ti,hwmods = "gpio4"; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + uart0: serial@44E09000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart1"; + clock-frequency = <48000000>; + }; + + uart1: serial@48022000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart2"; + clock-frequency = <48000000>; + }; + + uart2: serial@48024000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart3"; + clock-frequency = <48000000>; + }; + + uart3: serial@481A6000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart4"; + clock-frequency = <48000000>; + }; + + uart4: serial@481A8000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart5"; + clock-frequency = <48000000>; + }; + + uart5: serial@481AA000 { + compatible = "ti,omap3-uart"; + ti,hwmods = "uart6"; + clock-frequency = <48000000>; + }; + + i2c0: i2c@44E0B000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c1"; + }; + + i2c1: i2c@4802A000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c2"; + }; + + i2c2: i2c@4819C000 { + compatible = "ti,omap4-i2c"; + #address-cells = <1>; + #size-cells = <0>; + ti,hwmods = "i2c3"; + }; + }; +}; diff --git a/arch/arm/dts/imx6qdl.dtsi b/arch/arm/dts/imx6qdl.dtsi new file mode 100644 index 0000000000..06ec460b45 --- /dev/null +++ b/arch/arm/dts/imx6qdl.dtsi @@ -0,0 +1,800 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + gpio4 = &gpio5; + gpio5 = &gpio6; + gpio6 = &gpio7; + }; + + intc: interrupt-controller@00a01000 { + compatible = "arm,cortex-a9-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + reg = <0x00a01000 0x1000>, + <0x00a00100 0x100>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ckil { + compatible = "fsl,imx-ckil", "fixed-clock"; + clock-frequency = <32768>; + }; + + ckih1 { + compatible = "fsl,imx-ckih1", "fixed-clock"; + clock-frequency = <0>; + }; + + osc { + compatible = "fsl,imx-osc", "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&intc>; + ranges; + + dma-apbh@00110000 { + compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; + reg = <0x00110000 0x2000>; + clocks = <&clks 106>; + }; + + gpmi: gpmi-nand@00112000 { + compatible = "fsl,imx6q-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x00112000 0x2000>, <0x00114000 0x2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <0 13 0x04>, <0 15 0x04>; + interrupt-names = "gpmi-dma", "bch"; + clocks = <&clks 152>, <&clks 153>, <&clks 151>, + <&clks 150>, <&clks 149>; + clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", + "gpmi_bch_apb", "per1_bch"; + fsl,gpmi-dma-channel = <0>; + status = "disabled"; + }; + + timer@00a00600 { + compatible = "arm,cortex-a9-twd-timer"; + reg = <0x00a00600 0x20>; + interrupts = <1 13 0xf01>; + }; + + L2: l2-cache@00a02000 { + compatible = "arm,pl310-cache"; + reg = <0x00a02000 0x1000>; + interrupts = <0 92 0x04>; + cache-unified; + cache-level = <2>; + }; + + aips-bus@02000000 { /* AIPS1 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x100000>; + ranges; + + spba-bus@02000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02000000 0x40000>; + ranges; + + spdif: spdif@02004000 { + reg = <0x02004000 0x4000>; + interrupts = <0 52 0x04>; + }; + + ecspi1: ecspi@02008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; + reg = <0x02008000 0x4000>; + interrupts = <0 31 0x04>; + clocks = <&clks 112>, <&clks 112>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi2: ecspi@0200c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; + reg = <0x0200c000 0x4000>; + interrupts = <0 32 0x04>; + clocks = <&clks 113>, <&clks 113>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi3: ecspi@02010000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; + reg = <0x02010000 0x4000>; + interrupts = <0 33 0x04>; + clocks = <&clks 114>, <&clks 114>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + ecspi4: ecspi@02014000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; + reg = <0x02014000 0x4000>; + interrupts = <0 34 0x04>; + clocks = <&clks 115>, <&clks 115>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart1: serial@02020000 { + compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x02020000 0x4000>; + interrupts = <0 26 0x04>; + clocks = <&clks 160>, <&clks 161>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + esai: esai@02024000 { + reg = <0x02024000 0x4000>; + interrupts = <0 51 0x04>; + }; + + ssi1: ssi@02028000 { + compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; + reg = <0x02028000 0x4000>; + interrupts = <0 46 0x04>; + clocks = <&clks 178>; + fsl,fifo-depth = <15>; + fsl,ssi-dma-events = <38 37>; + status = "disabled"; + }; + + ssi2: ssi@0202c000 { + compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; + reg = <0x0202c000 0x4000>; + interrupts = <0 47 0x04>; + clocks = <&clks 179>; + fsl,fifo-depth = <15>; + fsl,ssi-dma-events = <42 41>; + status = "disabled"; + }; + + ssi3: ssi@02030000 { + compatible = "fsl,imx6q-ssi","fsl,imx21-ssi"; + reg = <0x02030000 0x4000>; + interrupts = <0 48 0x04>; + clocks = <&clks 180>; + fsl,fifo-depth = <15>; + fsl,ssi-dma-events = <46 45>; + status = "disabled"; + }; + + asrc: asrc@02034000 { + reg = <0x02034000 0x4000>; + interrupts = <0 50 0x04>; + }; + + spba@0203c000 { + reg = <0x0203c000 0x4000>; + }; + }; + + vpu: vpu@02040000 { + reg = <0x02040000 0x3c000>; + interrupts = <0 3 0x04 0 12 0x04>; + }; + + aipstz@0207c000 { /* AIPSTZ1 */ + reg = <0x0207c000 0x4000>; + }; + + pwm1: pwm@02080000 { + #pwm-cells = <2>; + compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; + reg = <0x02080000 0x4000>; + interrupts = <0 83 0x04>; + clocks = <&clks 62>, <&clks 145>; + clock-names = "ipg", "per"; + }; + + pwm2: pwm@02084000 { + #pwm-cells = <2>; + compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; + reg = <0x02084000 0x4000>; + interrupts = <0 84 0x04>; + clocks = <&clks 62>, <&clks 146>; + clock-names = "ipg", "per"; + }; + + pwm3: pwm@02088000 { + #pwm-cells = <2>; + compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; + reg = <0x02088000 0x4000>; + interrupts = <0 85 0x04>; + clocks = <&clks 62>, <&clks 147>; + clock-names = "ipg", "per"; + }; + + pwm4: pwm@0208c000 { + #pwm-cells = <2>; + compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm"; + reg = <0x0208c000 0x4000>; + interrupts = <0 86 0x04>; + clocks = <&clks 62>, <&clks 148>; + clock-names = "ipg", "per"; + }; + + can1: flexcan@02090000 { + reg = <0x02090000 0x4000>; + interrupts = <0 110 0x04>; + }; + + can2: flexcan@02094000 { + reg = <0x02094000 0x4000>; + interrupts = <0 111 0x04>; + }; + + gpt: gpt@02098000 { + compatible = "fsl,imx6q-gpt"; + reg = <0x02098000 0x4000>; + interrupts = <0 55 0x04>; + }; + + gpio1: gpio@0209c000 { + compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; + reg = <0x0209c000 0x4000>; + interrupts = <0 66 0x04 0 67 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@020a0000 { + compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; + reg = <0x020a0000 0x4000>; + interrupts = <0 68 0x04 0 69 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@020a4000 { + compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; + reg = <0x020a4000 0x4000>; + interrupts = <0 70 0x04 0 71 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@020a8000 { + compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; + reg = <0x020a8000 0x4000>; + interrupts = <0 72 0x04 0 73 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio5: gpio@020ac000 { + compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; + reg = <0x020ac000 0x4000>; + interrupts = <0 74 0x04 0 75 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio6: gpio@020b0000 { + compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; + reg = <0x020b0000 0x4000>; + interrupts = <0 76 0x04 0 77 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio7: gpio@020b4000 { + compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio"; + reg = <0x020b4000 0x4000>; + interrupts = <0 78 0x04 0 79 0x04>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + kpp: kpp@020b8000 { + reg = <0x020b8000 0x4000>; + interrupts = <0 82 0x04>; + }; + + wdog1: wdog@020bc000 { + compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; + reg = <0x020bc000 0x4000>; + interrupts = <0 80 0x04>; + clocks = <&clks 0>; + }; + + wdog2: wdog@020c0000 { + compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt"; + reg = <0x020c0000 0x4000>; + interrupts = <0 81 0x04>; + clocks = <&clks 0>; + status = "disabled"; + }; + + clks: ccm@020c4000 { + compatible = "fsl,imx6q-ccm"; + reg = <0x020c4000 0x4000>; + interrupts = <0 87 0x04 0 88 0x04>; + #clock-cells = <1>; + }; + + anatop: anatop@020c8000 { + compatible = "fsl,imx6q-anatop", "syscon", "simple-bus"; + reg = <0x020c8000 0x1000>; + interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>; + + regulator-1p1@110 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd1p1"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1375000>; + regulator-always-on; + anatop-reg-offset = <0x110>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <4>; + anatop-min-voltage = <800000>; + anatop-max-voltage = <1375000>; + }; + + regulator-3p0@120 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd3p0"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <3150000>; + regulator-always-on; + anatop-reg-offset = <0x120>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2625000>; + anatop-max-voltage = <3400000>; + }; + + regulator-2p5@130 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vdd2p5"; + regulator-min-microvolt = <2000000>; + regulator-max-microvolt = <2750000>; + regulator-always-on; + anatop-reg-offset = <0x130>; + anatop-vol-bit-shift = <8>; + anatop-vol-bit-width = <5>; + anatop-min-bit-val = <0>; + anatop-min-voltage = <2000000>; + anatop-max-voltage = <2750000>; + }; + + reg_arm: regulator-vddcore@140 { + compatible = "fsl,anatop-regulator"; + regulator-name = "cpu"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <0>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <24>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + reg_pu: regulator-vddpu@140 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddpu"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <9>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <26>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + + reg_soc: regulator-vddsoc@140 { + compatible = "fsl,anatop-regulator"; + regulator-name = "vddsoc"; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1450000>; + regulator-always-on; + anatop-reg-offset = <0x140>; + anatop-vol-bit-shift = <18>; + anatop-vol-bit-width = <5>; + anatop-delay-reg-offset = <0x170>; + anatop-delay-bit-shift = <28>; + anatop-delay-bit-width = <2>; + anatop-min-bit-val = <1>; + anatop-min-voltage = <725000>; + anatop-max-voltage = <1450000>; + }; + }; + + usbphy1: usbphy@020c9000 { + compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; + reg = <0x020c9000 0x1000>; + interrupts = <0 44 0x04>; + clocks = <&clks 182>; + }; + + usbphy2: usbphy@020ca000 { + compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy"; + reg = <0x020ca000 0x1000>; + interrupts = <0 45 0x04>; + clocks = <&clks 183>; + }; + + snvs@020cc000 { + compatible = "fsl,sec-v4.0-mon", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x020cc000 0x4000>; + + snvs-rtc-lp@34 { + compatible = "fsl,sec-v4.0-mon-rtc-lp"; + reg = <0x34 0x58>; + interrupts = <0 19 0x04 0 20 0x04>; + }; + }; + + epit1: epit@020d0000 { /* EPIT1 */ + reg = <0x020d0000 0x4000>; + interrupts = <0 56 0x04>; + }; + + epit2: epit@020d4000 { /* EPIT2 */ + reg = <0x020d4000 0x4000>; + interrupts = <0 57 0x04>; + }; + + src: src@020d8000 { + compatible = "fsl,imx6q-src"; + reg = <0x020d8000 0x4000>; + interrupts = <0 91 0x04 0 96 0x04>; + }; + + gpc: gpc@020dc000 { + compatible = "fsl,imx6q-gpc"; + reg = <0x020dc000 0x4000>; + interrupts = <0 89 0x04 0 90 0x04>; + }; + + gpr: iomuxc-gpr@020e0000 { + compatible = "fsl,imx6q-iomuxc-gpr", "syscon"; + reg = <0x020e0000 0x38>; + }; + + dcic1: dcic@020e4000 { + reg = <0x020e4000 0x4000>; + interrupts = <0 124 0x04>; + }; + + dcic2: dcic@020e8000 { + reg = <0x020e8000 0x4000>; + interrupts = <0 125 0x04>; + }; + + sdma: sdma@020ec000 { + compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma"; + reg = <0x020ec000 0x4000>; + interrupts = <0 2 0x04>; + clocks = <&clks 155>, <&clks 155>; + clock-names = "ipg", "ahb"; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; + }; + }; + + aips-bus@02100000 { /* AIPS2 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x02100000 0x100000>; + ranges; + + caam@02100000 { + reg = <0x02100000 0x40000>; + interrupts = <0 105 0x04 0 106 0x04>; + }; + + aipstz@0217c000 { /* AIPSTZ2 */ + reg = <0x0217c000 0x4000>; + }; + + usbotg: usb@02184000 { + compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; + reg = <0x02184000 0x200>; + interrupts = <0 43 0x04>; + clocks = <&clks 162>; + fsl,usbphy = <&usbphy1>; + fsl,usbmisc = <&usbmisc 0>; + status = "disabled"; + }; + + usbh1: usb@02184200 { + compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; + reg = <0x02184200 0x200>; + interrupts = <0 40 0x04>; + clocks = <&clks 162>; + fsl,usbphy = <&usbphy2>; + fsl,usbmisc = <&usbmisc 1>; + status = "disabled"; + }; + + usbh2: usb@02184400 { + compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; + reg = <0x02184400 0x200>; + interrupts = <0 41 0x04>; + clocks = <&clks 162>; + fsl,usbmisc = <&usbmisc 2>; + status = "disabled"; + }; + + usbh3: usb@02184600 { + compatible = "fsl,imx6q-usb", "fsl,imx27-usb"; + reg = <0x02184600 0x200>; + interrupts = <0 42 0x04>; + clocks = <&clks 162>; + fsl,usbmisc = <&usbmisc 3>; + status = "disabled"; + }; + + usbmisc: usbmisc: usbmisc@02184800 { + #index-cells = <1>; + compatible = "fsl,imx6q-usbmisc"; + reg = <0x02184800 0x200>; + clocks = <&clks 162>; + }; + + fec: ethernet@02188000 { + compatible = "fsl,imx6q-fec"; + reg = <0x02188000 0x4000>; + interrupts = <0 118 0x04 0 119 0x04>; + clocks = <&clks 117>, <&clks 117>, <&clks 190>; + clock-names = "ipg", "ahb", "ptp"; + status = "disabled"; + }; + + mlb@0218c000 { + reg = <0x0218c000 0x4000>; + interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>; + }; + + usdhc1: usdhc@02190000 { + compatible = "fsl,imx6q-usdhc"; + reg = <0x02190000 0x4000>; + interrupts = <0 22 0x04>; + clocks = <&clks 163>, <&clks 163>, <&clks 163>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc2: usdhc@02194000 { + compatible = "fsl,imx6q-usdhc"; + reg = <0x02194000 0x4000>; + interrupts = <0 23 0x04>; + clocks = <&clks 164>, <&clks 164>, <&clks 164>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc3: usdhc@02198000 { + compatible = "fsl,imx6q-usdhc"; + reg = <0x02198000 0x4000>; + interrupts = <0 24 0x04>; + clocks = <&clks 165>, <&clks 165>, <&clks 165>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + usdhc4: usdhc@0219c000 { + compatible = "fsl,imx6q-usdhc"; + reg = <0x0219c000 0x4000>; + interrupts = <0 25 0x04>; + clocks = <&clks 166>, <&clks 166>, <&clks 166>; + clock-names = "ipg", "ahb", "per"; + bus-width = <4>; + status = "disabled"; + }; + + i2c1: i2c@021a0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; + reg = <0x021a0000 0x4000>; + interrupts = <0 36 0x04>; + clocks = <&clks 125>; + status = "disabled"; + }; + + i2c2: i2c@021a4000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; + reg = <0x021a4000 0x4000>; + interrupts = <0 37 0x04>; + clocks = <&clks 126>; + status = "disabled"; + }; + + i2c3: i2c@021a8000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; + reg = <0x021a8000 0x4000>; + interrupts = <0 38 0x04>; + clocks = <&clks 127>; + status = "disabled"; + }; + + romcp@021ac000 { + reg = <0x021ac000 0x4000>; + }; + + mmdc0: mmdc@021b0000 { /* MMDC0 */ + compatible = "fsl,imx6q-mmdc"; + reg = <0x021b0000 0x4000>; + }; + + mmdc1: mmdc@021b4000 { /* MMDC1 */ + reg = <0x021b4000 0x4000>; + }; + + weim@021b8000 { + reg = <0x021b8000 0x4000>; + interrupts = <0 14 0x04>; + }; + + ocotp@021bc000 { + compatible = "fsl,imx6q-ocotp"; + reg = <0x021bc000 0x4000>; + }; + + ocotp@021c0000 { + reg = <0x021c0000 0x4000>; + interrupts = <0 21 0x04>; + }; + + tzasc@021d0000 { /* TZASC1 */ + reg = <0x021d0000 0x4000>; + interrupts = <0 108 0x04>; + }; + + tzasc@021d4000 { /* TZASC2 */ + reg = <0x021d4000 0x4000>; + interrupts = <0 109 0x04>; + }; + + audmux: audmux@021d8000 { + compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux"; + reg = <0x021d8000 0x4000>; + status = "disabled"; + }; + + mipi@021dc000 { /* MIPI-CSI */ + reg = <0x021dc000 0x4000>; + }; + + mipi@021e0000 { /* MIPI-DSI */ + reg = <0x021e0000 0x4000>; + }; + + vdoa@021e4000 { + reg = <0x021e4000 0x4000>; + interrupts = <0 18 0x04>; + }; + + uart2: serial@021e8000 { + compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021e8000 0x4000>; + interrupts = <0 27 0x04>; + clocks = <&clks 160>, <&clks 161>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart3: serial@021ec000 { + compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021ec000 0x4000>; + interrupts = <0 28 0x04>; + clocks = <&clks 160>, <&clks 161>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart4: serial@021f0000 { + compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021f0000 0x4000>; + interrupts = <0 29 0x04>; + clocks = <&clks 160>, <&clks 161>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + uart5: serial@021f4000 { + compatible = "fsl,imx6q-uart", "fsl,imx21-uart"; + reg = <0x021f4000 0x4000>; + interrupts = <0 30 0x04>; + clocks = <&clks 160>, <&clks 161>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + + ipu1: ipu@02400000 { + #crtc-cells = <1>; + compatible = "fsl,imx6q-ipu"; + reg = <0x02400000 0x400000>; + interrupts = <0 6 0x4 0 5 0x4>; + clocks = <&clks 130>, <&clks 131>, <&clks 132>; + clock-names = "bus", "di0", "di1"; + }; + }; +}; diff --git a/arch/arm/dts/mx28.dtsi b/arch/arm/dts/mx28.dtsi new file mode 100644 index 0000000000..a9bda8e2ec --- /dev/null +++ b/arch/arm/dts/mx28.dtsi @@ -0,0 +1,872 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + interrupt-parent = <&icoll>; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + saif0 = &saif0; + saif1 = &saif1; + serial0 = &auart0; + serial1 = &auart1; + serial2 = &auart2; + serial3 = &auart3; + serial4 = &auart4; + }; + + cpus { + cpu@0 { + compatible = "arm,arm926ejs"; + }; + }; + + apb@80000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80000000 0x80000>; + ranges; + + apbh@80000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80000000 0x3c900>; + ranges; + + icoll: interrupt-controller@80000000 { + compatible = "fsl,imx28-icoll", "fsl,mxs-icoll"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x80000000 0x2000>; + }; + + hsadc@80002000 { + reg = <0x80002000 0x2000>; + interrupts = <13 87>; + status = "disabled"; + }; + + dma-apbh@80004000 { + compatible = "fsl,imx28-dma-apbh"; + reg = <0x80004000 0x2000>; + }; + + perfmon@80006000 { + reg = <0x80006000 0x800>; + interrupts = <27>; + status = "disabled"; + }; + + gpmi-nand@8000c000 { + compatible = "fsl,imx28-gpmi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>; + reg-names = "gpmi-nand", "bch"; + interrupts = <88>, <41>; + interrupt-names = "gpmi-dma", "bch"; + fsl,gpmi-dma-channel = <4>; + status = "disabled"; + }; + + ssp0: ssp@80010000 { + reg = <0x80010000 0x2000>; + interrupts = <96 82>; + fsl,ssp-dma-channel = <0>; + status = "disabled"; + }; + + ssp1: ssp@80012000 { + reg = <0x80012000 0x2000>; + interrupts = <97 83>; + fsl,ssp-dma-channel = <1>; + status = "disabled"; + }; + + ssp2: ssp@80014000 { + reg = <0x80014000 0x2000>; + interrupts = <98 84>; + fsl,ssp-dma-channel = <2>; + status = "disabled"; + }; + + ssp3: ssp@80016000 { + reg = <0x80016000 0x2000>; + interrupts = <99 85>; + fsl,ssp-dma-channel = <3>; + status = "disabled"; + }; + + pinctrl@80018000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-pinctrl", "simple-bus"; + reg = <0x80018000 0x2000>; + + gpio0: gpio@0 { + compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; + interrupts = <127>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@1 { + compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; + interrupts = <126>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@2 { + compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; + interrupts = <125>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@3 { + compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; + interrupts = <124>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@4 { + compatible = "fsl,imx28-gpio", "fsl,mxs-gpio"; + interrupts = <123>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + duart_pins_a: duart@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3102 /* MX28_PAD_PWM0__DUART_RX */ + 0x3112 /* MX28_PAD_PWM1__DUART_TX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + duart_pins_b: duart@1 { + reg = <1>; + fsl,pinmux-ids = < + 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */ + 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + duart_4pins_a: duart-4pins@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3022 /* MX28_PAD_AUART0_CTS__DUART_RX */ + 0x3032 /* MX28_PAD_AUART0_RTS__DUART_TX */ + 0x3002 /* MX28_PAD_AUART0_RX__DUART_CTS */ + 0x3012 /* MX28_PAD_AUART0_TX__DUART_RTS */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + gpmi_pins_a: gpmi-nand@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x0000 /* MX28_PAD_GPMI_D00__GPMI_D0 */ + 0x0010 /* MX28_PAD_GPMI_D01__GPMI_D1 */ + 0x0020 /* MX28_PAD_GPMI_D02__GPMI_D2 */ + 0x0030 /* MX28_PAD_GPMI_D03__GPMI_D3 */ + 0x0040 /* MX28_PAD_GPMI_D04__GPMI_D4 */ + 0x0050 /* MX28_PAD_GPMI_D05__GPMI_D5 */ + 0x0060 /* MX28_PAD_GPMI_D06__GPMI_D6 */ + 0x0070 /* MX28_PAD_GPMI_D07__GPMI_D7 */ + 0x0100 /* MX28_PAD_GPMI_CE0N__GPMI_CE0N */ + 0x0140 /* MX28_PAD_GPMI_RDY0__GPMI_READY0 */ + 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */ + 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */ + 0x01a0 /* MX28_PAD_GPMI_ALE__GPMI_ALE */ + 0x01b0 /* MX28_PAD_GPMI_CLE__GPMI_CLE */ + 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + gpmi_status_cfg: gpmi-status-cfg { + fsl,pinmux-ids = < + 0x0180 /* MX28_PAD_GPMI_RDN__GPMI_RDN */ + 0x0190 /* MX28_PAD_GPMI_WRN__GPMI_WRN */ + 0x01c0 /* MX28_PAD_GPMI_RESETN__GPMI_RESETN */ + >; + fsl,drive-strength = <2>; + }; + + auart0_pins_a: auart0@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */ + 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */ + 0x3020 /* MX28_PAD_AUART0_CTS__AUART0_CTS */ + 0x3030 /* MX28_PAD_AUART0_RTS__AUART0_RTS */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + auart0_2pins_a: auart0-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3000 /* MX28_PAD_AUART0_RX__AUART0_RX */ + 0x3010 /* MX28_PAD_AUART0_TX__AUART0_TX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + auart1_pins_a: auart1@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */ + 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */ + 0x3060 /* MX28_PAD_AUART1_CTS__AUART1_CTS */ + 0x3070 /* MX28_PAD_AUART1_RTS__AUART1_RTS */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + auart1_2pins_a: auart1-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3040 /* MX28_PAD_AUART1_RX__AUART1_RX */ + 0x3050 /* MX28_PAD_AUART1_TX__AUART1_TX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + auart2_2pins_a: auart2-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2101 /* MX28_PAD_SSP2_SCK__AUART2_RX */ + 0x2111 /* MX28_PAD_SSP2_MOSI__AUART2_TX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + auart3_pins_a: auart3@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x30c0 /* MX28_PAD_AUART3_RX__AUART3_RX */ + 0x30d0 /* MX28_PAD_AUART3_TX__AUART3_TX */ + 0x30e0 /* MX28_PAD_AUART3_CTS__AUART3_CTS */ + 0x30f0 /* MX28_PAD_AUART3_RTS__AUART3_RTS */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + auart3_2pins_a: auart3-2pins@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2121 /* MX28_PAD_SSP2_MISO__AUART3_RX */ + 0x2131 /* MX28_PAD_SSP2_SS0__AUART3_TX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + mac0_pins_a: mac0@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x4000 /* MX28_PAD_ENET0_MDC__ENET0_MDC */ + 0x4010 /* MX28_PAD_ENET0_MDIO__ENET0_MDIO */ + 0x4020 /* MX28_PAD_ENET0_RX_EN__ENET0_RX_EN */ + 0x4030 /* MX28_PAD_ENET0_RXD0__ENET0_RXD0 */ + 0x4040 /* MX28_PAD_ENET0_RXD1__ENET0_RXD1 */ + 0x4060 /* MX28_PAD_ENET0_TX_EN__ENET0_TX_EN */ + 0x4070 /* MX28_PAD_ENET0_TXD0__ENET0_TXD0 */ + 0x4080 /* MX28_PAD_ENET0_TXD1__ENET0_TXD1 */ + 0x4100 /* MX28_PAD_ENET_CLK__CLKCTRL_ENET */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + + mac1_pins_a: mac1@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x40f1 /* MX28_PAD_ENET0_CRS__ENET1_RX_EN */ + 0x4091 /* MX28_PAD_ENET0_RXD2__ENET1_RXD0 */ + 0x40a1 /* MX28_PAD_ENET0_RXD3__ENET1_RXD1 */ + 0x40e1 /* MX28_PAD_ENET0_COL__ENET1_TX_EN */ + 0x40b1 /* MX28_PAD_ENET0_TXD2__ENET1_TXD0 */ + 0x40c1 /* MX28_PAD_ENET0_TXD3__ENET1_TXD1 */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + + mmc0_8bit_pins_a: mmc0-8bit@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */ + 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */ + 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */ + 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */ + 0x2040 /* MX28_PAD_SSP0_DATA4__SSP0_D4 */ + 0x2050 /* MX28_PAD_SSP0_DATA5__SSP0_D5 */ + 0x2060 /* MX28_PAD_SSP0_DATA6__SSP0_D6 */ + 0x2070 /* MX28_PAD_SSP0_DATA7__SSP0_D7 */ + 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */ + 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ + 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + + mmc0_4bit_pins_a: mmc0-4bit@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2000 /* MX28_PAD_SSP0_DATA0__SSP0_D0 */ + 0x2010 /* MX28_PAD_SSP0_DATA1__SSP0_D1 */ + 0x2020 /* MX28_PAD_SSP0_DATA2__SSP0_D2 */ + 0x2030 /* MX28_PAD_SSP0_DATA3__SSP0_D3 */ + 0x2080 /* MX28_PAD_SSP0_CMD__SSP0_CMD */ + 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ + 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + + mmc0_cd_cfg: mmc0-cd-cfg { + fsl,pinmux-ids = < + 0x2090 /* MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT */ + >; + fsl,pull-up = <0>; + }; + + mmc0_sck_cfg: mmc0-sck-cfg { + fsl,pinmux-ids = < + 0x20a0 /* MX28_PAD_SSP0_SCK__SSP0_SCK */ + >; + fsl,drive-strength = <2>; + fsl,pull-up = <0>; + }; + + i2c0_pins_a: i2c0@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3180 /* MX28_PAD_I2C0_SCL__I2C0_SCL */ + 0x3190 /* MX28_PAD_I2C0_SDA__I2C0_SDA */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + + i2c0_pins_b: i2c0@1 { + reg = <1>; + fsl,pinmux-ids = < + 0x3001 /* MX28_PAD_AUART0_RX__I2C0_SCL */ + 0x3011 /* MX28_PAD_AUART0_TX__I2C0_SDA */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + + i2c1_pins_a: i2c1@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3101 /* MX28_PAD_PWM0__I2C1_SCL */ + 0x3111 /* MX28_PAD_PWM1__I2C1_SDA */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + + saif0_pins_a: saif0@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3140 /* MX28_PAD_SAIF0_MCLK__SAIF0_MCLK */ + 0x3150 /* MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK */ + 0x3160 /* MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK */ + 0x3170 /* MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 */ + >; + fsl,drive-strength = <2>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + + saif1_pins_a: saif1@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x31a0 /* MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 */ + >; + fsl,drive-strength = <2>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + + pwm0_pins_a: pwm0@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3100 /* MX28_PAD_PWM0__PWM_0 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + pwm2_pins_a: pwm2@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x3120 /* MX28_PAD_PWM2__PWM_2 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + pwm4_pins_a: pwm4@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x31d0 /* MX28_PAD_PWM4__PWM_4 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + lcdif_24bit_pins_a: lcdif-24bit@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x1000 /* MX28_PAD_LCD_D00__LCD_D0 */ + 0x1010 /* MX28_PAD_LCD_D01__LCD_D1 */ + 0x1020 /* MX28_PAD_LCD_D02__LCD_D2 */ + 0x1030 /* MX28_PAD_LCD_D03__LCD_D3 */ + 0x1040 /* MX28_PAD_LCD_D04__LCD_D4 */ + 0x1050 /* MX28_PAD_LCD_D05__LCD_D5 */ + 0x1060 /* MX28_PAD_LCD_D06__LCD_D6 */ + 0x1070 /* MX28_PAD_LCD_D07__LCD_D7 */ + 0x1080 /* MX28_PAD_LCD_D08__LCD_D8 */ + 0x1090 /* MX28_PAD_LCD_D09__LCD_D9 */ + 0x10a0 /* MX28_PAD_LCD_D10__LCD_D10 */ + 0x10b0 /* MX28_PAD_LCD_D11__LCD_D11 */ + 0x10c0 /* MX28_PAD_LCD_D12__LCD_D12 */ + 0x10d0 /* MX28_PAD_LCD_D13__LCD_D13 */ + 0x10e0 /* MX28_PAD_LCD_D14__LCD_D14 */ + 0x10f0 /* MX28_PAD_LCD_D15__LCD_D15 */ + 0x1100 /* MX28_PAD_LCD_D16__LCD_D16 */ + 0x1110 /* MX28_PAD_LCD_D17__LCD_D17 */ + 0x1120 /* MX28_PAD_LCD_D18__LCD_D18 */ + 0x1130 /* MX28_PAD_LCD_D19__LCD_D19 */ + 0x1140 /* MX28_PAD_LCD_D20__LCD_D20 */ + 0x1150 /* MX28_PAD_LCD_D21__LCD_D21 */ + 0x1160 /* MX28_PAD_LCD_D22__LCD_D22 */ + 0x1170 /* MX28_PAD_LCD_D23__LCD_D23 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + can0_pins_a: can0@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x0161 /* MX28_PAD_GPMI_RDY2__CAN0_TX */ + 0x0171 /* MX28_PAD_GPMI_RDY3__CAN0_RX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + can1_pins_a: can1@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x0121 /* MX28_PAD_GPMI_CE2N__CAN1_TX */ + 0x0131 /* MX28_PAD_GPMI_CE3N__CAN1_RX */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + spi2_pins_a: spi2@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2100 /* MX28_PAD_SSP2_SCK__SSP2_SCK */ + 0x2110 /* MX28_PAD_SSP2_MOSI__SSP2_CMD */ + 0x2120 /* MX28_PAD_SSP2_MISO__SSP2_D0 */ + 0x2130 /* MX28_PAD_SSP2_SS0__SSP2_D3 */ + >; + fsl,drive-strength = <1>; + fsl,voltage = <1>; + fsl,pull-up = <1>; + }; + + usbphy0_pins_a: usbphy0@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2152 /* MX28_PAD_SSP2_SS2__USB0_OVERCURRENT */ + >; + fsl,drive-strength = <2>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + usbphy0_pins_b: usbphy0@1 { + reg = <1>; + fsl,pinmux-ids = < + 0x3061 /* MX28_PAD_AUART1_CTS__USB0_OVERCURRENT */ + >; + fsl,drive-strength = <2>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + usbphy1_pins_a: usbphy1@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x2142 /* MX28_PAD_SSP2_SS1__USB1_OVERCURRENT */ + >; + fsl,drive-strength = <2>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; + + digctl@8001c000 { + reg = <0x8001c000 0x2000>; + interrupts = <89>; + status = "disabled"; + }; + + etm@80022000 { + reg = <0x80022000 0x2000>; + status = "disabled"; + }; + + dma-apbx@80024000 { + compatible = "fsl,imx28-dma-apbx"; + reg = <0x80024000 0x2000>; + }; + + dcp@80028000 { + reg = <0x80028000 0x2000>; + interrupts = <52 53 54>; + status = "disabled"; + }; + + pxp@8002a000 { + reg = <0x8002a000 0x2000>; + interrupts = <39>; + status = "disabled"; + }; + + ocotp@8002c000 { + reg = <0x8002c000 0x2000>; + status = "disabled"; + }; + + axi-ahb@8002e000 { + reg = <0x8002e000 0x2000>; + status = "disabled"; + }; + + lcdif@80030000 { + compatible = "fsl,imx28-lcdif"; + reg = <0x80030000 0x2000>; + interrupts = <38 86>; + status = "disabled"; + }; + + can0: can@80032000 { + compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; + reg = <0x80032000 0x2000>; + interrupts = <8>; + status = "disabled"; + }; + + can1: can@80034000 { + compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan"; + reg = <0x80034000 0x2000>; + interrupts = <9>; + status = "disabled"; + }; + + simdbg@8003c000 { + reg = <0x8003c000 0x200>; + status = "disabled"; + }; + + simgpmisel@8003c200 { + reg = <0x8003c200 0x100>; + status = "disabled"; + }; + + simsspsel@8003c300 { + reg = <0x8003c300 0x100>; + status = "disabled"; + }; + + simmemsel@8003c400 { + reg = <0x8003c400 0x100>; + status = "disabled"; + }; + + gpiomon@8003c500 { + reg = <0x8003c500 0x100>; + status = "disabled"; + }; + + simenet@8003c700 { + reg = <0x8003c700 0x100>; + status = "disabled"; + }; + + armjtag@8003c800 { + reg = <0x8003c800 0x100>; + status = "disabled"; + }; + }; + + apbx@80040000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80040000 0x40000>; + ranges; + + clkctl@80040000 { + reg = <0x80040000 0x2000>; + status = "disabled"; + }; + + saif0: saif@80042000 { + compatible = "fsl,imx28-saif"; + reg = <0x80042000 0x2000>; + interrupts = <59 80>; + fsl,saif-dma-channel = <4>; + status = "disabled"; + }; + + power@80044000 { + reg = <0x80044000 0x2000>; + status = "disabled"; + }; + + saif1: saif@80046000 { + compatible = "fsl,imx28-saif"; + reg = <0x80046000 0x2000>; + interrupts = <58 81>; + fsl,saif-dma-channel = <5>; + status = "disabled"; + }; + + lradc@80050000 { + compatible = "fsl,imx28-lradc"; + reg = <0x80050000 0x2000>; + interrupts = <10 14 15 16 17 18 19 + 20 21 22 23 24 25>; + status = "disabled"; + }; + + spdif@80054000 { + reg = <0x80054000 0x2000>; + interrupts = <45 66>; + status = "disabled"; + }; + + rtc@80056000 { + compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc"; + reg = <0x80056000 0x2000>; + interrupts = <29>; + }; + + i2c0: i2c@80058000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-i2c"; + reg = <0x80058000 0x2000>; + interrupts = <111 68>; + clock-frequency = <100000>; + status = "disabled"; + }; + + i2c1: i2c@8005a000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx28-i2c"; + reg = <0x8005a000 0x2000>; + interrupts = <110 69>; + clock-frequency = <100000>; + status = "disabled"; + }; + + pwm: pwm@80064000 { + compatible = "fsl,imx28-pwm", "fsl,imx23-pwm"; + reg = <0x80064000 0x2000>; + #pwm-cells = <2>; + fsl,pwm-number = <8>; + status = "disabled"; + }; + + timrot@80068000 { + reg = <0x80068000 0x2000>; + status = "disabled"; + }; + + auart0: serial@8006a000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; + reg = <0x8006a000 0x2000>; + interrupts = <112 70 71>; + status = "disabled"; + }; + + auart1: serial@8006c000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; + reg = <0x8006c000 0x2000>; + interrupts = <113 72 73>; + status = "disabled"; + }; + + auart2: serial@8006e000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; + reg = <0x8006e000 0x2000>; + interrupts = <114 74 75>; + status = "disabled"; + }; + + auart3: serial@80070000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; + reg = <0x80070000 0x2000>; + interrupts = <115 76 77>; + status = "disabled"; + }; + + auart4: serial@80072000 { + compatible = "fsl,imx28-auart", "fsl,imx23-auart"; + reg = <0x80072000 0x2000>; + interrupts = <116 78 79>; + status = "disabled"; + }; + + duart: serial@80074000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0x80074000 0x1000>; + interrupts = <47>; + status = "disabled"; + }; + + usbphy0: usbphy@8007c000 { + compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; + reg = <0x8007c000 0x2000>; + status = "disabled"; + }; + + usbphy1: usbphy@8007e000 { + compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy"; + reg = <0x8007e000 0x2000>; + status = "disabled"; + }; + }; + }; + + ahb@80080000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80080000 0x80000>; + ranges; + + usb0: usb@80080000 { + compatible = "fsl,imx28-usb", "fsl,imx27-usb"; + reg = <0x80080000 0x10000>; + interrupts = <93>; + fsl,usbphy = <&usbphy0>; + status = "disabled"; + }; + + usb1: usb@80090000 { + compatible = "fsl,imx28-usb", "fsl,imx27-usb"; + reg = <0x80090000 0x10000>; + interrupts = <92>; + fsl,usbphy = <&usbphy1>; + status = "disabled"; + }; + + dflpt@800c0000 { + reg = <0x800c0000 0x10000>; + status = "disabled"; + }; + + mac0: ethernet@800f0000 { + compatible = "fsl,imx28-fec"; + reg = <0x800f0000 0x4000>; + interrupts = <101>; + status = "disabled"; + }; + + mac1: ethernet@800f4000 { + compatible = "fsl,imx28-fec"; + reg = <0x800f4000 0x4000>; + interrupts = <102>; + status = "disabled"; + }; + + switch@800f8000 { + reg = <0x800f8000 0x8000>; + status = "disabled"; + }; + + }; +}; diff --git a/arch/arm/dts/mx51.dtsi b/arch/arm/dts/mx51.dtsi new file mode 100644 index 0000000000..3688f31d4a --- /dev/null +++ b/arch/arm/dts/mx51.dtsi @@ -0,0 +1,476 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + ethernet0 = &fec0; + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + gpio3 = &gpio4; + }; + + tzic: tz-interrupt-controller@e0000000 { + compatible = "fsl,imx51-tzic", "fsl,tzic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0xe0000000 0x4000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ckil { + compatible = "fsl,imx-ckil", "fixed-clock"; + clock-frequency = <32768>; + }; + + ckih1 { + compatible = "fsl,imx-ckih1", "fixed-clock"; + clock-frequency = <22579200>; + }; + + ckih2 { + compatible = "fsl,imx-ckih2", "fixed-clock"; + clock-frequency = <0>; + }; + + osc { + compatible = "fsl,imx-osc", "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&tzic>; + ranges; + + ahb: ahb@40000000 { + compatible = "fsl,ahb-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x40000000 0x60000000>; + ranges; + + ipu@5e000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx-ipuv3"; + reg = <0x5e000000 0x02000000>; + interrupts = <10 11>; + status = "disabled"; + }; + }; + + aips@70000000 { /* AIPS1 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x70000000 0x10000000>; + ranges; + + spba@70000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x70000000 0x40000>; + ranges; + + esdhc@70004000 { /* ESDHC1 */ + compatible = "fsl,imx51-esdhc"; + reg = <0x70004000 0x4000>; + interrupts = <1>; + status = "disabled"; + }; + + esdhc@70008000 { /* ESDHC2 */ + compatible = "fsl,imx51-esdhc"; + reg = <0x70008000 0x4000>; + interrupts = <2>; + status = "disabled"; + }; + + uart3: serial@7000c000 { + compatible = "fsl,imx51-uart", "fsl,imx21-uart"; + reg = <0x7000c000 0x4000>; + interrupts = <33>; + status = "disabled"; + }; + + ecspi@70010000 { /* ECSPI1 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx51-ecspi"; + reg = <0x70010000 0x4000>; + interrupts = <36>; + status = "disabled"; + }; + + ssi2: ssi@70014000 { + compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; + reg = <0x70014000 0x4000>; + interrupts = <30>; + fsl,fifo-depth = <15>; + fsl,ssi-dma-events = <25 24 23 22>; /* TX0 RX0 TX1 RX1 */ + status = "disabled"; + }; + + esdhc@70020000 { /* ESDHC3 */ + compatible = "fsl,imx51-esdhc"; + reg = <0x70020000 0x4000>; + interrupts = <3>; + status = "disabled"; + }; + + esdhc@70024000 { /* ESDHC4 */ + compatible = "fsl,imx51-esdhc"; + reg = <0x70024000 0x4000>; + interrupts = <4>; + status = "disabled"; + }; + }; + + usb@73f80000 { + compatible = "fsl,imx51-usb", "fsl,imx27-usb"; + reg = <0x73f80000 0x0200>; + interrupts = <18>; + status = "disabled"; + }; + + usb@73f80200 { + compatible = "fsl,imx51-usb", "fsl,imx27-usb"; + reg = <0x73f80200 0x0200>; + interrupts = <14>; + status = "disabled"; + }; + + usb@73f80400 { + compatible = "fsl,imx51-usb", "fsl,imx27-usb"; + reg = <0x73f80400 0x0200>; + interrupts = <16>; + status = "disabled"; + }; + + usb@73f80600 { + compatible = "fsl,imx51-usb", "fsl,imx27-usb"; + reg = <0x73f80600 0x0200>; + interrupts = <17>; + status = "disabled"; + }; + + gpio1: gpio@73f84000 { + compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; + reg = <0x73f84000 0x4000>; + interrupts = <50 51>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@73f88000 { + compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; + reg = <0x73f88000 0x4000>; + interrupts = <52 53>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@73f8c000 { + compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; + reg = <0x73f8c000 0x4000>; + interrupts = <54 55>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@73f90000 { + compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; + reg = <0x73f90000 0x4000>; + interrupts = <56 57>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + keypad@73f94000 { + compatible = "fsl,imx-keypad"; + reg = <0x73f94000 0x4000>; + interrupts = <60>; + status = "disabled"; + }; + + wdog@73f98000 { /* WDOG1 */ + compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; + reg = <0x73f98000 0x4000>; + interrupts = <58>; + status = "disabled"; + }; + + wdog@73f9c000 { /* WDOG2 */ + compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; + reg = <0x73f9c000 0x4000>; + interrupts = <59>; + status = "disabled"; + }; + + iomuxc@73fa8000 { + compatible = "fsl,imx51-iomuxc"; + reg = <0x73fa8000 0x4000>; + + audmux { + pinctrl_audmux_1: audmuxgrp-1 { + fsl,pins = < + 384 0x80000000 /* MX51_PAD_AUD3_BB_TXD__AUD3_TXD */ + 386 0x80000000 /* MX51_PAD_AUD3_BB_RXD__AUD3_RXD */ + 389 0x80000000 /* MX51_PAD_AUD3_BB_CK__AUD3_TXC */ + 391 0x80000000 /* MX51_PAD_AUD3_BB_FS__AUD3_TXFS */ + >; + }; + }; + + fec { + pinctrl_fec_1: fecgrp-1 { + fsl,pins = < + 128 0x80000000 /* MX51_PAD_EIM_EB2__FEC_MDIO */ + 134 0x80000000 /* MX51_PAD_EIM_EB3__FEC_RDATA1 */ + 146 0x80000000 /* MX51_PAD_EIM_CS2__FEC_RDATA2 */ + 152 0x80000000 /* MX51_PAD_EIM_CS3__FEC_RDATA3 */ + 158 0x80000000 /* MX51_PAD_EIM_CS4__FEC_RX_ER */ + 165 0x80000000 /* MX51_PAD_EIM_CS5__FEC_CRS */ + 206 0x80000000 /* MX51_PAD_NANDF_RB2__FEC_COL */ + 213 0x80000000 /* MX51_PAD_NANDF_RB3__FEC_RX_CLK */ + 293 0x80000000 /* MX51_PAD_NANDF_D9__FEC_RDATA0 */ + 298 0x80000000 /* MX51_PAD_NANDF_D8__FEC_TDATA0 */ + 225 0x80000000 /* MX51_PAD_NANDF_CS2__FEC_TX_ER */ + 231 0x80000000 /* MX51_PAD_NANDF_CS3__FEC_MDC */ + 237 0x80000000 /* MX51_PAD_NANDF_CS4__FEC_TDATA1 */ + 243 0x80000000 /* MX51_PAD_NANDF_CS5__FEC_TDATA2 */ + 250 0x80000000 /* MX51_PAD_NANDF_CS6__FEC_TDATA3 */ + 255 0x80000000 /* MX51_PAD_NANDF_CS7__FEC_TX_EN */ + 260 0x80000000 /* MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK */ + >; + }; + }; + + ecspi1 { + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + 398 0x185 /* MX51_PAD_CSPI1_MISO__ECSPI1_MISO */ + 394 0x185 /* MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI */ + 409 0x185 /* MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK */ + >; + }; + }; + + esdhc1 { + pinctrl_esdhc1_1: esdhc1grp-1 { + fsl,pins = < + 666 0x400020d5 /* MX51_PAD_SD1_CMD__SD1_CMD */ + 669 0x20d5 /* MX51_PAD_SD1_CLK__SD1_CLK */ + 672 0x20d5 /* MX51_PAD_SD1_DATA0__SD1_DATA0 */ + 678 0x20d5 /* MX51_PAD_SD1_DATA1__SD1_DATA1 */ + 684 0x20d5 /* MX51_PAD_SD1_DATA2__SD1_DATA2 */ + 691 0x20d5 /* MX51_PAD_SD1_DATA3__SD1_DATA3 */ + >; + }; + }; + + esdhc2 { + pinctrl_esdhc2_1: esdhc2grp-1 { + fsl,pins = < + 704 0x400020d5 /* MX51_PAD_SD2_CMD__SD2_CMD */ + 707 0x20d5 /* MX51_PAD_SD2_CLK__SD2_CLK */ + 710 0x20d5 /* MX51_PAD_SD2_DATA0__SD2_DATA0 */ + 712 0x20d5 /* MX51_PAD_SD2_DATA1__SD2_DATA1 */ + 715 0x20d5 /* MX51_PAD_SD2_DATA2__SD2_DATA2 */ + 719 0x20d5 /* MX51_PAD_SD2_DATA3__SD2_DATA3 */ + >; + }; + }; + + i2c2 { + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + 449 0x400001ed /* MX51_PAD_KEY_COL4__I2C2_SCL */ + 454 0x400001ed /* MX51_PAD_KEY_COL5__I2C2_SDA */ + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + 413 0x1c5 /* MX51_PAD_UART1_RXD__UART1_RXD */ + 416 0x1c5 /* MX51_PAD_UART1_TXD__UART1_TXD */ + 418 0x1c5 /* MX51_PAD_UART1_RTS__UART1_RTS */ + 420 0x1c5 /* MX51_PAD_UART1_CTS__UART1_CTS */ + >; + }; + }; + + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + 423 0x1c5 /* MX51_PAD_UART2_RXD__UART2_RXD */ + 426 0x1c5 /* MX51_PAD_UART2_TXD__UART2_TXD */ + >; + }; + }; + + uart3 { + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + 54 0x1c5 /* MX51_PAD_EIM_D25__UART3_RXD */ + 59 0x1c5 /* MX51_PAD_EIM_D26__UART3_TXD */ + 65 0x1c5 /* MX51_PAD_EIM_D27__UART3_RTS */ + 49 0x1c5 /* MX51_PAD_EIM_D24__UART3_CTS */ + >; + }; + }; + }; + + pwm@73fb4000 { + compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; + reg = <0x73fb4000 0x4000>; + interrupts = <61>; + status = "disabled"; + }; + + pwm@73fb8000 { + compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; + reg = <0x73fb8000 0x4000>; + interrupts = <94>; + status = "disabled"; + }; + + uart1: serial@73fbc000 { + compatible = "fsl,imx51-uart", "fsl,imx21-uart"; + reg = <0x73fbc000 0x4000>; + interrupts = <31>; + status = "disabled"; + }; + + uart2: serial@73fc0000 { + compatible = "fsl,imx51-uart", "fsl,imx21-uart"; + reg = <0x73fc0000 0x4000>; + interrupts = <32>; + status = "disabled"; + }; + }; + + aips@80000000 { /* AIPS2 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x80000000 0x10000000>; + ranges; + + ecspi@83fac000 { /* ECSPI2 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx51-ecspi"; + reg = <0x83fac000 0x4000>; + interrupts = <37>; + status = "disabled"; + }; + + sdma@83fb0000 { + compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; + reg = <0x83fb0000 0x4000>; + interrupts = <6>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; + }; + + cspi@83fc0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; + reg = <0x83fc0000 0x4000>; + interrupts = <38>; + status = "disabled"; + }; + + i2c@83fc4000 { /* I2C2 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx51-i2c", "fsl,imx1-i2c"; + reg = <0x83fc4000 0x4000>; + interrupts = <63>; + status = "disabled"; + }; + + i2c@83fc8000 { /* I2C1 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx51-i2c", "fsl,imx1-i2c"; + reg = <0x83fc8000 0x4000>; + interrupts = <62>; + status = "disabled"; + }; + + ssi1: ssi@83fcc000 { + compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; + reg = <0x83fcc000 0x4000>; + interrupts = <29>; + fsl,fifo-depth = <15>; + fsl,ssi-dma-events = <29 28 27 26>; /* TX0 RX0 TX1 RX1 */ + status = "disabled"; + }; + + audmux@83fd0000 { + compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; + reg = <0x83fd0000 0x4000>; + ssi-ports = <0 1 2>; + ext-ports = <3 4 5 6>; + status = "disabled"; + }; + + nand@83fdb000 { + compatible = "fsl,imx51-nand"; + reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; + interrupts = <8>; + status = "disabled"; + }; + + ssi3: ssi@83fe8000 { + compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; + reg = <0x83fe8000 0x4000>; + interrupts = <96>; + fsl,fifo-depth = <15>; + fsl,ssi-dma-events = <47 46 37 35>; /* TX0 RX0 TX1 RX1 */ + status = "disabled"; + }; + + fec0: ethernet@83fec000 { + compatible = "fsl,imx51-fec", "fsl,imx27-fec"; + reg = <0x83fec000 0x4000>; + interrupts = <87>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/dts/mx53.dtsi b/arch/arm/dts/mx53.dtsi new file mode 100644 index 0000000000..e726be0f72 --- /dev/null +++ b/arch/arm/dts/mx53.dtsi @@ -0,0 +1,615 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/include/ "skeleton.dtsi" + +/ { + aliases { + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + gpio4 = &gpio4; + gpio5 = &gpio5; + gpio6 = &gpio6; + gpio7 = &gpio7; + }; + + tzic: tz-interrupt-controller@0fffc000 { + compatible = "fsl,imx53-tzic", "fsl,tzic"; + interrupt-controller; + #interrupt-cells = <1>; + reg = <0x0fffc000 0x4000>; + }; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + ckil { + compatible = "fsl,imx-ckil", "fixed-clock"; + clock-frequency = <32768>; + }; + + ckih1 { + compatible = "fsl,imx-ckih1", "fixed-clock"; + clock-frequency = <22579200>; + }; + + ckih2 { + compatible = "fsl,imx-ckih2", "fixed-clock"; + clock-frequency = <0>; + }; + + osc { + compatible = "fsl,imx-osc", "fixed-clock"; + clock-frequency = <24000000>; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + interrupt-parent = <&tzic>; + ranges; + + extmc@00000000 { + compatible = "fsl,extmc", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x00000000 0x40000000>; + ranges; + + sata@10000000 { + compatible = "fsl,imx53-sata", "fsl,imx-ahci"; + reg = <0x10000000 0x00004000>; + interrupts = <28>; + status = "disabled"; + }; + + ipu@1e000000 { + compatible = "fsl,imx-ipuv3"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1e000000 0x02000000>; + interrupts = <10 11>; + status = "disabled"; + }; + }; + + aips@50000000 { /* AIPS1 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x50000000 0x10000000>; + ranges; + + spba@50000000 { + compatible = "fsl,spba-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x50000000 0x40000>; + ranges; + + esdhc@50004000 { /* ESDHC1 */ + compatible = "fsl,imx53-esdhc"; + reg = <0x50004000 0x4000>; + interrupts = <1>; + status = "disabled"; + }; + + esdhc@50008000 { /* ESDHC2 */ + compatible = "fsl,imx53-esdhc"; + reg = <0x50008000 0x4000>; + interrupts = <2>; + status = "disabled"; + }; + + uart3: uart@5000c000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x5000c000 0x4000>; + interrupts = <33>; + status = "disabled"; + }; + + ecspi@50010000 { /* ECSPI1 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; + reg = <0x50010000 0x4000>; + interrupts = <36>; + status = "disabled"; + }; + + ssi2: ssi@50014000 { + compatible = "fsl,imx-ssi"; + reg = <0x50014000 0x4000>; + interrupts = <30>; + status = "disabled"; + }; + + esdhc@50020000 { /* ESDHC3 */ + compatible = "fsl,imx53-esdhc"; + reg = <0x50020000 0x4000>; + interrupts = <3>; + status = "disabled"; + }; + + esdhc@50024000 { /* ESDHC4 */ + compatible = "fsl,imx53-esdhc"; + reg = <0x50024000 0x4000>; + interrupts = <4>; + status = "disabled"; + }; + }; + + imxotg@53f80000 { + compatible = "fsl,imx-otg"; + reg = <0x53f80000 0x200>; + interrupts = <18>; + status = "disabled"; + + phy-mode = "utmi-wide"; + host-device-name = "mxc-ehci"; + host-device-id = <0>; + gadget-device-name = "fsl-usb2-udc"; + }; + + imxotg@53f80200 { + compatible = "fsl,imx-otg"; + reg = <0x53f80200 0x200>; + interrupts = <14>; + status = "disabled"; + + phy-mode = "utmi-wide"; + host-device-name = "mxc-ehci"; + host-device-id = <1>; + }; + + mxc-ehci@53f80400 { + compatible = "fsl,mxc-ehci"; + reg = <0x53f80400 0x200>; + interrupts = <16>; + status = "disabled"; + }; + + mxc-ehci@53f80600 { + compatible = "fsl,mxc-ehci"; + reg = <0x53f80600 0x200>; + interrupts = <17>; + status = "disabled"; + }; + + imx-usb-phy@53f80800 { + compatible = "fsl,imx53-usb-phy", "fsl,imx-usb-phy"; + reg = <0x53f80800 0x200>; + status = "disabled"; + }; + + gpio1: gpio@53f84000 { + compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; + reg = <0x53f84000 0x4000>; + interrupts = <50 51>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio2: gpio@53f88000 { + compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; + reg = <0x53f88000 0x4000>; + interrupts = <52 53>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio3: gpio@53f8c000 { + compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; + reg = <0x53f8c000 0x4000>; + interrupts = <54 55>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio4: gpio@53f90000 { + compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; + reg = <0x53f90000 0x4000>; + interrupts = <56 57>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + keypad@53f94000 { + compatible = "fsl,imx-keypad"; + reg = <0x53f94000 0x4000>; + interrupts = <60>; + status = "disabled"; + }; + + wdog@53f98000 { /* WDOG1 */ + compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; + reg = <0x53f98000 0x4000>; + interrupts = <58>; + status = "disabled"; + }; + + wdog@53f9c000 { /* WDOG2 */ + compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; + reg = <0x53f9c000 0x4000>; + interrupts = <59>; + status = "disabled"; + }; + + iomuxc@53fa8000 { + compatible = "fsl,imx53-iomuxc"; + reg = <0x53fa8000 0x4000>; + + audmux { + pinctrl_audmux_1: audmuxgrp-1 { + fsl,pins = < + 10 0x80 /* MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC */ + 17 0x80 /* MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD */ + 23 0x80 /* MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS */ + 30 0x80 /* MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD */ + >; + }; + }; + + fec { + pinctrl_fec_1: fecgrp-1 { + fsl,pins = < + 820 0x80 /* MX53_PAD_FEC_MDC__FEC_MDC */ + 779 0x80 /* MX53_PAD_FEC_MDIO__FEC_MDIO */ + 786 0x80 /* MX53_PAD_FEC_REF_CLK__FEC_TX_CLK */ + 791 0x80 /* MX53_PAD_FEC_RX_ER__FEC_RX_ER */ + 796 0x80 /* MX53_PAD_FEC_CRS_DV__FEC_RX_DV */ + 799 0x80 /* MX53_PAD_FEC_RXD1__FEC_RDATA_1 */ + 804 0x80 /* MX53_PAD_FEC_RXD0__FEC_RDATA_0 */ + 808 0x80 /* MX53_PAD_FEC_TX_EN__FEC_TX_EN */ + 811 0x80 /* MX53_PAD_FEC_TXD1__FEC_TDATA_1 */ + 816 0x80 /* MX53_PAD_FEC_TXD0__FEC_TDATA_0 */ + >; + }; + }; + + ecspi1 { + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + 433 0x80 /* MX53_PAD_EIM_D16__ECSPI1_SCLK */ + 439 0x80 /* MX53_PAD_EIM_D17__ECSPI1_MISO */ + 445 0x80 /* MX53_PAD_EIM_D18__ECSPI1_MOSI */ + >; + }; + }; + + esdhc1 { + pinctrl_esdhc1_1: esdhc1grp-1 { + fsl,pins = < + 995 0x1d4 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ + 1000 0x1d4 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ + 1010 0x1d4 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ + 1024 0x1c4 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ + 1005 0x1d4 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ + 1018 0x1d4 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ + >; + }; + + pinctrl_esdhc1_2: esdhc1grp-2 { + fsl,pins = < + 995 0x1d4 /* MX53_PAD_SD1_DATA0__ESDHC1_DAT0 */ + 1000 0x1d4 /* MX53_PAD_SD1_DATA1__ESDHC1_DAT1 */ + 1010 0x1d4 /* MX53_PAD_SD1_DATA2__ESDHC1_DAT2 */ + 1024 0x1c4 /* MX53_PAD_SD1_DATA3__ESDHC1_DAT3 */ + 941 0x1d4 /* MX53_PAD_PATA_DATA8__ESDHC1_DAT4 */ + 948 0x1d4 /* MX53_PAD_PATA_DATA9__ESDHC1_DAT5 */ + 955 0x1d4 /* MX53_PAD_PATA_DATA10__ESDHC1_DAT6 */ + 962 0x1d4 /* MX53_PAD_PATA_DATA11__ESDHC1_DAT7 */ + 1005 0x1d4 /* MX53_PAD_SD1_CMD__ESDHC1_CMD */ + 1018 0x1d4 /* MX53_PAD_SD1_CLK__ESDHC1_CLK */ + >; + }; + }; + + esdhc2 { + pinctrl_esdhc2_1: esdhc2grp-1 { + fsl,pins = < + 1038 0x1d5 /* MX53_PAD_SD2_CMD__ESDHC2_CMD */ + 1032 0x1d5 /* MX53_PAD_SD2_CLK__ESDHC2_CLK */ + 1062 0x1d5 /* MX53_PAD_SD2_DATA0__ESDHC2_DAT0 */ + 1056 0x1d5 /* MX53_PAD_SD2_DATA1__ESDHC2_DAT1 */ + 1050 0x1d5 /* MX53_PAD_SD2_DATA2__ESDHC2_DAT2 */ + 1044 0x1d5 /* MX53_PAD_SD2_DATA3__ESDHC2_DAT3 */ + >; + }; + }; + + esdhc3 { + pinctrl_esdhc3_1: esdhc3grp-1 { + fsl,pins = < + 943 0x1d5 /* MX53_PAD_PATA_DATA8__ESDHC3_DAT0 */ + 950 0x1d5 /* MX53_PAD_PATA_DATA9__ESDHC3_DAT1 */ + 957 0x1d5 /* MX53_PAD_PATA_DATA10__ESDHC3_DAT2 */ + 964 0x1d5 /* MX53_PAD_PATA_DATA11__ESDHC3_DAT3 */ + 893 0x1d5 /* MX53_PAD_PATA_DATA0__ESDHC3_DAT4 */ + 900 0x1d5 /* MX53_PAD_PATA_DATA1__ESDHC3_DAT5 */ + 906 0x1d5 /* MX53_PAD_PATA_DATA2__ESDHC3_DAT6 */ + 912 0x1d5 /* MX53_PAD_PATA_DATA3__ESDHC3_DAT7 */ + 857 0x1d5 /* MX53_PAD_PATA_RESET_B__ESDHC3_CMD */ + 863 0x1d5 /* MX53_PAD_PATA_IORDY__ESDHC3_CLK */ + >; + }; + }; + + i2c1 { + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + 333 0xc0 /* MX53_PAD_CSI0_DAT8__I2C1_SDA */ + 341 0xc0 /* MX53_PAD_CSI0_DAT9__I2C1_SCL */ + >; + }; + + pinctrl_i2c1_2: i2c1grp-2 { + fsl,pins = < + 529 0xc0 /* MX53_PAD_EIM_D28__I2C1_SDA */ + 469 0xc0 /* MX53_PAD_EIM_D21__I2C1_SCL */ + >; + }; + }; + + i2c2 { + pinctrl_i2c2_1: i2c2grp-1 { + fsl,pins = < + 61 0xc0 /* MX53_PAD_KEY_ROW3__I2C2_SDA */ + 53 0xc0 /* MX53_PAD_KEY_COL3__I2C2_SCL */ + >; + }; + }; + + i2c3 { + pinctrl_i2c3_1: i2c3grp-1 { + fsl,pins = < + 1102 0xc0 /* MX53_PAD_GPIO_6__I2C3_SDA */ + 1094 0xc0 /* MX53_PAD_GPIO_3__I2C3_SCL */ + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + 346 0x1c5 /* MX53_PAD_CSI0_DAT10__UART1_TXD_MUX */ + 354 0x1c5 /* MX53_PAD_CSI0_DAT11__UART1_RXD_MUX */ + >; + }; + + pinctrl_uart1_2: uart1grp-2 { + fsl,pins = < + 828 0x1c5 /* MX53_PAD_PATA_DIOW__UART1_TXD_MUX */ + 832 0x1c5 /* MX53_PAD_PATA_DMACK__UART1_RXD_MUX */ + >; + }; + }; + + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + 841 0x1c5 /* MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX */ + 836 0x1c5 /* MX53_PAD_PATA_DMARQ__UART2_TXD_MUX */ + >; + }; + }; + + uart3 { + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + 884 0x1c5 /* MX53_PAD_PATA_CS_0__UART3_TXD_MUX */ + 888 0x1c5 /* MX53_PAD_PATA_CS_1__UART3_RXD_MUX */ + 875 0x1c5 /* MX53_PAD_PATA_DA_1__UART3_CTS */ + 880 0x1c5 /* MX53_PAD_PATA_DA_2__UART3_RTS */ + >; + }; + }; + }; + pwm@53fb4000 { + compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; + reg = <0x53fb4000 0x4000>; + interrupts = <61>; + status = "disabled"; + }; + + pwm@53fb8000 { + compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; + reg = <0x53fb8000 0x4000>; + interrupts = <94>; + status = "disabled"; + }; + + uart1: uart@53fbc000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x53fbc000 0x4000>; + interrupts = <31>; + status = "disabled"; + }; + + uart2: uart@53fc0000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x53fc0000 0x4000>; + interrupts = <32>; + status = "disabled"; + }; + + can1: flexcan@53fc8000 { + compatible = "fsl,p1010-flexcan"; + reg = <0x53fc8000 0x4000>; + interrupts = <82>; + status = "disabled"; + }; + + can2: flexcan@53fcc000 { + compatible = "fsl,p1010-flexcan"; + reg = <0x53fcc000 0x4000>; + interrupts = <83>; + status = "disabled"; + }; + + gpio5: gpio@53fdc000 { + compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; + reg = <0x53fdc000 0x4000>; + interrupts = <103 104>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio6: gpio@53fe0000 { + compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; + reg = <0x53fe0000 0x4000>; + interrupts = <105 106>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + gpio7: gpio@53fe4000 { + compatible = "fsl,imx53-gpio", "fsl,imx31-gpio"; + reg = <0x53fe4000 0x4000>; + interrupts = <107 108>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <1>; + }; + + i2c@53fec000 { /* I2C3 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-i2c", "fsl,imx1-i2c"; + reg = <0x53fec000 0x4000>; + interrupts = <64>; + status = "disabled"; + }; + + uart4: uart@53ff0000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x53ff0000 0x4000>; + interrupts = <13>; + status = "disabled"; + }; + }; + + aips@60000000 { /* AIPS2 */ + compatible = "fsl,aips-bus", "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x60000000 0x10000000>; + ranges; + + uart5: uart@63f90000 { + compatible = "fsl,imx53-uart", "fsl,imx21-uart"; + reg = <0x63f90000 0x4000>; + interrupts = <86>; + status = "disabled"; + }; + + ecspi@63fac000 { /* ECSPI2 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; + reg = <0x63fac000 0x4000>; + interrupts = <37>; + status = "disabled"; + }; + + sdma@63fb0000 { + compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; + reg = <0x63fb0000 0x4000>; + interrupts = <6>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; + }; + + cspi@63fc0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; + reg = <0x63fc0000 0x4000>; + interrupts = <38>; + status = "disabled"; + }; + + i2c@63fc4000 { /* I2C2 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-i2c", "fsl,imx1-i2c"; + reg = <0x63fc4000 0x4000>; + interrupts = <63>; + status = "disabled"; + }; + + i2c@63fc8000 { /* I2C1 */ + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx53-i2c", "fsl,imx1-i2c"; + reg = <0x63fc8000 0x4000>; + interrupts = <62>; + status = "disabled"; + }; + + ssi1: ssi@63fcc000 { + compatible = "fsl,imx-ssi"; + reg = <0x63fcc000 0x4000>; + interrupts = <29>; + status = "disabled"; + }; + + audmux@63fd0000 { + compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; + reg = <0x63fd0000 0x4000>; + status = "disabled"; + }; + + nand@63fdb000 { + compatible = "fsl,imx53-nand", "mxc_nand"; + reg = <0xf7ff0000 0x10000>, <0x63fdb000 0x4000>; + interrupts = <8>; + status = "disabled"; + }; + + ssi3: ssi@63fe8000 { + compatible = "fsl,imx-ssi"; + reg = <0x63fe8000 0x4000>; + interrupts = <96>; + status = "disabled"; + }; + + ethernet@63fec000 { + compatible = "fsl,imx53-fec", "fsl,imx25-fec"; + reg = <0x63fec000 0x4000>; + interrupts = <87>; + status = "disabled"; + }; + }; + }; +}; diff --git a/arch/arm/dts/mx6dl.dtsi b/arch/arm/dts/mx6dl.dtsi new file mode 100644 index 0000000000..10905f166a --- /dev/null +++ b/arch/arm/dts/mx6dl.dtsi @@ -0,0 +1,413 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +/include/ "imx6qdl.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 792000 1150000 + 396000 950000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks 104>, <&clks 6>, <&clks 16>, + <&clks 17>, <&clks 170>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&L2>; + }; + }; + + soc { + aips-bus@02000000 { /* AIPS1 */ + spba-bus@02000000 { + ecspi5: ecspi@02018000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,iMX6DL-ecspi", "fsl,imx51-ecspi"; + reg = <0x02018000 0x4000>; + interrupts = <0 35 0x04>; + clocks = <&clks 116>, <&clks 116>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + + iomuxc: iomuxc@020e0000 { + compatible = "fsl,iMX6DL-iomuxc"; + reg = <0x020e0000 0x4000>; + + /* shared pinctrl settings */ + audmux { + pinctrl_audmux_1: audmux-1 { + fsl,pins = < + 18 0x80000000 /* MX6DL_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */ + 1586 0x80000000 /* MX6DL_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */ + 11 0x80000000 /* MX6DL_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */ + 3 0x80000000 /* MX6DL_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */ + >; + }; + }; + + ecspi1 { + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + 101 0x100b1 /* MX6DL_PAD_EIM_D17__ECSPI1_MISO */ + 109 0x100b1 /* MX6DL_PAD_EIM_D18__ECSPI1_MOSI */ + 94 0x100b1 /* MX6DL_PAD_EIM_D16__ECSPI1_SCLK */ + >; + }; + }; + + enet { + pinctrl_enet_1: enetgrp-1 { + fsl,pins = < + 695 0x1b0b0 /* MX6DL_PAD_ENET_MDIO__ENET_MDIO */ + 756 0x1b0b0 /* MX6DL_PAD_ENET_MDC__ENET_MDC */ + 24 0x1b0b0 /* MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC */ + 30 0x1b0b0 /* MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0 */ + 34 0x1b0b0 /* MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1 */ + 39 0x1b0b0 /* MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2 */ + 44 0x1b0b0 /* MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3 */ + 56 0x1b0b0 /* MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ + 702 0x1b0b0 /* MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK */ + 74 0x1b0b0 /* MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC */ + 52 0x1b0b0 /* MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0 */ + 61 0x1b0b0 /* MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1 */ + 66 0x1b0b0 /* MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2 */ + 70 0x1b0b0 /* MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3 */ + 48 0x1b0b0 /* MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ + 1033 0x4001b0a8 /* MX6DL_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/ + >; + }; + + pinctrl_enet_2: enetgrp-2 { + fsl,pins = < + 890 0x1b0b0 /* MX6DL_PAD_KEY_COL1__ENET_MDIO */ + 909 0x1b0b0 /* MX6DL_PAD_KEY_COL2__ENET_MDC */ + 24 0x1b0b0 /* MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC */ + 30 0x1b0b0 /* MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0 */ + 34 0x1b0b0 /* MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1 */ + 39 0x1b0b0 /* MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2 */ + 44 0x1b0b0 /* MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3 */ + 56 0x1b0b0 /* MX6DL_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ + 702 0x1b0b0 /* MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK */ + 74 0x1b0b0 /* MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC */ + 52 0x1b0b0 /* MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0 */ + 61 0x1b0b0 /* MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1 */ + 66 0x1b0b0 /* MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2 */ + 70 0x1b0b0 /* MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3 */ + 48 0x1b0b0 /* MX6DL_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ + >; + }; + }; + + gpmi-nand { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + 1328 0xb0b1 /* MX6DL_PAD_NANDF_CLE__RAWNAND_CLE */ + 1336 0xb0b1 /* MX6DL_PAD_NANDF_ALE__RAWNAND_ALE */ + 1344 0xb0b1 /* MX6DL_PAD_NANDF_WP_B__RAWNAND_RESETN */ + 1352 0xb000 /* MX6DL_PAD_NANDF_RB0__RAWNAND_READY0 */ + 1360 0xb0b1 /* MX6DL_PAD_NANDF_CS0__RAWNAND_CE0N */ + 1365 0xb0b1 /* MX6DL_PAD_NANDF_CS1__RAWNAND_CE1N */ + 1371 0xb0b1 /* MX6DL_PAD_NANDF_CS2__RAWNAND_CE2N */ + 1378 0xb0b1 /* MX6DL_PAD_NANDF_CS3__RAWNAND_CE3N */ + 1387 0xb0b1 /* MX6DL_PAD_SD4_CMD__RAWNAND_RDN */ + 1393 0xb0b1 /* MX6DL_PAD_SD4_CLK__RAWNAND_WRN */ + 1397 0xb0b1 /* MX6DL_PAD_NANDF_D0__RAWNAND_D0 */ + 1405 0xb0b1 /* MX6DL_PAD_NANDF_D1__RAWNAND_D1 */ + 1413 0xb0b1 /* MX6DL_PAD_NANDF_D2__RAWNAND_D2 */ + 1421 0xb0b1 /* MX6DL_PAD_NANDF_D3__RAWNAND_D3 */ + 1429 0xb0b1 /* MX6DL_PAD_NANDF_D4__RAWNAND_D4 */ + 1437 0xb0b1 /* MX6DL_PAD_NANDF_D5__RAWNAND_D5 */ + 1445 0xb0b1 /* MX6DL_PAD_NANDF_D6__RAWNAND_D6 */ + 1453 0xb0b1 /* MX6DL_PAD_NANDF_D7__RAWNAND_D7 */ + 1463 0x00b1 /* MX6DL_PAD_SD4_DAT0__RAWNAND_DQS */ + >; + }; + }; + + i2c1 { + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + 137 0x4001b8b1 /* MX6DL_PAD_EIM_D21__I2C1_SCL */ + 196 0x4001b8b1 /* MX6DL_PAD_EIM_D28__I2C1_SDA */ + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + 1140 0x1b0b1 /* MX6DL_PAD_CSI0_DAT10__UART1_TXD */ + 1148 0x1b0b1 /* MX6DL_PAD_CSI0_DAT11__UART1_RXD */ + >; + }; + pinctrl_uart1_2: uart1-grp-2 { + fsl,pins = < + 120 0x1b0b1 /* MX6DL_PAD_EIM_D19__UART1_CTS */ + 128 0x1b0b1 /* MX6DL_PAD_EIM_D20__UART1_RTS */ + >; + }; + + pinctrl_uart1_3: uart1grp-3 { + fsl,pins = < + 1242 0x1b0b1 /* MX6DL_PAD_SD3_DAT7__UART1_TXD */ + 1250 0x1b0b1 /* MX6DL_PAD_SD3_DAT6__UART1_RXD */ + >; + }; + pinctrl_uart1_4: uart1-grp-4 { + fsl,pins = < + 1290 0x1b0b1 /* MX6DL_PAD_SD3_DAT0__UART1_CTS */ + 1298 0x1b0b1 /* MX6DL_PAD_SD3_DAT1__UART1_RTS */ + >; + }; + }; + + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + 183 0x1b0b1 /* MX6DL_PAD_EIM_D26__UART2_TXD */ + 191 0x1b0b1 /* MX6DL_PAD_EIM_D27__UART2_RXD */ + >; + }; + pinctrl_uart2_2: uart2grp-2 { + fsl,pins = < + 199 0x1b0b1 /* MX6DL_PAD_EIM_D28__UART2_CTS */ + 206 0x1b0b1 /* MX6DL_PAD_EIM_D29__UART2_RTS */ + >; + }; + + pinctrl_uart2_3: uart2grp-3 { + fsl,pins = < + 1258 0x1b0b1 /* MX6DL_PAD_SD3_DAT5__UART2_TXD */ + 1266 0x1b0b1 /* MX6DL_PAD_SD3_DAT6__UART2_RXD */ + >; + }; + pinctrl_uart2_4: uart2grp-4 { + fsl,pins = < + 1274 0x1b0b1 /* MX6DL_PAD_SD3_CMD__UART2_CTS */ + 1282 0x1b0b1 /* MX6DL_PAD_SD3_CLK__UART2_RTS */ + >; + }; + + pinctrl_uart2_5: uart2grp-5 { + fsl,pins = < + 1518 0x1b0b1 /* MX6DL_PAD_SD4_DAT7__UART2_TXD */ + 1494 0x1b0b1 /* MX6DL_PAD_SD4_DAT4__UART2_RXD */ + >; + }; + pinctrl_uart2_6: uart2grp-6 { + fsl,pins = < + 1510 0x1b0b1 /* MX6DL_PAD_SD4_DAT6__UART2_CTS */ + 1502 0x1b0b1 /* MX6DL_PAD_SD4_DAT5__UART2_RTS */ + >; + }; + + pinctrl_uart2_7: uart2grp-7 { + fsl,pins = < + 1019 0x1b0b1 /* MX6DL_PAD_GPIO_7__UART2_TXD */ + 1027 0x1b0b1 /* MX6DL_PAD_GPIO_8__UART2_RXD */ + >; + }; + }; + + uart3 { + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + 165 0x1b0b1 /* MX6DL_PAD_EIM_D24__UART3_TXD */ + 173 0x1b0b1 /* MX6DL_PAD_EIM_D25__UART3_RXD */ + >; + }; + pinctrl_uart3_2: uart3grp-2 { + fsl,pins = < + 149 0x1b0b1 /* MX6DL_PAD_EIM_D23__UART3_CTS */ + 157 0x1b0b1 /* MX6DL_PAD_EIM_EB3__UART3_RTS */ + >; + }; + + pinctrl_uart3_3: uart3grp-3 { + fsl,pins = < + 1388 0x1b0b1 /* MX6DL_PAD_SD4_CMD__UART3_TXD */ + 1394 0x1b0b1 /* MX6DL_PAD_SD4_CLK__UART3_RXD */ + >; + }; + pinctrl_uart3_4: uart3grp-4 { + fsl,pins = < + 1313 0x1b0b1 /* MX6DL_PAD_SD3_DAT3__UART3_CTS */ + 1321 0x1b0b1 /* MX6DL_PAD_SD3_RST__UART3_RTS */ + >; + }; + + pinctrl_uart3_5: uart3grp-5 { + fsl,pins = < + 214 0x1b0b1 /* MX6DL_PAD_EIM_D30__UART3_CTS */ + 222 0x1b0b1 /* MX6DL_PAD_EIM_D31__UART3_RTS */ + >; + }; + }; + + uart4 { + pinctrl_uart4_1: uart4grp-1 { + fsl,pins = < + 877 0x1b0b1 /* MX6DL_PAD_KEY_COL0__UART4_TXD */ + 885 0x1b0b1 /* MX6DL_PAD_KEY_ROW0__UART4_RXD */ + >; + }; + }; + + usbotg { + pinctrl_usbotg_1: usbotggrp-1 { + fsl,pins = < + 1592 0x17059 /* MX6DL_PAD_GPIO_1__ANATOP_USBOTG_ID */ + >; + }; + }; + + usdhc1 { + pinctrl_usdhc1_1: usdhc1grp-1 { + fsl,pins = < + 1548 0x17059 /* MX6DL_PAD_SD1_CMD__USDHC1_CMD */ + 1562 0x10059 /* MX6DL_PAD_SD1_CLK__USDHC1_CLK */ + 1532 0x17059 /* MX6DL_PAD_SD1_DAT0__USDHC1_DAT0 */ + 1524 0x17059 /* MX6DL_PAD_SD1_DAT1__USDHC1_DAT1 */ + 1554 0x17059 /* MX6DL_PAD_SD1_DAT2__USDHC1_DAT2 */ + 1540 0x17059 /* MX6DL_PAD_SD1_DAT3__USDHC1_DAT3 */ + 1398 0x17059 /* MX6DL_PAD_NANDF_D0__USDHC1_DAT4 */ + 1406 0x17059 /* MX6DL_PAD_NANDF_D1__USDHC1_DAT5 */ + 1414 0x17059 /* MX6DL_PAD_NANDF_D2__USDHC1_DAT6 */ + 1422 0x17059 /* MX6DL_PAD_NANDF_D3__USDHC1_DAT7 */ + >; + }; + + pinctrl_usdhc1_2: usdhc1grp-2 { + fsl,pins = < + 1548 0x17059 /* MX6DL_PAD_SD1_CMD__USDHC1_CMD */ + 1562 0x10059 /* MX6DL_PAD_SD1_CLK__USDHC1_CLK */ + 1532 0x17059 /* MX6DL_PAD_SD1_DAT0__USDHC1_DAT0 */ + 1524 0x17059 /* MX6DL_PAD_SD1_DAT1__USDHC1_DAT1 */ + 1554 0x17059 /* MX6DL_PAD_SD1_DAT2__USDHC1_DAT2 */ + 1540 0x17059 /* MX6DL_PAD_SD1_DAT3__USDHC1_DAT3 */ + >; + }; + }; + + usdhc2 { + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + 1577 0x17059 /* MX6DL_PAD_SD2_CMD__USDHC2_CMD */ + 1569 0x10059 /* MX6DL_PAD_SD2_CLK__USDHC2_CLK */ + 16 0x17059 /* MX6DL_PAD_SD2_DAT0__USDHC2_DAT0 */ + 0 0x17059 /* MX6DL_PAD_SD2_DAT1__USDHC2_DAT1 */ + 8 0x17059 /* MX6DL_PAD_SD2_DAT2__USDHC2_DAT2 */ + 1583 0x17059 /* MX6DL_PAD_SD2_DAT3__USDHC2_DAT3 */ + 1430 0x17059 /* MX6DL_PAD_NANDF_D4__USDHC2_DAT4 */ + 1438 0x17059 /* MX6DL_PAD_NANDF_D5__USDHC2_DAT5 */ + 1446 0x17059 /* MX6DL_PAD_NANDF_D6__USDHC2_DAT6 */ + 1454 0x17059 /* MX6DL_PAD_NANDF_D7__USDHC2_DAT7 */ + >; + }; + + pinctrl_usdhc2_2: usdhc2grp-2 { + fsl,pins = < + 1577 0x17059 /* MX6DL_PAD_SD2_CMD__USDHC2_CMD */ + 1569 0x10059 /* MX6DL_PAD_SD2_CLK__USDHC2_CLK */ + 16 0x17059 /* MX6DL_PAD_SD2_DAT0__USDHC2_DAT0 */ + 0 0x17059 /* MX6DL_PAD_SD2_DAT1__USDHC2_DAT1 */ + 8 0x17059 /* MX6DL_PAD_SD2_DAT2__USDHC2_DAT2 */ + 1583 0x17059 /* MX6DL_PAD_SD2_DAT3__USDHC2_DAT3 */ + >; + }; + }; + + usdhc3 { + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + 1273 0x17059 /* MX6DL_PAD_SD3_CMD__USDHC3_CMD */ + 1281 0x10059 /* MX6DL_PAD_SD3_CLK__USDHC3_CLK */ + 1289 0x17059 /* MX6DL_PAD_SD3_DAT0__USDHC3_DAT0 */ + 1297 0x17059 /* MX6DL_PAD_SD3_DAT1__USDHC3_DAT1 */ + 1305 0x17059 /* MX6DL_PAD_SD3_DAT2__USDHC3_DAT2 */ + 1312 0x17059 /* MX6DL_PAD_SD3_DAT3__USDHC3_DAT3 */ + 1265 0x17059 /* MX6DL_PAD_SD3_DAT4__USDHC3_DAT4 */ + 1257 0x17059 /* MX6DL_PAD_SD3_DAT5__USDHC3_DAT5 */ + 1249 0x17059 /* MX6DL_PAD_SD3_DAT6__USDHC3_DAT6 */ + 1241 0x17059 /* MX6DL_PAD_SD3_DAT7__USDHC3_DAT7 */ + >; + }; + + pinctrl_usdhc3_2: usdhc3grp-2 { + fsl,pins = < + 1273 0x17059 /* MX6DL_PAD_SD3_CMD__USDHC3_CMD */ + 1281 0x10059 /* MX6DL_PAD_SD3_CLK__USDHC3_CLK */ + 1289 0x17059 /* MX6DL_PAD_SD3_DAT0__USDHC3_DAT0 */ + 1297 0x17059 /* MX6DL_PAD_SD3_DAT1__USDHC3_DAT1 */ + 1305 0x17059 /* MX6DL_PAD_SD3_DAT2__USDHC3_DAT2 */ + 1312 0x17059 /* MX6DL_PAD_SD3_DAT3__USDHC3_DAT3 */ + >; + }; + }; + + usdhc4 { + pinctrl_usdhc4_1: usdhc4grp-1 { + fsl,pins = < + 1386 0x17059 /* MX6DL_PAD_SD4_CMD__USDHC4_CMD */ + 1392 0x10059 /* MX6DL_PAD_SD4_CLK__USDHC4_CLK */ + 1462 0x17059 /* MX6DL_PAD_SD4_DAT0__USDHC4_DAT0 */ + 1470 0x17059 /* MX6DL_PAD_SD4_DAT1__USDHC4_DAT1 */ + 1478 0x17059 /* MX6DL_PAD_SD4_DAT2__USDHC4_DAT2 */ + 1486 0x17059 /* MX6DL_PAD_SD4_DAT3__USDHC4_DAT3 */ + 1493 0x17059 /* MX6DL_PAD_SD4_DAT4__USDHC4_DAT4 */ + 1501 0x17059 /* MX6DL_PAD_SD4_DAT5__USDHC4_DAT5 */ + 1509 0x17059 /* MX6DL_PAD_SD4_DAT6__USDHC4_DAT6 */ + 1517 0x17059 /* MX6DL_PAD_SD4_DAT7__USDHC4_DAT7 */ + >; + }; + + pinctrl_usdhc4_2: usdhc4grp-2 { + fsl,pins = < + 1386 0x17059 /* MX6DL_PAD_SD4_CMD__USDHC4_CMD */ + 1392 0x10059 /* MX6DL_PAD_SD4_CLK__USDHC4_CLK */ + 1462 0x17059 /* MX6DL_PAD_SD4_DAT0__USDHC4_DAT0 */ + 1470 0x17059 /* MX6DL_PAD_SD4_DAT1__USDHC4_DAT1 */ + 1478 0x17059 /* MX6DL_PAD_SD4_DAT2__USDHC4_DAT2 */ + 1486 0x17059 /* MX6DL_PAD_SD4_DAT3__USDHC4_DAT3 */ + >; + }; + }; + }; + }; + + ipu2: ipu@02800000 { + #crtc-cells = <1>; + compatible = "fsl,iMX6DL-ipu"; + reg = <0x02800000 0x400000>; + interrupts = <0 8 0x4 0 7 0x4>; + clocks = <&clks 133>, <&clks 134>, <&clks 137>; + clock-names = "bus", "di0", "di1"; + }; + }; +}; diff --git a/arch/arm/dts/mx6q.dtsi b/arch/arm/dts/mx6q.dtsi new file mode 100644 index 0000000000..a1eac173f8 --- /dev/null +++ b/arch/arm/dts/mx6q.dtsi @@ -0,0 +1,428 @@ + +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + */ + +/include/ "imx6qdl.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a9"; + reg = <0>; + next-level-cache = <&L2>; + operating-points = < + /* kHz uV */ + 1200000 1275000 + 996000 1250000 + 792000 1150000 + 396000 950000 + >; + clock-latency = <61036>; /* two CLK32 periods */ + clocks = <&clks 104>, <&clks 6>, <&clks 16>, + <&clks 17>, <&clks 170>; + clock-names = "arm", "pll2_pfd2_396m", "step", + "pll1_sw", "pll1_sys"; + arm-supply = <®_arm>; + pu-supply = <®_pu>; + soc-supply = <®_soc>; + }; + + cpu@1 { + compatible = "arm,cortex-a9"; + reg = <1>; + next-level-cache = <&L2>; + }; + + cpu@2 { + compatible = "arm,cortex-a9"; + reg = <2>; + next-level-cache = <&L2>; + }; + + cpu@3 { + compatible = "arm,cortex-a9"; + reg = <3>; + next-level-cache = <&L2>; + }; + }; + + soc { + aips-bus@02000000 { /* AIPS1 */ + spba-bus@02000000 { + ecspi5: ecspi@02018000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi"; + reg = <0x02018000 0x4000>; + interrupts = <0 35 0x04>; + clocks = <&clks 116>, <&clks 116>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + }; + + iomuxc: iomuxc@020e0000 { + compatible = "fsl,imx6q-iomuxc"; + reg = <0x020e0000 0x4000>; + + /* shared pinctrl settings */ + audmux { + pinctrl_audmux_1: audmux-1 { + fsl,pins = < + 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */ + 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */ + 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */ + 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */ + >; + }; + }; + + ecspi1 { + pinctrl_ecspi1_1: ecspi1grp-1 { + fsl,pins = < + 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */ + 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */ + 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */ + >; + }; + }; + + enet { + pinctrl_enet_1: enetgrp-1 { + fsl,pins = < + 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */ + 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */ + 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ + 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ + 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ + 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ + 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ + 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ + 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ + 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ + 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ + 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ + 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ + 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ + 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ + 1033 0x4001b0a8 /* MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/ + >; + }; + + pinctrl_enet_2: enetgrp-2 { + fsl,pins = < + 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */ + 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */ + 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */ + 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */ + 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */ + 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */ + 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */ + 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */ + 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */ + 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */ + 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */ + 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */ + 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */ + 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */ + 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */ + >; + }; + }; + + gpmi-nand { + pinctrl_gpmi_nand_1: gpmi-nand-1 { + fsl,pins = < + 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */ + 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */ + 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */ + 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */ + 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */ + 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */ + 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */ + 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */ + 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */ + 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */ + 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */ + 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */ + 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */ + 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */ + 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */ + 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */ + 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */ + 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */ + 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */ + >; + }; + }; + + i2c1 { + pinctrl_i2c1_1: i2c1grp-1 { + fsl,pins = < + 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */ + 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */ + >; + }; + }; + + uart1 { + pinctrl_uart1_1: uart1grp-1 { + fsl,pins = < + 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */ + 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */ + >; + }; + pinctrl_uart1_2: uart1-grp-2 { + fsl,pins = < + 120 0x1b0b1 /* MX6Q_PAD_EIM_D19__UART1_CTS */ + 128 0x1b0b1 /* MX6Q_PAD_EIM_D20__UART1_RTS */ + >; + }; + + pinctrl_uart1_3: uart1grp-3 { + fsl,pins = < + 1242 0x1b0b1 /* MX6Q_PAD_SD3_DAT7__UART1_TXD */ + 1250 0x1b0b1 /* MX6Q_PAD_SD3_DAT6__UART1_RXD */ + >; + }; + pinctrl_uart1_4: uart1-grp-4 { + fsl,pins = < + 1290 0x1b0b1 /* MX6Q_PAD_SD3_DAT0__UART1_CTS */ + 1298 0x1b0b1 /* MX6Q_PAD_SD3_DAT1__UART1_RTS */ + >; + }; + }; + + uart2 { + pinctrl_uart2_1: uart2grp-1 { + fsl,pins = < + 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */ + 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */ + >; + }; + pinctrl_uart2_2: uart2grp-2 { + fsl,pins = < + 199 0x1b0b1 /* MX6Q_PAD_EIM_D28__UART2_CTS */ + 206 0x1b0b1 /* MX6Q_PAD_EIM_D29__UART2_RTS */ + >; + }; + + pinctrl_uart2_3: uart2grp-3 { + fsl,pins = < + 1258 0x1b0b1 /* MX6Q_PAD_SD3_DAT5__UART2_TXD */ + 1266 0x1b0b1 /* MX6Q_PAD_SD3_DAT6__UART2_RXD */ + >; + }; + pinctrl_uart2_4: uart2grp-4 { + fsl,pins = < + 1274 0x1b0b1 /* MX6Q_PAD_SD3_CMD__UART2_CTS */ + 1282 0x1b0b1 /* MX6Q_PAD_SD3_CLK__UART2_RTS */ + >; + }; + + pinctrl_uart2_5: uart2grp-5 { + fsl,pins = < + 1518 0x1b0b1 /* MX6Q_PAD_SD4_DAT7__UART2_TXD */ + 1494 0x1b0b1 /* MX6Q_PAD_SD4_DAT4__UART2_RXD */ + >; + }; + pinctrl_uart2_6: uart2grp-6 { + fsl,pins = < + 1510 0x1b0b1 /* MX6Q_PAD_SD4_DAT6__UART2_CTS */ + 1502 0x1b0b1 /* MX6Q_PAD_SD4_DAT5__UART2_RTS */ + >; + }; + + pinctrl_uart2_7: uart2grp-7 { + fsl,pins = < + 1019 0x1b0b1 /* MX6Q_PAD_GPIO_7__UART2_TXD */ + 1027 0x1b0b1 /* MX6Q_PAD_GPIO_8__UART2_RXD */ + >; + }; + }; + + uart3 { + pinctrl_uart3_1: uart3grp-1 { + fsl,pins = < + 165 0x1b0b1 /* MX6Q_PAD_EIM_D24__UART3_TXD */ + 173 0x1b0b1 /* MX6Q_PAD_EIM_D25__UART3_RXD */ + >; + }; + pinctrl_uart3_2: uart3grp-2 { + fsl,pins = < + 149 0x1b0b1 /* MX6Q_PAD_EIM_D23__UART3_CTS */ + 157 0x1b0b1 /* MX6Q_PAD_EIM_EB3__UART3_RTS */ + >; + }; + + pinctrl_uart3_3: uart3grp-3 { + fsl,pins = < + 1388 0x1b0b1 /* MX6Q_PAD_SD4_CMD__UART3_TXD */ + 1394 0x1b0b1 /* MX6Q_PAD_SD4_CLK__UART3_RXD */ + >; + }; + pinctrl_uart3_4: uart3grp-4 { + fsl,pins = < + 1313 0x1b0b1 /* MX6Q_PAD_SD3_DAT3__UART3_CTS */ + 1321 0x1b0b1 /* MX6Q_PAD_SD3_RST__UART3_RTS */ + >; + }; + + pinctrl_uart3_5: uart3grp-5 { + fsl,pins = < + 214 0x1b0b1 /* MX6Q_PAD_EIM_D30__UART3_CTS */ + 222 0x1b0b1 /* MX6Q_PAD_EIM_D31__UART3_RTS */ + >; + }; + }; + + uart4 { + pinctrl_uart4_1: uart4grp-1 { + fsl,pins = < + 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */ + 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */ + >; + }; + }; + + usbotg { + pinctrl_usbotg_1: usbotggrp-1 { + fsl,pins = < + 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */ + >; + }; + }; + + usdhc1 { + pinctrl_usdhc1_1: usdhc1grp-1 { + fsl,pins = < + 1548 0x17059 /* MX6Q_PAD_SD1_CMD__USDHC1_CMD */ + 1562 0x10059 /* MX6Q_PAD_SD1_CLK__USDHC1_CLK */ + 1532 0x17059 /* MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 */ + 1524 0x17059 /* MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 */ + 1554 0x17059 /* MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 */ + 1540 0x17059 /* MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 */ + 1398 0x17059 /* MX6Q_PAD_NANDF_D0__USDHC1_DAT4 */ + 1406 0x17059 /* MX6Q_PAD_NANDF_D1__USDHC1_DAT5 */ + 1414 0x17059 /* MX6Q_PAD_NANDF_D2__USDHC1_DAT6 */ + 1422 0x17059 /* MX6Q_PAD_NANDF_D3__USDHC1_DAT7 */ + >; + }; + + pinctrl_usdhc1_2: usdhc1grp-2 { + fsl,pins = < + 1548 0x17059 /* MX6Q_PAD_SD1_CMD__USDHC1_CMD */ + 1562 0x10059 /* MX6Q_PAD_SD1_CLK__USDHC1_CLK */ + 1532 0x17059 /* MX6Q_PAD_SD1_DAT0__USDHC1_DAT0 */ + 1524 0x17059 /* MX6Q_PAD_SD1_DAT1__USDHC1_DAT1 */ + 1554 0x17059 /* MX6Q_PAD_SD1_DAT2__USDHC1_DAT2 */ + 1540 0x17059 /* MX6Q_PAD_SD1_DAT3__USDHC1_DAT3 */ + >; + }; + }; + + usdhc2 { + pinctrl_usdhc2_1: usdhc2grp-1 { + fsl,pins = < + 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */ + 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */ + 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */ + 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */ + 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */ + 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */ + 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */ + 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */ + 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */ + 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */ + >; + }; + + pinctrl_usdhc2_2: usdhc2grp-2 { + fsl,pins = < + 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */ + 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */ + 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */ + 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */ + 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */ + 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */ + >; + }; + }; + + usdhc3 { + pinctrl_usdhc3_1: usdhc3grp-1 { + fsl,pins = < + 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ + 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ + 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ + 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ + 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ + 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ + 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */ + 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */ + 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */ + 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */ + >; + }; + + pinctrl_usdhc3_2: usdhc3grp-2 { + fsl,pins = < + 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */ + 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */ + 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */ + 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */ + 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */ + 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */ + >; + }; + }; + + usdhc4 { + pinctrl_usdhc4_1: usdhc4grp-1 { + fsl,pins = < + 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ + 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ + 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ + 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ + 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ + 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ + 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */ + 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */ + 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */ + 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */ + >; + }; + + pinctrl_usdhc4_2: usdhc4grp-2 { + fsl,pins = < + 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */ + 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */ + 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */ + 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */ + 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */ + 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */ + >; + }; + }; + }; + }; + + ipu2: ipu@02800000 { + #crtc-cells = <1>; + compatible = "fsl,imx6q-ipu"; + reg = <0x02800000 0x400000>; + interrupts = <0 8 0x4 0 7 0x4>; + clocks = <&clks 133>, <&clks 134>, <&clks 137>; + clock-names = "bus", "di0", "di1"; + }; + }; +}; diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c index 0cd2538b21..c847a838f0 100644 --- a/arch/arm/imx-common/cpu.c +++ b/arch/arm/imx-common/cpu.c @@ -14,7 +14,6 @@ #include #include #include -#include #ifdef CONFIG_FSL_ESDHC #include @@ -170,11 +169,3 @@ u32 get_ahb_clk(void) return get_periph_clk() / (ahb_podf + 1); } - -#if defined(CONFIG_VIDEO_IPUV3) -void arch_preboot_os(void) -{ - /* disable video before launching O/S */ - ipuv3_fb_shutdown(); -} -#endif diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index b59b802830..fe43d872dd 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -37,11 +37,11 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad) __raw_writel(sel_input, base + sel_input_ofs); #ifdef CONFIG_IOMUX_SHARE_CONF_REG - if (!(pad_ctrl & NO_PAD_CTRL)) + if (pad & PAD_CTRL_VALID) __raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl, base + pad_ctrl_ofs); #else - if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs) + if ((pad & PAD_CTRL_VALID) && pad_ctrl_ofs) __raw_writel(pad_ctrl, base + pad_ctrl_ofs); #endif } @@ -52,6 +52,22 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, iomux_v3_cfg_t const *p = pad_list; int i; - for (i = 0; i < count; i++) + for (i = 0; i < count; i++) { +#ifdef DEBUG + u32 mux_ctrl_ofs = (*p & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT; + u32 mux_mode = (*p & MUX_MODE_MASK) >> MUX_MODE_SHIFT; + u32 sel_input_ofs = + (*p & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT; + u32 sel_input = + (*p & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT; + u32 pad_ctrl_ofs = + (*p & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT; + u32 pad_ctrl = (*p & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT; + + printf("PAD[%2d]=%016llx mux[%03x]=%02x pad[%03x]=%05x%c inp[%03x]=%d\n", + i, *p, mux_ctrl_ofs, mux_mode, pad_ctrl_ofs, pad_ctrl, + *p & PAD_CTRL_VALID ? ' ' : '!', sel_input_ofs, sel_input); +#endif imx_iomux_v3_setup_pad(*p++); + } } diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c index c63f78f682..a4b0137cf3 100644 --- a/arch/arm/imx-common/timer.c +++ b/arch/arm/imx-common/timer.c @@ -68,6 +68,7 @@ int timer_init(void) gd->arch.tbl = __raw_readl(&cur_gpt->counter); gd->arch.tbu = 0; + gd->arch.timer_rate_hz = MXC_CLK32; return 0; } @@ -117,5 +118,5 @@ void __udelay(unsigned long usec) */ ulong get_tbclk(void) { - return MXC_CLK32; + return gd->arch.timer_rate_hz; } diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h index 80e189916c..29b0964bdf 100644 --- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h +++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h @@ -16,6 +16,10 @@ #define CONFIG_SYS_MPUCLK 550 #endif +#define DISPPLL_M 200 +#define DISPPLL_N (OSC - 1) +#define DISPPLL_M2 1 + extern void pll_init(void); extern void enable_emif_clocks(void); extern void enable_dmm_clocks(void); diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index bcb4c5037f..72592bfb58 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -17,14 +17,14 @@ #include -#define BIT(x) (1 << x) -#define CL_BIT(x) (0 << x) +#define BIT(x) (1 << (x)) +#define CL_BIT(x) (0 << (x)) /* Timer register bits */ #define TCLR_ST BIT(0) /* Start=1 Stop=0 */ #define TCLR_AR BIT(1) /* Auto reload */ #define TCLR_PRE BIT(5) /* Pre-scaler enable */ -#define TCLR_PTV_SHIFT (2) /* Pre-scaler shift value */ +#define TCLR_PTV_SHIFT 2 /* Pre-scaler shift value */ #define TCLR_PRE_DISABLE CL_BIT(5) /* Pre-scalar disable */ /* device type */ @@ -40,8 +40,8 @@ #define DEVICE_ID (CTRL_BASE + 0x0600) /* This gives the status of the boot mode pins on the evm */ -#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2)\ - | BIT(3) | BIT(4)) +#define SYSBOOT_MASK (BIT(0) | BIT(1) | BIT(2) | \ + BIT(3) | BIT(4)) /* Reset control */ #ifdef CONFIG_AM33XX @@ -105,9 +105,6 @@ struct gpmc { struct bch_res_0_3 bch_result_0_3[2]; /* 0x240 */ }; -/* Used for board specific gpmc initialization */ -extern struct gpmc *gpmc_cfg; - /* Encapsulating core pll registers */ struct cm_wkuppll { unsigned int wkclkstctrl; /* offset 0x00 */ @@ -122,7 +119,9 @@ struct cm_wkuppll { unsigned int idlestdpllddr; /* offset 0x34 */ unsigned int resv5[2]; unsigned int clkseldpllddr; /* offset 0x40 */ - unsigned int resv6[4]; + unsigned int autoidledplldisp; /* offset 0x44 */ + unsigned int idlestdplldisp; /* offset 0x48 */ + unsigned int resv6[2]; unsigned int clkseldplldisp; /* offset 0x54 */ unsigned int resv7[1]; unsigned int idlestdpllcore; /* offset 0x5c */ @@ -147,7 +146,8 @@ struct cm_wkuppll { unsigned int resv11[1]; unsigned int wkup_uart0ctrl; /* offset 0xB4 */ unsigned int wkup_i2c0ctrl; /* offset 0xB8 */ - unsigned int resv12[7]; + unsigned int resv12[6]; + unsigned int wdtimer1ctrl; unsigned int divm6dpllcore; /* offset 0xD8 */ }; @@ -163,7 +163,7 @@ struct cm_perpll { unsigned int resv1; unsigned int cpgmac0clkctrl; /* offset 0x14 */ unsigned int lcdclkctrl; /* offset 0x18 */ - unsigned int usb0clkctrl; /* offset 0x1C */ + unsigned int usb0clkctrl; /* offset 0x1c */ unsigned int resv2; unsigned int tptc0clkctrl; /* offset 0x24 */ unsigned int emifclkctrl; /* offset 0x28 */ @@ -269,7 +269,7 @@ struct gptimer { unsigned int twpc; /* offset 0x48 */ unsigned int tmar; /* offset 0x4c */ unsigned int tcar1; /* offset 0x50 */ - unsigned int tscir; /* offset 0x54 */ + unsigned int tsicr; /* offset 0x54 */ unsigned int tcar2; /* offset 0x58 */ }; @@ -299,7 +299,7 @@ struct ctrl_stat { unsigned int resv1[16]; unsigned int statusreg; /* ofset 0x40 */ unsigned int resv2[51]; - unsigned int secure_emif_sdram_config; /* offset 0x0110 */ + unsigned int emif_sdram_config; /* offset 0x0110 */ }; /* AM33XX GPIO registers */ @@ -336,7 +336,26 @@ struct ctrl_dev { unsigned int resv4[4]; unsigned int miisel; /* offset 0x50 */ }; + +void init_timer(void); + +#define clk_get_rate(c,p) \ + __clk_get_rate(readl(&(c)->clkseldpll##p), \ + readl(&(c)->divm2dpll##p)) + +unsigned long __clk_get_rate(u32 m_n, u32 div_m2); + +unsigned long lcdc_clk_rate(void); +unsigned long mpu_clk_rate(void); + #endif /* __ASSEMBLY__ */ #endif /* __KERNEL_STRICT_NAMES */ +/* Ethernet MAC ID from EFuse */ +#define MAC_ID0_LO (CTRL_BASE + 0x630) +#define MAC_ID0_HI (CTRL_BASE + 0x634) +#define MAC_ID1_LO (CTRL_BASE + 0x638) +#define MAC_ID1_HI (CTRL_BASE + 0x63c) +#define MAC_MII_SEL (CTRL_BASE + 0x650) + #endif /* _AM33XX_CPU_H */ diff --git a/arch/arm/include/asm/arch-am33xx/da8xx-fb.h b/arch/arm/include/asm/arch-am33xx/da8xx-fb.h new file mode 100644 index 0000000000..208b2320e3 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/da8xx-fb.h @@ -0,0 +1,126 @@ +/* + * Porting to u-boot: + * + * (C) Copyright 2011 + * Stefano Babic, DENX Software Engineering, sbabic@denx.de. + * + * Copyright (C) 2008-2009 MontaVista Software Inc. + * Copyright (C) 2008-2009 Texas Instruments Inc + * + * Based on the LCD driver for TI Avalanche processors written by + * Ajay Singh and Shalom Hai. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option)any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef DA8XX_FB_H +#define DA8XX_FB_H + +enum panel_type { + QVGA = 0 +}; + +enum panel_shade { + MONOCHROME = 0, + COLOR_ACTIVE, + COLOR_PASSIVE, +}; + +enum raster_load_mode { + LOAD_DATA = 1, + LOAD_PALETTE, +}; + +struct display_panel { + enum panel_type panel_type; /* QVGA */ + int max_bpp; + int min_bpp; + enum panel_shade panel_shade; +}; + +struct da8xx_panel { + const char name[25]; /* Full name _ */ + unsigned short width; + unsigned short height; + int hfp; /* Horizontal front porch */ + int hbp; /* Horizontal back porch */ + int hsw; /* Horizontal Sync Pulse Width */ + int vfp; /* Vertical front porch */ + int vbp; /* Vertical back porch */ + int vsw; /* Vertical Sync Pulse Width */ + unsigned int pxl_clk; /* Pixel clock */ + unsigned char invert_pxl_clk; /* Invert Pixel clock */ +}; + +struct da8xx_lcdc_platform_data { + const char manu_name[10]; + void *controller_data; + const char type[25]; + void (*panel_power_ctrl)(int); +}; + +struct lcd_ctrl_config { + const struct display_panel *p_disp_panel; + + /* AC Bias Pin Frequency */ + int ac_bias; + + /* AC Bias Pin Transitions per Interrupt */ + int ac_bias_intrpt; + + /* DMA burst size */ + int dma_burst_sz; + + /* Bits per pixel */ + int bpp; + + /* FIFO DMA Request Delay */ + int fdd; + + /* TFT Alternative Signal Mapping (Only for active) */ + unsigned char tft_alt_mode; + + /* 12 Bit Per Pixel (5-6-5) Mode (Only for passive) */ + unsigned char stn_565_mode; + + /* Mono 8-bit Mode: 1=D0-D7 or 0=D0-D3 */ + unsigned char mono_8bit_mode; + + /* Invert line clock */ + unsigned char invert_line_clock; + + /* Invert frame clock */ + unsigned char invert_frm_clock; + + /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */ + unsigned char sync_edge; + + /* Horizontal and Vertical Sync: Control: 0=ignore */ + unsigned char sync_ctrl; + + /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */ + unsigned char raster_order; +}; + +struct lcd_sync_arg { + int back_porch; + int front_porch; + int pulse_width; +}; + +void da8xx_fb_disable(void); +void da8xx_video_init(const struct da8xx_panel *panel, int bits_pixel); + +#endif /* ifndef DA8XX_FB_H */ diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h index 18d7d99a4c..d8e9ee62aa 100644 --- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h +++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h @@ -17,7 +17,10 @@ /* AM335X EMIF Register values */ #define VTP_CTRL_READY (0x1 << 5) #define VTP_CTRL_ENABLE (0x1 << 6) -#define VTP_CTRL_START_EN (0x1) +#define VTP_CTRL_FILTER_SHIFT 1 +#define VTP_CTRL_FILTER_MASK (0x7 << VTP_CTRL_FILTER_SHIFT) +#define VTP_CTRL_FILTER(n) (((n) << VTP_CTRL_FILTER_SHIFT) & VTP_CTRL_FILTER_MASK) +#define VTP_CTRL_START_EN (0x1 << 0) #define PHY_DLL_LOCK_DIFF 0x0 #define DDR_CKE_CTRL_NORMAL 0x1 #define PHY_EN_DYN_PWRDN (0x1 << 20) diff --git a/arch/arm/include/asm/arch-am33xx/gpio.h b/arch/arm/include/asm/arch-am33xx/gpio.h index 13a047fd72..00af799516 100644 --- a/arch/arm/include/asm/arch-am33xx/gpio.h +++ b/arch/arm/include/asm/arch-am33xx/gpio.h @@ -13,4 +13,6 @@ #define AM33XX_GPIO2_BASE 0x481AC000 #define AM33XX_GPIO3_BASE 0x481AE000 +#define AM33XX_GPIO_NR(bank, pin) (((bank) << 5) | (pin)) + #endif /* _GPIO_AM33xx_H */ diff --git a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h index 51ba79190a..886ca65f46 100644 --- a/arch/arm/include/asm/arch-am33xx/mmc_host_def.h +++ b/arch/arm/include/asm/arch-am33xx/mmc_host_def.h @@ -21,8 +21,9 @@ /* * OMAP HSMMC register definitions */ -#define OMAP_HSMMC1_BASE 0x48060100 -#define OMAP_HSMMC2_BASE 0x481D8100 +#define OMAP_HSMMC1_BASE 0x48060000 +#define OMAP_HSMMC2_BASE 0x481D8000 +#define OMAP_HSMMC3_BASE 0x47810000 #if defined(CONFIG_TI814X) #undef MMC_CLOCK_REFERENCE diff --git a/arch/arm/include/asm/arch-am33xx/nand.h b/arch/arm/include/asm/arch-am33xx/nand.h new file mode 100644 index 0000000000..cde2da2830 --- /dev/null +++ b/arch/arm/include/asm/arch-am33xx/nand.h @@ -0,0 +1,219 @@ +/* + * (C) Copyright 2010-2011 Texas Instruments, + * Mansoor Ahamed + * + * Derived from work done by Rohit Choraria for omap3 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_ARCH_OMAP_GPMC_H +#define __ASM_ARCH_OMAP_GPMC_H + +#include + +#define GPMC_BUF_EMPTY 0 +#define GPMC_BUF_FULL 1 + +#define ECCCLEAR (0x1 << 8) +#define ECCRESULTREG1 (0x1 << 0) +#define ECCSIZE512BYTE 0xFF +#define ECCSIZE1 (ECCSIZE512BYTE << 22) +#define ECCSIZE0 (ECCSIZE512BYTE << 12) +#define ECCSIZE0SEL (0x000 << 0) + +/* Generic ECC Layouts */ +/* Large Page x8 NAND device Layout */ +#ifdef GPMC_NAND_ECC_LP_x8_LAYOUT +#define GPMC_NAND_HW_ECC_LAYOUT { \ + .eccbytes = 4 * 13, \ + .eccpos = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, \ + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, \ + 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, \ + 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, \ + }, \ + .oobfree = { \ + { .offset = 58, .length = 6, }, \ + }, \ +} +#endif + +/* Large Page x16 NAND device Layout */ +#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT +#define GPMC_NAND_HW_ECC_LAYOUT { \ + .eccbytes = 4 * 3, \ + .eccpos = { 2, 3, 4, \ + 5, 6, 7, \ + 8, 9, 10, \ + 11, 12, 13, \ + }, \ + .oobfree = { \ + { .offset = 14, .length = 50, }, \ + }, \ +} +#endif + +/* NAND device layout in synch with the kernel */ +#ifdef GPMC_NAND_ECC_LP_x16_LAYOUT +#define GPMC_NAND_HW_ECC_LAYOUT_KERNEL { \ + .eccbytes = 4 * 3, \ + .eccpos = { 40, 41, 42, \ + 43, 44, 45, \ + 46, 47, 48, \ + 49, 50, 51, \ + }, \ + .oobfree = { \ + { .offset = 2, .length = 38, }, \ + }, \ +} +#endif + +/* Small Page x8 NAND device Layout */ +#ifdef GPMC_NAND_ECC_SP_x8_LAYOUT +#define GPMC_NAND_HW_ECC_LAYOUT { \ + .eccbytes = 3, \ + .eccpos = { 1, 2, 3, }, \ + .oobfree = { \ + { .offset = 4, .length = 12, }, \ + }, \ +} +#endif + +/* Small Page x16 NAND device Layout */ +#ifdef GPMC_NAND_ECC_SP_x16_LAYOUT +#define GPMC_NAND_HW_ECC_LAYOUT { \ + .eccbytes = 3, \ + .eccpos = { 2, 3, 4, }, \ + .oobfree = { \ + { .offset = 58, .length = 6, }, \ + }, \ +} +#endif + +#define GPMC_NAND_HW_BCH4_ECC_LAYOUT { \ + .eccbytes = 4 * 8, \ + .eccpos = { 2, 3, 4, 5, 6, 7, 8, 9, \ + 10, 11, 12, 13, 14, 15, 16, 17, \ + 18, 19, 20, 21, 22, 23, 24, 25, \ + 26, 27, 28, 29, 30, 31, 32, 33, \ + }, \ + .oobfree = { \ + { .offset = 34, .length = 30, }, \ + }, \ +} + +#define GPMC_NAND_HW_BCH8_ECC_LAYOUT { \ + .eccbytes = 4 * 14, \ + .eccpos = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \ + 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, \ + 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, \ + }, \ + .oobfree = { \ + { .offset = 58, .length = 6, }, \ + } \ +} + +#define GPMC_NAND_HW_BCH16_ECC_LAYOUT { \ + .eccbytes = 4 * 26, \ + .eccpos = { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, \ + 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, \ + 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, \ + 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, \ + 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, \ + 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \ + 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, \ + 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, \ + }, \ + .oobfree = { \ + { .offset = 106, .length = 8, }, \ + }, \ +} + +/* + * ELM Module Registers + */ + +/* ELM registers bit fields */ +#define ELM_SYSCONFIG_SOFTRESET_MASK (0x2) +#define ELM_SYSCONFIG_SOFTRESET (0x2) +#define ELM_SYSSTATUS_RESETDONE_MASK (0x1) +#define ELM_SYSSTATUS_RESETDONE (0x1) +#define ELM_LOCATION_CONFIG_ECC_BCH_LEVEL_MASK (0x3) +#define ELM_LOCATION_CONFIG_ECC_SIZE_MASK (0x7FF0000) +#define ELM_LOCATION_CONFIG_ECC_SIZE_POS (16) +#define ELM_SYNDROME_FRAGMENT_6_SYNDROME_VALID (0x00010000) +#define ELM_LOCATION_STATUS_ECC_CORRECTABLE_MASK (0x100) +#define ELM_LOCATION_STATUS_ECC_NB_ERRORS_MASK (0x1F) + +#ifndef __KERNEL_STRICT_NAMES +#ifndef __ASSEMBLY__ + +enum bch_level { + BCH_4_BIT = 0, + BCH_8_BIT, + BCH_16_BIT +}; + + +/* BCH syndrome registers */ +struct syndrome { + u32 syndrome_fragment_x[7]; /* 0x400, 0x404.... 0x418 */ + u8 res1[36]; /* 0x41c */ +}; + +/* BCH error status & location register */ +struct location { + u32 location_status; /* 0x800 */ + u8 res1[124]; /* 0x804 */ + u32 error_location_x[16]; /* 0x880.... */ + u8 res2[64]; /* 0x8c0 */ +}; + +/* BCH ELM register map - do not try to allocate memmory for this structure. + * We have used plenty of reserved variables to fill the slots in the ELM + * register memory map. + * Directly initialize the struct pointer to ELM base address. + */ +struct elm { + u32 rev; /* 0x000 */ + u8 res1[12]; /* 0x004 */ + u32 sysconfig; /* 0x010 */ + u32 sysstatus; /* 0x014 */ + u32 irqstatus; /* 0x018 */ + u32 irqenable; /* 0x01c */ + u32 location_config; /* 0x020 */ + u8 res2[92]; /* 0x024 */ + u32 page_ctrl; /* 0x080 */ + u8 res3[892]; /* 0x084 */ + struct syndrome syndrome_fragments[8]; /* 0x400 */ + u8 res4[512]; /* 0x600 */ + struct location error_location[8]; /* 0x800 */ +}; + +int elm_check_error(u8 *syndrome, u32 nibbles, u32 *error_count, + u32 *error_locations); +int elm_config(enum bch_level level); +void elm_reset(void); +void elm_init(void); +void am33xx_nand_switch_ecc(nand_ecc_modes_t hardware, int32_t mode); +#endif /* __ASSEMBLY__ */ +#endif /* __KERNEL_STRICT_NAMES */ + + +#endif /* __ASM_ARCH_OMAP_GPMC_H */ diff --git a/arch/arm/include/asm/arch-exynos/system.h b/arch/arm/include/asm/arch-exynos/system.h index 7e2057ca62..d13af94495 100644 --- a/arch/arm/include/asm/arch-exynos/system.h +++ b/arch/arm/include/asm/arch-exynos/system.h @@ -10,7 +10,7 @@ #ifndef __ASSEMBLY__ struct exynos4_sysreg { - unsigned char res1[0x210]; + unsigned int res1[0x210 / 4]; unsigned int display_ctrl; unsigned int display_ctrl2; unsigned int camera_control; @@ -19,7 +19,7 @@ struct exynos4_sysreg { }; struct exynos5_sysreg { - unsigned char res1[0x214]; + unsigned int res1[0x214 / 4]; unsigned int disp1blk_cfg; unsigned int disp2blk_cfg; unsigned int hdcp_e_fuse; @@ -28,7 +28,7 @@ struct exynos5_sysreg { unsigned int reserved; unsigned int ispblk_cfg; unsigned int usb20phy_cfg; - unsigned char res2[0x29c]; + unsigned int res2[0x29c / 4]; unsigned int mipi_dphy; unsigned int dptx_dphy; unsigned int phyclk_sel; diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h index 406d150ae2..5d795bd7f5 100644 --- a/arch/arm/include/asm/arch-mx5/clock.h +++ b/arch/arm/include/asm/arch-mx5/clock.h @@ -41,10 +41,57 @@ enum mxc_clock { MXC_I2C_CLK, }; + +struct clk { + const char *name; + int id; + /* Source clock this clk depends on */ + struct clk *parent; + /* Secondary clock to enable/disable with this clock */ + struct clk *secondary; + /* Current clock rate */ + unsigned long rate; + /* Reference count of clock enable/disable */ + __s8 usecount; + /* Register bit position for clock's enable/disable control. */ + u8 enable_shift; + /* Register address for clock's enable/disable control. */ + void *enable_reg; + u32 flags; + /* + * Function ptr to recalculate the clock's rate based on parent + * clock's rate + */ + void (*recalc) (struct clk *); + /* + * Function ptr to set the clock to a new rate. The rate must match a + * supported rate returned from round_rate. Leave blank if clock is not + * programmable + */ + int (*set_rate) (struct clk *, unsigned long); + /* + * Function ptr to round the requested clock rate to the nearest + * supported rate that is less than or equal to the requested rate. + */ + unsigned long (*round_rate) (struct clk *, unsigned long); + /* + * Function ptr to enable the clock. Leave blank if clock can not + * be gated. + */ + int (*enable) (struct clk *); + /* + * Function ptr to disable the clock. Leave blank if clock can not + * be gated. + */ + void (*disable) (struct clk *); + /* Function ptr to set the parent clock of the clock. */ + int (*set_parent) (struct clk *, struct clk *); +}; + u32 imx_get_uartclk(void); u32 imx_get_fecclk(void); unsigned int mxc_get_clock(enum mxc_clock clk); -int mxc_set_clock(u32 ref, u32 freq, u32 clk_type); +int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk); void set_usb_phy_clk(void); void enable_usb_phy1_clk(unsigned char enable); void enable_usb_phy2_clk(unsigned char enable); @@ -53,5 +100,7 @@ void enable_usboh3_clk(unsigned char enable); void mxc_set_sata_internal_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); void enable_nfc_clk(unsigned char enable); +void ipu_clk_enable(void); +void ipu_clk_disable(void); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h index 392881c0e7..824d851804 100644 --- a/arch/arm/include/asm/arch-mx5/crm_regs.h +++ b/arch/arm/include/asm/arch-mx5/crm_regs.h @@ -40,7 +40,7 @@ struct mxc_ccm_reg { u32 cs1cdr; u32 cs2cdr; u32 cdcdr; /* 0x0030 */ - u32 chscdr; + u32 chsccdr; u32 cscdr2; u32 cscdr3; u32 cscdr4; /* 0x0040 */ @@ -303,7 +303,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCDR1_UART_CLK_PODF_RD(r) ((r) & 0x7) /* Define the bits in register CCDR */ -#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 17) +#define MXC_CCM_CCDR_IPU_HS_MASK (0x1 << 21) /* Define the bits in register CCGRx */ #define MXC_CCM_CCGR_CG_MASK 0x3 @@ -588,7 +588,7 @@ struct mxc_ccm_reg { #endif /* Define the bits in register CLPCR */ -#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) +#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) #define MXC_DPLLC_CTL_HFSM (1 << 7) #define MXC_DPLLC_CTL_DPDCK0_2_EN (1 << 12) diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h index 4955ccff87..b38a40caef 100644 --- a/arch/arm/include/asm/arch-mx5/imx-regs.h +++ b/arch/arm/include/asm/arch-mx5/imx-regs.h @@ -13,24 +13,24 @@ #define IRAM_BASE_ADDR 0x1FFE0000 /* internal ram */ #define IPU_SOC_BASE_ADDR 0x40000000 #define IPU_SOC_OFFSET 0x1E000000 -#define SPBA0_BASE_ADDR 0x70000000 -#define AIPS1_BASE_ADDR 0x73F00000 -#define AIPS2_BASE_ADDR 0x83F00000 -#define CSD0_BASE_ADDR 0x90000000 -#define CSD1_BASE_ADDR 0xA0000000 -#define NFC_BASE_ADDR_AXI 0xCFFF0000 -#define CS1_BASE_ADDR 0xB8000000 +#define SPBA0_BASE_ADDR 0x70000000 +#define AIPS1_BASE_ADDR 0x73F00000 +#define AIPS2_BASE_ADDR 0x83F00000 +#define CSD0_BASE_ADDR 0x90000000 +#define CSD1_BASE_ADDR 0xA0000000 +#define NFC_BASE_ADDR_AXI 0xCFFF0000 +#define CS1_BASE_ADDR 0xB8000000 #elif defined(CONFIG_MX53) #define IPU_SOC_BASE_ADDR 0x18000000 #define IPU_SOC_OFFSET 0x06000000 -#define SPBA0_BASE_ADDR 0x50000000 -#define AIPS1_BASE_ADDR 0x53F00000 -#define AIPS2_BASE_ADDR 0x63F00000 -#define CSD0_BASE_ADDR 0x70000000 -#define CSD1_BASE_ADDR 0xB0000000 -#define NFC_BASE_ADDR_AXI 0xF7FF0000 -#define IRAM_BASE_ADDR 0xF8000000 -#define CS1_BASE_ADDR 0xF4000000 +#define SPBA0_BASE_ADDR 0x50000000 +#define AIPS1_BASE_ADDR 0x53F00000 +#define AIPS2_BASE_ADDR 0x63F00000 +#define CSD0_BASE_ADDR 0x70000000 +#define CSD1_BASE_ADDR 0xB0000000 +#define NFC_BASE_ADDR_AXI 0xF7FF0000 +#define IRAM_BASE_ADDR 0xF8000000 +#define CS1_BASE_ADDR 0xF4000000 #define SATA_BASE_ADDR 0x10000000 #else #error "CPU_TYPE not defined" @@ -44,7 +44,7 @@ #define MMC_SDHC1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00004000) #define MMC_SDHC2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00008000) #define UART3_BASE (SPBA0_BASE_ADDR + 0x0000C000) -#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) +#define CSPI1_BASE_ADDR (SPBA0_BASE_ADDR + 0x00010000) #define SSI2_BASE_ADDR (SPBA0_BASE_ADDR + 0x00014000) #define MMC_SDHC3_BASE_ADDR (SPBA0_BASE_ADDR + 0x00020000) #define MMC_SDHC4_BASE_ADDR (SPBA0_BASE_ADDR + 0x00024000) @@ -79,11 +79,11 @@ #define GPC_BASE_ADDR (AIPS1_BASE_ADDR + 0x000D8000) #if defined(CONFIG_MX53) -#define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000) -#define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000) -#define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000) +#define GPIO5_BASE_ADDR (AIPS1_BASE_ADDR + 0x000DC000) +#define GPIO6_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E0000) +#define GPIO7_BASE_ADDR (AIPS1_BASE_ADDR + 0x000E4000) #define I2C3_BASE_ADDR (AIPS1_BASE_ADDR + 0x000EC000) -#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000) +#define UART4_BASE_ADDR (AIPS1_BASE_ADDR + 0x000F0000) #endif /* * AIPS 2 @@ -98,7 +98,7 @@ #define IIM_BASE_ADDR (AIPS2_BASE_ADDR + 0x00098000) #define CSU_BASE_ADDR (AIPS2_BASE_ADDR + 0x0009C000) #define ARM_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A0000) -#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) +#define OWIRE_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A4000) #define FIRI_BASE_ADDR (AIPS2_BASE_ADDR + 0x000A8000) #define CSPI2_BASE_ADDR (AIPS2_BASE_ADDR + 0x000AC000) #define SDMA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000B0000) @@ -125,7 +125,7 @@ #define SAHARA_BASE_ADDR (AIPS2_BASE_ADDR + 0x000F8000) #if defined(CONFIG_MX53) -#define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) +#define UART5_BASE_ADDR (AIPS2_BASE_ADDR + 0x00090000) #endif /* @@ -202,6 +202,16 @@ */ #define WBED 1 +/* + * WEIM WCR + */ +#define BCM 1 +#define GBCD(x) (((x) & 0x3) << 1) +#define INTEN (1 << 4) +#define INTPOL (1 << 5) +#define WDOG_EN (1 << 8) +#define WDOG_LIMIT(x) (((x) & 0x3) << 9) + #define CS0_128 0 #define CS0_64M_CS1_64M 1 #define CS0_64M_CS1_32M_CS2_32M 2 @@ -241,7 +251,7 @@ /* * Number of GPIO pins per port */ -#define GPIO_NUM_PIN 32 +#define GPIO_NUM_PIN 32 #define IIM_SREV 0x24 #define ROM_SI_REV 0x48 @@ -277,34 +287,46 @@ #define DP_MFD_665 (96 - 1) #define DP_MFN_665 89 +#define DP_OP_600 ((6 << 4) + ((1 - 1) << 0)) +#define DP_MFD_600 (4 - 1) +#define DP_MFN_600 1 + #define DP_OP_532 ((5 << 4) + ((1 - 1) << 0)) #define DP_MFD_532 (24 - 1) #define DP_MFN_532 13 -#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0)) -#define DP_MFD_400 (3 - 1) -#define DP_MFN_400 1 +#define DP_OP_533 ((5 << 4) + ((1 - 1) << 0)) +#define DP_MFD_533 (9 - 1) +#define DP_MFN_533 5 #define DP_OP_455 ((9 << 4) + ((2 - 1) << 0)) #define DP_MFD_455 (48 - 1) #define DP_MFN_455 23 +#define DP_OP_400 ((8 << 4) + ((2 - 1) << 0)) +#define DP_MFD_400 (3 - 1) +#define DP_MFN_400 1 + +#define DP_OP_333 ((6 << 4) + ((2 - 1) << 0)) +#define DP_MFD_333 (16 - 1) +#define DP_MFN_333 15 + #define DP_OP_216 ((6 << 4) + ((3 - 1) << 0)) #define DP_MFD_216 (4 - 1) #define DP_MFN_216 3 -#define CHIP_REV_1_0 0x10 -#define CHIP_REV_1_1 0x11 -#define CHIP_REV_2_0 0x20 -#define CHIP_REV_2_5 0x25 -#define CHIP_REV_3_0 0x30 +#define CHIP_REV_1_0 0x10 +#define CHIP_REV_1_1 0x11 +#define CHIP_REV_2_0 0x20 +#define CHIP_REV_2_5 0x25 +#define CHIP_REV_3_0 0x30 -#define BOARD_REV_1_0 0x0 -#define BOARD_REV_2_0 0x1 +#define BOARD_REV_1_0 0x0 +#define BOARD_REV_2_0 0x1 #define BOARD_VER_OFFSET 0x8 -#define IMX_IIM_BASE (IIM_BASE_ADDR) +#define IMX_IIM_BASE IIM_BASE_ADDR #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include @@ -477,7 +499,7 @@ struct cspi_regs { struct iim_regs { u32 stat; u32 statm; - u32 err; + u32 err; u32 emask; u32 fctl; u32 ua; @@ -485,7 +507,7 @@ struct iim_regs { u32 sdat; u32 prev; u32 srev; - u32 prg_p; + u32 preg_p; u32 scs0; u32 scs1; u32 scs2; diff --git a/arch/arm/include/asm/arch-mx5/iomux-mx51.h b/arch/arm/include/asm/arch-mx5/iomux-mx51.h index 70aaa37f9d..532ae4d62c 100644 --- a/arch/arm/include/asm/arch-mx5/iomux-mx51.h +++ b/arch/arm/include/asm/arch-mx5/iomux-mx51.h @@ -22,25 +22,30 @@ #include /* Pad control groupings */ -#define MX51_UART_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \ +#define MX51_UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \ PAD_CTL_HYS | PAD_CTL_SRE_FAST) -#define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ +#define MX51_I2C_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ PAD_CTL_HYS) -#define MX51_ESDHC_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ +#define MX51_ESDHC_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \ PAD_CTL_HYS) -#define MX51_USBH_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ +#define MX51_USBH_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) -#define MX51_ECSPI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_HYS | \ +#define MX51_ECSPI_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_HYS | \ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) -#define MX51_SDHCI_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \ +#define MX51_SDHCI_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \ PAD_CTL_SRE_FAST | PAD_CTL_DVS) -#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST) +#define MX51_GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST) -#define MX51_PAD_CTRL_2 (PAD_CTL_PKE | PAD_CTL_HYS) -#define MX51_PAD_CTRL_4 (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS) -#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) +#define MX51_PAD_CTRL_2 MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_HYS) +#define MX51_PAD_CTRL_4 MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS) +#define MX51_PAD_CTRL_5 MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_DSE_HIGH) + +#define MX51_PAD_CTRL_2 MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_HYS) +#define MX51_PAD_CTRL_3 MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) +#define MX51_PAD_CTRL_4 MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS) +#define MX51_PAD_CTRL_5 MUX_PAD_CTRL(PAD_CTL_DVS | PAD_CTL_DSE_HIGH) /* * The naming convention for the pad modes is MX51_PAD___ @@ -66,6 +71,9 @@ enum { MX51_PAD_EIM_A16__GPIO2_10 = IOMUX_PAD(0x430, 0x09c, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), MX51_PAD_EIM_A17__GPIO2_11 = IOMUX_PAD(0x434, 0x0a0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), MX51_PAD_EIM_A20__GPIO2_14 = IOMUX_PAD(0x440, 0x0ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_EIM_A21__BOOT_UART_SRC1 = IOMUX_PAD(0x444, 0x0b0, 7, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_EIM_A21__EIM_A21 = IOMUX_PAD(0x444, 0x0b0, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_EIM_A21__GPIO2_15 = IOMUX_PAD(0x444, 0x0b0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), MX51_PAD_EIM_A22__GPIO2_16 = IOMUX_PAD(0x448, 0x0b4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), MX51_PAD_EIM_A24__USBH2_CLK = IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, MX51_USBH_PAD_CTRL), MX51_PAD_EIM_A25__USBH2_DIR = IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, MX51_USBH_PAD_CTRL), @@ -82,6 +90,12 @@ enum { MX51_PAD_EIM_CS3__GPIO2_28 = IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), MX51_PAD_EIM_CS4__FEC_RX_ER = IOMUX_PAD(0x484, 0x0f0, 3, 0x970, 0, MX51_PAD_CTRL_2), MX51_PAD_EIM_CS4__GPIO2_29 = IOMUX_PAD(0x484, 0x0f0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_EIM_CS5__AUD5_TXFS = IOMUX_PAD(0x488, 0x0f4, 6, 0x8e8, 1, NO_PAD_CTRL), + MX51_PAD_EIM_CS5__CSI1_D7 = IOMUX_PAD(0x488, 0x0f4, 5, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_EIM_CS5__DISP1_EXT_CLK = IOMUX_PAD(0x488, 0x0f4, 4, 0x904, 0, NO_PAD_CTRL), + MX51_PAD_EIM_CS5__EIM_CS5 = IOMUX_PAD(0x488, 0x0f4, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_EIM_CS5__GPIO2_30 = IOMUX_PAD(0x488, 0x0f4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_EIM_CS5__USBOTG_DIR = IOMUX_PAD(0x488, 0x0f4, 2, __NA_, 0, NO_PAD_CTRL), MX51_PAD_EIM_CS5__FEC_CRS = IOMUX_PAD(0x488, 0x0f4, 3, 0x950, 0, MX51_PAD_CTRL_2), MX51_PAD_DRAM_RAS__DRAM_RAS = IOMUX_PAD(0x4a4, __NA_, 0, __NA_, 0, NO_PAD_CTRL), MX51_PAD_DRAM_CAS__DRAM_CAS = IOMUX_PAD(0x4a8, __NA_, 0, __NA_, 0, NO_PAD_CTRL), @@ -111,8 +125,13 @@ enum { MX51_PAD_NANDF_RB3__FEC_RX_CLK = IOMUX_PAD(0x504, 0x128, 1, 0x968, 0, MX51_PAD_CTRL_2), MX51_PAD_NANDF_RB3__GPIO3_11 = IOMUX_PAD(0x504, 0x128, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), MX51_PAD_GPIO_NAND__PATA_INTRQ = IOMUX_PAD(0x514, 0x12c, 1, __NA_, 0, NO_PAD_CTRL), - MX51_PAD_NANDF_CS2__FEC_TX_ER = IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5), + MX51_PAD_NANDF_CS2__NANDF_CS2 = IOMUX_PAD(0x520, 0x138, 0, __NA_, 0, NO_PAD_CTRL), MX51_PAD_NANDF_CS2__PATA_CS_0 = IOMUX_PAD(0x520, 0x138, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_NANDF_CS2__FEC_TX_ER = IOMUX_PAD(0x520, 0x138, 2, __NA_, 0, MX51_PAD_CTRL_5), + MX51_PAD_NANDF_CS2__GPIO3_18 = IOMUX_PAD(0x520, 0x138, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_NANDF_CS2__SD4_CLK = IOMUX_PAD(0x520, 0x138, 5, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS), + MX51_PAD_NANDF_CS2__CSPI_SCLK = IOMUX_PAD(0x520, 0x138, 6, 0x914, 0, MX51_ECSPI_PAD_CTRL), + MX51_PAD_NANDF_CS2__USBH3_H1_DP = IOMUX_PAD(0x520, 0x138, 7, __NA_, 0, NO_PAD_CTRL), MX51_PAD_NANDF_CS3__FEC_MDC = IOMUX_PAD(0x524, 0x13c, 2, __NA_, 0, MX51_PAD_CTRL_5), MX51_PAD_NANDF_CS3__PATA_CS_1 = IOMUX_PAD(0x524, 0x13c, 1, __NA_, 0, NO_PAD_CTRL), MX51_PAD_NANDF_CS4__FEC_TDATA1 = IOMUX_PAD(0x528, 0x140, 2, __NA_, 0, MX51_PAD_CTRL_5), @@ -149,6 +168,14 @@ enum { MX51_PAD_NANDF_D0__PATA_DATA0 = IOMUX_PAD(0x578, 0x190, 1, __NA_, 0, NO_PAD_CTRL), MX51_PAD_CSI2_D12__GPIO4_9 = IOMUX_PAD(0x5bc, 0x1cc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), MX51_PAD_CSI2_D13__GPIO4_10 = IOMUX_PAD(0x5c0, 0x1d0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_CSI2_VSYNC__CSI2_VSYNC = IOMUX_PAD(0x5dc, 0x1ec, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_CSI2_VSYNC__GPIO4_13 = IOMUX_PAD(0x5dc, 0x1ec, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_CSI2_HSYNC__CSI2_HSYNC = IOMUX_PAD(0x5e0, 0x1f0, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_CSI2_HSYNC__GPIO4_14 = IOMUX_PAD(0x5e0, 0x1f0, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_I2C1_CLK__GPIO4_16 = IOMUX_PAD(0x5e8, 0x1f8, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_I2C1_CLK__I2C1_CLK = IOMUX_PAD(0x5e8, 0x1f8, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL), + MX51_PAD_I2C1_DAT__GPIO4_17 = IOMUX_PAD(0x5ec, 0x1fc, 3, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_I2C1_DAT__I2C1_DAT = IOMUX_PAD(0x5ec, 0x1fc, 0x10, __NA_, 0, MX51_I2C_PAD_CTRL), MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI = IOMUX_PAD(0x600, 0x210, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL), MX51_PAD_CSPI1_MISO__ECSPI1_MISO = IOMUX_PAD(0x604, 0x214, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL), MX51_PAD_CSPI1_SS0__ECSPI1_SS0 = IOMUX_PAD(0x608, 0x218, 0, __NA_, 0, MX51_ECSPI_PAD_CTRL), @@ -182,6 +209,65 @@ enum { MX51_PAD_DI1_D1_CS__GPIO3_4 = IOMUX_PAD(0x6b8, 0x2b8, 4, 0x984, 1, MX51_GPIO_PAD_CTRL), MX51_PAD_DISPB2_SER_DIN__GPIO3_5 = IOMUX_PAD(0x6bc, 0x2bc, 4, 0x988, 1, MX51_GPIO_PAD_CTRL), MX51_PAD_DISPB2_SER_DIO__GPIO3_6 = IOMUX_PAD(0x6c0, 0x2c0, 4, 0x98c, 1, MX51_GPIO_PAD_CTRL), + MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS = IOMUX_PAD(0x6c8, 0x2c8, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 = IOMUX_PAD(0x6c8, 0x2c8, 2, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 = IOMUX_PAD(0x6c8, 0x2c8, 3, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISPB2_SER_RS__GPIO3_8 = IOMUX_PAD(0x6c8, 0x2c8, 4, 0x994, 1, MX51_GPIO_PAD_CTRL), + MX51_PAD_DISP1_DAT0__DISP1_DAT0 = IOMUX_PAD(0x6cc, 0x2cc, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT1__DISP1_DAT1 = IOMUX_PAD(0x6d0, 0x2d0, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT2__DISP1_DAT2 = IOMUX_PAD(0x6d4, 0x2d4, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT3__DISP1_DAT3 = IOMUX_PAD(0x6d8, 0x2d8, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT4__DISP1_DAT4 = IOMUX_PAD(0x6dc, 0x2dc, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT5__DISP1_DAT5 = IOMUX_PAD(0x6e0, 0x2e0, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT6__BOOT_USB_SRC = IOMUX_PAD(0x6e4, 0x2e4, 7, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT6__DISP1_DAT6 = IOMUX_PAD(0x6e4, 0x2e4, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG = IOMUX_PAD(0x6e8, 0x2e8, 7, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT7__DISP1_DAT7 = IOMUX_PAD(0x6e8, 0x2e8, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT8__BOOT_SRC0 = IOMUX_PAD(0x6ec, 0x2ec, 7, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT8__DISP1_DAT8 = IOMUX_PAD(0x6ec, 0x2ec, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT9__BOOT_SRC1 = IOMUX_PAD(0x6f0, 0x2f0, 7, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT9__DISP1_DAT9 = IOMUX_PAD(0x6f0, 0x2f0, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE = IOMUX_PAD(0x6f4, 0x2f4, 7, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT10__DISP1_DAT10 = IOMUX_PAD(0x6f4, 0x2f4, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 = IOMUX_PAD(0x6f8, 0x2f8, 7, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT11__DISP1_DAT11 = IOMUX_PAD(0x6f8, 0x2f8, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL = IOMUX_PAD(0x6fc, 0x2fc, 7, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT12__DISP1_DAT12 = IOMUX_PAD(0x6fc, 0x2fc, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 = IOMUX_PAD(0x700, 0x300, 7, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT13__DISP1_DAT13 = IOMUX_PAD(0x700, 0x300, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 = IOMUX_PAD(0x704, 0x304, 7, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT14__DISP1_DAT14 = IOMUX_PAD(0x704, 0x304, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH = IOMUX_PAD(0x708, 0x308, 7, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT15__DISP1_DAT15 = IOMUX_PAD(0x708, 0x308, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 = IOMUX_PAD(0x70c, 0x30c, 7, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT16__DISP1_DAT16 = IOMUX_PAD(0x70c, 0x30c, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 = IOMUX_PAD(0x710, 0x310, 7, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT17__DISP1_DAT17 = IOMUX_PAD(0x710, 0x310, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 = IOMUX_PAD(0x714, 0x314, 7, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT18__DISP1_DAT18 = IOMUX_PAD(0x714, 0x314, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT18__DISP2_PIN11 = IOMUX_PAD(0x714, 0x314, 5, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT18__DISP2_PIN5 = IOMUX_PAD(0x714, 0x314, 4, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 = IOMUX_PAD(0x718, 0x318, 7, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT19__DISP1_DAT19 = IOMUX_PAD(0x718, 0x318, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT19__DISP2_PIN12 = IOMUX_PAD(0x718, 0x318, 5, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT19__DISP2_PIN6 = IOMUX_PAD(0x718, 0x318, 4, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 = IOMUX_PAD(0x71c, 0x31c, 7, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT20__DISP1_DAT20 = IOMUX_PAD(0x71c, 0x31c, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT20__DISP2_PIN13 = IOMUX_PAD(0x71c, 0x31c, 5, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT20__DISP2_PIN7 = IOMUX_PAD(0x71c, 0x31c, 4, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 = IOMUX_PAD(0x720, 0x320, 7, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT21__DISP1_DAT21 = IOMUX_PAD(0x720, 0x320, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT21__DISP2_PIN14 = IOMUX_PAD(0x720, 0x320, 5, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT21__DISP2_PIN8 = IOMUX_PAD(0x720, 0x320, 4, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 = IOMUX_PAD(0x724, 0x324, 7, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT22__DISP1_DAT22 = IOMUX_PAD(0x724, 0x324, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT22__DISP2_D0_CS = IOMUX_PAD(0x724, 0x324, 6, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT22__DISP2_DAT16 = IOMUX_PAD(0x724, 0x324, 5, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 = IOMUX_PAD(0x728, 0x328, 7, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT23__DISP1_DAT23 = IOMUX_PAD(0x728, 0x328, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT23__DISP2_D1_CS = IOMUX_PAD(0x728, 0x328, 6, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT23__DISP2_DAT17 = IOMUX_PAD(0x728, 0x328, 5, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_DISP1_DAT23__DISP2_SER_CS = IOMUX_PAD(0x728, 0x328, 4, __NA_, 0, NO_PAD_CTRL), MX51_PAD_DI1_PIN3__DI1_PIN3 = IOMUX_PAD(0x72c, 0x32c, 0, __NA_, 0, NO_PAD_CTRL), MX51_PAD_DI1_PIN2__DI1_PIN2 = IOMUX_PAD(0x734, 0x330, 0, __NA_, 0, NO_PAD_CTRL), MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK = IOMUX_PAD(0x754, 0x34c, 0, __NA_, 0, NO_PAD_CTRL), @@ -195,6 +281,8 @@ enum { MX51_PAD_GPIO1_0__GPIO1_0 = IOMUX_PAD(0x7b4, 0x3ac, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), MX51_PAD_GPIO1_0__SD1_CD = IOMUX_PAD(0x7b4, 0x3ac, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL), MX51_PAD_GPIO1_1__SD1_WP = IOMUX_PAD(0x7b8, 0x3b0, 0, __NA_, 0, MX51_ESDHC_PAD_CTRL), + MX51_PAD_GPIO1_1__GPIO1_1 = IOMUX_PAD(0x7b8, 0x3b0, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_GPIO1_1__CSPI_MISO = IOMUX_PAD(0x7b8, 0x3b0, 2, 0x918, 2, MX51_ECSPI_PAD_CTRL), MX51_PAD_SD2_CMD__SD2_CMD = IOMUX_PAD(0x7bc, 0x3b4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), MX51_PAD_SD2_CLK__SD2_CLK = IOMUX_PAD(0x7c0, 0x3b8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS), MX51_PAD_SD2_DATA0__SD2_DATA0 = IOMUX_PAD(0x7c4, 0x3bc, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), @@ -204,11 +292,24 @@ enum { MX51_PAD_GPIO1_2__GPIO1_2 = IOMUX_PAD(0x7d4, 0x3cc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), MX51_PAD_GPIO1_2__PWM1_PWMO = IOMUX_PAD(0x7d4, 0x3cc, 1, __NA_, 0, NO_PAD_CTRL), MX51_PAD_GPIO1_3__GPIO1_3 = IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_GPIO1_4__DISP2_EXT_CLK = IOMUX_PAD(0x804, 0x3d8, 4, 0x908, 1, NO_PAD_CTRL), + MX51_PAD_GPIO1_4__EIM_RDY = IOMUX_PAD(0x804, 0x3d8, 3, 0x938, 1, NO_PAD_CTRL), + MX51_PAD_GPIO1_4__GPIO1_4 = IOMUX_PAD(0x804, 0x3d8, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_GPIO1_4__WDOG1_WDOG_B = IOMUX_PAD(0x804, 0x3d8, 2, __NA_, 0, NO_PAD_CTRL), MX51_PAD_GPIO1_5__GPIO1_5 = IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), MX51_PAD_GPIO1_6__GPIO1_6 = IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), MX51_PAD_GPIO1_7__GPIO1_7 = IOMUX_PAD(0x810, 0x3e4, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), MX51_PAD_GPIO1_7__SD2_WP = IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL), + MX51_PAD_GPIO1_8__CSI2_DATA_EN = IOMUX_PAD(0x814, 0x3e8, 2, 0x99c, 2, NO_PAD_CTRL), + MX51_PAD_GPIO1_8__GPIO1_8 = IOMUX_PAD(0x814, 0x3e8, 0, __NA_, 0, NO_PAD_CTRL), MX51_PAD_GPIO1_8__SD2_CD = IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL), + MX51_PAD_GPIO1_9__CCM_OUT_1 = IOMUX_PAD(0x818, 0x3ec, 3, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_GPIO1_9__DISP2_D1_CS = IOMUX_PAD(0x818, 0x3ec, 2, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_GPIO1_9__DISP2_SER_CS = IOMUX_PAD(0x818, 0x3ec, 7, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_GPIO1_9__GPIO1_9 = IOMUX_PAD(0x818, 0x3ec, 0, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_GPIO1_9__SD2_LCTL = IOMUX_PAD(0x818, 0x3ec, 6, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_GPIO1_9__USBH3_OC = IOMUX_PAD(0x818, 0x3ec, 1, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_GPIO1_8__USBH3_PWR = IOMUX_PAD(0x814, 0x3e8, 1, __NA_, 0, NO_PAD_CTRL), MX51_GRP_DDRPKS = IOMUX_PAD(0x820, __NA_, 0, __NA_, 0, NO_PAD_CTRL), MX51_GRP_DRAM_B4 = IOMUX_PAD(0x82c, __NA_, 0, __NA_, 0, NO_PAD_CTRL), MX51_GRP_PKEDDR = IOMUX_PAD(0x838, __NA_, 0, __NA_, 0, NO_PAD_CTRL), diff --git a/arch/arm/include/asm/arch-mx5/iomux-mx53.h b/arch/arm/include/asm/arch-mx5/iomux-mx53.h index 1b75fd1cfd..bc62621ea3 100644 --- a/arch/arm/include/asm/arch-mx5/iomux-mx53.h +++ b/arch/arm/include/asm/arch-mx5/iomux-mx53.h @@ -14,9 +14,9 @@ #include /* Pad control groupings */ -#define MX53_UART_PAD_CTRL (PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \ +#define MX53_UART_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN | PAD_CTL_DSE_HIGH | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) -#define MX53_SDHC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ +#define MX53_SDHC_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \ PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST) /* diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h index 9949ad1312..b164ec4f4e 100644 --- a/arch/arm/include/asm/arch-mx5/sys_proto.h +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h @@ -20,6 +20,7 @@ u32 get_cpu_rev(void); unsigned imx_ddr_size(void); void sdelay(unsigned long); void set_chipselect_size(int const); +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); /* * Initializes on-chip ethernet controllers. diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 21a4fbb59a..7d8915da01 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -42,12 +42,64 @@ enum mxc_clock { MXC_I2C_CLK, }; + +struct clk { + const char *name; + int id; + /* Source clock this clk depends on */ + struct clk *parent; + /* Secondary clock to enable/disable with this clock */ + struct clk *secondary; + /* Current clock rate */ + unsigned long rate; + /* Reference count of clock enable/disable */ + __s8 usecount; + /* Register bit position for clock's enable/disable control. */ + u8 enable_shift; + /* Register address for clock's enable/disable control. */ + void *enable_reg; + u32 flags; + /* + * Function ptr to recalculate the clock's rate based on parent + * clock's rate + */ + void (*recalc) (struct clk *); + /* + * Function ptr to set the clock to a new rate. The rate must match a + * supported rate returned from round_rate. Leave blank if clock is not + * programmable + */ + int (*set_rate) (struct clk *, unsigned long); + /* + * Function ptr to round the requested clock rate to the nearest + * supported rate that is less than or equal to the requested rate. + */ + unsigned long (*round_rate) (struct clk *, unsigned long); + /* + * Function ptr to enable the clock. Leave blank if clock can not + * be gated. + */ + int (*enable) (struct clk *); + /* + * Function ptr to disable the clock. Leave blank if clock can not + * be gated. + */ + void (*disable) (struct clk *); + /* Function ptr to set the parent clock of the clock. */ + int (*set_parent) (struct clk *, struct clk *); +}; + u32 imx_get_uartclk(void); u32 imx_get_fecclk(void); unsigned int mxc_get_clock(enum mxc_clock clk); +int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk); void enable_ocotp_clk(unsigned char enable); void enable_usboh3_clk(unsigned char enable); int enable_sata_clock(void); int enable_i2c_clk(unsigned char enable, unsigned i2c_num); +void ipu_clk_enable(void); +void ipu_clk_disable(void); +void ocotp_clk_enable(void); +void ocotp_clk_disable(void); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 74aefe60f4..c5e1ac2160 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -55,65 +55,61 @@ struct mxc_ccm_reg { u32 CCGR6; /* 0x0080 */ u32 CCGR7; u32 cmeor; - u32 resv[0xfdd]; - u32 analog_pll_sys; /* 0x4000 */ - u32 analog_pll_sys_set; - u32 analog_pll_sys_clr; - u32 analog_pll_sys_tog; - u32 analog_usb1_pll_480_ctrl; /* 0x4010 */ - u32 analog_usb1_pll_480_ctrl_set; - u32 analog_usb1_pll_480_ctrl_clr; - u32 analog_usb1_pll_480_ctrl_tog; - u32 analog_reserved0[4]; - u32 analog_pll_528; /* 0x4030 */ - u32 analog_pll_528_set; - u32 analog_pll_528_clr; - u32 analog_pll_528_tog; - u32 analog_pll_528_ss; /* 0x4040 */ - u32 analog_reserved1[3]; - u32 analog_pll_528_num; /* 0x4050 */ - u32 analog_reserved2[3]; - u32 analog_pll_528_denom; /* 0x4060 */ - u32 analog_reserved3[3]; - u32 analog_pll_audio; /* 0x4070 */ - u32 analog_pll_audio_set; - u32 analog_pll_audio_clr; - u32 analog_pll_audio_tog; - u32 analog_pll_audio_num; /* 0x4080*/ - u32 analog_reserved4[3]; - u32 analog_pll_audio_denom; /* 0x4090 */ - u32 analog_reserved5[3]; - u32 analog_pll_video; /* 0x40a0 */ - u32 analog_pll_video_set; - u32 analog_pll_video_clr; - u32 analog_pll_video_tog; - u32 analog_pll_video_num; /* 0x40b0 */ - u32 analog_reserved6[3]; - u32 analog_pll_vedio_denon; /* 0x40c0 */ - u32 analog_reserved7[7]; - u32 analog_pll_enet; /* 0x40e0 */ - u32 analog_pll_enet_set; - u32 analog_pll_enet_clr; - u32 analog_pll_enet_tog; - u32 analog_pfd_480; /* 0x40f0 */ - u32 analog_pfd_480_set; - u32 analog_pfd_480_clr; - u32 analog_pfd_480_tog; - u32 analog_pfd_528; /* 0x4100 */ - u32 analog_pfd_528_set; - u32 analog_pfd_528_clr; - u32 analog_pfd_528_tog; +}; + +struct anatop_regs { + mxs_reg_32(pll_arm); /* 0x000 */ + mxs_reg_32(usb1_pll_480_ctrl); /* 0x010 */ + mxs_reg_32(usb2_pll_480_ctrl); /* 0x020 */ + mxs_reg_32(pll_528); /* 0x030 */ + reg_32(pll_528_ss); /* 0x040 */ + reg_32(pll_528_num); /* 0x050 */ + reg_32(pll_528_denom); /* 0x060 */ + mxs_reg_32(pll_audio); /* 0x070 */ + reg_32(pll_audio_num); /* 0x080 */ + reg_32(pll_audio_denom); /* 0x090 */ + mxs_reg_32(pll_video); /* 0x0a0 */ + reg_32(pll_video_num); /* 0x0b0 */ + reg_32(pll_video_denom); /* 0x0c0 */ + mxs_reg_32(pll_mlb); /* 0x0d0 */ + mxs_reg_32(pll_enet); /* 0x0e0 */ + mxs_reg_32(pfd_480); /* 0x0f0 */ + mxs_reg_32(pfd_528); /* 0x100 */ + mxs_reg_32(reg_1p1); /* 0x110 */ + mxs_reg_32(reg_3p0); /* 0x120 */ + mxs_reg_32(reg_2p5); /* 0x130 */ + mxs_reg_32(reg_core); /* 0x140 */ + mxs_reg_32(ana_misc0); /* 0x150 */ + mxs_reg_32(ana_misc1); /* 0x160 */ + mxs_reg_32(ana_misc2); /* 0x170 */ + mxs_reg_32(tempsense0); /* 0x180 */ + mxs_reg_32(tempsense1); /* 0x190 */ + mxs_reg_32(usb1_vbus_detect); /* 0x1a0 */ + mxs_reg_32(usb1_chrg_detect); /* 0x1b0 */ + mxs_reg_32(usb1_vbus_det_stat); /* 0x1c0 */ + mxs_reg_32(usb1_chrg_det_stat); /* 0x1d0 */ + mxs_reg_32(usb1_loopback); /* 0x1e0 */ + mxs_reg_32(usb1_misc); /* 0x1f0 */ + mxs_reg_32(usb2_vbus_detect); /* 0x200 */ + mxs_reg_32(usb2_chrg_detect); /* 0x210 */ + mxs_reg_32(usb2_vbus_det_stat); /* 0x220 */ + mxs_reg_32(usb2_chrg_det_stat); /* 0x230 */ + mxs_reg_32(usb2_loopback); /* 0x240 */ + mxs_reg_32(usb2_misc); /* 0x250 */ + reg_32(digprog); /* 0x260 */ + reg_32(rsrvd); /* 0x270 */ + reg_32(digprog_sololite); /* 0x280 */ }; #endif /* Define the bits in register CCR */ #define MXC_CCM_CCR_RBC_EN (1 << 27) -#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21) +#define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << CCR_REG_BYPASS_CNT_OFFSET) #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21 -#define MXC_CCM_CCR_WB_COUNT_MASK 0x7 +#define MXC_CCM_CCR_WB_COUNT_MASK (0x7 << MXC_CCM_CCR_WB_COUNT_OFFSET) #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) #define MXC_CCM_CCR_COSC_EN (1 << 12) -#define MXC_CCM_CCR_OSCNT_MASK 0xFF +#define MXC_CCM_CCR_OSCNT_MASK (0xFF << MXC_CCM_CCR_OSCNT_OFFSET) #define MXC_CCM_CCR_OSCNT_OFFSET 0 /* Define the bits in register CCDR */ @@ -139,197 +135,195 @@ struct mxc_ccm_reg { /* Define the bits in register CACRR */ #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0 -#define MXC_CCM_CACRR_ARM_PODF_MASK 0x7 +#define MXC_CCM_CACRR_ARM_PODF_MASK (0x7 << MXC_CCM_CACRR_ARM_PODF_OFFSET) /* Define the bits in register CBCDR */ -#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27) +#define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET) #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27 #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26) #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25) -#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19) +#define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET) #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19 -#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16) +#define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << MXC_CCM_CBCDR_AXI_PODF_OFFSET) #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16 -#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10) +#define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << MXC_CCM_CBCDR_AHB_PODF_OFFSET) #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10 -#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8) +#define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << MXC_CCM_CBCDR_IPG_PODF_OFFSET) #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7) #define MXC_CCM_CBCDR_AXI_SEL (1 << 6) -#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3) +#define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET) #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3 -#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0) +#define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET) #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0 /* Define the bits in register CBCMR */ -#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29) +#define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET) #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29 -#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26) +#define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET) #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26 -#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23) +#define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET) #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 -#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) +#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20) -#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18) +#define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET) #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18 -#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET) #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16 -#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET) #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 -#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12) +#define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET) #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11) #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10) -#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET) #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8 -#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) +#define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET) #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1) #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0) /* Define the bits in register CSCMR1 */ -#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29) +#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET) #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29 -#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27) +#define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << MXC_CCM_CSCMR1_ACLK_EMI_OFFSET) #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27 -#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23) +#define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET) #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23 -#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) +#define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET) #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19) #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18) #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16) -#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET) #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14 -#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12) +#define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET) #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 -#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10) +#define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET) #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10 -#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F +#define MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET 0 +#define MXC_CCM_CSCMR1_PERCLK_PODF_MASK (0x3F << MXC_CCM_CSCMR1_PERCLK_PODF_OFFSET) /* Define the bits in register CSCMR2 */ -#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19) +#define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET) #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) -#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2) +#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET) #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2 /* Define the bits in register CSCDR1 */ -#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25) +#define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET) #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25 -#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22) +#define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET) #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22 -#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19) +#define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET) #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19 -#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16) +#define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET) #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16 -#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11) +#define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET) #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 -#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET) #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 -#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) +#define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET) #ifdef CONFIG_MX6SL -#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x1F -#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) +#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x1F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) +#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET) #else -#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F +#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET) #endif +#define MXC_CCM_CSCDR1_UART_CLK_SEL_OFFSET 6 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 /* Define the bits in register CS1CDR */ -#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) +#define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET) #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25 -#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16) +#define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET) #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16 -#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9) +#define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET) #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9 -#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET) #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6 -#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F +#define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK (0x3F << MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET) #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0 /* Define the bits in register CS2CDR */ -#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21) +#define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET) #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21 -#define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21) -#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18) +#define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET) +#define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET) #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18 -#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18) -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16) +#define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET) #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16 -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << 16) -#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET) +#define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET) #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12 -#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9) +#define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9 -#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6) +#define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET) #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6 -#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F +#define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK (0x3F << MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET) #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0 /* Define the bits in register CDCDR */ -#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29) +#define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET) #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28) -#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET) #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25 -#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET) #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 19 -#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20) +#define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET) #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20 -#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET) #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12 -#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9) +#define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET) #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9 -#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7) +#define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET) #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7 /* Define the bits in register CHSCCDR */ -#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15) +#define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_DI1_PRE_CLK_SEL_OFFSET) #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15 -#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12) +#define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET) #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12 -#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9) +#define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET) #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9 -#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6) +#define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_DI0_PRE_CLK_SEL_OFFSET) #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6 -#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3) +#define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET) #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3 -#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) +#define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET) #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 -#define CHSCCDR_CLK_SEL_LDB_DI0 3 -#define CHSCCDR_PODF_DIVIDE_BY_3 2 -#define CHSCCDR_IPU_PRE_CLK_540M_PFD 5 - /* Define the bits in register CSCDR2 */ -#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) +#define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET) #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 -#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) -#define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 -#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12) -#define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12 -#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9) -#define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9 -#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6) -#define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6 -#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3) -#define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3 -#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7 -#define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0 +#define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_DI1_PRE_CLK_SEL_OFFSET) +#define MXC_CCM_CSCDR2_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 +#define MXC_CCM_CSCDR2_IPU2_DI1_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET) +#define MXC_CCM_CSCDR2_IPU2_DI1_PODF_OFFSET 12 +#define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET) +#define MXC_CCM_CSCDR2_IPU2_DI1_CLK_SEL_OFFSET 9 +#define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_DI0_PRE_CLK_SEL_OFFSET) +#define MXC_CCM_CSCDR2_IPU2_DI0_PRE_CLK_SEL_OFFSET 6 +#define MXC_CCM_CSCDR2_IPU2_DI0_PODF_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET) +#define MXC_CCM_CSCDR2_IPU2_DI0_PODF_OFFSET 3 +#define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_MASK (0x7 << MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET) +#define MXC_CCM_CSCDR2_IPU2_DI0_CLK_SEL_OFFSET 0 /* Define the bits in register CSCDR3 */ -#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16) +#define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET) #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16 -#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14) +#define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET) #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14 -#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11) +#define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET) #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11 -#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9) +#define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET) #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9 /* Define the bits in register CDHIPR */ @@ -339,7 +333,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2) #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) -#define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1 +#define MXC_CCM_CDHIPR_AXI_PODF_BUSY (1 << 0) /* Define the bits in register CLPCR */ #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) @@ -353,16 +347,16 @@ struct mxc_ccm_reg { #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17) #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17) #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11) -#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) +#define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << MXC_CCM_CLPCR_STBY_COUNT_OFFSET) #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 #define MXC_CCM_CLPCR_VSTBY (1 << 8) #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) #define MXC_CCM_CLPCR_SBYOS (1 << 6) #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) -#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) +#define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET) #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2) -#define MXC_CCM_CLPCR_LPM_MASK 0x3 +#define MXC_CCM_CLPCR_LPM_MASK (0x3 << MXC_CCM_CLPCR_LPM_OFFSET) #define MXC_CCM_CLPCR_LPM_OFFSET 0 /* Define the bits in register CISR */ @@ -374,7 +368,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19) #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17) #define MXC_CCM_CISR_COSC_READY (1 << 6) -#define MXC_CCM_CISR_LRF_PLL 1 +#define MXC_CCM_CISR_LRF_PLL (1 << 0) /* Define the bits in register CIMR */ #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) @@ -385,24 +379,24 @@ struct mxc_ccm_reg { #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22) #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17) #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6) -#define MXC_CCM_CIMR_MASK_LRF_PLL 1 +#define MXC_CCM_CIMR_MASK_LRF_PLL (1 << 0) /* Define the bits in register CCOSR */ #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24) -#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21) +#define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKO2_DIV_OFFSET) #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16 -#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) +#define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << MXC_CCM_CCOSR_CKO2_SEL_OFFSET) #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) -#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) +#define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << MXC_CCM_CCOSR_CKOL_DIV_OFFSET) #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4 -#define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF +#define MXC_CCM_CCOSR_CKOL_SEL_MASK (0xF << MXC_CCM_CCOSR_CKOL_SEL_OFFSET) #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0 /* Define the bits in registers CGPR */ #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2) -#define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1 +#define MXC_CCM_CGPR_PMIC_DELAY_SCALER (1 << 0) /* Define the bits in registers CCGRx */ #define MXC_CCM_CCGR_CG_MASK 3 @@ -571,324 +565,405 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26 #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET) -#define MXC_CCM_CCGR6_USBOH3_OFFSET 0 -#define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET) -#define MXC_CCM_CCGR6_USDHC1_OFFSET 2 -#define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET) -#define MXC_CCM_CCGR6_USDHC2_OFFSET 4 -#define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET) -#define MXC_CCM_CCGR6_USDHC3_OFFSET 6 -#define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET) -#define MXC_CCM_CCGR6_USDHC4_OFFSET 8 -#define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET) -#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10 -#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET) -#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12 -#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET) - -#define BM_ANADIG_PLL_SYS_LOCK 0x80000000 -#define BP_ANADIG_PLL_SYS_RSVD0 20 -#define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000 -#define BF_ANADIG_PLL_SYS_RSVD0(v) \ - (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0) -#define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000 -#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000 -#define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000 -#define BM_ANADIG_PLL_SYS_BYPASS 0x00010000 -#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14 -#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000 -#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \ - (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC) -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_PLL_SYS_ENABLE 0x00002000 -#define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000 -#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400 -#define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200 -#define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100 -#define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080 -#define BP_ANADIG_PLL_SYS_DIV_SELECT 0 -#define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F -#define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \ - (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT) - -#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000 -#define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17 -#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000 -#define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \ - (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1) -#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000 -#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14 -#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000 -#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \ - (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000 -#define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000 -#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400 -#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200 -#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100 -#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080 -#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040 -#define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020 -#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2 -#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C -#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \ - (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0) -#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0 -#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003 -#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \ - (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) - -#define BM_ANADIG_PLL_528_LOCK 0x80000000 -#define BP_ANADIG_PLL_528_RSVD1 19 -#define BM_ANADIG_PLL_528_RSVD1 0x7FF80000 -#define BF_ANADIG_PLL_528_RSVD1(v) \ - (((v) << 19) & BM_ANADIG_PLL_528_RSVD1) -#define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000 -#define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000 -#define BM_ANADIG_PLL_528_BYPASS 0x00010000 -#define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14 -#define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000 -#define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \ - (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC) -#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_PLL_528_ENABLE 0x00002000 -#define BM_ANADIG_PLL_528_POWERDOWN 0x00001000 -#define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400 -#define BM_ANADIG_PLL_528_HALF_CP 0x00000200 -#define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100 -#define BM_ANADIG_PLL_528_HALF_LF 0x00000080 -#define BP_ANADIG_PLL_528_RSVD0 1 -#define BM_ANADIG_PLL_528_RSVD0 0x0000007E -#define BF_ANADIG_PLL_528_RSVD0(v) \ - (((v) << 1) & BM_ANADIG_PLL_528_RSVD0) -#define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001 - -#define BP_ANADIG_PLL_528_SS_STOP 16 -#define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000 -#define BF_ANADIG_PLL_528_SS_STOP(v) \ - (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP) -#define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000 -#define BP_ANADIG_PLL_528_SS_STEP 0 -#define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF -#define BF_ANADIG_PLL_528_SS_STEP(v) \ - (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP) - -#define BP_ANADIG_PLL_528_NUM_RSVD0 30 -#define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000 -#define BF_ANADIG_PLL_528_NUM_RSVD0(v) \ - (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0) -#define BP_ANADIG_PLL_528_NUM_A 0 -#define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF -#define BF_ANADIG_PLL_528_NUM_A(v) \ - (((v) << 0) & BM_ANADIG_PLL_528_NUM_A) - -#define BP_ANADIG_PLL_528_DENOM_RSVD0 30 -#define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000 -#define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \ - (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0) -#define BP_ANADIG_PLL_528_DENOM_B 0 -#define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF -#define BF_ANADIG_PLL_528_DENOM_B(v) \ - (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B) - -#define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000 -#define BP_ANADIG_PLL_AUDIO_RSVD0 22 -#define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000 -#define BF_ANADIG_PLL_AUDIO_RSVD0(v) \ - (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0) -#define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000 -#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19 -#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000 -#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \ - (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) -#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000 -#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000 -#define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000 -#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14 -#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000 -#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \ - (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) -#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000 -#define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000 -#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400 -#define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200 -#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100 -#define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080 -#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0 -#define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F -#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \ - (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT) - -#define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30 -#define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000 -#define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \ - (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0) -#define BP_ANADIG_PLL_AUDIO_NUM_A 0 -#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF -#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \ - (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A) - -#define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30 -#define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000 -#define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \ - (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0) -#define BP_ANADIG_PLL_AUDIO_DENOM_B 0 -#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF -#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \ - (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B) - -#define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000 -#define BP_ANADIG_PLL_VIDEO_RSVD0 22 -#define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000 -#define BF_ANADIG_PLL_VIDEO_RSVD0(v) \ - (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0) -#define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000 -#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19 -#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000 -#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \ - (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) -#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000 -#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000 -#define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000 -#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14 -#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000 -#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \ - (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) -#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000 -#define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000 -#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400 -#define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200 -#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100 -#define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080 -#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0 -#define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F -#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \ - (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT) - -#define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30 -#define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000 -#define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \ - (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0) -#define BP_ANADIG_PLL_VIDEO_NUM_A 0 -#define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF -#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \ - (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A) - -#define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30 -#define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000 -#define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \ - (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0) -#define BP_ANADIG_PLL_VIDEO_DENOM_B 0 -#define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF -#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \ - (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B) - -#define BM_ANADIG_PLL_ENET_LOCK 0x80000000 -#define BP_ANADIG_PLL_ENET_RSVD1 21 -#define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000 -#define BF_ANADIG_PLL_ENET_RSVD1(v) \ - (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1) -#define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000 -#define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000 -#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000 -#define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000 -#define BM_ANADIG_PLL_ENET_BYPASS 0x00010000 -#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14 -#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000 -#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \ - (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC) -#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0 -#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1 -#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2 -#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3 -#define BM_ANADIG_PLL_ENET_ENABLE 0x00002000 -#define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000 -#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800 -#define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400 -#define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200 -#define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100 -#define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080 -#define BP_ANADIG_PLL_ENET_RSVD0 2 -#define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C -#define BF_ANADIG_PLL_ENET_RSVD0(v) \ - (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0) -#define BP_ANADIG_PLL_ENET_DIV_SELECT 0 -#define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003 -#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ - (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) - -#define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 -#define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000 -#define BP_ANADIG_PFD_480_PFD3_FRAC 24 -#define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000 -#define BF_ANADIG_PFD_480_PFD3_FRAC(v) \ - (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC) -#define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000 -#define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000 -#define BP_ANADIG_PFD_480_PFD2_FRAC 16 -#define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000 -#define BF_ANADIG_PFD_480_PFD2_FRAC(v) \ - (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC) -#define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000 -#define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000 -#define BP_ANADIG_PFD_480_PFD1_FRAC 8 -#define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00 -#define BF_ANADIG_PFD_480_PFD1_FRAC(v) \ - (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC) -#define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080 -#define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040 -#define BP_ANADIG_PFD_480_PFD0_FRAC 0 -#define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F -#define BF_ANADIG_PFD_480_PFD0_FRAC(v) \ - (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC) - -#define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000 -#define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000 -#define BP_ANADIG_PFD_528_PFD3_FRAC 24 -#define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000 -#define BF_ANADIG_PFD_528_PFD3_FRAC(v) \ - (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC) -#define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000 -#define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000 -#define BP_ANADIG_PFD_528_PFD2_FRAC 16 -#define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000 -#define BF_ANADIG_PFD_528_PFD2_FRAC(v) \ - (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC) -#define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000 -#define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000 -#define BP_ANADIG_PFD_528_PFD1_FRAC 8 -#define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00 -#define BF_ANADIG_PFD_528_PFD1_FRAC(v) \ - (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC) -#define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080 -#define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040 -#define BP_ANADIG_PFD_528_PFD0_FRAC 0 -#define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F -#define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ - (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) +#define MXC_CCM_CCGR6_USBOH3_OFFSET 0 +#define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET) +#define MXC_CCM_CCGR6_USDHC1_OFFSET 2 +#define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET) +#define MXC_CCM_CCGR6_USDHC2_OFFSET 4 +#define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET) +#define MXC_CCM_CCGR6_USDHC3_OFFSET 6 +#define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET) +#define MXC_CCM_CCGR6_USDHC4_OFFSET 8 +#define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET) +#define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10 +#define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET) +#define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12 +#define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET) + +#define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0 +#define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f << ANATOP_PFD_480_PFD0_FRAC_SHIFT) +#define ANATOP_PFD_480_PFD0_STABLE_SHIFT 6 +#define ANATOP_PFD_480_PFD0_STABLE_MASK (1 << ANATOP_PFD_480_PFD0_STABLE_SHIFT) +#define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT 7 +#define ANATOP_PFD_480_PFD0_CLKGATE_MASK (1 << ANATOP_PFD_480_PFD0_CLKGATE_SHIFT) +#define ANATOP_PFD_480_PFD1_FRAC_SHIFT 8 +#define ANATOP_PFD_480_PFD1_FRAC_MASK (0x3f << ANATOP_PFD_480_PFD1_FRAC_SHIFT) +#define ANATOP_PFD_480_PFD1_STABLE_SHIFT 14 +#define ANATOP_PFD_480_PFD1_STABLE_MASK (1 << ANATOP_PFD_480_PFD1_STABLE_SHIFT) +#define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT 15 +#define ANATOP_PFD_480_PFD1_CLKGATE_MASK (0x3f << ANATOP_PFD_480_PFD1_CLKGATE_SHIFT) +#define ANATOP_PFD_480_PFD2_FRAC_SHIFT 16 +#define ANATOP_PFD_480_PFD2_FRAC_MASK (1 << ANATOP_PFD_480_PFD2_FRAC_SHIFT) +#define ANATOP_PFD_480_PFD2_STABLE_SHIFT 22 +#define ANATOP_PFD_480_PFD2_STABLE_MASK (1 << ANATOP_PFD_480_PFD2_STABLE_SHIFT) +#define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT 23 +#define ANATOP_PFD_480_PFD2_CLKGATE_MASK (0x3f << ANATOP_PFD_480_PFD2_CLKGATE_SHIFT) +#define ANATOP_PFD_480_PFD3_FRAC_SHIFT 24 +#define ANATOP_PFD_480_PFD3_FRAC_MASK (1 << ANATOP_PFD_480_PFD3_FRAC_SHIFT) +#define ANATOP_PFD_480_PFD3_STABLE_SHIFT 30 +#define ANATOP_PFD_480_PFD3_STABLE_MASK (1 << ANATOP_PFD_480_PFD3_STABLE_SHIFT) +#define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT 31 + +#define BM_ANADIG_PLL_ARM_LOCK (1 << 31) +#define BM_ANADIG_PLL_ARM_PLL_SEL (1 << 19) +#define BM_ANADIG_PLL_ARM_LVDS_24MHZ_SEL (1 << 18) +#define BM_ANADIG_PLL_ARM_LVDS_SEL (1 << 17) +#define BM_ANADIG_PLL_ARM_BYPASS (1 << 16) +#define BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC 14 +#define BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC) +#define BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(v) \ + (((v) << BP_ANADIG_PLL_ARM_BYPASS_CLK_SRC) & BM_ANADIG_PLL_ARM_BYPASS_CLK_SRC) +#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__OSC_24M BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(0) +#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_1 BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(1) +#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__ANACLK_2 BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(2) +#define BV_ANADIG_PLL_ARM_BYPASS_CLK_SRC__XOR BF_ANADIG_PLL_ARM_BYPASS_CLK_SRC(3) +#define BM_ANADIG_PLL_ARM_ENABLE (1 << 13) +#define BM_ANADIG_PLL_ARM_POWERDOWN (1 << 12) +#define BM_ANADIG_PLL_ARM_HOLD_RING_OFF (1 << 11) +#define BM_ANADIG_PLL_ARM_DOUBLE_CP (1 << 10) +#define BM_ANADIG_PLL_ARM_HALF_CP (1 << 9) +#define BM_ANADIG_PLL_ARM_DOUBLE_LF (1 << 8) +#define BM_ANADIG_PLL_ARM_HALF_LF (1 << 7) +#define BP_ANADIG_PLL_ARM_DIV_SELECT 0 +#define BM_ANADIG_PLL_ARM_DIV_SELECT (0x7F << BP_ANADIG_PLL_ARM_DIV_SELECT) +#define BF_ANADIG_PLL_ARM_DIV_SELECT(v) \ + (((v) << BP_ANADIG_PLL_ARM_DIV_SELECT) & \ + BM_ANADIG_PLL_ARM_DIV_SELECT) + +#define BM_ANADIG_USB1_PLL_480_CTRL_LOCK (1 << 31) +#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS (1 << 16) +#define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14 +#define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) +#define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \ + (((v) << BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) & \ + BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC) +#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(0) +#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(1) +#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(2) +#define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(3) +#define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE (1 << 13) +#define BM_ANADIG_USB1_PLL_480_CTRL_POWER (1 << 12) +#define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF (1 << 11) +#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP (1 << 10) +#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP (1 << 9) +#define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF (1 << 8) +#define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF (1 << 7) +#define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS (1 << 6) +#define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2 +#define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0) +#define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \ + (((v) << BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0) & \ + BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0) +#define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0 +#define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) +#define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \ + (((v) << BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) & \ + BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT) + +#define BM_ANADIG_USB2_PLL_480_CTRL_LOCK (1 << 31) +#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS (1 << 16) +#define BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC 14 +#define BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC (0x3 << BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC) +#define BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(v) \ + (((v) << BP_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC) & \ + BM_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC) +#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(0) +#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(1) +#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(2) +#define BV_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC__XOR BF_ANADIG_USB2_PLL_480_CTRL_BYPASS_CLK_SRC(3) +#define BM_ANADIG_USB2_PLL_480_CTRL_ENABLE (1 << 13) +#define BM_ANADIG_USB2_PLL_480_CTRL_POWER (1 << 12) +#define BM_ANADIG_USB2_PLL_480_CTRL_HOLD_RING_OFF (1 << 11) +#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_CP (1 << 10) +#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_CP (1 << 9) +#define BM_ANADIG_USB2_PLL_480_CTRL_DOUBLE_LF (1 << 8) +#define BM_ANADIG_USB2_PLL_480_CTRL_HALF_LF (1 << 7) +#define BM_ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS (1 << 6) +#define BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0 2 +#define BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0 (0x7 << BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0) +#define BF_ANADIG_USB2_PLL_480_CTRL_CONTROL0(v) \ + (((v) << BP_ANADIG_USB2_PLL_480_CTRL_CONTROL0) & \ + BM_ANADIG_USB2_PLL_480_CTRL_CONTROL0) +#define BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT 0 +#define BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT (0x3 << BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT) +#define BF_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT(v) \ + (((v) << BP_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT) & \ + BM_ANADIG_USB2_PLL_480_CTRL_DIV_SELECT) + +#define BM_ANADIG_PLL_SYS_LOCK (1 << 31) +#define BM_ANADIG_PLL_SYS_PLL_SEL (1 << 19) +#define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL (1 << 18) +#define BM_ANADIG_PLL_SYS_LVDS_SEL (1 << 17) +#define BM_ANADIG_PLL_SYS_BYPASS (1 << 16) +#define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14 +#define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC) +#define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \ + (((v) << BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC) +#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2 +#define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3 +#define BM_ANADIG_PLL_SYS_ENABLE (1 << 13) +#define BM_ANADIG_PLL_SYS_POWERDOWN (1 << 12) +#define BM_ANADIG_PLL_SYS_HOLD_RING_OFF (1 << 11) +#define BM_ANADIG_PLL_SYS_DOUBLE_CP (1 << 10) +#define BM_ANADIG_PLL_SYS_HALF_CP (1 << 9) +#define BM_ANADIG_PLL_SYS_DOUBLE_LF (1 << 8) +#define BM_ANADIG_PLL_SYS_HALF_LF (1 << 7) +#define BP_ANADIG_PLL_SYS_DIV_SELECT 0 +#define BM_ANADIG_PLL_SYS_DIV_SELECT (0x7F << BP_ANADIG_PLL_SYS_DIV_SELECT) +#define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \ + (((v) << BP_ANADIG_PLL_SYS_DIV_SELECT) & BM_ANADIG_PLL_SYS_DIV_SELECT) + +#define BM_ANADIG_PLL_AUDIO_LOCK (1 << 31) +#define BM_ANADIG_PLL_AUDIO_SSC_EN (1 << 21) +#define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19 +#define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) +#define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \ + (((v) << BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) +#define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN (1 << 18) +#define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE (1 << 17) +#define BM_ANADIG_PLL_AUDIO_BYPASS (1 << 16) +#define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14 +#define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) +#define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \ + (((v) << BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC) +#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2 +#define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3 +#define BM_ANADIG_PLL_AUDIO_ENABLE (1 << 13) +#define BM_ANADIG_PLL_AUDIO_POWERDOWN (1 << 12) +#define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF (1 << 11) +#define BM_ANADIG_PLL_AUDIO_DOUBLE_CP (1 << 10) +#define BM_ANADIG_PLL_AUDIO_HALF_CP (1 << 9) +#define BM_ANADIG_PLL_AUDIO_DOUBLE_LF (1 << 8) +#define BM_ANADIG_PLL_AUDIO_HALF_LF (1 << 7) +#define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0 +#define BM_ANADIG_PLL_AUDIO_DIV_SELECT (0x7F << BP_ANADIG_PLL_AUDIO_DIV_SELECT) +#define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \ + (((v) << BP_ANADIG_PLL_AUDIO_DIV_SELECT) & BM_ANADIG_PLL_AUDIO_DIV_SELECT) + +#define BP_ANADIG_PLL_AUDIO_NUM_A 0 +#define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF +#define BF_ANADIG_PLL_AUDIO_NUM_A(v) \ + (((v) << BP_ANADIG_PLL_AUDIO_NUM_A) & BM_ANADIG_PLL_AUDIO_NUM_A) + +#define BP_ANADIG_PLL_AUDIO_DENOM_B 0 +#define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF +#define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \ + (((v) << BP_ANADIG_PLL_AUDIO_DENOM_B) & BM_ANADIG_PLL_AUDIO_DENOM_B) + +#define BM_ANADIG_PLL_VIDEO_LOCK (1 << 31) +#define BM_ANADIG_PLL_VIDEO_SSC_EN (1 << 21) +#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19 +#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT (0x3 << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) +#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \ + (((v) << BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) +#define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN (1 << 18) +#define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE (1 << 17) +#define BM_ANADIG_PLL_VIDEO_BYPASS (1 << 16) +#define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14 +#define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) +#define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \ + (((v) << BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC) +#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2 +#define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3 +#define BM_ANADIG_PLL_VIDEO_ENABLE (1 << 13) +#define BM_ANADIG_PLL_VIDEO_POWERDOWN (1 << 12) +#define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF (1 << 11) +#define BM_ANADIG_PLL_VIDEO_DOUBLE_CP (1 << 10) +#define BM_ANADIG_PLL_VIDEO_HALF_CP (1 << 9) +#define BM_ANADIG_PLL_VIDEO_DOUBLE_LF (1 << 8) +#define BM_ANADIG_PLL_VIDEO_HALF_LF (1 << 7) +#define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0 +#define BM_ANADIG_PLL_VIDEO_DIV_SELECT (0x7F << BP_ANADIG_PLL_VIDEO_DIV_SELECT) +#define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \ + (((v) << BP_ANADIG_PLL_VIDEO_DIV_SELECT) & BM_ANADIG_PLL_VIDEO_DIV_SELECT) + +#define BP_ANADIG_PLL_VIDEO_NUM_A 0 +#define BM_ANADIG_PLL_VIDEO_NUM_A (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_NUM_A) +#define BF_ANADIG_PLL_VIDEO_NUM_A(v) \ + (((v) << BP_ANADIG_PLL_VIDEO_NUM_A) & BM_ANADIG_PLL_VIDEO_NUM_A) + +#define BP_ANADIG_PLL_VIDEO_DENOM_B 0 +#define BM_ANADIG_PLL_VIDEO_DENOM_B (0x3FFFFFFF << BP_ANADIG_PLL_VIDEO_DENOM_B) +#define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \ + (((v) << BP_ANADIG_PLL_VIDEO_DENOM_B) & BM_ANADIG_PLL_VIDEO_DENOM_B) + +#define BM_ANADIG_PLL_MLB_LOCK (1 << 31) +#define BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG 26 +#define BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) +#define BF_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG(v) \ + (((v) << BP_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) & BM_ANADIG_PLL_MLB_MLB_FLT_RES_DLY_CFG) +#define BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG 23 +#define BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) +#define BF_ANADIG_PLL_MLB_RX_CLK_DLY_CFG(v) \ + (((v) << BP_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) & BM_ANADIG_PLL_MLB_RX_CLK_DLY_CFG) +#define BP_ANADIG_PLL_MLB_VDDD_DLY_CFG 20 +#define BM_ANADIG_PLL_MLB_VDDD_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG) +#define BF_ANADIG_PLL_MLB_VDDD_DLY_CFG(v) \ + (((v) << BP_ANADIG_PLL_MLB_VDDD_DLY_CFG) & BM_ANADIG_PLL_MLB_VDDD_DLY_CFG) +#define BP_ANADIG_PLL_MLB_VDDA_DLY_CFG 17 +#define BM_ANADIG_PLL_MLB_VDDA_DLY_CFG (0x7 << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG) +#define BF_ANADIG_PLL_MLB_VDDA_DLY_CFG(v) \ + (((v) << BP_ANADIG_PLL_MLB_VDDA_DLY_CFG) & BM_ANADIG_PLL_MLB_VDDA_DLY_CFG) +#define BM_ANADIG_PLL_MLB_BYPASS (1 << 16) +#define BP_ANADIG_PLL_MLB_PHASE_SEL 12 +#define BM_ANADIG_PLL_MLB_PHASE_SEL (0x7 << BP_ANADIG_PLL_MLB_PHASE_SEL) +#define BF_ANADIG_PLL_MLB_PHASE_SEL(v) \ + (((v) << BP_ANADIG_PLL_MLB_PHASE_SEL) & BM_ANADIG_PLL_MLB_PHASE_SEL) +#define BM_ANADIG_PLL_MLB_HOLD_RING_OFF (1 << 11) + +#define BM_ANADIG_PLL_ENET_LOCK (1 << 31) +#define BM_ANADIG_PLL_ENET_ENABLE_SATA (1 << 20) +#define BM_ANADIG_PLL_ENET_ENABLE_PCIE (1 << 19) +#define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN (1 << 18) +#define BM_ANADIG_PLL_ENET_DITHER_ENABLE (1 << 17) +#define BM_ANADIG_PLL_ENET_BYPASS (1 << 16) +#define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14 +#define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC (0x3 << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) +#define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \ + (((v) << BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC) +#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0 +#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1 +#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2 +#define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3 +#define BM_ANADIG_PLL_ENET_ENABLE (1 << 13) +#define BM_ANADIG_PLL_ENET_POWERDOWN (1 << 12) +#define BM_ANADIG_PLL_ENET_HOLD_RING_OFF (1 << 11) +#define BM_ANADIG_PLL_ENET_DOUBLE_CP (1 << 10) +#define BM_ANADIG_PLL_ENET_HALF_CP (1 << 9) +#define BM_ANADIG_PLL_ENET_DOUBLE_LF (1 << 8) +#define BM_ANADIG_PLL_ENET_HALF_LF (1 << 7) +#define BP_ANADIG_PLL_ENET_DIV_SELECT 0 +#define BM_ANADIG_PLL_ENET_DIV_SELECT (0x3 << BP_ANADIG_PLL_ENET_DIV_SELECT) +#define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ + (((v) << BP_ANADIG_PLL_ENET_DIV_SELECT) & BM_ANADIG_PLL_ENET_DIV_SELECT) + +#define BM_ANADIG_PFD_480_PFD3_CLKGATE (1 << 31) +#define BM_ANADIG_PFD_480_PFD3_STABLE (1 << 30) +#define BP_ANADIG_PFD_480_PFD3_FRAC 24 +#define BM_ANADIG_PFD_480_PFD3_FRAC (0x3F << BP_ANADIG_PFD_480_PFD3_FRAC) +#define BF_ANADIG_PFD_480_PFD3_FRAC(v) \ + (((v) << BP_ANADIG_PFD_480_PFD3_FRAC) & BM_ANADIG_PFD_480_PFD3_FRAC) + +#define BP_ANADIG_ANA_MISC0_CLKGATE_DELAY 26 +#define BM_ANADIG_ANA_MISC0_CLKGATE_DELAY (0x7 << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY) +#define BF_ANADIG_ANA_MISC0_CLKGATE_DELAY(v) \ + (((v) << BP_ANADIG_ANA_MISC0_CLKGATE_DELAY) & BM_ANADIG_ANA_MISC0_CLKGATE_DELAY) +#define BM_ANADIG_ANA_MISC0_CLKGATE_CTRL (1 << 25) +#define BP_ANADIG_ANA_MISC0_ANAMUX 21 +#define BM_ANADIG_ANA_MISC0_ANAMUX (0xf << BP_ANADIG_ANA_MISC0_ANAMUX) +#define BF_ANADIG_ANA_MISC0_ANAMUX(v) \ + (((v) << BP_ANADIG_ANA_MISC0_ANAMUX) & BM_ANADIG_ANA_MISC0_ANAMUX) +#define BM_ANADIG_ANA_MISC0_ANAMUX_EN (1 << 20) +#define BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH 18 +#define BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH (0x3 << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) +#define BF_ANADIG_ANA_MISC0_WBCP_VPW_THRESH(v) \ + (((v) << BP_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) & BM_ANADIG_ANA_MISC0_WBCP_VPW_THRESH) +#define BM_ANADIG_ANA_MISC0_OSC_XTALOK_EN (1 << 17) +#define BM_ANADIG_ANA_MISC0_OSC_XTALOK (1 << 16) +#define BP_ANADIG_ANA_MISC0_OSC_I 14 +#define BM_ANADIG_ANA_MISC0_OSC_I 0x0000C000 +#define BF_ANADIG_ANA_MISC0_OSC_I(v) \ + (((v) << BP_ANADIG_ANA_MISC0_OSC_I) & BM_ANADIG_ANA_MISC0_OSC_I) +#define BM_ANADIG_ANA_MISC0_RTC_RINGOSC_EN (1 << 13) +#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG (1 << 12) +#define BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 8 +#define BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST 0x00000300 +#define BF_ANADIG_ANA_MISC0_REFTOP_BIAS_TST(v) \ + (((v) << BP_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) & BM_ANADIG_ANA_MISC0_REFTOP_BIAS_TST) +#define BM_ANADIG_ANA_MISC0_REFTOP_VBGUP (1 << 7) +#define BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ 4 +#define BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ (0x7 << BP_ANADIG_ANA_MISC0_REFTOP_VBGADJ) +#define BF_ANADIG_ANA_MISC0_REFTOP_VBGADJ(v) \ + (((v) << BM_ANADIG_ANA_MISC0_REFTOP_VBGUP) & BM_ANADIG_ANA_MISC0_REFTOP_VBGADJ) +#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF (1 << 3) +#define BM_ANADIG_ANA_MISC0_REFTOP_LOWPOWER (1 << 2) +#define BM_ANADIG_ANA_MISC0_REFTOP_PWDVBGUP (1 << 1) +#define BM_ANADIG_ANA_MISC0_REFTOP_PWD (1 << 0) + +#define BM_ANADIG_ANA_MISC1_IRQ_DIG_BO (1 << 31) +#define BM_ANADIG_ANA_MISC1_IRQ_ANA_BO 0x40000000 +#define BM_ANADIG_ANA_MISC1_IRQ_TEMPSENSE_BO 0x20000000 +#define BM_ANADIG_ANA_MISC1_LVDSCLK2_IBEN (1 << 13) +#define BM_ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12) +#define BM_ANADIG_ANA_MISC1_LVDSCLK2_OBEN (1 << 11) +#define BM_ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10) +#define BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 5 +#define BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL 0x000003E0 +#define BF_ANADIG_ANA_MISC1_LVDS2_CLK_SEL(v) \ + (((v) << BP_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) & BM_ANADIG_ANA_MISC1_LVDS2_CLK_SEL) +#define BP_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0 +#define BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL 0x0000001F +#define BF_ANADIG_ANA_MISC1_LVDS1_CLK_SEL(v) \ + (((v) << 0) & BM_ANADIG_ANA_MISC1_LVDS1_CLK_SEL) + +#define BP_ANADIG_ANA_MISC2_CONTROL3 30 +#define BM_ANADIG_ANA_MISC2_CONTROL3 0xC0000000 +#define BF_ANADIG_ANA_MISC2_CONTROL3(v) \ + (((v) << BP_ANADIG_ANA_MISC2_CONTROL3) & BM_ANADIG_ANA_MISC2_CONTROL3) +#define BP_ANADIG_ANA_MISC2_REG2_STEP_TIME 28 +#define BM_ANADIG_ANA_MISC2_REG2_STEP_TIME 0x30000000 +#define BF_ANADIG_ANA_MISC2_REG2_STEP_TIME(v) \ + (((v) << BP_ANADIG_ANA_MISC2_REG2_STEP_TIME) & BM_ANADIG_ANA_MISC2_REG2_STEP_TIME) +#define BP_ANADIG_ANA_MISC2_REG1_STEP_TIME 26 +#define BM_ANADIG_ANA_MISC2_REG1_STEP_TIME 0x0C000000 +#define BF_ANADIG_ANA_MISC2_REG1_STEP_TIME(v) \ + (((v) << BP_ANADIG_ANA_MISC2_REG1_STEP_TIME) & BM_ANADIG_ANA_MISC2_REG1_STEP_TIME) +#define BP_ANADIG_ANA_MISC2_REG0_STEP_TIME 24 +#define BM_ANADIG_ANA_MISC2_REG0_STEP_TIME 0x03000000 +#define BF_ANADIG_ANA_MISC2_REG0_STEP_TIME(v) \ + (((v) << BP_ANADIG_ANA_MISC2_REG0_STEP_TIME) & BM_ANADIG_ANA_MISC2_REG0_STEP_TIME) +#define BM_ANADIG_ANA_MISC2_CONTROL2 0x00800000 +#define BM_ANADIG_ANA_MISC2_REG2_OK 0x00400000 +#define BM_ANADIG_ANA_MISC2_REG2_ENABLE_BO (1 << 21) +#define BM_ANADIG_ANA_MISC2_REG2_BO_STATUS (1 << 19) +#define BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET 16 +#define BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET 0x00070000 +#define BF_ANADIG_ANA_MISC2_REG2_BO_OFFSET(v) \ + (((v) << BP_ANADIG_ANA_MISC2_REG2_BO_OFFSET) & BM_ANADIG_ANA_MISC2_REG2_BO_OFFSET) +#define BM_ANADIG_ANA_MISC2_CONTROL1 (1 << 15) +#define BM_ANADIG_ANA_MISC2_REG1_OK (1 << 14) +#define BM_ANADIG_ANA_MISC2_REG1_ENABLE_BO (1 << 13) +#define BM_ANADIG_ANA_MISC2_REG1_BO_STATUS (1 << 11) +#define BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET 8 +#define BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET 0x00000700 +#define BF_ANADIG_ANA_MISC2_REG1_BO_OFFSET(v) \ + (((v) << BP_ANADIG_ANA_MISC2_REG1_BO_OFFSET) & BM_ANADIG_ANA_MISC2_REG1_BO_OFFSET) +#define BM_ANADIG_ANA_MISC2_CONTROL0 (1 << 7) +#define BM_ANADIG_ANA_MISC2_REG0_OK (1 << 6) +#define BM_ANADIG_ANA_MISC2_REG0_ENABLE_BO (1 << 5) +#define BM_ANADIG_ANA_MISC2_REG0_BO_STATUS (1 << 3) +#define BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET 0 +#define BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET (0x7 << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET) +#define BF_ANADIG_ANA_MISC2_REG0_BO_OFFSET(v) \ + (((v) << BP_ANADIG_ANA_MISC2_REG0_BO_OFFSET) & BM_ANADIG_ANA_MISC2_REG0_BO_OFFSET) + +#define BP_ANADIG_TEMPSENSE0_ALARM_VALUE 20 +#define BM_ANADIG_TEMPSENSE0_ALARM_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_ALARM_VALUE) +#define BF_ANADIG_TEMPSENSE0_ALARM_VALUE(v) \ + (((v) << BP_ANADIG_TEMPSENSE0_ALARM_VALUE) & BM_ANADIG_TEMPSENSE0_ALARM_VALUE) +#define BP_ANADIG_TEMPSENSE0_TEMP_VALUE 8 +#define BM_ANADIG_TEMPSENSE0_TEMP_VALUE (0xFFF << BP_ANADIG_TEMPSENSE0_TEMP_VALUE) +#define BF_ANADIG_TEMPSENSE0_TEMP_VALUE(v) \ + (((v) << BP_ANADIG_TEMPSENSE0_TEMP_VALUE) & BM_ANADIG_TEMPSENSE0_TEMP_VALUE) +#define BM_ANADIG_TEMPSENSE0_TEST (1 << 6) +#define BP_ANADIG_TEMPSENSE0_VBGADJ 3 +#define BM_ANADIG_TEMPSENSE0_VBGADJ (0x7 << BP_ANADIG_TEMPSENSE0_VBGADJ) +#define BF_ANADIG_TEMPSENSE0_VBGADJ(v) \ + (((v) << BP_ANADIG_TEMPSENSE0_VBGADJ) & BM_ANADIG_TEMPSENSE0_VBGADJ) +#define BM_ANADIG_TEMPSENSE0_FINISHED (1 << 2) +#define BM_ANADIG_TEMPSENSE0_MEASURE_TEMP (1 << 1) +#define BM_ANADIG_TEMPSENSE0_POWER_DOWN (1 << 0) + +#define BP_ANADIG_TEMPSENSE1_MEASURE_FREQ 0 +#define BM_ANADIG_TEMPSENSE1_MEASURE_FREQ (0xFFFF << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ) +#define BF_ANADIG_TEMPSENSE1_MEASURE_FREQ(v) \ + (((v) << BP_ANADIG_TEMPSENSE1_MEASURE_FREQ) & BM_ANADIG_TEMPSENSE1_MEASURE_FREQ) #define PLL2_PFD0_FREQ 352000000 #define PLL2_PFD1_FREQ 594000000 diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 5d6bccbc0c..c06260dee2 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -7,31 +7,31 @@ #ifndef __ASM_ARCH_MX6_IMX_REGS_H__ #define __ASM_ARCH_MX6_IMX_REGS_H__ -#define ARCH_MXC +#include -#define CONFIG_SYS_CACHELINE_SIZE 32 +#define ARCH_MXC -#define ROMCP_ARB_BASE_ADDR 0x00000000 -#define ROMCP_ARB_END_ADDR 0x000FFFFF +#define ROMCP_ARB_BASE_ADDR 0x00000000 +#define ROMCP_ARB_END_ADDR 0x000FFFFF #ifdef CONFIG_MX6SL -#define GPU_2D_ARB_BASE_ADDR 0x02200000 -#define GPU_2D_ARB_END_ADDR 0x02203FFF -#define OPENVG_ARB_BASE_ADDR 0x02204000 -#define OPENVG_ARB_END_ADDR 0x02207FFF +#define GPU_2D_ARB_BASE_ADDR 0x02200000 +#define GPU_2D_ARB_END_ADDR 0x02203FFF +#define OPENVG_ARB_BASE_ADDR 0x02204000 +#define OPENVG_ARB_END_ADDR 0x02207FFF #else -#define CAAM_ARB_BASE_ADDR 0x00100000 -#define CAAM_ARB_END_ADDR 0x00103FFF -#define APBH_DMA_ARB_BASE_ADDR 0x00110000 -#define APBH_DMA_ARB_END_ADDR 0x00117FFF -#define HDMI_ARB_BASE_ADDR 0x00120000 -#define HDMI_ARB_END_ADDR 0x00128FFF -#define GPU_3D_ARB_BASE_ADDR 0x00130000 -#define GPU_3D_ARB_END_ADDR 0x00133FFF -#define GPU_2D_ARB_BASE_ADDR 0x00134000 -#define GPU_2D_ARB_END_ADDR 0x00137FFF -#define DTCP_ARB_BASE_ADDR 0x00138000 -#define DTCP_ARB_END_ADDR 0x0013BFFF +#define CAAM_ARB_BASE_ADDR 0x00100000 +#define CAAM_ARB_END_ADDR 0x00103FFF +#define APBH_DMA_ARB_BASE_ADDR 0x00110000 +#define APBH_DMA_ARB_END_ADDR 0x00117FFF +#define HDMI_ARB_BASE_ADDR 0x00120000 +#define HDMI_ARB_END_ADDR 0x00128FFF +#define GPU_3D_ARB_BASE_ADDR 0x00130000 +#define GPU_3D_ARB_END_ADDR 0x00133FFF +#define GPU_2D_ARB_BASE_ADDR 0x00134000 +#define GPU_2D_ARB_END_ADDR 0x00137FFF +#define DTCP_ARB_BASE_ADDR 0x00138000 +#define DTCP_ARB_END_ADDR 0x0013BFFF #endif /* CONFIG_MX6SL */ #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR @@ -40,7 +40,7 @@ /* GPV - PL301 configuration ports */ #ifdef CONFIG_MX6SL -#define GPV2_BASE_ADDR 0x00D00000 +#define GPV2_BASE_ADDR 0x00D00000 #else #define GPV2_BASE_ADDR 0x00200000 #endif @@ -48,182 +48,181 @@ #define GPV3_BASE_ADDR 0x00300000 #define GPV4_BASE_ADDR 0x00800000 #define IRAM_BASE_ADDR 0x00900000 -#define SCU_BASE_ADDR 0x00A00000 -#define IC_INTERFACES_BASE_ADDR 0x00A00100 -#define GLOBAL_TIMER_BASE_ADDR 0x00A00200 -#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 -#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 -#define GPV0_BASE_ADDR 0x00B00000 -#define GPV1_BASE_ADDR 0x00C00000 -#define PCIE_ARB_BASE_ADDR 0x01000000 -#define PCIE_ARB_END_ADDR 0x01FFFFFF - -#define AIPS1_ARB_BASE_ADDR 0x02000000 -#define AIPS1_ARB_END_ADDR 0x020FFFFF -#define AIPS2_ARB_BASE_ADDR 0x02100000 -#define AIPS2_ARB_END_ADDR 0x021FFFFF -#define SATA_ARB_BASE_ADDR 0x02200000 -#define SATA_ARB_END_ADDR 0x02203FFF -#define OPENVG_ARB_BASE_ADDR 0x02204000 -#define OPENVG_ARB_END_ADDR 0x02207FFF -#define HSI_ARB_BASE_ADDR 0x02208000 -#define HSI_ARB_END_ADDR 0x0220BFFF -#define IPU1_ARB_BASE_ADDR 0x02400000 -#define IPU1_ARB_END_ADDR 0x027FFFFF -#define IPU2_ARB_BASE_ADDR 0x02800000 -#define IPU2_ARB_END_ADDR 0x02BFFFFF -#define WEIM_ARB_BASE_ADDR 0x08000000 -#define WEIM_ARB_END_ADDR 0x0FFFFFFF +#define SCU_BASE_ADDR 0x00A00000 +#define IC_INTERFACES_BASE_ADDR 0x00A00100 +#define GLOBAL_TIMER_BASE_ADDR 0x00A00200 +#define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600 +#define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000 +#define GPV0_BASE_ADDR 0x00B00000 +#define GPV1_BASE_ADDR 0x00C00000 +#define PCIE_ARB_BASE_ADDR 0x01000000 +#define PCIE_ARB_END_ADDR 0x01FFFFFF + +#define AIPS1_ARB_BASE_ADDR 0x02000000 +#define AIPS1_ARB_END_ADDR 0x020FFFFF +#define AIPS2_ARB_BASE_ADDR 0x02100000 +#define AIPS2_ARB_END_ADDR 0x021FFFFF +#define SATA_ARB_BASE_ADDR 0x02200000 +#define SATA_ARB_END_ADDR 0x02203FFF +#define OPENVG_ARB_BASE_ADDR 0x02204000 +#define OPENVG_ARB_END_ADDR 0x02207FFF +#define HSI_ARB_BASE_ADDR 0x02208000 +#define HSI_ARB_END_ADDR 0x0220BFFF +#define IPU1_ARB_BASE_ADDR 0x02400000 +#define IPU1_ARB_END_ADDR 0x027FFFFF +#define IPU2_ARB_BASE_ADDR 0x02800000 +#define IPU2_ARB_END_ADDR 0x02BFFFFF +#define WEIM_ARB_BASE_ADDR 0x08000000 +#define WEIM_ARB_END_ADDR 0x0FFFFFFF #ifdef CONFIG_MX6SL -#define MMDC0_ARB_BASE_ADDR 0x80000000 -#define MMDC0_ARB_END_ADDR 0xFFFFFFFF -#define MMDC1_ARB_BASE_ADDR 0xC0000000 -#define MMDC1_ARB_END_ADDR 0xFFFFFFFF +#define MMDC0_ARB_BASE_ADDR 0x80000000 +#define MMDC0_ARB_END_ADDR 0xFFFFFFFF +#define MMDC1_ARB_BASE_ADDR 0xC0000000 +#define MMDC1_ARB_END_ADDR 0xFFFFFFFF #else -#define MMDC0_ARB_BASE_ADDR 0x10000000 -#define MMDC0_ARB_END_ADDR 0x7FFFFFFF -#define MMDC1_ARB_BASE_ADDR 0x80000000 -#define MMDC1_ARB_END_ADDR 0xFFFFFFFF +#define MMDC0_ARB_BASE_ADDR 0x10000000 +#define MMDC0_ARB_END_ADDR 0x7FFFFFFF +#define MMDC1_ARB_BASE_ADDR 0x80000000 +#define MMDC1_ARB_END_ADDR 0xFFFFFFFF #endif #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR #define IPU_SOC_OFFSET 0x00200000 /* Defines for Blocks connected via AIPS (SkyBlue) */ -#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR -#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR -#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR -#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR - -#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000) -#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000) -#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) -#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) -#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) +#define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR +#define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR +#define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR +#define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR + +#define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000) +#define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000) +#define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000) +#define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000) +#define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000) #ifdef CONFIG_MX6SL -#define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) -#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) -#define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) -#define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) -#define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) -#define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) -#define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) -#define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000) +#define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) +#define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000) +#define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) +#define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) +#define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) +#define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) +#define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) +#define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000) #else -#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) -#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) -#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) -#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) -#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) -#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) -#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) +#define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000) +#define UART1_BASE (ATZ1_BASE_ADDR + 0x20000) +#define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000) +#define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000) +#define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000) +#define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000) +#define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000) #endif -#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) -#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) -#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) - -#define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) -#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000) -#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000) -#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000) -#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) -#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) -#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) -#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) -#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) -#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) -#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) -#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) -#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) -#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) -#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) -#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) -#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) -#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) -#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) -#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) -#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) -#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) -#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) -#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) -#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) -#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) -#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) -#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) +#define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000) +#define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000) +#define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000) + +#define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000) +#define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000) +#define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000) +#define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000) +#define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000) +#define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000) +#define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000) +#define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000) +#define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000) +#define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000) +#define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000) +#define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000) +#define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000) +#define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000) +#define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000) +#define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000) +#define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000) +#define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000) +#define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000) +#define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000) +#define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000) +#define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000) +#define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000) +#define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000) +#define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000) +#define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000) +#define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000) +#define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000) #ifdef CONFIG_MX6SL -#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) -#define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) +#define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) +#define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) #else -#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) -#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) +#define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000) +#define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000) #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000) #endif -#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) -#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) -#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) +#define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000) +#define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000) +#define CAAM_BASE_ADDR (ATZ2_BASE_ADDR) #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000) #ifdef CONFIG_MX6SL #define USBO2H_PL301_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) -#define USBO2H_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) +#define USBO2H_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) #else -#define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) -#define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) +#define USBOH3_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) +#define USBOH3_USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) #endif -#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) +#define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000) #ifdef CONFIG_MX6SL -#define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) +#define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) #else -#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) +#define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000) #endif -#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000) -#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) -#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) -#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) -#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) -#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) -#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) -#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) -#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) +#define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000) +#define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000) +#define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000) +#define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000) +#define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000) +#define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000) +#define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000) +#define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000) +#define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000) #ifdef CONFIG_MX6SL -#define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) +#define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) #else -#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) +#define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000) #endif -#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) -#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) -#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) +#define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000) +#define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000) +#define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) -#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) -#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) -#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) -#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) -#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) -#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) -#define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) -#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) -#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) -#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) +#define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000) +#define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000) +#define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000) +#define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000) +#define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000) +#define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000) +#define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000) +#define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000) +#define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000) +#define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000) #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000) #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000) -#define CHIP_REV_1_0 0x10 -#define IRAM_SIZE 0x00040000 +#define CHIP_REV_1_0 0x10 +#define IRAM_SIZE 0x00040000 +#define IMX_IIM_BASE OCOTP_BASE_ADDR #define FEC_QUIRK_ENET_MAC #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include -extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); - /* System Reset Controller (SRC) */ struct src { u32 scr; @@ -232,17 +231,17 @@ struct src { u32 reserved1[2]; u32 sisr; u32 simr; - u32 sbmr2; - u32 gpr1; - u32 gpr2; - u32 gpr3; - u32 gpr4; - u32 gpr5; - u32 gpr6; - u32 gpr7; - u32 gpr8; - u32 gpr9; - u32 gpr10; + u32 sbmr2; + u32 gpr1; + u32 gpr2; + u32 gpr3; + u32 gpr4; + u32 gpr5; + u32 gpr6; + u32 gpr7; + u32 gpr8; + u32 gpr9; + u32 gpr10; }; /* GPR3 bitfields */ @@ -420,30 +419,17 @@ struct cspi_regs { #endif struct ocotp_regs { - u32 ctrl; - u32 ctrl_set; - u32 ctrl_clr; - u32 ctrl_tog; - u32 timing; - u32 rsvd0[3]; - u32 data; - u32 rsvd1[3]; - u32 read_ctrl; - u32 rsvd2[3]; - u32 read_fuse_data; - u32 rsvd3[3]; - u32 sw_sticky; - u32 rsvd4[3]; - u32 scs; - u32 scs_set; - u32 scs_clr; - u32 scs_tog; - u32 crc_addr; - u32 rsvd5[3]; - u32 crc_value; - u32 rsvd6[3]; - u32 version; - u32 rsvd7[0xdb]; + mxs_reg_32(ctrl); + reg_32(timing); + reg_32(data); + reg_32(read_ctrl); + reg_32(fuse_data); + reg_32(sticky); + mxs_reg_32(scs); + reg_32(crc_addr); + reg_32(crc_value); + reg_32(version); + u32 rsvd7[0xd8]; struct fuse_bank { u32 fuse_regs[0x20]; @@ -451,27 +437,21 @@ struct ocotp_regs { }; struct fuse_bank0_regs { - u32 lock; - u32 rsvd0[3]; - u32 uid_low; - u32 rsvd1[3]; - u32 uid_high; - u32 rsvd2[0x17]; + reg_32(misc_conf_lock); + reg_32(cfg0); + reg_32(cfg1); + reg_32(cfg2); + reg_32(cfg3); + reg_32(cfg4); + reg_32(cfg5); + reg_32(cfg6); }; struct fuse_bank4_regs { - u32 sjc_resp_low; - u32 rsvd0[3]; - u32 sjc_resp_high; - u32 rsvd1[3]; - u32 mac_addr_low; - u32 rsvd2[3]; - u32 mac_addr_high; - u32 rsvd3[0xb]; - u32 gp1; - u32 rsvd4[3]; - u32 gp2; - u32 rsvd5[3]; + reg_32(sjc_resp_low); + reg_32(sjc_resp_high); + reg_32(mac_addr_low); + reg_32(mac_addr_high); }; struct aipstz_regs { @@ -485,181 +465,13 @@ struct aipstz_regs { u32 opacr4; }; -struct anatop_regs { - u32 pll_sys; /* 0x000 */ - u32 pll_sys_set; /* 0x004 */ - u32 pll_sys_clr; /* 0x008 */ - u32 pll_sys_tog; /* 0x00c */ - u32 usb1_pll_480_ctrl; /* 0x010 */ - u32 usb1_pll_480_ctrl_set; /* 0x014 */ - u32 usb1_pll_480_ctrl_clr; /* 0x018 */ - u32 usb1_pll_480_ctrl_tog; /* 0x01c */ - u32 usb2_pll_480_ctrl; /* 0x020 */ - u32 usb2_pll_480_ctrl_set; /* 0x024 */ - u32 usb2_pll_480_ctrl_clr; /* 0x028 */ - u32 usb2_pll_480_ctrl_tog; /* 0x02c */ - u32 pll_528; /* 0x030 */ - u32 pll_528_set; /* 0x034 */ - u32 pll_528_clr; /* 0x038 */ - u32 pll_528_tog; /* 0x03c */ - u32 pll_528_ss; /* 0x040 */ - u32 rsvd0[3]; - u32 pll_528_num; /* 0x050 */ - u32 rsvd1[3]; - u32 pll_528_denom; /* 0x060 */ - u32 rsvd2[3]; - u32 pll_audio; /* 0x070 */ - u32 pll_audio_set; /* 0x074 */ - u32 pll_audio_clr; /* 0x078 */ - u32 pll_audio_tog; /* 0x07c */ - u32 pll_audio_num; /* 0x080 */ - u32 rsvd3[3]; - u32 pll_audio_denom; /* 0x090 */ - u32 rsvd4[3]; - u32 pll_video; /* 0x0a0 */ - u32 pll_video_set; /* 0x0a4 */ - u32 pll_video_clr; /* 0x0a8 */ - u32 pll_video_tog; /* 0x0ac */ - u32 pll_video_num; /* 0x0b0 */ - u32 rsvd5[3]; - u32 pll_video_denom; /* 0x0c0 */ - u32 rsvd6[3]; - u32 pll_mlb; /* 0x0d0 */ - u32 pll_mlb_set; /* 0x0d4 */ - u32 pll_mlb_clr; /* 0x0d8 */ - u32 pll_mlb_tog; /* 0x0dc */ - u32 pll_enet; /* 0x0e0 */ - u32 pll_enet_set; /* 0x0e4 */ - u32 pll_enet_clr; /* 0x0e8 */ - u32 pll_enet_tog; /* 0x0ec */ - u32 pfd_480; /* 0x0f0 */ - u32 pfd_480_set; /* 0x0f4 */ - u32 pfd_480_clr; /* 0x0f8 */ - u32 pfd_480_tog; /* 0x0fc */ - u32 pfd_528; /* 0x100 */ - u32 pfd_528_set; /* 0x104 */ - u32 pfd_528_clr; /* 0x108 */ - u32 pfd_528_tog; /* 0x10c */ - u32 reg_1p1; /* 0x110 */ - u32 reg_1p1_set; /* 0x114 */ - u32 reg_1p1_clr; /* 0x118 */ - u32 reg_1p1_tog; /* 0x11c */ - u32 reg_3p0; /* 0x120 */ - u32 reg_3p0_set; /* 0x124 */ - u32 reg_3p0_clr; /* 0x128 */ - u32 reg_3p0_tog; /* 0x12c */ - u32 reg_2p5; /* 0x130 */ - u32 reg_2p5_set; /* 0x134 */ - u32 reg_2p5_clr; /* 0x138 */ - u32 reg_2p5_tog; /* 0x13c */ - u32 reg_core; /* 0x140 */ - u32 reg_core_set; /* 0x144 */ - u32 reg_core_clr; /* 0x148 */ - u32 reg_core_tog; /* 0x14c */ - u32 ana_misc0; /* 0x150 */ - u32 ana_misc0_set; /* 0x154 */ - u32 ana_misc0_clr; /* 0x158 */ - u32 ana_misc0_tog; /* 0x15c */ - u32 ana_misc1; /* 0x160 */ - u32 ana_misc1_set; /* 0x164 */ - u32 ana_misc1_clr; /* 0x168 */ - u32 ana_misc1_tog; /* 0x16c */ - u32 ana_misc2; /* 0x170 */ - u32 ana_misc2_set; /* 0x174 */ - u32 ana_misc2_clr; /* 0x178 */ - u32 ana_misc2_tog; /* 0x17c */ - u32 tempsense0; /* 0x180 */ - u32 tempsense0_set; /* 0x184 */ - u32 tempsense0_clr; /* 0x188 */ - u32 tempsense0_tog; /* 0x18c */ - u32 tempsense1; /* 0x190 */ - u32 tempsense1_set; /* 0x194 */ - u32 tempsense1_clr; /* 0x198 */ - u32 tempsense1_tog; /* 0x19c */ - u32 usb1_vbus_detect; /* 0x1a0 */ - u32 usb1_vbus_detect_set; /* 0x1a4 */ - u32 usb1_vbus_detect_clr; /* 0x1a8 */ - u32 usb1_vbus_detect_tog; /* 0x1ac */ - u32 usb1_chrg_detect; /* 0x1b0 */ - u32 usb1_chrg_detect_set; /* 0x1b4 */ - u32 usb1_chrg_detect_clr; /* 0x1b8 */ - u32 usb1_chrg_detect_tog; /* 0x1bc */ - u32 usb1_vbus_det_stat; /* 0x1c0 */ - u32 usb1_vbus_det_stat_set; /* 0x1c4 */ - u32 usb1_vbus_det_stat_clr; /* 0x1c8 */ - u32 usb1_vbus_det_stat_tog; /* 0x1cc */ - u32 usb1_chrg_det_stat; /* 0x1d0 */ - u32 usb1_chrg_det_stat_set; /* 0x1d4 */ - u32 usb1_chrg_det_stat_clr; /* 0x1d8 */ - u32 usb1_chrg_det_stat_tog; /* 0x1dc */ - u32 usb1_loopback; /* 0x1e0 */ - u32 usb1_loopback_set; /* 0x1e4 */ - u32 usb1_loopback_clr; /* 0x1e8 */ - u32 usb1_loopback_tog; /* 0x1ec */ - u32 usb1_misc; /* 0x1f0 */ - u32 usb1_misc_set; /* 0x1f4 */ - u32 usb1_misc_clr; /* 0x1f8 */ - u32 usb1_misc_tog; /* 0x1fc */ - u32 usb2_vbus_detect; /* 0x200 */ - u32 usb2_vbus_detect_set; /* 0x204 */ - u32 usb2_vbus_detect_clr; /* 0x208 */ - u32 usb2_vbus_detect_tog; /* 0x20c */ - u32 usb2_chrg_detect; /* 0x210 */ - u32 usb2_chrg_detect_set; /* 0x214 */ - u32 usb2_chrg_detect_clr; /* 0x218 */ - u32 usb2_chrg_detect_tog; /* 0x21c */ - u32 usb2_vbus_det_stat; /* 0x220 */ - u32 usb2_vbus_det_stat_set; /* 0x224 */ - u32 usb2_vbus_det_stat_clr; /* 0x228 */ - u32 usb2_vbus_det_stat_tog; /* 0x22c */ - u32 usb2_chrg_det_stat; /* 0x230 */ - u32 usb2_chrg_det_stat_set; /* 0x234 */ - u32 usb2_chrg_det_stat_clr; /* 0x238 */ - u32 usb2_chrg_det_stat_tog; /* 0x23c */ - u32 usb2_loopback; /* 0x240 */ - u32 usb2_loopback_set; /* 0x244 */ - u32 usb2_loopback_clr; /* 0x248 */ - u32 usb2_loopback_tog; /* 0x24c */ - u32 usb2_misc; /* 0x250 */ - u32 usb2_misc_set; /* 0x254 */ - u32 usb2_misc_clr; /* 0x258 */ - u32 usb2_misc_tog; /* 0x25c */ - u32 digprog; /* 0x260 */ - u32 reserved1[7]; - u32 digprog_sololite; /* 0x280 */ -}; - -#define ANATOP_PFD_480_PFD0_FRAC_SHIFT 0 -#define ANATOP_PFD_480_PFD0_FRAC_MASK (0x3f< + * based on: + * Copyright (C) 2011 Marek Vasut + * on behalf of DENX Software Engineering GmbH + * + * Based on code from LTIB: + * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + */ + +#ifndef __MX6_REGS_OCOTP_H__ +#define __MX6_REGS_OCOTP_H__ + +#ifndef __ASSEMBLY__ +#define mx6_ocotp_reg_32(r) mxs_reg_32(hw_ocotp_##r) +#define ocotp_reg_32(r) reg_32(hw_ocotp_##r) + +struct mx6_ocotp_regs { + mx6_ocotp_reg_32(ctrl); /* 0x000 */ + ocotp_reg_32(timing); /* 0x010 */ + ocotp_reg_32(data); /* 0x020 */ + ocotp_reg_32(read_ctrl); /* 0x030 */ + ocotp_reg_32(read_fuse_data); /* 0x040 */ + ocotp_reg_32(sw_sticky); /* 0x050 */ + mx6_ocotp_reg_32(scs); /* 0x060 */ + reg_32(rsrvd1); /* 0x070 */ + reg_32(rsrvd2); /* 0x080 */ + ocotp_reg_32(version); /* 0x090 */ + + reg_32(rsrvd3[54]); /* 0x0a0 - 0x3ff */ + + /* bank 0 */ + ocotp_reg_32(lock); /* 0x400 */ + ocotp_reg_32(cfg0); /* 0x410 */ + ocotp_reg_32(cfg1); /* 0x420 */ + ocotp_reg_32(cfg2); /* 0x430 */ + ocotp_reg_32(cfg3); /* 0x440 */ + ocotp_reg_32(cfg4); /* 0x450 */ + ocotp_reg_32(cfg5); /* 0x460 */ + ocotp_reg_32(cfg6); /* 0x470 */ + + /* bank 1 */ + ocotp_reg_32(mem0); /* 0x480 */ + ocotp_reg_32(mem1); /* 0x490 */ + ocotp_reg_32(mem2); /* 0x4a0 */ + ocotp_reg_32(mem3); /* 0x4b0 */ + ocotp_reg_32(mem4); /* 0x4c0 */ + ocotp_reg_32(ana0); /* 0x4d0 */ + ocotp_reg_32(ana1); /* 0x4e0 */ + ocotp_reg_32(ana2); /* 0x4f0 */ + + /* bank 2 */ + reg_32(rsrvd4[8]); /* 0x500 - 0x57f */ + + /* bank 3 */ + ocotp_reg_32(srk0); /* 0x580 */ + ocotp_reg_32(srk1); /* 0x590 */ + ocotp_reg_32(srk2); /* 0x5a0 */ + ocotp_reg_32(srk3); /* 0x5b0 */ + ocotp_reg_32(srk4); /* 0x5c0 */ + ocotp_reg_32(srk5); /* 0x5d0 */ + ocotp_reg_32(srk6); /* 0x5e0 */ + ocotp_reg_32(srk7); /* 0x5f0 */ + + /* bank 4 */ + ocotp_reg_32(hsjc_resp0); /* 0x600 */ + ocotp_reg_32(hsjc_resp1); /* 0x610 */ + ocotp_reg_32(mac0); /* 0x620 */ + ocotp_reg_32(mac1); /* 0x630 */ + reg_32(rsrvd5[2]); /* 0x640 - 0x65f */ + ocotp_reg_32(gp1); /* 0x660 */ + ocotp_reg_32(gp2); /* 0x670 */ + + /* bank 5 */ + reg_32(rsrvd6[5]); /* 0x680 - 0x6cf */ + ocotp_reg_32(misc_conf); /* 0x6d0 */ + ocotp_reg_32(field_return); /* 0x6e0 */ + ocotp_reg_32(srk_revoke); /* 0x6f0 */ +}; + +#endif + +#define OCOTP_CTRL_BUSY (1 << 8) +#define OCOTP_CTRL_ERROR (1 << 9) +#define OCOTP_CTRL_RELOAD_SHADOWS (1 << 10) + +#define OCOTP_RD_CTRL_READ_FUSE (1 << 0) + +#define OCOTP_VERSION_MAJOR_MASK (0xff << 24) +#define OCOTP_VERSION_MAJOR_OFFSET 24 +#define OCOTP_VERSION_MINOR_MASK (0xff << 16) +#define OCOTP_VERSION_MINOR_OFFSET 16 +#define OCOTP_VERSION_STEP_MASK 0xffff +#define OCOTP_VERSION_STEP_OFFSET 0 + +#endif /* __MX6_REGS_OCOTP_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h b/arch/arm/include/asm/arch-mx6/sys_proto.h index bfdfd2911d..f37cca3fe1 100644 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h @@ -22,7 +22,10 @@ u32 get_cpu_rev(void); const char *get_imx_type(u32 imxtype); unsigned imx_ddr_size(void); -void set_vddsoc(u32 mv); + +struct mxs_register_32; + +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); /* * Initializes on-chip ethernet controllers. diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h index 1490ffd520..c7664900e2 100644 --- a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h +++ b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h @@ -17,40 +17,38 @@ #ifndef __ASSEMBLY__ struct mxs_clkctrl_regs { - mxs_reg_32(hw_clkctrl_pll0ctrl0) /* 0x00 */ - uint32_t hw_clkctrl_pll0ctrl1; /* 0x10 */ - uint32_t reserved_pll0ctrl1[3]; /* 0x14-0x1c */ - mxs_reg_32(hw_clkctrl_pll1ctrl0) /* 0x20 */ - uint32_t hw_clkctrl_pll1ctrl1; /* 0x30 */ - uint32_t reserved_pll1ctrl1[3]; /* 0x34-0x3c */ - mxs_reg_32(hw_clkctrl_pll2ctrl0) /* 0x40 */ - mxs_reg_32(hw_clkctrl_cpu) /* 0x50 */ - mxs_reg_32(hw_clkctrl_hbus) /* 0x60 */ - mxs_reg_32(hw_clkctrl_xbus) /* 0x70 */ - mxs_reg_32(hw_clkctrl_xtal) /* 0x80 */ - mxs_reg_32(hw_clkctrl_ssp0) /* 0x90 */ - mxs_reg_32(hw_clkctrl_ssp1) /* 0xa0 */ - mxs_reg_32(hw_clkctrl_ssp2) /* 0xb0 */ - mxs_reg_32(hw_clkctrl_ssp3) /* 0xc0 */ - mxs_reg_32(hw_clkctrl_gpmi) /* 0xd0 */ - mxs_reg_32(hw_clkctrl_spdif) /* 0xe0 */ - mxs_reg_32(hw_clkctrl_emi) /* 0xf0 */ - mxs_reg_32(hw_clkctrl_saif0) /* 0x100 */ - mxs_reg_32(hw_clkctrl_saif1) /* 0x110 */ - mxs_reg_32(hw_clkctrl_lcdif) /* 0x120 */ - mxs_reg_32(hw_clkctrl_etm) /* 0x130 */ - mxs_reg_32(hw_clkctrl_enet) /* 0x140 */ - mxs_reg_32(hw_clkctrl_hsadc) /* 0x150 */ - mxs_reg_32(hw_clkctrl_flexcan) /* 0x160 */ + mxs_reg_32(hw_clkctrl_pll0ctrl0); /* 0x00 */ + reg_32(hw_clkctrl_pll0ctrl1); /* 0x10 */ + mxs_reg_32(hw_clkctrl_pll1ctrl0); /* 0x20 */ + reg_32(hw_clkctrl_pll1ctrl1); /* 0x30 */ + mxs_reg_32(hw_clkctrl_pll2ctrl0); /* 0x40 */ + mxs_reg_32(hw_clkctrl_cpu); /* 0x50 */ + mxs_reg_32(hw_clkctrl_hbus); /* 0x60 */ + mxs_reg_32(hw_clkctrl_xbus); /* 0x70 */ + mxs_reg_32(hw_clkctrl_xtal); /* 0x80 */ + mxs_reg_32(hw_clkctrl_ssp0); /* 0x90 */ + mxs_reg_32(hw_clkctrl_ssp1); /* 0xa0 */ + mxs_reg_32(hw_clkctrl_ssp2); /* 0xb0 */ + mxs_reg_32(hw_clkctrl_ssp3); /* 0xc0 */ + mxs_reg_32(hw_clkctrl_gpmi); /* 0xd0 */ + mxs_reg_32(hw_clkctrl_spdif); /* 0xe0 */ + mxs_reg_32(hw_clkctrl_emi); /* 0xf0 */ + mxs_reg_32(hw_clkctrl_saif0); /* 0x100 */ + mxs_reg_32(hw_clkctrl_saif1); /* 0x110 */ + mxs_reg_32(hw_clkctrl_lcdif); /* 0x120 */ + mxs_reg_32(hw_clkctrl_etm); /* 0x130 */ + mxs_reg_32(hw_clkctrl_enet); /* 0x140 */ + mxs_reg_32(hw_clkctrl_hsadc); /* 0x150 */ + mxs_reg_32(hw_clkctrl_flexcan); /* 0x160 */ - uint32_t reserved[16]; + reg_32(reserved[4]); /* 0x170-0x1a0 */ - mxs_reg_8(hw_clkctrl_frac0) /* 0x1b0 */ - mxs_reg_8(hw_clkctrl_frac1) /* 0x1c0 */ - mxs_reg_32(hw_clkctrl_clkseq) /* 0x1d0 */ - mxs_reg_32(hw_clkctrl_reset) /* 0x1e0 */ - mxs_reg_32(hw_clkctrl_status) /* 0x1f0 */ - mxs_reg_32(hw_clkctrl_version) /* 0x200 */ + mxs_reg_8(hw_clkctrl_frac0); /* 0x1b0 */ + mxs_reg_8(hw_clkctrl_frac1); /* 0x1c0 */ + mxs_reg_32(hw_clkctrl_clkseq); /* 0x1d0 */ + mxs_reg_32(hw_clkctrl_reset); /* 0x1e0 */ + mxs_reg_32(hw_clkctrl_status); /* 0x1f0 */ + mxs_reg_32(hw_clkctrl_version); /* 0x200 */ }; #endif diff --git a/arch/arm/include/asm/arch-mxs/regs-digctl.h b/arch/arm/include/asm/arch-mxs/regs-digctl.h index 860be9e28f..a09a9976b0 100644 --- a/arch/arm/include/asm/arch-mxs/regs-digctl.h +++ b/arch/arm/include/asm/arch-mxs/regs-digctl.h @@ -13,16 +13,16 @@ #ifndef __ASSEMBLY__ struct mxs_digctl_regs { - mxs_reg_32(hw_digctl_ctrl) /* 0x000 */ - mxs_reg_32(hw_digctl_status) /* 0x010 */ - mxs_reg_32(hw_digctl_hclkcount) /* 0x020 */ - mxs_reg_32(hw_digctl_ramctrl) /* 0x030 */ - mxs_reg_32(hw_digctl_emi_status) /* 0x040 */ - mxs_reg_32(hw_digctl_read_margin) /* 0x050 */ + mxs_reg_32(hw_digctl_ctrl); /* 0x000 */ + mxs_reg_32(hw_digctl_status); /* 0x010 */ + mxs_reg_32(hw_digctl_hclkcount); /* 0x020 */ + mxs_reg_32(hw_digctl_ramctrl); /* 0x030 */ + mxs_reg_32(hw_digctl_emi_status); /* 0x040 */ + mxs_reg_32(hw_digctl_read_margin); /* 0x050 */ uint32_t hw_digctl_writeonce; /* 0x060 */ uint32_t reserved_writeonce[3]; - mxs_reg_32(hw_digctl_bist_ctl) /* 0x070 */ - mxs_reg_32(hw_digctl_bist_status) /* 0x080 */ + mxs_reg_32(hw_digctl_bist_ctl); /* 0x070 */ + mxs_reg_32(hw_digctl_bist_status); /* 0x080 */ uint32_t hw_digctl_entropy; /* 0x090 */ uint32_t reserved_entropy[3]; uint32_t hw_digctl_entropy_latched; /* 0x0a0 */ @@ -30,7 +30,7 @@ struct mxs_digctl_regs { uint32_t reserved1[4]; - mxs_reg_32(hw_digctl_microseconds) /* 0x0c0 */ + mxs_reg_32(hw_digctl_microseconds); /* 0x0c0 */ uint32_t hw_digctl_dbgrd; /* 0x0d0 */ uint32_t reserved_hw_digctl_dbgrd[3]; uint32_t hw_digctl_dbg; /* 0x0e0 */ @@ -38,21 +38,21 @@ struct mxs_digctl_regs { uint32_t reserved2[4]; - mxs_reg_32(hw_digctl_usb_loopback) /* 0x100 */ - mxs_reg_32(hw_digctl_ocram_status0) /* 0x110 */ - mxs_reg_32(hw_digctl_ocram_status1) /* 0x120 */ - mxs_reg_32(hw_digctl_ocram_status2) /* 0x130 */ - mxs_reg_32(hw_digctl_ocram_status3) /* 0x140 */ - mxs_reg_32(hw_digctl_ocram_status4) /* 0x150 */ - mxs_reg_32(hw_digctl_ocram_status5) /* 0x160 */ - mxs_reg_32(hw_digctl_ocram_status6) /* 0x170 */ - mxs_reg_32(hw_digctl_ocram_status7) /* 0x180 */ - mxs_reg_32(hw_digctl_ocram_status8) /* 0x190 */ - mxs_reg_32(hw_digctl_ocram_status9) /* 0x1a0 */ - mxs_reg_32(hw_digctl_ocram_status10) /* 0x1b0 */ - mxs_reg_32(hw_digctl_ocram_status11) /* 0x1c0 */ - mxs_reg_32(hw_digctl_ocram_status12) /* 0x1d0 */ - mxs_reg_32(hw_digctl_ocram_status13) /* 0x1e0 */ + mxs_reg_32(hw_digctl_usb_loopback); /* 0x100 */ + mxs_reg_32(hw_digctl_ocram_status0); /* 0x110 */ + mxs_reg_32(hw_digctl_ocram_status1); /* 0x120 */ + mxs_reg_32(hw_digctl_ocram_status2); /* 0x130 */ + mxs_reg_32(hw_digctl_ocram_status3); /* 0x140 */ + mxs_reg_32(hw_digctl_ocram_status4); /* 0x150 */ + mxs_reg_32(hw_digctl_ocram_status5); /* 0x160 */ + mxs_reg_32(hw_digctl_ocram_status6); /* 0x170 */ + mxs_reg_32(hw_digctl_ocram_status7); /* 0x180 */ + mxs_reg_32(hw_digctl_ocram_status8); /* 0x190 */ + mxs_reg_32(hw_digctl_ocram_status9); /* 0x1a0 */ + mxs_reg_32(hw_digctl_ocram_status10); /* 0x1b0 */ + mxs_reg_32(hw_digctl_ocram_status11); /* 0x1c0 */ + mxs_reg_32(hw_digctl_ocram_status12); /* 0x1d0 */ + mxs_reg_32(hw_digctl_ocram_status13); /* 0x1e0 */ uint32_t reserved3[36]; @@ -62,7 +62,7 @@ struct mxs_digctl_regs { uint32_t reserved_hw_digctl_scratch1[3]; uint32_t hw_digctl_armcache; /* 0x2a0 */ uint32_t reserved_hw_digctl_armcache[3]; - mxs_reg_32(hw_digctl_debug_trap) /* 0x2b0 */ + mxs_reg_32(hw_digctl_debug_trap); /* 0x2b0 */ uint32_t hw_digctl_debug_trap_l0_addr_low; /* 0x2c0 */ uint32_t reserved_hw_digctl_debug_trap_l0_addr_low[3]; uint32_t hw_digctl_debug_trap_l0_addr_high; /* 0x2d0 */ diff --git a/arch/arm/include/asm/arch-mxs/regs-i2c.h b/arch/arm/include/asm/arch-mxs/regs-i2c.h index a58303efb8..77ddd0bc49 100644 --- a/arch/arm/include/asm/arch-mxs/regs-i2c.h +++ b/arch/arm/include/asm/arch-mxs/regs-i2c.h @@ -14,20 +14,20 @@ #ifndef __ASSEMBLY__ struct mxs_i2c_regs { - mxs_reg_32(hw_i2c_ctrl0) - mxs_reg_32(hw_i2c_timing0) - mxs_reg_32(hw_i2c_timing1) - mxs_reg_32(hw_i2c_timing2) - mxs_reg_32(hw_i2c_ctrl1) - mxs_reg_32(hw_i2c_stat) - mxs_reg_32(hw_i2c_queuectrl) - mxs_reg_32(hw_i2c_queuestat) - mxs_reg_32(hw_i2c_queuecmd) - mxs_reg_32(hw_i2c_queuedata) - mxs_reg_32(hw_i2c_data) - mxs_reg_32(hw_i2c_debug0) - mxs_reg_32(hw_i2c_debug1) - mxs_reg_32(hw_i2c_version) + mxs_reg_32(hw_i2c_ctrl0); + mxs_reg_32(hw_i2c_timing0); + mxs_reg_32(hw_i2c_timing1); + mxs_reg_32(hw_i2c_timing2); + mxs_reg_32(hw_i2c_ctrl1); + mxs_reg_32(hw_i2c_stat); + mxs_reg_32(hw_i2c_queuectrl); + mxs_reg_32(hw_i2c_queuestat); + mxs_reg_32(hw_i2c_queuecmd); + mxs_reg_32(hw_i2c_queuedata); + mxs_reg_32(hw_i2c_data); + mxs_reg_32(hw_i2c_debug0); + mxs_reg_32(hw_i2c_debug1); + mxs_reg_32(hw_i2c_version); }; #endif diff --git a/arch/arm/include/asm/arch-mxs/regs-lcdif.h b/arch/arm/include/asm/arch-mxs/regs-lcdif.h index 8915d84d0d..a845883911 100644 --- a/arch/arm/include/asm/arch-mxs/regs-lcdif.h +++ b/arch/arm/include/asm/arch-mxs/regs-lcdif.h @@ -17,51 +17,51 @@ #ifndef __ASSEMBLY__ struct mxs_lcdif_regs { - mxs_reg_32(hw_lcdif_ctrl) /* 0x00 */ - mxs_reg_32(hw_lcdif_ctrl1) /* 0x10 */ + mxs_reg_32(hw_lcdif_ctrl); /* 0x00 */ + mxs_reg_32(hw_lcdif_ctrl1); /* 0x10 */ #if defined(CONFIG_MX28) mxs_reg_32(hw_lcdif_ctrl2) /* 0x20 */ -#endif - mxs_reg_32(hw_lcdif_transfer_count) /* 0x20/0x30 */ - mxs_reg_32(hw_lcdif_cur_buf) /* 0x30/0x40 */ - mxs_reg_32(hw_lcdif_next_buf) /* 0x40/0x50 */ +#endif /* MX23/MX28 */ + mxs_reg_32(hw_lcdif_transfer_count); /* 0x20/0x30 */ + mxs_reg_32(hw_lcdif_cur_buf); /* 0x30/0x40 */ + mxs_reg_32(hw_lcdif_next_buf); /* 0x40/0x50 */ #if defined(CONFIG_MX23) - uint32_t reserved1[4]; + reg_32(reserved1); /* 0x50 */ #endif - mxs_reg_32(hw_lcdif_timing) /* 0x60 */ - mxs_reg_32(hw_lcdif_vdctrl0) /* 0x70 */ - mxs_reg_32(hw_lcdif_vdctrl1) /* 0x80 */ - mxs_reg_32(hw_lcdif_vdctrl2) /* 0x90 */ - mxs_reg_32(hw_lcdif_vdctrl3) /* 0xa0 */ - mxs_reg_32(hw_lcdif_vdctrl4) /* 0xb0 */ - mxs_reg_32(hw_lcdif_dvictrl0) /* 0xc0 */ - mxs_reg_32(hw_lcdif_dvictrl1) /* 0xd0 */ - mxs_reg_32(hw_lcdif_dvictrl2) /* 0xe0 */ - mxs_reg_32(hw_lcdif_dvictrl3) /* 0xf0 */ - mxs_reg_32(hw_lcdif_dvictrl4) /* 0x100 */ - mxs_reg_32(hw_lcdif_csc_coeffctrl0) /* 0x110 */ - mxs_reg_32(hw_lcdif_csc_coeffctrl1) /* 0x120 */ - mxs_reg_32(hw_lcdif_csc_coeffctrl2) /* 0x130 */ - mxs_reg_32(hw_lcdif_csc_coeffctrl3) /* 0x140 */ - mxs_reg_32(hw_lcdif_csc_coeffctrl4) /* 0x150 */ - mxs_reg_32(hw_lcdif_csc_offset) /* 0x160 */ - mxs_reg_32(hw_lcdif_csc_limit) /* 0x170 */ + mxs_reg_32(hw_lcdif_timing); /* 0x60 */ + mxs_reg_32(hw_lcdif_vdctrl0); /* 0x70 */ + mxs_reg_32(hw_lcdif_vdctrl1); /* 0x80 */ + mxs_reg_32(hw_lcdif_vdctrl2); /* 0x90 */ + mxs_reg_32(hw_lcdif_vdctrl3); /* 0xa0 */ + mxs_reg_32(hw_lcdif_vdctrl4); /* 0xb0 */ + mxs_reg_32(hw_lcdif_dvictrl0); /* 0xc0 */ + mxs_reg_32(hw_lcdif_dvictrl1); /* 0xd0 */ + mxs_reg_32(hw_lcdif_dvictrl2); /* 0xe0 */ + mxs_reg_32(hw_lcdif_dvictrl3); /* 0xf0 */ + mxs_reg_32(hw_lcdif_dvictrl4); /* 0x100 */ + mxs_reg_32(hw_lcdif_csc_coeffctrl0); /* 0x110 */ + mxs_reg_32(hw_lcdif_csc_coeffctrl1); /* 0x120 */ + mxs_reg_32(hw_lcdif_csc_coeffctrl2); /* 0x130 */ + mxs_reg_32(hw_lcdif_csc_coeffctrl3); /* 0x140 */ + mxs_reg_32(hw_lcdif_csc_coeffctrl4); /* 0x150 */ + mxs_reg_32(hw_lcdif_csc_offset); /* 0x160 */ + mxs_reg_32(hw_lcdif_csc_limit); /* 0x170 */ #if defined(CONFIG_MX23) - uint32_t reserved2[12]; -#endif + reg_32(reserved2[3]); /* 0x180-0x1a0 */ +#endif /* MX23/MX28 */ mxs_reg_32(hw_lcdif_data) /* 0x1b0/0x180 */ mxs_reg_32(hw_lcdif_bm_error_stat) /* 0x1c0/0x190 */ #if defined(CONFIG_MX28) - mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */ + mxs_reg_32(hw_lcdif_crc_stat) /* 0x1a0 */ #endif - mxs_reg_32(hw_lcdif_lcdif_stat) /* 0x1d0/0x1b0 */ - mxs_reg_32(hw_lcdif_version) /* 0x1e0/0x1c0 */ - mxs_reg_32(hw_lcdif_debug0) /* 0x1f0/0x1d0 */ - mxs_reg_32(hw_lcdif_debug1) /* 0x200/0x1e0 */ - mxs_reg_32(hw_lcdif_debug2) /* 0x1f0 */ + mxs_reg_32(hw_lcdif_lcdif_stat); /* 0x1d0/0x1b0 */ + mxs_reg_32(hw_lcdif_version); /* 0x1e0/0x1c0 */ + mxs_reg_32(hw_lcdif_debug0); /* 0x1f0/0x1d0 */ + mxs_reg_32(hw_lcdif_debug1); /* 0x200/0x1e0 */ + mxs_reg_32(hw_lcdif_debug2); /* 0x1f0 */ }; #endif @@ -111,6 +111,8 @@ struct mxs_lcdif_regs { #define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS (1 << 20) #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xf << 16) #define LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET 16 +#define LCDIF_CTRL1_BYTE_PACKING_FORMAT(n) (((n) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET) & \ + LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK) #define LCDIF_CTRL1_OVERFLOW_IRQ_EN (1 << 15) #define LCDIF_CTRL1_UNDERFLOW_IRQ_EN (1 << 14) #define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN (1 << 13) @@ -157,8 +159,12 @@ struct mxs_lcdif_regs { #define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xffff << 16) #define LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET 16 +#define LCDIF_TRANSFER_COUNT_V_COUNT(n) (((n) << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) & \ + LCDIF_TRANSFER_COUNT_V_COUNT_MASK) #define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xffff << 0) #define LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET 0 +#define LCDIF_TRANSFER_COUNT_H_COUNT(n) (((n) << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET) & \ + LCDIF_TRANSFER_COUNT_H_COUNT_MASK) #define LCDIF_CUR_BUF_ADDR_MASK 0xffffffff #define LCDIF_CUR_BUF_ADDR_OFFSET 0 @@ -187,9 +193,13 @@ struct mxs_lcdif_regs { #define LCDIF_VDCTRL0_HALF_LINE_MODE (1 << 18) #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK 0x3ffff #define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET 0 +#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(n) (((n) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_OFFSET) & \ + LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK) #define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK 0xffffffff #define LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET 0 +#define LCDIF_VDCTRL1_VSYNC_PERIOD(n) (((n) << LCDIF_VDCTRL1_VSYNC_PERIOD_OFFSET) & \ + LCDIF_VDCTRL1_VSYNC_PERIOD_MASK) #if defined(CONFIG_MX23) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xff << 24) @@ -198,20 +208,32 @@ struct mxs_lcdif_regs { #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0x3fff << 18) #define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET 18 #endif +#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(n) (((n) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_OFFSET) & \ + LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK) #define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK 0x3ffff #define LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET 0 +#define LCDIF_VDCTRL2_HSYNC_PERIOD(n) (((n) << LCDIF_VDCTRL2_HSYNC_PERIOD_OFFSET) & \ + LCDIF_VDCTRL2_HSYNC_PERIOD_MASK) #define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS (1 << 29) #define LCDIF_VDCTRL3_VSYNC_ONLY (1 << 28) #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xfff << 16) #define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET 16 +#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(n) (((n) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_OFFSET) & \ + LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK) #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xffff << 0) #define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET 0 +#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(n) (((n) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_OFFSET) & \ + LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK) #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0x7 << 29) #define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET 29 +#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(n) (((n) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_OFFSET) & \ + LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK) #define LCDIF_VDCTRL4_SYNC_SIGNALS_ON (1 << 18) #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK 0x3ffff #define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET 0 +#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(n) (((n) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_OFFSET) & \ + LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK) #endif /* __MX28_REGS_LCDIF_H__ */ diff --git a/arch/arm/include/asm/arch-mxs/regs-ocotp.h b/arch/arm/include/asm/arch-mxs/regs-ocotp.h index bd80ac77fc..4c8a2dae46 100644 --- a/arch/arm/include/asm/arch-mxs/regs-ocotp.h +++ b/arch/arm/include/asm/arch-mxs/regs-ocotp.h @@ -17,49 +17,49 @@ #ifndef __ASSEMBLY__ struct mxs_ocotp_regs { - mxs_reg_32(hw_ocotp_ctrl) /* 0x0 */ - mxs_reg_32(hw_ocotp_data) /* 0x10 */ - mxs_reg_32(hw_ocotp_cust0) /* 0x20 */ - mxs_reg_32(hw_ocotp_cust1) /* 0x30 */ - mxs_reg_32(hw_ocotp_cust2) /* 0x40 */ - mxs_reg_32(hw_ocotp_cust3) /* 0x50 */ - mxs_reg_32(hw_ocotp_crypto0) /* 0x60 */ - mxs_reg_32(hw_ocotp_crypto1) /* 0x70 */ - mxs_reg_32(hw_ocotp_crypto2) /* 0x80 */ - mxs_reg_32(hw_ocotp_crypto3) /* 0x90 */ - mxs_reg_32(hw_ocotp_hwcap0) /* 0xa0 */ - mxs_reg_32(hw_ocotp_hwcap1) /* 0xb0 */ - mxs_reg_32(hw_ocotp_hwcap2) /* 0xc0 */ - mxs_reg_32(hw_ocotp_hwcap3) /* 0xd0 */ - mxs_reg_32(hw_ocotp_hwcap4) /* 0xe0 */ - mxs_reg_32(hw_ocotp_hwcap5) /* 0xf0 */ - mxs_reg_32(hw_ocotp_swcap) /* 0x100 */ - mxs_reg_32(hw_ocotp_custcap) /* 0x110 */ - mxs_reg_32(hw_ocotp_lock) /* 0x120 */ - mxs_reg_32(hw_ocotp_ops0) /* 0x130 */ - mxs_reg_32(hw_ocotp_ops1) /* 0x140 */ - mxs_reg_32(hw_ocotp_ops2) /* 0x150 */ - mxs_reg_32(hw_ocotp_ops3) /* 0x160 */ - mxs_reg_32(hw_ocotp_un0) /* 0x170 */ - mxs_reg_32(hw_ocotp_un1) /* 0x180 */ - mxs_reg_32(hw_ocotp_un2) /* 0x190 */ - mxs_reg_32(hw_ocotp_rom0) /* 0x1a0 */ - mxs_reg_32(hw_ocotp_rom1) /* 0x1b0 */ - mxs_reg_32(hw_ocotp_rom2) /* 0x1c0 */ - mxs_reg_32(hw_ocotp_rom3) /* 0x1d0 */ - mxs_reg_32(hw_ocotp_rom4) /* 0x1e0 */ - mxs_reg_32(hw_ocotp_rom5) /* 0x1f0 */ - mxs_reg_32(hw_ocotp_rom6) /* 0x200 */ - mxs_reg_32(hw_ocotp_rom7) /* 0x210 */ - mxs_reg_32(hw_ocotp_srk0) /* 0x220 */ - mxs_reg_32(hw_ocotp_srk1) /* 0x230 */ - mxs_reg_32(hw_ocotp_srk2) /* 0x240 */ - mxs_reg_32(hw_ocotp_srk3) /* 0x250 */ - mxs_reg_32(hw_ocotp_srk4) /* 0x260 */ - mxs_reg_32(hw_ocotp_srk5) /* 0x270 */ - mxs_reg_32(hw_ocotp_srk6) /* 0x280 */ - mxs_reg_32(hw_ocotp_srk7) /* 0x290 */ - mxs_reg_32(hw_ocotp_version) /* 0x2a0 */ + mxs_reg_32(hw_ocotp_ctrl); /* 0x0 */ + mxs_reg_32(hw_ocotp_data); /* 0x10 */ + mxs_reg_32(hw_ocotp_cust0); /* 0x20 */ + mxs_reg_32(hw_ocotp_cust1); /* 0x30 */ + mxs_reg_32(hw_ocotp_cust2); /* 0x40 */ + mxs_reg_32(hw_ocotp_cust3); /* 0x50 */ + mxs_reg_32(hw_ocotp_crypto0); /* 0x60 */ + mxs_reg_32(hw_ocotp_crypto1); /* 0x70 */ + mxs_reg_32(hw_ocotp_crypto2); /* 0x80 */ + mxs_reg_32(hw_ocotp_crypto3); /* 0x90 */ + mxs_reg_32(hw_ocotp_hwcap0); /* 0xa0 */ + mxs_reg_32(hw_ocotp_hwcap1); /* 0xb0 */ + mxs_reg_32(hw_ocotp_hwcap2); /* 0xc0 */ + mxs_reg_32(hw_ocotp_hwcap3); /* 0xd0 */ + mxs_reg_32(hw_ocotp_hwcap4); /* 0xe0 */ + mxs_reg_32(hw_ocotp_hwcap5); /* 0xf0 */ + mxs_reg_32(hw_ocotp_swcap); /* 0x100 */ + mxs_reg_32(hw_ocotp_custcap); /* 0x110 */ + mxs_reg_32(hw_ocotp_lock); /* 0x120 */ + mxs_reg_32(hw_ocotp_ops0); /* 0x130 */ + mxs_reg_32(hw_ocotp_ops1); /* 0x140 */ + mxs_reg_32(hw_ocotp_ops2); /* 0x150 */ + mxs_reg_32(hw_ocotp_ops3); /* 0x160 */ + mxs_reg_32(hw_ocotp_un0); /* 0x170 */ + mxs_reg_32(hw_ocotp_un1); /* 0x180 */ + mxs_reg_32(hw_ocotp_un2); /* 0x190 */ + mxs_reg_32(hw_ocotp_rom0); /* 0x1a0 */ + mxs_reg_32(hw_ocotp_rom1); /* 0x1b0 */ + mxs_reg_32(hw_ocotp_rom2); /* 0x1c0 */ + mxs_reg_32(hw_ocotp_rom3); /* 0x1d0 */ + mxs_reg_32(hw_ocotp_rom4); /* 0x1e0 */ + mxs_reg_32(hw_ocotp_rom5); /* 0x1f0 */ + mxs_reg_32(hw_ocotp_rom6); /* 0x200 */ + mxs_reg_32(hw_ocotp_rom7); /* 0x210 */ + mxs_reg_32(hw_ocotp_srk0); /* 0x220 */ + mxs_reg_32(hw_ocotp_srk1); /* 0x230 */ + mxs_reg_32(hw_ocotp_srk2); /* 0x240 */ + mxs_reg_32(hw_ocotp_srk3); /* 0x250 */ + mxs_reg_32(hw_ocotp_srk4); /* 0x260 */ + mxs_reg_32(hw_ocotp_srk5); /* 0x270 */ + mxs_reg_32(hw_ocotp_srk6); /* 0x280 */ + mxs_reg_32(hw_ocotp_srk7); /* 0x290 */ + mxs_reg_32(hw_ocotp_version); /* 0x2a0 */ }; #endif diff --git a/arch/arm/include/asm/arch-mxs/regs-pinctrl.h b/arch/arm/include/asm/arch-mxs/regs-pinctrl.h index 251fe6616d..6e6db1d4c6 100644 --- a/arch/arm/include/asm/arch-mxs/regs-pinctrl.h +++ b/arch/arm/include/asm/arch-mxs/regs-pinctrl.h @@ -17,129 +17,129 @@ #ifndef __ASSEMBLY__ struct mxs_pinctrl_regs { - mxs_reg_32(hw_pinctrl_ctrl) /* 0x0 */ + mxs_reg_32(hw_pinctrl_ctrl); /* 0x0 */ uint32_t reserved1[60]; - mxs_reg_32(hw_pinctrl_muxsel0) /* 0x100 */ - mxs_reg_32(hw_pinctrl_muxsel1) /* 0x110 */ - mxs_reg_32(hw_pinctrl_muxsel2) /* 0x120 */ - mxs_reg_32(hw_pinctrl_muxsel3) /* 0x130 */ - mxs_reg_32(hw_pinctrl_muxsel4) /* 0x140 */ - mxs_reg_32(hw_pinctrl_muxsel5) /* 0x150 */ - mxs_reg_32(hw_pinctrl_muxsel6) /* 0x160 */ - mxs_reg_32(hw_pinctrl_muxsel7) /* 0x170 */ - mxs_reg_32(hw_pinctrl_muxsel8) /* 0x180 */ - mxs_reg_32(hw_pinctrl_muxsel9) /* 0x190 */ - mxs_reg_32(hw_pinctrl_muxsel10) /* 0x1a0 */ - mxs_reg_32(hw_pinctrl_muxsel11) /* 0x1b0 */ - mxs_reg_32(hw_pinctrl_muxsel12) /* 0x1c0 */ - mxs_reg_32(hw_pinctrl_muxsel13) /* 0x1d0 */ + mxs_reg_32(hw_pinctrl_muxsel0); /* 0x100 */ + mxs_reg_32(hw_pinctrl_muxsel1); /* 0x110 */ + mxs_reg_32(hw_pinctrl_muxsel2); /* 0x120 */ + mxs_reg_32(hw_pinctrl_muxsel3); /* 0x130 */ + mxs_reg_32(hw_pinctrl_muxsel4); /* 0x140 */ + mxs_reg_32(hw_pinctrl_muxsel5); /* 0x150 */ + mxs_reg_32(hw_pinctrl_muxsel6); /* 0x160 */ + mxs_reg_32(hw_pinctrl_muxsel7); /* 0x170 */ + mxs_reg_32(hw_pinctrl_muxsel8); /* 0x180 */ + mxs_reg_32(hw_pinctrl_muxsel9); /* 0x190 */ + mxs_reg_32(hw_pinctrl_muxsel10); /* 0x1a0 */ + mxs_reg_32(hw_pinctrl_muxsel11); /* 0x1b0 */ + mxs_reg_32(hw_pinctrl_muxsel12); /* 0x1c0 */ + mxs_reg_32(hw_pinctrl_muxsel13); /* 0x1d0 */ uint32_t reserved2[72]; - mxs_reg_32(hw_pinctrl_drive0) /* 0x300 */ - mxs_reg_32(hw_pinctrl_drive1) /* 0x310 */ - mxs_reg_32(hw_pinctrl_drive2) /* 0x320 */ - mxs_reg_32(hw_pinctrl_drive3) /* 0x330 */ - mxs_reg_32(hw_pinctrl_drive4) /* 0x340 */ - mxs_reg_32(hw_pinctrl_drive5) /* 0x350 */ - mxs_reg_32(hw_pinctrl_drive6) /* 0x360 */ - mxs_reg_32(hw_pinctrl_drive7) /* 0x370 */ - mxs_reg_32(hw_pinctrl_drive8) /* 0x380 */ - mxs_reg_32(hw_pinctrl_drive9) /* 0x390 */ - mxs_reg_32(hw_pinctrl_drive10) /* 0x3a0 */ - mxs_reg_32(hw_pinctrl_drive11) /* 0x3b0 */ - mxs_reg_32(hw_pinctrl_drive12) /* 0x3c0 */ - mxs_reg_32(hw_pinctrl_drive13) /* 0x3d0 */ - mxs_reg_32(hw_pinctrl_drive14) /* 0x3e0 */ - mxs_reg_32(hw_pinctrl_drive15) /* 0x3f0 */ - mxs_reg_32(hw_pinctrl_drive16) /* 0x400 */ - mxs_reg_32(hw_pinctrl_drive17) /* 0x410 */ - mxs_reg_32(hw_pinctrl_drive18) /* 0x420 */ - mxs_reg_32(hw_pinctrl_drive19) /* 0x430 */ + mxs_reg_32(hw_pinctrl_drive0); /* 0x300 */ + mxs_reg_32(hw_pinctrl_drive1); /* 0x310 */ + mxs_reg_32(hw_pinctrl_drive2); /* 0x320 */ + mxs_reg_32(hw_pinctrl_drive3); /* 0x330 */ + mxs_reg_32(hw_pinctrl_drive4); /* 0x340 */ + mxs_reg_32(hw_pinctrl_drive5); /* 0x350 */ + mxs_reg_32(hw_pinctrl_drive6); /* 0x360 */ + mxs_reg_32(hw_pinctrl_drive7); /* 0x370 */ + mxs_reg_32(hw_pinctrl_drive8); /* 0x380 */ + mxs_reg_32(hw_pinctrl_drive9); /* 0x390 */ + mxs_reg_32(hw_pinctrl_drive10); /* 0x3a0 */ + mxs_reg_32(hw_pinctrl_drive11); /* 0x3b0 */ + mxs_reg_32(hw_pinctrl_drive12); /* 0x3c0 */ + mxs_reg_32(hw_pinctrl_drive13); /* 0x3d0 */ + mxs_reg_32(hw_pinctrl_drive14); /* 0x3e0 */ + mxs_reg_32(hw_pinctrl_drive15); /* 0x3f0 */ + mxs_reg_32(hw_pinctrl_drive16); /* 0x400 */ + mxs_reg_32(hw_pinctrl_drive17); /* 0x410 */ + mxs_reg_32(hw_pinctrl_drive18); /* 0x420 */ + mxs_reg_32(hw_pinctrl_drive19); /* 0x430 */ uint32_t reserved3[112]; - mxs_reg_32(hw_pinctrl_pull0) /* 0x600 */ - mxs_reg_32(hw_pinctrl_pull1) /* 0x610 */ - mxs_reg_32(hw_pinctrl_pull2) /* 0x620 */ - mxs_reg_32(hw_pinctrl_pull3) /* 0x630 */ - mxs_reg_32(hw_pinctrl_pull4) /* 0x640 */ - mxs_reg_32(hw_pinctrl_pull5) /* 0x650 */ - mxs_reg_32(hw_pinctrl_pull6) /* 0x660 */ + mxs_reg_32(hw_pinctrl_pull0); /* 0x600 */ + mxs_reg_32(hw_pinctrl_pull1); /* 0x610 */ + mxs_reg_32(hw_pinctrl_pull2); /* 0x620 */ + mxs_reg_32(hw_pinctrl_pull3); /* 0x630 */ + mxs_reg_32(hw_pinctrl_pull4); /* 0x640 */ + mxs_reg_32(hw_pinctrl_pull5); /* 0x650 */ + mxs_reg_32(hw_pinctrl_pull6); /* 0x660 */ uint32_t reserved4[36]; - mxs_reg_32(hw_pinctrl_dout0) /* 0x700 */ - mxs_reg_32(hw_pinctrl_dout1) /* 0x710 */ - mxs_reg_32(hw_pinctrl_dout2) /* 0x720 */ - mxs_reg_32(hw_pinctrl_dout3) /* 0x730 */ - mxs_reg_32(hw_pinctrl_dout4) /* 0x740 */ + mxs_reg_32(hw_pinctrl_dout0); /* 0x700 */ + mxs_reg_32(hw_pinctrl_dout1); /* 0x710 */ + mxs_reg_32(hw_pinctrl_dout2); /* 0x720 */ + mxs_reg_32(hw_pinctrl_dout3); /* 0x730 */ + mxs_reg_32(hw_pinctrl_dout4); /* 0x740 */ uint32_t reserved5[108]; - mxs_reg_32(hw_pinctrl_din0) /* 0x900 */ - mxs_reg_32(hw_pinctrl_din1) /* 0x910 */ - mxs_reg_32(hw_pinctrl_din2) /* 0x920 */ - mxs_reg_32(hw_pinctrl_din3) /* 0x930 */ - mxs_reg_32(hw_pinctrl_din4) /* 0x940 */ + mxs_reg_32(hw_pinctrl_din0); /* 0x900 */ + mxs_reg_32(hw_pinctrl_din1); /* 0x910 */ + mxs_reg_32(hw_pinctrl_din2); /* 0x920 */ + mxs_reg_32(hw_pinctrl_din3); /* 0x930 */ + mxs_reg_32(hw_pinctrl_din4); /* 0x940 */ uint32_t reserved6[108]; - mxs_reg_32(hw_pinctrl_doe0) /* 0xb00 */ - mxs_reg_32(hw_pinctrl_doe1) /* 0xb10 */ - mxs_reg_32(hw_pinctrl_doe2) /* 0xb20 */ - mxs_reg_32(hw_pinctrl_doe3) /* 0xb30 */ - mxs_reg_32(hw_pinctrl_doe4) /* 0xb40 */ + mxs_reg_32(hw_pinctrl_doe0); /* 0xb00 */ + mxs_reg_32(hw_pinctrl_doe1); /* 0xb10 */ + mxs_reg_32(hw_pinctrl_doe2); /* 0xb20 */ + mxs_reg_32(hw_pinctrl_doe3); /* 0xb30 */ + mxs_reg_32(hw_pinctrl_doe4); /* 0xb40 */ uint32_t reserved7[300]; - mxs_reg_32(hw_pinctrl_pin2irq0) /* 0x1000 */ - mxs_reg_32(hw_pinctrl_pin2irq1) /* 0x1010 */ - mxs_reg_32(hw_pinctrl_pin2irq2) /* 0x1020 */ - mxs_reg_32(hw_pinctrl_pin2irq3) /* 0x1030 */ - mxs_reg_32(hw_pinctrl_pin2irq4) /* 0x1040 */ + mxs_reg_32(hw_pinctrl_pin2irq0); /* 0x1000 */ + mxs_reg_32(hw_pinctrl_pin2irq1); /* 0x1010 */ + mxs_reg_32(hw_pinctrl_pin2irq2); /* 0x1020 */ + mxs_reg_32(hw_pinctrl_pin2irq3); /* 0x1030 */ + mxs_reg_32(hw_pinctrl_pin2irq4); /* 0x1040 */ uint32_t reserved8[44]; - mxs_reg_32(hw_pinctrl_irqen0) /* 0x1100 */ - mxs_reg_32(hw_pinctrl_irqen1) /* 0x1110 */ - mxs_reg_32(hw_pinctrl_irqen2) /* 0x1120 */ - mxs_reg_32(hw_pinctrl_irqen3) /* 0x1130 */ - mxs_reg_32(hw_pinctrl_irqen4) /* 0x1140 */ + mxs_reg_32(hw_pinctrl_irqen0); /* 0x1100 */ + mxs_reg_32(hw_pinctrl_irqen1); /* 0x1110 */ + mxs_reg_32(hw_pinctrl_irqen2); /* 0x1120 */ + mxs_reg_32(hw_pinctrl_irqen3); /* 0x1130 */ + mxs_reg_32(hw_pinctrl_irqen4); /* 0x1140 */ uint32_t reserved9[44]; - mxs_reg_32(hw_pinctrl_irqlevel0) /* 0x1200 */ - mxs_reg_32(hw_pinctrl_irqlevel1) /* 0x1210 */ - mxs_reg_32(hw_pinctrl_irqlevel2) /* 0x1220 */ - mxs_reg_32(hw_pinctrl_irqlevel3) /* 0x1230 */ - mxs_reg_32(hw_pinctrl_irqlevel4) /* 0x1240 */ + mxs_reg_32(hw_pinctrl_irqlevel0); /* 0x1200 */ + mxs_reg_32(hw_pinctrl_irqlevel1); /* 0x1210 */ + mxs_reg_32(hw_pinctrl_irqlevel2); /* 0x1220 */ + mxs_reg_32(hw_pinctrl_irqlevel3); /* 0x1230 */ + mxs_reg_32(hw_pinctrl_irqlevel4); /* 0x1240 */ uint32_t reserved10[44]; - mxs_reg_32(hw_pinctrl_irqpol0) /* 0x1300 */ - mxs_reg_32(hw_pinctrl_irqpol1) /* 0x1310 */ - mxs_reg_32(hw_pinctrl_irqpol2) /* 0x1320 */ - mxs_reg_32(hw_pinctrl_irqpol3) /* 0x1330 */ - mxs_reg_32(hw_pinctrl_irqpol4) /* 0x1340 */ + mxs_reg_32(hw_pinctrl_irqpol0); /* 0x1300 */ + mxs_reg_32(hw_pinctrl_irqpol1); /* 0x1310 */ + mxs_reg_32(hw_pinctrl_irqpol2); /* 0x1320 */ + mxs_reg_32(hw_pinctrl_irqpol3); /* 0x1330 */ + mxs_reg_32(hw_pinctrl_irqpol4); /* 0x1340 */ uint32_t reserved11[44]; - mxs_reg_32(hw_pinctrl_irqstat0) /* 0x1400 */ - mxs_reg_32(hw_pinctrl_irqstat1) /* 0x1410 */ - mxs_reg_32(hw_pinctrl_irqstat2) /* 0x1420 */ - mxs_reg_32(hw_pinctrl_irqstat3) /* 0x1430 */ - mxs_reg_32(hw_pinctrl_irqstat4) /* 0x1440 */ + mxs_reg_32(hw_pinctrl_irqstat0); /* 0x1400 */ + mxs_reg_32(hw_pinctrl_irqstat1); /* 0x1410 */ + mxs_reg_32(hw_pinctrl_irqstat2); /* 0x1420 */ + mxs_reg_32(hw_pinctrl_irqstat3); /* 0x1430 */ + mxs_reg_32(hw_pinctrl_irqstat4); /* 0x1440 */ uint32_t reserved12[380]; - mxs_reg_32(hw_pinctrl_emi_odt_ctrl) /* 0x1a40 */ + mxs_reg_32(hw_pinctrl_emi_odt_ctrl); /* 0x1a40 */ uint32_t reserved13[76]; - mxs_reg_32(hw_pinctrl_emi_ds_ctrl) /* 0x1b80 */ + mxs_reg_32(hw_pinctrl_emi_ds_ctrl); /* 0x1b80 */ }; #endif diff --git a/arch/arm/include/asm/arch-mxs/regs-power-mx28.h b/arch/arm/include/asm/arch-mxs/regs-power-mx28.h index 9528e3ce9a..f24d99da66 100644 --- a/arch/arm/include/asm/arch-mxs/regs-power-mx28.h +++ b/arch/arm/include/asm/arch-mxs/regs-power-mx28.h @@ -13,41 +13,32 @@ #ifndef __ASSEMBLY__ struct mxs_power_regs { - mxs_reg_32(hw_power_ctrl) - mxs_reg_32(hw_power_5vctrl) - mxs_reg_32(hw_power_minpwr) - mxs_reg_32(hw_power_charge) - uint32_t hw_power_vdddctrl; - uint32_t reserved_vddd[3]; - uint32_t hw_power_vddactrl; - uint32_t reserved_vdda[3]; - uint32_t hw_power_vddioctrl; - uint32_t reserved_vddio[3]; - uint32_t hw_power_vddmemctrl; - uint32_t reserved_vddmem[3]; - uint32_t hw_power_dcdc4p2; - uint32_t reserved_dcdc4p2[3]; - uint32_t hw_power_misc; - uint32_t reserved_misc[3]; - uint32_t hw_power_dclimits; - uint32_t reserved_dclimits[3]; - mxs_reg_32(hw_power_loopctrl) - uint32_t hw_power_sts; - uint32_t reserved_sts[3]; - mxs_reg_32(hw_power_speed) - uint32_t hw_power_battmonitor; - uint32_t reserved_battmonitor[3]; + mxs_reg_32(hw_power_ctrl); /* 0x00 */ + mxs_reg_32(hw_power_5vctrl); /* 0x10 */ + mxs_reg_32(hw_power_minpwr); /* 0x20 */ + mxs_reg_32(hw_power_charge); /* 0x30 */ + reg_32(hw_power_vdddctrl); /* 0x40 */ + reg_32(hw_power_vddactrl); /* 0x50 */ + reg_32(hw_power_vddioctrl); /* 0x60 */ + reg_32(hw_power_vddmemctrl); /* 0x70 */ + reg_32(hw_power_dcdc4p2); /* 0x80 */ + reg_32(hw_power_misc); /* 0x90 */ + reg_32(hw_power_dclimits); /* 0xa0 */ + mxs_reg_32(hw_power_loopctrl); /* 0xb0 */ + reg_32(hw_power_sts); /* 0xc0 */ + mxs_reg_32(hw_power_speed); /* 0xd0 */ + reg_32(hw_power_battmonitor); /* 0xe0 */ - uint32_t reserved[4]; + reg_32(reserved); /* 0xf0 */ - mxs_reg_32(hw_power_reset) - mxs_reg_32(hw_power_debug) - mxs_reg_32(hw_power_thermal) - mxs_reg_32(hw_power_usb1ctrl) - mxs_reg_32(hw_power_special) - mxs_reg_32(hw_power_version) - mxs_reg_32(hw_power_anaclkctrl) - mxs_reg_32(hw_power_refctrl) + mxs_reg_32(hw_power_reset); /* 0x100 */ + mxs_reg_32(hw_power_debug); /* 0x110 */ + mxs_reg_32(hw_power_thermal); /* 0x120 */ + mxs_reg_32(hw_power_usb1ctrl); /* 0x130 */ + mxs_reg_32(hw_power_special); /* 0x140 */ + mxs_reg_32(hw_power_version); /* 0x150 */ + mxs_reg_32(hw_power_anaclkctrl); /* 0x160 */ + mxs_reg_32(hw_power_refctrl); /* 0x170 */ }; #endif @@ -348,7 +339,8 @@ struct mxs_power_regs { #define POWER_THERMAL_PWD (1 << 7) #define POWER_THERMAL_LOW_POWER (1 << 6) #define POWER_THERMAL_OFFSET_ADJ_MASK (0x3 << 4) -#define POWER_THERMAL_OFFSET_ADJ_OFFSET 4 +#define POWER_THERMAL_OFFSET_ADJ_OFFSET(n) (((n) << 4) & \ + POWER_THERMAL_OFFSET_ADJ_MASK) #define POWER_THERMAL_OFFSET_ADJ_ENABLE (1 << 3) #define POWER_THERMAL_TEMP_THRESHOLD_MASK 0x7 #define POWER_THERMAL_TEMP_THRESHOLD_OFFSET 0 diff --git a/arch/arm/include/asm/arch-mxs/regs-rtc.h b/arch/arm/include/asm/arch-mxs/regs-rtc.h index 03e2e5dd62..8d3eccfb75 100644 --- a/arch/arm/include/asm/arch-mxs/regs-rtc.h +++ b/arch/arm/include/asm/arch-mxs/regs-rtc.h @@ -14,20 +14,20 @@ #ifndef __ASSEMBLY__ struct mxs_rtc_regs { - mxs_reg_32(hw_rtc_ctrl) - mxs_reg_32(hw_rtc_stat) - mxs_reg_32(hw_rtc_milliseconds) - mxs_reg_32(hw_rtc_seconds) - mxs_reg_32(hw_rtc_rtc_alarm) - mxs_reg_32(hw_rtc_watchdog) - mxs_reg_32(hw_rtc_persistent0) - mxs_reg_32(hw_rtc_persistent1) - mxs_reg_32(hw_rtc_persistent2) - mxs_reg_32(hw_rtc_persistent3) - mxs_reg_32(hw_rtc_persistent4) - mxs_reg_32(hw_rtc_persistent5) - mxs_reg_32(hw_rtc_debug) - mxs_reg_32(hw_rtc_version) + mxs_reg_32(hw_rtc_ctrl); + mxs_reg_32(hw_rtc_stat); + mxs_reg_32(hw_rtc_milliseconds); + mxs_reg_32(hw_rtc_seconds); + mxs_reg_32(hw_rtc_rtc_alarm); + mxs_reg_32(hw_rtc_watchdog); + mxs_reg_32(hw_rtc_persistent0); + mxs_reg_32(hw_rtc_persistent1); + mxs_reg_32(hw_rtc_persistent2); + mxs_reg_32(hw_rtc_persistent3); + mxs_reg_32(hw_rtc_persistent4); + mxs_reg_32(hw_rtc_persistent5); + mxs_reg_32(hw_rtc_debug); + mxs_reg_32(hw_rtc_version); }; #endif @@ -46,8 +46,24 @@ struct mxs_rtc_regs { #define RTC_STAT_WATCHDOG_PRESENT (1 << 29) #define RTC_STAT_XTAL32000_PRESENT (1 << 28) #define RTC_STAT_XTAL32768_PRESENT (1 << 27) +#define RTC_STAT_STALE_REGS_SECONDS (1 << 23) +#define RTC_STAT_STALE_REGS_ALARM (1 << 22) +#define RTC_STAT_STALE_REGS_PERSISTENT5 (1 << 21) +#define RTC_STAT_STALE_REGS_PERSISTENT4 (1 << 20) +#define RTC_STAT_STALE_REGS_PERSISTENT3 (1 << 19) +#define RTC_STAT_STALE_REGS_PERSISTENT2 (1 << 18) +#define RTC_STAT_STALE_REGS_PERSISTENT1 (1 << 17) +#define RTC_STAT_STALE_REGS_PERSISTENT0 (1 << 16) #define RTC_STAT_STALE_REGS_MASK (0xff << 16) #define RTC_STAT_STALE_REGS_OFFSET 16 +#define RTC_STAT_NEW_REGS_SECONDS (1 << 15) +#define RTC_STAT_NEW_REGS_ALARM (1 << 14) +#define RTC_STAT_NEW_REGS_PERSISTENT5 (1 << 13) +#define RTC_STAT_NEW_REGS_PERSISTENT4 (1 << 12) +#define RTC_STAT_NEW_REGS_PERSISTENT3 (1 << 11) +#define RTC_STAT_NEW_REGS_PERSISTENT2 (1 << 10) +#define RTC_STAT_NEW_REGS_PERSISTENT1 (1 << 9) +#define RTC_STAT_NEW_REGS_PERSISTENT0 (1 << 8) #define RTC_STAT_NEW_REGS_MASK (0xff << 8) #define RTC_STAT_NEW_REGS_OFFSET 8 diff --git a/arch/arm/include/asm/arch-mxs/regs-ssp.h b/arch/arm/include/asm/arch-mxs/regs-ssp.h index e991216d0b..be74e4b1cf 100644 --- a/arch/arm/include/asm/arch-mxs/regs-ssp.h +++ b/arch/arm/include/asm/arch-mxs/regs-ssp.h @@ -38,26 +38,26 @@ struct mxs_ssp_regs { }; #elif defined(CONFIG_MX28) struct mxs_ssp_regs { - mxs_reg_32(hw_ssp_ctrl0) - mxs_reg_32(hw_ssp_cmd0) - mxs_reg_32(hw_ssp_cmd1) - mxs_reg_32(hw_ssp_xfer_size) - mxs_reg_32(hw_ssp_block_size) - mxs_reg_32(hw_ssp_compref) - mxs_reg_32(hw_ssp_compmask) - mxs_reg_32(hw_ssp_timing) - mxs_reg_32(hw_ssp_ctrl1) - mxs_reg_32(hw_ssp_data) - mxs_reg_32(hw_ssp_sdresp0) - mxs_reg_32(hw_ssp_sdresp1) - mxs_reg_32(hw_ssp_sdresp2) - mxs_reg_32(hw_ssp_sdresp3) - mxs_reg_32(hw_ssp_ddr_ctrl) - mxs_reg_32(hw_ssp_dll_ctrl) - mxs_reg_32(hw_ssp_status) - mxs_reg_32(hw_ssp_dll_sts) - mxs_reg_32(hw_ssp_debug) - mxs_reg_32(hw_ssp_version) + mxs_reg_32(hw_ssp_ctrl0); + mxs_reg_32(hw_ssp_cmd0); + mxs_reg_32(hw_ssp_cmd1); + mxs_reg_32(hw_ssp_xfer_size); + mxs_reg_32(hw_ssp_block_size); + mxs_reg_32(hw_ssp_compref); + mxs_reg_32(hw_ssp_compmask); + mxs_reg_32(hw_ssp_timing); + mxs_reg_32(hw_ssp_ctrl1); + mxs_reg_32(hw_ssp_data); + mxs_reg_32(hw_ssp_sdresp0); + mxs_reg_32(hw_ssp_sdresp1); + mxs_reg_32(hw_ssp_sdresp2); + mxs_reg_32(hw_ssp_sdresp3); + mxs_reg_32(hw_ssp_ddr_ctrl); + mxs_reg_32(hw_ssp_dll_ctrl); + mxs_reg_32(hw_ssp_status); + mxs_reg_32(hw_ssp_dll_sts); + mxs_reg_32(hw_ssp_debug); + mxs_reg_32(hw_ssp_version); }; #endif diff --git a/arch/arm/include/asm/arch-mxs/regs-timrot.h b/arch/arm/include/asm/arch-mxs/regs-timrot.h index 713c630dcc..0ee3ec81bb 100644 --- a/arch/arm/include/asm/arch-mxs/regs-timrot.h +++ b/arch/arm/include/asm/arch-mxs/regs-timrot.h @@ -16,36 +16,36 @@ #ifndef __ASSEMBLY__ struct mxs_timrot_regs { - mxs_reg_32(hw_timrot_rotctrl) - mxs_reg_32(hw_timrot_rotcount) + mxs_reg_32(hw_timrot_rotctrl); + mxs_reg_32(hw_timrot_rotcount); #if defined(CONFIG_MX23) - mxs_reg_32(hw_timrot_timctrl0) - mxs_reg_32(hw_timrot_timcount0) - mxs_reg_32(hw_timrot_timctrl1) - mxs_reg_32(hw_timrot_timcount1) - mxs_reg_32(hw_timrot_timctrl2) - mxs_reg_32(hw_timrot_timcount2) - mxs_reg_32(hw_timrot_timctrl3) - mxs_reg_32(hw_timrot_timcount3) + mxs_reg_32(hw_timrot_timctrl0); + mxs_reg_32(hw_timrot_timcount0); + mxs_reg_32(hw_timrot_timctrl1); + mxs_reg_32(hw_timrot_timcount1); + mxs_reg_32(hw_timrot_timctrl2); + mxs_reg_32(hw_timrot_timcount2); + mxs_reg_32(hw_timrot_timctrl3); + mxs_reg_32(hw_timrot_timcount3); #elif defined(CONFIG_MX28) - mxs_reg_32(hw_timrot_timctrl0) - mxs_reg_32(hw_timrot_running_count0) - mxs_reg_32(hw_timrot_fixed_count0) - mxs_reg_32(hw_timrot_match_count0) - mxs_reg_32(hw_timrot_timctrl1) - mxs_reg_32(hw_timrot_running_count1) - mxs_reg_32(hw_timrot_fixed_count1) - mxs_reg_32(hw_timrot_match_count1) - mxs_reg_32(hw_timrot_timctrl2) - mxs_reg_32(hw_timrot_running_count2) - mxs_reg_32(hw_timrot_fixed_count2) - mxs_reg_32(hw_timrot_match_count2) - mxs_reg_32(hw_timrot_timctrl3) - mxs_reg_32(hw_timrot_running_count3) - mxs_reg_32(hw_timrot_fixed_count3) - mxs_reg_32(hw_timrot_match_count3) + mxs_reg_32(hw_timrot_timctrl0); + mxs_reg_32(hw_timrot_running_count0); + mxs_reg_32(hw_timrot_fixed_count0); + mxs_reg_32(hw_timrot_match_count0); + mxs_reg_32(hw_timrot_timctrl1); + mxs_reg_32(hw_timrot_running_count1); + mxs_reg_32(hw_timrot_fixed_count1); + mxs_reg_32(hw_timrot_match_count1); + mxs_reg_32(hw_timrot_timctrl2); + mxs_reg_32(hw_timrot_running_count2); + mxs_reg_32(hw_timrot_fixed_count2); + mxs_reg_32(hw_timrot_match_count2); + mxs_reg_32(hw_timrot_timctrl3); + mxs_reg_32(hw_timrot_running_count3); + mxs_reg_32(hw_timrot_fixed_count3); + mxs_reg_32(hw_timrot_match_count3); #endif - mxs_reg_32(hw_timrot_version) + mxs_reg_32(hw_timrot_version); }; #endif diff --git a/arch/arm/include/asm/arch-mxs/regs-usbphy.h b/arch/arm/include/asm/arch-mxs/regs-usbphy.h index eabefc6448..bf110a5e0e 100644 --- a/arch/arm/include/asm/arch-mxs/regs-usbphy.h +++ b/arch/arm/include/asm/arch-mxs/regs-usbphy.h @@ -11,16 +11,16 @@ #define __REGS_USBPHY_H__ struct mxs_usbphy_regs { - mxs_reg_32(hw_usbphy_pwd) - mxs_reg_32(hw_usbphy_tx) - mxs_reg_32(hw_usbphy_rx) - mxs_reg_32(hw_usbphy_ctrl) - mxs_reg_32(hw_usbphy_status) - mxs_reg_32(hw_usbphy_debug) - mxs_reg_32(hw_usbphy_debug0_status) - mxs_reg_32(hw_usbphy_debug1) - mxs_reg_32(hw_usbphy_version) - mxs_reg_32(hw_usbphy_ip) + mxs_reg_32(hw_usbphy_pwd); + mxs_reg_32(hw_usbphy_tx); + mxs_reg_32(hw_usbphy_rx); + mxs_reg_32(hw_usbphy_ctrl); + mxs_reg_32(hw_usbphy_status); + mxs_reg_32(hw_usbphy_debug); + mxs_reg_32(hw_usbphy_debug0_status); + mxs_reg_32(hw_usbphy_debug1); + mxs_reg_32(hw_usbphy_version); + mxs_reg_32(hw_usbphy_ip); }; #define USBPHY_PWD_RXPWDRX (1 << 20) diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h index 1038592c92..3f4c108942 100644 --- a/arch/arm/include/asm/arch-mxs/sys_proto.h +++ b/arch/arm/include/asm/arch-mxs/sys_proto.h @@ -10,6 +10,8 @@ #ifndef __SYS_PROTO_H__ #define __SYS_PROTO_H__ +struct mxs_register_32; + int mxs_reset_block(struct mxs_register_32 *reg); int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, @@ -20,6 +22,8 @@ int mxs_wait_mask_clr(struct mxs_register_32 *reg, int mxsmmc_initialize(bd_t *bis, int id, int (*wp)(int), int (*cd)(int)); +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); + #ifdef CONFIG_SPL_BUILD #if defined(CONFIG_MX23) diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 1b94a99c54..56cbd07431 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -585,111 +585,111 @@ /* Reg mapping structure */ struct emif_reg_struct { - u32 emif_mod_id_rev; - u32 emif_status; - u32 emif_sdram_config; - u32 emif_lpddr2_nvm_config; - u32 emif_sdram_ref_ctrl; - u32 emif_sdram_ref_ctrl_shdw; - u32 emif_sdram_tim_1; - u32 emif_sdram_tim_1_shdw; - u32 emif_sdram_tim_2; - u32 emif_sdram_tim_2_shdw; - u32 emif_sdram_tim_3; - u32 emif_sdram_tim_3_shdw; - u32 emif_lpddr2_nvm_tim; - u32 emif_lpddr2_nvm_tim_shdw; - u32 emif_pwr_mgmt_ctrl; - u32 emif_pwr_mgmt_ctrl_shdw; - u32 emif_lpddr2_mode_reg_data; - u32 padding1[1]; - u32 emif_lpddr2_mode_reg_data_es2; - u32 padding11[1]; - u32 emif_lpddr2_mode_reg_cfg; - u32 emif_l3_config; - u32 emif_l3_cfg_val_1; - u32 emif_l3_cfg_val_2; - u32 emif_iodft_tlgc; - u32 padding2[7]; - u32 emif_perf_cnt_1; - u32 emif_perf_cnt_2; - u32 emif_perf_cnt_cfg; - u32 emif_perf_cnt_sel; - u32 emif_perf_cnt_tim; - u32 padding3; - u32 emif_read_idlectrl; - u32 emif_read_idlectrl_shdw; - u32 padding4; - u32 emif_irqstatus_raw_sys; - u32 emif_irqstatus_raw_ll; - u32 emif_irqstatus_sys; - u32 emif_irqstatus_ll; - u32 emif_irqenable_set_sys; - u32 emif_irqenable_set_ll; - u32 emif_irqenable_clr_sys; - u32 emif_irqenable_clr_ll; - u32 padding5; - u32 emif_zq_config; - u32 emif_temp_alert_config; - u32 emif_l3_err_log; - u32 emif_rd_wr_lvl_rmp_win; - u32 emif_rd_wr_lvl_rmp_ctl; - u32 emif_rd_wr_lvl_ctl; - u32 padding6[1]; - u32 emif_ddr_phy_ctrl_1; - u32 emif_ddr_phy_ctrl_1_shdw; - u32 emif_ddr_phy_ctrl_2; - u32 padding7[12]; - u32 emif_rd_wr_exec_thresh; - u32 padding8[55]; - u32 emif_ddr_ext_phy_ctrl_1; - u32 emif_ddr_ext_phy_ctrl_1_shdw; - u32 emif_ddr_ext_phy_ctrl_2; - u32 emif_ddr_ext_phy_ctrl_2_shdw; - u32 emif_ddr_ext_phy_ctrl_3; - u32 emif_ddr_ext_phy_ctrl_3_shdw; - u32 emif_ddr_ext_phy_ctrl_4; - u32 emif_ddr_ext_phy_ctrl_4_shdw; - u32 emif_ddr_ext_phy_ctrl_5; - u32 emif_ddr_ext_phy_ctrl_5_shdw; - u32 emif_ddr_ext_phy_ctrl_6; - u32 emif_ddr_ext_phy_ctrl_6_shdw; - u32 emif_ddr_ext_phy_ctrl_7; - u32 emif_ddr_ext_phy_ctrl_7_shdw; - u32 emif_ddr_ext_phy_ctrl_8; - u32 emif_ddr_ext_phy_ctrl_8_shdw; - u32 emif_ddr_ext_phy_ctrl_9; - u32 emif_ddr_ext_phy_ctrl_9_shdw; - u32 emif_ddr_ext_phy_ctrl_10; - u32 emif_ddr_ext_phy_ctrl_10_shdw; - u32 emif_ddr_ext_phy_ctrl_11; - u32 emif_ddr_ext_phy_ctrl_11_shdw; - u32 emif_ddr_ext_phy_ctrl_12; - u32 emif_ddr_ext_phy_ctrl_12_shdw; - u32 emif_ddr_ext_phy_ctrl_13; - u32 emif_ddr_ext_phy_ctrl_13_shdw; - u32 emif_ddr_ext_phy_ctrl_14; - u32 emif_ddr_ext_phy_ctrl_14_shdw; - u32 emif_ddr_ext_phy_ctrl_15; - u32 emif_ddr_ext_phy_ctrl_15_shdw; - u32 emif_ddr_ext_phy_ctrl_16; - u32 emif_ddr_ext_phy_ctrl_16_shdw; - u32 emif_ddr_ext_phy_ctrl_17; - u32 emif_ddr_ext_phy_ctrl_17_shdw; - u32 emif_ddr_ext_phy_ctrl_18; - u32 emif_ddr_ext_phy_ctrl_18_shdw; - u32 emif_ddr_ext_phy_ctrl_19; - u32 emif_ddr_ext_phy_ctrl_19_shdw; - u32 emif_ddr_ext_phy_ctrl_20; - u32 emif_ddr_ext_phy_ctrl_20_shdw; - u32 emif_ddr_ext_phy_ctrl_21; - u32 emif_ddr_ext_phy_ctrl_21_shdw; - u32 emif_ddr_ext_phy_ctrl_22; - u32 emif_ddr_ext_phy_ctrl_22_shdw; - u32 emif_ddr_ext_phy_ctrl_23; - u32 emif_ddr_ext_phy_ctrl_23_shdw; - u32 emif_ddr_ext_phy_ctrl_24; - u32 emif_ddr_ext_phy_ctrl_24_shdw; + u32 emif_mod_id_rev; /* 0x000 */ + u32 emif_status; /* 0x004 */ + u32 emif_sdram_config; /* 0x008 */ + u32 emif_lpddr2_nvm_config; /* 0x00c */ + u32 emif_sdram_ref_ctrl; /* 0x010 */ + u32 emif_sdram_ref_ctrl_shdw; /* 0x014 */ + u32 emif_sdram_tim_1; /* 0x018 */ + u32 emif_sdram_tim_1_shdw; /* 0x01c */ + u32 emif_sdram_tim_2; /* 0x020 */ + u32 emif_sdram_tim_2_shdw; /* 0x024 */ + u32 emif_sdram_tim_3; /* 0x028 */ + u32 emif_sdram_tim_3_shdw; /* 0x02c */ + u32 emif_lpddr2_nvm_tim; /* 0x030 */ + u32 emif_lpddr2_nvm_tim_shdw; /* 0x034 */ + u32 emif_pwr_mgmt_ctrl; /* 0x038 */ + u32 emif_pwr_mgmt_ctrl_shdw; /* 0x03c */ + u32 emif_lpddr2_mode_reg_data; /* 0x040 */ + u32 padding1[1]; /* 0x044 */ + u32 emif_lpddr2_mode_reg_data_es2; /* 0x048 */ + u32 padding11[1]; /* 0x04c */ + u32 emif_lpddr2_mode_reg_cfg; /* 0x050 */ + u32 emif_l3_config; /* 0x054 */ + u32 emif_l3_cfg_val_1; /* 0x058 */ + u32 emif_l3_cfg_val_2; /* 0x05c */ + u32 emif_iodft_tlgc; /* 0x060 */ + u32 padding2[7]; /* 0x064 */ + u32 emif_perf_cnt_1; /* 0x080 */ + u32 emif_perf_cnt_2; /* 0x084 */ + u32 emif_perf_cnt_cfg; /* 0x088 */ + u32 emif_perf_cnt_sel; /* 0x08c */ + u32 emif_perf_cnt_tim; /* 0x090 */ + u32 padding3; /* 0x094 */ + u32 emif_read_idlectrl; /* 0x098 */ + u32 emif_read_idlectrl_shdw; /* 0x09c */ + u32 padding4; /* 0x0a0 */ + u32 emif_irqstatus_raw_sys; /* 0x0a4 */ + u32 emif_irqstatus_raw_ll; /* 0x0a8 */ + u32 emif_irqstatus_sys; /* 0x0ac */ + u32 emif_irqstatus_ll; /* 0x0b0 */ + u32 emif_irqenable_set_sys; /* 0x0b4 */ + u32 emif_irqenable_set_ll; /* 0x0b8 */ + u32 emif_irqenable_clr_sys; /* 0x0bc */ + u32 emif_irqenable_clr_ll; /* 0x0c0 */ + u32 padding5; /* 0x0c4 */ + u32 emif_zq_config; /* 0x0c8 */ + u32 emif_temp_alert_config; /* 0x0cc */ + u32 emif_l3_err_log; /* 0x0d0 */ + u32 emif_rd_wr_lvl_rmp_win; /* 0x0d4 */ + u32 emif_rd_wr_lvl_rmp_ctl; /* 0x0d8 */ + u32 emif_rd_wr_lvl_ctl; /* 0x0dc */ + u32 padding6[1]; /* 0x0e0 */ + u32 emif_ddr_phy_ctrl_1; /* 0x0e4 */ + u32 emif_ddr_phy_ctrl_1_shdw; /* 0x0e8 */ + u32 emif_ddr_phy_ctrl_2; /* 0x0ec */ + u32 padding7[12]; /* 0x0f0 */ + u32 emif_rd_wr_exec_thresh; /* 0x120 */ + u32 padding8[55]; /* 0x124 */ + u32 emif_ddr_ext_phy_ctrl_1; /* 0x200 */ + u32 emif_ddr_ext_phy_ctrl_1_shdw; /* 0x204 */ + u32 emif_ddr_ext_phy_ctrl_2; /* 0x248 */ + u32 emif_ddr_ext_phy_ctrl_2_shdw; /* 0x24c */ + u32 emif_ddr_ext_phy_ctrl_3; /* 0x200 */ + u32 emif_ddr_ext_phy_ctrl_3_shdw; /* 0x204 */ + u32 emif_ddr_ext_phy_ctrl_4; /* 0x208 */ + u32 emif_ddr_ext_phy_ctrl_4_shdw; /* 0x20c */ + u32 emif_ddr_ext_phy_ctrl_5; /* 0x210 */ + u32 emif_ddr_ext_phy_ctrl_5_shdw; /* 0x214 */ + u32 emif_ddr_ext_phy_ctrl_6; /* 0x218 */ + u32 emif_ddr_ext_phy_ctrl_6_shdw; /* 0x21c */ + u32 emif_ddr_ext_phy_ctrl_7; /* 0x220 */ + u32 emif_ddr_ext_phy_ctrl_7_shdw; /* 0x224 */ + u32 emif_ddr_ext_phy_ctrl_8; /* 0x228 */ + u32 emif_ddr_ext_phy_ctrl_8_shdw; /* 0x22c */ + u32 emif_ddr_ext_phy_ctrl_9; /* 0x230 */ + u32 emif_ddr_ext_phy_ctrl_9_shdw; /* 0x234 */ + u32 emif_ddr_ext_phy_ctrl_10; /* 0x238 */ + u32 emif_ddr_ext_phy_ctrl_10_shdw; /* 0x23c */ + u32 emif_ddr_ext_phy_ctrl_11; /* 0x240 */ + u32 emif_ddr_ext_phy_ctrl_11_shdw; /* 0x244 */ + u32 emif_ddr_ext_phy_ctrl_12; /* 0x248 */ + u32 emif_ddr_ext_phy_ctrl_12_shdw; /* 0x24c */ + u32 emif_ddr_ext_phy_ctrl_13; /* 0x250 */ + u32 emif_ddr_ext_phy_ctrl_13_shdw; /* 0x254 */ + u32 emif_ddr_ext_phy_ctrl_14; /* 0x258 */ + u32 emif_ddr_ext_phy_ctrl_14_shdw; /* 0x25c */ + u32 emif_ddr_ext_phy_ctrl_15; /* 0x260 */ + u32 emif_ddr_ext_phy_ctrl_15_shdw; /* 0x264 */ + u32 emif_ddr_ext_phy_ctrl_16; /* 0x268 */ + u32 emif_ddr_ext_phy_ctrl_16_shdw; /* 0x26c */ + u32 emif_ddr_ext_phy_ctrl_17; /* 0x270 */ + u32 emif_ddr_ext_phy_ctrl_17_shdw; /* 0x274 */ + u32 emif_ddr_ext_phy_ctrl_18; /* 0x278 */ + u32 emif_ddr_ext_phy_ctrl_18_shdw; /* 0x27c */ + u32 emif_ddr_ext_phy_ctrl_19; /* 0x280 */ + u32 emif_ddr_ext_phy_ctrl_19_shdw; /* 0x284 */ + u32 emif_ddr_ext_phy_ctrl_20; /* 0x288 */ + u32 emif_ddr_ext_phy_ctrl_20_shdw; /* 0x28c */ + u32 emif_ddr_ext_phy_ctrl_21; /* 0x290 */ + u32 emif_ddr_ext_phy_ctrl_21_shdw; /* 0x294 */ + u32 emif_ddr_ext_phy_ctrl_22; /* 0x298 */ + u32 emif_ddr_ext_phy_ctrl_22_shdw; /* 0x29c */ + u32 emif_ddr_ext_phy_ctrl_23; /* 0x2a0 */ + u32 emif_ddr_ext_phy_ctrl_23_shdw; /* 0x2a4 */ + u32 emif_ddr_ext_phy_ctrl_24; /* 0x2a8 */ + u32 emif_ddr_ext_phy_ctrl_24_shdw; /* 0x2ac */ }; struct dmm_lisa_map_regs { @@ -1141,9 +1141,9 @@ struct lpddr2_mr_regs { /* assert macros */ #if defined(DEBUG) -#define emif_assert(c) ({ if (!(c)) for (;;); }) +#define emif_assert(c) ({ if (!(c)) hang(); }) #else -#define emif_assert(c) ({ if (0) hang(); }) +#define emif_assert(c) (c) #endif #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 79a9597419..0649a4636d 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -17,6 +17,9 @@ struct arch_global_data { #if defined(CONFIG_FSL_ESDHC) u32 sdhc_clk; #endif +#ifdef CONFIG_VIDEO_IPUV3 + unsigned int ipu_hw_rev; +#endif #ifdef CONFIG_AT91FAMILY /* "static data" needed by at91's clock.c */ unsigned long cpu_clk_rate_hz; diff --git a/arch/arm/include/asm/imx-common/iomux-v3.h b/arch/arm/include/asm/imx-common/iomux-v3.h index dc2b3ef47a..5d0b83e742 100644 --- a/arch/arm/include/asm/imx-common/iomux-v3.h +++ b/arch/arm/include/asm/imx-common/iomux-v3.h @@ -8,8 +8,8 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef __MACH_IOMUX_V3_H__ -#define __MACH_IOMUX_V3_H__ +#ifndef __ASM_ARCH_IOMUX_V3_H__ +#define __ASM_ARCH_IOMUX_V3_H__ #include @@ -36,13 +36,13 @@ * * IOMUX/PAD Bit field definitions * - * MUX_CTRL_OFS: 0..11 (12) - * PAD_CTRL_OFS: 12..23 (12) - * SEL_INPUT_OFS: 24..35 (12) - * MUX_MODE + SION: 36..40 (5) - * PAD_CTRL + NO_PAD_CTRL: 41..58 (18) - * SEL_INP: 59..62 (4) - * reserved: 63 (1) + * MUX_CTRL_OFS: 0..11 (12) + * PAD_CTRL_OFS: 12..23 (12) + * SEL_INPUT_OFS: 24..35 (12) + * MUX_MODE + SION: 36..40 (5) + * PAD_CTRL + PAD_CTRL_VALID: 41..58 (18) + * SEL_INP: 59..61 (3) + * reserved: 62..63 (2) */ typedef u64 iomux_v3_cfg_t; @@ -59,11 +59,13 @@ typedef u64 iomux_v3_cfg_t; #define MUX_MODE_SHIFT 36 #define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT) #define MUX_PAD_CTRL_SHIFT 41 -#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x3ffff << MUX_PAD_CTRL_SHIFT) +#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x1ffff << MUX_PAD_CTRL_SHIFT) #define MUX_SEL_INPUT_SHIFT 59 -#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT) +#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0x7 << MUX_SEL_INPUT_SHIFT) -#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT) +#define __MUX_PAD_CTRL(x) ((x) | __PAD_CTRL_VALID) +#define MUX_PAD_CTRL(x) (((iomux_v3_cfg_t)__MUX_PAD_CTRL(x) << \ + MUX_PAD_CTRL_SHIFT)) #define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \ sel_input, pad_ctrl) \ @@ -81,76 +83,81 @@ typedef u64 iomux_v3_cfg_t; #define NO_MUX_I 0 #define NO_PAD_I 0 -#define NO_PAD_CTRL (1 << 17) +#define NO_MUX_I 0 +#define NO_PAD_I 0 + +#define NO_PAD_CTRL 0 +#define __PAD_CTRL_VALID (1 << 17) +#define PAD_CTRL_VALID ((iomux_v3_cfg_t)__PAD_CTRL_VALID << MUX_PAD_CTRL_SHIFT) #ifdef CONFIG_MX6 -#define PAD_CTL_HYS (1 << 16) +#define PAD_CTL_HYS __MUX_PAD_CTRL(1 << 16) -#define PAD_CTL_PUS_100K_DOWN (0 << 14 | PAD_CTL_PUE) -#define PAD_CTL_PUS_47K_UP (1 << 14 | PAD_CTL_PUE) -#define PAD_CTL_PUS_100K_UP (2 << 14 | PAD_CTL_PUE) -#define PAD_CTL_PUS_22K_UP (3 << 14 | PAD_CTL_PUE) -#define PAD_CTL_PUE (1 << 13 | PAD_CTL_PKE) -#define PAD_CTL_PKE (1 << 12) +#define PAD_CTL_PUS_100K_DOWN __MUX_PAD_CTRL(0 << 14 | PAD_CTL_PUE) +#define PAD_CTL_PUS_47K_UP __MUX_PAD_CTRL(1 << 14 | PAD_CTL_PUE) +#define PAD_CTL_PUS_100K_UP __MUX_PAD_CTRL(2 << 14 | PAD_CTL_PUE) +#define PAD_CTL_PUS_22K_UP __MUX_PAD_CTRL(3 << 14 | PAD_CTL_PUE) +#define PAD_CTL_PUE __MUX_PAD_CTRL(1 << 13 | PAD_CTL_PKE) +#define PAD_CTL_PKE __MUX_PAD_CTRL(1 << 12) -#define PAD_CTL_ODE (1 << 11) +#define PAD_CTL_ODE __MUX_PAD_CTRL(1 << 11) -#define PAD_CTL_SPEED_LOW (1 << 6) -#define PAD_CTL_SPEED_MED (2 << 6) -#define PAD_CTL_SPEED_HIGH (3 << 6) +#define PAD_CTL_SPEED_LOW __MUX_PAD_CTRL(1 << 6) +#define PAD_CTL_SPEED_MED __MUX_PAD_CTRL(2 << 6) +#define PAD_CTL_SPEED_HIGH __MUX_PAD_CTRL(3 << 6) -#define PAD_CTL_DSE_DISABLE (0 << 3) -#define PAD_CTL_DSE_240ohm (1 << 3) -#define PAD_CTL_DSE_120ohm (2 << 3) -#define PAD_CTL_DSE_80ohm (3 << 3) -#define PAD_CTL_DSE_60ohm (4 << 3) -#define PAD_CTL_DSE_48ohm (5 << 3) -#define PAD_CTL_DSE_40ohm (6 << 3) -#define PAD_CTL_DSE_34ohm (7 << 3) +#define PAD_CTL_DSE_DISABLE __MUX_PAD_CTRL(0 << 3) +#define PAD_CTL_DSE_240ohm __MUX_PAD_CTRL(1 << 3) +#define PAD_CTL_DSE_120ohm __MUX_PAD_CTRL(2 << 3) +#define PAD_CTL_DSE_80ohm __MUX_PAD_CTRL(3 << 3) +#define PAD_CTL_DSE_60ohm __MUX_PAD_CTRL(4 << 3) +#define PAD_CTL_DSE_48ohm __MUX_PAD_CTRL(5 << 3) +#define PAD_CTL_DSE_40ohm __MUX_PAD_CTRL(6 << 3) +#define PAD_CTL_DSE_34ohm __MUX_PAD_CTRL(7 << 3) #elif defined(CONFIG_VF610) #define PAD_MUX_MODE_SHIFT 20 -#define PAD_CTL_SPEED_MED (1 << 12) -#define PAD_CTL_SPEED_HIGH (3 << 12) +#define PAD_CTL_SPEED_MED __MUX_PAD_CTRL(1 << 12) +#define PAD_CTL_SPEED_HIGH __MUX_PAD_CTRL(3 << 12) -#define PAD_CTL_DSE_50ohm (3 << 6) -#define PAD_CTL_DSE_25ohm (6 << 6) -#define PAD_CTL_DSE_20ohm (7 << 6) +#define PAD_CTL_DSE_50ohm __MUX_PAD_CTRL(3 << 6) +#define PAD_CTL_DSE_25ohm __MUX_PAD_CTRL(6 << 6) +#define PAD_CTL_DSE_20ohm __MUX_PAD_CTRL(7 << 6) -#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) -#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) -#define PAD_CTL_PKE (1 << 3) -#define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE) +#define PAD_CTL_PUS_47K_UP __MUX_PAD_CTRL(1 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_100K_UP __MUX_PAD_CTRL(2 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PKE __MUX_PAD_CTRL(1 << 3) +#define PAD_CTL_PUE __MUX_PAD_CTRL(1 << 2 | PAD_CTL_PKE) -#define PAD_CTL_OBE_IBE_ENABLE (3 << 0) +#define PAD_CTL_OBE_IBE_ENABLE __MUX_PAD_CTRL(3 << 0) #else -#define PAD_CTL_DVS (1 << 13) -#define PAD_CTL_INPUT_DDR (1 << 9) -#define PAD_CTL_HYS (1 << 8) +#define PAD_CTL_DVS __MUX_PAD_CTRL(1 << 13) +#define PAD_CTL_INPUT_DDR __MUX_PAD_CTRL(1 << 9) +#define PAD_CTL_HYS __MUX_PAD_CTRL(1 << 8) -#define PAD_CTL_PKE (1 << 7) -#define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE) -#define PAD_CTL_PUS_100K_DOWN (0 << 4 | PAD_CTL_PUE) -#define PAD_CTL_PUS_47K_UP (1 << 4 | PAD_CTL_PUE) -#define PAD_CTL_PUS_100K_UP (2 << 4 | PAD_CTL_PUE) -#define PAD_CTL_PUS_22K_UP (3 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PKE __MUX_PAD_CTRL(1 << 7) +#define PAD_CTL_PUE __MUX_PAD_CTRL(1 << 6 | PAD_CTL_PKE) +#define PAD_CTL_PUS_100K_DOWN __MUX_PAD_CTRL(0 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_47K_UP __MUX_PAD_CTRL(1 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_100K_UP __MUX_PAD_CTRL(2 << 4 | PAD_CTL_PUE) +#define PAD_CTL_PUS_22K_UP __MUX_PAD_CTRL(3 << 4 | PAD_CTL_PUE) -#define PAD_CTL_ODE (1 << 3) +#define PAD_CTL_ODE __MUX_PAD_CTRL(1 << 3) -#define PAD_CTL_DSE_LOW (0 << 1) -#define PAD_CTL_DSE_MED (1 << 1) -#define PAD_CTL_DSE_HIGH (2 << 1) -#define PAD_CTL_DSE_MAX (3 << 1) +#define PAD_CTL_DSE_LOW __MUX_PAD_CTRL(0 << 1) +#define PAD_CTL_DSE_MED __MUX_PAD_CTRL(1 << 1) +#define PAD_CTL_DSE_HIGH __MUX_PAD_CTRL(2 << 1) +#define PAD_CTL_DSE_MAX __MUX_PAD_CTRL(3 << 1) #endif -#define PAD_CTL_SRE_SLOW (0 << 0) -#define PAD_CTL_SRE_FAST (1 << 0) +#define PAD_CTL_SRE_SLOW __MUX_PAD_CTRL(0 << 0) +#define PAD_CTL_SRE_FAST __MUX_PAD_CTRL(1 << 0) #define IOMUX_CONFIG_SION 0x10 @@ -168,4 +175,4 @@ void imx_iomux_v3_setup_pad(iomux_v3_cfg_t pad); void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, unsigned count); -#endif /* __MACH_IOMUX_V3_H__*/ +#endif /* __ASM_ARCH_IOMUX_V3_H__*/ diff --git a/arch/arm/include/asm/imx-common/regs-apbh.h b/arch/arm/include/asm/imx-common/regs-apbh.h index ca77436004..bcbde05df3 100644 --- a/arch/arm/include/asm/imx-common/regs-apbh.h +++ b/arch/arm/include/asm/imx-common/regs-apbh.h @@ -19,221 +19,221 @@ #if defined(CONFIG_MX23) struct mxs_apbh_regs { - mxs_reg_32(hw_apbh_ctrl0) - mxs_reg_32(hw_apbh_ctrl1) - mxs_reg_32(hw_apbh_ctrl2) - mxs_reg_32(hw_apbh_channel_ctrl) + mxs_reg_32(hw_apbh_ctrl0); + mxs_reg_32(hw_apbh_ctrl1); + mxs_reg_32(hw_apbh_ctrl2); + mxs_reg_32(hw_apbh_channel_ctrl); union { struct { - mxs_reg_32(hw_apbh_ch_curcmdar) - mxs_reg_32(hw_apbh_ch_nxtcmdar) - mxs_reg_32(hw_apbh_ch_cmd) - mxs_reg_32(hw_apbh_ch_bar) - mxs_reg_32(hw_apbh_ch_sema) - mxs_reg_32(hw_apbh_ch_debug1) - mxs_reg_32(hw_apbh_ch_debug2) + mxs_reg_32(hw_apbh_ch_curcmdar); + mxs_reg_32(hw_apbh_ch_nxtcmdar); + mxs_reg_32(hw_apbh_ch_cmd); + mxs_reg_32(hw_apbh_ch_bar); + mxs_reg_32(hw_apbh_ch_sema); + mxs_reg_32(hw_apbh_ch_debug1); + mxs_reg_32(hw_apbh_ch_debug2); } ch[8]; struct { - mxs_reg_32(hw_apbh_ch0_curcmdar) - mxs_reg_32(hw_apbh_ch0_nxtcmdar) - mxs_reg_32(hw_apbh_ch0_cmd) - mxs_reg_32(hw_apbh_ch0_bar) - mxs_reg_32(hw_apbh_ch0_sema) - mxs_reg_32(hw_apbh_ch0_debug1) - mxs_reg_32(hw_apbh_ch0_debug2) - mxs_reg_32(hw_apbh_ch1_curcmdar) - mxs_reg_32(hw_apbh_ch1_nxtcmdar) - mxs_reg_32(hw_apbh_ch1_cmd) - mxs_reg_32(hw_apbh_ch1_bar) - mxs_reg_32(hw_apbh_ch1_sema) - mxs_reg_32(hw_apbh_ch1_debug1) - mxs_reg_32(hw_apbh_ch1_debug2) - mxs_reg_32(hw_apbh_ch2_curcmdar) - mxs_reg_32(hw_apbh_ch2_nxtcmdar) - mxs_reg_32(hw_apbh_ch2_cmd) - mxs_reg_32(hw_apbh_ch2_bar) - mxs_reg_32(hw_apbh_ch2_sema) - mxs_reg_32(hw_apbh_ch2_debug1) - mxs_reg_32(hw_apbh_ch2_debug2) - mxs_reg_32(hw_apbh_ch3_curcmdar) - mxs_reg_32(hw_apbh_ch3_nxtcmdar) - mxs_reg_32(hw_apbh_ch3_cmd) - mxs_reg_32(hw_apbh_ch3_bar) - mxs_reg_32(hw_apbh_ch3_sema) - mxs_reg_32(hw_apbh_ch3_debug1) - mxs_reg_32(hw_apbh_ch3_debug2) - mxs_reg_32(hw_apbh_ch4_curcmdar) - mxs_reg_32(hw_apbh_ch4_nxtcmdar) - mxs_reg_32(hw_apbh_ch4_cmd) - mxs_reg_32(hw_apbh_ch4_bar) - mxs_reg_32(hw_apbh_ch4_sema) - mxs_reg_32(hw_apbh_ch4_debug1) - mxs_reg_32(hw_apbh_ch4_debug2) - mxs_reg_32(hw_apbh_ch5_curcmdar) - mxs_reg_32(hw_apbh_ch5_nxtcmdar) - mxs_reg_32(hw_apbh_ch5_cmd) - mxs_reg_32(hw_apbh_ch5_bar) - mxs_reg_32(hw_apbh_ch5_sema) - mxs_reg_32(hw_apbh_ch5_debug1) - mxs_reg_32(hw_apbh_ch5_debug2) - mxs_reg_32(hw_apbh_ch6_curcmdar) - mxs_reg_32(hw_apbh_ch6_nxtcmdar) - mxs_reg_32(hw_apbh_ch6_cmd) - mxs_reg_32(hw_apbh_ch6_bar) - mxs_reg_32(hw_apbh_ch6_sema) - mxs_reg_32(hw_apbh_ch6_debug1) - mxs_reg_32(hw_apbh_ch6_debug2) - mxs_reg_32(hw_apbh_ch7_curcmdar) - mxs_reg_32(hw_apbh_ch7_nxtcmdar) - mxs_reg_32(hw_apbh_ch7_cmd) - mxs_reg_32(hw_apbh_ch7_bar) - mxs_reg_32(hw_apbh_ch7_sema) - mxs_reg_32(hw_apbh_ch7_debug1) - mxs_reg_32(hw_apbh_ch7_debug2) + mxs_reg_32(hw_apbh_ch0_curcmdar); + mxs_reg_32(hw_apbh_ch0_nxtcmdar); + mxs_reg_32(hw_apbh_ch0_cmd); + mxs_reg_32(hw_apbh_ch0_bar); + mxs_reg_32(hw_apbh_ch0_sema); + mxs_reg_32(hw_apbh_ch0_debug1); + mxs_reg_32(hw_apbh_ch0_debug2); + mxs_reg_32(hw_apbh_ch1_curcmdar); + mxs_reg_32(hw_apbh_ch1_nxtcmdar); + mxs_reg_32(hw_apbh_ch1_cmd); + mxs_reg_32(hw_apbh_ch1_bar); + mxs_reg_32(hw_apbh_ch1_sema); + mxs_reg_32(hw_apbh_ch1_debug1); + mxs_reg_32(hw_apbh_ch1_debug2); + mxs_reg_32(hw_apbh_ch2_curcmdar); + mxs_reg_32(hw_apbh_ch2_nxtcmdar); + mxs_reg_32(hw_apbh_ch2_cmd); + mxs_reg_32(hw_apbh_ch2_bar); + mxs_reg_32(hw_apbh_ch2_sema); + mxs_reg_32(hw_apbh_ch2_debug1); + mxs_reg_32(hw_apbh_ch2_debug2); + mxs_reg_32(hw_apbh_ch3_curcmdar); + mxs_reg_32(hw_apbh_ch3_nxtcmdar); + mxs_reg_32(hw_apbh_ch3_cmd); + mxs_reg_32(hw_apbh_ch3_bar); + mxs_reg_32(hw_apbh_ch3_sema); + mxs_reg_32(hw_apbh_ch3_debug1); + mxs_reg_32(hw_apbh_ch3_debug2); + mxs_reg_32(hw_apbh_ch4_curcmdar); + mxs_reg_32(hw_apbh_ch4_nxtcmdar); + mxs_reg_32(hw_apbh_ch4_cmd); + mxs_reg_32(hw_apbh_ch4_bar); + mxs_reg_32(hw_apbh_ch4_sema); + mxs_reg_32(hw_apbh_ch4_debug1); + mxs_reg_32(hw_apbh_ch4_debug2); + mxs_reg_32(hw_apbh_ch5_curcmdar); + mxs_reg_32(hw_apbh_ch5_nxtcmdar); + mxs_reg_32(hw_apbh_ch5_cmd); + mxs_reg_32(hw_apbh_ch5_bar); + mxs_reg_32(hw_apbh_ch5_sema); + mxs_reg_32(hw_apbh_ch5_debug1); + mxs_reg_32(hw_apbh_ch5_debug2); + mxs_reg_32(hw_apbh_ch6_curcmdar); + mxs_reg_32(hw_apbh_ch6_nxtcmdar); + mxs_reg_32(hw_apbh_ch6_cmd); + mxs_reg_32(hw_apbh_ch6_bar); + mxs_reg_32(hw_apbh_ch6_sema); + mxs_reg_32(hw_apbh_ch6_debug1); + mxs_reg_32(hw_apbh_ch6_debug2); + mxs_reg_32(hw_apbh_ch7_curcmdar); + mxs_reg_32(hw_apbh_ch7_nxtcmdar); + mxs_reg_32(hw_apbh_ch7_cmd); + mxs_reg_32(hw_apbh_ch7_bar); + mxs_reg_32(hw_apbh_ch7_sema); + mxs_reg_32(hw_apbh_ch7_debug1); + mxs_reg_32(hw_apbh_ch7_debug2); }; }; - mxs_reg_32(hw_apbh_version) + mxs_reg_32(hw_apbh_version); }; #elif (defined(CONFIG_MX28) || defined(CONFIG_MX6)) struct mxs_apbh_regs { - mxs_reg_32(hw_apbh_ctrl0) - mxs_reg_32(hw_apbh_ctrl1) - mxs_reg_32(hw_apbh_ctrl2) - mxs_reg_32(hw_apbh_channel_ctrl) - mxs_reg_32(hw_apbh_devsel) - mxs_reg_32(hw_apbh_dma_burst_size) - mxs_reg_32(hw_apbh_debug) + mxs_reg_32(hw_apbh_ctrl0); /* 0x000 */ + mxs_reg_32(hw_apbh_ctrl1); /* 0x010 */ + mxs_reg_32(hw_apbh_ctrl2); /* 0x020 */ + mxs_reg_32(hw_apbh_channel_ctrl); /* 0x030 */ + mxs_reg_32(hw_apbh_devsel); /* 0x040 */ + mxs_reg_32(hw_apbh_dma_burst_size); /* 0x050 */ + mxs_reg_32(hw_apbh_debug); /* 0x060 */ - uint32_t reserved[36]; + reg_32(reserved[9]); /* 0x064-0x0fc */ union { struct { - mxs_reg_32(hw_apbh_ch_curcmdar) - mxs_reg_32(hw_apbh_ch_nxtcmdar) - mxs_reg_32(hw_apbh_ch_cmd) - mxs_reg_32(hw_apbh_ch_bar) - mxs_reg_32(hw_apbh_ch_sema) - mxs_reg_32(hw_apbh_ch_debug1) - mxs_reg_32(hw_apbh_ch_debug2) + mxs_reg_32(hw_apbh_ch_curcmdar); + mxs_reg_32(hw_apbh_ch_nxtcmdar); + mxs_reg_32(hw_apbh_ch_cmd); + mxs_reg_32(hw_apbh_ch_bar); + mxs_reg_32(hw_apbh_ch_sema); + mxs_reg_32(hw_apbh_ch_debug1); + mxs_reg_32(hw_apbh_ch_debug2); } ch[16]; struct { - mxs_reg_32(hw_apbh_ch0_curcmdar) - mxs_reg_32(hw_apbh_ch0_nxtcmdar) - mxs_reg_32(hw_apbh_ch0_cmd) - mxs_reg_32(hw_apbh_ch0_bar) - mxs_reg_32(hw_apbh_ch0_sema) - mxs_reg_32(hw_apbh_ch0_debug1) - mxs_reg_32(hw_apbh_ch0_debug2) - mxs_reg_32(hw_apbh_ch1_curcmdar) - mxs_reg_32(hw_apbh_ch1_nxtcmdar) - mxs_reg_32(hw_apbh_ch1_cmd) - mxs_reg_32(hw_apbh_ch1_bar) - mxs_reg_32(hw_apbh_ch1_sema) - mxs_reg_32(hw_apbh_ch1_debug1) - mxs_reg_32(hw_apbh_ch1_debug2) - mxs_reg_32(hw_apbh_ch2_curcmdar) - mxs_reg_32(hw_apbh_ch2_nxtcmdar) - mxs_reg_32(hw_apbh_ch2_cmd) - mxs_reg_32(hw_apbh_ch2_bar) - mxs_reg_32(hw_apbh_ch2_sema) - mxs_reg_32(hw_apbh_ch2_debug1) - mxs_reg_32(hw_apbh_ch2_debug2) - mxs_reg_32(hw_apbh_ch3_curcmdar) - mxs_reg_32(hw_apbh_ch3_nxtcmdar) - mxs_reg_32(hw_apbh_ch3_cmd) - mxs_reg_32(hw_apbh_ch3_bar) - mxs_reg_32(hw_apbh_ch3_sema) - mxs_reg_32(hw_apbh_ch3_debug1) - mxs_reg_32(hw_apbh_ch3_debug2) - mxs_reg_32(hw_apbh_ch4_curcmdar) - mxs_reg_32(hw_apbh_ch4_nxtcmdar) - mxs_reg_32(hw_apbh_ch4_cmd) - mxs_reg_32(hw_apbh_ch4_bar) - mxs_reg_32(hw_apbh_ch4_sema) - mxs_reg_32(hw_apbh_ch4_debug1) - mxs_reg_32(hw_apbh_ch4_debug2) - mxs_reg_32(hw_apbh_ch5_curcmdar) - mxs_reg_32(hw_apbh_ch5_nxtcmdar) - mxs_reg_32(hw_apbh_ch5_cmd) - mxs_reg_32(hw_apbh_ch5_bar) - mxs_reg_32(hw_apbh_ch5_sema) - mxs_reg_32(hw_apbh_ch5_debug1) - mxs_reg_32(hw_apbh_ch5_debug2) - mxs_reg_32(hw_apbh_ch6_curcmdar) - mxs_reg_32(hw_apbh_ch6_nxtcmdar) - mxs_reg_32(hw_apbh_ch6_cmd) - mxs_reg_32(hw_apbh_ch6_bar) - mxs_reg_32(hw_apbh_ch6_sema) - mxs_reg_32(hw_apbh_ch6_debug1) - mxs_reg_32(hw_apbh_ch6_debug2) - mxs_reg_32(hw_apbh_ch7_curcmdar) - mxs_reg_32(hw_apbh_ch7_nxtcmdar) - mxs_reg_32(hw_apbh_ch7_cmd) - mxs_reg_32(hw_apbh_ch7_bar) - mxs_reg_32(hw_apbh_ch7_sema) - mxs_reg_32(hw_apbh_ch7_debug1) - mxs_reg_32(hw_apbh_ch7_debug2) - mxs_reg_32(hw_apbh_ch8_curcmdar) - mxs_reg_32(hw_apbh_ch8_nxtcmdar) - mxs_reg_32(hw_apbh_ch8_cmd) - mxs_reg_32(hw_apbh_ch8_bar) - mxs_reg_32(hw_apbh_ch8_sema) - mxs_reg_32(hw_apbh_ch8_debug1) - mxs_reg_32(hw_apbh_ch8_debug2) - mxs_reg_32(hw_apbh_ch9_curcmdar) - mxs_reg_32(hw_apbh_ch9_nxtcmdar) - mxs_reg_32(hw_apbh_ch9_cmd) - mxs_reg_32(hw_apbh_ch9_bar) - mxs_reg_32(hw_apbh_ch9_sema) - mxs_reg_32(hw_apbh_ch9_debug1) - mxs_reg_32(hw_apbh_ch9_debug2) - mxs_reg_32(hw_apbh_ch10_curcmdar) - mxs_reg_32(hw_apbh_ch10_nxtcmdar) - mxs_reg_32(hw_apbh_ch10_cmd) - mxs_reg_32(hw_apbh_ch10_bar) - mxs_reg_32(hw_apbh_ch10_sema) - mxs_reg_32(hw_apbh_ch10_debug1) - mxs_reg_32(hw_apbh_ch10_debug2) - mxs_reg_32(hw_apbh_ch11_curcmdar) - mxs_reg_32(hw_apbh_ch11_nxtcmdar) - mxs_reg_32(hw_apbh_ch11_cmd) - mxs_reg_32(hw_apbh_ch11_bar) - mxs_reg_32(hw_apbh_ch11_sema) - mxs_reg_32(hw_apbh_ch11_debug1) - mxs_reg_32(hw_apbh_ch11_debug2) - mxs_reg_32(hw_apbh_ch12_curcmdar) - mxs_reg_32(hw_apbh_ch12_nxtcmdar) - mxs_reg_32(hw_apbh_ch12_cmd) - mxs_reg_32(hw_apbh_ch12_bar) - mxs_reg_32(hw_apbh_ch12_sema) - mxs_reg_32(hw_apbh_ch12_debug1) - mxs_reg_32(hw_apbh_ch12_debug2) - mxs_reg_32(hw_apbh_ch13_curcmdar) - mxs_reg_32(hw_apbh_ch13_nxtcmdar) - mxs_reg_32(hw_apbh_ch13_cmd) - mxs_reg_32(hw_apbh_ch13_bar) - mxs_reg_32(hw_apbh_ch13_sema) - mxs_reg_32(hw_apbh_ch13_debug1) - mxs_reg_32(hw_apbh_ch13_debug2) - mxs_reg_32(hw_apbh_ch14_curcmdar) - mxs_reg_32(hw_apbh_ch14_nxtcmdar) - mxs_reg_32(hw_apbh_ch14_cmd) - mxs_reg_32(hw_apbh_ch14_bar) - mxs_reg_32(hw_apbh_ch14_sema) - mxs_reg_32(hw_apbh_ch14_debug1) - mxs_reg_32(hw_apbh_ch14_debug2) - mxs_reg_32(hw_apbh_ch15_curcmdar) - mxs_reg_32(hw_apbh_ch15_nxtcmdar) - mxs_reg_32(hw_apbh_ch15_cmd) - mxs_reg_32(hw_apbh_ch15_bar) - mxs_reg_32(hw_apbh_ch15_sema) - mxs_reg_32(hw_apbh_ch15_debug1) - mxs_reg_32(hw_apbh_ch15_debug2) + mxs_reg_32(hw_apbh_ch0_curcmdar); + mxs_reg_32(hw_apbh_ch0_nxtcmdar); + mxs_reg_32(hw_apbh_ch0_cmd); + mxs_reg_32(hw_apbh_ch0_bar); + mxs_reg_32(hw_apbh_ch0_sema); + mxs_reg_32(hw_apbh_ch0_debug1); + mxs_reg_32(hw_apbh_ch0_debug2); + mxs_reg_32(hw_apbh_ch1_curcmdar); + mxs_reg_32(hw_apbh_ch1_nxtcmdar); + mxs_reg_32(hw_apbh_ch1_cmd); + mxs_reg_32(hw_apbh_ch1_bar); + mxs_reg_32(hw_apbh_ch1_sema); + mxs_reg_32(hw_apbh_ch1_debug1); + mxs_reg_32(hw_apbh_ch1_debug2); + mxs_reg_32(hw_apbh_ch2_curcmdar); + mxs_reg_32(hw_apbh_ch2_nxtcmdar); + mxs_reg_32(hw_apbh_ch2_cmd); + mxs_reg_32(hw_apbh_ch2_bar); + mxs_reg_32(hw_apbh_ch2_sema); + mxs_reg_32(hw_apbh_ch2_debug1); + mxs_reg_32(hw_apbh_ch2_debug2); + mxs_reg_32(hw_apbh_ch3_curcmdar); + mxs_reg_32(hw_apbh_ch3_nxtcmdar); + mxs_reg_32(hw_apbh_ch3_cmd); + mxs_reg_32(hw_apbh_ch3_bar); + mxs_reg_32(hw_apbh_ch3_sema); + mxs_reg_32(hw_apbh_ch3_debug1); + mxs_reg_32(hw_apbh_ch3_debug2); + mxs_reg_32(hw_apbh_ch4_curcmdar); + mxs_reg_32(hw_apbh_ch4_nxtcmdar); + mxs_reg_32(hw_apbh_ch4_cmd); + mxs_reg_32(hw_apbh_ch4_bar); + mxs_reg_32(hw_apbh_ch4_sema); + mxs_reg_32(hw_apbh_ch4_debug1); + mxs_reg_32(hw_apbh_ch4_debug2); + mxs_reg_32(hw_apbh_ch5_curcmdar); + mxs_reg_32(hw_apbh_ch5_nxtcmdar); + mxs_reg_32(hw_apbh_ch5_cmd); + mxs_reg_32(hw_apbh_ch5_bar); + mxs_reg_32(hw_apbh_ch5_sema); + mxs_reg_32(hw_apbh_ch5_debug1); + mxs_reg_32(hw_apbh_ch5_debug2); + mxs_reg_32(hw_apbh_ch6_curcmdar); + mxs_reg_32(hw_apbh_ch6_nxtcmdar); + mxs_reg_32(hw_apbh_ch6_cmd); + mxs_reg_32(hw_apbh_ch6_bar); + mxs_reg_32(hw_apbh_ch6_sema); + mxs_reg_32(hw_apbh_ch6_debug1); + mxs_reg_32(hw_apbh_ch6_debug2); + mxs_reg_32(hw_apbh_ch7_curcmdar); + mxs_reg_32(hw_apbh_ch7_nxtcmdar); + mxs_reg_32(hw_apbh_ch7_cmd); + mxs_reg_32(hw_apbh_ch7_bar); + mxs_reg_32(hw_apbh_ch7_sema); + mxs_reg_32(hw_apbh_ch7_debug1); + mxs_reg_32(hw_apbh_ch7_debug2); + mxs_reg_32(hw_apbh_ch8_curcmdar); + mxs_reg_32(hw_apbh_ch8_nxtcmdar); + mxs_reg_32(hw_apbh_ch8_cmd); + mxs_reg_32(hw_apbh_ch8_bar); + mxs_reg_32(hw_apbh_ch8_sema); + mxs_reg_32(hw_apbh_ch8_debug1); + mxs_reg_32(hw_apbh_ch8_debug2); + mxs_reg_32(hw_apbh_ch9_curcmdar); + mxs_reg_32(hw_apbh_ch9_nxtcmdar); + mxs_reg_32(hw_apbh_ch9_cmd); + mxs_reg_32(hw_apbh_ch9_bar); + mxs_reg_32(hw_apbh_ch9_sema); + mxs_reg_32(hw_apbh_ch9_debug1); + mxs_reg_32(hw_apbh_ch9_debug2); + mxs_reg_32(hw_apbh_ch10_curcmdar); + mxs_reg_32(hw_apbh_ch10_nxtcmdar); + mxs_reg_32(hw_apbh_ch10_cmd); + mxs_reg_32(hw_apbh_ch10_bar); + mxs_reg_32(hw_apbh_ch10_sema); + mxs_reg_32(hw_apbh_ch10_debug1); + mxs_reg_32(hw_apbh_ch10_debug2); + mxs_reg_32(hw_apbh_ch11_curcmdar); + mxs_reg_32(hw_apbh_ch11_nxtcmdar); + mxs_reg_32(hw_apbh_ch11_cmd); + mxs_reg_32(hw_apbh_ch11_bar); + mxs_reg_32(hw_apbh_ch11_sema); + mxs_reg_32(hw_apbh_ch11_debug1); + mxs_reg_32(hw_apbh_ch11_debug2); + mxs_reg_32(hw_apbh_ch12_curcmdar); + mxs_reg_32(hw_apbh_ch12_nxtcmdar); + mxs_reg_32(hw_apbh_ch12_cmd); + mxs_reg_32(hw_apbh_ch12_bar); + mxs_reg_32(hw_apbh_ch12_sema); + mxs_reg_32(hw_apbh_ch12_debug1); + mxs_reg_32(hw_apbh_ch12_debug2); + mxs_reg_32(hw_apbh_ch13_curcmdar); + mxs_reg_32(hw_apbh_ch13_nxtcmdar); + mxs_reg_32(hw_apbh_ch13_cmd); + mxs_reg_32(hw_apbh_ch13_bar); + mxs_reg_32(hw_apbh_ch13_sema); + mxs_reg_32(hw_apbh_ch13_debug1); + mxs_reg_32(hw_apbh_ch13_debug2); + mxs_reg_32(hw_apbh_ch14_curcmdar); + mxs_reg_32(hw_apbh_ch14_nxtcmdar); + mxs_reg_32(hw_apbh_ch14_cmd); + mxs_reg_32(hw_apbh_ch14_bar); + mxs_reg_32(hw_apbh_ch14_sema); + mxs_reg_32(hw_apbh_ch14_debug1); + mxs_reg_32(hw_apbh_ch14_debug2); + mxs_reg_32(hw_apbh_ch15_curcmdar); + mxs_reg_32(hw_apbh_ch15_nxtcmdar); + mxs_reg_32(hw_apbh_ch15_cmd); + mxs_reg_32(hw_apbh_ch15_bar); + mxs_reg_32(hw_apbh_ch15_sema); + mxs_reg_32(hw_apbh_ch15_debug1); + mxs_reg_32(hw_apbh_ch15_debug2); }; }; - mxs_reg_32(hw_apbh_version) + mxs_reg_32(hw_apbh_version); }; #endif diff --git a/arch/arm/include/asm/imx-common/regs-bch.h b/arch/arm/include/asm/imx-common/regs-bch.h index a33d3419b9..1ed5d94dd4 100644 --- a/arch/arm/include/asm/imx-common/regs-bch.h +++ b/arch/arm/include/asm/imx-common/regs-bch.h @@ -16,34 +16,36 @@ #include #ifndef __ASSEMBLY__ -struct mxs_bch_regs { - mxs_reg_32(hw_bch_ctrl) - mxs_reg_32(hw_bch_status0) - mxs_reg_32(hw_bch_mode) - mxs_reg_32(hw_bch_encodeptr) - mxs_reg_32(hw_bch_dataptr) - mxs_reg_32(hw_bch_metaptr) +struct bch_regs { + mxs_reg_32(hw_bch_ctrl); + mxs_reg_32(hw_bch_status0); + mxs_reg_32(hw_bch_mode); + mxs_reg_32(hw_bch_encodeptr); + mxs_reg_32(hw_bch_dataptr); + mxs_reg_32(hw_bch_metaptr); uint32_t reserved[4]; - mxs_reg_32(hw_bch_layoutselect) - mxs_reg_32(hw_bch_flash0layout0) - mxs_reg_32(hw_bch_flash0layout1) - mxs_reg_32(hw_bch_flash1layout0) - mxs_reg_32(hw_bch_flash1layout1) - mxs_reg_32(hw_bch_flash2layout0) - mxs_reg_32(hw_bch_flash2layout1) - mxs_reg_32(hw_bch_flash3layout0) - mxs_reg_32(hw_bch_flash3layout1) - mxs_reg_32(hw_bch_dbgkesread) - mxs_reg_32(hw_bch_dbgcsferead) - mxs_reg_32(hw_bch_dbgsyndegread) - mxs_reg_32(hw_bch_dbgahbmread) - mxs_reg_32(hw_bch_blockname) - mxs_reg_32(hw_bch_version) + mxs_reg_32(hw_bch_layoutselect); + mxs_reg_32(hw_bch_flash0layout0); + mxs_reg_32(hw_bch_flash0layout1); + mxs_reg_32(hw_bch_flash1layout0); + mxs_reg_32(hw_bch_flash1layout1); + mxs_reg_32(hw_bch_flash2layout0); + mxs_reg_32(hw_bch_flash2layout1); + mxs_reg_32(hw_bch_flash3layout0); + mxs_reg_32(hw_bch_flash3layout1); + mxs_reg_32(hw_bch_dbgkesread); + mxs_reg_32(hw_bch_dbgcsferead); + mxs_reg_32(hw_bch_dbgsyndegread); + mxs_reg_32(hw_bch_dbgahbmread); + mxs_reg_32(hw_bch_blockname); + mxs_reg_32(hw_bch_version); }; #endif +#define BCH_BASE_ADDRESS MXS_BCH_BASE + #define BCH_CTRL_SFTRST (1 << 31) #define BCH_CTRL_CLKGATE (1 << 30) #define BCH_CTRL_DEBUGSYNDROME (1 << 22) diff --git a/arch/arm/include/asm/imx-common/regs-common.h b/arch/arm/include/asm/imx-common/regs-common.h index e54a220fa3..6fdcc5987f 100644 --- a/arch/arm/include/asm/imx-common/regs-common.h +++ b/arch/arm/include/asm/imx-common/regs-common.h @@ -34,36 +34,48 @@ * */ +#ifndef __ASSEMBLY__ + +#include + #define __mxs_reg_8(name) \ uint8_t name[4]; \ uint8_t name##_set[4]; \ uint8_t name##_clr[4]; \ - uint8_t name##_tog[4]; \ + uint8_t name##_tog[4] #define __mxs_reg_32(name) \ uint32_t name; \ uint32_t name##_set; \ uint32_t name##_clr; \ - uint32_t name##_tog; + uint32_t name##_tog + +#define __reg_32(name) \ + uint32_t name; \ + uint32_t reserved_##name[3] struct mxs_register_8 { - __mxs_reg_8(reg) + __mxs_reg_8(reg); }; struct mxs_register_32 { - __mxs_reg_32(reg) + __mxs_reg_32(reg); }; -#define mxs_reg_8(name) \ +#define mxs_reg_8(name) \ union { \ - struct { __mxs_reg_8(name) }; \ + struct { __mxs_reg_8(name); }; \ struct mxs_register_8 name##_reg; \ - }; + } -#define mxs_reg_32(name) \ +#define mxs_reg_32(name); \ union { \ - struct { __mxs_reg_32(name) }; \ + struct { __mxs_reg_32(name); }; \ struct mxs_register_32 name##_reg; \ - }; + } + +#define reg_32(name) \ + struct { __reg_32(name); } +#endif #endif /* __MXS_REGS_COMMON_H__ */ diff --git a/arch/arm/include/asm/imx-common/regs-gpmi.h b/arch/arm/include/asm/imx-common/regs-gpmi.h index b93bfe55cb..642864f3cf 100644 --- a/arch/arm/include/asm/imx-common/regs-gpmi.h +++ b/arch/arm/include/asm/imx-common/regs-gpmi.h @@ -16,26 +16,28 @@ #include #ifndef __ASSEMBLY__ -struct mxs_gpmi_regs { - mxs_reg_32(hw_gpmi_ctrl0) - mxs_reg_32(hw_gpmi_compare) - mxs_reg_32(hw_gpmi_eccctrl) - mxs_reg_32(hw_gpmi_ecccount) - mxs_reg_32(hw_gpmi_payload) - mxs_reg_32(hw_gpmi_auxiliary) - mxs_reg_32(hw_gpmi_ctrl1) - mxs_reg_32(hw_gpmi_timing0) - mxs_reg_32(hw_gpmi_timing1) +struct gpmi_regs { + mxs_reg_32(hw_gpmi_ctrl0); + mxs_reg_32(hw_gpmi_compare); + mxs_reg_32(hw_gpmi_eccctrl); + mxs_reg_32(hw_gpmi_ecccount); + mxs_reg_32(hw_gpmi_payload); + mxs_reg_32(hw_gpmi_auxiliary); + mxs_reg_32(hw_gpmi_ctrl1); + mxs_reg_32(hw_gpmi_timing0); + mxs_reg_32(hw_gpmi_timing1); uint32_t reserved[4]; - mxs_reg_32(hw_gpmi_data) - mxs_reg_32(hw_gpmi_stat) - mxs_reg_32(hw_gpmi_debug) - mxs_reg_32(hw_gpmi_version) + mxs_reg_32(hw_gpmi_data); + mxs_reg_32(hw_gpmi_stat); + mxs_reg_32(hw_gpmi_debug); + mxs_reg_32(hw_gpmi_version); }; #endif +#define GPMI_BASE_ADDRESS MXS_GPMI_BASE + #define GPMI_CTRL0_SFTRST (1 << 31) #define GPMI_CTRL0_CLKGATE (1 << 30) #define GPMI_CTRL0_RUN (1 << 29) diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 760345f847..8b5b9f47b4 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -70,7 +70,7 @@ static inline unsigned int get_cr(void) { unsigned int val; - asm("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); + asm volatile("mrc p15, 0, %0, c1, c0, 0 @ get CR" : "=r" (val) : : "cc"); return val; } diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 4e78723ea9..a68adf97ab 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -20,8 +20,6 @@ GLSOBJS += _umodsi3.o GLCOBJS += div0.o -SOBJS-y += crt0.o - ifndef CONFIG_SPL_BUILD SOBJS-y += relocate.o ifndef CONFIG_SYS_GENERIC_BOARD @@ -32,10 +30,14 @@ COBJS-y += sections.o COBJS-$(CONFIG_OF_LIBFDT) += bootm-fdt.o COBJS-$(CONFIG_CMD_BOOTM) += bootm.o COBJS-$(CONFIG_SYS_L2_PL310) += cache-pl310.o +SOBJS-y += crt0.o SOBJS-$(CONFIG_USE_ARCH_MEMSET) += memset.o SOBJS-$(CONFIG_USE_ARCH_MEMCPY) += memcpy.o else COBJS-$(CONFIG_SPL_FRAMEWORK) += spl.o +ifndef CONFIG_SPL_NO_CPU_SUPPORT_CODE +SOBJS-y += crt0.o +endif endif COBJS-y += interrupts.o diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 8642010a17..f283248dfa 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -24,16 +24,6 @@ __weak void arm_init_domains(void) { } -static void cp_delay (void) -{ - volatile int i; - - /* copro seems to need some delay between reading and writing */ - for (i = 0; i < 100; i++) - nop(); - asm volatile("" : : : "memory"); -} - void set_section_dcache(int section, enum dcache_option option) { u32 *page_table = (u32 *)gd->arch.tlb_addr; @@ -99,18 +89,20 @@ static inline void mmu_setup(void) dram_bank_mmu_setup(i); } - /* Copy the page table address to cp15 */ - asm volatile("mcr p15, 0, %0, c2, c0, 0" - : : "r" (gd->arch.tlb_addr) : "memory"); - /* Set the access control to all-supervisor */ - asm volatile("mcr p15, 0, %0, c3, c0, 0" - : : "r" (~0)); + asm volatile( + /* Copy the page table address to cp15 */ + "mcr p15, 0, %0, c2, c0, 0\n" + /* Set the access control to all-supervisor */ + "mcr p15, 0, %1, c3, c0, 0\n" + : + : "r"(gd->arch.tlb_addr), "r"(~0) + : "memory" + ); arm_init_domains(); /* and enable the mmu */ reg = get_cr(); /* get control reg. */ - cp_delay(); set_cr(reg | CR_M); } @@ -128,7 +120,6 @@ static void cache_enable(uint32_t cache_bit) if ((cache_bit == CR_C) && !mmu_enabled()) mmu_setup(); reg = get_cr(); /* get control reg. */ - cp_delay(); set_cr(reg | cache_bit); } @@ -138,7 +129,6 @@ static void cache_disable(uint32_t cache_bit) uint32_t reg; reg = get_cr(); - cp_delay(); if (cache_bit == CR_C) { /* if cache isn;t enabled no need to disable */ @@ -148,7 +138,6 @@ static void cache_disable(uint32_t cache_bit) cache_bit |= CR_M; } reg = get_cr(); - cp_delay(); if (cache_bit == (CR_C | CR_M)) flush_dcache_all(); set_cr(reg & ~cache_bit); diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 6cc136aa3c..8105e25110 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -17,10 +17,12 @@ void __flush_cache(unsigned long start, unsigned long size) arm1136_cache_flush(); #endif #ifdef CONFIG_ARM926EJS - /* test and clean, page 2-23 of arm926ejs manual */ - asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); - /* disable write buffer as well (page 2-22) */ - asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); + asm( + /* test and clean, page 2-23 of arm926ejs manual */ + "0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" + /* flush write buffer as well (page 2-22) */ + "mcr p15, 0, %0, c7, c10, 4" : : "r"(0) : "memory" + ); #endif return; } diff --git a/arch/arm/lib/crt0.S b/arch/arm/lib/crt0.S index 960d12e732..7cfc52d6c2 100644 --- a/arch/arm/lib/crt0.S +++ b/arch/arm/lib/crt0.S @@ -62,9 +62,9 @@ ENTRY(_main) */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK) - ldr sp, =(CONFIG_SPL_STACK) + ldr sp, =CONFIG_SPL_STACK #else - ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) + ldr sp, =CONFIG_SYS_INIT_SP_ADDR #endif bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ sub sp, #GD_SIZE /* allocate one GD above SP */ diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c index 7a0358071c..3b057e3a3d 100644 --- a/arch/arm/lib/reset.c +++ b/arch/arm/lib/reset.c @@ -31,7 +31,5 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) disable_interrupts(); reset_cpu(0); - - /*NOTREACHED*/ - return 0; + hang(); } diff --git a/board/denx/m28evk/spl_boot.c b/board/denx/m28evk/spl_boot.c index 525ba6ae75..b7c09347bd 100644 --- a/board/denx/m28evk/spl_boot.c +++ b/board/denx/m28evk/spl_boot.c @@ -204,3 +204,53 @@ void board_init_ll(void) { mxs_common_spl_init(iomux_setup, ARRAY_SIZE(iomux_setup)); } + +static uint32_t dram_vals[] = { + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000100, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00010101, 0x01010101, 0x000f0f01, 0x0f02020a, + 0x00000000, 0x00010101, 0x00000100, 0x00000100, 0x00000000, + 0x00000002, 0x01010000, 0x05060302, 0x06005003, 0x0a0000c8, + 0x02009c40, 0x0000030c, 0x0036a609, 0x031a0612, 0x02030202, + 0x00c8001c, 0x00000000, 0x00000000, 0x00012100, 0xffff0303, + 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, 0x00012100, + 0xffff0303, 0x00000003, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000612, 0x01000F02, 0x06120612, 0x00000200, + 0x00020007, 0xf5014b27, 0xf5014b27, 0xf5014b27, 0xf5014b27, + 0x07000300, 0x07000300, 0x07000300, 0x07000300, 0x00000006, + 0x00000000, 0x00000000, 0x01000000, 0x01020408, 0x08040201, + 0x000f1133, 0x00000000, 0x00001f04, 0x00001f04, 0x00001f04, + 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x00000000, 0x00010000, 0x00020304, 0x00000004, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, 0x01010000, 0x01000000, 0x03030000, 0x00010303, + 0x01020202, 0x00000000, 0x02040303, 0x21002103, 0x00061200, + 0x06120612, 0x04320432, 0x04320432, 0x00040004, 0x00040004, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00010001 +}; + +void mx28_ddr2_setup(void) +{ + int i; + + serial_puts("\n"); + for (i = 0; i < ARRAY_SIZE(dram_vals); i++) + writel(dram_vals[i], MXS_DRAM_BASE + (4 * i)); +} diff --git a/board/freescale/mx6qarm2/mx6qarm2.c b/board/freescale/mx6qarm2/mx6qarm2.c index 05c938fcc9..4dae0231dc 100644 --- a/board/freescale/mx6qarm2/mx6qarm2.c +++ b/board/freescale/mx6qarm2/mx6qarm2.c @@ -53,7 +53,7 @@ iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_SD3_DAT5__USDHC3_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_CS0__GPIO_6_11 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_NANDF_CS0__GPIO_6_11, /* CD */ }; iomux_v3_cfg_t const usdhc4_pads[] = { diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 1cdf2cb097..d454d64dec 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -105,11 +105,11 @@ struct i2c_pads_info i2c_pad_info2 = { }; iomux_v3_cfg_t const i2c3_pads[] = { - MX6_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_A24__GPIO_5_4, }; iomux_v3_cfg_t const port_exp[] = { - MX6_PAD_SD2_DAT0__GPIO_1_15 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD2_DAT0__GPIO_1_15, }; static void setup_iomux_enet(void) @@ -129,7 +129,7 @@ iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_SD3_DAT6__USDHC3_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT7__USDHC3_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_GPIO_18__USDHC3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_CS2__GPIO_6_15 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS2__GPIO_6_15, }; static void setup_iomux_uart(void) diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c index 78451e6d06..02dc289e0e 100644 --- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c +++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c @@ -118,7 +118,7 @@ iomux_v3_cfg_t const usdhc3_pads[] = { MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD3_DAT5__GPIO_7_0 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_SD3_DAT5__GPIO_7_0, /* CD */ }; iomux_v3_cfg_t const usdhc4_pads[] = { @@ -128,7 +128,7 @@ iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_NANDF_D6__GPIO_2_6 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ + MX6_PAD_NANDF_D6__GPIO_2_6, /* CD */ }; iomux_v3_cfg_t const enet_pads1[] = { @@ -142,19 +142,19 @@ iomux_v3_cfg_t const enet_pads1[] = { MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), /* pin 35 - 1 (PHY_AD2) on reset */ - MX6_PAD_RGMII_RXC__GPIO_6_30 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RXC__GPIO_6_30, /* pin 32 - 1 - (MODE0) all */ - MX6_PAD_RGMII_RD0__GPIO_6_25 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD0__GPIO_6_25, /* pin 31 - 1 - (MODE1) all */ - MX6_PAD_RGMII_RD1__GPIO_6_27 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD1__GPIO_6_27, /* pin 28 - 1 - (MODE2) all */ - MX6_PAD_RGMII_RD2__GPIO_6_28 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD2__GPIO_6_28, /* pin 27 - 1 - (MODE3) all */ - MX6_PAD_RGMII_RD3__GPIO_6_29 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD3__GPIO_6_29, /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ - MX6_PAD_RGMII_RX_CTL__GPIO_6_24 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__GPIO_6_24, /* pin 42 PHY nRST */ - MX6_PAD_EIM_D23__GPIO_3_23 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D23__GPIO_3_23, }; iomux_v3_cfg_t const enet_pads2[] = { @@ -201,7 +201,7 @@ static void setup_iomux_enet(void) } iomux_v3_cfg_t const usb_pads[] = { - MX6_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_GPIO_17__GPIO_7_12, }; static void setup_iomux_uart(void) @@ -266,8 +266,8 @@ int board_mmc_init(bd_t *bis) case 1: imx_iomux_v3_setup_multiple_pads( usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); - break; - default: + break; + default: printf("Warning: you configured more USDHC controllers" "(%d) then supported by the board (%d)\n", index + 1, CONFIG_SYS_FSL_USDHC_NUM); @@ -380,11 +380,11 @@ int setup_sata(void) static iomux_v3_cfg_t const backlight_pads[] = { /* Backlight on RGB connector: J15 */ - MX6_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD1_DAT3__GPIO_1_21, #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21) /* Backlight on LVDS connector: J6 */ - MX6_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD1_CMD__GPIO_1_18, #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18) }; diff --git a/board/karo/common/Makefile b/board/karo/common/Makefile new file mode 100644 index 0000000000..ca8b0f6c36 --- /dev/null +++ b/board/karo/common/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2012 Lothar Waßmann +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License +# version 2 as published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +include $(TOPDIR)/config.mk + +ifneq ($(OBJTREE),$(SRCTREE)) +$(shell mkdir -p $(obj)board/$(VENDOR)/common) +endif + +LIB = $(obj)lib$(VENDOR).o + +ifeq ($(CONFIG_SPL_BUILD),) + COBJS-$(CONFIG_OF_BOARD_SETUP) += fdt.o + COBJS-$(CONFIG_SPLASH_SCREEN) += splashimage.o +endif + +COBJS := $(COBJS-y) +SOBJS := + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +all: $(LIB) + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/karo/common/fdt.c b/board/karo/common/fdt.c new file mode 100644 index 0000000000..06b56181c6 --- /dev/null +++ b/board/karo/common/fdt.c @@ -0,0 +1,539 @@ +/* + * (C) Copyright 2012 Lothar Waßmann + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * +*/ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "karo.h" + +#ifdef CONFIG_MAX_DTB_SIZE +#define MAX_DTB_SIZE CONFIG_MAX_DTB_SIZE +#else +#define MAX_DTB_SIZE SZ_64K +#endif + +DECLARE_GLOBAL_DATA_PTR; + +static void karo_set_fdtsize(void *fdt) +{ + char fdt_size[9]; + size_t fdtsize = getenv_ulong("fdtsize", 16, 0); + + if (fdtsize == fdt_totalsize(fdt)) { + return; + } + debug("FDT size changed from %u to %u\n", + fdtsize, fdt_totalsize(fdt)); + + snprintf(fdt_size, sizeof(fdt_size), "%08x", fdt_totalsize(fdt)); + setenv("fdtsize", fdt_size); +} + +void karo_fdt_move_fdt(void) +{ + void *fdt; + unsigned long fdt_addr = getenv_ulong("fdtaddr", 16, 0); + + if (working_fdt) { + debug("DTB already loaded\n"); + return; + } + + if (!fdt_addr) { + fdt_addr = CONFIG_SYS_FDT_ADDR; + printf("fdtaddr is not set; using default: %08lx\n", + fdt_addr); + } + + fdt = karo_fdt_load_dtb(); + if (fdt == NULL) { + fdt = (void *)gd->fdt_blob; + if (fdt == NULL) { + printf("Compiled in FDT not found\n"); + return; + } + debug("Checking FDT header @ %p\n", fdt); + if (fdt_check_header(fdt)) { + printf("ERROR: No valid DTB found at %p\n", fdt); + return; + } + printf("No DTB in flash; using default DTB\n"); + debug("Moving FDT from %p..%p to %08lx..%08lx\n", + fdt, fdt + fdt_totalsize(fdt) - 1, + fdt_addr, fdt_addr + fdt_totalsize(fdt) - 1); + memmove((void *)fdt_addr, fdt, fdt_totalsize(fdt)); + } + set_working_fdt_addr((void *)fdt_addr); + gd->fdt_blob = fdt; + karo_set_fdtsize(fdt); +} + +void karo_fdt_remove_node(void *blob, const char *node) +{ + int off = fdt_path_offset(blob, node); + int ret; + + debug("Removing node '%s' from DT\n", node); + + if (off < 0) { + printf("Could not find node '%s': %d\n", node, off); + } else { + ret = fdt_del_node(blob, off); + if (ret) + printf("Failed to remove node '%s': %d\n", + node, ret); + } + karo_set_fdtsize(blob); +} + +void karo_fdt_enable_node(void *blob, const char *node, int enable) +{ + int off = fdt_path_offset(blob, node); + + debug("%sabling node '%s'\n", enable ? "En" : "Dis", node); + if (off < 0) { + printf("Could not find node '%s': %d\n", node, off); + return; + } + fdt_set_node_status(blob, off, + enable ? FDT_STATUS_OKAY : FDT_STATUS_DISABLED, 0); + + karo_set_fdtsize(blob); +} + +static const char *karo_touchpanels[] = { + "ti,tsc2007", + "edt,edt-ft5x06", +#ifdef CONFIG_MX28 + "fsl,imx28-lradc", +#endif +}; + +static void fdt_del_tp_node(void *blob, const char *name) +{ + int offs = fdt_node_offset_by_compatible(blob, -1, name); + + if (offs < 0) { + debug("node '%s' not found: %d\n", name, offs); + return; + } + + debug("Removing node '%s' from DT\n", name); + fdt_del_node(blob, offs); +} + +void karo_fdt_fixup_touchpanel(void *blob) +{ + int i; + const char *model = getenv("touchpanel"); + + for (i = 0; i < ARRAY_SIZE(karo_touchpanels); i++) { + const char *tp = karo_touchpanels[i]; + + if (model != NULL && strcmp(model, tp) == 0) + continue; + + if (model != NULL) { + if (strcmp(model, tp) == 0) + continue; + tp = strchr(tp, ','); + if (tp != NULL && *tp != '\0' && strcmp(model, tp + 1) == 0) + continue; + } + fdt_del_tp_node(blob, karo_touchpanels[i]); + karo_set_fdtsize(blob); + } +} + +void karo_fdt_fixup_usb_otg(void *blob, const char *node, const char *phy) +{ + const char *otg_mode = getenv("otg_mode"); + int off; + int ret; + const uint32_t *ph; + + debug("OTG mode is '%s'\n", otg_mode ? otg_mode : ""); + + off = fdt_path_offset(blob, node); + if (off < 0) { + debug("Failed to find node %s\n", node); + return; + } + + if (otg_mode && (strcmp(otg_mode, "device") == 0 || + strcmp(otg_mode, "gadget") == 0)) { + ret = fdt_setprop_string(blob, off, "dr_mode", "peripheral"); + phy = NULL; + } else if (otg_mode && strcmp(otg_mode, "host") == 0) { + ret = fdt_setprop_string(blob, off, "dr_mode", "host"); + phy = NULL; + } else { + if (otg_mode && strcmp(otg_mode, "none") != 0) + printf("Invalid 'otg_mode' setting '%s'; disabling usbotg port\n", + otg_mode); + ret = fdt_setprop_string(blob, off, "status", "disabled"); + } + if (ret) + goto out; + + if (phy == NULL) + goto out; + + ph = fdt_getprop(blob, off, phy, NULL); + if (ph == NULL) { + printf("Failed to find '%s' phandle in node '%s'\n", phy, + fdt_get_name(blob, off, NULL)); + goto out; + } + + off = fdt_node_offset_by_phandle(blob, fdt32_to_cpu(*ph)); + if (off <= 0) { + printf("Failed to find '%s' node via phandle %04x\n", + phy, fdt32_to_cpu(*ph)); + goto out; + } + ret = fdt_setprop_string(blob, off, "status", "disabled"); + +out: + if (ret) + printf("Failed to update usbotg: %d\n", ret); + printf("node '%s' updated\n", node); + karo_set_fdtsize(blob); +} + +void karo_fdt_del_prop(void *blob, const char *compat, phys_addr_t offs, + const char *prop) +{ + int ret; + int offset; + const uint32_t *phandle; + uint32_t ph = 0; + + offset = fdt_node_offset_by_compat_reg(blob, compat, offs); + if (offset <= 0) + return; + + phandle = fdt_getprop(blob, offset, prop, NULL); + if (phandle) { + ph = fdt32_to_cpu(*phandle); + } + + debug("Removing property '%s' from node %s@%08lx\n", prop, compat, offs); + ret = fdt_delprop(blob, offset, prop); + if (ret == 0) + karo_set_fdtsize(blob); + + if (!ph) + return; + + offset = fdt_node_offset_by_phandle(blob, ph); + if (offset <= 0) + return; + + debug("Removing node @ %08x\n", offset); + fdt_del_node(blob, offset); + karo_set_fdtsize(blob); +} + +static int fdt_init_fb_mode(const void *blob, int off, struct fb_videomode *fb_mode) +{ + const uint32_t *prop; + + memset(fb_mode, 0, sizeof(*fb_mode)); + + prop = fdt_getprop(blob, off, "clock-frequency", NULL); + if (prop) + fb_mode->pixclock = KHZ2PICOS(fdt32_to_cpu(*prop) / 1000); + + prop = fdt_getprop(blob, off, "hactive", NULL); + if (prop) + fb_mode->xres = fdt32_to_cpu(*prop); + + prop = fdt_getprop(blob, off, "vactive", NULL); + if (prop) + fb_mode->yres = fdt32_to_cpu(*prop); + + prop = fdt_getprop(blob, off, "hback-porch", NULL); + if (prop) + fb_mode->left_margin = fdt32_to_cpu(*prop); + + prop = fdt_getprop(blob, off, "hsync-len", NULL); + if (prop) + fb_mode->hsync_len = fdt32_to_cpu(*prop); + + prop = fdt_getprop(blob, off, "hfront-porch", NULL); + if (prop) + fb_mode->right_margin = fdt32_to_cpu(*prop); + + prop = fdt_getprop(blob, off, "vback-porch", NULL); + if (prop) + fb_mode->upper_margin = fdt32_to_cpu(*prop); + + prop = fdt_getprop(blob, off, "vsync-len", NULL); + if (prop) + fb_mode->vsync_len = fdt32_to_cpu(*prop); + + prop = fdt_getprop(blob, off, "vfront-porch", NULL); + if (prop) + fb_mode->lower_margin = fdt32_to_cpu(*prop); + + prop = fdt_getprop(blob, off, "hsync-active", NULL); + if (prop) + fb_mode->sync |= *prop ? FB_SYNC_VERT_HIGH_ACT : 0; + + prop = fdt_getprop(blob, off, "vsync-active", NULL); + if (prop) + fb_mode->sync |= *prop ? FB_SYNC_VERT_HIGH_ACT : 0; +#if 0 + prop = fdt_getprop(blob, off, "de-active", NULL); + if (prop) + fb_mode->sync |= *prop ? FB_SYNC_DATA_ENABLE_HIGH_ACT : 0; + + prop = fdt_getprop(blob, off, "pixelclk-active", NULL); + if (prop) + fb_mode->sync |= *prop ? FB_SYNC_DOTCLK_FALLING_ACT : 0; +#endif + return 0; +} + +static int fdt_update_native_fb_mode(void *blob, int off) +{ + int ret; + uint32_t ph; + int i; + + for (i = 1; i < 16; i++) { + fdt_set_totalsize(blob, fdt_totalsize(blob) + 8 * 4); + karo_set_fdtsize(blob); + ph = fdt_create_phandle(blob, off); + if (ph) + break; + } + if (ph == 0) { + printf("Failed to create phandle for video timing\n"); + return -ENOMEM; + } + + debug("phandle of %s @ %06x=%04x\n", fdt_get_name(blob, off, NULL), + off, ph); + off = fdt_parent_offset(blob, off); + if (off < 0) + return off; + debug("parent offset=%06x\n", off); + ret = fdt_setprop_cell(blob, off, "native-mode", ph); + return ret; +} + +static int karo_fdt_find_video_timings(void *blob) +{ + int off = fdt_path_offset(blob, "display"); + const char *subnode = "display-timings"; + + if (off < 0) { + debug("Could not find node 'display' in FDT: %d\n", off); + return off; + } + + off = fdt_subnode_offset(blob, off, subnode); + if (off < 0) { + debug("Could not find node '%s' in FDT: %d\n", subnode, off); + } + return off; +} + +int karo_fdt_get_fb_mode(void *blob, const char *name, struct fb_videomode *fb_mode) +{ + int off = karo_fdt_find_video_timings(blob); + + if (off < 0) + return off; + do { + const char *n, *endp; + int len, d = 1; + + off = fdt_next_node(blob, off, &d); + if (d > 2) { + debug("Skipping node @ %04x %s depth %d\n", off, fdt_get_name(blob, off, NULL), d); + continue; + } + debug("parsing subnode @ %04x %s depth %d\n", off, fdt_get_name(blob, off, NULL), d); + if (off < 0 || d < 1) + break; + + n = fdt_getprop(blob, off, "panel-name", &len); + if (!n) { + printf("Missing 'panel-name' property in node '%s'\n", + fdt_get_name(blob, off, NULL)); + continue; + } + for (endp = n + len; n < endp; n += strlen(n) + 1) { + debug("Checking panel-name '%s'\n", n); + if (strcasecmp(n, name) == 0) { + fdt_init_fb_mode(blob, off, fb_mode); + return fdt_update_native_fb_mode(blob, off); + } + } + } while (off > 0); + return -EINVAL; +} + +int karo_fdt_update_fb_mode(void *blob, const char *name) +{ + int off = fdt_path_offset(blob, "display"); + const char *subnode = "display-timings"; + + if (off < 0) + return off; + + if (name == NULL) { + int parent = fdt_parent_offset(blob, off); + int ret; + + if (parent < 0) { + printf("Failed to find parent of node '%s'\n", + fdt_get_name(blob, off, NULL)); + return parent; + } + debug("parent offset=%06x\n", parent); + ret = fdt_setprop_string(blob, parent, "status", "disabled"); + return ret; + } + + off = fdt_subnode_offset(blob, off, subnode); + if (off < 0) { + debug("Could not find node '%s' in FDT: %d\n", subnode, off); + } + do { + const char *n, *endp; + int len, d = 1; + int node = fdt_next_node(blob, off, &d); + int do_del; + + if (d > 2) { + debug("Skipping node @ %04x %s depth %d\n", node, fdt_get_name(blob, node, NULL), d); + continue; + } + debug("parsing subnode @ %04x %s depth %d\n", node, fdt_get_name(blob, node, NULL), d); + if (node < 0 || d < 1) + break; + + n = fdt_getprop(blob, node, "panel-name", &len); + if (!n) { + printf("Missing 'panel-name' property in node '%s'\n", + fdt_get_name(blob, node, NULL)); + continue; + } + do_del = 1; + for (endp = n + len; n < endp; n += strlen(n) + 1) { + debug("Checking panel-name '%s'\n", n); + if (strcasecmp(n, name) == 0) { + debug("Keeping node %s @ %04x\n", + fdt_get_name(blob, node, NULL), node); + off = node; + do_del = 0; + break; + } + } + if (do_del) { + debug("Deleting node %s @ %04x\n", + fdt_get_name(blob, node, NULL), node); + fdt_del_node(blob, node); + } + + } while (off > 0); + + return 0; +} + +static int karo_load_part(const char *part, void *addr, size_t len) +{ + int ret; + struct mtd_device *dev; + struct part_info *part_info; + u8 part_num; + size_t actual; + + debug("Initializing mtd_parts\n"); + ret = mtdparts_init(); + if (ret) + return ret; + + debug("Trying to find NAND partition '%s'\n", part); + ret = find_dev_and_part(part, &dev, &part_num, + &part_info); + if (ret) { + printf("Failed to find flash partition '%s': %d\n", + part, ret); + + return ret; + } + debug("Found partition '%s': offset=%08x size=%08x\n", + part, part_info->offset, part_info->size); + if (part_info->size < len) { + printf("Warning: partition '%s' smaller than requested size: %u; truncating data to %u byte\n", + part, len, part_info->size); + len = part_info->size; + } + debug("Reading NAND partition '%s' to %p\n", part, addr); + ret = nand_read_skip_bad(&nand_info[0], part_info->offset, &len, + &actual, len, addr); + if (ret) { + printf("Failed to load partition '%s' to %p\n", part, addr); + return ret; + } + if (actual < len) + printf("Read only %u of %u bytes due to bad blocks\n", + actual, len); + + debug("Read %u byte from partition '%s' @ offset %08x\n", + len, part, part_info->offset); + return 0; +} + +void *karo_fdt_load_dtb(void) +{ + int ret; + void *fdt = (void *)getenv_ulong("fdtaddr", 16, CONFIG_SYS_FDT_ADDR); + + if (tstc()) { + debug("aborting DTB load\n"); + return NULL; + } + + /* clear FDT header in memory */ + memset(fdt, 0, 4); + + ret = karo_load_part("dtb", fdt, MAX_DTB_SIZE); + if (ret) { + printf("Failed to load dtb from flash: %d\n", ret); + return NULL; + } + + if (fdt_check_header(fdt)) { + debug("No valid DTB in flash\n"); + return NULL; + } + debug("Using DTB from flash\n"); + karo_set_fdtsize(fdt); + return fdt; +} diff --git a/board/karo/common/karo.h b/board/karo/common/karo.h new file mode 100644 index 0000000000..142aaaa69c --- /dev/null +++ b/board/karo/common/karo.h @@ -0,0 +1,68 @@ +/* + * (C) Copyright 2012 Lothar Waßmann + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * +*/ +struct fb_videomode; + +#ifdef CONFIG_OF_LIBFDT +void karo_fdt_remove_node(void *blob, const char *node); +void karo_fdt_move_fdt(void); +void karo_fdt_fixup_touchpanel(void *blob); +void karo_fdt_fixup_usb_otg(void *blob, const char *node, const char *phy); +void karo_fdt_del_prop(void *blob, const char *compat, phys_addr_t offs, + const char *prop); +void karo_fdt_enable_node(void *blob, const char *node, int enable); +void *karo_fdt_load_dtb(void); +int karo_fdt_get_fb_mode(void *blob, const char *name, + struct fb_videomode *fb_mode); +int karo_fdt_update_fb_mode(void *blob, const char *name); +#else +static inline void karo_fdt_remove_node(void *blob, const char *node) +{ +} +static inline void karo_fdt_move_fdt(void) +{ +} +static inline void karo_fdt_fixup_touchpanel(void *blob) +{ +} +static inline void karo_fdt_fixup_usb_otg(void *blob, const char *node, + const char *phy) +{ +} +static inline void karo_fdt_del_prop(void *blob, const char *compat, + phys_addr_t offs, const char *prop) +{ +} +static inline void karo_fdt_enable_node(void *blob, const char *node, + int enable) +{ +} +static inline void *karo_fdt_load_dtb(void) +{ + return NULL; +} +static inline int karo_fdt_get_fb_mode(void *blob, const char *name, + struct fb_videomode *fb_mode) +{ + return 0; +} +static inline int karo_fdt_update_fb_mode(void *blob, const char *name) +{ + return 0; +} +#endif + +int karo_load_splashimage(int mode); diff --git a/board/karo/common/splashimage.c b/board/karo/common/splashimage.c new file mode 100644 index 0000000000..bd1b64c8aa --- /dev/null +++ b/board/karo/common/splashimage.c @@ -0,0 +1,192 @@ +/* + * (C) Copyright 2012 Lothar Waßmann + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +static int karo_load_part(const char *part, void *addr, size_t len) +{ + int ret; + struct mtd_device *dev; + struct part_info *part_info; + u8 part_num; + size_t actual; + + debug("Initializing mtd_parts\n"); + ret = mtdparts_init(); + if (ret) + return ret; + + debug("Trying to find NAND partition '%s'\n", part); + ret = find_dev_and_part(part, &dev, &part_num, + &part_info); + if (ret) { + printf("Failed to find flash partition '%s': %d\n", + part, ret); + + return ret; + } + debug("Found partition '%s': offset=%08x size=%08x\n", + part, part_info->offset, part_info->size); + if (part_info->size < len) { + printf("Warning: partition '%s' smaller than requested size: %u; truncating data to %u byte\n", + part, len, part_info->size); + len = part_info->size; + } + debug("Reading NAND partition '%s' to %p\n", part, addr); + ret = nand_read_skip_bad(&nand_info[0], part_info->offset, &len, + &actual, len, addr); + if (ret) { + printf("Failed to load partition '%s' to %p\n", part, addr); + return ret; + } + if (actual < len) + printf("Read only %u of %u bytes due to bad blocks\n", + actual, len); + + debug("Read %u byte from partition '%s' @ offset %08x\n", + len, part, part_info->offset); + return 0; +} + +static ulong calc_fbsize(void) +{ + return panel_info.vl_row * panel_info.vl_col * + NBITS(panel_info.vl_bpix) / 8; +} + +int karo_load_splashimage(int mode) +{ + int ret; + int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]); + unsigned long la = gd->fb_base; + char *splashimage = getenv("splashimage"); + ulong fbsize = calc_fbsize(); + char *end; + + if (!la || !splashimage) + return 0; + + if ((simple_strtoul(splashimage, &end, 16) != 0) && + *end == '\0') { + if (mode) + return 0; + la = simple_strtoul(splashimage, NULL, 16); + splashimage = "logo.bmp"; + } else if (!mode) { + return 0; + } + + if (tstc()) + return -ENODEV; + + ret = karo_load_part(splashimage, (void *)la, fbsize); + if (ret) { + printf("Failed to load logo from '%s': %d\n", splashimage, ret); + return ret; + } + return 0; +} + +static int erase_flash(loff_t offs, size_t len) +{ + nand_erase_options_t nand_erase_options; + + memset(&nand_erase_options, 0, sizeof(nand_erase_options)); + nand_erase_options.length = len; + nand_erase_options.offset = offs; + + return nand_erase_opts(&nand_info[0], &nand_erase_options); +} + +int do_fbdump(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + int ret; + size_t fbsize = calc_fbsize(); + const char *part = "logo"; + struct mtd_device *dev; + struct part_info *part_info; + u8 part_num; + u_char *addr = (u_char *)gd->fb_base; + size_t actual; + + if (argc > 2) + return CMD_RET_USAGE; + + if (argc == 2) + part = argv[1]; + + if (!addr) { + printf("fb address unknown\n"); + return CMD_RET_FAILURE; + } + + debug("Initializing mtd_parts\n"); + ret = mtdparts_init(); + if (ret) + return ret; + + debug("Trying to find NAND partition '%s'\n", part); + ret = find_dev_and_part(part, &dev, &part_num, + &part_info); + if (ret) { + printf("Failed to find flash partition '%s': %d\n", + part, ret); + + return ret; + } + debug("Found partition '%s': offset=%08x size=%08x\n", + part, part_info->offset, part_info->size); + if (part_info->size < fbsize) { + printf("Error: partition '%s' smaller than frame buffer size: %u\n", + part, fbsize); + return CMD_RET_FAILURE; + } + debug("Writing framebuffer %p to NAND partition '%s'\n", + addr, part); + + ret = erase_flash(part_info->offset, fbsize); + if (ret) { + printf("Failed to erase partition '%s'\n", part); + return CMD_RET_FAILURE; + } + + ret = nand_write_skip_bad(&nand_info[0], part_info->offset, + &fbsize, &actual, part_info->size, + addr, WITH_DROP_FFS); + if (ret) { + printf("Failed to write partition '%s'\n", part); + return ret; + } + if (actual < fbsize) + printf("Wrote only %u of %u bytes due to bad blocks\n", + actual, fbsize); + + debug("Wrote %u byte from %p to partition '%s' @ offset %08x\n", + fbsize, addr, part, part_info->offset); + + return CMD_RET_SUCCESS; +} + +U_BOOT_CMD(fbdump, 2, 0, do_fbdump, "dump framebuffer contents to flash", + "[partition name]\n" + " default partition name: 'logo'\n"); diff --git a/board/karo/dts/tx28.dts b/board/karo/dts/tx28.dts new file mode 100644 index 0000000000..b10de03064 --- /dev/null +++ b/board/karo/dts/tx28.dts @@ -0,0 +1,377 @@ +/* + * Copyright 2012 + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "mx28.dtsi" + +/ { + model = "Ka-Ro electronics TX28 module"; + compatible = "karo,tx28", "fsl,imx28"; + + aliases { + usbphy0 = &usbphy0; + usbphy1 = &usbphy1; + usbotg = &usb0; + usbh1 = &usb1; + can1 = &can1; + ethernet0 = &mac0; + ethernet1 = &mac1; + ds1339 = &ds1339; + pca9554 = &pca9554; + stk5led = &stk5_led; + }; + + memory { + reg = <0 0>; + }; + + apb@80000000 { + apbh@80000000 { + ssp0: ssp@80010000 { + compatible = "fsl,imx28-mmc"; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_4bit_pins_a + &mmc0_cd_cfg + &mmc0_sck_cfg>; + bus-width = <4>; + status = "okay"; + }; + + pinctrl@80018000 { + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_a>; + + hog_pins_a: hog-gpios@1 { + reg = <0>; + fsl,pinmux-ids = < + 0x31b3 /* MX28_PAD_SPDIF__GPIO_3_27 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + hog_pins_stk_v3_led: hog-gpios@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x40a3 /* MX28_PAD_ENET0_RXD3__GPIO_4_10 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + mac0_pins_gpio: mac0-gpio-mode@0 { + reg = <0>; + fsl,pinmux-ids = < + 0x4003 /* MX28_PAD_ENET0_MDC__GPIO_4_0 */ + 0x4013 /* MX28_PAD_ENET0_MDIO__GPIO_4_1 */ + 0x4023 /* MX28_PAD_ENET0_RX_EN__GPIO_4_2 */ + 0x4033 /* MX28_PAD_ENET0_RXD0__GPIO_4_3 */ + 0x4043 /* MX28_PAD_ENET0_RXD1__GPIO_4_4 */ + 0x4063 /* MX28_PAD_ENET0_TX_EN__GPIO_4_6 */ + 0x4073 /* MX28_PAD_ENET0_TXD0__GPIO_4_7 */ + 0x4083 /* MX28_PAD_ENET0_TXD1__GPIO_4_8 */ + 0x4103 /* MX28_PAD_ENET_CLK__GPIO_4_16 */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + + lcdif_pins_tx28: lcdif-tx28@0 { + fsl,pinmux-ids = < + 0x1181 /* MX28_PAD_LCD_RD_E__LCD_VSYNC */ + 0x1191 /* MX28_PAD_LCD_WR_RWN__LCD_HSYNC */ + 0x11a1 /* MX28_PAD_LCD_RS__LCD_DOTCLK */ + 0x11b1 /* MX28_PAD_LCD_CS__LCD_ENABLE */ + >; + fsl,drive-strength = <0>; + fsl,voltage = <1>; + fsl,pull-up = <0>; + }; + }; + + lcdif@80030000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&lcdif_24bit_pins_a + &lcdif_pins_tx28>; + }; + + can0: can@80032000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&can0_pins_a>; + transceiver-switch = <&flexcan_transceiver>; + }; + + can1: can@80034000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&can1_pins_a>; + transceiver-switch = <&flexcan_transceiver>; + }; + }; + + apbx@80040000 { + saif0: saif@80042000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&saif0_pins_a>; + }; + + saif1: saif@80046000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&saif1_pins_a>; + fsl,saif-master = <&saif0>; + }; + + lradc@80050000 { + status = "okay"; + }; + + i2c0: i2c@80058000 { + status = "okay"; + + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins_a>; + + ds1339: rtc@68 { + compatible = "maxim,ds1339"; + reg = <0x68>; + }; + + pca9554: pca953x@20 { + compatible = "nxp,pca953x"; + reg = <0x20>; + interrupt-parent = <&gpio3>; + interrupts = <20>; + }; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + touchscreen: tsc2007@48 { + compatible = "ti,tsc2007"; + reg = <0x48>; + interrupt-parent = <&gpio3>; + interrupts = <20 0>; + pendown-gpio = <&gpio3 20 1>; + model = "2007"; + x-plate-ohms = <660>; + }; + + polytouch: edt-ft5x06@ { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio2>; + interrupts = <5>; + reset-switch = <&edt_ft5x06_reset>; + wake-switch = <&edt_ft5x06_wake>; + }; + }; + + pwm: pwm@80064000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins_a>; + }; + + auart1: serial@8006c000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&auart1_pins_a>; + }; + + auart3: serial@80070000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&auart3_pins_a>; + }; + + duart: serial@80074000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&duart_4pins_a>; + }; + + usbphy0: usbphy@8007c000 { + status = "okay"; + }; + + usbphy1: usbphy@8007e000 { + status = "okay"; + }; + }; + }; + + ahb@80080000 { + usb0: usb@80080000 { + status = "okay"; + + vbus-supply = <®_usb0_vbus>; + pinctrl-names = "default"; + }; + + usb1: usb@80090000 { + status = "okay"; + + vbus-supply = <®_usb1_vbus>; + pinctrl-names = "default"; + }; + + gpmi-nand@8000c000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpmi_pins_a>; + }; + + mac0: ethernet@800f0000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac0_pins_a>; + status = "okay"; + mac-address = [000000000000]; /* will be set bootloader */ + }; + + mac1: ethernet@800f4000 { + phy-mode = "rmii"; + pinctrl-names = "default"; + pinctrl-0 = <&mac1_pins_a>; + status = "okay"; + mac-address = [000000000000]; /* will be set by bootloader */ + }; + }; + + stk5_led: leds { + compatible = "gpio-leds"; + + user { + label = "Heartbeat"; + pinctrl-names = "default"; + pinctrl-0 = <&hog_pins_stk_v3_led>; + gpios = <&gpio4 10 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + backlight { + compatible = "pwm-backlight"; + pwms = <&pwm 0 5000000>; + brightness-levels = <100 95 90 85 80 75 70 65 60 55 + 50 45 40 35 30 25 20 15 10 5 0>; + default-brightness-level = <20>; + }; + + gpio-switch { + compatible = "gpio-switches", "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + flexcan_transceiver: gpio-switch@0 { + label = "flexcan transceiver switch"; + gpios = <&gpio1 0 1>; + gpio-shared; + }; + + lcd_power: gpio-switch@1 { + compatible = "linux,gpio-switch"; + gpios = <&gpio1 31 0>; + label = "LCD Power Enable"; + init-state = <0>; + }; + + lcd_reset: gpio-switch@2 { + compatible = "linux,gpio-switch"; + gpios = <&gpio3 30 1>; + label = "LCD Reset"; + init-state = <1>; + }; + + edt_ft5x06_reset: gpio-switch@3 { + compatible = "linux,gpio-switch"; + gpios = <&gpio2 6 1>; + label = "EDT-FT5x06 RESET"; + }; + + edt_ft5x06_wake: gpio-switch@4 { + compatible = "linux,gpio-switch"; + gpios = <&gpio4 9 0>; + label = "EDT-FT5x06 WAKE"; + init-state = <1>; + }; + + usbotg_vbus: gpio-switch@5 { + compatible = "linux,gpio-switch"; + gpios = <&gpio0 18 0>; + label = "USBOTG VBUS"; + }; + + usbh1_vbus: gpio-switch@6 { + compatible = "linux,gpio-switch"; + gpios = <&gpio3 27 0>; + label = "USBH1 VBUS"; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_2p5v: 2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usb0_vbus: usb0_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio0 18 1>; + }; + + reg_usb1_vbus: usb1_vbus { + compatible = "regulator-fixed"; + regulator-name = "usb1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio3 27 1>; + }; + }; +}; diff --git a/board/karo/dts/tx48.dts b/board/karo/dts/tx48.dts new file mode 100644 index 0000000000..a1328363fc --- /dev/null +++ b/board/karo/dts/tx48.dts @@ -0,0 +1,117 @@ +/* + * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "am33xx.dtsi" + +/ { + model = "Ka-Ro electronics TX48 module"; + compatible = "karo,tx48", "ti,am33xx"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + ocp { + i2c@44E0B000 { + rtc1: ds1339@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + trickle-charge = <0xa5>; + }; + + pmic: lt3589@48 { + compatible = "lt,lt3589"; + reg = <0x48>; + }; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + touchscreen: tsc2007@48 { + compatible = "ti,tsc2007"; + reg = <0x48>; + interrupt-parent = <&gpio3>; + interrupts = <16 0>; + pendown-gpio = <&gpio3 16 1>; + model = "2007"; + x-plate-ohms = <660>; + }; + + polytouch: edt-ft5x06@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <17>; + reset-switch = <&edt_ft5x06_reset>; + wake-switch = <&edt_ft5x06_wake>; + }; + }; + }; + + gpio-switch { + compatible = "gpio-switch"; + + can_xcvr_enable: can-xcvr-enable { + gpio = <&gpio0 22 1>; + label = "Flexcan Transceiver Enable"; + gpio-shared; + }; + + lcd_power: lcd-power { + compatible = "linux,gpio-switch"; + gpio = <&gpio1 22 0>; + label = "LCD Power Enable"; + }; + + lcd_reset: lcd-reset { + compatible = "linux,gpio-switch"; + gpio = <&gpio1 19 1>; + label = "LCD Reset"; + init-state = <1>; + }; + + edt_ft5x06_reset: edt-ft5x06-reset { + compatible = "linux,gpio-switch"; + gpio = <&gpio1 18 1>; + label = "EDT-FT5x06 RESET"; + }; + + edt_ft5x06_wake: edt-ft5x06-wake { + compatible = "linux,gpio-switch"; + gpio = <&gpio1 27 0>; + label = "EDT-FT5x06 WAKE"; + init-state = <1>; + }; + }; + + regulators { + compatible = "simple-bus"; + + reg_2p5v: 2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; diff --git a/board/karo/dts/tx51.dts b/board/karo/dts/tx51.dts new file mode 100644 index 0000000000..22f547e4a5 --- /dev/null +++ b/board/karo/dts/tx51.dts @@ -0,0 +1,323 @@ +/* + * Copyright 2012 + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "mx51.dtsi" + +/ { + model = "Ka-Ro electronics TX51 module"; + compatible = "karo,tx51", "fsl,imx51"; + + chosen { + bootargs = "init=/linuxrc console=ttymxc0,115200 root=/dev/mtdblock1 ro debug panic=1"; + }; + + aliases { + usbh1 = &usbh1; + usbotg = &usbotg; + usbphy = &usbphy; + }; + + clocks { + ckih1 { + clock-frequency = <0>; + }; + }; + + soc { + ahb: ahb@40000000 { + ipu: ipu@5e000000 { + status = "okay"; + }; + }; + + aips1: aips@70000000 { /* AIPS1 */ + spba@70000000 { + mmc0: esdhc@70004000 { /* ESDHC1 */ + cd-gpios = <&gpio3 8 0>; + fsl,wp-controller; + status = "okay"; + }; + + mmc1: esdhc@70008000 { /* ESDHC2 */ + cd-gpios = <&gpio3 6 0>; + status = "okay"; + }; + + uart@7000c000 { + status = "okay"; + fsl,uart-has-rtscts; + }; + + spi0: ecspi@70010000 { /* ECSPI1 */ + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio4 24 0 &gpio4 25 0>; + status = "okay"; + + spidev0: spi@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <250000000>; + }; + }; + }; + + usbotg: imxotg@73f80000 { + status = "okay"; + + ignore-overcurrent; + enable-wakeup; + phy-mode = "utmi-wide"; + }; + + usbh1: imxotg@73f80200 { + status = "okay"; + + phy-mode = "ulpi"; + ignore-overcurrent; + enable-wakeup; + itc-no-threshold; + }; + + usbphy: imx-usb-phy@73f80800 { + status = "okay"; + + device-ports = <&usbotg>; + host-ports = <&usbotg &usbh1>; + }; + + keypad@73f94000 { + status = "okay"; + /* sample keymap */ + linux,keymap = < 0x00000074 /* row 0, col 0, KEY_POWER */ + 0x00010052 /* row 0, col 1, KEY_KP0 */ + 0x0002004f /* row 0, col 2, KEY_KP1 */ + 0x00030050 /* row 0, col 3, KEY_KP2 */ + 0x00040051 /* row 0, col 4, KEY_KP3 */ + 0x0100004b /* row 1, col 0, KEY_KP4 */ + 0x0101004c /* row 1, col 1, KEY_KP5 */ + 0x0102004d /* row 1, col 2, KEY_KP6 */ + 0x01030047 /* row 1, col 3, KEY_KP7 */ + 0x01040048 /* row 1, col 4, KEY_KP8 */ + 0x02000049 /* row 2, col 0, KEY_KP9 */ + >; + }; + + wdog@73f98000 { /* WDOG1 */ + status = "okay"; + }; + + iomuxc@73fa8000 { + compatible = "fsl,imx51-iomuxc-tx51"; + reg = <0x73fa8000 0x4000>; + }; + + pwm1: pwm@73fb4000 { + status = "okay"; + }; + + uart@73fbc000 { + status = "okay"; + fsl,uart-has-rtscts; + }; + + uart@73fc0000 { + status = "okay"; + fsl,uart-has-rtscts; + }; + }; + + aips2: aips@80000000 { /* AIPS2 */ + + sdma@83fb0000 { + fsl,sdma-ram-script-name = "sdma-imx51.bin"; + }; + + i2c@83fc4000 { /* I2C2 */ + status = "okay"; + + codec: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + }; + + touchscreen: tsc2007@48 { + compatible = "ti,tsc2007"; + reg = <0x48>; + interrupt-parent = <&gpio3>; + interrupts = <3 0>; + pendown-gpio = <&gpio3 3 1>; + model = "2007"; + x-plate-ohms = <660>; + }; + + polytouch: edt-ft5x06@38 { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio1>; + interrupts = <5>; + reset-switch = <&edt_ft5x06_reset>; + wake-switch = <&edt_ft5x06_wake>; + }; + }; + + ssi@83fcc000 { + status = "okay"; + rx-dma = <28>; + tx-dma = <29>; + i2s-sync-mode; + }; + + ssi@70014000 { + status = "okay"; + }; + + audmux@83fd0000 { + status = "okay"; + }; + + sound-card@0 { + compatible = "fsl,imx-sgtl5000"; + status = "okay"; + /* '1' based port numbers according to datasheet names */ + ssi-port = <1>; + audmux-port = <3>; + sysclk = <26000000>; + }; + + nand@83fdb000 { + status = "okay"; + + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + }; + + ethernet@83fec000 { + phy-mode = "mii"; +/* + phy-reset-gpios = <&gpio2 14 0>; +*/ + status = "okay"; + phy-handle = <&phy0>; + mac-address = [000000000000]; + + phy0: ethernet-phy@0 { + interrupt-parent = <&gpio3>; + interrupts = <18>; + device_type = "ethernet-phy"; + }; + }; + }; + }; + + i2c-gpio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "i2c-gpio"; + gpios = <&gpio4 17 0 + &gpio4 16 0>; + clock-frequency = <400000>; + + rtc1: ds1339@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; + }; + + gpio-switch { + compatible = "gpio-switches", "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + lcd_power: gpio-switch@1 { + compatible = "linux,gpio-switch"; + gpio = <&gpio4 14 0>; + label = "LCD Power Enable"; + init-state = <0>; + }; + + lcd_reset: gpio-switch@2 { + compatible = "linux,gpio-switch"; + gpio = <&gpio4 13 1>; + label = "LCD Reset"; + init-state = <1>; + }; + + edt_ft5x06_reset: gpio-switch@3 { + compatible = "linux,gpio-switch"; + gpio = <&gpio4 15 1>; + label = "EDT-FT5x06 RESET"; + }; + + edt_ft5x06_wake: gpio-switch@4 { + compatible = "linux,gpio-switch"; + gpio = <&gpio4 9 0>; + label = "EDT-FT5x06 WAKE"; + init-state = <1>; + }; + + usbotg_vbus: gpio-switch@5 { + compatible = "linux,gpio-switch"; + gpio = <&gpio1 8 0>; + label = "USBOTG VBUS"; + }; + }; + + leds { + compatible = "gpio-leds"; + + user { + label = "Heartbeat"; + gpios = <&gpio4 10 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + lcd { + compatible = "of-gpio-lcd"; + parent = <&ipu>; + + power-switch = <&gpio4 14 0>; + reset-switch = <&gpio4 13 1>; + }; + + backlight: pwm-backlight { + compatible = "pwm-backlight"; + + pwm = <&pwm1>; + inverted; + max-brightness = <100>; + dft-brightness = <50>; + pwm-period-ns = <1000000>; + }; + + regulators { + compatible = "simple-bus"; + + reg_2p5v: 2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; diff --git a/board/karo/dts/tx53.dts b/board/karo/dts/tx53.dts new file mode 100644 index 0000000000..0dc6fced8c --- /dev/null +++ b/board/karo/dts/tx53.dts @@ -0,0 +1,432 @@ +/* + * Copyright 2012 + * based on imx53-qsb.dts + * Copyright 2011 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "mx53.dtsi" + +/ { + model = "Ka-Ro electronics TX53 module"; + compatible = "karo,tx53", "fsl,imx53"; + + chosen { + bootargs = "init=/linuxrc console=ttymxc0,115200 root=/dev/mtdblock3 rootfstype=jffs2 ro debug panic=1"; + }; + + aliases { + ipu = &ipu; + }; + + clocks { + ckih1 { + clock-frequency = <0>; + }; + }; + + soc { + extmc: extmc@00000000 { + sata: sata@10000000 { + status = "okay"; + }; + + ipu: ipu@1e000000 { + status = "okay"; + }; + }; + + aips1: aips@50000000 { /* AIPS1 */ + spba@50000000 { + mmc0: esdhc@50004000 { /* ESDHC1 */ + status = "okay"; + cd-gpios = <&gpio3 24 0>; + fsl,wp-controller; + }; + + mmc1: esdhc@50008000 { /* ESDHC2 */ + status = "okay"; + cd-gpios = <&gpio3 25 0>; + fsl,wp-controller; + }; + + uart3: uart@5000c000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_1>; + fsl,uart-has-rtscts; + }; + + spi0: ecspi@50010000 { /* ECSPI1 */ + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_ecspi1_1 + &pinctrl_cspi1_cs + >; + + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio2 30 0 &gpio3 19 0>; + + spidev0: spi@0 { + compatible = "spidev"; + reg = <0>; + spi-max-frequency = <54000000>; + }; + }; + }; + + usbotg: imxotg@53f80000 { + status = "okay"; + + ignore-overcurrent; + enable-wakeup; + vbus-gpio = <&usbotg_vbus>; + }; + + usbh1: imxotg@53f80200 { + status = "okay"; + + ignore-overcurrent; + enable-wakeup; + vbus-gpio = <&usbh1_vbus>; + }; + + usbphy: imx-usb-phy@53f80800 { + status = "okay"; + + device-ports = <&usbotg>; + host-ports = <&usbotg &usbh1>; + }; + + keypad@53f94000 { + status = "okay"; + /* sample keymap */ + /* row/col 0,1 are mapped to KPP row/col 6,7 */ + linux,keymap = < 0x06060074 /* row 6, col 6, KEY_POWER */ + 0x06070052 /* row 6, col 7, KEY_KP0 */ + 0x0602004f /* row 6, col 2, KEY_KP1 */ + 0x06030050 /* row 6, col 3, KEY_KP2 */ + 0x07060051 /* row 7, col 6, KEY_KP3 */ + 0x0707004b /* row 7, col 7, KEY_KP4 */ + 0x0702004c /* row 7, col 2, KEY_KP5 */ + 0x0703004d /* row 7, col 3, KEY_KP6 */ + 0x02060047 /* row 2, col 6, KEY_KP7 */ + 0x02070048 /* row 2, col 7, KEY_KP8 */ + 0x02020049 /* row 2, col 2, KEY_KP9 */ + >; + }; + + wdog@53f98000 { /* WDOG1 */ + status = "okay"; + }; + + iomuxc@53fa8000 { + compatible = "fsl,imx53-iomuxc-tx53"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tsc2007_pd>; + + pincontroller { + pinctrl_stk5_led: stk5-led-gpios { + fsl,pins = < + 589 0xc0 /* MX53_PAD_EIM_A18__GPIO2_20 */ + >; + }; + + pinctrl_ds1339_int: ds1339-gpios { + fsl,pins = < + 104 0xe0 /* MX53_PAD_DI0_PIN4__GPIO4_20 */ + >; + }; + + pinctrl_cspi1_cs: cspi1-cs-gpios { + fsl,pins = < + 424 0xe0 /* MX53_PAD_EIM_EB2__GPIO2_30 */ + 449 0xe0 /* MX53_PAD_EIM_D19__GPIO3_19 */ + >; + }; + + pinctrl_esdhc1_cd: esdhc1-cd-gpios { + fsl,pins = < + 493 0x1f0 /* MX53_PAD_EIM_D24__GPIO3_24 */ + >; + }; + + pinctrl_esdhc2_cd: esdhc2-cd-gpios { + fsl,pins = < + 501 0x1f0 /* MX53_PAD_EIM_D25__GPIO3_25 */ + >; + }; + + pinctrl_tsc2007_pd: pendown-gpios { + fsl,pins = < + 517 0x1f0 /* MX53_PAD_EIM_D27__GPIO3_27 */ + >; + }; + }; + }; + + pwm2: pwm@53fb8000 { + status = "okay"; + }; + + uart1: uart@53fbc000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_2>; + fsl,uart-has-rtscts; + }; + + uart2: uart@53fc0000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_1>; + fsl,uart-has-rtscts; + }; + + can1: flexcan@53fc8000 { + status = "okay"; + transceiver-switch = <&flexcan_transceiver>; + }; + + can2: flexcan@53fcc000 { + status = "okay"; + transceiver-switch = <&flexcan_transceiver>; + }; + + i2c@53fec000 { /* I2C3 */ + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3_1>; + + sgtl5000: sgtl5000@0a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + VDDA-supply = <®_2p5v>; + VDDIO-supply = <®_3p3v>; + clock-frequency = <26000000>; + }; + + touchscreen: tsc2007@48 { + compatible = "ti,tsc2007"; + reg = <0x48>; + interrupt-parent = <&gpio3>; + interrupts = <26 0>; + pendown-gpio = <&gpio3 26 1>; + model = "2007"; + x-plate-ohms = <660>; + }; + + polytouch: edt-ft5x06@ { + compatible = "edt,edt-ft5x06"; + reg = <0x38>; + interrupt-parent = <&gpio6>; + interrupts = <15 0>; + reset-switch = <&edt_ft5x06_reset>; + wake-switch = <&edt_ft5x06_wake>; + }; + }; + }; + + aips2: aips@60000000 { /* AIPS2 */ + + sdma@63fb0000 { + fsl,sdma-ram-script-name = "sdma-imx53.bin"; + }; + + i2c@63fc8000 { /* I2C1 */ + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = < + &pinctrl_i2c1_2 + &pinctrl_ds1339_int + >; + + rtc1: ds1339@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + trickle-charge = <0xa5>; + interrupt-parent = <&gpio4>; + interrupts = <20 0>; + }; + + pmic: lt3589@48 { + compatible = "lt,lt3589"; + reg = <0x48>; + }; + }; + + ssi@63fcc000 { + status = "okay"; + rx-dma = <28>; + tx-dma = <29>; + i2s-sync-mode; + }; + + ssi@50014000 { + status = "okay"; + }; + + audmux@63fd0000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux_1>; + }; + + nand@63fdb000 { + status = "okay"; + + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + }; + + ethernet@63fec000 { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_1>; + + phy-mode = "rmii"; + phy-reset-gpios = <&gpio7 6 0>; + phy-handle = <&phy0>; + mac-address = [000000000000]; + + phy0: ethernet-phy@0 { + interrupt-parent = <&gpio2>; + interrupts = <4>; + device_type = "ethernet-phy"; + }; + }; + }; + }; + + sound { + compatible = "fsl,imx-sgtl5000"; + status = "okay"; + /* '1' based port numbers according to datasheet names */ + ssi-port = <1>; + audmux-port = <5>; + sysclk = <26000000>; + }; + + gpio-switch { + compatible = "gpio-switches", "simple-bus"; + #address-cells = <1>; + #size-cells = <0>; + + flexcan_transceiver: gpio-switch@0 { + compatible = "linux,gpio-switch"; + gpio = <&gpio4 21 1>; + label = "Flexcan Transceiver Enable"; + gpio-shared; + init-state = <0>; + }; + + lcd_power: gpio-switch@1 { + compatible = "linux,gpio-switch"; + gpio = <&gpio2 31 0>; + label = "LCD Power Enable"; + init-state = <0>; + }; + + lcd_reset: gpio-switch@2 { + compatible = "linux,gpio-switch"; + gpio = <&gpio3 29 1>; + label = "LCD Reset"; + init-state = <1>; + }; + + edt_ft5x06_reset: gpio-switch@3 { + compatible = "linux,gpio-switch"; + gpio = <&gpio2 22 1>; + label = "EDT-FT5x06 RESET"; + }; + + edt_ft5x06_wake: gpio-switch@4 { + compatible = "linux,gpio-switch"; + gpio = <&gpio2 21 0>; + label = "EDT-FT5x06 WAKE"; + init-state = <1>; + }; + + usbotg_vbus: gpio-switch@5 { + compatible = "linux,gpio-switch"; + gpio = <&gpio1 7 0>; + label = "USBOTG VBUS"; + }; + + usbh1_vbus: gpio-switch@6 { + compatible = "linux,gpio-switch"; + gpio = <&gpio3 31 0>; + label = "USBH1 VBUS"; + }; + }; + + leds { + compatible = "gpio-leds"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_stk5_led>; + + user { + label = "Heartbeat"; + gpios = <&gpio2 20 0>; + linux,default-trigger = "heartbeat"; + }; + }; + + lcd { + compatible = "of-gpio-lcd"; + parent = <&ipu>; + + power-switch = <&lcd_power>; +/* + reset-switch = <&lcd_reset>; + reset-delay-us = <300>; +*/ + }; + + backlight: pwm-backlight { + compatible = "pwm-backlight"; + + pwm = <&pwm2>; + inverted; + max-brightness = <100>; + dft-brightness = <50>; + pwm-period-ns = <1000000>; + }; + + regulators { + compatible = "simple-bus"; + + reg_2p5v: 2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: 3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + }; +}; diff --git a/board/karo/dts/tx6dl.dts b/board/karo/dts/tx6dl.dts new file mode 100644 index 0000000000..dfbc506052 --- /dev/null +++ b/board/karo/dts/tx6dl.dts @@ -0,0 +1,62 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "mx6dl.dtsi" + +/ { + model = "Ka-Ro TX6Q module"; + compatible = "karo,imx6q-tx6q", "fsl,imx6q"; + + memory { + reg = <0 0>; /* filled in by U-Boot */ + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_3 &pinctrl_uart1_4>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_5 &pinctrl_uart2_6>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_1 &pinctrl_uart3_4>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_1>; + phy-mode = "rmii"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_2>; + cd-gpios = <&gpio7 2 0>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_2>; + cd-gpios = <&gpio7 3 0>; + status = "okay"; +}; diff --git a/board/karo/dts/tx6q.dts b/board/karo/dts/tx6q.dts new file mode 100644 index 0000000000..869c843ea2 --- /dev/null +++ b/board/karo/dts/tx6q.dts @@ -0,0 +1,62 @@ +/* + * Copyright 2012 Freescale Semiconductor, Inc. + * Copyright 2011 Linaro Ltd. + * + * The code contained herein is licensed under the GNU General Public + * License. You may obtain a copy of the GNU General Public License + * Version 2 or later at the following locations: + * + * http://www.opensource.org/licenses/gpl-license.html + * http://www.gnu.org/copyleft/gpl.html + */ + +/dts-v1/; +#include "mx6q.dtsi" + +/ { + model = "Ka-Ro TX6Q module"; + compatible = "karo,imx6q-tx6q", "fsl,imx6q"; + + memory { + reg = <0 0>; /* filled in by U-Boot */ + }; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1_3 &pinctrl_uart1_4>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2_5 &pinctrl_uart2_6>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3_1 &pinctrl_uart3_4>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet_1>; + phy-mode = "rmii"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1_2>; + cd-gpios = <&gpio7 2 0>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2_2>; + cd-gpios = <&gpio7 3 0>; + status = "okay"; +}; diff --git a/board/karo/tx28/Makefile b/board/karo/tx28/Makefile new file mode 100644 index 0000000000..e7931405f3 --- /dev/null +++ b/board/karo/tx28/Makefile @@ -0,0 +1,53 @@ +# +# (C) Copyright 2009 DENX Software Engineering +# Author: John Rigby +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := tx28.o +ifeq ($(CONFIG_SPL_BUILD),y) + COBJS += spl_boot.o +else +ifeq ($(CONFIG_CMD_ROMUPDATE),y) + COBJS += flash.o +endif +endif + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +$(obj)u-boot.db: u-boot.db.in + sed "s:@@BUILD_DIR@@:${BUILD_DIR:-.}/:" $< > $@ + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/karo/tx28/config.mk b/board/karo/tx28/config.mk new file mode 100644 index 0000000000..a11dc498e7 --- /dev/null +++ b/board/karo/tx28/config.mk @@ -0,0 +1,10 @@ +# stack is allocated below CONFIG_SYS_TEXT_BASE +CONFIG_SYS_TEXT_BASE := 0x40100000 +CONFIG_SPL_TEXT_BASE := 0x00000000 + +LOGO_BMP = logos/karo.bmp + +PLATFORM_CPPFLAGS += -Werror +ifneq ($(CONFIG_SPL_BUILD),y) + ALL-y += $(obj)u-boot.sb +endif diff --git a/board/karo/tx28/flash.c b/board/karo/tx28/flash.c new file mode 100644 index 0000000000..75b85196b7 --- /dev/null +++ b/board/karo/tx28/flash.c @@ -0,0 +1,602 @@ +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + +#define FCB_START_BLOCK 0 +#define NUM_FCB_BLOCKS 1 +#define MAX_FCB_BLOCKS 32768 + +struct mx28_nand_timing { + u8 data_setup; + u8 data_hold; + u8 address_setup; + u8 dsample_time; + u8 nand_timing_state; + u8 tREA; + u8 tRLOH; + u8 tRHOH; +}; + +struct mx28_fcb { + u32 checksum; + u32 fingerprint; + u32 version; + struct mx28_nand_timing timing; + u32 page_data_size; + u32 total_page_size; + u32 sectors_per_block; + u32 number_of_nands; /* not used by ROM code */ + u32 total_internal_die; /* not used by ROM code */ + u32 cell_type; /* not used by ROM code */ + u32 ecc_blockn_type; + u32 ecc_block0_size; + u32 ecc_blockn_size; + u32 ecc_block0_type; + u32 metadata_size; + u32 ecc_blocks_per_page; + u32 rsrvd[6]; /* not used by ROM code */ + u32 bch_mode; + u32 boot_patch; + u32 patch_sectors; + u32 fw1_start_page; + u32 fw2_start_page; + u32 fw1_sectors; + u32 fw2_sectors; + u32 dbbt_search_area; + u32 bb_mark_byte; + u32 bb_mark_startbit; + u32 bb_mark_phys_offset; +}; + +struct mx28_dbbt_header { + u32 checksum; + u32 fingerprint; + u32 version; + u32 number_bb; + u32 number_pages; + u8 spare[492]; +}; + +struct mx28_dbbt { + u32 nand_number; + u32 number_bb; + u32 bb_num[2040 / 4]; +}; + +#define BF_VAL(v, bf) (((v) & bf##_MASK) >> bf##_OFFSET) + +static nand_info_t *mtd = &nand_info[0]; + +extern void *_start; + +#define BIT(v,n) (((v) >> (n)) & 0x1) + +static u8 calculate_parity_13_8(u8 d) +{ + u8 p = 0; + + p |= (BIT(d, 6) ^ BIT(d, 5) ^ BIT(d, 3) ^ BIT(d, 2)) << 0; + p |= (BIT(d, 7) ^ BIT(d, 5) ^ BIT(d, 4) ^ BIT(d, 2) ^ BIT(d, 1)) << 1; + p |= (BIT(d, 7) ^ BIT(d, 6) ^ BIT(d, 5) ^ BIT(d, 1) ^ BIT(d, 0)) << 2; + p |= (BIT(d, 7) ^ BIT(d, 4) ^ BIT(d, 3) ^ BIT(d, 0)) << 3; + p |= (BIT(d, 6) ^ BIT(d, 4) ^ BIT(d, 3) ^ BIT(d, 2) ^ BIT(d, 1) ^ BIT(d, 0)) << 4; + return p; +} + +static void encode_hamming_13_8(void *_src, void *_ecc, size_t size) +{ + int i; + u8 *src = _src; + u8 *ecc = _ecc; + + for (i = 0; i < size; i++) + ecc[i] = calculate_parity_13_8(src[i]); +} + +static u32 calc_chksum(void *buf, size_t size) +{ + u32 chksum = 0; + u8 *bp = buf; + size_t i; + + for (i = 0; i < size; i++) { + chksum += bp[i]; + } + return ~chksum; +} + +/* + Physical organisation of data in NAND flash: + metadata + payload chunk 0 (may be empty) + ecc for metadata + payload chunk 0 + payload chunk 1 + ecc for payload chunk 1 +... + payload chunk n + ecc for payload chunk n + */ + +static int calc_bb_offset(nand_info_t *mtd, struct mx28_fcb *fcb) +{ + int bb_mark_offset; + int chunk_data_size = fcb->ecc_blockn_size * 8; + int chunk_ecc_size = (fcb->ecc_blockn_type << 1) * 13; + int chunk_total_size = chunk_data_size + chunk_ecc_size; + int bb_mark_chunk, bb_mark_chunk_offs; + + bb_mark_offset = (mtd->writesize - fcb->metadata_size) * 8; + if (fcb->ecc_block0_size == 0) + bb_mark_offset -= (fcb->ecc_block0_type << 1) * 13; + + bb_mark_chunk = bb_mark_offset / chunk_total_size; + bb_mark_chunk_offs = bb_mark_offset - (bb_mark_chunk * chunk_total_size); + if (bb_mark_chunk_offs > chunk_data_size) { + printf("Unsupported ECC layout; BB mark resides in ECC data: %u\n", + bb_mark_chunk_offs); + return -EINVAL; + } + bb_mark_offset -= bb_mark_chunk * chunk_ecc_size; + return bb_mark_offset; +} + +static struct mx28_fcb *create_fcb(void *buf, int fw1_start_block, + int fw2_start_block, size_t fw_size) +{ + struct gpmi_regs *gpmi_base = (void *)GPMI_BASE_ADDRESS; + struct bch_regs *bch_base = (void *)BCH_BASE_ADDRESS; + u32 fl0, fl1; + u32 t0; + int metadata_size; + int bb_mark_bit_offs; + struct mx28_fcb *fcb; + int fcb_offs; + + if (gpmi_base == NULL || bch_base == NULL) { + return ERR_PTR(-ENOMEM); + } + + fl0 = readl(&bch_base->hw_bch_flash0layout0); + fl1 = readl(&bch_base->hw_bch_flash0layout1); + t0 = readl(&gpmi_base->hw_gpmi_timing0); + + metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE); + + fcb = buf + ALIGN(metadata_size, 4); + fcb_offs = (void *)fcb - buf; + + memset(buf, 0xff, fcb_offs); + memset(fcb, 0x00, sizeof(*fcb)); + memset(fcb + 1, 0xff, mtd->erasesize - fcb_offs - sizeof(*fcb)); + + strncpy((char *)&fcb->fingerprint, "FCB ", 4); + fcb->version = cpu_to_be32(1); + + /* ROM code assumes GPMI clock of 25 MHz */ + fcb->timing.data_setup = BF_VAL(t0, GPMI_TIMING0_DATA_SETUP) * 40; + fcb->timing.data_hold = BF_VAL(t0, GPMI_TIMING0_DATA_HOLD) * 40; + fcb->timing.address_setup = BF_VAL(t0, GPMI_TIMING0_ADDRESS_SETUP) * 40; + + fcb->page_data_size = mtd->writesize; + fcb->total_page_size = mtd->writesize + mtd->oobsize; + fcb->sectors_per_block = mtd->erasesize / mtd->writesize; + + fcb->ecc_block0_type = BF_VAL(fl0, BCH_FLASHLAYOUT0_ECC0); + fcb->ecc_block0_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_DATA0_SIZE); + fcb->ecc_blockn_type = BF_VAL(fl1, BCH_FLASHLAYOUT1_ECCN); + fcb->ecc_blockn_size = BF_VAL(fl1, BCH_FLASHLAYOUT1_DATAN_SIZE); + + fcb->metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE); + fcb->ecc_blocks_per_page = BF_VAL(fl0, BCH_FLASHLAYOUT0_NBLOCKS); + fcb->bch_mode = readl(&bch_base->hw_bch_mode); +/* + fcb->boot_patch = 0; + fcb->patch_sectors = 0; +*/ + fcb->fw1_start_page = fw1_start_block * mtd->erasesize / mtd->writesize; + fcb->fw1_sectors = DIV_ROUND_UP(fw_size, mtd->writesize); + + if (fw2_start_block != 0 && fw2_start_block < mtd->size / mtd->erasesize) { + fcb->fw2_start_page = fw2_start_block * mtd->erasesize / mtd->writesize; + fcb->fw2_sectors = fcb->fw1_sectors; + } + + fcb->dbbt_search_area = 1; + + bb_mark_bit_offs = calc_bb_offset(mtd, fcb); + if (bb_mark_bit_offs < 0) + return ERR_PTR(bb_mark_bit_offs); + fcb->bb_mark_byte = bb_mark_bit_offs / 8; + fcb->bb_mark_startbit = bb_mark_bit_offs % 8; + fcb->bb_mark_phys_offset = mtd->writesize; + + fcb->checksum = calc_chksum(&fcb->fingerprint, 512 - 4); + return fcb; +} + +static int find_fcb(void *ref, int page) +{ + int ret = 0; + struct nand_chip *chip = mtd->priv; + void *buf = malloc(mtd->erasesize); + + if (buf == NULL) { + return -ENOMEM; + } + chip->select_chip(mtd, 0); + chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); + ret = chip->ecc.read_page_raw(mtd, chip, buf, 1, page); + if (ret) { + printf("Failed to read FCB from page %u: %d\n", page, ret); + return ret; + } + chip->select_chip(mtd, -1); + if (memcmp(buf, ref, mtd->writesize) == 0) { + debug("Found FCB in page %u (%08x)\n", + page, page * mtd->writesize); + ret = 1; + } + free(buf); + return ret; +} + +static int write_fcb(void *buf, int block) +{ + int ret; + struct nand_chip *chip = mtd->priv; + int page = block * mtd->erasesize / mtd->writesize; + + ret = find_fcb(buf, page); + if (ret > 0) { + printf("FCB at block %d is up to date\n", block); + return 0; + } + + ret = nand_erase(mtd, block * mtd->erasesize, mtd->erasesize); + if (ret) { + printf("Failed to erase FCB block %u\n", block); + return ret; + } + + printf("Writing FCB to block %d @ %08x\n", block, + block * mtd->erasesize); + chip->select_chip(mtd, 0); + ret = chip->write_page(mtd, chip, buf, 1, page, 0, 1); + if (ret) { + printf("Failed to write FCB to block %u: %d\n", block, ret); + } + chip->select_chip(mtd, -1); + return ret; +} + +static size_t count_good_blocks(int start, int end) +{ + size_t max_len = (end - start + 1); + int block; + + for (block = start; block <= end; block++) { + if (nand_block_isbad(mtd, block * mtd->erasesize)) + max_len--; + } + return max_len; +} + +#define chk_overlap(a,b) \ + ((a##_start_block <= b##_end_block && \ + a##_end_block >= b##_start_block) || \ + (b##_start_block <= a##_end_block && \ + b##_end_block >= a##_start_block)) + +#define fail_if_overlap(a,b,m1,m2) do { \ + if (chk_overlap(a, b)) { \ + printf("%s blocks %lu..%lu overlap %s in blocks %lu..%lu!\n", \ + m1, a##_start_block, a##_end_block, \ + m2, b##_start_block, b##_end_block); \ + return -EINVAL; \ + } \ +} while (0) + +#ifdef CONFIG_ENV_IS_IN_NAND +#ifndef CONFIG_ENV_OFFSET_REDUND +#define TOTAL_ENV_SIZE CONFIG_ENV_RANGE +#else +#define TOTAL_ENV_SIZE (CONFIG_ENV_RANGE * 2) +#endif +#endif + +int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + int ret; + int erase_size = mtd->erasesize; + int page_size = mtd->writesize; + void *buf; + char *load_addr; + char *file_size; + size_t size = 0; + void *addr = NULL; + struct mx28_fcb *fcb; + unsigned long fcb_start_block = FCB_START_BLOCK; + unsigned long num_fcb_blocks = NUM_FCB_BLOCKS; + unsigned long fcb_end_block; + unsigned long mtd_num_blocks = mtd->size / mtd->erasesize; +#ifdef CONFIG_ENV_IS_IN_NAND + unsigned long env_start_block = CONFIG_ENV_OFFSET / mtd->erasesize; + unsigned long env_end_block = env_start_block + + DIV_ROUND_UP(TOTAL_ENV_SIZE, mtd->erasesize) - 1; +#endif + int optind; + int fw1_set = 0; + int fw2_set = 0; + unsigned long fw1_start_block = 0, fw1_end_block; + unsigned long fw2_start_block = 0, fw2_end_block; + unsigned long fw_num_blocks; + unsigned long extra_blocks = 2; + nand_erase_options_t erase_opts = { 0, }; + size_t max_len1, max_len2; + size_t actual; + + for (optind = 1; optind < argc; optind++) { + if (strcmp(argv[optind], "-b") == 0) { + if (optind >= argc - 1) { + printf("Option %s requires an argument\n", argv[optind]); + return -EINVAL; + } + optind++; + fcb_start_block = simple_strtoul(argv[optind], NULL, 0); + if (fcb_start_block >= mtd_num_blocks) { + printf("Block number %lu is out of range: 0..%lu\n", + fcb_start_block, mtd_num_blocks - 1); + return -EINVAL; + } + } else if (strcmp(argv[optind], "-n") == 0) { + if (optind >= argc - 1) { + printf("Option %s requires an argument\n", argv[optind]); + return -EINVAL; + } + optind++; + num_fcb_blocks = simple_strtoul(argv[optind], NULL, 0); + if (num_fcb_blocks > MAX_FCB_BLOCKS) { + printf("Extraneous number of FCB blocks; max. allowed: %u\n", + MAX_FCB_BLOCKS); + return -EINVAL; + } + } else if (strcmp(argv[optind], "-f") == 0) { + if (optind >= argc - 1) { + printf("Option %s requires an argument\n", + argv[optind]); + return -EINVAL; + } + optind++; + fw1_start_block = simple_strtoul(argv[optind], NULL, 0); + if (fw1_start_block >= mtd_num_blocks) { + printf("Block number %lu is out of range: 0..%lu\n", + fw1_start_block, mtd_num_blocks - 1); + return -EINVAL; + } + fw1_set = 1; + } else if (strcmp(argv[optind], "-r") == 0) { + if (optind < argc - 1 && argv[optind + 1][0] != '-') { + optind++; + fw2_start_block = simple_strtoul(argv[optind], + NULL, 0); + if (fw2_start_block >= mtd_num_blocks) { + printf("Block number %lu is out of range: 0..%lu\n", + fw2_start_block, + mtd_num_blocks - 1); + return -EINVAL; + } + } + fw2_set = 1; + } else if (strcmp(argv[optind], "-e") == 0) { + if (optind >= argc - 1) { + printf("Option %s requires an argument\n", + argv[optind]); + return -EINVAL; + } + optind++; + extra_blocks = simple_strtoul(argv[optind], NULL, 0); + if (extra_blocks >= mtd_num_blocks) { + printf("Extra block count %lu is out of range: 0..%lu\n", + extra_blocks, + mtd_num_blocks - 1); + return -EINVAL; + } + } else if (argv[optind][0] == '-') { + printf("Unrecognized option %s\n", argv[optind]); + return -EINVAL; + } else { + break; + } + } + + load_addr = getenv("fileaddr"); + file_size = getenv("filesize"); + + if (argc - optind < 1 && load_addr == NULL) { + printf("Load address not specified\n"); + return -EINVAL; + } + if (argc - optind < 2 && file_size == NULL) { + printf("WARNING: Image size not specified; overwriting whole uboot partition\n"); + } + if (argc > optind) { + load_addr = NULL; + addr = (void *)simple_strtoul(argv[optind], NULL, 16); + optind++; + } + if (argc > optind) { + file_size = NULL; + size = simple_strtoul(argv[optind], NULL, 16); + optind++; + } + if (load_addr != NULL) { + addr = (void *)simple_strtoul(load_addr, NULL, 16); + printf("Using default load address %p\n", addr); + } + if (file_size != NULL) { + size = simple_strtoul(file_size, NULL, 16); + printf("Using default file size %08x\n", size); + } + fcb_end_block = fcb_start_block + num_fcb_blocks - 1; + if (size > 0) + fw_num_blocks = DIV_ROUND_UP(size, mtd->erasesize); + else + fw_num_blocks = CONFIG_U_BOOT_IMG_SIZE / mtd->erasesize - extra_blocks; + + if (!fw1_set) { + fw1_start_block = fcb_end_block + 1; + fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1; + } else { + fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1; + } + + if (fw2_set && fw2_start_block == 0) { + fw2_start_block = fw1_end_block + 1; + fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1; + } else { + fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1; + } + +#ifdef CONFIG_ENV_IS_IN_NAND + fail_if_overlap(fcb, env, "FCB", "Environment"); + fail_if_overlap(fw1, env, "FW1", "Environment"); +#endif + fail_if_overlap(fcb, fw1, "FCB", "FW1"); + if (fw2_set) { + fail_if_overlap(fcb, fw2, "FCB", "FW2"); +#ifdef CONFIG_ENV_IS_IN_NAND + fail_if_overlap(fw2, env, "FW2", "Environment"); +#endif + fail_if_overlap(fw1, fw2, "FW1", "FW2"); + } + + buf = malloc(erase_size); + if (buf == NULL) { + printf("Failed to allocate buffer\n"); + return -ENOMEM; + } + + /* search for bad blocks in FW1 block range */ + max_len1 = count_good_blocks(fw1_start_block, fw1_end_block); + printf("%u good blocks in %lu..%lu\n", + max_len1, fw1_start_block, fw1_end_block); + if (fw_num_blocks > max_len1) { + printf("Too many bad blocks in FW1 block range: %lu..%lu; max blocks: %u\n", + fw1_end_block + 1 - fw_num_blocks - extra_blocks, + fw1_end_block, max_len1); + return -EINVAL; + } + + /* search for bad blocks in FW2 block range */ + max_len2 = count_good_blocks(fw2_start_block, fw2_end_block); + if (fw2_start_block > 0 && fw_num_blocks > max_len2) { + printf("Too many bad blocks in FW2 block range: %lu..%lu\n", + fw2_end_block + 1 - fw_num_blocks - extra_blocks, + fw2_end_block); + return -EINVAL; + } + + fcb = create_fcb(buf, fw1_start_block, fw2_start_block, + ALIGN(fw_num_blocks * mtd->erasesize, mtd->writesize)); + if (IS_ERR(fcb)) { + printf("Failed to initialize FCB: %ld\n", PTR_ERR(fcb)); + return PTR_ERR(fcb); + } + encode_hamming_13_8(fcb, (void *)fcb + 512, 512); + + ret = write_fcb(buf, fcb_start_block); + if (ret) { + printf("Failed to write FCB to block %lu\n", fcb_start_block); + return ret; + } + + printf("Programming U-Boot image from %p to block %lu\n", + addr, fw1_start_block); + if (size & (page_size - 1)) { + memset(addr + size, 0xff, size & (page_size - 1)); + size = ALIGN(size, page_size); + } + + erase_opts.offset = fcb->fw1_start_page * page_size; + erase_opts.length = (fw1_end_block - fw1_start_block + 1) * + mtd->erasesize; + erase_opts.quiet = 1; + + printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset, + erase_opts.offset + erase_opts.length - 1); + + ret = nand_erase_opts(mtd, &erase_opts); + if (ret) { + printf("Failed to erase flash: %d\n", ret); + return ret; + } + if (size == 0) + max_len1 *= mtd->erasesize; + else + max_len1 = size; + + printf("Programming flash @ %08x..%08x from %p\n", + fcb->fw1_start_page * page_size, + fcb->fw1_start_page * page_size + max_len1 - 1, addr); + ret = nand_write_skip_bad(mtd, fcb->fw1_start_page * page_size, + &max_len1, &actual, erase_opts.length, addr, + WITH_DROP_FFS); + if (ret || actual < size) { + printf("Failed to program flash: %d\n", ret); + return ret ?: -EIO; + } + if (fw2_start_block == 0) { + return ret; + } + + printf("Programming redundant U-Boot image to block %lu\n", + fw2_start_block); + erase_opts.offset = fcb->fw2_start_page * page_size; + erase_opts.length = (fw2_end_block - fw2_start_block + 1) * + mtd->erasesize; + printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset, + erase_opts.offset + erase_opts.length - 1); + + ret = nand_erase_opts(mtd, &erase_opts); + if (ret) { + printf("Failed to erase flash: %d\n", ret); + return ret; + } + if (size == 0) + max_len2 *= mtd->erasesize; + else + max_len2 = size; + printf("Programming flash @ %08x..%08x from %p\n", + fcb->fw2_start_page * page_size, + fcb->fw2_start_page * page_size + max_len2 - 1, addr); + ret = nand_write_skip_bad(mtd, fcb->fw2_start_page * page_size, + &max_len2, &actual, erase_opts.length, addr, + WITH_DROP_FFS); + if (ret || actual < size) { + printf("Failed to program flash: %d\n", ret); + return ret ?: -EIO; + } + return ret; +} + +U_BOOT_CMD(romupdate, 11, 0, do_update, + "Creates an FCB data structure and writes an U-Boot image to flash\n", + "[-b #] [-n #] [-f #] [-r [#]] [
] []\n" + "\t-b #\tfirst FCB block number (default 0)\n" + "\t-n #\ttotal number of FCB blocks (default 1)\n" + "\t-f #\twrite bootloader image at block #\n" + "\t-r\twrite redundant bootloader image at next free block after first image\n" + "\t-r #\twrite redundant bootloader image at block #\n" + "\t-e #\tspecify number of redundant blocks per boot loader image (default 2)\n" + "\t
\tRAM address of bootloader image (default: ${fileaddr}\n" + "\t\tlength of bootloader image in RAM (default: ${filesize}" + ); diff --git a/board/karo/tx28/spl_boot.c b/board/karo/tx28/spl_boot.c new file mode 100644 index 0000000000..58335ff6f0 --- /dev/null +++ b/board/karo/tx28/spl_boot.c @@ -0,0 +1,388 @@ +/* + * Copyright (C) 2011 Lothar Waßmann + * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#define MUX_CONFIG_LED (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA) +#define MUX_CONFIG_TSC (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP0 (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_EMI (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_GPIO (MXS_PAD_3V3 | MXS_PAD_PULLUP) + +static iomux_cfg_t tx28_stk5_pads[] = { + /* LED */ + MX28_PAD_ENET0_RXD3__GPIO_4_10 | MUX_CONFIG_LED, + + /* framebuffer */ + MX28_PAD_LCD_D00__LCD_D0 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D01__LCD_D1 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D02__LCD_D2 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D03__LCD_D3 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D04__LCD_D4 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D05__LCD_D5 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D06__LCD_D6 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D07__LCD_D7 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D08__LCD_D8 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D09__LCD_D9 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D18__LCD_D18 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D19__LCD_D19 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D20__LCD_D20 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D21__LCD_D21 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D22__LCD_D22 | MUX_CONFIG_LCD, + MX28_PAD_LCD_D23__LCD_D23 | MUX_CONFIG_LCD, + MX28_PAD_LCD_RD_E__LCD_VSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_RS__LCD_DOTCLK | MUX_CONFIG_LCD, + MX28_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD, + MX28_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_HSYNC__LCD_HSYNC | MUX_CONFIG_LCD, + MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MUX_CONFIG_LCD, + MX28_PAD_LCD_ENABLE__GPIO_1_31 | MUX_CONFIG_LCD, + MX28_PAD_LCD_RESET__GPIO_3_30 | MUX_CONFIG_LCD, + + /* DUART pads */ + MX28_PAD_PWM0__GPIO_3_16 | MUX_CONFIG_GPIO, + MX28_PAD_PWM1__GPIO_3_17 | MUX_CONFIG_GPIO, + MX28_PAD_I2C0_SCL__GPIO_3_24 | MUX_CONFIG_GPIO, + MX28_PAD_I2C0_SDA__GPIO_3_25 | MUX_CONFIG_GPIO, + + MX28_PAD_AUART0_RTS__DUART_TX, + MX28_PAD_AUART0_CTS__DUART_RX, + MX28_PAD_AUART0_TX__DUART_RTS, + MX28_PAD_AUART0_RX__DUART_CTS, + + /* EMI */ + MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, + MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, + + MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, + + /* FEC pads */ + MX28_PAD_PWM4__GPIO_3_29 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, + MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RX_EN__GPIO_4_2 | MUX_CONFIG_ENET, /* COL/CRS_DV/MODE2 */ + MX28_PAD_ENET0_RXD0__GPIO_4_3 | MUX_CONFIG_ENET, /* RXD0/MODE0 */ + MX28_PAD_ENET0_RXD1__GPIO_4_4 | MUX_CONFIG_ENET, /* RXD1/MODE1 */ + MX28_PAD_ENET0_TX_CLK__GPIO_4_5 | MUX_CONFIG_ENET, /* nINT/TX_ER/TXD4 */ + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, + + /* MMC pads */ + MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA1__SSP0_D1 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA2__SSP0_D2 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0, + MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT | MUX_CONFIG_GPIO, + MX28_PAD_SSP0_SCK__SSP0_SCK | MUX_CONFIG_SSP0, + + /* GPMI pads */ + MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDN__GPMI_RDN | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, + + /* maybe used for EDT-FT5x06 */ + MX28_PAD_SSP0_DATA5__GPIO_2_5 | MUX_CONFIG_GPIO, + MX28_PAD_SSP0_DATA6__GPIO_2_6 | MUX_CONFIG_GPIO, + MX28_PAD_ENET0_RXD2__GPIO_4_9 | MUX_CONFIG_GPIO, + + /* unused pads */ + MX28_PAD_GPMI_RDY1__GPIO_0_21 | MUX_CONFIG_GPIO, + MX28_PAD_GPMI_RDY2__GPIO_0_22 | MUX_CONFIG_GPIO, + MX28_PAD_GPMI_RDY3__GPIO_0_23 | MUX_CONFIG_GPIO, + MX28_PAD_GPMI_CE1N__GPIO_0_17 | MUX_CONFIG_GPIO, + MX28_PAD_GPMI_CE2N__GPIO_0_18 | MUX_CONFIG_GPIO, + MX28_PAD_GPMI_CE3N__GPIO_0_19 | MUX_CONFIG_GPIO, + + MX28_PAD_SSP0_DATA4__GPIO_2_4 | MUX_CONFIG_GPIO, + MX28_PAD_SSP0_DATA7__GPIO_2_7 | MUX_CONFIG_GPIO, + + MX28_PAD_SSP2_SS0__GPIO_2_19 | MUX_CONFIG_GPIO, + MX28_PAD_SSP2_SS1__GPIO_2_20 | MUX_CONFIG_GPIO, + MX28_PAD_SSP2_SS2__GPIO_2_21 | MUX_CONFIG_GPIO, + MX28_PAD_SSP3_SS0__GPIO_2_27 | MUX_CONFIG_GPIO, + + MX28_PAD_ENET0_TXD2__GPIO_4_11 | MUX_CONFIG_GPIO, + MX28_PAD_ENET0_TXD3__GPIO_4_12 | MUX_CONFIG_GPIO, + MX28_PAD_ENET0_CRS__GPIO_4_15 | MUX_CONFIG_GPIO, +}; + +static void tx28_stk5_lcd_init(void) +{ + gpio_direction_output(MX28_PAD_PWM0__GPIO_3_16, 1); + gpio_direction_output(MX28_PAD_LCD_RESET__GPIO_3_30, 0); + gpio_direction_output(MX28_PAD_LCD_ENABLE__GPIO_1_31, 0); +} + +static void tx28_stk5_led_on(void) +{ + gpio_direction_output(MX28_PAD_ENET0_RXD3__GPIO_4_10, 1); +} + +void board_init_ll(void) +{ + mxs_common_spl_init(tx28_stk5_pads, ARRAY_SIZE(tx28_stk5_pads)); + tx28_stk5_lcd_init(); + tx28_stk5_led_on(); +} + +static uint32_t tx28_dram_vals[] = { +#ifdef CONFIG_TX28_S + /* TX28-41x0: NT5TU32M16DG-AC */ + /* 000 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 010 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 020 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 030 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 040 */ 0x00000000, 0x00000100, 0x00000000, 0x00000000, + /* 050 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 060 */ 0x00000000, 0x00000000, 0x00010101, 0x00010101, + /* 070 */ 0x000f0f01, 0x0102010a, 0x00000000, 0x00000101, + /* 080 */ 0x00000100, 0x00000100, 0x00000000, 0x00000002, + /* 090 */ 0x01010000, 0x07080403, 0x06005003, 0x0a0000c8, + /* 0a0 */ 0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612, + /* 0b0 */ 0x02030202, 0x00c8001c, 0x00000000, 0x00000000, + /* 0c0 */ 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + /* 0d0 */ 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + /* 0e0 */ 0x00000003, 0x00000000, 0x00000000, 0x00000000, + /* 0f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 100 */ 0x00000000, 0x00000000, 0x00000612, 0x01000f02, + /* 110 */ 0x06120612, 0x00000200, 0x00020007, 0xf4004a27, + /* 120 */ 0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07400300, + /* 130 */ 0x07400300, 0x07400300, 0x07400300, 0x00000005, + /* 140 */ 0x00000000, 0x00000000, 0x01000000, 0x01020408, + /* 150 */ 0x08040201, 0x000f1133, 0x00000000, 0x00001f04, + /* 160 */ 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, + /* 170 */ 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000, + /* 180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 280 */ 0x00000000, 0x00000000, 0x00010000, 0x00030404, + /* 290 */ 0x00000003, 0x00000000, 0x00000000, 0x00000000, + /* 2a0 */ 0x00000000, 0x00000000, 0x00000000, 0x01010000, + /* 2b0 */ 0x01000000, 0x03030000, 0x00010303, 0x01020202, + /* 2c0 */ 0x00000000, 0x02040303, 0x21002103, 0x00061200, + /* 2d0 */ 0x06120612, 0x04420442, 0x04420442, 0x00040004, + /* 2e0 */ 0x00040004, 0x00000000, 0x00000000, 0x00000000, + /* 2f0 */ 0x00000000, 0x00000000, +#elif CONFIG_SDRAM_SIZE == SZ_128M + /* TX28-40x0: MT47H64M16HR-3 */ + /* 000 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 010 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 020 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 030 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 040 */ 0x00000000, 0x00000100, 0x00000000, 0x00000000, + /* 050 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 060 */ 0x00000000, 0x00000000, 0x00010101, 0x01010101, + /* 070 */ 0x000f0f01, 0x0102020a, 0x00000000, 0x00010101, + /* 080 */ 0x00000100, 0x00000100, 0x00000000, 0x00000002, + /* 090 */ 0x01010000, 0x07080403, 0x06005003, 0x0a0000c8, + /* 0a0 */ 0x02009c40, 0x0002030c, 0x0036a609, 0x031a0612, + /* 0b0 */ 0x02030202, 0x00c8001c, 0x00000000, 0x00000000, + /* 0c0 */ 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + /* 0d0 */ 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + /* 0e0 */ 0x00000003, 0x00000000, 0x00000000, 0x00000000, + /* 0f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 100 */ 0x00000000, 0x00000000, 0x00000612, 0x01000f02, + /* 110 */ 0x06120612, 0x00000200, 0x00020007, 0xf4004a27, + /* 120 */ 0xf4004a27, 0xf4004a27, 0xf4004a27, 0x07400300, + /* 130 */ 0x07400300, 0x07400300, 0x07400300, 0x00000005, + /* 140 */ 0x00000000, 0x00000000, 0x01000000, 0x01020408, + /* 150 */ 0x08040201, 0x000f1133, 0x00000000, 0x00001f04, + /* 160 */ 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, + /* 170 */ 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000, + /* 180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 280 */ 0x00000000, 0x00000000, 0x00010000, 0x00030404, + /* 290 */ 0x00000003, 0x00000000, 0x00000000, 0x00000000, + /* 2a0 */ 0x00000000, 0x00000000, 0x00000000, 0x01010000, + /* 2b0 */ 0x01000000, 0x03030000, 0x00010303, 0x01020202, + /* 2c0 */ 0x00000000, 0x02040303, 0x21002103, 0x00061200, + /* 2d0 */ 0x06120612, 0x04420442, 0x04420442, 0x00040004, + /* 2e0 */ 0x00040004, 0x00000000, 0x00000000, 0x00000000, + /* 2f0 */ 0x00000000, 0x00000000, +#elif CONFIG_SDRAM_SIZE == SZ_256M + /* TX28-40x2: MEM2G16D2DABG */ + /* 000 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 010 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 020 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 030 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 040 */ 0x00000000, 0x00000100, 0x00000000, 0x00000000, + /* 050 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 060 */ 0x00000000, 0x00000000, 0x00010101, 0x01010101, + /* 070 */ 0x000f0f01, 0x0102010a, 0x00000000, 0x00010101, + /* 080 */ 0x00000100, 0x00000100, 0x00000000, 0x00000002, + /* 090 */ 0x01010000, 0x07080603, 0x07005003, 0x0a0000c8, + /* 0a0 */ 0x02009c40, 0x0002030c, 0x00380e09, 0x0328063f, + /* 0b0 */ 0x02030202, 0x00c8001c, 0x00000000, 0x00000000, + /* 0c0 */ 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + /* 0d0 */ 0x00012100, 0xffff0303, 0x00012100, 0xffff0303, + /* 0e0 */ 0x00000003, 0x00000000, 0x00000000, 0x00000000, + /* 0f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 100 */ 0x00000000, 0x00000000, 0x00000612, 0x01000102, + /* 110 */ 0x06120612, 0x00000200, 0x00020007, 0xf4002714, + /* 120 */ 0xf4002714, 0xf4002714, 0xf4002714, 0x07400300, + /* 130 */ 0x07400300, 0x07400300, 0x07400300, 0x00000005, + /* 140 */ 0x00000000, 0x00000000, 0x01000000, 0x01020408, + /* 150 */ 0x08040201, 0x000f1133, 0x00000000, 0x00001f04, + /* 160 */ 0x00001f04, 0x00001f04, 0x00001f04, 0x00001f04, + /* 170 */ 0x00001f04, 0x00001f04, 0x00001f04, 0x00000000, + /* 180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 1f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 280 */ 0x00000000, 0x00000000, 0x00010000, 0x00030404, + /* 290 */ 0x00000003, 0x00000000, 0x00000000, 0x00000000, + /* 2a0 */ 0x00000000, 0x00000000, 0x00000000, 0x01010000, + /* 2b0 */ 0x01000000, 0x03030000, 0x00010303, 0x01020202, + /* 2c0 */ 0x00000000, 0x02040303, 0x21002103, 0x00061200, + /* 2d0 */ 0x06120612, 0x04420442, 0x04420442, 0x00040004, + /* 2e0 */ 0x00040004, 0x00000000, 0x00000000, 0x00000000, + /* 2f0 */ 0x00000000, 0x00000000, +#else +#error No SDRAM configuration available +#endif +}; + +void mxs_adjust_memory_params(uint32_t *dram_vals) +{ + memcpy(dram_vals, tx28_dram_vals, sizeof(tx28_dram_vals)); +} diff --git a/board/karo/tx28/tx28.c b/board/karo/tx28/tx28.c new file mode 100644 index 0000000000..622522dedc --- /dev/null +++ b/board/karo/tx28/tx28.c @@ -0,0 +1,806 @@ +/* + * Copyright (C) 2011 Lothar Waßmann + * based on: board/freesclae/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/karo.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define MXS_GPIO_NR(p, o) (((p) << 5) | (o)) + +#define TX28_LCD_PWR_GPIO MX28_PAD_LCD_ENABLE__GPIO_1_31 +#define TX28_LCD_RST_GPIO MX28_PAD_LCD_RESET__GPIO_3_30 +#define TX28_LCD_BACKLIGHT_GPIO MX28_PAD_PWM0__GPIO_3_16 + +#define TX28_USBH_VBUSEN_GPIO MX28_PAD_SPDIF__GPIO_3_27 +#define TX28_USBH_OC_GPIO MX28_PAD_JTAG_RTCK__GPIO_4_20 +#define TX28_USBOTG_VBUSEN_GPIO MX28_PAD_GPMI_CE2N__GPIO_0_18 +#define TX28_USBOTG_OC_GPIO MX28_PAD_GPMI_CE3N__GPIO_0_19 +#define TX28_USBOTG_ID_GPIO MX28_PAD_PWM2__GPIO_3_18 + +#define TX28_LED_GPIO MX28_PAD_ENET0_RXD3__GPIO_4_10 + +static const struct gpio tx28_gpios[] = { + { TX28_USBH_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBH VBUSEN", }, + { TX28_USBH_OC_GPIO, GPIOF_INPUT, "USBH OC", }, + { TX28_USBOTG_VBUSEN_GPIO, GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUSEN", }, + { TX28_USBOTG_OC_GPIO, GPIOF_INPUT, "USBOTG OC", }, + { TX28_USBOTG_ID_GPIO, GPIOF_INPUT, "USBOTG ID", }, +}; + +static const iomux_cfg_t tx28_pads[] = { + /* UART pads */ +#if CONFIG_CONS_INDEX == 0 + MX28_PAD_AUART0_RX__DUART_CTS, + MX28_PAD_AUART0_TX__DUART_RTS, + MX28_PAD_AUART0_CTS__DUART_RX, + MX28_PAD_AUART0_RTS__DUART_TX, +#elif CONFIG_CONS_INDEX == 1 + MX28_PAD_AUART1_RX__AUART1_RX, + MX28_PAD_AUART1_TX__AUART1_TX, + MX28_PAD_AUART1_CTS__AUART1_CTS, + MX28_PAD_AUART1_RTS__AUART1_RTS, +#elif CONFIG_CONS_INDEX == 2 + MX28_PAD_AUART3_RX__AUART3_RX, + MX28_PAD_AUART3_TX__AUART3_TX, + MX28_PAD_AUART3_CTS__AUART3_CTS, + MX28_PAD_AUART3_RTS__AUART3_RTS, +#endif + /* I2C bus for internal DS1339, PCA9554 and on DIMM pins 40/41 */ + MX28_PAD_I2C0_SCL__I2C0_SCL, + MX28_PAD_I2C0_SDA__I2C0_SDA, + + /* USBH VBUSEN, OC */ + MX28_PAD_SPDIF__GPIO_3_27, + MX28_PAD_JTAG_RTCK__GPIO_4_20, + + /* USBOTG VBUSEN, OC, ID */ + MX28_PAD_GPMI_CE2N__GPIO_0_18, + MX28_PAD_GPMI_CE3N__GPIO_0_19, + MX28_PAD_PWM2__GPIO_3_18, +}; + +/* + * Functions + */ + +/* provide at least _some_ sort of randomness */ +#define MAX_LOOPS 100 + +static u32 random; + +static inline void random_init(void) +{ + struct mxs_digctl_regs *digctl_regs = (void *)MXS_DIGCTL_BASE; + u32 seed = 0; + int i; + + for (i = 0; i < MAX_LOOPS; i++) { + unsigned int usec = readl(&digctl_regs->hw_digctl_microseconds); + + seed = get_timer(usec + random + seed); + srand(seed); + random = rand(); + } +} + +int board_early_init_f(void) +{ + random_init(); + + /* IO0 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK0, 480000); + /* IO1 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK1, 480000); + + /* SSP0 clock at 96MHz */ + mxs_set_sspclk(MXC_SSPCLK0, 96000, 0); + /* SSP2 clock at 96MHz */ + mxs_set_sspclk(MXC_SSPCLK2, 96000, 0); + + gpio_request_array(tx28_gpios, ARRAY_SIZE(tx28_gpios)); + mxs_iomux_setup_multiple_pads(tx28_pads, ARRAY_SIZE(tx28_pads)); + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ +#ifdef CONFIG_OF_LIBFDT + gd->bd->bi_arch_number = -1; +#endif + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000; + return 0; +} + +int dram_init(void) +{ + return mxs_dram_init(); +} + +#ifdef CONFIG_CMD_MMC +static int tx28_mmc_wp(int dev_no) +{ + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + return mxsmmc_initialize(bis, 0, tx28_mmc_wp, NULL); +} +#endif /* CONFIG_CMD_MMC */ + +#ifdef CONFIG_FEC_MXC +#ifdef CONFIG_GET_FEC_MAC_ADDR_FROM_IIM + +#ifdef CONFIG_FEC_MXC_MULTI +#define FEC_MAX_IDX 1 +#else +#define FEC_MAX_IDX 0 +#endif +#ifndef ETH_ALEN +#define ETH_ALEN 6 +#endif + +static int fec_get_mac_addr(int index) +{ + int timeout = 1000; + struct mxs_ocotp_regs *ocotp_regs = + (struct mxs_ocotp_regs *)MXS_OCOTP_BASE; + u32 *cust = &ocotp_regs->hw_ocotp_cust0; + u8 mac[ETH_ALEN]; + char env_name[] = "eth.addr"; + u32 val = 0; + int i; + + if (index < 0 || index > FEC_MAX_IDX) + return -EINVAL; + + /* set this bit to open the OTP banks for reading */ + writel(OCOTP_CTRL_RD_BANK_OPEN, + &ocotp_regs->hw_ocotp_ctrl_set); + + /* wait until OTP contents are readable */ + while (OCOTP_CTRL_BUSY & readl(&ocotp_regs->hw_ocotp_ctrl)) { + if (timeout-- < 0) + return -ETIMEDOUT; + udelay(100); + } + + for (i = 0; i < sizeof(mac); i++) { + int shift = 24 - i % 4 * 8; + + if (i % 4 == 0) + val = readl(&cust[index * 8 + i]); + mac[i] = val >> shift; + } + if (!is_valid_ether_addr(mac)) + return 0; + + if (index == 0) + snprintf(env_name, sizeof(env_name), "ethaddr"); + else + snprintf(env_name, sizeof(env_name), "eth%daddr", index); + + eth_setenv_enetaddr(env_name, mac); + return 0; +} +#endif /* CONFIG_GET_FEC_MAC_ADDR_FROM_IIM */ + +static const iomux_cfg_t tx28_fec_pads[] = { + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN, + MX28_PAD_ENET0_RXD0__ENET0_RXD0, + MX28_PAD_ENET0_RXD1__ENET0_RXD1, +}; + +int board_eth_init(bd_t *bis) +{ + int ret; + + /* Reset the external phy */ + gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0); + + /* Power on the external phy */ + gpio_direction_output(MX28_PAD_PWM4__GPIO_3_29, 1); + + /* Pull strap pins to high */ + gpio_direction_output(MX28_PAD_ENET0_RX_EN__GPIO_4_2, 1); + gpio_direction_output(MX28_PAD_ENET0_RXD0__GPIO_4_3, 1); + gpio_direction_output(MX28_PAD_ENET0_RXD1__GPIO_4_4, 1); + gpio_direction_input(MX28_PAD_ENET0_TX_CLK__GPIO_4_5); + + udelay(25000); + gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1); + udelay(100); + + mxs_iomux_setup_multiple_pads(tx28_fec_pads, ARRAY_SIZE(tx28_fec_pads)); + + ret = cpu_eth_init(bis); + if (ret) { + printf("cpu_eth_init() failed: %d\n", ret); + return ret; + } + + ret = fec_get_mac_addr(0); + if (ret < 0) { + printf("Failed to read FEC0 MAC address from OCOTP\n"); + return ret; + } +#ifdef CONFIG_FEC_MXC_MULTI + if (getenv("ethaddr")) { + ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); + if (ret) { + printf("FEC MXS: Unable to init FEC0\n"); + return ret; + } + } + + ret = fec_get_mac_addr(1); + if (ret < 0) { + printf("Failed to read FEC1 MAC address from OCOTP\n"); + return ret; + } + if (getenv("eth1addr")) { + ret = fecmxc_initialize_multi(bis, 1, 1, MXS_ENET1_BASE); + if (ret) { + printf("FEC MXS: Unable to init FEC1\n"); + return ret; + } + } + return 0; +#else + if (getenv("ethaddr")) { + ret = fecmxc_initialize(bis); + } + return ret; +#endif +} +#endif /* CONFIG_FEC_MXC */ + +enum { + LED_STATE_INIT = -1, + LED_STATE_OFF, + LED_STATE_ON, +}; + +void show_activity(int arg) +{ + static int led_state = LED_STATE_INIT; + static ulong last; + + if (led_state == LED_STATE_INIT) { + last = get_timer(0); + gpio_set_value(TX28_LED_GPIO, 1); + led_state = LED_STATE_ON; + } else { + if (get_timer(last) > CONFIG_SYS_HZ) { + last = get_timer(0); + if (led_state == LED_STATE_ON) { + gpio_set_value(TX28_LED_GPIO, 0); + } else { + gpio_set_value(TX28_LED_GPIO, 1); + } + led_state = 1 - led_state; + } + } +} + +static const iomux_cfg_t stk5_pads[] = { + /* SW controlled LED on STK5 baseboard */ + MX28_PAD_ENET0_RXD3__GPIO_4_10, +}; + +static const struct gpio stk5_gpios[] = { +}; + +#ifdef CONFIG_LCD +static ushort tx28_cmap[256]; +vidinfo_t panel_info = { + /* set to max. size supported by SoC */ + .vl_col = 1600, + .vl_row = 1200, + + .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ + .cmap = tx28_cmap, +}; + +static struct fb_videomode tx28_fb_modes[] = { + { + /* Standard VGA timing */ + .name = "VGA", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = KHZ2PICOS(25175), + .left_margin = 48, + .hsync_len = 96, + .right_margin = 16, + .upper_margin = 31, + .vsync_len = 2, + .lower_margin = 12, + .vmode = FB_VMODE_NONINTERLACED, + }, + { + /* Emerging ETV570 640 x 480 display. Syncs low active, + * DE high active, 115.2 mm x 86.4 mm display area + * VGA compatible timing + */ + .name = "ETV570", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = KHZ2PICOS(25175), + .left_margin = 114, + .hsync_len = 30, + .right_margin = 16, + .upper_margin = 32, + .vsync_len = 3, + .lower_margin = 10, + .vmode = FB_VMODE_NONINTERLACED, + }, + { + /* Emerging ET0350G0DH6 320 x 240 display. + * 70.08 mm x 52.56 mm display area. + */ + .name = "ET0350", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = KHZ2PICOS(6500), + .left_margin = 68 - 34, + .hsync_len = 34, + .right_margin = 20, + .upper_margin = 18 - 3, + .vsync_len = 3, + .lower_margin = 4, + .vmode = FB_VMODE_NONINTERLACED, + }, + { + /* Emerging ET0430G0DH6 480 x 272 display. + * 95.04 mm x 53.856 mm display area. + */ + .name = "ET0430", + .refresh = 60, + .xres = 480, + .yres = 272, + .pixclock = KHZ2PICOS(9000), + .left_margin = 2, + .hsync_len = 41, + .right_margin = 2, + .upper_margin = 2, + .vsync_len = 10, + .lower_margin = 2, + .vmode = FB_VMODE_NONINTERLACED, + }, + { + /* Emerging ET0500G0DH6 800 x 480 display. + * 109.6 mm x 66.4 mm display area. + */ + .name = "ET0500", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = KHZ2PICOS(33260), + .left_margin = 216 - 128, + .hsync_len = 128, + .right_margin = 1056 - 800 - 216, + .upper_margin = 35 - 2, + .vsync_len = 2, + .lower_margin = 525 - 480 - 35, + .vmode = FB_VMODE_NONINTERLACED, + }, + { + /* Emerging ETQ570G0DH6 320 x 240 display. + * 115.2 mm x 86.4 mm display area. + */ + .name = "ETQ570", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = KHZ2PICOS(6400), + .left_margin = 38, + .hsync_len = 30, + .right_margin = 30, + .upper_margin = 16, /* 15 according to datasheet */ + .vsync_len = 3, /* TVP -> 1>x>5 */ + .lower_margin = 4, /* 4.5 according to datasheet */ + .vmode = FB_VMODE_NONINTERLACED, + }, + { + /* Emerging ET0700G0DH6 800 x 480 display. + * 152.4 mm x 91.44 mm display area. + */ + .name = "ET0700", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = KHZ2PICOS(33260), + .left_margin = 216 - 128, + .hsync_len = 128, + .right_margin = 1056 - 800 - 216, + .upper_margin = 35 - 2, + .vsync_len = 2, + .lower_margin = 525 - 480 - 35, + .vmode = FB_VMODE_NONINTERLACED, + }, + { + /* unnamed entry for assigning parameters parsed from 'video_mode' string */ + .vmode = FB_VMODE_NONINTERLACED, + }, +}; + +static int lcd_enabled = 1; + +void lcd_enable(void) +{ + /* HACK ALERT: + * global variable from common/lcd.c + * Set to 0 here to prevent messages from going to LCD + * rather than serial console + */ + lcd_is_enabled = 0; + + karo_load_splashimage(1); + if (lcd_enabled) { + debug("Switching LCD on\n"); + gpio_set_value(TX28_LCD_PWR_GPIO, 1); + udelay(100); + gpio_set_value(TX28_LCD_RST_GPIO, 1); + udelay(300000); + gpio_set_value(TX28_LCD_BACKLIGHT_GPIO, 0); + } +} + +void lcd_disable(void) +{ +} + +void lcd_panel_disable(void) +{ + if (lcd_enabled) { + debug("Switching LCD off\n"); + gpio_set_value(TX28_LCD_BACKLIGHT_GPIO, 1); + gpio_set_value(TX28_LCD_RST_GPIO, 0); + gpio_set_value(TX28_LCD_PWR_GPIO, 0); + } +} + +static const iomux_cfg_t stk5_lcd_pads[] = { + /* LCD RESET */ + MX28_PAD_LCD_RESET__GPIO_3_30 | MXS_PAD_CTRL, + /* LCD POWER_ENABLE */ + MX28_PAD_LCD_ENABLE__GPIO_1_31 | MXS_PAD_CTRL, + /* LCD Backlight (PWM) */ + MX28_PAD_PWM0__GPIO_3_16 | MXS_PAD_CTRL, + + /* Display */ + MX28_PAD_LCD_D00__LCD_D0 | MXS_PAD_CTRL, + MX28_PAD_LCD_D01__LCD_D1 | MXS_PAD_CTRL, + MX28_PAD_LCD_D02__LCD_D2 | MXS_PAD_CTRL, + MX28_PAD_LCD_D03__LCD_D3 | MXS_PAD_CTRL, + MX28_PAD_LCD_D04__LCD_D4 | MXS_PAD_CTRL, + MX28_PAD_LCD_D05__LCD_D5 | MXS_PAD_CTRL, + MX28_PAD_LCD_D06__LCD_D6 | MXS_PAD_CTRL, + MX28_PAD_LCD_D07__LCD_D7 | MXS_PAD_CTRL, + MX28_PAD_LCD_D08__LCD_D8 | MXS_PAD_CTRL, + MX28_PAD_LCD_D09__LCD_D9 | MXS_PAD_CTRL, + MX28_PAD_LCD_D10__LCD_D10 | MXS_PAD_CTRL, + MX28_PAD_LCD_D11__LCD_D11 | MXS_PAD_CTRL, + MX28_PAD_LCD_D12__LCD_D12 | MXS_PAD_CTRL, + MX28_PAD_LCD_D13__LCD_D13 | MXS_PAD_CTRL, + MX28_PAD_LCD_D14__LCD_D14 | MXS_PAD_CTRL, + MX28_PAD_LCD_D15__LCD_D15 | MXS_PAD_CTRL, + MX28_PAD_LCD_D16__LCD_D16 | MXS_PAD_CTRL, + MX28_PAD_LCD_D17__LCD_D17 | MXS_PAD_CTRL, + MX28_PAD_LCD_D18__LCD_D18 | MXS_PAD_CTRL, + MX28_PAD_LCD_D19__LCD_D19 | MXS_PAD_CTRL, + MX28_PAD_LCD_D20__LCD_D20 | MXS_PAD_CTRL, + MX28_PAD_LCD_D21__LCD_D21 | MXS_PAD_CTRL, + MX28_PAD_LCD_D22__LCD_D22 | MXS_PAD_CTRL, + MX28_PAD_LCD_D23__LCD_D23 | MXS_PAD_CTRL, + MX28_PAD_LCD_RD_E__LCD_VSYNC | MXS_PAD_CTRL, + MX28_PAD_LCD_WR_RWN__LCD_HSYNC | MXS_PAD_CTRL, + MX28_PAD_LCD_RS__LCD_DOTCLK | MXS_PAD_CTRL, + MX28_PAD_LCD_CS__LCD_CS | MXS_PAD_CTRL, + MX28_PAD_LCD_VSYNC__LCD_VSYNC | MXS_PAD_CTRL, + MX28_PAD_LCD_HSYNC__LCD_HSYNC | MXS_PAD_CTRL, + MX28_PAD_LCD_DOTCLK__LCD_DOTCLK | MXS_PAD_CTRL, +}; + +static const struct gpio stk5_lcd_gpios[] = { + { TX28_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", }, + { TX28_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", }, + { TX28_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, +}; + +extern void video_hw_init(void *lcdbase); + +void lcd_ctrl_init(void *lcdbase) +{ + int color_depth = 24; + char *vm; + unsigned long val; + int refresh = 60; + struct fb_videomode *p = tx28_fb_modes; + struct fb_videomode fb_mode; + int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0; + + if (!lcd_enabled) { + debug("LCD disabled\n"); + return; + } + + if (tstc()) { + debug("Disabling LCD\n"); + lcd_enabled = 0; + return; + } + + karo_fdt_move_fdt(); + + vm = getenv("video_mode"); + if (vm == NULL) { + debug("Disabling LCD\n"); + lcd_enabled = 0; + return; + } + if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) { + p = &fb_mode; + debug("Using video mode from FDT\n"); + vm += strlen(vm); + } + if (p->name != NULL) + debug("Trying compiled-in video modes\n"); + while (p->name != NULL) { + if (strcmp(p->name, vm) == 0) { + debug("Using video mode: '%s'\n", p->name); + vm += strlen(vm); + break; + } + p++; + } + if (*vm != '\0') + debug("Trying to decode video_mode: '%s'\n", vm); + while (*vm != '\0') { + if (*vm >= '0' && *vm <= '9') { + char *end; + + val = simple_strtoul(vm, &end, 0); + if (end > vm) { + if (!xres_set) { + if (val > panel_info.vl_col) + val = panel_info.vl_col; + p->xres = val; + xres_set = 1; + } else if (!yres_set) { + if (val > panel_info.vl_row) + val = panel_info.vl_row; + p->yres = val; + yres_set = 1; + } else if (!bpp_set) { + switch (val) { + case 8: + case 16: + case 18: + case 24: + color_depth = val; + break; + + default: + printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n", + end - vm, vm, color_depth); + } + bpp_set = 1; + } else if (!refresh_set) { + refresh = val; + refresh_set = 1; + } + } + vm = end; + } + switch (*vm) { + case '@': + bpp_set = 1; + /* fallthru */ + case '-': + yres_set = 1; + /* fallthru */ + case 'x': + xres_set = 1; + /* fallthru */ + case 'M': + case 'R': + vm++; + break; + + default: + if (*vm != '\0') + vm++; + } + } + if (p->xres == 0 || p->yres == 0) { + printf("Invalid video mode: %s\n", getenv("video_mode")); + lcd_enabled = 0; + printf("Supported video modes are:"); + for (p = &tx28_fb_modes[0]; p->name != NULL; p++) { + printf(" %s", p->name); + } + printf("\n"); + return; + } + p->pixclock = KHZ2PICOS(refresh * + (p->xres + p->left_margin + p->right_margin + p->hsync_len) * + (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) / + 1000); + debug("Pixel clock set to %lu.%03lu MHz\n", + PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000); + + gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios)); + mxs_iomux_setup_multiple_pads(stk5_lcd_pads, + ARRAY_SIZE(stk5_lcd_pads)); + + debug("video format: %ux%u-%u@%u\n", p->xres, p->yres, + color_depth, refresh); + + if (karo_load_splashimage(0) == 0) { + debug("Initializing LCD controller\n"); + video_hw_init(lcdbase); + } else { + debug("Skipping initialization of LCD controller\n"); + } +} +#else +#define lcd_enabled 0 +#endif /* CONFIG_LCD */ + +static void stk5_board_init(void) +{ + gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios)); + mxs_iomux_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads)); +} + +static void stk5v3_board_init(void) +{ + stk5_board_init(); +} + +static void stk5v5_board_init(void) +{ + stk5_board_init(); + + /* init flexcan transceiver enable GPIO */ + gpio_request_one(MXS_GPIO_NR(0, 1), GPIOF_OUTPUT_INIT_HIGH, + "Flexcan Transceiver"); + mxs_iomux_setup_pad(MX28_PAD_LCD_D00__GPIO_1_0); +} + +int board_late_init(void) +{ + const char *baseboard; + + karo_fdt_move_fdt(); + + baseboard = getenv("baseboard"); + if (!baseboard) + return 0; + + if (strncmp(baseboard, "stk5", 4) == 0) { + printf("Baseboard: %s\n", baseboard); + if ((strlen(baseboard) == 4) || + strcmp(baseboard, "stk5-v3") == 0) { + stk5v3_board_init(); + } else if (strcmp(baseboard, "stk5-v5") == 0) { + const char *otg_mode = getenv("otg_mode"); + + if (otg_mode && strcmp(otg_mode, "host") == 0) { + printf("otg_mode='%s' is incompatible with baseboard %s; setting to 'none'\n", + otg_mode, baseboard); + setenv("otg_mode", "none"); + } + stk5v5_board_init(); + } else { + printf("WARNING: Unsupported STK5 board rev.: %s\n", + baseboard + 4); + } + } else { + printf("WARNING: Unsupported baseboard: '%s'\n", + baseboard); + return -EINVAL; + } + + return 0; +} + +int checkboard(void) +{ + printf("Board: Ka-Ro TX28-4%sxx\n", TX28_MOD_SUFFIX); + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_FDT_FIXUP_PARTITIONS +#include +#include +struct node_info tx28_nand_nodes[] = { + { "gpmi-nand", MTD_DEV_TYPE_NAND, }, +}; +#else +#define fdt_fixup_mtdparts(b,n,c) do { } while (0) +#endif + +static void tx28_fixup_flexcan(void *blob) +{ + karo_fdt_del_prop(blob, "fsl,imx28-flexcan", 0x80032000, "transceiver-switch"); + karo_fdt_del_prop(blob, "fsl,imx28-flexcan", 0x80034000, "transceiver-switch"); +} + +static void tx28_fixup_fec(void *blob) +{ + karo_fdt_enable_node(blob, "ethernet1", 0); +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + const char *baseboard = getenv("baseboard"); + +#ifdef CONFIG_TX28_S + /* TX28-41xx (aka TX28S) has no external RTC + * and no I2C GPIO extender + */ + karo_fdt_remove_node(blob, "ds1339"); + karo_fdt_remove_node(blob, "gpio5"); +#endif + if (baseboard != NULL && strcmp(baseboard, "stk5-v5") == 0) { + karo_fdt_remove_node(blob, "stk5led"); + } else { + tx28_fixup_flexcan(blob); + tx28_fixup_fec(blob); + } + + if (baseboard != NULL && strcmp(baseboard, "stk5-v3") == 0) { + const char *otg_mode = getenv("otg_mode"); + + if (otg_mode && (strcmp(otg_mode, "device") == 0 || + strcmp(otg_mode, "gadget") == 0)) + karo_fdt_enable_node(blob, "can1", 0); + } + + fdt_fixup_mtdparts(blob, tx28_nand_nodes, ARRAY_SIZE(tx28_nand_nodes)); + fdt_fixup_ethernet(blob); + + karo_fdt_fixup_touchpanel(blob); + karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy"); + karo_fdt_update_fb_mode(blob, getenv("video_mode")); +} +#endif diff --git a/board/karo/tx28/u-boot.bd b/board/karo/tx28/u-boot.bd new file mode 100644 index 0000000000..bbf6658107 --- /dev/null +++ b/board/karo/tx28/u-boot.bd @@ -0,0 +1,14 @@ +sources { + u_boot_spl="@@BUILD_DIR@@spl/u-boot-spl"; + u_boot="@@BUILD_DIR@@u-boot"; +} + +section (0) { + load u_boot_spl; + load ivt (entry = u_boot_spl:reset) > 0x8000; + hab call 0x8000; + + load u_boot; + load ivt (entry = u_boot:reset) > 0x8000; + hab call 0x8000; +} diff --git a/board/karo/tx48/Makefile b/board/karo/tx48/Makefile new file mode 100644 index 0000000000..685af9de56 --- /dev/null +++ b/board/karo/tx48/Makefile @@ -0,0 +1,46 @@ +# +# Makefile +# +# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation version 2. +# +# This program is distributed "as is" WITHOUT ANY WARRANTY of any +# kind, whether express or implied; without even the implied warranty +# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +ifeq ($(CONFIG_SPL_BUILD),) + COBJS := tx48.o +else + COBJS := spl.o +endif + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/karo/tx48/config.mk b/board/karo/tx48/config.mk new file mode 100644 index 0000000000..51490f0d3b --- /dev/null +++ b/board/karo/tx48/config.mk @@ -0,0 +1,7 @@ +CONFIG_SYS_TEXT_BASE = 0x80800000 +ifneq ($(CONFIG_SPL_BUILD),) + CONFIG_SPL_TEXT_BASE = 0x402F0400 +endif +PLATFORM_CPPFLAGS += -Werror + +LOGO_BMP = logos/karo.bmp diff --git a/board/karo/tx48/spl.c b/board/karo/tx48/spl.c new file mode 100644 index 0000000000..38352627dc --- /dev/null +++ b/board/karo/tx48/spl.c @@ -0,0 +1,721 @@ +/* + * board/karo/tx48/spl.c + * Copyright (C) 2012 Lothar Waßmann + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define TX48_LED_GPIO AM33XX_GPIO_NR(1, 26) +#define TX48_ETH_PHY_RST_GPIO AM33XX_GPIO_NR(3, 8) +#define TX48_LCD_RST_GPIO AM33XX_GPIO_NR(1, 19) +#define TX48_LCD_PWR_GPIO AM33XX_GPIO_NR(1, 22) +#define TX48_LCD_BACKLIGHT_GPIO AM33XX_GPIO_NR(3, 14) + +#define GMII_SEL (CTRL_BASE + 0x650) + +/* UART Defines */ +#define UART_SYSCFG_OFFSET 0x54 +#define UART_SYSSTS_OFFSET 0x58 + +#define UART_RESET (0x1 << 1) +#define UART_RESETDONE (1 << 0) +#define UART_IDLE_MODE(m) (((m) << 3) & UART_IDLE_MODE_MASK) +#define UART_IDLE_MODE_MASK (0x3 << 3) + +/* Timer Defines */ +#define TSICR_REG 0x54 +#define TIOCP_CFG_REG 0x10 +#define TCLR_REG 0x38 + +/* RGMII mode define */ +#define RGMII_MODE_ENABLE 0xA +#define RMII_MODE_ENABLE 0x5 +#define MII_MODE_ENABLE 0x0 + +#define NO_OF_MAC_ADDR 1 +#define ETH_ALEN 6 + +#define MUX_CFG(value, offset) { \ + __raw_writel(value, (CTRL_BASE + (offset))); \ + } + +/* PAD Control Fields */ +#define SLEWCTRL (0x1 << 6) +#define RXACTIVE (0x1 << 5) +#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */ +#define PULLUDEN (0x0 << 3) /* Pull up enabled */ +#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ +#define MODE(val) (val) + +DECLARE_GLOBAL_DATA_PTR; + +/* + * PAD CONTROL OFFSETS + * Field names corresponds to the pad signal name + */ +struct pad_signals { + int gpmc_ad0; + int gpmc_ad1; + int gpmc_ad2; + int gpmc_ad3; + int gpmc_ad4; + int gpmc_ad5; + int gpmc_ad6; + int gpmc_ad7; + int gpmc_ad8; + int gpmc_ad9; + int gpmc_ad10; + int gpmc_ad11; + int gpmc_ad12; + int gpmc_ad13; + int gpmc_ad14; + int gpmc_ad15; + int gpmc_a0; + int gpmc_a1; + int gpmc_a2; + int gpmc_a3; + int gpmc_a4; + int gpmc_a5; + int gpmc_a6; + int gpmc_a7; + int gpmc_a8; + int gpmc_a9; + int gpmc_a10; + int gpmc_a11; + int gpmc_wait0; + int gpmc_wpn; + int gpmc_be1n; + int gpmc_csn0; + int gpmc_csn1; + int gpmc_csn2; + int gpmc_csn3; + int gpmc_clk; + int gpmc_advn_ale; + int gpmc_oen_ren; + int gpmc_wen; + int gpmc_be0n_cle; + int lcd_data0; + int lcd_data1; + int lcd_data2; + int lcd_data3; + int lcd_data4; + int lcd_data5; + int lcd_data6; + int lcd_data7; + int lcd_data8; + int lcd_data9; + int lcd_data10; + int lcd_data11; + int lcd_data12; + int lcd_data13; + int lcd_data14; + int lcd_data15; + int lcd_vsync; + int lcd_hsync; + int lcd_pclk; + int lcd_ac_bias_en; + int mmc0_dat3; + int mmc0_dat2; + int mmc0_dat1; + int mmc0_dat0; + int mmc0_clk; + int mmc0_cmd; + int mii1_col; + int mii1_crs; + int mii1_rxerr; + int mii1_txen; + int mii1_rxdv; + int mii1_txd3; + int mii1_txd2; + int mii1_txd1; + int mii1_txd0; + int mii1_txclk; + int mii1_rxclk; + int mii1_rxd3; + int mii1_rxd2; + int mii1_rxd1; + int mii1_rxd0; + int rmii1_refclk; + int mdio_data; + int mdio_clk; + int spi0_sclk; + int spi0_d0; + int spi0_d1; + int spi0_cs0; + int spi0_cs1; + int ecap0_in_pwm0_out; + int uart0_ctsn; + int uart0_rtsn; + int uart0_rxd; + int uart0_txd; + int uart1_ctsn; + int uart1_rtsn; + int uart1_rxd; + int uart1_txd; + int i2c0_sda; + int i2c0_scl; + int mcasp0_aclkx; + int mcasp0_fsx; + int mcasp0_axr0; + int mcasp0_ahclkr; + int mcasp0_aclkr; + int mcasp0_fsr; + int mcasp0_axr1; + int mcasp0_ahclkx; + int xdma_event_intr0; + int xdma_event_intr1; + int nresetin_out; + int porz; + int nnmi; + int osc0_in; + int osc0_out; + int rsvd1; + int tms; + int tdi; + int tdo; + int tck; + int ntrst; + int emu0; + int emu1; + int osc1_in; + int osc1_out; + int pmic_power_en; + int rtc_porz; + int rsvd2; + int ext_wakeup; + int enz_kaldo_1p8v; + int usb0_dm; + int usb0_dp; + int usb0_ce; + int usb0_id; + int usb0_vbus; + int usb0_drvvbus; + int usb1_dm; + int usb1_dp; + int usb1_ce; + int usb1_id; + int usb1_vbus; + int usb1_drvvbus; + int ddr_resetn; + int ddr_csn0; + int ddr_cke; + int ddr_ck; + int ddr_nck; + int ddr_casn; + int ddr_rasn; + int ddr_wen; + int ddr_ba0; + int ddr_ba1; + int ddr_ba2; + int ddr_a0; + int ddr_a1; + int ddr_a2; + int ddr_a3; + int ddr_a4; + int ddr_a5; + int ddr_a6; + int ddr_a7; + int ddr_a8; + int ddr_a9; + int ddr_a10; + int ddr_a11; + int ddr_a12; + int ddr_a13; + int ddr_a14; + int ddr_a15; + int ddr_odt; + int ddr_d0; + int ddr_d1; + int ddr_d2; + int ddr_d3; + int ddr_d4; + int ddr_d5; + int ddr_d6; + int ddr_d7; + int ddr_d8; + int ddr_d9; + int ddr_d10; + int ddr_d11; + int ddr_d12; + int ddr_d13; + int ddr_d14; + int ddr_d15; + int ddr_dqm0; + int ddr_dqm1; + int ddr_dqs0; + int ddr_dqsn0; + int ddr_dqs1; + int ddr_dqsn1; + int ddr_vref; + int ddr_vtp; + int ddr_strben0; + int ddr_strben1; + int ain7; + int ain6; + int ain5; + int ain4; + int ain3; + int ain2; + int ain1; + int ain0; + int vrefp; + int vrefn; +}; + +struct pin_mux { + short reg_offset; + uint8_t val; +}; + +#define PAD_CTRL_BASE 0x800 +#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \ + (PAD_CTRL_BASE))->x) + +static struct pin_mux tx48_pins[] = { +#ifdef CONFIG_CMD_NAND + { OFFSET(gpmc_ad0), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD0 */ + { OFFSET(gpmc_ad1), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD1 */ + { OFFSET(gpmc_ad2), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD2 */ + { OFFSET(gpmc_ad3), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD3 */ + { OFFSET(gpmc_ad4), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD4 */ + { OFFSET(gpmc_ad5), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD5 */ + { OFFSET(gpmc_ad6), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD6 */ + { OFFSET(gpmc_ad7), MODE(0) | PULLUP_EN | RXACTIVE, }, /* NAND AD7 */ + { OFFSET(gpmc_wait0), MODE(0) | RXACTIVE | PULLUP_EN, }, /* NAND WAIT */ + { OFFSET(gpmc_wpn), MODE(7) | PULLUP_EN | RXACTIVE, }, /* NAND_WPN */ + { OFFSET(gpmc_csn0), MODE(0) | PULLUDEN, }, /* NAND_CS0 */ + { OFFSET(gpmc_advn_ale), MODE(0) | PULLUDEN, }, /* NAND_ADV_ALE */ + { OFFSET(gpmc_oen_ren), MODE(0) | PULLUDEN, }, /* NAND_OE */ + { OFFSET(gpmc_wen), MODE(0) | PULLUDEN, }, /* NAND_WEN */ + { OFFSET(gpmc_be0n_cle), MODE(0) | PULLUDEN, }, /* NAND_BE_CLE */ +#endif + /* I2C0 */ + { OFFSET(i2c0_sda), MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, }, /* I2C_DATA */ + { OFFSET(i2c0_scl), MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL, }, /* I2C_SCLK */ + +#ifndef CONFIG_NO_ETH + /* RMII1 */ + { OFFSET(mii1_crs), MODE(1) | RXACTIVE, }, /* RMII1_CRS */ + { OFFSET(mii1_rxerr), MODE(1) | RXACTIVE | PULLUDEN, }, /* RMII1_RXERR */ + { OFFSET(mii1_txen), MODE(1), }, /* RMII1_TXEN */ + { OFFSET(mii1_txd1), MODE(1), }, /* RMII1_TXD1 */ + { OFFSET(mii1_txd0), MODE(1), }, /* RMII1_TXD0 */ + { OFFSET(mii1_rxd1), MODE(1) | RXACTIVE | PULLUP_EN, }, /* RMII1_RXD1 */ + { OFFSET(mii1_rxd0), MODE(1) | RXACTIVE | PULLUP_EN, }, /* RMII1_RXD0 */ + { OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN, }, /* MDIO_DATA */ + { OFFSET(mdio_clk), MODE(0) | PULLUP_EN, }, /* MDIO_CLK */ + { OFFSET(rmii1_refclk), MODE(0) | RXACTIVE, }, /* RMII1_REFCLK */ + { OFFSET(emu0), MODE(7) | RXACTIVE}, /* nINT */ + { OFFSET(emu1), MODE(7), }, /* nRST */ +#endif +}; + +static struct gpio tx48_gpios[] = { + /* configure this pin early to prevent flicker of the LCD */ + { TX48_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, +}; + +static struct pin_mux tx48_mmc_pins[] = { +#ifdef CONFIG_OMAP_HSMMC + /* MMC1 */ + { OFFSET(mii1_rxd2), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT3 */ + { OFFSET(mii1_rxd3), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT2 */ + { OFFSET(mii1_rxclk), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT1 */ + { OFFSET(mii1_txclk), MODE(4) | RXACTIVE | PULLUP_EN, }, /* MMC1_DAT0 */ + { OFFSET(gpmc_csn1), MODE(2) | RXACTIVE | PULLUP_EN, }, /* MMC1_CLK */ + { OFFSET(gpmc_csn2), MODE(2) | RXACTIVE | PULLUP_EN, }, /* MMC1_CMD */ + { OFFSET(mcasp0_fsx), MODE(4) | RXACTIVE, }, /* MMC1_CD */ +#endif +}; + +/* + * Configure the pin mux for the module + */ +static inline void tx48_set_pin_mux(const struct pin_mux *pin_mux, + int num_pins) +{ + int i; + + for (i = 0; i < num_pins; i++) + MUX_CFG(pin_mux[i].val, pin_mux[i].reg_offset); +} + +static struct pin_mux tx48_uart0_pins[] = { +#ifdef CONFIG_SYS_NS16550_COM1 + /* UART0 for early boot messages */ + { OFFSET(uart0_rxd), MODE(0) | PULLUP_EN | RXACTIVE, }, /* UART0_RXD */ + { OFFSET(uart0_txd), MODE(0) | PULLUDEN, }, /* UART0_TXD */ + { OFFSET(uart0_ctsn), MODE(0) | PULLUP_EN | RXACTIVE, },/* UART0_CTS */ + { OFFSET(uart0_rtsn), MODE(0) | PULLUDEN, }, /* UART0_RTS */ +#endif +#ifdef CONFIG_SYS_NS16550_COM2 + /* UART1 */ + { OFFSET(uart1_rxd), MODE(0) | PULLUP_EN | RXACTIVE, }, /* UART1_RXD */ + { OFFSET(uart1_txd), MODE(0) | PULLUDEN, }, /* UART1_TXD */ + { OFFSET(uart1_ctsn), MODE(0) | PULLUP_EN | RXACTIVE, },/* UART1_CTS */ + { OFFSET(uart1_rtsn), MODE(0) | PULLUDEN, }, /* UART1_RTS */ +#endif +#ifdef CONFIG_SYS_NS16550_COM3 + /* UART5 */ + { OFFSET(mii1_rxdv), MODE(3) | PULLUP_EN | RXACTIVE, }, /* UART5_RXD */ + { OFFSET(mii1_col), MODE(3) | PULLUDEN, }, /* UART5_TXD */ + { OFFSET(mmc0_dat1), MODE(2) | PULLUP_EN | RXACTIVE, }, /* UART5_CTS */ + { OFFSET(mmc0_dat0), MODE(2) | PULLUDEN, }, /* UART5_RTS */ +#endif +}; + +/* + * early system init of muxing and clocks. + */ +static void enable_uart0_pin_mux(void) +{ + tx48_set_pin_mux(tx48_uart0_pins, ARRAY_SIZE(tx48_uart0_pins)); +} + +static void enable_mmc0_pin_mux(void) +{ + tx48_set_pin_mux(tx48_mmc_pins, ARRAY_SIZE(tx48_mmc_pins)); +} + +#define SDRAM_CLK CONFIG_SYS_DDR_CLK + +#define ns_TO_ck(ns) (((ns) * SDRAM_CLK + 999) / 1000) +#define ck_TO_ns(ck) ((ck) * 1000 / SDRAM_CLK) + +#ifdef DEBUG +static inline unsigned ck_val_check(unsigned ck, unsigned offs, unsigned max, + const char *name) +{ + if (ck < offs) { + printf("value %u for parameter %s is out of range (min: %u\n", + ck, name, offs); + hang(); + } + if (ck > max) { + printf("value %u for parameter %s is out of range (max: %u\n", + ck, name, max); + hang(); + } + return ck - offs; +} +#define CK_VAL(ck, offs, max) ck_val_check(ck, offs, max, #ck) +#else +#define CK_VAL(ck, offs, max) ((ck) - (offs)) +#endif + +#define DDR3_NT5CB128 1 +#define DDR3_H5TQ2G8 2 + +#if 1 +#define SDRAM_TYPE DDR3_NT5CB128 +#else +#define SDRAM_TYPE DDR3_H5TQ2G8 +#endif + +#ifndef SDRAM_TYPE +#error No SDRAM_TYPE specified +#elif (SDRAM_TYPE == DDR3_NT5CB128) || (SDRAM_TYPE == DDR3_H5TQ2G8) +#define tRP ns_TO_ck(14) +#define tRCD ns_TO_ck(14) +#define tWR ns_TO_ck(15) +#define tRAS ns_TO_ck(35) +#define tRC ns_TO_ck(49) +#define tRRD max(ns_TO_ck(8), 4) +#define tWTR max(ns_TO_ck(8), 4) + +#define tXP max(ns_TO_ck(6), 3) +#define tXPR max(5, ns_TO_ck(ck_TO_ns(tRFC + 1) + 10)) +#define tODT ns_TO_ck(9) +#define tXSNR max(5, ns_TO_ck(ck_TO_ns(tRFC + 1) + 10)) +#define tXSRD 512 +#define tRTP max(ns_TO_ck(8), 4) +#define tCKE max(ns_TO_ck(6), 3) + +#define tPDLL_UL 512 +#define tZQCS 64 +#define tRFC ns_TO_ck(160) +#define tRAS_MAX 0xf + +static inline int cwl(u32 sdram_clk) +{ + if (sdram_clk <= 300) + return 5; + else if (sdram_clk > 300 && sdram_clk <= 333) + return 5; + else if (sdram_clk > 333 && sdram_clk <= 400) + return 5; + else if (sdram_clk > 400 && sdram_clk <= 533) + return 6; + else if (sdram_clk > 533 && sdram_clk <= 666) + return 7; + else if (SDRAM_TYPE != DDR3_H5TQ2G8) + ; + else if (sdram_clk > 666 && sdram_clk <= 800) + return 8; + + printf("SDRAM clock out of range\n"); + hang(); +} +#define CWL cwl(SDRAM_CLK) + +static inline int cl(u32 sdram_clk) +{ + if (sdram_clk <= 300) + return 5; + else if (sdram_clk > 300 && sdram_clk <= 333) + return 5; + else if (sdram_clk > 333 && sdram_clk <= 400) + return 6; + else if (sdram_clk > 400 && sdram_clk <= 533) + return 8; + else if (sdram_clk > 533 && sdram_clk <= 666) + return (SDRAM_TYPE == DDR3_H5TQ2G8) ? 10 : 9; + else if (SDRAM_TYPE != DDR3_H5TQ2G8) + ; + else if (sdram_clk > 666 && sdram_clk <= 800) + return 11; + + printf("SDRAM clock out of range\n"); + hang(); +} +#define CL cl(SDRAM_CLK) + +#define ROW_ADDR_BITS 14 +#define SDRAM_PG_SIZE 1024 +#else +#error Unsupported SDRAM_TYPE specified +#endif + +#define SDRAM_CONFIG_VAL ( \ + (3 << 29) /* SDRAM type: 0: DDR1 1: LPDDR1 2: DDR2 3: DDR3 */ | \ + (0 << 27) /* IBANK pos */ | \ + (2 << 24) /* termination resistor value 0: disable 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */ | \ + (0 << 23) /* DDR2 differential DQS */ | \ + (1 << 21) /* dynamic ODT 0: off 1: RZQ/4 2: RZQ/2 */ | \ + (0 << 20) /* DLL disable */ | \ + (1 << 18) /* drive strength 0: RZQ/6 1: RZQ/7 */ | \ + ((CWL - 5) << 16) /* CWL 0: 5 ... 3: 8 */ | \ + (1 << 14) /* SDRAM data bus width 0: 32 1: 16 */ | \ + (((CL - 4) * 2) << 10) /* CAS latency 2: 5 4: 6 6: 8 ... 14: 11 (DDR3) */ | \ + ((ROW_ADDR_BITS - 9) << 7) /* # of row addr bits 0: 9 ... 7: 16 */ | \ + (3 << 4) /* # of SDRAM internal banks 0: 1 1: 2 2: 4 3: 8 */ | \ + (0 << 3) /* # of CS lines */ | \ + ((ffs(SDRAM_PG_SIZE / 256) - 1) << 0) /* page size 0: 256 1: 512 2: 1024 3:2048 */ | \ + 0) + +#define SDREF_VAL ( \ + (0 << 31) /* */ | \ + (1 << 29) /* self refresh temperature range 1: extended temp range */ | \ + (0 << 28) /* auto self refresh enable */ | \ + (0 << 24) /* partial array self refresh */ | \ + ((SDRAM_CLK * 7800 / 1000) << 0) /* refresh interval */ | \ + 0) + +#define tFAW ns_TO_ck(45) + +#define SDRAM_TIM1_VAL ((CK_VAL(tRP, 1, 16) << 25) | \ + (CK_VAL(tRCD, 1, 16) << 21) | \ + (CK_VAL(tWR, 1, 16) << 17) | \ + (CK_VAL(tRAS, 1, 32) << 12) | \ + (CK_VAL(tRC, 1, 64) << 6) | \ + (CK_VAL(tRRD, 1, 8) << 3) | \ + (CK_VAL(tWTR, 1, 8) << 0)) + +#define SDRAM_TIM2_VAL ((CK_VAL(max(tCKE, tXP), 1, 8) << 28) | \ + (CK_VAL(tODT, 0, 8) << 25) | \ + (CK_VAL(tXSNR, 1, 128) << 16) | \ + (CK_VAL(tXSRD, 1, 1024) << 6) | \ + (CK_VAL(tRTP, 1, 8) << 3) | \ + (CK_VAL(tCKE, 1, 8) << 0)) + +#define SDRAM_TIM3_VAL ((CK_VAL(DIV_ROUND_UP(tPDLL_UL, 128), 0, 16) << 28) | \ + (CK_VAL(tZQCS, 1, 64) << 15) | \ + (CK_VAL(tRFC, 1, 1024) << 4) | \ + (CK_VAL(tRAS_MAX, 0, 16) << 0)) + +#define ZQ_CONFIG_VAL ( \ + (1 << 31) /* ZQ calib for CS1 */ | \ + (0 << 30) /* ZQ calib for CS0 */ | \ + (0 << 29) /* dual calib */ | \ + (1 << 28) /* ZQ calib on SR/PWDN exit */ | \ + (2 << 18) /* ZQCL intervals for ZQINIT */ | \ + (4 << 16) /* ZQCS intervals for ZQCL */ | \ + (80 << 0) /* refr periods between ZQCS commands */ | \ + 0) + +static struct ddr_data tx48_ddr3_data = { + /* reset defaults */ + .datardsratio0 = 0x04010040, + .datawdsratio0 = 0x0, + .datafwsratio0 = 0x0, + .datawrsratio0 = 0x04010040, + .datadldiff0 = 0x4, +}; + +static struct cmd_control tx48_ddr3_cmd_ctrl_data = { + /* reset defaults */ + .cmd0csratio = 0x80, + .cmd0dldiff = 0x04, + .cmd1csratio = 0x80, + .cmd1dldiff = 0x04, + .cmd2csratio = 0x80, + .cmd2dldiff = 0x04, +}; + +static void ddr3_calib_start(void) +{ + static struct emif_reg_struct *emif_reg = (void *)EMIF4_0_CFG_BASE; + int loops = 0; + u32 regval; + u32 emif_status; + + debug("Starting DDR3 calibration\n"); + + /* wait for DDR PHY ready */ + while (!((emif_status = readl(&emif_reg->emif_status)) & (1 << 2))) { + if (loops++ > 100000) + break; + udelay(1); + } + debug("EMIF status: %08x after %u loops\n", emif_status, loops); + + /* enable DDR3 write levelling */ + loops = 0; + writel(EMIF_REG_RDWRLVLFULL_START_MASK, &emif_reg->emif_rd_wr_lvl_ctl); + do { + regval = readl(&emif_reg->emif_rd_wr_lvl_ctl); + if (!(regval & EMIF_REG_RDWRLVLFULL_START_MASK)) + break; + udelay(1); + } while (loops++ < 100000); + if (regval & EMIF_REG_RDWRLVLFULL_START_MASK) { + printf("Full WRLVL timed out\n"); + } else { + debug("Full Write Levelling done after %u us\n", loops); + } + writel(0, &emif_reg->emif_rd_wr_lvl_rmp_ctl); + writel(0, &emif_reg->emif_rd_wr_lvl_rmp_win); + writel(0x0f808080, &emif_reg->emif_rd_wr_lvl_ctl); + debug("DDR3 calibration done\n"); +} + +static void tx48_ddr_init(void) +{ + struct emif_regs r = {0}; + + debug("Initialising SDRAM timing for %u MHz DDR clock\n", SDRAM_CLK); + + r.sdram_config = SDRAM_CONFIG_VAL; + r.ref_ctrl = SDREF_VAL; + r.sdram_tim1 = SDRAM_TIM1_VAL; + r.sdram_tim2 = SDRAM_TIM2_VAL; + r.sdram_tim3 = SDRAM_TIM3_VAL; + r.zq_config = ZQ_CONFIG_VAL; + r.emif_ddr_phy_ctlr_1 = 0x0000030b; + + config_ddr(SDRAM_CLK, 0x04, &tx48_ddr3_data, + &tx48_ddr3_cmd_ctrl_data, &r, 0); + + ddr3_calib_start(); + + debug("%s: config_ddr done\n", __func__); +} + +#ifdef CONFIG_HW_WATCHDOG +static inline void tx48_wdog_disable(void) +{ +} +#else +static inline void tx48_wdog_disable(void) +{ + struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; + + /* WDT1 is already running when the bootloader gets control + * Disable it to avoid "random" resets + */ + writel(0xAAAA, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; + writel(0x5555, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) != 0x0) + ; +} +#endif + +void s_init(void) +{ + struct uart_sys *uart_base = (struct uart_sys *)DEFAULT_UART_BASE; + int timeout = 1000; + + /* Setup the PLLs and the clocks for the peripherals */ + pll_init(); + + tx48_wdog_disable(); + + enable_uart0_pin_mux(); + + /* UART softreset */ + writel(readl(&uart_base->uartsyscfg) | UART_RESET, + &uart_base->uartsyscfg); + while (!(readl(&uart_base->uartsyssts) & UART_RESETDONE)) { + udelay(1); + if (timeout-- <= 0) + break; + } + + /* Disable smart idle */ + writel((readl(&uart_base->uartsyscfg) & ~UART_IDLE_MODE_MASK) | + UART_IDLE_MODE(1), &uart_base->uartsyscfg); + + gd = &gdata; + + preloader_console_init(); + + if (timeout <= 0) + printf("Timeout waiting for UART RESET\n"); + + + timer_init(); + + tx48_ddr_init(); + + gpmc_init(); + + /* Enable MMC0 */ + enable_mmc0_pin_mux(); + + gpio_request_array(tx48_gpios, ARRAY_SIZE(tx48_gpios)); + tx48_set_pin_mux(tx48_pins, ARRAY_SIZE(tx48_pins)); +} diff --git a/board/karo/tx48/tx48.c b/board/karo/tx48/tx48.c new file mode 100644 index 0000000000..9819868835 --- /dev/null +++ b/board/karo/tx48/tx48.c @@ -0,0 +1,894 @@ +/* + * tx48.c + * Copyright (C) 2012 Lothar Waßmann + * + * based on evm.c + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation version 2. + * + * This program is distributed "as is" WITHOUT ANY WARRANTY of any + * kind, whether express or implied; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/karo.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define TX48_LED_GPIO AM33XX_GPIO_NR(1, 26) +#define TX48_ETH_PHY_RST_GPIO AM33XX_GPIO_NR(3, 8) +#define TX48_LCD_RST_GPIO AM33XX_GPIO_NR(1, 19) +#define TX48_LCD_PWR_GPIO AM33XX_GPIO_NR(1, 22) +#define TX48_LCD_BACKLIGHT_GPIO AM33XX_GPIO_NR(3, 14) + +#define GMII_SEL (CTRL_BASE + 0x650) + +/* UART Defines */ +#define UART_SYSCFG_OFFSET 0x54 +#define UART_SYSSTS_OFFSET 0x58 + +#define UART_RESET (0x1 << 1) +#define UART_CLK_RUNNING_MASK 0x1 +#define UART_SMART_IDLE_EN (0x1 << 0x3) + +/* Timer Defines */ +#define TSICR_REG 0x54 +#define TIOCP_CFG_REG 0x10 +#define TCLR_REG 0x38 + +/* RGMII mode define */ +#define RGMII_MODE_ENABLE 0xA +#define RMII_MODE_ENABLE 0x5 +#define MII_MODE_ENABLE 0x0 + +#define NO_OF_MAC_ADDR 1 +#define ETH_ALEN 6 + +#define MUX_CFG(value, offset) { \ + __raw_writel(value, (CTRL_BASE + (offset))); \ + } + +/* PAD Control Fields */ +#define SLEWCTRL (0x1 << 6) +#define RXACTIVE (0x1 << 5) +#define PULLUP_EN (0x1 << 4) /* Pull UP Selection */ +#define PULLUDEN (0x0 << 3) /* Pull up enabled */ +#define PULLUDDIS (0x1 << 3) /* Pull up disabled */ +#define MODE(val) (val) + +/* + * PAD CONTROL OFFSETS + * Field names corresponds to the pad signal name + */ +struct pad_signals { + int gpmc_ad0; + int gpmc_ad1; + int gpmc_ad2; + int gpmc_ad3; + int gpmc_ad4; + int gpmc_ad5; + int gpmc_ad6; + int gpmc_ad7; + int gpmc_ad8; + int gpmc_ad9; + int gpmc_ad10; + int gpmc_ad11; + int gpmc_ad12; + int gpmc_ad13; + int gpmc_ad14; + int gpmc_ad15; + int gpmc_a0; + int gpmc_a1; + int gpmc_a2; + int gpmc_a3; + int gpmc_a4; + int gpmc_a5; + int gpmc_a6; + int gpmc_a7; + int gpmc_a8; + int gpmc_a9; + int gpmc_a10; + int gpmc_a11; + int gpmc_wait0; + int gpmc_wpn; + int gpmc_be1n; + int gpmc_csn0; + int gpmc_csn1; + int gpmc_csn2; + int gpmc_csn3; + int gpmc_clk; + int gpmc_advn_ale; + int gpmc_oen_ren; + int gpmc_wen; + int gpmc_be0n_cle; + int lcd_data0; + int lcd_data1; + int lcd_data2; + int lcd_data3; + int lcd_data4; + int lcd_data5; + int lcd_data6; + int lcd_data7; + int lcd_data8; + int lcd_data9; + int lcd_data10; + int lcd_data11; + int lcd_data12; + int lcd_data13; + int lcd_data14; + int lcd_data15; + int lcd_vsync; + int lcd_hsync; + int lcd_pclk; + int lcd_ac_bias_en; + int mmc0_dat3; + int mmc0_dat2; + int mmc0_dat1; + int mmc0_dat0; + int mmc0_clk; + int mmc0_cmd; + int mii1_col; + int mii1_crs; + int mii1_rxerr; + int mii1_txen; + int mii1_rxdv; + int mii1_txd3; + int mii1_txd2; + int mii1_txd1; + int mii1_txd0; + int mii1_txclk; + int mii1_rxclk; + int mii1_rxd3; + int mii1_rxd2; + int mii1_rxd1; + int mii1_rxd0; + int rmii1_refclk; + int mdio_data; + int mdio_clk; + int spi0_sclk; + int spi0_d0; + int spi0_d1; + int spi0_cs0; + int spi0_cs1; + int ecap0_in_pwm0_out; + int uart0_ctsn; + int uart0_rtsn; + int uart0_rxd; + int uart0_txd; + int uart1_ctsn; + int uart1_rtsn; + int uart1_rxd; + int uart1_txd; + int i2c0_sda; + int i2c0_scl; + int mcasp0_aclkx; + int mcasp0_fsx; + int mcasp0_axr0; + int mcasp0_ahclkr; + int mcasp0_aclkr; + int mcasp0_fsr; + int mcasp0_axr1; + int mcasp0_ahclkx; + int xdma_event_intr0; + int xdma_event_intr1; + int nresetin_out; + int porz; + int nnmi; + int osc0_in; + int osc0_out; + int rsvd1; + int tms; + int tdi; + int tdo; + int tck; + int ntrst; + int emu0; + int emu1; + int osc1_in; + int osc1_out; + int pmic_power_en; + int rtc_porz; + int rsvd2; + int ext_wakeup; + int enz_kaldo_1p8v; + int usb0_dm; + int usb0_dp; + int usb0_ce; + int usb0_id; + int usb0_vbus; + int usb0_drvvbus; + int usb1_dm; + int usb1_dp; + int usb1_ce; + int usb1_id; + int usb1_vbus; + int usb1_drvvbus; + int ddr_resetn; + int ddr_csn0; + int ddr_cke; + int ddr_ck; + int ddr_nck; + int ddr_casn; + int ddr_rasn; + int ddr_wen; + int ddr_ba0; + int ddr_ba1; + int ddr_ba2; + int ddr_a0; + int ddr_a1; + int ddr_a2; + int ddr_a3; + int ddr_a4; + int ddr_a5; + int ddr_a6; + int ddr_a7; + int ddr_a8; + int ddr_a9; + int ddr_a10; + int ddr_a11; + int ddr_a12; + int ddr_a13; + int ddr_a14; + int ddr_a15; + int ddr_odt; + int ddr_d0; + int ddr_d1; + int ddr_d2; + int ddr_d3; + int ddr_d4; + int ddr_d5; + int ddr_d6; + int ddr_d7; + int ddr_d8; + int ddr_d9; + int ddr_d10; + int ddr_d11; + int ddr_d12; + int ddr_d13; + int ddr_d14; + int ddr_d15; + int ddr_dqm0; + int ddr_dqm1; + int ddr_dqs0; + int ddr_dqsn0; + int ddr_dqs1; + int ddr_dqsn1; + int ddr_vref; + int ddr_vtp; + int ddr_strben0; + int ddr_strben1; + int ain7; + int ain6; + int ain5; + int ain4; + int ain3; + int ain2; + int ain1; + int ain0; + int vrefp; + int vrefn; +}; + +struct pin_mux { + short reg_offset; + uint8_t val; +}; + +#define PAD_CTRL_BASE 0x800 +#define OFFSET(x) (unsigned int) (&((struct pad_signals *) \ + (PAD_CTRL_BASE))->x) + +/* + * Configure the pin mux for the module + */ +static inline void tx48_set_pin_mux(const struct pin_mux *pin_mux, + int num_pins) +{ + int i; + + for (i = 0; i < num_pins; i++) + MUX_CFG(pin_mux[i].val, pin_mux[i].reg_offset); +} + +#define PRM_RSTST_GLOBAL_COLD_RST (1 << 0) +#define PRM_RSTST_GLOBAL_WARM_SW_RST (1 << 1) +#define PRM_RSTST_WDT1_RST (1 << 4) +#define PRM_RSTST_EXTERNAL_WARM_RST (1 << 5) +#define PRM_RSTST_ICEPICK_RST (1 << 9) + +static u32 prm_rstst __attribute__((section(".data"))); + +/* + * Basic board specific setup + */ +static const struct pin_mux stk5_pads[] = { + /* heartbeat LED */ + { OFFSET(gpmc_a10), MODE(7) | PULLUDEN, }, + /* LCD RESET */ + { OFFSET(gpmc_a3), MODE(7) | PULLUDEN, }, + /* LCD POWER_ENABLE */ + { OFFSET(gpmc_a6), MODE(7) | PULLUDEN, }, + /* LCD Backlight (PWM) */ + { OFFSET(mcasp0_aclkx), MODE(7) | PULLUDEN, }, +}; + +static const struct pin_mux stk5_lcd_pads[] = { + /* LCD data bus */ + { OFFSET(lcd_data0), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data1), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data2), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data3), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data4), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data5), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data6), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data7), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data8), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data9), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data10), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data11), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data12), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data13), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data14), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_data15), MODE(0) | PULLUDEN, }, + /* LCD control signals */ + { OFFSET(lcd_hsync), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_vsync), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_pclk), MODE(0) | PULLUDEN, }, + { OFFSET(lcd_ac_bias_en), MODE(0) | PULLUDEN, }, +}; + +static const struct gpio stk5_gpios[] = { + { AM33XX_GPIO_NR(1, 26), GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", }, +}; + +static const struct gpio stk5_lcd_gpios[] = { + { AM33XX_GPIO_NR(1, 19), GPIOF_OUTPUT_INIT_LOW, "LCD RESET", }, + { AM33XX_GPIO_NR(1, 22), GPIOF_OUTPUT_INIT_LOW, "LCD POWER", }, + { AM33XX_GPIO_NR(3, 14), GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, +}; + +static const struct pin_mux stk5v5_pads[] = { + /* CAN transceiver control */ + { OFFSET(gpmc_ad8), MODE(7) | PULLUDEN, }, +}; + +static const struct gpio stk5v5_gpios[] = { + { AM33XX_GPIO_NR(0, 22), GPIOF_OUTPUT_INIT_HIGH, "CAN XCVR", }, +}; + +#ifdef CONFIG_LCD +static u16 tx48_cmap[256]; +vidinfo_t panel_info = { + /* set to max. size supported by SoC */ + .vl_col = 1366, + .vl_row = 768, + + .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ + .cmap = tx48_cmap, +}; + +static struct da8xx_panel tx48_lcd_panel = { + .name = "640x480MR@60", + .width = 640, + .height = 480, + .hfp = 12, + .hbp = 144, + .hsw = 30, + .vfp = 10, + .vbp = 35, + .vsw = 3, + .pxl_clk = 25000000, + .invert_pxl_clk = 1, +}; + +void *lcd_base; /* Start of framebuffer memory */ +void *lcd_console_address; /* Start of console buffer */ + +int lcd_color_fg; +int lcd_color_bg; + +short console_col; +short console_row; + +static int lcd_enabled = 1; + +void lcd_initcolregs(void) +{ +} + +void lcd_setcolreg(ushort regno, ushort red, ushort green, ushort blue) +{ +} + +void lcd_enable(void) +{ + /* HACK ALERT: + * global variable from common/lcd.c + * Set to 0 here to prevent messages from going to LCD + * rather than serial console + */ + lcd_is_enabled = 0; + + if (lcd_enabled) { + karo_load_splashimage(1); + + gpio_set_value(TX48_LCD_PWR_GPIO, 1); + gpio_set_value(TX48_LCD_RST_GPIO, 1); + udelay(300000); + gpio_set_value(TX48_LCD_BACKLIGHT_GPIO, 0); + } +} + +void lcd_disable(void) +{ + if (lcd_enabled) { + da8xx_fb_disable(); + lcd_enabled = 0; + } +} + +void lcd_panel_disable(void) +{ + if (lcd_enabled) { + gpio_set_value(TX48_LCD_BACKLIGHT_GPIO, 1); + gpio_set_value(TX48_LCD_PWR_GPIO, 0); + gpio_set_value(TX48_LCD_RST_GPIO, 0); + } +} + +void lcd_ctrl_init(void *lcdbase) +{ + int color_depth = 24; + char *vm, *v; + unsigned long val; + struct da8xx_panel *p = &tx48_lcd_panel; + int refresh = 60; + + if (!lcd_enabled) { + printf("LCD disabled\n"); + return; + } + + if (tstc() || (prm_rstst & PRM_RSTST_WDT1_RST)) { + lcd_enabled = 0; + return; + } + + vm = getenv("video_mode"); + if (vm == NULL) { + lcd_enabled = 0; + return; + } + + if ((v = strstr(vm, ":"))) + vm = v + 1; + + strncpy((char *)p->name, vm, sizeof(p->name)); + + val = simple_strtoul(vm, &vm, 10); + if (val != 0) { + if (val > panel_info.vl_col) + val = panel_info.vl_col; + p->width = val; + panel_info.vl_col = val; + } + if (*vm == 'x') { + val = simple_strtoul(vm + 1, &vm, 10); + if (val > panel_info.vl_row) + val = panel_info.vl_row; + p->height = val; + panel_info.vl_row = val; + } + while (*vm != '\0') { + switch (*vm) { + case 'M': + case 'R': + vm++; + break; + + case '-': + color_depth = simple_strtoul(vm + 1, &vm, 10); + break; + + case '@': + refresh = simple_strtoul(vm + 1, &vm, 10); + break; + + default: + debug("Ignoring '%c'\n", *vm); + vm++; + } + } + switch (color_depth) { + case 8: + panel_info.vl_bpix = 3; + break; + + case 16: + panel_info.vl_bpix = 4; + break; + + case 24: + panel_info.vl_bpix = 5; + break; + + default: + printf("Invalid color_depth %u from video_mode '%s'; using default: %u\n", + color_depth, getenv("video_mode"), 24); + } + lcd_line_length = NBITS(panel_info.vl_bpix) / 8 * panel_info.vl_col; + p->pxl_clk = refresh * + (p->width + p->hfp + p->hbp + p->hsw) * + (p->height + p->vfp + p->vbp + p->vsw); + debug("Pixel clock set to %u.%03uMHz\n", + p->pxl_clk / 1000000, p->pxl_clk / 1000 % 1000); + + gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios)); + tx48_set_pin_mux(stk5_lcd_pads, ARRAY_SIZE(stk5_lcd_pads)); + debug("Initializing FB driver\n"); + da8xx_video_init(&tx48_lcd_panel, color_depth); + + if (karo_load_splashimage(0) == 0) { + debug("Initializing LCD controller\n"); + video_hw_init(); + } else { + debug("Skipping initialization of LCD controller\n"); + } +} +#else +#define lcd_enabled 0 +#endif /* CONFIG_LCD */ + +static void stk5_board_init(void) +{ + tx48_set_pin_mux(stk5_pads, ARRAY_SIZE(stk5_pads)); +} + +static void stk5v3_board_init(void) +{ + stk5_board_init(); +} + +static void stk5v5_board_init(void) +{ + stk5_board_init(); + tx48_set_pin_mux(stk5v5_pads, ARRAY_SIZE(stk5v5_pads)); + gpio_request_array(stk5v5_gpios, ARRAY_SIZE(stk5v5_gpios)); +} + +/* called with default environment! */ +int board_init(void) +{ + /* mach type passed to kernel */ +#ifdef CONFIG_OF_LIBFDT + gd->bd->bi_arch_number = -1; +#endif + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +static void show_reset_cause(u32 prm_rstst) +{ + const char *dlm = ""; + + printf("RESET cause: "); + if (prm_rstst & PRM_RSTST_GLOBAL_COLD_RST) { + printf("%sPOR", dlm); + dlm = " | "; + } + if (prm_rstst & PRM_RSTST_GLOBAL_WARM_SW_RST) { + printf("%sSW", dlm); + dlm = " | "; + } + if (prm_rstst & PRM_RSTST_WDT1_RST) { + printf("%sWATCHDOG", dlm); + dlm = " | "; + } + if (prm_rstst & PRM_RSTST_EXTERNAL_WARM_RST) { + printf("%sWARM", dlm); + dlm = " | "; + } + if (prm_rstst & PRM_RSTST_ICEPICK_RST) { + printf("%sJTAG", dlm); + dlm = " | "; + } + if (*dlm == '\0') + printf("unknown"); + + printf(" RESET\n"); +} + +/* called with default environment! */ +int checkboard(void) +{ + prm_rstst = readl(PRM_RSTST); + show_reset_cause(prm_rstst); + +#ifdef CONFIG_OF_LIBFDT + printf("Board: Ka-Ro TX48-7020 with FDT support\n"); +#else + printf("Board: Ka-Ro TX48-7020\n"); +#endif + timer_init(); + return 0; +} + +static void tx48_set_cpu_clock(void) +{ + unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0); + + if (tstc() || (prm_rstst & PRM_RSTST_WDT1_RST)) + return; + + if (cpu_clk == 0 || cpu_clk == mpu_clk_rate() / 1000000) + return; + + mpu_pll_config_val(cpu_clk); + + printf("CPU clock set to %lu.%03lu MHz\n", + mpu_clk_rate() / 1000000, + mpu_clk_rate() / 1000 % 1000); +} + +/* called with environment from NAND or MMC */ +int board_late_init(void) +{ + const char *baseboard; + + tx48_set_cpu_clock(); +#ifdef CONFIG_OF_BOARD_SETUP + karo_fdt_move_fdt(); +#endif + baseboard = getenv("baseboard"); + if (!baseboard) + return 0; + + if (strncmp(baseboard, "stk5", 4) == 0) { + printf("Baseboard: %s\n", baseboard); + if ((strlen(baseboard) == 4) || + strcmp(baseboard, "stk5-v3") == 0) { + stk5v3_board_init(); + } else if (strcmp(baseboard, "stk5-v5") == 0) { + stk5v5_board_init(); + } else { + printf("WARNING: Unsupported STK5 board rev.: %s\n", + baseboard + 4); + } + } else { + printf("WARNING: Unsupported baseboard: '%s'\n", + baseboard); + return -EINVAL; + } + + return 0; +} + +#ifdef CONFIG_DRIVER_TI_CPSW +static void tx48_phy_init(char *name, int addr) +{ + debug("%s: Resetting ethernet PHY\n", __func__); + + gpio_direction_output(TX48_ETH_PHY_RST_GPIO, 0); + + udelay(100); + + /* Release nRST */ + gpio_set_value(TX48_ETH_PHY_RST_GPIO, 1); + + /* Wait for PHY internal POR signal to deassert */ + udelay(25000); +} + +static void cpsw_control(int enabled) +{ + /* nothing for now */ + /* TODO : VTP was here before */ +} + +static struct cpsw_slave_data cpsw_slaves[] = { + { + .slave_reg_ofs = 0x208, + .sliver_reg_ofs = 0xd80, + .phy_id = 0, + .phy_if = PHY_INTERFACE_MODE_RMII, + }, +}; + +void s_init(void) +{ + /* Nothing to be done here */ +} + +static struct cpsw_platform_data cpsw_data = { + .mdio_base = CPSW_MDIO_BASE, + .cpsw_base = CPSW_BASE, + .mdio_div = 0xff, + .channels = 8, + .cpdma_reg_ofs = 0x800, + .slaves = ARRAY_SIZE(cpsw_slaves), + .slave_data = cpsw_slaves, + .ale_reg_ofs = 0xd00, + .ale_entries = 1024, + .host_port_reg_ofs = 0x108, + .hw_stats_reg_ofs = 0x900, + .mac_control = (1 << 5) /* MIIEN */, + .control = cpsw_control, + .phy_init = tx48_phy_init, + .gigabit_en = 0, + .host_port_num = 0, + .version = CPSW_CTRL_VERSION_2, +}; + +int board_eth_init(bd_t *bis) +{ + uint8_t mac_addr[ETH_ALEN]; + uint32_t mac_hi, mac_lo; + + /* try reading mac address from efuse */ + mac_lo = __raw_readl(MAC_ID0_LO); + mac_hi = __raw_readl(MAC_ID0_HI); + + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi & 0xFF00) >> 8; + mac_addr[2] = (mac_hi & 0xFF0000) >> 16; + mac_addr[3] = (mac_hi & 0xFF000000) >> 24; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo & 0xFF00) >> 8; + + if (is_valid_ether_addr(mac_addr)) { + printf("MAC addr from fuse: %pM\n", mac_addr); + eth_setenv_enetaddr("ethaddr", mac_addr); + } else { + printf("ERROR: Did not find a valid mac address in e-fuse\n"); + } + + __raw_writel(RMII_MODE_ENABLE, MAC_MII_SEL); + __raw_writel(0x5D, GMII_SEL); + return cpsw_register(&cpsw_data); +} +#endif /* CONFIG_DRIVER_TI_CPSW */ + +void tx48_disable_watchdog(void) +{ + struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE; + + while (readl(&wdtimer->wdtwwps) & (1 << 4)) + ; + writel(0xaaaa, &wdtimer->wdtwspr); + while (readl(&wdtimer->wdtwwps) & (1 << 4)) + ; + writel(0x5555, &wdtimer->wdtwspr); +} + +#if defined(CONFIG_NAND_AM33XX) && defined(CONFIG_CMD_SWITCH_ECC) +/****************************************************************************** + * Command to switch between NAND HW and SW ecc + *****************************************************************************/ +static int do_switch_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) +{ + int type = 0; + + if (argc < 2) + goto usage; + + if (strncmp(argv[1], "hw", 2) == 0) { + if (argc == 3) + type = simple_strtoul(argv[2], NULL, 10); + am33xx_nand_switch_ecc(NAND_ECC_HW, type); + } + else if (strncmp(argv[1], "sw", 2) == 0) + am33xx_nand_switch_ecc(NAND_ECC_SOFT, 0); + else + goto usage; + + return 0; + +usage: + printf("Usage: nandecc %s\n", cmdtp->usage); + return 1; +} + +U_BOOT_CMD( + nandecc, 3, 1, do_switch_ecc, + "Switch NAND ECC calculation algorithm b/w hardware and software", + "[sw|hw ] \n" + " [sw|hw]- Switch b/w hardware(hw) & software(sw) ecc algorithm\n" + " hw_type- 0 for Hamming code\n" + " 1 for bch4\n" + " 2 for bch8\n" + " 3 for bch16\n" +); +#endif /* CONFIG_NAND_AM33XX && CONFIG_CMD_SWITCH_ECC */ + +enum { + LED_STATE_INIT = -1, + LED_STATE_OFF, + LED_STATE_ON, +}; + +void show_activity(int arg) +{ + static int led_state = LED_STATE_INIT; + static ulong last; + + if (led_state == LED_STATE_INIT) { + last = get_timer(0); + gpio_set_value(TX48_LED_GPIO, 1); + led_state = LED_STATE_ON; + } else { + if (get_timer(last) > CONFIG_SYS_HZ) { + last = get_timer(0); + if (led_state == LED_STATE_ON) { + gpio_set_value(TX48_LED_GPIO, 0); + } else { + gpio_set_value(TX48_LED_GPIO, 1); + } + led_state = 1 - led_state; + } + } +} + +#ifdef CONFIG_OF_BOARD_SETUP +#ifdef CONFIG_FDT_FIXUP_PARTITIONS +#include +#include +struct node_info nodes[] = { + { "ti,omap2-nand", MTD_DEV_TYPE_NAND, }, +}; + +#else +#define fdt_fixup_mtdparts(b,n,c) do { } while (0) +#endif /* CONFIG_FDT_FIXUP_PARTITIONS */ + +static void tx48_fixup_flexcan(void *blob) +{ + const char *baseboard = getenv("baseboard"); + + if (baseboard && strcmp(baseboard, "stk5-v5") == 0) + return; + + karo_fdt_del_prop(blob, "ti,dcan", 0x481cc000, "can-xcvr-enable"); + karo_fdt_del_prop(blob, "ti,dcan", 0x481d0000, "can-xcvr-enable"); +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + fdt_fixup_ethernet(blob); + + karo_fdt_fixup_touchpanel(blob); + tx48_fixup_flexcan(blob); + + tx48_disable_watchdog(); +} +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/board/karo/tx48/u-boot.lds b/board/karo/tx48/u-boot.lds new file mode 100644 index 0000000000..493cc559a8 --- /dev/null +++ b/board/karo/tx48/u-boot.lds @@ -0,0 +1,106 @@ +/* + * Copyright (c) 2004-2008 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + .text : + { + *(.__image_copy_start) + CPUDIR/start.o (.text*) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + + . = .; + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + .image_copy_end : + { + *(.__image_copy_end) + } + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rel.dyn : + { + *(.rel*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + _end = .; + +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + /DISCARD/ : { *(.bss*) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynsym*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.hash*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/board/karo/tx51/Makefile b/board/karo/tx51/Makefile new file mode 100644 index 0000000000..53c68a2bf5 --- /dev/null +++ b/board/karo/tx51/Makefile @@ -0,0 +1,46 @@ +# +# (C) Copyright 2009 DENX Software Engineering +# Author: John Rigby +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LDSCRIPT := $(BOARDDIR)/u-boot.lds + +LIB = $(obj)lib$(BOARD).o + +COBJS := tx51.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/karo/tx51/config.mk b/board/karo/tx51/config.mk new file mode 100644 index 0000000000..899890754f --- /dev/null +++ b/board/karo/tx51/config.mk @@ -0,0 +1,5 @@ +# stack is allocated below CONFIG_SYS_TEXT_BASE +CONFIG_SYS_TEXT_BASE := 0x90100000 + +PLATFORM_CPPFLAGS += -Werror +LOGO_BMP = logos/karo.bmp diff --git a/board/karo/tx51/lowlevel_init.S b/board/karo/tx51/lowlevel_init.S new file mode 100644 index 0000000000..a4da3f6b06 --- /dev/null +++ b/board/karo/tx51/lowlevel_init.S @@ -0,0 +1,177 @@ +#include +#include +#include + +#define DCDGEN(type, addr, data) .long type, addr, data + +#define SDRAM_CLK CONFIG_SYS_SDRAM_CLK + +#ifdef PHYS_SDRAM_2_SIZE +#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) +#else +#define SDRAM_SIZE PHYS_SDRAM_1_SIZE +#endif + +#define REG_ESDCTL0 0x00 +#define REG_ESDCFG0 0x04 +#define REG_ESDCTL1 0x08 +#define REG_ESDCFG1 0x0c +#define REG_ESDMISC 0x10 +#define REG_ESDSCR 0x14 +#define REG_ESDGPR 0x34 + +#define REG_CCGR0 0x68 +#define REG_CCGR1 0x6c +#define REG_CCGR2 0x70 +#define REG_CCGR3 0x74 +#define REG_CCGR4 0x78 +#define REG_CCGR5 0x7c +#define REG_CCGR6 0x80 +#define REG_CMEOR 0x84 + +/* SDRAM timing setup */ +#define RALAT 1 +#define LHD 0 + +#if SDRAM_SIZE <= SZ_128M +#define RA_BITS (13 - 11) /* row addr bits - 11 */ +#else +#define RA_BITS (14 - 11) /* row addr bits - 11 */ +#endif + +#define CA_BITS (10 - 8) /* 0-2: col addr bits - 8 3: rsrvd */ +#define DSIZ 2 /* 0: D[31..16] 1: D[15..D0] 2: D[31..0] 3: rsrvd */ +#define SREFR 3 /* 0: disabled 1-5: 2^n rows/clock *: rsrvd */ +#define SRT 0 /* 0: disabled *: 1: self refr. ... */ +#define PWDT 0 /* 0: disabled 1: precharge pwdn + 2: pwdn after 64 clocks 3: pwdn after 128 clocks */ +#define ESDCTL_VAL (0x80000000 | (SREFR << 28) | (RA_BITS << 24) | (CA_BITS << 20) | \ + (DSIZ << 16) | (SRT << 14) | (PWDT << 12)) + +#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000) + + .macro CK_VAL, name, clks, offs + .iflt \clks - \offs + .set \name, 0 + .else + .set \name, \clks - \offs + .endif + .endm + + .macro NS_VAL, name, ns, offs + .iflt \ns - \offs + .set \name, 0 + .else + CK_VAL \name, NS_TO_CK(\ns), \offs + .endif + .endm + +#if SDRAM_CLK < 200 +/* MT46H32M32LF-6 */ +NS_VAL tRFC, 125, 10 /* clks - 10 (0..15) */ +NS_VAL tXSR, 138, 25 /* clks - 25 (0..15) */ +NS_VAL tXP, 25, 1 /* clks - 1 (0..7) */ +CK_VAL tWTR, 1, 1 /* clks - 1 (0..1) */ +NS_VAL tRP, 18, 2 /* clks - 2 (0..3) */ +CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */ +NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */ +NS_VAL tRAS, 42, 1 /* clks - 1 (0..15) */ +NS_VAL tRRD, 12, 1 /* clks - 1 (0..3) */ +NS_VAL tRCD, 18, 1 /* clks - 1 (0..7) */ +NS_VAL tRC, 60, 1 /* 0: 20 *: clks - 1 (0..15) */ +#else +/* MT46H64M32LF-5 or -6 */ +NS_VAL tRFC, 72, 10 /* clks - 10 (0..15) */ +NS_VAL tXSR, 113, 25 /* clks - 25 (0..15) */ +CK_VAL tXP, 2, 1 /* clks - 1 (0..7) */ +CK_VAL tWTR, 2, 1 /* clks - 1 (0..1) */ +NS_VAL tRP, 18, 2 /* clks - 2 (0..3) */ +CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */ +NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */ +NS_VAL tRAS, 42, 1 /* clks - 1 (0..15) */ +NS_VAL tRRD, 12, 1 /* clks - 1 (0..3) */ +NS_VAL tRCD, 18, 1 /* clks - 1 (0..7) */ +NS_VAL tRC, 60, 1 /* 0: 20 *: clks - 1 (0..15) */ +#endif + +#define ESDCFG_VAL ((tRFC << 28) | (tXSR << 24) | (tXP << 21) | \ + (tWTR << 20) | (tRP << 18) | (tMRD << 16) | \ + (tRAS << 12) | (tRRD << 10) | (tWR << 7) | \ + (tRCD << 4) | (tRC << 0)) + +#define ESDMISC_RALAT(n) (((n) & 0x3) << 7) +#define ESDMISC_DDR2_EN(n) (((n) & 0x1) << 4) +#define ESDMISC_DDR_EN(n) (((n) & 0x1) << 3) +#define ESDMISC_AP(n) (((n) & 0xf) << 16) +#define ESDMISC_VAL (ESDMISC_AP(10) | ESDMISC_RALAT(RALAT) | \ + (LHD << 5) | ESDMISC_DDR2_EN(0) | ESDMISC_DDR_EN(0)) + +app_start_addr: + .long _start +app_code_barker: + .long 0xB1 +app_code_csf: + .long 0 // 0x97f40000 - 0x1000 +dcd_ptr_ptr: + .long dcd_ptr +super_root_key: + .long 0 // hab_super_root_key +dcd_ptr: + .long dcd_data +app_dest_ptr: + .long CONFIG_SYS_TEXT_BASE +dcd_data: + .long 0xB17219E9 // Fixed. can't change. +dcd_len: + .long dcd_end - dcd_start +dcd_start: + DCDGEN(4, CCM_BASE_ADDR + REG_CCGR0, 0xffcffffc); + DCDGEN(4, CCM_BASE_ADDR + REG_CCGR1, 0x003fffff); + DCDGEN(4, CCM_BASE_ADDR + REG_CCGR2, 0x030c003c); + DCDGEN(4, CCM_BASE_ADDR + REG_CCGR3, 0x000000ff); + DCDGEN(4, CCM_BASE_ADDR + REG_CCGR4, 0x00000000); + DCDGEN(4, CCM_BASE_ADDR + REG_CCGR5, 0x003fc003); + DCDGEN(4, CCM_BASE_ADDR + REG_CCGR6, 0x00000000); + DCDGEN(4, CCM_BASE_ADDR + REG_CMEOR, 0x00000000); + + DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDCTL0, 0x80000000) + DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDSCR, 0x04008008) + DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDSCR, 0x00008010) + DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDSCR, 0x00008010) + DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDSCR, 0x00338018) + DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDCTL0, ESDCTL_VAL) + DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDCFG0, ESDCFG_VAL) +#ifdef RAM_BANK1_SIZE + DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDCTL1, ESDCTL_VAL) + DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDCFG1, ESDCFG_VAL) +#endif + DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDGPR, 0x00020000 | ((RALAT & 0x3) << 29)) + DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDMISC, ESDMISC_VAL) + DCDGEN(4, ESDCTL_BASE_ADDR + REG_ESDSCR, 0x00000000) + + /* UART1_RXD */ + DCDGEN(4, IOMUXC_BASE_ADDR + 0x228, 0x00000000) + DCDGEN(4, IOMUXC_BASE_ADDR + 0x618, 0x000001c1) + DCDGEN(4, IOMUXC_BASE_ADDR + 0x9e4, 0x00000000) + + /* UART1_TXD */ + DCDGEN(4, IOMUXC_BASE_ADDR + 0x22c, 0x00000000) + DCDGEN(4, IOMUXC_BASE_ADDR + 0x61c, 0x000000c5) + + /* UART1_RTS */ + DCDGEN(4, IOMUXC_BASE_ADDR + 0x230, 0x00000000) + DCDGEN(4, IOMUXC_BASE_ADDR + 0x620, 0x000001c1) + DCDGEN(4, IOMUXC_BASE_ADDR + 0x9e0, 0x00000000) + + /* UART1_CTS */ + DCDGEN(4, IOMUXC_BASE_ADDR + 0x234, 0x00000000) + DCDGEN(4, IOMUXC_BASE_ADDR + 0x624, 0x000000c5) + + /* STK5 board LED */ + DCDGEN(4, IOMUXC_BASE_ADDR + 0x1d0, 0x00000013) +dcd_end: + .ifgt dcd_end - dcd_start - 720 + DCD too large! + .endif +image_len: + .long CONFIG_U_BOOT_IMG_SIZE diff --git a/board/karo/tx51/tx51.c b/board/karo/tx51/tx51.c new file mode 100644 index 0000000000..f937d9a7e4 --- /dev/null +++ b/board/karo/tx51/tx51.c @@ -0,0 +1,1026 @@ +/* + * Copyright (C) 2011 Lothar Waßmann + * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/karo.h" + +#define TX51_FEC_RST_GPIO IMX_GPIO_NR(2, 14) +#define TX51_FEC_PWR_GPIO IMX_GPIO_NR(1, 3) +#define TX51_FEC_INT_GPIO IMX_GPIO_NR(3, 18) +#define TX51_LED_GPIO IMX_GPIO_NR(4, 10) + +#define TX51_LCD_PWR_GPIO IMX_GPIO_NR(4, 14) +#define TX51_LCD_RST_GPIO IMX_GPIO_NR(4, 13) +#define TX51_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 2) + +#define TX51_RESET_OUT_GPIO IMX_GPIO_NR(2, 15) + +DECLARE_GLOBAL_DATA_PTR; + +#define IOMUX_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0) + +#define FEC_PAD_CTRL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST) +#define FEC_PAD_CTRL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST) +#define GPIO_PAD_CTRL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) + +static iomux_v3_cfg_t tx51_pads[] = { + /* NAND flash pads are set up in lowlevel_init.S */ + + /* RESET_OUT */ + MX51_PAD_EIM_A21__GPIO2_15 | GPIO_PAD_CTRL, + + /* UART pads */ +#if CONFIG_MXC_UART_BASE == UART1_BASE + MX51_PAD_UART1_RXD__UART1_RXD, + MX51_PAD_UART1_TXD__UART1_TXD, + MX51_PAD_UART1_RTS__UART1_RTS, + MX51_PAD_UART1_CTS__UART1_CTS, +#endif +#if CONFIG_MXC_UART_BASE == UART2_BASE + MX51_PAD_UART2_RXD__UART2_RXD, + MX51_PAD_UART2_TXD__UART2_TXD, + MX51_PAD_EIM_D26__UART2_RTS, + MX51_PAD_EIM_D25__UART2_CTS, +#endif +#if CONFIG_MXC_UART_BASE == UART3_BASE + MX51_PAD_UART3_RXD__UART3_RXD, + MX51_PAD_UART3_TXD__UART3_TXD, + MX51_PAD_EIM_D18__UART3_RTS, + MX51_PAD_EIM_D17__UART3_CTS, +#endif + /* internal I2C */ + MX51_PAD_I2C1_DAT__GPIO4_17 | IOMUX_SION, + MX51_PAD_I2C1_CLK__GPIO4_16 | IOMUX_SION, + + /* FEC PHY GPIO functions */ + MX51_PAD_GPIO1_3__GPIO1_3 | GPIO_PAD_CTRL, /* PHY POWER */ + MX51_PAD_EIM_A20__GPIO2_14 | GPIO_PAD_CTRL, /* PHY RESET */ + MX51_PAD_NANDF_CS2__GPIO3_18 | GPIO_PAD_CTRL, /* PHY INT */ + + /* FEC functions */ + MX51_PAD_NANDF_CS3__FEC_MDC | FEC_PAD_CTRL, + MX51_PAD_EIM_EB2__FEC_MDIO | FEC_PAD_CTRL, + MX51_PAD_NANDF_D11__FEC_RX_DV | FEC_PAD_CTRL2, + MX51_PAD_EIM_CS4__FEC_RX_ER | FEC_PAD_CTRL2, + MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | FEC_PAD_CTRL2, + MX51_PAD_NANDF_CS7__FEC_TX_EN | FEC_PAD_CTRL, + MX51_PAD_NANDF_D8__FEC_TDATA0 | FEC_PAD_CTRL, + MX51_PAD_NANDF_CS4__FEC_TDATA1 | FEC_PAD_CTRL, + MX51_PAD_NANDF_CS5__FEC_TDATA2 | FEC_PAD_CTRL, + MX51_PAD_NANDF_CS6__FEC_TDATA3 | FEC_PAD_CTRL, + + /* strap pins for PHY configuration */ + MX51_PAD_NANDF_RB3__GPIO3_11 | GPIO_PAD_CTRL, /* RX_CLK/REGOFF */ + MX51_PAD_NANDF_D9__GPIO3_31 | GPIO_PAD_CTRL, /* RXD0/Mode0 */ + MX51_PAD_EIM_EB3__GPIO2_23 | GPIO_PAD_CTRL, /* RXD1/Mode1 */ + MX51_PAD_EIM_CS2__GPIO2_27 | GPIO_PAD_CTRL, /* RXD2/Mode2 */ + MX51_PAD_EIM_CS3__GPIO2_28 | GPIO_PAD_CTRL, /* RXD3/nINTSEL */ + MX51_PAD_NANDF_RB2__GPIO3_10 | GPIO_PAD_CTRL, /* COL/RMII/CRSDV */ + MX51_PAD_EIM_CS5__GPIO2_30 | GPIO_PAD_CTRL, /* CRS/PHYAD4 */ + + /* unusable pins on TX51 */ + MX51_PAD_GPIO1_0__GPIO1_0, + MX51_PAD_GPIO1_1__GPIO1_1, +}; + +static const struct gpio tx51_gpios[] = { + /* RESET_OUT */ + { TX51_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_LOW, "RESET_OUT", }, + + /* FEC PHY control GPIOs */ + { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC POWER", }, /* PHY POWER */ + { TX51_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC RESET", }, /* PHY RESET */ + { TX51_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", }, /* PHY INT (TX_ER) */ + + /* FEC PHY strap pins */ + { IMX_GPIO_NR(3, 11), GPIOF_OUTPUT_INIT_LOW, "FEC PHY REGOFF", }, /* RX_CLK/REGOFF */ + { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE0", }, /* RXD0/Mode0 */ + { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE1", }, /* RXD1/Mode1 */ + { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_LOW, "FEC PHY MODE2", }, /* RXD2/Mode2 */ + { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_LOW, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */ + { IMX_GPIO_NR(3, 10), GPIOF_OUTPUT_INIT_LOW, "FEC PHY RMII", }, /* COL/RMII/CRSDV */ + { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */ + + /* module internal I2C bus */ + { IMX_GPIO_NR(4, 17), GPIOF_INPUT, "I2C1 SDA", }, + { IMX_GPIO_NR(4, 16), GPIOF_INPUT, "I2C1 SCL", }, + + /* Unconnected pins */ + { IMX_GPIO_NR(1, 0), GPIOF_OUTPUT_INIT_LOW, "N/C", }, + { IMX_GPIO_NR(1, 1), GPIOF_OUTPUT_INIT_LOW, "N/C", }, +}; + +/* + * Functions + */ +/* placed in section '.data' to prevent overwriting relocation info + * overlayed with bss + */ +static u32 wrsr __attribute__((section(".data"))); + +#define WRSR_POR (1 << 4) +#define WRSR_TOUT (1 << 1) +#define WRSR_SFTW (1 << 0) + +static void print_reset_cause(void) +{ + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR; + u32 srsr; + char *dlm = ""; + + printf("Reset cause: "); + + srsr = readl(&src_regs->srsr); + wrsr = readw(wdt_base + 4); + + if (wrsr & WRSR_POR) { + printf("%sPOR", dlm); + dlm = " | "; + } + if (srsr & 0x00004) { + printf("%sCSU", dlm); + dlm = " | "; + } + if (srsr & 0x00008) { + printf("%sIPP USER", dlm); + dlm = " | "; + } + if (srsr & 0x00010) { + if (wrsr & WRSR_SFTW) { + printf("%sSOFT", dlm); + dlm = " | "; + } + if (wrsr & WRSR_TOUT) { + printf("%sWDOG", dlm); + dlm = " | "; + } + } + if (srsr & 0x00020) { + printf("%sJTAG HIGH-Z", dlm); + dlm = " | "; + } + if (srsr & 0x00040) { + printf("%sJTAG SW", dlm); + dlm = " | "; + } + if (srsr & 0x10000) { + printf("%sWARM BOOT", dlm); + dlm = " | "; + } + if (dlm[0] == '\0') + printf("unknown"); + + printf("\n"); +} + +static void tx51_print_cpuinfo(void) +{ + u32 cpurev; + + cpurev = get_cpu_rev(); + + printf("CPU: Freescale i.MX51 rev%d.%d at %d MHz\n", + (cpurev & 0x000F0) >> 4, + (cpurev & 0x0000F) >> 0, + mxc_get_clock(MXC_ARM_CLK) / 1000000); + + print_reset_cause(); +} + +int board_early_init_f(void) +{ + struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE; + +#ifdef CONFIG_CMD_BOOTCE + /* WinCE fails to enable these clocks */ + writel(readl(&ccm_regs->CCGR2) | 0x0c000000, &ccm_regs->CCGR2); /* usboh3_ipg_ahb */ + writel(readl(&ccm_regs->CCGR4) | 0x30000000, &ccm_regs->CCGR4); /* srtc */ + writel(readl(&ccm_regs->CCGR6) | 0x00000300, &ccm_regs->CCGR6); /* emi_garb */ +#endif + gpio_request_array(tx51_gpios, ARRAY_SIZE(tx51_gpios)); + imx_iomux_v3_setup_multiple_pads(tx51_pads, ARRAY_SIZE(tx51_pads)); + + writel(0x77777777, AIPS1_BASE_ADDR + 0x00); + writel(0x77777777, AIPS1_BASE_ADDR + 0x04); + + writel(0x00000000, AIPS1_BASE_ADDR + 0x40); + writel(0x00000000, AIPS1_BASE_ADDR + 0x44); + writel(0x00000000, AIPS1_BASE_ADDR + 0x48); + writel(0x00000000, AIPS1_BASE_ADDR + 0x4c); + writel(0x00000000, AIPS1_BASE_ADDR + 0x50); + + writel(0x77777777, AIPS2_BASE_ADDR + 0x00); + writel(0x77777777, AIPS2_BASE_ADDR + 0x04); + + writel(0x00000000, AIPS2_BASE_ADDR + 0x40); + writel(0x00000000, AIPS2_BASE_ADDR + 0x44); + writel(0x00000000, AIPS2_BASE_ADDR + 0x48); + writel(0x00000000, AIPS2_BASE_ADDR + 0x4c); + writel(0x00000000, AIPS2_BASE_ADDR + 0x50); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000; + return 0; +} + +int dram_init(void) +{ + int ret; + + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + PHYS_SDRAM_1_SIZE); + + ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, + CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK); + if (ret) + printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__, + CONFIG_SYS_SDRAM_CLK, ret); + else + debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n", + __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000, + mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000, + CONFIG_SYS_SDRAM_CLK); + return ret; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); +#if CONFIG_NR_DRAM_BANKS > 1 + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, + PHYS_SDRAM_2_SIZE); +#endif +} + +#ifdef CONFIG_CMD_MMC +static const iomux_v3_cfg_t mmc0_pads[] = { + MX51_PAD_SD1_CMD__SD1_CMD, + MX51_PAD_SD1_CLK__SD1_CLK, + MX51_PAD_SD1_DATA0__SD1_DATA0, + MX51_PAD_SD1_DATA1__SD1_DATA1, + MX51_PAD_SD1_DATA2__SD1_DATA2, + MX51_PAD_SD1_DATA3__SD1_DATA3, + /* SD1 CD */ + MX51_PAD_DISPB2_SER_RS__GPIO3_8 | MUX_PAD_CTRL(PAD_CTL_PUE | PAD_CTL_PKE), +}; + +static const iomux_v3_cfg_t mmc1_pads[] = { + MX51_PAD_SD2_CMD__SD2_CMD, + MX51_PAD_SD2_CLK__SD2_CLK, + MX51_PAD_SD2_DATA0__SD2_DATA0, + MX51_PAD_SD2_DATA1__SD2_DATA1, + MX51_PAD_SD2_DATA2__SD2_DATA2, + MX51_PAD_SD2_DATA3__SD2_DATA3, + /* SD2 CD */ + MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | MUX_PAD_CTRL(PAD_CTL_PUE | PAD_CTL_PKE), +}; + +static struct tx51_esdhc_cfg { + const iomux_v3_cfg_t *pads; + int num_pads; + struct fsl_esdhc_cfg cfg; + int cd_gpio; +} tx51_esdhc_cfg[] = { + { + .pads = mmc0_pads, + .num_pads = ARRAY_SIZE(mmc0_pads), + .cfg = { + .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR, + }, + .cd_gpio = IMX_GPIO_NR(3, 8), + }, + { + .pads = mmc1_pads, + .num_pads = ARRAY_SIZE(mmc1_pads), + .cfg = { + .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR, + }, + .cd_gpio = IMX_GPIO_NR(3, 6), + }, +}; + +static struct tx51_esdhc_cfg *to_tx51_esdhc_cfg(struct fsl_esdhc_cfg *cfg) +{ + return container_of(cfg, struct tx51_esdhc_cfg, cfg); +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct tx51_esdhc_cfg *cfg = to_tx51_esdhc_cfg(mmc->priv); + + if (cfg->cd_gpio < 0) + return cfg->cd_gpio; + + debug("SD card %d is %spresent\n", + cfg - tx51_esdhc_cfg, + gpio_get_value(cfg->cd_gpio) ? "NOT " : ""); + return !gpio_get_value(cfg->cd_gpio); +} + +int board_mmc_init(bd_t *bis) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(tx51_esdhc_cfg); i++) { + struct mmc *mmc; + struct tx51_esdhc_cfg *cfg = &tx51_esdhc_cfg[i]; + int ret; + + if (i >= CONFIG_SYS_FSL_ESDHC_NUM) + break; + + imx_iomux_v3_setup_multiple_pads(cfg->pads, + cfg->num_pads); + cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + fsl_esdhc_initialize(bis, &cfg->cfg); + + ret = gpio_request_one(cfg->cd_gpio, + GPIOF_INPUT, "MMC CD"); + if (ret) { + printf("Error %d requesting GPIO%d_%d\n", + ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32); + continue; + } + + mmc = find_mmc_device(i); + if (mmc == NULL) + continue; + if (board_mmc_getcd(mmc) > 0) + mmc_init(mmc); + } + return 0; +} +#endif /* CONFIG_CMD_MMC */ + +#ifdef CONFIG_FEC_MXC + +#ifndef ETH_ALEN +#define ETH_ALEN 6 +#endif + +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + int i; + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; + struct fuse_bank *bank = &iim->bank[1]; + struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs; + + if (dev_id > 0) + return; + + for (i = 0; i < ETH_ALEN; i++) + mac[ETH_ALEN - i - 1] = readl(&fuse->mac_addr[i]); +} + +static iomux_v3_cfg_t tx51_fec_pads[] = { + /* reconfigure strap pins for FEC function */ + MX51_PAD_NANDF_RB3__FEC_RX_CLK | FEC_PAD_CTRL2, + MX51_PAD_NANDF_D9__FEC_RDATA0 | FEC_PAD_CTRL2, + MX51_PAD_EIM_EB3__FEC_RDATA1 | FEC_PAD_CTRL2, + MX51_PAD_EIM_CS2__FEC_RDATA2 | FEC_PAD_CTRL2, + MX51_PAD_EIM_CS3__FEC_RDATA3 | FEC_PAD_CTRL2, + MX51_PAD_NANDF_RB2__FEC_COL | FEC_PAD_CTRL2, + MX51_PAD_EIM_CS5__FEC_CRS | FEC_PAD_CTRL, +}; + +/* take bit 4 of PHY address from configured PHY address or + * set it to 0 if PHYADDR is -1 (probe for PHY) + */ +#define PHYAD4 ((CONFIG_FEC_MXC_PHYADDR >> 4) & !(CONFIG_FEC_MXC_PHYADDR >> 5)) + +static struct gpio tx51_fec_gpios[] = { + { TX51_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY POWER", }, + { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode0", }, /* RXD0/Mode0 */ + { IMX_GPIO_NR(2, 23), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode1", }, /* RXD1/Mode1 */ + { IMX_GPIO_NR(2, 27), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY Mode2", }, /* RXD2/Mode2 */ + { IMX_GPIO_NR(2, 28), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY nINTSEL", }, /* RXD3/nINTSEL */ +#if PHYAD4 + { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */ +#else + { IMX_GPIO_NR(2, 30), GPIOF_OUTPUT_INIT_LOW, "FEC PHY PHYAD4", }, /* CRS/PHYAD4 */ +#endif +}; + +int board_eth_init(bd_t *bis) +{ + int ret; + unsigned char mac[ETH_ALEN]; + + /* Power up the external phy and assert strap options */ + gpio_request_array(tx51_fec_gpios, ARRAY_SIZE(tx51_fec_gpios)); + + /* delay at least 21ms for the PHY internal POR signal to deassert */ + udelay(22000); + + /* Deassert RESET to the external phy */ + gpio_set_value(TX51_FEC_RST_GPIO, 1); + + /* Without this delay the PHY won't work, though nothing in + * the datasheets suggests that it should be necessary! + */ + udelay(400); + imx_iomux_v3_setup_multiple_pads(tx51_fec_pads, + ARRAY_SIZE(tx51_fec_pads)); + + ret = cpu_eth_init(bis); + if (ret) { + printf("cpu_eth_init() failed: %d\n", ret); + return ret; + } + + imx_get_mac_from_fuse(0, mac); + eth_setenv_enetaddr("ethaddr", mac); + printf("MAC addr from fuse: %pM\n", mac); + + return ret; +} +#endif /* CONFIG_FEC_MXC */ + +enum { + LED_STATE_INIT = -1, + LED_STATE_OFF, + LED_STATE_ON, +}; + +void show_activity(int arg) +{ + static int led_state = LED_STATE_INIT; + static ulong last; + + if (led_state == LED_STATE_INIT) { + last = get_timer(0); + gpio_set_value(TX51_LED_GPIO, 1); + led_state = LED_STATE_ON; + } else { + if (get_timer(last) > CONFIG_SYS_HZ) { + last = get_timer(0); + if (led_state == LED_STATE_ON) { + gpio_set_value(TX51_LED_GPIO, 0); + } else { + gpio_set_value(TX51_LED_GPIO, 1); + } + led_state = 1 - led_state; + } + } +} + +static const iomux_v3_cfg_t stk5_pads[] = { + /* SW controlled LED on STK5 baseboard */ + MX51_PAD_CSI2_D13__GPIO4_10, + + /* USB PHY reset */ + MX51_PAD_GPIO1_4__GPIO1_4, + /* USBOTG OC */ + MX51_PAD_GPIO1_6__GPIO1_6, + /* USB PHY clock enable */ + MX51_PAD_GPIO1_7__GPIO1_7, + /* USBH1 VBUS enable */ + MX51_PAD_GPIO1_8__GPIO1_8, + /* USBH1 OC */ + MX51_PAD_GPIO1_9__GPIO1_9, +}; + +static const struct gpio stk5_gpios[] = { + { TX51_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", }, + + { IMX_GPIO_NR(1, 4), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY clk enable", }, + { IMX_GPIO_NR(1, 6), GPIOF_INPUT, "USBOTG OC", }, + { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "ULPI PHY reset", }, + { IMX_GPIO_NR(1, 8), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", }, + { IMX_GPIO_NR(1, 9), GPIOF_INPUT, "USBH1 OC", }, +}; + +#ifdef CONFIG_LCD +static ushort tx51_cmap[256]; +vidinfo_t panel_info = { + /* set to max. size supported by SoC */ + .vl_col = 1600, + .vl_row = 1200, + + .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ + .cmap = tx51_cmap, +}; + +static struct fb_videomode tx51_fb_modes[] = { + { + /* Standard VGA timing */ + .name = "VGA", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = KHZ2PICOS(25175), + .left_margin = 48, + .hsync_len = 96, + .right_margin = 16, + .upper_margin = 31, + .vsync_len = 2, + .lower_margin = 12, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ETV570 640 x 480 display. Syncs low active, + * DE high active, 115.2 mm x 86.4 mm display area + * VGA compatible timing + */ + .name = "ETV570", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = KHZ2PICOS(25175), + .left_margin = 114, + .hsync_len = 30, + .right_margin = 16, + .upper_margin = 32, + .vsync_len = 3, + .lower_margin = 10, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ET0350G0DH6 320 x 240 display. + * 70.08 mm x 52.56 mm display area. + */ + .name = "ET0350", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = KHZ2PICOS(6500), + .left_margin = 68 - 34, + .hsync_len = 34, + .right_margin = 20, + .upper_margin = 18 - 3, + .vsync_len = 3, + .lower_margin = 4, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ET0430G0DH6 480 x 272 display. + * 95.04 mm x 53.856 mm display area. + */ + .name = "ET0430", + .refresh = 60, + .xres = 480, + .yres = 272, + .pixclock = KHZ2PICOS(9000), + .left_margin = 2, + .hsync_len = 41, + .right_margin = 2, + .upper_margin = 2, + .vsync_len = 10, + .lower_margin = 2, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ET0500G0DH6 800 x 480 display. + * 109.6 mm x 66.4 mm display area. + */ + .name = "ET0500", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = KHZ2PICOS(33260), + .left_margin = 216 - 128, + .hsync_len = 128, + .right_margin = 1056 - 800 - 216, + .upper_margin = 35 - 2, + .vsync_len = 2, + .lower_margin = 525 - 480 - 35, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ETQ570G0DH6 320 x 240 display. + * 115.2 mm x 86.4 mm display area. + */ + .name = "ETQ570", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = KHZ2PICOS(6400), + .left_margin = 38, + .hsync_len = 30, + .right_margin = 30, + .upper_margin = 16, /* 15 according to datasheet */ + .vsync_len = 3, /* TVP -> 1>x>5 */ + .lower_margin = 4, /* 4.5 according to datasheet */ + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ET0700G0DH6 800 x 480 display. + * 152.4 mm x 91.44 mm display area. + */ + .name = "ET0700", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = KHZ2PICOS(33260), + .left_margin = 216 - 128, + .hsync_len = 128, + .right_margin = 1056 - 800 - 216, + .upper_margin = 35 - 2, + .vsync_len = 2, + .lower_margin = 525 - 480 - 35, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* unnamed entry for assigning parameters parsed from 'video_mode' string */ + .refresh = 60, + .left_margin = 48, + .hsync_len = 96, + .right_margin = 16, + .upper_margin = 31, + .vsync_len = 2, + .lower_margin = 12, + .sync = FB_SYNC_CLK_LAT_FALL, + }, +}; + +static int lcd_enabled = 1; + +void lcd_enable(void) +{ + /* HACK ALERT: + * global variable from common/lcd.c + * Set to 0 here to prevent messages from going to LCD + * rather than serial console + */ + lcd_is_enabled = 0; + + karo_load_splashimage(1); + if (lcd_enabled) { + debug("Switching LCD on\n"); + gpio_set_value(TX51_LCD_PWR_GPIO, 1); + udelay(100); + gpio_set_value(TX51_LCD_RST_GPIO, 1); + udelay(300000); + gpio_set_value(TX51_LCD_BACKLIGHT_GPIO, 0); + } +} + +void lcd_disable(void) +{ + printf("Disabling LCD\n"); +} + +void lcd_panel_disable(void) +{ + if (lcd_enabled) { + debug("Switching LCD off\n"); + gpio_set_value(TX51_LCD_BACKLIGHT_GPIO, 1); + gpio_set_value(TX51_LCD_RST_GPIO, 0); + gpio_set_value(TX51_LCD_PWR_GPIO, 0); + } +} + +static const iomux_v3_cfg_t stk5_lcd_pads[] = { + /* LCD RESET */ + MX51_PAD_CSI2_VSYNC__GPIO4_13, + /* LCD POWER_ENABLE */ + MX51_PAD_CSI2_HSYNC__GPIO4_14, + /* LCD Backlight (PWM) */ + MX51_PAD_GPIO1_2__GPIO1_2, + + /* Display */ + MX51_PAD_DISP1_DAT0__DISP1_DAT0, + MX51_PAD_DISP1_DAT1__DISP1_DAT1, + MX51_PAD_DISP1_DAT2__DISP1_DAT2, + MX51_PAD_DISP1_DAT3__DISP1_DAT3, + MX51_PAD_DISP1_DAT4__DISP1_DAT4, + MX51_PAD_DISP1_DAT5__DISP1_DAT5, + MX51_PAD_DISP1_DAT6__DISP1_DAT6, + MX51_PAD_DISP1_DAT7__DISP1_DAT7, + MX51_PAD_DISP1_DAT8__DISP1_DAT8, + MX51_PAD_DISP1_DAT9__DISP1_DAT9, + MX51_PAD_DISP1_DAT10__DISP1_DAT10, + MX51_PAD_DISP1_DAT11__DISP1_DAT11, + MX51_PAD_DISP1_DAT12__DISP1_DAT12, + MX51_PAD_DISP1_DAT13__DISP1_DAT13, + MX51_PAD_DISP1_DAT14__DISP1_DAT14, + MX51_PAD_DISP1_DAT15__DISP1_DAT15, + MX51_PAD_DISP1_DAT16__DISP1_DAT16, + MX51_PAD_DISP1_DAT17__DISP1_DAT17, + MX51_PAD_DISP1_DAT18__DISP1_DAT18, + MX51_PAD_DISP1_DAT19__DISP1_DAT19, + MX51_PAD_DISP1_DAT20__DISP1_DAT20, + MX51_PAD_DISP1_DAT21__DISP1_DAT21, + MX51_PAD_DISP1_DAT22__DISP1_DAT22, + MX51_PAD_DISP1_DAT23__DISP1_DAT23, + MX51_PAD_DI1_PIN2__DI1_PIN2, /* HSYNC */ + MX51_PAD_DI1_PIN3__DI1_PIN3, /* VSYNC */ +}; + +static const struct gpio stk5_lcd_gpios[] = { + { TX51_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", }, + { TX51_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", }, + { TX51_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, +}; + +void lcd_ctrl_init(void *lcdbase) +{ + int color_depth = 24; + char *vm; + unsigned long val; + int refresh = 60; + struct fb_videomode *p = &tx51_fb_modes[0]; + struct fb_videomode fb_mode; + int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0; + int pix_fmt = 0; + ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3; + unsigned long di_clk_rate = 65000000; + + if (!lcd_enabled) { + debug("LCD disabled\n"); + return; + } + + if (tstc() || (wrsr & WRSR_TOUT)) { + debug("Disabling LCD\n"); + lcd_enabled = 0; + return; + } + + karo_fdt_move_fdt(); + + vm = getenv("video_mode"); + if (vm == NULL) { + debug("Disabling LCD\n"); + lcd_enabled = 0; + return; + } + if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) { + p = &fb_mode; + debug("Using video mode from FDT\n"); + vm += strlen(vm); + if (fb_mode.xres < panel_info.vl_col) + panel_info.vl_col = fb_mode.xres; + if (fb_mode.yres < panel_info.vl_row) + panel_info.vl_row = fb_mode.yres; + } + if (p->name != NULL) + debug("Trying compiled-in video modes\n"); + while (p->name != NULL) { + if (strcmp(p->name, vm) == 0) { + debug("Using video mode: '%s'\n", p->name); + vm += strlen(vm); + break; + } + p++; + } + if (*vm != '\0') + debug("Trying to decode video_mode: '%s'\n", vm); + while (*vm != '\0') { + if (*vm >= '0' && *vm <= '9') { + char *end; + + val = simple_strtoul(vm, &end, 0); + if (end > vm) { + if (!xres_set) { + if (val > panel_info.vl_col) + val = panel_info.vl_col; + p->xres = val; + panel_info.vl_col = val; + xres_set = 1; + } else if (!yres_set) { + if (val > panel_info.vl_row) + val = panel_info.vl_row; + p->yres = val; + panel_info.vl_row = val; + yres_set = 1; + } else if (!bpp_set) { + switch (val) { + case 8: + case 16: + case 24: + color_depth = val; + break; + + default: + printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n", + end - vm, vm, color_depth); + } + bpp_set = 1; + } else if (!refresh_set) { + refresh = val; + refresh_set = 1; + } + } + vm = end; + } + switch (*vm) { + case '@': + bpp_set = 1; + /* fallthru */ + case '-': + yres_set = 1; + /* fallthru */ + case 'x': + xres_set = 1; + /* fallthru */ + case 'M': + case 'R': + vm++; + break; + + default: + if (!pix_fmt) { + char *tmp; + + pix_fmt = IPU_PIX_FMT_RGB24; + tmp = strchr(vm, ':'); + if (tmp) + vm = tmp; + } + if (*vm != '\0') + vm++; + } + } + if (p->xres == 0 || p->yres == 0) { + printf("Invalid video mode: %s\n", getenv("video_mode")); + lcd_enabled = 0; + printf("Supported video modes are:"); + for (p = &tx51_fb_modes[0]; p->name != NULL; p++) { + printf(" %s", p->name); + } + printf("\n"); + return; + } + + p->pixclock = KHZ2PICOS(refresh * + (p->xres + p->left_margin + p->right_margin + p->hsync_len) * + (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) + / 1000); + debug("Pixel clock set to %lu.%03lu MHz\n", + PICOS2KHZ(p->pixclock) / 1000, + PICOS2KHZ(p->pixclock) % 1000); + + gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios)); + imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads, + ARRAY_SIZE(stk5_lcd_pads)); + + debug("Initializing FB driver\n"); + if (!pix_fmt) + pix_fmt = IPU_PIX_FMT_RGB24; + + if (karo_load_splashimage(0) == 0) { + struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)MXC_CCM_BASE; + u32 ccgr4 = readl(&ccm_regs->CCGR4); + + /* MIPI HSC clock is required for initialization */ + writel(ccgr4 | (3 << 12), &ccm_regs->CCGR4); + + debug("Initializing LCD controller\n"); + ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1); + + writel(ccgr4 & ~(3 << 12), &ccm_regs->CCGR4); + } else { + debug("Skipping initialization of LCD controller\n"); + } +} +#else +#define lcd_enabled 0 +#endif /* CONFIG_LCD */ + +static void stk5_board_init(void) +{ + gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios)); + imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads)); +} + +static void stk5v3_board_init(void) +{ + stk5_board_init(); +} + +static void tx51_set_cpu_clock(void) +{ + unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0); + int ret; + + if (tstc() || (wrsr & WRSR_TOUT)) + return; + + if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000) + return; + + ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK); + if (ret != 0) { + printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk); + return; + } + printf("CPU clock set to %u.%03u MHz\n", + mxc_get_clock(MXC_ARM_CLK) / 1000000, + mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000); +} + +int board_late_init(void) +{ + int ret = 0; + const char *baseboard; + + tx51_set_cpu_clock(); + karo_fdt_move_fdt(); + + baseboard = getenv("baseboard"); + if (!baseboard) + goto exit; + + if (strncmp(baseboard, "stk5", 4) == 0) { + printf("Baseboard: %s\n", baseboard); + if ((strlen(baseboard) == 4) || + strcmp(baseboard, "stk5-v3") == 0) { + stk5v3_board_init(); + } else if (strcmp(baseboard, "stk5-v5") == 0) { + printf("ERROR: Baseboard '%s' incompatible with TX51 module!\n", + baseboard); + stk5v3_board_init(); + } else { + printf("WARNING: Unsupported STK5 board rev.: %s\n", + baseboard + 4); + } + } else { + printf("WARNING: Unsupported baseboard: '%s'\n", + baseboard); + ret = -EINVAL; + } + +exit: + gpio_set_value(TX51_RESET_OUT_GPIO, 1); + return ret; +} + +int checkboard(void) +{ + tx51_print_cpuinfo(); + + printf("Board: Ka-Ro TX51-%sxx%s\n", + TX51_MOD_PREFIX, TX51_MOD_SUFFIX); + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_FDT_FIXUP_PARTITIONS +#include +#include +struct node_info nodes[] = { + { "fsl,imx51-nand", MTD_DEV_TYPE_NAND, }, +}; + +#else +#define fdt_fixup_mtdparts(b,n,c) do { } while (0) +#endif + +void ft_board_setup(void *blob, bd_t *bd) +{ + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + fdt_fixup_ethernet(blob); + + karo_fdt_fixup_touchpanel(blob); + karo_fdt_fixup_usb_otg(blob, "fsl,imx-otg", "fsl,usbphy"); +} +#endif diff --git a/board/karo/tx51/u-boot.lds b/board/karo/tx51/u-boot.lds new file mode 100644 index 0000000000..6fcc460a5c --- /dev/null +++ b/board/karo/tx51/u-boot.lds @@ -0,0 +1,100 @@ +/* + * (C) Copyright 2012 Lothar Waßmann + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + .text : + { + *(.__image_copy_start) + CPUDIR/start.o (.text*) + . = 0x400; + KEEP(board/karo/tx51/lowlevel_init.o (.text*)) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + .image_copy_end : + { + *(.__image_copy_end) + } + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rel.dyn : + { + *(.rel*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + _end = .; + +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + /DISCARD/ : { *(.bss*) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynsym*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.hash*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/board/karo/tx53/Makefile b/board/karo/tx53/Makefile new file mode 100644 index 0000000000..3c106666d3 --- /dev/null +++ b/board/karo/tx53/Makefile @@ -0,0 +1,39 @@ +# +# (C) Copyright 2012 Lothar Waßmann +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License +# version 2 as published by the Free Software Foundation. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +include $(TOPDIR)/config.mk + +LDSCRIPT := $(BOARDDIR)/u-boot.lds + +LIB = $(obj)lib$(BOARD).o + +COBJS := tx53.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/karo/tx53/config.mk b/board/karo/tx53/config.mk new file mode 100644 index 0000000000..e765c3a0dd --- /dev/null +++ b/board/karo/tx53/config.mk @@ -0,0 +1,5 @@ +# stack is allocated below CONFIG_SYS_TEXT_BASE +CONFIG_SYS_TEXT_BASE := 0x70100000 + +PLATFORM_CPPFLAGS += -Werror +LOGO_BMP = logos/karo.bmp diff --git a/board/karo/tx53/lowlevel_init.S b/board/karo/tx53/lowlevel_init.S new file mode 100644 index 0000000000..85b204df6a --- /dev/null +++ b/board/karo/tx53/lowlevel_init.S @@ -0,0 +1,586 @@ +#include +#include +#include + +#define DEBUG_LED_BIT 20 +#define LED_GPIO_BASE GPIO2_BASE_ADDR +#define LED_MUX_OFFSET 0x174 +#define LED_MUX_MODE 0x11 + +#define SDRAM_CLK CONFIG_SYS_SDRAM_CLK + +#ifdef PHYS_SDRAM_2_SIZE +#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) +#else +#define SDRAM_SIZE PHYS_SDRAM_1_SIZE +#endif + +#define REG_CCOSR 0x60 + +#define REG_CCGR0 0x68 +#define REG_CCGR1 0x6c +#define REG_CCGR2 0x70 +#define REG_CCGR3 0x74 +#define REG_CCGR4 0x78 +#define REG_CCGR5 0x7c +#define REG_CCGR6 0x80 +#define REG_CCGR7 0x84 +#define REG_CMEOR 0x88 + +#define CPU_2_BE_32(l) \ + ((((l) << 24) & 0xFF000000) | \ + (((l) << 8) & 0x00FF0000) | \ + (((l) >> 8) & 0x0000FF00) | \ + (((l) >> 24) & 0x000000FF)) + +/* +CCM register set 0x53FD4000 0x53FD7FFF +EIM register set 0x63FDA000 0x63FDAFFF +NANDFC register set 0xF7FF0000 0xF7FFFFFF +IOMUX Control (IOMUXC) registers 0x53FA8000 0x53FABFFF +DPLLC1 register 0x63F80000 0x63F83FFF +DPLLC2 register 0x63F84000 0x63F87FFF +DPLLC3 register 0x63F88000 0x63F8BFFF +DPLLC4 register 0x63F8C000 0x63F8FFFF +ESD RAM controller register 0x63FD9000 0x63FD9FFF +M4IF register 0x63FD8000 0x63FD8FFF +DDR 0x70000000 0xEFFFFFFF +EIM 0xF0000000 0xF7FEFFFF +NANDFC Buffers 0xF7FF0000 0xF7FFFFFF +IRAM Free Space 0xF8006000 0xF8017FF0 +GPU Memory 0xF8020000 0xF805FFFF +*/ +#define CHECK_DCD_ADDR(a) ( \ + ((a) >= 0x53fd4000 && (a) <= 0x53fd7fff) /* CCM */ || \ + ((a) >= 0x63fda000 && (a) <= 0x63fdafff) /* EIM (CS0) */ || \ + ((a) >= 0x53fa8000 && (a) <= 0x53fabfff) /* IOMUXC */ || \ + ((a) >= 0x63f80000 && (a) <= 0x63f8ffff) /* DPLLC1..4 */ || \ + ((a) >= 0x63fd8000 && (a) <= 0x63fd9fff) /* M4IF & SDRAM Contr. */ || \ + ((a) >= 0x70000000 && (a) <= 0xefffffff) /* SDRAM */ || \ + ((a) >= 0xf0000000 && (a) <= 0xf7ffffff) /* EIM & NANDFC buffers */ || \ + ((a) >= 0xf8006000 && (a) <= 0xf8017ff0) /* IRAM free space */ || \ + ((a) >= 0xf8020000 && (a) <= 0xf805ffff) /* GPU RAM */) + + .macro mxc_dcd_item addr, val + .ifne CHECK_DCD_ADDR(\addr) + .word CPU_2_BE_32(\addr), CPU_2_BE_32(\val) + .else + .error "Address \addr not accessible from DCD" + .endif + .endm + +#define MXC_DCD_ITEM(addr, val) mxc_dcd_item addr, val + +#define MXC_DCD_CMD_SZ_BYTE 1 +#define MXC_DCD_CMD_SZ_SHORT 2 +#define MXC_DCD_CMD_SZ_WORD 4 +#define MXC_DCD_CMD_FLAG_WRITE 0x0 +#define MXC_DCD_CMD_FLAG_CLR 0x1 +#define MXC_DCD_CMD_FLAG_SET 0x3 +#define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0) +#define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1) +#define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1) + +#define MXC_DCD_CMD_WRT(type, flags, next) \ + .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type)) + +#define MXC_DCD_CMD_CHK(type, flags, addr, mask) \ + .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\ + CPU_2_BE_32(addr), CPU_2_BE_32(mask) + +#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \ + .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\ + CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count) + +#define MXC_DCD_CMD_NOP() \ + .word CPU_2_BE_32((0xc0 << 24) | (4 << 8)) + +#define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK) +#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000) +#define NS_TO_CK10(ns) DIV_ROUND_UP(NS_TO_CK(ns), 10) + + .macro CK_VAL, name, clks, offs, max + .iflt \clks - \offs + .set \name, 0 + .else + .ifle \clks - \offs - \max + .set \name, \clks - \offs + .else + .error "Value \clks out of range for parameter \name" + .endif + .endif + .endm + + .macro NS_VAL, name, ns, offs, max + .iflt \ns - \offs + .set \name, 0 + .else + CK_VAL \name, NS_TO_CK(\ns), \offs, \max + .endif + .endm + + .macro CK_MAX, name, ck1, ck2, offs, max + .ifgt \ck1 - \ck2 + CK_VAL \name, \ck1, \offs, \max + .else + CK_VAL \name, \ck2, \offs, \max + .endif + .endm + +#define ESDMISC_DDR_TYPE_DDR3 0 +#define ESDMISC_DDR_TYPE_LPDDR2 1 +#define ESDMISC_DDR_TYPE_DDR2 2 + +#define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d)) + +#define CKIL_FREQ_Hz 32768 +#define ESDOR_CLK_PERIOD_ns (1000000000 / CKIL_FREQ_Hz / 2) /* base clock for ESDOR values */ + +/* DDR3 SDRAM */ +#if SDRAM_SIZE > PHYS_SDRAM_1_SIZE +#define BANK_ADDR_BITS 2 +#else +#define BANK_ADDR_BITS 1 +#endif +#define SDRAM_BURST_LENGTH 8 +#define RALAT 5 +#define WALAT 0 +#define BI_ON 0 +#define ADDR_MIRROR 0 +#define DDR_TYPE ESDMISC_DDR_TYPE_DDR3 + +/* 512/1024MiB SDRAM: NT5CB128M16FP-DII */ +#if SDRAM_CLK > 666 && SDRAM_CLK <= 800 +#define CL_VAL 11 +#define CWL_VAL 8 +#elif SDRAM_CLK > 533 && SDRAM_CLK <= 666 +#define CL_VAL 9 // or 10 +#define CWL_VAL 7 +#elif SDRAM_CLK > 400 && SDRAM_CLK <= 533 +#define CL_VAL 7 // or 8 +#define CWL_VAL 6 +#elif SDRAM_CLK > 333 && SDRAM_CLK <= 400 +#define CL_VAL 6 +#define CWL_VAL 5 +#elif SDRAM_CLK >= 303 && SDRAM_CLK <= 333 +#define CL_VAL 5 +#define CWL_VAL 5 +#else +#error SDRAM clock out of range: 303 .. 800 +#endif + +/* ESDCFG0 0x0c */ +NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */ +CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ +CK_MAX tXP, NS_TO_CK10(75), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */ +CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */ +NS_VAL tFAW, 50, 1, 31 /* clks - 1 (0..31) */ +CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */ + +/* ESDCFG1 0x10 */ +CK_VAL tRCD, NS_TO_CK10(125), 1, 7 /* clks - 1 (0..7) */ /* 12.5 */ +CK_VAL tRP, NS_TO_CK10(125), 1, 7 /* clks - 1 (0..7) */ /* 12.5 */ +NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */ +CK_VAL tRAS, NS_TO_CK10(375), 1, 31 /* clks - 1 (0..31) */ /* 37.5 */ +CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */ +NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */ + +/* ESDCFG2 0x14 */ +CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */ +CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ +CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ +CK_MAX tRRD, NS_TO_CK(10), 4, 1, 7 /* clks - 1 (0..7) */ + +/* ESDOR 0x30 */ +CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */ +#define tSDE_RST (DIV_ROUND_UP(200000, ESDOR_CLK_PERIOD_ns) + 1) + /* Add an extra (or two?) ESDOR_CLK_PERIOD_ns according to + * erroneous Erratum Engcm12377 + */ +#define tRST_CKE (DIV_ROUND_UP(500000 + 2 * ESDOR_CLK_PERIOD_ns, ESDOR_CLK_PERIOD_ns) + 1) + + +/* ESDOTC 0x08 */ +CK_VAL tAOFPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */ +CK_VAL tAONPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */ +CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tODTLon tCWL, 0, 7 /* clks - 1 (0..7) */ /* CWL+AL-2 */ +CK_VAL tODTLoff tCWL, 0, 31 /* clks - 1 (0..31) */ /* CWL+AL-2 */ + +/* ESDPDC 0x04 */ +CK_MAX tCKE, NS_TO_CK(5), 3, 1, 7 +CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7 +CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7 + +#define PRCT 0 +#define PWDT 5 +#define SLOW_PD 0 +#define BOTH_CS_PD 1 + +#define ESDPDC_VAL_0 ( \ + (PRCT << 28) | \ + (PRCT << 24) | \ + (tCKE << 16) | \ + (SLOW_PD << 7) | \ + (BOTH_CS_PD << 6) | \ + (tCKSRX << 3) | \ + (tCKSRE << 0) \ + ) + +#define ESDPDC_VAL_1 (ESDPDC_VAL_0 | \ + (PWDT << 12) | \ + (PWDT << 8) \ + ) + +#define ROW_ADDR_BITS 14 +#define COL_ADDR_BITS 10 + +#define Rtt_Nom 1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */ +#define Rtt_WR 0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */ +#define DLL_DISABLE 0 + + .iflt tWR - 7 + .set mr0_val, (((1 - DLL_DISABLE) << 8) /* DLL Reset */ | \ + (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\ + ((tWR + 1 - 4) << 9) | \ + ((((tCL + 3) - 4) & 0x7) << 4) | \ + ((((tCL + 3) - 4) & 0x8) >> 1)) + .else + .set mr0_val, ((1 << 8) /* DLL Reset */ | \ + (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\ + (((tWR + 1) / 2) << 9) | \ + ((((tCL + 3) - 4) & 0x7) << 4) | \ + ((((tCL + 3) - 4) & 0x8) >> 1)) + .endif + +#define mr1_val ( \ + ((Rtt_Nom & 1) << 2) | \ + (((Rtt_Nom >> 1) & 1) << 6) | \ + (((Rtt_Nom >> 2) & 1) << 9) | \ + (DLL_DISABLE << 0) | \ + 0) +#define mr2_val ( \ + (Rtt_WR << 9) /* dynamic ODT */ | \ + (0 << 7) /* SRT: Ext. temp. (mutually exclusive with ASR!) */ | \ + (1 << 6) | /* ASR: Automatic Self Refresh */ \ + (((tCWL + 2) - 5) << 3) | \ + 0) +#define mr3_val 0 + +#define ESDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \ + (1 << 15) /* CON_REQ */ | \ + 0x80 | \ + (3 << 4) /* MRS command */ | \ + ((cs) << 3) | \ + ((mr) << 0) | \ + 0) + +#define ESDCFG0_VAL ( \ + (tRFC << 24) | \ + (tXS << 16) | \ + (tXP << 13) | \ + (tXPDLL << 9) | \ + (tFAW << 4) | \ + (tCL << 0)) \ + +#define ESDCFG1_VAL ( \ + (tRCD << 29) | \ + (tRP << 26) | \ + (tRC << 21) | \ + (tRAS << 16) | \ + (tRPA << 15) | \ + (tWR << 9) | \ + (tMRD << 5) | \ + (tCWL << 0)) \ + +#define ESDCFG2_VAL ( \ + (tDLLK << 16) | \ + (tRTP << 6) | \ + (tWTR << 3) | \ + (tRRD << 0)) + +#define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */ + +#define ESDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \ + ((COL_ADDR_BITS - 9) << 20) | \ + (BURST_LEN << 19) | \ + (1 << 16) | /* SDRAM bus width */ \ + ((-1) << (32 - BANK_ADDR_BITS))) + +#define ESDMISC_VAL ((ADDR_MIRROR << 19) | \ + (WALAT << 16) | \ + (BI_ON << 12) | \ + (0x3 << 9) | \ + (RALAT << 6) | \ + (DDR_TYPE << 3)) + +#define ESDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0)) + +#define ESDOTC_VAL ((tAOFPD << 27) | \ + (tAONPD << 24) | \ + (tANPD << 20) | \ + (tAXPD << 16) | \ + (tODTLon << 12) | \ + (tODTLoff << 4)) + +fcb_start: + b _start + .word 0x20424346 /* "FCB " marker */ + .word 0x01 /* FCB version number */ + .org 0x68 + .word 0x0 /* primary image starting page number */ + .word 0x0 /* secondary image starting page number */ + .word 0x6b + .word 0x6b + .word 0x0 /* DBBT start page (0 == NO DBBT) */ + .word 0 /* Bad block marker offset in main area (unused) */ + .org 0xac + .word 0 /* BI Swap disabled */ + .word 0 /* Bad Block marker offset in spare area */ +fcb_end: + + .org 0x400 +ivt_header: + .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40) +app_start_addr: + .long _start + .long 0x0 +dcd_ptr: + .long dcd_hdr +boot_data_ptr: + .word boot_data +self_ptr: + .word ivt_header +app_code_csf: + .word 0x0 + .word 0x0 +boot_data: + .long fcb_start +image_len: + .long CONFIG_U_BOOT_IMG_SIZE +plugin: + .word 0 +ivt_end: +#define DCD_VERSION 0x40 + +dcd_hdr: + .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) +dcd_start: + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib) + + MXC_DCD_ITEM(0x53fa8004, 0x00194005) @ set LDO to 1.3V + + /* disable all irrelevant clocks */ + MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR0, 0xffcf0fff) + MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR1, 0x000fffc3) + MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR2, 0x033c0000) + MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR3, 0x000000ff) + MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR4, 0x00000000) + MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR5, 0x00fff033) + MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR6, 0x0f00030f) + MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCGR7, 0xfff00000) + MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CMEOR, 0x00000000) +#if 1 + MXC_DCD_ITEM(CCM_BASE_ADDR + REG_CCOSR, (1 << 24) | (0xe << 16)) + MXC_DCD_ITEM(IOMUXC_BASE_ADDR + 0x320, 0x4) /* GPIO_3 => CLKO2 */ +#endif + MXC_DCD_ITEM(IOMUXC_BASE_ADDR + 0x340, 0x11) /* GPIO_17 => RESET_OUT */ + + MXC_DCD_ITEM(0x63fd800c, 0x00000000) /* M4IF: MUX NFC signals on WEIM */ +#if SDRAM_CLK > 333 + MXC_DCD_ITEM(0x53fd4014, 0x00888944) /* CBCDR */ +#else + MXC_DCD_ITEM(0x53fd4014, 0x00888644) /* CBCDR */ +#endif + MXC_DCD_ITEM(0x53fd4018, 0x00016154) /* CBCMR */ + + MXC_DCD_ITEM(0x53fd401c, 0xa6a2a020) /* CSCMR1 */ + MXC_DCD_ITEM(0x53fd4020, 0xb6b12f0a) /* CSCMR2 */ + MXC_DCD_ITEM(0x53fd4024, 0x00080b18) /* CSCDR1 */ + +#define DDR_SEL_VAL 2 +#define DSE_VAL 5 +#define ODT_VAL 2 + +#define DDR_SEL_SHIFT 25 +#define ODT_SHIFT 22 +#define DSE_SHIFT 19 +#define DDR_INPUT_SHIFT 9 +#define HYS_SHIFT 8 +#define PKE_SHIFT 7 +#define PUE_SHIFT 6 +#define PUS_SHIFT 4 + +#define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT) +#define DSE_MASK (DSE_VAL << DSE_SHIFT) +#define ODT_MASK (ODT_VAL << ODT_SHIFT) + +#define DQM_VAL DSE_MASK +#define SDQS_VAL (ODT_MASK | DSE_MASK | (1 << PUE_SHIFT)) +#define SDODT_VAL (DSE_MASK | (0 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) +#define SDCLK_VAL DSE_MASK +#define SDCKE_VAL ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) + + MXC_DCD_ITEM(0x53fa8724, DDR_SEL_MASK) /* DDR_TYPE: DDR3 */ + MXC_DCD_ITEM(0x53fa86f4, 0 << DDR_INPUT_SHIFT) /* DDRMODE_CTL */ + MXC_DCD_ITEM(0x53fa8714, 0 << DDR_INPUT_SHIFT) /* GRP_DDRMODE */ + MXC_DCD_ITEM(0x53fa86fc, 1 << PKE_SHIFT) /* GRP_DDRPKE */ + MXC_DCD_ITEM(0x53fa8710, 0 << HYS_SHIFT) /* GRP_DDRHYS */ + MXC_DCD_ITEM(0x53fa8708, 1 << PUE_SHIFT) /* GRP_DDRPK */ + + MXC_DCD_ITEM(0x53fa8584, DQM_VAL) /* DQM0 */ + MXC_DCD_ITEM(0x53fa8594, DQM_VAL) /* DQM1 */ + MXC_DCD_ITEM(0x53fa8560, DQM_VAL) /* DQM2 */ + MXC_DCD_ITEM(0x53fa8554, DQM_VAL) /* DQM3 */ + + MXC_DCD_ITEM(0x53fa857c, SDQS_VAL) /* SDQS0 */ + MXC_DCD_ITEM(0x53fa8590, SDQS_VAL) /* SDQS1 */ + MXC_DCD_ITEM(0x53fa8568, SDQS_VAL) /* SDQS2 */ + MXC_DCD_ITEM(0x53fa8558, SDQS_VAL) /* SDQS3 */ + + MXC_DCD_ITEM(0x53fa8580, SDODT_VAL) /* SDODT0 */ + MXC_DCD_ITEM(0x53fa8578, SDCLK_VAL) /* SDCLK0 */ + + MXC_DCD_ITEM(0x53fa8564, SDODT_VAL) /* SDODT1 */ + MXC_DCD_ITEM(0x53fa8570, SDCLK_VAL) /* SDCLK1 */ + + MXC_DCD_ITEM(0x53fa858c, SDCKE_VAL) /* SDCKE0 */ + MXC_DCD_ITEM(0x53fa855c, SDCKE_VAL) /* SDCKE1 */ + + MXC_DCD_ITEM(0x53fa8574, DSE_MASK) /* DRAM_CAS */ + MXC_DCD_ITEM(0x53fa8588, DSE_MASK) /* DRAM_RAS */ + + MXC_DCD_ITEM(0x53fa86f0, DSE_MASK) /* GRP_ADDDS */ + MXC_DCD_ITEM(0x53fa8720, DSE_MASK) /* GRP_CTLDS */ + MXC_DCD_ITEM(0x53fa8718, DSE_MASK) /* GRP_B0DS */ + MXC_DCD_ITEM(0x53fa871c, DSE_MASK) /* GRP_B1DS */ + MXC_DCD_ITEM(0x53fa8728, DSE_MASK) /* GRP_B2DS */ + MXC_DCD_ITEM(0x53fa872c, DSE_MASK) /* GRP_B3DS */ + + /* calibration defaults */ + MXC_DCD_ITEM(0x63fd904c, 0x001f001f) + MXC_DCD_ITEM(0x63fd9050, 0x001f001f) + MXC_DCD_ITEM(0x63fd907c, 0x011e011e) + MXC_DCD_ITEM(0x63fd9080, 0x011f0120) + MXC_DCD_ITEM(0x63fd9088, 0x3a393d3b) + MXC_DCD_ITEM(0x63fd9090, 0x3f3f3f3f) + + MXC_DCD_ITEM(0x63fd9018, ESDMISC_VAL) + MXC_DCD_ITEM(0x63fd9000, ESDCTL_VAL) + MXC_DCD_ITEM(0x63fd900c, ESDCFG0_VAL) + MXC_DCD_ITEM(0x63fd9010, ESDCFG1_VAL) + MXC_DCD_ITEM(0x63fd9014, ESDCFG2_VAL) + + MXC_DCD_ITEM(0x63fd902c, 0x000026d2) + MXC_DCD_ITEM(0x63fd9030, ESDOR_VAL) + MXC_DCD_ITEM(0x63fd9008, ESDOTC_VAL) + MXC_DCD_ITEM(0x63fd9004, ESDPDC_VAL_0) + + /* MR0..3 - CS0 */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 2, mr2_val)) /* MRS: MR2 */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, mr3_val)) /* MRS: MR3 */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: MR1 */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 0, mr0_val)) /* MRS: MR0 */ +#if BANK_ADDR_BITS > 1 + /* MR0..3 - CS1 */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 2, 0x0000)) /* MRS: MR2 */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 3, 0x0000)) /* MRS: MR3 */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 1, 0x0040)) /* MRS: MR1 */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(1, 0, mr0_val)) /* MRS: MR0 */ +#endif + MXC_DCD_ITEM(0x63fd9020, 3 << 14) /* disable refresh during calibration */ + MXC_DCD_ITEM(0x63fd9058, 0x00022222) + + MXC_DCD_ITEM(0x63fd90d0, 0x00000003) /* select default compare pattern for calibration */ + + /* ZQ calibration */ + MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */ + MXC_DCD_ITEM(0x63fd901c, 0x00008040) /* MRS: ZQ calibration */ + MXC_DCD_ITEM(0x63fd9040, 0x0539002b) /* Force ZQ calibration */ +zq_calib: + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd9040, 0x00010000) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib) + + /* Write Leveling */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 1, mr1_val | (1 << 7)) | (1 << 9)) /* MRS: start write leveling */ + MXC_DCD_ITEM(0x63fd901c, 0x00000000) + MXC_DCD_ITEM(0x63fd9048, 0x00000001) +wl_calib: + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd9048, 0x00000001) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib) + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */ + + /* DQS calibration */ + MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */ + MXC_DCD_ITEM(0x63fd907c, 0x90000000) /* reset RD fifo and start DQS calib. */ +dqs_calib: + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd907c, 0x90000000) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib) + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */ + + /* WR DL calibration */ + MXC_DCD_ITEM(0x63fd901c, 0x00000000) + MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */ + MXC_DCD_ITEM(0x63fd90a4, 0x00000010) +wr_dl_calib: /* 6c4 */ + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd90a4, 0x00000010) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib) + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */ + + /* RD DL calibration */ + MXC_DCD_ITEM(0x63fd901c, 0x04008010) /* precharge all */ + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, (1 << 2))) /* MRS: select MPR */ + MXC_DCD_ITEM(0x63fd90a0, 0x00000010) +rd_dl_calib: /* 70c */ + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, 0, 0x63fd90a0, 0x00000010) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dcd_end) + MXC_DCD_ITEM(0x63fd901c, ESDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */ + MXC_DCD_ITEM(0x63fd9020, (3 << 11) | (0 << 14)) /* refresh interval: 4 cycles every 64kHz period */ + MXC_DCD_ITEM(0x63fd9004, ESDPDC_VAL_1) + + MXC_DCD_ITEM(0x63fd901c, 0x00000000) + + /* setup NFC pads */ + /* MUX_SEL */ + MXC_DCD_ITEM(0x53fa819c, 0x00000000) @ EIM_DA0 + MXC_DCD_ITEM(0x53fa81a0, 0x00000000) @ EIM_DA1 + MXC_DCD_ITEM(0x53fa81a4, 0x00000000) @ EIM_DA2 + MXC_DCD_ITEM(0x53fa81a8, 0x00000000) @ EIM_DA3 + MXC_DCD_ITEM(0x53fa81ac, 0x00000000) @ EIM_DA4 + MXC_DCD_ITEM(0x53fa81b0, 0x00000000) @ EIM_DA5 + MXC_DCD_ITEM(0x53fa81b4, 0x00000000) @ EIM_DA6 + MXC_DCD_ITEM(0x53fa81b8, 0x00000000) @ EIM_DA7 + MXC_DCD_ITEM(0x53fa81dc, 0x00000000) @ WE_B + MXC_DCD_ITEM(0x53fa81e0, 0x00000000) @ RE_B + MXC_DCD_ITEM(0x53fa8228, 0x00000000) @ CLE + MXC_DCD_ITEM(0x53fa822c, 0x00000000) @ ALE + MXC_DCD_ITEM(0x53fa8230, 0x00000000) @ WP_B + MXC_DCD_ITEM(0x53fa8234, 0x00000000) @ RB0 + MXC_DCD_ITEM(0x53fa8238, 0x00000000) @ CS0 + /* PAD_CTL */ + MXC_DCD_ITEM(0x53fa84ec, 0x000000e4) @ EIM_DA0 + MXC_DCD_ITEM(0x53fa84f0, 0x000000e4) @ EIM_DA1 + MXC_DCD_ITEM(0x53fa84f4, 0x000000e4) @ EIM_DA2 + MXC_DCD_ITEM(0x53fa84f8, 0x000000e4) @ EIM_DA3 + MXC_DCD_ITEM(0x53fa84fc, 0x000000e4) @ EIM_DA4 + MXC_DCD_ITEM(0x53fa8500, 0x000000e4) @ EIM_DA5 + MXC_DCD_ITEM(0x53fa8504, 0x000000e4) @ EIM_DA6 + MXC_DCD_ITEM(0x53fa8508, 0x000000e4) @ EIM_DA7 + MXC_DCD_ITEM(0x53fa852c, 0x00000004) @ NANDF_WE_B + MXC_DCD_ITEM(0x53fa8530, 0x00000004) @ NANDF_RE_B + MXC_DCD_ITEM(0x53fa85a0, 0x00000004) @ NANDF_CLE_B + MXC_DCD_ITEM(0x53fa85a4, 0x00000004) @ NANDF_ALE_B + MXC_DCD_ITEM(0x53fa85a8, 0x000000e4) @ NANDF_WE_B + MXC_DCD_ITEM(0x53fa85ac, 0x000000e4) @ NANDF_RB0 + MXC_DCD_ITEM(0x53fa85b0, 0x00000004) @ NANDF_CS0 +dcd_end: + .ifgt dcd_end - dcd_start - 1768 + .error "DCD too large!" + .endif diff --git a/board/karo/tx53/tx53.c b/board/karo/tx53/tx53.c new file mode 100644 index 0000000000..51845f8ac4 --- /dev/null +++ b/board/karo/tx53/tx53.c @@ -0,0 +1,1042 @@ +/* + * Copyright (C) 2011 Lothar Waßmann + * based on: board/freescale/mx28_evk.c (C) 2010 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/karo.h" + +#define TX53_FEC_RST_GPIO IMX_GPIO_NR(7, 6) +#define TX53_FEC_PWR_GPIO IMX_GPIO_NR(3, 20) +#define TX53_FEC_INT_GPIO IMX_GPIO_NR(2, 4) +#define TX53_LED_GPIO IMX_GPIO_NR(2, 20) + +#define TX53_LCD_PWR_GPIO IMX_GPIO_NR(2, 31) +#define TX53_LCD_RST_GPIO IMX_GPIO_NR(3, 29) +#define TX53_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1) + +#define TX53_RESET_OUT_GPIO IMX_GPIO_NR(7, 12) + +DECLARE_GLOBAL_DATA_PTR; + +#define MX53_GPIO_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_DSE_HIGH | PAD_CTL_PUS_22K_UP) + +#define TX53_SDHC_PAD_CTRL MUX_PAD_CTRL(PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST | PAD_CTL_PUS_47K_UP) + +static iomux_v3_cfg_t tx53_pads[] = { + /* NAND flash pads are set up in lowlevel_init.S */ + + /* UART pads */ +#if CONFIG_MXC_UART_BASE == UART1_BASE + MX53_PAD_PATA_DIOW__UART1_TXD_MUX, + MX53_PAD_PATA_DMACK__UART1_RXD_MUX, + MX53_PAD_PATA_IORDY__UART1_RTS, + MX53_PAD_PATA_RESET_B__UART1_CTS, +#endif +#if CONFIG_MXC_UART_BASE == UART2_BASE + MX53_PAD_PATA_BUFFER_EN__UART2_RXD_MUX, + MX53_PAD_PATA_DMARQ__UART2_TXD_MUX, + MX53_PAD_PATA_DIOR__UART2_RTS, + MX53_PAD_PATA_INTRQ__UART2_CTS, +#endif +#if CONFIG_MXC_UART_BASE == UART3_BASE + MX53_PAD_PATA_CS_0__UART3_TXD_MUX, + MX53_PAD_PATA_CS_1__UART3_RXD_MUX, + MX53_PAD_PATA_DA_2__UART3_RTS, + MX53_PAD_PATA_DA_1__UART3_CTS, +#endif + /* internal I2C */ + MX53_PAD_EIM_D28__I2C1_SDA | MX53_GPIO_PAD_CTRL, + MX53_PAD_EIM_D21__I2C1_SCL | MX53_GPIO_PAD_CTRL, + + /* FEC PHY GPIO functions */ + MX53_PAD_EIM_D20__GPIO3_20, /* PHY POWER */ + MX53_PAD_PATA_DA_0__GPIO7_6, /* PHY RESET */ + MX53_PAD_PATA_DATA4__GPIO2_4, /* PHY INT */ + + /* FEC functions */ + MX53_PAD_FEC_MDC__FEC_MDC, + MX53_PAD_FEC_MDIO__FEC_MDIO, + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK, + MX53_PAD_FEC_RX_ER__FEC_RX_ER, + MX53_PAD_FEC_CRS_DV__FEC_RX_DV, + MX53_PAD_FEC_RXD1__FEC_RDATA_1, + MX53_PAD_FEC_RXD0__FEC_RDATA_0, + MX53_PAD_FEC_TX_EN__FEC_TX_EN, + MX53_PAD_FEC_TXD1__FEC_TDATA_1, + MX53_PAD_FEC_TXD0__FEC_TDATA_0, +}; + +static const struct gpio tx53_gpios[] = { + { TX53_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", }, + { TX53_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", }, + { TX53_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", }, + { TX53_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", }, +}; + +/* + * Functions + */ +/* placed in section '.data' to prevent overwriting relocation info + * overlayed with bss + */ +static u32 wrsr __attribute__((section(".data"))); + +#define WRSR_POR (1 << 4) +#define WRSR_TOUT (1 << 1) +#define WRSR_SFTW (1 << 0) + +static void print_reset_cause(void) +{ + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR; + u32 srsr; + char *dlm = ""; + + printf("Reset cause: "); + + srsr = readl(&src_regs->srsr); + wrsr = readw(wdt_base + 4); + + if (wrsr & WRSR_POR) { + printf("%sPOR", dlm); + dlm = " | "; + } + if (srsr & 0x00004) { + printf("%sCSU", dlm); + dlm = " | "; + } + if (srsr & 0x00008) { + printf("%sIPP USER", dlm); + dlm = " | "; + } + if (srsr & 0x00010) { + if (wrsr & WRSR_SFTW) { + printf("%sSOFT", dlm); + dlm = " | "; + } + if (wrsr & WRSR_TOUT) { + printf("%sWDOG", dlm); + dlm = " | "; + } + } + if (srsr & 0x00020) { + printf("%sJTAG HIGH-Z", dlm); + dlm = " | "; + } + if (srsr & 0x00040) { + printf("%sJTAG SW", dlm); + dlm = " | "; + } + if (srsr & 0x10000) { + printf("%sWARM BOOT", dlm); + dlm = " | "; + } + if (dlm[0] == '\0') + printf("unknown"); + + printf("\n"); +} + +static void tx53_print_cpuinfo(void) +{ + u32 cpurev; + + cpurev = get_cpu_rev(); + + printf("CPU: Freescale i.MX53 rev%d.%d at %d MHz\n", + (cpurev & 0x000F0) >> 4, + (cpurev & 0x0000F) >> 0, + mxc_get_clock(MXC_ARM_CLK) / 1000000); + + print_reset_cause(); +} + +int board_early_init_f(void) +{ + struct mxc_ccm_reg *ccm_regs = (void *)CCM_BASE_ADDR; + + gpio_request_array(tx53_gpios, ARRAY_SIZE(tx53_gpios)); + imx_iomux_v3_setup_multiple_pads(tx53_pads, ARRAY_SIZE(tx53_pads)); + + writel(0x77777777, AIPS1_BASE_ADDR + 0x00); + writel(0x77777777, AIPS1_BASE_ADDR + 0x04); + + writel(0x00000000, AIPS1_BASE_ADDR + 0x40); + writel(0x00000000, AIPS1_BASE_ADDR + 0x44); + writel(0x00000000, AIPS1_BASE_ADDR + 0x48); + writel(0x00000000, AIPS1_BASE_ADDR + 0x4c); + writel(0x00000000, AIPS1_BASE_ADDR + 0x50); + + writel(0x77777777, AIPS2_BASE_ADDR + 0x00); + writel(0x77777777, AIPS2_BASE_ADDR + 0x04); + + writel(0x00000000, AIPS2_BASE_ADDR + 0x40); + writel(0x00000000, AIPS2_BASE_ADDR + 0x44); + writel(0x00000000, AIPS2_BASE_ADDR + 0x48); + writel(0x00000000, AIPS2_BASE_ADDR + 0x4c); + writel(0x00000000, AIPS2_BASE_ADDR + 0x50); + + writel(0xffcf0fff, &ccm_regs->CCGR0); + writel(0x000fffc3, &ccm_regs->CCGR1); + writel(0x033c0000, &ccm_regs->CCGR2); + writel(0x000000ff, &ccm_regs->CCGR3); + writel(0x00000000, &ccm_regs->CCGR4); + writel(0x00fff033, &ccm_regs->CCGR5); + writel(0x0f00030f, &ccm_regs->CCGR6); + writel(0xfff00000, &ccm_regs->CCGR7); + writel(0x00000000, &ccm_regs->cmeor); + + return 0; +} + +int board_init(void) +{ + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000; + return 0; +} + +int dram_init(void) +{ + int ret; + + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + PHYS_SDRAM_1_SIZE); + + ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, + CONFIG_SYS_SDRAM_CLK, MXC_DDR_CLK); + if (ret) + printf("%s: Failed to set DDR clock to %u MHz: %d\n", __func__, + CONFIG_SYS_SDRAM_CLK, ret); + else + debug("%s: DDR clock set to %u.%03u MHz (desig.: %u.000 MHz)\n", + __func__, mxc_get_clock(MXC_DDR_CLK) / 1000000, + mxc_get_clock(MXC_DDR_CLK) / 1000 % 1000, + CONFIG_SYS_SDRAM_CLK); + return ret; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); +#if CONFIG_NR_DRAM_BANKS > 1 + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, + PHYS_SDRAM_2_SIZE); +#endif +} + +#ifdef CONFIG_CMD_MMC +static const iomux_v3_cfg_t mmc0_pads[] = { + MX53_PAD_SD1_CMD__ESDHC1_CMD | TX53_SDHC_PAD_CTRL, + MX53_PAD_SD1_CLK__ESDHC1_CLK | TX53_SDHC_PAD_CTRL, + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 | TX53_SDHC_PAD_CTRL, + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 | TX53_SDHC_PAD_CTRL, + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 | TX53_SDHC_PAD_CTRL, + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 | TX53_SDHC_PAD_CTRL, + /* SD1 CD */ + MX53_PAD_EIM_D24__GPIO3_24 | MX53_GPIO_PAD_CTRL, +}; + +static const iomux_v3_cfg_t mmc1_pads[] = { + MX53_PAD_SD2_CMD__ESDHC2_CMD | TX53_SDHC_PAD_CTRL, + MX53_PAD_SD2_CLK__ESDHC2_CLK | TX53_SDHC_PAD_CTRL, + MX53_PAD_SD2_DATA0__ESDHC2_DAT0 | TX53_SDHC_PAD_CTRL, + MX53_PAD_SD2_DATA1__ESDHC2_DAT1 | TX53_SDHC_PAD_CTRL, + MX53_PAD_SD2_DATA2__ESDHC2_DAT2 | TX53_SDHC_PAD_CTRL, + MX53_PAD_SD2_DATA3__ESDHC2_DAT3 | TX53_SDHC_PAD_CTRL, + /* SD2 CD */ + MX53_PAD_EIM_D25__GPIO3_25 | MX53_GPIO_PAD_CTRL, +}; + +static struct tx53_esdhc_cfg { + const iomux_v3_cfg_t *pads; + int num_pads; + struct fsl_esdhc_cfg cfg; + int cd_gpio; +} tx53_esdhc_cfg[] = { + { + .pads = mmc0_pads, + .num_pads = ARRAY_SIZE(mmc0_pads), + .cfg = { + .esdhc_base = (void __iomem *)MMC_SDHC1_BASE_ADDR, + .max_bus_width = 4, + }, + .cd_gpio = IMX_GPIO_NR(3, 24), + }, + { + .pads = mmc1_pads, + .num_pads = ARRAY_SIZE(mmc1_pads), + .cfg = { + .esdhc_base = (void __iomem *)MMC_SDHC2_BASE_ADDR, + .max_bus_width = 4, + }, + .cd_gpio = IMX_GPIO_NR(3, 25), + }, +}; + +#if 1 +#define to_tx53_esdhc_cfg(p) container_of(p, struct tx53_esdhc_cfg, cfg) +#else +static struct tx53_esdhc_cfg *to_tx53_esdhc_cfg(struct fsl_esdhc_cfg *cfg) +{ + void *p = cfg; + + return p - offsetof(struct tx53_esdhc_cfg, cfg); +} +#endif + +int board_mmc_getcd(struct mmc *mmc) +{ + struct tx53_esdhc_cfg *cfg = to_tx53_esdhc_cfg(mmc->priv); + + if (cfg->cd_gpio < 0) + return cfg->cd_gpio; + + debug("SD card %d is %spresent\n", + cfg - tx53_esdhc_cfg, + gpio_get_value(cfg->cd_gpio) ? "NOT " : ""); + return !gpio_get_value(cfg->cd_gpio); +} + +int board_mmc_init(bd_t *bis) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(tx53_esdhc_cfg); i++) { + struct mmc *mmc; + struct tx53_esdhc_cfg *cfg = &tx53_esdhc_cfg[i]; + int ret; + + if (i >= CONFIG_SYS_FSL_ESDHC_NUM) + break; + + imx_iomux_v3_setup_multiple_pads(cfg->pads, + cfg->num_pads); + cfg->cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); + + fsl_esdhc_initialize(bis, &cfg->cfg); + + ret = gpio_request_one(cfg->cd_gpio, + GPIOF_INPUT, "MMC CD"); + if (ret) { + printf("Error %d requesting GPIO%d_%d\n", + ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32); + continue; + } + + mmc = find_mmc_device(i); + if (mmc == NULL) + continue; + if (board_mmc_getcd(mmc) > 0) + mmc_init(mmc); + } + return 0; +} +#endif /* CONFIG_CMD_MMC */ + +#ifdef CONFIG_FEC_MXC + +#ifndef ETH_ALEN +#define ETH_ALEN 6 +#endif + +void imx_get_mac_from_fuse(int dev_id, unsigned char *mac) +{ + int i; + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; + struct fuse_bank *bank = &iim->bank[1]; + struct fuse_bank1_regs *fuse = (struct fuse_bank1_regs *)bank->fuse_regs; + + if (dev_id > 0) + return; + + for (i = 0; i < ETH_ALEN; i++) + mac[i] = readl(&fuse->mac_addr[i]); +} + +#define FEC_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST) +#define FEC_PAD_CTL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST) +#define GPIO_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) + +int board_eth_init(bd_t *bis) +{ + int ret; + unsigned char mac[ETH_ALEN]; + + /* delay at least 21ms for the PHY internal POR signal to deassert */ + udelay(22000); + + /* Deassert RESET to the external phy */ + gpio_set_value(TX53_FEC_RST_GPIO, 1); + + ret = cpu_eth_init(bis); + if (ret) { + printf("cpu_eth_init() failed: %d\n", ret); + return ret; + } + + imx_get_mac_from_fuse(0, mac); + eth_setenv_enetaddr("ethaddr", mac); + printf("MAC addr from fuse: %pM\n", mac); + + return ret; +} +#endif /* CONFIG_FEC_MXC */ + +enum { + LED_STATE_INIT = -1, + LED_STATE_OFF, + LED_STATE_ON, +}; + +void show_activity(int arg) +{ + static int led_state = LED_STATE_INIT; + static ulong last; + + if (led_state == LED_STATE_INIT) { + last = get_timer(0); + gpio_set_value(TX53_LED_GPIO, 1); + led_state = LED_STATE_ON; + } else { + if (get_timer(last) > CONFIG_SYS_HZ) { + last = get_timer(0); + if (led_state == LED_STATE_ON) { + gpio_set_value(TX53_LED_GPIO, 0); + } else { + gpio_set_value(TX53_LED_GPIO, 1); + } + led_state = 1 - led_state; + } + } +} + +static const iomux_v3_cfg_t stk5_pads[] = { + /* SW controlled LED on STK5 baseboard */ + MX53_PAD_EIM_A18__GPIO2_20, + + /* I2C bus on DIMM pins 40/41 */ + MX53_PAD_GPIO_6__I2C3_SDA | MX53_GPIO_PAD_CTRL, + MX53_PAD_GPIO_3__I2C3_SCL | MX53_GPIO_PAD_CTRL, + + /* TSC200x PEN IRQ */ + MX53_PAD_EIM_D26__GPIO3_26 | MX53_GPIO_PAD_CTRL, + + /* EDT-FT5x06 Polytouch panel */ + MX53_PAD_NANDF_CS2__GPIO6_15 | MX53_GPIO_PAD_CTRL, /* IRQ */ + MX53_PAD_EIM_A16__GPIO2_22 | MX53_GPIO_PAD_CTRL, /* RESET */ + MX53_PAD_EIM_A17__GPIO2_21 | MX53_GPIO_PAD_CTRL, /* WAKE */ + + /* USBH1 */ + MX53_PAD_EIM_D31__GPIO3_31 | MX53_GPIO_PAD_CTRL, /* VBUSEN */ + MX53_PAD_EIM_D30__GPIO3_30 | MX53_GPIO_PAD_CTRL, /* OC */ + /* USBOTG */ + MX53_PAD_GPIO_7__GPIO1_7, /* VBUSEN */ + MX53_PAD_GPIO_8__GPIO1_8, /* OC */ + + /* DS1339 Interrupt */ + MX53_PAD_DI0_PIN4__GPIO4_20 | MX53_GPIO_PAD_CTRL, +}; + +static const struct gpio stk5_gpios[] = { + { TX53_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", }, + + { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", }, + { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", }, + { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", }, + { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", }, +}; + +#ifdef CONFIG_LCD +static ushort tx53_cmap[256]; +vidinfo_t panel_info = { + /* set to max. size supported by SoC */ + .vl_col = 1600, + .vl_row = 1200, + + .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ + .cmap = tx53_cmap, +}; + +static struct fb_videomode tx53_fb_modes[] = { + { + /* Standard VGA timing */ + .name = "VGA", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = KHZ2PICOS(25175), + .left_margin = 48, + .hsync_len = 96, + .right_margin = 16, + .upper_margin = 31, + .vsync_len = 2, + .lower_margin = 12, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ETV570 640 x 480 display. Syncs low active, + * DE high active, 115.2 mm x 86.4 mm display area + * VGA compatible timing + */ + .name = "ETV570", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = KHZ2PICOS(25175), + .left_margin = 114, + .hsync_len = 30, + .right_margin = 16, + .upper_margin = 32, + .vsync_len = 3, + .lower_margin = 10, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ET0350G0DH6 320 x 240 display. + * 70.08 mm x 52.56 mm display area. + */ + .name = "ET0350", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = KHZ2PICOS(6500), + .left_margin = 68 - 34, + .hsync_len = 34, + .right_margin = 20, + .upper_margin = 18 - 3, + .vsync_len = 3, + .lower_margin = 4, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ET0430G0DH6 480 x 272 display. + * 95.04 mm x 53.856 mm display area. + */ + .name = "ET0430", + .refresh = 60, + .xres = 480, + .yres = 272, + .pixclock = KHZ2PICOS(9000), + .left_margin = 2, + .hsync_len = 41, + .right_margin = 2, + .upper_margin = 2, + .vsync_len = 10, + .lower_margin = 2, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ET0500G0DH6 800 x 480 display. + * 109.6 mm x 66.4 mm display area. + */ + .name = "ET0500", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = KHZ2PICOS(33260), + .left_margin = 216 - 128, + .hsync_len = 128, + .right_margin = 1056 - 800 - 216, + .upper_margin = 35 - 2, + .vsync_len = 2, + .lower_margin = 525 - 480 - 35, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ETQ570G0DH6 320 x 240 display. + * 115.2 mm x 86.4 mm display area. + */ + .name = "ETQ570", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = KHZ2PICOS(6400), + .left_margin = 38, + .hsync_len = 30, + .right_margin = 30, + .upper_margin = 16, /* 15 according to datasheet */ + .vsync_len = 3, /* TVP -> 1>x>5 */ + .lower_margin = 4, /* 4.5 according to datasheet */ + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ET0700G0DH6 800 x 480 display. + * 152.4 mm x 91.44 mm display area. + */ + .name = "ET0700", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = KHZ2PICOS(33260), + .left_margin = 216 - 128, + .hsync_len = 128, + .right_margin = 1056 - 800 - 216, + .upper_margin = 35 - 2, + .vsync_len = 2, + .lower_margin = 525 - 480 - 35, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* unnamed entry for assigning parameters parsed from 'video_mode' string */ + .refresh = 60, + .left_margin = 48, + .hsync_len = 96, + .right_margin = 16, + .upper_margin = 31, + .vsync_len = 2, + .lower_margin = 12, + .sync = FB_SYNC_CLK_LAT_FALL, + }, +}; + +static int lcd_enabled = 1; + +void lcd_enable(void) +{ + /* HACK ALERT: + * global variable from common/lcd.c + * Set to 0 here to prevent messages from going to LCD + * rather than serial console + */ + lcd_is_enabled = 0; + + karo_load_splashimage(1); + if (lcd_enabled) { + debug("Switching LCD on\n"); + gpio_set_value(TX53_LCD_PWR_GPIO, 1); + udelay(100); + gpio_set_value(TX53_LCD_RST_GPIO, 1); + udelay(300000); + gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 0); + } +} + +void lcd_disable(void) +{ + printf("Disabling LCD\n"); +} + +void lcd_panel_disable(void) +{ + if (lcd_enabled) { + debug("Switching LCD off\n"); + gpio_set_value(TX53_LCD_BACKLIGHT_GPIO, 1); + gpio_set_value(TX53_LCD_RST_GPIO, 0); + gpio_set_value(TX53_LCD_PWR_GPIO, 0); + } +} + +static const iomux_v3_cfg_t stk5_lcd_pads[] = { + /* LCD RESET */ + MX53_PAD_EIM_D29__GPIO3_29 | MX53_GPIO_PAD_CTRL, + /* LCD POWER_ENABLE */ + MX53_PAD_EIM_EB3__GPIO2_31 | MX53_GPIO_PAD_CTRL, + /* LCD Backlight (PWM) */ + MX53_PAD_GPIO_1__GPIO1_1 | MX53_GPIO_PAD_CTRL, + + /* Display */ + MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK, + MX53_PAD_DI0_PIN15__IPU_DI0_PIN15, + MX53_PAD_DI0_PIN2__IPU_DI0_PIN2, + MX53_PAD_DI0_PIN3__IPU_DI0_PIN3, + MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0, + MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1, + MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2, + MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3, + MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4, + MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5, + MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6, + MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7, + MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8, + MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9, + MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10, + MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11, + MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12, + MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13, + MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14, + MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15, + MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16, + MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17, + MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18, + MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19, + MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20, + MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21, + MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22, + MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23, + + /* LVDS option */ + MX53_PAD_LVDS1_TX3_P__LDB_LVDS1_TX3, + MX53_PAD_LVDS1_TX2_P__LDB_LVDS1_TX2, + MX53_PAD_LVDS1_CLK_P__LDB_LVDS1_CLK, + MX53_PAD_LVDS1_TX1_P__LDB_LVDS1_TX1, + MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0, + MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3, + MX53_PAD_LVDS0_CLK_P__LDB_LVDS0_CLK, + MX53_PAD_LVDS0_TX2_P__LDB_LVDS0_TX2, + MX53_PAD_LVDS0_TX1_P__LDB_LVDS0_TX1, + MX53_PAD_LVDS0_TX0_P__LDB_LVDS0_TX0, +}; + +static const struct gpio stk5_lcd_gpios[] = { + { TX53_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", }, + { TX53_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", }, + { TX53_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, +}; + +void lcd_ctrl_init(void *lcdbase) +{ + int color_depth = 24; + char *vm; + unsigned long val; + int refresh = 60; + struct fb_videomode *p = &tx53_fb_modes[0]; + struct fb_videomode fb_mode; + int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0; + int pix_fmt = 0; + ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3; + unsigned long di_clk_rate = 65000000; + + if (!lcd_enabled) { + debug("LCD disabled\n"); + return; + } + + if (tstc() || (wrsr & WRSR_TOUT)) { + debug("Disabling LCD\n"); + lcd_enabled = 0; + return; + } + + karo_fdt_move_fdt(); + + vm = getenv("video_mode"); + if (vm == NULL) { + debug("Disabling LCD\n"); + lcd_enabled = 0; + return; + } + if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) { + p = &fb_mode; + debug("Using video mode from FDT\n"); + vm += strlen(vm); + if (fb_mode.xres < panel_info.vl_col) + panel_info.vl_col = fb_mode.xres; + if (fb_mode.yres < panel_info.vl_row) + panel_info.vl_row = fb_mode.yres; + } + if (p->name != NULL) + debug("Trying compiled-in video modes\n"); + while (p->name != NULL) { + if (strcmp(p->name, vm) == 0) { + debug("Using video mode: '%s'\n", p->name); + vm += strlen(vm); + break; + } + p++; + } + if (*vm != '\0') + debug("Trying to decode video_mode: '%s'\n", vm); + while (*vm != '\0') { + if (*vm >= '0' && *vm <= '9') { + char *end; + + val = simple_strtoul(vm, &end, 0); + if (end > vm) { + if (!xres_set) { + if (val > panel_info.vl_col) + val = panel_info.vl_col; + p->xres = val; + panel_info.vl_col = val; + xres_set = 1; + } else if (!yres_set) { + if (val > panel_info.vl_row) + val = panel_info.vl_row; + p->yres = val; + panel_info.vl_row = val; + yres_set = 1; + } else if (!bpp_set) { + switch (val) { + case 32: + case 24: + if (pix_fmt == IPU_PIX_FMT_LVDS666) + pix_fmt = IPU_PIX_FMT_LVDS888; + /* fallthru */ + case 16: + case 8: + color_depth = val; + break; + + case 18: + if (pix_fmt == IPU_PIX_FMT_LVDS666) { + color_depth = val; + break; + } + /* fallthru */ + default: + printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n", + end - vm, vm, color_depth); + } + bpp_set = 1; + } else if (!refresh_set) { + refresh = val; + refresh_set = 1; + } + } + vm = end; + } + switch (*vm) { + case '@': + bpp_set = 1; + /* fallthru */ + case '-': + yres_set = 1; + /* fallthru */ + case 'x': + xres_set = 1; + /* fallthru */ + case 'M': + case 'R': + vm++; + break; + + default: + if (!pix_fmt) { + char *tmp; + + if (strncmp(vm, "LVDS", 4) == 0) { + pix_fmt = IPU_PIX_FMT_LVDS666; + di_clk_parent = DI_PCLK_LDB; + } else { + pix_fmt = IPU_PIX_FMT_RGB24; + } + tmp = strchr(vm, ':'); + if (tmp) + vm = tmp; + } + if (*vm != '\0') + vm++; + } + } + if (p->xres == 0 || p->yres == 0) { + printf("Invalid video mode: %s\n", getenv("video_mode")); + lcd_enabled = 0; + printf("Supported video modes are:"); + for (p = &tx53_fb_modes[0]; p->name != NULL; p++) { + printf(" %s", p->name); + } + printf("\n"); + return; + } + + p->pixclock = KHZ2PICOS(refresh * + (p->xres + p->left_margin + p->right_margin + p->hsync_len) * + (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) + / 1000); + debug("Pixel clock set to %lu.%03lu MHz\n", + PICOS2KHZ(p->pixclock) / 1000, + PICOS2KHZ(p->pixclock) % 1000); + + gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios)); + imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads, + ARRAY_SIZE(stk5_lcd_pads)); + + debug("Initializing FB driver\n"); + if (!pix_fmt) + pix_fmt = IPU_PIX_FMT_RGB24; + else if (pix_fmt == IPU_PIX_FMT_LVDS666) { + writel(0x01, IOMUXC_BASE_ADDR + 8); + } else if (pix_fmt == IPU_PIX_FMT_LVDS888) { + writel(0x21, IOMUXC_BASE_ADDR + 8); + } + if (pix_fmt != IPU_PIX_FMT_RGB24) { + struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + /* enable LDB & DI0 clock */ + writel(readl(&ccm_regs->CCGR6) | (3 << 28) | (3 << 10), + &ccm_regs->CCGR6); + } + + if (karo_load_splashimage(0) == 0) { + debug("Initializing LCD controller\n"); + ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1); + } else { + debug("Skipping initialization of LCD controller\n"); + } +} +#else +#define lcd_enabled 0 +#endif /* CONFIG_LCD */ + +static void stk5_board_init(void) +{ + gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios)); + imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads)); +} + +static void stk5v3_board_init(void) +{ + stk5_board_init(); +} + +static void stk5v5_board_init(void) +{ + stk5_board_init(); + + gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH, + "Flexcan Transceiver"); + imx_iomux_v3_setup_pad(MX53_PAD_DISP0_DAT0__GPIO4_21); +} + +static void tx53_set_cpu_clock(void) +{ + unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0); + int ret; + + if (tstc() || (wrsr & WRSR_TOUT)) + return; + + if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000) + return; + + ret = mxc_set_clock(CONFIG_SYS_MX5_HCLK, cpu_clk, MXC_ARM_CLK); + if (ret != 0) { + printf("Error: Failed to set CPU clock to %lu MHz\n", cpu_clk); + return; + } + printf("CPU clock set to %u.%03u MHz\n", + mxc_get_clock(MXC_ARM_CLK) / 1000000, + mxc_get_clock(MXC_ARM_CLK) / 1000 % 1000); +} + +int board_late_init(void) +{ + int ret = 0; + const char *baseboard; + + tx53_set_cpu_clock(); + karo_fdt_move_fdt(); + + baseboard = getenv("baseboard"); + if (!baseboard) + goto exit; + + if (strncmp(baseboard, "stk5", 4) == 0) { + printf("Baseboard: %s\n", baseboard); + if ((strlen(baseboard) == 4) || + strcmp(baseboard, "stk5-v3") == 0) { + stk5v3_board_init(); + } else if (strcmp(baseboard, "stk5-v5") == 0) { + stk5v5_board_init(); + } else { + printf("WARNING: Unsupported STK5 board rev.: %s\n", + baseboard + 4); + } + } else { + printf("WARNING: Unsupported baseboard: '%s'\n", + baseboard); + ret = -EINVAL; + } + +exit: + gpio_set_value(TX53_RESET_OUT_GPIO, 1); + return ret; +} + +int checkboard(void) +{ + tx53_print_cpuinfo(); + + printf("Board: Ka-Ro TX53-xx3%s\n", + TX53_MOD_SUFFIX); + + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_FDT_FIXUP_PARTITIONS +#include +#include +struct node_info nodes[] = { + { "fsl,imx53-nand", MTD_DEV_TYPE_NAND, }, +}; + +#else +#define fdt_fixup_mtdparts(b,n,c) do { } while (0) +#endif + +static void tx53_fixup_flexcan(void *blob) +{ + const char *baseboard = getenv("baseboard"); + + if (baseboard && strcmp(baseboard, "stk5-v5") == 0) + return; + + karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x53fc8000, "transceiver-switch"); + karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x53fcc000, "transceiver-switch"); +} + +#ifdef CONFIG_SYS_TX53_HWREV_2 +void tx53_fixup_rtc(void *blob) +{ + karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupt-parent"); + karo_fdt_del_prop(blob, "dallas,ds1339", 0x68, "interrupts"); +} +#else +static inline void tx53_fixup_rtc(void *blob) +{ +} +#endif + +void ft_board_setup(void *blob, bd_t *bd) +{ + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + fdt_fixup_ethernet(blob); + + karo_fdt_enable_node(blob, "ipu", getenv("video_mode") != NULL); + karo_fdt_fixup_touchpanel(blob); + karo_fdt_fixup_usb_otg(blob, "fsl,imx-otg", "fsl,usbphy"); + tx53_fixup_flexcan(blob); + tx53_fixup_rtc(blob); +} +#endif diff --git a/board/karo/tx53/u-boot.lds b/board/karo/tx53/u-boot.lds new file mode 100644 index 0000000000..d775349e8e --- /dev/null +++ b/board/karo/tx53/u-boot.lds @@ -0,0 +1,99 @@ +/* + * (C) Copyright 2012 Lothar Waßmann + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + .text : + { + KEEP(board/karo/tx53/lowlevel_init.o (.text*)) + *(.__image_copy_start) + CPUDIR/start.o (.text*) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + .image_copy_end : + { + *(.__image_copy_end) + } + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rel.dyn : + { + *(.rel*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + _end = .; + +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + /DISCARD/ : { *(.bss*) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynsym*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.hash*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/board/karo/tx6/Makefile b/board/karo/tx6/Makefile new file mode 100644 index 0000000000..37c90e7620 --- /dev/null +++ b/board/karo/tx6/Makefile @@ -0,0 +1,31 @@ +# +# (C) Copyright 2009 DENX Software Engineering +# Author: John Rigby +# +# SPDX-License-Identifier: GPL-2.0+ +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := tx6qdl.o +SOBJS := lowlevel_init.o +ifeq ($(CONFIG_CMD_ROMUPDATE),y) + COBJS += flash.o +endif + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +######################################################################### + +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/karo/tx6/config.mk b/board/karo/tx6/config.mk new file mode 100644 index 0000000000..c899960a1c --- /dev/null +++ b/board/karo/tx6/config.mk @@ -0,0 +1,29 @@ +# stack is allocated below CONFIG_SYS_TEXT_BASE +CONFIG_SYS_TEXT_BASE := 0x27800000 +#CONFIG_SYS_TEXT_BASE := 0x17800000 +#CONFIG_SPL_TEXT_BASE := 0x00000000 + +LOGO_BMP = logos/karo.bmp +#PLATFORM_CPPFLAGS += -DDEBUG +#PLATFORM_CPPFLAGS += -Wno-unused-but-set-variable +PLATFORM_CPPFLAGS += -Werror + +# calculate U_BOOT_IMG_SIZE to be at least 3 eraseblocks larger than the maximum expected image size +CONFIG_SYS_NAND_BLOCK_SIZE := 131072 +CONFIG_SYS_NAND_BLOCKS := 1024 +ifneq ($(CONFIG_SYS_NAND_BLOCK_SIZE),) +CONFIG_U_BOOT_IMG_SIZE = $(shell echo 'e=$(CONFIG_SYS_NAND_BLOCK_SIZE);s=640*1024;s + (e - s % e) % e + 3*e' | bc) +CONFIG_SYS_USERFS_SIZE = $(shell expr \( $(CONFIG_SYS_NAND_BLOCKS) - 9 \) \* $(CONFIG_SYS_NAND_BLOCK_SIZE) - $(CONFIG_U_BOOT_IMG_SIZE) - 36 \* 1048576) +CONFIG_SYS_USERFS_SIZE2 = $(shell expr \( $(CONFIG_SYS_NAND_BLOCKS) - 12 \) \* $(CONFIG_SYS_NAND_BLOCK_SIZE) - $(CONFIG_U_BOOT_IMG_SIZE) - 36 \* 1048576) + +PLATFORM_CPPFLAGS += -DCONFIG_SYS_NAND_BLOCK_SIZE=$(CONFIG_SYS_NAND_BLOCK_SIZE) +PLATFORM_CPPFLAGS += -DCONFIG_U_BOOT_IMG_SIZE=$(CONFIG_U_BOOT_IMG_SIZE) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_U_BOOT_PART_SIZE=$(shell printf "%uk" `expr $(CONFIG_U_BOOT_IMG_SIZE) / 1024`) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_NAND_U_BOOT_OFFS=$(shell printf "0x%x" `expr $(CONFIG_SYS_NAND_BLOCK_SIZE)`) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_ENV_PART_SIZE=$(shell printf "%uk" `expr 3 \* $(CONFIG_SYS_NAND_BLOCK_SIZE) / 1024`) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_USERFS_PART_SIZE=$(shell printf "%uk" `expr $(CONFIG_SYS_USERFS_SIZE) / 1024`) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_USERFS_PART_SIZE2=$(shell printf "%uk" `expr $(CONFIG_SYS_USERFS_SIZE) / 1024`) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_DTB_PART_SIZE=$(shell printf "%uk" `expr $(CONFIG_SYS_NAND_BLOCK_SIZE) / 1024`) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_NAND_BBT_SIZE=$(shell printf "%uk" `expr 4 \* $(CONFIG_SYS_NAND_BLOCK_SIZE) / 1024`) +PLATFORM_CPPFLAGS += -DCONFIG_SYS_NAND_BBT_OFFSET=$(shell printf "0x%x" `expr \( $(CONFIG_SYS_NAND_BLOCKS) - 4 \) \* $(CONFIG_SYS_NAND_BLOCK_SIZE)`) +endif diff --git a/board/karo/tx6/flash.c b/board/karo/tx6/flash.c new file mode 100644 index 0000000000..540b360e46 --- /dev/null +++ b/board/karo/tx6/flash.c @@ -0,0 +1,661 @@ +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include + +#if CONFIG_SYS_NAND_U_BOOT_OFFS < 0x20000 +#error CONFIG_SYS_NAND_U_BOOT_OFFS must be >= 128kIB +#endif + +struct mx6_nand_timing { + u8 data_setup; + u8 data_hold; + u8 address_setup; + u8 dsample_time; + u8 nand_timing_state; + u8 tREA; + u8 tRLOH; + u8 tRHOH; +}; + +struct mx6_fcb { + u32 checksum; + u32 fingerprint; + u32 version; + struct mx6_nand_timing timing; + u32 page_data_size; + u32 total_page_size; + u32 sectors_per_block; + u32 number_of_nands; /* not used by ROM code */ + u32 total_internal_die; /* not used by ROM code */ + u32 cell_type; /* not used by ROM code */ + u32 ecc_blockn_type; + u32 ecc_block0_size; + u32 ecc_blockn_size; + u32 ecc_block0_type; + u32 metadata_size; + u32 ecc_blocks_per_page; + u32 rsrvd1[6]; /* not used by ROM code */ + u32 bch_mode; /* erase_threshold */ + u32 rsrvd2[2]; + u32 fw1_start_page; + u32 fw2_start_page; + u32 fw1_sectors; + u32 fw2_sectors; + u32 dbbt_search_area; + u32 bb_mark_byte; + u32 bb_mark_startbit; + u32 bb_mark_phys_offset; + u32 bch_type; + u32 rsrvd3[8]; /* Toggle NAND timing parameters */ + u32 disbbm; + u32 bb_mark_spare_offset; + u32 rsrvd4[9]; /* ONFI NAND parameters */ + u32 disbb_search; +}; + +struct mx6_dbbt_header { + u32 checksum; + u32 fingerprint; + u32 version; + u32 number_bb; + u32 number_pages; + u8 spare[492]; +}; + +struct mx6_dbbt { + u32 nand_number; + u32 number_bb; + u32 bb_num[2040 / 4]; +}; + +#define BF_VAL(v, bf) (((v) & bf##_MASK) >> bf##_OFFSET) + +static nand_info_t *mtd = &nand_info[0]; + +extern void *_start; + +#define BIT(v,n) (((v) >> (n)) & 0x1) + +static inline void memdump(const void *addr, size_t len) +{ + const char *buf = addr; + int i; + + for (i = 0; i < len; i++) { + if (i % 16 == 0) { + if (i > 0) + printf("\n"); + printf("%p:", &buf[i]); + } + printf(" %02x", buf[i]); + } + printf("\n"); +} + +static u8 calculate_parity_13_8(u8 d) +{ + u8 p = 0; + + p |= (BIT(d, 6) ^ BIT(d, 5) ^ BIT(d, 3) ^ BIT(d, 2)) << 0; + p |= (BIT(d, 7) ^ BIT(d, 5) ^ BIT(d, 4) ^ BIT(d, 2) ^ BIT(d, 1)) << 1; + p |= (BIT(d, 7) ^ BIT(d, 6) ^ BIT(d, 5) ^ BIT(d, 1) ^ BIT(d, 0)) << 2; + p |= (BIT(d, 7) ^ BIT(d, 4) ^ BIT(d, 3) ^ BIT(d, 0)) << 3; + p |= (BIT(d, 6) ^ BIT(d, 4) ^ BIT(d, 3) ^ BIT(d, 2) ^ BIT(d, 1) ^ BIT(d, 0)) << 4; + return p; +} + +static void encode_hamming_13_8(void *_src, void *_ecc, size_t size) +{ + int i; + u8 *src = _src; + u8 *ecc = _ecc; + + for (i = 0; i < size; i++) + ecc[i] = calculate_parity_13_8(src[i]); +} + +static u32 calc_chksum(void *buf, size_t size) +{ + u32 chksum = 0; + u8 *bp = buf; + size_t i; + + for (i = 0; i < size; i++) { + chksum += bp[i]; + } + return ~chksum; +} + +/* + Physical organisation of data in NAND flash: + metadata + payload chunk 0 (may be empty) + ecc for metadata + payload chunk 0 + payload chunk 1 + ecc for payload chunk 1 +... + payload chunk n + ecc for payload chunk n + */ + +static int calc_bb_offset(nand_info_t *mtd, struct mx6_fcb *fcb) +{ + int bb_mark_offset; + int chunk_data_size = fcb->ecc_blockn_size * 8; + int chunk_ecc_size = (fcb->ecc_blockn_type << 1) * 13; + int chunk_total_size = chunk_data_size + chunk_ecc_size; + int bb_mark_chunk, bb_mark_chunk_offs; + + bb_mark_offset = (mtd->writesize - fcb->metadata_size) * 8; + if (fcb->ecc_block0_size == 0) + bb_mark_offset -= (fcb->ecc_block0_type << 1) * 13; + + bb_mark_chunk = bb_mark_offset / chunk_total_size; + bb_mark_chunk_offs = bb_mark_offset - (bb_mark_chunk * chunk_total_size); + if (bb_mark_chunk_offs > chunk_data_size) { + printf("Unsupported ECC layout; BB mark resides in ECC data: %u\n", + bb_mark_chunk_offs); + return -EINVAL; + } + bb_mark_offset -= bb_mark_chunk * chunk_ecc_size; + return bb_mark_offset; +} + +#define pr_fcb_val(p, n) debug("%s=%08x(%d)\n", #n, (p)->n, (p)->n) + +static struct mx6_fcb *create_fcb(void *buf, int fw1_start_block, + int fw2_start_block, size_t fw_size) +{ + struct gpmi_regs *gpmi_base = (void *)GPMI_BASE_ADDRESS; + struct bch_regs *bch_base = (void *)BCH_BASE_ADDRESS; + u32 fl0, fl1; + u32 t0; + int metadata_size; + int bb_mark_bit_offs; + struct mx6_fcb *fcb; + int fcb_offs; + + if (gpmi_base == NULL || bch_base == NULL) { + return ERR_PTR(-ENOMEM); + } + + fl0 = readl(&bch_base->hw_bch_flash0layout0); + fl1 = readl(&bch_base->hw_bch_flash0layout1); + t0 = readl(&gpmi_base->hw_gpmi_timing0); + + metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE); + + fcb = buf + ALIGN(metadata_size, 4); + fcb_offs = (void *)fcb - buf; + + memset(buf, 0xff, fcb_offs); + memset(fcb, 0x00, sizeof(*fcb)); + memset(fcb + 1, 0xff, mtd->erasesize - fcb_offs - sizeof(*fcb)); + + strncpy((char *)&fcb->fingerprint, "FCB ", 4); + fcb->version = cpu_to_be32(1); + + fcb->disbb_search = 1; + fcb->disbbm = 1; + + /* ROM code assumes GPMI clock of 25 MHz */ + fcb->timing.data_setup = BF_VAL(t0, GPMI_TIMING0_DATA_SETUP) * 40; + fcb->timing.data_hold = BF_VAL(t0, GPMI_TIMING0_DATA_HOLD) * 40; + fcb->timing.address_setup = BF_VAL(t0, GPMI_TIMING0_ADDRESS_SETUP) * 40; + + fcb->page_data_size = mtd->writesize; + fcb->total_page_size = mtd->writesize + mtd->oobsize; + fcb->sectors_per_block = mtd->erasesize / mtd->writesize; + + fcb->ecc_block0_type = BF_VAL(fl0, BCH_FLASHLAYOUT0_ECC0); + fcb->ecc_block0_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_DATA0_SIZE) * 4; + fcb->ecc_blockn_type = BF_VAL(fl1, BCH_FLASHLAYOUT1_ECCN); + fcb->ecc_blockn_size = BF_VAL(fl1, BCH_FLASHLAYOUT1_DATAN_SIZE) * 4; + + pr_fcb_val(fcb, ecc_block0_type); + pr_fcb_val(fcb, ecc_blockn_type); + pr_fcb_val(fcb, ecc_block0_size); + pr_fcb_val(fcb, ecc_blockn_size); + + fcb->metadata_size = BF_VAL(fl0, BCH_FLASHLAYOUT0_META_SIZE); + fcb->ecc_blocks_per_page = BF_VAL(fl0, BCH_FLASHLAYOUT0_NBLOCKS); + fcb->bch_mode = readl(&bch_base->hw_bch_mode); + fcb->bch_type = 0; /* BCH20 */ + + fcb->fw1_start_page = fw1_start_block * mtd->erasesize / mtd->writesize; + fcb->fw1_sectors = DIV_ROUND_UP(fw_size, mtd->writesize); + + if (fw2_start_block != 0 && fw2_start_block < mtd->size / mtd->erasesize) { + fcb->fw2_start_page = fw2_start_block * mtd->erasesize / mtd->writesize; + fcb->fw2_sectors = fcb->fw1_sectors; + } + + fcb->dbbt_search_area = 1; + + bb_mark_bit_offs = calc_bb_offset(mtd, fcb); + if (bb_mark_bit_offs < 0) + return ERR_PTR(bb_mark_bit_offs); + fcb->bb_mark_byte = bb_mark_bit_offs / 8; + fcb->bb_mark_startbit = bb_mark_bit_offs % 8; + fcb->bb_mark_phys_offset = mtd->writesize; + + pr_fcb_val(fcb, bb_mark_byte); + pr_fcb_val(fcb, bb_mark_startbit); + pr_fcb_val(fcb, bb_mark_phys_offset); + + fcb->checksum = calc_chksum(&fcb->fingerprint, 512 - 4); + return fcb; +} + +static int find_fcb(void *ref, int page) +{ + int ret = 0; + struct nand_chip *chip = mtd->priv; + void *buf = malloc(mtd->erasesize); + + if (buf == NULL) { + return -ENOMEM; + } + chip->select_chip(mtd, 0); + chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page); + ret = chip->ecc.read_page_raw(mtd, chip, buf, 1, page); + if (ret) { + printf("Failed to read FCB from page %u: %d\n", page, ret); + return ret; + } + chip->select_chip(mtd, -1); + if (memcmp(buf, ref, mtd->writesize) == 0) { + debug("Found FCB in page %u (%08x)\n", + page, page * mtd->writesize); + ret = 1; + } + free(buf); + return ret; +} + +static int write_fcb(void *buf, int block) +{ + int ret; + struct nand_chip *chip = mtd->priv; + int page = block * mtd->erasesize / mtd->writesize; + + ret = find_fcb(buf, page); + if (ret > 0) { + printf("FCB at block %d is up to date\n", block); + return 0; + } + + ret = nand_erase(mtd, block * mtd->erasesize, mtd->erasesize); + if (ret) { + printf("Failed to erase FCB block %u\n", block); + return ret; + } + + printf("Writing FCB to block %d @ %08x\n", block, + block * mtd->erasesize); + chip->select_chip(mtd, 0); + ret = chip->write_page(mtd, chip, buf, 1, page, 0, 1); + if (ret) { + printf("Failed to write FCB to block %u: %d\n", block, ret); + } + chip->select_chip(mtd, -1); + return ret; +} + +struct mx6_ivt { + u32 magic; + u32 entry; + u32 rsrvd1; + void *dcd; + void *boot_data; + void *self; + void *csf; + u32 rsrvd2; +}; + +struct mx6_boot_data { + u32 start; + u32 length; + u32 plugin; +}; + +static size_t count_good_blocks(int start, int end) +{ + size_t max_len = (end - start + 1); + int block; + + for (block = start; block <= end; block++) { + if (nand_block_isbad(mtd, block * mtd->erasesize)) + max_len--; + } + return max_len; +} + +static int find_ivt(void *buf) +{ + struct mx6_ivt *ivt_hdr = buf + 0x400; + + if ((ivt_hdr->magic & 0xff0000ff) != 0x400000d1) + return 0; + + return 1; +} + +static inline void *reloc(void *dst, void *base, void *ptr) +{ + return dst + (ptr - base); +} + +static int patch_ivt(void *buf, size_t fsize) +{ + struct mx6_ivt *ivt_hdr = buf + 0x400; + struct mx6_boot_data *boot_data; + + if (!find_ivt(buf)) { + printf("No IVT found in image at %p\n", buf); + return -EINVAL; + } + boot_data = reloc(ivt_hdr, ivt_hdr->self, ivt_hdr->boot_data); + boot_data->length = fsize; + + return 0; +} + +#define chk_overlap(a,b) \ + ((a##_start_block <= b##_end_block && \ + a##_end_block >= b##_start_block) || \ + (b##_start_block <= a##_end_block && \ + b##_end_block >= a##_start_block)) + +#define fail_if_overlap(a,b,m1,m2) do { \ + if (chk_overlap(a, b)) { \ + printf("%s blocks %lu..%lu overlap %s in blocks %lu..%lu!\n", \ + m1, a##_start_block, a##_end_block, \ + m2, b##_start_block, b##_end_block); \ + return -EINVAL; \ + } \ +} while (0) + +#ifdef CONFIG_ENV_IS_IN_NAND +#ifndef CONFIG_ENV_OFFSET_REDUND +#define TOTAL_ENV_SIZE CONFIG_ENV_RANGE +#else +#define TOTAL_ENV_SIZE (CONFIG_ENV_RANGE * 2) +#endif +#endif + +#define pr_fcb_offset(n) printf("%s: %04x (%d)\n", #n, \ + offsetof(struct mx6_fcb, n), offsetof(struct mx6_fcb, n)) + +int do_update(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + int ret; + const unsigned long fcb_start_block = 0, fcb_end_block = 0; + int erase_size = mtd->erasesize; + int page_size = mtd->writesize; + void *buf; + char *load_addr; + char *file_size; + size_t size = 0; + void *addr = NULL; + struct mx6_fcb *fcb; + unsigned long mtd_num_blocks = mtd->size / mtd->erasesize; +#ifdef CONFIG_ENV_IS_IN_NAND + unsigned long env_start_block = CONFIG_ENV_OFFSET / mtd->erasesize; + unsigned long env_end_block = env_start_block + + DIV_ROUND_UP(TOTAL_ENV_SIZE, mtd->erasesize) - 1; +#endif + int optind; + int fw1_set = 0; + int fw2_set = 0; + unsigned long fw1_start_block = 0, fw1_end_block; + unsigned long fw2_start_block = 0, fw2_end_block; + unsigned long fw_num_blocks; + unsigned long extra_blocks = 2; + nand_erase_options_t erase_opts = { 0, }; + size_t max_len1, max_len2; + size_t actual; + + for (optind = 1; optind < argc; optind++) { + if (strcmp(argv[optind], "-f") == 0) { + if (optind >= argc - 1) { + printf("Option %s requires an argument\n", + argv[optind]); + return -EINVAL; + } + optind++; + fw1_start_block = simple_strtoul(argv[optind], NULL, 0); + if (fw1_start_block >= mtd_num_blocks) { + printf("Block number %lu is out of range: 0..%lu\n", + fw1_start_block, mtd_num_blocks - 1); + return -EINVAL; + } + fw1_set = 1; + } else if (strcmp(argv[optind], "-r") == 0) { + if (optind < argc - 1 && argv[optind + 1][0] != '-') { + optind++; + fw2_start_block = simple_strtoul(argv[optind], + NULL, 0); + if (fw2_start_block >= mtd_num_blocks) { + printf("Block number %lu is out of range: 0..%lu\n", + fw2_start_block, + mtd_num_blocks - 1); + return -EINVAL; + } + } + fw2_set = 1; + } else if (strcmp(argv[optind], "-e") == 0) { + if (optind >= argc - 1) { + printf("Option %s requires an argument\n", + argv[optind]); + return -EINVAL; + } + optind++; + extra_blocks = simple_strtoul(argv[optind], NULL, 0); + if (extra_blocks >= mtd_num_blocks) { + printf("Extra block count %lu is out of range: 0..%lu\n", + extra_blocks, + mtd_num_blocks - 1); + return -EINVAL; + } + } else if (argv[optind][0] == '-') { + printf("Unrecognized option %s\n", argv[optind]); + return -EINVAL; + } else { + break; + } + } + + load_addr = getenv("fileaddr"); + file_size = getenv("filesize"); + + if (argc - optind < 1 && load_addr == NULL) { + printf("Load address not specified\n"); + return -EINVAL; + } + if (argc - optind < 2 && file_size == NULL) { + printf("WARNING: Image size not specified; overwriting whole uboot partition\n"); + } + if (argc > optind) { + load_addr = NULL; + addr = (void *)simple_strtoul(argv[optind], NULL, 16); + optind++; + } + if (argc > optind) { + file_size = NULL; + size = simple_strtoul(argv[optind], NULL, 16); + optind++; + } + if (load_addr != NULL) { + addr = (void *)simple_strtoul(load_addr, NULL, 16); + printf("Using default load address %p\n", addr); + } + if (file_size != NULL) { + size = simple_strtoul(file_size, NULL, 16); + printf("Using default file size %08x\n", size); + } + if (size > 0) + fw_num_blocks = DIV_ROUND_UP(size, mtd->erasesize); + else + fw_num_blocks = CONFIG_U_BOOT_IMG_SIZE / mtd->erasesize - extra_blocks; + + if (!fw1_set) { + fw1_start_block = CONFIG_SYS_NAND_U_BOOT_OFFS / mtd->erasesize; + fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1; + } else { + fw1_end_block = fw1_start_block + fw_num_blocks + extra_blocks - 1; + } + + if (fw2_set && fw2_start_block == 0) { + fw2_start_block = fw1_end_block + 1; + fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1; + } else { + fw2_end_block = fw2_start_block + fw_num_blocks + extra_blocks - 1; + } + +#ifdef CONFIG_ENV_IS_IN_NAND + fail_if_overlap(fcb, env, "FCB", "Environment"); + fail_if_overlap(fw1, env, "FW1", "Environment"); +#endif + fail_if_overlap(fcb, fw1, "FCB", "FW1"); + if (fw2_set) { + fail_if_overlap(fcb, fw2, "FCB", "FW2"); +#ifdef CONFIG_ENV_IS_IN_NAND + fail_if_overlap(fw2, env, "FW2", "Environment"); +#endif + fail_if_overlap(fw1, fw2, "FW1", "FW2"); + } + + buf = malloc(erase_size); + if (buf == NULL) { + printf("Failed to allocate buffer\n"); + return -ENOMEM; + } + + /* search for bad blocks in FW1 block range */ + max_len1 = count_good_blocks(fw1_start_block, fw1_end_block); + printf("%u good blocks in %lu..%lu\n", + max_len1, fw1_start_block, fw1_end_block); + if (fw_num_blocks > max_len1) { + printf("Too many bad blocks in FW1 block range: %lu..%lu; max blocks: %u\n", + fw1_end_block + 1 - fw_num_blocks - extra_blocks, + fw1_end_block, max_len1); + return -EINVAL; + } + + /* search for bad blocks in FW2 block range */ + max_len2 = count_good_blocks(fw2_start_block, fw2_end_block); + if (fw2_start_block > 0 && fw_num_blocks > max_len2) { + printf("Too many bad blocks in FW2 block range: %lu..%lu\n", + fw2_end_block + 1 - fw_num_blocks - extra_blocks, + fw2_end_block); + return -EINVAL; + } + + fcb = create_fcb(buf, fw1_start_block, fw2_start_block, + ALIGN(fw_num_blocks * mtd->erasesize, mtd->writesize)); + if (IS_ERR(fcb)) { + printf("Failed to initialize FCB: %ld\n", PTR_ERR(fcb)); + return PTR_ERR(fcb); + } + encode_hamming_13_8(fcb, (void *)fcb + 512, 512); + + ret = write_fcb(buf, fcb_start_block); + if (ret) { + printf("Failed to write FCB to block %lu\n", fcb_start_block); + return ret; + } + + ret = patch_ivt(addr, size ?: fw_num_blocks * mtd->erasesize); + if (ret) { + return ret; + } + + printf("Programming U-Boot image from %p to block %lu\n", + addr, fw1_start_block); + if (size & (page_size - 1)) { + memset(addr + size, 0xff, size & (page_size - 1)); + size = ALIGN(size, page_size); + } + + erase_opts.offset = fcb->fw1_start_page * page_size; + erase_opts.length = (fw1_end_block - fw1_start_block + 1) * + mtd->erasesize; + erase_opts.quiet = 1; + + printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset, + erase_opts.offset + erase_opts.length - 1); + + ret = nand_erase_opts(mtd, &erase_opts); + if (ret) { + printf("Failed to erase flash: %d\n", ret); + return ret; + } + if (size == 0) + max_len1 *= mtd->erasesize; + else + max_len1 = size; + + printf("Programming flash @ %08x..%08x from %p\n", + fcb->fw1_start_page * page_size, + fcb->fw1_start_page * page_size + max_len1 - 1, addr); + ret = nand_write_skip_bad(mtd, fcb->fw1_start_page * page_size, + &max_len1, &actual, erase_opts.length, addr, + WITH_DROP_FFS); + if (ret || actual < size) { + printf("Failed to program flash: %d\n", ret); + return ret ?: -EIO; + } + if (fw2_start_block == 0) { + return ret; + } + + printf("Programming redundant U-Boot image to block %lu\n", + fw2_start_block); + erase_opts.offset = fcb->fw2_start_page * page_size; + erase_opts.length = (fw2_end_block - fw2_start_block + 1) * + mtd->erasesize; + printf("Erasing flash @ %08llx..%08llx\n", erase_opts.offset, + erase_opts.offset + erase_opts.length - 1); + + ret = nand_erase_opts(mtd, &erase_opts); + if (ret) { + printf("Failed to erase flash: %d\n", ret); + return ret; + } + if (size == 0) + max_len2 *= mtd->erasesize; + else + max_len2 = size; + printf("Programming flash @ %08x..%08x from %p\n", + fcb->fw2_start_page * page_size, + fcb->fw2_start_page * page_size + max_len2 - 1, addr); + ret = nand_write_skip_bad(mtd, fcb->fw2_start_page * page_size, + &max_len2, &actual, erase_opts.length, addr, + WITH_DROP_FFS); + if (ret || actual < size) { + printf("Failed to program flash: %d\n", ret); + return ret ?: -EIO; + } + return ret; +} + +U_BOOT_CMD(romupdate, 11, 0, do_update, + "Creates an FCB data structure and writes an U-Boot image to flash\n", + "[-f #] [-r [#]] [-e #] [
] []\n" + "\t-f #\twrite bootloader image at block #\n" + "\t-r\twrite redundant bootloader image at next free block after first image\n" + "\t-r #\twrite redundant bootloader image at block #\n" + "\t-e #\tspecify number of redundant blocks per boot loader image (default 2)\n" + "\t
\tRAM address of bootloader image (default: ${fileaddr}\n" + "\t\tlength of bootloader image in RAM (default: ${filesize}" + ); diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S new file mode 100644 index 0000000000..95f0b6d9a9 --- /dev/null +++ b/board/karo/tx6/lowlevel_init.S @@ -0,0 +1,955 @@ +#include +#include +#include +#include + +//#define DO_WL_CALIB + +#ifndef CCM_CCR +#error asm-offsets not included +#endif + +#define DEBUG_LED_BIT 20 +#define LED_GPIO_BASE GPIO2_BASE_ADDR +#define LED_MUX_OFFSET 0x0ec +#define LED_MUX_MODE 0x15 + +#define SDRAM_CLK CONFIG_SYS_SDRAM_CLK + +#ifdef PHYS_SDRAM_2_SIZE +#define SDRAM_SIZE (PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE) +#else +#define SDRAM_SIZE PHYS_SDRAM_1_SIZE +#endif + +#define CPU_2_BE_32(l) \ + ((((l) << 24) & 0xFF000000) | \ + (((l) << 8) & 0x00FF0000) | \ + (((l) >> 8) & 0x0000FF00) | \ + (((l) >> 24) & 0x000000FF)) + +#define CHECK_DCD_ADDR(a) ( \ + ((a) >= 0x020E0000 && (a) <= 0x020E3FFF) /* IOMUXC */ || \ + ((a) >= 0x020C4000 && (a) <= 0x020C7FFF) /* CCM */ || \ + ((a) >= 0x020C8000 && (a) <= 0x020C8FFF) /* ANALOG */ || \ + ((a) >= 0x021B0000 && (a) <= 0x021B7FFF) /* MMDC */ || \ + ((a) >= 0x00907000 && (a) <= 0x00937FF0) /* OCRAM */ || \ + ((a) >= 0x08000000 && (a) <= 0x0FFEFFFF) /* EIM (CS0) */ || \ + ((a) >= 0x10000000 && (a) <= 0xFFFFFFFF) /* SDRAM */) + + .macro mxc_dcd_item addr, val + .ifne CHECK_DCD_ADDR(\addr) + .word CPU_2_BE_32(\addr), CPU_2_BE_32(\val) + .else + .error "Address \addr not accessible from DCD" + .endif + .endm + +#define MXC_DCD_ITEM(addr, val) mxc_dcd_item addr, val +#if PHYS_SDRAM_1_WIDTH == 64 +#define MXC_DCD_ITEM_64(addr, val) mxc_dcd_item addr, val +#define MXC_DCD_CMD_CHK_64(type, flags, addr, mask) MXC_DCD_CMD_CHK(type, flags, addr, mask) +#else +#define MXC_DCD_ITEM_64(addr, val) +#define MXC_DCD_CMD_CHK_64(type, flags, addr, mask) +#endif + +#define MXC_DCD_CMD_SZ_BYTE 1 +#define MXC_DCD_CMD_SZ_SHORT 2 +#define MXC_DCD_CMD_SZ_WORD 4 +#define MXC_DCD_CMD_FLAG_WRITE 0x0 +#define MXC_DCD_CMD_FLAG_CLR 0x1 +#define MXC_DCD_CMD_FLAG_SET 0x3 +#define MXC_DCD_CMD_FLAG_CHK_ANY (1 << 0) +#define MXC_DCD_CMD_FLAG_CHK_SET (1 << 1) +#define MXC_DCD_CMD_FLAG_CHK_CLR (0 << 1) + +#define MXC_DCD_CMD_WRT(type, flags, next) \ + .word CPU_2_BE_32((0xcc << 24) | (((next) - .) << 8) | ((flags) << 3) | (type)) + +#define MXC_DCD_CMD_CHK(type, flags, addr, mask) \ + .word CPU_2_BE_32((0xcf << 24) | (12 << 8) | ((flags) << 3) | (type)),\ + CPU_2_BE_32(addr), CPU_2_BE_32(mask) + +#define MXC_DCD_CMD_CHK_CNT(type, flags, addr, mask, count) \ + .word CPU_2_BE_32((0xcf << 24) | (16 << 8) | ((flags) << 3) | (type)),\ + CPU_2_BE_32(addr), CPU_2_BE_32(mask), CPU_2_BE_32(count) + +#define MXC_DCD_CMD_NOP() \ + .word CPU_2_BE_32((0xc0 << 24) | (4 << 8)) + +#define CK_TO_NS(ck) (((ck) * 1000 + SDRAM_CLK / 2) / SDRAM_CLK) +#define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000) +#define NS_TO_CK10(ns) DIV_ROUND_UP(NS_TO_CK(ns), 10) + + .macro CK_VAL, name, clks, offs, max + .iflt \clks - \offs + .set \name, 0 + .else + .ifle \clks - \offs - \max + .set \name, \clks - \offs + .else + .error "Value \clks out of range for parameter \name" + .endif + .endif + .endm + + .macro NS_VAL, name, ns, offs, max + .iflt \ns - \offs + .set \name, 0 + .else + CK_VAL \name, NS_TO_CK(\ns), \offs, \max + .endif + .endm + + .macro CK_MAX, name, ck1, ck2, offs, max + .ifgt \ck1 - \ck2 + CK_VAL \name, \ck1, \offs, \max + .else + CK_VAL \name, \ck2, \offs, \max + .endif + .endm + +#define MDMISC_DDR_TYPE_DDR3 0 +#define MDMISC_DDR_TYPE_LPDDR2 1 +#define MDMISC_DDR_TYPE_DDR2 2 + +#define DIV_ROUND_UP(m,d) (((m) + (d) - 1) / (d)) + +#define MDOR_CLK_PERIOD_ns 15258 /* base clock for MDOR values */ + +/* DDR3 SDRAM */ +#if SDRAM_SIZE > PHYS_SDRAM_1_SIZE +#define BANK_ADDR_BITS 2 +#else +#define BANK_ADDR_BITS 1 +#endif +#define SDRAM_BURST_LENGTH 8 +#define RALAT 5 +#define WALAT 0 +#define BI_ON 0 +#define ADDR_MIRROR 0 +#define DDR_TYPE MDMISC_DDR_TYPE_DDR3 + +/* 512/1024MiB SDRAM: NT5CB128M16FP-DII */ +#if SDRAM_CLK > 666 && SDRAM_CLK <= 800 +#define CL_VAL 11 +#define CWL_VAL 8 +#elif SDRAM_CLK > 533 && SDRAM_CLK <= 666 +#define CL_VAL 9 // or 10 +#define CWL_VAL 7 +#elif SDRAM_CLK > 400 && SDRAM_CLK <= 533 +#define CL_VAL 7 // or 8 +#define CWL_VAL 6 +#elif SDRAM_CLK > 333 && SDRAM_CLK <= 400 +#define CL_VAL 6 +#define CWL_VAL 5 +#elif SDRAM_CLK >= 303 && SDRAM_CLK <= 333 +#define CL_VAL 5 +#define CWL_VAL 5 +#else +#error SDRAM clock out of range: 303 .. 800 +#endif + +/* MDCFG0 0x0c */ +NS_VAL tRFC, 160, 1, 255 /* clks - 1 (0..255) */ +CK_MAX tXS, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) tRFC + 10 */ +CK_MAX tXP, NS_TO_CK10(75), 3, 1, 7 /* clks - 1 (0..7) */ /* max(3tCK, 7.5ns) */ +CK_MAX tXPDLL, NS_TO_CK(24), 2, 1, 15 /* clks - 1 (0..15) */ +NS_VAL tFAW, 50, 1, 31 /* clks - 1 (0..31) */ +CK_VAL tCL, CL_VAL, 3, 8 /* clks - 3 (0..8) CAS Latency */ + +/* MDCFG1 0x10 */ +CK_VAL tRCD, NS_TO_CK10(125), 1, 7 /* clks - 1 (0..7) */ /* 12.5 */ +CK_VAL tRP, NS_TO_CK10(125), 1, 7 /* clks - 1 (0..7) */ /* 12.5 */ +NS_VAL tRC, 50, 1, 31 /* clks - 1 (0..31) */ +CK_VAL tRAS, NS_TO_CK10(375), 1, 31 /* clks - 1 (0..31) */ /* 37.5 */ +CK_VAL tRPA, 1, 0, 1 /* clks (0..1) */ +NS_VAL tWR, 15, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tMRD, 4, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tCWL, CWL_VAL, 2, 6 /* clks - 2 (0..6) */ + +/* MDCFG2 0x14 */ +CK_VAL tDLLK, 512, 1, 511 /* clks - 1 (0..511) */ +CK_MAX tRTP, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ +CK_MAX tWTR, NS_TO_CK10(75), 4, 1, 7 /* clks - 1 (0..7) */ /* max(4tCK, 7.5ns) */ +CK_MAX tRRD, NS_TO_CK(10), 4, 1, 7 /* clks - 1 (0..7) */ + +/* MDOR 0x30 */ +CK_MAX tXPR, NS_TO_CK(CK_TO_NS(tRFC + 1) + 10), 5, 1, 255 /* clks - 1 (0..255) max(tRFC + 10, 5CK) */ +#define tSDE_RST (DIV_ROUND_UP(200000, MDOR_CLK_PERIOD_ns) + 2) +#define tRST_CKE (DIV_ROUND_UP(500000, MDOR_CLK_PERIOD_ns) + 2) + +/* MDOTC 0x08 */ +CK_VAL tAOFPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */ +CK_VAL tAONPD, NS_TO_CK10(85), 1, 7 /* clks - 1 (0..7) */ /* 8.5ns */ +CK_VAL tANPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tAXPD, tCWL + 1, 1, 15 /* clks - 1 (0..15) */ +CK_VAL tODTLon tCWL, 0, 7 /* clks - 1 (0..7) */ /* CWL+AL-2 */ +CK_VAL tODTLoff tCWL, 0, 31 /* clks - 1 (0..31) */ /* CWL+AL-2 */ + +/* MDPDC 0x04 */ +CK_MAX tCKE, NS_TO_CK(5), 3, 1, 7 +CK_MAX tCKSRX, NS_TO_CK(10), 5, 0, 7 +CK_MAX tCKSRE, NS_TO_CK(10), 5, 0, 7 + +#define PRCT 0 +#define PWDT 5 +#define SLOW_PD 0 +#define BOTH_CS_PD 1 + +#define MDPDC_VAL_0 ( \ + (PRCT << 28) | \ + (PRCT << 24) | \ + (tCKE << 16) | \ + (SLOW_PD << 7) | \ + (BOTH_CS_PD << 6) | \ + (tCKSRX << 3) | \ + (tCKSRE << 0) \ + ) + +#define MDPDC_VAL_1 (MDPDC_VAL_0 | \ + (PWDT << 12) | \ + (PWDT << 8) \ + ) + +#define ROW_ADDR_BITS 14 +#define COL_ADDR_BITS 10 + +#define Rtt_Nom 1 /* ODT: 0: off 1: RZQ/4 2: RZQ/2 3: RZQ/6 4: RZQ/12 5: RZQ/8 */ +#define Rtt_WR 0 /* Dynamic ODT: 0: off 1: RZQ/4 2: RZQ/2 */ +#define DLL_DISABLE 0 + + .iflt tWR - 7 + .set mr0_val, (((1 - DLL_DISABLE) << 8) /* DLL Reset */ | \ + (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\ + ((tWR + 1 - 4) << 9) | \ + ((((tCL + 3) - 4) & 0x7) << 4) | \ + ((((tCL + 3) - 4) & 0x8) >> 1)) + .else + .set mr0_val, ((1 << 8) /* DLL Reset */ | \ + (SLOW_PD << 12) /* PD exit: 0: fast 1: slow */ |\ + (((tWR + 1) / 2) << 9) | \ + ((((tCL + 3) - 4) & 0x7) << 4) | \ + ((((tCL + 3) - 4) & 0x8) >> 1)) + .endif + +#define mr1_val ( \ + ((Rtt_Nom & 1) << 2) | \ + (((Rtt_Nom >> 1) & 1) << 6) | \ + (((Rtt_Nom >> 2) & 1) << 9) | \ + (DLL_DISABLE << 0) | \ + 0) +#define mr2_val ( \ + (Rtt_WR << 9) /* dynamic ODT */ | \ + (0 << 7) /* SRT: Ext. temp. (mutually exclusive with ASR!) */ | \ + (1 << 6) | /* ASR: Automatic Self Refresh */ \ + (((tCWL + 2) - 5) << 3) | \ + 0) +#define mr3_val 0 + +#define MDSCR_MRS_VAL(cs, mr, val) (((val) << 16) | \ + (1 << 15) /* CON_REQ */ | \ + (3 << 4) /* MRS command */ | \ + ((cs) << 3) | \ + ((mr) << 0) | \ + 0) + +#define MDCFG0_VAL ( \ + (tRFC << 24) | \ + (tXS << 16) | \ + (tXP << 13) | \ + (tXPDLL << 9) | \ + (tFAW << 4) | \ + (tCL << 0)) \ + +#define MDCFG1_VAL ( \ + (tRCD << 29) | \ + (tRP << 26) | \ + (tRC << 21) | \ + (tRAS << 16) | \ + (tRPA << 15) | \ + (tWR << 9) | \ + (tMRD << 5) | \ + (tCWL << 0)) \ + +#define MDCFG2_VAL ( \ + (tDLLK << 16) | \ + (tRTP << 6) | \ + (tWTR << 3) | \ + (tRRD << 0)) + +#define BURST_LEN (SDRAM_BURST_LENGTH / 8) /* 0: 4 byte 1: 8 byte */ + +#define MDCTL_VAL (((ROW_ADDR_BITS - 11) << 24) | \ + ((COL_ADDR_BITS - 9) << 20) | \ + (BURST_LEN << 19) | \ + ((PHYS_SDRAM_1_WIDTH / 32) << 16) | \ + ((-1) << (32 - BANK_ADDR_BITS))) + +#define MDMISC_VAL ((ADDR_MIRROR << 19) | \ + (WALAT << 16) | \ + (BI_ON << 12) | \ + (0x3 << 9) | \ + (RALAT << 6) | \ + (DDR_TYPE << 3)) + +#define MDOR_VAL ((tXPR << 16) | (tSDE_RST << 8) | (tRST_CKE << 0)) + +#define MDOTC_VAL ((tAOFPD << 27) | \ + (tAONPD << 24) | \ + (tANPD << 20) | \ + (tAXPD << 16) | \ + (tODTLon << 12) | \ + (tODTLoff << 4)) + +ivt_header: + .word CPU_2_BE_32((0xd1 << 24) | (32 << 8) | 0x40) +app_start_addr: + .long _start + .long 0x0 +dcd_ptr: + .long dcd_hdr +boot_data_ptr: + .word boot_data +self_ptr: + .word ivt_header +app_code_csf: + .word 0x0 + .word 0x0 +boot_data: + .long _start +image_len: + .long CONFIG_U_BOOT_IMG_SIZE +plugin: + .word 0 +ivt_end: +#define DCD_VERSION 0x40 + +#define CLKCTL_CCGR0 0x68 +#define CLKCTL_CCGR1 0x6c +#define CLKCTL_CCGR2 0x70 +#define CLKCTL_CCGR3 0x74 +#define CLKCTL_CCGR4 0x78 +#define CLKCTL_CCGR5 0x7c +#define CLKCTL_CCGR6 0x80 +#define CLKCTL_CCGR7 0x84 +#define CLKCTL_CMEOR 0x88 + +#define DDR_SEL_VAL 3 +#define DSE_VAL 6 +#define ODT_VAL 2 + +#define DDR_SEL_SHIFT 18 +#define DDR_MODE_SHIFT 17 +#define ODT_SHIFT 8 +#define DSE_SHIFT 3 +#define HYS_SHIFT 16 +#define PKE_SHIFT 12 +#define PUE_SHIFT 13 +#define PUS_SHIFT 14 + +#define DDR_SEL_MASK (DDR_SEL_VAL << DDR_SEL_SHIFT) +#define DDR_MODE_MASK (1 << DDR_MODE_SHIFT) +#define DSE_MASK (DSE_VAL << DSE_SHIFT) +#define ODT_MASK (ODT_VAL << ODT_SHIFT) + +#define DQM_MASK (DDR_MODE_MASK | DSE_MASK) +#define SDQS_MASK DSE_MASK +#define SDODT_MASK (DSE_MASK | (1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) +#define SDCLK_MASK (DDR_MODE_MASK | DSE_MASK) +#define SDCKE_MASK ((1 << PKE_SHIFT) | (1 << PUE_SHIFT) | (0 << PUS_SHIFT)) +#define DDR_ADDR_MASK 0 +#define DDR_CTRL_MASK (DDR_MODE_MASK | DSE_MASK) + +#define MMDC1_MDCTL 0x021b0000 +#define MMDC1_MDPDC 0x021b0004 +#define MMDC1_MDOTC 0x021b0008 +#define MMDC1_MDCFG0 0x021b000c +#define MMDC1_MDCFG1 0x021b0010 +#define MMDC1_MDCFG2 0x021b0014 +#define MMDC1_MDMISC 0x021b0018 +#define MMDC1_MDSCR 0x021b001c +#define MMDC1_MDREF 0x021b0020 +#define MMDC1_MDRWD 0x021b002c +#define MMDC1_MDOR 0x021b0030 +#define MMDC1_MDASP 0x021b0040 +#define MMDC1_MAPSR 0x021b0404 +#define MMDC1_MPZQHWCTRL 0x021b0800 +#define MMDC1_MPWLGCR 0x021b0808 +#define MMDC1_MPWLDECTRL0 0x021b080c +#define MMDC1_MPWLDECTRL1 0x021b0810 +#define MMDC1_MPWLDLST 0x021b0814 +#define MMDC1_MPODTCTRL 0x021b0818 +#define MMDC1_MPRDDQBY0DL 0x021b081c +#define MMDC1_MPRDDQBY1DL 0x021b0820 +#define MMDC1_MPRDDQBY2DL 0x021b0824 +#define MMDC1_MPRDDQBY3DL 0x021b0828 +#define MMDC1_MPDGCTRL0 0x021b083c +#define MMDC1_MPDGCTRL1 0x021b0840 +#define MMDC1_MPDGDLST0 0x021b0844 +#define MMDC1_MPWRDLST 0x021b0854 +#define MMDC1_MPRDDLCTL 0x021b0848 +#define MMDC1_MPRDDLST 0x021b084c +#define MMDC1_MPWRDLCTL 0x021b0850 +#define MMDC1_MPWRDLST 0x021b0854 +#define MMDC1_MPRDDLHWCTL 0x021b0860 +#define MMDC1_MPWRDLHWCTL 0x021b0864 +#define MMDC1_MPPDCMPR2 0x021b0890 +#define MMDC1_MPSWDRDR0 0x021b0898 +#define MMDC1_MPSWDRDR1 0x021b089c +#define MMDC1_MPSWDRDR2 0x021b08a0 +#define MMDC1_MPSWDRDR3 0x021b08a4 +#define MMDC1_MPSWDRDR4 0x021b08a8 +#define MMDC1_MPSWDRDR5 0x021b08ac +#define MMDC1_MPSWDRDR6 0x021b08b0 +#define MMDC1_MPSWDRDR7 0x021b08b4 +#define MMDC1_MPMUR0 0x021b08b8 + +#if PHYS_SDRAM_1_WIDTH == 64 +#define MMDC2_MDPDC 0x021b4004 +#define MMDC2_MPWLGCR 0x021b4808 +#define MMDC2_MPWLDECTRL0 0x021b480c +#define MMDC2_MPWLDECTRL1 0x021b4810 +#define MMDC2_MPWLDLST 0x021b4814 +#define MMDC2_MPODTCTRL 0x021b4818 +#define MMDC2_MPRDDQBY0DL 0x021b481c +#define MMDC2_MPRDDQBY1DL 0x021b4820 +#define MMDC2_MPRDDQBY2DL 0x021b4824 +#define MMDC2_MPRDDQBY3DL 0x021b4828 +#define MMDC2_MPDGCTRL0 0x021b483c +#define MMDC2_MPDGCTRL1 0x021b4840 +#define MMDC2_MPDGDLST0 0x021b4844 +#define MMDC2_MPRDDLCTL 0x021b4848 +#define MMDC2_MPRDDLST 0x021b484c +#define MMDC2_MPWRDLCTL 0x021b4850 +#define MMDC2_MPWRDLST 0x021b4854 +#define MMDC2_MPRDDLHWCTL 0x021b4860 +#define MMDC2_MPWRDLHWCTL 0x021b4864 +#define MMDC2_MPRDDLHWST0 0x021b4868 +#define MMDC2_MPRDDLHWST1 0x021b486c +#define MMDC2_MPWRDLHWST0 0x021b4870 +#define MMDC2_MPWRDLHWST1 0x021b4874 +#define MMDC2_MPWLHWERR 0x021b4878 +#define MMDC2_MPDGHWST0 0x021b487c +#define MMDC2_MPDGHWST1 0x021b4880 +#define MMDC2_MPDGHWST2 0x021b4884 +#define MMDC2_MPDGHWST3 0x021b4888 +#define MMDC2_MPSWDAR0 0x021b4894 +#define MMDC2_MPSWDRDR0 0x021b4898 +#define MMDC2_MPSWDRDR1 0x021b489c +#define MMDC2_MPSWDRDR2 0x021b48a0 +#define MMDC2_MPSWDRDR3 0x021b48a4 +#define MMDC2_MPSWDRDR4 0x021b48a8 +#define MMDC2_MPSWDRDR5 0x021b48ac +#define MMDC2_MPSWDRDR6 0x021b48b0 +#define MMDC2_MPSWDRDR7 0x021b48b4 +#endif + +#ifdef CONFIG_MX6Q +#define IOMUXC_GPR1 0x020e0004 +#define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x020e024c +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x020e02a8 +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 0x020e02ac +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 0x020e02c0 +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 0x020e02c4 +#define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x020e02d4 +#define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x020e02d8 +#define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x020e02dc +#define IOMUXC_SW_MUX_CTL_PAD_NAND_READY 0x020e02e0 +#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B 0x020e02e4 +#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B 0x020e02ec +#define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD 0x020e02f4 +#define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK 0x020e02f8 +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 0x020e02fc +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 0x020e0300 +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 0x020e0304 +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 0x020e0308 +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 0x020e030c +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x020e0310 +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x020e0314 +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x020e0318 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P 0x020e050c +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 0x020e0510 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 0x020e0514 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P 0x020e0518 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P 0x020e051c +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x020e0520 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P 0x020e0524 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x020e0528 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 0x020e052c +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 0x020e0530 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 0x020e0534 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 0x020e0538 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 0x020e053c +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 0x020e0540 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 0x020e0544 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 0x020e0548 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 0x020e054c +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 0x020e0550 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 0x020e0554 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 0x020e0558 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 0x020e055c +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 0x020e0560 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 0x020e0564 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 0x020e0568 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS 0x020e056c +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS 0x020e0578 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET 0x020e057c +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 0x020e0580 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 0x020e0584 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P 0x020e0588 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 0x020e058c +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x020e0590 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P 0x020e0594 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x020e0598 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 0x020e059c +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 0x020e05a0 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P 0x020e05a8 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x020e05ac +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P 0x020e05b0 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x020e05b4 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P 0x020e05b8 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 0x020e05bc +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P 0x020e05c0 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 0x020e05c4 +#define IOMUXC_SW_PAD_CTL_GRP_B7DS 0x020e0748 +#define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x020e074c +#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x020e0750 +#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0 0x020e0754 +#define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x020e0758 +#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1 0x020e075c +#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2 0x020e0760 +#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3 0x020e0764 +#define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x020e0768 +#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4 0x020e076c +#define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x020e0770 +#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x020e0774 +#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5 0x020e0778 +#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6 0x020e077c +#define IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7 0x020e0780 +#define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x020e0784 +#define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x020e0788 +#define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x020e078c +#define IOMUXC_SW_PAD_CTL_GRP_B2DS 0x020e0794 +#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x020e0798 +#define IOMUXC_SW_PAD_CTL_GRP_B3DS 0x020e079c +#define IOMUXC_SW_PAD_CTL_GRP_B4DS 0x020e07a0 +#define IOMUXC_SW_PAD_CTL_GRP_B5DS 0x020e07a4 +#define IOMUXC_SW_PAD_CTL_GRP_B6DS 0x020e07a8 +#define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x020e091c +#define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0920 +#endif + +#ifdef CONFIG_MX6DL +#define IOMUXC_GPR1 0x020e0004 +#define IOMUXC_SW_MUX_CTL_PAD_GPIO17 0x020e0218 +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7 0x020e0330 +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6 0x020e032c +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0 0x020e0314 +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1 0x020e0318 +#define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE 0x020e0270 +#define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE 0x020e026c +#define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B 0x020e02a8 +#define IOMUXC_SW_MUX_CTL_PAD_NAND_READY 0x020e02a4 +#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B 0x020e0274 +#define IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B 0x020e027c +#define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD 0x020e033c +#define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK 0x020e0338 +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00 0x020e0284 +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01 0x020e0288 +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02 0x020e028c +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03 0x020e0290 +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04 0x020e0294 +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05 0x020e0298 +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06 0x020e029c +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07 0x020e02a0 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P 0x020e04d0 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5 0x020e0484 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4 0x020e0480 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P 0x020e04cc +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P 0x020e04c8 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3 0x020e047c +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P 0x020e04c4 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2 0x020e0478 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00 0x020e0424 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01 0x020e0428 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02 0x020e0444 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03 0x020e0448 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04 0x020e044c +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05 0x020e0450 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06 0x020e0454 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07 0x020e0458 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08 0x020e045c +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09 0x020e0460 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10 0x020e042c +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11 0x020e0430 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12 0x020e0434 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13 0x020e0438 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14 0x020e043c +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15 0x020e0440 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS 0x020e0464 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS 0x020e0490 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET 0x020e0494 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0 0x020e0498 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1 0x020e049c +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P 0x020e04ac +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 0x020e04a0 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0 0x020e04a4 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P 0x020e04b0 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1 0x020e04a8 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 0x020e04b4 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 0x020e04b8 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P 0x020e04bc +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 0x020e0470 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P 0x020e04c0 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 0x020e0474 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P 0x020e04d4 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6 0x020e0488 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P 0x020e04d8 +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7 0x020e048c +#define IOMUXC_SW_PAD_CTL_GRP_B7DS 0x020e0748 +#define IOMUXC_SW_PAD_CTL_GRP_ADDDS 0x020e074c +#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL 0x020e0750 +#define IOMUXC_SW_PAD_CTL_GRP_DDRPKE 0x020e0754 +#define IOMUXC_SW_PAD_CTL_GRP_DDRPK 0x020e0754 +#define IOMUXC_SW_PAD_CTL_GRP_DDRHYS 0x020e075c +#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE 0x020e0760 +#define IOMUXC_SW_PAD_CTL_GRP_B0DS 0x020e0784 +#define IOMUXC_SW_PAD_CTL_GRP_B1DS 0x020e0788 +#define IOMUXC_SW_PAD_CTL_GRP_CTLDS 0x020e078c +#define IOMUXC_SW_PAD_CTL_GRP_B2DS 0x020e0794 +#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE 0x020e0798 +#define IOMUXC_SW_PAD_CTL_GRP_B3DS 0x020e079c +#define IOMUXC_SW_PAD_CTL_GRP_B4DS 0x020e07a0 +#define IOMUXC_SW_PAD_CTL_GRP_B5DS 0x020e07a4 +#define IOMUXC_SW_PAD_CTL_GRP_B6DS 0x020e07a8 +#define IOMUXC_UART1_UART_RTS_B_SELECT_INPUT 0x020e091c +#define IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT 0x020e0920 +#endif + +dcd_hdr: + .word CPU_2_BE_32((0xd2 << 24) | ((dcd_end - .) << 8) | DCD_VERSION) +dcd_start: + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_reset) + /* RESET_OUT GPIO_7_12 */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005) + + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* CS2CDR default: 0x007236c1 */ + + MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002001) /* ENET PLL */ + + /* enable all relevant clocks... */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, 0xf0c03f3f) /* default: 0xf0c03f0f APBH-DMA */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, 0xf0fc0c00) /* default: 0xf0fc0000 */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, 0xfc3ff0cc) /* default: 0xfc3ff00c I2C1 */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR3, 0x3ff00000) /* default: 0x3ff00000 */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, 0xff00ff00) /* default: 0x0000ff00 GPMI BCH */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, 0xff033f0f) /* default: 0xf0033f0f UART1 */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, 0xffff03ff) /* default: 0xffff0003 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) */ + + /* IOMUX: */ + MXC_DCD_ITEM(IOMUXC_GPR1, 0x48640005) /* default: 0x48400005 ENET_CLK output */ + /* UART1 pad config */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7, 0x00000001) /* UART1 TXD */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6, 0x00000001) /* UART1 RXD */ + MXC_DCD_ITEM(IOMUXC_UART1_UART_RX_DATA_SELECT_INPUT, 0x00000003) /* UART1 RXD INPUT_SEL */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0, 0x00000001) /* UART1 CTS */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1, 0x00000001) /* UART1 RTS */ + MXC_DCD_ITEM(IOMUXC_UART1_UART_RTS_B_SELECT_INPUT, 0x00000003) /* UART1 RTS INPUT_SEL */ + + /* NAND */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CLE, 0x00000000) /* NANDF_CLE: NANDF_CLE */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_ALE, 0x00000000) /* NANDF_ALE: NANDF_ALE */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B, 0x00000000) /* NANDF_WP_B: NANDF_WPn */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_READY, 0x00000000) /* NANDF_RB0: NANDF_READY0 */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS0_B, 0x00000000) /* NANDF_CS0: NANDF_CS0 */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CMD, 0x00000001) /* SD4_CMD: NANDF_RDn */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SD4_CLK, 0x00000001) /* SD4_CLK: NANDF_WRn */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00, 0x00000000) /* NANDF_D0: NANDF_D0 */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01, 0x00000000) /* NANDF_D1: NANDF_D1 */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02, 0x00000000) /* NANDF_D2: NANDF_D2 */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03, 0x00000000) /* NANDF_D3: NANDF_D3 */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04, 0x00000000) /* NANDF_D4: NANDF_D4 */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05, 0x00000000) /* NANDF_D5: NANDF_D5 */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06, 0x00000000) /* NANDF_D6: NANDF_D6 */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07, 0x00000000) /* NANDF_D7: NANDF_D7 */ + + /* ext. mem CS */ + MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_NAND_CS2_B, 0x00000000) /* NANDF_CS2: NANDF_CS2 */ + /* DRAM_DQM[0..7] */ + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0, DQM_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1, DQM_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2, DQM_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3, DQM_MASK) + MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM4, DQM_MASK) + MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM5, DQM_MASK) + MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM6, DQM_MASK) + MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM7, DQM_MASK) + + /* DRAM_A[0..15] */ + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, DDR_ADDR_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01, DDR_ADDR_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02, DDR_ADDR_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03, DDR_ADDR_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04, DDR_ADDR_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05, DDR_ADDR_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06, DDR_ADDR_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07, DDR_ADDR_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08, DDR_ADDR_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09, DDR_ADDR_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10, DDR_ADDR_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11, DDR_ADDR_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12, DDR_ADDR_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13, DDR_ADDR_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14, DDR_ADDR_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15, DDR_ADDR_MASK) + /* DRAM_CAS */ + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS, DDR_CTRL_MASK) + /* DRAM_RAS */ + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS, DDR_CTRL_MASK) + /* DRAM_SDCLK[0..1] */ + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P, SDCLK_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK1_P, SDCLK_MASK) + /* DRAM_RESET */ + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET, DDR_CTRL_MASK) + /* DRAM_SDCKE[0..1] */ + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0, SDCKE_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1, SDCKE_MASK) + /* DRAM_SDBA[0..2] */ + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0, 0x00000000) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1, 0x00000000) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2, 0x00000000) + /* DRAM_SDODT[0..1] */ + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0, SDODT_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1, SDODT_MASK) + /* DRAM_B[0..7]DS */ + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B0DS, DSE_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B1DS, DSE_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B2DS, DSE_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_B3DS, DSE_MASK) + MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B4DS, DSE_MASK) + MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B5DS, DSE_MASK) + MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B6DS, DSE_MASK) + MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_GRP_B7DS, DSE_MASK) + /* ADDDS */ + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_ADDDS, DSE_MASK) + /* DDRMODE_CTL */ + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL, DDR_MODE_MASK) + /* DDRPKE */ + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPKE, 0x00000000) + /* DDRMODE */ + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRMODE, DDR_MODE_MASK) + /* CTLDS */ + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_CTLDS, DSE_MASK) + /* DDR_TYPE */ + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE, DDR_SEL_MASK) + /* DDRPK */ + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRPK, 1 << PUE_SHIFT) + /* DDRHYS */ + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_DDRHYS, 0x00000000) + +#ifdef CONFIG_MX6Q + /* TERM_CTL[0..7] */ + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL0, ODT_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL1, ODT_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL2, ODT_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL3, ODT_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL4, ODT_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL5, ODT_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL6, ODT_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_GRP_TERM_CTL7, ODT_MASK) +#endif + /* SDRAM initialization */ + /* MPRDDQBY[0..7]DL */ + MXC_DCD_ITEM(MMDC1_MPRDDQBY0DL, 0x33333333) + MXC_DCD_ITEM(MMDC1_MPRDDQBY1DL, 0x33333333) + MXC_DCD_ITEM(MMDC1_MPRDDQBY2DL, 0x33333333) + MXC_DCD_ITEM(MMDC1_MPRDDQBY3DL, 0x33333333) + MXC_DCD_ITEM_64(MMDC2_MPRDDQBY0DL, 0x33333333) + MXC_DCD_ITEM_64(MMDC2_MPRDDQBY1DL, 0x33333333) + MXC_DCD_ITEM_64(MMDC2_MPRDDQBY2DL, 0x33333333) + MXC_DCD_ITEM_64(MMDC2_MPRDDQBY3DL, 0x33333333) + /* MDMISC */ + MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL | 2) /* reset MMDC FSM */ +ddr_reset: + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDMISC, 0x00000002) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack) + + /* MSDSCR Conf Req */ + MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008000) +con_ack: + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDSCR, 0x00004000) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, ddr_calib) + /* MDCTL */ + MXC_DCD_ITEM(MMDC1_MDCTL, MDCTL_VAL) +ddr_calib: + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_SET, MMDC1_MDMISC, 0x40000000) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, zq_calib) + + MXC_DCD_ITEM(MMDC1_MDCFG0, MDCFG0_VAL) + MXC_DCD_ITEM(MMDC1_MDCFG1, MDCFG1_VAL) + MXC_DCD_ITEM(MMDC1_MDCFG2, MDCFG2_VAL) + MXC_DCD_ITEM(MMDC1_MDRWD, 0x000026d2) /* MDRWD */ + MXC_DCD_ITEM(MMDC1_MDOR, MDOR_VAL) + MXC_DCD_ITEM(MMDC1_MDOTC, MDOTC_VAL) + MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_0) + MXC_DCD_ITEM_64(MMDC2_MDPDC, MDPDC_VAL_0) + MXC_DCD_ITEM(MMDC1_MDASP, (PHYS_SDRAM_1_SIZE + SZ_256M) / SZ_32M - 1) /* MDASP */ + + /* CS0 MRS: */ + MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 0, mr0_val)) + MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val)) + MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 2, mr2_val)) + MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) +#if BANK_ADDR_BITS > 1 + /* CS1 MRS: MR2 */ + MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 0, mr0_val)) + MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 1, mr1_val)) + MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 2, mr2_val)) + MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(1, 3, 4)) /* MRS: select MPR */ +#endif + + MXC_DCD_ITEM(MMDC1_MDREF, 0x0000c000) /* disable refresh */ + + MXC_DCD_ITEM(MMDC1_MPODTCTRL, 0x00022222) /* MPODTCTRL */ + MXC_DCD_ITEM_64(MMDC2_MPODTCTRL, 0x00022222) + + /* DDR3 calibration */ + MXC_DCD_ITEM(MMDC1_MPPDCMPR2, 0x00000003) /* select default compare pattern for DQ calibration */ + MXC_DCD_ITEM(MMDC1_MAPSR, 0x00011007) + + /* ZQ calibration */ + MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008010) /* precharge all */ + MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008040) /* MRS: ZQ calibration */ + MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa139002b) + +zq_calib: + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPZQHWCTRL, 0x00010000) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wl_calib) + + MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa1380000) + +#ifndef DO_WL_CALIB +#define WL_DLY_DQS_VAL 30 +#define WL_DLY_DQS0 (WL_DLY_DQS_VAL + 0) +#define WL_DLY_DQS1 (WL_DLY_DQS_VAL + 0) +#define WL_DLY_DQS2 (WL_DLY_DQS_VAL + 0) +#define WL_DLY_DQS3 (WL_DLY_DQS_VAL + 0) +#define WL_DLY_DQS4 (WL_DLY_DQS_VAL + 0) +#define WL_DLY_DQS5 (WL_DLY_DQS_VAL + 0) +#define WL_DLY_DQS6 (WL_DLY_DQS_VAL + 0) +#define WL_DLY_DQS7 (WL_DLY_DQS_VAL + 0) +#endif + /* Write leveling */ + MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 4)) /* MRS: select MPR */ +#ifdef DO_WL_CALIB + MXC_DCD_ITEM(MMDC1_MDSCR, 0x00808231) /* MRS: start write leveling */ + MXC_DCD_ITEM(MMDC1_MPWLGCR, 0x00000001) /* initiate Write leveling */ +wl_calib: + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000001) + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWLGCR, 0x00000f00) +#if PHYS_SDRAM_1_WIDTH == 64 + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000001) + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWLGCR, 0x00000f00) +#endif /* PHYS_SDRAM_1_WIDTH == 64 */ +#else + MXC_DCD_ITEM(MMDC1_MPWLDECTRL0, (WL_DLY_DQS1 << 16) | (WL_DLY_DQS0 << 0)) + MXC_DCD_ITEM(MMDC1_MPWLDECTRL1, (WL_DLY_DQS3 << 16) | (WL_DLY_DQS2 << 0)) + MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL0, (WL_DLY_DQS5 << 16) | (WL_DLY_DQS4 << 0)) + MXC_DCD_ITEM_64(MMDC2_MPWLDECTRL1, (WL_DLY_DQS7 << 16) | (WL_DLY_DQS6 << 0)) +wl_calib: +#endif /* DO_WL_CALIB */ + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset) + + MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 1, mr1_val)) /* MRS: end write leveling */ + + MXC_DCD_ITEM(MMDC1_MPZQHWCTRL, 0xa138002b) + + /* DQS gating calibration */ + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK | 0x7000) /* enable Pullups on DQS pads */ + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK | 0x7000) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK | 0x7000) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK | 0x7000) + MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK | 0x7000) + MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK | 0x7000) + MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK | 0x7000) + MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK | 0x7000) + + MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL) + + MXC_DCD_ITEM(MMDC1_MDSCR, 0x00008020) /* issue one refresh cycle */ + MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */ + + MXC_DCD_ITEM(MMDC1_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */ + MXC_DCD_ITEM(MMDC1_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */ + MXC_DCD_ITEM_64(MMDC2_MPRDDLCTL, 0x40404040) /* DQ RD Delay default values */ + MXC_DCD_ITEM_64(MMDC2_MPWRDLCTL, 0x40404040) /* DQ WR Delay default values */ + MXC_DCD_ITEM(MMDC1_MPMUR0, 0x00000800) + MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue fifo reset */ +dqs_fifo_reset: + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_fifo_reset2) + MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x80000000) /* issue 2nd fifo reset */ +dqs_fifo_reset2: + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x80000000) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, dqs_calib) + MXC_DCD_ITEM(MMDC1_MPDGCTRL0, 0x50800000) /* choose 32 wait cycles and start DQS calib. */ +dqs_calib: + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x10000000) + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPDGCTRL0, 0x00001000) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, rd_dl_calib) + + /* DRAM_SDQS[0..7] pad config */ + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P, SDQS_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P, SDQS_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P, SDQS_MASK) + MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P, SDQS_MASK) + MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS4_P, SDQS_MASK) + MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS5_P, SDQS_MASK) + MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS6_P, SDQS_MASK) + MXC_DCD_ITEM_64(IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS7_P, SDQS_MASK) + MXC_DCD_ITEM(MMDC1_MDMISC, MDMISC_VAL) + + /* Read delay calibration */ + MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */ + MXC_DCD_ITEM(MMDC1_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */ + MXC_DCD_ITEM_64(MMDC2_MPRDDLHWCTL, 0x00000030) /* MPRDDLHWCTL: HW_WR_DL_CMP_CYC | HW_RD_DL_EN */ +rd_dl_calib: + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x00000010) + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPRDDLHWCTL, 0x0000000f) + MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x00000010) + MXC_DCD_CMD_CHK_64(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPRDDLHWCTL, 0x0000000f) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib) + + MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */ + MXC_DCD_ITEM(MMDC1_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */ +wr_dl_calib: + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x00000010) + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MPWRDLHWCTL, 0x0000000f) +#if PHYS_SDRAM_1_WIDTH == 64 + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, wr_dl_calib2) + + MXC_DCD_ITEM(MMDC1_MDSCR, 0x04008050) /* precharge all to bank 0 */ + MXC_DCD_ITEM(MMDC2_MPWRDLHWCTL, 0x00000030) /* start WR DL calibration */ +wr_dl_calib2: + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x00000010) + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC2_MPWRDLHWCTL, 0x0000000f) +#endif + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE, con_ack_clr) + + MXC_DCD_ITEM(MMDC1_MDSCR, MDSCR_MRS_VAL(0, 3, 0)) /* MRS: select normal data path */ + MXC_DCD_ITEM(MMDC1_MDREF, (3 << 11) | (0 << 14)) /* 4 cycles per 64kHz period (3.9us) */ + MXC_DCD_ITEM(MMDC1_MAPSR, 0x00011006) /* MAPSR */ + MXC_DCD_ITEM(MMDC1_MDPDC, MDPDC_VAL_1) + MXC_DCD_ITEM_64(MMDC2_MDPDC, MDPDC_VAL_1) + + /* MDSCR: Normal operation */ + MXC_DCD_ITEM(MMDC1_MDSCR, 0x00000000) + +con_ack_clr: + MXC_DCD_CMD_CHK(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CHK_CLR, MMDC1_MDSCR, 0x00004000) +dcd_end: + .ifgt dcd_end - dcd_start - 1768 + .error "DCD too large!" + .endif diff --git a/board/karo/tx6/tx6qdl.c b/board/karo/tx6/tx6qdl.c new file mode 100644 index 0000000000..c979c476c9 --- /dev/null +++ b/board/karo/tx6/tx6qdl.c @@ -0,0 +1,1147 @@ +/* + * Copyright (C) 2012 Lothar Waßmann + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/karo.h" + +#define TX6_FEC_RST_GPIO IMX_GPIO_NR(7, 6) +#define TX6_FEC_PWR_GPIO IMX_GPIO_NR(3, 20) +#define TX6_FEC_INT_GPIO IMX_GPIO_NR(2, 4) +#define TX6_LED_GPIO IMX_GPIO_NR(2, 20) + +#define TX6_LCD_PWR_GPIO IMX_GPIO_NR(2, 31) +#define TX6_LCD_RST_GPIO IMX_GPIO_NR(3, 29) +#define TX6_LCD_BACKLIGHT_GPIO IMX_GPIO_NR(1, 1) + +#define TX6_RESET_OUT_GPIO IMX_GPIO_NR(7, 12) + +#define TEMPERATURE_MIN -40 +#define TEMPERATURE_HOT 80 +#define TEMPERATURE_MAX 125 + +DECLARE_GLOBAL_DATA_PTR; + +#define MUX_CFG_SION IOMUX_PAD(0, 0, IOMUX_CONFIG_SION, 0, 0, 0) + +static const iomux_v3_cfg_t tx6qdl_pads[] = { + /* NAND flash pads */ + MX6_PAD_NANDF_CLE__RAWNAND_CLE, + MX6_PAD_NANDF_ALE__RAWNAND_ALE, + MX6_PAD_NANDF_WP_B__RAWNAND_RESETN, + MX6_PAD_NANDF_RB0__RAWNAND_READY0, + MX6_PAD_NANDF_CS0__RAWNAND_CE0N, + MX6_PAD_SD4_CMD__RAWNAND_RDN, + MX6_PAD_SD4_CLK__RAWNAND_WRN, + MX6_PAD_NANDF_D0__RAWNAND_D0, + MX6_PAD_NANDF_D1__RAWNAND_D1, + MX6_PAD_NANDF_D2__RAWNAND_D2, + MX6_PAD_NANDF_D3__RAWNAND_D3, + MX6_PAD_NANDF_D4__RAWNAND_D4, + MX6_PAD_NANDF_D5__RAWNAND_D5, + MX6_PAD_NANDF_D6__RAWNAND_D6, + MX6_PAD_NANDF_D7__RAWNAND_D7, + + /* RESET_OUT */ + MX6_PAD_GPIO_17__GPIO_7_12, + + /* UART pads */ +#if CONFIG_MXC_UART_BASE == UART1_BASE + MX6_PAD_SD3_DAT7__UART1_TXD, + MX6_PAD_SD3_DAT6__UART1_RXD, + MX6_PAD_SD3_DAT1__UART1_RTS, + MX6_PAD_SD3_DAT0__UART1_CTS, +#endif +#if CONFIG_MXC_UART_BASE == UART2_BASE + MX6_PAD_SD4_DAT4__UART2_RXD, + MX6_PAD_SD4_DAT7__UART2_TXD, + MX6_PAD_SD4_DAT5__UART2_RTS, + MX6_PAD_SD4_DAT6__UART2_CTS, +#endif +#if CONFIG_MXC_UART_BASE == UART3_BASE + MX6_PAD_EIM_D24__UART3_TXD, + MX6_PAD_EIM_D25__UART3_RXD, + MX6_PAD_SD3_RST__UART3_RTS, + MX6_PAD_SD3_DAT3__UART3_CTS, +#endif + /* internal I2C */ + MX6_PAD_EIM_D28__I2C1_SDA, + MX6_PAD_EIM_D21__I2C1_SCL, + + /* FEC PHY GPIO functions */ + MX6_PAD_EIM_D20__GPIO_3_20 | MUX_CFG_SION, /* PHY POWER */ + MX6_PAD_SD3_DAT2__GPIO_7_6 | MUX_CFG_SION, /* PHY RESET */ + MX6_PAD_SD3_DAT4__GPIO_7_1, /* PHY INT */ +}; + +static const iomux_v3_cfg_t tx6qdl_fec_pads[] = { + /* FEC functions */ + MX6_PAD_ENET_MDC__ENET_MDC, + MX6_PAD_ENET_MDIO__ENET_MDIO, + MX6_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT, + MX6_PAD_ENET_RX_ER__ENET_RX_ER, + MX6_PAD_ENET_CRS_DV__ENET_RX_EN, + MX6_PAD_ENET_RXD1__ENET_RDATA_1, + MX6_PAD_ENET_RXD0__ENET_RDATA_0, + MX6_PAD_ENET_TX_EN__ENET_TX_EN, + MX6_PAD_ENET_TXD1__ENET_TDATA_1, + MX6_PAD_ENET_TXD0__ENET_TDATA_0, +}; + +static const struct gpio tx6qdl_gpios[] = { + { TX6_RESET_OUT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "#RESET_OUT", }, + { TX6_FEC_PWR_GPIO, GPIOF_OUTPUT_INIT_HIGH, "FEC PHY PWR", }, + { TX6_FEC_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "FEC PHY RESET", }, + { TX6_FEC_INT_GPIO, GPIOF_INPUT, "FEC PHY INT", }, +}; + +/* + * Functions + */ +/* placed in section '.data' to prevent overwriting relocation info + * overlayed with bss + */ +static u32 wrsr __attribute__((section(".data"))); + +#define WRSR_POR (1 << 4) +#define WRSR_TOUT (1 << 1) +#define WRSR_SFTW (1 << 0) + +static void print_reset_cause(void) +{ + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + void __iomem *wdt_base = (void __iomem *)WDOG1_BASE_ADDR; + u32 srsr; + char *dlm = ""; + + printf("Reset cause: "); + + srsr = readl(&src_regs->srsr); + wrsr = readw(wdt_base + 4); + + if (wrsr & WRSR_POR) { + printf("%sPOR", dlm); + dlm = " | "; + } + if (srsr & 0x00004) { + printf("%sCSU", dlm); + dlm = " | "; + } + if (srsr & 0x00008) { + printf("%sIPP USER", dlm); + dlm = " | "; + } + if (srsr & 0x00010) { + if (wrsr & WRSR_SFTW) { + printf("%sSOFT", dlm); + dlm = " | "; + } + if (wrsr & WRSR_TOUT) { + printf("%sWDOG", dlm); + dlm = " | "; + } + } + if (srsr & 0x00020) { + printf("%sJTAG HIGH-Z", dlm); + dlm = " | "; + } + if (srsr & 0x00040) { + printf("%sJTAG SW", dlm); + dlm = " | "; + } + if (srsr & 0x10000) { + printf("%sWARM BOOT", dlm); + dlm = " | "; + } + if (dlm[0] == '\0') + printf("unknown"); + + printf("\n"); +} + +int read_cpu_temperature(void); +int check_cpu_temperature(int boot); + +static void tx6qdl_print_cpuinfo(void) +{ + u32 cpurev = get_cpu_rev(); + char *cpu_str = "?"; + + switch ((cpurev >> 12) & 0xff) { + case MXC_CPU_MX6SL: + cpu_str = "SL"; + break; + case MXC_CPU_MX6DL: + cpu_str = "DL"; + break; + case MXC_CPU_MX6SOLO: + cpu_str = "SOLO"; + break; + case MXC_CPU_MX6Q: + cpu_str = "Q"; + break; + } + + printf("CPU: Freescale i.MX6%s rev%d.%d at %d MHz\n", + cpu_str, + (cpurev & 0x000F0) >> 4, + (cpurev & 0x0000F) >> 0, + mxc_get_clock(MXC_ARM_CLK) / 1000000); + + print_reset_cause(); + check_cpu_temperature(1); +} + +#define LTC3676_DVB2A 0x0C +#define LTC3676_DVB2B 0x0D +#define LTC3676_DVB4A 0x10 +#define LTC3676_DVB4B 0x11 + +#define VDD_SOC_mV (1375 + 50) +#define VDD_CORE_mV (1375 + 50) + +#define mV_to_regval(mV) (((mV) * 360 / 330 - 825 + 1) / 25) +#define regval_to_mV(v) (((v) * 25 + 825) * 330 / 360) + +static int setup_pmic_voltages(void) +{ + int ret; + unsigned char value; + + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + + ret = i2c_probe(CONFIG_SYS_I2C_SLAVE); + if (ret != 0) { + printf("Failed to initialize I2C\n"); + return ret; + } + + ret = i2c_read(CONFIG_SYS_I2C_SLAVE, 0x11, 1, &value, 1); + if (ret) { + printf("%s: i2c_read error: %d\n", __func__, ret); + return ret; + } + + /* VDDCORE/VDDSOC default 1.375V is not enough, considering + pfuze tolerance and IR drop and ripple, need increase + to 1.425V for SabreSD */ + + value = 0x39; /* VB default value & PGOOD not forced when slewing */ + ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2B, 1, &value, 1); + if (ret) { + printf("%s: failed to write PMIC DVB2B register: %d\n", + __func__, ret); + return ret; + } + ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4B, 1, &value, 1); + if (ret) { + printf("%s: failed to write PMIC DVB4B register: %d\n", + __func__, ret); + return ret; + } + + value = mV_to_regval(VDD_SOC_mV); + ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB2A, 1, &value, 1); + if (ret) { + printf("%s: failed to write PMIC DVB2A register: %d\n", + __func__, ret); + return ret; + } + printf("VDDSOC set to %dmV\n", regval_to_mV(value)); + + value = mV_to_regval(VDD_CORE_mV); + ret = i2c_write(CONFIG_SYS_I2C_SLAVE, LTC3676_DVB4A, 1, &value, 1); + if (ret) { + printf("%s: failed to write PMIC DVB4A register: %d\n", + __func__, ret); + return ret; + } + printf("VDDCORE set to %dmV\n", regval_to_mV(value)); + return 0; +} + +int board_early_init_f(void) +{ + gpio_request_array(tx6qdl_gpios, ARRAY_SIZE(tx6qdl_gpios)); + imx_iomux_v3_setup_multiple_pads(tx6qdl_pads, ARRAY_SIZE(tx6qdl_pads)); + + return 0; +} + +int board_init(void) +{ + int ret; + + /* Address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x1000; +#ifdef CONFIG_OF_LIBFDT + gd->bd->bi_arch_number = -1; +#else + gd->bd->bi_arch_number = 4429; +#endif + ret = setup_pmic_voltages(); + if (ret) { + printf("Failed to setup PMIC voltages\n"); + hang(); + } + return 0; +} + +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + PHYS_SDRAM_1_SIZE); + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = get_ram_size((void *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); +#if CONFIG_NR_DRAM_BANKS > 1 + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; + gd->bd->bi_dram[1].size = get_ram_size((void *)PHYS_SDRAM_2, + PHYS_SDRAM_2_SIZE); +#endif +} + +#ifdef CONFIG_CMD_MMC +static const iomux_v3_cfg_t mmc0_pads[] = { + MX6_PAD_SD1_CMD__USDHC1_CMD, + MX6_PAD_SD1_CLK__USDHC1_CLK, + MX6_PAD_SD1_DAT0__USDHC1_DAT0, + MX6_PAD_SD1_DAT1__USDHC1_DAT1, + MX6_PAD_SD1_DAT2__USDHC1_DAT2, + MX6_PAD_SD1_DAT3__USDHC1_DAT3, + /* SD1 CD */ + MX6_PAD_SD3_CMD__GPIO_7_2, +}; + +static const iomux_v3_cfg_t mmc1_pads[] = { + MX6_PAD_SD2_CMD__USDHC2_CMD, + MX6_PAD_SD2_CLK__USDHC2_CLK, + MX6_PAD_SD2_DAT0__USDHC2_DAT0, + MX6_PAD_SD2_DAT1__USDHC2_DAT1, + MX6_PAD_SD2_DAT2__USDHC2_DAT2, + MX6_PAD_SD2_DAT3__USDHC2_DAT3, + /* SD2 CD */ + MX6_PAD_SD3_CLK__GPIO_7_3, +}; + +static struct tx6_esdhc_cfg { + const iomux_v3_cfg_t *pads; + int num_pads; + enum mxc_clock clkid; + struct fsl_esdhc_cfg cfg; + int cd_gpio; +} tx6qdl_esdhc_cfg[] = { + { + .pads = mmc0_pads, + .num_pads = ARRAY_SIZE(mmc0_pads), + .clkid = MXC_ESDHC_CLK, + .cfg = { + .esdhc_base = (void __iomem *)USDHC1_BASE_ADDR, + .max_bus_width = 4, + }, + .cd_gpio = IMX_GPIO_NR(7, 2), + }, + { + .pads = mmc1_pads, + .num_pads = ARRAY_SIZE(mmc1_pads), + .clkid = MXC_ESDHC2_CLK, + .cfg = { + .esdhc_base = (void __iomem *)USDHC2_BASE_ADDR, + .max_bus_width = 4, + }, + .cd_gpio = IMX_GPIO_NR(7, 3), + }, +}; + +static inline struct tx6_esdhc_cfg *to_tx6_esdhc_cfg(struct fsl_esdhc_cfg *cfg) +{ + void *p = cfg; + + return p - offsetof(struct tx6_esdhc_cfg, cfg); +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct tx6_esdhc_cfg *cfg = to_tx6_esdhc_cfg(mmc->priv); + + if (cfg->cd_gpio < 0) + return cfg->cd_gpio; + + debug("SD card %d is %spresent\n", + cfg - tx6qdl_esdhc_cfg, + gpio_get_value(cfg->cd_gpio) ? "NOT " : ""); + return !gpio_get_value(cfg->cd_gpio); +} + +int board_mmc_init(bd_t *bis) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(tx6qdl_esdhc_cfg); i++) { + struct mmc *mmc; + struct tx6_esdhc_cfg *cfg = &tx6qdl_esdhc_cfg[i]; + int ret; + + if (i >= CONFIG_SYS_FSL_ESDHC_NUM) + break; + + cfg->cfg.sdhc_clk = mxc_get_clock(cfg->clkid); + imx_iomux_v3_setup_multiple_pads(cfg->pads, cfg->num_pads); + + ret = gpio_request_one(cfg->cd_gpio, + GPIOF_INPUT, "MMC CD"); + if (ret) { + printf("Error %d requesting GPIO%d_%d\n", + ret, cfg->cd_gpio / 32, cfg->cd_gpio % 32); + continue; + } + + debug("%s: Initializing MMC slot %d\n", __func__, i); + fsl_esdhc_initialize(bis, &cfg->cfg); + + mmc = find_mmc_device(i); + if (mmc == NULL) + continue; + if (board_mmc_getcd(mmc) > 0) + mmc_init(mmc); + } + return 0; +} +#endif /* CONFIG_CMD_MMC */ + +#ifdef CONFIG_FEC_MXC + +#define FEC_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH | \ + PAD_CTL_SRE_FAST) +#define FEC_PAD_CTL2 (PAD_CTL_DVS | PAD_CTL_SRE_FAST) +#define GPIO_PAD_CTL (PAD_CTL_DVS | PAD_CTL_DSE_HIGH) + +#ifndef ETH_ALEN +#define ETH_ALEN 6 +#endif + +int board_eth_init(bd_t *bis) +{ + int ret; + + /* delay at least 21ms for the PHY internal POR signal to deassert */ + udelay(22000); + + imx_iomux_v3_setup_multiple_pads(tx6qdl_fec_pads, ARRAY_SIZE(tx6qdl_fec_pads)); + + /* Deassert RESET to the external phy */ + gpio_set_value(TX6_FEC_RST_GPIO, 1); + + ret = cpu_eth_init(bis); + if (ret) + printf("cpu_eth_init() failed: %d\n", ret); + + return ret; +} +#endif /* CONFIG_FEC_MXC */ + +enum { + LED_STATE_INIT = -1, + LED_STATE_OFF, + LED_STATE_ON, +}; + +static inline int calc_blink_rate(int tmp) +{ + return CONFIG_SYS_HZ + CONFIG_SYS_HZ / 10 - + (tmp - TEMPERATURE_MIN) * CONFIG_SYS_HZ / + (TEMPERATURE_HOT - TEMPERATURE_MIN); +} + +void show_activity(int arg) +{ + static int led_state = LED_STATE_INIT; + static int blink_rate; + static ulong last; + + if (led_state == LED_STATE_INIT) { + last = get_timer(0); + gpio_set_value(TX6_LED_GPIO, 1); + led_state = LED_STATE_ON; + blink_rate = calc_blink_rate(check_cpu_temperature(0)); + } else { + if (get_timer(last) > blink_rate) { + blink_rate = calc_blink_rate(check_cpu_temperature(0)); + last = get_timer_masked(); + if (led_state == LED_STATE_ON) { + gpio_set_value(TX6_LED_GPIO, 0); + } else { + gpio_set_value(TX6_LED_GPIO, 1); + } + led_state = 1 - led_state; + } + } +} + +static const iomux_v3_cfg_t stk5_pads[] = { + /* SW controlled LED on STK5 baseboard */ + MX6_PAD_EIM_A18__GPIO_2_20, + + /* LCD data pins */ + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, /* HSYNC */ + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, /* VSYNC */ + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* OE_ACD */ + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* LSCLK */ + + /* I2C bus on DIMM pins 40/41 */ + MX6_PAD_GPIO_6__I2C3_SDA, + MX6_PAD_GPIO_3__I2C3_SCL, + + /* TSC200x PEN IRQ */ + MX6_PAD_EIM_D26__GPIO_3_26, + + /* EDT-FT5x06 Polytouch panel */ + MX6_PAD_NANDF_CS2__GPIO_6_15, /* IRQ */ + MX6_PAD_EIM_A16__GPIO_2_22, /* RESET */ + MX6_PAD_EIM_A17__GPIO_2_21, /* WAKE */ + + /* USBH1 */ + MX6_PAD_EIM_D31__GPIO_3_31, /* VBUSEN */ + MX6_PAD_EIM_D30__GPIO_3_30, /* OC */ + /* USBOTG */ + MX6_PAD_EIM_D23__GPIO_3_23, /* USBOTG ID */ + MX6_PAD_GPIO_7__GPIO_1_7, /* VBUSEN */ + MX6_PAD_GPIO_8__GPIO_1_8, /* OC */ +}; + +static const struct gpio stk5_gpios[] = { + { TX6_LED_GPIO, GPIOF_OUTPUT_INIT_LOW, "HEARTBEAT LED", }, + + { IMX_GPIO_NR(3, 23), GPIOF_INPUT, "USBOTG ID", }, + { IMX_GPIO_NR(1, 8), GPIOF_INPUT, "USBOTG OC", }, + { IMX_GPIO_NR(1, 7), GPIOF_OUTPUT_INIT_LOW, "USBOTG VBUS enable", }, + { IMX_GPIO_NR(3, 30), GPIOF_INPUT, "USBH1 OC", }, + { IMX_GPIO_NR(3, 31), GPIOF_OUTPUT_INIT_LOW, "USBH1 VBUS enable", }, +}; + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + /* set to max. size supported by SoC */ + .vl_col = 1920, + .vl_row = 1080, + + .vl_bpix = LCD_COLOR24, /* Bits per pixel, 0: 1bpp, 1: 2bpp, 2: 4bpp, 3: 8bpp ... */ +}; + +static struct fb_videomode tx6_fb_modes[] = { + { + /* Standard VGA timing */ + .name = "VGA", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = KHZ2PICOS(25175), + .left_margin = 48, + .hsync_len = 96, + .right_margin = 16, + .upper_margin = 31, + .vsync_len = 2, + .lower_margin = 12, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ETV570 640 x 480 display. Syncs low active, + * DE high active, 115.2 mm x 86.4 mm display area + * VGA compatible timing + */ + .name = "ETV570", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = KHZ2PICOS(25175), + .left_margin = 114, + .hsync_len = 30, + .right_margin = 16, + .upper_margin = 32, + .vsync_len = 3, + .lower_margin = 10, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ET0350G0DH6 320 x 240 display. + * 70.08 mm x 52.56 mm display area. + */ + .name = "ET0350", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = KHZ2PICOS(6500), + .left_margin = 68 - 34, + .hsync_len = 34, + .right_margin = 20, + .upper_margin = 18 - 3, + .vsync_len = 3, + .lower_margin = 4, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ET0430G0DH6 480 x 272 display. + * 95.04 mm x 53.856 mm display area. + */ + .name = "ET0430", + .refresh = 60, + .xres = 480, + .yres = 272, + .pixclock = KHZ2PICOS(9000), + .left_margin = 2, + .hsync_len = 41, + .right_margin = 2, + .upper_margin = 2, + .vsync_len = 10, + .lower_margin = 2, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ET0500G0DH6 800 x 480 display. + * 109.6 mm x 66.4 mm display area. + */ + .name = "ET0500", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = KHZ2PICOS(33260), + .left_margin = 216 - 128, + .hsync_len = 128, + .right_margin = 1056 - 800 - 216, + .upper_margin = 35 - 2, + .vsync_len = 2, + .lower_margin = 525 - 480 - 35, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ETQ570G0DH6 320 x 240 display. + * 115.2 mm x 86.4 mm display area. + */ + .name = "ETQ570", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = KHZ2PICOS(6400), + .left_margin = 38, + .hsync_len = 30, + .right_margin = 30, + .upper_margin = 16, /* 15 according to datasheet */ + .vsync_len = 3, /* TVP -> 1>x>5 */ + .lower_margin = 4, /* 4.5 according to datasheet */ + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ET0700G0DH6 800 x 480 display. + * 152.4 mm x 91.44 mm display area. + */ + .name = "ET0700", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = KHZ2PICOS(33260), + .left_margin = 216 - 128, + .hsync_len = 128, + .right_margin = 1056 - 800 - 216, + .upper_margin = 35 - 2, + .vsync_len = 2, + .lower_margin = 525 - 480 - 35, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* unnamed entry for assigning parameters parsed from 'video_mode' string */ + .refresh = 60, + .left_margin = 48, + .hsync_len = 96, + .right_margin = 16, + .upper_margin = 31, + .vsync_len = 2, + .lower_margin = 12, + .sync = FB_SYNC_CLK_LAT_FALL, + }, +}; + +static int lcd_enabled = 1; + +void lcd_enable(void) +{ + /* HACK ALERT: + * global variable from common/lcd.c + * Set to 0 here to prevent messages from going to LCD + * rather than serial console + */ + lcd_is_enabled = 0; + + karo_load_splashimage(1); + + if (lcd_enabled) { + debug("Switching LCD on\n"); + gpio_set_value(TX6_LCD_PWR_GPIO, 1); + udelay(100); + gpio_set_value(TX6_LCD_RST_GPIO, 1); + udelay(300000); + gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, 0); + } +} + +void lcd_disable(void) +{ + printf("Disabling LCD\n"); +} + +void lcd_panel_disable(void) +{ + if (lcd_enabled) { + debug("Switching LCD off\n"); + gpio_set_value(TX6_LCD_BACKLIGHT_GPIO, 1); + gpio_set_value(TX6_LCD_RST_GPIO, 0); + gpio_set_value(TX6_LCD_PWR_GPIO, 0); + } +} + +static const iomux_v3_cfg_t stk5_lcd_pads[] = { + /* LCD RESET */ + MX6_PAD_EIM_D29__GPIO_3_29, + /* LCD POWER_ENABLE */ + MX6_PAD_EIM_EB3__GPIO_2_31, + /* LCD Backlight (PWM) */ + MX6_PAD_GPIO_1__GPIO_1_1, + + /* Display */ + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN2, + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN3, + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0, + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1, + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2, + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3, + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4, + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5, + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6, + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7, + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8, + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9, + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10, + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11, + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12, + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13, + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14, + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15, + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16, + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17, + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18, + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19, + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20, + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21, + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22, + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23, +}; + +static const struct gpio stk5_lcd_gpios[] = { + { TX6_LCD_RST_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD RESET", }, + { TX6_LCD_PWR_GPIO, GPIOF_OUTPUT_INIT_LOW, "LCD POWER", }, + { TX6_LCD_BACKLIGHT_GPIO, GPIOF_OUTPUT_INIT_HIGH, "LCD BACKLIGHT", }, +}; + +void lcd_ctrl_init(void *lcdbase) +{ + int color_depth = 24; + char *vm; + unsigned long val; + int refresh = 60; + struct fb_videomode *p = &tx6_fb_modes[0]; + struct fb_videomode fb_mode; + int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0; + int pix_fmt = 0; + ipu_di_clk_parent_t di_clk_parent = DI_PCLK_PLL3; + unsigned long di_clk_rate = 65000000; + + if (!lcd_enabled) { + debug("LCD disabled\n"); + return; + } + + if (tstc() || (wrsr & WRSR_TOUT)) { + debug("Disabling LCD\n"); + lcd_enabled = 0; + return; + } + + karo_fdt_move_fdt(); + + vm = getenv("video_mode"); + if (vm == NULL) { + debug("Disabling LCD\n"); + lcd_enabled = 0; + return; + } + if (karo_fdt_get_fb_mode(working_fdt, vm, &fb_mode) == 0) { + p = &fb_mode; + debug("Using video mode from FDT\n"); + vm += strlen(vm); + if (fb_mode.xres < panel_info.vl_col) + panel_info.vl_col = fb_mode.xres; + if (fb_mode.yres < panel_info.vl_row) + panel_info.vl_row = fb_mode.yres; + } + if (p->name != NULL) + debug("Trying compiled-in video modes\n"); + while (p->name != NULL) { + if (strcmp(p->name, vm) == 0) { + debug("Using video mode: '%s'\n", p->name); + vm += strlen(vm); + break; + } + p++; + } + if (*vm != '\0') + debug("Trying to decode video_mode: '%s'\n", vm); + while (*vm != '\0') { + if (*vm >= '0' && *vm <= '9') { + char *end; + + val = simple_strtoul(vm, &end, 0); + if (end > vm) { + if (!xres_set) { + if (val > panel_info.vl_col) + val = panel_info.vl_col; + p->xres = val; + panel_info.vl_col = val; + xres_set = 1; + } else if (!yres_set) { + if (val > panel_info.vl_row) + val = panel_info.vl_row; + p->yres = val; + panel_info.vl_row = val; + yres_set = 1; + } else if (!bpp_set) { + switch (val) { + case 32: + case 24: + if (pix_fmt == IPU_PIX_FMT_LVDS666) + pix_fmt = IPU_PIX_FMT_LVDS888; + /* fallthru */ + case 16: + case 8: + color_depth = val; + break; + + case 18: + if (pix_fmt == IPU_PIX_FMT_LVDS666) { + color_depth = val; + break; + } + /* fallthru */ + default: + printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n", + end - vm, vm, color_depth); + } + bpp_set = 1; + } else if (!refresh_set) { + refresh = val; + refresh_set = 1; + } + } + vm = end; + } + switch (*vm) { + case '@': + bpp_set = 1; + /* fallthru */ + case '-': + yres_set = 1; + /* fallthru */ + case 'x': + xres_set = 1; + /* fallthru */ + case 'M': + case 'R': + vm++; + break; + + default: + if (!pix_fmt) { + char *tmp; + + if (strncmp(vm, "LVDS", 4) == 0) { + pix_fmt = IPU_PIX_FMT_LVDS666; + di_clk_parent = DI_PCLK_LDB; + } else { + pix_fmt = IPU_PIX_FMT_RGB24; + } + tmp = strchr(vm, ':'); + if (tmp) + vm = tmp; + } + if (*vm != '\0') + vm++; + } + } + if (p->xres == 0 || p->yres == 0) { + printf("Invalid video mode: %s\n", getenv("video_mode")); + lcd_enabled = 0; + printf("Supported video modes are:"); + for (p = &tx6_fb_modes[0]; p->name != NULL; p++) { + printf(" %s", p->name); + } + printf("\n"); + return; + } + + p->pixclock = KHZ2PICOS(refresh * + (p->xres + p->left_margin + p->right_margin + p->hsync_len) * + (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) + / 1000); + debug("Pixel clock set to %lu.%03lu MHz\n", + PICOS2KHZ(p->pixclock) / 1000, + PICOS2KHZ(p->pixclock) % 1000); + + gpio_request_array(stk5_lcd_gpios, ARRAY_SIZE(stk5_lcd_gpios)); + imx_iomux_v3_setup_multiple_pads(stk5_lcd_pads, + ARRAY_SIZE(stk5_lcd_pads)); + + debug("Initializing FB driver\n"); + if (!pix_fmt) + pix_fmt = IPU_PIX_FMT_RGB24; + else if (pix_fmt == IPU_PIX_FMT_LVDS666) { + writel(0x01, IOMUXC_BASE_ADDR + 8); + } else if (pix_fmt == IPU_PIX_FMT_LVDS888) { + writel(0x21, IOMUXC_BASE_ADDR + 8); + } + if (pix_fmt != IPU_PIX_FMT_RGB24) { + struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + /* enable LDB & DI0 clock */ + writel(readl(&ccm_regs->CCGR3) | MXC_CCM_CCGR3_LDB_DI0_MASK | + MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK, + &ccm_regs->CCGR3); + } + + if (karo_load_splashimage(0) == 0) { + debug("Initializing LCD controller\n"); + ipuv3_fb_init(p, 0, pix_fmt, di_clk_parent, di_clk_rate, -1); + } else { + debug("Skipping initialization of LCD controller\n"); + } +} +#else +#define lcd_enabled 0 +#endif /* CONFIG_LCD */ + +static void stk5_board_init(void) +{ + gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios)); + imx_iomux_v3_setup_multiple_pads(stk5_pads, ARRAY_SIZE(stk5_pads)); +} + +static void stk5v3_board_init(void) +{ + stk5_board_init(); +} + +static void stk5v5_board_init(void) +{ + stk5_board_init(); + + gpio_request_one(IMX_GPIO_NR(4, 21), GPIOF_OUTPUT_INIT_HIGH, + "Flexcan Transceiver"); + imx_iomux_v3_setup_pad(MX6_PAD_DISP0_DAT0__GPIO_4_21); +} + +static void tx6qdl_set_cpu_clock(void) +{ + unsigned long cpu_clk = getenv_ulong("cpu_clk", 10, 0); + + if (tstc() || (wrsr & WRSR_TOUT)) + return; + + if (cpu_clk == 0 || cpu_clk == mxc_get_clock(MXC_ARM_CLK) / 1000000) + return; + + if (mxc_set_clock(CONFIG_SYS_MX6_HCLK, cpu_clk, MXC_ARM_CLK) == 0) { + cpu_clk = mxc_get_clock(MXC_ARM_CLK); + printf("CPU clock set to %lu.%03lu MHz\n", + cpu_clk / 1000000, cpu_clk / 1000 % 1000); + } else { + printf("Failed to set CPU clock to %lu MHz\n", cpu_clk); + } +} + +static void tx6_init_mac(void) +{ + u8 mac[ETH_ALEN]; + + imx_get_mac_from_fuse(-1, mac); + if (!is_valid_ether_addr(mac)) { + printf("No valid MAC address programmed\n"); + return; + } + + eth_setenv_enetaddr("ethaddr", mac); + printf("MAC addr from fuse: %pM\n", mac); +} + +int board_late_init(void) +{ + int ret = 0; + const char *baseboard; + + tx6qdl_set_cpu_clock(); + karo_fdt_move_fdt(); + + baseboard = getenv("baseboard"); + if (!baseboard) + goto exit; + + printf("Baseboard: %s\n", baseboard); + + if (strncmp(baseboard, "stk5", 4) == 0) { + if ((strlen(baseboard) == 4) || + strcmp(baseboard, "stk5-v3") == 0) { + stk5v3_board_init(); + } else if (strcmp(baseboard, "stk5-v5") == 0) { + stk5v5_board_init(); + } else { + printf("WARNING: Unsupported STK5 board rev.: %s\n", + baseboard + 4); + } + } else { + printf("WARNING: Unsupported baseboard: '%s'\n", + baseboard); + ret = -EINVAL; + } + +exit: + tx6_init_mac(); + + gpio_set_value(TX6_RESET_OUT_GPIO, 1); + return ret; +} + +int checkboard(void) +{ + u32 cpurev = get_cpu_rev(); + int cpu_variant = (cpurev >> 12) & 0xff; + + tx6qdl_print_cpuinfo(); + + printf("Board: Ka-Ro TX6%c-%dxx%d\n", + cpu_variant == MXC_CPU_MX6Q ? 'Q' : 'U', + cpu_variant == MXC_CPU_MX6Q ? 1 : 8, + 1 - PHYS_SDRAM_1_WIDTH / 64); + + return 0; +} + +#ifdef CONFIG_SERIAL_TAG +void get_board_serial(struct tag_serialnr *serialnr) +{ + struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank0_regs *fuse = (void *)ocotp->bank[0].fuse_regs; + + serialnr->low = readl(&fuse->cfg0); + serialnr->high = readl(&fuse->cfg1); +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_FDT_FIXUP_PARTITIONS +#include +#include +struct node_info nodes[] = { + { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, +}; + +#else +#define fdt_fixup_mtdparts(b,n,c) do { } while (0) +#endif + +static void tx6qdl_fixup_flexcan(void *blob) +{ + const char *baseboard = getenv("baseboard"); + + if (baseboard && strcmp(baseboard, "stk5-v5") == 0) + return; + + karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x02090000, "transceiver-switch"); + karo_fdt_del_prop(blob, "fsl,p1010-flexcan", 0x02094000, "transceiver-switch"); +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + fdt_fixup_ethernet(blob); + + karo_fdt_fixup_touchpanel(blob); + karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy"); + tx6qdl_fixup_flexcan(blob); + karo_fdt_update_fb_mode(blob, getenv("video_mode")); +} +#endif diff --git a/board/karo/tx6/u-boot.lds b/board/karo/tx6/u-boot.lds new file mode 100644 index 0000000000..832cfb77d9 --- /dev/null +++ b/board/karo/tx6/u-boot.lds @@ -0,0 +1,100 @@ +/* + * (C) Copyright 2012 Lothar Waßmann + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + .text : + { + *(.__image_copy_start) + CPUDIR/start.o (.text*) + . = 0x400; + KEEP(board/karo/tx6/lowlevel_init.o (.text*)) + *(.text*) + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { + *(.data*) + } + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + .image_copy_end : + { + *(.__image_copy_end) + } + + .rel_dyn_start : + { + *(.__rel_dyn_start) + } + + .rel.dyn : + { + *(.rel*) + } + + .rel_dyn_end : + { + *(.__rel_dyn_end) + } + + _end = .; + +/* + * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c + * __bss_base and __bss_limit are for linker only (overlay ordering) + */ + + .bss_start __rel_dyn_start (OVERLAY) : { + KEEP(*(.__bss_start)); + __bss_base = .; + } + + .bss __bss_base (OVERLAY) : { + *(.bss*) + . = ALIGN(4); + __bss_limit = .; + } + .bss_end __bss_limit (OVERLAY) : { + KEEP(*(.__bss_end)); + } + + /DISCARD/ : { *(.bss*) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynsym*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.hash*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +} diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index 7138d739e4..9ea5dd3a3b 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -24,7 +24,7 @@ #include #include #include -#include +//#include #include "board.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/boards.cfg b/boards.cfg index 944ed4cf05..9cbce53a40 100644 --- a/boards.cfg +++ b/boards.cfg @@ -194,6 +194,9 @@ devkit3250 arm arm926ejs devkit3250 timll jadecpu arm arm926ejs jadecpu syteco mb86r0x mx25pdk arm arm926ejs mx25pdk freescale mx25 mx25pdk:IMX_CONFIG=board/freescale/mx25pdk/imximage.cfg tx25 arm arm926ejs tx25 karo mx25 +tx28-40x1 arm arm926ejs tx28 karo mxs tx28:TX28,SDRAM_SIZE=SZ_128M +tx28-40x2 arm arm926ejs tx28 karo mxs tx28:TX28,SDRAM_SIZE=SZ_256M +tx28-41x0 arm arm926ejs tx28 karo mxs tx28:TX28_S,SDRAM_SIZE=SZ_64M zmx25 arm arm926ejs zmx25 syteco mx25 imx27lite arm arm926ejs imx27lite logicpd mx27 magnesium arm arm926ejs imx27lite logicpd mx27 @@ -254,6 +257,8 @@ pcm051 arm armv7 pcm051 phytec sama5d3xek_mmc arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_MMC sama5d3xek_nandflash arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_NANDFLASH sama5d3xek_spiflash arm armv7 sama5d3xek atmel at91 sama5d3xek:SAMA5D3,SYS_USE_SERIALFLASH +tx48 arm armv7 tx48 karo am33xx tx48:SYS_MPU_CLK=720,SYS_DDR_CLK=400 +tx48-dt arm armv7 tx48 karo am33xx tx48:OF_LIBFDT,SYS_MPU_CLK=720,SYS_DDR_CLK=400 highbank arm armv7 highbank - highbank m53evk arm armv7 m53evk denx mx5 m53evk:IMX_CONFIG=board/denx/m53evk/imximage.cfg mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg @@ -265,7 +270,24 @@ mx53loco arm armv7 mx53loco freesca mx53smd arm armv7 mx53smd freescale mx5 mx53smd:IMX_CONFIG=board/freescale/mx53smd/imximage.cfg ima3-mx53 arm armv7 ima3-mx53 esg mx5 ima3-mx53:IMX_CONFIG=board/esg/ima3-mx53/imximage.cfg vision2 arm armv7 vision2 ttcontrol mx5 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg -cgtqmx6qeval arm armv7 cgtqmx6eval congatec mx6 cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q +cgtqmx6qeval arm armv7 cgtqmx6eval congatec mx6 cgtqmx6eval:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q +tx51-6xx0 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=600,NR_DRAM_BANKS=1,SYS_SDRAM_CLK=166 +tx51-6xx1 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=600,NR_DRAM_BANKS=2,SYS_SDRAM_CLK=200 +tx51-6xx2 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=600,NR_DRAM_BANKS=2,SYS_SDRAM_CLK=166 +tx51-8xx0 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=800,NR_DRAM_BANKS=1,SYS_SDRAM_CLK=166 +tx51-8xx1 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=800,NR_DRAM_BANKS=2,SYS_SDRAM_CLK=200 +tx51-8xx2 arm armv7 tx51 karo mx5 tx51:SYS_CPU_CLK=800,NR_DRAM_BANKS=2,SYS_SDRAM_CLK=166 +tx53-xx30 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=1 +tx53-xx31 arm armv7 tx53 karo mx5 tx53:NR_DRAM_BANKS=2 +tx6u-8xx0 arm armv7 tx6 karo mx6 tx6:MX6DL +tx6u-8xx0_mfg arm armv7 tx6 karo mx6 tx6:MX6DL,MFG +tx6u-8xx0_noenv arm armv7 tx6 karo mx6 tx6:MX6DL,ENV_IS_NOWHERE +tx6u-8xx1 arm armv7 tx6 karo mx6 tx6:MX6DL,SYS_SDRAM_BUS_WIDTH=32 +tx6u-8xx1_mfg arm armv7 tx6 karo mx6 tx6:MX6DL,SYS_SDRAM_BUS_WIDTH=32,MFG +tx6u-8xx1_noenv arm armv7 tx6 karo mx6 tx6:MX6DL,SYS_SDRAM_BUS_WIDTH=32,ENV_IS_NOWHERE +tx6q-1xx0 arm armv7 tx6 karo mx6 tx6:MX6Q +tx6q-1xx0_mfg arm armv7 tx6 karo mx6 tx6:MX6Q,MFG +tx6q-1xx0_noenv arm armv7 tx6 karo mx6 tx6:MX6Q,ENV_IS_NOWHERE mx6qarm2 arm armv7 mx6qarm2 freescale mx6 mx6qarm2:IMX_CONFIG=board/freescale/mx6qarm2/imximage.cfg mx6qsabreauto arm armv7 mx6qsabreauto freescale mx6 mx6qsabreauto:IMX_CONFIG=board/freescale/mx6qsabreauto/imximage.cfg,MX6Q mx6qsabrelite arm armv7 mx6qsabrelite freescale mx6 mx6qsabrelite:IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg diff --git a/common/Makefile b/common/Makefile index 288690bca5..1ced298fe2 100644 --- a/common/Makefile +++ b/common/Makefile @@ -58,6 +58,7 @@ COBJS-$(CONFIG_CMD_SOURCE) += cmd_source.o COBJS-$(CONFIG_CMD_BDI) += cmd_bdinfo.o COBJS-$(CONFIG_CMD_BEDBUG) += bedbug.o cmd_bedbug.o COBJS-$(CONFIG_CMD_BMP) += cmd_bmp.o +COBJS-$(CONFIG_CMD_BOOTCE) += cmd_bootce.o COBJS-$(CONFIG_CMD_BOOTMENU) += cmd_bootmenu.o COBJS-$(CONFIG_CMD_BOOTLDR) += cmd_bootldr.o COBJS-$(CONFIG_CMD_BOOTSTAGE) += cmd_bootstage.o @@ -97,6 +98,7 @@ COBJS-$(CONFIG_CMD_FS_GENERIC) += cmd_fs.o COBJS-$(CONFIG_CMD_FUSE) += cmd_fuse.o COBJS-$(CONFIG_CMD_GETTIME) += cmd_gettime.o COBJS-$(CONFIG_CMD_GPIO) += cmd_gpio.o +COBJS-$(CONFIG_CMD_IIM) += cmd_iim.o COBJS-$(CONFIG_CMD_I2C) += cmd_i2c.o COBJS-$(CONFIG_CMD_HASH) += cmd_hash.o COBJS-$(CONFIG_CMD_IDE) += cmd_ide.o @@ -133,6 +135,7 @@ COBJS-$(CONFIG_CMD_NET) += cmd_net.o COBJS-$(CONFIG_CMD_ONENAND) += cmd_onenand.o COBJS-$(CONFIG_CMD_OTP) += cmd_otp.o COBJS-$(CONFIG_CMD_PART) += cmd_part.o +COBJS-$(CONFIG_CMD_PATA) += cmd_pata.o ifdef CONFIG_PCI COBJS-$(CONFIG_CMD_PCI) += cmd_pci.o endif diff --git a/common/cmd_bootce.c b/common/cmd_bootce.c new file mode 100644 index 0000000000..002acf905b --- /dev/null +++ b/common/cmd_bootce.c @@ -0,0 +1,1063 @@ +/* + * Copyright (C) 2012 Lothar Waßmann + * based on: code from RedBoot (C) Uwe Steinkohl + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define WINCE_VRAM_BASE 0x80000000 +#define CE_FIX_ADDRESS(a) ((void *)((a) - WINCE_VRAM_BASE + CONFIG_SYS_SDRAM_BASE)) + +#ifndef INT_MAX +#define INT_MAX ((int)(~0U >> 1)) +#endif + +/* Bin image parse states */ +#define CE_PS_RTI_ADDR 0 +#define CE_PS_RTI_LEN 1 +#define CE_PS_E_ADDR 2 +#define CE_PS_E_LEN 3 +#define CE_PS_E_CHKSUM 4 +#define CE_PS_E_DATA 5 + +#define CE_MIN(a, b) (((a) < (b)) ? (a) : (b)) +#define CE_MAX(a, b) (((a) > (b)) ? (a) : (b)) + +static ce_bin __attribute__ ((aligned (32))) g_bin; +static ce_net __attribute__ ((aligned (32))) g_net; +static IPaddr_t server_ip; + +static void ce_init_bin(ce_bin *bin, unsigned char *dataBuffer) +{ + memset(bin, 0, sizeof(*bin)); + + bin->data = dataBuffer; + bin->parseState = CE_PS_RTI_ADDR; + bin->parsePtr = (unsigned char *)bin; +} + +static int ce_is_bin_image(void *image, int imglen) +{ + if (imglen < CE_BIN_SIGN_LEN) { + return 0; + } + + return memcmp(image, CE_BIN_SIGN, CE_BIN_SIGN_LEN) == 0; +} + +static const struct ce_magic { + char magic[8]; + size_t size; + ce_std_driver_globals drv_glb; +} ce_magic_template = { + .magic = "KARO_CE6", + .size = sizeof(ce_std_driver_globals), + .drv_glb = { + .header = { + .signature = STD_DRV_GLB_SIGNATURE, + .oalVersion = 1, + .bspVersion = 2, + }, + }, +}; + +#ifdef DEBUG +static void __attribute__((unused)) ce_dump_block(void *ptr, int length) +{ + char *p = ptr; + int i; + int j; + + for (i = 0; i < length; i++) { + if (!(i % 16)) { + printf("\n%p: ", ptr + i); + } + + printf("%02x ", p[i]); + if (!((i + 1) % 16)){ + printf(" "); + for (j = i - 15; j <= i; j++){ + if((p[j] > 0x1f) && (p[j] < 0x7f)) { + printf("%c", p[j]); + } else { + printf("."); + } + } + } + } + printf("\n"); +} +#else +static inline void ce_dump_block(void *ptr, int length) +{ +} +#endif + +static void ce_setup_std_drv_globals(ce_std_driver_globals *std_drv_glb) +{ + char *mtdparts = getenv("mtdparts"); + size_t max_len = ALIGN((unsigned long)std_drv_glb, SZ_4K) - + (unsigned long)&std_drv_glb->mtdparts; + + if (eth_get_dev()) { + memcpy(&std_drv_glb->kitl.mac, eth_get_dev()->enetaddr, + sizeof(std_drv_glb->kitl.mac)); + } + snprintf(std_drv_glb->deviceId, sizeof(std_drv_glb->deviceId), + "Triton%02X", eth_get_dev()->enetaddr[5]); + + NetCopyIP(&std_drv_glb->kitl.ipAddress, &NetOurIP); + std_drv_glb->kitl.ipMask = getenv_IPaddr("netmask"); + std_drv_glb->kitl.ipRoute = getenv_IPaddr("gatewayip"); + + if (mtdparts) { + strncpy(std_drv_glb->mtdparts, mtdparts, max_len); + std_drv_glb->mtdparts[max_len - 1] = '\0'; + } else { + printf("Failed to get mtdparts environment variable\n"); + } +} + +static void ce_prepare_run_bin(ce_bin *bin) +{ + ce_driver_globals *drv_glb; + struct ce_magic *ce_magic = (void *)CONFIG_SYS_SDRAM_BASE + 0x160; + ce_std_driver_globals *std_drv_glb = &ce_magic->drv_glb; + + /* Clear os RAM area (if needed) */ + if (bin->edbgConfig.flags & EDBG_FL_CLEANBOOT) { + debug("cleaning memory from %p to %p\n", + bin->eRamStart, bin->eRamStart + bin->eRamLen); + + printf("Preparing clean boot ... "); + memset(bin->eRamStart, 0, bin->eRamLen); + printf("ok\n"); + } + + /* Prepare driver globals (if needed) */ + if (bin->eDrvGlb) { + debug("Copying CE MAGIC from %p to %p..%p\n", + &ce_magic_template, ce_magic, + (void *)ce_magic + sizeof(*ce_magic) - 1); + memcpy(ce_magic, &ce_magic_template, sizeof(*ce_magic)); + + ce_setup_std_drv_globals(std_drv_glb); + ce_magic->size = sizeof(*std_drv_glb) + + strlen(std_drv_glb->mtdparts) + 1; + ce_dump_block(ce_magic, offsetof(struct ce_magic, drv_glb) + + ce_magic->size); + + drv_glb = bin->eDrvGlb; + memset(drv_glb, 0, sizeof(*drv_glb)); + + drv_glb->signature = DRV_GLB_SIGNATURE; + + /* Local ethernet MAC address */ + memcpy(drv_glb->macAddr, std_drv_glb->kitl.mac, + sizeof(drv_glb->macAddr)); + debug("got MAC address %pM from environment\n", + drv_glb->macAddr); + + /* Local IP address */ + drv_glb->ipAddr = getenv_IPaddr("ipaddr"); + + /* Subnet mask */ + drv_glb->ipMask = getenv_IPaddr("netmask"); + + /* Gateway config */ + drv_glb->ipGate = getenv_IPaddr("gatewayip"); +#ifdef DEBUG + debug("got IP address %pI4 from environment\n", + &drv_glb->ipAddr); + debug("got IP mask %pI4 from environment\n", + &drv_glb->ipMask); + debug("got gateway address %pI4 from environment\n", + &drv_glb->ipGate); +#endif + /* EDBG services config */ + memcpy(&drv_glb->edbgConfig, &bin->edbgConfig, + sizeof(bin->edbgConfig)); + } + + /* + * Make sure, all the above makes it into SDRAM because + * WinCE switches the cache & MMU off, obviously without + * flushing it first! + */ + flush_dcache_all(); +} + +static int ce_lookup_ep_bin(ce_bin *bin) +{ + ce_rom_hdr *header; + ce_toc_entry *tentry; + e32_rom *e32; + unsigned int i; + uint32_t *sig = (uint32_t *)(bin->rtiPhysAddr + ROM_SIGNATURE_OFFSET); + + debug("Looking for TOC signature at %p\n", sig); + + /* Check image Table Of Contents (TOC) signature */ + if (*sig != ROM_SIGNATURE) { + printf("Error: Did not find image TOC signature!\n"); + printf("Expected %08x at address %p; found %08x instead\n", + ROM_SIGNATURE, sig, *sig); + return 0; + } + + /* Lookup entry point */ + header = CE_FIX_ADDRESS(*(unsigned int *)(bin->rtiPhysAddr + + ROM_SIGNATURE_OFFSET + + sizeof(unsigned int))); + tentry = (ce_toc_entry *)(header + 1); + + for (i = 0; i < header->nummods; i++) { + // Look for 'nk.exe' module + if (strcmp(CE_FIX_ADDRESS(tentry[i].fileName), "nk.exe") == 0) { + // Save entry point and RAM addresses + + e32 = CE_FIX_ADDRESS(tentry[i].e32Offset); + + bin->eEntryPoint = CE_FIX_ADDRESS(tentry[i].loadOffset) + + e32->e32_entryrva; + bin->eRamStart = CE_FIX_ADDRESS(header->ramStart); + bin->eRamLen = header->ramEnd - header->ramStart; + // Save driver_globals address + // Must follow RAM section in CE config.bib file + // + // eg. + // + // RAM 80900000 03200000 RAM + // DRV_GLB 83B00000 00001000 RESERVED + // + bin->eDrvGlb = CE_FIX_ADDRESS(header->ramEnd); + return 1; + } + } + + // Error: Did not find 'nk.exe' module + return 0; +} + +static int ce_parse_bin(ce_bin *bin) +{ + unsigned char *pbData = bin->data; + int len = bin->dataLen; + int copyLen; + + debug("starting ce image parsing:\n\tbin->binLen: 0x%08X\n", bin->binLen); + + if (len) { + if (bin->binLen == 0) { + // Check for the .BIN signature first + if (!ce_is_bin_image(pbData, len)) { + printf("Error: Invalid or corrupted .BIN image!\n"); + return CE_PR_ERROR; + } + + printf("Loading Windows CE .BIN image ...\n"); + // Skip signature + len -= CE_BIN_SIGN_LEN; + pbData += CE_BIN_SIGN_LEN; + } + + while (len) { + switch (bin->parseState) { + case CE_PS_RTI_ADDR: + case CE_PS_RTI_LEN: + case CE_PS_E_ADDR: + case CE_PS_E_LEN: + case CE_PS_E_CHKSUM: + copyLen = CE_MIN(sizeof(unsigned int) - bin->parseLen, len); + memcpy(&bin->parsePtr[bin->parseLen], pbData, copyLen); + + bin->parseLen += copyLen; + len -= copyLen; + pbData += copyLen; + + if (bin->parseLen == sizeof(unsigned int)) { + if (bin->parseState == CE_PS_RTI_ADDR) + bin->rtiPhysAddr = CE_FIX_ADDRESS(bin->rtiPhysAddr); + else if (bin->parseState == CE_PS_E_ADDR && + bin->ePhysAddr) + bin->ePhysAddr = CE_FIX_ADDRESS(bin->ePhysAddr); + + bin->parseState++; + bin->parseLen = 0; + bin->parsePtr += sizeof(unsigned int); + + if (bin->parseState == CE_PS_E_DATA) { + if (bin->ePhysAddr) { + bin->parsePtr = bin->ePhysAddr; + bin->parseChkSum = 0; + } else { + /* EOF */ + len = 0; + bin->endOfBin = 1; + } + } + } + break; + + case CE_PS_E_DATA: + debug("ePhysAddr=%p physlen=%08x parselen=%08x\n", + bin->ePhysAddr, bin->ePhysLen, bin->parseLen); + if (bin->ePhysAddr) { + copyLen = CE_MIN(bin->ePhysLen - bin->parseLen, len); + bin->parseLen += copyLen; + len -= copyLen; + + while (copyLen--) { + bin->parseChkSum += *pbData; + *bin->parsePtr++ = *pbData++; + } + + if (bin->parseLen == bin->ePhysLen) { + printf("Section [%02d]: address %p, size 0x%08X, checksum %s\n", + bin->section, + bin->ePhysAddr, + bin->ePhysLen, + (bin->eChkSum == bin->parseChkSum) ? "ok" : "fail"); + + if (bin->eChkSum != bin->parseChkSum) { + printf("Error: Checksum error, corrupted .BIN file!\n"); + printf("checksum calculated: 0x%08x from file: 0x%08x\n", + bin->parseChkSum, bin->eChkSum); + bin->binLen = 0; + return CE_PR_ERROR; + } + + bin->section++; + bin->parseState = CE_PS_E_ADDR; + bin->parseLen = 0; + bin->parsePtr = (unsigned char *)&bin->ePhysAddr; + } + } else { + bin->parseLen = 0; + bin->endOfBin = 1; + len = 0; + } + break; + } + } + } + + if (bin->endOfBin) { + if (!ce_lookup_ep_bin(bin)) { + printf("Error: entry point not found!\n"); + bin->binLen = 0; + return CE_PR_ERROR; + } + + printf("Entry point: %p, address range: %p-%p\n", + bin->eEntryPoint, + bin->rtiPhysAddr, + bin->rtiPhysAddr + bin->rtiPhysLen); + + return CE_PR_EOF; + } + + /* Need more data */ + bin->binLen += bin->dataLen; + return CE_PR_MORE; +} + +static int ce_bin_load(void *image, int imglen) +{ + ce_init_bin(&g_bin, image); + g_bin.dataLen = imglen; + if (ce_parse_bin(&g_bin) == CE_PR_EOF) { + ce_prepare_run_bin(&g_bin); + return 1; + } + + return 0; +} + +static void ce_run_bin(void (*entry)(void)) +{ + printf("Launching Windows CE ...\n"); +#ifdef TEST_LAUNCH +return; +#endif + entry(); +} + +static int do_bootce(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + void *addr; + size_t image_size; + + if (argc > 1) { + addr = (void *)simple_strtoul(argv[1], NULL, 16); + image_size = INT_MAX; /* actually we do not know the image size */ + } else if (getenv("fileaddr") != NULL) { + addr = (void *)getenv_ulong("fileaddr", 16, 0); + image_size = getenv_ulong("filesize", 16, INT_MAX); + } else { + return CMD_RET_USAGE; + } + + printf ("## Booting Windows CE Image from address %p ...\n", addr); + + /* check if there is a valid windows CE image */ + if (ce_is_bin_image(addr, image_size)) { + if (!ce_bin_load(addr, image_size)) { + /* Ops! Corrupted .BIN image! */ + /* Handle error here ... */ + printf("corrupted .BIN image !!!\n"); + return CMD_RET_FAILURE; + } + if (getenv_yesno("autostart") != 1) { + /* + * just use bootce to load the image to SDRAM; + * Do not start it automatically. + */ + setenv_addr("fileaddr", g_bin.eEntryPoint); + return CMD_RET_SUCCESS; + } + ce_run_bin(g_bin.eEntryPoint); /* start the image */ + } else { + printf("Image does not seem to be a valid Windows CE image!\n"); + return CMD_RET_FAILURE; + } + return CMD_RET_FAILURE; /* never reached - just to keep compiler happy */ +} +U_BOOT_CMD( + bootce, 2, 0, do_bootce, + "Boot a Windows CE image from RAM\n", + "[addr]\n" + "\taddr\t\tboot image from address addr (default ${fileaddr})\n" +); + +static int ce_nand_load(ce_bin *bin, loff_t *offset, void *buf, size_t max_len) +{ + int ret; + size_t len = max_len; + nand_info_t *nand = &nand_info[0]; + + while (nand_block_isbad(nand, *offset & ~(max_len - 1))) { + printf("Skipping bad block 0x%08llx\n", + *offset & ~(max_len - 1)); + *offset += max_len; + if (*offset + max_len > nand->size) + return -EINVAL; + } + + ret = nand_read(nand, *offset, &len, buf); + if (ret < 0) + return ret; + + bin->dataLen = len; + return len; +} + +static int do_nbootce(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + int ret; + struct mtd_device *dev; + struct part_info *part_info; + u8 part_num; + loff_t offset; + char *end; + void *buffer; + size_t bufsize = nand_info[0].erasesize, len; + + if (argc < 2 || argc > 3) + return CMD_RET_USAGE; + + ret = mtdparts_init(); + if (ret) + return CMD_RET_FAILURE; + + offset = simple_strtoul(argv[1], &end, 16); + if (*end != '\0') { + ret = find_dev_and_part(argv[1], &dev, &part_num, + &part_info); + if (ret != 0) { + printf("Partition '%s' not found\n", argv[1]); + return CMD_RET_FAILURE; + } + offset = part_info->offset; + printf ("## Booting Windows CE Image from NAND partition %s at offset %08llx\n", + argv[1], offset); + } else { + printf ("## Booting Windows CE Image from NAND offset %08llx\n", + offset); + } + + buffer = malloc(bufsize); + if (buffer == NULL) { + printf("Failed to allocate %u byte buffer\n", bufsize); + return CMD_RET_FAILURE; + } + + ce_init_bin(&g_bin, buffer); + + ret = ce_nand_load(&g_bin, &offset, buffer, bufsize); + if (ret < 0) { + printf("Failed to read NAND: %d\n", ret); + goto err; + } + len = ret; + /* check if there is a valid windows CE image header */ + if (ce_is_bin_image(buffer, len)) { + do { + ret = ce_parse_bin(&g_bin); + switch (ret) { + case CE_PR_MORE: + { + if (ctrlc()) { + printf("NBOOTCE - canceled by user\n"); + goto err; + } + offset += len; + len = ce_nand_load(&g_bin, &offset, buffer, + bufsize); + if (len < 0) { + printf("Nand read error: %d\n", len); + ret = len; + goto err; + } + } + break; + + case CE_PR_EOF: + case CE_PR_ERROR: + break; + } + } while (ret == CE_PR_MORE); + if (ret != CE_PR_EOF) + return CMD_RET_FAILURE; + + free(buffer); + if (getenv_yesno("autostart") != 1) { + /* + * just use bootce to load the image to SDRAM; + * Do not start it automatically. + */ + setenv_addr("fileaddr", g_bin.eEntryPoint); + return CMD_RET_SUCCESS; + } + ce_run_bin(g_bin.eEntryPoint); /* start the image */ + } else { + printf("Image does not seem to be a valid Windows CE image!\n"); + } +err: + free(buffer); + return CMD_RET_FAILURE; +} +U_BOOT_CMD( + nbootce, 2, 0, do_nbootce, + "Boot a Windows CE image from NAND\n", + "off|partitition\n" + "\toff\t\t- flash offset (hex)\n" + "\tpartition\t- partition name\n" +); + +static int ce_send_write_ack(ce_net *net) +{ + int ret; + unsigned short wdata[2]; + int retries = 0; + + wdata[0] = htons(EDBG_CMD_WRITE_ACK); + wdata[1] = htons(net->blockNum); + net->dataLen = sizeof(wdata); + memcpy(net->data, wdata, net->dataLen); + + do { + ret = bootme_send_frame(net->data, net->dataLen); + if (ret) { + printf("Failed to send write ack %d; retries=%d\n", + ret, retries); + } + } while (ret != 0 && retries-- > 0); + return ret; +} + +static enum bootme_state ce_process_download(ce_net *net, ce_bin *bin) +{ + int ret = net->state; + + if (net->dataLen >= 4) { + unsigned short command; + unsigned short blknum; + + memcpy(&command, net->data, sizeof(command)); + command = ntohs(command); + debug("command found: 0x%04X\n", command); + + if (net->state == BOOTME_DOWNLOAD) { + unsigned short nxt = net->blockNum + 1; + + memcpy(&blknum, &net->data[2], sizeof(blknum)); + blknum = ntohs(blknum); + if (blknum == nxt) { + net->blockNum = blknum; + } else { + int rc = ce_send_write_ack(net); + + printf("Dropping out of sequence packet with ID %d (expected %d)\n", + blknum, nxt); + if (rc != 0) + return rc; + + return ret; + } + } + + switch (command) { + case EDBG_CMD_WRITE_REQ: + if (net->state == BOOTME_INIT) { + // Check file name for WRITE request + // CE EShell uses "boot.bin" file name + if (strncmp((char *)&net->data[2], + "boot.bin", 8) == 0) { + // Some diag output + if (net->verbose) { + printf("Locked Down download link, IP: %pI4\n", + &NetServerIP); + printf("Sending BOOTME request [%d] to %pI4\n", + net->seqNum, &NetServerIP); + } + + // Lock down EShell download link + ret = BOOTME_DOWNLOAD; + } else { + // Unknown link + printf("Unknown link\n"); + } + + if (ret == BOOTME_DOWNLOAD) { + int rc = ce_send_write_ack(net); + if (rc != 0) + return rc; + } + } + break; + + case EDBG_CMD_WRITE: + /* Fixup data len */ + bin->data = &net->data[4]; + bin->dataLen = net->dataLen - 4; + ret = ce_parse_bin(bin); + if (ret != CE_PR_ERROR) { + int rc = ce_send_write_ack(net); + if (rc) + return rc; + if (ret == CE_PR_EOF) + ret = BOOTME_DONE; + } else { + ret = BOOTME_ERROR; + } + break; + + case EDBG_CMD_READ_REQ: + printf("Ignoring EDBG_CMD_READ_REQ\n"); + /* Read requests are not supported + * Do nothing ... + */ + break; + + case EDBG_CMD_ERROR: + printf("Error: unknown error on the host side\n"); + + bin->binLen = 0; + ret = BOOTME_ERROR; + break; + + default: + printf("unknown command 0x%04X\n", command); + net->state = BOOTME_ERROR; + } + } + return ret; +} + +static enum bootme_state ce_process_edbg(ce_net *net, ce_bin *bin) +{ + enum bootme_state ret = net->state; + eth_dbg_hdr header; + + if (net->dataLen < sizeof(header)) { + /* Bad packet */ + printf("Invalid packet size %u\n", net->dataLen); + net->dataLen = 0; + return ret; + } + memcpy(&header, net->data, sizeof(header)); + if (header.id != EDBG_ID) { + /* Bad packet */ + printf("Bad EDBG ID %08x\n", header.id); + net->dataLen = 0; + return ret; + } + + if (header.service != EDBG_SVC_ADMIN) { + /* Unknown service */ + printf("Bad EDBG service %02x\n", header.service); + net->dataLen = 0; + return ret; + } + + if (net->state == BOOTME_INIT) { + /* Some diag output */ + if (net->verbose) { + printf("Locked Down EDBG service link, IP: %pI4\n", + &NetServerIP); + } + + /* Lock down EDBG link */ + net->state = BOOTME_DEBUG; + } + +debug("%s@%d\n", __func__, __LINE__); + switch (header.cmd) { + case EDBG_CMD_JUMPIMG: +debug("%s@%d\n", __func__, __LINE__); + net->gotJumpingRequest = 1; + + if (net->verbose) { + printf("Received JUMPING command\n"); + } + /* Just pass through and copy CONFIG structure */ + case EDBG_CMD_OS_CONFIG: +debug("%s@%d\n", __func__, __LINE__); + /* Copy config structure */ + memcpy(&bin->edbgConfig, header.data, + sizeof(edbg_os_config_data)); + if (net->verbose) { + printf("Received CONFIG command\n"); + if (bin->edbgConfig.flags & EDBG_FL_DBGMSG) { + printf("--> Enabling DBGMSG service, IP: %pI4, port: %d\n", + &bin->edbgConfig.dbgMsgIPAddr, + ntohs(bin->edbgConfig.dbgMsgPort)); + } + + if (bin->edbgConfig.flags & EDBG_FL_PPSH) { + printf("--> Enabling PPSH service, IP: %pI4, port: %d\n", + &bin->edbgConfig.ppshIPAddr, + ntohs(bin->edbgConfig.ppshPort)); + } + + if (bin->edbgConfig.flags & EDBG_FL_KDBG) { + printf("--> Enabling KDBG service, IP: %pI4, port: %d\n", + &bin->edbgConfig.kdbgIPAddr, + ntohs(bin->edbgConfig.kdbgPort)); + } + + if (bin->edbgConfig.flags & EDBG_FL_CLEANBOOT) { + printf("--> Force clean boot\n"); + } + } + ret = BOOTME_DEBUG; + break; + + default: + if (net->verbose) { + printf("Received unknown command: %08X\n", header.cmd); + } + return BOOTME_ERROR; + } + + /* Respond with ack */ + header.flags = EDBG_FL_FROM_DEV | EDBG_FL_ACK; + net->dataLen = EDBG_DATA_OFFSET; +debug("%s@%d: sending packet %p len %u\n", __func__, __LINE__, + net->data, net->dataLen); + bootme_send_frame(net->data, net->dataLen); + return ret; +} + +static enum bootme_state ce_edbg_handler(const void *buf, size_t len) +{ + if (len == 0) + return BOOTME_DONE; + + g_net.data = (void *)buf; + g_net.dataLen = len; + + return ce_process_edbg(&g_net, &g_bin); +} + +static void ce_init_edbg_link(ce_net *net) +{ + /* Initialize EDBG link for commands */ + net->state = BOOTME_INIT; +} + +static enum bootme_state ce_download_handler(const void *buf, size_t len) +{ + g_net.data = (void *)buf; + g_net.dataLen = len; + + g_net.state = ce_process_download(&g_net, &g_bin); + return g_net.state; +} + +static int ce_send_bootme(ce_net *net) +{ + eth_dbg_hdr *header; + edbg_bootme_data *data; + unsigned char txbuf[PKTSIZE_ALIGN]; +#ifdef DEBUG + int i; + unsigned char *pkt; +#endif + /* Fill out BOOTME packet */ + net->data = txbuf; + + memset(net->data, 0, PKTSIZE); + header = (eth_dbg_hdr *)net->data; + data = (edbg_bootme_data *)header->data; + + header->id = EDBG_ID; + header->service = EDBG_SVC_ADMIN; + header->flags = EDBG_FL_FROM_DEV; + header->seqNum = net->seqNum++; + header->cmd = EDBG_CMD_BOOTME; + + data->versionMajor = 0; + data->versionMinor = 0; + data->cpuId = EDBG_CPU_TYPE_ARM; + data->bootmeVer = EDBG_CURRENT_BOOTME_VERSION; + data->bootFlags = 0; + data->downloadPort = 0; + data->svcPort = 0; + + /* MAC address from environment*/ + if (!eth_getenv_enetaddr("ethaddr", data->macAddr)) { + printf("'ethaddr' is not set or invalid\n"); + memset(data->macAddr, 0, sizeof(data->macAddr)); + } + + /* IP address from active config */ + NetCopyIP(&data->ipAddr, &NetOurIP); + + // Device name string (NULL terminated). Should include + // platform and number based on Ether address (e.g. Odo42, CEPCLS2346, etc) + + // We will use lower MAC address segment to create device name + // eg. MAC '00-0C-C6-69-09-05', device name 'Triton05' + + strncpy(data->platformId, "Triton", sizeof(data->platformId)); + snprintf(data->deviceName, sizeof(data->deviceName), "%s%02X", + data->platformId, data->macAddr[5]); + +#ifdef DEBUG + printf("header->id: %08X\n", header->id); + printf("header->service: %08X\n", header->service); + printf("header->flags: %08X\n", header->flags); + printf("header->seqNum: %08X\n", header->seqNum); + printf("header->cmd: %08X\n\n", header->cmd); + + printf("data->versionMajor: %08X\n", data->versionMajor); + printf("data->versionMinor: %08X\n", data->versionMinor); + printf("data->cpuId: %08X\n", data->cpuId); + printf("data->bootmeVer: %08X\n", data->bootmeVer); + printf("data->bootFlags: %08X\n", data->bootFlags); + printf("data->svcPort: %08X\n\n", ntohs(data->svcPort)); + + printf("data->macAddr: %pM\n", data->macAddr); + printf("data->ipAddr: %pI4\n", &data->ipAddr); + printf("data->platformId: %s\n", data->platformId); + printf("data->deviceName: %s\n", data->deviceName); +#endif + // Some diag output ... + if (net->verbose) { + printf("Sending BOOTME request [%d] to %pI4\n", net->seqNum, + &server_ip); + } + + net->dataLen = BOOTME_PKT_SIZE; +// net->status = CE_PR_MORE; + net->state = BOOTME_INIT; +#ifdef DEBUG + debug("Start of buffer: %p\n", net->data); + debug("Start of ethernet buffer: %p\n", net->data); + debug("Start of CE header: %p\n", header); + debug("Start of CE data: %p\n", data); + + pkt = net->data; + debug("packet to send (ceconnect): \n"); + for (i = 0; i < net->dataLen; i++) { + debug("0x%02X ", pkt[i]); + if (!((i + 1) % 16)) + debug("\n"); + } + debug("\n"); +#endif + return BootMeRequest(server_ip, net->data, net->dataLen, 1); +} + +static inline int ce_init_download_link(ce_net *net, ce_bin *bin, int verbose) +{ + if (!eth_get_dev()) { + printf("No network interface available\n"); + return -ENODEV; + } + printf("Using device '%s'\n", eth_get_name()); + + /* Initialize EDBG link for download */ + memset(net, 0, sizeof(*net)); + + net->verbose = verbose; + + /* buffer will be dynamically assigned in ce_download_handler() */ + ce_init_bin(bin, NULL); + return 0; +} + +#define UINT_MAX ~0UL + +static inline int ce_download_file(ce_net *net, ulong timeout) +{ + ulong start = get_timer_masked(); + + while (net->state == BOOTME_INIT) { + int ret; + + if (timeout && get_timer(start) > timeout) { + printf("CELOAD - Canceled, timeout\n"); + return 1; + } + + if (ctrlc()) { + printf("CELOAD - canceled by user\n"); + return 1; + } + + if (ce_send_bootme(&g_net)) { + printf("CELOAD - error while sending BOOTME request\n"); + return 1; + } + if (net->verbose) { + if (timeout) { + printf("Waiting for connection, timeout %lu sec\n", + DIV_ROUND_UP(timeout - get_timer(start), + CONFIG_SYS_HZ)); + } else { + printf("Waiting for connection, enter ^C to abort\n"); + } + } + + ret = BootMeDownload(ce_download_handler); + if (ret == BOOTME_ERROR) { + printf("CELOAD - aborted\n"); + return 1; + } + } + return 0; +} + +static void ce_disconnect(void) +{ + net_set_udp_handler(NULL); + eth_halt(); +} + +static int do_ceconnect(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + int verbose = 0; + ulong timeout = 0; + int ret = 1; + int i; + + server_ip = 0; + + for (i = 1; i < argc; i++){ + if (*argv[i] != '-') + break; + if (argv[i][1] == 'v') { + verbose = 1; + } else if (argv[i][1] == 't') { + i++; + if (argc > i) { + timeout = simple_strtoul(argv[i], + NULL, 10); + if (timeout >= UINT_MAX / CONFIG_SYS_HZ) { + printf("Timeout value %lu out of range (max.: %lu)\n", + timeout, UINT_MAX / CONFIG_SYS_HZ - 1); + return CMD_RET_USAGE; + } + timeout *= CONFIG_SYS_HZ; + } else { + printf("Option requires an argument - t\n"); + return CMD_RET_USAGE; + } + } else if (argv[i][1] == 'h') { + i++; + if (argc > i) { + server_ip = string_to_ip(argv[i]); + printf("Using server %pI4\n", &server_ip); + } else { + printf("Option requires an argument - t\n"); + return CMD_RET_USAGE; + } + } + } + + if (ce_init_download_link(&g_net, &g_bin, verbose) != 0) + goto err; + + if (ce_download_file(&g_net, timeout)) + goto err; + + if (g_bin.binLen) { + // Try to receive edbg commands from host + ce_init_edbg_link(&g_net); + if (verbose) + printf("Waiting for EDBG commands ...\n"); + + ret = BootMeDebugStart(ce_edbg_handler); + if (ret != BOOTME_DONE) + goto err; + + // Prepare WinCE image for execution + ce_prepare_run_bin(&g_bin); + + // Launch WinCE, if necessary + if (g_net.gotJumpingRequest) + ce_run_bin(g_bin.eEntryPoint); + } + ret = 0; +err: + ce_disconnect(); + return ret == 0 ? CMD_RET_SUCCESS : CMD_RET_FAILURE; +} +U_BOOT_CMD( + ceconnect, 6, 1, do_ceconnect, + "Set up a connection to the CE host PC over TCP/IP and download the run-time image\n", + "[-v] [-t ] [-h host]\n" + " -v - verbose operation\n" + " -t - max wait time (#sec) for the connection\n" + " -h - send BOOTME requests to (default: broadcast address 255.255.255.255)" +); diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 886212aa07..be14b5f6ca 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -477,7 +477,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* Only "dump" is repeatable. */ if (repeat && strcmp(cmd, "dump")) - return 0; + return CMD_RET_FAILURE; if (strcmp(cmd, "info") == 0) { @@ -486,7 +486,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (nand_info[i].name) nand_print_and_set_info(i); } - return 0; + return CMD_RET_SUCCESS; } if (strcmp(cmd, "device") == 0) { @@ -496,19 +496,20 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) puts("no devices available\n"); else nand_print_and_set_info(dev); - return 0; + return CMD_RET_SUCCESS; } dev = (int)simple_strtoul(argv[2], NULL, 10); set_dev(dev); - return 0; + return CMD_RET_SUCCESS; } #ifdef CONFIG_ENV_OFFSET_OOB /* this command operates only on the first nand device */ if (strcmp(cmd, "env.oob") == 0) - return do_nand_env_oob(cmdtp, argc - 1, argv + 1); + return do_nand_env_oob(cmdtp, argc - 1, argv + 1) ? + CMD_RET_FAILURE : CMD_RET_SUCCESS;; #endif /* The following commands operate on the current device, unless @@ -520,7 +521,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[dev].name) { puts("\nno devices available\n"); - return 1; + return CMD_RET_FAILURE; } nand = &nand_info[dev]; @@ -529,7 +530,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) for (off = 0; off < nand->size; off += nand->erasesize) if (nand_block_isbad(nand, off)) printf(" %08llx\n", (unsigned long long)off); - return 0; + return CMD_RET_SUCCESS; } /* @@ -581,7 +582,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* skip first two or three arguments, look for offset and size */ if (arg_off_size(argc - o, argv + o, &dev, &off, &size, &maxsize) != 0) - return 1; + return CMD_RET_FAILURE; nand = &nand_info[dev]; @@ -604,17 +605,17 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) opts.scrub = 1; else { puts("scrub aborted\n"); - return -1; + return CMD_RET_FAILURE; } } else { puts("scrub aborted\n"); - return -1; + return CMD_RET_FAILURE; } } ret = nand_erase_opts(nand, &opts); printf("%s\n", ret ? "ERROR" : "OK"); - return ret == 0 ? 0 : 1; + return ret == 0 ? CMD_RET_SUCCESS : CMD_RET_FAILURE; } if (strncmp(cmd, "dump", 4) == 0) { @@ -624,7 +625,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) off = (int)simple_strtoul(argv[2], NULL, 16); ret = nand_dump(nand, off, !strcmp(&cmd[4], ".oob"), repeat); - return ret == 0 ? 1 : 0; + return ret == 0 ? CMD_RET_SUCCESS : CMD_RET_FAILURE; } if (strncmp(cmd, "read", 4) == 0 || strncmp(cmd, "write", 5) == 0) { @@ -687,7 +688,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } else if (!strcmp(s, ".trimffs")) { if (read) { printf("Unknown nand command suffix '%s'\n", s); - return 1; + return CMD_RET_FAILURE; } ret = nand_write_skip_bad(nand, off, &rwsize, NULL, maxsize, (u_char *)addr, @@ -697,7 +698,7 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } else if (!strcmp(s, ".yaffs")) { if (read) { printf("Unknown nand command suffix '%s'.\n", s); - return 1; + return CMD_RET_FAILURE; } ret = nand_write_skip_bad(nand, off, &rwsize, NULL, maxsize, (u_char *)addr, @@ -719,13 +720,13 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) ret = raw_access(nand, addr, off, pagecount, read); } else { printf("Unknown nand command suffix '%s'.\n", s); - return 1; + return CMD_RET_FAILURE; } printf(" %zu bytes %s: %s\n", rwsize, read ? "read" : "written", ret ? "ERROR" : "OK"); - return ret == 0 ? 0 : 1; + return ret == 0 ? CMD_RET_SUCCESS : CMD_RET_FAILURE; } #ifdef CONFIG_CMD_NAND_TORTURE @@ -770,12 +771,12 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) --argc; ++argv; } - return ret; + return ret == 0 ? CMD_RET_SUCCESS : CMD_RET_FAILURE; } if (strcmp(cmd, "biterr") == 0) { /* todo */ - return 1; + return CMD_RET_FAILURE; } #ifdef CONFIG_CMD_NAND_LOCK_UNLOCK @@ -795,10 +796,10 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) puts("NAND flash successfully locked\n"); } else { puts("Error locking NAND flash\n"); - return 1; + return CMD_RET_FAILURE; } } - return 0; + return CMD_RET_SUCCESS; } if (strncmp(cmd, "unlock", 5) == 0) { @@ -811,16 +812,16 @@ static int do_nand(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) if (arg_off_size(argc - 2, argv + 2, &dev, &off, &size, &maxsize) < 0) - return 1; + return CMD_RET_FAILURE; if (!nand_unlock(&nand_info[dev], off, size, allexcept)) { puts("NAND flash successfully unlocked\n"); } else { puts("Error unlocking NAND flash, " "write and erase will probably fail\n"); - return 1; + return CMD_RET_FAILURE; } - return 0; + return CMD_RET_SUCCESS; } #endif diff --git a/common/env_nand.c b/common/env_nand.c index 9a6b8a6fb2..9ae28ecbe7 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -44,8 +44,6 @@ char *env_name_spec = "NAND"; env_t *env_ptr = &environment; #elif defined(CONFIG_NAND_ENV_DST) env_t *env_ptr = (env_t *)CONFIG_NAND_ENV_DST; -#else /* ! ENV_IS_EMBEDDED */ -env_t *env_ptr; #endif /* ENV_IS_EMBEDDED */ DECLARE_GLOBAL_DATA_PTR; @@ -363,7 +361,9 @@ void env_relocate_spec(void) gd->env_valid = 1; } +#ifdef CONFIG_NAND_ENV_DST free(env_ptr); +#endif if (gd->env_valid == 1) ep = tmp_env1; diff --git a/common/fdt_support.c b/common/fdt_support.c index b034c9835b..18af0fa312 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -1084,7 +1084,7 @@ static u64 __of_translate_address(void *blob, int node_offset, const fdt32_t *in goto bail; bus = &of_busses[0]; - /* Cound address cells & copy address locally */ + /* Count address cells & copy address locally */ bus->count_cells(blob, parent, &na, &ns); if (!OF_CHECK_COUNTS(na, ns)) { printf("%s: Bad cell count for %s\n", __FUNCTION__, diff --git a/common/lcd.c b/common/lcd.c index 8d5c63c29e..8ba13160c4 100644 --- a/common/lcd.c +++ b/common/lcd.c @@ -59,7 +59,7 @@ #ifdef CONFIG_LCD_LOGO # include /* Get logo data, width and height */ # include -# if (CONSOLE_COLOR_WHITE >= BMP_LOGO_OFFSET) && (LCD_BPP != LCD_COLOR16) +# if (CONSOLE_COLOR_WHITE >= BMP_LOGO_OFFSET) && (LCD_BPP < LCD_COLOR16) # error Default Color Map overlaps with Logo Color Map # endif #endif @@ -95,7 +95,7 @@ #if LCD_BPP == LCD_MONOCHROME # define COLOR_MASK(c) ((c) | (c) << 1 | (c) << 2 | (c) << 3 | \ (c) << 4 | (c) << 5 | (c) << 6 | (c) << 7) -#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16) +#elif (LCD_BPP == LCD_COLOR8) || (LCD_BPP == LCD_COLOR16) || (LCD_BPP == LCD_COLOR24) # define COLOR_MASK(c) (c) #else # error Unsupported LCD BPP. @@ -275,7 +275,7 @@ void lcd_printf(const char *fmt, ...) static void lcd_drawchars(ushort x, ushort y, uchar *str, int count) { - uchar *dest; + void *dest; ushort row; #if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO) @@ -286,13 +286,15 @@ static void lcd_drawchars(ushort x, ushort y, uchar *str, int count) ushort off = x * (1 << LCD_BPP) % 8; #endif - dest = (uchar *)(lcd_base + y * lcd_line_length + x * (1 << LCD_BPP) / 8); + dest = lcd_base + y * lcd_line_length + x * (1 << LCD_BPP) / 8; for (row = 0; row < VIDEO_FONT_HEIGHT; ++row, dest += lcd_line_length) { uchar *s = str; int i; -#if LCD_BPP == LCD_COLOR16 - ushort *d = (ushort *)dest; +#if LCD_BPP == LCD_COLOR24 + ulong *d = dest; +#elif LCD_BPP == LCD_COLOR16 + ushort *d = dest; #else uchar *d = dest; #endif @@ -313,13 +315,7 @@ static void lcd_drawchars(ushort x, ushort y, uchar *str, int count) *d++ = rest | (sym >> off); rest = sym << (8-off); -#elif LCD_BPP == LCD_COLOR8 - for (c = 0; c < 8; ++c) { - *d++ = (bits & 0x80) ? - lcd_color_fg : lcd_color_bg; - bits <<= 1; - } -#elif LCD_BPP == LCD_COLOR16 +#else for (c = 0; c < 8; ++c) { *d++ = (bits & 0x80) ? lcd_color_fg : lcd_color_bg; @@ -360,6 +356,16 @@ static int test_colors[N_BLK_HOR * N_BLK_VERT] = { CONSOLE_COLOR_BLUE, CONSOLE_COLOR_MAGENTA, CONSOLE_COLOR_CYAN, }; +#if LCD_BPP == LCD_COLOR8 +typedef uchar pix_t; +#elif LCD_BPP == LCD_COLOR16 +typedef ushort pix_t; +#elif LCD_BPP == LCD_COLOR24 +typedef ulong pix_t; +#else +#error Unsupported pixelformat +#endif + static void test_pattern(void) { ushort v_max = panel_info.vl_row; @@ -367,7 +373,7 @@ static void test_pattern(void) ushort v_step = (v_max + N_BLK_VERT - 1) / N_BLK_VERT; ushort h_step = (h_max + N_BLK_HOR - 1) / N_BLK_HOR; ushort v, h; - uchar *pix = (uchar *)lcd_base; + pix_t *pix = lcd_base; printf("[LCD] Test Pattern: %d x %d [%d x %d]\n", h_max, v_max, h_step, v_step); @@ -399,7 +405,7 @@ int drv_lcd_init(void) struct stdio_dev lcddev; int rc; - lcd_base = (void *) gd->fb_base; + lcd_base = (void *)gd->fb_base; lcd_init(lcd_base); /* LCD initialization */ @@ -454,7 +460,7 @@ void lcd_clear(void) lcd_line_length * panel_info.vl_row); #endif /* Paint the logo and retrieve LCD base address */ - debug("[LCD] Drawing the logo...\n"); + debug("[LCD] Drawing the logo @ %p...\n", lcd_base); lcd_console_address = lcd_logo(); console_col = 0; @@ -480,7 +486,9 @@ U_BOOT_CMD( static int lcd_init(void *lcdbase) { /* Initialize the lcd controller */ - debug("[LCD] Initializing LCD frambuffer at %p\n", lcdbase); + debug("[LCD] Initializing %ux%ux%u LCD framebuffer at %p\n", + panel_info.vl_col, panel_info.vl_row, NBITS(panel_info.vl_bpix), + lcdbase); lcd_ctrl_init(lcdbase); @@ -569,7 +577,7 @@ int lcd_getfgcolor(void) /*----------------------------------------------------------------------*/ -static int lcd_getbgcolor(void) +static inline int lcd_getbgcolor(void) { return lcd_color_bg; } @@ -583,7 +591,7 @@ static inline ushort *configuration_get_cmap(void) struct pxafb_info *fbi = &panel_info.pxa; return (ushort *)fbi->palette; #elif defined(CONFIG_MPC823) - immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; cpm8xx_t *cp = &(immr->im_cpm); return (ushort *)&(cp->lcd_cmap[255 * sizeof(ushort)]); #elif defined(CONFIG_ATMEL_LCD) @@ -610,7 +618,7 @@ void bitmap_plot(int x, int y) uchar *fb; ushort *fb16; #if defined(CONFIG_MPC823) - immap_t *immr = (immap_t *) CONFIG_SYS_IMMR; + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; cpm8xx_t *cp = &(immr->im_cpm); #endif unsigned bpix = NBITS(panel_info.vl_bpix); @@ -670,8 +678,7 @@ void bitmap_plot(int x, int y) bmap += BMP_LOGO_WIDTH; fb += panel_info.vl_col; } - } - else { /* true color mode */ + } else if (NBITS(panel_info.vl_bpix) == 16) { u16 col16; fb16 = (ushort *)fb; for (i = 0; i < BMP_LOGO_HEIGHT; ++i) { @@ -685,6 +692,21 @@ void bitmap_plot(int x, int y) bmap += BMP_LOGO_WIDTH; fb16 += panel_info.vl_col; } + } else { /* true color mode */ + u16 col16; + u32 *fb32 = lcd_base + y * lcd_line_length + x; + + for (i = 0; i < BMP_LOGO_HEIGHT; i++) { + for (j = 0; j < BMP_LOGO_WIDTH; j++) { + col16 = bmp_logo_palette[bmap[j] - 16]; + fb32[j] = + ((col16 & 0x000F) << 4) | + ((col16 & 0x00F0) << 8) | + ((col16 & 0x0F00) << 12); + } + bmap += BMP_LOGO_WIDTH; + fb32 += panel_info.vl_col; + } } WATCHDOG_RESET(); @@ -886,9 +908,10 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) bmp_image_t *bmp=(bmp_image_t *)bmp_image; uchar *bmap; ushort padded_width; - unsigned long width, height, byte_width; + unsigned long width, height; unsigned long pwidth = panel_info.vl_col; - unsigned colors, bpix, bmp_bpix; + unsigned long long colors; + unsigned bpix, bmp_bpix; if (!bmp || !(bmp->header.signature[0] == 'B' && bmp->header.signature[1] == 'M')) { @@ -900,7 +923,7 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) width = le32_to_cpu(bmp->header.width); height = le32_to_cpu(bmp->header.height); bmp_bpix = le16_to_cpu(bmp->header.bit_count); - colors = 1 << bmp_bpix; + colors = 1ULL << bmp_bpix; bpix = NBITS(panel_info.vl_bpix); @@ -911,8 +934,8 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) return 1; } - /* We support displaying 8bpp BMPs on 16bpp LCDs */ - if (bpix != bmp_bpix && !(bmp_bpix == 8 && bpix == 16)) { + /* We support displaying 8bpp BMPs on 16bpp or 32bpp LCDs */ + if (bpix != bmp_bpix && (bmp_bpix != 8 || (bpix != 16 && bpix != 32))) { printf ("Error: %d bit/pixel mode, but BMP has %d bit/pixel\n", bpix, le16_to_cpu(bmp->header.bit_count)); @@ -920,8 +943,8 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) return 1; } - debug("Display-bmp: %d x %d with %d colors\n", - (int)width, (int)height, (int)colors); + debug("Display-bmp: %lu x %lu with %llu colors\n", + width, height, colors); #if !defined(CONFIG_MCC200) /* MCC200 LCD doesn't need CMAP, supports 1bpp b&w only */ @@ -966,26 +989,29 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) */ #if defined(CONFIG_MCC200) if (bpix == 1) { - width = ((width + 7) & ~7) >> 3; - x = ((x + 7) & ~7) >> 3; - pwidth= ((pwidth + 7) & ~7) >> 3; + width = ALIGN(width, 8) >> 3; + x = ALIGN(x, 8) >> 3; + pwidth= ALIGN(pwidth, 8) >> 3; } #endif - padded_width = (width & 0x3 ? (width & ~0x3) + 4 : width); + padded_width = ALIGN(width, 4); #ifdef CONFIG_SPLASH_SCREEN_ALIGN splash_align_axis(&x, pwidth, width); splash_align_axis(&y, panel_info.vl_row, height); #endif /* CONFIG_SPLASH_SCREEN_ALIGN */ + bmap = (uchar *)bmp + le32_to_cpu (bmp->header.data_offset); if ((x + width) > pwidth) - width = pwidth - x; - if ((y + height) > panel_info.vl_row) + width = max(pwidth - x, pwidth); + if ((y + height) > panel_info.vl_row) { height = panel_info.vl_row - y; + bmap += (panel_info.vl_row - y) * padded_width; + } - bmap = (uchar *) bmp + le32_to_cpu(bmp->header.data_offset); - fb = (uchar *) (lcd_base + + bmap = (uchar *)bmp + le32_to_cpu(bmp->header.data_offset); + fb = (uchar *)(lcd_base + (y + height - 1) * lcd_line_length + x * bpix / 8); switch (bmp_bpix) { @@ -1003,23 +1029,26 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) } #endif - if (bpix != 16) - byte_width = width; - else - byte_width = width * 2; - for (i = 0; i < height; ++i) { WATCHDOG_RESET(); for (j = 0; j < width; j++) { - if (bpix != 16) { - FB_PUT_BYTE(fb, bmap); - } else { + if (bpix == 32) { + int i = *bmap++; + + fb[3] = 0; /* T */ + fb[0] = bmp->color_table[i].blue; + fb[1] = bmp->color_table[i].green; + fb[2] = bmp->color_table[i].red; + fb += sizeof(uint32_t) / sizeof(*fb); + } else if (bpix == 16) { *(uint16_t *)fb = cmap_base[*(bmap++)]; fb += sizeof(uint16_t) / sizeof(*fb); + } else { + FB_PUT_BYTE(fb, bmap); } } - bmap += (padded_width - width); - fb -= byte_width + lcd_line_length; + bmap += padded_width - width; + fb -= width + lcd_line_length; } break; @@ -1035,25 +1064,21 @@ int lcd_display_bitmap(ulong bmp_image, int x, int y) } break; #endif /* CONFIG_BMP_16BPP */ - -#if defined(CONFIG_BMP_32BPP) case 32: for (i = 0; i < height; ++i) { + WATCHDOG_RESET(); for (j = 0; j < width; j++) { - *(fb++) = *(bmap++); - *(fb++) = *(bmap++); - *(fb++) = *(bmap++); - *(fb++) = *(bmap++); + fb[3] = *bmap++; /* T */ + fb[0] = *bmap++; /* B */ + fb[1] = *bmap++; /* G */ + fb[2] = *bmap++; /* R */ + fb += 4; } fb -= lcd_line_length + width * (bpix / 8); } break; -#endif /* CONFIG_BMP_32BPP */ - default: - break; }; - lcd_sync(); return 0; } #endif @@ -1067,12 +1092,16 @@ static void *lcd_logo(void) if (do_splash && (s = getenv("splashimage")) != NULL) { int x = 0, y = 0; + char *end; + do_splash = 0; if (splash_screen_prepare()) return (void *)lcd_base; - addr = simple_strtoul (s, NULL, 16); + addr = simple_strtoul (s, &end, 16); + if (addr == 0 || *end != '\0') + return lcd_base; splash_get_pos(&x, &y); @@ -1090,10 +1119,10 @@ static void *lcd_logo(void) #endif /* CONFIG_LCD_INFO */ #if defined(CONFIG_LCD_LOGO) && !defined(CONFIG_LCD_INFO_BELOW_LOGO) - return (void *)((ulong)lcd_base + BMP_LOGO_HEIGHT * lcd_line_length); + return lcd_base + BMP_LOGO_HEIGHT * lcd_line_length; #else - return (void *)lcd_base; -#endif /* CONFIG_LCD_LOGO && !defined(CONFIG_LCD_INFO_BELOW_LOGO) */ + return lcd_base; +#endif /* CONFIG_LCD_LOGO && !CONFIG_LCD_INFO_BELOW_LOGO */ } #ifdef CONFIG_SPLASHIMAGE_GUARD diff --git a/common/main.c b/common/main.c index ae37fee46d..e852989f73 100644 --- a/common/main.c +++ b/common/main.c @@ -517,9 +517,9 @@ void main_loop(void) else rc = run_command(lastcommand, flag); - if (rc <= 0) { + if (rc || len < 0) { /* invalid command or not repeatable, forget it */ - lastcommand[0] = 0; + lastcommand[0] = '\0'; } } #endif /*CONFIG_SYS_HUSH_PARSER*/ @@ -1020,6 +1020,13 @@ int readline_into_buffer(const char *const prompt, char *buffer, int timeout) if (prompt) puts (prompt); +#ifdef CONFIG_SHOW_ACTIVITY + while (!tstc()) { + extern void show_activity(int arg); + show_activity(0); + WATCHDOG_RESET(); + } +#endif rc = cread_line(prompt, p, &len, timeout); return rc < 0 ? rc : len; @@ -1406,7 +1413,7 @@ static int builtin_run_command(const char *cmd, int flag) continue; } - if (cmd_process(flag, argc, argv, &repeatable, NULL)) + if (cmd_process(flag, argc, argv, &repeatable, NULL) != CMD_RET_SUCCESS) rc = -1; /* Did the user stop this? */ @@ -1432,7 +1439,7 @@ int run_command(const char *cmd, int flag) * builtin_run_command can return 0 or 1 for success, so clean up * its result. */ - if (builtin_run_command(cmd, flag) == -1) + if (builtin_run_command(cmd, flag) != 1) return 1; return 0; diff --git a/common/spl/spl.c b/common/spl/spl.c index d6b0e01075..fc49fba707 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -167,8 +167,9 @@ void board_init_r(gd_t *dummy1, ulong dummy2) #endif #ifdef CONFIG_SPL_NAND_SUPPORT case BOOT_DEVICE_NAND: - spl_nand_load_image(); - break; + if (spl_nand_load_image() == 0) + break; + /* fallthru in case of failure to activate ymodem download */ #endif #ifdef CONFIG_SPL_ONENAND_SUPPORT case BOOT_DEVICE_ONENAND: diff --git a/common/spl/spl_nand.c b/common/spl/spl_nand.c index 9da021862e..da14d1faaf 100644 --- a/common/spl/spl_nand.c +++ b/common/spl/spl_nand.c @@ -10,8 +10,9 @@ #include #include -void spl_nand_load_image(void) +int spl_nand_load_image(void) { + int ret; struct image_header *header; int *src __attribute__((unused)); int *dst __attribute__((unused)); @@ -20,7 +21,7 @@ void spl_nand_load_image(void) nand_init(); /*use CONFIG_SYS_TEXT_BASE as temporary storage area */ - header = (struct image_header *)(CONFIG_SYS_TEXT_BASE); + header = (struct image_header *)CONFIG_SYS_TEXT_BASE; #ifdef CONFIG_SPL_OS_BOOT if (!spl_start_uboot()) { /* @@ -51,12 +52,12 @@ void spl_nand_load_image(void) nand_spl_load_image(CONFIG_SYS_NAND_SPL_KERNEL_OFFS, spl_image.size, (void *)spl_image.load_addr); nand_deselect(); - return; + return 0; } else { - puts("The Expected Linux image was not " - "found. Please check your NAND " + printf("The Expected Linux image was not" + "found. Please check your NAND" "configuration.\n"); - puts("Trying to start u-boot now...\n"); + printf("Trying to start u-boot now...\n"); } } #endif @@ -75,10 +76,13 @@ void spl_nand_load_image(void) #endif #endif /* Load u-boot */ - nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, - CONFIG_SYS_NAND_PAGE_SIZE, (void *)header); - spl_parse_image_header(header); - nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, - spl_image.size, (void *)spl_image.load_addr); + ret = nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, + CONFIG_SYS_NAND_PAGE_SIZE, (void *)header); + if (ret == 0) { + spl_parse_image_header(header); + ret = nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, + spl_image.size, (void *)spl_image.load_addr); + } nand_deselect(); + return ret; } diff --git a/common/spl/spl_ymodem.c b/common/spl/spl_ymodem.c index 0f1e997079..10e69427df 100644 --- a/common/spl/spl_ymodem.c +++ b/common/spl/spl_ymodem.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include @@ -34,22 +35,23 @@ void spl_ymodem_load_image(void) ulong store_addr = ~0; ulong addr = 0; +loop: info.mode = xyzModem_ymodem; ret = xyzModem_stream_open(&info, &err); - - if (!ret) { - while ((res = - xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0) { + if (ret == 0) { + while ((res = xyzModem_stream_read(buf, BUF_SIZE, &err)) > 0) { + WATCHDOG_RESET(); if (addr == 0) spl_parse_image_header((struct image_header *)buf); store_addr = addr + spl_image.load_addr; size += res; addr += res; - memcpy((char *)(store_addr), buf, res); + memcpy((char *)store_addr, buf, res); } } else { - printf("spl: ymodem err - %s\n", xyzModem_error(err)); - hang(); + WATCHDOG_RESET(); + printf("Retrying...\n"); + goto loop; } xyzModem_stream_close(&err); diff --git a/common/xyzModem.c b/common/xyzModem.c index 39f7d17a7c..82039df1f3 100644 --- a/common/xyzModem.c +++ b/common/xyzModem.c @@ -37,7 +37,7 @@ #define BSP 0x08 #define NAK 0x15 #define CAN 0x18 -#define EOF 0x1A /* ^Z for DOS officionados */ +#define EOF 0x1A /* ^Z for DOS aficionados */ #define USE_YMODEM_LENGTH @@ -203,7 +203,7 @@ parse_num (char *s, unsigned long *val, char **es, char *delim) static int zm_dprintf (char *fmt, ...) { - int cur_console; + int cur_console __attribute__((unused)); va_list args; va_start (args, fmt); @@ -217,9 +217,10 @@ zm_dprintf (char *fmt, ...) #ifdef REDBOOT CYGACC_CALL_IF_SET_CONSOLE_COMM (cur_console); #endif + return 0; } -static void +static inline void zm_flush (void) { } @@ -250,7 +251,7 @@ zm_dprintf (char *fmt, ...) return len; } -static void +static inline void zm_flush (void) { #ifdef REDBOOT @@ -275,19 +276,19 @@ zm_dump_buf (void *buf, int len) static unsigned char zm_buf[2048]; static unsigned char *zm_bp; -static void +static inline void zm_new (void) { zm_bp = zm_buf; } -static void +static inline void zm_save (unsigned char c) { *zm_bp++ = c; } -static void +static inline void zm_dump (int line) { zm_dprintf ("Packet at line: %d\n", line); diff --git a/config.mk b/config.mk index 3e84f36d83..4c4551828f 100644 --- a/config.mk +++ b/config.mk @@ -250,12 +250,16 @@ CFLAGS += -DBUILD_TAG='"$(BUILD_TAG)"' endif CFLAGS_SSP := $(call cc-option,-fno-stack-protector) -CFLAGS += $(CFLAGS_SSP) + # Some toolchains enable security related warning flags by default, # but they don't make much sense in the u-boot world, so disable them. CFLAGS_WARN := $(call cc-option,-Wno-format-nonliteral) \ $(call cc-option,-Wno-format-security) -CFLAGS += $(CFLAGS_WARN) + +CFLAGS := $(CFLAGS_SSP) $(CFLAGS_WARN) $(CPPFLAGS) -Wall -Wstrict-prototypes +ifdef BUILD_TAG + CFLAGS += -DBUILD_TAG='"$(BUILD_TAG)"' +endif # Report stack usage if supported CFLAGS_STACK := $(call cc-option,-fstack-usage) diff --git a/disk/part.c b/disk/part.c index d2e34cfcfa..6827744df3 100644 --- a/disk/part.c +++ b/disk/part.c @@ -28,6 +28,9 @@ static const struct block_drvr block_drvr[] = { #if defined(CONFIG_CMD_IDE) { .name = "ide", .get_dev = ide_get_dev, }, #endif +#if defined(CONFIG_CMD_PATA) + { .name = "pata", .get_dev = pata_get_dev, }, +#endif #if defined(CONFIG_CMD_SATA) {.name = "sata", .get_dev = sata_get_dev, }, #endif diff --git a/doc/README.KARO b/doc/README.KARO new file mode 100755 index 0000000000..9fc611e893 --- /dev/null +++ b/doc/README.KARO @@ -0,0 +1,39 @@ + Building & Flashing U-Boot for TX28 + =================================== + +Building U-Boot +--------------- + +Unpacking the source +-------------------- +mkdir u-boot +cd u-boot +tar -xjf /cdrom/U-Boot/u-boot-src.tar.bz2 + +Compiling U-Boot +---------------- +export ARCH=arm +export CROSS_COMPILE=arm-926ejs-linux-gnueabi- +make tx28_config +make + + +Flashing U-Boot Image +--------------------- +Load the U-Boot image with sbloader (either the Windows version or the +Linux version) and use the builtin 'romupdate' command to program the +image into the flash. + +Put the u-boot.sb file in the TFTP server data directory (usually +/tftpboot). + +Load the U-Boot image: +Enter the following commands at the U-Boot prompt +set autostart no +set autoload yes +set bootfile u-boot.sb +bootp +romupdate + +Power down the module, make sure the BOOT_MODE jumper (ST3) is removed +and re-apply power to start from flash. diff --git a/doc/README.KARO-FDT b/doc/README.KARO-FDT new file mode 100644 index 0000000000..4bf01fac29 --- /dev/null +++ b/doc/README.KARO-FDT @@ -0,0 +1,35 @@ + Managing the device tree data in U-Boot + ======================================= + +The 'fdt' command can be used to manipulate the device tree (DT) data +that is passed from U-Boot to Linux. + +- 'fdt boardsetup' will trim out some device nodes according to + environment settings: + +Environment setting removed nodes +--------------------------------------------- +otg_mode=host usbh1 +otg_mode=device usbotg +otg_mode= + usbphy + +touchpanel=edt-ft5x06 ti,tsc2007 +touchpanel=tsc2007 edt,edt-ft5x06 +touchpanel= + +Note: This command is automatically executed when booting Linux via + 'run bootm_cmd'. + +- 'fdt rm' and 'fdt add' can be used to remove/create additional nodes. + +The whole DT data can be saved to and reloaded from the flash partition +'dtb' (or any other partition): + nand erase.part dtb + nand write.jffs2 ${fdtaddr} dtb ${fdtsize} + +If a DT is loaded from flash which should not be further manipulated +upon booting Linux, the string 'fdt boardsetup;' should be removed +from the 'bootm_cmd' environment variable. + +Loading the DT data: + nand read ${fdtaddr} dtb diff --git a/doc/README.KARO-TX28 b/doc/README.KARO-TX28 new file mode 100644 index 0000000000..6f3f20e014 --- /dev/null +++ b/doc/README.KARO-TX28 @@ -0,0 +1,77 @@ + U-Boot for TX28 + =============== + +Building U-Boot +--------------- + +Note: There are currently two variants of the TX28 module, that + require slightly different U-Boot configurations. They are + distinguished through the last digit of the module name. Replace + the '?' in the following description with the corresponding + number from your TX28 module. + E.g. TX28-4031 => 'make tx28-40xx_config' + +Unpacking the source +-------------------- +mkdir u-boot +cd u-boot +tar -xjf /cdrom/U-Boot/u-boot-src.tar.bz2 + +Alternatively you can access the current source via the git repository: +git://git.kernelconcepts.de/karo-tx-uboot.git master + + +Compiling U-Boot +---------------- +export ARCH=arm +export CROSS_COMPILE=arm-cortexa8-linux-gnueabi- +make tx28-4?xx_config (see above Note!) +make + + +Flashing U-Boot Image +--------------------- +If you want to replace a working U-Boot with a new version, you can +load the new U-Boot image via TFTP and program it like any other flash +partition with: +nand erase.part u-boot;nand write.trimffs ${fileaddr} u-boot ${filesize} + +If you want to revive a bricked module, U-Boot can be downloaded via +USB with the 'sbloader' tool in recovery boot mode (Jumper ST3 +on Starterkit-5 baseboard closed). See TX28-U-Boot.pdf for details. + + +U-Boot Features +--------------- + +Environment variables: + +cpu_clk +touchpanel {tsc2007|edt-ft5x06} +otg_mode [host|device|none] +video_mode