From aaf07da607386e74d94a1a3848750b9110d7a04a Mon Sep 17 00:00:00 2001 From: =?utf8?q?Lothar=20Wa=C3=9Fmann?= Date: Tue, 23 Jun 2015 12:59:12 +0200 Subject: [PATCH] karo: add support for TXA5 (SAMA5D4) modules --- arch/arm/Kconfig | 5 + board/karo/txa5/Kconfig | 93 ++++ board/karo/txa5/MAINTAINERS | 7 + board/karo/txa5/Makefile | 7 + board/karo/txa5/txa5.c | 884 ++++++++++++++++++++++++++++++++++++ configs/txa5-5010_defconfig | 18 + configs/txa5-5011_defconfig | 18 + include/configs/txa5.h | 241 ++++++++++ 8 files changed, 1273 insertions(+) create mode 100644 board/karo/txa5/Kconfig create mode 100644 board/karo/txa5/MAINTAINERS create mode 100644 board/karo/txa5/Makefile create mode 100644 board/karo/txa5/txa5.c create mode 100644 configs/txa5-5010_defconfig create mode 100644 configs/txa5-5011_defconfig create mode 100644 include/configs/txa5.h diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 025e44494d..b3297f1547 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -337,6 +337,10 @@ config TARGET_TX6 bool "Support tx6" select SOC_MX6 +config TARGET_TXA5 + bool "Support txA5" + select SOC_SAMA5D4 + config TARGET_ZMX25 bool "Support zmx25" select CPU_ARM926EJS @@ -1030,6 +1034,7 @@ source "board/karo/tx48/Kconfig" source "board/karo/tx51/Kconfig" source "board/karo/tx53/Kconfig" source "board/karo/tx6/Kconfig" +source "board/karo/txa5/Kconfig" source "board/kosagi/novena/Kconfig" source "board/logicpd/imx27lite/Kconfig" source "board/logicpd/imx31_litekit/Kconfig" diff --git a/board/karo/txa5/Kconfig b/board/karo/txa5/Kconfig new file mode 100644 index 0000000000..5daac1f258 --- /dev/null +++ b/board/karo/txa5/Kconfig @@ -0,0 +1,93 @@ +if TARGET_TXA5 + +config SYS_BOARD + default "txa5" + +config SYS_VENDOR + default "karo" + +config SYS_SOC + default "at91" + +config SYS_CONFIG_NAME + default "txa5" + +config TXA5 + bool + default y + select CC_OPTIMIZE_LIBS_FOR_SPEED + select CMD_BMP if LCD + select CMD_BOOTCE + select CMD_BOOTZ + select CMD_CACHE + select CMD_I2C if I2C + select CMD_MEMINFO + select CMD_MEMTEST + select CMD_MMC + select CMD_TIME + select DM + select DM_GPIO +# select GET_FEC_MAC_ADDR_FROM_IIM +# select IMX_WATCHDOG + select MMC + select OF_LIBFDT + select OF_BOARD_SETUP + select PHYLIB +# select PHY_SMSC +# select SYS_I2C +# select SYS_I2C_MXC + +config TXA5_NAND + bool + select TXA5 + select CMD_NAND + select CMD_NAND_TRIMFFS + select CMD_ROMUPDATE + select ENV_IS_IN_NAND if !TXA5_UBOOT_NOENV + select FDT_FIXUP_PARTITIONS if OF_LIBFDT + select MTD_PARTITIONS + select MTD_DEVICE + select NAND + select NAND_ATMEL + select SYS_NAND_USE_FLASH_BBT + +config TXA5_EMMC + bool + select TXA5 + select SUPPORT_EMMC_BOOT + select ENV_IS_IN_MMC if !TXA5_UBOOT_NOENV + +choice + prompt "TXA5 module variant" + +config TARGET_TXA5_5010 + bool "TXA5-5010 (NAND)" + select TXA5_NAND + +config TARGET_TXA5_5011 + bool "TXA5-5011 (eMMC)" + select TXA5_EMMC + +endchoice + +# +# variables selected depending on module variant +# + +config NR_DRAM_BANKS + int + default 1 + +choice + prompt "U-Boot image variant" + +config TXA5_UBOOT + bool "Standard U-Boot image" + +config TXA5_UBOOT_NOENV + bool "U-Boot using only built-in environment" + select ENV_IS_NOWHERE + +endchoice + +endif diff --git a/board/karo/txa5/MAINTAINERS b/board/karo/txa5/MAINTAINERS new file mode 100644 index 0000000000..decabee994 --- /dev/null +++ b/board/karo/txa5/MAINTAINERS @@ -0,0 +1,7 @@ +Ka-Ro TXA5 SoM +M: Lothar Waßmann +S: Maintained +F: board/karo/txa5/ +F: include/configs/txa5.h +F: configs/txa5-5010_defconfig +F: configs/txa5-5011_defconfig diff --git a/board/karo/txa5/Makefile b/board/karo/txa5/Makefile new file mode 100644 index 0000000000..b9c372cc7d --- /dev/null +++ b/board/karo/txa5/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2015 Lothar Waßmann +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += txa5.o diff --git a/board/karo/txa5/txa5.c b/board/karo/txa5/txa5.c new file mode 100644 index 0000000000..ce40c1cc28 --- /dev/null +++ b/board/karo/txa5/txa5.c @@ -0,0 +1,884 @@ +/* + * Copyright (C) 2015 Lothar Waßmann + * based on: board/atmel/sama5d4_xplained/sama5d4_xplained.c + * Copyright (C) 2014 Atmel Bo Shen + * + * See file CREDITS for list of people who contributed to this + * project. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#define DEBUG + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../common/karo.h" + +#define TXA5_LCD_RST_GPIO GPIO_PIN_PA(25) +#define TXA5_LCD_PWR_GPIO GPIO_PIN_PB(15) +#define TXA5_LCD_BACKLIGHT_GPIO GPIO_PIN_PA(24) + +#define TXA5_ETH_RST_GPIO GPIO_PIN_PD(30) +//#define TXA5_ETH_PWR_GPIO GPIO_PIN_BU(7) +#define TXA5_ETH_INT_GPIO GPIO_PIN_PE(1) + +#define TXA5_LED_GPIO GPIO_PIN_PD(29) + +DECLARE_GLOBAL_DATA_PTR; + +static int wdreset; + +#ifdef CONFIG_NAND_ATMEL +static void txa5_nand_hw_init(void) +{ + struct at91_smc *smc = (void *)ATMEL_BASE_SMC; + + at91_periph_clk_enable(ATMEL_ID_SMC); + + /* Configure SMC CS3 for NAND */ + writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) | + AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(1), + &smc->cs[3].setup); + writel(AT91_SMC_PULSE_NWE(2) | AT91_SMC_PULSE_NCS_WR(3) | + AT91_SMC_PULSE_NRD(2) | AT91_SMC_PULSE_NCS_RD(3), + &smc->cs[3].pulse); + writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5), + &smc->cs[3].cycle); + writel(AT91_SMC_TIMINGS_TCLR(2) | AT91_SMC_TIMINGS_TADL(7) | + AT91_SMC_TIMINGS_TAR(2) | AT91_SMC_TIMINGS_TRR(3) | + AT91_SMC_TIMINGS_TWB(7) | AT91_SMC_TIMINGS_RBNSEL(3)| + AT91_SMC_TIMINGS_NFSEL(1), &smc->cs[3].timings); + writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | + AT91_SMC_MODE_EXNW_DISABLE | + AT91_SMC_MODE_DBW_8 | + AT91_SMC_MODE_TDF_CYCLE(3), + &smc->cs[3].mode); + + at91_set_a_periph(AT91_PIO_PORTC, 5, 0); /* D0 */ + at91_set_a_periph(AT91_PIO_PORTC, 6, 0); /* D1 */ + at91_set_a_periph(AT91_PIO_PORTC, 7, 0); /* D2 */ + at91_set_a_periph(AT91_PIO_PORTC, 8, 0); /* D3 */ + at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* D4 */ + at91_set_a_periph(AT91_PIO_PORTC, 10, 0); /* D5 */ + at91_set_a_periph(AT91_PIO_PORTC, 11, 0); /* D6 */ + at91_set_a_periph(AT91_PIO_PORTC, 12, 0); /* D7 */ + at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RE */ + at91_set_a_periph(AT91_PIO_PORTC, 14, 0); /* WE */ + at91_set_a_periph(AT91_PIO_PORTC, 15, 1); /* NCS */ + at91_set_a_periph(AT91_PIO_PORTC, 16, 1); /* RDY */ + at91_set_a_periph(AT91_PIO_PORTC, 17, 1); /* ALE */ + at91_set_a_periph(AT91_PIO_PORTC, 18, 1); /* CLE */ +} +#endif + +static inline void txa5_serial0_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTD, 13, 1); /* TXD0 */ + at91_set_a_periph(AT91_PIO_PORTD, 12, 0); /* RXD0 */ + at91_set_a_periph(AT91_PIO_PORTD, 10, 1); /* CTS0 */ + at91_set_a_periph(AT91_PIO_PORTD, 11, 0); /* RTS0 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_USART0); +} + +static inline void txa5_serial1_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTD, 17, 1); /* TXD1 */ + at91_set_a_periph(AT91_PIO_PORTD, 16, 0); /* RXD1 */ + at91_set_a_periph(AT91_PIO_PORTD, 14, 1); /* CTS1 */ + at91_set_a_periph(AT91_PIO_PORTD, 15, 0); /* RTS1 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_USART1); +} + +static inline void txa5_serial3_hw_init(void) +{ + at91_set_b_periph(AT91_PIO_PORTE, 17, 1); /* TXD3 */ + at91_set_b_periph(AT91_PIO_PORTE, 16, 0); /* RXD3 */ + at91_set_b_periph(AT91_PIO_PORTE, 5, 1); /* CTS3 */ + at91_set_b_periph(AT91_PIO_PORTE, 24, 0); /* RTS3 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_USART3); +} + +#ifdef CONFIG_GENERIC_ATMEL_MCI +void txa5_mci1_hw_init(void) +{ + at91_set_c_periph(AT91_PIO_PORTE, 19, 1); /* MCI1 CDA */ + at91_set_c_periph(AT91_PIO_PORTE, 20, 1); /* MCI1 DA0 */ + at91_set_c_periph(AT91_PIO_PORTE, 21, 1); /* MCI1 DA1 */ + at91_set_c_periph(AT91_PIO_PORTE, 22, 1); /* MCI1 DA2 */ + at91_set_c_periph(AT91_PIO_PORTE, 23, 1); /* MCI1 DA3 */ + at91_set_c_periph(AT91_PIO_PORTE, 18, 0); /* MCI1 CLK */ + + /* + * As the mci io internal pull down is too strong, so if the io needs + * external pull up, the pull up resistor will be very small, if so + * the power consumption will increase, so disable the interanl pull + * down to save the power. + */ + at91_set_pio_pulldown(AT91_PIO_PORTE, 18, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 19, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 20, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 21, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 22, 0); + at91_set_pio_pulldown(AT91_PIO_PORTE, 23, 0); + + /* SD Card Detect */ + at91_set_pio_input(AT91_PIO_PORTE, 6, 1); + at91_set_pio_deglitch(AT91_PIO_PORTE, 6, 1); + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_MCI1); +} +#endif + +#ifdef CONFIG_MACB +void txa5_macb0_hw_init(void) +{ + at91_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ETXCK_EREFCK */ + at91_set_a_periph(AT91_PIO_PORTB, 6, 0); /* ERXDV */ + at91_set_a_periph(AT91_PIO_PORTB, 8, 0); /* ERX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ERX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ERXER */ + at91_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ETXEN */ + at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* ETX0 */ + at91_set_a_periph(AT91_PIO_PORTB, 13, 0); /* ETX1 */ + at91_set_a_periph(AT91_PIO_PORTB, 17, 0); /* EMDIO */ + at91_set_a_periph(AT91_PIO_PORTB, 16, 0); /* EMDC */ + + at91_set_pio_input(AT91_PIO_PORTE, 1, 0); /* IRQ */ + at91_set_pio_deglitch(AT91_PIO_PORTE, 1, 1); + + at91_set_pio_output(AT91_PIO_PORTD, 30, 0); /* PHY RESET */ + at91_set_pio_pullup(AT91_PIO_PORTD, 30, 1); + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_GMAC0); +} +#endif + +int board_early_init_f(void) +{ + at91_periph_clk_enable(ATMEL_ID_PIOA); + at91_periph_clk_enable(ATMEL_ID_PIOB); + at91_periph_clk_enable(ATMEL_ID_PIOC); + at91_periph_clk_enable(ATMEL_ID_PIOD); + at91_periph_clk_enable(ATMEL_ID_PIOE); + +#ifdef CONFIG_USART_ID +#if CONFIG_USART_ID == ATMEL_ID_USART0 + txa5_serial0_hw_init(); +#elif CONFIG_USART_ID == ATMEL_ID_USART1 + txa5_serial1_hw_init(); +#elif CONFIG_USART_ID == ATMEL_ID_USART3 +#else +#error No console UART defined +#endif + txa5_serial3_hw_init(); +#endif /* CONFIG_USART_ID */ + + return 0; +} + +/* called with default environment! */ +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + +#ifdef CONFIG_NAND_ATMEL + txa5_nand_hw_init(); +#endif +#ifdef CONFIG_GENERIC_ATMEL_MCI + txa5_mci1_hw_init(); +#endif + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE); + return 0; +} + +#ifdef CONFIG_GENERIC_ATMEL_MCI +int board_mmc_init(bd_t *bis) +{ + return atmel_mci_init((void *)ATMEL_BASE_MCI1); +} +#endif /* CONFIG_GENERIC_ATMEL_MCI */ + +#ifdef CONFIG_MACB +int board_eth_init(bd_t *bis) +{ + int ret; + + txa5_macb0_hw_init(); + + /* delay at least 21ms for the PHY internal POR signal to deassert */ + udelay(22000); + + /* Deassert RESET to the external phy */ + at91_set_gpio_value(TXA5_ETH_RST_GPIO, 1); + + ret = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00); + + return ret; +} +#endif + +#ifndef ETH_ALEN +#define ETH_ALEN 6 +#endif +#define MAC_ID0_HI (void *)0xfc060040 +#define MAC_ID0_LO (void *)0xfc060044 + +static void txa5_init_mac(void) +{ + uint8_t mac_addr[ETH_ALEN]; + uint32_t mac_hi, mac_lo; + + /* try reading mac address from efuse */ + mac_lo = __raw_readl(MAC_ID0_LO); + mac_hi = __raw_readl(MAC_ID0_HI); + + mac_addr[0] = mac_hi & 0xFF; + mac_addr[1] = (mac_hi >> 8) & 0xFF; + mac_addr[2] = (mac_hi >> 16) & 0xFF; + mac_addr[3] = (mac_hi >> 24) & 0xFF; + mac_addr[4] = mac_lo & 0xFF; + mac_addr[5] = (mac_lo >> 8) & 0xFF; + + if (!is_valid_ether_addr(mac_addr)) { + printf("No valid MAC address programmed\n"); + return; + } + printf("MAC addr from fuse: %pM\n", mac_addr); + eth_setenv_enetaddr("ethaddr", mac_addr); +} + +enum { + LED_STATE_INIT = -1, + LED_STATE_OFF, + LED_STATE_ON, +}; + +void show_activity(int arg) +{ + static int led_state = LED_STATE_INIT; + static ulong last; + + if (led_state == LED_STATE_INIT) { + last = get_timer(0); + at91_set_gpio_value(TXA5_LED_GPIO, 1); + led_state = LED_STATE_ON; + } else { + if (get_timer(last) > CONFIG_SYS_HZ) { + last = get_timer(0); + if (led_state == LED_STATE_ON) { + at91_set_gpio_value(TXA5_LED_GPIO, 0); + } else { + at91_set_gpio_value(TXA5_LED_GPIO, 1); + } + led_state = 1 - led_state; + } + } +} + +#ifdef CONFIG_LCD +vidinfo_t panel_info = { + /* set to max. size supported by SoC */ + .vl_col = 2048, + .vl_row = 2048, + .vl_bpix = LCD_COLOR16, + .vl_tft = 1, + .mmio = (void *)ATMEL_BASE_LCDC, +}; + +#define FB_SYNC_OE_LOW_ACT (1 << 31) +#define FB_SYNC_CLK_LAT_FALL (1 << 30) + +static struct fb_videomode txa5_fb_modes[] = { + { + /* Standard VGA timing */ + .name = "VGA", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = KHZ2PICOS(25175), + .left_margin = 48, + .hsync_len = 96, + .right_margin = 16, + .upper_margin = 31, + .vsync_len = 2, + .lower_margin = 12, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ETV570 640 x 480 display. Syncs low active, + * DE high active, 115.2 mm x 86.4 mm display area + * VGA compatible timing + */ + .name = "ETV570", + .refresh = 60, + .xres = 640, + .yres = 480, + .pixclock = KHZ2PICOS(25175), + .left_margin = 114, + .hsync_len = 30, + .right_margin = 16, + .upper_margin = 32, + .vsync_len = 3, + .lower_margin = 10, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ET0350G0DH6 320 x 240 display. + * 70.08 mm x 52.56 mm display area. + */ + .name = "ET0350", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = KHZ2PICOS(6500), + .left_margin = 68 - 34, + .hsync_len = 34, + .right_margin = 20, + .upper_margin = 18 - 3, + .vsync_len = 3, + .lower_margin = 4, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ET0430G0DH6 480 x 272 display. + * 95.04 mm x 53.856 mm display area. + */ + .name = "ET0430", + .refresh = 60, + .xres = 480, + .yres = 272, + .pixclock = KHZ2PICOS(9000), + .left_margin = 2, + .hsync_len = 41, + .right_margin = 2, + .upper_margin = 2, + .vsync_len = 10, + .lower_margin = 2, + }, + { + /* Emerging ET0500G0DH6 800 x 480 display. + * 109.6 mm x 66.4 mm display area. + */ + .name = "ET0500", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = KHZ2PICOS(33260), + .left_margin = 216 - 128, + .hsync_len = 128, + .right_margin = 1056 - 800 - 216, + .upper_margin = 35 - 2, + .vsync_len = 2, + .lower_margin = 525 - 480 - 35, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ETQ570G0DH6 320 x 240 display. + * 115.2 mm x 86.4 mm display area. + */ + .name = "ETQ570", + .refresh = 60, + .xres = 320, + .yres = 240, + .pixclock = KHZ2PICOS(6400), + .left_margin = 38, + .hsync_len = 30, + .right_margin = 30, + .upper_margin = 16, /* 15 according to datasheet */ + .vsync_len = 3, /* TVP -> 1>x>5 */ + .lower_margin = 4, /* 4.5 according to datasheet */ + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* Emerging ET0700G0DH6 800 x 480 display. + * 152.4 mm x 91.44 mm display area. + */ + .name = "ET0700", + .refresh = 60, + .xres = 800, + .yres = 480, + .pixclock = KHZ2PICOS(33260), + .left_margin = 216 - 128, + .hsync_len = 128, + .right_margin = 1056 - 800 - 216, + .upper_margin = 35 - 2, + .vsync_len = 2, + .lower_margin = 525 - 480 - 35, + .sync = FB_SYNC_CLK_LAT_FALL, + }, + { + /* unnamed entry for assigning parameters parsed from 'video_mode' string */ + .refresh = 60, + .left_margin = 48, + .hsync_len = 96, + .right_margin = 16, + .upper_margin = 31, + .vsync_len = 2, + .lower_margin = 12, + .sync = FB_SYNC_CLK_LAT_FALL, + }, +}; + +static int lcd_enabled = 1; +static int lcd_bl_polarity; +int lcd_output_bpp; + +static int lcd_backlight_polarity(void) +{ + return lcd_bl_polarity; +} + +void lcd_enable(void) +{ + /* HACK ALERT: + * global variable from common/lcd.c + * Set to 0 here to prevent messages from going to LCD + * rather than serial console + */ + lcd_is_enabled = 0; + + if (lcd_enabled) { + karo_load_splashimage(1); + + debug("Switching LCD on\n"); + at91_set_gpio_value(TXA5_LCD_PWR_GPIO, 1); + udelay(100); + at91_set_gpio_value(TXA5_LCD_RST_GPIO, 1); + udelay(300000); + at91_set_gpio_value(TXA5_LCD_BACKLIGHT_GPIO, + lcd_backlight_polarity()); + } +} + +void lcd_disable(void) +{ +} + +void lcd_panel_disable(void) +{ + if (lcd_enabled) { + debug("Switching LCD off\n"); + at91_set_gpio_value(TXA5_LCD_BACKLIGHT_GPIO, + !lcd_backlight_polarity()); + at91_set_gpio_value(TXA5_LCD_PWR_GPIO, 0); + at91_set_gpio_value(TXA5_LCD_RST_GPIO, 0); + } +} + +static void txa5_lcd_panel_setup(struct fb_videomode *fb) +{ + panel_info.vl_clk = PICOS2KHZ(fb->pixclock) * 1000; + + panel_info.vl_col = fb->xres; + panel_info.vl_left_margin = fb->left_margin; + panel_info.vl_hsync_len = fb->hsync_len; + panel_info.vl_right_margin = fb->right_margin; + + panel_info.vl_row = fb->yres; + panel_info.vl_upper_margin = fb->upper_margin; + panel_info.vl_vsync_len = fb->vsync_len; + panel_info.vl_lower_margin = fb->lower_margin; + + if (!(fb->sync & FB_SYNC_HOR_HIGH_ACT)) + panel_info.vl_sync |= LCDC_LCDCFG5_HSPOL; + if (!(fb->sync & FB_SYNC_VERT_HIGH_ACT)) + panel_info.vl_sync |= LCDC_LCDCFG5_VSPOL; + if (fb->sync & FB_SYNC_OE_LOW_ACT) + panel_info.vl_sync |= LCDC_LCDCFG5_DISPPOL; + + panel_info.vl_clk_pol = !!(fb->sync & FB_SYNC_CLK_LAT_FALL); +} + +static void txa5_lcd_hw_init(void) +{ + at91_set_pio_output(AT91_PIO_PORTA, 24, 0); /* LCDPWM */ + at91_set_pio_output(AT91_PIO_PORTA, 25, 0); /* LCD RST */ + at91_set_pio_output(AT91_PIO_PORTB, 15, 0); /* LCD PWR */ + + at91_set_a_periph(AT91_PIO_PORTA, 26, 0); /* LCDVSYNC */ + at91_set_a_periph(AT91_PIO_PORTA, 27, 0); /* LCDHSYNC */ + at91_set_a_periph(AT91_PIO_PORTA, 28, 0); /* LCDDOTCK */ + at91_set_a_periph(AT91_PIO_PORTA, 29, 0); /* LCDDEN */ + + at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* LCDD0 */ + at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* LCDD1 */ + at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* LCDD2 */ + at91_set_a_periph(AT91_PIO_PORTA, 3, 0); /* LCDD3 */ + at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* LCDD4 */ + at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* LCDD5 */ + at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* LCDD6 */ + at91_set_a_periph(AT91_PIO_PORTA, 7, 0); /* LCDD7 */ + + at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* LCDD9 */ + at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* LCDD8 */ + at91_set_a_periph(AT91_PIO_PORTA, 10, 0); /* LCDD10 */ + at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* LCDD11 */ + at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* LCDD12 */ + at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* LCDD13 */ + at91_set_a_periph(AT91_PIO_PORTA, 14, 0); /* LCDD14 */ + at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* LCDD15 */ + + at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* LCDD16 */ + at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* LCDD17 */ + at91_set_a_periph(AT91_PIO_PORTA, 18, 0); /* LCDD18 */ + at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* LCDD19 */ + at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* LCDD20 */ + at91_set_a_periph(AT91_PIO_PORTA, 21, 0); /* LCDD21 */ + at91_set_a_periph(AT91_PIO_PORTA, 22, 0); /* LCDD22 */ + at91_set_a_periph(AT91_PIO_PORTA, 23, 0); /* LCDD23 */ + + /* Enable clock */ + at91_periph_clk_enable(ATMEL_ID_LCDC); +} + +#ifdef CONFIG_LCD_INFO +void lcd_show_board_info(void) +{ + ulong dram_size, nand_size; + int i; + char temp[32]; + + lcd_printf("2015 Ka-Ro electronics GmbH\n"); + lcd_printf("%s CPU at %s MHz\n", get_cpu_name(), + strmhz(temp, get_cpu_clk_rate())); + + dram_size = 0; + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) + dram_size += gd->bd->bi_dram[i].size; + + nand_size = 0; +#ifdef CONFIG_NAND_ATMEL + for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) + nand_size += nand_info[i].size; +#endif + lcd_printf("%ld MB SDRAM, %ld MB NAND\n", + dram_size >> 20, nand_size >> 20); +} +#endif /* CONFIG_LCD_INFO */ + +unsigned int has_lcdc(void) +{ + int color_depth = 16; + const char *video_mode = karo_get_vmode(getenv("video_mode")); + const char *vm; + unsigned long val; + int refresh = 60; + struct fb_videomode *p = &txa5_fb_modes[0]; + struct fb_videomode fb_mode; + int xres_set = 0, yres_set = 0, bpp_set = 0, refresh_set = 0; + int lcd_bus_width; + + if (!lcd_enabled) { + debug("LCD disabled\n"); + return 0; + } + + if (had_ctrlc() || wdreset) { + debug("Disabling LCD\n"); + lcd_enabled = 0; + setenv("splashimage", NULL); + return 0; + } + + karo_fdt_move_fdt(); + + if (video_mode == NULL) { + debug("Disabling LCD\n"); + lcd_enabled = 0; + return 0; + } + + lcd_bl_polarity = karo_fdt_get_backlight_polarity(working_fdt); + vm = video_mode; + if (karo_fdt_get_fb_mode(working_fdt, video_mode, &fb_mode) == 0) { + p = &fb_mode; + debug("Using video mode from FDT\n"); + vm += strlen(vm); + if (fb_mode.xres > panel_info.vl_col || + fb_mode.yres > panel_info.vl_row) { + printf("video resolution from DT: %dx%d exceeds hardware limits: %dx%d\n", + fb_mode.xres, fb_mode.yres, + panel_info.vl_col, panel_info.vl_row); + lcd_enabled = 0; + return 0; + } + } + if (p->name != NULL) + debug("Trying compiled-in video modes\n"); + while (p->name != NULL) { + if (strcmp(p->name, vm) == 0) { + debug("Using video mode: '%s'\n", p->name); + vm += strlen(vm); + break; + } + p++; + } + if (*vm != '\0') + debug("Trying to decode video_mode: '%s'\n", vm); + while (*vm != '\0') { + if (*vm >= '0' && *vm <= '9') { + char *end; + + val = simple_strtoul(vm, &end, 0); + if (end > vm) { + if (!xres_set) { + if (val > panel_info.vl_col) + val = panel_info.vl_col; + p->xres = val; + panel_info.vl_col = val; + xres_set = 1; + } else if (!yres_set) { + if (val > panel_info.vl_row) + val = panel_info.vl_row; + p->yres = val; + panel_info.vl_row = val; + yres_set = 1; + } else if (!bpp_set) { + switch (val) { + case 16: + color_depth = val; + break; + + default: + printf("Invalid color depth: '%.*s' in video_mode; using default: '%u'\n", + end - vm, vm, color_depth); + } + bpp_set = 1; + } else if (!refresh_set) { + refresh = val; + refresh_set = 1; + } + } + vm = end; + } + switch (*vm) { + case '@': + bpp_set = 1; + /* fallthru */ + case '-': + yres_set = 1; + /* fallthru */ + case 'x': + xres_set = 1; + /* fallthru */ + case 'M': + case 'R': + vm++; + break; + + default: + if (*vm != '\0') + vm++; + } + } + if (p->xres == 0 || p->yres == 0) { + printf("Invalid video mode: %s\n", getenv("video_mode")); + lcd_enabled = 0; + printf("Supported video modes are:"); + for (p = &txa5_fb_modes[0]; p->name != NULL; p++) { + printf(" %s", p->name); + } + printf("\n"); + return 0; + } + if (p->xres > panel_info.vl_col || p->yres > panel_info.vl_row) { + printf("video resolution: %dx%d exceeds hardware limits: %dx%d\n", + p->xres, p->yres, panel_info.vl_col, panel_info.vl_row); + lcd_enabled = 0; + return 0; + } + panel_info.vl_col = p->xres; + panel_info.vl_row = p->yres; + + p->pixclock = KHZ2PICOS(refresh * + (p->xres + p->left_margin + p->right_margin + p->hsync_len) * + (p->yres + p->upper_margin + p->lower_margin + p->vsync_len) / + 1000); + debug("Pixel clock set to %lu.%03lu MHz\n", + PICOS2KHZ(p->pixclock) / 1000, PICOS2KHZ(p->pixclock) % 1000); + + if (p != &fb_mode) { + int ret; + + debug("Creating new display-timing node from '%s'\n", + video_mode); + ret = karo_fdt_create_fb_mode(working_fdt, video_mode, p); + if (ret) + printf("Failed to create new display-timing node from '%s': %d\n", + video_mode, ret); + } + + txa5_lcd_hw_init(); + + lcd_bus_width = karo_fdt_get_lcd_bus_width(working_fdt, 24); + switch (lcd_bus_width) { + case 16: + case 18: + case 24: + lcd_output_bpp = lcd_bus_width; + break; + + default: + lcd_enabled = 0; + printf("Invalid LCD bus width: %d\n", lcd_bus_width); + return 0; + } + if (karo_load_splashimage(0) == 0) { + debug("Initializing FB driver\n"); + txa5_lcd_panel_setup(p); + return 1; + } else { + debug("Skipping initialization of LCD controller\n"); + return 0; + } +} +#else +#define lcd_enabled 0 +#endif /* CONFIG_LCD */ + +static void stk5_board_init(void) +{ +#if 0 + gpio_request_array(stk5_gpios, ARRAY_SIZE(stk5_gpios)); + txa5_set_pin_mux(stk5_pads, ARRAY_SIZE(stk5_pads)); +#endif +} + +static void stk5v3_board_init(void) +{ + stk5_board_init(); +} + +static void stk5v5_board_init(void) +{ + stk5_board_init(); + +#if 0 + gpio_request_array(stk5v5_gpios, ARRAY_SIZE(stk5v5_gpios)); + txa5_set_pin_mux(stk5v5_pads, ARRAY_SIZE(stk5v5_pads)); +#endif +} + +/* called with environment from NAND or MMC */ +int board_late_init(void) +{ + int ret = 0; + const char *baseboard; + + env_cleanup(); + +// txa5_set_cpu_clock(); + + if (had_ctrlc()) + setenv_ulong("safeboot", 1); +#if 0 + else if (prm_rstst & PRM_RSTST_WDT1_RST) + setenv_ulong("wdreset", 1); +#endif + else + karo_fdt_move_fdt(); + + baseboard = getenv("baseboard"); + if (!baseboard) + goto exit; + + if (strncmp(baseboard, "stk5", 4) == 0) { + printf("Baseboard: %s\n", baseboard); + if ((strlen(baseboard) == 4) || + strcmp(baseboard, "stk5-v3") == 0) { + stk5v3_board_init(); + } else if (strcmp(baseboard, "stk5-v5") == 0) { + stk5v5_board_init(); + } else { + printf("WARNING: Unsupported STK5 board rev.: %s\n", + baseboard + 4); + } + } else { + printf("WARNING: Unsupported baseboard: '%s'\n", + baseboard); + ret = -EINVAL; + } + +exit: + txa5_init_mac(); + clear_ctrlc(); + return ret; +} + +#if defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_FDT_FIXUP_PARTITIONS +#include +#include +static struct node_info nodes[] = { + { "atmel,sama5d4-nand", MTD_DEV_TYPE_NAND, }, +}; +#else +#define fdt_fixup_mtdparts(b,n,c) do { } while (0) +#endif + +static const char *txa5_touchpanels[] = { + "ti,tsc2007", + "edt,edt-ft5x06", + "eeti,egalax_ts", +}; + +int ft_board_setup(void *blob, bd_t *bd) +{ + const char *baseboard = getenv("baseboard"); + int stk5_v5 = baseboard != NULL && (strcmp(baseboard, "stk5-v5") == 0); + const char *video_mode = karo_get_vmode(getenv("video_mode")); + int ret; + + ret = fdt_increase_size(blob, 4096); + if (ret) { + printf("Failed to increase FDT size: %s\n", fdt_strerror(ret)); + return ret; + } + if (stk5_v5) + karo_fdt_enable_node(blob, "stk5led", 0); + + fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); + fdt_fixup_ethernet(blob); + + karo_fdt_fixup_touchpanel(blob, txa5_touchpanels, + ARRAY_SIZE(txa5_touchpanels)); +// karo_fdt_fixup_usb_otg(blob, "usbotg", "fsl,usbphy", "vbus-supply"); +// karo_fdt_fixup_flexcan(blob, stk5_v5); + karo_fdt_update_fb_mode(blob, video_mode); + + return 0; +} +#endif /* CONFIG_OF_BOARD_SETUP */ diff --git a/configs/txa5-5010_defconfig b/configs/txa5-5010_defconfig new file mode 100644 index 0000000000..78bec57fdd --- /dev/null +++ b/configs/txa5-5010_defconfig @@ -0,0 +1,18 @@ +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_NANDFLASH" +CONFIG_ARM=y +CONFIG_TARGET_TXA5=y +CONFIG_TARGET_TXA5_5010=y +CONFIG_TXA5_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +#CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_NAND=y diff --git a/configs/txa5-5011_defconfig b/configs/txa5-5011_defconfig new file mode 100644 index 0000000000..a184de8eb9 --- /dev/null +++ b/configs/txa5-5011_defconfig @@ -0,0 +1,18 @@ +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D4,SYS_USE_MMC" +CONFIG_ARM=y +CONFIG_TARGET_TXA5=y +CONFIG_TARGET_TXA5_5011=y +CONFIG_TXA5_UBOOT=y +CONFIG_CMD_MII=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_BOOTP_SUBNETMASK=y +CONFIG_BOOTP_GATEWAY=y +CONFIG_BOOTP_DNS=y +CONFIG_MMC=y +CONFIG_LCD=y +CONFIG_NET=y +CONFIG_NETDEVICES=y +#CONFIG_CMD_I2C=y +CONFIG_DOS_PARTITION=y +CONFIG_ENV_IS_IN_MMC=y diff --git a/include/configs/txa5.h b/include/configs/txa5.h new file mode 100644 index 0000000000..fff51d95ad --- /dev/null +++ b/include/configs/txa5.h @@ -0,0 +1,241 @@ +/* + * Copyright (C) 2015 + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include +#include + +#define CONFIG_SYS_TEXT_BASE 0x20100000 + +/* ARM asynchronous clock */ +#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 +#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */ + +#define CONFIG_ARCH_CPU_INIT + +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_BOARD_LATE_INIT +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_DISPLAY_CPUINFO + +#define CONFIG_SYS_GENERIC_BOARD + +/* general purpose I/O */ +#define CONFIG_AT91_GPIO + +/* serial console */ +#define CONFIG_ATMEL_USART +#define CONFIG_USART_BASE ATMEL_BASE_USART0 +#define CONFIG_USART_ID ATMEL_ID_USART0 +#define CONFIG_SYS_CONSOLE_INFO_QUIET + +#define xstr(s) str(s) +#define str(s) #s +#define __pfx(x, s) (x##s) +#define _pfx(x, s) __pfx(x, s) + +/* SDRAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_DDRCS +#define CONFIG_SYS_SDRAM_SIZE 0x20000000 + +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_SDRAM_BASE + SZ_4K - GENERATED_GBL_DATA_SIZE) + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK +#define CONFIG_SYS_AUTOLOAD "no" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "init=/linuxrc console=ttyS0,115200 ro debug panic=1" +#define CONFIG_BOOTCOMMAND "run bootcmd_${boot_mode} bootm_cmd" +#define CONFIG_LOADADDR 22000000 /* load address */ +#define CONFIG_FDTADDR 21000000 +#define CONFIG_SYS_LOAD_ADDR _pfx(0x, CONFIG_LOADADDR) +#define CONFIG_SYS_FDT_ADDR _pfx(0x, CONFIG_FDTADDR) +#define CONFIG_U_BOOT_IMG_SIZE SZ_1M + +/* NAND flash */ +#ifdef CONFIG_TXA5_NAND +#define CONFIG_SYS_MAX_NAND_DEVICE 0x1 +/* our ALE is AD21 */ +#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) +/* our CLE is AD22 */ +#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) +#define CONFIG_SYS_NAND_ONFI_DETECTION +/* PMECC & PMERRLOC */ +#define CONFIG_ATMEL_NAND_HWECC +#define CONFIG_ATMEL_NAND_HW_PMECC +#ifdef CONFIG_ENV_IS_IN_NAND +#define CONFIG_SYS_NAND_U_BOOT_OFFS SZ_128K +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_OFFSET (CONFIG_U_BOOT_IMG_SIZE + CONFIG_SYS_NAND_U_BOOT_OFFS) +#define CONFIG_ENV_SIZE SZ_128K +#define CONFIG_ENV_RANGE 0x60000 +#endif /* CONFIG_ENV_IS_IN_NAND */ +#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 +#define CONFIG_SYS_NAND_SIZE SZ_128M +#define NAND_BASE CONFIG_SYS_NAND_BASE +#endif /* CONFIG_CMD_NAND */ + +/* MMC */ +#ifdef CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_GENERIC_ATMEL_MCI +#define ATMEL_BASE_MMCI ATMEL_BASE_MCI1 + +#define CONFIG_CMD_FAT +#define CONFIG_FAT_WRITE +#define CONFIG_CMD_EXT2 +#endif + +/* Ethernet Hardware */ +#define CONFIG_MACB +#define CONFIG_RMII +#define CONFIG_NET_RETRY_COUNT 20 +#define CONFIG_MACB_SEARCH_PHY + +/* LCD */ +/* #define CONFIG_LCD */ +#ifdef CONFIG_LCD +#ifndef __ASSEMBLY__ +extern int lcd_output_bpp; +#endif +#define LCD_BPP LCD_COLOR16 +#define LCD_OUTPUT_BPP lcd_output_bpp +#define CONFIG_LCD_LOGO +#define CONFIG_ATMEL_HLCD +#define CONFIG_ATMEL_LCD_RGB565 +#define CONFIG_CMD_BMP +#define CONFIG_VIDEO_BMP_RLE8 +#endif + +#ifdef CONFIG_TXA5_NAND +#define CONFIG_SYS_DEFAULT_BOOT_MODE "nand" +#define CONFIG_SYS_BOOT_CMD_NAND \ + "bootcmd_nand=set autostart no;run bootargs_ubifs;nboot linux\0" +#define CONFIG_SYS_FDTSAVE_CMD \ + "fdtsave=fdt resize;nand erase.part dtb" \ + ";nand write ${fdtaddr} dtb ${fdtsize}\0" +#define MTD_NAME "atmel_nand" +#define MTDIDS_DEFAULT "nand0=" MTD_NAME +#ifdef CONFIG_ENV_OFFSET_REDUND +#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \ + "128k(u-boot-spl)," \ + "1m(u-boot)," \ + xstr(CONFIG_ENV_RANGE) \ + "(env)," \ + xstr(CONFIG_ENV_RANGE) \ + "(env2),6m(linux),32m(rootfs),89216k(userfs),512k@0x7f00000(dtb),512k@0x7f80000(bbt)ro" +#else +#define MTDPARTS_DEFAULT "mtdparts=" MTD_NAME ":" \ + "128k(u-boot-spl)," \ + "1m(u-boot)," \ + xstr(CONFIG_ENV_RANGE) \ + "(env),6m(linux),32m(rootfs),89600k(userfs),512k@0x7f00000(dtb),512k@0x7f80000(bbt)ro" +#endif + +#define MMC_ROOT_STR " root=/dev/mmcblk0p2 rootwait\0" +#define ROOTPART_UUID_STR "" + +#else /* CONFIG_TXA5_NAND */ +/* bootstrap + u-boot + env in sd card */ +#define CONFIG_SYS_FDTSAVE_CMD \ + "fdtsave=mmc open 0 1;mmc write ${fdtaddr} " \ + xstr(CONFIG_SYS_DTB_BLKNO) " 80;mmc close 0 1\0" +#define MMC_ROOT_STR " root=PARTUUID=${rootpart_uuid} rootwait\0" +#define ROOTPART_UUID_STR "rootpart_uuid=0cc66cc0-02\0" +#define MTD_NAME "" +#define MTDIDS_DEFAULT "" +#define MTDPARTS_DEFAULT "" +#define CONFIG_SYS_DEFAULT_BOOT_MODE "mmc" +#define CONFIG_SYS_BOOT_CMD_NAND "" +#define CONFIG_SYS_FDTSAVE_CMD \ + "fdtsave=mmc open 0 1;mmc write ${fdtaddr} " \ + xstr(CONFIG_SYS_DTB_BLKNO) " 80;mmc close 0 1\0" +#define MMC_ROOT_STR " root=PARTUUID=${rootpart_uuid} rootwait\0" +#define ROOTPART_UUID_STR "rootpart_uuid=0cc66cc0-02\0" +#ifdef CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_SIZE SZ_128K +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 0x1 +#define CONFIG_DYNAMIC_MMC_DEVNO +#endif /* CONFIG_ENV_IS_IN_MMC */ +#endif /* CONFIG_TXA5_NAND */ + +/* + * Extra Environment Settings + */ +#ifdef CONFIG_ENV_IS_NOWHERE +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autostart=no\0" \ + "autoload=no\0" \ + "bootdelay=-1\0" \ + "fdtaddr=" xstr(CONFIG_FDTADDR) "\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" +#else +#define CONFIG_EXTRA_ENV_SETTINGS \ + "autostart=no\0" \ + "baseboard=stk5-v3\0" \ + "bootargs_jffs2=run default_bootargs;set bootargs ${bootargs}" \ + " root=/dev/mtdblock4 rootfstype=jffs2\0" \ + "bootargs_mmc=run default_bootargs;set bootargs ${bootargs}" \ + MMC_ROOT_STR \ + "bootargs_nfs=run default_bootargs;set bootargs ${bootargs}" \ + " root=/dev/nfs nfsroot=${nfs_server}:${nfsroot},nolock" \ + " ip=dhcp\0" \ + "bootargs_ubifs=run default_bootargs;set bootargs ${bootargs}" \ + " ubi.mtd=rootfs root=ubi0:rootfs rootfstype=ubifs\0" \ + "bootcmd_jffs2=set autostart no;run bootargs_jffs2" \ + ";nboot linux\0" \ + "bootcmd_mmc=set autostart no;run bootargs_mmc" \ + ";fatload mmc 0 ${loadaddr} uImage\0" \ + CONFIG_SYS_BOOT_CMD_NAND \ + "bootcmd_net=set autoload y;set autostart n;run bootargs_nfs" \ + ";dhcp\0" \ + "bootm_cmd=bootm ${loadaddr} - ${fdtaddr}\0" \ + "boot_mode=" CONFIG_SYS_DEFAULT_BOOT_MODE "\0" \ + "default_bootargs=set bootargs " CONFIG_BOOTARGS \ + " ${append_bootargs}\0" \ + "fdtaddr=" xstr(CONFIG_FDTADDR) "\0" \ + CONFIG_SYS_FDTSAVE_CMD \ + "mtdids=" MTDIDS_DEFAULT "\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "nfsroot=/tftpboot/rootfs\0" \ + "otg_mode=device\0" \ + ROOTPART_UUID_STR \ + "touchpanel=tsc2007\0" \ + "video_mode=VGA\0" +#endif /* CONFIG_ENV_IS_NOWHERE */ + + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_PROMPT "TXA5 U-Boot > " +#define CONFIG_SYS_CBSIZE 2048 +#define CONFIG_SYS_PBSIZE \ + (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 256 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_VERSION_VARIABLE /* U-BOOT version */ +#define CONFIG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_SYS_64BIT_VSPRINTF + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN SZ_4M +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Memtest start address */ +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + SZ_4M) + +#endif -- 2.39.2