From fa23bfa321c224d4cfc97fe5448a7658f5eb5664 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Lothar=20Wa=C3=9Fmann?= Date: Mon, 18 Apr 2016 14:42:17 +0200 Subject: [PATCH] karo: tx6: disable gpmi clk before changing podf and clk_sel --- board/karo/tx6/lowlevel_init.S | 21 +++++++++++++++------ board/karo/tx6/tx6ul_ll_init.S | 15 ++++++++++++++- 2 files changed, 29 insertions(+), 7 deletions(-) diff --git a/board/karo/tx6/lowlevel_init.S b/board/karo/tx6/lowlevel_init.S index e8d44801c5..d43c5dc482 100644 --- a/board/karo/tx6/lowlevel_init.S +++ b/board/karo/tx6/lowlevel_init.S @@ -22,6 +22,8 @@ #define SDRAM_SIZE PHYS_SDRAM_1_SIZE #endif +#define CCGR(m) (3 << ((m) * 2)) + #define CPU_2_BE_32(l) \ ((((l) << 24) & 0xFF000000) | \ (((l) << 8) & 0x00FF0000) | \ @@ -726,16 +728,23 @@ dcd_hdr: /* RESET_OUT GPIO_7_12 */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_GPIO17, 0x00000005) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_GPIO17, 0x000030b0) - +#ifndef CONFIG_TX6_EMMC + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CLR) + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14)) + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7)) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x006336c1) /* default: 0x007236c1 */ - MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CHSCCDR, 0x00012093) /* default: 0x0002a150 */ - MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 */ - + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET) + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14)) + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7)) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) +#endif + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CHSCCDR, 0x00012093) /* default: 0x0002a150 (0x00029148) */ + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 (0x00029148) */ MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002001) /* ENET PLL */ /* enable all relevant clocks... */ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET) -#define CCGR(m) (3 << ((m) * 2)) MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR0, CCGR(2)) /* 0xf0c03f3f default: 0xf0c03f0f APBH-DMA */ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR1, CCGR(5)) /* 0xf0fc0c00 default: 0xf0fc0000 ENET */ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(3)) /* 0xfc3fc0cc default: 0xfc3fc00c I2C1 */ @@ -744,7 +753,7 @@ dcd_hdr: MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR5, CCGR(13) | CCGR(12)) /* 0xff033f3f default: 0xf0033f3f UART1 */ MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR6, CCGR(4) | CCGR(3) | CCGR(2) | CCGR(1)) /* 0xffff03ff default: 0xffff0000 USDHC4 (for APBH-DMA!) USDHC3 (for BCH!) USDHC1 USDHC1 */ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) - MXC_DCD_ITEM(0x020c80a0, 0x80082029) /* set video PLL to 984MHz */ + MXC_DCD_ITEM(0x020c80a0, 0x00082029) /* set video PLL to 498MHz */ MXC_DCD_ITEM(0x020c80b0, 0x00065b9a) MXC_DCD_ITEM(0x020c80c0, 0x000f4240) diff --git a/board/karo/tx6/tx6ul_ll_init.S b/board/karo/tx6/tx6ul_ll_init.S index 299e469d7b..bdd2214c9a 100644 --- a/board/karo/tx6/tx6ul_ll_init.S +++ b/board/karo/tx6/tx6ul_ll_init.S @@ -22,6 +22,8 @@ #define SDRAM_SIZE PHYS_SDRAM_1_SIZE #endif +#define CCGR(m) (3 << ((m) * 2)) + #define CPU_2_BE_32(l) \ ((((l) << 24) & 0xFF000000) | \ (((l) << 8) & 0x00FF0000) | \ @@ -559,11 +561,22 @@ dcd_hdr: /* ETN PHY Power */ MXC_DCD_ITEM(IOMUXC_SW_MUX_CTL_PAD_SNVS_TAMPER5, 0x00000015) MXC_DCD_ITEM(IOMUXC_SW_PAD_CTL_PAD_SNVS_TAMPER5, 0x000010b0) +#ifndef CONFIG_TX6_EMMC + /* switch NFC clock to 99MHz */ + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_CLR) + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14)) + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7)) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CS2CDR, 0x0061b6c1) /* default: 0x000336c1 */ + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET) + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR4, CCGR(14)) + MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CCGR2, CCGR(7)) + MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_WRITE) +#endif MXC_DCD_ITEM(CCM_BASE_ADDR + CCM_CSCDR2, 0x00012090) /* default: 0x0002a150 */ MXC_DCD_ITEM(ANATOP_BASE_ADDR + ANATOP_PLL_ENET, 0x00002005) /* ENET PLL */ -#define CCGR(m) (3 << ((m) * 2)) + /* enable all relevant clocks... */ MXC_DCD_CMD_WRT(MXC_DCD_CMD_SZ_WORD, MXC_DCD_CMD_FLAG_SET) /* enable UART clock depending on selected console port */ -- 2.39.2