board/kosagi/novena/video.c

   1 /*
   2  * Novena video output support
   3  *
   4  * Copyright (C) 2014 Marek Vasut <marex@denx.de>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/errno.h>
  11 #include <asm/gpio.h>
  12 #include <asm/io.h>
  13 #include <asm/arch/clock.h>
  14 #include <asm/arch/crm_regs.h>
  15 #include <asm/arch/imx-regs.h>
  16 #include <asm/arch/iomux.h>
  17 #include <asm/arch/mxc_hdmi.h>
  18 #include <asm/arch/sys_proto.h>
  19 #include <asm/imx-common/iomux-v3.h>
  20 #include <asm/imx-common/mxc_i2c.h>
  21 #include <asm/imx-common/video.h>
  22 #include <i2c.h>
  23 #include <input.h>
  24 #include <ipu_pixfmt.h>
  25 #include <linux/fb.h>
  26 #include <linux/input.h>
  27 #include <malloc.h>
  28 #include <stdio_dev.h>
  29
  30 #include "novena.h"
  31
  32 static void enable_hdmi(struct display_info_t const *dev)
  33 {
  34         imx_enable_hdmi_phy();
  35 }
  36
  37 struct display_info_t const displays[] = {
  38         {
  39                 /* HDMI Output */
  40                 .bus    = -1,
  41                 .addr   = 0,
  42                 .pixfmt = IPU_PIX_FMT_RGB24,
  43                 .detect = detect_hdmi,
  44                 .enable = enable_hdmi,
  45                 .mode   = {
  46                         .name           = "HDMI",
  47                         .refresh        = 60,
  48                         .xres           = 1024,
  49                         .yres           = 768,
  50                         .pixclock       = 15384,
  51                         .left_margin    = 220,
  52                         .right_margin   = 40,
  53                         .upper_margin   = 21,
  54                         .lower_margin   = 7,
  55                         .hsync_len      = 60,
  56                         .vsync_len      = 10,
  57                         .sync           = FB_SYNC_EXT,
  58                         .vmode          = FB_VMODE_NONINTERLACED
  59                 },
  60         },
  61 };
  62
  63 size_t display_count = ARRAY_SIZE(displays);
  64
  65 void setup_display_clock(void)
  66 {
  67         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  68         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
  69
  70         enable_ipu_clock();
  71         imx_setup_hdmi();
  72
  73         /* Turn on LDB0,IPU,IPU DI0 clocks */
  74         setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK);
  75
  76         /* set LDB0, LDB1 clk select to 011/011 */
  77         clrsetbits_le32(&mxc_ccm->cs2cdr,
  78                         MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
  79                         MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK,
  80                         (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
  81                         (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET));
  82
  83         setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV);
  84
  85         setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 <<
  86                      MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
  87
  88         writel(IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES |
  89                IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH |
  90                IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
  91                IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
  92                IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
  93                IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
  94                IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
  95                IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED |
  96                IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0,
  97                &iomux->gpr[2]);
  98
  99         clrsetbits_le32(&iomux->gpr[3], IOMUXC_GPR3_LVDS0_MUX_CTL_MASK,
 100                         IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
 101                         IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 102 }