mtd: nand: allow NAND_NO_SUBPAGE_WRITE to be set from driver
The NAND_CHIPOPTIONS_MSK has limited utility and is causing real bugs. It
silently masks off at least one flag that might be set by the driver
(NAND_NO_SUBPAGE_WRITE). This breaks the GPMI NAND driver and possibly
others.
Really, as long as driver writers exercise a small amount of care with
NAND_* options, this mask is not necessary at all; it was only here to
prevent certain options from accidentally being set by the driver. But the
original thought turns out to be a bad idea occasionally. Thus, kill it.
Note, this patch fixes some major gpmi-nand breakage.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Eric Nelson <eric.nelson@boundarydevices.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Joe Hershberger [Wed, 22 Aug 2012 21:49:45 +0000 (16:49 -0500)]
nand: Make NAND lock status compatible with Micron
Micron NAND flash (e.g. MT29F4G08ABADAH4) BLOCK LOCK READ STATUS is not
the same as others. Instead of bit 1 being lock, it is #lock_tight.
To make the driver support either format, ignore bit 1 and use only
bit 0 and bit 2.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Joe Hershberger [Wed, 22 Aug 2012 21:49:42 +0000 (16:49 -0500)]
nand: Add support for unlock.invert
NAND unlock command allows an invert bit to be set to unlock all but
the selected page range.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
[scottwood@freescale.com: updated docs and added comment about invert bit] Signed-off-by: Scott Wood <scottwood@freescale.com>
Matthieu CASTET [Mon, 19 Mar 2012 14:35:25 +0000 (15:35 +0100)]
mtd: support ONFI multi lun NAND
With onfi a flash is organized into one or more logical units (LUNs).
A logical unit (LUN) is the minimum unit that can independently execute
commands and report status.
Mtd does not exploit LUN, so make it see a big single flash where size is
lun_size * number_of_lun.
Without this patch MT29F8G08ADBDAH4 size is 512MiB instead of 1GiB.
Signed-off-by: Matthieu Castet <matthieu.castet@parrot.com> Acked-by: Florian Fainelli <ffainelli@freebox.fr> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
[scottwood@freescale.com: picked from Linux into U-Boot] Reported-by: Rafael Beims <rafael.beims@gmail.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
Otavio Salvador [Sat, 15 Sep 2012 08:26:17 +0000 (08:26 +0000)]
mx28evk: extend default environment
The environment has been based on mx53loco and m28evk but keeping the
possibility to easy change the default console device as Freescale and
mainline kernels differ on the device name.
Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
Constants set with binary value (0b...) are not compiled
from old toolchain when used by the clrsetbits_le32 macro.
Replaces them with the corresponding hex value.
The error reported (for example with the mx6qsabrelite board)
is something like:
mx6qsabrelite.c:369:1: error: invalid suffix "b101" on integer constant
mx6qsabrelite.c:369:1: error: invalid suffix "b10010" on integer constant
mx6qsabrelite.c:369:1: error: invalid suffix "b0000" on integer constant
mx6qsabrelite.c:369:1: error: invalid suffix "b10001" on integer constant
Marek Vasut [Wed, 5 Sep 2012 06:34:44 +0000 (08:34 +0200)]
fdt: Check if the FDT address is configured
In case the "fdt addr" command wasn't ran yet and any other "fdt"
subcommand was issued, the system crashed due to NULL pointer being
used.
This is caused by "fdt addr" command setting up a pointer to the
FDT memory location. Prior issuing "fdt addr", the pointer is NULL
so calling any other subcommands crashed the u-boot.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 4 Sep 2012 11:31:07 +0000 (11:31 +0000)]
Fix strict-aliasing warning in dlmalloc
This fixes the following warnings in dlmalloc seen with my gcc 4.6.
dlmalloc.c: In function 'malloc_bin_reloc':
dlmalloc.c:1493: warning: dereferencing pointer 'p' does break strict-aliasing rules
dlmalloc.c:1493: warning: dereferencing pointer 'p' does break strict-aliasing rules
dlmalloc.c:1490: note: initialized from here
dlmalloc.c:1493: note: initialized from here
This version is tested on avr32 arch boards.
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
Tom Warren [Mon, 10 Sep 2012 15:47:51 +0000 (08:47 -0700)]
NAND: MXS: include common.h first so cache.h is included in correct order
With Simon Glass's include/nand.h alignment changes, some mxs builds
were generating errors. Fix is to ensure asm/cache.h is included before
linux/mtd/nand.h. Moving common.h to top of include list does that.
Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de>
Lucas Stach [Tue, 7 Aug 2012 08:19:15 +0000 (08:19 +0000)]
tegra20: usb: rework set_host_mode
This allows for two things:
- VBus GPIO may be used on other ports than the OTG one
- VBus GPIO may be low active if specified by DT
Signed-off-by: Lucas Stach <dev@lynxeye.de> CC: Stephen Warren <swarren@wwwdotorg.org> CC: Tom Warren <TWarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
MX: set a common place to share code for Freescale i.MX
Up now only MX5 and MX6 can share code, because they have
a common source directory in cpu/armv7. Other not armv7
i.MX can profit of the same shared code. Move these files
into a directory accessible for all, similar to plat-mxc
in linux.
Using ZLIB compression with UBIFS fails if last data node is not a size of
UBIFS_BLOCK_SIZE (4096 bytes).
Easiest way to test this is trying to read a file smaller than 4k:
=> ubifsload 41000000 /etc/fstab
Loading file '/etc/fstab' to addr 0x41000000 with size 704 (0x000002c0)...
UBIFS error (pid 0): read_block: bad data node (block 0, inode 2506)
UBIFS error (pid 0): do_readpage: cannot read page 0 of inode 2506, error -22
Error reading file '/etc/fstab'
/etc/fstab not found!
exit not allowed from main input shell.
=>
With this patch:
=> ubifsload 41000000 /etc/fstab
Loading file '/etc/fstab' to addr 0x41000000 with size 704 (0x000002c0)...
Done
=>
Signed-off-by: Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com> Cc: kmpark@infradead.org Tested-by: Andreas Bießmann <andreas.devel@googlemail.com> Signed-off-by: Stefan Roese <sr@denx.de>
Stephen Warren [Fri, 3 Aug 2012 06:55:04 +0000 (06:55 +0000)]
ARM: tegra: fix Ventana standalone build
Ventana always pulls in files from the Seaboard directory, so needs to
mkdir $(obj)../seaboard unconditionally. This fixes:
git clean -f -d -x
./MAKEALL ventana
"MAKEALL -s tegra20" passes without this change, because Seaboard
happens to be built before Ventana, and hence the directory has already
been created.
I believe the mkdir is only needed for out-of-tree builds, since the
seaboard directory is part of the source tree. However, since we always
build an SPL for Tegra now, which I believe is effectively an out-of-tree
build, we will always need this at some time. The overhead of just
uncondtionally executing the mkdir is minimal, and simplifies the
Makefile, since we don't need to code up the exact minimal condition to
execute the mkdir.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Mon, 30 Jul 2012 10:55:45 +0000 (10:55 +0000)]
tegra: put eMMC environment into the boot sectors
When I set up Tegra's config files to put the environment into eMMC, I
assumed that CONFIG_ENV_OFFSET was a linearized address relative to the
start of the eMMC device, and spanning HW partitions boot0, boot1,
general* and the user area in order. However, it turns out that the
offset is actually relative to the beginning of the user area. Hence,
the environment block ended up in a different location to expected and
documented.
Set CONFIG_SYS_MMC_ENV_PART=2 (boot1) to solve this, and adjust
CONFIG_ENV_OFFSET to be relative to the start of boot1, not the entire
eMMC.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Mon, 30 Jul 2012 10:55:44 +0000 (10:55 +0000)]
env_mmc: allow environment to be in an eMMC partition
eMMC devices may have hardware-level partitions: 2 boot partitions,
up to 4 general partitions, plus the user area. This change introduces
optional config variable CONFIG_SYS_MMC_ENV_PART to indicate which
partition the environment should be stored in: 0=user, 1=boot0, 2=boot1,
4..7=general0..3. This allows the environment to be kept out of the user
area, which simplifies the management of OS-/user-level (MBR/GPT)
partitions within the user area.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
Stephen Warren [Mon, 30 Jul 2012 10:55:43 +0000 (10:55 +0000)]
mmc: detect boot sectors using EXT_CSD_BOOT_MULT too
Some eMMC devices contain boot partitions, but do not set the PART_SUPPORT
bit in EXT_CSD_PARTITIONING_SUPPORT. Allow partition selection on such
devices, by enabling partition switching when EXT_CSD_BOOT_MULT is set.
Note that the Linux kernel enables access to boot partitions solely based
on the value of EXT_CSD_BOOT_MULT; EXT_CSD_PARTITIONING_SUPPORT only
influences access to "general" partitions.
eMMC devices affected by this issue exist on various NVIDIA Tegra
platforms (and presumably many others too), such as Harmony (plug-in eMMC),
Seaboard, Springbank, and Whistler (plug-in eMMC).
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
This commit enables NAND support on the Tamonten Evaluation Carrier and
adds the corresponding device tree nodes. Furthermore, the U-Boot
environment can now be stored in NAND.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
Simon Glass [Sun, 29 Jul 2012 20:53:25 +0000 (20:53 +0000)]
nand: Try to align the default buffers
The NAND layer needs to use cache-aligned buffers by default. Towards this
goal. align the default buffers and their members according to the minimum
DMA alignment defined for the architecture.
Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Scott Wood <scottwood@freescale.com>
Andy Fleming [Thu, 6 Sep 2012 20:23:13 +0000 (15:23 -0500)]
mmc: Remove incorrect cmd->flags usage
There were a couple of drivers that were actually using the flags
field of the cmd structure, despite the fact that no one ever
*set* that field. When we removed the field, those drivers failed
to compile. Replaced the references with the correct usage of
resp_type.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Marek Vasut [Fri, 31 Aug 2012 16:18:10 +0000 (16:18 +0000)]
MX28: MMC: Avoid DMA DCache race condition
This patch prevents dcache-related problem. The problem manifested
itself on the SPI driver, this is just a port to the MMC driver.
The scenario is the same. In case an "mmc read" is issued to a
buffer which was written right before it and data cache is enabled,
the cache eviction might happen during the DMA transfer into the
buffer, therefore corrupting the buffer. Clear any cache lines that
might contain the buffer to prevent such issue.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
Marek Vasut [Fri, 31 Aug 2012 16:08:00 +0000 (16:08 +0000)]
MX28: SPI: Fix the DMA chaining
It turns out that in order for the SPI DMA to properly support
continuous transfers longer than 65280 bytes, there are some very
important parts that were left out from the documentation.
Firstly, the XFER_SIZE register is not written with the whole length
of a transfer, but is written by each and every chained descriptor
with the length of the descriptors data buffer.
Next, unlike the demo code supplied by FSL, which only writes one PIO
word per descriptor, this does not apply if the descriptors are chained,
since the XFER_SIZE register must be written. Therefore, it is essential
to use four PIO words, CTRL0, CMD0, CMD1, XFER_SIZE. CMD0 and CMD1 are
written with zero, since they don't apply. The DMA programs the PIO words
in an incrementing order, so four PIO words.
Finally, unlike the demo code supplied by FSL, the SSP_CTRL0_IGNORE_CRC
must not be set during the whole transfer, but it must be set only on the
last descriptor in the chain.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
Marek Vasut [Fri, 31 Aug 2012 16:07:59 +0000 (16:07 +0000)]
MX28: SPI: Fix the DMA DCache race condition
This patch fixes dcache-related problem. The problem manifested
when dcache was enabled and the following command issued twice:
mw 0x42000000 0 0x4000 ; sf probe ; sf read 0x42000000 0x0 0x10000 ; sha1sum 0x42000000 0x10000
The SHA1 checksum was correct during the first call. Yet with
every subsequent call of the above command, it differed and was
wrong.
It turns out this was because of a race condition. On the first
time the command was called, no cacheline contained any data from
the destination memory location. The DMA transfered data into the
location and the cache above the location was invalidated. Then the
checksum was computed, but that meant the data were loaded into data
cache.
On any subsequent call, the DMA again transfered data into the same
destination. Yet during the transfer, some of the DCache lines were
evicted and written back into the main memory. Once the DMA transfer
completed, the data cache was invalidated over the memory location as
usual. But the data that were to be loaded back into the data cache
by subsequent SHA1 checksuming were corrupted.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Otavio Salvador <otavio@ossystems.com.br> Cc: Stefano Babic <sbabic@denx.de>
Switch the mx35 timer driver to the 32-kHz clock source to avoid calling
mxc_get_clock() again and again, and to be consistent with the timer drivers of
other i.MX SoCs.
The clock dividers that were used do not match at all the reference manual. They
were either completely broken, or came from an early silicon revision
incompatible with the current one.
Joe Hershberger [Fri, 17 Aug 2012 10:18:54 +0000 (10:18 +0000)]
mmc: Fix version check for clock API in sdhci driver
When setting up the clocks in the sdhci driver, the "spec version"
must be masked off. Otherwise any time the vendor version is not 0,
the check will allways assume the interface is version 3. This breaks
when the interface is actually version 1 or 2.
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Stephen Warren [Mon, 30 Jul 2012 10:55:45 +0000 (10:55 +0000)]
tegra: put eMMC environment into the boot sectors
When I set up Tegra's config files to put the environment into eMMC, I
assumed that CONFIG_ENV_OFFSET was a linearized address relative to the
start of the eMMC device, and spanning HW partitions boot0, boot1,
general* and the user area in order. However, it turns out that the
offset is actually relative to the beginning of the user area. Hence,
the environment block ended up in a different location to expected and
documented.
Set CONFIG_SYS_MMC_ENV_PART=2 (boot1) to solve this, and adjust
CONFIG_ENV_OFFSET to be relative to the start of boot1, not the entire
eMMC.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Stephen Warren [Mon, 30 Jul 2012 10:55:44 +0000 (10:55 +0000)]
env_mmc: allow environment to be in an eMMC partition
eMMC devices may have hardware-level partitions: 2 boot partitions,
up to 4 general partitions, plus the user area. This change introduces
optional config variable CONFIG_SYS_MMC_ENV_PART to indicate which
partition the environment should be stored in: 0=user, 1=boot0, 2=boot1,
4..7=general0..3. This allows the environment to be kept out of the user
area, which simplifies the management of OS-/user-level (MBR/GPT)
partitions within the user area.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Stephen Warren [Mon, 30 Jul 2012 10:55:43 +0000 (10:55 +0000)]
mmc: detect boot sectors using EXT_CSD_BOOT_MULT too
Some eMMC devices contain boot partitions, but do not set the PART_SUPPORT
bit in EXT_CSD_PARTITIONING_SUPPORT. Allow partition selection on such
devices, by enabling partition switching when EXT_CSD_BOOT_MULT is set.
Note that the Linux kernel enables access to boot partitions solely based
on the value of EXT_CSD_BOOT_MULT; EXT_CSD_PARTITIONING_SUPPORT only
influences access to "general" partitions.
eMMC devices affected by this issue exist on various NVIDIA Tegra
platforms (and presumably many others too), such as Harmony (plug-in eMMC),
Seaboard, Springbank, and Whistler (plug-in eMMC).
Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
The controller can control high capacity cards. So, the patch adds
the flag. If the flag is not set, "mmcinfo" will fail when a high
capacity card is used.
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Tom Rini [Mon, 6 Aug 2012 08:49:54 +0000 (08:49 +0000)]
am33xx: Remove redundant timer config
We have the timer code in arch/arm/cpu/armv7/omap-common/timer.c that
has been configuring and enabling the timer, so remove our code that
does the same thing by different methods.
Stefano Babic [Wed, 29 Aug 2012 01:21:59 +0000 (01:21 +0000)]
OMAP3: tam3517: add function to read MAC from EEPROM
The manufacturer delivers the TAM3517 SOM with 4 MAC address.
They are stored on the EEPROM of the SOM. The patch adds a
function to get their values and set the ethaddr variables.
AM/DM37x SoCs add the CTRL_WKUP_CTRL register. It contains the
GPIO_IO_PWRDNZ bit, which is required to be set to enable the I/O pads
of gpio_126, gpio_127 and gpio_129.
Signed-off-by: Arnout Vandecappelle (Essensium/Mind) <arnout@mind.be> Cc: Tom Rini <trini@ti.com>
Markus Hubig [Thu, 16 Aug 2012 08:22:09 +0000 (08:22 +0000)]
Fixes the crippled console output on PortuxG20.
In order to use the serial interface on the PortuxG20 we need to enable the
level converter first by setting the PC9 pin to high. The level converter needs
some time to settle so we have to use the mdelay() function to wait for some
time. Unfortunately we have no timers available at board_early_init_f() so we
enable the serial output early within board_postclk_init().
Now the U-Boot output looks fine:
| U-Boot 2012.07-00132-gaf1a3b0-dirty (Aug 16 2012 - 18:21:32)
|
| CPU: AT91SAM9G20
| Crystal frequency: 18.432 MHz
| CPU clock : 396.288 MHz
| Master clock : 132.096 MHz
| DRAM: 64 MiB
| WARNING: Caches not enabled
| NAND: 128 MiB
| In: serial
| Out: serial
| Err: serial
| Net: macb0
| Hit any key to stop autoboot: 0
Signed-off-by: Markus Hubig <mhubig@imko.de> Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
projects / karo-tx-uboot.git / log