arch/arm/boot/dts/armada-xp-db.dts

   1 /*
   2  * Device Tree file for Marvell Armada XP evaluation board
   3  * (DB-78460-BP)
   4  *
   5  * Copyright (C) 2012 Marvell
   6  *
   7  * Lior Amsalem <alior@marvell.com>
   8  * Gregory CLEMENT <gregory.clement@free-electrons.com>
   9  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2.  This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 /dts-v1/;
  17 #include "armada-xp-mv78460.dtsi"
  18
  19 / {
  20         model = "Marvell Armada XP Evaluation Board";
  21         compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
  22
  23         chosen {
  24                 bootargs = "console=ttyS0,115200 earlyprintk";
  25         };
  26
  27         memory {
  28                 device_type = "memory";
  29                 reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
  30         };
  31
  32         soc {
  33                 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
  34                           MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
  35                           MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
  36
  37                 devbus-bootcs {
  38                         status = "okay";
  39
  40                         /* Device Bus parameters are required */
  41
  42                         /* Read parameters */
  43                         devbus,bus-width    = <8>;
  44                         devbus,turn-off-ps  = <60000>;
  45                         devbus,badr-skew-ps = <0>;
  46                         devbus,acc-first-ps = <124000>;
  47                         devbus,acc-next-ps  = <248000>;
  48                         devbus,rd-setup-ps  = <0>;
  49                         devbus,rd-hold-ps   = <0>;
  50
  51                         /* Write parameters */
  52                         devbus,sync-enable = <0>;
  53                         devbus,wr-high-ps  = <60000>;
  54                         devbus,wr-low-ps   = <60000>;
  55                         devbus,ale-wr-ps   = <60000>;
  56
  57                         /* NOR 16 MiB */
  58                         nor@0 {
  59                                 compatible = "cfi-flash";
  60                                 reg = <0 0x1000000>;
  61                                 bank-width = <2>;
  62                         };
  63                 };
  64
  65                 pcie-controller {
  66                         status = "okay";
  67
  68                         /*
  69                          * All 6 slots are physically present as
  70                          * standard PCIe slots on the board.
  71                          */
  72                         pcie@1,0 {
  73                                 /* Port 0, Lane 0 */
  74                                 status = "okay";
  75                         };
  76                         pcie@2,0 {
  77                                 /* Port 0, Lane 1 */
  78                                 status = "okay";
  79                         };
  80                         pcie@3,0 {
  81                                 /* Port 0, Lane 2 */
  82                                 status = "okay";
  83                         };
  84                         pcie@4,0 {
  85                                 /* Port 0, Lane 3 */
  86                                 status = "okay";
  87                         };
  88                         pcie@9,0 {
  89                                 /* Port 2, Lane 0 */
  90                                 status = "okay";
  91                         };
  92                         pcie@10,0 {
  93                                 /* Port 3, Lane 0 */
  94                                 status = "okay";
  95                         };
  96                 };
  97
  98                 internal-regs {
  99                         serial@12000 {
 100                                 clock-frequency = <250000000>;
 101                                 status = "okay";
 102                         };
 103                         serial@12100 {
 104                                 clock-frequency = <250000000>;
 105                                 status = "okay";
 106                         };
 107                         serial@12200 {
 108                                 clock-frequency = <250000000>;
 109                                 status = "okay";
 110                         };
 111                         serial@12300 {
 112                                 clock-frequency = <250000000>;
 113                                 status = "okay";
 114                         };
 115
 116                         sata@a0000 {
 117                                 nr-ports = <2>;
 118                                 status = "okay";
 119                         };
 120
 121                         mdio {
 122                                 phy0: ethernet-phy@0 {
 123                                         reg = <0>;
 124                                 };
 125
 126                                 phy1: ethernet-phy@1 {
 127                                         reg = <1>;
 128                                 };
 129
 130                                 phy2: ethernet-phy@2 {
 131                                         reg = <25>;
 132                                 };
 133
 134                                 phy3: ethernet-phy@3 {
 135                                         reg = <27>;
 136                                 };
 137                         };
 138
 139                         ethernet@70000 {
 140                                 status = "okay";
 141                                 phy = <&phy0>;
 142                                 phy-mode = "rgmii-id";
 143                         };
 144                         ethernet@74000 {
 145                                 status = "okay";
 146                                 phy = <&phy1>;
 147                                 phy-mode = "rgmii-id";
 148                         };
 149                         ethernet@30000 {
 150                                 status = "okay";
 151                                 phy = <&phy2>;
 152                                 phy-mode = "sgmii";
 153                         };
 154                         ethernet@34000 {
 155                                 status = "okay";
 156                                 phy = <&phy3>;
 157                                 phy-mode = "sgmii";
 158                         };
 159
 160                         mvsdio@d4000 {
 161                                 pinctrl-0 = <&sdio_pins>;
 162                                 pinctrl-names = "default";
 163                                 status = "okay";
 164                                 /* No CD or WP GPIOs */
 165                                 broken-cd;
 166                         };
 167
 168                         usb@50000 {
 169                                 status = "okay";
 170                         };
 171
 172                         usb@51000 {
 173                                 status = "okay";
 174                         };
 175
 176                         usb@52000 {
 177                                 status = "okay";
 178                         };
 179
 180                         spi0: spi@10600 {
 181                                 status = "okay";
 182
 183                                 spi-flash@0 {
 184                                         #address-cells = <1>;
 185                                         #size-cells = <1>;
 186                                         compatible = "m25p64";
 187                                         reg = <0>; /* Chip select 0 */
 188                                         spi-max-frequency = <20000000>;
 189                                 };
 190                         };
 191                 };
 192         };
 193 };