arch/arm/boot/dts/atlas6.dtsi

   1 /*
   2  * DTS file for CSR SiRFatlas6 SoC
   3  *
   4  * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10 / {
  11         compatible = "sirf,atlas6";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         interrupt-parent = <&intc>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         reg = <0x0>;
  22                         d-cache-line-size = <32>;
  23                         i-cache-line-size = <32>;
  24                         d-cache-size = <32768>;
  25                         i-cache-size = <32768>;
  26                         /* from bootloader */
  27                         timebase-frequency = <0>;
  28                         bus-frequency = <0>;
  29                         clock-frequency = <0>;
  30                 };
  31         };
  32
  33         axi {
  34                 compatible = "simple-bus";
  35                 #address-cells = <1>;
  36                 #size-cells = <1>;
  37                 ranges = <0x40000000 0x40000000 0x80000000>;
  38
  39                 intc: interrupt-controller@80020000 {
  40                         #interrupt-cells = <1>;
  41                         interrupt-controller;
  42                         compatible = "sirf,prima2-intc";
  43                         reg = <0x80020000 0x1000>;
  44                 };
  45
  46                 sys-iobg {
  47                         compatible = "simple-bus";
  48                         #address-cells = <1>;
  49                         #size-cells = <1>;
  50                         ranges = <0x88000000 0x88000000 0x40000>;
  51
  52                         clks: clock-controller@88000000 {
  53                                 compatible = "sirf,atlas6-clkc";
  54                                 reg = <0x88000000 0x1000>;
  55                                 interrupts = <3>;
  56                                 #clock-cells = <1>;
  57                         };
  58
  59                         reset-controller@88010000 {
  60                                 compatible = "sirf,prima2-rstc";
  61                                 reg = <0x88010000 0x1000>;
  62                         };
  63
  64                         rsc-controller@88020000 {
  65                                 compatible = "sirf,prima2-rsc";
  66                                 reg = <0x88020000 0x1000>;
  67                         };
  68                 };
  69
  70                 mem-iobg {
  71                         compatible = "simple-bus";
  72                         #address-cells = <1>;
  73                         #size-cells = <1>;
  74                         ranges = <0x90000000 0x90000000 0x10000>;
  75
  76                         memory-controller@90000000 {
  77                                 compatible = "sirf,prima2-memc";
  78                                 reg = <0x90000000 0x10000>;
  79                                 interrupts = <27>;
  80                                 clocks = <&clks 5>;
  81                         };
  82                 };
  83
  84                 disp-iobg {
  85                         compatible = "simple-bus";
  86                         #address-cells = <1>;
  87                         #size-cells = <1>;
  88                         ranges = <0x90010000 0x90010000 0x30000>;
  89
  90                         lcd@90010000 {
  91                                 compatible = "sirf,prima2-lcd";
  92                                 reg = <0x90010000 0x20000>;
  93                                 interrupts = <30>;
  94                                 clocks = <&clks 34>;
  95                                 display=<&display>;
  96                                 /* later transfer to pwm */
  97                                 bl-gpio = <&gpio 7 0>;
  98                                 default-panel = <&panel0>;
  99                         };
 100
 101                         vpp@90020000 {
 102                                 compatible = "sirf,prima2-vpp";
 103                                 reg = <0x90020000 0x10000>;
 104                                 interrupts = <31>;
 105                                 clocks = <&clks 35>;
 106                         };
 107                 };
 108
 109                 graphics-iobg {
 110                         compatible = "simple-bus";
 111                         #address-cells = <1>;
 112                         #size-cells = <1>;
 113                         ranges = <0x98000000 0x98000000 0x8000000>;
 114
 115                         graphics@98000000 {
 116                                 compatible = "powervr,sgx510";
 117                                 reg = <0x98000000 0x8000000>;
 118                                 interrupts = <6>;
 119                                 clocks = <&clks 32>;
 120                         };
 121                 };
 122
 123                 dsp-iobg {
 124                         compatible = "simple-bus";
 125                         #address-cells = <1>;
 126                         #size-cells = <1>;
 127                         ranges = <0xa8000000 0xa8000000 0x2000000>;
 128
 129                         dspif@a8000000 {
 130                                 compatible = "sirf,prima2-dspif";
 131                                 reg = <0xa8000000 0x10000>;
 132                                 interrupts = <9>;
 133                         };
 134
 135                         gps@a8010000 {
 136                                 compatible = "sirf,prima2-gps";
 137                                 reg = <0xa8010000 0x10000>;
 138                                 interrupts = <7>;
 139                                 clocks = <&clks 9>;
 140                         };
 141
 142                         dsp@a9000000 {
 143                                 compatible = "sirf,prima2-dsp";
 144                                 reg = <0xa9000000 0x1000000>;
 145                                 interrupts = <8>;
 146                                 clocks = <&clks 8>;
 147                         };
 148                 };
 149
 150                 peri-iobg {
 151                         compatible = "simple-bus";
 152                         #address-cells = <1>;
 153                         #size-cells = <1>;
 154                         ranges = <0xb0000000 0xb0000000 0x180000>,
 155                                <0x56000000 0x56000000 0x1b00000>;
 156
 157                         timer@b0020000 {
 158                                 compatible = "sirf,prima2-tick";
 159                                 reg = <0xb0020000 0x1000>;
 160                                 interrupts = <0>;
 161                         };
 162
 163                         nand@b0030000 {
 164                                 compatible = "sirf,prima2-nand";
 165                                 reg = <0xb0030000 0x10000>;
 166                                 interrupts = <41>;
 167                                 clocks = <&clks 26>;
 168                         };
 169
 170                         audio@b0040000 {
 171                                 compatible = "sirf,prima2-audio";
 172                                 reg = <0xb0040000 0x10000>;
 173                                 interrupts = <35>;
 174                                 clocks = <&clks 27>;
 175                         };
 176
 177                         uart0: uart@b0050000 {
 178                                 cell-index = <0>;
 179                                 compatible = "sirf,prima2-uart";
 180                                 reg = <0xb0050000 0x1000>;
 181                                 interrupts = <17>;
 182                                 fifosize = <128>;
 183                                 clocks = <&clks 13>;
 184                                 sirf,uart-dma-rx-channel = <21>;
 185                                 sirf,uart-dma-tx-channel = <2>;
 186                         };
 187
 188                         uart1: uart@b0060000 {
 189                                 cell-index = <1>;
 190                                 compatible = "sirf,prima2-uart";
 191                                 reg = <0xb0060000 0x1000>;
 192                                 interrupts = <18>;
 193                                 fifosize = <32>;
 194                                 clocks = <&clks 14>;
 195                         };
 196
 197                         uart2: uart@b0070000 {
 198                                 cell-index = <2>;
 199                                 compatible = "sirf,prima2-uart";
 200                                 reg = <0xb0070000 0x1000>;
 201                                 interrupts = <19>;
 202                                 fifosize = <128>;
 203                                 clocks = <&clks 15>;
 204                                 sirf,uart-dma-rx-channel = <6>;
 205                                 sirf,uart-dma-tx-channel = <7>;
 206                         };
 207
 208                         usp0: usp@b0080000 {
 209                                 cell-index = <0>;
 210                                 compatible = "sirf,prima2-usp";
 211                                 reg = <0xb0080000 0x10000>;
 212                                 interrupts = <20>;
 213                                 fifosize = <128>;
 214                                 clocks = <&clks 28>;
 215                                 sirf,usp-dma-rx-channel = <17>;
 216                                 sirf,usp-dma-tx-channel = <18>;
 217                         };
 218
 219                         usp1: usp@b0090000 {
 220                                 cell-index = <1>;
 221                                 compatible = "sirf,prima2-usp";
 222                                 reg = <0xb0090000 0x10000>;
 223                                 interrupts = <21>;
 224                                 fifosize = <128>;
 225                                 clocks = <&clks 29>;
 226                                 sirf,usp-dma-rx-channel = <14>;
 227                                 sirf,usp-dma-tx-channel = <15>;
 228                         };
 229
 230                         dmac0: dma-controller@b00b0000 {
 231                                 cell-index = <0>;
 232                                 compatible = "sirf,prima2-dmac";
 233                                 reg = <0xb00b0000 0x10000>;
 234                                 interrupts = <12>;
 235                                 clocks = <&clks 24>;
 236                         };
 237
 238                         dmac1: dma-controller@b0160000 {
 239                                 cell-index = <1>;
 240                                 compatible = "sirf,prima2-dmac";
 241                                 reg = <0xb0160000 0x10000>;
 242                                 interrupts = <13>;
 243                                 clocks = <&clks 25>;
 244                         };
 245
 246                         vip@b00C0000 {
 247                                 compatible = "sirf,prima2-vip";
 248                                 reg = <0xb00C0000 0x10000>;
 249                                 clocks = <&clks 31>;
 250                                 interrupts = <14>;
 251                                 sirf,vip-dma-rx-channel = <16>;
 252                         };
 253
 254                         spi0: spi@b00d0000 {
 255                                 cell-index = <0>;
 256                                 compatible = "sirf,prima2-spi";
 257                                 reg = <0xb00d0000 0x10000>;
 258                                 interrupts = <15>;
 259                                 sirf,spi-num-chipselects = <1>;
 260                                 cs-gpios = <&gpio 0 0>;
 261                                 sirf,spi-dma-rx-channel = <25>;
 262                                 sirf,spi-dma-tx-channel = <20>;
 263                                 #address-cells = <1>;
 264                                 #size-cells = <0>;
 265                                 clocks = <&clks 19>;
 266                                 status = "disabled";
 267                         };
 268
 269                         spi1: spi@b0170000 {
 270                                 cell-index = <1>;
 271                                 compatible = "sirf,prima2-spi";
 272                                 reg = <0xb0170000 0x10000>;
 273                                 interrupts = <16>;
 274                                 clocks = <&clks 20>;
 275                                 status = "disabled";
 276                         };
 277
 278                         i2c0: i2c@b00e0000 {
 279                                 cell-index = <0>;
 280                                 compatible = "sirf,prima2-i2c";
 281                                 reg = <0xb00e0000 0x10000>;
 282                                 interrupts = <24>;
 283                                 #address-cells = <1>;
 284                                 #size-cells = <0>;
 285                                 clocks = <&clks 17>;
 286                         };
 287
 288                         i2c1: i2c@b00f0000 {
 289                                 cell-index = <1>;
 290                                 compatible = "sirf,prima2-i2c";
 291                                 reg = <0xb00f0000 0x10000>;
 292                                 interrupts = <25>;
 293                                 #address-cells = <1>;
 294                                 #size-cells = <0>;
 295                                 clocks = <&clks 18>;
 296                         };
 297
 298                         tsc@b0110000 {
 299                                 compatible = "sirf,prima2-tsc";
 300                                 reg = <0xb0110000 0x10000>;
 301                                 interrupts = <33>;
 302                                 clocks = <&clks 16>;
 303                         };
 304
 305                         gpio: pinctrl@b0120000 {
 306                                 #gpio-cells = <2>;
 307                                 #interrupt-cells = <2>;
 308                                 compatible = "sirf,atlas6-pinctrl";
 309                                 reg = <0xb0120000 0x10000>;
 310                                 interrupts = <43 44 45 46 47>;
 311                                 gpio-controller;
 312                                 interrupt-controller;
 313
 314                                 lcd_16pins_a: lcd0@0 {
 315                                         lcd {
 316                                                 sirf,pins = "lcd_16bitsgrp";
 317                                                 sirf,function = "lcd_16bits";
 318                                         };
 319                                 };
 320                                 lcd_18pins_a: lcd0@1 {
 321                                         lcd {
 322                                                 sirf,pins = "lcd_18bitsgrp";
 323                                                 sirf,function = "lcd_18bits";
 324                                         };
 325                                 };
 326                                 lcd_24pins_a: lcd0@2 {
 327                                         lcd {
 328                                                 sirf,pins = "lcd_24bitsgrp";
 329                                                 sirf,function = "lcd_24bits";
 330                                         };
 331                                 };
 332                                 lcdrom_pins_a: lcdrom0@0 {
 333                                         lcd {
 334                                                 sirf,pins = "lcdromgrp";
 335                                                 sirf,function = "lcdrom";
 336                                         };
 337                                 };
 338                                 uart0_pins_a: uart0@0 {
 339                                         uart {
 340                                                 sirf,pins = "uart0grp";
 341                                                 sirf,function = "uart0";
 342                                         };
 343                                 };
 344                                 uart0_noflow_pins_a: uart0@1 {
 345                                         uart {
 346                                                 sirf,pins = "uart0_nostreamctrlgrp";
 347                                                 sirf,function = "uart0_nostreamctrl";
 348                                         };
 349                                 };
 350                                 uart1_pins_a: uart1@0 {
 351                                         uart {
 352                                                 sirf,pins = "uart1grp";
 353                                                 sirf,function = "uart1";
 354                                         };
 355                                 };
 356                                 uart2_pins_a: uart2@0 {
 357                                         uart {
 358                                                 sirf,pins = "uart2grp";
 359                                                 sirf,function = "uart2";
 360                                         };
 361                                 };
 362                                 uart2_noflow_pins_a: uart2@1 {
 363                                         uart {
 364                                                 sirf,pins = "uart2_nostreamctrlgrp";
 365                                                 sirf,function = "uart2_nostreamctrl";
 366                                         };
 367                                 };
 368                                 spi0_pins_a: spi0@0 {
 369                                         spi {
 370                                                 sirf,pins = "spi0grp";
 371                                                 sirf,function = "spi0";
 372                                         };
 373                                 };
 374                                 spi1_pins_a: spi1@0 {
 375                                         spi {
 376                                                 sirf,pins = "spi1grp";
 377                                                 sirf,function = "spi1";
 378                                         };
 379                                 };
 380                                 i2c0_pins_a: i2c0@0 {
 381                                         i2c {
 382                                                 sirf,pins = "i2c0grp";
 383                                                 sirf,function = "i2c0";
 384                                         };
 385                                 };
 386                                 i2c1_pins_a: i2c1@0 {
 387                                         i2c {
 388                                                 sirf,pins = "i2c1grp";
 389                                                 sirf,function = "i2c1";
 390                                         };
 391                                 };
 392                                 pwm0_pins_a: pwm0@0 {
 393                                         pwm {
 394                                                 sirf,pins = "pwm0grp";
 395                                                 sirf,function = "pwm0";
 396                                         };
 397                                 };
 398                                 pwm1_pins_a: pwm1@0 {
 399                                         pwm {
 400                                                 sirf,pins = "pwm1grp";
 401                                                 sirf,function = "pwm1";
 402                                         };
 403                                 };
 404                                 pwm2_pins_a: pwm2@0 {
 405                                         pwm {
 406                                                 sirf,pins = "pwm2grp";
 407                                                 sirf,function = "pwm2";
 408                                         };
 409                                 };
 410                                 pwm3_pins_a: pwm3@0 {
 411                                         pwm {
 412                                                 sirf,pins = "pwm3grp";
 413                                                 sirf,function = "pwm3";
 414                                         };
 415                                 };
 416                                 pwm4_pins_a: pwm4@0 {
 417                                         pwm {
 418                                                 sirf,pins = "pwm4grp";
 419                                                 sirf,function = "pwm4";
 420                                         };
 421                                 };
 422                                 gps_pins_a: gps@0 {
 423                                         gps {
 424                                                 sirf,pins = "gpsgrp";
 425                                                 sirf,function = "gps";
 426                                         };
 427                                 };
 428                                 vip_pins_a: vip@0 {
 429                                         vip {
 430                                                 sirf,pins = "vipgrp";
 431                                                 sirf,function = "vip";
 432                                         };
 433                                 };
 434                                 sdmmc0_pins_a: sdmmc0@0 {
 435                                         sdmmc0 {
 436                                                 sirf,pins = "sdmmc0grp";
 437                                                 sirf,function = "sdmmc0";
 438                                         };
 439                                 };
 440                                 sdmmc1_pins_a: sdmmc1@0 {
 441                                         sdmmc1 {
 442                                                 sirf,pins = "sdmmc1grp";
 443                                                 sirf,function = "sdmmc1";
 444                                         };
 445                                 };
 446                                 sdmmc2_pins_a: sdmmc2@0 {
 447                                         sdmmc2 {
 448                                                 sirf,pins = "sdmmc2grp";
 449                                                 sirf,function = "sdmmc2";
 450                                         };
 451                                 };
 452                                 sdmmc2_nowp_pins_a: sdmmc2_nowp@0 {
 453                                         sdmmc2_nowp {
 454                                                 sirf,pins = "sdmmc2_nowpgrp";
 455                                                 sirf,function = "sdmmc2_nowp";
 456                                         };
 457                                 };
 458                                 sdmmc3_pins_a: sdmmc3@0 {
 459                                         sdmmc3 {
 460                                                 sirf,pins = "sdmmc3grp";
 461                                                 sirf,function = "sdmmc3";
 462                                         };
 463                                 };
 464                                 sdmmc5_pins_a: sdmmc5@0 {
 465                                         sdmmc5 {
 466                                                 sirf,pins = "sdmmc5grp";
 467                                                 sirf,function = "sdmmc5";
 468                                         };
 469                                 };
 470                                 i2s_pins_a: i2s@0 {
 471                                         i2s {
 472                                                 sirf,pins = "i2sgrp";
 473                                                 sirf,function = "i2s";
 474                                         };
 475                                 };
 476                                 i2s_no_din_pins_a: i2s_no_din@0 {
 477                                         i2s_no_din {
 478                                                 sirf,pins = "i2s_no_dingrp";
 479                                                 sirf,function = "i2s_no_din";
 480                                         };
 481                                 };
 482                                 i2s_6chn_pins_a: i2s_6chn@0 {
 483                                         i2s_6chn {
 484                                                 sirf,pins = "i2s_6chngrp";
 485                                                 sirf,function = "i2s_6chn";
 486                                         };
 487                                 };
 488                                 ac97_pins_a: ac97@0 {
 489                                         ac97 {
 490                                                 sirf,pins = "ac97grp";
 491                                                 sirf,function = "ac97";
 492                                         };
 493                                 };
 494                                 nand_pins_a: nand@0 {
 495                                         nand {
 496                                                 sirf,pins = "nandgrp";
 497                                                 sirf,function = "nand";
 498                                         };
 499                                 };
 500                                 usp0_pins_a: usp0@0 {
 501                                         usp0 {
 502                                                 sirf,pins = "usp0grp";
 503                                                 sirf,function = "usp0";
 504                                         };
 505                                 };
 506                                 usp0_uart_nostreamctrl_pins_a: usp0@1 {
 507                                         usp0 {
 508                                                 sirf,pins = "usp0_uart_nostreamctrl_grp";
 509                                                 sirf,function = "usp0_uart_nostreamctrl";
 510                                         };
 511                                 };
 512                                 usp1_pins_a: usp1@0 {
 513                                         usp1 {
 514                                                 sirf,pins = "usp1grp";
 515                                                 sirf,function = "usp1";
 516                                         };
 517                                 };
 518                                 usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
 519                                         usb0_upli_drvbus {
 520                                                 sirf,pins = "usb0_upli_drvbusgrp";
 521                                                 sirf,function = "usb0_upli_drvbus";
 522                                         };
 523                                 };
 524                                 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
 525                                         usb1_utmi_drvbus {
 526                                                 sirf,pins = "usb1_utmi_drvbusgrp";
 527                                                 sirf,function = "usb1_utmi_drvbus";
 528                                         };
 529                                 };
 530                                 usb1_dp_dn_pins_a: usb1_dp_dn@0 {
 531                                         usb1_dp_dn {
 532                                                 sirf,pins = "usb1_dp_dngrp";
 533                                                 sirf,function = "usb1_dp_dn";
 534                                         };
 535                                 };
 536                                 uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
 537                                         uart1_route_io_usb1 {
 538                                                 sirf,pins = "uart1_route_io_usb1grp";
 539                                                 sirf,function = "uart1_route_io_usb1";
 540                                         };
 541                                 };
 542                                 warm_rst_pins_a: warm_rst@0 {
 543                                         warm_rst {
 544                                                 sirf,pins = "warm_rstgrp";
 545                                                 sirf,function = "warm_rst";
 546                                         };
 547                                 };
 548                                 pulse_count_pins_a: pulse_count@0 {
 549                                         pulse_count {
 550                                                 sirf,pins = "pulse_countgrp";
 551                                                 sirf,function = "pulse_count";
 552                                         };
 553                                 };
 554                                 cko0_pins_a: cko0@0 {
 555                                         cko0 {
 556                                                 sirf,pins = "cko0grp";
 557                                                 sirf,function = "cko0";
 558                                         };
 559                                 };
 560                                 cko1_pins_a: cko1@0 {
 561                                         cko1 {
 562                                                 sirf,pins = "cko1grp";
 563                                                 sirf,function = "cko1";
 564                                         };
 565                                 };
 566                         };
 567
 568                         pwm@b0130000 {
 569                                 compatible = "sirf,prima2-pwm";
 570                                 reg = <0xb0130000 0x10000>;
 571                                 clocks = <&clks 21>;
 572                         };
 573
 574                         efusesys@b0140000 {
 575                                 compatible = "sirf,prima2-efuse";
 576                                 reg = <0xb0140000 0x10000>;
 577                                 clocks = <&clks 22>;
 578                         };
 579
 580                         pulsec@b0150000 {
 581                                 compatible = "sirf,prima2-pulsec";
 582                                 reg = <0xb0150000 0x10000>;
 583                                 interrupts = <48>;
 584                                 clocks = <&clks 23>;
 585                         };
 586
 587                         pci-iobg {
 588                                 compatible = "sirf,prima2-pciiobg", "simple-bus";
 589                                 #address-cells = <1>;
 590                                 #size-cells = <1>;
 591                                 ranges = <0x56000000 0x56000000 0x1b00000>;
 592
 593                                 sd0: sdhci@56000000 {
 594                                         cell-index = <0>;
 595                                         compatible = "sirf,prima2-sdhc";
 596                                         reg = <0x56000000 0x100000>;
 597                                         interrupts = <38>;
 598                                         bus-width = <8>;
 599                                         clocks = <&clks 36>;
 600                                 };
 601
 602                                 sd1: sdhci@56100000 {
 603                                         cell-index = <1>;
 604                                         compatible = "sirf,prima2-sdhc";
 605                                         reg = <0x56100000 0x100000>;
 606                                         interrupts = <38>;
 607                                         status = "disabled";
 608                                         clocks = <&clks 36>;
 609                                 };
 610
 611                                 sd2: sdhci@56200000 {
 612                                         cell-index = <2>;
 613                                         compatible = "sirf,prima2-sdhc";
 614                                         reg = <0x56200000 0x100000>;
 615                                         interrupts = <23>;
 616                                         status = "disabled";
 617                                         clocks = <&clks 37>;
 618                                 };
 619
 620                                 sd3: sdhci@56300000 {
 621                                         cell-index = <3>;
 622                                         compatible = "sirf,prima2-sdhc";
 623                                         reg = <0x56300000 0x100000>;
 624                                         interrupts = <23>;
 625                                         status = "disabled";
 626                                         clocks = <&clks 37>;
 627                                 };
 628
 629                                 sd5: sdhci@56500000 {
 630                                         cell-index = <5>;
 631                                         compatible = "sirf,prima2-sdhc";
 632                                         reg = <0x56500000 0x100000>;
 633                                         interrupts = <39>;
 634                                         status = "disabled";
 635                                         clocks = <&clks 38>;
 636                                 };
 637
 638                                 pci-copy@57900000 {
 639                                         compatible = "sirf,prima2-pcicp";
 640                                         reg = <0x57900000 0x100000>;
 641                                         interrupts = <40>;
 642                                 };
 643
 644                                 rom-interface@57a00000 {
 645                                         compatible = "sirf,prima2-romif";
 646                                         reg = <0x57a00000 0x100000>;
 647                                 };
 648                         };
 649                 };
 650
 651                 rtc-iobg {
 652                         compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
 653                         #address-cells = <1>;
 654                         #size-cells = <1>;
 655                         reg = <0x80030000 0x10000>;
 656
 657                         gpsrtc@1000 {
 658                                 compatible = "sirf,prima2-gpsrtc";
 659                                 reg = <0x1000 0x1000>;
 660                                 interrupts = <55 56 57>;
 661                         };
 662
 663                         sysrtc@2000 {
 664                                 compatible = "sirf,prima2-sysrtc";
 665                                 reg = <0x2000 0x1000>;
 666                                 interrupts = <52 53 54>;
 667                         };
 668
 669                         pwrc@3000 {
 670                                 compatible = "sirf,prima2-pwrc";
 671                                 reg = <0x3000 0x1000>;
 672                                 interrupts = <32>;
 673                         };
 674                 };
 675
 676                 uus-iobg {
 677                         compatible = "simple-bus";
 678                         #address-cells = <1>;
 679                         #size-cells = <1>;
 680                         ranges = <0xb8000000 0xb8000000 0x40000>;
 681
 682                         usb0: usb@b00e0000 {
 683                                 compatible = "chipidea,ci13611a-prima2";
 684                                 reg = <0xb8000000 0x10000>;
 685                                 interrupts = <10>;
 686                                 clocks = <&clks 40>;
 687                         };
 688
 689                         usb1: usb@b00f0000 {
 690                                 compatible = "chipidea,ci13611a-prima2";
 691                                 reg = <0xb8010000 0x10000>;
 692                                 interrupts = <11>;
 693                                 clocks = <&clks 41>;
 694                         };
 695
 696                         security@b00f0000 {
 697                                 compatible = "sirf,prima2-security";
 698                                 reg = <0xb8030000 0x10000>;
 699                                 interrupts = <42>;
 700                                 clocks = <&clks 7>;
 701                         };
 702                 };
 703         };
 704 };