arch/arm/boot/dts/exynos5420.dtsi

   1 /*
   2  * SAMSUNG EXYNOS5420 SoC device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SAMSUNG EXYNOS54200 SoC device nodes are listed in this file.
   8  * EXYNOS5420 based board files can include this file and provide
   9  * values for board specfic bindings.
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15
  16 #include "exynos5.dtsi"
  17 #include "exynos5420-pinctrl.dtsi"
  18
  19 #include <dt-bindings/clk/exynos-audss-clk.h>
  20
  21 / {
  22         compatible = "samsung,exynos5420";
  23
  24         aliases {
  25                 mshc0 = &mmc_0;
  26                 mshc1 = &mmc_1;
  27                 mshc2 = &mmc_2;
  28                 pinctrl0 = &pinctrl_0;
  29                 pinctrl1 = &pinctrl_1;
  30                 pinctrl2 = &pinctrl_2;
  31                 pinctrl3 = &pinctrl_3;
  32                 pinctrl4 = &pinctrl_4;
  33                 i2c0 = &i2c_0;
  34                 i2c1 = &i2c_1;
  35                 i2c2 = &i2c_2;
  36                 i2c3 = &i2c_3;
  37                 gsc0 = &gsc_0;
  38                 gsc1 = &gsc_1;
  39         };
  40
  41         cpus {
  42                 #address-cells = <1>;
  43                 #size-cells = <0>;
  44
  45                 cpu0: cpu@0 {
  46                         device_type = "cpu";
  47                         compatible = "arm,cortex-a15";
  48                         reg = <0x0>;
  49                         clock-frequency = <1800000000>;
  50                 };
  51
  52                 cpu1: cpu@1 {
  53                         device_type = "cpu";
  54                         compatible = "arm,cortex-a15";
  55                         reg = <0x1>;
  56                         clock-frequency = <1800000000>;
  57                 };
  58
  59                 cpu2: cpu@2 {
  60                         device_type = "cpu";
  61                         compatible = "arm,cortex-a15";
  62                         reg = <0x2>;
  63                         clock-frequency = <1800000000>;
  64                 };
  65
  66                 cpu3: cpu@3 {
  67                         device_type = "cpu";
  68                         compatible = "arm,cortex-a15";
  69                         reg = <0x3>;
  70                         clock-frequency = <1800000000>;
  71                 };
  72         };
  73
  74         clock: clock-controller@10010000 {
  75                 compatible = "samsung,exynos5420-clock";
  76                 reg = <0x10010000 0x30000>;
  77                 #clock-cells = <1>;
  78         };
  79
  80         clock_audss: audss-clock-controller@3810000 {
  81                 compatible = "samsung,exynos5420-audss-clock";
  82                 reg = <0x03810000 0x0C>;
  83                 #clock-cells = <1>;
  84                 clocks = <&clock 148>;
  85                 clock-names = "sclk_audio";
  86         };
  87
  88         codec@11000000 {
  89                 compatible = "samsung,mfc-v7";
  90                 reg = <0x11000000 0x10000>;
  91                 interrupts = <0 96 0>;
  92                 clocks = <&clock 401>;
  93                 clock-names = "mfc";
  94         };
  95
  96         mmc_0: mmc@12200000 {
  97                 compatible = "samsung,exynos5420-dw-mshc-smu";
  98                 interrupts = <0 75 0>;
  99                 #address-cells = <1>;
 100                 #size-cells = <0>;
 101                 reg = <0x12200000 0x2000>;
 102                 clocks = <&clock 351>, <&clock 132>;
 103                 clock-names = "biu", "ciu";
 104                 fifo-depth = <0x40>;
 105                 status = "disabled";
 106         };
 107
 108         mmc_1: mmc@12210000 {
 109                 compatible = "samsung,exynos5420-dw-mshc-smu";
 110                 interrupts = <0 76 0>;
 111                 #address-cells = <1>;
 112                 #size-cells = <0>;
 113                 reg = <0x12210000 0x2000>;
 114                 clocks = <&clock 352>, <&clock 133>;
 115                 clock-names = "biu", "ciu";
 116                 fifo-depth = <0x40>;
 117                 status = "disabled";
 118         };
 119
 120         mmc_2: mmc@12220000 {
 121                 compatible = "samsung,exynos5420-dw-mshc";
 122                 interrupts = <0 77 0>;
 123                 #address-cells = <1>;
 124                 #size-cells = <0>;
 125                 reg = <0x12220000 0x1000>;
 126                 clocks = <&clock 353>, <&clock 134>;
 127                 clock-names = "biu", "ciu";
 128                 fifo-depth = <0x40>;
 129                 status = "disabled";
 130         };
 131
 132         mct@101C0000 {
 133                 compatible = "samsung,exynos4210-mct";
 134                 reg = <0x101C0000 0x800>;
 135                 interrupt-controller;
 136                 #interrups-cells = <1>;
 137                 interrupt-parent = <&mct_map>;
 138                 interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>;
 139                 clocks = <&clock 1>, <&clock 315>;
 140                 clock-names = "fin_pll", "mct";
 141
 142                 mct_map: mct-map {
 143                         #interrupt-cells = <1>;
 144                         #address-cells = <0>;
 145                         #size-cells = <0>;
 146                         interrupt-map = <0 &combiner 23 3>,
 147                                         <1 &combiner 23 4>,
 148                                         <2 &combiner 25 2>,
 149                                         <3 &combiner 25 3>,
 150                                         <4 &gic 0 120 0>,
 151                                         <5 &gic 0 121 0>,
 152                                         <6 &gic 0 122 0>,
 153                                         <7 &gic 0 123 0>;
 154                 };
 155         };
 156
 157         gsc_pd: power-domain@10044000 {
 158                 compatible = "samsung,exynos4210-pd";
 159                 reg = <0x10044000 0x20>;
 160         };
 161
 162         isp_pd: power-domain@10044020 {
 163                 compatible = "samsung,exynos4210-pd";
 164                 reg = <0x10044020 0x20>;
 165         };
 166
 167         mfc_pd: power-domain@10044060 {
 168                 compatible = "samsung,exynos4210-pd";
 169                 reg = <0x10044060 0x20>;
 170         };
 171
 172         disp_pd: power-domain@100440C0 {
 173                 compatible = "samsung,exynos4210-pd";
 174                 reg = <0x100440C0 0x20>;
 175         };
 176
 177         mau_pd: power-domain@100440E0 {
 178                 compatible = "samsung,exynos4210-pd";
 179                 reg = <0x100440E0 0x20>;
 180         };
 181
 182         g2d_pd: power-domain@10044100 {
 183                 compatible = "samsung,exynos4210-pd";
 184                 reg = <0x10044100 0x20>;
 185         };
 186
 187         msc_pd: power-domain@10044120 {
 188                 compatible = "samsung,exynos4210-pd";
 189                 reg = <0x10044120 0x20>;
 190         };
 191
 192         pinctrl_0: pinctrl@13400000 {
 193                 compatible = "samsung,exynos5420-pinctrl";
 194                 reg = <0x13400000 0x1000>;
 195                 interrupts = <0 45 0>;
 196
 197                 wakeup-interrupt-controller {
 198                         compatible = "samsung,exynos4210-wakeup-eint";
 199                         interrupt-parent = <&gic>;
 200                         interrupts = <0 32 0>;
 201                 };
 202         };
 203
 204         pinctrl_1: pinctrl@13410000 {
 205                 compatible = "samsung,exynos5420-pinctrl";
 206                 reg = <0x13410000 0x1000>;
 207                 interrupts = <0 78 0>;
 208         };
 209
 210         pinctrl_2: pinctrl@14000000 {
 211                 compatible = "samsung,exynos5420-pinctrl";
 212                 reg = <0x14000000 0x1000>;
 213                 interrupts = <0 46 0>;
 214         };
 215
 216         pinctrl_3: pinctrl@14010000 {
 217                 compatible = "samsung,exynos5420-pinctrl";
 218                 reg = <0x14010000 0x1000>;
 219                 interrupts = <0 50 0>;
 220         };
 221
 222         pinctrl_4: pinctrl@03860000 {
 223                 compatible = "samsung,exynos5420-pinctrl";
 224                 reg = <0x03860000 0x1000>;
 225                 interrupts = <0 47 0>;
 226         };
 227
 228         rtc@101E0000 {
 229                 clocks = <&clock 317>;
 230                 clock-names = "rtc";
 231                 status = "okay";
 232         };
 233
 234         serial@12C00000 {
 235                 clocks = <&clock 257>, <&clock 128>;
 236                 clock-names = "uart", "clk_uart_baud0";
 237         };
 238
 239         serial@12C10000 {
 240                 clocks = <&clock 258>, <&clock 129>;
 241                 clock-names = "uart", "clk_uart_baud0";
 242         };
 243
 244         serial@12C20000 {
 245                 clocks = <&clock 259>, <&clock 130>;
 246                 clock-names = "uart", "clk_uart_baud0";
 247         };
 248
 249         serial@12C30000 {
 250                 clocks = <&clock 260>, <&clock 131>;
 251                 clock-names = "uart", "clk_uart_baud0";
 252         };
 253
 254         dp_phy: video-phy@10040728 {
 255                 compatible = "samsung,exynos5250-dp-video-phy";
 256                 reg = <0x10040728 4>;
 257                 #phy-cells = <0>;
 258         };
 259
 260         dp-controller@145B0000 {
 261                 clocks = <&clock 412>;
 262                 clock-names = "dp";
 263                 phys = <&dp_phy>;
 264                 phy-names = "dp";
 265         };
 266
 267         fimd@14400000 {
 268                 samsung,power-domain = <&disp_pd>;
 269                 clocks = <&clock 147>, <&clock 421>;
 270                 clock-names = "sclk_fimd", "fimd";
 271         };
 272
 273         adc: adc@12D10000 {
 274                 compatible = "samsung,exynos-adc-v2";
 275                 reg = <0x12D10000 0x100>, <0x10040720 0x4>;
 276                 interrupts = <0 106 0>;
 277                 clocks = <&clock 270>;
 278                 clock-names = "adc";
 279                 #io-channel-cells = <1>;
 280                 io-channel-ranges;
 281                 status = "disabled";
 282         };
 283
 284         i2c_0: i2c@12C60000 {
 285                 compatible = "samsung,s3c2440-i2c";
 286                 reg = <0x12C60000 0x100>;
 287                 interrupts = <0 56 0>;
 288                 #address-cells = <1>;
 289                 #size-cells = <0>;
 290                 clocks = <&clock 261>;
 291                 clock-names = "i2c";
 292                 pinctrl-names = "default";
 293                 pinctrl-0 = <&i2c0_bus>;
 294                 status = "disabled";
 295         };
 296
 297         i2c_1: i2c@12C70000 {
 298                 compatible = "samsung,s3c2440-i2c";
 299                 reg = <0x12C70000 0x100>;
 300                 interrupts = <0 57 0>;
 301                 #address-cells = <1>;
 302                 #size-cells = <0>;
 303                 clocks = <&clock 262>;
 304                 clock-names = "i2c";
 305                 pinctrl-names = "default";
 306                 pinctrl-0 = <&i2c1_bus>;
 307                 status = "disabled";
 308         };
 309
 310         i2c_2: i2c@12C80000 {
 311                 compatible = "samsung,s3c2440-i2c";
 312                 reg = <0x12C80000 0x100>;
 313                 interrupts = <0 58 0>;
 314                 #address-cells = <1>;
 315                 #size-cells = <0>;
 316                 clocks = <&clock 263>;
 317                 clock-names = "i2c";
 318                 pinctrl-names = "default";
 319                 pinctrl-0 = <&i2c2_bus>;
 320                 status = "disabled";
 321         };
 322
 323         i2c_3: i2c@12C90000 {
 324                 compatible = "samsung,s3c2440-i2c";
 325                 reg = <0x12C90000 0x100>;
 326                 interrupts = <0 59 0>;
 327                 #address-cells = <1>;
 328                 #size-cells = <0>;
 329                 clocks = <&clock 264>;
 330                 clock-names = "i2c";
 331                 pinctrl-names = "default";
 332                 pinctrl-0 = <&i2c3_bus>;
 333                 status = "disabled";
 334         };
 335
 336         hdmi@14530000 {
 337                 compatible = "samsung,exynos4212-hdmi";
 338                 reg = <0x14530000 0x70000>;
 339                 interrupts = <0 95 0>;
 340                 clocks = <&clock 413>, <&clock 143>, <&clock 768>,
 341                         <&clock 158>, <&clock 640>;
 342                 clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
 343                         "sclk_hdmiphy", "mout_hdmi";
 344                 status = "disabled";
 345         };
 346
 347         mixer@14450000 {
 348                 compatible = "samsung,exynos5420-mixer";
 349                 reg = <0x14450000 0x10000>;
 350                 interrupts = <0 94 0>;
 351                 clocks = <&clock 431>, <&clock 143>;
 352                 clock-names = "mixer", "sclk_hdmi";
 353         };
 354
 355         gsc_0: video-scaler@13e00000 {
 356                 compatible = "samsung,exynos5-gsc";
 357                 reg = <0x13e00000 0x1000>;
 358                 interrupts = <0 85 0>;
 359                 clocks = <&clock 465>;
 360                 clock-names = "gscl";
 361                 samsung,power-domain = <&gsc_pd>;
 362         };
 363
 364         gsc_1: video-scaler@13e10000 {
 365                 compatible = "samsung,exynos5-gsc";
 366                 reg = <0x13e10000 0x1000>;
 367                 interrupts = <0 86 0>;
 368                 clocks = <&clock 466>;
 369                 clock-names = "gscl";
 370                 samsung,power-domain = <&gsc_pd>;
 371         };
 372 };