arch/arm/boot/dts/imx27.dtsi

   1 /*
   2  * Copyright 2012 Sascha Hauer, Pengutronix
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  */
  11
  12 #include "imx27-pinfunc.h"
  13
  14 #include <dt-bindings/clock/imx27-clock.h>
  15 #include <dt-bindings/gpio/gpio.h>
  16 #include <dt-bindings/input/input.h>
  17 #include <dt-bindings/interrupt-controller/irq.h>
  18
  19 / {
  20         #address-cells = <1>;
  21         #size-cells = <1>;
  22
  23         aliases {
  24                 ethernet0 = &fec;
  25                 gpio0 = &gpio1;
  26                 gpio1 = &gpio2;
  27                 gpio2 = &gpio3;
  28                 gpio3 = &gpio4;
  29                 gpio4 = &gpio5;
  30                 gpio5 = &gpio6;
  31                 i2c0 = &i2c1;
  32                 i2c1 = &i2c2;
  33                 serial0 = &uart1;
  34                 serial1 = &uart2;
  35                 serial2 = &uart3;
  36                 serial3 = &uart4;
  37                 serial4 = &uart5;
  38                 serial5 = &uart6;
  39                 spi0 = &cspi1;
  40                 spi1 = &cspi2;
  41                 spi2 = &cspi3;
  42         };
  43
  44         aitc: aitc-interrupt-controller@e0000000 {
  45                 compatible = "fsl,imx27-aitc", "fsl,avic";
  46                 interrupt-controller;
  47                 #interrupt-cells = <1>;
  48                 reg = <0x10040000 0x1000>;
  49         };
  50
  51         clocks {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54
  55                 osc26m {
  56                         compatible = "fsl,imx-osc26m", "fixed-clock";
  57                         #clock-cells = <0>;
  58                         clock-frequency = <26000000>;
  59                 };
  60         };
  61
  62         cpus {
  63                 #size-cells = <0>;
  64                 #address-cells = <1>;
  65
  66                 cpu: cpu@0 {
  67                         device_type = "cpu";
  68                         compatible = "arm,arm926ej-s";
  69                         operating-points = <
  70                                 /* kHz uV */
  71                                 266000 1300000
  72                                 399000 1450000
  73                         >;
  74                         clock-latency = <62500>;
  75                         clocks = <&clks IMX27_CLK_CPU_DIV>;
  76                         voltage-tolerance = <5>;
  77                 };
  78         };
  79
  80         soc {
  81                 #address-cells = <1>;
  82                 #size-cells = <1>;
  83                 compatible = "simple-bus";
  84                 interrupt-parent = <&aitc>;
  85                 ranges;
  86
  87                 aipi@10000000 { /* AIPI1 */
  88                         compatible = "fsl,aipi-bus", "simple-bus";
  89                         #address-cells = <1>;
  90                         #size-cells = <1>;
  91                         reg = <0x10000000 0x20000>;
  92                         ranges;
  93
  94                         dma: dma@10001000 {
  95                                 compatible = "fsl,imx27-dma";
  96                                 reg = <0x10001000 0x1000>;
  97                                 interrupts = <32>;
  98                                 clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
  99                                          <&clks IMX27_CLK_DMA_AHB_GATE>;
 100                                 clock-names = "ipg", "ahb";
 101                                 #dma-cells = <1>;
 102                                 #dma-channels = <16>;
 103                         };
 104
 105                         wdog: wdog@10002000 {
 106                                 compatible = "fsl,imx27-wdt", "fsl,imx21-wdt";
 107                                 reg = <0x10002000 0x1000>;
 108                                 interrupts = <27>;
 109                                 clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
 110                         };
 111
 112                         gpt1: timer@10003000 {
 113                                 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
 114                                 reg = <0x10003000 0x1000>;
 115                                 interrupts = <26>;
 116                                 clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
 117                                          <&clks IMX27_CLK_PER1_GATE>;
 118                                 clock-names = "ipg", "per";
 119                         };
 120
 121                         gpt2: timer@10004000 {
 122                                 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
 123                                 reg = <0x10004000 0x1000>;
 124                                 interrupts = <25>;
 125                                 clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
 126                                          <&clks IMX27_CLK_PER1_GATE>;
 127                                 clock-names = "ipg", "per";
 128                         };
 129
 130                         gpt3: timer@10005000 {
 131                                 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
 132                                 reg = <0x10005000 0x1000>;
 133                                 interrupts = <24>;
 134                                 clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
 135                                          <&clks IMX27_CLK_PER1_GATE>;
 136                                 clock-names = "ipg", "per";
 137                         };
 138
 139                         pwm: pwm@10006000 {
 140                                 #pwm-cells = <2>;
 141                                 compatible = "fsl,imx27-pwm";
 142                                 reg = <0x10006000 0x1000>;
 143                                 interrupts = <23>;
 144                                 clocks = <&clks IMX27_CLK_PWM_IPG_GATE>,
 145                                          <&clks IMX27_CLK_PER1_GATE>;
 146                                 clock-names = "ipg", "per";
 147                         };
 148
 149                         rtc: rtc@10007000 {
 150                                 compatible = "fsl,imx21-rtc";
 151                                 reg = <0x10007000 0x1000>;
 152                                 interrupts = <22>;
 153                                 clocks = <&clks IMX27_CLK_CKIL>,
 154                                          <&clks IMX27_CLK_RTC_IPG_GATE>;
 155                                 clock-names = "ref", "ipg";
 156                         };
 157
 158                         kpp: kpp@10008000 {
 159                                 compatible = "fsl,imx27-kpp", "fsl,imx21-kpp";
 160                                 reg = <0x10008000 0x1000>;
 161                                 interrupts = <21>;
 162                                 clocks = <&clks IMX27_CLK_KPP_IPG_GATE>;
 163                                 status = "disabled";
 164                         };
 165
 166                         owire: owire@10009000 {
 167                                 compatible = "fsl,imx27-owire", "fsl,imx21-owire";
 168                                 reg = <0x10009000 0x1000>;
 169                                 clocks = <&clks IMX27_CLK_OWIRE_IPG_GATE>;
 170                                 status = "disabled";
 171                         };
 172
 173                         uart1: serial@1000a000 {
 174                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 175                                 reg = <0x1000a000 0x1000>;
 176                                 interrupts = <20>;
 177                                 clocks = <&clks IMX27_CLK_UART1_IPG_GATE>,
 178                                          <&clks IMX27_CLK_PER1_GATE>;
 179                                 clock-names = "ipg", "per";
 180                                 status = "disabled";
 181                         };
 182
 183                         uart2: serial@1000b000 {
 184                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 185                                 reg = <0x1000b000 0x1000>;
 186                                 interrupts = <19>;
 187                                 clocks = <&clks IMX27_CLK_UART2_IPG_GATE>,
 188                                          <&clks IMX27_CLK_PER1_GATE>;
 189                                 clock-names = "ipg", "per";
 190                                 status = "disabled";
 191                         };
 192
 193                         uart3: serial@1000c000 {
 194                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 195                                 reg = <0x1000c000 0x1000>;
 196                                 interrupts = <18>;
 197                                 clocks = <&clks IMX27_CLK_UART3_IPG_GATE>,
 198                                          <&clks IMX27_CLK_PER1_GATE>;
 199                                 clock-names = "ipg", "per";
 200                                 status = "disabled";
 201                         };
 202
 203                         uart4: serial@1000d000 {
 204                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 205                                 reg = <0x1000d000 0x1000>;
 206                                 interrupts = <17>;
 207                                 clocks = <&clks IMX27_CLK_UART4_IPG_GATE>,
 208                                          <&clks IMX27_CLK_PER1_GATE>;
 209                                 clock-names = "ipg", "per";
 210                                 status = "disabled";
 211                         };
 212
 213                         cspi1: cspi@1000e000 {
 214                                 #address-cells = <1>;
 215                                 #size-cells = <0>;
 216                                 compatible = "fsl,imx27-cspi";
 217                                 reg = <0x1000e000 0x1000>;
 218                                 interrupts = <16>;
 219                                 clocks = <&clks IMX27_CLK_CSPI1_IPG_GATE>,
 220                                          <&clks IMX27_CLK_PER2_GATE>;
 221                                 clock-names = "ipg", "per";
 222                                 status = "disabled";
 223                         };
 224
 225                         cspi2: cspi@1000f000 {
 226                                 #address-cells = <1>;
 227                                 #size-cells = <0>;
 228                                 compatible = "fsl,imx27-cspi";
 229                                 reg = <0x1000f000 0x1000>;
 230                                 interrupts = <15>;
 231                                 clocks = <&clks IMX27_CLK_CSPI2_IPG_GATE>,
 232                                          <&clks IMX27_CLK_PER2_GATE>;
 233                                 clock-names = "ipg", "per";
 234                                 status = "disabled";
 235                         };
 236
 237                         ssi1: ssi@10010000 {
 238                                 #sound-dai-cells = <0>;
 239                                 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
 240                                 reg = <0x10010000 0x1000>;
 241                                 interrupts = <14>;
 242                                 clocks = <&clks IMX27_CLK_SSI1_IPG_GATE>;
 243                                 dmas = <&dma 12>, <&dma 13>, <&dma 14>, <&dma 15>;
 244                                 dma-names = "rx0", "tx0", "rx1", "tx1";
 245                                 fsl,fifo-depth = <8>;
 246                                 status = "disabled";
 247                         };
 248
 249                         ssi2: ssi@10011000 {
 250                                 #sound-dai-cells = <0>;
 251                                 compatible = "fsl,imx27-ssi", "fsl,imx21-ssi";
 252                                 reg = <0x10011000 0x1000>;
 253                                 interrupts = <13>;
 254                                 clocks = <&clks IMX27_CLK_SSI2_IPG_GATE>;
 255                                 dmas = <&dma 8>, <&dma 9>, <&dma 10>, <&dma 11>;
 256                                 dma-names = "rx0", "tx0", "rx1", "tx1";
 257                                 fsl,fifo-depth = <8>;
 258                                 status = "disabled";
 259                         };
 260
 261                         i2c1: i2c@10012000 {
 262                                 #address-cells = <1>;
 263                                 #size-cells = <0>;
 264                                 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
 265                                 reg = <0x10012000 0x1000>;
 266                                 interrupts = <12>;
 267                                 clocks = <&clks IMX27_CLK_I2C1_IPG_GATE>;
 268                                 status = "disabled";
 269                         };
 270
 271                         sdhci1: sdhci@10013000 {
 272                                 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
 273                                 reg = <0x10013000 0x1000>;
 274                                 interrupts = <11>;
 275                                 clocks = <&clks IMX27_CLK_SDHC1_IPG_GATE>,
 276                                          <&clks IMX27_CLK_PER2_GATE>;
 277                                 clock-names = "ipg", "per";
 278                                 dmas = <&dma 7>;
 279                                 dma-names = "rx-tx";
 280                                 status = "disabled";
 281                         };
 282
 283                         sdhci2: sdhci@10014000 {
 284                                 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
 285                                 reg = <0x10014000 0x1000>;
 286                                 interrupts = <10>;
 287                                 clocks = <&clks IMX27_CLK_SDHC2_IPG_GATE>,
 288                                          <&clks IMX27_CLK_PER2_GATE>;
 289                                 clock-names = "ipg", "per";
 290                                 dmas = <&dma 6>;
 291                                 dma-names = "rx-tx";
 292                                 status = "disabled";
 293                         };
 294
 295                         iomuxc: iomuxc@10015000 {
 296                                 compatible = "fsl,imx27-iomuxc";
 297                                 reg = <0x10015000 0x600>;
 298                                 #address-cells = <1>;
 299                                 #size-cells = <1>;
 300                                 ranges;
 301
 302                                 gpio1: gpio@10015000 {
 303                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 304                                         reg = <0x10015000 0x100>;
 305                                         clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
 306                                         interrupts = <8>;
 307                                         gpio-controller;
 308                                         #gpio-cells = <2>;
 309                                         interrupt-controller;
 310                                         #interrupt-cells = <2>;
 311                                 };
 312
 313                                 gpio2: gpio@10015100 {
 314                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 315                                         reg = <0x10015100 0x100>;
 316                                         clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
 317                                         interrupts = <8>;
 318                                         gpio-controller;
 319                                         #gpio-cells = <2>;
 320                                         interrupt-controller;
 321                                         #interrupt-cells = <2>;
 322                                 };
 323
 324                                 gpio3: gpio@10015200 {
 325                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 326                                         reg = <0x10015200 0x100>;
 327                                         clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
 328                                         interrupts = <8>;
 329                                         gpio-controller;
 330                                         #gpio-cells = <2>;
 331                                         interrupt-controller;
 332                                         #interrupt-cells = <2>;
 333                                 };
 334
 335                                 gpio4: gpio@10015300 {
 336                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 337                                         reg = <0x10015300 0x100>;
 338                                         clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
 339                                         interrupts = <8>;
 340                                         gpio-controller;
 341                                         #gpio-cells = <2>;
 342                                         interrupt-controller;
 343                                         #interrupt-cells = <2>;
 344                                 };
 345
 346                                 gpio5: gpio@10015400 {
 347                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 348                                         reg = <0x10015400 0x100>;
 349                                         clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
 350                                         interrupts = <8>;
 351                                         gpio-controller;
 352                                         #gpio-cells = <2>;
 353                                         interrupt-controller;
 354                                         #interrupt-cells = <2>;
 355                                 };
 356
 357                                 gpio6: gpio@10015500 {
 358                                         compatible = "fsl,imx27-gpio", "fsl,imx21-gpio";
 359                                         reg = <0x10015500 0x100>;
 360                                         clocks = <&clks IMX27_CLK_GPIO_IPG_GATE>;
 361                                         interrupts = <8>;
 362                                         gpio-controller;
 363                                         #gpio-cells = <2>;
 364                                         interrupt-controller;
 365                                         #interrupt-cells = <2>;
 366                                 };
 367                         };
 368
 369                         audmux: audmux@10016000 {
 370                                 compatible = "fsl,imx27-audmux", "fsl,imx21-audmux";
 371                                 reg = <0x10016000 0x1000>;
 372                                 clocks = <&clks IMX27_CLK_DUMMY>;
 373                                 clock-names = "audmux";
 374                                 status = "disabled";
 375                         };
 376
 377                         cspi3: cspi@10017000 {
 378                                 #address-cells = <1>;
 379                                 #size-cells = <0>;
 380                                 compatible = "fsl,imx27-cspi";
 381                                 reg = <0x10017000 0x1000>;
 382                                 interrupts = <6>;
 383                                 clocks = <&clks IMX27_CLK_CSPI3_IPG_GATE>,
 384                                          <&clks IMX27_CLK_PER2_GATE>;
 385                                 clock-names = "ipg", "per";
 386                                 status = "disabled";
 387                         };
 388
 389                         gpt4: timer@10019000 {
 390                                 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
 391                                 reg = <0x10019000 0x1000>;
 392                                 interrupts = <4>;
 393                                 clocks = <&clks IMX27_CLK_GPT4_IPG_GATE>,
 394                                          <&clks IMX27_CLK_PER1_GATE>;
 395                                 clock-names = "ipg", "per";
 396                         };
 397
 398                         gpt5: timer@1001a000 {
 399                                 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
 400                                 reg = <0x1001a000 0x1000>;
 401                                 interrupts = <3>;
 402                                 clocks = <&clks IMX27_CLK_GPT5_IPG_GATE>,
 403                                          <&clks IMX27_CLK_PER1_GATE>;
 404                                 clock-names = "ipg", "per";
 405                         };
 406
 407                         uart5: serial@1001b000 {
 408                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 409                                 reg = <0x1001b000 0x1000>;
 410                                 interrupts = <49>;
 411                                 clocks = <&clks IMX27_CLK_UART5_IPG_GATE>,
 412                                          <&clks IMX27_CLK_PER1_GATE>;
 413                                 clock-names = "ipg", "per";
 414                                 status = "disabled";
 415                         };
 416
 417                         uart6: serial@1001c000 {
 418                                 compatible = "fsl,imx27-uart", "fsl,imx21-uart";
 419                                 reg = <0x1001c000 0x1000>;
 420                                 interrupts = <48>;
 421                                 clocks = <&clks IMX27_CLK_UART6_IPG_GATE>,
 422                                          <&clks IMX27_CLK_PER1_GATE>;
 423                                 clock-names = "ipg", "per";
 424                                 status = "disabled";
 425                         };
 426
 427                         i2c2: i2c@1001d000 {
 428                                 #address-cells = <1>;
 429                                 #size-cells = <0>;
 430                                 compatible = "fsl,imx27-i2c", "fsl,imx21-i2c";
 431                                 reg = <0x1001d000 0x1000>;
 432                                 interrupts = <1>;
 433                                 clocks = <&clks IMX27_CLK_I2C2_IPG_GATE>;
 434                                 status = "disabled";
 435                         };
 436
 437                         sdhci3: sdhci@1001e000 {
 438                                 compatible = "fsl,imx27-mmc", "fsl,imx21-mmc";
 439                                 reg = <0x1001e000 0x1000>;
 440                                 interrupts = <9>;
 441                                 clocks = <&clks IMX27_CLK_SDHC3_IPG_GATE>,
 442                                          <&clks IMX27_CLK_PER2_GATE>;
 443                                 clock-names = "ipg", "per";
 444                                 dmas = <&dma 36>;
 445                                 dma-names = "rx-tx";
 446                                 status = "disabled";
 447                         };
 448
 449                         gpt6: timer@1001f000 {
 450                                 compatible = "fsl,imx27-gpt", "fsl,imx21-gpt";
 451                                 reg = <0x1001f000 0x1000>;
 452                                 interrupts = <2>;
 453                                 clocks = <&clks IMX27_CLK_GPT6_IPG_GATE>,
 454                                          <&clks IMX27_CLK_PER1_GATE>;
 455                                 clock-names = "ipg", "per";
 456                         };
 457                 };
 458
 459                 aipi@10020000 { /* AIPI2 */
 460                         compatible = "fsl,aipi-bus", "simple-bus";
 461                         #address-cells = <1>;
 462                         #size-cells = <1>;
 463                         reg = <0x10020000 0x20000>;
 464                         ranges;
 465
 466                         fb: fb@10021000 {
 467                                 compatible = "fsl,imx27-fb", "fsl,imx21-fb";
 468                                 interrupts = <61>;
 469                                 reg = <0x10021000 0x1000>;
 470                                 clocks = <&clks IMX27_CLK_LCDC_IPG_GATE>,
 471                                          <&clks IMX27_CLK_LCDC_AHB_GATE>,
 472                                          <&clks IMX27_CLK_PER3_GATE>;
 473                                 clock-names = "ipg", "ahb", "per";
 474                                 status = "disabled";
 475                         };
 476
 477                         coda: coda@10023000 {
 478                                 compatible = "fsl,imx27-vpu", "cnm,codadx6";
 479                                 reg = <0x10023000 0x0200>;
 480                                 interrupts = <53>;
 481                                 clocks = <&clks IMX27_CLK_VPU_BAUD_GATE>,
 482                                          <&clks IMX27_CLK_VPU_AHB_GATE>;
 483                                 clock-names = "per", "ahb";
 484                                 iram = <&iram>;
 485                         };
 486
 487                         usbotg: usb@10024000 {
 488                                 compatible = "fsl,imx27-usb";
 489                                 reg = <0x10024000 0x200>;
 490                                 interrupts = <56>;
 491                                 clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
 492                                         <&clks IMX27_CLK_USB_AHB_GATE>,
 493                                         <&clks IMX27_CLK_USB_DIV>;
 494                                 clock-names = "ipg", "ahb", "per";
 495                                 fsl,usbmisc = <&usbmisc 0>;
 496                                 status = "disabled";
 497                         };
 498
 499                         usbh1: usb@10024200 {
 500                                 compatible = "fsl,imx27-usb";
 501                                 reg = <0x10024200 0x200>;
 502                                 interrupts = <54>;
 503                                 clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
 504                                         <&clks IMX27_CLK_USB_AHB_GATE>,
 505                                         <&clks IMX27_CLK_USB_DIV>;
 506                                 clock-names = "ipg", "ahb", "per";
 507                                 fsl,usbmisc = <&usbmisc 1>;
 508                                 dr_mode = "host";
 509                                 status = "disabled";
 510                         };
 511
 512                         usbh2: usb@10024400 {
 513                                 compatible = "fsl,imx27-usb";
 514                                 reg = <0x10024400 0x200>;
 515                                 interrupts = <55>;
 516                                 clocks = <&clks IMX27_CLK_USB_IPG_GATE>,
 517                                         <&clks IMX27_CLK_USB_AHB_GATE>,
 518                                         <&clks IMX27_CLK_USB_DIV>;
 519                                 clock-names = "ipg", "ahb", "per";
 520                                 fsl,usbmisc = <&usbmisc 2>;
 521                                 dr_mode = "host";
 522                                 status = "disabled";
 523                         };
 524
 525                         usbmisc: usbmisc@10024600 {
 526                                 #index-cells = <1>;
 527                                 compatible = "fsl,imx27-usbmisc";
 528                                 reg = <0x10024600 0x200>;
 529                         };
 530
 531                         sahara2: sahara@10025000 {
 532                                 compatible = "fsl,imx27-sahara";
 533                                 reg = <0x10025000 0x1000>;
 534                                 interrupts = <59>;
 535                                 clocks = <&clks IMX27_CLK_SAHARA_IPG_GATE>,
 536                                          <&clks IMX27_CLK_SAHARA_AHB_GATE>;
 537                                 clock-names = "ipg", "ahb";
 538                         };
 539
 540                         clks: ccm@10027000{
 541                                 compatible = "fsl,imx27-ccm";
 542                                 reg = <0x10027000 0x1000>;
 543                                 #clock-cells = <1>;
 544                         };
 545
 546                         iim: iim@10028000 {
 547                                 compatible = "fsl,imx27-iim";
 548                                 reg = <0x10028000 0x1000>;
 549                                 interrupts = <62>;
 550                                 clocks = <&clks IMX27_CLK_IIM_IPG_GATE>;
 551                         };
 552
 553                         fec: ethernet@1002b000 {
 554                                 compatible = "fsl,imx27-fec";
 555                                 reg = <0x1002b000 0x1000>;
 556                                 interrupts = <50>;
 557                                 clocks = <&clks IMX27_CLK_FEC_IPG_GATE>,
 558                                          <&clks IMX27_CLK_FEC_AHB_GATE>;
 559                                 clock-names = "ipg", "ahb";
 560                                 status = "disabled";
 561                         };
 562                 };
 563
 564                 nfc: nand@d8000000 {
 565                         #address-cells = <1>;
 566                         #size-cells = <1>;
 567                         compatible = "fsl,imx27-nand";
 568                         reg = <0xd8000000 0x1000>;
 569                         interrupts = <29>;
 570                         clocks = <&clks IMX27_CLK_NFC_BAUD_GATE>;
 571                         status = "disabled";
 572                 };
 573
 574                 weim: weim@d8002000 {
 575                         #address-cells = <2>;
 576                         #size-cells = <1>;
 577                         compatible = "fsl,imx27-weim";
 578                         reg = <0xd8002000 0x1000>;
 579                         clocks = <&clks IMX27_CLK_EMI_AHB_GATE>;
 580                         ranges = <
 581                                 0 0 0xc0000000 0x08000000
 582                                 1 0 0xc8000000 0x08000000
 583                                 2 0 0xd0000000 0x02000000
 584                                 3 0 0xd2000000 0x02000000
 585                                 4 0 0xd4000000 0x02000000
 586                                 5 0 0xd6000000 0x02000000
 587                         >;
 588                         status = "disabled";
 589                 };
 590
 591                 iram: iram@ffff4c00 {
 592                         compatible = "mmio-sram";
 593                         reg = <0xffff4c00 0xb400>;
 594                 };
 595         };
 596 };