2 * Copyright 2012 Freescale Semiconductor, Inc.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include "skeleton.dtsi"
13 #include "imx28-pinfunc.h"
16 interrupt-parent = <&icoll>;
42 compatible = "arm,arm926ej-s";
48 compatible = "simple-bus";
51 reg = <0x80000000 0x80000>;
55 compatible = "simple-bus";
58 reg = <0x80000000 0x3c900>;
61 icoll: interrupt-controller@80000000 {
62 compatible = "fsl,imx28-icoll", "fsl,icoll";
64 #interrupt-cells = <1>;
65 reg = <0x80000000 0x2000>;
68 hsadc: hsadc@80002000 {
69 reg = <0x80002000 0x2000>;
71 dmas = <&dma_apbh 12>;
76 dma_apbh: dma-apbh@80004000 {
77 compatible = "fsl,imx28-dma-apbh";
78 reg = <0x80004000 0x2000>;
79 interrupts = <82 83 84 85
83 interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3",
84 "gpmi0", "gmpi1", "gpmi2", "gmpi3",
85 "gpmi4", "gmpi5", "gpmi6", "gmpi7",
86 "hsadc", "lcdif", "empty", "empty";
92 perfmon: perfmon@80006000 {
93 reg = <0x80006000 0x800>;
98 gpmi: gpmi-nand@8000c000 {
99 compatible = "fsl,imx28-gpmi-nand";
100 #address-cells = <1>;
102 reg = <0x8000c000 0x2000>, <0x8000a000 0x2000>;
103 reg-names = "gpmi-nand", "bch";
105 interrupt-names = "bch";
107 clock-names = "gpmi_io";
108 dmas = <&dma_apbh 4>;
114 #address-cells = <1>;
116 reg = <0x80010000 0x2000>;
119 dmas = <&dma_apbh 0>;
125 #address-cells = <1>;
127 reg = <0x80012000 0x2000>;
130 dmas = <&dma_apbh 1>;
136 #address-cells = <1>;
138 reg = <0x80014000 0x2000>;
141 dmas = <&dma_apbh 2>;
147 #address-cells = <1>;
149 reg = <0x80016000 0x2000>;
152 dmas = <&dma_apbh 3>;
157 pinctrl: pinctrl@80018000 {
158 #address-cells = <1>;
160 compatible = "fsl,imx28-pinctrl", "simple-bus";
161 reg = <0x80018000 0x2000>;
164 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
168 interrupt-controller;
169 #interrupt-cells = <2>;
173 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
177 interrupt-controller;
178 #interrupt-cells = <2>;
182 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
186 interrupt-controller;
187 #interrupt-cells = <2>;
191 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
195 interrupt-controller;
196 #interrupt-cells = <2>;
200 compatible = "fsl,imx28-gpio", "fsl,mxs-gpio";
204 interrupt-controller;
205 #interrupt-cells = <2>;
208 duart_pins_a: duart@0 {
211 MX28_PAD_PWM0__DUART_RX
212 MX28_PAD_PWM1__DUART_TX
214 fsl,drive-strength = <0>;
219 duart_pins_b: duart@1 {
222 MX28_PAD_AUART0_CTS__DUART_RX
223 MX28_PAD_AUART0_RTS__DUART_TX
225 fsl,drive-strength = <0>;
230 duart_4pins_a: duart-4pins@0 {
233 MX28_PAD_AUART0_CTS__DUART_RX
234 MX28_PAD_AUART0_RTS__DUART_TX
235 MX28_PAD_AUART0_RX__DUART_CTS
236 MX28_PAD_AUART0_TX__DUART_RTS
238 fsl,drive-strength = <0>;
243 gpmi_pins_a: gpmi-nand@0 {
246 MX28_PAD_GPMI_D00__GPMI_D0
247 MX28_PAD_GPMI_D01__GPMI_D1
248 MX28_PAD_GPMI_D02__GPMI_D2
249 MX28_PAD_GPMI_D03__GPMI_D3
250 MX28_PAD_GPMI_D04__GPMI_D4
251 MX28_PAD_GPMI_D05__GPMI_D5
252 MX28_PAD_GPMI_D06__GPMI_D6
253 MX28_PAD_GPMI_D07__GPMI_D7
254 MX28_PAD_GPMI_CE0N__GPMI_CE0N
255 MX28_PAD_GPMI_RDY0__GPMI_READY0
256 MX28_PAD_GPMI_RDN__GPMI_RDN
257 MX28_PAD_GPMI_WRN__GPMI_WRN
258 MX28_PAD_GPMI_ALE__GPMI_ALE
259 MX28_PAD_GPMI_CLE__GPMI_CLE
260 MX28_PAD_GPMI_RESETN__GPMI_RESETN
262 fsl,drive-strength = <0>;
267 gpmi_status_cfg: gpmi-status-cfg {
269 MX28_PAD_GPMI_RDN__GPMI_RDN
270 MX28_PAD_GPMI_WRN__GPMI_WRN
271 MX28_PAD_GPMI_RESETN__GPMI_RESETN
273 fsl,drive-strength = <2>;
276 auart0_pins_a: auart0@0 {
279 MX28_PAD_AUART0_RX__AUART0_RX
280 MX28_PAD_AUART0_TX__AUART0_TX
281 MX28_PAD_AUART0_CTS__AUART0_CTS
282 MX28_PAD_AUART0_RTS__AUART0_RTS
284 fsl,drive-strength = <0>;
289 auart0_2pins_a: auart0-2pins@0 {
292 MX28_PAD_AUART0_RX__AUART0_RX
293 MX28_PAD_AUART0_TX__AUART0_TX
295 fsl,drive-strength = <0>;
300 auart1_pins_a: auart1@0 {
303 MX28_PAD_AUART1_RX__AUART1_RX
304 MX28_PAD_AUART1_TX__AUART1_TX
305 MX28_PAD_AUART1_CTS__AUART1_CTS
306 MX28_PAD_AUART1_RTS__AUART1_RTS
308 fsl,drive-strength = <0>;
313 auart1_2pins_a: auart1-2pins@0 {
316 MX28_PAD_AUART1_RX__AUART1_RX
317 MX28_PAD_AUART1_TX__AUART1_TX
319 fsl,drive-strength = <0>;
324 auart2_2pins_a: auart2-2pins@0 {
327 MX28_PAD_SSP2_SCK__AUART2_RX
328 MX28_PAD_SSP2_MOSI__AUART2_TX
330 fsl,drive-strength = <0>;
335 auart2_2pins_b: auart2-2pins@1 {
338 MX28_PAD_AUART2_RX__AUART2_RX
339 MX28_PAD_AUART2_TX__AUART2_TX
341 fsl,drive-strength = <0>;
346 auart3_pins_a: auart3@0 {
349 MX28_PAD_AUART3_RX__AUART3_RX
350 MX28_PAD_AUART3_TX__AUART3_TX
351 MX28_PAD_AUART3_CTS__AUART3_CTS
352 MX28_PAD_AUART3_RTS__AUART3_RTS
354 fsl,drive-strength = <0>;
359 auart3_2pins_a: auart3-2pins@0 {
362 MX28_PAD_SSP2_MISO__AUART3_RX
363 MX28_PAD_SSP2_SS0__AUART3_TX
365 fsl,drive-strength = <0>;
370 auart3_2pins_b: auart3-2pins@1 {
373 MX28_PAD_AUART3_RX__AUART3_RX
374 MX28_PAD_AUART3_TX__AUART3_TX
376 fsl,drive-strength = <0>;
381 auart4_2pins_a: auart4@0 {
384 MX28_PAD_SSP3_SCK__AUART4_TX
385 MX28_PAD_SSP3_MOSI__AUART4_RX
387 fsl,drive-strength = <0>;
392 mac0_pins_a: mac0@0 {
395 MX28_PAD_ENET0_MDC__ENET0_MDC
396 MX28_PAD_ENET0_MDIO__ENET0_MDIO
397 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN
398 MX28_PAD_ENET0_RXD0__ENET0_RXD0
399 MX28_PAD_ENET0_RXD1__ENET0_RXD1
400 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN
401 MX28_PAD_ENET0_TXD0__ENET0_TXD0
402 MX28_PAD_ENET0_TXD1__ENET0_TXD1
403 MX28_PAD_ENET_CLK__CLKCTRL_ENET
405 fsl,drive-strength = <1>;
410 mac1_pins_a: mac1@0 {
413 MX28_PAD_ENET0_CRS__ENET1_RX_EN
414 MX28_PAD_ENET0_RXD2__ENET1_RXD0
415 MX28_PAD_ENET0_RXD3__ENET1_RXD1
416 MX28_PAD_ENET0_COL__ENET1_TX_EN
417 MX28_PAD_ENET0_TXD2__ENET1_TXD0
418 MX28_PAD_ENET0_TXD3__ENET1_TXD1
420 fsl,drive-strength = <1>;
425 mmc0_8bit_pins_a: mmc0-8bit@0 {
428 MX28_PAD_SSP0_DATA0__SSP0_D0
429 MX28_PAD_SSP0_DATA1__SSP0_D1
430 MX28_PAD_SSP0_DATA2__SSP0_D2
431 MX28_PAD_SSP0_DATA3__SSP0_D3
432 MX28_PAD_SSP0_DATA4__SSP0_D4
433 MX28_PAD_SSP0_DATA5__SSP0_D5
434 MX28_PAD_SSP0_DATA6__SSP0_D6
435 MX28_PAD_SSP0_DATA7__SSP0_D7
436 MX28_PAD_SSP0_CMD__SSP0_CMD
437 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
438 MX28_PAD_SSP0_SCK__SSP0_SCK
440 fsl,drive-strength = <1>;
445 mmc0_4bit_pins_a: mmc0-4bit@0 {
448 MX28_PAD_SSP0_DATA0__SSP0_D0
449 MX28_PAD_SSP0_DATA1__SSP0_D1
450 MX28_PAD_SSP0_DATA2__SSP0_D2
451 MX28_PAD_SSP0_DATA3__SSP0_D3
452 MX28_PAD_SSP0_CMD__SSP0_CMD
453 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
454 MX28_PAD_SSP0_SCK__SSP0_SCK
456 fsl,drive-strength = <1>;
461 mmc0_cd_cfg: mmc0-cd-cfg {
463 MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT
468 mmc0_sck_cfg: mmc0-sck-cfg {
470 MX28_PAD_SSP0_SCK__SSP0_SCK
472 fsl,drive-strength = <2>;
476 i2c0_pins_a: i2c0@0 {
479 MX28_PAD_I2C0_SCL__I2C0_SCL
480 MX28_PAD_I2C0_SDA__I2C0_SDA
482 fsl,drive-strength = <1>;
487 i2c0_pins_b: i2c0@1 {
490 MX28_PAD_AUART0_RX__I2C0_SCL
491 MX28_PAD_AUART0_TX__I2C0_SDA
493 fsl,drive-strength = <1>;
498 i2c1_pins_a: i2c1@0 {
501 MX28_PAD_PWM0__I2C1_SCL
502 MX28_PAD_PWM1__I2C1_SDA
504 fsl,drive-strength = <1>;
509 saif0_pins_a: saif0@0 {
512 MX28_PAD_SAIF0_MCLK__SAIF0_MCLK
513 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
514 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
515 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
517 fsl,drive-strength = <2>;
522 saif0_pins_b: saif0@1 {
525 MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK
526 MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK
527 MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0
529 fsl,drive-strength = <2>;
534 saif1_pins_a: saif1@0 {
537 MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0
539 fsl,drive-strength = <2>;
544 pwm0_pins_a: pwm0@0 {
549 fsl,drive-strength = <0>;
554 pwm2_pins_a: pwm2@0 {
559 fsl,drive-strength = <0>;
564 pwm3_pins_a: pwm3@0 {
569 fsl,drive-strength = <0>;
574 pwm3_pins_b: pwm3@1 {
577 MX28_PAD_SAIF0_MCLK__PWM_3
579 fsl,drive-strength = <0>;
584 pwm4_pins_a: pwm4@0 {
589 fsl,drive-strength = <0>;
594 lcdif_24bit_pins_a: lcdif-24bit@0 {
597 MX28_PAD_LCD_D00__LCD_D0
598 MX28_PAD_LCD_D01__LCD_D1
599 MX28_PAD_LCD_D02__LCD_D2
600 MX28_PAD_LCD_D03__LCD_D3
601 MX28_PAD_LCD_D04__LCD_D4
602 MX28_PAD_LCD_D05__LCD_D5
603 MX28_PAD_LCD_D06__LCD_D6
604 MX28_PAD_LCD_D07__LCD_D7
605 MX28_PAD_LCD_D08__LCD_D8
606 MX28_PAD_LCD_D09__LCD_D9
607 MX28_PAD_LCD_D10__LCD_D10
608 MX28_PAD_LCD_D11__LCD_D11
609 MX28_PAD_LCD_D12__LCD_D12
610 MX28_PAD_LCD_D13__LCD_D13
611 MX28_PAD_LCD_D14__LCD_D14
612 MX28_PAD_LCD_D15__LCD_D15
613 MX28_PAD_LCD_D16__LCD_D16
614 MX28_PAD_LCD_D17__LCD_D17
615 MX28_PAD_LCD_D18__LCD_D18
616 MX28_PAD_LCD_D19__LCD_D19
617 MX28_PAD_LCD_D20__LCD_D20
618 MX28_PAD_LCD_D21__LCD_D21
619 MX28_PAD_LCD_D22__LCD_D22
620 MX28_PAD_LCD_D23__LCD_D23
622 fsl,drive-strength = <0>;
627 lcdif_16bit_pins_a: lcdif-16bit@0 {
630 MX28_PAD_LCD_D00__LCD_D0
631 MX28_PAD_LCD_D01__LCD_D1
632 MX28_PAD_LCD_D02__LCD_D2
633 MX28_PAD_LCD_D03__LCD_D3
634 MX28_PAD_LCD_D04__LCD_D4
635 MX28_PAD_LCD_D05__LCD_D5
636 MX28_PAD_LCD_D06__LCD_D6
637 MX28_PAD_LCD_D07__LCD_D7
638 MX28_PAD_LCD_D08__LCD_D8
639 MX28_PAD_LCD_D09__LCD_D9
640 MX28_PAD_LCD_D10__LCD_D10
641 MX28_PAD_LCD_D11__LCD_D11
642 MX28_PAD_LCD_D12__LCD_D12
643 MX28_PAD_LCD_D13__LCD_D13
644 MX28_PAD_LCD_D14__LCD_D14
645 MX28_PAD_LCD_D15__LCD_D15
647 fsl,drive-strength = <0>;
652 lcdif_sync_pins_a: lcdif-sync@0 {
655 MX28_PAD_LCD_RS__LCD_DOTCLK
656 MX28_PAD_LCD_CS__LCD_ENABLE
657 MX28_PAD_LCD_RD_E__LCD_VSYNC
658 MX28_PAD_LCD_WR_RWN__LCD_HSYNC
660 fsl,drive-strength = <0>;
665 can0_pins_a: can0@0 {
668 MX28_PAD_GPMI_RDY2__CAN0_TX
669 MX28_PAD_GPMI_RDY3__CAN0_RX
671 fsl,drive-strength = <0>;
676 can1_pins_a: can1@0 {
679 MX28_PAD_GPMI_CE2N__CAN1_TX
680 MX28_PAD_GPMI_CE3N__CAN1_RX
682 fsl,drive-strength = <0>;
687 spi2_pins_a: spi2@0 {
690 MX28_PAD_SSP2_SCK__SSP2_SCK
691 MX28_PAD_SSP2_MOSI__SSP2_CMD
692 MX28_PAD_SSP2_MISO__SSP2_D0
693 MX28_PAD_SSP2_SS0__SSP2_D3
695 fsl,drive-strength = <1>;
700 spi3_pins_a: spi3@0 {
703 MX28_PAD_AUART2_RX__SSP3_D4
704 MX28_PAD_AUART2_TX__SSP3_D5
705 MX28_PAD_SSP3_SCK__SSP3_SCK
706 MX28_PAD_SSP3_MOSI__SSP3_CMD
707 MX28_PAD_SSP3_MISO__SSP3_D0
708 MX28_PAD_SSP3_SS0__SSP3_D3
710 fsl,drive-strength = <1>;
715 usbphy0_pins_a: usbphy0@0 {
718 MX28_PAD_SSP2_SS2__USB0_OVERCURRENT
720 fsl,drive-strength = <2>;
725 usbphy0_pins_b: usbphy0@1 {
728 MX28_PAD_AUART1_CTS__USB0_OVERCURRENT
730 fsl,drive-strength = <2>;
735 usbphy1_pins_a: usbphy1@0 {
738 MX28_PAD_SSP2_SS1__USB1_OVERCURRENT
740 fsl,drive-strength = <2>;
745 usb0_id_pins_a: usb0id@0 {
748 0x3071 /* MX28_PAD_AUART1_RTS__USB0_ID */
750 fsl,drive-strength = <2>;
756 digctl: digctl@8001c000 {
757 compatible = "fsl,imx28-digctl", "fsl,imx23-digctl";
758 reg = <0x8001c000 0x2000>;
764 reg = <0x80022000 0x2000>;
768 dma_apbx: dma-apbx@80024000 {
769 compatible = "fsl,imx28-dma-apbx";
770 reg = <0x80024000 0x2000>;
771 interrupts = <78 79 66 0
775 interrupt-names = "auart4-rx", "aurat4-tx", "spdif-tx", "empty",
776 "saif0", "saif1", "i2c0", "i2c1",
777 "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx",
778 "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx";
785 reg = <0x80028000 0x2000>;
786 interrupts = <52 53 54>;
787 compatible = "fsl-dcp";
791 reg = <0x8002a000 0x2000>;
796 ocotp: ocotp@8002c000 {
797 compatible = "fsl,ocotp";
798 reg = <0x8002c000 0x2000>;
803 reg = <0x8002e000 0x2000>;
807 lcdif: lcdif@80030000 {
808 compatible = "fsl,imx28-lcdif";
809 reg = <0x80030000 0x2000>;
812 dmas = <&dma_apbh 13>;
818 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
819 reg = <0x80032000 0x2000>;
821 clocks = <&clks 58>, <&clks 58>;
822 clock-names = "ipg", "per";
827 compatible = "fsl,imx28-flexcan", "fsl,p1010-flexcan";
828 reg = <0x80034000 0x2000>;
830 clocks = <&clks 59>, <&clks 59>;
831 clock-names = "ipg", "per";
835 simdbg: simdbg@8003c000 {
836 reg = <0x8003c000 0x200>;
840 simgpmisel: simgpmisel@8003c200 {
841 reg = <0x8003c200 0x100>;
845 simsspsel: simsspsel@8003c300 {
846 reg = <0x8003c300 0x100>;
850 simmemsel: simmemsel@8003c400 {
851 reg = <0x8003c400 0x100>;
855 gpiomon: gpiomon@8003c500 {
856 reg = <0x8003c500 0x100>;
860 simenet: simenet@8003c700 {
861 reg = <0x8003c700 0x100>;
865 armjtag: armjtag@8003c800 {
866 reg = <0x8003c800 0x100>;
872 compatible = "simple-bus";
873 #address-cells = <1>;
875 reg = <0x80040000 0x40000>;
878 clks: clkctrl@80040000 {
879 compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
880 reg = <0x80040000 0x2000>;
884 saif0: saif@80042000 {
885 compatible = "fsl,imx28-saif";
886 reg = <0x80042000 0x2000>;
890 dmas = <&dma_apbx 4>;
895 power: power@80044000 {
896 reg = <0x80044000 0x2000>;
900 saif1: saif@80046000 {
901 compatible = "fsl,imx28-saif";
902 reg = <0x80046000 0x2000>;
905 dmas = <&dma_apbx 5>;
910 lradc: lradc@80050000 {
911 compatible = "fsl,imx28-lradc";
912 reg = <0x80050000 0x2000>;
913 interrupts = <10 14 15 16 17 18 19
918 spdif: spdif@80054000 {
919 reg = <0x80054000 0x2000>;
921 dmas = <&dma_apbx 2>;
926 mxs_rtc: rtc@80056000 {
927 compatible = "fsl,imx28-rtc", "fsl,stmp3xxx-rtc";
928 reg = <0x80056000 0x2000>;
933 #address-cells = <1>;
935 compatible = "fsl,imx28-i2c";
936 reg = <0x80058000 0x2000>;
938 clock-frequency = <100000>;
939 dmas = <&dma_apbx 6>;
945 #address-cells = <1>;
947 compatible = "fsl,imx28-i2c";
948 reg = <0x8005a000 0x2000>;
950 clock-frequency = <100000>;
951 dmas = <&dma_apbx 7>;
957 compatible = "fsl,imx28-pwm", "fsl,imx23-pwm";
958 reg = <0x80064000 0x2000>;
961 fsl,pwm-number = <8>;
965 timer: timrot@80068000 {
966 compatible = "fsl,imx28-timrot", "fsl,timrot";
967 reg = <0x80068000 0x2000>;
968 interrupts = <48 49 50 51>;
972 auart0: serial@8006a000 {
973 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
974 reg = <0x8006a000 0x2000>;
976 dmas = <&dma_apbx 8>, <&dma_apbx 9>;
977 dma-names = "rx", "tx";
982 auart1: serial@8006c000 {
983 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
984 reg = <0x8006c000 0x2000>;
986 dmas = <&dma_apbx 10>, <&dma_apbx 11>;
987 dma-names = "rx", "tx";
992 auart2: serial@8006e000 {
993 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
994 reg = <0x8006e000 0x2000>;
996 dmas = <&dma_apbx 12>, <&dma_apbx 13>;
997 dma-names = "rx", "tx";
1002 auart3: serial@80070000 {
1003 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1004 reg = <0x80070000 0x2000>;
1006 dmas = <&dma_apbx 14>, <&dma_apbx 15>;
1007 dma-names = "rx", "tx";
1008 clocks = <&clks 45>;
1009 status = "disabled";
1012 auart4: serial@80072000 {
1013 compatible = "fsl,imx28-auart", "fsl,imx23-auart";
1014 reg = <0x80072000 0x2000>;
1016 dmas = <&dma_apbx 0>, <&dma_apbx 1>;
1017 dma-names = "rx", "tx";
1018 clocks = <&clks 45>;
1019 status = "disabled";
1022 duart: serial@80074000 {
1023 compatible = "arm,pl011", "arm,primecell";
1024 reg = <0x80074000 0x1000>;
1026 clocks = <&clks 45>, <&clks 26>;
1027 clock-names = "uart", "apb_pclk";
1028 status = "disabled";
1031 usbphy0: usbphy@8007c000 {
1032 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
1033 reg = <0x8007c000 0x2000>;
1034 clocks = <&clks 62>;
1035 status = "disabled";
1038 usbphy1: usbphy@8007e000 {
1039 compatible = "fsl,imx28-usbphy", "fsl,imx23-usbphy";
1040 reg = <0x8007e000 0x2000>;
1041 clocks = <&clks 63>;
1042 status = "disabled";
1048 compatible = "simple-bus";
1049 #address-cells = <1>;
1051 reg = <0x80080000 0x80000>;
1054 usb0: usb@80080000 {
1055 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1056 reg = <0x80080000 0x10000>;
1058 clocks = <&clks 60>;
1059 fsl,usbphy = <&usbphy0>;
1060 status = "disabled";
1063 usb1: usb@80090000 {
1064 compatible = "fsl,imx28-usb", "fsl,imx27-usb";
1065 reg = <0x80090000 0x10000>;
1067 clocks = <&clks 61>;
1068 fsl,usbphy = <&usbphy1>;
1069 status = "disabled";
1072 dflpt: dflpt@800c0000 {
1073 reg = <0x800c0000 0x10000>;
1074 status = "disabled";
1077 mac0: ethernet@800f0000 {
1078 compatible = "fsl,imx28-fec";
1079 reg = <0x800f0000 0x4000>;
1081 clocks = <&clks 57>, <&clks 57>, <&clks 64>;
1082 clock-names = "ipg", "ahb", "enet_out";
1083 status = "disabled";
1086 mac1: ethernet@800f4000 {
1087 compatible = "fsl,imx28-fec";
1088 reg = <0x800f4000 0x4000>;
1090 clocks = <&clks 57>, <&clks 57>;
1091 clock-names = "ipg", "ahb";
1092 status = "disabled";
1095 etn_switch: switch@800f8000 {
1096 reg = <0x800f8000 0x8000>;
1097 status = "disabled";