arch/arm/boot/dts/imx6dl.dtsi

   1
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #include "imx6dl-pinfunc.h"
  12 #include "imx6qdl.dtsi"
  13
  14 / {
  15         cpus {
  16                 #address-cells = <1>;
  17                 #size-cells = <0>;
  18
  19                 cpu@0 {
  20                         compatible = "arm,cortex-a9";
  21                         device_type = "cpu";
  22                         reg = <0>;
  23                         next-level-cache = <&L2>;
  24                 };
  25
  26                 cpu@1 {
  27                         compatible = "arm,cortex-a9";
  28                         device_type = "cpu";
  29                         reg = <1>;
  30                         next-level-cache = <&L2>;
  31                 };
  32         };
  33
  34         soc {
  35                 ocram: sram@00900000 {
  36                         compatible = "mmio-sram";
  37                         reg = <0x00900000 0x20000>;
  38                         clocks = <&clks 142>;
  39                 };
  40
  41                 aips1: aips-bus@02000000 {
  42                         iomuxc: iomuxc@020e0000 {
  43                                 compatible = "fsl,imx6dl-iomuxc";
  44                         };
  45
  46                         pxp: pxp@020f0000 {
  47                                 reg = <0x020f0000 0x4000>;
  48                                 interrupts = <0 98 0x04>;
  49                         };
  50
  51                         epdc: epdc@020f4000 {
  52                                 reg = <0x020f4000 0x4000>;
  53                                 interrupts = <0 97 0x04>;
  54                         };
  55
  56                         lcdif: lcdif@020f8000 {
  57                                 reg = <0x020f8000 0x4000>;
  58                                 interrupts = <0 39 0x04>;
  59                         };
  60                 };
  61
  62                 aips2: aips-bus@02100000 {
  63                         i2c4: i2c@021f8000 {
  64                                 #address-cells = <1>;
  65                                 #size-cells = <0>;
  66                                 compatible = "fsl,imx1-i2c";
  67                                 reg = <0x021f8000 0x4000>;
  68                                 interrupts = <0 35 0x04>;
  69                                 status = "disabled";
  70                         };
  71                 };
  72         };
  73 };
  74
  75 &ldb {
  76         clocks = <&clks 33>, <&clks 34>,
  77                  <&clks 39>, <&clks 40>,
  78                  <&clks 135>, <&clks 136>;
  79         clock-names = "di0_pll", "di1_pll",
  80                       "di0_sel", "di1_sel",
  81                       "di0", "di1";
  82
  83         lvds-channel@0 {
  84                 crtcs = <&ipu1 0>, <&ipu1 1>;
  85         };
  86
  87         lvds-channel@1 {
  88                 crtcs = <&ipu1 0>, <&ipu1 1>;
  89         };
  90 };