arch/arm/boot/dts/imx6q.dtsi

   1
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  *
   9  */
  10
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include "imx6q-pinfunc.h"
  13 #include "imx6qdl.dtsi"
  14
  15 / {
  16         aliases {
  17                 spi4 = &ecspi5;
  18         };
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu@0 {
  25                         compatible = "arm,cortex-a9";
  26                         device_type = "cpu";
  27                         reg = <0>;
  28                         next-level-cache = <&L2>;
  29                         operating-points = <
  30                                 /* kHz    uV */
  31                                 1200000 1275000
  32                                 996000  1250000
  33                                 852000  1250000
  34                                 792000  1150000
  35                                 396000  975000
  36                         >;
  37                         fsl,soc-operating-points = <
  38                                 /* ARM kHz  SOC-PU uV */
  39                                 1200000 1275000
  40                                 996000  1250000
  41                                 852000  1250000
  42                                 792000  1175000
  43                                 396000  1175000
  44                         >;
  45                         clock-latency = <61036>; /* two CLK32 periods */
  46                         clocks = <&clks 104>, <&clks 6>, <&clks 16>,
  47                                  <&clks 17>, <&clks 170>;
  48                         clock-names = "arm", "pll2_pfd2_396m", "step",
  49                                       "pll1_sw", "pll1_sys";
  50                         arm-supply = <&reg_arm>;
  51                         pu-supply = <&reg_pu>;
  52                         soc-supply = <&reg_soc>;
  53                 };
  54
  55                 cpu@1 {
  56                         compatible = "arm,cortex-a9";
  57                         device_type = "cpu";
  58                         reg = <1>;
  59                         next-level-cache = <&L2>;
  60                 };
  61
  62                 cpu@2 {
  63                         compatible = "arm,cortex-a9";
  64                         device_type = "cpu";
  65                         reg = <2>;
  66                         next-level-cache = <&L2>;
  67                 };
  68
  69                 cpu@3 {
  70                         compatible = "arm,cortex-a9";
  71                         device_type = "cpu";
  72                         reg = <3>;
  73                         next-level-cache = <&L2>;
  74                 };
  75         };
  76
  77         soc {
  78                 gpu@00130000 {
  79                         compatible = "fsl,imx6q-gpu";
  80                         reg = <0x00130000 0x4000>, <0x00134000 0x4000>,
  81                               <0x02204000 0x4000>, <0x0 0x0>;
  82                         reg-names = "iobase_3d", "iobase_2d",
  83                                     "iobase_vg", "phys_baseaddr";
  84                         interrupts = <0 9 0x04>, <0 10 0x04>,<0 11 0x04>;
  85                         interrupt-names = "irq_3d", "irq_2d", "irq_vg";
  86                         clocks = <&clks 26>, <&clks 143>,
  87                                  <&clks 27>, <&clks 121>,
  88                                  <&clks 122>, <&clks 74>;
  89                         clock-names = "gpu2d_axi_clk", "openvg_axi_clk",
  90                                       "gpu3d_axi_clk", "gpu2d_clk",
  91                                       "gpu3d_clk", "gpu3d_shader_clk";
  92                         resets = <&src 0>, <&src 3>, <&src 3>;
  93                         reset-names = "gpu3d", "gpu2d", "gpuvg";
  94                 };
  95
  96                 ocram: sram@00900000 {
  97                         compatible = "mmio-sram";
  98                         reg = <0x00900000 0x40000>;
  99                         clocks = <&clks 142>;
 100                 };
 101
 102                 aips-bus@02000000 { /* AIPS1 */
 103                         spba-bus@02000000 {
 104                                 ecspi5: ecspi@02018000 {
 105                                         #address-cells = <1>;
 106                                         #size-cells = <0>;
 107                                         compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
 108                                         reg = <0x02018000 0x4000>;
 109                                         interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>;
 110                                         clocks = <&clks 116>, <&clks 116>;
 111                                         clock-names = "ipg", "per";
 112                                         status = "disabled";
 113                                 };
 114                         };
 115
 116                         vpu@02040000 {
 117                                 status = "okay";
 118                         };
 119
 120                         iomuxc: iomuxc@020e0000 {
 121                                 compatible = "fsl,imx6q-iomuxc";
 122
 123                                 ipu2 {
 124                                         pinctrl_ipu2_1: ipu2grp-1 {
 125                                                 fsl,pins = <
 126                                                         MX6QDL_PAD_DI0_DISP_CLK__IPU2_DI0_DISP_CLK 0x10
 127                                                         MX6QDL_PAD_DI0_PIN15__IPU2_DI0_PIN15       0x10
 128                                                         MX6QDL_PAD_DI0_PIN2__IPU2_DI0_PIN02        0x10
 129                                                         MX6QDL_PAD_DI0_PIN3__IPU2_DI0_PIN03        0x10
 130                                                         MX6QDL_PAD_DI0_PIN4__IPU2_DI0_PIN04        0x80000000
 131                                                         MX6QDL_PAD_DISP0_DAT0__IPU2_DISP0_DATA00   0x10
 132                                                         MX6QDL_PAD_DISP0_DAT1__IPU2_DISP0_DATA01   0x10
 133                                                         MX6QDL_PAD_DISP0_DAT2__IPU2_DISP0_DATA02   0x10
 134                                                         MX6QDL_PAD_DISP0_DAT3__IPU2_DISP0_DATA03   0x10
 135                                                         MX6QDL_PAD_DISP0_DAT4__IPU2_DISP0_DATA04   0x10
 136                                                         MX6QDL_PAD_DISP0_DAT5__IPU2_DISP0_DATA05   0x10
 137                                                         MX6QDL_PAD_DISP0_DAT6__IPU2_DISP0_DATA06   0x10
 138                                                         MX6QDL_PAD_DISP0_DAT7__IPU2_DISP0_DATA07   0x10
 139                                                         MX6QDL_PAD_DISP0_DAT8__IPU2_DISP0_DATA08   0x10
 140                                                         MX6QDL_PAD_DISP0_DAT9__IPU2_DISP0_DATA09   0x10
 141                                                         MX6QDL_PAD_DISP0_DAT10__IPU2_DISP0_DATA10  0x10
 142                                                         MX6QDL_PAD_DISP0_DAT11__IPU2_DISP0_DATA11  0x10
 143                                                         MX6QDL_PAD_DISP0_DAT12__IPU2_DISP0_DATA12  0x10
 144                                                         MX6QDL_PAD_DISP0_DAT13__IPU2_DISP0_DATA13  0x10
 145                                                         MX6QDL_PAD_DISP0_DAT14__IPU2_DISP0_DATA14  0x10
 146                                                         MX6QDL_PAD_DISP0_DAT15__IPU2_DISP0_DATA15  0x10
 147                                                         MX6QDL_PAD_DISP0_DAT16__IPU2_DISP0_DATA16  0x10
 148                                                         MX6QDL_PAD_DISP0_DAT17__IPU2_DISP0_DATA17  0x10
 149                                                         MX6QDL_PAD_DISP0_DAT18__IPU2_DISP0_DATA18  0x10
 150                                                         MX6QDL_PAD_DISP0_DAT19__IPU2_DISP0_DATA19  0x10
 151                                                         MX6QDL_PAD_DISP0_DAT20__IPU2_DISP0_DATA20  0x10
 152                                                         MX6QDL_PAD_DISP0_DAT21__IPU2_DISP0_DATA21  0x10
 153                                                         MX6QDL_PAD_DISP0_DAT22__IPU2_DISP0_DATA22  0x10
 154                                                         MX6QDL_PAD_DISP0_DAT23__IPU2_DISP0_DATA23  0x10
 155                                                 >;
 156                                         };
 157                                 };
 158                         };
 159                 };
 160
 161                 sata: sata@02200000 {
 162                         compatible = "fsl,imx6q-ahci";
 163                         reg = <0x02200000 0x4000>;
 164                         interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
 165                         clocks =  <&clks 154>, <&clks 187>, <&clks 105>;
 166                         clock-names = "sata", "sata_ref", "ahb";
 167                         status = "disabled";
 168                 };
 169
 170                 ipu2: ipu@02800000 {
 171                         #address-cells = <1>;
 172                         #size-cells = <0>;
 173                         compatible = "fsl,imx6q-ipu";
 174                         reg = <0x02800000 0x400000>;
 175                         interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
 176                                      <0 7 IRQ_TYPE_LEVEL_HIGH>;
 177                         clocks = <&clks 133>, <&clks 134>, <&clks 137>;
 178                         clock-names = "bus", "di0", "di1";
 179                         resets = <&src 4>;
 180
 181                         ipu2_di0: port@2 {
 182                                 #address-cells = <1>;
 183                                 #size-cells = <0>;
 184                                 reg = <2>;
 185
 186                                 ipu2_di0_disp0: endpoint@0 {
 187                                 };
 188
 189                                 ipu2_di0_hdmi: endpoint@1 {
 190                                         remote-endpoint = <&hdmi_mux_2>;
 191                                 };
 192
 193                                 ipu2_di0_mipi: endpoint@2 {
 194                                 };
 195
 196                                 ipu2_di0_lvds0: endpoint@3 {
 197                                         remote-endpoint = <&lvds0_mux_2>;
 198                                 };
 199
 200                                 ipu2_di0_lvds1: endpoint@4 {
 201                                         remote-endpoint = <&lvds1_mux_2>;
 202                                 };
 203                         };
 204
 205                         ipu2_di1: port@3 {
 206                                 #address-cells = <1>;
 207                                 #size-cells = <0>;
 208                                 reg = <3>;
 209
 210                                 ipu2_di1_hdmi: endpoint@1 {
 211                                         remote-endpoint = <&hdmi_mux_3>;
 212                                 };
 213
 214                                 ipu2_di1_mipi: endpoint@2 {
 215                                 };
 216
 217                                 ipu2_di1_lvds0: endpoint@3 {
 218                                         remote-endpoint = <&lvds0_mux_3>;
 219                                 };
 220
 221                                 ipu2_di1_lvds1: endpoint@4 {
 222                                         remote-endpoint = <&lvds1_mux_3>;
 223                                 };
 224                         };
 225                 };
 226         };
 227
 228         display-subsystem {
 229                 compatible = "fsl,imx-display-subsystem";
 230                 ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
 231         };
 232 };
 233
 234 &hdmi {
 235         compatible = "fsl,imx6q-hdmi";
 236
 237         port@2 {
 238                 reg = <2>;
 239
 240                 hdmi_mux_2: endpoint {
 241                         remote-endpoint = <&ipu2_di0_hdmi>;
 242                 };
 243         };
 244
 245         port@3 {
 246                 reg = <3>;
 247
 248                 hdmi_mux_3: endpoint {
 249                         remote-endpoint = <&ipu2_di1_hdmi>;
 250                 };
 251         };
 252 };
 253
 254 &ldb {
 255         clocks = <&clks 33>, <&clks 34>,
 256                  <&clks 39>, <&clks 40>, <&clks 41>, <&clks 42>,
 257                  <&clks 135>, <&clks 136>;
 258         clock-names = "di0_pll", "di1_pll",
 259                       "di0_sel", "di1_sel", "di2_sel", "di3_sel",
 260                       "di0", "di1";
 261
 262         lvds-channel@0 {
 263                 port@2 {
 264                         reg = <2>;
 265
 266                         lvds0_mux_2: endpoint {
 267                                 remote-endpoint = <&ipu2_di0_lvds0>;
 268                         };
 269                 };
 270
 271                 port@3 {
 272                         reg = <3>;
 273
 274                         lvds0_mux_3: endpoint {
 275                                 remote-endpoint = <&ipu2_di1_lvds0>;
 276                         };
 277                 };
 278         };
 279
 280         lvds-channel@1 {
 281                 port@2 {
 282                         reg = <2>;
 283
 284                         lvds1_mux_2: endpoint {
 285                                 remote-endpoint = <&ipu2_di0_lvds1>;
 286                         };
 287                 };
 288
 289                 port@3 {
 290                         reg = <3>;
 291
 292                         lvds1_mux_3: endpoint {
 293                                 remote-endpoint = <&ipu2_di1_lvds1>;
 294                         };
 295                 };
 296         };
 297 };
 298
 299 &mipi_dsi {
 300         port@2 {
 301                 reg = <2>;
 302
 303                 mipi_mux_2: endpoint {
 304                         remote-endpoint = <&ipu2_di0_mipi>;
 305                 };
 306         };
 307
 308         port@3 {
 309                 reg = <3>;
 310
 311                 mipi_mux_3: endpoint {
 312                         remote-endpoint = <&ipu2_di1_mipi>;
 313                 };
 314         };
 315 };