2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #include "skeleton.dtsi"
50 intc: interrupt-controller@00a01000 {
51 compatible = "arm,cortex-a9-gic";
52 #interrupt-cells = <3>;
54 reg = <0x00a01000 0x1000>,
63 compatible = "fsl,imx-ckil", "fixed-clock";
65 clock-frequency = <32768>;
69 compatible = "fsl,imx-ckih1", "fixed-clock";
71 clock-frequency = <0>;
75 compatible = "fsl,imx-osc", "fixed-clock";
77 clock-frequency = <24000000>;
84 compatible = "simple-bus";
85 interrupt-parent = <&intc>;
88 dma_apbh: dma-apbh@00110000 {
89 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
90 reg = <0x00110000 0x2000>;
91 interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
92 <0 13 IRQ_TYPE_LEVEL_HIGH>,
93 <0 13 IRQ_TYPE_LEVEL_HIGH>,
94 <0 13 IRQ_TYPE_LEVEL_HIGH>;
95 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
101 gpmi: gpmi-nand@00112000 {
102 compatible = "fsl,imx6q-gpmi-nand";
103 #address-cells = <1>;
105 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
106 reg-names = "gpmi-nand", "bch";
107 interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
108 interrupt-names = "bch";
109 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
110 <&clks 150>, <&clks 149>;
111 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
112 "gpmi_bch_apb", "per1_bch";
113 dmas = <&dma_apbh 0>;
119 compatible = "arm,cortex-a9-twd-timer";
120 reg = <0x00a00600 0x20>;
121 interrupts = <1 13 0xf01>;
125 L2: l2-cache@00a02000 {
126 compatible = "arm,pl310-cache";
127 reg = <0x00a02000 0x1000>;
128 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
131 arm,tag-latency = <4 2 3>;
132 arm,data-latency = <4 2 3>;
135 pcie: pcie@0x01000000 {
136 compatible = "fsl,imx6q-pcie", "snps,dw-pcie";
137 reg = <0x01ffc000 0x4000>; /* DBI */
138 #address-cells = <3>;
141 ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */
142 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */
143 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */
145 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
146 interrupt-names = "msi";
147 #interrupt-cells = <1>;
148 interrupt-map-mask = <0 0 0 0x7>;
149 interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
150 <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
151 <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
152 <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
153 clocks = <&clks 144>, <&clks 206>, <&clks 189>;
154 clock-names = "pcie", "pcie_bus", "pcie_phy";
159 compatible = "arm,cortex-a9-pmu";
160 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>;
163 aips-bus@02000000 { /* AIPS1 */
164 compatible = "fsl,aips-bus", "simple-bus";
165 #address-cells = <1>;
167 reg = <0x02000000 0x100000>;
171 compatible = "fsl,spba-bus", "simple-bus";
172 #address-cells = <1>;
174 reg = <0x02000000 0x40000>;
177 spdif: spdif@02004000 {
178 compatible = "fsl,imx35-spdif";
179 reg = <0x02004000 0x4000>;
180 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
181 dmas = <&sdma 14 18 0>,
183 dma-names = "rx", "tx";
184 clocks = <&clks 197>, <&clks 3>,
185 <&clks 197>, <&clks 107>,
186 <&clks 0>, <&clks 118>,
187 <&clks 0>, <&clks 139>,
189 clock-names = "core", "rxtx0",
197 ecspi1: ecspi@02008000 {
198 #address-cells = <1>;
200 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
201 reg = <0x02008000 0x4000>;
202 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&clks 112>, <&clks 112>;
204 clock-names = "ipg", "per";
205 dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
206 dma-names = "rx", "tx";
210 ecspi2: ecspi@0200c000 {
211 #address-cells = <1>;
213 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
214 reg = <0x0200c000 0x4000>;
215 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>;
216 clocks = <&clks 113>, <&clks 113>;
217 clock-names = "ipg", "per";
218 dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
219 dma-names = "rx", "tx";
223 ecspi3: ecspi@02010000 {
224 #address-cells = <1>;
226 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
227 reg = <0x02010000 0x4000>;
228 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
229 clocks = <&clks 114>, <&clks 114>;
230 clock-names = "ipg", "per";
231 dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
232 dma-names = "rx", "tx";
236 ecspi4: ecspi@02014000 {
237 #address-cells = <1>;
239 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
240 reg = <0x02014000 0x4000>;
241 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&clks 115>, <&clks 115>;
243 clock-names = "ipg", "per";
244 dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
245 dma-names = "rx", "tx";
249 uart1: serial@02020000 {
250 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
251 reg = <0x02020000 0x4000>;
252 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&clks 160>, <&clks 161>;
254 clock-names = "ipg", "per";
255 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
256 dma-names = "rx", "tx";
260 esai: esai@02024000 {
261 compatible = "fsl,imx6q-esai";
262 reg = <0x02024000 0x4000>;
263 interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&clks 118>, <&clks 156>;
265 clock-names = "core", "dma";
266 fsl,esai-dma-events = <24 23>;
272 compatible = "fsl,imx6q-ssi",
275 reg = <0x02028000 0x4000>;
276 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>;
277 clocks = <&clks 178>;
278 dmas = <&sdma 37 1 0>,
280 dma-names = "rx", "tx";
281 fsl,fifo-depth = <15>;
282 fsl,ssi-dma-events = <38 37>;
287 compatible = "fsl,imx6q-ssi",
290 reg = <0x0202c000 0x4000>;
291 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&clks 179>;
293 dmas = <&sdma 41 1 0>,
295 dma-names = "rx", "tx";
296 fsl,fifo-depth = <15>;
297 fsl,ssi-dma-events = <42 41>;
302 compatible = "fsl,imx6q-ssi",
305 reg = <0x02030000 0x4000>;
306 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&clks 180>;
308 dmas = <&sdma 45 1 0>,
310 dma-names = "rx", "tx";
311 fsl,fifo-depth = <15>;
312 fsl,ssi-dma-events = <46 45>;
316 asrc: asrc@02034000 {
317 reg = <0x02034000 0x4000>;
318 interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
322 reg = <0x0203c000 0x4000>;
327 reg = <0x02040000 0x3c000>;
328 reg-names = "vpu_regs";
329 interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
330 <0 12 IRQ_TYPE_LEVEL_HIGH>;
331 interrupt-names = "vpu_jpu_irq", "vpu_ipi_irq";
332 clocks = <&clks 168>, <&clks 140>, <&clks 142>;
333 clock-names = "vpu_clk", "mmdc_ch0_axi", "ocram";
334 iramsize = <0x21000>;
337 pu-supply = <®_pu>;
341 aipstz@0207c000 { /* AIPSTZ1 */
342 reg = <0x0207c000 0x4000>;
347 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
348 reg = <0x02080000 0x4000>;
349 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>;
350 clocks = <&clks 62>, <&clks 145>;
351 clock-names = "ipg", "per";
356 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
357 reg = <0x02084000 0x4000>;
358 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&clks 62>, <&clks 146>;
360 clock-names = "ipg", "per";
365 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
366 reg = <0x02088000 0x4000>;
367 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
368 clocks = <&clks 62>, <&clks 147>;
369 clock-names = "ipg", "per";
374 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
375 reg = <0x0208c000 0x4000>;
376 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
377 clocks = <&clks 62>, <&clks 148>;
378 clock-names = "ipg", "per";
381 can1: flexcan@02090000 {
382 compatible = "fsl,imx6q-flexcan";
383 reg = <0x02090000 0x4000>;
384 interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&clks 108>, <&clks 109>;
386 clock-names = "ipg", "per";
390 can2: flexcan@02094000 {
391 compatible = "fsl,imx6q-flexcan";
392 reg = <0x02094000 0x4000>;
393 interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&clks 110>, <&clks 111>;
395 clock-names = "ipg", "per";
400 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
401 reg = <0x02098000 0x4000>;
402 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
403 clocks = <&clks 119>, <&clks 120>;
404 clock-names = "ipg", "per";
407 gpio1: gpio@0209c000 {
408 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
409 reg = <0x0209c000 0x4000>;
410 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>,
411 <0 67 IRQ_TYPE_LEVEL_HIGH>;
414 interrupt-controller;
415 #interrupt-cells = <2>;
418 gpio2: gpio@020a0000 {
419 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
420 reg = <0x020a0000 0x4000>;
421 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>,
422 <0 69 IRQ_TYPE_LEVEL_HIGH>;
425 interrupt-controller;
426 #interrupt-cells = <2>;
429 gpio3: gpio@020a4000 {
430 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
431 reg = <0x020a4000 0x4000>;
432 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>,
433 <0 71 IRQ_TYPE_LEVEL_HIGH>;
436 interrupt-controller;
437 #interrupt-cells = <2>;
440 gpio4: gpio@020a8000 {
441 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
442 reg = <0x020a8000 0x4000>;
443 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>,
444 <0 73 IRQ_TYPE_LEVEL_HIGH>;
447 interrupt-controller;
448 #interrupt-cells = <2>;
451 gpio5: gpio@020ac000 {
452 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
453 reg = <0x020ac000 0x4000>;
454 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>,
455 <0 75 IRQ_TYPE_LEVEL_HIGH>;
458 interrupt-controller;
459 #interrupt-cells = <2>;
462 gpio6: gpio@020b0000 {
463 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
464 reg = <0x020b0000 0x4000>;
465 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>,
466 <0 77 IRQ_TYPE_LEVEL_HIGH>;
469 interrupt-controller;
470 #interrupt-cells = <2>;
473 gpio7: gpio@020b4000 {
474 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
475 reg = <0x020b4000 0x4000>;
476 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>,
477 <0 79 IRQ_TYPE_LEVEL_HIGH>;
480 interrupt-controller;
481 #interrupt-cells = <2>;
485 compatible = "fsl,imx6qdl-kpp", "fsl,imx21-kpp";
486 reg = <0x020b8000 0x4000>;
487 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
491 wdog1: wdog@020bc000 {
492 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
493 reg = <0x020bc000 0x4000>;
494 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
498 wdog2: wdog@020c0000 {
499 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
500 reg = <0x020c0000 0x4000>;
501 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
507 compatible = "fsl,imx6q-ccm";
508 reg = <0x020c4000 0x4000>;
509 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>,
510 <0 88 IRQ_TYPE_LEVEL_HIGH>;
514 anatop: anatop@020c8000 {
515 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
516 reg = <0x020c8000 0x1000>;
517 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>,
518 <0 54 IRQ_TYPE_LEVEL_HIGH>,
519 <0 127 IRQ_TYPE_LEVEL_HIGH>;
522 compatible = "fsl,anatop-regulator";
523 regulator-name = "vdd1p1";
524 regulator-min-microvolt = <800000>;
525 regulator-max-microvolt = <1375000>;
527 anatop-reg-offset = <0x110>;
528 anatop-vol-bit-shift = <8>;
529 anatop-vol-bit-width = <5>;
530 anatop-min-bit-val = <4>;
531 anatop-min-voltage = <800000>;
532 anatop-max-voltage = <1375000>;
536 compatible = "fsl,anatop-regulator";
537 regulator-name = "vdd3p0";
538 regulator-min-microvolt = <2800000>;
539 regulator-max-microvolt = <3150000>;
541 anatop-reg-offset = <0x120>;
542 anatop-vol-bit-shift = <8>;
543 anatop-vol-bit-width = <5>;
544 anatop-min-bit-val = <0>;
545 anatop-min-voltage = <2625000>;
546 anatop-max-voltage = <3400000>;
550 compatible = "fsl,anatop-regulator";
551 regulator-name = "vdd2p5";
552 regulator-min-microvolt = <2000000>;
553 regulator-max-microvolt = <2750000>;
555 anatop-reg-offset = <0x130>;
556 anatop-vol-bit-shift = <8>;
557 anatop-vol-bit-width = <5>;
558 anatop-min-bit-val = <0>;
559 anatop-min-voltage = <2000000>;
560 anatop-max-voltage = <2750000>;
563 reg_arm: regulator-vddcore@140 {
564 compatible = "fsl,anatop-regulator";
565 regulator-name = "vddarm";
566 regulator-min-microvolt = <725000>;
567 regulator-max-microvolt = <1450000>;
569 anatop-reg-offset = <0x140>;
570 anatop-vol-bit-shift = <0>;
571 anatop-vol-bit-width = <5>;
572 anatop-delay-reg-offset = <0x170>;
573 anatop-delay-bit-shift = <24>;
574 anatop-delay-bit-width = <2>;
575 anatop-min-bit-val = <1>;
576 anatop-min-voltage = <725000>;
577 anatop-max-voltage = <1450000>;
580 reg_pu: regulator-vddpu@140 {
581 compatible = "fsl,anatop-regulator";
582 regulator-name = "vddpu";
583 regulator-min-microvolt = <725000>;
584 regulator-max-microvolt = <1450000>;
586 anatop-reg-offset = <0x140>;
587 anatop-vol-bit-shift = <9>;
588 anatop-vol-bit-width = <5>;
589 anatop-delay-reg-offset = <0x170>;
590 anatop-delay-bit-shift = <26>;
591 anatop-delay-bit-width = <2>;
592 anatop-min-bit-val = <1>;
593 anatop-min-voltage = <725000>;
594 anatop-max-voltage = <1450000>;
597 reg_soc: regulator-vddsoc@140 {
598 compatible = "fsl,anatop-regulator";
599 regulator-name = "vddsoc";
600 regulator-min-microvolt = <725000>;
601 regulator-max-microvolt = <1450000>;
603 anatop-reg-offset = <0x140>;
604 anatop-vol-bit-shift = <18>;
605 anatop-vol-bit-width = <5>;
606 anatop-delay-reg-offset = <0x170>;
607 anatop-delay-bit-shift = <28>;
608 anatop-delay-bit-width = <2>;
609 anatop-min-bit-val = <1>;
610 anatop-min-voltage = <725000>;
611 anatop-max-voltage = <1450000>;
616 compatible = "fsl,imx6q-tempmon";
617 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
618 fsl,tempmon = <&anatop>;
619 fsl,tempmon-data = <&ocotp>;
620 clocks = <&clks 172>;
623 usbphy1: usbphy@020c9000 {
624 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
625 reg = <0x020c9000 0x1000>;
626 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>;
627 clocks = <&clks 182>;
628 fsl,anatop = <&anatop>;
631 usbphy2: usbphy@020ca000 {
632 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
633 reg = <0x020ca000 0x1000>;
634 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>;
635 clocks = <&clks 183>;
636 fsl,anatop = <&anatop>;
640 compatible = "fsl,sec-v4.0-mon", "simple-bus";
641 #address-cells = <1>;
643 ranges = <0 0x020cc000 0x4000>;
646 compatible = "fsl,sec-v4.0-mon-rtc-lp";
648 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
649 <0 20 IRQ_TYPE_LEVEL_HIGH>;
653 epit1: epit@020d0000 { /* EPIT1 */
654 reg = <0x020d0000 0x4000>;
655 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
658 epit2: epit@020d4000 { /* EPIT2 */
659 reg = <0x020d4000 0x4000>;
660 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
664 compatible = "fsl,imx6q-src", "fsl,imx51-src";
665 reg = <0x020d8000 0x4000>;
666 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>,
667 <0 96 IRQ_TYPE_LEVEL_HIGH>;
672 compatible = "fsl,imx6q-gpc";
673 reg = <0x020dc000 0x4000>;
674 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
675 <0 90 IRQ_TYPE_LEVEL_HIGH>;
678 gpr: iomuxc-gpr@020e0000 {
679 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
680 reg = <0x020e0000 0x38>;
683 iomuxc: iomuxc@020e0000 {
684 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
685 reg = <0x020e0000 0x4000>;
689 #address-cells = <1>;
691 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
692 reg = <0x020e0000 0x4000>;
693 clocks = <&clks 135>, <&clks 136>,
694 <&clks 39>, <&clks 40>,
695 <&clks 41>, <&clks 42>,
696 <&clks 184>, <&clks 185>,
697 <&clks 209>, <&clks 210>,
698 <&clks 211>, <&clks 212>;
699 clock-names = "ldb_di0", "ldb_di1",
700 "ipu1_di0_sel", "ipu1_di1_sel",
701 "ipu2_di0_sel", "ipu2_di1_sel",
702 "di0_div_3_5", "di1_div_3_5",
703 "di0_div_7", "di1_div_7",
704 "di0_div_sel", "di1_div_sel";
710 #address-cells = <1>;
718 lvds0_mux_0: endpoint {
719 remote-endpoint = <&ipu1_di0_lvds0>;
726 lvds0_mux_1: endpoint {
727 remote-endpoint = <&ipu1_di1_lvds0>;
733 #address-cells = <1>;
741 lvds1_mux_0: endpoint {
742 remote-endpoint = <&ipu1_di0_lvds1>;
749 lvds1_mux_1: endpoint {
750 remote-endpoint = <&ipu1_di1_lvds1>;
757 #address-cells = <1>;
759 reg = <0x00120000 0x9000>;
760 interrupts = <0 115 0x04>;
762 clocks = <&clks 123>, <&clks 124>;
763 clock-names = "iahb", "isfr";
769 hdmi_mux_0: endpoint {
770 remote-endpoint = <&ipu1_di0_hdmi>;
777 hdmi_mux_1: endpoint {
778 remote-endpoint = <&ipu1_di1_hdmi>;
783 dcic1: dcic@020e4000 {
784 reg = <0x020e4000 0x4000>;
785 interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
788 dcic2: dcic@020e8000 {
789 reg = <0x020e8000 0x4000>;
790 interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
793 sdma: sdma@020ec000 {
794 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
795 reg = <0x020ec000 0x4000>;
796 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>;
797 clocks = <&clks 155>, <&clks 155>;
798 clock-names = "ipg", "ahb";
800 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
804 aips-bus@02100000 { /* AIPS2 */
805 compatible = "fsl,aips-bus", "simple-bus";
806 #address-cells = <1>;
808 reg = <0x02100000 0x100000>;
812 reg = <0x02100000 0x40000>;
813 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>,
814 <0 106 IRQ_TYPE_LEVEL_HIGH>;
817 aipstz@0217c000 { /* AIPSTZ2 */
818 reg = <0x0217c000 0x4000>;
821 usbotg: usb@02184000 {
822 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
823 reg = <0x02184000 0x200>;
824 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>;
825 clocks = <&clks 162>;
826 fsl,usbphy = <&usbphy1>;
827 fsl,usbmisc = <&usbmisc 0>;
831 usbh1: usb@02184200 {
832 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
833 reg = <0x02184200 0x200>;
834 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&clks 162>;
836 fsl,usbphy = <&usbphy2>;
837 fsl,usbmisc = <&usbmisc 1>;
841 usbh2: usb@02184400 {
842 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
843 reg = <0x02184400 0x200>;
844 interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
845 clocks = <&clks 162>;
846 fsl,usbmisc = <&usbmisc 2>;
850 usbh3: usb@02184600 {
851 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
852 reg = <0x02184600 0x200>;
853 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
854 clocks = <&clks 162>;
855 fsl,usbmisc = <&usbmisc 3>;
859 usbmisc: usbmisc@02184800 {
861 compatible = "fsl,imx6q-usbmisc";
862 reg = <0x02184800 0x200>;
863 clocks = <&clks 162>;
866 fec: ethernet@02188000 {
867 compatible = "fsl,imx6q-fec";
868 reg = <0x02188000 0x4000>;
869 interrupts-extended =
870 <&intc 0 118 IRQ_TYPE_LEVEL_HIGH>,
871 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
872 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
873 clock-names = "ipg", "ahb", "ptp";
878 reg = <0x0218c000 0x4000>;
879 interrupts = <0 53 IRQ_TYPE_LEVEL_HIGH>,
880 <0 117 IRQ_TYPE_LEVEL_HIGH>,
881 <0 126 IRQ_TYPE_LEVEL_HIGH>;
884 usdhc1: usdhc@02190000 {
885 compatible = "fsl,imx6q-usdhc";
886 reg = <0x02190000 0x4000>;
887 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
888 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
889 clock-names = "ipg", "ahb", "per";
894 usdhc2: usdhc@02194000 {
895 compatible = "fsl,imx6q-usdhc";
896 reg = <0x02194000 0x4000>;
897 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
898 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
899 clock-names = "ipg", "ahb", "per";
904 usdhc3: usdhc@02198000 {
905 compatible = "fsl,imx6q-usdhc";
906 reg = <0x02198000 0x4000>;
907 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
908 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
909 clock-names = "ipg", "ahb", "per";
914 usdhc4: usdhc@0219c000 {
915 compatible = "fsl,imx6q-usdhc";
916 reg = <0x0219c000 0x4000>;
917 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
918 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
919 clock-names = "ipg", "ahb", "per";
925 #address-cells = <1>;
927 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
928 reg = <0x021a0000 0x4000>;
929 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>;
930 clocks = <&clks 125>;
935 #address-cells = <1>;
937 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
938 reg = <0x021a4000 0x4000>;
939 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>;
940 clocks = <&clks 126>;
945 #address-cells = <1>;
947 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
948 reg = <0x021a8000 0x4000>;
949 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>;
950 clocks = <&clks 127>;
955 reg = <0x021ac000 0x4000>;
958 mmdc0: mmdc@021b0000 { /* MMDC0 */
959 compatible = "fsl,imx6q-mmdc";
960 reg = <0x021b0000 0x4000>;
963 mmdc1: mmdc@021b4000 { /* MMDC1 */
964 reg = <0x021b4000 0x4000>;
967 weim: weim@021b8000 {
968 compatible = "fsl,imx6q-weim";
969 reg = <0x021b8000 0x4000>;
970 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
971 clocks = <&clks 196>;
974 ocotp: ocotp@021bc000 {
975 compatible = "fsl,imx6q-ocotp", "syscon";
976 reg = <0x021bc000 0x4000>;
979 tzasc@021d0000 { /* TZASC1 */
980 reg = <0x021d0000 0x4000>;
981 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
984 tzasc@021d4000 { /* TZASC2 */
985 reg = <0x021d4000 0x4000>;
986 interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
989 audmux: audmux@021d8000 {
990 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
991 reg = <0x021d8000 0x4000>;
995 mipi_csi: mipi@021dc000 {
996 reg = <0x021dc000 0x4000>;
999 mipi_dsi: mipi@021e0000 {
1000 #address-cells = <1>;
1002 reg = <0x021e0000 0x4000>;
1003 status = "disabled";
1008 mipi_mux_0: endpoint {
1009 remote-endpoint = <&ipu1_di0_mipi>;
1016 mipi_mux_1: endpoint {
1017 remote-endpoint = <&ipu1_di1_mipi>;
1023 reg = <0x021e4000 0x4000>;
1024 interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
1027 uart2: serial@021e8000 {
1028 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1029 reg = <0x021e8000 0x4000>;
1030 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>;
1031 clocks = <&clks 160>, <&clks 161>;
1032 clock-names = "ipg", "per";
1033 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1034 dma-names = "rx", "tx";
1035 status = "disabled";
1038 uart3: serial@021ec000 {
1039 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1040 reg = <0x021ec000 0x4000>;
1041 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>;
1042 clocks = <&clks 160>, <&clks 161>;
1043 clock-names = "ipg", "per";
1044 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1045 dma-names = "rx", "tx";
1046 status = "disabled";
1049 uart4: serial@021f0000 {
1050 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1051 reg = <0x021f0000 0x4000>;
1052 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
1053 clocks = <&clks 160>, <&clks 161>;
1054 clock-names = "ipg", "per";
1055 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1056 dma-names = "rx", "tx";
1057 status = "disabled";
1060 uart5: serial@021f4000 {
1061 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1062 reg = <0x021f4000 0x4000>;
1063 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
1064 clocks = <&clks 160>, <&clks 161>;
1065 clock-names = "ipg", "per";
1066 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1067 dma-names = "rx", "tx";
1068 status = "disabled";
1072 ipu1: ipu@02400000 {
1073 #address-cells = <1>;
1075 compatible = "fsl,imx6q-ipu";
1076 reg = <0x02400000 0x400000>;
1077 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>,
1078 <0 5 IRQ_TYPE_LEVEL_HIGH>;
1079 clocks = <&clks 130>, <&clks 131>, <&clks 132>,
1080 <&clks 39>, <&clks 40>,
1081 <&clks 135>, <&clks 136>;
1082 clock-names = "bus", "di0", "di1",
1083 "di0_sel", "di1_sel",
1084 "ldb_di0", "ldb_di1";
1089 #address-cells = <1>;
1093 ipu1_di0_disp0: endpoint@0 {
1096 ipu1_di0_hdmi: endpoint@1 {
1097 remote-endpoint = <&hdmi_mux_0>;
1100 ipu1_di0_mipi: endpoint@2 {
1101 remote-endpoint = <&mipi_mux_0>;
1104 ipu1_di0_lvds0: endpoint@3 {
1105 remote-endpoint = <&lvds0_mux_0>;
1108 ipu1_di0_lvds1: endpoint@4 {
1109 remote-endpoint = <&lvds1_mux_0>;
1114 #address-cells = <1>;
1118 ipu1_di0_disp1: endpoint@0 {
1121 ipu1_di1_hdmi: endpoint@1 {
1122 remote-endpoint = <&hdmi_mux_1>;
1125 ipu1_di1_mipi: endpoint@2 {
1126 remote-endpoint = <&mipi_mux_1>;
1129 ipu1_di1_lvds0: endpoint@3 {
1130 remote-endpoint = <&lvds0_mux_1>;
1133 ipu1_di1_lvds1: endpoint@4 {
1134 remote-endpoint = <&lvds1_mux_1>;