arch/arm/boot/dts/imx6ul-txul-mainboard.dtsi

   1 /*
   2  * Copyright 2017 Lothar Waßmann <LW@KARO-electronics.de>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License
  11  *     version 2 as published by the Free Software Foundation.
  12  *
  13  *     This file is distributed in the hope that it will be useful,
  14  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *     GNU General Public License for more details.
  17  *
  18  * Or, alternatively,
  19  *
  20  *  b) Permission is hereby granted, free of charge, to any person
  21  *     obtaining a copy of this software and associated documentation
  22  *     files (the "Software"), to deal in the Software without
  23  *     restriction, including without limitation the rights to use,
  24  *     copy, modify, merge, publish, distribute, sublicense, and/or
  25  *     sell copies of the Software, and to permit persons to whom the
  26  *     Software is furnished to do so, subject to the following
  27  *     conditions:
  28  *
  29  *     The above copyright notice and this permission notice shall be
  30  *     included in all copies or substantial portions of the Software.
  31  *
  32  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  33  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  34  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  35  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  36  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  37  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  38  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  39  *     OTHER DEALINGS IN THE SOFTWARE.
  40  */
  41
  42 / {
  43         aliases {
  44                 lcdif_24bit_pins_a = &pinctrl_disp0_3;
  45                 serial2 = &uart3;
  46                 serial4 = &uart5;
  47         };
  48
  49         /delete-node/ sound;
  50 };
  51
  52 &can1 {
  53         xceiver-supply = <&reg_3v3>;
  54 };
  55
  56 &can2 {
  57         xceiver-supply = <&reg_3v3>;
  58 };
  59
  60 &ds1339 {
  61         status = "disabled";
  62 };
  63
  64 &fec1 {
  65         pinctrl-0 = <&pinctrl_enet1 &pinctrl_etnphy0_rst>;
  66         /delete-node/ mdio;
  67 };
  68
  69 &fec2 {
  70         pinctrl-names = "default";
  71         pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio &pinctrl_etnphy1_rst>;
  72         phy-mode = "rmii";
  73         phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
  74         phy-supply = <&reg_3v3_etn>;
  75         phy-handle = <&etnphy1>;
  76         status = "okay";
  77
  78         mdio {
  79                 #address-cells = <1>;
  80                 #size-cells = <0>;
  81
  82                 etnphy0: ethernet-phy@0 {
  83                         compatible = "ethernet-phy-ieee802.3-c22";
  84                         reg = <0>;
  85                         pinctrl-names = "default";
  86                         pinctrl-0 = <&pinctrl_etnphy0_int>;
  87                         interrupt-parent = <&gpio5>;
  88                         interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
  89                         status = "okay";
  90                 };
  91
  92                 etnphy1: ethernet-phy@2 {
  93                         compatible = "ethernet-phy-ieee802.3-c22";
  94                         reg = <2>;
  95                         pinctrl-names = "default";
  96                         pinctrl-0 = <&pinctrl_etnphy1_int>;
  97                         interrupt-parent = <&gpio4>;
  98                         interrupts = <27 IRQ_TYPE_EDGE_FALLING>;
  99                         status = "okay";
 100                 };
 101         };
 102 };
 103
 104 &i2c_gpio {
 105         status = "disabled";
 106 };
 107
 108 &i2c2 {
 109         /delete-node/ codec@0a;
 110         /delete-node/ touchscreen@48;
 111
 112         rtc: mcp7940x@6f {
 113                 compatible = "microchip,mcp7940x";
 114                 reg = <0x6f>;
 115         };
 116 };
 117
 118 &kpp {
 119         status = "disabled";
 120 };
 121
 122 &lcdif {
 123         pinctrl-0 = <&pinctrl_disp0_3>;
 124 };
 125
 126 &reg_usbotg_vbus {
 127         status = "disabled";
 128 };
 129
 130 &usdhc1 {
 131         pinctrl-0 = <&pinctrl_usdhc1>;
 132         non-removable;
 133         /delete-property/ cd-gpios;
 134         cap-sdio-irq;
 135 };
 136
 137 &uart1 {
 138         pinctrl-0 = <&pinctrl_uart1>;
 139         /delete-property/ uart-has-rtscts;
 140 };
 141
 142 &uart2 {
 143         pinctrl-0 = <&pinctrl_uart2>;
 144         /delete-property/ uart-has-rtscts;
 145         status = "okay";
 146 };
 147
 148 &uart3 {
 149         pinctrl-names = "default";
 150         pinctrl-0 = <&pinctrl_uart3>;
 151         status = "okay";
 152 };
 153
 154 &uart4 {
 155         pinctrl-names = "default";
 156         pinctrl-0 = <&pinctrl_uart4>;
 157         status = "okay";
 158 };
 159
 160 &uart5 {
 161         pinctrl-names = "default";
 162         pinctrl-0 = <&pinctrl_uart5>;
 163         status = "okay";
 164 };
 165
 166 &uart6 {
 167         pinctrl-names = "default";
 168         pinctrl-0 = <&pinctrl_uart6>;
 169         status = "okay";
 170 };
 171
 172 &uart7 {
 173         pinctrl-names = "default";
 174         pinctrl-0 = <&pinctrl_uart7>;
 175         status = "okay";
 176 };
 177
 178 &uart8 {
 179         pinctrl-names = "default";
 180         pinctrl-0 = <&pinctrl_uart8>;
 181         status = "disabled"; /* conflicts with LCDIF */
 182 };
 183
 184 &iomuxc {
 185         hoggrp {
 186                 fsl,pins = <
 187                         MX6UL_PAD_CSI_DATA01__GPIO4_IO22        0x0b0b0 /* WLAN_RESET */
 188                 >;
 189         };
 190
 191         pinctrl_disp0_3: disp0grp-3 {
 192                 fsl,pins = <
 193                         MX6UL_PAD_LCD_CLK__LCDIF_CLK            0x10 /* LSCLK */
 194                         MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE      0x10 /* OE_ACD */
 195                         MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC        0x10 /* HSYNC */
 196                         MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC        0x10 /* VSYNC */
 197                         MX6UL_PAD_LCD_DATA02__LCDIF_DATA02      0x10
 198                         MX6UL_PAD_LCD_DATA03__LCDIF_DATA03      0x10
 199                         MX6UL_PAD_LCD_DATA04__LCDIF_DATA04      0x10
 200                         MX6UL_PAD_LCD_DATA05__LCDIF_DATA05      0x10
 201                         MX6UL_PAD_LCD_DATA06__LCDIF_DATA06      0x10
 202                         MX6UL_PAD_LCD_DATA07__LCDIF_DATA07      0x10
 203                         /* LCD_DATA08..09 not wired */
 204                         MX6UL_PAD_LCD_DATA10__LCDIF_DATA10      0x10
 205                         MX6UL_PAD_LCD_DATA11__LCDIF_DATA11      0x10
 206                         MX6UL_PAD_LCD_DATA12__LCDIF_DATA12      0x10
 207                         MX6UL_PAD_LCD_DATA13__LCDIF_DATA13      0x10
 208                         MX6UL_PAD_LCD_DATA14__LCDIF_DATA14      0x10
 209                         MX6UL_PAD_LCD_DATA15__LCDIF_DATA15      0x10
 210                         /* LCD_DATA16..17 not wired */
 211                         MX6UL_PAD_LCD_DATA18__LCDIF_DATA18      0x10
 212                         MX6UL_PAD_LCD_DATA19__LCDIF_DATA19      0x10
 213                         MX6UL_PAD_LCD_DATA20__LCDIF_DATA20      0x10
 214                         MX6UL_PAD_LCD_DATA21__LCDIF_DATA21      0x10
 215                         MX6UL_PAD_LCD_DATA22__LCDIF_DATA22      0x10
 216                         MX6UL_PAD_LCD_DATA23__LCDIF_DATA23      0x10
 217                 >;
 218         };
 219
 220         pinctrl_enet2_mdio: enet2-mdiogrp {
 221                 fsl,pins = <
 222                         MX6UL_PAD_GPIO1_IO07__ENET2_MDC         0x0b0b0
 223                         MX6UL_PAD_GPIO1_IO06__ENET2_MDIO        0x1b0b0
 224                 >;
 225         };
 226
 227         pinctrl_uart3: uart3grp {
 228                 fsl,pins = <
 229                         MX6UL_PAD_UART3_TX_DATA__UART3_DCE_TX   0x0b0b0
 230                         MX6UL_PAD_UART3_RX_DATA__UART3_DCE_RX   0x0b0b0
 231                 >;
 232         };
 233
 234         pinctrl_uart4: uart4grp {
 235                 fsl,pins = <
 236                         MX6UL_PAD_UART4_TX_DATA__UART4_DCE_TX   0x0b0b0
 237                         MX6UL_PAD_UART4_RX_DATA__UART4_DCE_RX   0x0b0b0
 238                 >;
 239         };
 240
 241         pinctrl_uart6: uart6grp {
 242                 fsl,pins = <
 243                         MX6UL_PAD_CSI_MCLK__UART6_DCE_TX        0x0b0b0
 244                         MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX      0x0b0b0
 245                 >;
 246         };
 247
 248         pinctrl_uart7: uart7grp {
 249                 fsl,pins = <
 250                         MX6UL_PAD_LCD_DATA16__UART7_DCE_TX      0x0b0b0
 251                         MX6UL_PAD_LCD_DATA17__UART7_DCE_RX      0x0b0b0
 252                 >;
 253         };
 254
 255         pinctrl_uart8: uart8grp {
 256                 fsl,pins = <
 257                         MX6UL_PAD_LCD_DATA20__UART8_DCE_TX      0x0b0b0
 258                         MX6UL_PAD_LCD_DATA21__UART8_DCE_RX      0x0b0b0
 259                 >;
 260         };
 261 };