arch/arm/boot/dts/imx6ul.dtsi

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <dt-bindings/clock/imx6ul-clock.h>
  10 #include <dt-bindings/gpio/gpio.h>
  11 #include <dt-bindings/input/input.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include "imx6ul-pinfunc.h"
  14 #include "skeleton.dtsi"
  15
  16 / {
  17         aliases {
  18                 ethernet0 = &fec1;
  19                 ethernet1 = &fec2;
  20                 gpio0 = &gpio1;
  21                 gpio1 = &gpio2;
  22                 gpio2 = &gpio3;
  23                 gpio3 = &gpio4;
  24                 gpio4 = &gpio5;
  25                 i2c0 = &i2c1;
  26                 i2c1 = &i2c2;
  27                 i2c2 = &i2c3;
  28                 i2c3 = &i2c4;
  29                 mmc0 = &usdhc1;
  30                 mmc1 = &usdhc2;
  31                 serial0 = &uart1;
  32                 serial1 = &uart2;
  33                 serial2 = &uart3;
  34                 serial3 = &uart4;
  35                 serial4 = &uart5;
  36                 serial5 = &uart6;
  37                 serial6 = &uart7;
  38                 serial7 = &uart8;
  39                 spi0 = &ecspi1;
  40                 spi1 = &ecspi2;
  41                 spi2 = &ecspi3;
  42                 spi3 = &ecspi4;
  43                 usbphy0 = &usbphy1;
  44                 usbphy1 = &usbphy2;
  45         };
  46
  47         cpus {
  48                 #address-cells = <1>;
  49                 #size-cells = <0>;
  50
  51                 cpu0: cpu@0 {
  52                         compatible = "arm,cortex-a7";
  53                         device_type = "cpu";
  54                         reg = <0>;
  55                         clock-latency = <61036>; /* two CLK32 periods */
  56                         operating-points = <
  57                                 /* kHz  uV */
  58                                 528000  1250000
  59                                 396000  1150000
  60                                 198000  1150000
  61                         >;
  62                         fsl,soc-operating-points = <
  63                                 /* KHz  uV */
  64                                 528000  1250000
  65                                 396000  1150000
  66                                 198000  1150000
  67                         >;
  68                         clocks = <&clks IMX6UL_CLK_ARM>,
  69                                  <&clks IMX6UL_CLK_PLL2_BUS>,
  70                                  <&clks IMX6UL_CLK_PLL2_PFD2>,
  71                                  <&clks IMX6UL_CA7_SECONDARY_SEL>,
  72                                  <&clks IMX6UL_CLK_STEP>,
  73                                  <&clks IMX6UL_CLK_PLL1_SW>,
  74                                  <&clks IMX6UL_CLK_PLL1_SYS>,
  75                                  <&clks IMX6UL_PLL1_BYPASS>,
  76                                  <&clks IMX6UL_CLK_PLL1>,
  77                                  <&clks IMX6UL_PLL1_BYPASS_SRC>,
  78                                  <&clks IMX6UL_CLK_OSC>;
  79                         clock-names = "arm", "pll2_bus",  "pll2_pfd2_396m",
  80                                       "secondary_sel", "step", "pll1_sw",
  81                                       "pll1_sys", "pll1_bypass", "pll1",
  82                                       "pll1_bypass_src", "osc";
  83                         arm-supply = <&reg_arm>;
  84                         soc-supply = <&reg_soc>;
  85                 };
  86         };
  87
  88         intc: interrupt-controller@00a01000 {
  89                 compatible = "arm,cortex-a7-gic";
  90                 #interrupt-cells = <3>;
  91                 interrupt-controller;
  92                 reg = <0x00a01000 0x1000>,
  93                       <0x00a02000 0x1000>,
  94                       <0x00a04000 0x2000>,
  95                       <0x00a06000 0x2000>;
  96         };
  97
  98         ckil: clock-cli {
  99                 compatible = "fixed-clock";
 100                 #clock-cells = <0>;
 101                 clock-frequency = <32768>;
 102                 clock-output-names = "ckil";
 103         };
 104
 105         osc: clock-osc {
 106                 compatible = "fixed-clock";
 107                 #clock-cells = <0>;
 108                 clock-frequency = <24000000>;
 109                 clock-output-names = "osc";
 110         };
 111
 112         ipp_di0: clock-di0 {
 113                 compatible = "fixed-clock";
 114                 #clock-cells = <0>;
 115                 clock-frequency = <0>;
 116                 clock-output-names = "ipp_di0";
 117         };
 118
 119         ipp_di1: clock-di1 {
 120                 compatible = "fixed-clock";
 121                 #clock-cells = <0>;
 122                 clock-frequency = <0>;
 123                 clock-output-names = "ipp_di1";
 124         };
 125
 126         soc {
 127                 #address-cells = <1>;
 128                 #size-cells = <1>;
 129                 compatible = "simple-bus";
 130                 interrupt-parent = <&gpc>;
 131                 ranges;
 132
 133                 pmu {
 134                         compatible = "arm,cortex-a7-pmu";
 135                         interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
 136                         status = "disabled";
 137                 };
 138
 139                 ocram: sram@00900000 {
 140                         compatible = "mmio-sram";
 141                         reg = <0x00900000 0x20000>;
 142                 };
 143
 144                 dma_apbh: dma-apbh@01804000 {
 145                         compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
 146                         reg = <0x01804000 0x2000>;
 147                         interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
 148                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 149                                      <0 13 IRQ_TYPE_LEVEL_HIGH>,
 150                                      <0 13 IRQ_TYPE_LEVEL_HIGH>;
 151                         interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
 152                         #dma-cells = <1>;
 153                         dma-channels = <4>;
 154                         clocks = <&clks IMX6UL_CLK_APBHDMA>;
 155                 };
 156
 157                 gpmi: gpmi-nand@01806000         {
 158                         compatible = "fsl,imx6q-gpmi-nand";
 159                         #address-cells = <1>;
 160                         #size-cells = <1>;
 161                         reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
 162                         reg-names = "gpmi-nand", "bch";
 163                         interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
 164                         interrupt-names = "bch";
 165                         clocks = <&clks IMX6UL_CLK_GPMI_IO>,
 166                                  <&clks IMX6UL_CLK_GPMI_APB>,
 167                                  <&clks IMX6UL_CLK_GPMI_BCH>,
 168                                  <&clks IMX6UL_CLK_GPMI_BCH_APB>,
 169                                  <&clks IMX6UL_CLK_PER_BCH>;
 170                         clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
 171                                       "gpmi_bch_apb", "per1_bch";
 172                         dmas = <&dma_apbh 0>;
 173                         dma-names = "rx-tx";
 174                         status = "disabled";
 175                 };
 176
 177                 aips1: aips-bus@02000000 {
 178                         compatible = "fsl,aips-bus", "simple-bus";
 179                         #address-cells = <1>;
 180                         #size-cells = <1>;
 181                         reg = <0x02000000 0x100000>;
 182                         ranges;
 183
 184                         spba-bus@02000000 {
 185                                 compatible = "fsl,spba-bus", "simple-bus";
 186                                 #address-cells = <1>;
 187                                 #size-cells = <1>;
 188                                 reg = <0x02000000 0x40000>;
 189                                 ranges;
 190
 191                                 ecspi1: ecspi@02008000 {
 192                                         #address-cells = <1>;
 193                                         #size-cells = <0>;
 194                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 195                                         reg = <0x02008000 0x4000>;
 196                                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
 197                                         clocks = <&clks IMX6UL_CLK_ECSPI1>,
 198                                                  <&clks IMX6UL_CLK_ECSPI1>;
 199                                         clock-names = "ipg", "per";
 200                                         status = "disabled";
 201                                 };
 202
 203                                 ecspi2: ecspi@0200c000 {
 204                                         #address-cells = <1>;
 205                                         #size-cells = <0>;
 206                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 207                                         reg = <0x0200c000 0x4000>;
 208                                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 209                                         clocks = <&clks IMX6UL_CLK_ECSPI2>,
 210                                                  <&clks IMX6UL_CLK_ECSPI2>;
 211                                         clock-names = "ipg", "per";
 212                                         status = "disabled";
 213                                 };
 214
 215                                 ecspi3: ecspi@02010000 {
 216                                         #address-cells = <1>;
 217                                         #size-cells = <0>;
 218                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 219                                         reg = <0x02010000 0x4000>;
 220                                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 221                                         clocks = <&clks IMX6UL_CLK_ECSPI3>,
 222                                                  <&clks IMX6UL_CLK_ECSPI3>;
 223                                         clock-names = "ipg", "per";
 224                                         status = "disabled";
 225                                 };
 226
 227                                 ecspi4: ecspi@02014000 {
 228                                         #address-cells = <1>;
 229                                         #size-cells = <0>;
 230                                         compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
 231                                         reg = <0x02014000 0x4000>;
 232                                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 233                                         clocks = <&clks IMX6UL_CLK_ECSPI4>,
 234                                                  <&clks IMX6UL_CLK_ECSPI4>;
 235                                         clock-names = "ipg", "per";
 236                                         status = "disabled";
 237                                 };
 238
 239                                 uart7: serial@02018000 {
 240                                         compatible = "fsl,imx6ul-uart",
 241                                                      "fsl,imx6q-uart";
 242                                         reg = <0x02018000 0x4000>;
 243                                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 244                                         clocks = <&clks IMX6UL_CLK_UART7_IPG>,
 245                                                  <&clks IMX6UL_CLK_UART7_SERIAL>;
 246                                         clock-names = "ipg", "per";
 247                                         status = "disabled";
 248                                 };
 249
 250                                 uart1: serial@02020000 {
 251                                         compatible = "fsl,imx6ul-uart",
 252                                                      "fsl,imx6q-uart";
 253                                         reg = <0x02020000 0x4000>;
 254                                         interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
 255                                         clocks = <&clks IMX6UL_CLK_UART1_IPG>,
 256                                                  <&clks IMX6UL_CLK_UART1_SERIAL>;
 257                                         clock-names = "ipg", "per";
 258                                         status = "disabled";
 259                                 };
 260
 261                                 uart8: serial@02024000 {
 262                                         compatible = "fsl,imx6ul-uart",
 263                                                      "fsl,imx6q-uart";
 264                                         reg = <0x02024000 0x4000>;
 265                                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 266                                         clocks = <&clks IMX6UL_CLK_UART8_IPG>,
 267                                                  <&clks IMX6UL_CLK_UART8_SERIAL>;
 268                                         clock-names = "ipg", "per";
 269                                         status = "disabled";
 270                                 };
 271
 272                                 sai1: sai@02028000 {
 273                                         #sound-dai-cells = <0>;
 274                                         compatible = "fsl,imx6q-ssi",
 275                                                         "fsl,imx51-ssi";
 276                                         reg = <0x02028000 0x4000>;
 277                                         interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 278                                         clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
 279                                                  <&clks IMX6UL_CLK_SAI1>;
 280                                         clock-names = "ipg", "baud";
 281                                         dmas = <&sdma 35 1 0>,
 282                                                <&sdma 36 1 0>;
 283                                         dma-names = "rx", "tx";
 284                                         fsl,fifo-depth = <15>;
 285                                         status = "disabled";
 286                                 };
 287
 288                                 sai2: sai@0202c000 {
 289                                         #sound-dai-cells = <0>;
 290                                         compatible = "fsl,imx6q-ssi",
 291                                                         "fsl,imx51-ssi";
 292                                         reg = <0x0202c000 0x4000>;
 293                                         interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
 294                                         clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
 295                                                  <&clks IMX6UL_CLK_SAI2>;
 296                                         clock-names = "ipg", "baud";
 297                                         dmas = <&sdma 37 1 0>,
 298                                                <&sdma 38 1 0>;
 299                                         dma-names = "rx", "tx";
 300                                         fsl,fifo-depth = <15>;
 301                                         status = "disabled";
 302                                 };
 303
 304                                 sai3: sai@02030000 {
 305                                         #sound-dai-cells = <0>;
 306                                         compatible = "fsl,imx6q-ssi",
 307                                                         "fsl,imx51-ssi";
 308                                         reg = <0x02030000 0x4000>;
 309                                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 310                                         clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
 311                                                  <&clks IMX6UL_CLK_SAI3>;
 312                                         clock-names = "ipg", "baud";
 313                                         dmas = <&sdma 39 1 0>,
 314                                                <&sdma 40 1 0>;
 315                                         dma-names = "rx", "tx";
 316                                         fsl,fifo-depth = <15>;
 317                                         status = "disabled";
 318                                 };
 319                         };
 320
 321                         tsc: tsc@02040000 {
 322                                 compatible = "fsl,imx6ul-tsc";
 323                                 reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
 324                                 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 325                                              <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
 326                                 clocks = <&clks IMX6UL_CLK_IPG>,
 327                                          <&clks IMX6UL_CLK_ADC2>;
 328                                 clock-names = "tsc", "adc";
 329                                 status = "disabled";
 330                         };
 331
 332                         can1: flexcan@02090000 {
 333                                 compatible = "fsl,imx6q-flexcan";
 334                                 reg = <0x02090000 0x4000>;
 335                                 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 336                                 clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
 337                                          <&clks IMX6UL_CLK_CAN1_SERIAL>;
 338                                 clock-names = "ipg", "per";
 339                                 status = "disabled";
 340                         };
 341
 342                         can2: flexcan@02094000 {
 343                                 compatible = "fsl,imx6q-flexcan";
 344                                 reg = <0x02094000 0x4000>;
 345                                 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
 346                                 clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
 347                                          <&clks IMX6UL_CLK_CAN2_SERIAL>;
 348                                 clock-names = "ipg", "per";
 349                                 status = "disabled";
 350                         };
 351
 352                         gpt1: gpt@02098000 {
 353                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 354                                 reg = <0x02098000 0x4000>;
 355                                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 356                                 clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
 357                                          <&clks IMX6UL_CLK_GPT1_SERIAL>;
 358                                 clock-names = "ipg", "per";
 359                         };
 360
 361                         gpio1: gpio@0209c000 {
 362                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 363                                 reg = <0x0209c000 0x4000>;
 364                                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
 365                                              <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 366                                 gpio-controller;
 367                                 #gpio-cells = <2>;
 368                                 interrupt-controller;
 369                                 #interrupt-cells = <2>;
 370                         };
 371
 372                         gpio2: gpio@020a0000 {
 373                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 374                                 reg = <0x020a0000 0x4000>;
 375                                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 376                                              <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
 377                                 gpio-controller;
 378                                 #gpio-cells = <2>;
 379                                 interrupt-controller;
 380                                 #interrupt-cells = <2>;
 381                         };
 382
 383                         gpio3: gpio@020a4000 {
 384                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 385                                 reg = <0x020a4000 0x4000>;
 386                                 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
 387                                              <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
 388                                 gpio-controller;
 389                                 #gpio-cells = <2>;
 390                                 interrupt-controller;
 391                                 #interrupt-cells = <2>;
 392                         };
 393
 394                         gpio4: gpio@020a8000 {
 395                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 396                                 reg = <0x020a8000 0x4000>;
 397                                 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 398                                              <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 399                                 gpio-controller;
 400                                 #gpio-cells = <2>;
 401                                 interrupt-controller;
 402                                 #interrupt-cells = <2>;
 403                         };
 404
 405                         gpio5: gpio@020ac000 {
 406                                 compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
 407                                 reg = <0x020ac000 0x4000>;
 408                                 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
 409                                              <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 410                                 gpio-controller;
 411                                 #gpio-cells = <2>;
 412                                 interrupt-controller;
 413                                 #interrupt-cells = <2>;
 414                         };
 415
 416                         fec2: ethernet@020b4000 {
 417                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 418                                 reg = <0x020b4000 0x4000>;
 419                                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 420                                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 421                                 clocks = <&clks IMX6UL_CLK_ENET>,
 422                                          <&clks IMX6UL_CLK_ENET_AHB>,
 423                                          <&clks IMX6UL_CLK_ENET_PTP>,
 424                                          <&clks IMX6UL_CLK_ENET2_REF_125M>,
 425                                          <&clks IMX6UL_CLK_ENET2_REF_125M>;
 426                                 clock-names = "ipg", "ahb", "ptp",
 427                                               "enet_clk_ref", "enet_out";
 428                                 fsl,num-tx-queues=<1>;
 429                                 fsl,num-rx-queues=<1>;
 430                                 status = "disabled";
 431                         };
 432
 433                         kpp: kpp@020b8000 {
 434                                 compatible = "fsl,imx6q-kpp", "fsl,imx21-kpp";
 435                                 reg = <0x020b8000 0x4000>;
 436                                 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 437                                 clocks = <&clks IMX6UL_CLK_KPP>;
 438                                 status = "disabled";
 439                         };
 440
 441                         wdog1: wdog@020bc000 {
 442                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 443                                 reg = <0x020bc000 0x4000>;
 444                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
 445                                 clocks = <&clks IMX6UL_CLK_WDOG1>;
 446                         };
 447
 448                         wdog2: wdog@020c0000 {
 449                                 compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
 450                                 reg = <0x020c0000 0x4000>;
 451                                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
 452                                 clocks = <&clks IMX6UL_CLK_WDOG2>;
 453                                 status = "disabled";
 454                         };
 455
 456                         clks: ccm@020c4000 {
 457                                 compatible = "fsl,imx6ul-ccm";
 458                                 reg = <0x020c4000 0x4000>;
 459                                 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
 460                                              <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 461                                 #clock-cells = <1>;
 462                                 clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
 463                                 clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
 464                         };
 465
 466                         anatop: anatop@020c8000 {
 467                                 compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
 468                                              "syscon", "simple-bus";
 469                                 reg = <0x020c8000 0x1000>;
 470                                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
 471                                              <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
 472                                              <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
 473
 474                                 reg_3p0: regulator-3p0@120 {
 475                                         compatible = "fsl,anatop-regulator";
 476                                         regulator-name = "vdd3p0";
 477                                         regulator-min-microvolt = <2625000>;
 478                                         regulator-max-microvolt = <3400000>;
 479                                         anatop-reg-offset = <0x120>;
 480                                         anatop-vol-bit-shift = <8>;
 481                                         anatop-vol-bit-width = <5>;
 482                                         anatop-min-bit-val = <0>;
 483                                         anatop-min-voltage = <2625000>;
 484                                         anatop-max-voltage = <3400000>;
 485                                         anatop-enable-bit = <0>;
 486                                 };
 487
 488                                 reg_arm: regulator-vddcore@140 {
 489                                         compatible = "fsl,anatop-regulator";
 490                                         regulator-name = "cpu";
 491                                         regulator-min-microvolt = <725000>;
 492                                         regulator-max-microvolt = <1450000>;
 493                                         regulator-always-on;
 494                                         anatop-reg-offset = <0x140>;
 495                                         anatop-vol-bit-shift = <0>;
 496                                         anatop-vol-bit-width = <5>;
 497                                         anatop-delay-reg-offset = <0x170>;
 498                                         anatop-delay-bit-shift = <24>;
 499                                         anatop-delay-bit-width = <2>;
 500                                         anatop-min-bit-val = <1>;
 501                                         anatop-min-voltage = <725000>;
 502                                         anatop-max-voltage = <1450000>;
 503                                 };
 504
 505                                 reg_soc: regulator-vddsoc@140 {
 506                                         compatible = "fsl,anatop-regulator";
 507                                         regulator-name = "vddsoc";
 508                                         regulator-min-microvolt = <725000>;
 509                                         regulator-max-microvolt = <1450000>;
 510                                         regulator-always-on;
 511                                         anatop-reg-offset = <0x140>;
 512                                         anatop-vol-bit-shift = <18>;
 513                                         anatop-vol-bit-width = <5>;
 514                                         anatop-delay-reg-offset = <0x170>;
 515                                         anatop-delay-bit-shift = <28>;
 516                                         anatop-delay-bit-width = <2>;
 517                                         anatop-min-bit-val = <1>;
 518                                         anatop-min-voltage = <725000>;
 519                                         anatop-max-voltage = <1450000>;
 520                                 };
 521                         };
 522
 523                         usbphy1: usbphy@020c9000 {
 524                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 525                                 reg = <0x020c9000 0x1000>;
 526                                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 527                                 clocks = <&clks IMX6UL_CLK_USBPHY1>;
 528                                 phy-3p0-supply = <&reg_3p0>;
 529                                 fsl,anatop = <&anatop>;
 530                         };
 531
 532                         usbphy2: usbphy@020ca000 {
 533                                 compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
 534                                 reg = <0x020ca000 0x1000>;
 535                                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 536                                 clocks = <&clks IMX6UL_CLK_USBPHY2>;
 537                                 phy-3p0-supply = <&reg_3p0>;
 538                                 fsl,anatop = <&anatop>;
 539                         };
 540
 541                         snvs: snvs@020cc000 {
 542                                 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
 543                                 reg = <0x020cc000 0x4000>;
 544
 545                                 snvs_rtc: snvs-rtc-lp {
 546                                         compatible = "fsl,sec-v4.0-mon-rtc-lp";
 547                                         regmap = <&snvs>;
 548                                         offset = <0x34>;
 549                                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 550                                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
 551                                 };
 552
 553                                 snvs_poweroff: snvs-poweroff {
 554                                         compatible = "syscon-poweroff";
 555                                         regmap = <&snvs>;
 556                                         offset = <0x38>;
 557                                         mask = <0x60>;
 558                                         status = "disabled";
 559                                 };
 560
 561                                 snvs_pwrkey: snvs-powerkey {
 562                                         compatible = "fsl,sec-v4.0-pwrkey";
 563                                         regmap = <&snvs>;
 564                                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 565                                         linux,keycode = <KEY_POWER>;
 566                                         wakeup-source;
 567                                 };
 568                         };
 569
 570                         epit1: epit@020d0000 {
 571                                 reg = <0x020d0000 0x4000>;
 572                                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 573                         };
 574
 575                         epit2: epit@020d4000 {
 576                                 reg = <0x020d4000 0x4000>;
 577                                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
 578                         };
 579
 580                         src: src@020d8000 {
 581                                 compatible = "fsl,imx6ul-src", "fsl,imx51-src";
 582                                 reg = <0x020d8000 0x4000>;
 583                                 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
 584                                              <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 585                                 #reset-cells = <1>;
 586                         };
 587
 588                         gpc: gpc@020dc000 {
 589                                 compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
 590                                 reg = <0x020dc000 0x4000>;
 591                                 interrupt-controller;
 592                                 #interrupt-cells = <3>;
 593                                 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 594                                 interrupt-parent = <&intc>;
 595                         };
 596
 597                         iomuxc: iomuxc@020e0000 {
 598                                 compatible = "fsl,imx6ul-iomuxc";
 599                                 reg = <0x020e0000 0x4000>;
 600                         };
 601
 602                         gpr: iomuxc-gpr@020e4000 {
 603                                 compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
 604                                 reg = <0x020e4000 0x4000>;
 605                         };
 606
 607                         gpt2: gpt@020e8000 {
 608                                 compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
 609                                 reg = <0x020e8000 0x4000>;
 610                                 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
 611                                 clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
 612                                          <&clks IMX6UL_CLK_GPT2_SERIAL>;
 613                                 clock-names = "ipg", "per";
 614                         };
 615
 616                         sdma: sdma@020ec000 {
 617                                 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
 618                                 reg = <0x020ec000 0x4000>;
 619                                 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 620                                 clocks = <&clks IMX6UL_CLK_SDMA>,
 621                                          <&clks IMX6UL_CLK_SDMA>;
 622                                 clock-names = "ipg", "ahb";
 623                                 #dma-cells = <3>;
 624                                 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
 625                         };
 626
 627                         pwm5: pwm@020f0000 {
 628                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 629                                 reg = <0x020f0000 0x4000>;
 630                                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 631                                 clocks = <&clks IMX6UL_CLK_PWM5>,
 632                                          <&clks IMX6UL_CLK_PWM5>;
 633                                 clock-names = "ipg", "per";
 634                                 #pwm-cells = <2>;
 635                         };
 636
 637                         pwm6: pwm@020f4000 {
 638                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 639                                 reg = <0x020f4000 0x4000>;
 640                                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
 641                                 clocks = <&clks IMX6UL_CLK_PWM6>,
 642                                          <&clks IMX6UL_CLK_PWM6>;
 643                                 clock-names = "ipg", "per";
 644                                 #pwm-cells = <2>;
 645                         };
 646
 647                         pwm7: pwm@020f8000 {
 648                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 649                                 reg = <0x020f8000 0x4000>;
 650                                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
 651                                 clocks = <&clks IMX6UL_CLK_PWM7>,
 652                                          <&clks IMX6UL_CLK_PWM7>;
 653                                 clock-names = "ipg", "per";
 654                                 #pwm-cells = <2>;
 655                         };
 656
 657                         pwm8: pwm@020fc000 {
 658                                 compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
 659                                 reg = <0x020fc000 0x4000>;
 660                                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
 661                                 clocks = <&clks IMX6UL_CLK_PWM8>,
 662                                          <&clks IMX6UL_CLK_PWM8>;
 663                                 clock-names = "ipg", "per";
 664                                 #pwm-cells = <2>;
 665                         };
 666                 };
 667
 668                 aips2: aips-bus@02100000 {
 669                         compatible = "fsl,aips-bus", "simple-bus";
 670                         #address-cells = <1>;
 671                         #size-cells = <1>;
 672                         reg = <0x02100000 0x100000>;
 673                         ranges;
 674
 675                         usbotg1: usb@02184000 {
 676                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 677                                 reg = <0x02184000 0x200>;
 678                                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 679                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 680                                 fsl,usbphy = <&usbphy1>;
 681                                 fsl,usbmisc = <&usbmisc 0>;
 682                                 fsl,anatop = <&anatop>;
 683                                 status = "disabled";
 684                         };
 685
 686                         usbotg2: usb@02184200 {
 687                                 compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
 688                                 reg = <0x02184200 0x200>;
 689                                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 690                                 clocks = <&clks IMX6UL_CLK_USBOH3>;
 691                                 fsl,usbphy = <&usbphy2>;
 692                                 fsl,usbmisc = <&usbmisc 1>;
 693                                 status = "disabled";
 694                         };
 695
 696                         usbmisc: usbmisc@02184800 {
 697                                 #index-cells = <1>;
 698                                 compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
 699                                 reg = <0x02184800 0x200>;
 700                         };
 701
 702                         fec1: ethernet@02188000 {
 703                                 compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
 704                                 reg = <0x02188000 0x4000>;
 705                                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
 706                                              <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 707                                 clocks = <&clks IMX6UL_CLK_ENET>,
 708                                          <&clks IMX6UL_CLK_ENET_AHB>,
 709                                          <&clks IMX6UL_CLK_ENET_PTP>,
 710                                          <&clks IMX6UL_CLK_ENET_REF>,
 711                                          <&clks IMX6UL_CLK_ENET_REF>;
 712                                 clock-names = "ipg", "ahb", "ptp",
 713                                               "enet_clk_ref", "enet_out";
 714                                 fsl,num-tx-queues=<1>;
 715                                 fsl,num-rx-queues=<1>;
 716                                 status = "disabled";
 717                         };
 718
 719                         usdhc1: usdhc@02190000 {
 720                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 721                                 reg = <0x02190000 0x4000>;
 722                                 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 723                                 clocks = <&clks IMX6UL_CLK_USDHC1>,
 724                                          <&clks IMX6UL_CLK_USDHC1>,
 725                                          <&clks IMX6UL_CLK_USDHC1>;
 726                                 clock-names = "ipg", "ahb", "per";
 727                                 bus-width = <4>;
 728                                 status = "disabled";
 729                         };
 730
 731                         usdhc2: usdhc@02194000 {
 732                                 compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
 733                                 reg = <0x02194000 0x4000>;
 734                                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
 735                                 clocks = <&clks IMX6UL_CLK_USDHC2>,
 736                                          <&clks IMX6UL_CLK_USDHC2>,
 737                                          <&clks IMX6UL_CLK_USDHC2>;
 738                                 clock-names = "ipg", "ahb", "per";
 739                                 bus-width = <4>;
 740                                 status = "disabled";
 741                         };
 742
 743                         i2c1: i2c@021a0000 {
 744                                 #address-cells = <1>;
 745                                 #size-cells = <0>;
 746                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 747                                 reg = <0x021a0000 0x4000>;
 748                                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
 749                                 clocks = <&clks IMX6UL_CLK_I2C1>;
 750                                 status = "disabled";
 751                         };
 752
 753                         i2c2: i2c@021a4000 {
 754                                 #address-cells = <1>;
 755                                 #size-cells = <0>;
 756                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 757                                 reg = <0x021a4000 0x4000>;
 758                                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 759                                 clocks = <&clks IMX6UL_CLK_I2C2>;
 760                                 status = "disabled";
 761                         };
 762
 763                         i2c3: i2c@021a8000 {
 764                                 #address-cells = <1>;
 765                                 #size-cells = <0>;
 766                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 767                                 reg = <0x021a8000 0x4000>;
 768                                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 769                                 clocks = <&clks IMX6UL_CLK_I2C3>;
 770                                 status = "disabled";
 771                         };
 772
 773                         mmdc: mmdc@021b0000 {
 774                                 compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
 775                                 reg = <0x021b0000 0x4000>;
 776                         };
 777
 778                         lcdif: lcdif@021c8000 {
 779                                 compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
 780                                 reg = <0x021c8000 0x4000>;
 781                                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 782                                 clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
 783                                          <&clks IMX6UL_CLK_LCDIF_APB>,
 784                                          <&clks IMX6UL_CLK_DUMMY>;
 785                                 clock-names = "pix", "axi", "disp_axi";
 786                                 status = "disabled";
 787                         };
 788
 789                         qspi: qspi@021e0000 {
 790                                 #address-cells = <1>;
 791                                 #size-cells = <0>;
 792                                 compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
 793                                 reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
 794                                 reg-names = "QuadSPI", "QuadSPI-memory";
 795                                 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
 796                                 clocks = <&clks IMX6UL_CLK_QSPI>,
 797                                          <&clks IMX6UL_CLK_QSPI>;
 798                                 clock-names = "qspi_en", "qspi";
 799                                 status = "disabled";
 800                         };
 801
 802                         uart2: serial@021e8000 {
 803                                 compatible = "fsl,imx6ul-uart",
 804                                              "fsl,imx6q-uart";
 805                                 reg = <0x021e8000 0x4000>;
 806                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 807                                 clocks = <&clks IMX6UL_CLK_UART2_IPG>,
 808                                          <&clks IMX6UL_CLK_UART2_SERIAL>;
 809                                 clock-names = "ipg", "per";
 810                                 status = "disabled";
 811                         };
 812
 813                         uart3: serial@021ec000 {
 814                                 compatible = "fsl,imx6ul-uart",
 815                                              "fsl,imx6q-uart";
 816                                 reg = <0x021ec000 0x4000>;
 817                                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 818                                 clocks = <&clks IMX6UL_CLK_UART3_IPG>,
 819                                          <&clks IMX6UL_CLK_UART3_SERIAL>;
 820                                 clock-names = "ipg", "per";
 821                                 status = "disabled";
 822                         };
 823
 824                         uart4: serial@021f0000 {
 825                                 compatible = "fsl,imx6ul-uart",
 826                                              "fsl,imx6q-uart";
 827                                 reg = <0x021f0000 0x4000>;
 828                                 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 829                                 clocks = <&clks IMX6UL_CLK_UART4_IPG>,
 830                                          <&clks IMX6UL_CLK_UART4_SERIAL>;
 831                                 clock-names = "ipg", "per";
 832                                 status = "disabled";
 833                         };
 834
 835                         uart5: serial@021f4000 {
 836                                 compatible = "fsl,imx6ul-uart",
 837                                              "fsl,imx6q-uart";
 838                                 reg = <0x021f4000 0x4000>;
 839                                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
 840                                 clocks = <&clks IMX6UL_CLK_UART5_IPG>,
 841                                          <&clks IMX6UL_CLK_UART5_SERIAL>;
 842                                 clock-names = "ipg", "per";
 843                                 status = "disabled";
 844                         };
 845
 846                         i2c4: i2c@021f8000 {
 847                                 #address-cells = <1>;
 848                                 #size-cells = <0>;
 849                                 compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
 850                                 reg = <0x021f8000 0x4000>;
 851                                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 852                                 clocks = <&clks IMX6UL_CLK_I2C4>;
 853                                 status = "disabled";
 854                         };
 855
 856                         uart6: serial@021fc000 {
 857                                 compatible = "fsl,imx6ul-uart",
 858                                              "fsl,imx6q-uart";
 859                                 reg = <0x021fc000 0x4000>;
 860                                 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 861                                 clocks = <&clks IMX6UL_CLK_UART6_IPG>,
 862                                          <&clks IMX6UL_CLK_UART6_SERIAL>;
 863                                 clock-names = "ipg", "per";
 864                                 status = "disabled";
 865                         };
 866                 };
 867         };
 868 };