arch/arm/boot/dts/prima2.dtsi

   1 /*
   2  * DTS file for CSR SiRFprimaII SoC
   3  *
   4  * Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 /include/ "skeleton.dtsi"
  10 / {
  11         compatible = "sirf,prima2";
  12         #address-cells = <1>;
  13         #size-cells = <1>;
  14         interrupt-parent = <&intc>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 cpu@0 {
  21                         compatible = "arm,cortex-a9";
  22                         device_type = "cpu";
  23                         reg = <0x0>;
  24                         d-cache-line-size = <32>;
  25                         i-cache-line-size = <32>;
  26                         d-cache-size = <32768>;
  27                         i-cache-size = <32768>;
  28                         /* from bootloader */
  29                         timebase-frequency = <0>;
  30                         bus-frequency = <0>;
  31                         clock-frequency = <0>;
  32                 };
  33         };
  34
  35         axi {
  36                 compatible = "simple-bus";
  37                 #address-cells = <1>;
  38                 #size-cells = <1>;
  39                 ranges = <0x40000000 0x40000000 0x80000000>;
  40
  41                 l2-cache-controller@80040000 {
  42                         compatible = "arm,pl310-cache", "sirf,prima2-pl310-cache";
  43                         reg = <0x80040000 0x1000>;
  44                         interrupts = <59>;
  45                         arm,tag-latency = <1 1 1>;
  46                         arm,data-latency = <1 1 1>;
  47                         arm,filter-ranges = <0 0x40000000>;
  48                 };
  49
  50                 intc: interrupt-controller@80020000 {
  51                         #interrupt-cells = <1>;
  52                         interrupt-controller;
  53                         compatible = "sirf,prima2-intc";
  54                         reg = <0x80020000 0x1000>;
  55                 };
  56
  57                 sys-iobg {
  58                         compatible = "simple-bus";
  59                         #address-cells = <1>;
  60                         #size-cells = <1>;
  61                         ranges = <0x88000000 0x88000000 0x40000>;
  62
  63                         clks: clock-controller@88000000 {
  64                                 compatible = "sirf,prima2-clkc";
  65                                 reg = <0x88000000 0x1000>;
  66                                 interrupts = <3>;
  67                                 #clock-cells = <1>;
  68                         };
  69
  70                         reset-controller@88010000 {
  71                                 compatible = "sirf,prima2-rstc";
  72                                 reg = <0x88010000 0x1000>;
  73                         };
  74
  75                         rsc-controller@88020000 {
  76                                 compatible = "sirf,prima2-rsc";
  77                                 reg = <0x88020000 0x1000>;
  78                         };
  79                 };
  80
  81                 mem-iobg {
  82                         compatible = "simple-bus";
  83                         #address-cells = <1>;
  84                         #size-cells = <1>;
  85                         ranges = <0x90000000 0x90000000 0x10000>;
  86
  87                         memory-controller@90000000 {
  88                                 compatible = "sirf,prima2-memc";
  89                                 reg = <0x90000000 0x10000>;
  90                                 interrupts = <27>;
  91                                 clocks = <&clks 5>;
  92                         };
  93                 };
  94
  95                 disp-iobg {
  96                         compatible = "simple-bus";
  97                         #address-cells = <1>;
  98                         #size-cells = <1>;
  99                         ranges = <0x90010000 0x90010000 0x30000>;
 100
 101                         display@90010000 {
 102                                 compatible = "sirf,prima2-lcd";
 103                                 reg = <0x90010000 0x20000>;
 104                                 interrupts = <30>;
 105                         };
 106
 107                         vpp@90020000 {
 108                                 compatible = "sirf,prima2-vpp";
 109                                 reg = <0x90020000 0x10000>;
 110                                 interrupts = <31>;
 111                                 clocks = <&clks 35>;
 112                         };
 113                 };
 114
 115                 graphics-iobg {
 116                         compatible = "simple-bus";
 117                         #address-cells = <1>;
 118                         #size-cells = <1>;
 119                         ranges = <0x98000000 0x98000000 0x8000000>;
 120
 121                         graphics@98000000 {
 122                                 compatible = "powervr,sgx531";
 123                                 reg = <0x98000000 0x8000000>;
 124                                 interrupts = <6>;
 125                                 clocks = <&clks 32>;
 126                         };
 127                 };
 128
 129                 multimedia-iobg {
 130                         compatible = "simple-bus";
 131                         #address-cells = <1>;
 132                         #size-cells = <1>;
 133                         ranges = <0xa0000000 0xa0000000 0x8000000>;
 134
 135                         multimedia@a0000000 {
 136                                 compatible = "sirf,prima2-video-codec";
 137                                 reg = <0xa0000000 0x8000000>;
 138                                 interrupts = <5>;
 139                                 clocks = <&clks 33>;
 140                         };
 141                 };
 142
 143                 dsp-iobg {
 144                         compatible = "simple-bus";
 145                         #address-cells = <1>;
 146                         #size-cells = <1>;
 147                         ranges = <0xa8000000 0xa8000000 0x2000000>;
 148
 149                         dspif@a8000000 {
 150                                 compatible = "sirf,prima2-dspif";
 151                                 reg = <0xa8000000 0x10000>;
 152                                 interrupts = <9>;
 153                         };
 154
 155                         gps@a8010000 {
 156                                 compatible = "sirf,prima2-gps";
 157                                 reg = <0xa8010000 0x10000>;
 158                                 interrupts = <7>;
 159                                 clocks = <&clks 9>;
 160                         };
 161
 162                         dsp@a9000000 {
 163                                 compatible = "sirf,prima2-dsp";
 164                                 reg = <0xa9000000 0x1000000>;
 165                                 interrupts = <8>;
 166                                 clocks = <&clks 8>;
 167                         };
 168                 };
 169
 170                 peri-iobg {
 171                         compatible = "simple-bus";
 172                         #address-cells = <1>;
 173                         #size-cells = <1>;
 174                         ranges = <0xb0000000 0xb0000000 0x180000>;
 175
 176                         timer@b0020000 {
 177                                 compatible = "sirf,prima2-tick";
 178                                 reg = <0xb0020000 0x1000>;
 179                                 interrupts = <0>;
 180                         };
 181
 182                         nand@b0030000 {
 183                                 compatible = "sirf,prima2-nand";
 184                                 reg = <0xb0030000 0x10000>;
 185                                 interrupts = <41>;
 186                                 clocks = <&clks 26>;
 187                         };
 188
 189                         audio@b0040000 {
 190                                 compatible = "sirf,prima2-audio";
 191                                 reg = <0xb0040000 0x10000>;
 192                                 interrupts = <35>;
 193                                 clocks = <&clks 27>;
 194                         };
 195
 196                         uart0: uart@b0050000 {
 197                                 cell-index = <0>;
 198                                 compatible = "sirf,prima2-uart";
 199                                 reg = <0xb0050000 0x10000>;
 200                                 interrupts = <17>;
 201                                 clocks = <&clks 13>;
 202                         };
 203
 204                         uart1: uart@b0060000 {
 205                                 cell-index = <1>;
 206                                 compatible = "sirf,prima2-uart";
 207                                 reg = <0xb0060000 0x10000>;
 208                                 interrupts = <18>;
 209                                 clocks = <&clks 14>;
 210                         };
 211
 212                         uart2: uart@b0070000 {
 213                                 cell-index = <2>;
 214                                 compatible = "sirf,prima2-uart";
 215                                 reg = <0xb0070000 0x10000>;
 216                                 interrupts = <19>;
 217                                 clocks = <&clks 15>;
 218                         };
 219
 220                         usp0: usp@b0080000 {
 221                                 cell-index = <0>;
 222                                 compatible = "sirf,prima2-usp";
 223                                 reg = <0xb0080000 0x10000>;
 224                                 interrupts = <20>;
 225                                 clocks = <&clks 28>;
 226                         };
 227
 228                         usp1: usp@b0090000 {
 229                                 cell-index = <1>;
 230                                 compatible = "sirf,prima2-usp";
 231                                 reg = <0xb0090000 0x10000>;
 232                                 interrupts = <21>;
 233                                 clocks = <&clks 29>;
 234                         };
 235
 236                         usp2: usp@b00a0000 {
 237                                 cell-index = <2>;
 238                                 compatible = "sirf,prima2-usp";
 239                                 reg = <0xb00a0000 0x10000>;
 240                                 interrupts = <22>;
 241                                 clocks = <&clks 30>;
 242                         };
 243
 244                         dmac0: dma-controller@b00b0000 {
 245                                 cell-index = <0>;
 246                                 compatible = "sirf,prima2-dmac";
 247                                 reg = <0xb00b0000 0x10000>;
 248                                 interrupts = <12>;
 249                                 clocks = <&clks 24>;
 250                         };
 251
 252                         dmac1: dma-controller@b0160000 {
 253                                 cell-index = <1>;
 254                                 compatible = "sirf,prima2-dmac";
 255                                 reg = <0xb0160000 0x10000>;
 256                                 interrupts = <13>;
 257                                 clocks = <&clks 25>;
 258                         };
 259
 260                         vip@b00C0000 {
 261                                 compatible = "sirf,prima2-vip";
 262                                 reg = <0xb00C0000 0x10000>;
 263                                 clocks = <&clks 31>;
 264                         };
 265
 266                         spi0: spi@b00d0000 {
 267                                 cell-index = <0>;
 268                                 compatible = "sirf,prima2-spi";
 269                                 reg = <0xb00d0000 0x10000>;
 270                                 interrupts = <15>;
 271                                 clocks = <&clks 19>;
 272                         };
 273
 274                         spi1: spi@b0170000 {
 275                                 cell-index = <1>;
 276                                 compatible = "sirf,prima2-spi";
 277                                 reg = <0xb0170000 0x10000>;
 278                                 interrupts = <16>;
 279                                 clocks = <&clks 20>;
 280                         };
 281
 282                         i2c0: i2c@b00e0000 {
 283                                 cell-index = <0>;
 284                                 compatible = "sirf,prima2-i2c";
 285                                 reg = <0xb00e0000 0x10000>;
 286                                 interrupts = <24>;
 287                                 clocks = <&clks 17>;
 288                         };
 289
 290                         i2c1: i2c@b00f0000 {
 291                                 cell-index = <1>;
 292                                 compatible = "sirf,prima2-i2c";
 293                                 reg = <0xb00f0000 0x10000>;
 294                                 interrupts = <25>;
 295                                 clocks = <&clks 18>;
 296                         };
 297
 298                         tsc@b0110000 {
 299                                 compatible = "sirf,prima2-tsc";
 300                                 reg = <0xb0110000 0x10000>;
 301                                 interrupts = <33>;
 302                                 clocks = <&clks 16>;
 303                         };
 304
 305                         gpio: pinctrl@b0120000 {
 306                                 #gpio-cells = <2>;
 307                                 #interrupt-cells = <2>;
 308                                 compatible = "sirf,prima2-pinctrl";
 309                                 reg = <0xb0120000 0x10000>;
 310                                 interrupts = <43 44 45 46 47>;
 311                                 gpio-controller;
 312                                 interrupt-controller;
 313
 314                                 lcd_16pins_a: lcd0@0 {
 315                                         lcd {
 316                                                 sirf,pins = "lcd_16bitsgrp";
 317                                                 sirf,function = "lcd_16bits";
 318                                         };
 319                                 };
 320                                 lcd_18pins_a: lcd0@1 {
 321                                         lcd {
 322                                                 sirf,pins = "lcd_18bitsgrp";
 323                                                 sirf,function = "lcd_18bits";
 324                                         };
 325                                 };
 326                                 lcd_24pins_a: lcd0@2 {
 327                                         lcd {
 328                                                 sirf,pins = "lcd_24bitsgrp";
 329                                                 sirf,function = "lcd_24bits";
 330                                         };
 331                                 };
 332                                 lcdrom_pins_a: lcdrom0@0 {
 333                                         lcd {
 334                                                 sirf,pins = "lcdromgrp";
 335                                                 sirf,function = "lcdrom";
 336                                         };
 337                                 };
 338                                 uart0_pins_a: uart0@0 {
 339                                         uart {
 340                                                 sirf,pins = "uart0grp";
 341                                                 sirf,function = "uart0";
 342                                         };
 343                                 };
 344                                 uart1_pins_a: uart1@0 {
 345                                         uart {
 346                                                 sirf,pins = "uart1grp";
 347                                                 sirf,function = "uart1";
 348                                         };
 349                                 };
 350                                 uart2_pins_a: uart2@0 {
 351                                         uart {
 352                                                 sirf,pins = "uart2grp";
 353                                                 sirf,function = "uart2";
 354                                         };
 355                                 };
 356                                 uart2_noflow_pins_a: uart2@1 {
 357                                         uart {
 358                                                 sirf,pins = "uart2_nostreamctrlgrp";
 359                                                 sirf,function = "uart2_nostreamctrl";
 360                                         };
 361                                 };
 362                                 spi0_pins_a: spi0@0 {
 363                                         spi {
 364                                                 sirf,pins = "spi0grp";
 365                                                 sirf,function = "spi0";
 366                                         };
 367                                 };
 368                                 spi1_pins_a: spi1@0 {
 369                                         spi {
 370                                                 sirf,pins = "spi1grp";
 371                                                 sirf,function = "spi1";
 372                                         };
 373                                 };
 374                                 i2c0_pins_a: i2c0@0 {
 375                                         i2c {
 376                                                 sirf,pins = "i2c0grp";
 377                                                 sirf,function = "i2c0";
 378                                         };
 379                                 };
 380                                 i2c1_pins_a: i2c1@0 {
 381                                         i2c {
 382                                                 sirf,pins = "i2c1grp";
 383                                                 sirf,function = "i2c1";
 384                                         };
 385                                 };
 386                                 pwm0_pins_a: pwm0@0 {
 387                                         pwm {
 388                                                 sirf,pins = "pwm0grp";
 389                                                 sirf,function = "pwm0";
 390                                         };
 391                                 };
 392                                 pwm1_pins_a: pwm1@0 {
 393                                         pwm {
 394                                                 sirf,pins = "pwm1grp";
 395                                                 sirf,function = "pwm1";
 396                                         };
 397                                 };
 398                                 pwm2_pins_a: pwm2@0 {
 399                                         pwm {
 400                                                 sirf,pins = "pwm2grp";
 401                                                 sirf,function = "pwm2";
 402                                         };
 403                                 };
 404                                 pwm3_pins_a: pwm3@0 {
 405                                         pwm {
 406                                                 sirf,pins = "pwm3grp";
 407                                                 sirf,function = "pwm3";
 408                                         };
 409                                 };
 410                                 gps_pins_a: gps@0 {
 411                                         gps {
 412                                                 sirf,pins = "gpsgrp";
 413                                                 sirf,function = "gps";
 414                                         };
 415                                 };
 416                                 vip_pins_a: vip@0 {
 417                                         vip {
 418                                                 sirf,pins = "vipgrp";
 419                                                 sirf,function = "vip";
 420                                         };
 421                                 };
 422                                 sdmmc0_pins_a: sdmmc0@0 {
 423                                         sdmmc0 {
 424                                                 sirf,pins = "sdmmc0grp";
 425                                                 sirf,function = "sdmmc0";
 426                                         };
 427                                 };
 428                                 sdmmc1_pins_a: sdmmc1@0 {
 429                                         sdmmc1 {
 430                                                 sirf,pins = "sdmmc1grp";
 431                                                 sirf,function = "sdmmc1";
 432                                         };
 433                                 };
 434                                 sdmmc2_pins_a: sdmmc2@0 {
 435                                         sdmmc2 {
 436                                                 sirf,pins = "sdmmc2grp";
 437                                                 sirf,function = "sdmmc2";
 438                                         };
 439                                 };
 440                                 sdmmc3_pins_a: sdmmc3@0 {
 441                                         sdmmc3 {
 442                                                 sirf,pins = "sdmmc3grp";
 443                                                 sirf,function = "sdmmc3";
 444                                         };
 445                                 };
 446                                 sdmmc4_pins_a: sdmmc4@0 {
 447                                         sdmmc4 {
 448                                                 sirf,pins = "sdmmc4grp";
 449                                                 sirf,function = "sdmmc4";
 450                                         };
 451                                 };
 452                                 sdmmc5_pins_a: sdmmc5@0 {
 453                                         sdmmc5 {
 454                                                 sirf,pins = "sdmmc5grp";
 455                                                 sirf,function = "sdmmc5";
 456                                         };
 457                                 };
 458                                 i2s_pins_a: i2s@0 {
 459                                         i2s {
 460                                                 sirf,pins = "i2sgrp";
 461                                                 sirf,function = "i2s";
 462                                         };
 463                                 };
 464                                 ac97_pins_a: ac97@0 {
 465                                         ac97 {
 466                                                 sirf,pins = "ac97grp";
 467                                                 sirf,function = "ac97";
 468                                         };
 469                                 };
 470                                 nand_pins_a: nand@0 {
 471                                         nand {
 472                                                 sirf,pins = "nandgrp";
 473                                                 sirf,function = "nand";
 474                                         };
 475                                 };
 476                                 usp0_pins_a: usp0@0 {
 477                                         usp0 {
 478                                                 sirf,pins = "usp0grp";
 479                                                 sirf,function = "usp0";
 480                                         };
 481                                 };
 482                                 usp1_pins_a: usp1@0 {
 483                                         usp1 {
 484                                                 sirf,pins = "usp1grp";
 485                                                 sirf,function = "usp1";
 486                                         };
 487                                 };
 488                                 usp2_pins_a: usp2@0 {
 489                                         usp2 {
 490                                                 sirf,pins = "usp2grp";
 491                                                 sirf,function = "usp2";
 492                                         };
 493                                 };
 494                                 usb0_utmi_drvbus_pins_a: usb0_utmi_drvbus@0 {
 495                                         usb0_utmi_drvbus {
 496                                                 sirf,pins = "usb0_utmi_drvbusgrp";
 497                                                 sirf,function = "usb0_utmi_drvbus";
 498                                         };
 499                                 };
 500                                 usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
 501                                         usb1_utmi_drvbus {
 502                                                 sirf,pins = "usb1_utmi_drvbusgrp";
 503                                                 sirf,function = "usb1_utmi_drvbus";
 504                                         };
 505                                 };
 506                                 warm_rst_pins_a: warm_rst@0 {
 507                                         warm_rst {
 508                                                 sirf,pins = "warm_rstgrp";
 509                                                 sirf,function = "warm_rst";
 510                                         };
 511                                 };
 512                                 pulse_count_pins_a: pulse_count@0 {
 513                                         pulse_count {
 514                                                 sirf,pins = "pulse_countgrp";
 515                                                 sirf,function = "pulse_count";
 516                                         };
 517                                 };
 518                                 cko0_pins_a: cko0@0 {
 519                                         cko0 {
 520                                                 sirf,pins = "cko0grp";
 521                                                 sirf,function = "cko0";
 522                                         };
 523                                 };
 524                                 cko1_pins_a: cko1@0 {
 525                                         cko1 {
 526                                                 sirf,pins = "cko1grp";
 527                                                 sirf,function = "cko1";
 528                                         };
 529                                 };
 530                         };
 531
 532                         pwm@b0130000 {
 533                                 compatible = "sirf,prima2-pwm";
 534                                 reg = <0xb0130000 0x10000>;
 535                                 clocks = <&clks 21>;
 536                         };
 537
 538                         efusesys@b0140000 {
 539                                 compatible = "sirf,prima2-efuse";
 540                                 reg = <0xb0140000 0x10000>;
 541                                 clocks = <&clks 22>;
 542                         };
 543
 544                         pulsec@b0150000 {
 545                                 compatible = "sirf,prima2-pulsec";
 546                                 reg = <0xb0150000 0x10000>;
 547                                 interrupts = <48>;
 548                                 clocks = <&clks 23>;
 549                         };
 550
 551                         pci-iobg {
 552                                 compatible = "sirf,prima2-pciiobg", "simple-bus";
 553                                 #address-cells = <1>;
 554                                 #size-cells = <1>;
 555                                 ranges = <0x56000000 0x56000000 0x1b00000>;
 556
 557                                 sd0: sdhci@56000000 {
 558                                         cell-index = <0>;
 559                                         compatible = "sirf,prima2-sdhc";
 560                                         reg = <0x56000000 0x100000>;
 561                                         interrupts = <38>;
 562                                 };
 563
 564                                 sd1: sdhci@56100000 {
 565                                         cell-index = <1>;
 566                                         compatible = "sirf,prima2-sdhc";
 567                                         reg = <0x56100000 0x100000>;
 568                                         interrupts = <38>;
 569                                 };
 570
 571                                 sd2: sdhci@56200000 {
 572                                         cell-index = <2>;
 573                                         compatible = "sirf,prima2-sdhc";
 574                                         reg = <0x56200000 0x100000>;
 575                                         interrupts = <23>;
 576                                 };
 577
 578                                 sd3: sdhci@56300000 {
 579                                         cell-index = <3>;
 580                                         compatible = "sirf,prima2-sdhc";
 581                                         reg = <0x56300000 0x100000>;
 582                                         interrupts = <23>;
 583                                 };
 584
 585                                 sd4: sdhci@56400000 {
 586                                         cell-index = <4>;
 587                                         compatible = "sirf,prima2-sdhc";
 588                                         reg = <0x56400000 0x100000>;
 589                                         interrupts = <39>;
 590                                 };
 591
 592                                 sd5: sdhci@56500000 {
 593                                         cell-index = <5>;
 594                                         compatible = "sirf,prima2-sdhc";
 595                                         reg = <0x56500000 0x100000>;
 596                                         interrupts = <39>;
 597                                 };
 598
 599                                 pci-copy@57900000 {
 600                                         compatible = "sirf,prima2-pcicp";
 601                                         reg = <0x57900000 0x100000>;
 602                                         interrupts = <40>;
 603                                 };
 604
 605                                 rom-interface@57a00000 {
 606                                         compatible = "sirf,prima2-romif";
 607                                         reg = <0x57a00000 0x100000>;
 608                                 };
 609                         };
 610                 };
 611
 612                 rtc-iobg {
 613                         compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
 614                         #address-cells = <1>;
 615                         #size-cells = <1>;
 616                         reg = <0x80030000 0x10000>;
 617
 618                         gpsrtc@1000 {
 619                                 compatible = "sirf,prima2-gpsrtc";
 620                                 reg = <0x1000 0x1000>;
 621                                 interrupts = <55 56 57>;
 622                         };
 623
 624                         sysrtc@2000 {
 625                                 compatible = "sirf,prima2-sysrtc";
 626                                 reg = <0x2000 0x1000>;
 627                                 interrupts = <52 53 54>;
 628                         };
 629
 630                         pwrc@3000 {
 631                                 compatible = "sirf,prima2-pwrc";
 632                                 reg = <0x3000 0x1000>;
 633                                 interrupts = <32>;
 634                         };
 635                 };
 636
 637                 uus-iobg {
 638                         compatible = "simple-bus";
 639                         #address-cells = <1>;
 640                         #size-cells = <1>;
 641                         ranges = <0xb8000000 0xb8000000 0x40000>;
 642
 643                         usb0: usb@b00e0000 {
 644                                 compatible = "chipidea,ci13611a-prima2";
 645                                 reg = <0xb8000000 0x10000>;
 646                                 interrupts = <10>;
 647                                 clocks = <&clks 40>;
 648                         };
 649
 650                         usb1: usb@b00f0000 {
 651                                 compatible = "chipidea,ci13611a-prima2";
 652                                 reg = <0xb8010000 0x10000>;
 653                                 interrupts = <11>;
 654                                 clocks = <&clks 41>;
 655                         };
 656
 657                         sata@b00f0000 {
 658                                 compatible = "synopsys,dwc-ahsata";
 659                                 reg = <0xb8020000 0x10000>;
 660                                 interrupts = <37>;
 661                         };
 662
 663                         security@b00f0000 {
 664                                 compatible = "sirf,prima2-security";
 665                                 reg = <0xb8030000 0x10000>;
 666                                 interrupts = <42>;
 667                                 clocks = <&clks 7>;
 668                         };
 669                 };
 670         };
 671 };