arch/arm/boot/dts/r8a7745.dtsi

   1 /*
   2  * Device Tree Source for the r8a7745 SoC
   3  *
   4  * Copyright (C) 2016 Cogent Embedded Inc.
   5  *
   6  * This file is licensed under the terms of the GNU General Public License
   7  * version 2. This program is licensed "as is" without any warranty of any
   8  * kind, whether express or implied.
   9  */
  10
  11 #include <dt-bindings/interrupt-controller/irq.h>
  12 #include <dt-bindings/interrupt-controller/arm-gic.h>
  13 #include <dt-bindings/clock/r8a7745-cpg-mssr.h>
  14 #include <dt-bindings/power/r8a7745-sysc.h>
  15
  16 / {
  17         compatible = "renesas,r8a7745";
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         cpus {
  22                 #address-cells = <1>;
  23                 #size-cells = <0>;
  24
  25                 cpu0: cpu@0 {
  26                         device_type = "cpu";
  27                         compatible = "arm,cortex-a7";
  28                         reg = <0>;
  29                         clock-frequency = <1000000000>;
  30                         clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
  31                         power-domains = <&sysc R8A7745_PD_CA7_CPU0>;
  32                         next-level-cache = <&L2_CA7>;
  33                 };
  34
  35                 L2_CA7: cache-controller@0 {
  36                         compatible = "cache";
  37                         reg = <0>;
  38                         cache-unified;
  39                         cache-level = <2>;
  40                         power-domains = <&sysc R8A7745_PD_CA7_SCU>;
  41                 };
  42         };
  43
  44         soc {
  45                 compatible = "simple-bus";
  46                 interrupt-parent = <&gic>;
  47
  48                 #address-cells = <2>;
  49                 #size-cells = <2>;
  50                 ranges;
  51
  52                 gic: interrupt-controller@f1001000 {
  53                         compatible = "arm,gic-400";
  54                         #interrupt-cells = <3>;
  55                         #address-cells = <0>;
  56                         interrupt-controller;
  57                         reg = <0 0xf1001000 0 0x1000>,
  58                               <0 0xf1002000 0 0x1000>,
  59                               <0 0xf1004000 0 0x2000>,
  60                               <0 0xf1006000 0 0x2000>;
  61                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
  62                                                  IRQ_TYPE_LEVEL_HIGH)>;
  63                 };
  64
  65                 timer {
  66                         compatible = "arm,armv7-timer";
  67                         interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
  68                                                   IRQ_TYPE_LEVEL_LOW)>,
  69                                      <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
  70                                                   IRQ_TYPE_LEVEL_LOW)>,
  71                                      <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
  72                                                   IRQ_TYPE_LEVEL_LOW)>,
  73                                      <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
  74                                                   IRQ_TYPE_LEVEL_LOW)>;
  75                 };
  76
  77                 cpg: clock-controller@e6150000 {
  78                         compatible = "renesas,r8a7745-cpg-mssr";
  79                         reg = <0 0xe6150000 0 0x1000>;
  80                         clocks = <&extal_clk>, <&usb_extal_clk>;
  81                         clock-names = "extal", "usb_extal";
  82                         #clock-cells = <2>;
  83                         #power-domain-cells = <0>;
  84                 };
  85
  86                 sysc: system-controller@e6180000 {
  87                         compatible = "renesas,r8a7745-sysc";
  88                         reg = <0 0xe6180000 0 0x200>;
  89                         #power-domain-cells = <1>;
  90                 };
  91
  92                 rst: reset-controller@e6160000 {
  93                         compatible = "renesas,r8a7745-rst";
  94                         reg = <0 0xe6160000 0 0x100>;
  95                 };
  96
  97                 dmac0: dma-controller@e6700000 {
  98                         compatible = "renesas,dmac-r8a7745",
  99                                      "renesas,rcar-dmac";
 100                         reg = <0 0xe6700000 0 0x20000>;
 101                         interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
 102                                       GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
 103                                       GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
 104                                       GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
 105                                       GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
 106                                       GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
 107                                       GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
 108                                       GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
 109                                       GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
 110                                       GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
 111                                       GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
 112                                       GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
 113                                       GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
 114                                       GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
 115                                       GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
 116                                       GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
 117                         interrupt-names = "error",
 118                                         "ch0", "ch1", "ch2", "ch3",
 119                                         "ch4", "ch5", "ch6", "ch7",
 120                                         "ch8", "ch9", "ch10", "ch11",
 121                                         "ch12", "ch13", "ch14";
 122                         clocks = <&cpg CPG_MOD 219>;
 123                         clock-names = "fck";
 124                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 125                         #dma-cells = <1>;
 126                         dma-channels = <15>;
 127                 };
 128
 129                 dmac1: dma-controller@e6720000 {
 130                         compatible = "renesas,dmac-r8a7745",
 131                                      "renesas,rcar-dmac";
 132                         reg = <0 0xe6720000 0 0x20000>;
 133                         interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
 134                                       GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
 135                                       GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
 136                                       GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
 137                                       GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
 138                                       GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
 139                                       GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
 140                                       GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
 141                                       GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
 142                                       GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
 143                                       GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
 144                                       GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
 145                                       GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
 146                                       GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
 147                                       GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
 148                                       GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
 149                         interrupt-names = "error",
 150                                         "ch0", "ch1", "ch2", "ch3",
 151                                         "ch4", "ch5", "ch6", "ch7",
 152                                         "ch8", "ch9", "ch10", "ch11",
 153                                         "ch12", "ch13", "ch14";
 154                         clocks = <&cpg CPG_MOD 218>;
 155                         clock-names = "fck";
 156                         power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
 157                         #dma-cells = <1>;
 158                         dma-channels = <15>;
 159                 };
 160         };
 161
 162         /* External root clock */
 163         extal_clk: extal {
 164                 compatible = "fixed-clock";
 165                 #clock-cells = <0>;
 166                 /* This value must be overridden by the board. */
 167                 clock-frequency = <0>;
 168         };
 169
 170         /* External USB clock - can be overridden by the board */
 171         usb_extal_clk: usb_extal {
 172                 compatible = "fixed-clock";
 173                 #clock-cells = <0>;
 174                 clock-frequency = <48000000>;
 175         };
 176
 177         /* External SCIF clock */
 178         scif_clk: scif {
 179                 compatible = "fixed-clock";
 180                 #clock-cells = <0>;
 181                 /* This value must be overridden by the board. */
 182                 clock-frequency = <0>;
 183         };
 184 };