arch/arm/boot/dts/stm32f429.dtsi

   1 /*
   2  * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  *     You should have received a copy of the GNU General Public
  20  *     License along with this file; if not, write to the Free
  21  *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
  22  *     MA 02110-1301 USA
  23  *
  24  * Or, alternatively,
  25  *
  26  *  b) Permission is hereby granted, free of charge, to any person
  27  *     obtaining a copy of this software and associated documentation
  28  *     files (the "Software"), to deal in the Software without
  29  *     restriction, including without limitation the rights to use,
  30  *     copy, modify, merge, publish, distribute, sublicense, and/or
  31  *     sell copies of the Software, and to permit persons to whom the
  32  *     Software is furnished to do so, subject to the following
  33  *     conditions:
  34  *
  35  *     The above copyright notice and this permission notice shall be
  36  *     included in all copies or substantial portions of the Software.
  37  *
  38  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  39  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  40  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  41  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  42  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  43  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  44  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  45  *     OTHER DEALINGS IN THE SOFTWARE.
  46  */
  47
  48 #include "skeleton.dtsi"
  49 #include "armv7-m.dtsi"
  50 #include <dt-bindings/pinctrl/stm32f429-pinfunc.h>
  51 #include <dt-bindings/clock/stm32fx-clock.h>
  52 #include <dt-bindings/mfd/stm32f4-rcc.h>
  53
  54 / {
  55         clocks {
  56                 clk_hse: clk-hse {
  57                         #clock-cells = <0>;
  58                         compatible = "fixed-clock";
  59                         clock-frequency = <0>;
  60                 };
  61
  62                 clk-lse {
  63                         #clock-cells = <0>;
  64                         compatible = "fixed-clock";
  65                         clock-frequency = <32768>;
  66                 };
  67
  68                 clk-lsi {
  69                         #clock-cells = <0>;
  70                         compatible = "fixed-clock";
  71                         clock-frequency = <32000>;
  72                 };
  73
  74                 clk_i2s_ckin: i2s-ckin {
  75                         #clock-cells = <0>;
  76                         compatible = "fixed-clock";
  77                         clock-frequency = <0>;
  78                 };
  79         };
  80
  81         soc {
  82                 timer2: timer@40000000 {
  83                         compatible = "st,stm32-timer";
  84                         reg = <0x40000000 0x400>;
  85                         interrupts = <28>;
  86                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
  87                         status = "disabled";
  88                 };
  89
  90                 timers2: timers@40000000 {
  91                         #address-cells = <1>;
  92                         #size-cells = <0>;
  93                         compatible = "st,stm32-timers";
  94                         reg = <0x40000000 0x400>;
  95                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
  96                         clock-names = "int";
  97                         status = "disabled";
  98
  99                         pwm {
 100                                 compatible = "st,stm32-pwm";
 101                                 status = "disabled";
 102                         };
 103
 104                         timer@1 {
 105                                 compatible = "st,stm32-timer-trigger";
 106                                 reg = <1>;
 107                                 status = "disabled";
 108                         };
 109                 };
 110
 111                 timer3: timer@40000400 {
 112                         compatible = "st,stm32-timer";
 113                         reg = <0x40000400 0x400>;
 114                         interrupts = <29>;
 115                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
 116                         status = "disabled";
 117                 };
 118
 119                 timers3: timers@40000400 {
 120                         #address-cells = <1>;
 121                         #size-cells = <0>;
 122                         compatible = "st,stm32-timers";
 123                         reg = <0x40000400 0x400>;
 124                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
 125                         clock-names = "int";
 126                         status = "disabled";
 127
 128                         pwm {
 129                                 compatible = "st,stm32-pwm";
 130                                 status = "disabled";
 131                         };
 132
 133                         timer@2 {
 134                                 compatible = "st,stm32-timer-trigger";
 135                                 reg = <2>;
 136                                 status = "disabled";
 137                         };
 138                 };
 139
 140                 timer4: timer@40000800 {
 141                         compatible = "st,stm32-timer";
 142                         reg = <0x40000800 0x400>;
 143                         interrupts = <30>;
 144                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
 145                         status = "disabled";
 146                 };
 147
 148                 timers4: timers@40000800 {
 149                         #address-cells = <1>;
 150                         #size-cells = <0>;
 151                         compatible = "st,stm32-timers";
 152                         reg = <0x40000800 0x400>;
 153                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
 154                         clock-names = "int";
 155                         status = "disabled";
 156
 157                         pwm {
 158                                 compatible = "st,stm32-pwm";
 159                                 status = "disabled";
 160                         };
 161
 162                         timer@3 {
 163                                 compatible = "st,stm32-timer-trigger";
 164                                 reg = <3>;
 165                                 status = "disabled";
 166                         };
 167                 };
 168
 169                 timer5: timer@40000c00 {
 170                         compatible = "st,stm32-timer";
 171                         reg = <0x40000c00 0x400>;
 172                         interrupts = <50>;
 173                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
 174                 };
 175
 176                 timers5: timers@40000c00 {
 177                         #address-cells = <1>;
 178                         #size-cells = <0>;
 179                         compatible = "st,stm32-timers";
 180                         reg = <0x40000C00 0x400>;
 181                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
 182                         clock-names = "int";
 183                         status = "disabled";
 184
 185                         pwm {
 186                                 compatible = "st,stm32-pwm";
 187                                 status = "disabled";
 188                         };
 189
 190                         timer@4 {
 191                                 compatible = "st,stm32-timer-trigger";
 192                                 reg = <4>;
 193                                 status = "disabled";
 194                         };
 195                 };
 196
 197                 timer6: timer@40001000 {
 198                         compatible = "st,stm32-timer";
 199                         reg = <0x40001000 0x400>;
 200                         interrupts = <54>;
 201                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
 202                         status = "disabled";
 203                 };
 204
 205                 timers6: timers@40001000 {
 206                         #address-cells = <1>;
 207                         #size-cells = <0>;
 208                         compatible = "st,stm32-timers";
 209                         reg = <0x40001000 0x400>;
 210                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
 211                         clock-names = "int";
 212                         status = "disabled";
 213
 214                         timer@5 {
 215                                 compatible = "st,stm32-timer-trigger";
 216                                 reg = <5>;
 217                                 status = "disabled";
 218                         };
 219                 };
 220
 221                 timer7: timer@40001400 {
 222                         compatible = "st,stm32-timer";
 223                         reg = <0x40001400 0x400>;
 224                         interrupts = <55>;
 225                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
 226                         status = "disabled";
 227                 };
 228
 229                 timers7: timers@40001400 {
 230                         #address-cells = <1>;
 231                         #size-cells = <0>;
 232                         compatible = "st,stm32-timers";
 233                         reg = <0x40001400 0x400>;
 234                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
 235                         clock-names = "int";
 236                         status = "disabled";
 237
 238                         timer@6 {
 239                                 compatible = "st,stm32-timer-trigger";
 240                                 reg = <6>;
 241                                 status = "disabled";
 242                         };
 243                 };
 244
 245                 timers12: timers@40001800 {
 246                         #address-cells = <1>;
 247                         #size-cells = <0>;
 248                         compatible = "st,stm32-timers";
 249                         reg = <0x40001800 0x400>;
 250                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
 251                         clock-names = "int";
 252                         status = "disabled";
 253
 254                         pwm {
 255                                 compatible = "st,stm32-pwm";
 256                                 status = "disabled";
 257                         };
 258
 259                         timer@11 {
 260                                 compatible = "st,stm32-timer-trigger";
 261                                 reg = <11>;
 262                                 status = "disabled";
 263                         };
 264                 };
 265
 266                 timers13: timers@40001c00 {
 267                         #address-cells = <1>;
 268                         #size-cells = <0>;
 269                         compatible = "st,stm32-timers";
 270                         reg = <0x40001C00 0x400>;
 271                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
 272                         clock-names = "int";
 273                         status = "disabled";
 274
 275                         pwm {
 276                                 compatible = "st,stm32-pwm";
 277                                 status = "disabled";
 278                         };
 279                 };
 280
 281                 timers14: timers@40002000 {
 282                         #address-cells = <1>;
 283                         #size-cells = <0>;
 284                         compatible = "st,stm32-timers";
 285                         reg = <0x40002000 0x400>;
 286                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
 287                         clock-names = "int";
 288                         status = "disabled";
 289
 290                         pwm {
 291                                 compatible = "st,stm32-pwm";
 292                                 status = "disabled";
 293                         };
 294                 };
 295
 296                 rtc: rtc@40002800 {
 297                         compatible = "st,stm32-rtc";
 298                         reg = <0x40002800 0x400>;
 299                         clocks = <&rcc 1 CLK_RTC>;
 300                         clock-names = "ck_rtc";
 301                         assigned-clocks = <&rcc 1 CLK_RTC>;
 302                         assigned-clock-parents = <&rcc 1 CLK_LSE>;
 303                         interrupt-parent = <&exti>;
 304                         interrupts = <17 1>;
 305                         interrupt-names = "alarm";
 306                         st,syscfg = <&pwrcfg>;
 307                         status = "disabled";
 308                 };
 309
 310                 usart2: serial@40004400 {
 311                         compatible = "st,stm32-usart", "st,stm32-uart";
 312                         reg = <0x40004400 0x400>;
 313                         interrupts = <38>;
 314                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
 315                         status = "disabled";
 316                 };
 317
 318                 usart3: serial@40004800 {
 319                         compatible = "st,stm32-usart", "st,stm32-uart";
 320                         reg = <0x40004800 0x400>;
 321                         interrupts = <39>;
 322                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
 323                         status = "disabled";
 324                         dmas = <&dma1 1 4 0x400 0x0>,
 325                                <&dma1 3 4 0x400 0x0>;
 326                         dma-names = "rx", "tx";
 327                 };
 328
 329                 usart4: serial@40004c00 {
 330                         compatible = "st,stm32-uart";
 331                         reg = <0x40004c00 0x400>;
 332                         interrupts = <52>;
 333                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
 334                         status = "disabled";
 335                 };
 336
 337                 usart5: serial@40005000 {
 338                         compatible = "st,stm32-uart";
 339                         reg = <0x40005000 0x400>;
 340                         interrupts = <53>;
 341                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
 342                         status = "disabled";
 343                 };
 344
 345                 i2c1: i2c@40005400 {
 346                         compatible = "st,stm32f4-i2c";
 347                         reg = <0x40005400 0x400>;
 348                         interrupts = <31>,
 349                                      <32>;
 350                         resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
 351                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
 352                         #address-cells = <1>;
 353                         #size-cells = <0>;
 354                         status = "disabled";
 355                 };
 356
 357                 usart7: serial@40007800 {
 358                         compatible = "st,stm32-usart", "st,stm32-uart";
 359                         reg = <0x40007800 0x400>;
 360                         interrupts = <82>;
 361                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
 362                         status = "disabled";
 363                 };
 364
 365                 usart8: serial@40007c00 {
 366                         compatible = "st,stm32-usart", "st,stm32-uart";
 367                         reg = <0x40007c00 0x400>;
 368                         interrupts = <83>;
 369                         clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
 370                         status = "disabled";
 371                 };
 372
 373                 timers1: timers@40010000 {
 374                         #address-cells = <1>;
 375                         #size-cells = <0>;
 376                         compatible = "st,stm32-timers";
 377                         reg = <0x40010000 0x400>;
 378                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
 379                         clock-names = "int";
 380                         status = "disabled";
 381
 382                         pwm {
 383                                 compatible = "st,stm32-pwm";
 384                                 status = "disabled";
 385                         };
 386
 387                         timer@0 {
 388                                 compatible = "st,stm32-timer-trigger";
 389                                 reg = <0>;
 390                                 status = "disabled";
 391                         };
 392                 };
 393
 394                 timers8: timers@40010400 {
 395                         #address-cells = <1>;
 396                         #size-cells = <0>;
 397                         compatible = "st,stm32-timers";
 398                         reg = <0x40010400 0x400>;
 399                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
 400                         clock-names = "int";
 401                         status = "disabled";
 402
 403                         pwm {
 404                                 compatible = "st,stm32-pwm";
 405                                 status = "disabled";
 406                         };
 407
 408                         timer@7 {
 409                                 compatible = "st,stm32-timer-trigger";
 410                                 reg = <7>;
 411                                 status = "disabled";
 412                         };
 413                 };
 414
 415                 usart1: serial@40011000 {
 416                         compatible = "st,stm32-usart", "st,stm32-uart";
 417                         reg = <0x40011000 0x400>;
 418                         interrupts = <37>;
 419                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
 420                         status = "disabled";
 421                         dmas = <&dma2 2 4 0x400 0x0>,
 422                                <&dma2 7 4 0x400 0x0>;
 423                         dma-names = "rx", "tx";
 424                 };
 425
 426                 usart6: serial@40011400 {
 427                         compatible = "st,stm32-usart", "st,stm32-uart";
 428                         reg = <0x40011400 0x400>;
 429                         interrupts = <71>;
 430                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
 431                         status = "disabled";
 432                 };
 433
 434                 adc: adc@40012000 {
 435                         compatible = "st,stm32f4-adc-core";
 436                         reg = <0x40012000 0x400>;
 437                         interrupts = <18>;
 438                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
 439                         clock-names = "adc";
 440                         interrupt-controller;
 441                         #interrupt-cells = <1>;
 442                         #address-cells = <1>;
 443                         #size-cells = <0>;
 444                         status = "disabled";
 445
 446                         adc1: adc@0 {
 447                                 compatible = "st,stm32f4-adc";
 448                                 #io-channel-cells = <1>;
 449                                 reg = <0x0>;
 450                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
 451                                 interrupt-parent = <&adc>;
 452                                 interrupts = <0>;
 453                                 dmas = <&dma2 0 0 0x400 0x0>;
 454                                 dma-names = "rx";
 455                                 status = "disabled";
 456                         };
 457
 458                         adc2: adc@100 {
 459                                 compatible = "st,stm32f4-adc";
 460                                 #io-channel-cells = <1>;
 461                                 reg = <0x100>;
 462                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
 463                                 interrupt-parent = <&adc>;
 464                                 interrupts = <1>;
 465                                 dmas = <&dma2 3 1 0x400 0x0>;
 466                                 dma-names = "rx";
 467                                 status = "disabled";
 468                         };
 469
 470                         adc3: adc@200 {
 471                                 compatible = "st,stm32f4-adc";
 472                                 #io-channel-cells = <1>;
 473                                 reg = <0x200>;
 474                                 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
 475                                 interrupt-parent = <&adc>;
 476                                 interrupts = <2>;
 477                                 dmas = <&dma2 1 2 0x400 0x0>;
 478                                 dma-names = "rx";
 479                                 status = "disabled";
 480                         };
 481                 };
 482
 483                 syscfg: system-config@40013800 {
 484                         compatible = "syscon";
 485                         reg = <0x40013800 0x400>;
 486                 };
 487
 488                 exti: interrupt-controller@40013c00 {
 489                         compatible = "st,stm32-exti";
 490                         interrupt-controller;
 491                         #interrupt-cells = <2>;
 492                         reg = <0x40013C00 0x400>;
 493                         interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
 494                 };
 495
 496                 timers9: timers@40014000 {
 497                         #address-cells = <1>;
 498                         #size-cells = <0>;
 499                         compatible = "st,stm32-timers";
 500                         reg = <0x40014000 0x400>;
 501                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
 502                         clock-names = "int";
 503                         status = "disabled";
 504
 505                         pwm {
 506                                 compatible = "st,stm32-pwm";
 507                                 status = "disabled";
 508                         };
 509
 510                         timer@8 {
 511                                 compatible = "st,stm32-timer-trigger";
 512                                 reg = <8>;
 513                                 status = "disabled";
 514                         };
 515                 };
 516
 517                 timers10: timers@40014400 {
 518                         #address-cells = <1>;
 519                         #size-cells = <0>;
 520                         compatible = "st,stm32-timers";
 521                         reg = <0x40014400 0x400>;
 522                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
 523                         clock-names = "int";
 524                         status = "disabled";
 525
 526                         pwm {
 527                                 compatible = "st,stm32-pwm";
 528                                 status = "disabled";
 529                         };
 530                 };
 531
 532                 timers11: timers@40014800 {
 533                         #address-cells = <1>;
 534                         #size-cells = <0>;
 535                         compatible = "st,stm32-timers";
 536                         reg = <0x40014800 0x400>;
 537                         clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
 538                         clock-names = "int";
 539                         status = "disabled";
 540
 541                         pwm {
 542                                 compatible = "st,stm32-pwm";
 543                                 status = "disabled";
 544                         };
 545                 };
 546
 547                 pwrcfg: power-config@40007000 {
 548                         compatible = "syscon";
 549                         reg = <0x40007000 0x400>;
 550                 };
 551
 552                 pin-controller {
 553                         #address-cells = <1>;
 554                         #size-cells = <1>;
 555                         compatible = "st,stm32f429-pinctrl";
 556                         ranges = <0 0x40020000 0x3000>;
 557                         interrupt-parent = <&exti>;
 558                         st,syscfg = <&syscfg 0x8>;
 559                         pins-are-numbered;
 560
 561                         gpioa: gpio@40020000 {
 562                                 gpio-controller;
 563                                 #gpio-cells = <2>;
 564                                 reg = <0x0 0x400>;
 565                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
 566                                 st,bank-name = "GPIOA";
 567                         };
 568
 569                         gpiob: gpio@40020400 {
 570                                 gpio-controller;
 571                                 #gpio-cells = <2>;
 572                                 reg = <0x400 0x400>;
 573                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
 574                                 st,bank-name = "GPIOB";
 575                         };
 576
 577                         gpioc: gpio@40020800 {
 578                                 gpio-controller;
 579                                 #gpio-cells = <2>;
 580                                 reg = <0x800 0x400>;
 581                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
 582                                 st,bank-name = "GPIOC";
 583                         };
 584
 585                         gpiod: gpio@40020c00 {
 586                                 gpio-controller;
 587                                 #gpio-cells = <2>;
 588                                 reg = <0xc00 0x400>;
 589                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
 590                                 st,bank-name = "GPIOD";
 591                         };
 592
 593                         gpioe: gpio@40021000 {
 594                                 gpio-controller;
 595                                 #gpio-cells = <2>;
 596                                 reg = <0x1000 0x400>;
 597                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
 598                                 st,bank-name = "GPIOE";
 599                         };
 600
 601                         gpiof: gpio@40021400 {
 602                                 gpio-controller;
 603                                 #gpio-cells = <2>;
 604                                 reg = <0x1400 0x400>;
 605                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
 606                                 st,bank-name = "GPIOF";
 607                         };
 608
 609                         gpiog: gpio@40021800 {
 610                                 gpio-controller;
 611                                 #gpio-cells = <2>;
 612                                 reg = <0x1800 0x400>;
 613                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
 614                                 st,bank-name = "GPIOG";
 615                         };
 616
 617                         gpioh: gpio@40021c00 {
 618                                 gpio-controller;
 619                                 #gpio-cells = <2>;
 620                                 reg = <0x1c00 0x400>;
 621                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
 622                                 st,bank-name = "GPIOH";
 623                         };
 624
 625                         gpioi: gpio@40022000 {
 626                                 gpio-controller;
 627                                 #gpio-cells = <2>;
 628                                 reg = <0x2000 0x400>;
 629                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
 630                                 st,bank-name = "GPIOI";
 631                         };
 632
 633                         gpioj: gpio@40022400 {
 634                                 gpio-controller;
 635                                 #gpio-cells = <2>;
 636                                 reg = <0x2400 0x400>;
 637                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOJ)>;
 638                                 st,bank-name = "GPIOJ";
 639                         };
 640
 641                         gpiok: gpio@40022800 {
 642                                 gpio-controller;
 643                                 #gpio-cells = <2>;
 644                                 reg = <0x2800 0x400>;
 645                                 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOK)>;
 646                                 st,bank-name = "GPIOK";
 647                         };
 648
 649                         usart1_pins_a: usart1@0 {
 650                                 pins1 {
 651                                         pinmux = <STM32F429_PA9_FUNC_USART1_TX>;
 652                                         bias-disable;
 653                                         drive-push-pull;
 654                                         slew-rate = <0>;
 655                                 };
 656                                 pins2 {
 657                                         pinmux = <STM32F429_PA10_FUNC_USART1_RX>;
 658                                         bias-disable;
 659                                 };
 660                         };
 661
 662                         usart3_pins_a: usart3@0 {
 663                                 pins1 {
 664                                         pinmux = <STM32F429_PB10_FUNC_USART3_TX>;
 665                                         bias-disable;
 666                                         drive-push-pull;
 667                                         slew-rate = <0>;
 668                                 };
 669                                 pins2 {
 670                                         pinmux = <STM32F429_PB11_FUNC_USART3_RX>;
 671                                         bias-disable;
 672                                 };
 673                         };
 674
 675                         usbotg_fs_pins_a: usbotg_fs@0 {
 676                                 pins {
 677                                         pinmux = <STM32F429_PA10_FUNC_OTG_FS_ID>,
 678                                                  <STM32F429_PA11_FUNC_OTG_FS_DM>,
 679                                                  <STM32F429_PA12_FUNC_OTG_FS_DP>;
 680                                         bias-disable;
 681                                         drive-push-pull;
 682                                         slew-rate = <2>;
 683                                 };
 684                         };
 685
 686                         usbotg_fs_pins_b: usbotg_fs@1 {
 687                                 pins {
 688                                         pinmux = <STM32F429_PB12_FUNC_OTG_HS_ID>,
 689                                                  <STM32F429_PB14_FUNC_OTG_HS_DM>,
 690                                                  <STM32F429_PB15_FUNC_OTG_HS_DP>;
 691                                         bias-disable;
 692                                         drive-push-pull;
 693                                         slew-rate = <2>;
 694                                 };
 695                         };
 696
 697                         usbotg_hs_pins_a: usbotg_hs@0 {
 698                                 pins {
 699                                         pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>,
 700                                                  <STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>,
 701                                                  <STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>,
 702                                                  <STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>,
 703                                                  <STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>,
 704                                                  <STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>,
 705                                                  <STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>,
 706                                                  <STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>,
 707                                                  <STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>,
 708                                                  <STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>,
 709                                                  <STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>,
 710                                                  <STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>;
 711                                         bias-disable;
 712                                         drive-push-pull;
 713                                         slew-rate = <2>;
 714                                 };
 715                         };
 716
 717                         ethernet_mii: mii@0 {
 718                                 pins {
 719                                         pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>,
 720                                                  <STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>,
 721                                                  <STM32F429_PC2_FUNC_ETH_MII_TXD2>,
 722                                                  <STM32F429_PB8_FUNC_ETH_MII_TXD3>,
 723                                                  <STM32F429_PC3_FUNC_ETH_MII_TX_CLK>,
 724                                                  <STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>,
 725                                                  <STM32F429_PA2_FUNC_ETH_MDIO>,
 726                                                  <STM32F429_PC1_FUNC_ETH_MDC>,
 727                                                  <STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>,
 728                                                  <STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>,
 729                                                  <STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>,
 730                                                  <STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>,
 731                                                  <STM32F429_PH6_FUNC_ETH_MII_RXD2>,
 732                                                  <STM32F429_PH7_FUNC_ETH_MII_RXD3>;
 733                                         slew-rate = <2>;
 734                                 };
 735                         };
 736
 737                         adc3_in8_pin: adc@200 {
 738                                 pins {
 739                                         pinmux = <STM32F429_PF10_FUNC_ANALOG>;
 740                                 };
 741                         };
 742
 743                         pwm1_pins: pwm@1 {
 744                                 pins {
 745                                         pinmux = <STM32F429_PA8_FUNC_TIM1_CH1>,
 746                                                  <STM32F429_PB13_FUNC_TIM1_CH1N>,
 747                                                  <STM32F429_PB12_FUNC_TIM1_BKIN>;
 748                                 };
 749                         };
 750
 751                         pwm3_pins: pwm@3 {
 752                                 pins {
 753                                         pinmux = <STM32F429_PB4_FUNC_TIM3_CH1>,
 754                                                  <STM32F429_PB5_FUNC_TIM3_CH2>;
 755                                 };
 756                         };
 757
 758                         i2c1_pins: i2c1@0 {
 759                                 pins {
 760                                         pinmux = <STM32F429_PB9_FUNC_I2C1_SDA>,
 761                                                  <STM32F429_PB6_FUNC_I2C1_SCL>;
 762                                         bias-disable;
 763                                         drive-open-drain;
 764                                         slew-rate = <3>;
 765                                 };
 766                         };
 767                 };
 768
 769                 rcc: rcc@40023810 {
 770                         #reset-cells = <1>;
 771                         #clock-cells = <2>;
 772                         compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
 773                         reg = <0x40023800 0x400>;
 774                         clocks = <&clk_hse>, <&clk_i2s_ckin>;
 775                         st,syscfg = <&pwrcfg>;
 776                         assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
 777                         assigned-clock-rates = <1000000>;
 778                 };
 779
 780                 dma1: dma-controller@40026000 {
 781                         compatible = "st,stm32-dma";
 782                         reg = <0x40026000 0x400>;
 783                         interrupts = <11>,
 784                                      <12>,
 785                                      <13>,
 786                                      <14>,
 787                                      <15>,
 788                                      <16>,
 789                                      <17>,
 790                                      <47>;
 791                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
 792                         #dma-cells = <4>;
 793                 };
 794
 795                 dma2: dma-controller@40026400 {
 796                         compatible = "st,stm32-dma";
 797                         reg = <0x40026400 0x400>;
 798                         interrupts = <56>,
 799                                      <57>,
 800                                      <58>,
 801                                      <59>,
 802                                      <60>,
 803                                      <68>,
 804                                      <69>,
 805                                      <70>;
 806                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
 807                         #dma-cells = <4>;
 808                         st,mem2mem;
 809                 };
 810
 811                 mac: ethernet@40028000 {
 812                         compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
 813                         reg = <0x40028000 0x8000>;
 814                         reg-names = "stmmaceth";
 815                         interrupts = <61>;
 816                         interrupt-names = "macirq";
 817                         clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
 818                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
 819                                         <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
 820                                         <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
 821                         st,syscon = <&syscfg 0x4>;
 822                         snps,pbl = <8>;
 823                         snps,mixed-burst;
 824                         status = "disabled";
 825                 };
 826
 827                 usbotg_hs: usb@40040000 {
 828                         compatible = "snps,dwc2";
 829                         reg = <0x40040000 0x40000>;
 830                         interrupts = <77>;
 831                         clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
 832                         clock-names = "otg";
 833                         status = "disabled";
 834                 };
 835
 836                 usbotg_fs: usb@50000000 {
 837                         compatible = "st,stm32f4x9-fsotg";
 838                         reg = <0x50000000 0x40000>;
 839                         interrupts = <67>;
 840                         clocks = <&rcc 0 39>;
 841                         clock-names = "otg";
 842                         status = "disabled";
 843                 };
 844
 845                 rng: rng@50060800 {
 846                         compatible = "st,stm32-rng";
 847                         reg = <0x50060800 0x400>;
 848                         interrupts = <80>;
 849                         clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
 850
 851                 };
 852         };
 853 };
 854
 855 &systick {
 856         clocks = <&rcc 1 SYSTICK>;
 857         status = "okay";
 858 };