arch/arm/boot/dts/sun4i-a10.dtsi

   1 /*
   2  * Copyright 2012 Stefan Roese
   3  * Stefan Roese <sr@denx.de>
   4  *
   5  * This file is dual-licensed: you can use it either under the terms
   6  * of the GPL or the X11 license, at your option. Note that this dual
   7  * licensing only applies to this file, and not this project as a
   8  * whole.
   9  *
  10  *  a) This library is free software; you can redistribute it and/or
  11  *     modify it under the terms of the GNU General Public License as
  12  *     published by the Free Software Foundation; either version 2 of the
  13  *     License, or (at your option) any later version.
  14  *
  15  *     This library is distributed in the hope that it will be useful,
  16  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *     GNU General Public License for more details.
  19  *
  20  * Or, alternatively,
  21  *
  22  *  b) Permission is hereby granted, free of charge, to any person
  23  *     obtaining a copy of this software and associated documentation
  24  *     files (the "Software"), to deal in the Software without
  25  *     restriction, including without limitation the rights to use,
  26  *     copy, modify, merge, publish, distribute, sublicense, and/or
  27  *     sell copies of the Software, and to permit persons to whom the
  28  *     Software is furnished to do so, subject to the following
  29  *     conditions:
  30  *
  31  *     The above copyright notice and this permission notice shall be
  32  *     included in all copies or substantial portions of the Software.
  33  *
  34  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  35  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  36  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  37  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  38  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  39  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  40  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  41  *     OTHER DEALINGS IN THE SOFTWARE.
  42  */
  43
  44 #include "skeleton.dtsi"
  45
  46 #include <dt-bindings/thermal/thermal.h>
  47
  48 #include <dt-bindings/clock/sun4i-a10-pll2.h>
  49 #include <dt-bindings/dma/sun4i-a10.h>
  50 #include <dt-bindings/pinctrl/sun4i-a10.h>
  51
  52 / {
  53         interrupt-parent = <&intc>;
  54
  55         aliases {
  56                 ethernet0 = &emac;
  57         };
  58
  59         chosen {
  60                 #address-cells = <1>;
  61                 #size-cells = <1>;
  62                 ranges;
  63
  64                 framebuffer@0 {
  65                         compatible = "allwinner,simple-framebuffer",
  66                                      "simple-framebuffer";
  67                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  68                         clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
  69                                  <&ahb_gates 43>, <&ahb_gates 44>,
  70                                  <&dram_gates 26>;
  71                         status = "disabled";
  72                 };
  73
  74                 framebuffer@1 {
  75                         compatible = "allwinner,simple-framebuffer",
  76                                      "simple-framebuffer";
  77                         allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi";
  78                         clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
  79                                  <&ahb_gates 43>, <&ahb_gates 44>,
  80                                  <&ahb_gates 46>,
  81                                  <&dram_gates 25>, <&dram_gates 26>;
  82                         status = "disabled";
  83                 };
  84
  85                 framebuffer@2 {
  86                         compatible = "allwinner,simple-framebuffer",
  87                                      "simple-framebuffer";
  88                         allwinner,pipeline = "de_fe0-de_be0-lcd0";
  89                         clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
  90                                  <&ahb_gates 44>, <&ahb_gates 46>,
  91                                  <&dram_gates 25>, <&dram_gates 26>;
  92                         status = "disabled";
  93                 };
  94
  95                 framebuffer@3 {
  96                         compatible = "allwinner,simple-framebuffer",
  97                                      "simple-framebuffer";
  98                         allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0";
  99                         clocks = <&pll3>, <&pll5 1>, <&ahb_gates 34>,
 100                                  <&ahb_gates 36>, <&ahb_gates 44>,
 101                                  <&ahb_gates 46>,
 102                                  <&dram_gates 5>, <&dram_gates 25>, <&dram_gates 26>;
 103                         status = "disabled";
 104                 };
 105         };
 106
 107         cpus {
 108                 #address-cells = <1>;
 109                 #size-cells = <0>;
 110                 cpu0: cpu@0 {
 111                         device_type = "cpu";
 112                         compatible = "arm,cortex-a8";
 113                         reg = <0x0>;
 114                         clocks = <&cpu>;
 115                         clock-latency = <244144>; /* 8 32k periods */
 116                         operating-points = <
 117                                 /* kHz    uV */
 118                                 1008000 1400000
 119                                 912000  1350000
 120                                 864000  1300000
 121                                 624000  1250000
 122                                 >;
 123                         #cooling-cells = <2>;
 124                         cooling-min-level = <0>;
 125                         cooling-max-level = <3>;
 126                 };
 127         };
 128
 129         thermal-zones {
 130                 cpu_thermal {
 131                         /* milliseconds */
 132                         polling-delay-passive = <250>;
 133                         polling-delay = <1000>;
 134                         thermal-sensors = <&rtp>;
 135
 136                         cooling-maps {
 137                                 map0 {
 138                                         trip = <&cpu_alert0>;
 139                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 140                                 };
 141                         };
 142
 143                         trips {
 144                                 cpu_alert0: cpu_alert0 {
 145                                         /* milliCelsius */
 146                                         temperature = <850000>;
 147                                         hysteresis = <2000>;
 148                                         type = "passive";
 149                                 };
 150
 151                                 cpu_crit: cpu_crit {
 152                                         /* milliCelsius */
 153                                         temperature = <100000>;
 154                                         hysteresis = <2000>;
 155                                         type = "critical";
 156                                 };
 157                         };
 158                 };
 159         };
 160
 161         memory {
 162                 reg = <0x40000000 0x80000000>;
 163         };
 164
 165         clocks {
 166                 #address-cells = <1>;
 167                 #size-cells = <1>;
 168                 ranges;
 169
 170                 /*
 171                  * This is a dummy clock, to be used as placeholder on
 172                  * other mux clocks when a specific parent clock is not
 173                  * yet implemented. It should be dropped when the driver
 174                  * is complete.
 175                  */
 176                 dummy: dummy {
 177                         #clock-cells = <0>;
 178                         compatible = "fixed-clock";
 179                         clock-frequency = <0>;
 180                 };
 181
 182                 osc24M: clk@01c20050 {
 183                         #clock-cells = <0>;
 184                         compatible = "allwinner,sun4i-a10-osc-clk";
 185                         reg = <0x01c20050 0x4>;
 186                         clock-frequency = <24000000>;
 187                         clock-output-names = "osc24M";
 188                 };
 189
 190                 osc3M: osc3M_clk {
 191                         compatible = "fixed-factor-clock";
 192                         #clock-cells = <0>;
 193                         clock-div = <8>;
 194                         clock-mult = <1>;
 195                         clocks = <&osc24M>;
 196                         clock-output-names = "osc3M";
 197                 };
 198
 199                 osc32k: clk@0 {
 200                         #clock-cells = <0>;
 201                         compatible = "fixed-clock";
 202                         clock-frequency = <32768>;
 203                         clock-output-names = "osc32k";
 204                 };
 205
 206                 pll1: clk@01c20000 {
 207                         #clock-cells = <0>;
 208                         compatible = "allwinner,sun4i-a10-pll1-clk";
 209                         reg = <0x01c20000 0x4>;
 210                         clocks = <&osc24M>;
 211                         clock-output-names = "pll1";
 212                 };
 213
 214                 pll2: clk@01c20008 {
 215                         #clock-cells = <1>;
 216                         compatible = "allwinner,sun4i-a10-pll2-clk";
 217                         reg = <0x01c20008 0x8>;
 218                         clocks = <&osc24M>;
 219                         clock-output-names = "pll2-1x", "pll2-2x",
 220                                              "pll2-4x", "pll2-8x";
 221                 };
 222
 223                 pll3: clk@01c20010 {
 224                         #clock-cells = <0>;
 225                         compatible = "allwinner,sun4i-a10-pll3-clk";
 226                         reg = <0x01c20010 0x4>;
 227                         clocks = <&osc3M>;
 228                         clock-output-names = "pll3";
 229                 };
 230
 231                 pll3x2: pll3x2_clk {
 232                         compatible = "fixed-factor-clock";
 233                         #clock-cells = <0>;
 234                         clock-div = <1>;
 235                         clock-mult = <2>;
 236                         clocks = <&pll3>;
 237                         clock-output-names = "pll3-2x";
 238                 };
 239
 240                 pll4: clk@01c20018 {
 241                         #clock-cells = <0>;
 242                         compatible = "allwinner,sun4i-a10-pll1-clk";
 243                         reg = <0x01c20018 0x4>;
 244                         clocks = <&osc24M>;
 245                         clock-output-names = "pll4";
 246                 };
 247
 248                 pll5: clk@01c20020 {
 249                         #clock-cells = <1>;
 250                         compatible = "allwinner,sun4i-a10-pll5-clk";
 251                         reg = <0x01c20020 0x4>;
 252                         clocks = <&osc24M>;
 253                         clock-output-names = "pll5_ddr", "pll5_other";
 254                 };
 255
 256                 pll6: clk@01c20028 {
 257                         #clock-cells = <1>;
 258                         compatible = "allwinner,sun4i-a10-pll6-clk";
 259                         reg = <0x01c20028 0x4>;
 260                         clocks = <&osc24M>;
 261                         clock-output-names = "pll6_sata", "pll6_other", "pll6";
 262                 };
 263
 264                 pll7: clk@01c20030 {
 265                         #clock-cells = <0>;
 266                         compatible = "allwinner,sun4i-a10-pll3-clk";
 267                         reg = <0x01c20030 0x4>;
 268                         clocks = <&osc3M>;
 269                         clock-output-names = "pll7";
 270                 };
 271
 272                 pll7x2: pll7x2_clk {
 273                         compatible = "fixed-factor-clock";
 274                         #clock-cells = <0>;
 275                         clock-div = <1>;
 276                         clock-mult = <2>;
 277                         clocks = <&pll7>;
 278                         clock-output-names = "pll7-2x";
 279                 };
 280
 281                 /* dummy is 200M */
 282                 cpu: cpu@01c20054 {
 283                         #clock-cells = <0>;
 284                         compatible = "allwinner,sun4i-a10-cpu-clk";
 285                         reg = <0x01c20054 0x4>;
 286                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
 287                         clock-output-names = "cpu";
 288                 };
 289
 290                 axi: axi@01c20054 {
 291                         #clock-cells = <0>;
 292                         compatible = "allwinner,sun4i-a10-axi-clk";
 293                         reg = <0x01c20054 0x4>;
 294                         clocks = <&cpu>;
 295                         clock-output-names = "axi";
 296                 };
 297
 298                 axi_gates: clk@01c2005c {
 299                         #clock-cells = <1>;
 300                         compatible = "allwinner,sun4i-a10-axi-gates-clk";
 301                         reg = <0x01c2005c 0x4>;
 302                         clocks = <&axi>;
 303                         clock-indices = <0>;
 304                         clock-output-names = "axi_dram";
 305                 };
 306
 307                 ahb: ahb@01c20054 {
 308                         #clock-cells = <0>;
 309                         compatible = "allwinner,sun4i-a10-ahb-clk";
 310                         reg = <0x01c20054 0x4>;
 311                         clocks = <&axi>;
 312                         clock-output-names = "ahb";
 313                 };
 314
 315                 ahb_gates: clk@01c20060 {
 316                         #clock-cells = <1>;
 317                         compatible = "allwinner,sun4i-a10-ahb-gates-clk";
 318                         reg = <0x01c20060 0x8>;
 319                         clocks = <&ahb>;
 320                         clock-indices = <0>, <1>,
 321                                         <2>, <3>,
 322                                         <4>, <5>, <6>,
 323                                         <7>, <8>, <9>,
 324                                         <10>, <11>, <12>,
 325                                         <13>, <14>, <16>,
 326                                         <17>, <18>, <20>,
 327                                         <21>, <22>, <23>,
 328                                         <24>, <25>, <26>,
 329                                         <32>, <33>, <34>,
 330                                         <35>, <36>, <37>,
 331                                         <40>, <41>, <43>,
 332                                         <44>, <45>,
 333                                         <46>, <47>,
 334                                         <50>, <52>;
 335                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 336                                              "ahb_ohci0", "ahb_ehci1",
 337                                              "ahb_ohci1", "ahb_ss", "ahb_dma",
 338                                              "ahb_bist", "ahb_mmc0", "ahb_mmc1",
 339                                              "ahb_mmc2", "ahb_mmc3", "ahb_ms",
 340                                              "ahb_nand", "ahb_sdram", "ahb_ace",
 341                                              "ahb_emac", "ahb_ts", "ahb_spi0",
 342                                              "ahb_spi1", "ahb_spi2", "ahb_spi3",
 343                                              "ahb_pata", "ahb_sata", "ahb_gps",
 344                                              "ahb_ve", "ahb_tvd", "ahb_tve0",
 345                                              "ahb_tve1", "ahb_lcd0", "ahb_lcd1",
 346                                              "ahb_csi0", "ahb_csi1", "ahb_hdmi",
 347                                              "ahb_de_be0", "ahb_de_be1",
 348                                              "ahb_de_fe0", "ahb_de_fe1",
 349                                              "ahb_mp", "ahb_mali400";
 350                 };
 351
 352                 apb0: apb0@01c20054 {
 353                         #clock-cells = <0>;
 354                         compatible = "allwinner,sun4i-a10-apb0-clk";
 355                         reg = <0x01c20054 0x4>;
 356                         clocks = <&ahb>;
 357                         clock-output-names = "apb0";
 358                 };
 359
 360                 apb0_gates: clk@01c20068 {
 361                         #clock-cells = <1>;
 362                         compatible = "allwinner,sun4i-a10-apb0-gates-clk";
 363                         reg = <0x01c20068 0x4>;
 364                         clocks = <&apb0>;
 365                         clock-indices = <0>, <1>,
 366                                         <2>, <3>,
 367                                         <5>, <6>,
 368                                         <7>, <10>;
 369                         clock-output-names = "apb0_codec", "apb0_spdif",
 370                                              "apb0_ac97", "apb0_iis",
 371                                              "apb0_pio", "apb0_ir0",
 372                                              "apb0_ir1", "apb0_keypad";
 373                 };
 374
 375                 apb1: clk@01c20058 {
 376                         #clock-cells = <0>;
 377                         compatible = "allwinner,sun4i-a10-apb1-clk";
 378                         reg = <0x01c20058 0x4>;
 379                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 380                         clock-output-names = "apb1";
 381                 };
 382
 383                 apb1_gates: clk@01c2006c {
 384                         #clock-cells = <1>;
 385                         compatible = "allwinner,sun4i-a10-apb1-gates-clk";
 386                         reg = <0x01c2006c 0x4>;
 387                         clocks = <&apb1>;
 388                         clock-indices = <0>, <1>,
 389                                         <2>, <4>,
 390                                         <5>, <6>,
 391                                         <7>, <16>,
 392                                         <17>, <18>,
 393                                         <19>, <20>,
 394                                         <21>, <22>,
 395                                         <23>;
 396                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 397                                              "apb1_i2c2", "apb1_can",
 398                                              "apb1_scr", "apb1_ps20",
 399                                              "apb1_ps21", "apb1_uart0",
 400                                              "apb1_uart1", "apb1_uart2",
 401                                              "apb1_uart3", "apb1_uart4",
 402                                              "apb1_uart5", "apb1_uart6",
 403                                              "apb1_uart7";
 404                 };
 405
 406                 nand_clk: clk@01c20080 {
 407                         #clock-cells = <0>;
 408                         compatible = "allwinner,sun4i-a10-mod0-clk";
 409                         reg = <0x01c20080 0x4>;
 410                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 411                         clock-output-names = "nand";
 412                 };
 413
 414                 ms_clk: clk@01c20084 {
 415                         #clock-cells = <0>;
 416                         compatible = "allwinner,sun4i-a10-mod0-clk";
 417                         reg = <0x01c20084 0x4>;
 418                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 419                         clock-output-names = "ms";
 420                 };
 421
 422                 mmc0_clk: clk@01c20088 {
 423                         #clock-cells = <1>;
 424                         compatible = "allwinner,sun4i-a10-mmc-clk";
 425                         reg = <0x01c20088 0x4>;
 426                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 427                         clock-output-names = "mmc0",
 428                                              "mmc0_output",
 429                                              "mmc0_sample";
 430                 };
 431
 432                 mmc1_clk: clk@01c2008c {
 433                         #clock-cells = <1>;
 434                         compatible = "allwinner,sun4i-a10-mmc-clk";
 435                         reg = <0x01c2008c 0x4>;
 436                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 437                         clock-output-names = "mmc1",
 438                                              "mmc1_output",
 439                                              "mmc1_sample";
 440                 };
 441
 442                 mmc2_clk: clk@01c20090 {
 443                         #clock-cells = <1>;
 444                         compatible = "allwinner,sun4i-a10-mmc-clk";
 445                         reg = <0x01c20090 0x4>;
 446                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 447                         clock-output-names = "mmc2",
 448                                              "mmc2_output",
 449                                              "mmc2_sample";
 450                 };
 451
 452                 mmc3_clk: clk@01c20094 {
 453                         #clock-cells = <1>;
 454                         compatible = "allwinner,sun4i-a10-mmc-clk";
 455                         reg = <0x01c20094 0x4>;
 456                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 457                         clock-output-names = "mmc3",
 458                                              "mmc3_output",
 459                                              "mmc3_sample";
 460                 };
 461
 462                 ts_clk: clk@01c20098 {
 463                         #clock-cells = <0>;
 464                         compatible = "allwinner,sun4i-a10-mod0-clk";
 465                         reg = <0x01c20098 0x4>;
 466                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 467                         clock-output-names = "ts";
 468                 };
 469
 470                 ss_clk: clk@01c2009c {
 471                         #clock-cells = <0>;
 472                         compatible = "allwinner,sun4i-a10-mod0-clk";
 473                         reg = <0x01c2009c 0x4>;
 474                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 475                         clock-output-names = "ss";
 476                 };
 477
 478                 spi0_clk: clk@01c200a0 {
 479                         #clock-cells = <0>;
 480                         compatible = "allwinner,sun4i-a10-mod0-clk";
 481                         reg = <0x01c200a0 0x4>;
 482                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 483                         clock-output-names = "spi0";
 484                 };
 485
 486                 spi1_clk: clk@01c200a4 {
 487                         #clock-cells = <0>;
 488                         compatible = "allwinner,sun4i-a10-mod0-clk";
 489                         reg = <0x01c200a4 0x4>;
 490                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 491                         clock-output-names = "spi1";
 492                 };
 493
 494                 spi2_clk: clk@01c200a8 {
 495                         #clock-cells = <0>;
 496                         compatible = "allwinner,sun4i-a10-mod0-clk";
 497                         reg = <0x01c200a8 0x4>;
 498                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 499                         clock-output-names = "spi2";
 500                 };
 501
 502                 pata_clk: clk@01c200ac {
 503                         #clock-cells = <0>;
 504                         compatible = "allwinner,sun4i-a10-mod0-clk";
 505                         reg = <0x01c200ac 0x4>;
 506                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 507                         clock-output-names = "pata";
 508                 };
 509
 510                 ir0_clk: clk@01c200b0 {
 511                         #clock-cells = <0>;
 512                         compatible = "allwinner,sun4i-a10-mod0-clk";
 513                         reg = <0x01c200b0 0x4>;
 514                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 515                         clock-output-names = "ir0";
 516                 };
 517
 518                 ir1_clk: clk@01c200b4 {
 519                         #clock-cells = <0>;
 520                         compatible = "allwinner,sun4i-a10-mod0-clk";
 521                         reg = <0x01c200b4 0x4>;
 522                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 523                         clock-output-names = "ir1";
 524                 };
 525
 526                 spdif_clk: clk@01c200c0 {
 527                         #clock-cells = <0>;
 528                         compatible = "allwinner,sun4i-a10-mod1-clk";
 529                         reg = <0x01c200c0 0x4>;
 530                         clocks = <&pll2 SUN4I_A10_PLL2_8X>,
 531                                  <&pll2 SUN4I_A10_PLL2_4X>,
 532                                  <&pll2 SUN4I_A10_PLL2_2X>,
 533                                  <&pll2 SUN4I_A10_PLL2_1X>;
 534                         clock-output-names = "spdif";
 535                 };
 536
 537                 usb_clk: clk@01c200cc {
 538                         #clock-cells = <1>;
 539                         #reset-cells = <1>;
 540                         compatible = "allwinner,sun4i-a10-usb-clk";
 541                         reg = <0x01c200cc 0x4>;
 542                         clocks = <&pll6 1>;
 543                         clock-output-names = "usb_ohci0", "usb_ohci1",
 544                                              "usb_phy";
 545                 };
 546
 547                 spi3_clk: clk@01c200d4 {
 548                         #clock-cells = <0>;
 549                         compatible = "allwinner,sun4i-a10-mod0-clk";
 550                         reg = <0x01c200d4 0x4>;
 551                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 552                         clock-output-names = "spi3";
 553                 };
 554
 555                 dram_gates: clk@01c20100 {
 556                         #clock-cells = <1>;
 557                         compatible = "allwinner,sun4i-a10-dram-gates-clk";
 558                         reg = <0x01c20100 0x4>;
 559                         clocks = <&pll5 0>;
 560                         clock-indices = <0>,
 561                                         <1>, <2>,
 562                                         <3>,
 563                                         <4>,
 564                                         <5>, <6>,
 565                                         <15>,
 566                                         <24>, <25>,
 567                                         <26>, <27>,
 568                                         <28>, <29>;
 569                         clock-output-names = "dram_ve",
 570                                              "dram_csi0", "dram_csi1",
 571                                              "dram_ts",
 572                                              "dram_tvd",
 573                                              "dram_tve0", "dram_tve1",
 574                                              "dram_output",
 575                                              "dram_de_fe1", "dram_de_fe0",
 576                                              "dram_de_be0", "dram_de_be1",
 577                                              "dram_de_mp", "dram_ace";
 578                 };
 579
 580                 ve_clk: clk@01c2013c {
 581                         #clock-cells = <0>;
 582                         #reset-cells = <0>;
 583                         compatible = "allwinner,sun4i-a10-ve-clk";
 584                         reg = <0x01c2013c 0x4>;
 585                         clocks = <&pll4>;
 586                         clock-output-names = "ve";
 587                 };
 588
 589                 codec_clk: clk@01c20140 {
 590                         #clock-cells = <0>;
 591                         compatible = "allwinner,sun4i-a10-codec-clk";
 592                         reg = <0x01c20140 0x4>;
 593                         clocks = <&pll2 SUN4I_A10_PLL2_1X>;
 594                         clock-output-names = "codec";
 595                 };
 596         };
 597
 598         soc@01c00000 {
 599                 compatible = "simple-bus";
 600                 #address-cells = <1>;
 601                 #size-cells = <1>;
 602                 ranges;
 603
 604                 sram-controller@01c00000 {
 605                         compatible = "allwinner,sun4i-a10-sram-controller";
 606                         reg = <0x01c00000 0x30>;
 607                         #address-cells = <1>;
 608                         #size-cells = <1>;
 609                         ranges;
 610
 611                         sram_a: sram@00000000 {
 612                                 compatible = "mmio-sram";
 613                                 reg = <0x00000000 0xc000>;
 614                                 #address-cells = <1>;
 615                                 #size-cells = <1>;
 616                                 ranges = <0 0x00000000 0xc000>;
 617
 618                                 emac_sram: sram-section@8000 {
 619                                         compatible = "allwinner,sun4i-a10-sram-a3-a4";
 620                                         reg = <0x8000 0x4000>;
 621                                         status = "disabled";
 622                                 };
 623                         };
 624
 625                         sram_d: sram@00010000 {
 626                                 compatible = "mmio-sram";
 627                                 reg = <0x00010000 0x1000>;
 628                                 #address-cells = <1>;
 629                                 #size-cells = <1>;
 630                                 ranges = <0 0x00010000 0x1000>;
 631
 632                                 otg_sram: sram-section@0000 {
 633                                         compatible = "allwinner,sun4i-a10-sram-d";
 634                                         reg = <0x0000 0x1000>;
 635                                         status = "disabled";
 636                                 };
 637                         };
 638                 };
 639
 640                 dma: dma-controller@01c02000 {
 641                         compatible = "allwinner,sun4i-a10-dma";
 642                         reg = <0x01c02000 0x1000>;
 643                         interrupts = <27>;
 644                         clocks = <&ahb_gates 6>;
 645                         #dma-cells = <2>;
 646                 };
 647
 648                 spi0: spi@01c05000 {
 649                         compatible = "allwinner,sun4i-a10-spi";
 650                         reg = <0x01c05000 0x1000>;
 651                         interrupts = <10>;
 652                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 653                         clock-names = "ahb", "mod";
 654                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 655                                <&dma SUN4I_DMA_DEDICATED 26>;
 656                         dma-names = "rx", "tx";
 657                         status = "disabled";
 658                         #address-cells = <1>;
 659                         #size-cells = <0>;
 660                 };
 661
 662                 spi1: spi@01c06000 {
 663                         compatible = "allwinner,sun4i-a10-spi";
 664                         reg = <0x01c06000 0x1000>;
 665                         interrupts = <11>;
 666                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 667                         clock-names = "ahb", "mod";
 668                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 669                                <&dma SUN4I_DMA_DEDICATED 8>;
 670                         dma-names = "rx", "tx";
 671                         status = "disabled";
 672                         #address-cells = <1>;
 673                         #size-cells = <0>;
 674                 };
 675
 676                 emac: ethernet@01c0b000 {
 677                         compatible = "allwinner,sun4i-a10-emac";
 678                         reg = <0x01c0b000 0x1000>;
 679                         interrupts = <55>;
 680                         clocks = <&ahb_gates 17>;
 681                         allwinner,sram = <&emac_sram 1>;
 682                         status = "disabled";
 683                 };
 684
 685                 mdio: mdio@01c0b080 {
 686                         compatible = "allwinner,sun4i-a10-mdio";
 687                         reg = <0x01c0b080 0x14>;
 688                         status = "disabled";
 689                         #address-cells = <1>;
 690                         #size-cells = <0>;
 691                 };
 692
 693                 mmc0: mmc@01c0f000 {
 694                         compatible = "allwinner,sun4i-a10-mmc";
 695                         reg = <0x01c0f000 0x1000>;
 696                         clocks = <&ahb_gates 8>,
 697                                  <&mmc0_clk 0>,
 698                                  <&mmc0_clk 1>,
 699                                  <&mmc0_clk 2>;
 700                         clock-names = "ahb",
 701                                       "mmc",
 702                                       "output",
 703                                       "sample";
 704                         interrupts = <32>;
 705                         status = "disabled";
 706                         #address-cells = <1>;
 707                         #size-cells = <0>;
 708                 };
 709
 710                 mmc1: mmc@01c10000 {
 711                         compatible = "allwinner,sun4i-a10-mmc";
 712                         reg = <0x01c10000 0x1000>;
 713                         clocks = <&ahb_gates 9>,
 714                                  <&mmc1_clk 0>,
 715                                  <&mmc1_clk 1>,
 716                                  <&mmc1_clk 2>;
 717                         clock-names = "ahb",
 718                                       "mmc",
 719                                       "output",
 720                                       "sample";
 721                         interrupts = <33>;
 722                         status = "disabled";
 723                         #address-cells = <1>;
 724                         #size-cells = <0>;
 725                 };
 726
 727                 mmc2: mmc@01c11000 {
 728                         compatible = "allwinner,sun4i-a10-mmc";
 729                         reg = <0x01c11000 0x1000>;
 730                         clocks = <&ahb_gates 10>,
 731                                  <&mmc2_clk 0>,
 732                                  <&mmc2_clk 1>,
 733                                  <&mmc2_clk 2>;
 734                         clock-names = "ahb",
 735                                       "mmc",
 736                                       "output",
 737                                       "sample";
 738                         interrupts = <34>;
 739                         status = "disabled";
 740                         #address-cells = <1>;
 741                         #size-cells = <0>;
 742                 };
 743
 744                 mmc3: mmc@01c12000 {
 745                         compatible = "allwinner,sun4i-a10-mmc";
 746                         reg = <0x01c12000 0x1000>;
 747                         clocks = <&ahb_gates 11>,
 748                                  <&mmc3_clk 0>,
 749                                  <&mmc3_clk 1>,
 750                                  <&mmc3_clk 2>;
 751                         clock-names = "ahb",
 752                                       "mmc",
 753                                       "output",
 754                                       "sample";
 755                         interrupts = <35>;
 756                         status = "disabled";
 757                         #address-cells = <1>;
 758                         #size-cells = <0>;
 759                 };
 760
 761                 usb_otg: usb@01c13000 {
 762                         compatible = "allwinner,sun4i-a10-musb";
 763                         reg = <0x01c13000 0x0400>;
 764                         clocks = <&ahb_gates 0>;
 765                         interrupts = <38>;
 766                         interrupt-names = "mc";
 767                         phys = <&usbphy 0>;
 768                         phy-names = "usb";
 769                         extcon = <&usbphy 0>;
 770                         allwinner,sram = <&otg_sram 1>;
 771                         status = "disabled";
 772                 };
 773
 774                 usbphy: phy@01c13400 {
 775                         #phy-cells = <1>;
 776                         compatible = "allwinner,sun4i-a10-usb-phy";
 777                         reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
 778                         reg-names = "phy_ctrl", "pmu1", "pmu2";
 779                         clocks = <&usb_clk 8>;
 780                         clock-names = "usb_phy";
 781                         resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
 782                         reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
 783                         status = "disabled";
 784                 };
 785
 786                 ehci0: usb@01c14000 {
 787                         compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
 788                         reg = <0x01c14000 0x100>;
 789                         interrupts = <39>;
 790                         clocks = <&ahb_gates 1>;
 791                         phys = <&usbphy 1>;
 792                         phy-names = "usb";
 793                         status = "disabled";
 794                 };
 795
 796                 ohci0: usb@01c14400 {
 797                         compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
 798                         reg = <0x01c14400 0x100>;
 799                         interrupts = <64>;
 800                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 801                         phys = <&usbphy 1>;
 802                         phy-names = "usb";
 803                         status = "disabled";
 804                 };
 805
 806                 crypto: crypto-engine@01c15000 {
 807                         compatible = "allwinner,sun4i-a10-crypto";
 808                         reg = <0x01c15000 0x1000>;
 809                         interrupts = <86>;
 810                         clocks = <&ahb_gates 5>, <&ss_clk>;
 811                         clock-names = "ahb", "mod";
 812                 };
 813
 814                 spi2: spi@01c17000 {
 815                         compatible = "allwinner,sun4i-a10-spi";
 816                         reg = <0x01c17000 0x1000>;
 817                         interrupts = <12>;
 818                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 819                         clock-names = "ahb", "mod";
 820                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 821                                <&dma SUN4I_DMA_DEDICATED 28>;
 822                         dma-names = "rx", "tx";
 823                         status = "disabled";
 824                         #address-cells = <1>;
 825                         #size-cells = <0>;
 826                 };
 827
 828                 ahci: sata@01c18000 {
 829                         compatible = "allwinner,sun4i-a10-ahci";
 830                         reg = <0x01c18000 0x1000>;
 831                         interrupts = <56>;
 832                         clocks = <&pll6 0>, <&ahb_gates 25>;
 833                         status = "disabled";
 834                 };
 835
 836                 ehci1: usb@01c1c000 {
 837                         compatible = "allwinner,sun4i-a10-ehci", "generic-ehci";
 838                         reg = <0x01c1c000 0x100>;
 839                         interrupts = <40>;
 840                         clocks = <&ahb_gates 3>;
 841                         phys = <&usbphy 2>;
 842                         phy-names = "usb";
 843                         status = "disabled";
 844                 };
 845
 846                 ohci1: usb@01c1c400 {
 847                         compatible = "allwinner,sun4i-a10-ohci", "generic-ohci";
 848                         reg = <0x01c1c400 0x100>;
 849                         interrupts = <65>;
 850                         clocks = <&usb_clk 7>, <&ahb_gates 4>;
 851                         phys = <&usbphy 2>;
 852                         phy-names = "usb";
 853                         status = "disabled";
 854                 };
 855
 856                 spi3: spi@01c1f000 {
 857                         compatible = "allwinner,sun4i-a10-spi";
 858                         reg = <0x01c1f000 0x1000>;
 859                         interrupts = <50>;
 860                         clocks = <&ahb_gates 23>, <&spi3_clk>;
 861                         clock-names = "ahb", "mod";
 862                         dmas = <&dma SUN4I_DMA_DEDICATED 31>,
 863                                <&dma SUN4I_DMA_DEDICATED 30>;
 864                         dma-names = "rx", "tx";
 865                         status = "disabled";
 866                         #address-cells = <1>;
 867                         #size-cells = <0>;
 868                 };
 869
 870                 intc: interrupt-controller@01c20400 {
 871                         compatible = "allwinner,sun4i-a10-ic";
 872                         reg = <0x01c20400 0x400>;
 873                         interrupt-controller;
 874                         #interrupt-cells = <1>;
 875                 };
 876
 877                 pio: pinctrl@01c20800 {
 878                         compatible = "allwinner,sun4i-a10-pinctrl";
 879                         reg = <0x01c20800 0x400>;
 880                         interrupts = <28>;
 881                         clocks = <&apb0_gates 5>;
 882                         gpio-controller;
 883                         interrupt-controller;
 884                         #interrupt-cells = <3>;
 885                         #gpio-cells = <3>;
 886
 887                         pwm0_pins_a: pwm0@0 {
 888                                 allwinner,pins = "PB2";
 889                                 allwinner,function = "pwm";
 890                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 891                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 892                         };
 893
 894                         pwm1_pins_a: pwm1@0 {
 895                                 allwinner,pins = "PI3";
 896                                 allwinner,function = "pwm";
 897                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 898                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 899                         };
 900
 901                         uart0_pins_a: uart0@0 {
 902                                 allwinner,pins = "PB22", "PB23";
 903                                 allwinner,function = "uart0";
 904                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 905                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 906                         };
 907
 908                         uart0_pins_b: uart0@1 {
 909                                 allwinner,pins = "PF2", "PF4";
 910                                 allwinner,function = "uart0";
 911                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 912                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 913                         };
 914
 915                         uart1_pins_a: uart1@0 {
 916                                 allwinner,pins = "PA10", "PA11";
 917                                 allwinner,function = "uart1";
 918                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 919                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 920                         };
 921
 922                         i2c0_pins_a: i2c0@0 {
 923                                 allwinner,pins = "PB0", "PB1";
 924                                 allwinner,function = "i2c0";
 925                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 926                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 927                         };
 928
 929                         i2c1_pins_a: i2c1@0 {
 930                                 allwinner,pins = "PB18", "PB19";
 931                                 allwinner,function = "i2c1";
 932                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 933                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 934                         };
 935
 936                         i2c2_pins_a: i2c2@0 {
 937                                 allwinner,pins = "PB20", "PB21";
 938                                 allwinner,function = "i2c2";
 939                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 940                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 941                         };
 942
 943                         emac_pins_a: emac0@0 {
 944                                 allwinner,pins = "PA0", "PA1", "PA2",
 945                                                 "PA3", "PA4", "PA5", "PA6",
 946                                                 "PA7", "PA8", "PA9", "PA10",
 947                                                 "PA11", "PA12", "PA13", "PA14",
 948                                                 "PA15", "PA16";
 949                                 allwinner,function = "emac";
 950                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 951                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 952                         };
 953
 954                         mmc0_pins_a: mmc0@0 {
 955                                 allwinner,pins = "PF0", "PF1", "PF2",
 956                                                  "PF3", "PF4", "PF5";
 957                                 allwinner,function = "mmc0";
 958                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 959                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 960                         };
 961
 962                         mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
 963                                 allwinner,pins = "PH1";
 964                                 allwinner,function = "gpio_in";
 965                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 966                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
 967                         };
 968
 969                         ir0_rx_pins_a: ir0@0 {
 970                                 allwinner,pins = "PB4";
 971                                 allwinner,function = "ir0";
 972                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 973                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 974                         };
 975
 976                         ir0_tx_pins_a: ir0@1 {
 977                                 allwinner,pins = "PB3";
 978                                 allwinner,function = "ir0";
 979                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 980                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 981                         };
 982
 983                         ir1_rx_pins_a: ir1@0 {
 984                                 allwinner,pins = "PB23";
 985                                 allwinner,function = "ir1";
 986                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 987                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 988                         };
 989
 990                         ir1_tx_pins_a: ir1@1 {
 991                                 allwinner,pins = "PB22";
 992                                 allwinner,function = "ir1";
 993                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 994                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 995                         };
 996
 997                         spi0_pins_a: spi0@0 {
 998                                 allwinner,pins = "PI11", "PI12", "PI13";
 999                                 allwinner,function = "spi0";
1000                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1001                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1002                         };
1003
1004                         spi0_cs0_pins_a: spi0_cs0@0 {
1005                                 allwinner,pins = "PI10";
1006                                 allwinner,function = "spi0";
1007                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1008                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1009                         };
1010
1011                         spi1_pins_a: spi1@0 {
1012                                 allwinner,pins = "PI17", "PI18", "PI19";
1013                                 allwinner,function = "spi1";
1014                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1015                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1016                         };
1017
1018                         spi1_cs0_pins_a: spi1_cs0@0 {
1019                                 allwinner,pins = "PI16";
1020                                 allwinner,function = "spi1";
1021                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1022                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1023                         };
1024
1025                         spi2_pins_a: spi2@0 {
1026                                 allwinner,pins = "PC20", "PC21", "PC22";
1027                                 allwinner,function = "spi2";
1028                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1029                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1030                         };
1031
1032                         spi2_pins_b: spi2@1 {
1033                                 allwinner,pins = "PB15", "PB16", "PB17";
1034                                 allwinner,function = "spi2";
1035                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1036                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1037                         };
1038
1039                         spi2_cs0_pins_a: spi2_cs0@0 {
1040                                 allwinner,pins = "PC19";
1041                                 allwinner,function = "spi2";
1042                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1043                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1044                         };
1045
1046                         spi2_cs0_pins_b: spi2_cs0@1 {
1047                                 allwinner,pins = "PB14";
1048                                 allwinner,function = "spi2";
1049                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1050                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1051                         };
1052
1053                         ps20_pins_a: ps20@0 {
1054                                 allwinner,pins = "PI20", "PI21";
1055                                 allwinner,function = "ps2";
1056                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1057                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1058                         };
1059
1060                         ps21_pins_a: ps21@0 {
1061                                 allwinner,pins = "PH12", "PH13";
1062                                 allwinner,function = "ps2";
1063                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1064                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1065                         };
1066
1067                         spdif_tx_pins_a: spdif@0 {
1068                                 allwinner,pins = "PB13";
1069                                 allwinner,function = "spdif";
1070                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1071                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1072                         };
1073                 };
1074
1075                 timer@01c20c00 {
1076                         compatible = "allwinner,sun4i-a10-timer";
1077                         reg = <0x01c20c00 0x90>;
1078                         interrupts = <22>;
1079                         clocks = <&osc24M>;
1080                 };
1081
1082                 wdt: watchdog@01c20c90 {
1083                         compatible = "allwinner,sun4i-a10-wdt";
1084                         reg = <0x01c20c90 0x10>;
1085                 };
1086
1087                 rtc: rtc@01c20d00 {
1088                         compatible = "allwinner,sun4i-a10-rtc";
1089                         reg = <0x01c20d00 0x20>;
1090                         interrupts = <24>;
1091                 };
1092
1093                 pwm: pwm@01c20e00 {
1094                         compatible = "allwinner,sun4i-a10-pwm";
1095                         reg = <0x01c20e00 0xc>;
1096                         clocks = <&osc24M>;
1097                         #pwm-cells = <3>;
1098                         status = "disabled";
1099                 };
1100
1101                 spdif: spdif@01c21000 {
1102                         #sound-dai-cells = <0>;
1103                         compatible = "allwinner,sun4i-a10-spdif";
1104                         reg = <0x01c21000 0x400>;
1105                         interrupts = <13>;
1106                         clocks = <&apb0_gates 1>, <&spdif_clk>;
1107                         clock-names = "apb", "spdif";
1108                         dmas = <&dma SUN4I_DMA_NORMAL 2>,
1109                                <&dma SUN4I_DMA_NORMAL 2>;
1110                         dma-names = "rx", "tx";
1111                         status = "disabled";
1112                 };
1113
1114                 ir0: ir@01c21800 {
1115                         compatible = "allwinner,sun4i-a10-ir";
1116                         clocks = <&apb0_gates 6>, <&ir0_clk>;
1117                         clock-names = "apb", "ir";
1118                         interrupts = <5>;
1119                         reg = <0x01c21800 0x40>;
1120                         status = "disabled";
1121                 };
1122
1123                 ir1: ir@01c21c00 {
1124                         compatible = "allwinner,sun4i-a10-ir";
1125                         clocks = <&apb0_gates 7>, <&ir1_clk>;
1126                         clock-names = "apb", "ir";
1127                         interrupts = <6>;
1128                         reg = <0x01c21c00 0x40>;
1129                         status = "disabled";
1130                 };
1131
1132                 lradc: lradc@01c22800 {
1133                         compatible = "allwinner,sun4i-a10-lradc-keys";
1134                         reg = <0x01c22800 0x100>;
1135                         interrupts = <31>;
1136                         status = "disabled";
1137                 };
1138
1139                 codec: codec@01c22c00 {
1140                         #sound-dai-cells = <0>;
1141                         compatible = "allwinner,sun4i-a10-codec";
1142                         reg = <0x01c22c00 0x40>;
1143                         interrupts = <30>;
1144                         clocks = <&apb0_gates 0>, <&codec_clk>;
1145                         clock-names = "apb", "codec";
1146                         dmas = <&dma SUN4I_DMA_NORMAL 19>,
1147                                <&dma SUN4I_DMA_NORMAL 19>;
1148                         dma-names = "rx", "tx";
1149                         status = "disabled";
1150                 };
1151
1152                 sid: eeprom@01c23800 {
1153                         compatible = "allwinner,sun4i-a10-sid";
1154                         reg = <0x01c23800 0x10>;
1155                 };
1156
1157                 rtp: rtp@01c25000 {
1158                         compatible = "allwinner,sun4i-a10-ts";
1159                         reg = <0x01c25000 0x100>;
1160                         interrupts = <29>;
1161                         #thermal-sensor-cells = <0>;
1162                 };
1163
1164                 uart0: serial@01c28000 {
1165                         compatible = "snps,dw-apb-uart";
1166                         reg = <0x01c28000 0x400>;
1167                         interrupts = <1>;
1168                         reg-shift = <2>;
1169                         reg-io-width = <4>;
1170                         clocks = <&apb1_gates 16>;
1171                         status = "disabled";
1172                 };
1173
1174                 uart1: serial@01c28400 {
1175                         compatible = "snps,dw-apb-uart";
1176                         reg = <0x01c28400 0x400>;
1177                         interrupts = <2>;
1178                         reg-shift = <2>;
1179                         reg-io-width = <4>;
1180                         clocks = <&apb1_gates 17>;
1181                         status = "disabled";
1182                 };
1183
1184                 uart2: serial@01c28800 {
1185                         compatible = "snps,dw-apb-uart";
1186                         reg = <0x01c28800 0x400>;
1187                         interrupts = <3>;
1188                         reg-shift = <2>;
1189                         reg-io-width = <4>;
1190                         clocks = <&apb1_gates 18>;
1191                         status = "disabled";
1192                 };
1193
1194                 uart3: serial@01c28c00 {
1195                         compatible = "snps,dw-apb-uart";
1196                         reg = <0x01c28c00 0x400>;
1197                         interrupts = <4>;
1198                         reg-shift = <2>;
1199                         reg-io-width = <4>;
1200                         clocks = <&apb1_gates 19>;
1201                         status = "disabled";
1202                 };
1203
1204                 uart4: serial@01c29000 {
1205                         compatible = "snps,dw-apb-uart";
1206                         reg = <0x01c29000 0x400>;
1207                         interrupts = <17>;
1208                         reg-shift = <2>;
1209                         reg-io-width = <4>;
1210                         clocks = <&apb1_gates 20>;
1211                         status = "disabled";
1212                 };
1213
1214                 uart5: serial@01c29400 {
1215                         compatible = "snps,dw-apb-uart";
1216                         reg = <0x01c29400 0x400>;
1217                         interrupts = <18>;
1218                         reg-shift = <2>;
1219                         reg-io-width = <4>;
1220                         clocks = <&apb1_gates 21>;
1221                         status = "disabled";
1222                 };
1223
1224                 uart6: serial@01c29800 {
1225                         compatible = "snps,dw-apb-uart";
1226                         reg = <0x01c29800 0x400>;
1227                         interrupts = <19>;
1228                         reg-shift = <2>;
1229                         reg-io-width = <4>;
1230                         clocks = <&apb1_gates 22>;
1231                         status = "disabled";
1232                 };
1233
1234                 uart7: serial@01c29c00 {
1235                         compatible = "snps,dw-apb-uart";
1236                         reg = <0x01c29c00 0x400>;
1237                         interrupts = <20>;
1238                         reg-shift = <2>;
1239                         reg-io-width = <4>;
1240                         clocks = <&apb1_gates 23>;
1241                         status = "disabled";
1242                 };
1243
1244                 i2c0: i2c@01c2ac00 {
1245                         compatible = "allwinner,sun4i-a10-i2c";
1246                         reg = <0x01c2ac00 0x400>;
1247                         interrupts = <7>;
1248                         clocks = <&apb1_gates 0>;
1249                         status = "disabled";
1250                         #address-cells = <1>;
1251                         #size-cells = <0>;
1252                 };
1253
1254                 i2c1: i2c@01c2b000 {
1255                         compatible = "allwinner,sun4i-a10-i2c";
1256                         reg = <0x01c2b000 0x400>;
1257                         interrupts = <8>;
1258                         clocks = <&apb1_gates 1>;
1259                         status = "disabled";
1260                         #address-cells = <1>;
1261                         #size-cells = <0>;
1262                 };
1263
1264                 i2c2: i2c@01c2b400 {
1265                         compatible = "allwinner,sun4i-a10-i2c";
1266                         reg = <0x01c2b400 0x400>;
1267                         interrupts = <9>;
1268                         clocks = <&apb1_gates 2>;
1269                         status = "disabled";
1270                         #address-cells = <1>;
1271                         #size-cells = <0>;
1272                 };
1273
1274                 ps20: ps2@01c2a000 {
1275                         compatible = "allwinner,sun4i-a10-ps2";
1276                         reg = <0x01c2a000 0x400>;
1277                         interrupts = <62>;
1278                         clocks = <&apb1_gates 6>;
1279                         status = "disabled";
1280                 };
1281
1282                 ps21: ps2@01c2a400 {
1283                         compatible = "allwinner,sun4i-a10-ps2";
1284                         reg = <0x01c2a400 0x400>;
1285                         interrupts = <63>;
1286                         clocks = <&apb1_gates 7>;
1287                         status = "disabled";
1288                 };
1289         };
1290 };