arch/arm/boot/dts/sun7i-a20.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "skeleton.dtsi"
  46
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48 #include <dt-bindings/thermal/thermal.h>
  49
  50 #include <dt-bindings/clock/sun4i-a10-pll2.h>
  51 #include <dt-bindings/dma/sun4i-a10.h>
  52 #include <dt-bindings/pinctrl/sun4i-a10.h>
  53
  54 / {
  55         interrupt-parent = <&gic>;
  56
  57         aliases {
  58                 ethernet0 = &gmac;
  59         };
  60
  61         chosen {
  62                 #address-cells = <1>;
  63                 #size-cells = <1>;
  64                 ranges;
  65
  66                 framebuffer@0 {
  67                         compatible = "allwinner,simple-framebuffer",
  68                                      "simple-framebuffer";
  69                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  70                         clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
  71                                  <&ahb_gates 43>, <&ahb_gates 44>,
  72                                  <&dram_gates 26>;
  73                         status = "disabled";
  74                 };
  75
  76                 framebuffer@1 {
  77                         compatible = "allwinner,simple-framebuffer",
  78                                      "simple-framebuffer";
  79                         allwinner,pipeline = "de_be0-lcd0";
  80                         clocks = <&pll3>, <&pll5 1>, <&ahb_gates 36>,
  81                                  <&ahb_gates 44>, <&dram_gates 26>;
  82                         status = "disabled";
  83                 };
  84
  85                 framebuffer@2 {
  86                         compatible = "allwinner,simple-framebuffer",
  87                                      "simple-framebuffer";
  88                         allwinner,pipeline = "de_be0-lcd0-tve0";
  89                         clocks = <&pll3>, <&pll5 1>,
  90                                  <&ahb_gates 34>, <&ahb_gates 36>, <&ahb_gates 44>,
  91                                  <&dram_gates 5>, <&dram_gates 26>;
  92                         status = "disabled";
  93                 };
  94         };
  95
  96         cpus {
  97                 #address-cells = <1>;
  98                 #size-cells = <0>;
  99
 100                 cpu0: cpu@0 {
 101                         compatible = "arm,cortex-a7";
 102                         device_type = "cpu";
 103                         reg = <0>;
 104                         clocks = <&cpu>;
 105                         clock-latency = <244144>; /* 8 32k periods */
 106                         operating-points = <
 107                                 /* kHz    uV */
 108                                 960000  1400000
 109                                 912000  1400000
 110                                 864000  1300000
 111                                 720000  1200000
 112                                 528000  1100000
 113                                 312000  1000000
 114                                 144000  1000000
 115                                 >;
 116                         #cooling-cells = <2>;
 117                         cooling-min-level = <0>;
 118                         cooling-max-level = <6>;
 119                 };
 120
 121                 cpu@1 {
 122                         compatible = "arm,cortex-a7";
 123                         device_type = "cpu";
 124                         reg = <1>;
 125                 };
 126         };
 127
 128         thermal-zones {
 129                 cpu_thermal {
 130                         /* milliseconds */
 131                         polling-delay-passive = <250>;
 132                         polling-delay = <1000>;
 133                         thermal-sensors = <&rtp>;
 134
 135                         cooling-maps {
 136                                 map0 {
 137                                         trip = <&cpu_alert0>;
 138                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 139                                 };
 140                         };
 141
 142                         trips {
 143                                 cpu_alert0: cpu_alert0 {
 144                                         /* milliCelsius */
 145                                         temperature = <75000>;
 146                                         hysteresis = <2000>;
 147                                         type = "passive";
 148                                 };
 149
 150                                 cpu_crit: cpu_crit {
 151                                         /* milliCelsius */
 152                                         temperature = <100000>;
 153                                         hysteresis = <2000>;
 154                                         type = "critical";
 155                                 };
 156                         };
 157                 };
 158         };
 159
 160         memory {
 161                 reg = <0x40000000 0x80000000>;
 162         };
 163
 164         timer {
 165                 compatible = "arm,armv7-timer";
 166                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 167                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 168                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 169                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 170         };
 171
 172         pmu {
 173                 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
 174                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 175                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 176         };
 177
 178         clocks {
 179                 #address-cells = <1>;
 180                 #size-cells = <1>;
 181                 ranges;
 182
 183                 osc24M: clk@01c20050 {
 184                         #clock-cells = <0>;
 185                         compatible = "allwinner,sun4i-a10-osc-clk";
 186                         reg = <0x01c20050 0x4>;
 187                         clock-frequency = <24000000>;
 188                         clock-output-names = "osc24M";
 189                 };
 190
 191                 osc3M: osc3M_clk {
 192                         #clock-cells = <0>;
 193                         compatible = "fixed-factor-clock";
 194                         clock-div = <8>;
 195                         clock-mult = <1>;
 196                         clocks = <&osc24M>;
 197                         clock-output-names = "osc3M";
 198                 };
 199
 200                 osc32k: clk@0 {
 201                         #clock-cells = <0>;
 202                         compatible = "fixed-clock";
 203                         clock-frequency = <32768>;
 204                         clock-output-names = "osc32k";
 205                 };
 206
 207                 pll1: clk@01c20000 {
 208                         #clock-cells = <0>;
 209                         compatible = "allwinner,sun4i-a10-pll1-clk";
 210                         reg = <0x01c20000 0x4>;
 211                         clocks = <&osc24M>;
 212                         clock-output-names = "pll1";
 213                 };
 214
 215                 pll2: clk@01c20008 {
 216                         #clock-cells = <1>;
 217                         compatible = "allwinner,sun4i-a10-pll2-clk";
 218                         reg = <0x01c20008 0x8>;
 219                         clocks = <&osc24M>;
 220                         clock-output-names = "pll2-1x", "pll2-2x",
 221                                              "pll2-4x", "pll2-8x";
 222                 };
 223
 224                 pll3: clk@01c20010 {
 225                         #clock-cells = <0>;
 226                         compatible = "allwinner,sun4i-a10-pll3-clk";
 227                         reg = <0x01c20010 0x4>;
 228                         clocks = <&osc3M>;
 229                         clock-output-names = "pll3";
 230                 };
 231
 232                 pll3x2: pll3x2_clk {
 233                         #clock-cells = <0>;
 234                         compatible = "fixed-factor-clock";
 235                         clocks = <&pll3>;
 236                         clock-div = <1>;
 237                         clock-mult = <2>;
 238                         clock-output-names = "pll3-2x";
 239                 };
 240
 241                 pll4: clk@01c20018 {
 242                         #clock-cells = <0>;
 243                         compatible = "allwinner,sun7i-a20-pll4-clk";
 244                         reg = <0x01c20018 0x4>;
 245                         clocks = <&osc24M>;
 246                         clock-output-names = "pll4";
 247                 };
 248
 249                 pll5: clk@01c20020 {
 250                         #clock-cells = <1>;
 251                         compatible = "allwinner,sun4i-a10-pll5-clk";
 252                         reg = <0x01c20020 0x4>;
 253                         clocks = <&osc24M>;
 254                         clock-output-names = "pll5_ddr", "pll5_other";
 255                 };
 256
 257                 pll6: clk@01c20028 {
 258                         #clock-cells = <1>;
 259                         compatible = "allwinner,sun4i-a10-pll6-clk";
 260                         reg = <0x01c20028 0x4>;
 261                         clocks = <&osc24M>;
 262                         clock-output-names = "pll6_sata", "pll6_other", "pll6",
 263                                              "pll6_div_4";
 264                 };
 265
 266                 pll7: clk@01c20030 {
 267                         #clock-cells = <0>;
 268                         compatible = "allwinner,sun4i-a10-pll3-clk";
 269                         reg = <0x01c20030 0x4>;
 270                         clocks = <&osc3M>;
 271                         clock-output-names = "pll7";
 272                 };
 273
 274                 pll7x2: pll7x2_clk {
 275                         #clock-cells = <0>;
 276                         compatible = "fixed-factor-clock";
 277                         clocks = <&pll7>;
 278                         clock-div = <1>;
 279                         clock-mult = <2>;
 280                         clock-output-names = "pll7-2x";
 281                 };
 282
 283                 pll8: clk@01c20040 {
 284                         #clock-cells = <0>;
 285                         compatible = "allwinner,sun7i-a20-pll4-clk";
 286                         reg = <0x01c20040 0x4>;
 287                         clocks = <&osc24M>;
 288                         clock-output-names = "pll8";
 289                 };
 290
 291                 cpu: cpu@01c20054 {
 292                         #clock-cells = <0>;
 293                         compatible = "allwinner,sun4i-a10-cpu-clk";
 294                         reg = <0x01c20054 0x4>;
 295                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll6 1>;
 296                         clock-output-names = "cpu";
 297                 };
 298
 299                 axi: axi@01c20054 {
 300                         #clock-cells = <0>;
 301                         compatible = "allwinner,sun4i-a10-axi-clk";
 302                         reg = <0x01c20054 0x4>;
 303                         clocks = <&cpu>;
 304                         clock-output-names = "axi";
 305                 };
 306
 307                 ahb: ahb@01c20054 {
 308                         #clock-cells = <0>;
 309                         compatible = "allwinner,sun5i-a13-ahb-clk";
 310                         reg = <0x01c20054 0x4>;
 311                         clocks = <&axi>, <&pll6 3>, <&pll6 1>;
 312                         clock-output-names = "ahb";
 313                         /*
 314                          * Use PLL6 as parent, instead of CPU/AXI
 315                          * which has rate changes due to cpufreq
 316                          */
 317                         assigned-clocks = <&ahb>;
 318                         assigned-clock-parents = <&pll6 3>;
 319                 };
 320
 321                 ahb_gates: clk@01c20060 {
 322                         #clock-cells = <1>;
 323                         compatible = "allwinner,sun7i-a20-ahb-gates-clk";
 324                         reg = <0x01c20060 0x8>;
 325                         clocks = <&ahb>;
 326                         clock-indices = <0>, <1>,
 327                                         <2>, <3>, <4>,
 328                                         <5>, <6>, <7>, <8>,
 329                                         <9>, <10>, <11>, <12>,
 330                                         <13>, <14>, <16>,
 331                                         <17>, <18>, <20>, <21>,
 332                                         <22>, <23>, <25>,
 333                                         <28>, <32>, <33>, <34>,
 334                                         <35>, <36>, <37>, <40>,
 335                                         <41>, <42>, <43>,
 336                                         <44>, <45>, <46>,
 337                                         <47>, <49>, <50>,
 338                                         <52>;
 339                         clock-output-names = "ahb_usb0", "ahb_ehci0",
 340                                 "ahb_ohci0", "ahb_ehci1", "ahb_ohci1",
 341                                 "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
 342                                 "ahb_mmc1", "ahb_mmc2", "ahb_mmc3", "ahb_ms",
 343                                 "ahb_nand", "ahb_sdram", "ahb_ace",
 344                                 "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1",
 345                                 "ahb_spi2", "ahb_spi3", "ahb_sata",
 346                                 "ahb_hstimer", "ahb_ve", "ahb_tvd", "ahb_tve0",
 347                                 "ahb_tve1", "ahb_lcd0", "ahb_lcd1", "ahb_csi0",
 348                                 "ahb_csi1", "ahb_hdmi1", "ahb_hdmi0",
 349                                 "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
 350                                 "ahb_de_fe1", "ahb_gmac", "ahb_mp",
 351                                 "ahb_mali";
 352                 };
 353
 354                 apb0: apb0@01c20054 {
 355                         #clock-cells = <0>;
 356                         compatible = "allwinner,sun4i-a10-apb0-clk";
 357                         reg = <0x01c20054 0x4>;
 358                         clocks = <&ahb>;
 359                         clock-output-names = "apb0";
 360                 };
 361
 362                 apb0_gates: clk@01c20068 {
 363                         #clock-cells = <1>;
 364                         compatible = "allwinner,sun7i-a20-apb0-gates-clk";
 365                         reg = <0x01c20068 0x4>;
 366                         clocks = <&apb0>;
 367                         clock-indices = <0>, <1>,
 368                                         <2>, <3>, <4>,
 369                                         <5>, <6>, <7>,
 370                                         <8>, <10>;
 371                         clock-output-names = "apb0_codec", "apb0_spdif",
 372                                 "apb0_ac97", "apb0_iis0", "apb0_iis1",
 373                                 "apb0_pio", "apb0_ir0", "apb0_ir1",
 374                                 "apb0_iis2", "apb0_keypad";
 375                 };
 376
 377                 apb1: clk@01c20058 {
 378                         #clock-cells = <0>;
 379                         compatible = "allwinner,sun4i-a10-apb1-clk";
 380                         reg = <0x01c20058 0x4>;
 381                         clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
 382                         clock-output-names = "apb1";
 383                 };
 384
 385                 apb1_gates: clk@01c2006c {
 386                         #clock-cells = <1>;
 387                         compatible = "allwinner,sun7i-a20-apb1-gates-clk";
 388                         reg = <0x01c2006c 0x4>;
 389                         clocks = <&apb1>;
 390                         clock-indices = <0>, <1>,
 391                                         <2>, <3>, <4>,
 392                                         <5>, <6>, <7>,
 393                                         <15>, <16>, <17>,
 394                                         <18>, <19>, <20>,
 395                                         <21>, <22>, <23>;
 396                         clock-output-names = "apb1_i2c0", "apb1_i2c1",
 397                                 "apb1_i2c2", "apb1_i2c3", "apb1_can",
 398                                 "apb1_scr", "apb1_ps20", "apb1_ps21",
 399                                 "apb1_i2c4", "apb1_uart0", "apb1_uart1",
 400                                 "apb1_uart2", "apb1_uart3", "apb1_uart4",
 401                                 "apb1_uart5", "apb1_uart6", "apb1_uart7";
 402                 };
 403
 404                 nand_clk: clk@01c20080 {
 405                         #clock-cells = <0>;
 406                         compatible = "allwinner,sun4i-a10-mod0-clk";
 407                         reg = <0x01c20080 0x4>;
 408                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 409                         clock-output-names = "nand";
 410                 };
 411
 412                 ms_clk: clk@01c20084 {
 413                         #clock-cells = <0>;
 414                         compatible = "allwinner,sun4i-a10-mod0-clk";
 415                         reg = <0x01c20084 0x4>;
 416                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 417                         clock-output-names = "ms";
 418                 };
 419
 420                 mmc0_clk: clk@01c20088 {
 421                         #clock-cells = <1>;
 422                         compatible = "allwinner,sun4i-a10-mmc-clk";
 423                         reg = <0x01c20088 0x4>;
 424                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 425                         clock-output-names = "mmc0",
 426                                              "mmc0_output",
 427                                              "mmc0_sample";
 428                 };
 429
 430                 mmc1_clk: clk@01c2008c {
 431                         #clock-cells = <1>;
 432                         compatible = "allwinner,sun4i-a10-mmc-clk";
 433                         reg = <0x01c2008c 0x4>;
 434                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 435                         clock-output-names = "mmc1",
 436                                              "mmc1_output",
 437                                              "mmc1_sample";
 438                 };
 439
 440                 mmc2_clk: clk@01c20090 {
 441                         #clock-cells = <1>;
 442                         compatible = "allwinner,sun4i-a10-mmc-clk";
 443                         reg = <0x01c20090 0x4>;
 444                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 445                         clock-output-names = "mmc2",
 446                                              "mmc2_output",
 447                                              "mmc2_sample";
 448                 };
 449
 450                 mmc3_clk: clk@01c20094 {
 451                         #clock-cells = <1>;
 452                         compatible = "allwinner,sun4i-a10-mmc-clk";
 453                         reg = <0x01c20094 0x4>;
 454                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 455                         clock-output-names = "mmc3",
 456                                              "mmc3_output",
 457                                              "mmc3_sample";
 458                 };
 459
 460                 ts_clk: clk@01c20098 {
 461                         #clock-cells = <0>;
 462                         compatible = "allwinner,sun4i-a10-mod0-clk";
 463                         reg = <0x01c20098 0x4>;
 464                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 465                         clock-output-names = "ts";
 466                 };
 467
 468                 ss_clk: clk@01c2009c {
 469                         #clock-cells = <0>;
 470                         compatible = "allwinner,sun4i-a10-mod0-clk";
 471                         reg = <0x01c2009c 0x4>;
 472                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 473                         clock-output-names = "ss";
 474                 };
 475
 476                 spi0_clk: clk@01c200a0 {
 477                         #clock-cells = <0>;
 478                         compatible = "allwinner,sun4i-a10-mod0-clk";
 479                         reg = <0x01c200a0 0x4>;
 480                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 481                         clock-output-names = "spi0";
 482                 };
 483
 484                 spi1_clk: clk@01c200a4 {
 485                         #clock-cells = <0>;
 486                         compatible = "allwinner,sun4i-a10-mod0-clk";
 487                         reg = <0x01c200a4 0x4>;
 488                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 489                         clock-output-names = "spi1";
 490                 };
 491
 492                 spi2_clk: clk@01c200a8 {
 493                         #clock-cells = <0>;
 494                         compatible = "allwinner,sun4i-a10-mod0-clk";
 495                         reg = <0x01c200a8 0x4>;
 496                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 497                         clock-output-names = "spi2";
 498                 };
 499
 500                 pata_clk: clk@01c200ac {
 501                         #clock-cells = <0>;
 502                         compatible = "allwinner,sun4i-a10-mod0-clk";
 503                         reg = <0x01c200ac 0x4>;
 504                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 505                         clock-output-names = "pata";
 506                 };
 507
 508                 ir0_clk: clk@01c200b0 {
 509                         #clock-cells = <0>;
 510                         compatible = "allwinner,sun4i-a10-mod0-clk";
 511                         reg = <0x01c200b0 0x4>;
 512                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 513                         clock-output-names = "ir0";
 514                 };
 515
 516                 ir1_clk: clk@01c200b4 {
 517                         #clock-cells = <0>;
 518                         compatible = "allwinner,sun4i-a10-mod0-clk";
 519                         reg = <0x01c200b4 0x4>;
 520                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 521                         clock-output-names = "ir1";
 522                 };
 523
 524                 spdif_clk: clk@01c200c0 {
 525                         #clock-cells = <0>;
 526                         compatible = "allwinner,sun4i-a10-mod1-clk";
 527                         reg = <0x01c200c0 0x4>;
 528                         clocks = <&pll2 SUN4I_A10_PLL2_8X>,
 529                                  <&pll2 SUN4I_A10_PLL2_4X>,
 530                                  <&pll2 SUN4I_A10_PLL2_2X>,
 531                                  <&pll2 SUN4I_A10_PLL2_1X>;
 532                         clock-output-names = "spdif";
 533                 };
 534
 535                 keypad_clk: clk@01c200c4 {
 536                         #clock-cells = <0>;
 537                         compatible = "allwinner,sun4i-a10-mod0-clk";
 538                         reg = <0x01c200c4 0x4>;
 539                         clocks = <&osc24M>;
 540                         clock-output-names = "keypad";
 541                 };
 542
 543                 usb_clk: clk@01c200cc {
 544                         #clock-cells = <1>;
 545                         #reset-cells = <1>;
 546                         compatible = "allwinner,sun4i-a10-usb-clk";
 547                         reg = <0x01c200cc 0x4>;
 548                         clocks = <&pll6 1>;
 549                         clock-output-names = "usb_ohci0", "usb_ohci1",
 550                                              "usb_phy";
 551                 };
 552
 553                 spi3_clk: clk@01c200d4 {
 554                         #clock-cells = <0>;
 555                         compatible = "allwinner,sun4i-a10-mod0-clk";
 556                         reg = <0x01c200d4 0x4>;
 557                         clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
 558                         clock-output-names = "spi3";
 559                 };
 560
 561                 dram_gates: clk@01c20100 {
 562                         #clock-cells = <1>;
 563                         compatible = "allwinner,sun4i-a10-dram-gates-clk";
 564                         reg = <0x01c20100 0x4>;
 565                         clocks = <&pll5 0>;
 566                         clock-indices = <0>,
 567                                         <1>, <2>,
 568                                         <3>,
 569                                         <4>,
 570                                         <5>, <6>,
 571                                         <15>,
 572                                         <24>, <25>,
 573                                         <26>, <27>,
 574                                         <28>, <29>;
 575                         clock-output-names = "dram_ve",
 576                                              "dram_csi0", "dram_csi1",
 577                                              "dram_ts",
 578                                              "dram_tvd",
 579                                              "dram_tve0", "dram_tve1",
 580                                              "dram_output",
 581                                              "dram_de_fe1", "dram_de_fe0",
 582                                              "dram_de_be0", "dram_de_be1",
 583                                              "dram_de_mp", "dram_ace";
 584                 };
 585
 586                 ve_clk: clk@01c2013c {
 587                         #clock-cells = <0>;
 588                         #reset-cells = <0>;
 589                         compatible = "allwinner,sun4i-a10-ve-clk";
 590                         reg = <0x01c2013c 0x4>;
 591                         clocks = <&pll4>;
 592                         clock-output-names = "ve";
 593                 };
 594
 595                 codec_clk: clk@01c20140 {
 596                         #clock-cells = <0>;
 597                         compatible = "allwinner,sun4i-a10-codec-clk";
 598                         reg = <0x01c20140 0x4>;
 599                         clocks = <&pll2 SUN4I_A10_PLL2_1X>;
 600                         clock-output-names = "codec";
 601                 };
 602
 603                 mbus_clk: clk@01c2015c {
 604                         #clock-cells = <0>;
 605                         compatible = "allwinner,sun5i-a13-mbus-clk";
 606                         reg = <0x01c2015c 0x4>;
 607                         clocks = <&osc24M>, <&pll6 2>, <&pll5 1>;
 608                         clock-output-names = "mbus";
 609                 };
 610
 611                 /*
 612                  * The following two are dummy clocks, placeholders
 613                  * used in the gmac_tx clock. The gmac driver will
 614                  * choose one parent depending on the PHY interface
 615                  * mode, using clk_set_rate auto-reparenting.
 616                  *
 617                  * The actual TX clock rate is not controlled by the
 618                  * gmac_tx clock.
 619                  */
 620                 mii_phy_tx_clk: clk@2 {
 621                         #clock-cells = <0>;
 622                         compatible = "fixed-clock";
 623                         clock-frequency = <25000000>;
 624                         clock-output-names = "mii_phy_tx";
 625                 };
 626
 627                 gmac_int_tx_clk: clk@3 {
 628                         #clock-cells = <0>;
 629                         compatible = "fixed-clock";
 630                         clock-frequency = <125000000>;
 631                         clock-output-names = "gmac_int_tx";
 632                 };
 633
 634                 gmac_tx_clk: clk@01c20164 {
 635                         #clock-cells = <0>;
 636                         compatible = "allwinner,sun7i-a20-gmac-clk";
 637                         reg = <0x01c20164 0x4>;
 638                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 639                         clock-output-names = "gmac_tx";
 640                 };
 641
 642                 /*
 643                  * Dummy clock used by output clocks
 644                  */
 645                 osc24M_32k: clk@1 {
 646                         #clock-cells = <0>;
 647                         compatible = "fixed-factor-clock";
 648                         clock-div = <750>;
 649                         clock-mult = <1>;
 650                         clocks = <&osc24M>;
 651                         clock-output-names = "osc24M_32k";
 652                 };
 653
 654                 clk_out_a: clk@01c201f0 {
 655                         #clock-cells = <0>;
 656                         compatible = "allwinner,sun7i-a20-out-clk";
 657                         reg = <0x01c201f0 0x4>;
 658                         clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
 659                         clock-output-names = "clk_out_a";
 660                 };
 661
 662                 clk_out_b: clk@01c201f4 {
 663                         #clock-cells = <0>;
 664                         compatible = "allwinner,sun7i-a20-out-clk";
 665                         reg = <0x01c201f4 0x4>;
 666                         clocks = <&osc24M_32k>, <&osc32k>, <&osc24M>;
 667                         clock-output-names = "clk_out_b";
 668                 };
 669         };
 670
 671         soc@01c00000 {
 672                 compatible = "simple-bus";
 673                 #address-cells = <1>;
 674                 #size-cells = <1>;
 675                 ranges;
 676
 677                 sram-controller@01c00000 {
 678                         compatible = "allwinner,sun4i-a10-sram-controller";
 679                         reg = <0x01c00000 0x30>;
 680                         #address-cells = <1>;
 681                         #size-cells = <1>;
 682                         ranges;
 683
 684                         sram_a: sram@00000000 {
 685                                 compatible = "mmio-sram";
 686                                 reg = <0x00000000 0xc000>;
 687                                 #address-cells = <1>;
 688                                 #size-cells = <1>;
 689                                 ranges = <0 0x00000000 0xc000>;
 690
 691                                 emac_sram: sram-section@8000 {
 692                                         compatible = "allwinner,sun4i-a10-sram-a3-a4";
 693                                         reg = <0x8000 0x4000>;
 694                                         status = "disabled";
 695                                 };
 696                         };
 697
 698                         sram_d: sram@00010000 {
 699                                 compatible = "mmio-sram";
 700                                 reg = <0x00010000 0x1000>;
 701                                 #address-cells = <1>;
 702                                 #size-cells = <1>;
 703                                 ranges = <0 0x00010000 0x1000>;
 704
 705                                 otg_sram: sram-section@0000 {
 706                                         compatible = "allwinner,sun4i-a10-sram-d";
 707                                         reg = <0x0000 0x1000>;
 708                                         status = "disabled";
 709                                 };
 710                         };
 711                 };
 712
 713                 nmi_intc: interrupt-controller@01c00030 {
 714                         compatible = "allwinner,sun7i-a20-sc-nmi";
 715                         interrupt-controller;
 716                         #interrupt-cells = <2>;
 717                         reg = <0x01c00030 0x0c>;
 718                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 719                 };
 720
 721                 dma: dma-controller@01c02000 {
 722                         compatible = "allwinner,sun4i-a10-dma";
 723                         reg = <0x01c02000 0x1000>;
 724                         interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 725                         clocks = <&ahb_gates 6>;
 726                         #dma-cells = <2>;
 727                 };
 728
 729                 spi0: spi@01c05000 {
 730                         compatible = "allwinner,sun4i-a10-spi";
 731                         reg = <0x01c05000 0x1000>;
 732                         interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 733                         clocks = <&ahb_gates 20>, <&spi0_clk>;
 734                         clock-names = "ahb", "mod";
 735                         dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 736                                <&dma SUN4I_DMA_DEDICATED 26>;
 737                         dma-names = "rx", "tx";
 738                         status = "disabled";
 739                         #address-cells = <1>;
 740                         #size-cells = <0>;
 741                 };
 742
 743                 spi1: spi@01c06000 {
 744                         compatible = "allwinner,sun4i-a10-spi";
 745                         reg = <0x01c06000 0x1000>;
 746                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 747                         clocks = <&ahb_gates 21>, <&spi1_clk>;
 748                         clock-names = "ahb", "mod";
 749                         dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 750                                <&dma SUN4I_DMA_DEDICATED 8>;
 751                         dma-names = "rx", "tx";
 752                         status = "disabled";
 753                         #address-cells = <1>;
 754                         #size-cells = <0>;
 755                 };
 756
 757                 emac: ethernet@01c0b000 {
 758                         compatible = "allwinner,sun4i-a10-emac";
 759                         reg = <0x01c0b000 0x1000>;
 760                         interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 761                         clocks = <&ahb_gates 17>;
 762                         allwinner,sram = <&emac_sram 1>;
 763                         status = "disabled";
 764                 };
 765
 766                 mdio: mdio@01c0b080 {
 767                         compatible = "allwinner,sun4i-a10-mdio";
 768                         reg = <0x01c0b080 0x14>;
 769                         status = "disabled";
 770                         #address-cells = <1>;
 771                         #size-cells = <0>;
 772                 };
 773
 774                 mmc0: mmc@01c0f000 {
 775                         compatible = "allwinner,sun5i-a13-mmc";
 776                         reg = <0x01c0f000 0x1000>;
 777                         clocks = <&ahb_gates 8>,
 778                                  <&mmc0_clk 0>,
 779                                  <&mmc0_clk 1>,
 780                                  <&mmc0_clk 2>;
 781                         clock-names = "ahb",
 782                                       "mmc",
 783                                       "output",
 784                                       "sample";
 785                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 786                         status = "disabled";
 787                         #address-cells = <1>;
 788                         #size-cells = <0>;
 789                 };
 790
 791                 mmc1: mmc@01c10000 {
 792                         compatible = "allwinner,sun5i-a13-mmc";
 793                         reg = <0x01c10000 0x1000>;
 794                         clocks = <&ahb_gates 9>,
 795                                  <&mmc1_clk 0>,
 796                                  <&mmc1_clk 1>,
 797                                  <&mmc1_clk 2>;
 798                         clock-names = "ahb",
 799                                       "mmc",
 800                                       "output",
 801                                       "sample";
 802                         interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 803                         status = "disabled";
 804                         #address-cells = <1>;
 805                         #size-cells = <0>;
 806                 };
 807
 808                 mmc2: mmc@01c11000 {
 809                         compatible = "allwinner,sun5i-a13-mmc";
 810                         reg = <0x01c11000 0x1000>;
 811                         clocks = <&ahb_gates 10>,
 812                                  <&mmc2_clk 0>,
 813                                  <&mmc2_clk 1>,
 814                                  <&mmc2_clk 2>;
 815                         clock-names = "ahb",
 816                                       "mmc",
 817                                       "output",
 818                                       "sample";
 819                         interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 820                         status = "disabled";
 821                         #address-cells = <1>;
 822                         #size-cells = <0>;
 823                 };
 824
 825                 mmc3: mmc@01c12000 {
 826                         compatible = "allwinner,sun5i-a13-mmc";
 827                         reg = <0x01c12000 0x1000>;
 828                         clocks = <&ahb_gates 11>,
 829                                  <&mmc3_clk 0>,
 830                                  <&mmc3_clk 1>,
 831                                  <&mmc3_clk 2>;
 832                         clock-names = "ahb",
 833                                       "mmc",
 834                                       "output",
 835                                       "sample";
 836                         interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 837                         status = "disabled";
 838                         #address-cells = <1>;
 839                         #size-cells = <0>;
 840                 };
 841
 842                 usb_otg: usb@01c13000 {
 843                         compatible = "allwinner,sun4i-a10-musb";
 844                         reg = <0x01c13000 0x0400>;
 845                         clocks = <&ahb_gates 0>;
 846                         interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 847                         interrupt-names = "mc";
 848                         phys = <&usbphy 0>;
 849                         phy-names = "usb";
 850                         extcon = <&usbphy 0>;
 851                         allwinner,sram = <&otg_sram 1>;
 852                         status = "disabled";
 853                 };
 854
 855                 usbphy: phy@01c13400 {
 856                         #phy-cells = <1>;
 857                         compatible = "allwinner,sun7i-a20-usb-phy";
 858                         reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>;
 859                         reg-names = "phy_ctrl", "pmu1", "pmu2";
 860                         clocks = <&usb_clk 8>;
 861                         clock-names = "usb_phy";
 862                         resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>;
 863                         reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
 864                         status = "disabled";
 865                 };
 866
 867                 ehci0: usb@01c14000 {
 868                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 869                         reg = <0x01c14000 0x100>;
 870                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 871                         clocks = <&ahb_gates 1>;
 872                         phys = <&usbphy 1>;
 873                         phy-names = "usb";
 874                         status = "disabled";
 875                 };
 876
 877                 ohci0: usb@01c14400 {
 878                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 879                         reg = <0x01c14400 0x100>;
 880                         interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 881                         clocks = <&usb_clk 6>, <&ahb_gates 2>;
 882                         phys = <&usbphy 1>;
 883                         phy-names = "usb";
 884                         status = "disabled";
 885                 };
 886
 887                 crypto: crypto-engine@01c15000 {
 888                         compatible = "allwinner,sun4i-a10-crypto";
 889                         reg = <0x01c15000 0x1000>;
 890                         interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 891                         clocks = <&ahb_gates 5>, <&ss_clk>;
 892                         clock-names = "ahb", "mod";
 893                 };
 894
 895                 spi2: spi@01c17000 {
 896                         compatible = "allwinner,sun4i-a10-spi";
 897                         reg = <0x01c17000 0x1000>;
 898                         interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 899                         clocks = <&ahb_gates 22>, <&spi2_clk>;
 900                         clock-names = "ahb", "mod";
 901                         dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 902                                <&dma SUN4I_DMA_DEDICATED 28>;
 903                         dma-names = "rx", "tx";
 904                         status = "disabled";
 905                         #address-cells = <1>;
 906                         #size-cells = <0>;
 907                 };
 908
 909                 ahci: sata@01c18000 {
 910                         compatible = "allwinner,sun4i-a10-ahci";
 911                         reg = <0x01c18000 0x1000>;
 912                         interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 913                         clocks = <&pll6 0>, <&ahb_gates 25>;
 914                         status = "disabled";
 915                 };
 916
 917                 ehci1: usb@01c1c000 {
 918                         compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 919                         reg = <0x01c1c000 0x100>;
 920                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 921                         clocks = <&ahb_gates 3>;
 922                         phys = <&usbphy 2>;
 923                         phy-names = "usb";
 924                         status = "disabled";
 925                 };
 926
 927                 ohci1: usb@01c1c400 {
 928                         compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 929                         reg = <0x01c1c400 0x100>;
 930                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 931                         clocks = <&usb_clk 7>, <&ahb_gates 4>;
 932                         phys = <&usbphy 2>;
 933                         phy-names = "usb";
 934                         status = "disabled";
 935                 };
 936
 937                 spi3: spi@01c1f000 {
 938                         compatible = "allwinner,sun4i-a10-spi";
 939                         reg = <0x01c1f000 0x1000>;
 940                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 941                         clocks = <&ahb_gates 23>, <&spi3_clk>;
 942                         clock-names = "ahb", "mod";
 943                         dmas = <&dma SUN4I_DMA_DEDICATED 31>,
 944                                <&dma SUN4I_DMA_DEDICATED 30>;
 945                         dma-names = "rx", "tx";
 946                         status = "disabled";
 947                         #address-cells = <1>;
 948                         #size-cells = <0>;
 949                 };
 950
 951                 pio: pinctrl@01c20800 {
 952                         compatible = "allwinner,sun7i-a20-pinctrl";
 953                         reg = <0x01c20800 0x400>;
 954                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 955                         clocks = <&apb0_gates 5>;
 956                         gpio-controller;
 957                         interrupt-controller;
 958                         #interrupt-cells = <3>;
 959                         #gpio-cells = <3>;
 960
 961                         pwm0_pins_a: pwm0@0 {
 962                                 allwinner,pins = "PB2";
 963                                 allwinner,function = "pwm";
 964                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 965                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 966                         };
 967
 968                         pwm1_pins_a: pwm1@0 {
 969                                 allwinner,pins = "PI3";
 970                                 allwinner,function = "pwm";
 971                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 972                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 973                         };
 974
 975                         uart0_pins_a: uart0@0 {
 976                                 allwinner,pins = "PB22", "PB23";
 977                                 allwinner,function = "uart0";
 978                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 979                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 980                         };
 981
 982                         uart2_pins_a: uart2@0 {
 983                                 allwinner,pins = "PI16", "PI17", "PI18", "PI19";
 984                                 allwinner,function = "uart2";
 985                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 986                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 987                         };
 988
 989                         uart3_pins_a: uart3@0 {
 990                                 allwinner,pins = "PG6", "PG7", "PG8", "PG9";
 991                                 allwinner,function = "uart3";
 992                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 993                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 994                         };
 995
 996                         uart3_pins_b: uart3@1 {
 997                                 allwinner,pins = "PH0", "PH1";
 998                                 allwinner,function = "uart3";
 999                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1000                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1001                         };
1002
1003                         uart4_pins_a: uart4@0 {
1004                                 allwinner,pins = "PG10", "PG11";
1005                                 allwinner,function = "uart4";
1006                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1007                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1008                         };
1009
1010                         uart4_pins_b: uart4@1 {
1011                                 allwinner,pins = "PH4", "PH5";
1012                                 allwinner,function = "uart4";
1013                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1014                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1015                         };
1016
1017                         uart5_pins_a: uart5@0 {
1018                                 allwinner,pins = "PI10", "PI11";
1019                                 allwinner,function = "uart5";
1020                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1021                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1022                         };
1023
1024                         uart6_pins_a: uart6@0 {
1025                                 allwinner,pins = "PI12", "PI13";
1026                                 allwinner,function = "uart6";
1027                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1028                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1029                         };
1030
1031                         uart7_pins_a: uart7@0 {
1032                                 allwinner,pins = "PI20", "PI21";
1033                                 allwinner,function = "uart7";
1034                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1035                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1036                         };
1037
1038                         i2c0_pins_a: i2c0@0 {
1039                                 allwinner,pins = "PB0", "PB1";
1040                                 allwinner,function = "i2c0";
1041                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1042                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1043                         };
1044
1045                         i2c1_pins_a: i2c1@0 {
1046                                 allwinner,pins = "PB18", "PB19";
1047                                 allwinner,function = "i2c1";
1048                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1049                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1050                         };
1051
1052                         i2c2_pins_a: i2c2@0 {
1053                                 allwinner,pins = "PB20", "PB21";
1054                                 allwinner,function = "i2c2";
1055                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1056                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1057                         };
1058
1059                         i2c3_pins_a: i2c3@0 {
1060                                 allwinner,pins = "PI0", "PI1";
1061                                 allwinner,function = "i2c3";
1062                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1063                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1064                         };
1065
1066                         emac_pins_a: emac0@0 {
1067                                 allwinner,pins = "PA0", "PA1", "PA2",
1068                                                 "PA3", "PA4", "PA5", "PA6",
1069                                                 "PA7", "PA8", "PA9", "PA10",
1070                                                 "PA11", "PA12", "PA13", "PA14",
1071                                                 "PA15", "PA16";
1072                                 allwinner,function = "emac";
1073                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1074                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1075                         };
1076
1077                         clk_out_a_pins_a: clk_out_a@0 {
1078                                 allwinner,pins = "PI12";
1079                                 allwinner,function = "clk_out_a";
1080                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1081                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1082                         };
1083
1084                         clk_out_b_pins_a: clk_out_b@0 {
1085                                 allwinner,pins = "PI13";
1086                                 allwinner,function = "clk_out_b";
1087                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1088                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1089                         };
1090
1091                         gmac_pins_mii_a: gmac_mii@0 {
1092                                 allwinner,pins = "PA0", "PA1", "PA2",
1093                                                 "PA3", "PA4", "PA5", "PA6",
1094                                                 "PA7", "PA8", "PA9", "PA10",
1095                                                 "PA11", "PA12", "PA13", "PA14",
1096                                                 "PA15", "PA16";
1097                                 allwinner,function = "gmac";
1098                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1099                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1100                         };
1101
1102                         gmac_pins_rgmii_a: gmac_rgmii@0 {
1103                                 allwinner,pins = "PA0", "PA1", "PA2",
1104                                                 "PA3", "PA4", "PA5", "PA6",
1105                                                 "PA7", "PA8", "PA10",
1106                                                 "PA11", "PA12", "PA13",
1107                                                 "PA15", "PA16";
1108                                 allwinner,function = "gmac";
1109                                 /*
1110                                  * data lines in RGMII mode use DDR mode
1111                                  * and need a higher signal drive strength
1112                                  */
1113                                 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
1114                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1115                         };
1116
1117                         spi0_pins_a: spi0@0 {
1118                                 allwinner,pins = "PI11", "PI12", "PI13";
1119                                 allwinner,function = "spi0";
1120                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1121                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1122                         };
1123
1124                         spi0_cs0_pins_a: spi0_cs0@0 {
1125                                 allwinner,pins = "PI10";
1126                                 allwinner,function = "spi0";
1127                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1128                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1129                         };
1130
1131                         spi0_cs1_pins_a: spi0_cs1@0 {
1132                                 allwinner,pins = "PI14";
1133                                 allwinner,function = "spi0";
1134                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1135                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1136                         };
1137
1138                         spi1_pins_a: spi1@0 {
1139                                 allwinner,pins = "PI17", "PI18", "PI19";
1140                                 allwinner,function = "spi1";
1141                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1142                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1143                         };
1144
1145                         spi1_cs0_pins_a: spi1_cs0@0 {
1146                                 allwinner,pins = "PI16";
1147                                 allwinner,function = "spi1";
1148                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1149                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1150                         };
1151
1152                         spi2_pins_a: spi2@0 {
1153                                 allwinner,pins = "PC20", "PC21", "PC22";
1154                                 allwinner,function = "spi2";
1155                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1156                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1157                         };
1158
1159                         spi2_pins_b: spi2@1 {
1160                                 allwinner,pins = "PB15", "PB16", "PB17";
1161                                 allwinner,function = "spi2";
1162                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1163                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1164                         };
1165
1166                         spi2_cs0_pins_a: spi2_cs0@0 {
1167                                 allwinner,pins = "PC19";
1168                                 allwinner,function = "spi2";
1169                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1170                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1171                         };
1172
1173                         spi2_cs0_pins_b: spi2_cs0@1 {
1174                                 allwinner,pins = "PB14";
1175                                 allwinner,function = "spi2";
1176                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1177                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1178                         };
1179
1180                         mmc0_pins_a: mmc0@0 {
1181                                 allwinner,pins = "PF0", "PF1", "PF2",
1182                                                  "PF3", "PF4", "PF5";
1183                                 allwinner,function = "mmc0";
1184                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1185                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1186                         };
1187
1188                         mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
1189                                 allwinner,pins = "PH1";
1190                                 allwinner,function = "gpio_in";
1191                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1192                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1193                         };
1194
1195                         mmc2_pins_a: mmc2@0 {
1196                                 allwinner,pins = "PC6", "PC7", "PC8",
1197                                                  "PC9", "PC10", "PC11";
1198                                 allwinner,function = "mmc2";
1199                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1200                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1201                         };
1202
1203                         mmc3_pins_a: mmc3@0 {
1204                                 allwinner,pins = "PI4", "PI5", "PI6",
1205                                                  "PI7", "PI8", "PI9";
1206                                 allwinner,function = "mmc3";
1207                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
1208                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1209                         };
1210
1211                         ir0_rx_pins_a: ir0@0 {
1212                                     allwinner,pins = "PB4";
1213                                     allwinner,function = "ir0";
1214                                     allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1215                                     allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1216                         };
1217
1218                         ir0_tx_pins_a: ir0@1 {
1219                                     allwinner,pins = "PB3";
1220                                     allwinner,function = "ir0";
1221                                     allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1222                                     allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1223                         };
1224
1225                         ir1_rx_pins_a: ir1@0 {
1226                                     allwinner,pins = "PB23";
1227                                     allwinner,function = "ir1";
1228                                     allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1229                                     allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1230                         };
1231
1232                         ir1_tx_pins_a: ir1@1 {
1233                                     allwinner,pins = "PB22";
1234                                     allwinner,function = "ir1";
1235                                     allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1236                                     allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1237                         };
1238
1239                         ps20_pins_a: ps20@0 {
1240                                 allwinner,pins = "PI20", "PI21";
1241                                 allwinner,function = "ps2";
1242                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1243                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1244                         };
1245
1246                         ps21_pins_a: ps21@0 {
1247                                 allwinner,pins = "PH12", "PH13";
1248                                 allwinner,function = "ps2";
1249                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1250                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1251                         };
1252
1253                         spdif_tx_pins_a: spdif@0 {
1254                                 allwinner,pins = "PB13";
1255                                 allwinner,function = "spdif";
1256                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1257                                 allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
1258                         };
1259                 };
1260
1261                 timer@01c20c00 {
1262                         compatible = "allwinner,sun4i-a10-timer";
1263                         reg = <0x01c20c00 0x90>;
1264                         interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
1265                                      <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
1266                                      <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1267                                      <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1268                                      <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1269                                      <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1270                         clocks = <&osc24M>;
1271                 };
1272
1273                 wdt: watchdog@01c20c90 {
1274                         compatible = "allwinner,sun4i-a10-wdt";
1275                         reg = <0x01c20c90 0x10>;
1276                 };
1277
1278                 rtc: rtc@01c20d00 {
1279                         compatible = "allwinner,sun7i-a20-rtc";
1280                         reg = <0x01c20d00 0x20>;
1281                         interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1282                 };
1283
1284                 pwm: pwm@01c20e00 {
1285                         compatible = "allwinner,sun7i-a20-pwm";
1286                         reg = <0x01c20e00 0xc>;
1287                         clocks = <&osc24M>;
1288                         #pwm-cells = <3>;
1289                         status = "disabled";
1290                 };
1291
1292                 spdif: spdif@01c21000 {
1293                         #sound-dai-cells = <0>;
1294                         compatible = "allwinner,sun4i-a10-spdif";
1295                         reg = <0x01c21000 0x400>;
1296                         interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1297                         clocks = <&apb0_gates 1>, <&spdif_clk>;
1298                         clock-names = "apb", "spdif";
1299                         dmas = <&dma SUN4I_DMA_NORMAL 2>,
1300                                <&dma SUN4I_DMA_NORMAL 2>;
1301                         dma-names = "rx", "tx";
1302                         status = "disabled";
1303                 };
1304
1305                 ir0: ir@01c21800 {
1306                         compatible = "allwinner,sun4i-a10-ir";
1307                         clocks = <&apb0_gates 6>, <&ir0_clk>;
1308                         clock-names = "apb", "ir";
1309                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1310                         reg = <0x01c21800 0x40>;
1311                         status = "disabled";
1312                 };
1313
1314                 ir1: ir@01c21c00 {
1315                         compatible = "allwinner,sun4i-a10-ir";
1316                         clocks = <&apb0_gates 7>, <&ir1_clk>;
1317                         clock-names = "apb", "ir";
1318                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1319                         reg = <0x01c21c00 0x40>;
1320                         status = "disabled";
1321                 };
1322
1323                 lradc: lradc@01c22800 {
1324                         compatible = "allwinner,sun4i-a10-lradc-keys";
1325                         reg = <0x01c22800 0x100>;
1326                         interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1327                         status = "disabled";
1328                 };
1329
1330                 codec: codec@01c22c00 {
1331                         #sound-dai-cells = <0>;
1332                         compatible = "allwinner,sun7i-a20-codec";
1333                         reg = <0x01c22c00 0x40>;
1334                         interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1335                         clocks = <&apb0_gates 0>, <&codec_clk>;
1336                         clock-names = "apb", "codec";
1337                         dmas = <&dma SUN4I_DMA_NORMAL 19>,
1338                                <&dma SUN4I_DMA_NORMAL 19>;
1339                         dma-names = "rx", "tx";
1340                         status = "disabled";
1341                 };
1342
1343                 sid: eeprom@01c23800 {
1344                         compatible = "allwinner,sun7i-a20-sid";
1345                         reg = <0x01c23800 0x200>;
1346                 };
1347
1348                 rtp: rtp@01c25000 {
1349                         compatible = "allwinner,sun5i-a13-ts";
1350                         reg = <0x01c25000 0x100>;
1351                         interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1352                         #thermal-sensor-cells = <0>;
1353                 };
1354
1355                 uart0: serial@01c28000 {
1356                         compatible = "snps,dw-apb-uart";
1357                         reg = <0x01c28000 0x400>;
1358                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1359                         reg-shift = <2>;
1360                         reg-io-width = <4>;
1361                         clocks = <&apb1_gates 16>;
1362                         status = "disabled";
1363                 };
1364
1365                 uart1: serial@01c28400 {
1366                         compatible = "snps,dw-apb-uart";
1367                         reg = <0x01c28400 0x400>;
1368                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1369                         reg-shift = <2>;
1370                         reg-io-width = <4>;
1371                         clocks = <&apb1_gates 17>;
1372                         status = "disabled";
1373                 };
1374
1375                 uart2: serial@01c28800 {
1376                         compatible = "snps,dw-apb-uart";
1377                         reg = <0x01c28800 0x400>;
1378                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1379                         reg-shift = <2>;
1380                         reg-io-width = <4>;
1381                         clocks = <&apb1_gates 18>;
1382                         status = "disabled";
1383                 };
1384
1385                 uart3: serial@01c28c00 {
1386                         compatible = "snps,dw-apb-uart";
1387                         reg = <0x01c28c00 0x400>;
1388                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1389                         reg-shift = <2>;
1390                         reg-io-width = <4>;
1391                         clocks = <&apb1_gates 19>;
1392                         status = "disabled";
1393                 };
1394
1395                 uart4: serial@01c29000 {
1396                         compatible = "snps,dw-apb-uart";
1397                         reg = <0x01c29000 0x400>;
1398                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1399                         reg-shift = <2>;
1400                         reg-io-width = <4>;
1401                         clocks = <&apb1_gates 20>;
1402                         status = "disabled";
1403                 };
1404
1405                 uart5: serial@01c29400 {
1406                         compatible = "snps,dw-apb-uart";
1407                         reg = <0x01c29400 0x400>;
1408                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1409                         reg-shift = <2>;
1410                         reg-io-width = <4>;
1411                         clocks = <&apb1_gates 21>;
1412                         status = "disabled";
1413                 };
1414
1415                 uart6: serial@01c29800 {
1416                         compatible = "snps,dw-apb-uart";
1417                         reg = <0x01c29800 0x400>;
1418                         interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1419                         reg-shift = <2>;
1420                         reg-io-width = <4>;
1421                         clocks = <&apb1_gates 22>;
1422                         status = "disabled";
1423                 };
1424
1425                 uart7: serial@01c29c00 {
1426                         compatible = "snps,dw-apb-uart";
1427                         reg = <0x01c29c00 0x400>;
1428                         interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1429                         reg-shift = <2>;
1430                         reg-io-width = <4>;
1431                         clocks = <&apb1_gates 23>;
1432                         status = "disabled";
1433                 };
1434
1435                 i2c0: i2c@01c2ac00 {
1436                         compatible = "allwinner,sun7i-a20-i2c",
1437                                      "allwinner,sun4i-a10-i2c";
1438                         reg = <0x01c2ac00 0x400>;
1439                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1440                         clocks = <&apb1_gates 0>;
1441                         status = "disabled";
1442                         #address-cells = <1>;
1443                         #size-cells = <0>;
1444                 };
1445
1446                 i2c1: i2c@01c2b000 {
1447                         compatible = "allwinner,sun7i-a20-i2c",
1448                                      "allwinner,sun4i-a10-i2c";
1449                         reg = <0x01c2b000 0x400>;
1450                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1451                         clocks = <&apb1_gates 1>;
1452                         status = "disabled";
1453                         #address-cells = <1>;
1454                         #size-cells = <0>;
1455                 };
1456
1457                 i2c2: i2c@01c2b400 {
1458                         compatible = "allwinner,sun7i-a20-i2c",
1459                                      "allwinner,sun4i-a10-i2c";
1460                         reg = <0x01c2b400 0x400>;
1461                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1462                         clocks = <&apb1_gates 2>;
1463                         status = "disabled";
1464                         #address-cells = <1>;
1465                         #size-cells = <0>;
1466                 };
1467
1468                 i2c3: i2c@01c2b800 {
1469                         compatible = "allwinner,sun7i-a20-i2c",
1470                                      "allwinner,sun4i-a10-i2c";
1471                         reg = <0x01c2b800 0x400>;
1472                         interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1473                         clocks = <&apb1_gates 3>;
1474                         status = "disabled";
1475                         #address-cells = <1>;
1476                         #size-cells = <0>;
1477                 };
1478
1479                 i2c4: i2c@01c2c000 {
1480                         compatible = "allwinner,sun7i-a20-i2c",
1481                                      "allwinner,sun4i-a10-i2c";
1482                         reg = <0x01c2c000 0x400>;
1483                         interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1484                         clocks = <&apb1_gates 15>;
1485                         status = "disabled";
1486                         #address-cells = <1>;
1487                         #size-cells = <0>;
1488                 };
1489
1490                 gmac: ethernet@01c50000 {
1491                         compatible = "allwinner,sun7i-a20-gmac";
1492                         reg = <0x01c50000 0x10000>;
1493                         interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1494                         interrupt-names = "macirq";
1495                         clocks = <&ahb_gates 49>, <&gmac_tx_clk>;
1496                         clock-names = "stmmaceth", "allwinner_gmac_tx";
1497                         snps,pbl = <2>;
1498                         snps,fixed-burst;
1499                         snps,force_sf_dma_mode;
1500                         status = "disabled";
1501                         #address-cells = <1>;
1502                         #size-cells = <0>;
1503                 };
1504
1505                 hstimer@01c60000 {
1506                         compatible = "allwinner,sun7i-a20-hstimer";
1507                         reg = <0x01c60000 0x1000>;
1508                         interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1509                                      <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1510                                      <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1511                                      <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1512                         clocks = <&ahb_gates 28>;
1513                 };
1514
1515                 gic: interrupt-controller@01c81000 {
1516                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
1517                         reg = <0x01c81000 0x1000>,
1518                               <0x01c82000 0x1000>,
1519                               <0x01c84000 0x2000>,
1520                               <0x01c86000 0x2000>;
1521                         interrupt-controller;
1522                         #interrupt-cells = <3>;
1523                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1524                 };
1525
1526                 ps20: ps2@01c2a000 {
1527                         compatible = "allwinner,sun4i-a10-ps2";
1528                         reg = <0x01c2a000 0x400>;
1529                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1530                         clocks = <&apb1_gates 6>;
1531                         status = "disabled";
1532                 };
1533
1534                 ps21: ps2@01c2a400 {
1535                         compatible = "allwinner,sun4i-a10-ps2";
1536                         reg = <0x01c2a400 0x400>;
1537                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1538                         clocks = <&apb1_gates 7>;
1539                         status = "disabled";
1540                 };
1541         };
1542 };