arch/arm/mach-omap2/board-am335xevm.c

   1 /*
   2  * Code for AM335X EVM.
   3  *
   4  * Copyright (C) 2011 Texas Instruments, Inc. - http://www.ti.com/
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/i2c.h>
  18 #include <linux/i2c/at24.h>
  19 #include <linux/phy.h>
  20 #include <linux/gpio.h>
  21 #include <linux/spi/spi.h>
  22 #include <linux/spi/flash.h>
  23 #include <linux/input.h>
  24 #include <linux/gpio_keys.h>
  25 #include <linux/input/matrix_keypad.h>
  26 #include <linux/mtd/mtd.h>
  27 #include <linux/mtd/nand.h>
  28 #include <linux/mtd/partitions.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/clk.h>
  31 #include <linux/err.h>
  32 #include <linux/wl12xx.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mfd/tps65910.h>
  35
  36 /* LCD controller is similar to DA850 */
  37 #include <video/da8xx-fb.h>
  38
  39 #include <mach/hardware.h>
  40 #include <mach/board-am335xevm.h>
  41
  42 #include <asm/mach-types.h>
  43 #include <asm/mach/arch.h>
  44 #include <asm/mach/map.h>
  45 #include <asm/hardware/asp.h>
  46
  47 #include <plat/irqs.h>
  48 #include <plat/board.h>
  49 #include <plat/common.h>
  50 #include <plat/lcdc.h>
  51 #include <plat/usb.h>
  52 #include <plat/mmc.h>
  53
  54 #include "board-flash.h"
  55 #include "cpuidle33xx.h"
  56 #include "mux.h"
  57 #include "devices.h"
  58 #include "hsmmc.h"
  59
  60 /* TLK PHY IDs */
  61 #define TLK110_PHY_ID           0x2000A201
  62 #define TLK110_PHY_MASK         0xfffffff0
  63
  64 /* BBB PHY IDs */
  65 #define BBB_PHY_ID              0x7c0f1
  66 #define BBB_PHY_MASK            0xfffffffd
  67
  68 /* Convert GPIO signal to GPIO pin number */
  69 #define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
  70
  71 static const struct display_panel disp_panel = {
  72         WVGA,
  73         32,
  74         32,
  75         COLOR_ACTIVE,
  76 };
  77
  78 static struct lcd_ctrl_config lcd_cfg = {
  79         &disp_panel,
  80         .ac_bias                = 255,
  81         .ac_bias_intrpt         = 0,
  82         .dma_burst_sz           = 16,
  83         .bpp                    = 32,
  84         .fdd                    = 0x80,
  85         .tft_alt_mode           = 0,
  86         .stn_565_mode           = 0,
  87         .mono_8bit_mode         = 0,
  88         .invert_line_clock      = 1,
  89         .invert_frm_clock       = 1,
  90         .sync_edge              = 0,
  91         .sync_ctrl              = 1,
  92         .raster_order           = 0,
  93 };
  94
  95 struct da8xx_lcdc_platform_data TFC_S9700RTWV35TR_01B_pdata = {
  96         .manu_name              = "ThreeFive",
  97         .controller_data        = &lcd_cfg,
  98         .type                   = "TFC_S9700RTWV35TR_01B",
  99 };
 100
 101 /* TSc controller */
 102 #include <linux/input/ti_tscadc.h>
 103 #include <linux/lis3lv02d.h>
 104
 105 static struct resource tsc_resources[]  = {
 106         [0] = {
 107                 .start  = AM33XX_TSC_BASE,
 108                 .end    = AM33XX_TSC_BASE + SZ_8K - 1,
 109                 .flags  = IORESOURCE_MEM,
 110         },
 111         [1] = {
 112                 .start  = AM33XX_IRQ_ADC_GEN,
 113                 .end    = AM33XX_IRQ_ADC_GEN,
 114                 .flags  = IORESOURCE_IRQ,
 115         },
 116 };
 117
 118 static struct tsc_data am335x_touchscreen_data  = {
 119         .wires  = 4,
 120         .x_plate_resistance = 200,
 121 };
 122
 123 static struct platform_device tsc_device = {
 124         .name   = "tsc",
 125         .id     = -1,
 126         .dev    = {
 127                         .platform_data  = &am335x_touchscreen_data,
 128         },
 129         .num_resources  = ARRAY_SIZE(tsc_resources),
 130         .resource       = tsc_resources,
 131 };
 132
 133 static u8 am335x_iis_serializer_direction1[] = {
 134         INACTIVE_MODE,  INACTIVE_MODE,  TX_MODE,        RX_MODE,
 135         INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
 136         INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
 137         INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,  INACTIVE_MODE,
 138 };
 139
 140 static struct snd_platform_data am335x_evm_snd_data1 = {
 141         .tx_dma_offset  = 0x46400000,   /* McASP1 */
 142         .rx_dma_offset  = 0x46400000,
 143         .op_mode        = DAVINCI_MCASP_IIS_MODE,
 144         .num_serializer = ARRAY_SIZE(am335x_iis_serializer_direction1),
 145         .tdm_slots      = 2,
 146         .serial_dir     = am335x_iis_serializer_direction1,
 147         .asp_chan_q     = EVENTQ_2,
 148         .version        = MCASP_VERSION_3,
 149         .txnumevt       = 1,
 150         .rxnumevt       = 1,
 151 };
 152
 153 static struct omap2_hsmmc_info am335x_mmc[] __initdata = {
 154         {
 155                 .mmc            = 1,
 156                 .caps           = MMC_CAP_4_BIT_DATA,
 157                 .gpio_cd        = GPIO_TO_PIN(3, 24),
 158                 .gpio_wp        = GPIO_TO_PIN(3, 18),
 159                 .ocr_mask       = MMC_VDD_32_33 | MMC_VDD_33_34, /* 3V3 */
 160         },
 161         {
 162                 .mmc            = 0,    /* will be set at runtime */
 163         },
 164         {
 165                 .mmc            = 0,    /* will be set at runtime */
 166         },
 167         {}      /* Terminator */
 168 };
 169
 170
 171 #ifdef CONFIG_OMAP_MUX
 172 static struct omap_board_mux board_mux[] __initdata = {
 173         AM33XX_MUX(I2C0_SDA, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
 174                         AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
 175         AM33XX_MUX(I2C0_SCL, OMAP_MUX_MODE0 | AM33XX_SLEWCTRL_SLOW |
 176                         AM33XX_INPUT_EN | AM33XX_PIN_OUTPUT),
 177         { .reg_offset = OMAP_MUX_TERMINATOR },
 178 };
 179 #else
 180 #define board_mux       NULL
 181 #endif
 182
 183 /* module pin mux structure */
 184 struct pinmux_config {
 185         const char *string_name; /* signal name format */
 186         int val; /* Options for the mux register value */
 187 };
 188
 189 struct evm_dev_cfg {
 190         void (*device_init)(int evm_id, int profile);
 191
 192 /*
 193 * If the device is required on both baseboard & daughter board (ex i2c),
 194 * specify DEV_ON_BASEBOARD
 195 */
 196 #define DEV_ON_BASEBOARD        0
 197 #define DEV_ON_DGHTR_BRD        1
 198         u32 device_on;
 199
 200         u32 profile;    /* Profiles (0-7) in which the module is present */
 201 };
 202
 203 /* AM335X - CPLD Register Offsets */
 204 #define CPLD_DEVICE_HDR 0x00 /* CPLD Header */
 205 #define CPLD_DEVICE_ID  0x04 /* CPLD identification */
 206 #define CPLD_DEVICE_REV 0x0C /* Revision of the CPLD code */
 207 #define CPLD_CFG_REG    0x10 /* Configuration Register */
 208
 209 static struct i2c_client *cpld_client;
 210
 211 static u32 am335x_evm_id;
 212
 213 static struct omap_board_config_kernel am335x_evm_config[] __initdata = {
 214 };
 215
 216 /*
 217 * EVM Config held in On-Board eeprom device.
 218 *
 219 * Header Format
 220 *
 221 *  Name                 Size    Contents
 222 *                       (Bytes)
 223 *-------------------------------------------------------------
 224 *  Header               4       0xAA, 0x55, 0x33, 0xEE
 225 *
 226 *  Board Name           8       Name for board in ASCII.
 227 *                               example "A33515BB" = "AM335X
 228                                 Low Cost EVM board"
 229 *
 230 *  Version              4       Hardware version code for board in
 231 *                               in ASCII. "1.0A" = rev.01.0A
 232 *
 233 *  Serial Number        12      Serial number of the board. This is a 12
 234 *                               character string which is WWYY4P16nnnn, where
 235 *                               WW = 2 digit week of the year of production
 236 *                               YY = 2 digit year of production
 237 *                               nnnn = incrementing board number
 238 *
 239 *  Configuration option 32      Codes(TBD) to show the configuration
 240 *                               setup on this board.
 241 *
 242 *  Available            32720   Available space for other non-volatile
 243 *                               data.
 244 */
 245 struct am335x_evm_eeprom_config {
 246         u32     header;
 247         u8      name[8];
 248         char    version[4];
 249         u8      serial[12];
 250         u8      opt[32];
 251 };
 252
 253 static struct am335x_evm_eeprom_config config;
 254 static bool daughter_brd_detected;
 255
 256 #define GP_EVM_REV_IS_1_0               0x1
 257 #define GP_EVM_REV_IS_1_1A              0x2
 258 #define GP_EVM_REV_IS_UNKNOWN           0xFF
 259 static unsigned int gp_evm_revision = GP_EVM_REV_IS_UNKNOWN;
 260 unsigned int gigabit_enable = 0;
 261
 262 #define EEPROM_MAC_ADDRESS_OFFSET       60 /* 4+8+4+12+32 */
 263 #define EEPROM_NO_OF_MAC_ADDR           3
 264 static char am335x_mac_addr[EEPROM_NO_OF_MAC_ADDR][ETH_ALEN];
 265
 266 #define AM335X_EEPROM_HEADER            0xEE3355AA
 267
 268 /* current profile if exists else PROFILE_0 on error */
 269 static u32 am335x_get_profile_selection(void)
 270 {
 271         int val = 0;
 272
 273         if (!cpld_client)
 274                 /* error checking is not done in func's calling this routine.
 275                 so return profile 0 on error */
 276                 return 0;
 277
 278         val = i2c_smbus_read_word_data(cpld_client, CPLD_CFG_REG);
 279         if (val < 0)
 280                 return 0;       /* default to Profile 0 on Error */
 281         else
 282                 return val & 0x7;
 283 }
 284
 285 /* Module pin mux for LCDC */
 286 static struct pinmux_config lcdc_pin_mux[] = {
 287         {"lcd_data0.lcd_data0",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 288                                                        | AM33XX_PULL_DISA},
 289         {"lcd_data1.lcd_data1",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 290                                                        | AM33XX_PULL_DISA},
 291         {"lcd_data2.lcd_data2",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 292                                                        | AM33XX_PULL_DISA},
 293         {"lcd_data3.lcd_data3",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 294                                                        | AM33XX_PULL_DISA},
 295         {"lcd_data4.lcd_data4",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 296                                                        | AM33XX_PULL_DISA},
 297         {"lcd_data5.lcd_data5",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 298                                                        | AM33XX_PULL_DISA},
 299         {"lcd_data6.lcd_data6",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 300                                                        | AM33XX_PULL_DISA},
 301         {"lcd_data7.lcd_data7",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 302                                                        | AM33XX_PULL_DISA},
 303         {"lcd_data8.lcd_data8",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 304                                                        | AM33XX_PULL_DISA},
 305         {"lcd_data9.lcd_data9",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 306                                                        | AM33XX_PULL_DISA},
 307         {"lcd_data10.lcd_data10",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 308                                                        | AM33XX_PULL_DISA},
 309         {"lcd_data11.lcd_data11",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 310                                                        | AM33XX_PULL_DISA},
 311         {"lcd_data12.lcd_data12",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 312                                                        | AM33XX_PULL_DISA},
 313         {"lcd_data13.lcd_data13",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 314                                                        | AM33XX_PULL_DISA},
 315         {"lcd_data14.lcd_data14",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 316                                                        | AM33XX_PULL_DISA},
 317         {"lcd_data15.lcd_data15",       OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT
 318                                                        | AM33XX_PULL_DISA},
 319         {"gpmc_ad8.lcd_data16",         OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 320         {"gpmc_ad9.lcd_data17",         OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 321         {"gpmc_ad10.lcd_data18",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 322         {"gpmc_ad11.lcd_data19",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 323         {"gpmc_ad12.lcd_data20",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 324         {"gpmc_ad13.lcd_data21",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 325         {"gpmc_ad14.lcd_data22",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 326         {"gpmc_ad15.lcd_data23",        OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 327         {"lcd_vsync.lcd_vsync",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 328         {"lcd_hsync.lcd_hsync",         OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 329         {"lcd_pclk.lcd_pclk",           OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 330         {"lcd_ac_bias_en.lcd_ac_bias_en", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 331         {NULL, 0},
 332 };
 333
 334 static struct pinmux_config tsc_pin_mux[] = {
 335         {"ain0.ain0",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
 336         {"ain1.ain1",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
 337         {"ain2.ain2",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
 338         {"ain3.ain3",           OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
 339         {"vrefp.vrefp",         OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
 340         {"vrefn.vrefn",         OMAP_MUX_MODE0 | AM33XX_INPUT_EN},
 341         {NULL, 0},
 342 };
 343
 344 /* Pin mux for nand flash module */
 345 static struct pinmux_config nand_pin_mux[] = {
 346         {"gpmc_ad0.gpmc_ad0",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 347         {"gpmc_ad1.gpmc_ad1",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 348         {"gpmc_ad2.gpmc_ad2",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 349         {"gpmc_ad3.gpmc_ad3",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 350         {"gpmc_ad4.gpmc_ad4",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 351         {"gpmc_ad5.gpmc_ad5",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 352         {"gpmc_ad6.gpmc_ad6",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 353         {"gpmc_ad7.gpmc_ad7",     OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 354         {"gpmc_wait0.gpmc_wait0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 355         {"gpmc_wpn.gpmc_wpn",     OMAP_MUX_MODE7 | AM33XX_PIN_INPUT_PULLUP},
 356         {"gpmc_csn0.gpmc_csn0",   OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
 357         {"gpmc_advn_ale.gpmc_advn_ale",  OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
 358         {"gpmc_oen_ren.gpmc_oen_ren",    OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
 359         {"gpmc_wen.gpmc_wen",     OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
 360         {"gpmc_ben0_cle.gpmc_ben0_cle",  OMAP_MUX_MODE0 | AM33XX_PULL_DISA},
 361         {NULL, 0},
 362 };
 363
 364 /* Module pin mux for SPI fash */
 365 static struct pinmux_config spi0_pin_mux[] = {
 366         {"spi0_sclk.spi0_sclk", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
 367                                                         | AM33XX_INPUT_EN},
 368         {"spi0_d0.spi0_d0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
 369                                                         | AM33XX_INPUT_EN},
 370         {"spi0_d1.spi0_d1", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL
 371                                                         | AM33XX_INPUT_EN},
 372         {"spi0_cs0.spi0_cs0", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL | AM33XX_PULL_UP
 373                                                         | AM33XX_INPUT_EN},
 374         {NULL, 0},
 375 };
 376
 377 /* Module pin mux for SPI flash */
 378 static struct pinmux_config spi1_pin_mux[] = {
 379         {"mcasp0_aclkx.spi1_sclk", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
 380                 | AM33XX_INPUT_EN},
 381         {"mcasp0_fsx.spi1_d0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
 382                 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
 383         {"mcasp0_axr0.spi1_d1", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
 384                 | AM33XX_INPUT_EN},
 385         {"mcasp0_ahclkr.spi1_cs0", OMAP_MUX_MODE3 | AM33XX_PULL_ENBL
 386                 | AM33XX_PULL_UP | AM33XX_INPUT_EN},
 387         {NULL, 0},
 388 };
 389
 390 /* Module pin mux for rgmii1 */
 391 static struct pinmux_config rgmii1_pin_mux[] = {
 392         {"mii1_txen.rgmii1_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 393         {"mii1_rxdv.rgmii1_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 394         {"mii1_txd3.rgmii1_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 395         {"mii1_txd2.rgmii1_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 396         {"mii1_txd1.rgmii1_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 397         {"mii1_txd0.rgmii1_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 398         {"mii1_txclk.rgmii1_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 399         {"mii1_rxclk.rgmii1_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 400         {"mii1_rxd3.rgmii1_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 401         {"mii1_rxd2.rgmii1_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 402         {"mii1_rxd1.rgmii1_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 403         {"mii1_rxd0.rgmii1_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 404         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 405         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
 406         {NULL, 0},
 407 };
 408
 409 /* Module pin mux for rgmii2 */
 410 static struct pinmux_config rgmii2_pin_mux[] = {
 411         {"gpmc_a0.rgmii2_tctl", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 412         {"gpmc_a1.rgmii2_rctl", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 413         {"gpmc_a2.rgmii2_td3", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 414         {"gpmc_a3.rgmii2_td2", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 415         {"gpmc_a4.rgmii2_td1", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 416         {"gpmc_a5.rgmii2_td0", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 417         {"gpmc_a6.rgmii2_tclk", OMAP_MUX_MODE2 | AM33XX_PIN_OUTPUT},
 418         {"gpmc_a7.rgmii2_rclk", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 419         {"gpmc_a8.rgmii2_rd3", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 420         {"gpmc_a9.rgmii2_rd2", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 421         {"gpmc_a10.rgmii2_rd1", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 422         {"gpmc_a11.rgmii2_rd0", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLDOWN},
 423         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 424         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
 425         {NULL, 0},
 426 };
 427
 428 /* Module pin mux for mii1 */
 429 static struct pinmux_config mii1_pin_mux[] = {
 430         {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 431         {"mii1_txen.mii1_txen", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 432         {"mii1_rxdv.mii1_rxdv", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 433         {"mii1_txd3.mii1_txd3", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 434         {"mii1_txd2.mii1_txd2", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 435         {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 436         {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 437         {"mii1_txclk.mii1_txclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 438         {"mii1_rxclk.mii1_rxclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 439         {"mii1_rxd3.mii1_rxd3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 440         {"mii1_rxd2.mii1_rxd2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 441         {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 442         {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLDOWN},
 443         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 444         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
 445         {NULL, 0},
 446 };
 447
 448 /* Module pin mux for rmii1 */
 449 static struct pinmux_config rmii1_pin_mux[] = {
 450         {"mii1_crs.rmii1_crs_dv", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
 451         {"mii1_rxerr.mii1_rxerr", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
 452         {"mii1_txen.mii1_txen", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 453         {"mii1_txd1.mii1_txd1", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 454         {"mii1_txd0.mii1_txd0", OMAP_MUX_MODE1 | AM33XX_PIN_OUTPUT},
 455         {"mii1_rxd1.mii1_rxd1", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
 456         {"mii1_rxd0.mii1_rxd0", OMAP_MUX_MODE1 | AM33XX_PIN_INPUT_PULLDOWN},
 457         {"rmii1_refclk.rmii1_refclk", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
 458         {"mdio_data.mdio_data", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 459         {"mdio_clk.mdio_clk", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT_PULLUP},
 460         {NULL, 0},
 461 };
 462
 463 static struct pinmux_config i2c1_pin_mux[] = {
 464         {"spi0_d1.i2c1_sda",    OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
 465                                         AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
 466         {"spi0_cs0.i2c1_scl",   OMAP_MUX_MODE2 | AM33XX_SLEWCTRL_SLOW |
 467                                         AM33XX_PULL_ENBL | AM33XX_INPUT_EN},
 468         {NULL, 0},
 469 };
 470
 471 /* Module pin mux for mcasp1 */
 472 static struct pinmux_config mcasp1_pin_mux[] = {
 473         {"mii1_crs.mcasp1_aclkx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
 474         {"mii1_rxerr.mcasp1_fsx", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
 475         {"mii1_col.mcasp1_axr2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
 476         {"rmii1_refclk.mcasp1_axr3", OMAP_MUX_MODE4 |
 477                                                 AM33XX_PIN_INPUT_PULLDOWN},
 478         {NULL, 0},
 479 };
 480
 481
 482 /* Module pin mux for mmc0 */
 483 static struct pinmux_config mmc0_pin_mux[] = {
 484         {"mii1_rxd2.mmc1_dat3", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLUP},
 485         {"mii1_rxd3.mmc1_dat2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLUP},
 486         {"mii1_rxclk.mmc1_dat1",        OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLUP},
 487         {"mii1_txclk.mmc1_dat0",        OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLUP},
 488         {"gpmc_csn1.mmc1_clk",  OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
 489         {"gpmc_csn2.mmc1_cmd",  OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
 490         {"mcasp0_fsx.mmc1_sdcd", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLUP},
 491         {NULL, 0},
 492 };
 493
 494 static struct pinmux_config mmc0_no_cd_pin_mux[] = {
 495         {"mmc0_dat3.mmc0_dat3", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 496         {"mmc0_dat2.mmc0_dat2", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 497         {"mmc0_dat1.mmc0_dat1", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 498         {"mmc0_dat0.mmc0_dat0", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 499         {"mmc0_clk.mmc0_clk",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 500         {"mmc0_cmd.mmc0_cmd",   OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 501         {"mcasp0_aclkr.mmc0_sdwp", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLDOWN},
 502         {NULL, 0},
 503 };
 504
 505 /* Module pin mux for mmc1 */
 506 static struct pinmux_config mmc1_pin_mux[] = {
 507         {"mii1_rxd2.mmc1_dat3", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLUP},
 508         {"mii1_rxd3.mmc1_dat2", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLUP},
 509         {"mii1_rxclk.mmc1_dat1",        OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLUP},
 510         {"mii1_txclk.mmc1_dat0",        OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLUP},
 511         {"gpmc_csn1.mmc1_clk",  OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
 512         {"gpmc_csn2.mmc1_cmd",  OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
 513         {"mcasp0_fsx.mmc1_sdcd", OMAP_MUX_MODE4 | AM33XX_PIN_INPUT_PULLUP},
 514         {NULL, 0},
 515 };
 516
 517 /* Module pin mux for uart3 */
 518 static struct pinmux_config uart3_pin_mux[] = {
 519         {"spi0_cs1.uart3_rxd", AM33XX_PIN_INPUT_PULLUP},
 520         {"ecap0_in_pwm0_out.uart3_txd", AM33XX_PULL_ENBL},
 521         {NULL, 0},
 522 };
 523
 524 static struct pinmux_config d_can_gp_pin_mux[] = {
 525         {"uart0_ctsn.d_can1_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
 526         {"uart0_rtsn.d_can1_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
 527         {NULL, 0},
 528 };
 529
 530 static struct pinmux_config d_can_ia_pin_mux[] = {
 531         {"uart0_rxd.d_can0_tx", OMAP_MUX_MODE2 | AM33XX_PULL_ENBL},
 532         {"uart0_txd.d_can0_rx", OMAP_MUX_MODE2 | AM33XX_PIN_INPUT_PULLUP},
 533         {NULL, 0},
 534 };
 535
 536 /*
 537 * @pin_mux - single module pin-mux structure which defines pin-mux
 538 *                       details for all its pins.
 539 */
 540 static void setup_pin_mux(struct pinmux_config *pin_mux)
 541 {
 542         int i;
 543
 544         for (i = 0; pin_mux->string_name != NULL; pin_mux++)
 545                 omap_mux_init_signal(pin_mux->string_name, pin_mux->val);
 546
 547 }
 548
 549 /*
 550 * @evm_id - evm id which needs to be configured
 551 * @dev_cfg - single evm structure which includes
 552 *                               all module inits, pin-mux defines
 553 * @profile - if present, else PROFILE_NONE
 554 * @dghtr_brd_flg - Whether Daughter board is present or not
 555 */
 556 static void _configure_device(int evm_id, struct evm_dev_cfg *dev_cfg,
 557         int profile)
 558 {
 559         int i;
 560
 561         /*
 562         * Only General Purpose & Industrial Auto Motro Control
 563         * EVM has profiles. So check if this evm has profile.
 564         * If not, ignore the profile comparison
 565         */
 566
 567         /*
 568         * If the device is on baseboard, directly configure it. Else (device on
 569         * Daughter board), check if the daughter card is detected.
 570         */
 571         if (profile == PROFILE_NONE) {
 572                 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
 573                         if (dev_cfg->device_on == DEV_ON_BASEBOARD)
 574                                 dev_cfg->device_init(evm_id, profile);
 575                         else if (daughter_brd_detected == true)
 576                                 dev_cfg->device_init(evm_id, profile);
 577                 }
 578         } else {
 579                 for (i = 0; dev_cfg->device_init != NULL; dev_cfg++) {
 580                         if (dev_cfg->profile & profile) {
 581                                 if (dev_cfg->device_on == DEV_ON_BASEBOARD)
 582                                         dev_cfg->device_init(evm_id, profile);
 583                                 else if (daughter_brd_detected == true)
 584                                         dev_cfg->device_init(evm_id, profile);
 585                         }
 586                 }
 587         }
 588 }
 589
 590 #define AM335X_LCD_BL_PIN       GPIO_TO_PIN(3, 14)
 591
 592 /* pinmux for usb0 drvvbus */
 593 static struct pinmux_config usb0_pin_mux[] = {
 594         {NULL, 0},
 595 };
 596
 597 /* pinmux for usb1 drvvbus */
 598 static struct pinmux_config usb1_pin_mux[] = {
 599         {"usb1_drvvbus.usb1_drvvbus",    OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 600         {NULL, 0},
 601 };
 602
 603 /* pinmux for profibus */
 604 static struct pinmux_config profibus_pin_mux[] = {
 605         {"uart1_rxd.pr1_uart0_rxd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_INPUT},
 606         {"uart1_txd.pr1_uart0_txd_mux1", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
 607         {"mcasp0_fsr.pr1_pru0_pru_r30_5", OMAP_MUX_MODE5 | AM33XX_PIN_OUTPUT},
 608         {NULL, 0},
 609 };
 610
 611 /* Module pin mux for eCAP0 */
 612 static struct pinmux_config ecap0_pin_mux[] = {
 613         {"mcasp0_aclkx.gpio3_14", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
 614         {NULL, 0},
 615 };
 616
 617 #define AM335XEVM_WLAN_IRQ_GPIO         GPIO_TO_PIN(3, 17)
 618
 619 struct wl12xx_platform_data am335xevm_wlan_data = {
 620         .irq = OMAP_GPIO_IRQ(AM335XEVM_WLAN_IRQ_GPIO),
 621         .board_ref_clock = WL12XX_REFCLOCK_38_XTAL, /* 38.4Mhz */
 622 };
 623
 624 /* Module pin mux for wlan and bluetooth */
 625 static struct pinmux_config mmc2_wl12xx_pin_mux[] = {
 626         {"gpmc_a1.mmc2_dat0", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
 627         {"gpmc_a2.mmc2_dat1", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
 628         {"gpmc_a3.mmc2_dat2", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
 629         {"gpmc_ben1.mmc2_dat3", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
 630         {"gpmc_csn3.mmc2_cmd", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
 631         {"gpmc_clk.mmc2_clk", OMAP_MUX_MODE3 | AM33XX_PIN_INPUT_PULLUP},
 632         {NULL, 0},
 633 };
 634
 635 static struct pinmux_config uart1_wl12xx_pin_mux[] = {
 636         {"uart1_ctsn.uart1_ctsn", OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT},
 637         {"uart1_rtsn.uart1_rtsn", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT},
 638         {"uart1_rxd.uart1_rxd", OMAP_MUX_MODE0 | AM33XX_PIN_INPUT_PULLUP},
 639         {"uart1_txd.uart1_txd", OMAP_MUX_MODE0 | AM33XX_PULL_ENBL},
 640         {NULL, 0},
 641 };
 642
 643 static struct pinmux_config wl12xx_pin_mux_evm_rev1_1a[] = {
 644         {"gpmc_a0.gpio1_16", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
 645         {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
 646         {"mcasp0_ahclkx.gpio3_21", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
 647         {NULL, 0},
 648  };
 649
 650 static struct pinmux_config wl12xx_pin_mux_evm_rev1_0[] = {
 651         {"gpmc_csn1.gpio1_30", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
 652         {"mcasp0_ahclkr.gpio3_17", OMAP_MUX_MODE7 | AM33XX_PIN_INPUT},
 653         {"gpmc_csn2.gpio1_31", OMAP_MUX_MODE7 | AM33XX_PIN_OUTPUT},
 654         {NULL, 0},
 655  };
 656
 657 static int backlight_enable = false;
 658
 659 static void enable_ecap0(int evm_id, int profile)
 660 {
 661         backlight_enable = true;
 662 }
 663
 664 static int __init ecap0_init(void)
 665 {
 666         int status = 0;
 667
 668         if (backlight_enable) {
 669                 setup_pin_mux(ecap0_pin_mux);
 670
 671                 status = gpio_request(AM335X_LCD_BL_PIN, "lcd bl\n");
 672                 if (status < 0)
 673                         pr_warn("Failed to request gpio for LCD backlight\n");
 674
 675                 gpio_direction_output(AM335X_LCD_BL_PIN, 1);
 676                 gpio_set_value(AM335X_LCD_BL_PIN, 0);
 677         }
 678         return status;
 679 }
 680 late_initcall(ecap0_init);
 681
 682 static int __init conf_disp_pll(int rate)
 683 {
 684         struct clk *disp_pll;
 685         int ret = -EINVAL;
 686
 687         disp_pll = clk_get(NULL, "dpll_disp_ck");
 688         if (IS_ERR(disp_pll)) {
 689                 pr_err("Cannot clk_get disp_pll\n");
 690                 goto out;
 691         }
 692
 693         ret = clk_set_rate(disp_pll, rate);
 694         clk_put(disp_pll);
 695 out:
 696         return ret;
 697 }
 698
 699 static void lcdc_init(int evm_id, int profile)
 700 {
 701
 702         setup_pin_mux(lcdc_pin_mux);
 703
 704         if (conf_disp_pll(300000000)) {
 705                 pr_info("Failed configure display PLL, not attempting to"
 706                                 "register LCDC\n");
 707                 return;
 708         }
 709
 710         if (am33xx_register_lcdc(&TFC_S9700RTWV35TR_01B_pdata))
 711                 pr_info("Failed to register LCDC device\n");
 712         return;
 713 }
 714
 715 static void tsc_init(int evm_id, int profile)
 716 {
 717         int err;
 718
 719         if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
 720                 am335x_touchscreen_data.analog_input = 1;
 721                 pr_info("TSC connected to beta GP EVM\n");
 722         } else {
 723                 am335x_touchscreen_data.analog_input = 0;
 724                 pr_info("TSC connected to alpha GP EVM\n");
 725         }
 726         setup_pin_mux(tsc_pin_mux);
 727         err = platform_device_register(&tsc_device);
 728         if (err)
 729                 pr_err("failed to register touchscreen device\n");
 730 }
 731
 732 static void rgmii1_init(int evm_id, int profile)
 733 {
 734         setup_pin_mux(rgmii1_pin_mux);
 735         return;
 736 }
 737
 738 static void rgmii2_init(int evm_id, int profile)
 739 {
 740         setup_pin_mux(rgmii2_pin_mux);
 741         return;
 742 }
 743
 744 static void mii1_init(int evm_id, int profile)
 745 {
 746         setup_pin_mux(mii1_pin_mux);
 747         return;
 748 }
 749
 750 static void rmii1_init(int evm_id, int profile)
 751 {
 752         setup_pin_mux(rmii1_pin_mux);
 753         return;
 754 }
 755
 756 static void usb0_init(int evm_id, int profile)
 757 {
 758         setup_pin_mux(usb0_pin_mux);
 759         return;
 760 }
 761
 762 static void usb1_init(int evm_id, int profile)
 763 {
 764         setup_pin_mux(usb1_pin_mux);
 765         return;
 766 }
 767
 768 /* setup uart3 */
 769 static void uart3_init(int evm_id, int profile)
 770 {
 771         setup_pin_mux(uart3_pin_mux);
 772         return;
 773 }
 774
 775 /* NAND partition information */
 776 static struct mtd_partition am335x_nand_partitions[] = {
 777 /* All the partition sizes are listed in terms of NAND block size */
 778         {
 779                 .name           = "SPL",
 780                 .offset         = 0,                    /* Offset = 0x0 */
 781                 .size           = SZ_128K,
 782         },
 783         {
 784                 .name           = "SPL.backup1",
 785                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x20000 */
 786                 .size           = SZ_128K,
 787         },
 788         {
 789                 .name           = "SPL.backup2",
 790                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x40000 */
 791                 .size           = SZ_128K,
 792         },
 793         {
 794                 .name           = "SPL.backup3",
 795                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x60000 */
 796                 .size           = SZ_128K,
 797         },
 798         {
 799                 .name           = "U-Boot",
 800                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x80000 */
 801                 .size           = 15 * SZ_128K,
 802         },
 803         {
 804                 .name           = "U-Boot Env",
 805                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x260000 */
 806                 .size           = 1 * SZ_128K,
 807         },
 808         {
 809                 .name           = "Kernel",
 810                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x280000 */
 811                 .size           = 40 * SZ_128K,
 812         },
 813         {
 814                 .name           = "File System",
 815                 .offset         = MTDPART_OFS_APPEND,   /* Offset = 0x780000 */
 816                 .size           = MTDPART_SIZ_FULL,
 817         },
 818 };
 819
 820 /* SPI 0/1 Platform Data */
 821 /* SPI flash information */
 822 static struct mtd_partition am335x_spi_partitions[] = {
 823         /* All the partition sizes are listed in terms of erase size */
 824         {
 825                 .name       = "U-Boot-min",
 826                 .offset     = 0,
 827                 .size       = SZ_128K,
 828                 .mask_flags = MTD_WRITEABLE,    /* force read-only */
 829         },
 830         {
 831                 .name       = "U-Boot",
 832                 .offset     = MTDPART_OFS_APPEND,
 833                 .size       = 2 * SZ_128K,
 834                 .mask_flags = MTD_WRITEABLE,    /* force read-only */
 835         },
 836         {
 837                 .name       = "U-Boot Env",
 838                 .offset     = MTDPART_OFS_APPEND,
 839                 .size       = 2 * SZ_4K,
 840         },
 841         {
 842                 .name       = "Kernel",
 843                 .offset     = MTDPART_OFS_APPEND,
 844                 .size       = 28 * SZ_128K,
 845         },
 846         {
 847                 .name       = "File System",
 848                 .offset     = MTDPART_OFS_APPEND,
 849                 .size       = MTDPART_SIZ_FULL,     /* size ~= 1.1 MiB */
 850         }
 851 };
 852
 853 static const struct flash_platform_data am335x_spi_flash = {
 854         .type      = "w25q64",
 855         .name      = "spi_flash",
 856         .parts     = am335x_spi_partitions,
 857         .nr_parts  = ARRAY_SIZE(am335x_spi_partitions),
 858 };
 859
 860 /*
 861  * SPI Flash works at 80Mhz however SPI Controller works at 48MHz.
 862  * So setup Max speed to be less than that of Controller speed
 863  */
 864 static struct spi_board_info am335x_spi0_slave_info[] = {
 865         {
 866                 .modalias      = "m25p80",
 867                 .platform_data = &am335x_spi_flash,
 868                 .irq           = -1,
 869                 .max_speed_hz  = 24000000,
 870                 .bus_num       = 1,
 871                 .chip_select   = 0,
 872         },
 873 };
 874
 875 static struct spi_board_info am335x_spi1_slave_info[] = {
 876         {
 877                 .modalias      = "m25p80",
 878                 .platform_data = &am335x_spi_flash,
 879                 .irq           = -1,
 880                 .max_speed_hz  = 12000000,
 881                 .bus_num       = 2,
 882                 .chip_select   = 0,
 883         },
 884 };
 885
 886 static void evm_nand_init(int evm_id, int profile)
 887 {
 888         setup_pin_mux(nand_pin_mux);
 889         board_nand_init(am335x_nand_partitions,
 890                 ARRAY_SIZE(am335x_nand_partitions), 0, 0);
 891 }
 892
 893 static struct lis3lv02d_platform_data lis331dlh_pdata = {
 894         .click_flags = LIS3_CLICK_SINGLE_X |
 895                         LIS3_CLICK_SINGLE_Y |
 896                         LIS3_CLICK_SINGLE_Z,
 897         .wakeup_flags = LIS3_WAKEUP_X_LO | LIS3_WAKEUP_X_HI |
 898                         LIS3_WAKEUP_Y_LO | LIS3_WAKEUP_Y_HI |
 899                         LIS3_WAKEUP_Z_LO | LIS3_WAKEUP_Z_HI,
 900         .irq_cfg = LIS3_IRQ1_CLICK | LIS3_IRQ2_CLICK,
 901         .wakeup_thresh  = 10,
 902         .click_thresh_x = 10,
 903         .click_thresh_y = 10,
 904         .click_thresh_z = 10,
 905         .g_range        = 2,
 906         .st_min_limits[0] = 120,
 907         .st_min_limits[1] = 120,
 908         .st_min_limits[2] = 140,
 909         .st_max_limits[0] = 550,
 910         .st_max_limits[1] = 550,
 911         .st_max_limits[2] = 750,
 912 };
 913
 914 static struct i2c_board_info am335x_i2c_boardinfo1[] = {
 915         {
 916                 I2C_BOARD_INFO("tlv320aic3x", 0x1b),
 917         },
 918         {
 919                 I2C_BOARD_INFO("lis331dlh", 0x18),
 920                 .platform_data = &lis331dlh_pdata,
 921         },
 922         {
 923                 I2C_BOARD_INFO("tsl2550", 0x39),
 924         },
 925         {
 926                 I2C_BOARD_INFO("tmp275", 0x48),
 927         },
 928 };
 929
 930 static void i2c1_init(int evm_id, int profile)
 931 {
 932         setup_pin_mux(i2c1_pin_mux);
 933         omap_register_i2c_bus(2, 100, am335x_i2c_boardinfo1,
 934                         ARRAY_SIZE(am335x_i2c_boardinfo1));
 935         return;
 936 }
 937
 938 /* Setup McASP 1 */
 939 static void mcasp1_init(int evm_id, int profile)
 940 {
 941         /* Configure McASP */
 942         setup_pin_mux(mcasp1_pin_mux);
 943         am335x_register_mcasp1(&am335x_evm_snd_data1);
 944         return;
 945 }
 946
 947 static void mmc1_init(int evm_id, int profile)
 948 {
 949         setup_pin_mux(mmc1_pin_mux);
 950
 951         pr_info("mmc1_init\n");
 952
 953         am335x_mmc[1].mmc = 2;
 954         am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA;
 955         am335x_mmc[1].gpio_cd = GPIO_TO_PIN(3, 15);
 956         am335x_mmc[1].gpio_wp = -EINVAL;
 957         am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
 958
 959         /* mmc will be initialized when mmc0_init is called */
 960         return;
 961 }
 962
 963 static void mmc2_wl12xx_init(int evm_id, int profile)
 964 {
 965         setup_pin_mux(mmc2_wl12xx_pin_mux);
 966
 967         am335x_mmc[1].mmc = 3;
 968         am335x_mmc[1].name = "wl1271";
 969         am335x_mmc[1].caps = MMC_CAP_4_BIT_DATA | MMC_CAP_POWER_OFF_CARD
 970                                 | MMC_PM_KEEP_POWER;
 971         am335x_mmc[1].nonremovable = true;
 972         am335x_mmc[1].gpio_cd = -EINVAL;
 973         am335x_mmc[1].gpio_wp = -EINVAL;
 974         am335x_mmc[1].ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34; /* 3V3 */
 975
 976         /* mmc will be initialized when mmc0_init is called */
 977         return;
 978 }
 979
 980 static void uart1_wl12xx_init(int evm_id, int profile)
 981 {
 982         setup_pin_mux(uart1_wl12xx_pin_mux);
 983 }
 984
 985 static void wl12xx_bluetooth_enable(void)
 986 {
 987         int status = gpio_request(am335xevm_wlan_data.bt_enable_gpio,
 988                 "bt_en\n");
 989         if (status < 0)
 990                 pr_err("Failed to request gpio for bt_enable");
 991
 992         pr_info("Configure Bluetooth Enable pin...\n");
 993         gpio_direction_output(am335xevm_wlan_data.bt_enable_gpio, 0);
 994 }
 995
 996 static int wl12xx_set_power(struct device *dev, int slot, int on, int vdd)
 997 {
 998         if (on) {
 999                 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 1);
1000                 mdelay(70);
1001         }
1002         else
1003                 gpio_set_value(am335xevm_wlan_data.wlan_enable_gpio, 0);
1004
1005         return 0;
1006 }
1007
1008 static void wl12xx_init(int evm_id, int profile)
1009 {
1010         struct device *dev;
1011         struct omap_mmc_platform_data *pdata;
1012         int ret;
1013
1014         /* Register WLAN and BT enable pins based on the evm board revision */
1015         if (gp_evm_revision == GP_EVM_REV_IS_1_1A) {
1016                 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 16);
1017                 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(3, 21);
1018         }
1019         else {
1020                 am335xevm_wlan_data.wlan_enable_gpio = GPIO_TO_PIN(1, 30);
1021                 am335xevm_wlan_data.bt_enable_gpio = GPIO_TO_PIN(1, 31);
1022         }
1023
1024         wl12xx_bluetooth_enable();
1025
1026         if (wl12xx_set_platform_data(&am335xevm_wlan_data))
1027                 pr_err("error setting wl12xx data\n");
1028
1029         dev = am335x_mmc[1].dev;
1030         if (!dev) {
1031                 pr_err("wl12xx mmc device initialization failed\n");
1032                 goto out;
1033         }
1034
1035         pdata = dev->platform_data;
1036         if (!pdata) {
1037                 pr_err("Platfrom data of wl12xx device not set\n");
1038                 goto out;
1039         }
1040
1041         ret = gpio_request_one(am335xevm_wlan_data.wlan_enable_gpio,
1042                 GPIOF_OUT_INIT_LOW, "wlan_en");
1043         if (ret) {
1044                 pr_err("Error requesting wlan enable gpio: %d\n", ret);
1045                 goto out;
1046         }
1047
1048         if (gp_evm_revision == GP_EVM_REV_IS_1_1A)
1049                 setup_pin_mux(wl12xx_pin_mux_evm_rev1_1a);
1050         else
1051                 setup_pin_mux(wl12xx_pin_mux_evm_rev1_0);
1052
1053         pdata->slots[0].set_power = wl12xx_set_power;
1054 out:
1055         return;
1056 }
1057
1058 static void d_can_init(int evm_id, int profile)
1059 {
1060         switch (evm_id) {
1061         case IND_AUT_MTR_EVM:
1062                 if ((profile == PROFILE_0) || (profile == PROFILE_1)) {
1063                         setup_pin_mux(d_can_ia_pin_mux);
1064                         /* Instance Zero */
1065                         am33xx_d_can_init(0);
1066                 }
1067                 break;
1068         case GEN_PURP_EVM:
1069                 if (profile == PROFILE_1) {
1070                         setup_pin_mux(d_can_gp_pin_mux);
1071                         /* Instance One */
1072                         am33xx_d_can_init(1);
1073                 }
1074                 break;
1075         default:
1076                 break;
1077         }
1078 }
1079
1080 static void mmc0_init(int evm_id, int profile)
1081 {
1082         setup_pin_mux(mmc0_pin_mux);
1083
1084         omap2_hsmmc_init(am335x_mmc);
1085         return;
1086 }
1087
1088 static void mmc0_no_cd_init(int evm_id, int profile)
1089 {
1090         setup_pin_mux(mmc0_no_cd_pin_mux);
1091
1092         omap2_hsmmc_init(am335x_mmc);
1093         return;
1094 }
1095
1096
1097 /* setup spi0 */
1098 static void spi0_init(int evm_id, int profile)
1099 {
1100         setup_pin_mux(spi0_pin_mux);
1101         spi_register_board_info(am335x_spi0_slave_info,
1102                         ARRAY_SIZE(am335x_spi0_slave_info));
1103         return;
1104 }
1105
1106 /* setup spi1 */
1107 static void spi1_init(int evm_id, int profile)
1108 {
1109         setup_pin_mux(spi1_pin_mux);
1110         spi_register_board_info(am335x_spi1_slave_info,
1111                         ARRAY_SIZE(am335x_spi1_slave_info));
1112         return;
1113 }
1114
1115
1116 static int beaglebone_phy_fixup(struct phy_device *phydev)
1117 {
1118         phydev->supported &= ~(SUPPORTED_100baseT_Half |
1119                                 SUPPORTED_100baseT_Full);
1120
1121         return 0;
1122 }
1123
1124
1125 /* General Purpose EVM */
1126 static struct evm_dev_cfg gen_purp_evm_dev_cfg[] = {
1127         {enable_ecap0,  DEV_ON_BASEBOARD, PROFILE_ALL},
1128         {lcdc_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1129         {tsc_init,      DEV_ON_BASEBOARD, PROFILE_ALL},
1130         {rmii1_init,    DEV_ON_BASEBOARD, PROFILE_ALL},
1131         {usb0_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1132         {usb1_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1133         {evm_nand_init, DEV_ON_BASEBOARD, PROFILE_ALL},
1134         {mmc1_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1135         {mmc0_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1136         {spi0_init,     DEV_ON_BASEBOARD, PROFILE_ALL},
1137         {d_can_init,    DEV_ON_BASEBOARD, PROFILE_ALL},
1138         {NULL, 0, 0},
1139 };
1140
1141 static void setup_general_purpose_evm(void)
1142 {
1143         u32 prof_sel = am335x_get_profile_selection();
1144         pr_info("The board is general purpose EVM in profile %d\n", prof_sel);
1145
1146         if (!strncmp("1.1A", config.version, 4)) {
1147                 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1148         } else if (!strncmp("1.0", config.version, 3)) {
1149                 gp_evm_revision = GP_EVM_REV_IS_1_0;
1150         } else {
1151                 pr_err("Found invalid GP EVM revision, falling back to Rev1.1A");
1152                 gp_evm_revision = GP_EVM_REV_IS_1_1A;
1153         }
1154
1155         _configure_device(GEN_PURP_EVM, gen_purp_evm_dev_cfg, (1L << prof_sel));
1156 }
1157
1158
1159 static void am335x_setup_daughter_board(struct memory_accessor *m, void *c)
1160 {
1161         u8 tmp;
1162         int ret;
1163
1164         /*
1165          * try reading a byte from the EEPROM to see if it is
1166          * present. We could read a lot more, but that would
1167          * just slow the boot process and we have all the information
1168          * we need from the EEPROM on the base board anyway.
1169          */
1170         ret = m->read(m, &tmp, 0, sizeof(u8));
1171         if (ret == sizeof(u8)) {
1172                 pr_info("Detected a daughter card on AM335x EVM..");
1173                 daughter_brd_detected = true;
1174         } else {
1175                 pr_info("No daughter card found\n");
1176                 daughter_brd_detected = false;
1177         }
1178 }
1179
1180 static void am335x_evm_setup(struct memory_accessor *mem_acc, void *context)
1181 {
1182         int ret;
1183         char tmp[10];
1184
1185         /* 1st get the MAC address from EEPROM */
1186         ret = mem_acc->read(mem_acc, (char *)&am335x_mac_addr,
1187                 EEPROM_MAC_ADDRESS_OFFSET, sizeof(am335x_mac_addr));
1188
1189         if (ret != sizeof(am335x_mac_addr)) {
1190                 pr_warning("AM335X: MV Config read fail: %d\n", ret);
1191         }
1192
1193         /* Fillup global mac id */
1194         am33xx_cpsw_macidfillup(&am335x_mac_addr[0][0],
1195                                 &am335x_mac_addr[1][0]);
1196
1197         /* get board specific data */
1198
1199         setup_general_purpose_evm();
1200         /* Initialize cpsw after board detection is completed as board
1201          * information is required for configuring phy address and hence
1202          * should be call only after board detection
1203          */
1204         am33xx_cpsw_init(gigabit_enable);
1205
1206         return;
1207 out:
1208         /*
1209          * If the EEPROM hasn't been programed or an incorrect header
1210          * or board name are read, assume this is an old beaglebone board
1211          * (< Rev A3)
1212          */
1213         pr_err("Could not detect any board, falling back to: "
1214                 "Beaglebone (< Rev A3) with no daughter card connected\n");
1215         daughter_brd_detected = false;
1216
1217         /* Initialize cpsw after board detection is completed as board
1218          * information is required for configuring phy address and hence
1219          * should be call only after board detection
1220          */
1221
1222         am33xx_cpsw_init(gigabit_enable);
1223 }
1224
1225 static struct at24_platform_data am335x_daughter_board_eeprom_info = {
1226         .byte_len       = (256*1024) / 8,
1227         .page_size      = 64,
1228         .flags          = AT24_FLAG_ADDR16,
1229         .setup          = am335x_setup_daughter_board,
1230         .context        = (void *)NULL,
1231 };
1232
1233 static struct at24_platform_data am335x_baseboard_eeprom_info = {
1234         .byte_len       = (256*1024) / 8,
1235         .page_size      = 64,
1236         .flags          = AT24_FLAG_ADDR16,
1237         .setup          = am335x_evm_setup,
1238         .context        = (void *)NULL,
1239 };
1240
1241 static struct regulator_init_data am335x_dummy;
1242
1243 static struct regulator_consumer_supply am335x_vdd1_supply[] = {
1244         REGULATOR_SUPPLY("mpu", "mpu.0"),
1245 };
1246
1247 static struct regulator_init_data am335x_vdd1 = {
1248         .constraints = {
1249                 .min_uV                 = 600000,
1250                 .max_uV                 = 1500000,
1251                 .valid_modes_mask       = REGULATOR_MODE_NORMAL,
1252                 .valid_ops_mask         = REGULATOR_CHANGE_VOLTAGE,
1253                 .always_on              = 1,
1254         },
1255         .num_consumer_supplies  = ARRAY_SIZE(am335x_vdd1_supply),
1256         .consumer_supplies      = am335x_vdd1_supply,
1257 };
1258
1259 static struct tps65910_board am335x_tps65910_info = {
1260         .tps65910_pmic_init_data[TPS65910_REG_VRTC]     = &am335x_dummy,
1261         .tps65910_pmic_init_data[TPS65910_REG_VIO]      = &am335x_dummy,
1262         .tps65910_pmic_init_data[TPS65910_REG_VDD1]     = &am335x_vdd1,
1263         .tps65910_pmic_init_data[TPS65910_REG_VDD2]     = &am335x_dummy,
1264         .tps65910_pmic_init_data[TPS65910_REG_VDD3]     = &am335x_dummy,
1265         .tps65910_pmic_init_data[TPS65910_REG_VDIG1]    = &am335x_dummy,
1266         .tps65910_pmic_init_data[TPS65910_REG_VDIG2]    = &am335x_dummy,
1267         .tps65910_pmic_init_data[TPS65910_REG_VPLL]     = &am335x_dummy,
1268         .tps65910_pmic_init_data[TPS65910_REG_VDAC]     = &am335x_dummy,
1269         .tps65910_pmic_init_data[TPS65910_REG_VAUX1]    = &am335x_dummy,
1270         .tps65910_pmic_init_data[TPS65910_REG_VAUX2]    = &am335x_dummy,
1271         .tps65910_pmic_init_data[TPS65910_REG_VAUX33]   = &am335x_dummy,
1272         .tps65910_pmic_init_data[TPS65910_REG_VMMC]     = &am335x_dummy,
1273 };
1274
1275 /*
1276 * Daughter board Detection.
1277 * Every board has a ID memory (EEPROM) on board. We probe these devices at
1278 * machine init, starting from daughter board and ending with baseboard.
1279 * Assumptions :
1280 *       1. probe for i2c devices are called in the order they are included in
1281 *          the below struct. Daughter boards eeprom are probed 1st. Baseboard
1282 *          eeprom probe is called last.
1283 */
1284 static struct i2c_board_info __initdata am335x_i2c_boardinfo[] = {
1285         {
1286                 /* Daughter Board EEPROM */
1287                 I2C_BOARD_INFO("24c256", DAUG_BOARD_I2C_ADDR),
1288                 .platform_data  = &am335x_daughter_board_eeprom_info,
1289         },
1290         {
1291                 /* Baseboard board EEPROM */
1292                 I2C_BOARD_INFO("24c256", BASEBOARD_I2C_ADDR),
1293                 .platform_data  = &am335x_baseboard_eeprom_info,
1294         },
1295         {
1296                 I2C_BOARD_INFO("cpld_reg", 0x35),
1297         },
1298         {
1299                 I2C_BOARD_INFO("tlc59108", 0x40),
1300         },
1301         {
1302                 I2C_BOARD_INFO("tps65910", TPS65910_I2C_ID1),
1303                 .platform_data  = &am335x_tps65910_info,
1304         },
1305
1306 };
1307
1308 static struct omap_musb_board_data musb_board_data = {
1309         .interface_type = MUSB_INTERFACE_ULPI,
1310         .mode           = MUSB_OTG,
1311         .power          = 500,
1312         .instances      = 1,
1313 };
1314
1315 static int cpld_reg_probe(struct i2c_client *client,
1316             const struct i2c_device_id *id)
1317 {
1318         cpld_client = client;
1319         return 0;
1320 }
1321
1322 static int __devexit cpld_reg_remove(struct i2c_client *client)
1323 {
1324         cpld_client = NULL;
1325         return 0;
1326 }
1327
1328 static const struct i2c_device_id cpld_reg_id[] = {
1329         { "cpld_reg", 0 },
1330         { }
1331 };
1332
1333 static struct i2c_driver cpld_reg_driver = {
1334         .driver = {
1335                 .name   = "cpld_reg",
1336         },
1337         .probe          = cpld_reg_probe,
1338         .remove         = cpld_reg_remove,
1339         .id_table       = cpld_reg_id,
1340 };
1341
1342 static void evm_init_cpld(void)
1343 {
1344         i2c_add_driver(&cpld_reg_driver);
1345 }
1346
1347 static void __init am335x_evm_i2c_init(void)
1348 {
1349         /* Initially assume Low Cost EVM Config */
1350         am335x_evm_id = LOW_COST_EVM;
1351
1352         evm_init_cpld();
1353
1354         omap_register_i2c_bus(1, 100, am335x_i2c_boardinfo,
1355                                 ARRAY_SIZE(am335x_i2c_boardinfo));
1356 }
1357
1358 static struct resource am335x_rtc_resources[] = {
1359         {
1360                 .start          = AM33XX_RTC_BASE,
1361                 .end            = AM33XX_RTC_BASE + SZ_4K - 1,
1362                 .flags          = IORESOURCE_MEM,
1363         },
1364         { /* timer irq */
1365                 .start          = AM33XX_IRQ_RTC_TIMER,
1366                 .end            = AM33XX_IRQ_RTC_TIMER,
1367                 .flags          = IORESOURCE_IRQ,
1368         },
1369         { /* alarm irq */
1370                 .start          = AM33XX_IRQ_RTC_ALARM,
1371                 .end            = AM33XX_IRQ_RTC_ALARM,
1372                 .flags          = IORESOURCE_IRQ,
1373         },
1374 };
1375
1376 static struct platform_device am335x_rtc_device = {
1377         .name           = "omap_rtc",
1378         .id             = -1,
1379         .num_resources  = ARRAY_SIZE(am335x_rtc_resources),
1380         .resource       = am335x_rtc_resources,
1381 };
1382
1383 static int am335x_rtc_init(void)
1384 {
1385         void __iomem *base;
1386         struct clk *clk;
1387
1388         clk = clk_get(NULL, "rtc_fck");
1389         if (IS_ERR(clk)) {
1390                 pr_err("rtc : Failed to get RTC clock\n");
1391                 return -1;
1392         }
1393
1394         if (clk_enable(clk)) {
1395                 pr_err("rtc: Clock Enable Failed\n");
1396                 return -1;
1397         }
1398
1399         base = ioremap(AM33XX_RTC_BASE, SZ_4K);
1400
1401         if (WARN_ON(!base))
1402                 return -ENOMEM;
1403
1404         /* Unlock the rtc's registers */
1405         __raw_writel(0x83e70b13, base + 0x6c);
1406         __raw_writel(0x95a4f1e0, base + 0x70);
1407
1408         /*
1409          * Enable the 32K OSc
1410          * TODO: Need a better way to handle this
1411          * Since we want the clock to be running before mmc init
1412          * we need to do it before the rtc probe happens
1413          */
1414         __raw_writel(0x48, base + 0x54);
1415
1416         iounmap(base);
1417
1418         return  platform_device_register(&am335x_rtc_device);
1419 }
1420
1421 /* Enable clkout2 */
1422 static struct pinmux_config clkout2_pin_mux[] = {
1423         {"xdma_event_intr1.clkout2", OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT},
1424         {NULL, 0},
1425 };
1426
1427 static void __init clkout2_enable(void)
1428 {
1429         struct clk *ck_32;
1430
1431         ck_32 = clk_get(NULL, "clkout2_ck");
1432         if (IS_ERR(ck_32)) {
1433                 pr_err("Cannot clk_get ck_32\n");
1434                 return;
1435         }
1436
1437         clk_enable(ck_32);
1438
1439         setup_pin_mux(clkout2_pin_mux);
1440 }
1441
1442 void __iomem * __init am33xx_get_mem_ctlr(void)
1443 {
1444         void __iomem *am33xx_emif_base;
1445
1446         am33xx_emif_base = ioremap(AM33XX_EMIF0_BASE, SZ_32K);
1447
1448         if (!am33xx_emif_base)
1449                 pr_warning("%s: Unable to map DDR2 controller", __func__);
1450
1451         return am33xx_emif_base;
1452 }
1453
1454 static struct resource am33xx_cpuidle_resources[] = {
1455         {
1456                 .start          = AM33XX_EMIF0_BASE,
1457                 .end            = AM33XX_EMIF0_BASE + SZ_32K - 1,
1458                 .flags          = IORESOURCE_MEM,
1459         },
1460 };
1461
1462 /* AM33XX devices support DDR2 power down */
1463 static struct am33xx_cpuidle_config am33xx_cpuidle_pdata = {
1464         .ddr2_pdown     = 1,
1465 };
1466
1467 static struct platform_device am33xx_cpuidle_device = {
1468         .name                   = "cpuidle-am33xx",
1469         .num_resources          = ARRAY_SIZE(am33xx_cpuidle_resources),
1470         .resource               = am33xx_cpuidle_resources,
1471         .dev = {
1472                 .platform_data  = &am33xx_cpuidle_pdata,
1473         },
1474 };
1475
1476 static void __init am33xx_cpuidle_init(void)
1477 {
1478         int ret;
1479
1480         am33xx_cpuidle_pdata.emif_base = am33xx_get_mem_ctlr();
1481
1482         ret = platform_device_register(&am33xx_cpuidle_device);
1483
1484         if (ret)
1485                 pr_warning("AM33XX cpuidle registration failed\n");
1486
1487 }
1488
1489 static void __init am335x_evm_init(void)
1490 {
1491         am33xx_cpuidle_init();
1492         am33xx_mux_init(board_mux);
1493         omap_serial_init();
1494         am335x_rtc_init();
1495         clkout2_enable();
1496         am335x_evm_i2c_init();
1497         omap_sdrc_init(NULL, NULL);
1498         usb_musb_init(&musb_board_data);
1499         omap_board_config = am335x_evm_config;
1500         omap_board_config_size = ARRAY_SIZE(am335x_evm_config);
1501         /* Create an alias for icss clock */
1502         if (clk_add_alias("pruss", NULL, "icss_uart_gclk", NULL))
1503                 pr_err("failed to create an alias: icss_uart_gclk --> pruss\n");
1504         /* Create an alias for gfx/sgx clock */
1505         if (clk_add_alias("sgx_ck", NULL, "gfx_fclk", NULL))
1506                 pr_err("failed to create an alias: gfx_fclk --> sgx_ck\n");
1507 }
1508
1509 static void __init am335x_evm_map_io(void)
1510 {
1511         omap2_set_globals_am33xx();
1512         omapam33xx_map_common_io();
1513 }
1514
1515 MACHINE_START(AM335XEVM, "am335xevm")
1516         /* Maintainer: Texas Instruments */
1517         .atag_offset    = 0x100,
1518         .map_io         = am335x_evm_map_io,
1519         .init_irq       = ti816x_init_irq,
1520         .init_early     = am335x_init_early,
1521         .timer          = &omap3_am33xx_timer,
1522         .init_machine   = am335x_evm_init,
1523 MACHINE_END
1524
1525 MACHINE_START(AM335XIAEVM, "am335xiaevm")
1526         /* Maintainer: Texas Instruments */
1527         .atag_offset    = 0x100,
1528         .map_io         = am335x_evm_map_io,
1529         .init_irq       = ti816x_init_irq,
1530         .init_early     = am335x_init_early,
1531         .timer          = &omap3_am33xx_timer,
1532         .init_machine   = am335x_evm_init,
1533 MACHINE_END