arch/mips/mm/c-r4k.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
   7  * Copyright (C) 1997, 1998, 1999, 2000, 2001, 2002 Ralf Baechle (ralf@gnu.org)
   8  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
   9  */
  10 #include <linux/hardirq.h>
  11 #include <linux/init.h>
  12 #include <linux/highmem.h>
  13 #include <linux/kernel.h>
  14 #include <linux/linkage.h>
  15 #include <linux/preempt.h>
  16 #include <linux/sched.h>
  17 #include <linux/smp.h>
  18 #include <linux/mm.h>
  19 #include <linux/module.h>
  20 #include <linux/bitops.h>
  21
  22 #include <asm/bcache.h>
  23 #include <asm/bootinfo.h>
  24 #include <asm/cache.h>
  25 #include <asm/cacheops.h>
  26 #include <asm/cpu.h>
  27 #include <asm/cpu-features.h>
  28 #include <asm/cpu-type.h>
  29 #include <asm/io.h>
  30 #include <asm/page.h>
  31 #include <asm/pgtable.h>
  32 #include <asm/r4kcache.h>
  33 #include <asm/sections.h>
  34 #include <asm/mmu_context.h>
  35 #include <asm/war.h>
  36 #include <asm/cacheflush.h> /* for run_uncached() */
  37 #include <asm/traps.h>
  38 #include <asm/dma-coherence.h>
  39
  40 /*
  41  * Special Variant of smp_call_function for use by cache functions:
  42  *
  43  *  o No return value
  44  *  o collapses to normal function call on UP kernels
  45  *  o collapses to normal function call on systems with a single shared
  46  *    primary cache.
  47  *  o doesn't disable interrupts on the local CPU
  48  */
  49 static inline void r4k_on_each_cpu(void (*func) (void *info), void *info)
  50 {
  51         preempt_disable();
  52
  53 #if !defined(CONFIG_MIPS_MT_SMP) && !defined(CONFIG_MIPS_MT_SMTC)
  54         smp_call_function(func, info, 1);
  55 #endif
  56         func(info);
  57         preempt_enable();
  58 }
  59
  60 #if defined(CONFIG_MIPS_CMP)
  61 #define cpu_has_safe_index_cacheops 0
  62 #else
  63 #define cpu_has_safe_index_cacheops 1
  64 #endif
  65
  66 /*
  67  * Must die.
  68  */
  69 static unsigned long icache_size __read_mostly;
  70 static unsigned long dcache_size __read_mostly;
  71 static unsigned long scache_size __read_mostly;
  72
  73 /*
  74  * Dummy cache handling routines for machines without boardcaches
  75  */
  76 static void cache_noop(void) {}
  77
  78 static struct bcache_ops no_sc_ops = {
  79         .bc_enable = (void *)cache_noop,
  80         .bc_disable = (void *)cache_noop,
  81         .bc_wback_inv = (void *)cache_noop,
  82         .bc_inv = (void *)cache_noop
  83 };
  84
  85 struct bcache_ops *bcops = &no_sc_ops;
  86
  87 #define cpu_is_r4600_v1_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002010)
  88 #define cpu_is_r4600_v2_x()     ((read_c0_prid() & 0xfffffff0) == 0x00002020)
  89
  90 #define R4600_HIT_CACHEOP_WAR_IMPL                                      \
  91 do {                                                                    \
  92         if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())            \
  93                 *(volatile unsigned long *)CKSEG1;                      \
  94         if (R4600_V1_HIT_CACHEOP_WAR)                                   \
  95                 __asm__ __volatile__("nop;nop;nop;nop");                \
  96 } while (0)
  97
  98 static void (*r4k_blast_dcache_page)(unsigned long addr);
  99
 100 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
 101 {
 102         R4600_HIT_CACHEOP_WAR_IMPL;
 103         blast_dcache32_page(addr);
 104 }
 105
 106 static inline void r4k_blast_dcache_page_dc64(unsigned long addr)
 107 {
 108         R4600_HIT_CACHEOP_WAR_IMPL;
 109         blast_dcache64_page(addr);
 110 }
 111
 112 static void r4k_blast_dcache_page_setup(void)
 113 {
 114         unsigned long  dc_lsize = cpu_dcache_line_size();
 115
 116         if (dc_lsize == 0)
 117                 r4k_blast_dcache_page = (void *)cache_noop;
 118         else if (dc_lsize == 16)
 119                 r4k_blast_dcache_page = blast_dcache16_page;
 120         else if (dc_lsize == 32)
 121                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
 122         else if (dc_lsize == 64)
 123                 r4k_blast_dcache_page = r4k_blast_dcache_page_dc64;
 124 }
 125
 126 static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
 127
 128 static void r4k_blast_dcache_page_indexed_setup(void)
 129 {
 130         unsigned long dc_lsize = cpu_dcache_line_size();
 131
 132         if (dc_lsize == 0)
 133                 r4k_blast_dcache_page_indexed = (void *)cache_noop;
 134         else if (dc_lsize == 16)
 135                 r4k_blast_dcache_page_indexed = blast_dcache16_page_indexed;
 136         else if (dc_lsize == 32)
 137                 r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
 138         else if (dc_lsize == 64)
 139                 r4k_blast_dcache_page_indexed = blast_dcache64_page_indexed;
 140 }
 141
 142 void (* r4k_blast_dcache)(void);
 143 EXPORT_SYMBOL(r4k_blast_dcache);
 144
 145 static void r4k_blast_dcache_setup(void)
 146 {
 147         unsigned long dc_lsize = cpu_dcache_line_size();
 148
 149         if (dc_lsize == 0)
 150                 r4k_blast_dcache = (void *)cache_noop;
 151         else if (dc_lsize == 16)
 152                 r4k_blast_dcache = blast_dcache16;
 153         else if (dc_lsize == 32)
 154                 r4k_blast_dcache = blast_dcache32;
 155         else if (dc_lsize == 64)
 156                 r4k_blast_dcache = blast_dcache64;
 157 }
 158
 159 /* force code alignment (used for TX49XX_ICACHE_INDEX_INV_WAR) */
 160 #define JUMP_TO_ALIGN(order) \
 161         __asm__ __volatile__( \
 162                 "b\t1f\n\t" \
 163                 ".align\t" #order "\n\t" \
 164                 "1:\n\t" \
 165                 )
 166 #define CACHE32_UNROLL32_ALIGN  JUMP_TO_ALIGN(10) /* 32 * 32 = 1024 */
 167 #define CACHE32_UNROLL32_ALIGN2 JUMP_TO_ALIGN(11)
 168
 169 static inline void blast_r4600_v1_icache32(void)
 170 {
 171         unsigned long flags;
 172
 173         local_irq_save(flags);
 174         blast_icache32();
 175         local_irq_restore(flags);
 176 }
 177
 178 static inline void tx49_blast_icache32(void)
 179 {
 180         unsigned long start = INDEX_BASE;
 181         unsigned long end = start + current_cpu_data.icache.waysize;
 182         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 183         unsigned long ws_end = current_cpu_data.icache.ways <<
 184                                current_cpu_data.icache.waybit;
 185         unsigned long ws, addr;
 186
 187         CACHE32_UNROLL32_ALIGN2;
 188         /* I'm in even chunk.  blast odd chunks */
 189         for (ws = 0; ws < ws_end; ws += ws_inc)
 190                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 191                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 192         CACHE32_UNROLL32_ALIGN;
 193         /* I'm in odd chunk.  blast even chunks */
 194         for (ws = 0; ws < ws_end; ws += ws_inc)
 195                 for (addr = start; addr < end; addr += 0x400 * 2)
 196                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 197 }
 198
 199 static inline void blast_icache32_r4600_v1_page_indexed(unsigned long page)
 200 {
 201         unsigned long flags;
 202
 203         local_irq_save(flags);
 204         blast_icache32_page_indexed(page);
 205         local_irq_restore(flags);
 206 }
 207
 208 static inline void tx49_blast_icache32_page_indexed(unsigned long page)
 209 {
 210         unsigned long indexmask = current_cpu_data.icache.waysize - 1;
 211         unsigned long start = INDEX_BASE + (page & indexmask);
 212         unsigned long end = start + PAGE_SIZE;
 213         unsigned long ws_inc = 1UL << current_cpu_data.icache.waybit;
 214         unsigned long ws_end = current_cpu_data.icache.ways <<
 215                                current_cpu_data.icache.waybit;
 216         unsigned long ws, addr;
 217
 218         CACHE32_UNROLL32_ALIGN2;
 219         /* I'm in even chunk.  blast odd chunks */
 220         for (ws = 0; ws < ws_end; ws += ws_inc)
 221                 for (addr = start + 0x400; addr < end; addr += 0x400 * 2)
 222                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 223         CACHE32_UNROLL32_ALIGN;
 224         /* I'm in odd chunk.  blast even chunks */
 225         for (ws = 0; ws < ws_end; ws += ws_inc)
 226                 for (addr = start; addr < end; addr += 0x400 * 2)
 227                         cache32_unroll32(addr|ws, Index_Invalidate_I);
 228 }
 229
 230 static void (* r4k_blast_icache_page)(unsigned long addr);
 231
 232 static void r4k_blast_icache_page_setup(void)
 233 {
 234         unsigned long ic_lsize = cpu_icache_line_size();
 235
 236         if (ic_lsize == 0)
 237                 r4k_blast_icache_page = (void *)cache_noop;
 238         else if (ic_lsize == 16)
 239                 r4k_blast_icache_page = blast_icache16_page;
 240         else if (ic_lsize == 32)
 241                 r4k_blast_icache_page = blast_icache32_page;
 242         else if (ic_lsize == 64)
 243                 r4k_blast_icache_page = blast_icache64_page;
 244 }
 245
 246
 247 static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
 248
 249 static void r4k_blast_icache_page_indexed_setup(void)
 250 {
 251         unsigned long ic_lsize = cpu_icache_line_size();
 252
 253         if (ic_lsize == 0)
 254                 r4k_blast_icache_page_indexed = (void *)cache_noop;
 255         else if (ic_lsize == 16)
 256                 r4k_blast_icache_page_indexed = blast_icache16_page_indexed;
 257         else if (ic_lsize == 32) {
 258                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 259                         r4k_blast_icache_page_indexed =
 260                                 blast_icache32_r4600_v1_page_indexed;
 261                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 262                         r4k_blast_icache_page_indexed =
 263                                 tx49_blast_icache32_page_indexed;
 264                 else
 265                         r4k_blast_icache_page_indexed =
 266                                 blast_icache32_page_indexed;
 267         } else if (ic_lsize == 64)
 268                 r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
 269 }
 270
 271 void (* r4k_blast_icache)(void);
 272 EXPORT_SYMBOL(r4k_blast_icache);
 273
 274 static void r4k_blast_icache_setup(void)
 275 {
 276         unsigned long ic_lsize = cpu_icache_line_size();
 277
 278         if (ic_lsize == 0)
 279                 r4k_blast_icache = (void *)cache_noop;
 280         else if (ic_lsize == 16)
 281                 r4k_blast_icache = blast_icache16;
 282         else if (ic_lsize == 32) {
 283                 if (R4600_V1_INDEX_ICACHEOP_WAR && cpu_is_r4600_v1_x())
 284                         r4k_blast_icache = blast_r4600_v1_icache32;
 285                 else if (TX49XX_ICACHE_INDEX_INV_WAR)
 286                         r4k_blast_icache = tx49_blast_icache32;
 287                 else
 288                         r4k_blast_icache = blast_icache32;
 289         } else if (ic_lsize == 64)
 290                 r4k_blast_icache = blast_icache64;
 291 }
 292
 293 static void (* r4k_blast_scache_page)(unsigned long addr);
 294
 295 static void r4k_blast_scache_page_setup(void)
 296 {
 297         unsigned long sc_lsize = cpu_scache_line_size();
 298
 299         if (scache_size == 0)
 300                 r4k_blast_scache_page = (void *)cache_noop;
 301         else if (sc_lsize == 16)
 302                 r4k_blast_scache_page = blast_scache16_page;
 303         else if (sc_lsize == 32)
 304                 r4k_blast_scache_page = blast_scache32_page;
 305         else if (sc_lsize == 64)
 306                 r4k_blast_scache_page = blast_scache64_page;
 307         else if (sc_lsize == 128)
 308                 r4k_blast_scache_page = blast_scache128_page;
 309 }
 310
 311 static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
 312
 313 static void r4k_blast_scache_page_indexed_setup(void)
 314 {
 315         unsigned long sc_lsize = cpu_scache_line_size();
 316
 317         if (scache_size == 0)
 318                 r4k_blast_scache_page_indexed = (void *)cache_noop;
 319         else if (sc_lsize == 16)
 320                 r4k_blast_scache_page_indexed = blast_scache16_page_indexed;
 321         else if (sc_lsize == 32)
 322                 r4k_blast_scache_page_indexed = blast_scache32_page_indexed;
 323         else if (sc_lsize == 64)
 324                 r4k_blast_scache_page_indexed = blast_scache64_page_indexed;
 325         else if (sc_lsize == 128)
 326                 r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
 327 }
 328
 329 static void (* r4k_blast_scache)(void);
 330
 331 static void r4k_blast_scache_setup(void)
 332 {
 333         unsigned long sc_lsize = cpu_scache_line_size();
 334
 335         if (scache_size == 0)
 336                 r4k_blast_scache = (void *)cache_noop;
 337         else if (sc_lsize == 16)
 338                 r4k_blast_scache = blast_scache16;
 339         else if (sc_lsize == 32)
 340                 r4k_blast_scache = blast_scache32;
 341         else if (sc_lsize == 64)
 342                 r4k_blast_scache = blast_scache64;
 343         else if (sc_lsize == 128)
 344                 r4k_blast_scache = blast_scache128;
 345 }
 346
 347 static inline void local_r4k___flush_cache_all(void * args)
 348 {
 349         switch (current_cpu_type()) {
 350         case CPU_LOONGSON2:
 351         case CPU_R4000SC:
 352         case CPU_R4000MC:
 353         case CPU_R4400SC:
 354         case CPU_R4400MC:
 355         case CPU_R10000:
 356         case CPU_R12000:
 357         case CPU_R14000:
 358                 /*
 359                  * These caches are inclusive caches, that is, if something
 360                  * is not cached in the S-cache, we know it also won't be
 361                  * in one of the primary caches.
 362                  */
 363                 r4k_blast_scache();
 364                 break;
 365
 366         default:
 367                 r4k_blast_dcache();
 368                 r4k_blast_icache();
 369                 break;
 370         }
 371 }
 372
 373 static void r4k___flush_cache_all(void)
 374 {
 375         r4k_on_each_cpu(local_r4k___flush_cache_all, NULL);
 376 }
 377
 378 static inline int has_valid_asid(const struct mm_struct *mm)
 379 {
 380 #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
 381         int i;
 382
 383         for_each_online_cpu(i)
 384                 if (cpu_context(i, mm))
 385                         return 1;
 386
 387         return 0;
 388 #else
 389         return cpu_context(smp_processor_id(), mm);
 390 #endif
 391 }
 392
 393 static void r4k__flush_cache_vmap(void)
 394 {
 395         r4k_blast_dcache();
 396 }
 397
 398 static void r4k__flush_cache_vunmap(void)
 399 {
 400         r4k_blast_dcache();
 401 }
 402
 403 static inline void local_r4k_flush_cache_range(void * args)
 404 {
 405         struct vm_area_struct *vma = args;
 406         int exec = vma->vm_flags & VM_EXEC;
 407
 408         if (!(has_valid_asid(vma->vm_mm)))
 409                 return;
 410
 411         r4k_blast_dcache();
 412         if (exec)
 413                 r4k_blast_icache();
 414 }
 415
 416 static void r4k_flush_cache_range(struct vm_area_struct *vma,
 417         unsigned long start, unsigned long end)
 418 {
 419         int exec = vma->vm_flags & VM_EXEC;
 420
 421         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc))
 422                 r4k_on_each_cpu(local_r4k_flush_cache_range, vma);
 423 }
 424
 425 static inline void local_r4k_flush_cache_mm(void * args)
 426 {
 427         struct mm_struct *mm = args;
 428
 429         if (!has_valid_asid(mm))
 430                 return;
 431
 432         /*
 433          * Kludge alert.  For obscure reasons R4000SC and R4400SC go nuts if we
 434          * only flush the primary caches but R10000 and R12000 behave sane ...
 435          * R4000SC and R4400SC indexed S-cache ops also invalidate primary
 436          * caches, so we can bail out early.
 437          */
 438         if (current_cpu_type() == CPU_R4000SC ||
 439             current_cpu_type() == CPU_R4000MC ||
 440             current_cpu_type() == CPU_R4400SC ||
 441             current_cpu_type() == CPU_R4400MC) {
 442                 r4k_blast_scache();
 443                 return;
 444         }
 445
 446         r4k_blast_dcache();
 447 }
 448
 449 static void r4k_flush_cache_mm(struct mm_struct *mm)
 450 {
 451         if (!cpu_has_dc_aliases)
 452                 return;
 453
 454         r4k_on_each_cpu(local_r4k_flush_cache_mm, mm);
 455 }
 456
 457 struct flush_cache_page_args {
 458         struct vm_area_struct *vma;
 459         unsigned long addr;
 460         unsigned long pfn;
 461 };
 462
 463 static inline void local_r4k_flush_cache_page(void *args)
 464 {
 465         struct flush_cache_page_args *fcp_args = args;
 466         struct vm_area_struct *vma = fcp_args->vma;
 467         unsigned long addr = fcp_args->addr;
 468         struct page *page = pfn_to_page(fcp_args->pfn);
 469         int exec = vma->vm_flags & VM_EXEC;
 470         struct mm_struct *mm = vma->vm_mm;
 471         int map_coherent = 0;
 472         pgd_t *pgdp;
 473         pud_t *pudp;
 474         pmd_t *pmdp;
 475         pte_t *ptep;
 476         void *vaddr;
 477
 478         /*
 479          * If ownes no valid ASID yet, cannot possibly have gotten
 480          * this page into the cache.
 481          */
 482         if (!has_valid_asid(mm))
 483                 return;
 484
 485         addr &= PAGE_MASK;
 486         pgdp = pgd_offset(mm, addr);
 487         pudp = pud_offset(pgdp, addr);
 488         pmdp = pmd_offset(pudp, addr);
 489         ptep = pte_offset(pmdp, addr);
 490
 491         /*
 492          * If the page isn't marked valid, the page cannot possibly be
 493          * in the cache.
 494          */
 495         if (!(pte_present(*ptep)))
 496                 return;
 497
 498         if ((mm == current->active_mm) && (pte_val(*ptep) & _PAGE_VALID))
 499                 vaddr = NULL;
 500         else {
 501                 /*
 502                  * Use kmap_coherent or kmap_atomic to do flushes for
 503                  * another ASID than the current one.
 504                  */
 505                 map_coherent = (cpu_has_dc_aliases &&
 506                                 page_mapped(page) && !Page_dcache_dirty(page));
 507                 if (map_coherent)
 508                         vaddr = kmap_coherent(page, addr);
 509                 else
 510                         vaddr = kmap_atomic(page);
 511                 addr = (unsigned long)vaddr;
 512         }
 513
 514         if (cpu_has_dc_aliases || (exec && !cpu_has_ic_fills_f_dc)) {
 515                 r4k_blast_dcache_page(addr);
 516                 if (exec && !cpu_icache_snoops_remote_store)
 517                         r4k_blast_scache_page(addr);
 518         }
 519         if (exec) {
 520                 if (vaddr && cpu_has_vtag_icache && mm == current->active_mm) {
 521                         int cpu = smp_processor_id();
 522
 523                         if (cpu_context(cpu, mm) != 0)
 524                                 drop_mmu_context(mm, cpu);
 525                 } else
 526                         r4k_blast_icache_page(addr);
 527         }
 528
 529         if (vaddr) {
 530                 if (map_coherent)
 531                         kunmap_coherent();
 532                 else
 533                         kunmap_atomic(vaddr);
 534         }
 535 }
 536
 537 static void r4k_flush_cache_page(struct vm_area_struct *vma,
 538         unsigned long addr, unsigned long pfn)
 539 {
 540         struct flush_cache_page_args args;
 541
 542         args.vma = vma;
 543         args.addr = addr;
 544         args.pfn = pfn;
 545
 546         r4k_on_each_cpu(local_r4k_flush_cache_page, &args);
 547 }
 548
 549 static inline void local_r4k_flush_data_cache_page(void * addr)
 550 {
 551         r4k_blast_dcache_page((unsigned long) addr);
 552 }
 553
 554 static void r4k_flush_data_cache_page(unsigned long addr)
 555 {
 556         if (in_atomic())
 557                 local_r4k_flush_data_cache_page((void *)addr);
 558         else
 559                 r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr);
 560 }
 561
 562 struct flush_icache_range_args {
 563         unsigned long start;
 564         unsigned long end;
 565 };
 566
 567 static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end)
 568 {
 569         if (!cpu_has_ic_fills_f_dc) {
 570                 if (end - start >= dcache_size) {
 571                         r4k_blast_dcache();
 572                 } else {
 573                         R4600_HIT_CACHEOP_WAR_IMPL;
 574                         protected_blast_dcache_range(start, end);
 575                 }
 576         }
 577
 578         if (end - start > icache_size)
 579                 r4k_blast_icache();
 580         else {
 581                 switch (boot_cpu_type()) {
 582                 case CPU_LOONGSON2:
 583                         protected_blast_icache_range(start, end);
 584                         break;
 585
 586                 default:
 587                         protected_loongson23_blast_icache_range(start, end);
 588                         break;
 589                 }
 590         }
 591 }
 592
 593 static inline void local_r4k_flush_icache_range_ipi(void *args)
 594 {
 595         struct flush_icache_range_args *fir_args = args;
 596         unsigned long start = fir_args->start;
 597         unsigned long end = fir_args->end;
 598
 599         local_r4k_flush_icache_range(start, end);
 600 }
 601
 602 static void r4k_flush_icache_range(unsigned long start, unsigned long end)
 603 {
 604         struct flush_icache_range_args args;
 605
 606         args.start = start;
 607         args.end = end;
 608
 609         r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args);
 610         instruction_hazard();
 611 }
 612
 613 #ifdef CONFIG_DMA_NONCOHERENT
 614
 615 static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
 616 {
 617         /* Catch bad driver code */
 618         BUG_ON(size == 0);
 619
 620         preempt_disable();
 621         if (cpu_has_inclusive_pcaches) {
 622                 if (size >= scache_size)
 623                         r4k_blast_scache();
 624                 else
 625                         blast_scache_range(addr, addr + size);
 626                 preempt_enable();
 627                 __sync();
 628                 return;
 629         }
 630
 631         /*
 632          * Either no secondary cache or the available caches don't have the
 633          * subset property so we have to flush the primary caches
 634          * explicitly
 635          */
 636         if (cpu_has_safe_index_cacheops && size >= dcache_size) {
 637                 r4k_blast_dcache();
 638         } else {
 639                 R4600_HIT_CACHEOP_WAR_IMPL;
 640                 blast_dcache_range(addr, addr + size);
 641         }
 642         preempt_enable();
 643
 644         bc_wback_inv(addr, size);
 645         __sync();
 646 }
 647
 648 static void r4k_dma_cache_inv(unsigned long addr, unsigned long size)
 649 {
 650         /* Catch bad driver code */
 651         BUG_ON(size == 0);
 652
 653         preempt_disable();
 654         if (cpu_has_inclusive_pcaches) {
 655                 if (size >= scache_size)
 656                         r4k_blast_scache();
 657                 else {
 658                         /*
 659                          * There is no clearly documented alignment requirement
 660                          * for the cache instruction on MIPS processors and
 661                          * some processors, among them the RM5200 and RM7000
 662                          * QED processors will throw an address error for cache
 663                          * hit ops with insufficient alignment.  Solved by
 664                          * aligning the address to cache line size.
 665                          */
 666                         blast_inv_scache_range(addr, addr + size);
 667                 }
 668                 preempt_enable();
 669                 __sync();
 670                 return;
 671         }
 672
 673         if (cpu_has_safe_index_cacheops && size >= dcache_size) {
 674                 r4k_blast_dcache();
 675         } else {
 676                 R4600_HIT_CACHEOP_WAR_IMPL;
 677                 blast_inv_dcache_range(addr, addr + size);
 678         }
 679         preempt_enable();
 680
 681         bc_inv(addr, size);
 682         __sync();
 683 }
 684 #endif /* CONFIG_DMA_NONCOHERENT */
 685
 686 /*
 687  * While we're protected against bad userland addresses we don't care
 688  * very much about what happens in that case.  Usually a segmentation
 689  * fault will dump the process later on anyway ...
 690  */
 691 static void local_r4k_flush_cache_sigtramp(void * arg)
 692 {
 693         unsigned long ic_lsize = cpu_icache_line_size();
 694         unsigned long dc_lsize = cpu_dcache_line_size();
 695         unsigned long sc_lsize = cpu_scache_line_size();
 696         unsigned long addr = (unsigned long) arg;
 697
 698         R4600_HIT_CACHEOP_WAR_IMPL;
 699         if (dc_lsize)
 700                 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
 701         if (!cpu_icache_snoops_remote_store && scache_size)
 702                 protected_writeback_scache_line(addr & ~(sc_lsize - 1));
 703         if (ic_lsize)
 704                 protected_flush_icache_line(addr & ~(ic_lsize - 1));
 705         if (MIPS4K_ICACHE_REFILL_WAR) {
 706                 __asm__ __volatile__ (
 707                         ".set push\n\t"
 708                         ".set noat\n\t"
 709                         ".set mips3\n\t"
 710 #ifdef CONFIG_32BIT
 711                         "la     $at,1f\n\t"
 712 #endif
 713 #ifdef CONFIG_64BIT
 714                         "dla    $at,1f\n\t"
 715 #endif
 716                         "cache  %0,($at)\n\t"
 717                         "nop; nop; nop\n"
 718                         "1:\n\t"
 719                         ".set pop"
 720                         :
 721                         : "i" (Hit_Invalidate_I));
 722         }
 723         if (MIPS_CACHE_SYNC_WAR)
 724                 __asm__ __volatile__ ("sync");
 725 }
 726
 727 static void r4k_flush_cache_sigtramp(unsigned long addr)
 728 {
 729         r4k_on_each_cpu(local_r4k_flush_cache_sigtramp, (void *) addr);
 730 }
 731
 732 static void r4k_flush_icache_all(void)
 733 {
 734         if (cpu_has_vtag_icache)
 735                 r4k_blast_icache();
 736 }
 737
 738 struct flush_kernel_vmap_range_args {
 739         unsigned long   vaddr;
 740         int             size;
 741 };
 742
 743 static inline void local_r4k_flush_kernel_vmap_range(void *args)
 744 {
 745         struct flush_kernel_vmap_range_args *vmra = args;
 746         unsigned long vaddr = vmra->vaddr;
 747         int size = vmra->size;
 748
 749         /*
 750          * Aliases only affect the primary caches so don't bother with
 751          * S-caches or T-caches.
 752          */
 753         if (cpu_has_safe_index_cacheops && size >= dcache_size)
 754                 r4k_blast_dcache();
 755         else {
 756                 R4600_HIT_CACHEOP_WAR_IMPL;
 757                 blast_dcache_range(vaddr, vaddr + size);
 758         }
 759 }
 760
 761 static void r4k_flush_kernel_vmap_range(unsigned long vaddr, int size)
 762 {
 763         struct flush_kernel_vmap_range_args args;
 764
 765         args.vaddr = (unsigned long) vaddr;
 766         args.size = size;
 767
 768         r4k_on_each_cpu(local_r4k_flush_kernel_vmap_range, &args);
 769 }
 770
 771 static inline void rm7k_erratum31(void)
 772 {
 773         const unsigned long ic_lsize = 32;
 774         unsigned long addr;
 775
 776         /* RM7000 erratum #31. The icache is screwed at startup. */
 777         write_c0_taglo(0);
 778         write_c0_taghi(0);
 779
 780         for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) {
 781                 __asm__ __volatile__ (
 782                         ".set push\n\t"
 783                         ".set noreorder\n\t"
 784                         ".set mips3\n\t"
 785                         "cache\t%1, 0(%0)\n\t"
 786                         "cache\t%1, 0x1000(%0)\n\t"
 787                         "cache\t%1, 0x2000(%0)\n\t"
 788                         "cache\t%1, 0x3000(%0)\n\t"
 789                         "cache\t%2, 0(%0)\n\t"
 790                         "cache\t%2, 0x1000(%0)\n\t"
 791                         "cache\t%2, 0x2000(%0)\n\t"
 792                         "cache\t%2, 0x3000(%0)\n\t"
 793                         "cache\t%1, 0(%0)\n\t"
 794                         "cache\t%1, 0x1000(%0)\n\t"
 795                         "cache\t%1, 0x2000(%0)\n\t"
 796                         "cache\t%1, 0x3000(%0)\n\t"
 797                         ".set pop\n"
 798                         :
 799                         : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill));
 800         }
 801 }
 802
 803 static inline void alias_74k_erratum(struct cpuinfo_mips *c)
 804 {
 805         unsigned int imp = c->processor_id & PRID_IMP_MASK;
 806         unsigned int rev = c->processor_id & PRID_REV_MASK;
 807
 808         /*
 809          * Early versions of the 74K do not update the cache tags on a
 810          * vtag miss/ptag hit which can occur in the case of KSEG0/KUSEG
 811          * aliases. In this case it is better to treat the cache as always
 812          * having aliases.
 813          */
 814         switch (imp) {
 815         case PRID_IMP_74K:
 816                 if (rev <= PRID_REV_ENCODE_332(2, 4, 0))
 817                         c->dcache.flags |= MIPS_CACHE_VTAG;
 818                 if (rev == PRID_REV_ENCODE_332(2, 4, 0))
 819                         write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
 820                 break;
 821         case PRID_IMP_1074K:
 822                 if (rev <= PRID_REV_ENCODE_332(1, 1, 0)) {
 823                         c->dcache.flags |= MIPS_CACHE_VTAG;
 824                         write_c0_config6(read_c0_config6() | MIPS_CONF6_SYND);
 825                 }
 826                 break;
 827         default:
 828                 BUG();
 829         }
 830 }
 831
 832 static char *way_string[] = { NULL, "direct mapped", "2-way",
 833         "3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
 834 };
 835
 836 static void probe_pcache(void)
 837 {
 838         struct cpuinfo_mips *c = &current_cpu_data;
 839         unsigned int config = read_c0_config();
 840         unsigned int prid = read_c0_prid();
 841         unsigned long config1;
 842         unsigned int lsize;
 843
 844         switch (current_cpu_type()) {
 845         case CPU_R4600:                 /* QED style two way caches? */
 846         case CPU_R4700:
 847         case CPU_R5000:
 848         case CPU_NEVADA:
 849                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 850                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 851                 c->icache.ways = 2;
 852                 c->icache.waybit = __ffs(icache_size/2);
 853
 854                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 855                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 856                 c->dcache.ways = 2;
 857                 c->dcache.waybit= __ffs(dcache_size/2);
 858
 859                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 860                 break;
 861
 862         case CPU_R5432:
 863         case CPU_R5500:
 864                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 865                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 866                 c->icache.ways = 2;
 867                 c->icache.waybit= 0;
 868
 869                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 870                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 871                 c->dcache.ways = 2;
 872                 c->dcache.waybit = 0;
 873
 874                 c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH;
 875                 break;
 876
 877         case CPU_TX49XX:
 878                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 879                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 880                 c->icache.ways = 4;
 881                 c->icache.waybit= 0;
 882
 883                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 884                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 885                 c->dcache.ways = 4;
 886                 c->dcache.waybit = 0;
 887
 888                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 889                 c->options |= MIPS_CPU_PREFETCH;
 890                 break;
 891
 892         case CPU_R4000PC:
 893         case CPU_R4000SC:
 894         case CPU_R4000MC:
 895         case CPU_R4400PC:
 896         case CPU_R4400SC:
 897         case CPU_R4400MC:
 898         case CPU_R4300:
 899                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 900                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 901                 c->icache.ways = 1;
 902                 c->icache.waybit = 0;   /* doesn't matter */
 903
 904                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 905                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 906                 c->dcache.ways = 1;
 907                 c->dcache.waybit = 0;   /* does not matter */
 908
 909                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 910                 break;
 911
 912         case CPU_R10000:
 913         case CPU_R12000:
 914         case CPU_R14000:
 915                 icache_size = 1 << (12 + ((config & R10K_CONF_IC) >> 29));
 916                 c->icache.linesz = 64;
 917                 c->icache.ways = 2;
 918                 c->icache.waybit = 0;
 919
 920                 dcache_size = 1 << (12 + ((config & R10K_CONF_DC) >> 26));
 921                 c->dcache.linesz = 32;
 922                 c->dcache.ways = 2;
 923                 c->dcache.waybit = 0;
 924
 925                 c->options |= MIPS_CPU_PREFETCH;
 926                 break;
 927
 928         case CPU_VR4133:
 929                 write_c0_config(config & ~VR41_CONF_P4K);
 930         case CPU_VR4131:
 931                 /* Workaround for cache instruction bug of VR4131 */
 932                 if (c->processor_id == 0x0c80U || c->processor_id == 0x0c81U ||
 933                     c->processor_id == 0x0c82U) {
 934                         config |= 0x00400000U;
 935                         if (c->processor_id == 0x0c80U)
 936                                 config |= VR41_CONF_BP;
 937                         write_c0_config(config);
 938                 } else
 939                         c->options |= MIPS_CPU_CACHE_CDEX_P;
 940
 941                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
 942                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 943                 c->icache.ways = 2;
 944                 c->icache.waybit = __ffs(icache_size/2);
 945
 946                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
 947                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 948                 c->dcache.ways = 2;
 949                 c->dcache.waybit = __ffs(dcache_size/2);
 950                 break;
 951
 952         case CPU_VR41XX:
 953         case CPU_VR4111:
 954         case CPU_VR4121:
 955         case CPU_VR4122:
 956         case CPU_VR4181:
 957         case CPU_VR4181A:
 958                 icache_size = 1 << (10 + ((config & CONF_IC) >> 9));
 959                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 960                 c->icache.ways = 1;
 961                 c->icache.waybit = 0;   /* doesn't matter */
 962
 963                 dcache_size = 1 << (10 + ((config & CONF_DC) >> 6));
 964                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 965                 c->dcache.ways = 1;
 966                 c->dcache.waybit = 0;   /* does not matter */
 967
 968                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 969                 break;
 970
 971         case CPU_RM7000:
 972                 rm7k_erratum31();
 973
 974                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 975                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 976                 c->icache.ways = 4;
 977                 c->icache.waybit = __ffs(icache_size / c->icache.ways);
 978
 979                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 980                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 981                 c->dcache.ways = 4;
 982                 c->dcache.waybit = __ffs(dcache_size / c->dcache.ways);
 983
 984                 c->options |= MIPS_CPU_CACHE_CDEX_P;
 985                 c->options |= MIPS_CPU_PREFETCH;
 986                 break;
 987
 988         case CPU_LOONGSON2:
 989                 icache_size = 1 << (12 + ((config & CONF_IC) >> 9));
 990                 c->icache.linesz = 16 << ((config & CONF_IB) >> 5);
 991                 if (prid & 0x3)
 992                         c->icache.ways = 4;
 993                 else
 994                         c->icache.ways = 2;
 995                 c->icache.waybit = 0;
 996
 997                 dcache_size = 1 << (12 + ((config & CONF_DC) >> 6));
 998                 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4);
 999                 if (prid & 0x3)
1000                         c->dcache.ways = 4;
1001                 else
1002                         c->dcache.ways = 2;
1003                 c->dcache.waybit = 0;
1004                 break;
1005
1006         default:
1007                 if (!(config & MIPS_CONF_M))
1008                         panic("Don't know how to probe P-caches on this cpu.");
1009
1010                 /*
1011                  * So we seem to be a MIPS32 or MIPS64 CPU
1012                  * So let's probe the I-cache ...
1013                  */
1014                 config1 = read_c0_config1();
1015
1016                 if ((lsize = ((config1 >> 19) & 7)))
1017                         c->icache.linesz = 2 << lsize;
1018                 else
1019                         c->icache.linesz = lsize;
1020                 c->icache.sets = 32 << (((config1 >> 22) + 1) & 7);
1021                 c->icache.ways = 1 + ((config1 >> 16) & 7);
1022
1023                 icache_size = c->icache.sets *
1024                               c->icache.ways *
1025                               c->icache.linesz;
1026                 c->icache.waybit = __ffs(icache_size/c->icache.ways);
1027
1028                 if (config & 0x8)               /* VI bit */
1029                         c->icache.flags |= MIPS_CACHE_VTAG;
1030
1031                 /*
1032                  * Now probe the MIPS32 / MIPS64 data cache.
1033                  */
1034                 c->dcache.flags = 0;
1035
1036                 if ((lsize = ((config1 >> 10) & 7)))
1037                         c->dcache.linesz = 2 << lsize;
1038                 else
1039                         c->dcache.linesz= lsize;
1040                 c->dcache.sets = 32 << (((config1 >> 13) + 1) & 7);
1041                 c->dcache.ways = 1 + ((config1 >> 7) & 7);
1042
1043                 dcache_size = c->dcache.sets *
1044                               c->dcache.ways *
1045                               c->dcache.linesz;
1046                 c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
1047
1048                 c->options |= MIPS_CPU_PREFETCH;
1049                 break;
1050         }
1051
1052         /*
1053          * Processor configuration sanity check for the R4000SC erratum
1054          * #5.  With page sizes larger than 32kB there is no possibility
1055          * to get a VCE exception anymore so we don't care about this
1056          * misconfiguration.  The case is rather theoretical anyway;
1057          * presumably no vendor is shipping his hardware in the "bad"
1058          * configuration.
1059          */
1060         if ((prid & PRID_IMP_MASK) == PRID_IMP_R4000 &&
1061             (prid & PRID_REV_MASK) < PRID_REV_R4400 &&
1062             !(config & CONF_SC) && c->icache.linesz != 16 &&
1063             PAGE_SIZE <= 0x8000)
1064                 panic("Improper R4000SC processor configuration detected");
1065
1066         /* compute a couple of other cache variables */
1067         c->icache.waysize = icache_size / c->icache.ways;
1068         c->dcache.waysize = dcache_size / c->dcache.ways;
1069
1070         c->icache.sets = c->icache.linesz ?
1071                 icache_size / (c->icache.linesz * c->icache.ways) : 0;
1072         c->dcache.sets = c->dcache.linesz ?
1073                 dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
1074
1075         /*
1076          * R10000 and R12000 P-caches are odd in a positive way.  They're 32kB
1077          * 2-way virtually indexed so normally would suffer from aliases.  So
1078          * normally they'd suffer from aliases but magic in the hardware deals
1079          * with that for us so we don't need to take care ourselves.
1080          */
1081         switch (current_cpu_type()) {
1082         case CPU_20KC:
1083         case CPU_25KF:
1084         case CPU_SB1:
1085         case CPU_SB1A:
1086         case CPU_XLR:
1087                 c->dcache.flags |= MIPS_CACHE_PINDEX;
1088                 break;
1089
1090         case CPU_R10000:
1091         case CPU_R12000:
1092         case CPU_R14000:
1093                 break;
1094
1095         case CPU_M14KC:
1096         case CPU_M14KEC:
1097         case CPU_24K:
1098         case CPU_34K:
1099         case CPU_74K:
1100         case CPU_1004K:
1101                 if (current_cpu_type() == CPU_74K)
1102                         alias_74k_erratum(c);
1103                 if ((read_c0_config7() & (1 << 16))) {
1104                         /* effectively physically indexed dcache,
1105                            thus no virtual aliases. */
1106                         c->dcache.flags |= MIPS_CACHE_PINDEX;
1107                         break;
1108                 }
1109         default:
1110                 if (c->dcache.waysize > PAGE_SIZE)
1111                         c->dcache.flags |= MIPS_CACHE_ALIASES;
1112         }
1113
1114         switch (current_cpu_type()) {
1115         case CPU_20KC:
1116                 /*
1117                  * Some older 20Kc chips doesn't have the 'VI' bit in
1118                  * the config register.
1119                  */
1120                 c->icache.flags |= MIPS_CACHE_VTAG;
1121                 break;
1122
1123         case CPU_ALCHEMY:
1124                 c->icache.flags |= MIPS_CACHE_IC_F_DC;
1125                 break;
1126
1127         case CPU_LOONGSON2:
1128                 /*
1129                  * LOONGSON2 has 4 way icache, but when using indexed cache op,
1130                  * one op will act on all 4 ways
1131                  */
1132                 c->icache.ways = 1;
1133         }
1134
1135         printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
1136                icache_size >> 10,
1137                c->icache.flags & MIPS_CACHE_VTAG ? "VIVT" : "VIPT",
1138                way_string[c->icache.ways], c->icache.linesz);
1139
1140         printk("Primary data cache %ldkB, %s, %s, %s, linesize %d bytes\n",
1141                dcache_size >> 10, way_string[c->dcache.ways],
1142                (c->dcache.flags & MIPS_CACHE_PINDEX) ? "PIPT" : "VIPT",
1143                (c->dcache.flags & MIPS_CACHE_ALIASES) ?
1144                         "cache aliases" : "no aliases",
1145                c->dcache.linesz);
1146 }
1147
1148 /*
1149  * If you even _breathe_ on this function, look at the gcc output and make sure
1150  * it does not pop things on and off the stack for the cache sizing loop that
1151  * executes in KSEG1 space or else you will crash and burn badly.  You have
1152  * been warned.
1153  */
1154 static int probe_scache(void)
1155 {
1156         unsigned long flags, addr, begin, end, pow2;
1157         unsigned int config = read_c0_config();
1158         struct cpuinfo_mips *c = &current_cpu_data;
1159
1160         if (config & CONF_SC)
1161                 return 0;
1162
1163         begin = (unsigned long) &_stext;
1164         begin &= ~((4 * 1024 * 1024) - 1);
1165         end = begin + (4 * 1024 * 1024);
1166
1167         /*
1168          * This is such a bitch, you'd think they would make it easy to do
1169          * this.  Away you daemons of stupidity!
1170          */
1171         local_irq_save(flags);
1172
1173         /* Fill each size-multiple cache line with a valid tag. */
1174         pow2 = (64 * 1024);
1175         for (addr = begin; addr < end; addr = (begin + pow2)) {
1176                 unsigned long *p = (unsigned long *) addr;
1177                 __asm__ __volatile__("nop" : : "r" (*p)); /* whee... */
1178                 pow2 <<= 1;
1179         }
1180
1181         /* Load first line with zero (therefore invalid) tag. */
1182         write_c0_taglo(0);
1183         write_c0_taghi(0);
1184         __asm__ __volatile__("nop; nop; nop; nop;"); /* avoid the hazard */
1185         cache_op(Index_Store_Tag_I, begin);
1186         cache_op(Index_Store_Tag_D, begin);
1187         cache_op(Index_Store_Tag_SD, begin);
1188
1189         /* Now search for the wrap around point. */
1190         pow2 = (128 * 1024);
1191         for (addr = begin + (128 * 1024); addr < end; addr = begin + pow2) {
1192                 cache_op(Index_Load_Tag_SD, addr);
1193                 __asm__ __volatile__("nop; nop; nop; nop;"); /* hazard... */
1194                 if (!read_c0_taglo())
1195                         break;
1196                 pow2 <<= 1;
1197         }
1198         local_irq_restore(flags);
1199         addr -= begin;
1200
1201         scache_size = addr;
1202         c->scache.linesz = 16 << ((config & R4K_CONF_SB) >> 22);
1203         c->scache.ways = 1;
1204         c->dcache.waybit = 0;           /* does not matter */
1205
1206         return 1;
1207 }
1208
1209 static void __init loongson2_sc_init(void)
1210 {
1211         struct cpuinfo_mips *c = &current_cpu_data;
1212
1213         scache_size = 512*1024;
1214         c->scache.linesz = 32;
1215         c->scache.ways = 4;
1216         c->scache.waybit = 0;
1217         c->scache.waysize = scache_size / (c->scache.ways);
1218         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1219         pr_info("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1220                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1221
1222         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1223 }
1224
1225 extern int r5k_sc_init(void);
1226 extern int rm7k_sc_init(void);
1227 extern int mips_sc_init(void);
1228
1229 static void setup_scache(void)
1230 {
1231         struct cpuinfo_mips *c = &current_cpu_data;
1232         unsigned int config = read_c0_config();
1233         int sc_present = 0;
1234
1235         /*
1236          * Do the probing thing on R4000SC and R4400SC processors.  Other
1237          * processors don't have a S-cache that would be relevant to the
1238          * Linux memory management.
1239          */
1240         switch (current_cpu_type()) {
1241         case CPU_R4000SC:
1242         case CPU_R4000MC:
1243         case CPU_R4400SC:
1244         case CPU_R4400MC:
1245                 sc_present = run_uncached(probe_scache);
1246                 if (sc_present)
1247                         c->options |= MIPS_CPU_CACHE_CDEX_S;
1248                 break;
1249
1250         case CPU_R10000:
1251         case CPU_R12000:
1252         case CPU_R14000:
1253                 scache_size = 0x80000 << ((config & R10K_CONF_SS) >> 16);
1254                 c->scache.linesz = 64 << ((config >> 13) & 1);
1255                 c->scache.ways = 2;
1256                 c->scache.waybit= 0;
1257                 sc_present = 1;
1258                 break;
1259
1260         case CPU_R5000:
1261         case CPU_NEVADA:
1262 #ifdef CONFIG_R5000_CPU_SCACHE
1263                 r5k_sc_init();
1264 #endif
1265                 return;
1266
1267         case CPU_RM7000:
1268 #ifdef CONFIG_RM7000_CPU_SCACHE
1269                 rm7k_sc_init();
1270 #endif
1271                 return;
1272
1273         case CPU_LOONGSON2:
1274                 loongson2_sc_init();
1275                 return;
1276
1277         case CPU_XLP:
1278                 /* don't need to worry about L2, fully coherent */
1279                 return;
1280
1281         default:
1282                 if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
1283                                     MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
1284 #ifdef CONFIG_MIPS_CPU_SCACHE
1285                         if (mips_sc_init ()) {
1286                                 scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
1287                                 printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
1288                                        scache_size >> 10,
1289                                        way_string[c->scache.ways], c->scache.linesz);
1290                         }
1291 #else
1292                         if (!(c->scache.flags & MIPS_CACHE_NOT_PRESENT))
1293                                 panic("Dunno how to handle MIPS32 / MIPS64 second level cache");
1294 #endif
1295                         return;
1296                 }
1297                 sc_present = 0;
1298         }
1299
1300         if (!sc_present)
1301                 return;
1302
1303         /* compute a couple of other cache variables */
1304         c->scache.waysize = scache_size / c->scache.ways;
1305
1306         c->scache.sets = scache_size / (c->scache.linesz * c->scache.ways);
1307
1308         printk("Unified secondary cache %ldkB %s, linesize %d bytes.\n",
1309                scache_size >> 10, way_string[c->scache.ways], c->scache.linesz);
1310
1311         c->options |= MIPS_CPU_INCLUSIVE_CACHES;
1312 }
1313
1314 void au1x00_fixup_config_od(void)
1315 {
1316         /*
1317          * c0_config.od (bit 19) was write only (and read as 0)
1318          * on the early revisions of Alchemy SOCs.  It disables the bus
1319          * transaction overlapping and needs to be set to fix various errata.
1320          */
1321         switch (read_c0_prid()) {
1322         case 0x00030100: /* Au1000 DA */
1323         case 0x00030201: /* Au1000 HA */
1324         case 0x00030202: /* Au1000 HB */
1325         case 0x01030200: /* Au1500 AB */
1326         /*
1327          * Au1100 errata actually keeps silence about this bit, so we set it
1328          * just in case for those revisions that require it to be set according
1329          * to the (now gone) cpu table.
1330          */
1331         case 0x02030200: /* Au1100 AB */
1332         case 0x02030201: /* Au1100 BA */
1333         case 0x02030202: /* Au1100 BC */
1334                 set_c0_config(1 << 19);
1335                 break;
1336         }
1337 }
1338
1339 /* CP0 hazard avoidance. */
1340 #define NXP_BARRIER()                                                   \
1341          __asm__ __volatile__(                                          \
1342         ".set noreorder\n\t"                                            \
1343         "nop; nop; nop; nop; nop; nop;\n\t"                             \
1344         ".set reorder\n\t")
1345
1346 static void nxp_pr4450_fixup_config(void)
1347 {
1348         unsigned long config0;
1349
1350         config0 = read_c0_config();
1351
1352         /* clear all three cache coherency fields */
1353         config0 &= ~(0x7 | (7 << 25) | (7 << 28));
1354         config0 |= (((_page_cachable_default >> _CACHE_SHIFT) <<  0) |
1355                     ((_page_cachable_default >> _CACHE_SHIFT) << 25) |
1356                     ((_page_cachable_default >> _CACHE_SHIFT) << 28));
1357         write_c0_config(config0);
1358         NXP_BARRIER();
1359 }
1360
1361 static int cca = -1;
1362
1363 static int __init cca_setup(char *str)
1364 {
1365         get_option(&str, &cca);
1366
1367         return 0;
1368 }
1369
1370 early_param("cca", cca_setup);
1371
1372 static void coherency_setup(void)
1373 {
1374         if (cca < 0 || cca > 7)
1375                 cca = read_c0_config() & CONF_CM_CMASK;
1376         _page_cachable_default = cca << _CACHE_SHIFT;
1377
1378         pr_debug("Using cache attribute %d\n", cca);
1379         change_c0_config(CONF_CM_CMASK, cca);
1380
1381         /*
1382          * c0_status.cu=0 specifies that updates by the sc instruction use
1383          * the coherency mode specified by the TLB; 1 means cachable
1384          * coherent update on write will be used.  Not all processors have
1385          * this bit and; some wire it to zero, others like Toshiba had the
1386          * silly idea of putting something else there ...
1387          */
1388         switch (current_cpu_type()) {
1389         case CPU_R4000PC:
1390         case CPU_R4000SC:
1391         case CPU_R4000MC:
1392         case CPU_R4400PC:
1393         case CPU_R4400SC:
1394         case CPU_R4400MC:
1395                 clear_c0_config(CONF_CU);
1396                 break;
1397         /*
1398          * We need to catch the early Alchemy SOCs with
1399          * the write-only co_config.od bit and set it back to one on:
1400          * Au1000 rev DA, HA, HB;  Au1100 AB, BA, BC, Au1500 AB
1401          */
1402         case CPU_ALCHEMY:
1403                 au1x00_fixup_config_od();
1404                 break;
1405
1406         case PRID_IMP_PR4450:
1407                 nxp_pr4450_fixup_config();
1408                 break;
1409         }
1410 }
1411
1412 static void r4k_cache_error_setup(void)
1413 {
1414         extern char __weak except_vec2_generic;
1415         extern char __weak except_vec2_sb1;
1416
1417         switch (current_cpu_type()) {
1418         case CPU_SB1:
1419         case CPU_SB1A:
1420                 set_uncached_handler(0x100, &except_vec2_sb1, 0x80);
1421                 break;
1422
1423         default:
1424                 set_uncached_handler(0x100, &except_vec2_generic, 0x80);
1425                 break;
1426         }
1427 }
1428
1429 void r4k_cache_init(void)
1430 {
1431         extern void build_clear_page(void);
1432         extern void build_copy_page(void);
1433         struct cpuinfo_mips *c = &current_cpu_data;
1434
1435         probe_pcache();
1436         setup_scache();
1437
1438         r4k_blast_dcache_page_setup();
1439         r4k_blast_dcache_page_indexed_setup();
1440         r4k_blast_dcache_setup();
1441         r4k_blast_icache_page_setup();
1442         r4k_blast_icache_page_indexed_setup();
1443         r4k_blast_icache_setup();
1444         r4k_blast_scache_page_setup();
1445         r4k_blast_scache_page_indexed_setup();
1446         r4k_blast_scache_setup();
1447
1448         /*
1449          * Some MIPS32 and MIPS64 processors have physically indexed caches.
1450          * This code supports virtually indexed processors and will be
1451          * unnecessarily inefficient on physically indexed processors.
1452          */
1453         if (c->dcache.linesz)
1454                 shm_align_mask = max_t( unsigned long,
1455                                         c->dcache.sets * c->dcache.linesz - 1,
1456                                         PAGE_SIZE - 1);
1457         else
1458                 shm_align_mask = PAGE_SIZE-1;
1459
1460         __flush_cache_vmap      = r4k__flush_cache_vmap;
1461         __flush_cache_vunmap    = r4k__flush_cache_vunmap;
1462
1463         flush_cache_all         = cache_noop;
1464         __flush_cache_all       = r4k___flush_cache_all;
1465         flush_cache_mm          = r4k_flush_cache_mm;
1466         flush_cache_page        = r4k_flush_cache_page;
1467         flush_cache_range       = r4k_flush_cache_range;
1468
1469         __flush_kernel_vmap_range = r4k_flush_kernel_vmap_range;
1470
1471         flush_cache_sigtramp    = r4k_flush_cache_sigtramp;
1472         flush_icache_all        = r4k_flush_icache_all;
1473         local_flush_data_cache_page     = local_r4k_flush_data_cache_page;
1474         flush_data_cache_page   = r4k_flush_data_cache_page;
1475         flush_icache_range      = r4k_flush_icache_range;
1476         local_flush_icache_range        = local_r4k_flush_icache_range;
1477
1478 #if defined(CONFIG_DMA_NONCOHERENT)
1479         if (coherentio) {
1480                 _dma_cache_wback_inv    = (void *)cache_noop;
1481                 _dma_cache_wback        = (void *)cache_noop;
1482                 _dma_cache_inv          = (void *)cache_noop;
1483         } else {
1484                 _dma_cache_wback_inv    = r4k_dma_cache_wback_inv;
1485                 _dma_cache_wback        = r4k_dma_cache_wback_inv;
1486                 _dma_cache_inv          = r4k_dma_cache_inv;
1487         }
1488 #endif
1489
1490         build_clear_page();
1491         build_copy_page();
1492
1493         /*
1494          * We want to run CMP kernels on core with and without coherent
1495          * caches. Therefore, do not use CONFIG_MIPS_CMP to decide whether
1496          * or not to flush caches.
1497          */
1498         local_r4k___flush_cache_all(NULL);
1499
1500         coherency_setup();
1501         board_cache_error_setup = r4k_cache_error_setup;
1502 }