arch/mips/mti-malta/malta-int.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Carsten Langgaard, carstenl@mips.com
   7  * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc.
   8  * Copyright (C) 2001 Ralf Baechle
   9  * Copyright (C) 2013 Imagination Technologies Ltd.
  10  *
  11  * Routines for generic manipulation of the interrupts found on the MIPS
  12  * Malta board. The interrupt controller is located in the South Bridge
  13  * a PIIX4 device with two internal 82C95 interrupt controllers.
  14  */
  15 #include <linux/init.h>
  16 #include <linux/irq.h>
  17 #include <linux/irqchip.h>
  18 #include <linux/sched.h>
  19 #include <linux/smp.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/irqchip/mips-gic.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/kernel_stat.h>
  25 #include <linux/kernel.h>
  26 #include <linux/random.h>
  27
  28 #include <asm/traps.h>
  29 #include <asm/i8259.h>
  30 #include <asm/irq_cpu.h>
  31 #include <asm/irq_regs.h>
  32 #include <asm/mips-cm.h>
  33 #include <asm/mips-boards/malta.h>
  34 #include <asm/mips-boards/maltaint.h>
  35 #include <asm/gt64120.h>
  36 #include <asm/mips-boards/generic.h>
  37 #include <asm/mips-boards/msc01_pci.h>
  38 #include <asm/msc01_ic.h>
  39 #include <asm/setup.h>
  40 #include <asm/rtlx.h>
  41
  42 static inline int mips_pcibios_iack(void)
  43 {
  44         int irq;
  45
  46         /*
  47          * Determine highest priority pending interrupt by performing
  48          * a PCI Interrupt Acknowledge cycle.
  49          */
  50         switch (mips_revision_sconid) {
  51         case MIPS_REVISION_SCON_SOCIT:
  52         case MIPS_REVISION_SCON_ROCIT:
  53         case MIPS_REVISION_SCON_SOCITSC:
  54         case MIPS_REVISION_SCON_SOCITSCP:
  55                 MSC_READ(MSC01_PCI_IACK, irq);
  56                 irq &= 0xff;
  57                 break;
  58         case MIPS_REVISION_SCON_GT64120:
  59                 irq = GT_READ(GT_PCI0_IACK_OFS);
  60                 irq &= 0xff;
  61                 break;
  62         case MIPS_REVISION_SCON_BONITO:
  63                 /* The following will generate a PCI IACK cycle on the
  64                  * Bonito controller. It's a little bit kludgy, but it
  65                  * was the easiest way to implement it in hardware at
  66                  * the given time.
  67                  */
  68                 BONITO_PCIMAP_CFG = 0x20000;
  69
  70                 /* Flush Bonito register block */
  71                 (void) BONITO_PCIMAP_CFG;
  72                 iob();    /* sync */
  73
  74                 irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg);
  75                 iob();    /* sync */
  76                 irq &= 0xff;
  77                 BONITO_PCIMAP_CFG = 0;
  78                 break;
  79         default:
  80                 pr_emerg("Unknown system controller.\n");
  81                 return -1;
  82         }
  83         return irq;
  84 }
  85
  86 static void corehi_irqdispatch(void)
  87 {
  88         unsigned int intedge, intsteer, pcicmd, pcibadaddr;
  89         unsigned int pcimstat, intisr, inten, intpol;
  90         unsigned int intrcause, datalo, datahi;
  91         struct pt_regs *regs = get_irq_regs();
  92
  93         pr_emerg("CoreHI interrupt, shouldn't happen, we die here!\n");
  94         pr_emerg("epc    : %08lx\nStatus: %08lx\n"
  95                  "Cause : %08lx\nbadVaddr : %08lx\n",
  96                  regs->cp0_epc, regs->cp0_status,
  97                  regs->cp0_cause, regs->cp0_badvaddr);
  98
  99         /* Read all the registers and then print them as there is a
 100            problem with interspersed printk's upsetting the Bonito controller.
 101            Do it for the others too.
 102         */
 103
 104         switch (mips_revision_sconid) {
 105         case MIPS_REVISION_SCON_SOCIT:
 106         case MIPS_REVISION_SCON_ROCIT:
 107         case MIPS_REVISION_SCON_SOCITSC:
 108         case MIPS_REVISION_SCON_SOCITSCP:
 109                 ll_msc_irq();
 110                 break;
 111         case MIPS_REVISION_SCON_GT64120:
 112                 intrcause = GT_READ(GT_INTRCAUSE_OFS);
 113                 datalo = GT_READ(GT_CPUERR_ADDRLO_OFS);
 114                 datahi = GT_READ(GT_CPUERR_ADDRHI_OFS);
 115                 pr_emerg("GT_INTRCAUSE = %08x\n", intrcause);
 116                 pr_emerg("GT_CPUERR_ADDR = %02x%08x\n",
 117                                 datahi, datalo);
 118                 break;
 119         case MIPS_REVISION_SCON_BONITO:
 120                 pcibadaddr = BONITO_PCIBADADDR;
 121                 pcimstat = BONITO_PCIMSTAT;
 122                 intisr = BONITO_INTISR;
 123                 inten = BONITO_INTEN;
 124                 intpol = BONITO_INTPOL;
 125                 intedge = BONITO_INTEDGE;
 126                 intsteer = BONITO_INTSTEER;
 127                 pcicmd = BONITO_PCICMD;
 128                 pr_emerg("BONITO_INTISR = %08x\n", intisr);
 129                 pr_emerg("BONITO_INTEN = %08x\n", inten);
 130                 pr_emerg("BONITO_INTPOL = %08x\n", intpol);
 131                 pr_emerg("BONITO_INTEDGE = %08x\n", intedge);
 132                 pr_emerg("BONITO_INTSTEER = %08x\n", intsteer);
 133                 pr_emerg("BONITO_PCICMD = %08x\n", pcicmd);
 134                 pr_emerg("BONITO_PCIBADADDR = %08x\n", pcibadaddr);
 135                 pr_emerg("BONITO_PCIMSTAT = %08x\n", pcimstat);
 136                 break;
 137         }
 138
 139         die("CoreHi interrupt", regs);
 140 }
 141
 142 static irqreturn_t corehi_handler(int irq, void *dev_id)
 143 {
 144         corehi_irqdispatch();
 145         return IRQ_HANDLED;
 146 }
 147
 148 static struct irqaction corehi_irqaction = {
 149         .handler = corehi_handler,
 150         .name = "CoreHi",
 151         .flags = IRQF_NO_THREAD,
 152 };
 153
 154 static msc_irqmap_t msc_irqmap[] __initdata = {
 155         {MSC01C_INT_TMR,                MSC01_IRQ_EDGE, 0},
 156         {MSC01C_INT_PCI,                MSC01_IRQ_LEVEL, 0},
 157 };
 158 static int msc_nr_irqs __initdata = ARRAY_SIZE(msc_irqmap);
 159
 160 static msc_irqmap_t msc_eicirqmap[] __initdata = {
 161         {MSC01E_INT_SW0,                MSC01_IRQ_LEVEL, 0},
 162         {MSC01E_INT_SW1,                MSC01_IRQ_LEVEL, 0},
 163         {MSC01E_INT_I8259A,             MSC01_IRQ_LEVEL, 0},
 164         {MSC01E_INT_SMI,                MSC01_IRQ_LEVEL, 0},
 165         {MSC01E_INT_COREHI,             MSC01_IRQ_LEVEL, 0},
 166         {MSC01E_INT_CORELO,             MSC01_IRQ_LEVEL, 0},
 167         {MSC01E_INT_TMR,                MSC01_IRQ_EDGE, 0},
 168         {MSC01E_INT_PCI,                MSC01_IRQ_LEVEL, 0},
 169         {MSC01E_INT_PERFCTR,            MSC01_IRQ_LEVEL, 0},
 170         {MSC01E_INT_CPUCTR,             MSC01_IRQ_LEVEL, 0}
 171 };
 172
 173 static int msc_nr_eicirqs __initdata = ARRAY_SIZE(msc_eicirqmap);
 174
 175 void __init arch_init_irq(void)
 176 {
 177         int corehi_irq;
 178
 179         /*
 180          * Preallocate the i8259's expected virq's here. Since irqchip_init()
 181          * will probe the irqchips in hierarchial order, i8259 is probed last.
 182          * If anything allocates a virq before the i8259 is probed, it will
 183          * be given one of the i8259's expected range and consequently setup
 184          * of the i8259 will fail.
 185          */
 186         WARN(irq_alloc_descs(I8259A_IRQ_BASE, I8259A_IRQ_BASE,
 187                             16, numa_node_id()) < 0,
 188                 "Cannot reserve i8259 virqs at IRQ%d\n", I8259A_IRQ_BASE);
 189
 190         i8259_set_poll(mips_pcibios_iack);
 191         irqchip_init();
 192
 193         switch (mips_revision_sconid) {
 194         case MIPS_REVISION_SCON_SOCIT:
 195         case MIPS_REVISION_SCON_ROCIT:
 196                 if (cpu_has_veic)
 197                         init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
 198                                         MSC01E_INT_BASE, msc_eicirqmap,
 199                                         msc_nr_eicirqs);
 200                 else
 201                         init_msc_irqs(MIPS_MSC01_IC_REG_BASE,
 202                                         MSC01C_INT_BASE, msc_irqmap,
 203                                         msc_nr_irqs);
 204                 break;
 205
 206         case MIPS_REVISION_SCON_SOCITSC:
 207         case MIPS_REVISION_SCON_SOCITSCP:
 208                 if (cpu_has_veic)
 209                         init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
 210                                         MSC01E_INT_BASE, msc_eicirqmap,
 211                                         msc_nr_eicirqs);
 212                 else
 213                         init_msc_irqs(MIPS_SOCITSC_IC_REG_BASE,
 214                                         MSC01C_INT_BASE, msc_irqmap,
 215                                         msc_nr_irqs);
 216         }
 217
 218         if (gic_present) {
 219                 corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
 220         } else if (cpu_has_veic) {
 221                 set_vi_handler(MSC01E_INT_COREHI, corehi_irqdispatch);
 222                 corehi_irq = MSC01E_INT_BASE + MSC01E_INT_COREHI;
 223         } else {
 224                 corehi_irq = MIPS_CPU_IRQ_BASE + MIPSCPU_INT_COREHI;
 225         }
 226
 227         setup_irq(corehi_irq, &corehi_irqaction);
 228 }