2 * This file contains the 64-bit "server" PowerPC variant
3 * of the low level exception handling including exception
4 * vectors, exception return, part of the slb and stab
5 * handling and other fixed offset specific things.
7 * This file is meant to be #included from head_64.S due to
8 * position dependent assembly.
10 * Most of this originates from head_64.S and thus has the same
15 #include <asm/hw_irq.h>
16 #include <asm/exception-64s.h>
17 #include <asm/ptrace.h>
18 #include <asm/cpuidle.h>
19 #include <asm/head-64.h>
22 * There are a few constraints to be concerned with.
23 * - Real mode exceptions code/data must be located at their physical location.
24 * - Virtual mode exceptions must be mapped at their 0xc000... location.
25 * - Fixed location code must not call directly beyond the __end_interrupts
26 * area when built with CONFIG_RELOCATABLE. LOAD_HANDLER / bctr sequence
28 * - LOAD_HANDLER targets must be within first 64K of physical 0 /
30 * - Conditional branch targets must be within +/-32K of caller.
32 * "Virtual exceptions" run with relocation on (MSR_IR=1, MSR_DR=1), and
33 * therefore don't have to run in physically located code or rfid to
34 * virtual mode kernel code. However on relocatable kernels they do have
35 * to branch to KERNELBASE offset because the rest of the kernel (outside
36 * the exception vectors) may be located elsewhere.
38 * Virtual exceptions correspond with physical, except their entry points
39 * are offset by 0xc000000000000000 and also tend to get an added 0x4000
40 * offset applied. Virtual exceptions are enabled with the Alternate
41 * Interrupt Location (AIL) bit set in the LPCR. However this does not
42 * guarantee they will be delivered virtually. Some conditions (see the ISA)
43 * cause exceptions to be delivered in real mode.
45 * It's impossible to receive interrupts below 0x300 via AIL.
47 * KVM: None of the virtual exceptions are from the guest. Anything that
48 * escalated to HV=1 from HV=0 is delivered via real mode handlers.
51 * We layout physical memory as follows:
52 * 0x0000 - 0x00ff : Secondary processor spin code
53 * 0x0100 - 0x18ff : Real mode pSeries interrupt vectors
54 * 0x1900 - 0x3fff : Real mode trampolines
55 * 0x4000 - 0x58ff : Relon (IR=1,DR=1) mode pSeries interrupt vectors
56 * 0x5900 - 0x6fff : Relon mode trampolines
57 * 0x7000 - 0x7fff : FWNMI data area
58 * 0x8000 - .... : Common interrupt handlers, remaining early
59 * setup code, rest of kernel.
61 * We could reclaim 0x4000-0x42ff for real mode trampolines if the space
62 * is necessary. Until then it's more consistent to explicitly put VIRT_NONE
65 OPEN_FIXED_SECTION(real_vectors, 0x0100, 0x1900)
66 OPEN_FIXED_SECTION(real_trampolines, 0x1900, 0x4000)
67 OPEN_FIXED_SECTION(virt_vectors, 0x4000, 0x5900)
68 OPEN_FIXED_SECTION(virt_trampolines, 0x5900, 0x7000)
69 #if defined(CONFIG_PPC_PSERIES) || defined(CONFIG_PPC_POWERNV)
71 * Data area reserved for FWNMI option.
72 * This address (0x7000) is fixed by the RPA.
73 * pseries and powernv need to keep the whole page from
74 * 0x7000 to 0x8000 free for use by the firmware
76 ZERO_FIXED_SECTION(fwnmi_page, 0x7000, 0x8000)
77 OPEN_TEXT_SECTION(0x8000)
79 OPEN_TEXT_SECTION(0x7000)
82 USE_FIXED_SECTION(real_vectors)
85 * This is the start of the interrupt handlers for pSeries
86 * This code runs with relocation off.
87 * Code from here to __end_interrupts gets copied down to real
88 * address 0x100 when we are running a relocatable kernel.
89 * Therefore any relative branches in this section must only
90 * branch to labels in this section.
92 .globl __start_interrupts
95 /* No virt vectors corresponding with 0x0..0x100 */
96 EXC_VIRT_NONE(0x4000, 0x100)
99 #ifdef CONFIG_PPC_P7_NAP
101 * If running native on arch 2.06 or later, check if we are waking up
102 * from nap/sleep/winkle, and branch to idle handler.
104 #define IDLETEST(n) \
105 BEGIN_FTR_SECTION ; \
106 mfspr r10,SPRN_SRR1 ; \
107 rlwinm. r10,r10,47-31,30,31 ; \
110 BRANCH_TO_COMMON(r10, system_reset_idle_common) ; \
112 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
114 #define IDLETEST NOTEST
117 EXC_REAL_BEGIN(system_reset, 0x100, 0x100)
119 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD,
122 EXC_REAL_END(system_reset, 0x100, 0x100)
123 EXC_VIRT_NONE(0x4100, 0x100)
125 #ifdef CONFIG_PPC_P7_NAP
126 EXC_COMMON_BEGIN(system_reset_idle_common)
127 b pnv_powersave_wakeup
130 EXC_COMMON(system_reset_common, 0x100, system_reset_exception)
132 #ifdef CONFIG_PPC_PSERIES
134 * Vectors for the FWNMI option. Share common code.
136 TRAMP_REAL_BEGIN(system_reset_fwnmi)
137 SET_SCRATCH0(r13) /* save r13 */
138 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, system_reset_common, EXC_STD,
140 #endif /* CONFIG_PPC_PSERIES */
143 EXC_REAL_BEGIN(machine_check, 0x200, 0x100)
144 /* This is moved out of line as it can be patched by FW, but
145 * some code path might still want to branch into the original
148 SET_SCRATCH0(r13) /* save r13 */
149 EXCEPTION_PROLOG_0(PACA_EXMC)
151 b machine_check_powernv_early
153 b machine_check_pSeries_0
154 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
155 EXC_REAL_END(machine_check, 0x200, 0x100)
156 EXC_VIRT_NONE(0x4200, 0x100)
157 TRAMP_REAL_BEGIN(machine_check_powernv_early)
159 EXCEPTION_PROLOG_1(PACA_EXMC, NOTEST, 0x200)
164 * Original R9 to R13 is saved on PACA_EXMC
166 * Switch to mc_emergency stack and handle re-entrancy (we limit
167 * the nested MCE upto level 4 to avoid stack overflow).
168 * Save MCE registers srr1, srr0, dar and dsisr and then set ME=1
170 * We use paca->in_mce to check whether this is the first entry or
171 * nested machine check. We increment paca->in_mce to track nested
174 * If this is the first entry then set stack pointer to
175 * paca->mc_emergency_sp, otherwise r1 is already pointing to
176 * stack frame on mc_emergency stack.
178 * NOTE: We are here with MSR_ME=0 (off), which means we risk a
179 * checkstop if we get another machine check exception before we do
180 * rfid with MSR_ME=1.
182 * This interrupt can wake directly from idle. If that is the case,
183 * the machine check is handled then the idle wakeup code is called
184 * to restore state. In that case, the POWER9 DD1 idle PACA workaround
185 * is not applied in the early machine check code, which will cause
188 mr r11,r1 /* Save r1 */
189 lhz r10,PACA_IN_MCE(r13)
190 cmpwi r10,0 /* Are we in nested machine check */
191 bne 0f /* Yes, we are. */
192 /* First machine check entry */
193 ld r1,PACAMCEMERGSP(r13) /* Use MC emergency stack */
194 0: subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
195 addi r10,r10,1 /* increment paca->in_mce */
196 sth r10,PACA_IN_MCE(r13)
197 /* Limit nested MCE to level 4 to avoid stack overflow */
199 bgt 2f /* Check if we hit limit of 4 */
200 std r11,GPR1(r1) /* Save r1 on the stack. */
201 std r11,0(r1) /* make stack chain pointer */
202 mfspr r11,SPRN_SRR0 /* Save SRR0 */
204 mfspr r11,SPRN_SRR1 /* Save SRR1 */
206 mfspr r11,SPRN_DAR /* Save DAR */
208 mfspr r11,SPRN_DSISR /* Save DSISR */
210 std r9,_CCR(r1) /* Save CR in stackframe */
211 /* Save r9 through r13 from EXMC save area to stack frame. */
212 EXCEPTION_PROLOG_COMMON_2(PACA_EXMC)
213 mfmsr r11 /* get MSR value */
214 ori r11,r11,MSR_ME /* turn on ME bit */
215 ori r11,r11,MSR_RI /* turn on RI bit */
216 LOAD_HANDLER(r12, machine_check_handle_early)
217 1: mtspr SPRN_SRR0,r12
220 b . /* prevent speculative execution */
222 /* Stack overflow. Stay on emergency stack and panic.
223 * Keep the ME bit off while panic-ing, so that if we hit
224 * another machine check we checkstop.
226 addi r1,r1,INT_FRAME_SIZE /* go back to previous stack frame */
228 LOAD_HANDLER(r12, unrecover_mce)
230 andc r11,r11,r10 /* Turn off MSR_ME */
232 b . /* prevent speculative execution */
233 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
235 TRAMP_REAL_BEGIN(machine_check_pSeries)
236 .globl machine_check_fwnmi
238 SET_SCRATCH0(r13) /* save r13 */
239 EXCEPTION_PROLOG_0(PACA_EXMC)
240 machine_check_pSeries_0:
241 EXCEPTION_PROLOG_1(PACA_EXMC, KVMTEST_PR, 0x200)
243 * MSR_RI is not enabled, because PACA_EXMC is being used, so a
244 * nested machine check corrupts it. machine_check_common enables
247 EXCEPTION_PROLOG_PSERIES_1_NORI(machine_check_common, EXC_STD)
249 TRAMP_KVM_SKIP(PACA_EXMC, 0x200)
251 EXC_COMMON_BEGIN(machine_check_common)
253 * Machine check is different because we use a different
254 * save area: PACA_EXMC instead of PACA_EXGEN.
257 std r10,PACA_EXMC+EX_DAR(r13)
259 stw r10,PACA_EXMC+EX_DSISR(r13)
260 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
262 RECONCILE_IRQ_STATE(r10, r11)
263 ld r3,PACA_EXMC+EX_DAR(r13)
264 lwz r4,PACA_EXMC+EX_DSISR(r13)
265 /* Enable MSR_RI when finished with PACA_EXMC */
271 addi r3,r1,STACK_FRAME_OVERHEAD
272 bl machine_check_exception
275 #define MACHINE_CHECK_HANDLER_WINDUP \
276 /* Clear MSR_RI before setting SRR0 and SRR1. */\
278 mfmsr r9; /* get MSR value */ \
280 mtmsrd r9,1; /* Clear MSR_RI */ \
281 /* Move original SRR0 and SRR1 into the respective regs */ \
283 mtspr SPRN_SRR1,r9; \
285 mtspr SPRN_SRR0,r3; \
297 /* Decrement paca->in_mce. */ \
298 lhz r12,PACA_IN_MCE(r13); \
300 sth r12,PACA_IN_MCE(r13); \
302 REST_2GPRS(12, r1); \
303 /* restore original r1. */ \
306 #ifdef CONFIG_PPC_P7_NAP
308 * This is an idle wakeup. Low level machine check has already been
309 * done. Queue the event then call the idle code to do the wake up.
311 EXC_COMMON_BEGIN(machine_check_idle_common)
312 bl machine_check_queue_event
315 * We have not used any non-volatile GPRs here, and as a rule
316 * most exception code including machine check does not.
317 * Therefore PACA_NAPSTATELOST does not need to be set. Idle
318 * wakeup will restore volatile registers.
320 * Load the original SRR1 into r3 for pnv_powersave_wakeup_mce.
322 * Then decrement MCE nesting after finishing with the stack.
326 lhz r11,PACA_IN_MCE(r13)
328 sth r11,PACA_IN_MCE(r13)
330 /* Turn off the RI bit because SRR1 is used by idle wakeup code. */
331 /* Recoverability could be improved by reducing the use of SRR1. */
335 b pnv_powersave_wakeup_mce
338 * Handle machine check early in real mode. We come here with
339 * ME=1, MMU (IR=0 and DR=0) off and using MC emergency stack.
341 EXC_COMMON_BEGIN(machine_check_handle_early)
342 std r0,GPR0(r1) /* Save r0 */
343 EXCEPTION_PROLOG_COMMON_3(0x200)
345 addi r3,r1,STACK_FRAME_OVERHEAD
346 bl machine_check_early
347 std r3,RESULT(r1) /* Save result */
350 #ifdef CONFIG_PPC_P7_NAP
352 * Check if thread was in power saving mode. We come here when any
353 * of the following is true:
354 * a. thread wasn't in power saving mode
355 * b. thread was in power saving mode with no state loss,
356 * supervisor state loss or hypervisor state loss.
358 * Go back to nap/sleep/winkle mode again if (b) is true.
361 rlwinm. r11,r12,47-31,30,31
363 BRANCH_TO_COMMON(r10, machine_check_idle_common)
365 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
369 * Check if we are coming from hypervisor userspace. If yes then we
370 * continue in host kernel in V mode to deliver the MC event.
372 rldicl. r11,r12,4,63 /* See if MC hit while in HV mode. */
374 andi. r11,r12,MSR_PR /* See if coming from user. */
375 bne 9f /* continue in V mode if we are. */
378 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
380 * We are coming from kernel context. Check if we are coming from
381 * guest. if yes, then we can continue. We will fall through
382 * do_kvm_200->kvmppc_interrupt to deliver the MC event to guest.
384 lbz r11,HSTATE_IN_GUEST(r13)
385 cmpwi r11,0 /* Check if coming from guest */
386 bne 9f /* continue if we are. */
389 * At this point we are not sure about what context we come from.
390 * Queue up the MCE event and return from the interrupt.
391 * But before that, check if this is an un-recoverable exception.
392 * If yes, then stay on emergency stack and panic.
396 1: mfspr r11,SPRN_SRR0
397 LOAD_HANDLER(r10,unrecover_mce)
401 * We are going down. But there are chances that we might get hit by
402 * another MCE during panic path and we may run into unstable state
403 * with no way out. Hence, turn ME bit off while going down, so that
404 * when another MCE is hit during panic path, system will checkstop
405 * and hypervisor will get restarted cleanly by SP.
408 andc r10,r10,r3 /* Turn off MSR_ME */
414 * Check if we have successfully handled/recovered from error, if not
415 * then stay on emergency stack and panic.
417 ld r3,RESULT(r1) /* Load result */
418 cmpdi r3,0 /* see if we handled MCE successfully */
420 beq 1b /* if !handled then panic */
422 * Return from MC interrupt.
423 * Queue up the MCE event so that we can log it later, while
424 * returning from kernel or opal call.
426 bl machine_check_queue_event
427 MACHINE_CHECK_HANDLER_WINDUP
430 /* Deliver the machine check to host kernel in V mode. */
431 MACHINE_CHECK_HANDLER_WINDUP
432 b machine_check_pSeries
434 EXC_COMMON_BEGIN(unrecover_mce)
435 /* Invoke machine_check_exception to print MCE event and panic. */
436 addi r3,r1,STACK_FRAME_OVERHEAD
437 bl machine_check_exception
439 * We will not reach here. Even if we did, there is no way out. Call
440 * unrecoverable_exception and die.
442 1: addi r3,r1,STACK_FRAME_OVERHEAD
443 bl unrecoverable_exception
447 EXC_REAL(data_access, 0x300, 0x80)
448 EXC_VIRT(data_access, 0x4300, 0x80, 0x300)
449 TRAMP_KVM_SKIP(PACA_EXGEN, 0x300)
451 EXC_COMMON_BEGIN(data_access_common)
453 * Here r13 points to the paca, r9 contains the saved CR,
454 * SRR0 and SRR1 are saved in r11 and r12,
455 * r9 - r13 are saved in paca->exgen.
458 std r10,PACA_EXGEN+EX_DAR(r13)
460 stw r10,PACA_EXGEN+EX_DSISR(r13)
461 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
462 RECONCILE_IRQ_STATE(r10, r11)
464 ld r3,PACA_EXGEN+EX_DAR(r13)
465 lwz r4,PACA_EXGEN+EX_DSISR(r13)
469 BEGIN_MMU_FTR_SECTION
470 b do_hash_page /* Try to handle as hpte fault */
473 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
476 EXC_REAL_BEGIN(data_access_slb, 0x380, 0x80)
478 EXCEPTION_PROLOG_0(PACA_EXSLB)
479 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x380)
480 std r3,PACA_EXSLB+EX_R3(r13)
484 #ifndef CONFIG_RELOCATABLE
488 * We can't just use a direct branch to slb_miss_realmode
489 * because the distance from here to there depends on where
490 * the kernel ends up being put.
493 LOAD_HANDLER(r10, slb_miss_realmode)
497 EXC_REAL_END(data_access_slb, 0x380, 0x80)
499 EXC_VIRT_BEGIN(data_access_slb, 0x4380, 0x80)
501 EXCEPTION_PROLOG_0(PACA_EXSLB)
502 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x380)
503 std r3,PACA_EXSLB+EX_R3(r13)
507 #ifndef CONFIG_RELOCATABLE
511 * We can't just use a direct branch to slb_miss_realmode
512 * because the distance from here to there depends on where
513 * the kernel ends up being put.
516 LOAD_HANDLER(r10, slb_miss_realmode)
520 EXC_VIRT_END(data_access_slb, 0x4380, 0x80)
521 TRAMP_KVM_SKIP(PACA_EXSLB, 0x380)
524 EXC_REAL(instruction_access, 0x400, 0x80)
525 EXC_VIRT(instruction_access, 0x4400, 0x80, 0x400)
526 TRAMP_KVM(PACA_EXGEN, 0x400)
528 EXC_COMMON_BEGIN(instruction_access_common)
529 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
530 RECONCILE_IRQ_STATE(r10, r11)
537 BEGIN_MMU_FTR_SECTION
538 b do_hash_page /* Try to handle as hpte fault */
541 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_TYPE_RADIX)
544 EXC_REAL_BEGIN(instruction_access_slb, 0x480, 0x80)
546 EXCEPTION_PROLOG_0(PACA_EXSLB)
547 EXCEPTION_PROLOG_1(PACA_EXSLB, KVMTEST_PR, 0x480)
548 std r3,PACA_EXSLB+EX_R3(r13)
549 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
552 #ifndef CONFIG_RELOCATABLE
556 LOAD_HANDLER(r10, slb_miss_realmode)
560 EXC_REAL_END(instruction_access_slb, 0x480, 0x80)
562 EXC_VIRT_BEGIN(instruction_access_slb, 0x4480, 0x80)
564 EXCEPTION_PROLOG_0(PACA_EXSLB)
565 EXCEPTION_PROLOG_1(PACA_EXSLB, NOTEST, 0x480)
566 std r3,PACA_EXSLB+EX_R3(r13)
567 mfspr r3,SPRN_SRR0 /* SRR0 is faulting address */
570 #ifndef CONFIG_RELOCATABLE
574 LOAD_HANDLER(r10, slb_miss_realmode)
578 EXC_VIRT_END(instruction_access_slb, 0x4480, 0x80)
579 TRAMP_KVM(PACA_EXSLB, 0x480)
582 /* This handler is used by both 0x380 and 0x480 slb miss interrupts */
583 EXC_COMMON_BEGIN(slb_miss_realmode)
585 * r13 points to the PACA, r9 contains the saved CR,
586 * r12 contain the saved SRR1, SRR0 is still ready for return
587 * r3 has the faulting address
588 * r9 - r13 are saved in paca->exslb.
589 * r3 is saved in paca->slb_r3
590 * cr6.eq is set for a D-SLB miss, clear for a I-SLB miss
591 * We assume we aren't going to take any exceptions during this
595 #ifdef CONFIG_RELOCATABLE
599 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
600 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
601 std r3,PACA_EXSLB+EX_DAR(r13)
604 #ifdef CONFIG_PPC_STD_MMU_64
605 BEGIN_MMU_FTR_SECTION
606 bl slb_allocate_realmode
607 END_MMU_FTR_SECTION_IFCLR(MMU_FTR_TYPE_RADIX)
610 ld r10,PACA_EXSLB+EX_LR(r13)
611 ld r3,PACA_EXSLB+EX_R3(r13)
612 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
615 beq 8f /* if bad address, make full stack frame */
617 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
620 /* All done -- return from exception. */
625 mtcrf 0x02,r9 /* I/D indication is in cr6 */
626 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
629 RESTORE_PPR_PACA(PACA_EXSLB, r9)
630 ld r9,PACA_EXSLB+EX_R9(r13)
631 ld r10,PACA_EXSLB+EX_R10(r13)
632 ld r11,PACA_EXSLB+EX_R11(r13)
633 ld r12,PACA_EXSLB+EX_R12(r13)
634 ld r13,PACA_EXSLB+EX_R13(r13)
636 b . /* prevent speculative execution */
638 2: mfspr r11,SPRN_SRR0
639 LOAD_HANDLER(r10,unrecov_slb)
646 8: mfspr r11,SPRN_SRR0
647 LOAD_HANDLER(r10,bad_addr_slb)
654 EXC_COMMON_BEGIN(unrecov_slb)
655 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
656 RECONCILE_IRQ_STATE(r10, r11)
658 1: addi r3,r1,STACK_FRAME_OVERHEAD
659 bl unrecoverable_exception
662 EXC_COMMON_BEGIN(bad_addr_slb)
663 EXCEPTION_PROLOG_COMMON(0x380, PACA_EXSLB)
664 RECONCILE_IRQ_STATE(r10, r11)
665 ld r3, PACA_EXSLB+EX_DAR(r13)
668 li r10, 0x480 /* fix trap number for I-SLB miss */
671 addi r3, r1, STACK_FRAME_OVERHEAD
675 EXC_REAL_BEGIN(hardware_interrupt, 0x500, 0x100)
676 .globl hardware_interrupt_hv;
677 hardware_interrupt_hv:
679 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
680 EXC_HV, SOFTEN_TEST_HV)
682 _MASKABLE_EXCEPTION_PSERIES(0x500, hardware_interrupt_common,
683 EXC_STD, SOFTEN_TEST_PR)
684 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE | CPU_FTR_ARCH_206)
685 EXC_REAL_END(hardware_interrupt, 0x500, 0x100)
687 EXC_VIRT_BEGIN(hardware_interrupt, 0x4500, 0x100)
688 .globl hardware_interrupt_relon_hv;
689 hardware_interrupt_relon_hv:
691 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_HV, SOFTEN_TEST_HV)
693 _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt_common, EXC_STD, SOFTEN_TEST_PR)
694 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
695 EXC_VIRT_END(hardware_interrupt, 0x4500, 0x100)
697 TRAMP_KVM(PACA_EXGEN, 0x500)
698 TRAMP_KVM_HV(PACA_EXGEN, 0x500)
699 EXC_COMMON_ASYNC(hardware_interrupt_common, 0x500, do_IRQ)
702 EXC_REAL(alignment, 0x600, 0x100)
703 EXC_VIRT(alignment, 0x4600, 0x100, 0x600)
704 TRAMP_KVM(PACA_EXGEN, 0x600)
705 EXC_COMMON_BEGIN(alignment_common)
707 std r10,PACA_EXGEN+EX_DAR(r13)
709 stw r10,PACA_EXGEN+EX_DSISR(r13)
710 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
711 ld r3,PACA_EXGEN+EX_DAR(r13)
712 lwz r4,PACA_EXGEN+EX_DSISR(r13)
716 RECONCILE_IRQ_STATE(r10, r11)
717 addi r3,r1,STACK_FRAME_OVERHEAD
718 bl alignment_exception
722 EXC_REAL(program_check, 0x700, 0x100)
723 EXC_VIRT(program_check, 0x4700, 0x100, 0x700)
724 TRAMP_KVM(PACA_EXGEN, 0x700)
725 EXC_COMMON_BEGIN(program_check_common)
726 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
728 RECONCILE_IRQ_STATE(r10, r11)
729 addi r3,r1,STACK_FRAME_OVERHEAD
730 bl program_check_exception
734 EXC_REAL(fp_unavailable, 0x800, 0x100)
735 EXC_VIRT(fp_unavailable, 0x4800, 0x100, 0x800)
736 TRAMP_KVM(PACA_EXGEN, 0x800)
737 EXC_COMMON_BEGIN(fp_unavailable_common)
738 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
739 bne 1f /* if from user, just load it up */
741 RECONCILE_IRQ_STATE(r10, r11)
742 addi r3,r1,STACK_FRAME_OVERHEAD
743 bl kernel_fp_unavailable_exception
746 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
748 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
749 * transaction), go do TM stuff
751 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
753 END_FTR_SECTION_IFSET(CPU_FTR_TM)
756 b fast_exception_return
757 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
758 2: /* User process was in a transaction */
760 RECONCILE_IRQ_STATE(r10, r11)
761 addi r3,r1,STACK_FRAME_OVERHEAD
767 EXC_REAL_MASKABLE(decrementer, 0x900, 0x80)
768 EXC_VIRT_MASKABLE(decrementer, 0x4900, 0x80, 0x900)
769 TRAMP_KVM(PACA_EXGEN, 0x900)
770 EXC_COMMON_ASYNC(decrementer_common, 0x900, timer_interrupt)
773 EXC_REAL_HV(hdecrementer, 0x980, 0x80)
774 EXC_VIRT_HV(hdecrementer, 0x4980, 0x80, 0x980)
775 TRAMP_KVM_HV(PACA_EXGEN, 0x980)
776 EXC_COMMON(hdecrementer_common, 0x980, hdec_interrupt)
779 EXC_REAL_MASKABLE(doorbell_super, 0xa00, 0x100)
780 EXC_VIRT_MASKABLE(doorbell_super, 0x4a00, 0x100, 0xa00)
781 TRAMP_KVM(PACA_EXGEN, 0xa00)
782 #ifdef CONFIG_PPC_DOORBELL
783 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, doorbell_exception)
785 EXC_COMMON_ASYNC(doorbell_super_common, 0xa00, unknown_exception)
789 EXC_REAL(trap_0b, 0xb00, 0x100)
790 EXC_VIRT(trap_0b, 0x4b00, 0x100, 0xb00)
791 TRAMP_KVM(PACA_EXGEN, 0xb00)
792 EXC_COMMON(trap_0b_common, 0xb00, unknown_exception)
794 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
796 * If CONFIG_KVM_BOOK3S_64_HANDLER is set, save the PPR (on systems
797 * that support it) before changing to HMT_MEDIUM. That allows the KVM
798 * code to save that value into the guest state (it is the guest's PPR
799 * value). Otherwise just change to HMT_MEDIUM as userspace has
800 * already saved the PPR.
802 #define SYSCALL_KVMTEST \
805 std r9,PACA_EXGEN+EX_R9(r13); \
806 OPT_GET_SPR(r9, SPRN_PPR, CPU_FTR_HAS_PPR); \
808 std r10,PACA_EXGEN+EX_R10(r13); \
809 OPT_SAVE_REG_TO_PACA(PACA_EXGEN+EX_PPR, r9, CPU_FTR_HAS_PPR); \
815 #define SYSCALL_KVMTEST \
819 #define LOAD_SYSCALL_HANDLER(reg) \
820 __LOAD_HANDLER(reg, system_call_common)
822 /* Syscall routine is used twice, in reloc-off and reloc-on paths */
823 #define SYSCALL_PSERIES_1 \
827 END_FTR_SECTION_IFSET(CPU_FTR_REAL_LE) \
830 mfspr r11,SPRN_SRR0 ; \
833 #define SYSCALL_PSERIES_2_RFID \
834 mfspr r12,SPRN_SRR1 ; \
835 LOAD_SYSCALL_HANDLER(r10) ; \
836 mtspr SPRN_SRR0,r10 ; \
837 ld r10,PACAKMSR(r13) ; \
838 mtspr SPRN_SRR1,r10 ; \
840 b . ; /* prevent speculative execution */
842 #define SYSCALL_PSERIES_3 \
843 /* Fast LE/BE switch system call */ \
844 1: mfspr r12,SPRN_SRR1 ; \
845 xori r12,r12,MSR_LE ; \
846 mtspr SPRN_SRR1,r12 ; \
847 rfid ; /* return to userspace */ \
848 b . ; /* prevent speculative execution */
850 #if defined(CONFIG_RELOCATABLE)
852 * We can't branch directly so we do it via the CTR which
853 * is volatile across system calls.
855 #define SYSCALL_PSERIES_2_DIRECT \
856 LOAD_SYSCALL_HANDLER(r12) ; \
858 mfspr r12,SPRN_SRR1 ; \
863 /* We can branch directly */
864 #define SYSCALL_PSERIES_2_DIRECT \
865 mfspr r12,SPRN_SRR1 ; \
867 mtmsrd r10,1 ; /* Set RI (EE=0) */ \
868 b system_call_common ;
871 EXC_REAL_BEGIN(system_call, 0xc00, 0x100)
874 SYSCALL_PSERIES_2_RFID
876 EXC_REAL_END(system_call, 0xc00, 0x100)
878 EXC_VIRT_BEGIN(system_call, 0x4c00, 0x100)
881 SYSCALL_PSERIES_2_DIRECT
883 EXC_VIRT_END(system_call, 0x4c00, 0x100)
885 TRAMP_KVM(PACA_EXGEN, 0xc00)
888 EXC_REAL(single_step, 0xd00, 0x100)
889 EXC_VIRT(single_step, 0x4d00, 0x100, 0xd00)
890 TRAMP_KVM(PACA_EXGEN, 0xd00)
891 EXC_COMMON(single_step_common, 0xd00, single_step_exception)
893 EXC_REAL_OOL_HV(h_data_storage, 0xe00, 0x20)
894 EXC_VIRT_OOL_HV(h_data_storage, 0x4e00, 0x20, 0xe00)
895 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0xe00)
896 EXC_COMMON_BEGIN(h_data_storage_common)
898 std r10,PACA_EXGEN+EX_DAR(r13)
899 mfspr r10,SPRN_HDSISR
900 stw r10,PACA_EXGEN+EX_DSISR(r13)
901 EXCEPTION_PROLOG_COMMON(0xe00, PACA_EXGEN)
903 RECONCILE_IRQ_STATE(r10, r11)
904 addi r3,r1,STACK_FRAME_OVERHEAD
909 EXC_REAL_OOL_HV(h_instr_storage, 0xe20, 0x20)
910 EXC_VIRT_OOL_HV(h_instr_storage, 0x4e20, 0x20, 0xe20)
911 TRAMP_KVM_HV(PACA_EXGEN, 0xe20)
912 EXC_COMMON(h_instr_storage_common, 0xe20, unknown_exception)
915 EXC_REAL_OOL_HV(emulation_assist, 0xe40, 0x20)
916 EXC_VIRT_OOL_HV(emulation_assist, 0x4e40, 0x20, 0xe40)
917 TRAMP_KVM_HV(PACA_EXGEN, 0xe40)
918 EXC_COMMON(emulation_assist_common, 0xe40, emulation_assist_interrupt)
922 * hmi_exception trampoline is a special case. It jumps to hmi_exception_early
923 * first, and then eventaully from there to the trampoline to get into virtual
926 __EXC_REAL_OOL_HV_DIRECT(hmi_exception, 0xe60, 0x20, hmi_exception_early)
927 __TRAMP_REAL_OOL_MASKABLE_HV(hmi_exception, 0xe60)
928 EXC_VIRT_NONE(0x4e60, 0x20)
929 TRAMP_KVM_HV(PACA_EXGEN, 0xe60)
930 TRAMP_REAL_BEGIN(hmi_exception_early)
931 EXCEPTION_PROLOG_1(PACA_EXGEN, KVMTEST_HV, 0xe60)
932 mr r10,r1 /* Save r1 */
933 ld r1,PACAEMERGSP(r13) /* Use emergency stack for realmode */
934 subi r1,r1,INT_FRAME_SIZE /* alloc stack frame */
935 mfspr r11,SPRN_HSRR0 /* Save HSRR0 */
936 mfspr r12,SPRN_HSRR1 /* Save HSRR1 */
937 EXCEPTION_PROLOG_COMMON_1()
938 EXCEPTION_PROLOG_COMMON_2(PACA_EXGEN)
939 EXCEPTION_PROLOG_COMMON_3(0xe60)
940 addi r3,r1,STACK_FRAME_OVERHEAD
941 BRANCH_LINK_TO_FAR(r4, hmi_exception_realmode)
942 /* Windup the stack. */
943 /* Move original HSRR0 and HSRR1 into the respective regs */
961 /* restore original r1. */
965 * Go to virtual mode and pull the HMI event information from
968 .globl hmi_exception_after_realmode
969 hmi_exception_after_realmode:
971 EXCEPTION_PROLOG_0(PACA_EXGEN)
972 b tramp_real_hmi_exception
974 EXC_COMMON_ASYNC(hmi_exception_common, 0xe60, handle_hmi_exception)
977 EXC_REAL_OOL_MASKABLE_HV(h_doorbell, 0xe80, 0x20)
978 EXC_VIRT_OOL_MASKABLE_HV(h_doorbell, 0x4e80, 0x20, 0xe80)
979 TRAMP_KVM_HV(PACA_EXGEN, 0xe80)
980 #ifdef CONFIG_PPC_DOORBELL
981 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, doorbell_exception)
983 EXC_COMMON_ASYNC(h_doorbell_common, 0xe80, unknown_exception)
987 EXC_REAL_OOL_MASKABLE_HV(h_virt_irq, 0xea0, 0x20)
988 EXC_VIRT_OOL_MASKABLE_HV(h_virt_irq, 0x4ea0, 0x20, 0xea0)
989 TRAMP_KVM_HV(PACA_EXGEN, 0xea0)
990 EXC_COMMON_ASYNC(h_virt_irq_common, 0xea0, do_IRQ)
993 EXC_REAL_NONE(0xec0, 0x20)
994 EXC_VIRT_NONE(0x4ec0, 0x20)
995 EXC_REAL_NONE(0xee0, 0x20)
996 EXC_VIRT_NONE(0x4ee0, 0x20)
999 EXC_REAL_OOL(performance_monitor, 0xf00, 0x20)
1000 EXC_VIRT_OOL(performance_monitor, 0x4f00, 0x20, 0xf00)
1001 TRAMP_KVM(PACA_EXGEN, 0xf00)
1002 EXC_COMMON_ASYNC(performance_monitor_common, 0xf00, performance_monitor_exception)
1005 EXC_REAL_OOL(altivec_unavailable, 0xf20, 0x20)
1006 EXC_VIRT_OOL(altivec_unavailable, 0x4f20, 0x20, 0xf20)
1007 TRAMP_KVM(PACA_EXGEN, 0xf20)
1008 EXC_COMMON_BEGIN(altivec_unavailable_common)
1009 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
1010 #ifdef CONFIG_ALTIVEC
1013 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1014 BEGIN_FTR_SECTION_NESTED(69)
1015 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1016 * transaction), go do TM stuff
1018 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1020 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1023 b fast_exception_return
1024 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1025 2: /* User process was in a transaction */
1027 RECONCILE_IRQ_STATE(r10, r11)
1028 addi r3,r1,STACK_FRAME_OVERHEAD
1029 bl altivec_unavailable_tm
1033 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
1036 RECONCILE_IRQ_STATE(r10, r11)
1037 addi r3,r1,STACK_FRAME_OVERHEAD
1038 bl altivec_unavailable_exception
1042 EXC_REAL_OOL(vsx_unavailable, 0xf40, 0x20)
1043 EXC_VIRT_OOL(vsx_unavailable, 0x4f40, 0x20, 0xf40)
1044 TRAMP_KVM(PACA_EXGEN, 0xf40)
1045 EXC_COMMON_BEGIN(vsx_unavailable_common)
1046 EXCEPTION_PROLOG_COMMON(0xf40, PACA_EXGEN)
1050 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1051 BEGIN_FTR_SECTION_NESTED(69)
1052 /* Test if 2 TM state bits are zero. If non-zero (ie. userspace was in
1053 * transaction), go do TM stuff
1055 rldicl. r0, r12, (64-MSR_TS_LG), (64-2)
1057 END_FTR_SECTION_NESTED(CPU_FTR_TM, CPU_FTR_TM, 69)
1060 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1061 2: /* User process was in a transaction */
1063 RECONCILE_IRQ_STATE(r10, r11)
1064 addi r3,r1,STACK_FRAME_OVERHEAD
1065 bl vsx_unavailable_tm
1069 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
1072 RECONCILE_IRQ_STATE(r10, r11)
1073 addi r3,r1,STACK_FRAME_OVERHEAD
1074 bl vsx_unavailable_exception
1078 EXC_REAL_OOL(facility_unavailable, 0xf60, 0x20)
1079 EXC_VIRT_OOL(facility_unavailable, 0x4f60, 0x20, 0xf60)
1080 TRAMP_KVM(PACA_EXGEN, 0xf60)
1081 EXC_COMMON(facility_unavailable_common, 0xf60, facility_unavailable_exception)
1084 EXC_REAL_OOL_HV(h_facility_unavailable, 0xf80, 0x20)
1085 EXC_VIRT_OOL_HV(h_facility_unavailable, 0x4f80, 0x20, 0xf80)
1086 TRAMP_KVM_HV(PACA_EXGEN, 0xf80)
1087 EXC_COMMON(h_facility_unavailable_common, 0xf80, facility_unavailable_exception)
1090 EXC_REAL_NONE(0xfa0, 0x20)
1091 EXC_VIRT_NONE(0x4fa0, 0x20)
1092 EXC_REAL_NONE(0xfc0, 0x20)
1093 EXC_VIRT_NONE(0x4fc0, 0x20)
1094 EXC_REAL_NONE(0xfe0, 0x20)
1095 EXC_VIRT_NONE(0x4fe0, 0x20)
1097 EXC_REAL_NONE(0x1000, 0x100)
1098 EXC_VIRT_NONE(0x5000, 0x100)
1099 EXC_REAL_NONE(0x1100, 0x100)
1100 EXC_VIRT_NONE(0x5100, 0x100)
1102 #ifdef CONFIG_CBE_RAS
1103 EXC_REAL_HV(cbe_system_error, 0x1200, 0x100)
1104 EXC_VIRT_NONE(0x5200, 0x100)
1105 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1200)
1106 EXC_COMMON(cbe_system_error_common, 0x1200, cbe_system_error_exception)
1107 #else /* CONFIG_CBE_RAS */
1108 EXC_REAL_NONE(0x1200, 0x100)
1109 EXC_VIRT_NONE(0x5200, 0x100)
1113 EXC_REAL(instruction_breakpoint, 0x1300, 0x100)
1114 EXC_VIRT(instruction_breakpoint, 0x5300, 0x100, 0x1300)
1115 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1300)
1116 EXC_COMMON(instruction_breakpoint_common, 0x1300, instruction_breakpoint_exception)
1118 EXC_REAL_NONE(0x1400, 0x100)
1119 EXC_VIRT_NONE(0x5400, 0x100)
1121 EXC_REAL_BEGIN(denorm_exception_hv, 0x1500, 0x100)
1122 mtspr SPRN_SPRG_HSCRATCH0,r13
1123 EXCEPTION_PROLOG_0(PACA_EXGEN)
1124 EXCEPTION_PROLOG_1(PACA_EXGEN, NOTEST, 0x1500)
1126 #ifdef CONFIG_PPC_DENORMALISATION
1127 mfspr r10,SPRN_HSRR1
1128 mfspr r11,SPRN_HSRR0 /* save HSRR0 */
1129 andis. r10,r10,(HSRR1_DENORM)@h /* denorm? */
1130 addi r11,r11,-4 /* HSRR0 is next instruction */
1135 EXCEPTION_PROLOG_PSERIES_1(denorm_common, EXC_HV)
1136 EXC_REAL_END(denorm_exception_hv, 0x1500, 0x100)
1138 #ifdef CONFIG_PPC_DENORMALISATION
1139 EXC_VIRT_BEGIN(denorm_exception, 0x5500, 0x100)
1140 b exc_real_0x1500_denorm_exception_hv
1141 EXC_VIRT_END(denorm_exception, 0x5500, 0x100)
1143 EXC_VIRT_NONE(0x5500, 0x100)
1146 TRAMP_KVM_SKIP(PACA_EXGEN, 0x1500)
1148 #ifdef CONFIG_PPC_DENORMALISATION
1149 TRAMP_REAL_BEGIN(denorm_assist)
1152 * To denormalise we need to move a copy of the register to itself.
1153 * For POWER6 do that here for all FP regs.
1156 ori r10,r10,(MSR_FP|MSR_FE0|MSR_FE1)
1157 xori r10,r10,(MSR_FE0|MSR_FE1)
1161 #define FMR2(n) fmr (n), (n) ; fmr n+1, n+1
1162 #define FMR4(n) FMR2(n) ; FMR2(n+2)
1163 #define FMR8(n) FMR4(n) ; FMR4(n+4)
1164 #define FMR16(n) FMR8(n) ; FMR8(n+8)
1165 #define FMR32(n) FMR16(n) ; FMR16(n+16)
1170 * To denormalise we need to move a copy of the register to itself.
1171 * For POWER7 do that here for the first 32 VSX registers only.
1174 oris r10,r10,MSR_VSX@h
1178 #define XVCPSGNDP2(n) XVCPSGNDP(n,n,n) ; XVCPSGNDP(n+1,n+1,n+1)
1179 #define XVCPSGNDP4(n) XVCPSGNDP2(n) ; XVCPSGNDP2(n+2)
1180 #define XVCPSGNDP8(n) XVCPSGNDP4(n) ; XVCPSGNDP4(n+4)
1181 #define XVCPSGNDP16(n) XVCPSGNDP8(n) ; XVCPSGNDP8(n+8)
1182 #define XVCPSGNDP32(n) XVCPSGNDP16(n) ; XVCPSGNDP16(n+16)
1185 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_206)
1189 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1191 * To denormalise we need to move a copy of the register to itself.
1192 * For POWER8 we need to do that for all 64 VSX registers
1196 mtspr SPRN_HSRR0,r11
1198 ld r9,PACA_EXGEN+EX_R9(r13)
1199 RESTORE_PPR_PACA(PACA_EXGEN, r10)
1201 ld r10,PACA_EXGEN+EX_CFAR(r13)
1203 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1204 ld r10,PACA_EXGEN+EX_R10(r13)
1205 ld r11,PACA_EXGEN+EX_R11(r13)
1206 ld r12,PACA_EXGEN+EX_R12(r13)
1207 ld r13,PACA_EXGEN+EX_R13(r13)
1212 EXC_COMMON_HV(denorm_common, 0x1500, unknown_exception)
1215 #ifdef CONFIG_CBE_RAS
1216 EXC_REAL_HV(cbe_maintenance, 0x1600, 0x100)
1217 EXC_VIRT_NONE(0x5600, 0x100)
1218 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1600)
1219 EXC_COMMON(cbe_maintenance_common, 0x1600, cbe_maintenance_exception)
1220 #else /* CONFIG_CBE_RAS */
1221 EXC_REAL_NONE(0x1600, 0x100)
1222 EXC_VIRT_NONE(0x5600, 0x100)
1226 EXC_REAL(altivec_assist, 0x1700, 0x100)
1227 EXC_VIRT(altivec_assist, 0x5700, 0x100, 0x1700)
1228 TRAMP_KVM(PACA_EXGEN, 0x1700)
1229 #ifdef CONFIG_ALTIVEC
1230 EXC_COMMON(altivec_assist_common, 0x1700, altivec_assist_exception)
1232 EXC_COMMON(altivec_assist_common, 0x1700, unknown_exception)
1236 #ifdef CONFIG_CBE_RAS
1237 EXC_REAL_HV(cbe_thermal, 0x1800, 0x100)
1238 EXC_VIRT_NONE(0x5800, 0x100)
1239 TRAMP_KVM_HV_SKIP(PACA_EXGEN, 0x1800)
1240 EXC_COMMON(cbe_thermal_common, 0x1800, cbe_thermal_exception)
1241 #else /* CONFIG_CBE_RAS */
1242 EXC_REAL_NONE(0x1800, 0x100)
1243 EXC_VIRT_NONE(0x5800, 0x100)
1248 * An interrupt came in while soft-disabled. We set paca->irq_happened, then:
1249 * - If it was a decrementer interrupt, we bump the dec to max and and return.
1250 * - If it was a doorbell we return immediately since doorbells are edge
1251 * triggered and won't automatically refire.
1252 * - If it was a HMI we return immediately since we handled it in realmode
1253 * and it won't refire.
1254 * - else we hard disable and return.
1255 * This is called with r10 containing the value to OR to the paca field.
1257 #define MASKED_INTERRUPT(_H) \
1258 masked_##_H##interrupt: \
1259 std r11,PACA_EXGEN+EX_R11(r13); \
1260 lbz r11,PACAIRQHAPPENED(r13); \
1262 stb r11,PACAIRQHAPPENED(r13); \
1263 cmpwi r10,PACA_IRQ_DEC; \
1266 ori r10,r10,0xffff; \
1267 mtspr SPRN_DEC,r10; \
1269 1: cmpwi r10,PACA_IRQ_DBELL; \
1271 cmpwi r10,PACA_IRQ_HMI; \
1273 mfspr r10,SPRN_##_H##SRR1; \
1274 rldicl r10,r10,48,1; /* clear MSR_EE */ \
1275 rotldi r10,r10,16; \
1276 mtspr SPRN_##_H##SRR1,r10; \
1278 ld r9,PACA_EXGEN+EX_R9(r13); \
1279 ld r10,PACA_EXGEN+EX_R10(r13); \
1280 ld r11,PACA_EXGEN+EX_R11(r13); \
1281 GET_SCRATCH0(r13); \
1286 * Real mode exceptions actually use this too, but alternate
1287 * instruction code patches (which end up in the common .text area)
1288 * cannot reach these if they are put there.
1290 USE_FIXED_SECTION(virt_trampolines)
1294 #ifdef CONFIG_KVM_BOOK3S_64_HANDLER
1295 TRAMP_REAL_BEGIN(kvmppc_skip_interrupt)
1297 * Here all GPRs are unchanged from when the interrupt happened
1298 * except for r13, which is saved in SPRG_SCRATCH0.
1300 mfspr r13, SPRN_SRR0
1302 mtspr SPRN_SRR0, r13
1307 TRAMP_REAL_BEGIN(kvmppc_skip_Hinterrupt)
1309 * Here all GPRs are unchanged from when the interrupt happened
1310 * except for r13, which is saved in SPRG_SCRATCH0.
1312 mfspr r13, SPRN_HSRR0
1314 mtspr SPRN_HSRR0, r13
1321 * Ensure that any handlers that get invoked from the exception prologs
1322 * above are below the first 64KB (0x10000) of the kernel image because
1323 * the prologs assemble the addresses of these handlers using the
1324 * LOAD_HANDLER macro, which uses an ori instruction.
1327 /*** Common interrupt handlers ***/
1331 * Relocation-on interrupts: A subset of the interrupts can be delivered
1332 * with IR=1/DR=1, if AIL==2 and MSR.HV won't be changed by delivering
1333 * it. Addresses are the same as the original interrupt addresses, but
1334 * offset by 0xc000000000004000.
1335 * It's impossible to receive interrupts below 0x300 via this mechanism.
1336 * KVM: None of these traps are from the guest ; anything that escalated
1337 * to HV=1 from HV=0 is delivered via real mode handlers.
1341 * This uses the standard macro, since the original 0x300 vector
1342 * only has extra guff for STAB-based processors -- which never
1346 EXC_COMMON_BEGIN(ppc64_runlatch_on_trampoline)
1347 b __ppc64_runlatch_on
1349 USE_FIXED_SECTION(virt_trampolines)
1351 * The __end_interrupts marker must be past the out-of-line (OOL)
1352 * handlers, so that they are copied to real address 0x100 when running
1353 * a relocatable kernel. This ensures they can be reached from the short
1354 * trampoline handlers (like 0x4f00, 0x4f20, etc.) which branch
1355 * directly, without using LOAD_HANDLER().
1358 .globl __end_interrupts
1360 DEFINE_FIXED_SYMBOL(__end_interrupts)
1362 #ifdef CONFIG_PPC_970_NAP
1363 EXC_COMMON_BEGIN(power4_fixup_nap)
1365 std r9,TI_LOCAL_FLAGS(r11)
1366 ld r10,_LINK(r1) /* make idle task do the */
1367 std r10,_NIP(r1) /* equivalent of a blr */
1371 CLOSE_FIXED_SECTION(real_vectors);
1372 CLOSE_FIXED_SECTION(real_trampolines);
1373 CLOSE_FIXED_SECTION(virt_vectors);
1374 CLOSE_FIXED_SECTION(virt_trampolines);
1381 .balign IFETCH_ALIGN_BYTES
1383 #ifdef CONFIG_PPC_STD_MMU_64
1384 andis. r0,r4,0xa410 /* weird error? */
1385 bne- handle_page_fault /* if not, try to insert a HPTE */
1386 andis. r0,r4,DSISR_DABRMATCH@h
1387 bne- handle_dabr_fault
1388 CURRENT_THREAD_INFO(r11, r1)
1389 lwz r0,TI_PREEMPT(r11) /* If we're in an "NMI" */
1390 andis. r0,r0,NMI_MASK@h /* (i.e. an irq when soft-disabled) */
1391 bne 77f /* then don't call hash_page now */
1394 * r3 contains the faulting address
1396 * r5 contains the trap number
1399 * at return r3 = 0 for success, 1 for page fault, negative for error
1403 bl __hash_page /* build HPTE if possible */
1404 cmpdi r3,0 /* see if __hash_page succeeded */
1407 beq fast_exc_return_irq /* Return from exception on success */
1411 #endif /* CONFIG_PPC_STD_MMU_64 */
1413 /* Here we have a page fault that hash_page can't handle. */
1417 addi r3,r1,STACK_FRAME_OVERHEAD
1423 addi r3,r1,STACK_FRAME_OVERHEAD
1428 /* We have a data breakpoint exception - handle it */
1433 addi r3,r1,STACK_FRAME_OVERHEAD
1435 12: b ret_from_except_lite
1438 #ifdef CONFIG_PPC_STD_MMU_64
1439 /* We have a page fault that hash_page could handle but HV refused
1444 addi r3,r1,STACK_FRAME_OVERHEAD
1451 * We come here as a result of a DSI at a point where we don't want
1452 * to call hash_page, such as when we are accessing memory (possibly
1453 * user memory) inside a PMU interrupt that occurred while interrupts
1454 * were soft-disabled. We want to invoke the exception handler for
1455 * the access, or panic if there isn't a handler.
1459 addi r3,r1,STACK_FRAME_OVERHEAD
1465 * Here we have detected that the kernel stack pointer is bad.
1466 * R9 contains the saved CR, r13 points to the paca,
1467 * r10 contains the (bad) kernel stack pointer,
1468 * r11 and r12 contain the saved SRR0 and SRR1.
1469 * We switch to using an emergency stack, save the registers there,
1470 * and call kernel_bad_stack(), which panics.
1473 ld r1,PACAEMERGSP(r13)
1474 subi r1,r1,64+INT_FRAME_SIZE
1480 mfspr r12,SPRN_DSISR
1506 std r10,ORIG_GPR3(r1)
1507 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1510 lhz r12,PACA_TRAP_SAVE(r13)
1512 addi r11,r1,INT_FRAME_SIZE
1517 ld r11,exception_marker@toc(r2)
1519 std r11,STACK_FRAME_OVERHEAD-16(r1)
1520 1: addi r3,r1,STACK_FRAME_OVERHEAD
1525 * Called from arch_local_irq_enable when an interrupt needs
1526 * to be resent. r3 contains 0x500, 0x900, 0xa00 or 0xe80 to indicate
1527 * which kind of interrupt. MSR:EE is already off. We generate a
1528 * stackframe like if a real interrupt had happened.
1530 * Note: While MSR:EE is off, we need to make sure that _MSR
1531 * in the generated frame has EE set to 1 or the exception
1532 * handler will not properly re-enable them.
1534 _GLOBAL(__replay_interrupt)
1535 /* We are going to jump to the exception common code which
1536 * will retrieve various register values from the PACA which
1537 * we don't give a damn about, so we don't bother storing them.
1544 beq decrementer_common
1546 beq hardware_interrupt_common
1549 beq h_doorbell_common
1551 beq h_virt_irq_common
1553 beq hmi_exception_common
1556 beq doorbell_super_common
1557 ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)