2 * TLB flush routines for radix kernels.
4 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
13 #include <linux/hugetlb.h>
14 #include <linux/memblock.h>
15 #include <asm/ppc-opcode.h>
18 #include <asm/tlbflush.h>
21 #define RIC_FLUSH_TLB 0
22 #define RIC_FLUSH_PWC 1
23 #define RIC_FLUSH_ALL 2
25 static inline void __tlbiel_pid(unsigned long pid, int set,
28 unsigned long rb,rs,prs,r;
30 rb = PPC_BIT(53); /* IS = 1 */
31 rb |= set << PPC_BITLSHIFT(51);
32 rs = ((unsigned long)pid) << PPC_BITLSHIFT(31);
33 prs = 1; /* process scoped */
34 r = 1; /* raidx format */
36 asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
37 : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
41 * We use 128 set in radix mode and 256 set in hpt mode.
43 static inline void _tlbiel_pid(unsigned long pid, unsigned long ric)
47 asm volatile("ptesync": : :"memory");
50 * Flush the first set of the TLB, and if we're doing a RIC_FLUSH_ALL,
51 * also flush the entire Page Walk Cache.
53 __tlbiel_pid(pid, 0, ric);
55 if (ric == RIC_FLUSH_ALL)
56 /* For the remaining sets, just flush the TLB */
59 for (set = 1; set < POWER9_TLB_SETS_RADIX ; set++)
60 __tlbiel_pid(pid, set, ric);
62 asm volatile("ptesync": : :"memory");
63 asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory");
66 static inline void tlbiel_pwc(unsigned long pid)
68 asm volatile("ptesync": : :"memory");
70 /* For PWC flush, we don't look at set number */
71 __tlbiel_pid(pid, 0, RIC_FLUSH_PWC);
73 asm volatile("ptesync": : :"memory");
74 asm volatile(PPC_INVALIDATE_ERAT "; isync" : : :"memory");
77 static inline void _tlbie_pid(unsigned long pid, unsigned long ric)
79 unsigned long rb,rs,prs,r;
81 rb = PPC_BIT(53); /* IS = 1 */
82 rs = pid << PPC_BITLSHIFT(31);
83 prs = 1; /* process scoped */
84 r = 1; /* raidx format */
86 asm volatile("ptesync": : :"memory");
87 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
88 : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
89 asm volatile("eieio; tlbsync; ptesync": : :"memory");
92 static inline void _tlbiel_va(unsigned long va, unsigned long pid,
93 unsigned long ap, unsigned long ric)
95 unsigned long rb,rs,prs,r;
97 rb = va & ~(PPC_BITMASK(52, 63));
98 rb |= ap << PPC_BITLSHIFT(58);
99 rs = pid << PPC_BITLSHIFT(31);
100 prs = 1; /* process scoped */
101 r = 1; /* raidx format */
103 asm volatile("ptesync": : :"memory");
104 asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
105 : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
106 asm volatile("ptesync": : :"memory");
109 static inline void _tlbie_va(unsigned long va, unsigned long pid,
110 unsigned long ap, unsigned long ric)
112 unsigned long rb,rs,prs,r;
114 rb = va & ~(PPC_BITMASK(52, 63));
115 rb |= ap << PPC_BITLSHIFT(58);
116 rs = pid << PPC_BITLSHIFT(31);
117 prs = 1; /* process scoped */
118 r = 1; /* raidx format */
120 asm volatile("ptesync": : :"memory");
121 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
122 : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
123 asm volatile("eieio; tlbsync; ptesync": : :"memory");
127 * Base TLB flushing operations:
129 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
130 * - flush_tlb_page(vma, vmaddr) flushes one page
131 * - flush_tlb_range(vma, start, end) flushes a range of pages
132 * - flush_tlb_kernel_range(start, end) flushes kernel pages
134 * - local_* variants of page and mm only apply to the current
137 void radix__local_flush_tlb_mm(struct mm_struct *mm)
142 pid = mm->context.id;
143 if (pid != MMU_NO_CONTEXT)
144 _tlbiel_pid(pid, RIC_FLUSH_ALL);
147 EXPORT_SYMBOL(radix__local_flush_tlb_mm);
149 void radix__local_flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
152 struct mm_struct *mm = tlb->mm;
154 * If we are doing a full mm flush, we will do a tlb flush
155 * with RIC_FLUSH_ALL later.
162 pid = mm->context.id;
163 if (pid != MMU_NO_CONTEXT)
168 EXPORT_SYMBOL(radix__local_flush_tlb_pwc);
170 void radix__local_flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,
174 unsigned long ap = mmu_get_ap(psize);
177 pid = mm ? mm->context.id : 0;
178 if (pid != MMU_NO_CONTEXT)
179 _tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
183 void radix__local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
185 #ifdef CONFIG_HUGETLB_PAGE
186 /* need the return fix for nohash.c */
187 if (vma && is_vm_hugetlb_page(vma))
188 return __local_flush_hugetlb_page(vma, vmaddr);
190 radix__local_flush_tlb_page_psize(vma ? vma->vm_mm : NULL, vmaddr,
193 EXPORT_SYMBOL(radix__local_flush_tlb_page);
196 void radix__flush_tlb_mm(struct mm_struct *mm)
201 pid = mm->context.id;
202 if (unlikely(pid == MMU_NO_CONTEXT))
205 if (!mm_is_thread_local(mm))
206 _tlbie_pid(pid, RIC_FLUSH_ALL);
208 _tlbiel_pid(pid, RIC_FLUSH_ALL);
212 EXPORT_SYMBOL(radix__flush_tlb_mm);
214 void radix__flush_tlb_pwc(struct mmu_gather *tlb, unsigned long addr)
217 struct mm_struct *mm = tlb->mm;
220 * If we are doing a full mm flush, we will do a tlb flush
221 * with RIC_FLUSH_ALL later.
227 pid = mm->context.id;
228 if (unlikely(pid == MMU_NO_CONTEXT))
231 if (!mm_is_thread_local(mm))
232 _tlbie_pid(pid, RIC_FLUSH_PWC);
238 EXPORT_SYMBOL(radix__flush_tlb_pwc);
240 void radix__flush_tlb_page_psize(struct mm_struct *mm, unsigned long vmaddr,
244 unsigned long ap = mmu_get_ap(psize);
247 pid = mm ? mm->context.id : 0;
248 if (unlikely(pid == MMU_NO_CONTEXT))
250 if (!mm_is_thread_local(mm))
251 _tlbie_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
253 _tlbiel_va(vmaddr, pid, ap, RIC_FLUSH_TLB);
258 void radix__flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
260 #ifdef CONFIG_HUGETLB_PAGE
261 if (vma && is_vm_hugetlb_page(vma))
262 return flush_hugetlb_page(vma, vmaddr);
264 radix__flush_tlb_page_psize(vma ? vma->vm_mm : NULL, vmaddr,
267 EXPORT_SYMBOL(radix__flush_tlb_page);
269 #endif /* CONFIG_SMP */
271 void radix__flush_tlb_kernel_range(unsigned long start, unsigned long end)
273 _tlbie_pid(0, RIC_FLUSH_ALL);
275 EXPORT_SYMBOL(radix__flush_tlb_kernel_range);
278 * Currently, for range flushing, we just do a full mm flush. Because
279 * we use this in code path where we don' track the page size.
281 void radix__flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
285 struct mm_struct *mm = vma->vm_mm;
286 radix__flush_tlb_mm(mm);
288 EXPORT_SYMBOL(radix__flush_tlb_range);
290 static int radix_get_mmu_psize(int page_size)
294 if (page_size == (1UL << mmu_psize_defs[mmu_virtual_psize].shift))
295 psize = mmu_virtual_psize;
296 else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_2M].shift))
298 else if (page_size == (1UL << mmu_psize_defs[MMU_PAGE_1G].shift))
305 void radix__tlb_flush(struct mmu_gather *tlb)
308 struct mm_struct *mm = tlb->mm;
309 int page_size = tlb->page_size;
311 psize = radix_get_mmu_psize(page_size);
313 * if page size is not something we understand, do a full mm flush
315 if (psize != -1 && !tlb->fullmm && !tlb->need_flush_all)
316 radix__flush_tlb_range_psize(mm, tlb->start, tlb->end, psize);
318 radix__flush_tlb_mm(mm);
321 #define TLB_FLUSH_ALL -1UL
323 * Number of pages above which we will do a bcast tlbie. Just a
324 * number at this point copied from x86
326 static unsigned long tlb_single_page_flush_ceiling __read_mostly = 33;
328 void radix__flush_tlb_range_psize(struct mm_struct *mm, unsigned long start,
329 unsigned long end, int psize)
333 int local = mm_is_thread_local(mm);
334 unsigned long ap = mmu_get_ap(psize);
335 unsigned long page_size = 1UL << mmu_psize_defs[psize].shift;
339 pid = mm ? mm->context.id : 0;
340 if (unlikely(pid == MMU_NO_CONTEXT))
343 if (end == TLB_FLUSH_ALL ||
344 (end - start) > tlb_single_page_flush_ceiling * page_size) {
346 _tlbiel_pid(pid, RIC_FLUSH_TLB);
348 _tlbie_pid(pid, RIC_FLUSH_TLB);
351 for (addr = start; addr < end; addr += page_size) {
354 _tlbiel_va(addr, pid, ap, RIC_FLUSH_TLB);
356 _tlbie_va(addr, pid, ap, RIC_FLUSH_TLB);
362 void radix__flush_tlb_lpid_va(unsigned long lpid, unsigned long gpa,
363 unsigned long page_size)
365 unsigned long rb,rs,prs,r;
367 unsigned long ric = RIC_FLUSH_TLB;
369 ap = mmu_get_ap(radix_get_mmu_psize(page_size));
370 rb = gpa & ~(PPC_BITMASK(52, 63));
371 rb |= ap << PPC_BITLSHIFT(58);
372 rs = lpid & ((1UL << 32) - 1);
373 prs = 0; /* process scoped */
374 r = 1; /* raidx format */
376 asm volatile("ptesync": : :"memory");
377 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
378 : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
379 asm volatile("eieio; tlbsync; ptesync": : :"memory");
381 EXPORT_SYMBOL(radix__flush_tlb_lpid_va);
383 void radix__flush_tlb_lpid(unsigned long lpid)
385 unsigned long rb,rs,prs,r;
386 unsigned long ric = RIC_FLUSH_ALL;
388 rb = 0x2 << PPC_BITLSHIFT(53); /* IS = 2 */
389 rs = lpid & ((1UL << 32) - 1);
390 prs = 0; /* partition scoped */
391 r = 1; /* raidx format */
393 asm volatile("ptesync": : :"memory");
394 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
395 : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(rs) : "memory");
396 asm volatile("eieio; tlbsync; ptesync": : :"memory");
398 EXPORT_SYMBOL(radix__flush_tlb_lpid);
400 void radix__flush_pmd_tlb_range(struct vm_area_struct *vma,
401 unsigned long start, unsigned long end)
403 radix__flush_tlb_range_psize(vma->vm_mm, start, end, MMU_PAGE_2M);
405 EXPORT_SYMBOL(radix__flush_pmd_tlb_range);
407 void radix__flush_tlb_all(void)
409 unsigned long rb,prs,r,rs;
410 unsigned long ric = RIC_FLUSH_ALL;
412 rb = 0x3 << PPC_BITLSHIFT(53); /* IS = 3 */
413 prs = 0; /* partition scoped */
414 r = 1; /* raidx format */
415 rs = 1 & ((1UL << 32) - 1); /* any LPID value to flush guest mappings */
417 asm volatile("ptesync": : :"memory");
419 * now flush guest entries by passing PRS = 1 and LPID != 0
421 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
422 : : "r"(rb), "i"(r), "i"(1), "i"(ric), "r"(rs) : "memory");
424 * now flush host entires by passing PRS = 0 and LPID == 0
426 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
427 : : "r"(rb), "i"(r), "i"(prs), "i"(ric), "r"(0) : "memory");
428 asm volatile("eieio; tlbsync; ptesync": : :"memory");
431 void radix__flush_tlb_pte_p9_dd1(unsigned long old_pte, struct mm_struct *mm,
432 unsigned long address)
435 * We track page size in pte only for DD1, So we can
436 * call this only on DD1.
438 if (!cpu_has_feature(CPU_FTR_POWER9_DD1)) {
443 if (old_pte & R_PAGE_LARGE)
444 radix__flush_tlb_page_psize(mm, address, MMU_PAGE_2M);
446 radix__flush_tlb_page_psize(mm, address, mmu_virtual_psize);