2 * Copyright 2010 Ben Herrenschmidt, IBM Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
12 #include <linux/kernel.h>
13 #include <linux/pci.h>
14 #include <linux/delay.h>
15 #include <linux/string.h>
16 #include <linux/init.h>
17 #include <linux/bootmem.h>
18 #include <linux/irq.h>
19 #include <linux/interrupt.h>
20 #include <linux/debugfs.h>
22 #include <asm/sections.h>
25 #include <asm/pci-bridge.h>
26 #include <asm/machdep.h>
27 #include <asm/ppc-pci.h>
28 #include <asm/iommu.h>
29 #include <asm/io-workarounds.h>
30 #include <asm/debug.h>
37 /* Max number of TVTs for one table. Only 32-bit tables can use
38 * multiple TVTs and so the max currently supported is thus 8
39 * since only 2G of DMA space is supported
41 #define MAX_TABLE_TVT_COUNT 8
43 struct wsp_dma_table {
44 struct list_head link;
45 struct iommu_table table;
47 struct page *tces[MAX_TABLE_TVT_COUNT];
50 /* We support DMA regions from 0...2G in 32bit space (no support for
51 * 64-bit DMA just yet). Each device gets a separate TCE table (TVT
52 * entry) with validation enabled (though not supported by SimiCS
55 * To simplify things, we divide this 2G space into N regions based
56 * on the constant below which could be turned into a tunable eventually
58 * We then assign dynamically those regions to devices as they show up.
60 * We use a bitmap as an allocator for these.
62 * Tables are allocated/created dynamically as devices are discovered,
63 * multiple TVT entries are used if needed
65 * When 64-bit DMA support is added we should simply use a separate set
66 * of larger regions (the HW supports 64 TVT entries). We can
67 * additionally create a bypass region in 64-bit space for performances
68 * though that would have a cost in term of security.
70 * If you set NUM_DMA32_REGIONS to 1, then a single table is shared
71 * for all devices and bus/dev/fn validation is disabled
73 * Note that a DMA32 region cannot be smaller than 256M so the max
74 * supported here for now is 8. We don't yet support sharing regions
75 * between multiple devices so the max number of devices supported
76 * is MAX_TABLE_TVT_COUNT.
78 #define NUM_DMA32_REGIONS 1
81 struct pci_controller *hose;
83 /* Lock controlling access to the list of dma tables.
84 * It does -not- protect against dma_* operations on
85 * those tables, those should be stopped before an entry
86 * is removed from the list.
88 * The lock is also used for error handling operations
91 struct list_head dma_tables;
92 unsigned long dma32_map;
93 unsigned long dma32_base;
94 unsigned int dma32_num_regions;
95 unsigned long dma32_region_size;
100 struct list_head all;
102 static LIST_HEAD(wsp_phbs);
104 //#define cfg_debug(fmt...) pr_debug(fmt)
105 #define cfg_debug(fmt...)
108 static int wsp_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
109 int offset, int len, u32 *val)
111 struct pci_controller *hose;
115 hose = pci_bus_to_host(bus);
117 return PCIBIOS_DEVICE_NOT_FOUND;
118 if (offset >= 0x1000)
119 return PCIBIOS_BAD_REGISTER_NUMBER;
120 addr = PCIE_REG_CA_ENABLE |
121 ((u64)bus->number) << PCIE_REG_CA_BUS_SHIFT |
122 ((u64)devfn) << PCIE_REG_CA_FUNC_SHIFT |
123 ((u64)offset & ~3) << PCIE_REG_CA_REG_SHIFT;
127 * Note: the caller has already checked that offset is
128 * suitably aligned and that len is 1, 2 or 4.
133 addr |= (0x8ul >> suboff) << PCIE_REG_CA_BE_SHIFT;
134 out_be64(hose->cfg_data + PCIE_REG_CONFIG_ADDRESS, addr);
135 *val = (in_le32(hose->cfg_data + PCIE_REG_CONFIG_DATA)
136 >> (suboff << 3)) & 0xff;
137 cfg_debug("read 1 %02x:%02x:%02x + %02x/%x addr=0x%llx val=%02x\n",
138 bus->number, devfn >> 3, devfn & 7,
139 offset, suboff, addr, *val);
142 addr |= (0xcul >> suboff) << PCIE_REG_CA_BE_SHIFT;
143 out_be64(hose->cfg_data + PCIE_REG_CONFIG_ADDRESS, addr);
144 *val = (in_le32(hose->cfg_data + PCIE_REG_CONFIG_DATA)
145 >> (suboff << 3)) & 0xffff;
146 cfg_debug("read 2 %02x:%02x:%02x + %02x/%x addr=0x%llx val=%04x\n",
147 bus->number, devfn >> 3, devfn & 7,
148 offset, suboff, addr, *val);
151 addr |= 0xful << PCIE_REG_CA_BE_SHIFT;
152 out_be64(hose->cfg_data + PCIE_REG_CONFIG_ADDRESS, addr);
153 *val = in_le32(hose->cfg_data + PCIE_REG_CONFIG_DATA);
154 cfg_debug("read 4 %02x:%02x:%02x + %02x/%x addr=0x%llx val=%08x\n",
155 bus->number, devfn >> 3, devfn & 7,
156 offset, suboff, addr, *val);
159 return PCIBIOS_SUCCESSFUL;
162 static int wsp_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
163 int offset, int len, u32 val)
165 struct pci_controller *hose;
169 hose = pci_bus_to_host(bus);
171 return PCIBIOS_DEVICE_NOT_FOUND;
172 if (offset >= 0x1000)
173 return PCIBIOS_BAD_REGISTER_NUMBER;
174 addr = PCIE_REG_CA_ENABLE |
175 ((u64)bus->number) << PCIE_REG_CA_BUS_SHIFT |
176 ((u64)devfn) << PCIE_REG_CA_FUNC_SHIFT |
177 ((u64)offset & ~3) << PCIE_REG_CA_REG_SHIFT;
181 * Note: the caller has already checked that offset is
182 * suitably aligned and that len is 1, 2 or 4.
186 addr |= (0x8ul >> suboff) << PCIE_REG_CA_BE_SHIFT;
188 out_be64(hose->cfg_data + PCIE_REG_CONFIG_ADDRESS, addr);
189 out_le32(hose->cfg_data + PCIE_REG_CONFIG_DATA, val);
190 cfg_debug("write 1 %02x:%02x:%02x + %02x/%x addr=0x%llx val=%02x\n",
191 bus->number, devfn >> 3, devfn & 7,
192 offset, suboff, addr, val);
195 addr |= (0xcul >> suboff) << PCIE_REG_CA_BE_SHIFT;
197 out_be64(hose->cfg_data + PCIE_REG_CONFIG_ADDRESS, addr);
198 out_le32(hose->cfg_data + PCIE_REG_CONFIG_DATA, val);
199 cfg_debug("write 2 %02x:%02x:%02x + %02x/%x addr=0x%llx val=%04x\n",
200 bus->number, devfn >> 3, devfn & 7,
201 offset, suboff, addr, val);
204 addr |= 0xful << PCIE_REG_CA_BE_SHIFT;
205 out_be64(hose->cfg_data + PCIE_REG_CONFIG_ADDRESS, addr);
206 out_le32(hose->cfg_data + PCIE_REG_CONFIG_DATA, val);
207 cfg_debug("write 4 %02x:%02x:%02x + %02x/%x addr=0x%llx val=%08x\n",
208 bus->number, devfn >> 3, devfn & 7,
209 offset, suboff, addr, val);
212 return PCIBIOS_SUCCESSFUL;
215 static struct pci_ops wsp_pcie_pci_ops =
217 .read = wsp_pcie_read_config,
218 .write = wsp_pcie_write_config,
222 #define TCE_PAGE_SIZE (1 << TCE_SHIFT)
223 #define TCE_PCI_WRITE 0x2 /* write from PCI allowed */
224 #define TCE_PCI_READ 0x1 /* read from PCI allowed */
225 #define TCE_RPN_MASK 0x3fffffffffful /* 42-bit RPN (4K pages) */
226 #define TCE_RPN_SHIFT 12
228 //#define dma_debug(fmt...) pr_debug(fmt)
229 #define dma_debug(fmt...)
231 static int tce_build_wsp(struct iommu_table *tbl, long index, long npages,
232 unsigned long uaddr, enum dma_data_direction direction,
233 struct dma_attrs *attrs)
235 struct wsp_dma_table *ptbl = container_of(tbl,
236 struct wsp_dma_table,
242 proto_tce = TCE_PCI_READ;
243 #ifdef CONFIG_WSP_DD1_WORKAROUND_DD1_TCE_BUGS
244 proto_tce |= TCE_PCI_WRITE;
246 if (direction != DMA_TO_DEVICE)
247 proto_tce |= TCE_PCI_WRITE;
250 /* XXX Make this faster by factoring out the page address for
254 /* We don't use it->base as the table can be scattered */
255 tcep = (u64 *)page_address(ptbl->tces[index >> 16]);
256 tcep += (index & 0xffff);
258 /* can't move this out since we might cross LMB boundary */
259 rpn = __pa(uaddr) >> TCE_SHIFT;
260 *tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
262 dma_debug("[DMA] TCE %p set to 0x%016llx (dma addr: 0x%lx)\n",
263 tcep, *tcep, (tbl->it_offset + index) << IOMMU_PAGE_SHIFT_4K);
265 uaddr += TCE_PAGE_SIZE;
271 static void tce_free_wsp(struct iommu_table *tbl, long index, long npages)
273 struct wsp_dma_table *ptbl = container_of(tbl,
274 struct wsp_dma_table,
276 #ifndef CONFIG_WSP_DD1_WORKAROUND_DD1_TCE_BUGS
277 struct pci_controller *hose = ptbl->phb->hose;
281 /* XXX Make this faster by factoring out the page address for
282 * within a TCE table. Also use line-kill option to kill multiple
286 /* We don't use it->base as the table can be scattered */
287 tcep = (u64 *)page_address(ptbl->tces[index >> 16]);
288 tcep += (index & 0xffff);
289 dma_debug("[DMA] TCE %p cleared\n", tcep);
291 #ifndef CONFIG_WSP_DD1_WORKAROUND_DD1_TCE_BUGS
292 /* Don't write there since it would pollute other MMIO accesses */
293 out_be64(hose->cfg_data + PCIE_REG_TCE_KILL,
294 PCIE_REG_TCEKILL_SINGLE | PCIE_REG_TCEKILL_PS_4K |
295 (__pa(tcep) & PCIE_REG_TCEKILL_ADDR_MASK));
301 static struct wsp_dma_table *wsp_pci_create_dma32_table(struct wsp_phb *phb,
303 struct pci_dev *validate)
305 struct pci_controller *hose = phb->hose;
306 unsigned long size = phb->dma32_region_size;
307 unsigned long addr = phb->dma32_region_size * region + phb->dma32_base;
308 struct wsp_dma_table *tbl;
309 int tvts_per_table, i, tvt, nid;
312 nid = of_node_to_nid(phb->hose->dn);
314 /* Calculate how many TVTs are needed */
315 tvts_per_table = size / 0x10000000;
316 if (tvts_per_table == 0)
319 /* Calculate the base TVT index. We know all tables have the same
320 * size so we just do a simple multiply here
322 tvt = region * tvts_per_table;
324 pr_debug(" Region : %d\n", region);
325 pr_debug(" DMA range : 0x%08lx..0x%08lx\n", addr, addr + size - 1);
326 pr_debug(" Number of TVTs : %d\n", tvts_per_table);
327 pr_debug(" Base TVT : %d\n", tvt);
328 pr_debug(" Node : %d\n", nid);
330 tbl = kzalloc_node(sizeof(struct wsp_dma_table), GFP_KERNEL, nid);
332 return ERR_PTR(-ENOMEM);
335 /* Create as many TVTs as needed, each represents 256M at most */
336 for (i = 0; i < tvts_per_table; i++) {
337 u64 tvt_data1, tvt_data0;
339 /* Allocate table. We use a 4K TCE size for now always so
340 * one table is always 8 * (258M / 4K) == 512K
342 tbl->tces[i] = alloc_pages_node(nid, GFP_KERNEL, get_order(0x80000));
343 if (tbl->tces[i] == NULL)
345 memset(page_address(tbl->tces[i]), 0, 0x80000);
347 pr_debug(" TCE table %d at : %p\n", i, page_address(tbl->tces[i]));
349 /* Table size. We currently set it to be the whole 256M region */
350 tvt_data0 = 2ull << IODA_TVT0_TCE_TABLE_SIZE_SHIFT;
351 /* IO page size set to 4K */
352 tvt_data1 = 1ull << IODA_TVT1_IO_PAGE_SIZE_SHIFT;
353 /* Shift in the address */
354 tvt_data0 |= __pa(page_address(tbl->tces[i])) << IODA_TVT0_TTA_SHIFT;
356 /* Validation stuff. We only validate fully bus/dev/fn for now
357 * one day maybe we can group devices but that isn't the case
361 tvt_data0 |= IODA_TVT0_BUSNUM_VALID_MASK;
362 tvt_data0 |= validate->bus->number;
363 tvt_data1 |= IODA_TVT1_DEVNUM_VALID;
364 tvt_data1 |= ((u64)PCI_SLOT(validate->devfn))
365 << IODA_TVT1_DEVNUM_VALUE_SHIFT;
366 tvt_data1 |= IODA_TVT1_FUNCNUM_VALID;
367 tvt_data1 |= ((u64)PCI_FUNC(validate->devfn))
368 << IODA_TVT1_FUNCNUM_VALUE_SHIFT;
371 /* XX PE number is always 0 for now */
373 /* Program the values using the PHB lock */
374 spin_lock_irqsave(&phb->lock, flags);
375 out_be64(hose->cfg_data + PCIE_REG_IODA_ADDR,
376 (tvt + i) | PCIE_REG_IODA_AD_TBL_TVT);
377 out_be64(hose->cfg_data + PCIE_REG_IODA_DATA1, tvt_data1);
378 out_be64(hose->cfg_data + PCIE_REG_IODA_DATA0, tvt_data0);
379 spin_unlock_irqrestore(&phb->lock, flags);
382 /* Init bits and pieces */
383 tbl->table.it_blocksize = 16;
384 tbl->table.it_page_shift = IOMMU_PAGE_SHIFT_4K;
385 tbl->table.it_offset = addr >> tbl->table.it_page_shift;
386 tbl->table.it_size = size >> tbl->table.it_page_shift;
389 * It's already blank but we clear it anyway.
390 * Consider an aditiona interface that makes cleaing optional
392 iommu_init_table(&tbl->table, nid);
394 list_add(&tbl->link, &phb->dma_tables);
398 pr_debug(" Failed to allocate a 256M TCE table !\n");
399 for (i = 0; i < tvts_per_table; i++)
401 __free_pages(tbl->tces[i], get_order(0x80000));
403 return ERR_PTR(-ENOMEM);
406 static void wsp_pci_dma_dev_setup(struct pci_dev *pdev)
408 struct dev_archdata *archdata = &pdev->dev.archdata;
409 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
410 struct wsp_phb *phb = hose->private_data;
411 struct wsp_dma_table *table = NULL;
415 /* Don't assign an iommu table to a bridge */
416 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
419 pr_debug("%s: Setting up DMA...\n", pci_name(pdev));
421 spin_lock_irqsave(&phb->lock, flags);
423 /* If only one region, check if it already exist */
424 if (phb->dma32_num_regions == 1) {
425 spin_unlock_irqrestore(&phb->lock, flags);
426 if (list_empty(&phb->dma_tables))
427 table = wsp_pci_create_dma32_table(phb, 0, NULL);
429 table = list_first_entry(&phb->dma_tables,
430 struct wsp_dma_table,
433 /* else find a free region */
434 for (i = 0; i < phb->dma32_num_regions && !table; i++) {
435 if (__test_and_set_bit(i, &phb->dma32_map))
437 spin_unlock_irqrestore(&phb->lock, flags);
438 table = wsp_pci_create_dma32_table(phb, i, pdev);
442 /* Check if we got an error */
444 pr_err("%s: Failed to create DMA table, err %ld !\n",
445 pci_name(pdev), PTR_ERR(table));
449 /* Or a valid table */
451 pr_info("%s: Setup iommu: 32-bit DMA region 0x%08lx..0x%08lx\n",
453 table->table.it_offset << IOMMU_PAGE_SHIFT_4K,
454 (table->table.it_offset << IOMMU_PAGE_SHIFT_4K)
455 + phb->dma32_region_size - 1);
456 archdata->dma_data.iommu_table_base = &table->table;
461 spin_unlock_irqrestore(&phb->lock, flags);
462 pr_err("%s: Out of DMA space !\n", pci_name(pdev));
465 static void __init wsp_pcie_configure_hw(struct pci_controller *hose)
470 #define DUMP_REG(x) \
471 pr_debug("%-30s : 0x%016llx\n", #x, in_be64(hose->cfg_data + x))
474 * Some WSP variants has a bogus class code by default in the PCI-E
475 * root complex's built-in P2P bridge
477 val = in_be64(hose->cfg_data + PCIE_REG_SYS_CFG1);
478 pr_debug("PCI-E SYS_CFG1 : 0x%llx\n", val);
479 out_be64(hose->cfg_data + PCIE_REG_SYS_CFG1,
480 (val & ~PCIE_REG_SYS_CFG1_CLASS_CODE) | (PCI_CLASS_BRIDGE_PCI << 8));
481 pr_debug("PCI-E SYS_CFG1 : 0x%llx\n", in_be64(hose->cfg_data + PCIE_REG_SYS_CFG1));
483 #ifdef CONFIG_WSP_DD1_WORKAROUND_DD1_TCE_BUGS
484 /* XXX Disable TCE caching, it doesn't work on DD1 */
485 out_be64(hose->cfg_data + 0xe50,
486 in_be64(hose->cfg_data + 0xe50) | (3ull << 62));
487 printk("PCI-E DEBUG CONTROL 5 = 0x%llx\n", in_be64(hose->cfg_data + 0xe50));
490 /* Configure M32A and IO. IO is hard wired to be 1M for now */
491 out_be64(hose->cfg_data + PCIE_REG_IO_BASE_ADDR, hose->io_base_phys);
492 out_be64(hose->cfg_data + PCIE_REG_IO_BASE_MASK,
493 (~(hose->io_resource.end - hose->io_resource.start)) &
495 out_be64(hose->cfg_data + PCIE_REG_IO_START_ADDR, 0 | 1);
497 out_be64(hose->cfg_data + PCIE_REG_M32A_BASE_ADDR,
498 hose->mem_resources[0].start);
499 printk("Want to write to M32A_BASE_MASK : 0x%llx\n",
500 (~(hose->mem_resources[0].end -
501 hose->mem_resources[0].start)) & 0x3ffffff0000ul);
502 out_be64(hose->cfg_data + PCIE_REG_M32A_BASE_MASK,
503 (~(hose->mem_resources[0].end -
504 hose->mem_resources[0].start)) & 0x3ffffff0000ul);
505 out_be64(hose->cfg_data + PCIE_REG_M32A_START_ADDR,
506 (hose->mem_resources[0].start - hose->mem_offset[0]) | 1);
508 /* Clear all TVT entries
510 * XX Might get TVT count from device-tree
512 for (i = 0; i < IODA_TVT_COUNT; i++) {
513 out_be64(hose->cfg_data + PCIE_REG_IODA_ADDR,
514 PCIE_REG_IODA_AD_TBL_TVT | i);
515 out_be64(hose->cfg_data + PCIE_REG_IODA_DATA1, 0);
516 out_be64(hose->cfg_data + PCIE_REG_IODA_DATA0, 0);
519 /* Kill the TCE cache */
520 out_be64(hose->cfg_data + PCIE_REG_PHB_CONFIG,
521 in_be64(hose->cfg_data + PCIE_REG_PHB_CONFIG) |
522 PCIE_REG_PHBC_64B_TCE_EN);
524 /* Enable 32 & 64-bit MSIs, IO space and M32A */
525 val = PCIE_REG_PHBC_32BIT_MSI_EN |
526 PCIE_REG_PHBC_IO_EN |
527 PCIE_REG_PHBC_64BIT_MSI_EN |
528 PCIE_REG_PHBC_M32A_EN;
530 val |= PCIE_REG_PHBC_DMA_XLATE_BYPASS;
531 pr_debug("Will write config: 0x%llx\n", val);
532 out_be64(hose->cfg_data + PCIE_REG_PHB_CONFIG, val);
534 /* Enable error reporting */
535 out_be64(hose->cfg_data + 0xe00,
536 in_be64(hose->cfg_data + 0xe00) | 0x0008000000000000ull);
538 /* Mask an error that's generated when doing config space probe
540 * XXX Maybe we should only mask it around config space cycles... that or
541 * ignore it when we know we had a config space cycle recently ?
543 out_be64(hose->cfg_data + PCIE_REG_DMA_ERR_STATUS_MASK, 0x8000000000000000ull);
544 out_be64(hose->cfg_data + PCIE_REG_DMA_ERR1_STATUS_MASK, 0x8000000000000000ull);
546 /* Enable UTL errors, for now, all of them got to UTL irq 1
548 * We similarily mask one UTL error caused apparently during normal
549 * probing. We also mask the link up error
551 out_be64(hose->cfg_data + PCIE_UTL_SYS_BUS_AGENT_ERR_SEV, 0);
552 out_be64(hose->cfg_data + PCIE_UTL_RC_ERR_SEVERITY, 0);
553 out_be64(hose->cfg_data + PCIE_UTL_PCIE_PORT_ERROR_SEV, 0);
554 out_be64(hose->cfg_data + PCIE_UTL_SYS_BUS_AGENT_IRQ_EN, 0xffffffff00000000ull);
555 out_be64(hose->cfg_data + PCIE_UTL_PCIE_PORT_IRQ_EN, 0xff5fffff00000000ull);
556 out_be64(hose->cfg_data + PCIE_UTL_EP_ERR_IRQ_EN, 0xffffffff00000000ull);
558 DUMP_REG(PCIE_REG_IO_BASE_ADDR);
559 DUMP_REG(PCIE_REG_IO_BASE_MASK);
560 DUMP_REG(PCIE_REG_IO_START_ADDR);
561 DUMP_REG(PCIE_REG_M32A_BASE_ADDR);
562 DUMP_REG(PCIE_REG_M32A_BASE_MASK);
563 DUMP_REG(PCIE_REG_M32A_START_ADDR);
564 DUMP_REG(PCIE_REG_M32B_BASE_ADDR);
565 DUMP_REG(PCIE_REG_M32B_BASE_MASK);
566 DUMP_REG(PCIE_REG_M32B_START_ADDR);
567 DUMP_REG(PCIE_REG_M64_BASE_ADDR);
568 DUMP_REG(PCIE_REG_M64_BASE_MASK);
569 DUMP_REG(PCIE_REG_M64_START_ADDR);
570 DUMP_REG(PCIE_REG_PHB_CONFIG);
573 static void wsp_pci_wait_io_idle(struct wsp_phb *phb, unsigned long port)
578 for (i = 0; i < 10000; i++) {
579 val = in_be64(phb->hose->cfg_data + 0xe08);
580 if ((val & 0x1900000000000000ull) == 0x0100000000000000ull)
584 pr_warning("PCI IO timeout on domain %d port 0x%lx\n",
585 phb->hose->global_number, port);
588 #define DEF_PCI_AC_RET_pio(name, ret, at, al, aa) \
589 static ret wsp_pci_##name at \
591 struct iowa_bus *bus; \
592 struct wsp_phb *phb; \
593 unsigned long flags; \
595 bus = iowa_pio_find_bus(aa); \
597 phb = bus->private; \
598 spin_lock_irqsave(&phb->lock, flags); \
599 wsp_pci_wait_io_idle(phb, aa); \
600 rval = __do_##name al; \
601 spin_unlock_irqrestore(&phb->lock, flags); \
605 #define DEF_PCI_AC_NORET_pio(name, at, al, aa) \
606 static void wsp_pci_##name at \
608 struct iowa_bus *bus; \
609 struct wsp_phb *phb; \
610 unsigned long flags; \
611 bus = iowa_pio_find_bus(aa); \
613 phb = bus->private; \
614 spin_lock_irqsave(&phb->lock, flags); \
615 wsp_pci_wait_io_idle(phb, aa); \
617 spin_unlock_irqrestore(&phb->lock, flags); \
620 #define DEF_PCI_AC_RET_mem(name, ret, at, al, aa)
621 #define DEF_PCI_AC_NORET_mem(name, at, al, aa)
623 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
624 DEF_PCI_AC_RET_##space(name, ret, at, al, aa)
626 #define DEF_PCI_AC_NORET(name, at, al, space, aa) \
627 DEF_PCI_AC_NORET_##space(name, at, al, aa) \
630 #include <asm/io-defs.h>
632 #undef DEF_PCI_AC_RET
633 #undef DEF_PCI_AC_NORET
635 static struct ppc_pci_io wsp_pci_iops = {
639 .outb = wsp_pci_outb,
640 .outw = wsp_pci_outw,
641 .outl = wsp_pci_outl,
642 .insb = wsp_pci_insb,
643 .insw = wsp_pci_insw,
644 .insl = wsp_pci_insl,
645 .outsb = wsp_pci_outsb,
646 .outsw = wsp_pci_outsw,
647 .outsl = wsp_pci_outsl,
650 static int __init wsp_setup_one_phb(struct device_node *np)
652 struct pci_controller *hose;
655 pr_info("PCI: Setting up PCIe host bridge 0x%s\n", np->full_name);
657 phb = zalloc_maybe_bootmem(sizeof(struct wsp_phb), GFP_KERNEL);
660 hose = pcibios_alloc_controller(np);
662 /* Can't really free the phb */
665 hose->private_data = phb;
668 INIT_LIST_HEAD(&phb->dma_tables);
669 spin_lock_init(&phb->lock);
671 /* XXX Use bus-range property ? */
672 hose->first_busno = 0;
673 hose->last_busno = 0xff;
675 /* We use cfg_data as the address for the whole bridge MMIO space
677 hose->cfg_data = of_iomap(hose->dn, 0);
679 pr_debug("PCIe registers mapped at 0x%p\n", hose->cfg_data);
681 /* Get the ranges of the device-tree */
682 pci_process_bridge_OF_ranges(hose, np, 0);
684 /* XXX Force re-assigning of everything for now */
685 pci_add_flags(PCI_REASSIGN_ALL_BUS | PCI_REASSIGN_ALL_RSRC |
686 PCI_ENABLE_PROC_DOMAINS);
688 /* Calculate how the TCE space is divided */
690 phb->dma32_num_regions = NUM_DMA32_REGIONS;
691 if (phb->dma32_num_regions > MAX_TABLE_TVT_COUNT) {
692 pr_warning("IOMMU: Clamped to %d DMA32 regions\n",
693 MAX_TABLE_TVT_COUNT);
694 phb->dma32_num_regions = MAX_TABLE_TVT_COUNT;
696 phb->dma32_region_size = 0x80000000 / phb->dma32_num_regions;
698 BUG_ON(!is_power_of_2(phb->dma32_region_size));
700 /* Setup config ops */
701 hose->ops = &wsp_pcie_pci_ops;
703 /* Configure the HW */
704 wsp_pcie_configure_hw(hose);
706 /* Instanciate IO workarounds */
707 iowa_register_bus(hose, &wsp_pci_iops, NULL, phb);
708 #ifdef CONFIG_PCI_MSI
709 wsp_setup_phb_msi(hose);
712 /* Add to global list */
713 list_add(&phb->all, &wsp_phbs);
718 void __init wsp_setup_pci(void)
720 struct device_node *np;
723 /* Find host bridges */
724 for_each_compatible_node(np, "pciex", PCIE_COMPATIBLE) {
725 rc = wsp_setup_one_phb(np);
727 pr_err("Failed to setup PCIe bridge %s, rc=%d\n",
731 /* Establish device-tree linkage */
734 /* Set DMA ops to use TCEs */
736 pr_info("PCI-E: Disabled TCEs, using direct DMA\n");
737 set_pci_dma_ops(&dma_direct_ops);
739 ppc_md.pci_dma_dev_setup = wsp_pci_dma_dev_setup;
740 ppc_md.tce_build = tce_build_wsp;
741 ppc_md.tce_free = tce_free_wsp;
742 set_pci_dma_ops(&dma_iommu_ops);
746 #define err_debug(fmt...) pr_debug(fmt)
747 //#define err_debug(fmt...)
749 static int __init wsp_pci_get_err_irq_no_dt(struct device_node *np)
754 /* Ok, no interrupts property, let's try to find our child P2P */
755 np = of_get_next_child(np, NULL);
759 /* Grab it's interrupt map */
760 prop = of_get_property(np, "interrupt-map", NULL);
764 /* Grab one of the interrupts in there, keep the low 4 bits */
765 hw_irq = prop[5] & 0xf;
767 /* 0..4 for PHB 0 and 5..9 for PHB 1 */
772 hw_irq |= prop[5] & ~0xf;
774 err_debug("PCI: Using 0x%x as error IRQ for %s\n",
775 hw_irq, np->parent->full_name);
776 return irq_create_mapping(NULL, hw_irq);
779 static const struct {
783 #define DREG(x) { PCIE_REG_##x, #x }
784 #define DUTL(x) { PCIE_UTL_##x, "UTL_" #x }
785 /* Architected registers except CONFIG_ and IODA
786 * to avoid side effects
788 DREG(DMA_CHAN_STATUS),
789 DREG(CPU_LOADSTORE_STATUS),
796 DREG(M32A_BASE_ADDR),
797 DREG(M32A_BASE_MASK),
798 DREG(M32A_START_ADDR),
799 DREG(M32B_BASE_ADDR),
800 DREG(M32B_BASE_MASK),
801 DREG(M32B_START_ADDR),
804 DREG(M64_START_ADDR),
811 DREG(PAPR_ERR_INJ_CONTROL),
812 DREG(PAPR_ERR_INJ_ADDR),
813 DREG(PAPR_ERR_INJ_MASK),
816 DUTL(SYS_BUS_CONTROL),
818 DUTL(SYS_BUS_AGENT_STATUS),
819 DUTL(SYS_BUS_AGENT_ERR_SEV),
820 DUTL(SYS_BUS_AGENT_IRQ_EN),
821 DUTL(SYS_BUS_BURST_SZ_CONF),
823 DUTL(OUT_POST_HDR_BUF_ALLOC),
824 DUTL(OUT_POST_DAT_BUF_ALLOC),
825 DUTL(IN_POST_HDR_BUF_ALLOC),
826 DUTL(IN_POST_DAT_BUF_ALLOC),
827 DUTL(OUT_NP_BUF_ALLOC),
828 DUTL(IN_NP_BUF_ALLOC),
829 DUTL(PCIE_TAGS_ALLOC),
830 DUTL(GBIF_READ_TAGS_ALLOC),
832 DUTL(PCIE_PORT_CONTROL),
833 DUTL(PCIE_PORT_STATUS),
834 DUTL(PCIE_PORT_ERROR_SEV),
835 DUTL(PCIE_PORT_IRQ_EN),
837 DUTL(RC_ERR_SEVERITY),
840 DUTL(EP_ERR_SEVERITY),
845 /* PCIe stack regs */
846 DREG(SYSTEM_CONFIG1),
847 DREG(SYSTEM_CONFIG2),
848 DREG(EP_SYSTEM_CONFIG),
855 DREG(ERR_REPORT_CONTROL),
859 DREG(BUFFERS_CONFIG),
862 DREG(PF0_SRIOV_STATUS),
863 DREG(PF1_SRIOV_STATUS),
865 DREG(POR_SYSTEM_CONFIG),
867 /* Internal logic regs */
871 DREG(PHB_TIMEOUT_CONTROL1),
872 DREG(PHB_QUIESCE_DMA),
873 DREG(PHB_DMA_READ_TAG_ACTV),
874 DREG(PHB_TCE_READ_TAG_ACTV),
878 DREG(LEM_FIR_AND_MASK),
879 DREG(LEM_FIR_OR_MASK),
882 DREG(LEM_ERROR_MASK),
883 DREG(LEM_ERROR_AND_MASK),
884 DREG(LEM_ERROR_OR_MASK),
886 /* Error traps registers */
887 DREG(PHB_ERR_STATUS),
888 DREG(PHB_ERR_STATUS),
889 DREG(PHB_ERR1_STATUS),
890 DREG(PHB_ERR_INJECT),
891 DREG(PHB_ERR_LEM_ENABLE),
892 DREG(PHB_ERR_IRQ_ENABLE),
893 DREG(PHB_ERR_FREEZE_ENABLE),
894 DREG(PHB_ERR_SIDE_ENABLE),
897 DREG(PHB_ERR_STATUS_MASK),
898 DREG(PHB_ERR1_STATUS_MASK),
899 DREG(MMIO_ERR_STATUS),
900 DREG(MMIO_ERR1_STATUS),
901 DREG(MMIO_ERR_INJECT),
902 DREG(MMIO_ERR_LEM_ENABLE),
903 DREG(MMIO_ERR_IRQ_ENABLE),
904 DREG(MMIO_ERR_FREEZE_ENABLE),
905 DREG(MMIO_ERR_SIDE_ENABLE),
906 DREG(MMIO_ERR_LOG_0),
907 DREG(MMIO_ERR_LOG_1),
908 DREG(MMIO_ERR_STATUS_MASK),
909 DREG(MMIO_ERR1_STATUS_MASK),
910 DREG(DMA_ERR_STATUS),
911 DREG(DMA_ERR1_STATUS),
912 DREG(DMA_ERR_INJECT),
913 DREG(DMA_ERR_LEM_ENABLE),
914 DREG(DMA_ERR_IRQ_ENABLE),
915 DREG(DMA_ERR_FREEZE_ENABLE),
916 DREG(DMA_ERR_SIDE_ENABLE),
919 DREG(DMA_ERR_STATUS_MASK),
920 DREG(DMA_ERR1_STATUS_MASK),
922 /* Debug and Trace registers */
923 DREG(PHB_DEBUG_CONTROL0),
924 DREG(PHB_DEBUG_STATUS0),
925 DREG(PHB_DEBUG_CONTROL1),
926 DREG(PHB_DEBUG_STATUS1),
927 DREG(PHB_DEBUG_CONTROL2),
928 DREG(PHB_DEBUG_STATUS2),
929 DREG(PHB_DEBUG_CONTROL3),
930 DREG(PHB_DEBUG_STATUS3),
931 DREG(PHB_DEBUG_CONTROL4),
932 DREG(PHB_DEBUG_STATUS4),
933 DREG(PHB_DEBUG_CONTROL5),
934 DREG(PHB_DEBUG_STATUS5),
936 /* Don't seem to exist ...
937 DREG(PHB_DEBUG_CONTROL6),
938 DREG(PHB_DEBUG_STATUS6),
942 static int wsp_pci_regs_show(struct seq_file *m, void *private)
944 struct wsp_phb *phb = m->private;
945 struct pci_controller *hose = phb->hose;
948 for (i = 0; i < ARRAY_SIZE(wsp_pci_regs); i++) {
949 /* Skip write-only regs */
950 if (wsp_pci_regs[i].offset == 0xc08 ||
951 wsp_pci_regs[i].offset == 0xc10 ||
952 wsp_pci_regs[i].offset == 0xc38 ||
953 wsp_pci_regs[i].offset == 0xc40)
955 seq_printf(m, "0x%03x: 0x%016llx %s\n",
956 wsp_pci_regs[i].offset,
957 in_be64(hose->cfg_data + wsp_pci_regs[i].offset),
958 wsp_pci_regs[i].name);
963 static int wsp_pci_regs_open(struct inode *inode, struct file *file)
965 return single_open(file, wsp_pci_regs_show, inode->i_private);
968 static const struct file_operations wsp_pci_regs_fops = {
969 .open = wsp_pci_regs_open,
972 .release = single_release,
975 static int wsp_pci_reg_set(void *data, u64 val)
977 out_be64((void __iomem *)data, val);
981 static int wsp_pci_reg_get(void *data, u64 *val)
983 *val = in_be64((void __iomem *)data);
987 DEFINE_SIMPLE_ATTRIBUTE(wsp_pci_reg_fops, wsp_pci_reg_get, wsp_pci_reg_set, "0x%llx\n");
989 static irqreturn_t wsp_pci_err_irq(int irq, void *dev_id)
991 struct wsp_phb *phb = dev_id;
992 struct pci_controller *hose = phb->hose;
993 irqreturn_t handled = IRQ_NONE;
994 struct wsp_pcie_err_log_data ed;
996 pr_err("PCI: Error interrupt on %s (PHB %d)\n",
997 hose->dn->full_name, hose->global_number);
999 memset(&ed, 0, sizeof(ed));
1001 /* Read and clear UTL errors */
1002 ed.utl_sys_err = in_be64(hose->cfg_data + PCIE_UTL_SYS_BUS_AGENT_STATUS);
1004 out_be64(hose->cfg_data + PCIE_UTL_SYS_BUS_AGENT_STATUS, ed.utl_sys_err);
1005 ed.utl_port_err = in_be64(hose->cfg_data + PCIE_UTL_PCIE_PORT_STATUS);
1006 if (ed.utl_port_err)
1007 out_be64(hose->cfg_data + PCIE_UTL_PCIE_PORT_STATUS, ed.utl_port_err);
1008 ed.utl_rc_err = in_be64(hose->cfg_data + PCIE_UTL_RC_STATUS);
1010 out_be64(hose->cfg_data + PCIE_UTL_RC_STATUS, ed.utl_rc_err);
1012 /* Read and clear main trap errors */
1013 ed.phb_err = in_be64(hose->cfg_data + PCIE_REG_PHB_ERR_STATUS);
1015 ed.phb_err1 = in_be64(hose->cfg_data + PCIE_REG_PHB_ERR1_STATUS);
1016 ed.phb_log0 = in_be64(hose->cfg_data + PCIE_REG_PHB_ERR_LOG_0);
1017 ed.phb_log1 = in_be64(hose->cfg_data + PCIE_REG_PHB_ERR_LOG_1);
1018 out_be64(hose->cfg_data + PCIE_REG_PHB_ERR1_STATUS, 0);
1019 out_be64(hose->cfg_data + PCIE_REG_PHB_ERR_STATUS, 0);
1021 ed.mmio_err = in_be64(hose->cfg_data + PCIE_REG_MMIO_ERR_STATUS);
1023 ed.mmio_err1 = in_be64(hose->cfg_data + PCIE_REG_MMIO_ERR1_STATUS);
1024 ed.mmio_log0 = in_be64(hose->cfg_data + PCIE_REG_MMIO_ERR_LOG_0);
1025 ed.mmio_log1 = in_be64(hose->cfg_data + PCIE_REG_MMIO_ERR_LOG_1);
1026 out_be64(hose->cfg_data + PCIE_REG_MMIO_ERR1_STATUS, 0);
1027 out_be64(hose->cfg_data + PCIE_REG_MMIO_ERR_STATUS, 0);
1029 ed.dma_err = in_be64(hose->cfg_data + PCIE_REG_DMA_ERR_STATUS);
1031 ed.dma_err1 = in_be64(hose->cfg_data + PCIE_REG_DMA_ERR1_STATUS);
1032 ed.dma_log0 = in_be64(hose->cfg_data + PCIE_REG_DMA_ERR_LOG_0);
1033 ed.dma_log1 = in_be64(hose->cfg_data + PCIE_REG_DMA_ERR_LOG_1);
1034 out_be64(hose->cfg_data + PCIE_REG_DMA_ERR1_STATUS, 0);
1035 out_be64(hose->cfg_data + PCIE_REG_DMA_ERR_STATUS, 0);
1038 /* Now print things out */
1040 pr_err(" PHB Error Status : 0x%016llx\n", ed.phb_err);
1041 pr_err(" PHB First Error Status: 0x%016llx\n", ed.phb_err1);
1042 pr_err(" PHB Error Log 0 : 0x%016llx\n", ed.phb_log0);
1043 pr_err(" PHB Error Log 1 : 0x%016llx\n", ed.phb_log1);
1046 pr_err(" MMIO Error Status : 0x%016llx\n", ed.mmio_err);
1047 pr_err(" MMIO First Error Status: 0x%016llx\n", ed.mmio_err1);
1048 pr_err(" MMIO Error Log 0 : 0x%016llx\n", ed.mmio_log0);
1049 pr_err(" MMIO Error Log 1 : 0x%016llx\n", ed.mmio_log1);
1052 pr_err(" DMA Error Status : 0x%016llx\n", ed.dma_err);
1053 pr_err(" DMA First Error Status: 0x%016llx\n", ed.dma_err1);
1054 pr_err(" DMA Error Log 0 : 0x%016llx\n", ed.dma_log0);
1055 pr_err(" DMA Error Log 1 : 0x%016llx\n", ed.dma_log1);
1058 pr_err(" UTL Sys Error Status : 0x%016llx\n", ed.utl_sys_err);
1059 if (ed.utl_port_err)
1060 pr_err(" UTL Port Error Status : 0x%016llx\n", ed.utl_port_err);
1062 pr_err(" UTL RC Error Status : 0x%016llx\n", ed.utl_rc_err);
1064 /* Interrupts are caused by the error traps. If we had any error there
1065 * we loop again in case the UTL buffered some new stuff between
1066 * going there and going to the traps
1068 if (ed.dma_err || ed.mmio_err || ed.phb_err) {
1069 handled = IRQ_HANDLED;
1075 static void __init wsp_setup_pci_err_reporting(struct wsp_phb *phb)
1077 struct pci_controller *hose = phb->hose;
1081 /* Create a debugfs file for that PHB */
1082 sprintf(fname, "phb%d", phb->hose->global_number);
1083 phb->ddir = debugfs_create_dir(fname, powerpc_debugfs_root);
1085 /* Some useful debug output */
1087 struct dentry *d = debugfs_create_dir("regs", phb->ddir);
1090 for (i = 0; i < ARRAY_SIZE(wsp_pci_regs); i++) {
1091 sprintf(tmp, "%03x_%s", wsp_pci_regs[i].offset,
1092 wsp_pci_regs[i].name);
1093 debugfs_create_file(tmp, 0600, d,
1094 hose->cfg_data + wsp_pci_regs[i].offset,
1097 debugfs_create_file("all_regs", 0600, phb->ddir, phb, &wsp_pci_regs_fops);
1100 /* Find the IRQ number for that PHB */
1101 err_irq = irq_of_parse_and_map(hose->dn, 0);
1103 /* XXX Error IRQ lacking from device-tree */
1104 err_irq = wsp_pci_get_err_irq_no_dt(hose->dn);
1106 pr_err("PCI: Failed to fetch error interrupt for %s\n",
1107 hose->dn->full_name);
1111 rc = request_irq(err_irq, wsp_pci_err_irq, 0, "wsp_pci error", phb);
1113 pr_err("PCI: Failed to request interrupt for %s\n",
1114 hose->dn->full_name);
1116 /* Enable interrupts for all errors for now */
1117 out_be64(hose->cfg_data + PCIE_REG_PHB_ERR_IRQ_ENABLE, 0xffffffffffffffffull);
1118 out_be64(hose->cfg_data + PCIE_REG_MMIO_ERR_IRQ_ENABLE, 0xffffffffffffffffull);
1119 out_be64(hose->cfg_data + PCIE_REG_DMA_ERR_IRQ_ENABLE, 0xffffffffffffffffull);
1123 * This is called later to hookup with the error interrupt
1125 static int __init wsp_setup_pci_late(void)
1127 struct wsp_phb *phb;
1129 list_for_each_entry(phb, &wsp_phbs, all)
1130 wsp_setup_pci_err_reporting(phb);
1134 arch_initcall(wsp_setup_pci_late);