arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22 #include "lapic.h"
  23
  24 #include <linux/kvm_host.h>
  25 #include <linux/module.h>
  26 #include <linux/kernel.h>
  27 #include <linux/mm.h>
  28 #include <linux/highmem.h>
  29 #include <linux/sched.h>
  30 #include <linux/moduleparam.h>
  31 #include <linux/mod_devicetable.h>
  32 #include <linux/trace_events.h>
  33 #include <linux/slab.h>
  34 #include <linux/tboot.h>
  35 #include <linux/hrtimer.h>
  36 #include "kvm_cache_regs.h"
  37 #include "x86.h"
  38
  39 #include <asm/cpu.h>
  40 #include <asm/io.h>
  41 #include <asm/desc.h>
  42 #include <asm/vmx.h>
  43 #include <asm/virtext.h>
  44 #include <asm/mce.h>
  45 #include <asm/fpu/internal.h>
  46 #include <asm/perf_event.h>
  47 #include <asm/debugreg.h>
  48 #include <asm/kexec.h>
  49 #include <asm/apic.h>
  50 #include <asm/irq_remapping.h>
  51
  52 #include "trace.h"
  53 #include "pmu.h"
  54
  55 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  56 #define __ex_clear(x, reg) \
  57         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  58
  59 MODULE_AUTHOR("Qumranet");
  60 MODULE_LICENSE("GPL");
  61
  62 static const struct x86_cpu_id vmx_cpu_id[] = {
  63         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  64         {}
  65 };
  66 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  67
  68 static bool __read_mostly enable_vpid = 1;
  69 module_param_named(vpid, enable_vpid, bool, 0444);
  70
  71 static bool __read_mostly flexpriority_enabled = 1;
  72 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  73
  74 static bool __read_mostly enable_ept = 1;
  75 module_param_named(ept, enable_ept, bool, S_IRUGO);
  76
  77 static bool __read_mostly enable_unrestricted_guest = 1;
  78 module_param_named(unrestricted_guest,
  79                         enable_unrestricted_guest, bool, S_IRUGO);
  80
  81 static bool __read_mostly enable_ept_ad_bits = 1;
  82 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  83
  84 static bool __read_mostly emulate_invalid_guest_state = true;
  85 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  86
  87 static bool __read_mostly vmm_exclusive = 1;
  88 module_param(vmm_exclusive, bool, S_IRUGO);
  89
  90 static bool __read_mostly fasteoi = 1;
  91 module_param(fasteoi, bool, S_IRUGO);
  92
  93 static bool __read_mostly enable_apicv = 1;
  94 module_param(enable_apicv, bool, S_IRUGO);
  95
  96 static bool __read_mostly enable_shadow_vmcs = 1;
  97 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  98 /*
  99  * If nested=1, nested virtualization is supported, i.e., guests may use
 100  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 101  * use VMX instructions.
 102  */
 103 static bool __read_mostly nested = 0;
 104 module_param(nested, bool, S_IRUGO);
 105
 106 static u64 __read_mostly host_xss;
 107
 108 static bool __read_mostly enable_pml = 1;
 109 module_param_named(pml, enable_pml, bool, S_IRUGO);
 110
 111 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 112
 113 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 114 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 115 #define KVM_VM_CR0_ALWAYS_ON                                            \
 116         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 117 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 118         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 119          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 120
 121 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 122 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 123
 124 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 125
 126 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 127
 128 /*
 129  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 130  * ple_gap:    upper bound on the amount of time between two successive
 131  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 132  *             According to test, this time is usually smaller than 128 cycles.
 133  * ple_window: upper bound on the amount of time a guest is allowed to execute
 134  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 135  *             less than 2^12 cycles
 136  * Time is measured based on a counter that runs at the same rate as the TSC,
 137  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 138  */
 139 #define KVM_VMX_DEFAULT_PLE_GAP           128
 140 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 141 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 142 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 143 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 144                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 145
 146 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 147 module_param(ple_gap, int, S_IRUGO);
 148
 149 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 150 module_param(ple_window, int, S_IRUGO);
 151
 152 /* Default doubles per-vcpu window every exit. */
 153 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 154 module_param(ple_window_grow, int, S_IRUGO);
 155
 156 /* Default resets per-vcpu window every exit to ple_window. */
 157 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 158 module_param(ple_window_shrink, int, S_IRUGO);
 159
 160 /* Default is to compute the maximum so we can never overflow. */
 161 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 162 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 163 module_param(ple_window_max, int, S_IRUGO);
 164
 165 extern const ulong vmx_return;
 166
 167 #define NR_AUTOLOAD_MSRS 8
 168 #define VMCS02_POOL_SIZE 1
 169
 170 struct vmcs {
 171         u32 revision_id;
 172         u32 abort;
 173         char data[0];
 174 };
 175
 176 /*
 177  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 178  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 179  * loaded on this CPU (so we can clear them if the CPU goes down).
 180  */
 181 struct loaded_vmcs {
 182         struct vmcs *vmcs;
 183         int cpu;
 184         int launched;
 185         struct list_head loaded_vmcss_on_cpu_link;
 186 };
 187
 188 struct shared_msr_entry {
 189         unsigned index;
 190         u64 data;
 191         u64 mask;
 192 };
 193
 194 /*
 195  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 196  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 197  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 198  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 199  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 200  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 201  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 202  * underlying hardware which will be used to run L2.
 203  * This structure is packed to ensure that its layout is identical across
 204  * machines (necessary for live migration).
 205  * If there are changes in this struct, VMCS12_REVISION must be changed.
 206  */
 207 typedef u64 natural_width;
 208 struct __packed vmcs12 {
 209         /* According to the Intel spec, a VMCS region must start with the
 210          * following two fields. Then follow implementation-specific data.
 211          */
 212         u32 revision_id;
 213         u32 abort;
 214
 215         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 216         u32 padding[7]; /* room for future expansion */
 217
 218         u64 io_bitmap_a;
 219         u64 io_bitmap_b;
 220         u64 msr_bitmap;
 221         u64 vm_exit_msr_store_addr;
 222         u64 vm_exit_msr_load_addr;
 223         u64 vm_entry_msr_load_addr;
 224         u64 tsc_offset;
 225         u64 virtual_apic_page_addr;
 226         u64 apic_access_addr;
 227         u64 posted_intr_desc_addr;
 228         u64 ept_pointer;
 229         u64 eoi_exit_bitmap0;
 230         u64 eoi_exit_bitmap1;
 231         u64 eoi_exit_bitmap2;
 232         u64 eoi_exit_bitmap3;
 233         u64 xss_exit_bitmap;
 234         u64 guest_physical_address;
 235         u64 vmcs_link_pointer;
 236         u64 guest_ia32_debugctl;
 237         u64 guest_ia32_pat;
 238         u64 guest_ia32_efer;
 239         u64 guest_ia32_perf_global_ctrl;
 240         u64 guest_pdptr0;
 241         u64 guest_pdptr1;
 242         u64 guest_pdptr2;
 243         u64 guest_pdptr3;
 244         u64 guest_bndcfgs;
 245         u64 host_ia32_pat;
 246         u64 host_ia32_efer;
 247         u64 host_ia32_perf_global_ctrl;
 248         u64 padding64[8]; /* room for future expansion */
 249         /*
 250          * To allow migration of L1 (complete with its L2 guests) between
 251          * machines of different natural widths (32 or 64 bit), we cannot have
 252          * unsigned long fields with no explict size. We use u64 (aliased
 253          * natural_width) instead. Luckily, x86 is little-endian.
 254          */
 255         natural_width cr0_guest_host_mask;
 256         natural_width cr4_guest_host_mask;
 257         natural_width cr0_read_shadow;
 258         natural_width cr4_read_shadow;
 259         natural_width cr3_target_value0;
 260         natural_width cr3_target_value1;
 261         natural_width cr3_target_value2;
 262         natural_width cr3_target_value3;
 263         natural_width exit_qualification;
 264         natural_width guest_linear_address;
 265         natural_width guest_cr0;
 266         natural_width guest_cr3;
 267         natural_width guest_cr4;
 268         natural_width guest_es_base;
 269         natural_width guest_cs_base;
 270         natural_width guest_ss_base;
 271         natural_width guest_ds_base;
 272         natural_width guest_fs_base;
 273         natural_width guest_gs_base;
 274         natural_width guest_ldtr_base;
 275         natural_width guest_tr_base;
 276         natural_width guest_gdtr_base;
 277         natural_width guest_idtr_base;
 278         natural_width guest_dr7;
 279         natural_width guest_rsp;
 280         natural_width guest_rip;
 281         natural_width guest_rflags;
 282         natural_width guest_pending_dbg_exceptions;
 283         natural_width guest_sysenter_esp;
 284         natural_width guest_sysenter_eip;
 285         natural_width host_cr0;
 286         natural_width host_cr3;
 287         natural_width host_cr4;
 288         natural_width host_fs_base;
 289         natural_width host_gs_base;
 290         natural_width host_tr_base;
 291         natural_width host_gdtr_base;
 292         natural_width host_idtr_base;
 293         natural_width host_ia32_sysenter_esp;
 294         natural_width host_ia32_sysenter_eip;
 295         natural_width host_rsp;
 296         natural_width host_rip;
 297         natural_width paddingl[8]; /* room for future expansion */
 298         u32 pin_based_vm_exec_control;
 299         u32 cpu_based_vm_exec_control;
 300         u32 exception_bitmap;
 301         u32 page_fault_error_code_mask;
 302         u32 page_fault_error_code_match;
 303         u32 cr3_target_count;
 304         u32 vm_exit_controls;
 305         u32 vm_exit_msr_store_count;
 306         u32 vm_exit_msr_load_count;
 307         u32 vm_entry_controls;
 308         u32 vm_entry_msr_load_count;
 309         u32 vm_entry_intr_info_field;
 310         u32 vm_entry_exception_error_code;
 311         u32 vm_entry_instruction_len;
 312         u32 tpr_threshold;
 313         u32 secondary_vm_exec_control;
 314         u32 vm_instruction_error;
 315         u32 vm_exit_reason;
 316         u32 vm_exit_intr_info;
 317         u32 vm_exit_intr_error_code;
 318         u32 idt_vectoring_info_field;
 319         u32 idt_vectoring_error_code;
 320         u32 vm_exit_instruction_len;
 321         u32 vmx_instruction_info;
 322         u32 guest_es_limit;
 323         u32 guest_cs_limit;
 324         u32 guest_ss_limit;
 325         u32 guest_ds_limit;
 326         u32 guest_fs_limit;
 327         u32 guest_gs_limit;
 328         u32 guest_ldtr_limit;
 329         u32 guest_tr_limit;
 330         u32 guest_gdtr_limit;
 331         u32 guest_idtr_limit;
 332         u32 guest_es_ar_bytes;
 333         u32 guest_cs_ar_bytes;
 334         u32 guest_ss_ar_bytes;
 335         u32 guest_ds_ar_bytes;
 336         u32 guest_fs_ar_bytes;
 337         u32 guest_gs_ar_bytes;
 338         u32 guest_ldtr_ar_bytes;
 339         u32 guest_tr_ar_bytes;
 340         u32 guest_interruptibility_info;
 341         u32 guest_activity_state;
 342         u32 guest_sysenter_cs;
 343         u32 host_ia32_sysenter_cs;
 344         u32 vmx_preemption_timer_value;
 345         u32 padding32[7]; /* room for future expansion */
 346         u16 virtual_processor_id;
 347         u16 posted_intr_nv;
 348         u16 guest_es_selector;
 349         u16 guest_cs_selector;
 350         u16 guest_ss_selector;
 351         u16 guest_ds_selector;
 352         u16 guest_fs_selector;
 353         u16 guest_gs_selector;
 354         u16 guest_ldtr_selector;
 355         u16 guest_tr_selector;
 356         u16 guest_intr_status;
 357         u16 host_es_selector;
 358         u16 host_cs_selector;
 359         u16 host_ss_selector;
 360         u16 host_ds_selector;
 361         u16 host_fs_selector;
 362         u16 host_gs_selector;
 363         u16 host_tr_selector;
 364 };
 365
 366 /*
 367  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 368  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 369  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 370  */
 371 #define VMCS12_REVISION 0x11e57ed0
 372
 373 /*
 374  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 375  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 376  * current implementation, 4K are reserved to avoid future complications.
 377  */
 378 #define VMCS12_SIZE 0x1000
 379
 380 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 381 struct vmcs02_list {
 382         struct list_head list;
 383         gpa_t vmptr;
 384         struct loaded_vmcs vmcs02;
 385 };
 386
 387 /*
 388  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 389  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 390  */
 391 struct nested_vmx {
 392         /* Has the level1 guest done vmxon? */
 393         bool vmxon;
 394         gpa_t vmxon_ptr;
 395
 396         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 397         gpa_t current_vmptr;
 398         /* The host-usable pointer to the above */
 399         struct page *current_vmcs12_page;
 400         struct vmcs12 *current_vmcs12;
 401         struct vmcs *current_shadow_vmcs;
 402         /*
 403          * Indicates if the shadow vmcs must be updated with the
 404          * data hold by vmcs12
 405          */
 406         bool sync_shadow_vmcs;
 407
 408         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 409         struct list_head vmcs02_pool;
 410         int vmcs02_num;
 411         u64 vmcs01_tsc_offset;
 412         /* L2 must run next, and mustn't decide to exit to L1. */
 413         bool nested_run_pending;
 414         /*
 415          * Guest pages referred to in vmcs02 with host-physical pointers, so
 416          * we must keep them pinned while L2 runs.
 417          */
 418         struct page *apic_access_page;
 419         struct page *virtual_apic_page;
 420         struct page *pi_desc_page;
 421         struct pi_desc *pi_desc;
 422         bool pi_pending;
 423         u16 posted_intr_nv;
 424         u64 msr_ia32_feature_control;
 425
 426         struct hrtimer preemption_timer;
 427         bool preemption_timer_expired;
 428
 429         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 430         u64 vmcs01_debugctl;
 431
 432         u16 vpid02;
 433         u16 last_vpid;
 434
 435         u32 nested_vmx_procbased_ctls_low;
 436         u32 nested_vmx_procbased_ctls_high;
 437         u32 nested_vmx_true_procbased_ctls_low;
 438         u32 nested_vmx_secondary_ctls_low;
 439         u32 nested_vmx_secondary_ctls_high;
 440         u32 nested_vmx_pinbased_ctls_low;
 441         u32 nested_vmx_pinbased_ctls_high;
 442         u32 nested_vmx_exit_ctls_low;
 443         u32 nested_vmx_exit_ctls_high;
 444         u32 nested_vmx_true_exit_ctls_low;
 445         u32 nested_vmx_entry_ctls_low;
 446         u32 nested_vmx_entry_ctls_high;
 447         u32 nested_vmx_true_entry_ctls_low;
 448         u32 nested_vmx_misc_low;
 449         u32 nested_vmx_misc_high;
 450         u32 nested_vmx_ept_caps;
 451         u32 nested_vmx_vpid_caps;
 452 };
 453
 454 #define POSTED_INTR_ON  0
 455 #define POSTED_INTR_SN  1
 456
 457 /* Posted-Interrupt Descriptor */
 458 struct pi_desc {
 459         u32 pir[8];     /* Posted interrupt requested */
 460         union {
 461                 struct {
 462                                 /* bit 256 - Outstanding Notification */
 463                         u16     on      : 1,
 464                                 /* bit 257 - Suppress Notification */
 465                                 sn      : 1,
 466                                 /* bit 271:258 - Reserved */
 467                                 rsvd_1  : 14;
 468                                 /* bit 279:272 - Notification Vector */
 469                         u8      nv;
 470                                 /* bit 287:280 - Reserved */
 471                         u8      rsvd_2;
 472                                 /* bit 319:288 - Notification Destination */
 473                         u32     ndst;
 474                 };
 475                 u64 control;
 476         };
 477         u32 rsvd[6];
 478 } __aligned(64);
 479
 480 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 481 {
 482         return test_and_set_bit(POSTED_INTR_ON,
 483                         (unsigned long *)&pi_desc->control);
 484 }
 485
 486 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 487 {
 488         return test_and_clear_bit(POSTED_INTR_ON,
 489                         (unsigned long *)&pi_desc->control);
 490 }
 491
 492 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 493 {
 494         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 495 }
 496
 497 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 498 {
 499         return clear_bit(POSTED_INTR_SN,
 500                         (unsigned long *)&pi_desc->control);
 501 }
 502
 503 static inline void pi_set_sn(struct pi_desc *pi_desc)
 504 {
 505         return set_bit(POSTED_INTR_SN,
 506                         (unsigned long *)&pi_desc->control);
 507 }
 508
 509 static inline int pi_test_on(struct pi_desc *pi_desc)
 510 {
 511         return test_bit(POSTED_INTR_ON,
 512                         (unsigned long *)&pi_desc->control);
 513 }
 514
 515 static inline int pi_test_sn(struct pi_desc *pi_desc)
 516 {
 517         return test_bit(POSTED_INTR_SN,
 518                         (unsigned long *)&pi_desc->control);
 519 }
 520
 521 struct vcpu_vmx {
 522         struct kvm_vcpu       vcpu;
 523         unsigned long         host_rsp;
 524         u8                    fail;
 525         bool                  nmi_known_unmasked;
 526         u32                   exit_intr_info;
 527         u32                   idt_vectoring_info;
 528         ulong                 rflags;
 529         struct shared_msr_entry *guest_msrs;
 530         int                   nmsrs;
 531         int                   save_nmsrs;
 532         unsigned long         host_idt_base;
 533 #ifdef CONFIG_X86_64
 534         u64                   msr_host_kernel_gs_base;
 535         u64                   msr_guest_kernel_gs_base;
 536 #endif
 537         u32 vm_entry_controls_shadow;
 538         u32 vm_exit_controls_shadow;
 539         /*
 540          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 541          * non-nested (L1) guest, it always points to vmcs01. For a nested
 542          * guest (L2), it points to a different VMCS.
 543          */
 544         struct loaded_vmcs    vmcs01;
 545         struct loaded_vmcs   *loaded_vmcs;
 546         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 547         struct msr_autoload {
 548                 unsigned nr;
 549                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 550                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 551         } msr_autoload;
 552         struct {
 553                 int           loaded;
 554                 u16           fs_sel, gs_sel, ldt_sel;
 555 #ifdef CONFIG_X86_64
 556                 u16           ds_sel, es_sel;
 557 #endif
 558                 int           gs_ldt_reload_needed;
 559                 int           fs_reload_needed;
 560                 u64           msr_host_bndcfgs;
 561                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 562         } host_state;
 563         struct {
 564                 int vm86_active;
 565                 ulong save_rflags;
 566                 struct kvm_segment segs[8];
 567         } rmode;
 568         struct {
 569                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 570                 struct kvm_save_segment {
 571                         u16 selector;
 572                         unsigned long base;
 573                         u32 limit;
 574                         u32 ar;
 575                 } seg[8];
 576         } segment_cache;
 577         int vpid;
 578         bool emulation_required;
 579
 580         /* Support for vnmi-less CPUs */
 581         int soft_vnmi_blocked;
 582         ktime_t entry_time;
 583         s64 vnmi_blocked_time;
 584         u32 exit_reason;
 585
 586         /* Posted interrupt descriptor */
 587         struct pi_desc pi_desc;
 588
 589         /* Support for a guest hypervisor (nested VMX) */
 590         struct nested_vmx nested;
 591
 592         /* Dynamic PLE window. */
 593         int ple_window;
 594         bool ple_window_dirty;
 595
 596         /* Support for PML */
 597 #define PML_ENTITY_NUM          512
 598         struct page *pml_pg;
 599
 600         u64 current_tsc_ratio;
 601
 602         bool guest_pkru_valid;
 603         u32 guest_pkru;
 604         u32 host_pkru;
 605 };
 606
 607 enum segment_cache_field {
 608         SEG_FIELD_SEL = 0,
 609         SEG_FIELD_BASE = 1,
 610         SEG_FIELD_LIMIT = 2,
 611         SEG_FIELD_AR = 3,
 612
 613         SEG_FIELD_NR = 4
 614 };
 615
 616 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 617 {
 618         return container_of(vcpu, struct vcpu_vmx, vcpu);
 619 }
 620
 621 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 622 {
 623         return &(to_vmx(vcpu)->pi_desc);
 624 }
 625
 626 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 627 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 628 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 629                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 630
 631
 632 static unsigned long shadow_read_only_fields[] = {
 633         /*
 634          * We do NOT shadow fields that are modified when L0
 635          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 636          * VMXON...) executed by L1.
 637          * For example, VM_INSTRUCTION_ERROR is read
 638          * by L1 if a vmx instruction fails (part of the error path).
 639          * Note the code assumes this logic. If for some reason
 640          * we start shadowing these fields then we need to
 641          * force a shadow sync when L0 emulates vmx instructions
 642          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 643          * by nested_vmx_failValid)
 644          */
 645         VM_EXIT_REASON,
 646         VM_EXIT_INTR_INFO,
 647         VM_EXIT_INSTRUCTION_LEN,
 648         IDT_VECTORING_INFO_FIELD,
 649         IDT_VECTORING_ERROR_CODE,
 650         VM_EXIT_INTR_ERROR_CODE,
 651         EXIT_QUALIFICATION,
 652         GUEST_LINEAR_ADDRESS,
 653         GUEST_PHYSICAL_ADDRESS
 654 };
 655 static int max_shadow_read_only_fields =
 656         ARRAY_SIZE(shadow_read_only_fields);
 657
 658 static unsigned long shadow_read_write_fields[] = {
 659         TPR_THRESHOLD,
 660         GUEST_RIP,
 661         GUEST_RSP,
 662         GUEST_CR0,
 663         GUEST_CR3,
 664         GUEST_CR4,
 665         GUEST_INTERRUPTIBILITY_INFO,
 666         GUEST_RFLAGS,
 667         GUEST_CS_SELECTOR,
 668         GUEST_CS_AR_BYTES,
 669         GUEST_CS_LIMIT,
 670         GUEST_CS_BASE,
 671         GUEST_ES_BASE,
 672         GUEST_BNDCFGS,
 673         CR0_GUEST_HOST_MASK,
 674         CR0_READ_SHADOW,
 675         CR4_READ_SHADOW,
 676         TSC_OFFSET,
 677         EXCEPTION_BITMAP,
 678         CPU_BASED_VM_EXEC_CONTROL,
 679         VM_ENTRY_EXCEPTION_ERROR_CODE,
 680         VM_ENTRY_INTR_INFO_FIELD,
 681         VM_ENTRY_INSTRUCTION_LEN,
 682         VM_ENTRY_EXCEPTION_ERROR_CODE,
 683         HOST_FS_BASE,
 684         HOST_GS_BASE,
 685         HOST_FS_SELECTOR,
 686         HOST_GS_SELECTOR
 687 };
 688 static int max_shadow_read_write_fields =
 689         ARRAY_SIZE(shadow_read_write_fields);
 690
 691 static const unsigned short vmcs_field_to_offset_table[] = {
 692         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 693         FIELD(POSTED_INTR_NV, posted_intr_nv),
 694         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 695         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 696         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 697         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 698         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 699         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 700         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 701         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 702         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 703         FIELD(HOST_ES_SELECTOR, host_es_selector),
 704         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 705         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 706         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 707         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 708         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 709         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 710         FIELD64(IO_BITMAP_A, io_bitmap_a),
 711         FIELD64(IO_BITMAP_B, io_bitmap_b),
 712         FIELD64(MSR_BITMAP, msr_bitmap),
 713         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 714         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 715         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 716         FIELD64(TSC_OFFSET, tsc_offset),
 717         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 718         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 719         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 720         FIELD64(EPT_POINTER, ept_pointer),
 721         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 722         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 723         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 724         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 725         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 726         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 727         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 728         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 729         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 730         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 731         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 732         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 733         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 734         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 735         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 736         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 737         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 738         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 739         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 740         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 741         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 742         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 743         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 744         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 745         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 746         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 747         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 748         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 749         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 750         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 751         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 752         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 753         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 754         FIELD(TPR_THRESHOLD, tpr_threshold),
 755         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 756         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 757         FIELD(VM_EXIT_REASON, vm_exit_reason),
 758         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 759         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 760         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 761         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 762         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 763         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 764         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 765         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 766         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 767         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 768         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 769         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 770         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 771         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 772         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 773         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 774         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 775         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 776         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 777         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 778         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 779         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 780         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 781         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 782         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 783         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 784         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 785         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 786         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 787         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 788         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 789         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 790         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 791         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 792         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 793         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 794         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 795         FIELD(EXIT_QUALIFICATION, exit_qualification),
 796         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 797         FIELD(GUEST_CR0, guest_cr0),
 798         FIELD(GUEST_CR3, guest_cr3),
 799         FIELD(GUEST_CR4, guest_cr4),
 800         FIELD(GUEST_ES_BASE, guest_es_base),
 801         FIELD(GUEST_CS_BASE, guest_cs_base),
 802         FIELD(GUEST_SS_BASE, guest_ss_base),
 803         FIELD(GUEST_DS_BASE, guest_ds_base),
 804         FIELD(GUEST_FS_BASE, guest_fs_base),
 805         FIELD(GUEST_GS_BASE, guest_gs_base),
 806         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 807         FIELD(GUEST_TR_BASE, guest_tr_base),
 808         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 809         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 810         FIELD(GUEST_DR7, guest_dr7),
 811         FIELD(GUEST_RSP, guest_rsp),
 812         FIELD(GUEST_RIP, guest_rip),
 813         FIELD(GUEST_RFLAGS, guest_rflags),
 814         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 815         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 816         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 817         FIELD(HOST_CR0, host_cr0),
 818         FIELD(HOST_CR3, host_cr3),
 819         FIELD(HOST_CR4, host_cr4),
 820         FIELD(HOST_FS_BASE, host_fs_base),
 821         FIELD(HOST_GS_BASE, host_gs_base),
 822         FIELD(HOST_TR_BASE, host_tr_base),
 823         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 824         FIELD(HOST_IDTR_BASE, host_idtr_base),
 825         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 826         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 827         FIELD(HOST_RSP, host_rsp),
 828         FIELD(HOST_RIP, host_rip),
 829 };
 830
 831 static inline short vmcs_field_to_offset(unsigned long field)
 832 {
 833         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 834
 835         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 836             vmcs_field_to_offset_table[field] == 0)
 837                 return -ENOENT;
 838
 839         return vmcs_field_to_offset_table[field];
 840 }
 841
 842 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 843 {
 844         return to_vmx(vcpu)->nested.current_vmcs12;
 845 }
 846
 847 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 848 {
 849         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 850         if (is_error_page(page))
 851                 return NULL;
 852
 853         return page;
 854 }
 855
 856 static void nested_release_page(struct page *page)
 857 {
 858         kvm_release_page_dirty(page);
 859 }
 860
 861 static void nested_release_page_clean(struct page *page)
 862 {
 863         kvm_release_page_clean(page);
 864 }
 865
 866 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 867 static u64 construct_eptp(unsigned long root_hpa);
 868 static void kvm_cpu_vmxon(u64 addr);
 869 static void kvm_cpu_vmxoff(void);
 870 static bool vmx_xsaves_supported(void);
 871 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 872 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 873                             struct kvm_segment *var, int seg);
 874 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 875                             struct kvm_segment *var, int seg);
 876 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 877 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 878 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 879 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 880 static int alloc_identity_pagetable(struct kvm *kvm);
 881
 882 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 883 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 884 /*
 885  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 886  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 887  */
 888 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 889 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 890
 891 /*
 892  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 893  * can find which vCPU should be waken up.
 894  */
 895 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 896 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 897
 898 static unsigned long *vmx_io_bitmap_a;
 899 static unsigned long *vmx_io_bitmap_b;
 900 static unsigned long *vmx_msr_bitmap_legacy;
 901 static unsigned long *vmx_msr_bitmap_longmode;
 902 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 903 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 904 static unsigned long *vmx_msr_bitmap_nested;
 905 static unsigned long *vmx_vmread_bitmap;
 906 static unsigned long *vmx_vmwrite_bitmap;
 907
 908 static bool cpu_has_load_ia32_efer;
 909 static bool cpu_has_load_perf_global_ctrl;
 910
 911 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 912 static DEFINE_SPINLOCK(vmx_vpid_lock);
 913
 914 static struct vmcs_config {
 915         int size;
 916         int order;
 917         u32 revision_id;
 918         u32 pin_based_exec_ctrl;
 919         u32 cpu_based_exec_ctrl;
 920         u32 cpu_based_2nd_exec_ctrl;
 921         u32 vmexit_ctrl;
 922         u32 vmentry_ctrl;
 923 } vmcs_config;
 924
 925 static struct vmx_capability {
 926         u32 ept;
 927         u32 vpid;
 928 } vmx_capability;
 929
 930 #define VMX_SEGMENT_FIELD(seg)                                  \
 931         [VCPU_SREG_##seg] = {                                   \
 932                 .selector = GUEST_##seg##_SELECTOR,             \
 933                 .base = GUEST_##seg##_BASE,                     \
 934                 .limit = GUEST_##seg##_LIMIT,                   \
 935                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 936         }
 937
 938 static const struct kvm_vmx_segment_field {
 939         unsigned selector;
 940         unsigned base;
 941         unsigned limit;
 942         unsigned ar_bytes;
 943 } kvm_vmx_segment_fields[] = {
 944         VMX_SEGMENT_FIELD(CS),
 945         VMX_SEGMENT_FIELD(DS),
 946         VMX_SEGMENT_FIELD(ES),
 947         VMX_SEGMENT_FIELD(FS),
 948         VMX_SEGMENT_FIELD(GS),
 949         VMX_SEGMENT_FIELD(SS),
 950         VMX_SEGMENT_FIELD(TR),
 951         VMX_SEGMENT_FIELD(LDTR),
 952 };
 953
 954 static u64 host_efer;
 955
 956 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 957
 958 /*
 959  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 960  * away by decrementing the array size.
 961  */
 962 static const u32 vmx_msr_index[] = {
 963 #ifdef CONFIG_X86_64
 964         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 965 #endif
 966         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 967 };
 968
 969 static inline bool is_exception_n(u32 intr_info, u8 vector)
 970 {
 971         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 972                              INTR_INFO_VALID_MASK)) ==
 973                 (INTR_TYPE_HARD_EXCEPTION | vector | INTR_INFO_VALID_MASK);
 974 }
 975
 976 static inline bool is_debug(u32 intr_info)
 977 {
 978         return is_exception_n(intr_info, DB_VECTOR);
 979 }
 980
 981 static inline bool is_breakpoint(u32 intr_info)
 982 {
 983         return is_exception_n(intr_info, BP_VECTOR);
 984 }
 985
 986 static inline bool is_page_fault(u32 intr_info)
 987 {
 988         return is_exception_n(intr_info, PF_VECTOR);
 989 }
 990
 991 static inline bool is_no_device(u32 intr_info)
 992 {
 993         return is_exception_n(intr_info, NM_VECTOR);
 994 }
 995
 996 static inline bool is_invalid_opcode(u32 intr_info)
 997 {
 998         return is_exception_n(intr_info, UD_VECTOR);
 999 }
1000
1001 static inline bool is_external_interrupt(u32 intr_info)
1002 {
1003         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1004                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
1005 }
1006
1007 static inline bool is_machine_check(u32 intr_info)
1008 {
1009         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
1010                              INTR_INFO_VALID_MASK)) ==
1011                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
1012 }
1013
1014 static inline bool cpu_has_vmx_msr_bitmap(void)
1015 {
1016         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1017 }
1018
1019 static inline bool cpu_has_vmx_tpr_shadow(void)
1020 {
1021         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1022 }
1023
1024 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1025 {
1026         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1027 }
1028
1029 static inline bool cpu_has_secondary_exec_ctrls(void)
1030 {
1031         return vmcs_config.cpu_based_exec_ctrl &
1032                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1033 }
1034
1035 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1036 {
1037         return vmcs_config.cpu_based_2nd_exec_ctrl &
1038                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1039 }
1040
1041 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1042 {
1043         return vmcs_config.cpu_based_2nd_exec_ctrl &
1044                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1045 }
1046
1047 static inline bool cpu_has_vmx_apic_register_virt(void)
1048 {
1049         return vmcs_config.cpu_based_2nd_exec_ctrl &
1050                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1051 }
1052
1053 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1054 {
1055         return vmcs_config.cpu_based_2nd_exec_ctrl &
1056                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1057 }
1058
1059 static inline bool cpu_has_vmx_posted_intr(void)
1060 {
1061         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1062                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1063 }
1064
1065 static inline bool cpu_has_vmx_apicv(void)
1066 {
1067         return cpu_has_vmx_apic_register_virt() &&
1068                 cpu_has_vmx_virtual_intr_delivery() &&
1069                 cpu_has_vmx_posted_intr();
1070 }
1071
1072 static inline bool cpu_has_vmx_flexpriority(void)
1073 {
1074         return cpu_has_vmx_tpr_shadow() &&
1075                 cpu_has_vmx_virtualize_apic_accesses();
1076 }
1077
1078 static inline bool cpu_has_vmx_ept_execute_only(void)
1079 {
1080         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1081 }
1082
1083 static inline bool cpu_has_vmx_ept_2m_page(void)
1084 {
1085         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1086 }
1087
1088 static inline bool cpu_has_vmx_ept_1g_page(void)
1089 {
1090         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1091 }
1092
1093 static inline bool cpu_has_vmx_ept_4levels(void)
1094 {
1095         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1096 }
1097
1098 static inline bool cpu_has_vmx_ept_ad_bits(void)
1099 {
1100         return vmx_capability.ept & VMX_EPT_AD_BIT;
1101 }
1102
1103 static inline bool cpu_has_vmx_invept_context(void)
1104 {
1105         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1106 }
1107
1108 static inline bool cpu_has_vmx_invept_global(void)
1109 {
1110         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1111 }
1112
1113 static inline bool cpu_has_vmx_invvpid_single(void)
1114 {
1115         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1116 }
1117
1118 static inline bool cpu_has_vmx_invvpid_global(void)
1119 {
1120         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1121 }
1122
1123 static inline bool cpu_has_vmx_ept(void)
1124 {
1125         return vmcs_config.cpu_based_2nd_exec_ctrl &
1126                 SECONDARY_EXEC_ENABLE_EPT;
1127 }
1128
1129 static inline bool cpu_has_vmx_unrestricted_guest(void)
1130 {
1131         return vmcs_config.cpu_based_2nd_exec_ctrl &
1132                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1133 }
1134
1135 static inline bool cpu_has_vmx_ple(void)
1136 {
1137         return vmcs_config.cpu_based_2nd_exec_ctrl &
1138                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1139 }
1140
1141 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1142 {
1143         return flexpriority_enabled && lapic_in_kernel(vcpu);
1144 }
1145
1146 static inline bool cpu_has_vmx_vpid(void)
1147 {
1148         return vmcs_config.cpu_based_2nd_exec_ctrl &
1149                 SECONDARY_EXEC_ENABLE_VPID;
1150 }
1151
1152 static inline bool cpu_has_vmx_rdtscp(void)
1153 {
1154         return vmcs_config.cpu_based_2nd_exec_ctrl &
1155                 SECONDARY_EXEC_RDTSCP;
1156 }
1157
1158 static inline bool cpu_has_vmx_invpcid(void)
1159 {
1160         return vmcs_config.cpu_based_2nd_exec_ctrl &
1161                 SECONDARY_EXEC_ENABLE_INVPCID;
1162 }
1163
1164 static inline bool cpu_has_virtual_nmis(void)
1165 {
1166         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1167 }
1168
1169 static inline bool cpu_has_vmx_wbinvd_exit(void)
1170 {
1171         return vmcs_config.cpu_based_2nd_exec_ctrl &
1172                 SECONDARY_EXEC_WBINVD_EXITING;
1173 }
1174
1175 static inline bool cpu_has_vmx_shadow_vmcs(void)
1176 {
1177         u64 vmx_msr;
1178         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1179         /* check if the cpu supports writing r/o exit information fields */
1180         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1181                 return false;
1182
1183         return vmcs_config.cpu_based_2nd_exec_ctrl &
1184                 SECONDARY_EXEC_SHADOW_VMCS;
1185 }
1186
1187 static inline bool cpu_has_vmx_pml(void)
1188 {
1189         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1190 }
1191
1192 static inline bool cpu_has_vmx_tsc_scaling(void)
1193 {
1194         return vmcs_config.cpu_based_2nd_exec_ctrl &
1195                 SECONDARY_EXEC_TSC_SCALING;
1196 }
1197
1198 static inline bool report_flexpriority(void)
1199 {
1200         return flexpriority_enabled;
1201 }
1202
1203 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1204 {
1205         return vmcs12->cpu_based_vm_exec_control & bit;
1206 }
1207
1208 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1209 {
1210         return (vmcs12->cpu_based_vm_exec_control &
1211                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1212                 (vmcs12->secondary_vm_exec_control & bit);
1213 }
1214
1215 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1216 {
1217         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1218 }
1219
1220 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1221 {
1222         return vmcs12->pin_based_vm_exec_control &
1223                 PIN_BASED_VMX_PREEMPTION_TIMER;
1224 }
1225
1226 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1227 {
1228         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1229 }
1230
1231 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1232 {
1233         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1234                 vmx_xsaves_supported();
1235 }
1236
1237 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1238 {
1239         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1240 }
1241
1242 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1243 {
1244         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1245 }
1246
1247 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1248 {
1249         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1250 }
1251
1252 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1253 {
1254         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1255 }
1256
1257 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1258 {
1259         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1260 }
1261
1262 static inline bool is_exception(u32 intr_info)
1263 {
1264         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1265                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1266 }
1267
1268 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1269                               u32 exit_intr_info,
1270                               unsigned long exit_qualification);
1271 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1272                         struct vmcs12 *vmcs12,
1273                         u32 reason, unsigned long qualification);
1274
1275 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1276 {
1277         int i;
1278
1279         for (i = 0; i < vmx->nmsrs; ++i)
1280                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1281                         return i;
1282         return -1;
1283 }
1284
1285 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1286 {
1287     struct {
1288         u64 vpid : 16;
1289         u64 rsvd : 48;
1290         u64 gva;
1291     } operand = { vpid, 0, gva };
1292
1293     asm volatile (__ex(ASM_VMX_INVVPID)
1294                   /* CF==1 or ZF==1 --> rc = -1 */
1295                   "; ja 1f ; ud2 ; 1:"
1296                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1297 }
1298
1299 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1300 {
1301         struct {
1302                 u64 eptp, gpa;
1303         } operand = {eptp, gpa};
1304
1305         asm volatile (__ex(ASM_VMX_INVEPT)
1306                         /* CF==1 or ZF==1 --> rc = -1 */
1307                         "; ja 1f ; ud2 ; 1:\n"
1308                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1309 }
1310
1311 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1312 {
1313         int i;
1314
1315         i = __find_msr_index(vmx, msr);
1316         if (i >= 0)
1317                 return &vmx->guest_msrs[i];
1318         return NULL;
1319 }
1320
1321 static void vmcs_clear(struct vmcs *vmcs)
1322 {
1323         u64 phys_addr = __pa(vmcs);
1324         u8 error;
1325
1326         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1327                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1328                       : "cc", "memory");
1329         if (error)
1330                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1331                        vmcs, phys_addr);
1332 }
1333
1334 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1335 {
1336         vmcs_clear(loaded_vmcs->vmcs);
1337         loaded_vmcs->cpu = -1;
1338         loaded_vmcs->launched = 0;
1339 }
1340
1341 static void vmcs_load(struct vmcs *vmcs)
1342 {
1343         u64 phys_addr = __pa(vmcs);
1344         u8 error;
1345
1346         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1347                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1348                         : "cc", "memory");
1349         if (error)
1350                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1351                        vmcs, phys_addr);
1352 }
1353
1354 #ifdef CONFIG_KEXEC_CORE
1355 /*
1356  * This bitmap is used to indicate whether the vmclear
1357  * operation is enabled on all cpus. All disabled by
1358  * default.
1359  */
1360 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1361
1362 static inline void crash_enable_local_vmclear(int cpu)
1363 {
1364         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1365 }
1366
1367 static inline void crash_disable_local_vmclear(int cpu)
1368 {
1369         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1370 }
1371
1372 static inline int crash_local_vmclear_enabled(int cpu)
1373 {
1374         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1375 }
1376
1377 static void crash_vmclear_local_loaded_vmcss(void)
1378 {
1379         int cpu = raw_smp_processor_id();
1380         struct loaded_vmcs *v;
1381
1382         if (!crash_local_vmclear_enabled(cpu))
1383                 return;
1384
1385         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1386                             loaded_vmcss_on_cpu_link)
1387                 vmcs_clear(v->vmcs);
1388 }
1389 #else
1390 static inline void crash_enable_local_vmclear(int cpu) { }
1391 static inline void crash_disable_local_vmclear(int cpu) { }
1392 #endif /* CONFIG_KEXEC_CORE */
1393
1394 static void __loaded_vmcs_clear(void *arg)
1395 {
1396         struct loaded_vmcs *loaded_vmcs = arg;
1397         int cpu = raw_smp_processor_id();
1398
1399         if (loaded_vmcs->cpu != cpu)
1400                 return; /* vcpu migration can race with cpu offline */
1401         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1402                 per_cpu(current_vmcs, cpu) = NULL;
1403         crash_disable_local_vmclear(cpu);
1404         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1405
1406         /*
1407          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1408          * is before setting loaded_vmcs->vcpu to -1 which is done in
1409          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1410          * then adds the vmcs into percpu list before it is deleted.
1411          */
1412         smp_wmb();
1413
1414         loaded_vmcs_init(loaded_vmcs);
1415         crash_enable_local_vmclear(cpu);
1416 }
1417
1418 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1419 {
1420         int cpu = loaded_vmcs->cpu;
1421
1422         if (cpu != -1)
1423                 smp_call_function_single(cpu,
1424                          __loaded_vmcs_clear, loaded_vmcs, 1);
1425 }
1426
1427 static inline void vpid_sync_vcpu_single(int vpid)
1428 {
1429         if (vpid == 0)
1430                 return;
1431
1432         if (cpu_has_vmx_invvpid_single())
1433                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1434 }
1435
1436 static inline void vpid_sync_vcpu_global(void)
1437 {
1438         if (cpu_has_vmx_invvpid_global())
1439                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1440 }
1441
1442 static inline void vpid_sync_context(int vpid)
1443 {
1444         if (cpu_has_vmx_invvpid_single())
1445                 vpid_sync_vcpu_single(vpid);
1446         else
1447                 vpid_sync_vcpu_global();
1448 }
1449
1450 static inline void ept_sync_global(void)
1451 {
1452         if (cpu_has_vmx_invept_global())
1453                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1454 }
1455
1456 static inline void ept_sync_context(u64 eptp)
1457 {
1458         if (enable_ept) {
1459                 if (cpu_has_vmx_invept_context())
1460                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1461                 else
1462                         ept_sync_global();
1463         }
1464 }
1465
1466 static __always_inline void vmcs_check16(unsigned long field)
1467 {
1468         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1469                          "16-bit accessor invalid for 64-bit field");
1470         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1471                          "16-bit accessor invalid for 64-bit high field");
1472         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1473                          "16-bit accessor invalid for 32-bit high field");
1474         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1475                          "16-bit accessor invalid for natural width field");
1476 }
1477
1478 static __always_inline void vmcs_check32(unsigned long field)
1479 {
1480         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1481                          "32-bit accessor invalid for 16-bit field");
1482         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1483                          "32-bit accessor invalid for natural width field");
1484 }
1485
1486 static __always_inline void vmcs_check64(unsigned long field)
1487 {
1488         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1489                          "64-bit accessor invalid for 16-bit field");
1490         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1491                          "64-bit accessor invalid for 64-bit high field");
1492         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1493                          "64-bit accessor invalid for 32-bit field");
1494         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x6000,
1495                          "64-bit accessor invalid for natural width field");
1496 }
1497
1498 static __always_inline void vmcs_checkl(unsigned long field)
1499 {
1500         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0,
1501                          "Natural width accessor invalid for 16-bit field");
1502         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2000,
1503                          "Natural width accessor invalid for 64-bit field");
1504         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6001) == 0x2001,
1505                          "Natural width accessor invalid for 64-bit high field");
1506         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x4000,
1507                          "Natural width accessor invalid for 32-bit field");
1508 }
1509
1510 static __always_inline unsigned long __vmcs_readl(unsigned long field)
1511 {
1512         unsigned long value;
1513
1514         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1515                       : "=a"(value) : "d"(field) : "cc");
1516         return value;
1517 }
1518
1519 static __always_inline u16 vmcs_read16(unsigned long field)
1520 {
1521         vmcs_check16(field);
1522         return __vmcs_readl(field);
1523 }
1524
1525 static __always_inline u32 vmcs_read32(unsigned long field)
1526 {
1527         vmcs_check32(field);
1528         return __vmcs_readl(field);
1529 }
1530
1531 static __always_inline u64 vmcs_read64(unsigned long field)
1532 {
1533         vmcs_check64(field);
1534 #ifdef CONFIG_X86_64
1535         return __vmcs_readl(field);
1536 #else
1537         return __vmcs_readl(field) | ((u64)__vmcs_readl(field+1) << 32);
1538 #endif
1539 }
1540
1541 static __always_inline unsigned long vmcs_readl(unsigned long field)
1542 {
1543         vmcs_checkl(field);
1544         return __vmcs_readl(field);
1545 }
1546
1547 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1548 {
1549         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1550                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1551         dump_stack();
1552 }
1553
1554 static __always_inline void __vmcs_writel(unsigned long field, unsigned long value)
1555 {
1556         u8 error;
1557
1558         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1559                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1560         if (unlikely(error))
1561                 vmwrite_error(field, value);
1562 }
1563
1564 static __always_inline void vmcs_write16(unsigned long field, u16 value)
1565 {
1566         vmcs_check16(field);
1567         __vmcs_writel(field, value);
1568 }
1569
1570 static __always_inline void vmcs_write32(unsigned long field, u32 value)
1571 {
1572         vmcs_check32(field);
1573         __vmcs_writel(field, value);
1574 }
1575
1576 static __always_inline void vmcs_write64(unsigned long field, u64 value)
1577 {
1578         vmcs_check64(field);
1579         __vmcs_writel(field, value);
1580 #ifndef CONFIG_X86_64
1581         asm volatile ("");
1582         __vmcs_writel(field+1, value >> 32);
1583 #endif
1584 }
1585
1586 static __always_inline void vmcs_writel(unsigned long field, unsigned long value)
1587 {
1588         vmcs_checkl(field);
1589         __vmcs_writel(field, value);
1590 }
1591
1592 static __always_inline void vmcs_clear_bits(unsigned long field, u32 mask)
1593 {
1594         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1595                          "vmcs_clear_bits does not support 64-bit fields");
1596         __vmcs_writel(field, __vmcs_readl(field) & ~mask);
1597 }
1598
1599 static __always_inline void vmcs_set_bits(unsigned long field, u32 mask)
1600 {
1601         BUILD_BUG_ON_MSG(__builtin_constant_p(field) && ((field) & 0x6000) == 0x2000,
1602                          "vmcs_set_bits does not support 64-bit fields");
1603         __vmcs_writel(field, __vmcs_readl(field) | mask);
1604 }
1605
1606 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1607 {
1608         vmcs_write32(VM_ENTRY_CONTROLS, val);
1609         vmx->vm_entry_controls_shadow = val;
1610 }
1611
1612 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1613 {
1614         if (vmx->vm_entry_controls_shadow != val)
1615                 vm_entry_controls_init(vmx, val);
1616 }
1617
1618 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1619 {
1620         return vmx->vm_entry_controls_shadow;
1621 }
1622
1623
1624 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1625 {
1626         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1627 }
1628
1629 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1630 {
1631         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1632 }
1633
1634 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1635 {
1636         vmcs_write32(VM_EXIT_CONTROLS, val);
1637         vmx->vm_exit_controls_shadow = val;
1638 }
1639
1640 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1641 {
1642         if (vmx->vm_exit_controls_shadow != val)
1643                 vm_exit_controls_init(vmx, val);
1644 }
1645
1646 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1647 {
1648         return vmx->vm_exit_controls_shadow;
1649 }
1650
1651
1652 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1653 {
1654         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1655 }
1656
1657 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1658 {
1659         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1660 }
1661
1662 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1663 {
1664         vmx->segment_cache.bitmask = 0;
1665 }
1666
1667 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1668                                        unsigned field)
1669 {
1670         bool ret;
1671         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1672
1673         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1674                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1675                 vmx->segment_cache.bitmask = 0;
1676         }
1677         ret = vmx->segment_cache.bitmask & mask;
1678         vmx->segment_cache.bitmask |= mask;
1679         return ret;
1680 }
1681
1682 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1683 {
1684         u16 *p = &vmx->segment_cache.seg[seg].selector;
1685
1686         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1687                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1688         return *p;
1689 }
1690
1691 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1692 {
1693         ulong *p = &vmx->segment_cache.seg[seg].base;
1694
1695         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1696                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1697         return *p;
1698 }
1699
1700 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1701 {
1702         u32 *p = &vmx->segment_cache.seg[seg].limit;
1703
1704         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1705                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1706         return *p;
1707 }
1708
1709 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1710 {
1711         u32 *p = &vmx->segment_cache.seg[seg].ar;
1712
1713         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1714                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1715         return *p;
1716 }
1717
1718 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1719 {
1720         u32 eb;
1721
1722         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1723              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1724         if ((vcpu->guest_debug &
1725              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1726             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1727                 eb |= 1u << BP_VECTOR;
1728         if (to_vmx(vcpu)->rmode.vm86_active)
1729                 eb = ~0;
1730         if (enable_ept)
1731                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1732         if (vcpu->fpu_active)
1733                 eb &= ~(1u << NM_VECTOR);
1734
1735         /* When we are running a nested L2 guest and L1 specified for it a
1736          * certain exception bitmap, we must trap the same exceptions and pass
1737          * them to L1. When running L2, we will only handle the exceptions
1738          * specified above if L1 did not want them.
1739          */
1740         if (is_guest_mode(vcpu))
1741                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1742
1743         vmcs_write32(EXCEPTION_BITMAP, eb);
1744 }
1745
1746 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1747                 unsigned long entry, unsigned long exit)
1748 {
1749         vm_entry_controls_clearbit(vmx, entry);
1750         vm_exit_controls_clearbit(vmx, exit);
1751 }
1752
1753 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1754 {
1755         unsigned i;
1756         struct msr_autoload *m = &vmx->msr_autoload;
1757
1758         switch (msr) {
1759         case MSR_EFER:
1760                 if (cpu_has_load_ia32_efer) {
1761                         clear_atomic_switch_msr_special(vmx,
1762                                         VM_ENTRY_LOAD_IA32_EFER,
1763                                         VM_EXIT_LOAD_IA32_EFER);
1764                         return;
1765                 }
1766                 break;
1767         case MSR_CORE_PERF_GLOBAL_CTRL:
1768                 if (cpu_has_load_perf_global_ctrl) {
1769                         clear_atomic_switch_msr_special(vmx,
1770                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1771                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1772                         return;
1773                 }
1774                 break;
1775         }
1776
1777         for (i = 0; i < m->nr; ++i)
1778                 if (m->guest[i].index == msr)
1779                         break;
1780
1781         if (i == m->nr)
1782                 return;
1783         --m->nr;
1784         m->guest[i] = m->guest[m->nr];
1785         m->host[i] = m->host[m->nr];
1786         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1787         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1788 }
1789
1790 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1791                 unsigned long entry, unsigned long exit,
1792                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1793                 u64 guest_val, u64 host_val)
1794 {
1795         vmcs_write64(guest_val_vmcs, guest_val);
1796         vmcs_write64(host_val_vmcs, host_val);
1797         vm_entry_controls_setbit(vmx, entry);
1798         vm_exit_controls_setbit(vmx, exit);
1799 }
1800
1801 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1802                                   u64 guest_val, u64 host_val)
1803 {
1804         unsigned i;
1805         struct msr_autoload *m = &vmx->msr_autoload;
1806
1807         switch (msr) {
1808         case MSR_EFER:
1809                 if (cpu_has_load_ia32_efer) {
1810                         add_atomic_switch_msr_special(vmx,
1811                                         VM_ENTRY_LOAD_IA32_EFER,
1812                                         VM_EXIT_LOAD_IA32_EFER,
1813                                         GUEST_IA32_EFER,
1814                                         HOST_IA32_EFER,
1815                                         guest_val, host_val);
1816                         return;
1817                 }
1818                 break;
1819         case MSR_CORE_PERF_GLOBAL_CTRL:
1820                 if (cpu_has_load_perf_global_ctrl) {
1821                         add_atomic_switch_msr_special(vmx,
1822                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1823                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1824                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1825                                         HOST_IA32_PERF_GLOBAL_CTRL,
1826                                         guest_val, host_val);
1827                         return;
1828                 }
1829                 break;
1830         case MSR_IA32_PEBS_ENABLE:
1831                 /* PEBS needs a quiescent period after being disabled (to write
1832                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1833                  * provide that period, so a CPU could write host's record into
1834                  * guest's memory.
1835                  */
1836                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1837         }
1838
1839         for (i = 0; i < m->nr; ++i)
1840                 if (m->guest[i].index == msr)
1841                         break;
1842
1843         if (i == NR_AUTOLOAD_MSRS) {
1844                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1845                                 "Can't add msr %x\n", msr);
1846                 return;
1847         } else if (i == m->nr) {
1848                 ++m->nr;
1849                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1850                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1851         }
1852
1853         m->guest[i].index = msr;
1854         m->guest[i].value = guest_val;
1855         m->host[i].index = msr;
1856         m->host[i].value = host_val;
1857 }
1858
1859 static void reload_tss(void)
1860 {
1861         /*
1862          * VT restores TR but not its size.  Useless.
1863          */
1864         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1865         struct desc_struct *descs;
1866
1867         descs = (void *)gdt->address;
1868         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1869         load_TR_desc();
1870 }
1871
1872 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1873 {
1874         u64 guest_efer = vmx->vcpu.arch.efer;
1875         u64 ignore_bits = 0;
1876
1877         if (!enable_ept) {
1878                 /*
1879                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
1880                  * host CPUID is more efficient than testing guest CPUID
1881                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
1882                  */
1883                 if (boot_cpu_has(X86_FEATURE_SMEP))
1884                         guest_efer |= EFER_NX;
1885                 else if (!(guest_efer & EFER_NX))
1886                         ignore_bits |= EFER_NX;
1887         }
1888
1889         /*
1890          * LMA and LME handled by hardware; SCE meaningless outside long mode.
1891          */
1892         ignore_bits |= EFER_SCE;
1893 #ifdef CONFIG_X86_64
1894         ignore_bits |= EFER_LMA | EFER_LME;
1895         /* SCE is meaningful only in long mode on Intel */
1896         if (guest_efer & EFER_LMA)
1897                 ignore_bits &= ~(u64)EFER_SCE;
1898 #endif
1899
1900         clear_atomic_switch_msr(vmx, MSR_EFER);
1901
1902         /*
1903          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1904          * On CPUs that support "load IA32_EFER", always switch EFER
1905          * atomically, since it's faster than switching it manually.
1906          */
1907         if (cpu_has_load_ia32_efer ||
1908             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1909                 if (!(guest_efer & EFER_LMA))
1910                         guest_efer &= ~EFER_LME;
1911                 if (guest_efer != host_efer)
1912                         add_atomic_switch_msr(vmx, MSR_EFER,
1913                                               guest_efer, host_efer);
1914                 return false;
1915         } else {
1916                 guest_efer &= ~ignore_bits;
1917                 guest_efer |= host_efer & ignore_bits;
1918
1919                 vmx->guest_msrs[efer_offset].data = guest_efer;
1920                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1921
1922                 return true;
1923         }
1924 }
1925
1926 static unsigned long segment_base(u16 selector)
1927 {
1928         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1929         struct desc_struct *d;
1930         unsigned long table_base;
1931         unsigned long v;
1932
1933         if (!(selector & ~3))
1934                 return 0;
1935
1936         table_base = gdt->address;
1937
1938         if (selector & 4) {           /* from ldt */
1939                 u16 ldt_selector = kvm_read_ldt();
1940
1941                 if (!(ldt_selector & ~3))
1942                         return 0;
1943
1944                 table_base = segment_base(ldt_selector);
1945         }
1946         d = (struct desc_struct *)(table_base + (selector & ~7));
1947         v = get_desc_base(d);
1948 #ifdef CONFIG_X86_64
1949        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1950                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1951 #endif
1952         return v;
1953 }
1954
1955 static inline unsigned long kvm_read_tr_base(void)
1956 {
1957         u16 tr;
1958         asm("str %0" : "=g"(tr));
1959         return segment_base(tr);
1960 }
1961
1962 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1963 {
1964         struct vcpu_vmx *vmx = to_vmx(vcpu);
1965         int i;
1966
1967         if (vmx->host_state.loaded)
1968                 return;
1969
1970         vmx->host_state.loaded = 1;
1971         /*
1972          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1973          * allow segment selectors with cpl > 0 or ti == 1.
1974          */
1975         vmx->host_state.ldt_sel = kvm_read_ldt();
1976         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1977         savesegment(fs, vmx->host_state.fs_sel);
1978         if (!(vmx->host_state.fs_sel & 7)) {
1979                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1980                 vmx->host_state.fs_reload_needed = 0;
1981         } else {
1982                 vmcs_write16(HOST_FS_SELECTOR, 0);
1983                 vmx->host_state.fs_reload_needed = 1;
1984         }
1985         savesegment(gs, vmx->host_state.gs_sel);
1986         if (!(vmx->host_state.gs_sel & 7))
1987                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1988         else {
1989                 vmcs_write16(HOST_GS_SELECTOR, 0);
1990                 vmx->host_state.gs_ldt_reload_needed = 1;
1991         }
1992
1993 #ifdef CONFIG_X86_64
1994         savesegment(ds, vmx->host_state.ds_sel);
1995         savesegment(es, vmx->host_state.es_sel);
1996 #endif
1997
1998 #ifdef CONFIG_X86_64
1999         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
2000         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
2001 #else
2002         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
2003         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
2004 #endif
2005
2006 #ifdef CONFIG_X86_64
2007         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2008         if (is_long_mode(&vmx->vcpu))
2009                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2010 #endif
2011         if (boot_cpu_has(X86_FEATURE_MPX))
2012                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2013         for (i = 0; i < vmx->save_nmsrs; ++i)
2014                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
2015                                    vmx->guest_msrs[i].data,
2016                                    vmx->guest_msrs[i].mask);
2017 }
2018
2019 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
2020 {
2021         if (!vmx->host_state.loaded)
2022                 return;
2023
2024         ++vmx->vcpu.stat.host_state_reload;
2025         vmx->host_state.loaded = 0;
2026 #ifdef CONFIG_X86_64
2027         if (is_long_mode(&vmx->vcpu))
2028                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
2029 #endif
2030         if (vmx->host_state.gs_ldt_reload_needed) {
2031                 kvm_load_ldt(vmx->host_state.ldt_sel);
2032 #ifdef CONFIG_X86_64
2033                 load_gs_index(vmx->host_state.gs_sel);
2034 #else
2035                 loadsegment(gs, vmx->host_state.gs_sel);
2036 #endif
2037         }
2038         if (vmx->host_state.fs_reload_needed)
2039                 loadsegment(fs, vmx->host_state.fs_sel);
2040 #ifdef CONFIG_X86_64
2041         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
2042                 loadsegment(ds, vmx->host_state.ds_sel);
2043                 loadsegment(es, vmx->host_state.es_sel);
2044         }
2045 #endif
2046         reload_tss();
2047 #ifdef CONFIG_X86_64
2048         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
2049 #endif
2050         if (vmx->host_state.msr_host_bndcfgs)
2051                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
2052         /*
2053          * If the FPU is not active (through the host task or
2054          * the guest vcpu), then restore the cr0.TS bit.
2055          */
2056         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
2057                 stts();
2058         load_gdt(this_cpu_ptr(&host_gdt));
2059 }
2060
2061 static void vmx_load_host_state(struct vcpu_vmx *vmx)
2062 {
2063         preempt_disable();
2064         __vmx_load_host_state(vmx);
2065         preempt_enable();
2066 }
2067
2068 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
2069 {
2070         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2071         struct pi_desc old, new;
2072         unsigned int dest;
2073
2074         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2075                 !irq_remapping_cap(IRQ_POSTING_CAP))
2076                 return;
2077
2078         do {
2079                 old.control = new.control = pi_desc->control;
2080
2081                 /*
2082                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2083                  * are two possible cases:
2084                  * 1. After running 'pre_block', context switch
2085                  *    happened. For this case, 'sn' was set in
2086                  *    vmx_vcpu_put(), so we need to clear it here.
2087                  * 2. After running 'pre_block', we were blocked,
2088                  *    and woken up by some other guy. For this case,
2089                  *    we don't need to do anything, 'pi_post_block'
2090                  *    will do everything for us. However, we cannot
2091                  *    check whether it is case #1 or case #2 here
2092                  *    (maybe, not needed), so we also clear sn here,
2093                  *    I think it is not a big deal.
2094                  */
2095                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2096                         if (vcpu->cpu != cpu) {
2097                                 dest = cpu_physical_id(cpu);
2098
2099                                 if (x2apic_enabled())
2100                                         new.ndst = dest;
2101                                 else
2102                                         new.ndst = (dest << 8) & 0xFF00;
2103                         }
2104
2105                         /* set 'NV' to 'notification vector' */
2106                         new.nv = POSTED_INTR_VECTOR;
2107                 }
2108
2109                 /* Allow posting non-urgent interrupts */
2110                 new.sn = 0;
2111         } while (cmpxchg(&pi_desc->control, old.control,
2112                         new.control) != old.control);
2113 }
2114
2115 /*
2116  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2117  * vcpu mutex is already taken.
2118  */
2119 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2120 {
2121         struct vcpu_vmx *vmx = to_vmx(vcpu);
2122         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2123
2124         if (!vmm_exclusive)
2125                 kvm_cpu_vmxon(phys_addr);
2126         else if (vmx->loaded_vmcs->cpu != cpu)
2127                 loaded_vmcs_clear(vmx->loaded_vmcs);
2128
2129         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2130                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2131                 vmcs_load(vmx->loaded_vmcs->vmcs);
2132         }
2133
2134         if (vmx->loaded_vmcs->cpu != cpu) {
2135                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2136                 unsigned long sysenter_esp;
2137
2138                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2139                 local_irq_disable();
2140                 crash_disable_local_vmclear(cpu);
2141
2142                 /*
2143                  * Read loaded_vmcs->cpu should be before fetching
2144                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2145                  * See the comments in __loaded_vmcs_clear().
2146                  */
2147                 smp_rmb();
2148
2149                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2150                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2151                 crash_enable_local_vmclear(cpu);
2152                 local_irq_enable();
2153
2154                 /*
2155                  * Linux uses per-cpu TSS and GDT, so set these when switching
2156                  * processors.
2157                  */
2158                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2159                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2160
2161                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2162                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2163
2164                 vmx->loaded_vmcs->cpu = cpu;
2165         }
2166
2167         /* Setup TSC multiplier */
2168         if (kvm_has_tsc_control &&
2169             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) {
2170                 vmx->current_tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2171                 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2172         }
2173
2174         vmx_vcpu_pi_load(vcpu, cpu);
2175         vmx->host_pkru = read_pkru();
2176 }
2177
2178 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2179 {
2180         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2181
2182         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2183                 !irq_remapping_cap(IRQ_POSTING_CAP))
2184                 return;
2185
2186         /* Set SN when the vCPU is preempted */
2187         if (vcpu->preempted)
2188                 pi_set_sn(pi_desc);
2189 }
2190
2191 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2192 {
2193         vmx_vcpu_pi_put(vcpu);
2194
2195         __vmx_load_host_state(to_vmx(vcpu));
2196         if (!vmm_exclusive) {
2197                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2198                 vcpu->cpu = -1;
2199                 kvm_cpu_vmxoff();
2200         }
2201 }
2202
2203 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2204 {
2205         ulong cr0;
2206
2207         if (vcpu->fpu_active)
2208                 return;
2209         vcpu->fpu_active = 1;
2210         cr0 = vmcs_readl(GUEST_CR0);
2211         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2212         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2213         vmcs_writel(GUEST_CR0, cr0);
2214         update_exception_bitmap(vcpu);
2215         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2216         if (is_guest_mode(vcpu))
2217                 vcpu->arch.cr0_guest_owned_bits &=
2218                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2219         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2220 }
2221
2222 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2223
2224 /*
2225  * Return the cr0 value that a nested guest would read. This is a combination
2226  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2227  * its hypervisor (cr0_read_shadow).
2228  */
2229 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2230 {
2231         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2232                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2233 }
2234 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2235 {
2236         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2237                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2238 }
2239
2240 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2241 {
2242         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2243          * set this *before* calling this function.
2244          */
2245         vmx_decache_cr0_guest_bits(vcpu);
2246         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2247         update_exception_bitmap(vcpu);
2248         vcpu->arch.cr0_guest_owned_bits = 0;
2249         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2250         if (is_guest_mode(vcpu)) {
2251                 /*
2252                  * L1's specified read shadow might not contain the TS bit,
2253                  * so now that we turned on shadowing of this bit, we need to
2254                  * set this bit of the shadow. Like in nested_vmx_run we need
2255                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2256                  * up-to-date here because we just decached cr0.TS (and we'll
2257                  * only update vmcs12->guest_cr0 on nested exit).
2258                  */
2259                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2260                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2261                         (vcpu->arch.cr0 & X86_CR0_TS);
2262                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2263         } else
2264                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2265 }
2266
2267 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2268 {
2269         unsigned long rflags, save_rflags;
2270
2271         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2272                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2273                 rflags = vmcs_readl(GUEST_RFLAGS);
2274                 if (to_vmx(vcpu)->rmode.vm86_active) {
2275                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2276                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2277                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2278                 }
2279                 to_vmx(vcpu)->rflags = rflags;
2280         }
2281         return to_vmx(vcpu)->rflags;
2282 }
2283
2284 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2285 {
2286         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2287         to_vmx(vcpu)->rflags = rflags;
2288         if (to_vmx(vcpu)->rmode.vm86_active) {
2289                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2290                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2291         }
2292         vmcs_writel(GUEST_RFLAGS, rflags);
2293 }
2294
2295 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2296 {
2297         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2298         int ret = 0;
2299
2300         if (interruptibility & GUEST_INTR_STATE_STI)
2301                 ret |= KVM_X86_SHADOW_INT_STI;
2302         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2303                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2304
2305         return ret;
2306 }
2307
2308 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2309 {
2310         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2311         u32 interruptibility = interruptibility_old;
2312
2313         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2314
2315         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2316                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2317         else if (mask & KVM_X86_SHADOW_INT_STI)
2318                 interruptibility |= GUEST_INTR_STATE_STI;
2319
2320         if ((interruptibility != interruptibility_old))
2321                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2322 }
2323
2324 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2325 {
2326         unsigned long rip;
2327
2328         rip = kvm_rip_read(vcpu);
2329         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2330         kvm_rip_write(vcpu, rip);
2331
2332         /* skipping an emulated instruction also counts */
2333         vmx_set_interrupt_shadow(vcpu, 0);
2334 }
2335
2336 /*
2337  * KVM wants to inject page-faults which it got to the guest. This function
2338  * checks whether in a nested guest, we need to inject them to L1 or L2.
2339  */
2340 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2341 {
2342         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2343
2344         if (!(vmcs12->exception_bitmap & (1u << nr)))
2345                 return 0;
2346
2347         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2348                           vmcs_read32(VM_EXIT_INTR_INFO),
2349                           vmcs_readl(EXIT_QUALIFICATION));
2350         return 1;
2351 }
2352
2353 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2354                                 bool has_error_code, u32 error_code,
2355                                 bool reinject)
2356 {
2357         struct vcpu_vmx *vmx = to_vmx(vcpu);
2358         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2359
2360         if (!reinject && is_guest_mode(vcpu) &&
2361             nested_vmx_check_exception(vcpu, nr))
2362                 return;
2363
2364         if (has_error_code) {
2365                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2366                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2367         }
2368
2369         if (vmx->rmode.vm86_active) {
2370                 int inc_eip = 0;
2371                 if (kvm_exception_is_soft(nr))
2372                         inc_eip = vcpu->arch.event_exit_inst_len;
2373                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2374                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2375                 return;
2376         }
2377
2378         if (kvm_exception_is_soft(nr)) {
2379                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2380                              vmx->vcpu.arch.event_exit_inst_len);
2381                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2382         } else
2383                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2384
2385         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2386 }
2387
2388 static bool vmx_rdtscp_supported(void)
2389 {
2390         return cpu_has_vmx_rdtscp();
2391 }
2392
2393 static bool vmx_invpcid_supported(void)
2394 {
2395         return cpu_has_vmx_invpcid() && enable_ept;
2396 }
2397
2398 /*
2399  * Swap MSR entry in host/guest MSR entry array.
2400  */
2401 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2402 {
2403         struct shared_msr_entry tmp;
2404
2405         tmp = vmx->guest_msrs[to];
2406         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2407         vmx->guest_msrs[from] = tmp;
2408 }
2409
2410 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2411 {
2412         unsigned long *msr_bitmap;
2413
2414         if (is_guest_mode(vcpu))
2415                 msr_bitmap = vmx_msr_bitmap_nested;
2416         else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
2417                 if (is_long_mode(vcpu))
2418                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2419                 else
2420                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2421         } else {
2422                 if (is_long_mode(vcpu))
2423                         msr_bitmap = vmx_msr_bitmap_longmode;
2424                 else
2425                         msr_bitmap = vmx_msr_bitmap_legacy;
2426         }
2427
2428         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2429 }
2430
2431 /*
2432  * Set up the vmcs to automatically save and restore system
2433  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2434  * mode, as fiddling with msrs is very expensive.
2435  */
2436 static void setup_msrs(struct vcpu_vmx *vmx)
2437 {
2438         int save_nmsrs, index;
2439
2440         save_nmsrs = 0;
2441 #ifdef CONFIG_X86_64
2442         if (is_long_mode(&vmx->vcpu)) {
2443                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2444                 if (index >= 0)
2445                         move_msr_up(vmx, index, save_nmsrs++);
2446                 index = __find_msr_index(vmx, MSR_LSTAR);
2447                 if (index >= 0)
2448                         move_msr_up(vmx, index, save_nmsrs++);
2449                 index = __find_msr_index(vmx, MSR_CSTAR);
2450                 if (index >= 0)
2451                         move_msr_up(vmx, index, save_nmsrs++);
2452                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2453                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2454                         move_msr_up(vmx, index, save_nmsrs++);
2455                 /*
2456                  * MSR_STAR is only needed on long mode guests, and only
2457                  * if efer.sce is enabled.
2458                  */
2459                 index = __find_msr_index(vmx, MSR_STAR);
2460                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2461                         move_msr_up(vmx, index, save_nmsrs++);
2462         }
2463 #endif
2464         index = __find_msr_index(vmx, MSR_EFER);
2465         if (index >= 0 && update_transition_efer(vmx, index))
2466                 move_msr_up(vmx, index, save_nmsrs++);
2467
2468         vmx->save_nmsrs = save_nmsrs;
2469
2470         if (cpu_has_vmx_msr_bitmap())
2471                 vmx_set_msr_bitmap(&vmx->vcpu);
2472 }
2473
2474 /*
2475  * reads and returns guest's timestamp counter "register"
2476  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2477  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2478  */
2479 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2480 {
2481         u64 host_tsc, tsc_offset;
2482
2483         host_tsc = rdtsc();
2484         tsc_offset = vmcs_read64(TSC_OFFSET);
2485         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2486 }
2487
2488 /*
2489  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2490  * counter, even if a nested guest (L2) is currently running.
2491  */
2492 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2493 {
2494         u64 tsc_offset;
2495
2496         tsc_offset = is_guest_mode(vcpu) ?
2497                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2498                 vmcs_read64(TSC_OFFSET);
2499         return host_tsc + tsc_offset;
2500 }
2501
2502 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2503 {
2504         return vmcs_read64(TSC_OFFSET);
2505 }
2506
2507 /*
2508  * writes 'offset' into guest's timestamp counter offset register
2509  */
2510 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2511 {
2512         if (is_guest_mode(vcpu)) {
2513                 /*
2514                  * We're here if L1 chose not to trap WRMSR to TSC. According
2515                  * to the spec, this should set L1's TSC; The offset that L1
2516                  * set for L2 remains unchanged, and still needs to be added
2517                  * to the newly set TSC to get L2's TSC.
2518                  */
2519                 struct vmcs12 *vmcs12;
2520                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2521                 /* recalculate vmcs02.TSC_OFFSET: */
2522                 vmcs12 = get_vmcs12(vcpu);
2523                 vmcs_write64(TSC_OFFSET, offset +
2524                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2525                          vmcs12->tsc_offset : 0));
2526         } else {
2527                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2528                                            vmcs_read64(TSC_OFFSET), offset);
2529                 vmcs_write64(TSC_OFFSET, offset);
2530         }
2531 }
2532
2533 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2534 {
2535         u64 offset = vmcs_read64(TSC_OFFSET);
2536
2537         vmcs_write64(TSC_OFFSET, offset + adjustment);
2538         if (is_guest_mode(vcpu)) {
2539                 /* Even when running L2, the adjustment needs to apply to L1 */
2540                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2541         } else
2542                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2543                                            offset + adjustment);
2544 }
2545
2546 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2547 {
2548         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2549         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2550 }
2551
2552 /*
2553  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2554  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2555  * all guests if the "nested" module option is off, and can also be disabled
2556  * for a single guest by disabling its VMX cpuid bit.
2557  */
2558 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2559 {
2560         return nested && guest_cpuid_has_vmx(vcpu);
2561 }
2562
2563 /*
2564  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2565  * returned for the various VMX controls MSRs when nested VMX is enabled.
2566  * The same values should also be used to verify that vmcs12 control fields are
2567  * valid during nested entry from L1 to L2.
2568  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2569  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2570  * bit in the high half is on if the corresponding bit in the control field
2571  * may be on. See also vmx_control_verify().
2572  */
2573 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2574 {
2575         /*
2576          * Note that as a general rule, the high half of the MSRs (bits in
2577          * the control fields which may be 1) should be initialized by the
2578          * intersection of the underlying hardware's MSR (i.e., features which
2579          * can be supported) and the list of features we want to expose -
2580          * because they are known to be properly supported in our code.
2581          * Also, usually, the low half of the MSRs (bits which must be 1) can
2582          * be set to 0, meaning that L1 may turn off any of these bits. The
2583          * reason is that if one of these bits is necessary, it will appear
2584          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2585          * fields of vmcs01 and vmcs02, will turn these bits off - and
2586          * nested_vmx_exit_handled() will not pass related exits to L1.
2587          * These rules have exceptions below.
2588          */
2589
2590         /* pin-based controls */
2591         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2592                 vmx->nested.nested_vmx_pinbased_ctls_low,
2593                 vmx->nested.nested_vmx_pinbased_ctls_high);
2594         vmx->nested.nested_vmx_pinbased_ctls_low |=
2595                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2596         vmx->nested.nested_vmx_pinbased_ctls_high &=
2597                 PIN_BASED_EXT_INTR_MASK |
2598                 PIN_BASED_NMI_EXITING |
2599                 PIN_BASED_VIRTUAL_NMIS;
2600         vmx->nested.nested_vmx_pinbased_ctls_high |=
2601                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2602                 PIN_BASED_VMX_PREEMPTION_TIMER;
2603         if (kvm_vcpu_apicv_active(&vmx->vcpu))
2604                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2605                         PIN_BASED_POSTED_INTR;
2606
2607         /* exit controls */
2608         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2609                 vmx->nested.nested_vmx_exit_ctls_low,
2610                 vmx->nested.nested_vmx_exit_ctls_high);
2611         vmx->nested.nested_vmx_exit_ctls_low =
2612                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2613
2614         vmx->nested.nested_vmx_exit_ctls_high &=
2615 #ifdef CONFIG_X86_64
2616                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2617 #endif
2618                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2619         vmx->nested.nested_vmx_exit_ctls_high |=
2620                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2621                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2622                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2623
2624         if (kvm_mpx_supported())
2625                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2626
2627         /* We support free control of debug control saving. */
2628         vmx->nested.nested_vmx_true_exit_ctls_low =
2629                 vmx->nested.nested_vmx_exit_ctls_low &
2630                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2631
2632         /* entry controls */
2633         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2634                 vmx->nested.nested_vmx_entry_ctls_low,
2635                 vmx->nested.nested_vmx_entry_ctls_high);
2636         vmx->nested.nested_vmx_entry_ctls_low =
2637                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2638         vmx->nested.nested_vmx_entry_ctls_high &=
2639 #ifdef CONFIG_X86_64
2640                 VM_ENTRY_IA32E_MODE |
2641 #endif
2642                 VM_ENTRY_LOAD_IA32_PAT;
2643         vmx->nested.nested_vmx_entry_ctls_high |=
2644                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2645         if (kvm_mpx_supported())
2646                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2647
2648         /* We support free control of debug control loading. */
2649         vmx->nested.nested_vmx_true_entry_ctls_low =
2650                 vmx->nested.nested_vmx_entry_ctls_low &
2651                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2652
2653         /* cpu-based controls */
2654         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2655                 vmx->nested.nested_vmx_procbased_ctls_low,
2656                 vmx->nested.nested_vmx_procbased_ctls_high);
2657         vmx->nested.nested_vmx_procbased_ctls_low =
2658                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2659         vmx->nested.nested_vmx_procbased_ctls_high &=
2660                 CPU_BASED_VIRTUAL_INTR_PENDING |
2661                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2662                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2663                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2664                 CPU_BASED_CR3_STORE_EXITING |
2665 #ifdef CONFIG_X86_64
2666                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2667 #endif
2668                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2669                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2670                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2671                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2672                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2673         /*
2674          * We can allow some features even when not supported by the
2675          * hardware. For example, L1 can specify an MSR bitmap - and we
2676          * can use it to avoid exits to L1 - even when L0 runs L2
2677          * without MSR bitmaps.
2678          */
2679         vmx->nested.nested_vmx_procbased_ctls_high |=
2680                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2681                 CPU_BASED_USE_MSR_BITMAPS;
2682
2683         /* We support free control of CR3 access interception. */
2684         vmx->nested.nested_vmx_true_procbased_ctls_low =
2685                 vmx->nested.nested_vmx_procbased_ctls_low &
2686                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2687
2688         /* secondary cpu-based controls */
2689         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2690                 vmx->nested.nested_vmx_secondary_ctls_low,
2691                 vmx->nested.nested_vmx_secondary_ctls_high);
2692         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2693         vmx->nested.nested_vmx_secondary_ctls_high &=
2694                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2695                 SECONDARY_EXEC_RDTSCP |
2696                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2697                 SECONDARY_EXEC_ENABLE_VPID |
2698                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2699                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2700                 SECONDARY_EXEC_WBINVD_EXITING |
2701                 SECONDARY_EXEC_XSAVES |
2702                 SECONDARY_EXEC_PCOMMIT;
2703
2704         if (enable_ept) {
2705                 /* nested EPT: emulate EPT also to L1 */
2706                 vmx->nested.nested_vmx_secondary_ctls_high |=
2707                         SECONDARY_EXEC_ENABLE_EPT;
2708                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2709                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2710                          VMX_EPT_INVEPT_BIT;
2711                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2712                 /*
2713                  * For nested guests, we don't do anything specific
2714                  * for single context invalidation. Hence, only advertise
2715                  * support for global context invalidation.
2716                  */
2717                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2718         } else
2719                 vmx->nested.nested_vmx_ept_caps = 0;
2720
2721         /*
2722          * Old versions of KVM use the single-context version without
2723          * checking for support, so declare that it is supported even
2724          * though it is treated as global context.  The alternative is
2725          * not failing the single-context invvpid, and it is worse.
2726          */
2727         if (enable_vpid)
2728                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2729                                 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |
2730                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2731         else
2732                 vmx->nested.nested_vmx_vpid_caps = 0;
2733
2734         if (enable_unrestricted_guest)
2735                 vmx->nested.nested_vmx_secondary_ctls_high |=
2736                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2737
2738         /* miscellaneous data */
2739         rdmsr(MSR_IA32_VMX_MISC,
2740                 vmx->nested.nested_vmx_misc_low,
2741                 vmx->nested.nested_vmx_misc_high);
2742         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2743         vmx->nested.nested_vmx_misc_low |=
2744                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2745                 VMX_MISC_ACTIVITY_HLT;
2746         vmx->nested.nested_vmx_misc_high = 0;
2747 }
2748
2749 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2750 {
2751         /*
2752          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2753          */
2754         return ((control & high) | low) == control;
2755 }
2756
2757 static inline u64 vmx_control_msr(u32 low, u32 high)
2758 {
2759         return low | ((u64)high << 32);
2760 }
2761
2762 /* Returns 0 on success, non-0 otherwise. */
2763 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2764 {
2765         struct vcpu_vmx *vmx = to_vmx(vcpu);
2766
2767         switch (msr_index) {
2768         case MSR_IA32_VMX_BASIC:
2769                 /*
2770                  * This MSR reports some information about VMX support. We
2771                  * should return information about the VMX we emulate for the
2772                  * guest, and the VMCS structure we give it - not about the
2773                  * VMX support of the underlying hardware.
2774                  */
2775                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2776                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2777                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2778                 break;
2779         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2780         case MSR_IA32_VMX_PINBASED_CTLS:
2781                 *pdata = vmx_control_msr(
2782                         vmx->nested.nested_vmx_pinbased_ctls_low,
2783                         vmx->nested.nested_vmx_pinbased_ctls_high);
2784                 break;
2785         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2786                 *pdata = vmx_control_msr(
2787                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2788                         vmx->nested.nested_vmx_procbased_ctls_high);
2789                 break;
2790         case MSR_IA32_VMX_PROCBASED_CTLS:
2791                 *pdata = vmx_control_msr(
2792                         vmx->nested.nested_vmx_procbased_ctls_low,
2793                         vmx->nested.nested_vmx_procbased_ctls_high);
2794                 break;
2795         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2796                 *pdata = vmx_control_msr(
2797                         vmx->nested.nested_vmx_true_exit_ctls_low,
2798                         vmx->nested.nested_vmx_exit_ctls_high);
2799                 break;
2800         case MSR_IA32_VMX_EXIT_CTLS:
2801                 *pdata = vmx_control_msr(
2802                         vmx->nested.nested_vmx_exit_ctls_low,
2803                         vmx->nested.nested_vmx_exit_ctls_high);
2804                 break;
2805         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2806                 *pdata = vmx_control_msr(
2807                         vmx->nested.nested_vmx_true_entry_ctls_low,
2808                         vmx->nested.nested_vmx_entry_ctls_high);
2809                 break;
2810         case MSR_IA32_VMX_ENTRY_CTLS:
2811                 *pdata = vmx_control_msr(
2812                         vmx->nested.nested_vmx_entry_ctls_low,
2813                         vmx->nested.nested_vmx_entry_ctls_high);
2814                 break;
2815         case MSR_IA32_VMX_MISC:
2816                 *pdata = vmx_control_msr(
2817                         vmx->nested.nested_vmx_misc_low,
2818                         vmx->nested.nested_vmx_misc_high);
2819                 break;
2820         /*
2821          * These MSRs specify bits which the guest must keep fixed (on or off)
2822          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2823          * We picked the standard core2 setting.
2824          */
2825 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2826 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2827         case MSR_IA32_VMX_CR0_FIXED0:
2828                 *pdata = VMXON_CR0_ALWAYSON;
2829                 break;
2830         case MSR_IA32_VMX_CR0_FIXED1:
2831                 *pdata = -1ULL;
2832                 break;
2833         case MSR_IA32_VMX_CR4_FIXED0:
2834                 *pdata = VMXON_CR4_ALWAYSON;
2835                 break;
2836         case MSR_IA32_VMX_CR4_FIXED1:
2837                 *pdata = -1ULL;
2838                 break;
2839         case MSR_IA32_VMX_VMCS_ENUM:
2840                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2841                 break;
2842         case MSR_IA32_VMX_PROCBASED_CTLS2:
2843                 *pdata = vmx_control_msr(
2844                         vmx->nested.nested_vmx_secondary_ctls_low,
2845                         vmx->nested.nested_vmx_secondary_ctls_high);
2846                 break;
2847         case MSR_IA32_VMX_EPT_VPID_CAP:
2848                 /* Currently, no nested vpid support */
2849                 *pdata = vmx->nested.nested_vmx_ept_caps |
2850                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2851                 break;
2852         default:
2853                 return 1;
2854         }
2855
2856         return 0;
2857 }
2858
2859 /*
2860  * Reads an msr value (of 'msr_index') into 'pdata'.
2861  * Returns 0 on success, non-0 otherwise.
2862  * Assumes vcpu_load() was already called.
2863  */
2864 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2865 {
2866         struct shared_msr_entry *msr;
2867
2868         switch (msr_info->index) {
2869 #ifdef CONFIG_X86_64
2870         case MSR_FS_BASE:
2871                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2872                 break;
2873         case MSR_GS_BASE:
2874                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2875                 break;
2876         case MSR_KERNEL_GS_BASE:
2877                 vmx_load_host_state(to_vmx(vcpu));
2878                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2879                 break;
2880 #endif
2881         case MSR_EFER:
2882                 return kvm_get_msr_common(vcpu, msr_info);
2883         case MSR_IA32_TSC:
2884                 msr_info->data = guest_read_tsc(vcpu);
2885                 break;
2886         case MSR_IA32_SYSENTER_CS:
2887                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2888                 break;
2889         case MSR_IA32_SYSENTER_EIP:
2890                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2891                 break;
2892         case MSR_IA32_SYSENTER_ESP:
2893                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2894                 break;
2895         case MSR_IA32_BNDCFGS:
2896                 if (!kvm_mpx_supported())
2897                         return 1;
2898                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2899                 break;
2900         case MSR_IA32_FEATURE_CONTROL:
2901                 if (!nested_vmx_allowed(vcpu))
2902                         return 1;
2903                 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2904                 break;
2905         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2906                 if (!nested_vmx_allowed(vcpu))
2907                         return 1;
2908                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2909         case MSR_IA32_XSS:
2910                 if (!vmx_xsaves_supported())
2911                         return 1;
2912                 msr_info->data = vcpu->arch.ia32_xss;
2913                 break;
2914         case MSR_TSC_AUX:
2915                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2916                         return 1;
2917                 /* Otherwise falls through */
2918         default:
2919                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2920                 if (msr) {
2921                         msr_info->data = msr->data;
2922                         break;
2923                 }
2924                 return kvm_get_msr_common(vcpu, msr_info);
2925         }
2926
2927         return 0;
2928 }
2929
2930 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2931
2932 /*
2933  * Writes msr value into into the appropriate "register".
2934  * Returns 0 on success, non-0 otherwise.
2935  * Assumes vcpu_load() was already called.
2936  */
2937 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2938 {
2939         struct vcpu_vmx *vmx = to_vmx(vcpu);
2940         struct shared_msr_entry *msr;
2941         int ret = 0;
2942         u32 msr_index = msr_info->index;
2943         u64 data = msr_info->data;
2944
2945         switch (msr_index) {
2946         case MSR_EFER:
2947                 ret = kvm_set_msr_common(vcpu, msr_info);
2948                 break;
2949 #ifdef CONFIG_X86_64
2950         case MSR_FS_BASE:
2951                 vmx_segment_cache_clear(vmx);
2952                 vmcs_writel(GUEST_FS_BASE, data);
2953                 break;
2954         case MSR_GS_BASE:
2955                 vmx_segment_cache_clear(vmx);
2956                 vmcs_writel(GUEST_GS_BASE, data);
2957                 break;
2958         case MSR_KERNEL_GS_BASE:
2959                 vmx_load_host_state(vmx);
2960                 vmx->msr_guest_kernel_gs_base = data;
2961                 break;
2962 #endif
2963         case MSR_IA32_SYSENTER_CS:
2964                 vmcs_write32(GUEST_SYSENTER_CS, data);
2965                 break;
2966         case MSR_IA32_SYSENTER_EIP:
2967                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2968                 break;
2969         case MSR_IA32_SYSENTER_ESP:
2970                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2971                 break;
2972         case MSR_IA32_BNDCFGS:
2973                 if (!kvm_mpx_supported())
2974                         return 1;
2975                 vmcs_write64(GUEST_BNDCFGS, data);
2976                 break;
2977         case MSR_IA32_TSC:
2978                 kvm_write_tsc(vcpu, msr_info);
2979                 break;
2980         case MSR_IA32_CR_PAT:
2981                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2982                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2983                                 return 1;
2984                         vmcs_write64(GUEST_IA32_PAT, data);
2985                         vcpu->arch.pat = data;
2986                         break;
2987                 }
2988                 ret = kvm_set_msr_common(vcpu, msr_info);
2989                 break;
2990         case MSR_IA32_TSC_ADJUST:
2991                 ret = kvm_set_msr_common(vcpu, msr_info);
2992                 break;
2993         case MSR_IA32_FEATURE_CONTROL:
2994                 if (!nested_vmx_allowed(vcpu) ||
2995                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2996                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2997                         return 1;
2998                 vmx->nested.msr_ia32_feature_control = data;
2999                 if (msr_info->host_initiated && data == 0)
3000                         vmx_leave_nested(vcpu);
3001                 break;
3002         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3003                 return 1; /* they are read-only */
3004         case MSR_IA32_XSS:
3005                 if (!vmx_xsaves_supported())
3006                         return 1;
3007                 /*
3008                  * The only supported bit as of Skylake is bit 8, but
3009                  * it is not supported on KVM.
3010                  */
3011                 if (data != 0)
3012                         return 1;
3013                 vcpu->arch.ia32_xss = data;
3014                 if (vcpu->arch.ia32_xss != host_xss)
3015                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
3016                                 vcpu->arch.ia32_xss, host_xss);
3017                 else
3018                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
3019                 break;
3020         case MSR_TSC_AUX:
3021                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
3022                         return 1;
3023                 /* Check reserved bit, higher 32 bits should be zero */
3024                 if ((data >> 32) != 0)
3025                         return 1;
3026                 /* Otherwise falls through */
3027         default:
3028                 msr = find_msr_entry(vmx, msr_index);
3029                 if (msr) {
3030                         u64 old_msr_data = msr->data;
3031                         msr->data = data;
3032                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
3033                                 preempt_disable();
3034                                 ret = kvm_set_shared_msr(msr->index, msr->data,
3035                                                          msr->mask);
3036                                 preempt_enable();
3037                                 if (ret)
3038                                         msr->data = old_msr_data;
3039                         }
3040                         break;
3041                 }
3042                 ret = kvm_set_msr_common(vcpu, msr_info);
3043         }
3044
3045         return ret;
3046 }
3047
3048 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
3049 {
3050         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
3051         switch (reg) {
3052         case VCPU_REGS_RSP:
3053                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
3054                 break;
3055         case VCPU_REGS_RIP:
3056                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
3057                 break;
3058         case VCPU_EXREG_PDPTR:
3059                 if (enable_ept)
3060                         ept_save_pdptrs(vcpu);
3061                 break;
3062         default:
3063                 break;
3064         }
3065 }
3066
3067 static __init int cpu_has_kvm_support(void)
3068 {
3069         return cpu_has_vmx();
3070 }
3071
3072 static __init int vmx_disabled_by_bios(void)
3073 {
3074         u64 msr;
3075
3076         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
3077         if (msr & FEATURE_CONTROL_LOCKED) {
3078                 /* launched w/ TXT and VMX disabled */
3079                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3080                         && tboot_enabled())
3081                         return 1;
3082                 /* launched w/o TXT and VMX only enabled w/ TXT */
3083                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3084                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3085                         && !tboot_enabled()) {
3086                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3087                                 "activate TXT before enabling KVM\n");
3088                         return 1;
3089                 }
3090                 /* launched w/o TXT and VMX disabled */
3091                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3092                         && !tboot_enabled())
3093                         return 1;
3094         }
3095
3096         return 0;
3097 }
3098
3099 static void kvm_cpu_vmxon(u64 addr)
3100 {
3101         asm volatile (ASM_VMX_VMXON_RAX
3102                         : : "a"(&addr), "m"(addr)
3103                         : "memory", "cc");
3104 }
3105
3106 static int hardware_enable(void)
3107 {
3108         int cpu = raw_smp_processor_id();
3109         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3110         u64 old, test_bits;
3111
3112         if (cr4_read_shadow() & X86_CR4_VMXE)
3113                 return -EBUSY;
3114
3115         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3116         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3117         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3118
3119         /*
3120          * Now we can enable the vmclear operation in kdump
3121          * since the loaded_vmcss_on_cpu list on this cpu
3122          * has been initialized.
3123          *
3124          * Though the cpu is not in VMX operation now, there
3125          * is no problem to enable the vmclear operation
3126          * for the loaded_vmcss_on_cpu list is empty!
3127          */
3128         crash_enable_local_vmclear(cpu);
3129
3130         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3131
3132         test_bits = FEATURE_CONTROL_LOCKED;
3133         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3134         if (tboot_enabled())
3135                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3136
3137         if ((old & test_bits) != test_bits) {
3138                 /* enable and lock */
3139                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3140         }
3141         cr4_set_bits(X86_CR4_VMXE);
3142
3143         if (vmm_exclusive) {
3144                 kvm_cpu_vmxon(phys_addr);
3145                 ept_sync_global();
3146         }
3147
3148         native_store_gdt(this_cpu_ptr(&host_gdt));
3149
3150         return 0;
3151 }
3152
3153 static void vmclear_local_loaded_vmcss(void)
3154 {
3155         int cpu = raw_smp_processor_id();
3156         struct loaded_vmcs *v, *n;
3157
3158         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3159                                  loaded_vmcss_on_cpu_link)
3160                 __loaded_vmcs_clear(v);
3161 }
3162
3163
3164 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3165  * tricks.
3166  */
3167 static void kvm_cpu_vmxoff(void)
3168 {
3169         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3170 }
3171
3172 static void hardware_disable(void)
3173 {
3174         if (vmm_exclusive) {
3175                 vmclear_local_loaded_vmcss();
3176                 kvm_cpu_vmxoff();
3177         }
3178         cr4_clear_bits(X86_CR4_VMXE);
3179 }
3180
3181 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3182                                       u32 msr, u32 *result)
3183 {
3184         u32 vmx_msr_low, vmx_msr_high;
3185         u32 ctl = ctl_min | ctl_opt;
3186
3187         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3188
3189         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3190         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3191
3192         /* Ensure minimum (required) set of control bits are supported. */
3193         if (ctl_min & ~ctl)
3194                 return -EIO;
3195
3196         *result = ctl;
3197         return 0;
3198 }
3199
3200 static __init bool allow_1_setting(u32 msr, u32 ctl)
3201 {
3202         u32 vmx_msr_low, vmx_msr_high;
3203
3204         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3205         return vmx_msr_high & ctl;
3206 }
3207
3208 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3209 {
3210         u32 vmx_msr_low, vmx_msr_high;
3211         u32 min, opt, min2, opt2;
3212         u32 _pin_based_exec_control = 0;
3213         u32 _cpu_based_exec_control = 0;
3214         u32 _cpu_based_2nd_exec_control = 0;
3215         u32 _vmexit_control = 0;
3216         u32 _vmentry_control = 0;
3217
3218         min = CPU_BASED_HLT_EXITING |
3219 #ifdef CONFIG_X86_64
3220               CPU_BASED_CR8_LOAD_EXITING |
3221               CPU_BASED_CR8_STORE_EXITING |
3222 #endif
3223               CPU_BASED_CR3_LOAD_EXITING |
3224               CPU_BASED_CR3_STORE_EXITING |
3225               CPU_BASED_USE_IO_BITMAPS |
3226               CPU_BASED_MOV_DR_EXITING |
3227               CPU_BASED_USE_TSC_OFFSETING |
3228               CPU_BASED_MWAIT_EXITING |
3229               CPU_BASED_MONITOR_EXITING |
3230               CPU_BASED_INVLPG_EXITING |
3231               CPU_BASED_RDPMC_EXITING;
3232
3233         opt = CPU_BASED_TPR_SHADOW |
3234               CPU_BASED_USE_MSR_BITMAPS |
3235               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3236         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3237                                 &_cpu_based_exec_control) < 0)
3238                 return -EIO;
3239 #ifdef CONFIG_X86_64
3240         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3241                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3242                                            ~CPU_BASED_CR8_STORE_EXITING;
3243 #endif
3244         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3245                 min2 = 0;
3246                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3247                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3248                         SECONDARY_EXEC_WBINVD_EXITING |
3249                         SECONDARY_EXEC_ENABLE_VPID |
3250                         SECONDARY_EXEC_ENABLE_EPT |
3251                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3252                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3253                         SECONDARY_EXEC_RDTSCP |
3254                         SECONDARY_EXEC_ENABLE_INVPCID |
3255                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3256                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3257                         SECONDARY_EXEC_SHADOW_VMCS |
3258                         SECONDARY_EXEC_XSAVES |
3259                         SECONDARY_EXEC_ENABLE_PML |
3260                         SECONDARY_EXEC_PCOMMIT |
3261                         SECONDARY_EXEC_TSC_SCALING;
3262                 if (adjust_vmx_controls(min2, opt2,
3263                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3264                                         &_cpu_based_2nd_exec_control) < 0)
3265                         return -EIO;
3266         }
3267 #ifndef CONFIG_X86_64
3268         if (!(_cpu_based_2nd_exec_control &
3269                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3270                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3271 #endif
3272
3273         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3274                 _cpu_based_2nd_exec_control &= ~(
3275                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3276                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3277                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3278
3279         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3280                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3281                    enabled */
3282                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3283                                              CPU_BASED_CR3_STORE_EXITING |
3284                                              CPU_BASED_INVLPG_EXITING);
3285                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3286                       vmx_capability.ept, vmx_capability.vpid);
3287         }
3288
3289         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3290 #ifdef CONFIG_X86_64
3291         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3292 #endif
3293         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3294                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3295         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3296                                 &_vmexit_control) < 0)
3297                 return -EIO;
3298
3299         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3300         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3301         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3302                                 &_pin_based_exec_control) < 0)
3303                 return -EIO;
3304
3305         if (!(_cpu_based_2nd_exec_control &
3306                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3307                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3308                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3309
3310         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3311         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3312         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3313                                 &_vmentry_control) < 0)
3314                 return -EIO;
3315
3316         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3317
3318         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3319         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3320                 return -EIO;
3321
3322 #ifdef CONFIG_X86_64
3323         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3324         if (vmx_msr_high & (1u<<16))
3325                 return -EIO;
3326 #endif
3327
3328         /* Require Write-Back (WB) memory type for VMCS accesses. */
3329         if (((vmx_msr_high >> 18) & 15) != 6)
3330                 return -EIO;
3331
3332         vmcs_conf->size = vmx_msr_high & 0x1fff;
3333         vmcs_conf->order = get_order(vmcs_config.size);
3334         vmcs_conf->revision_id = vmx_msr_low;
3335
3336         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3337         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3338         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3339         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3340         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3341
3342         cpu_has_load_ia32_efer =
3343                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3344                                 VM_ENTRY_LOAD_IA32_EFER)
3345                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3346                                    VM_EXIT_LOAD_IA32_EFER);
3347
3348         cpu_has_load_perf_global_ctrl =
3349                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3350                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3351                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3352                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3353
3354         /*
3355          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3356          * but due to arrata below it can't be used. Workaround is to use
3357          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3358          *
3359          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3360          *
3361          * AAK155             (model 26)
3362          * AAP115             (model 30)
3363          * AAT100             (model 37)
3364          * BC86,AAY89,BD102   (model 44)
3365          * BA97               (model 46)
3366          *
3367          */
3368         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3369                 switch (boot_cpu_data.x86_model) {
3370                 case 26:
3371                 case 30:
3372                 case 37:
3373                 case 44:
3374                 case 46:
3375                         cpu_has_load_perf_global_ctrl = false;
3376                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3377                                         "does not work properly. Using workaround\n");
3378                         break;
3379                 default:
3380                         break;
3381                 }
3382         }
3383
3384         if (cpu_has_xsaves)
3385                 rdmsrl(MSR_IA32_XSS, host_xss);
3386
3387         return 0;
3388 }
3389
3390 static struct vmcs *alloc_vmcs_cpu(int cpu)
3391 {
3392         int node = cpu_to_node(cpu);
3393         struct page *pages;
3394         struct vmcs *vmcs;
3395
3396         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3397         if (!pages)
3398                 return NULL;
3399         vmcs = page_address(pages);
3400         memset(vmcs, 0, vmcs_config.size);
3401         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3402         return vmcs;
3403 }
3404
3405 static struct vmcs *alloc_vmcs(void)
3406 {
3407         return alloc_vmcs_cpu(raw_smp_processor_id());
3408 }
3409
3410 static void free_vmcs(struct vmcs *vmcs)
3411 {
3412         free_pages((unsigned long)vmcs, vmcs_config.order);
3413 }
3414
3415 /*
3416  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3417  */
3418 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3419 {
3420         if (!loaded_vmcs->vmcs)
3421                 return;
3422         loaded_vmcs_clear(loaded_vmcs);
3423         free_vmcs(loaded_vmcs->vmcs);
3424         loaded_vmcs->vmcs = NULL;
3425 }
3426
3427 static void free_kvm_area(void)
3428 {
3429         int cpu;
3430
3431         for_each_possible_cpu(cpu) {
3432                 free_vmcs(per_cpu(vmxarea, cpu));
3433                 per_cpu(vmxarea, cpu) = NULL;
3434         }
3435 }
3436
3437 static void init_vmcs_shadow_fields(void)
3438 {
3439         int i, j;
3440
3441         /* No checks for read only fields yet */
3442
3443         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3444                 switch (shadow_read_write_fields[i]) {
3445                 case GUEST_BNDCFGS:
3446                         if (!kvm_mpx_supported())
3447                                 continue;
3448                         break;
3449                 default:
3450                         break;
3451                 }
3452
3453                 if (j < i)
3454                         shadow_read_write_fields[j] =
3455                                 shadow_read_write_fields[i];
3456                 j++;
3457         }
3458         max_shadow_read_write_fields = j;
3459
3460         /* shadowed fields guest access without vmexit */
3461         for (i = 0; i < max_shadow_read_write_fields; i++) {
3462                 clear_bit(shadow_read_write_fields[i],
3463                           vmx_vmwrite_bitmap);
3464                 clear_bit(shadow_read_write_fields[i],
3465                           vmx_vmread_bitmap);
3466         }
3467         for (i = 0; i < max_shadow_read_only_fields; i++)
3468                 clear_bit(shadow_read_only_fields[i],
3469                           vmx_vmread_bitmap);
3470 }
3471
3472 static __init int alloc_kvm_area(void)
3473 {
3474         int cpu;
3475
3476         for_each_possible_cpu(cpu) {
3477                 struct vmcs *vmcs;
3478
3479                 vmcs = alloc_vmcs_cpu(cpu);
3480                 if (!vmcs) {
3481                         free_kvm_area();
3482                         return -ENOMEM;
3483                 }
3484
3485                 per_cpu(vmxarea, cpu) = vmcs;
3486         }
3487         return 0;
3488 }
3489
3490 static bool emulation_required(struct kvm_vcpu *vcpu)
3491 {
3492         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3493 }
3494
3495 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3496                 struct kvm_segment *save)
3497 {
3498         if (!emulate_invalid_guest_state) {
3499                 /*
3500                  * CS and SS RPL should be equal during guest entry according
3501                  * to VMX spec, but in reality it is not always so. Since vcpu
3502                  * is in the middle of the transition from real mode to
3503                  * protected mode it is safe to assume that RPL 0 is a good
3504                  * default value.
3505                  */
3506                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3507                         save->selector &= ~SEGMENT_RPL_MASK;
3508                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3509                 save->s = 1;
3510         }
3511         vmx_set_segment(vcpu, save, seg);
3512 }
3513
3514 static void enter_pmode(struct kvm_vcpu *vcpu)
3515 {
3516         unsigned long flags;
3517         struct vcpu_vmx *vmx = to_vmx(vcpu);
3518
3519         /*
3520          * Update real mode segment cache. It may be not up-to-date if sement
3521          * register was written while vcpu was in a guest mode.
3522          */
3523         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3524         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3525         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3526         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3527         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3528         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3529
3530         vmx->rmode.vm86_active = 0;
3531
3532         vmx_segment_cache_clear(vmx);
3533
3534         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3535
3536         flags = vmcs_readl(GUEST_RFLAGS);
3537         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3538         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3539         vmcs_writel(GUEST_RFLAGS, flags);
3540
3541         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3542                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3543
3544         update_exception_bitmap(vcpu);
3545
3546         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3547         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3548         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3549         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3550         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3551         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3552 }
3553
3554 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3555 {
3556         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3557         struct kvm_segment var = *save;
3558
3559         var.dpl = 0x3;
3560         if (seg == VCPU_SREG_CS)
3561                 var.type = 0x3;
3562
3563         if (!emulate_invalid_guest_state) {
3564                 var.selector = var.base >> 4;
3565                 var.base = var.base & 0xffff0;
3566                 var.limit = 0xffff;
3567                 var.g = 0;
3568                 var.db = 0;
3569                 var.present = 1;
3570                 var.s = 1;
3571                 var.l = 0;
3572                 var.unusable = 0;
3573                 var.type = 0x3;
3574                 var.avl = 0;
3575                 if (save->base & 0xf)
3576                         printk_once(KERN_WARNING "kvm: segment base is not "
3577                                         "paragraph aligned when entering "
3578                                         "protected mode (seg=%d)", seg);
3579         }
3580
3581         vmcs_write16(sf->selector, var.selector);
3582         vmcs_write32(sf->base, var.base);
3583         vmcs_write32(sf->limit, var.limit);
3584         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3585 }
3586
3587 static void enter_rmode(struct kvm_vcpu *vcpu)
3588 {
3589         unsigned long flags;
3590         struct vcpu_vmx *vmx = to_vmx(vcpu);
3591
3592         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3593         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3594         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3595         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3596         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3597         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3598         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3599
3600         vmx->rmode.vm86_active = 1;
3601
3602         /*
3603          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3604          * vcpu. Warn the user that an update is overdue.
3605          */
3606         if (!vcpu->kvm->arch.tss_addr)
3607                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3608                              "called before entering vcpu\n");
3609
3610         vmx_segment_cache_clear(vmx);
3611
3612         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3613         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3614         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3615
3616         flags = vmcs_readl(GUEST_RFLAGS);
3617         vmx->rmode.save_rflags = flags;
3618
3619         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3620
3621         vmcs_writel(GUEST_RFLAGS, flags);
3622         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3623         update_exception_bitmap(vcpu);
3624
3625         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3626         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3627         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3628         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3629         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3630         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3631
3632         kvm_mmu_reset_context(vcpu);
3633 }
3634
3635 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3636 {
3637         struct vcpu_vmx *vmx = to_vmx(vcpu);
3638         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3639
3640         if (!msr)
3641                 return;
3642
3643         /*
3644          * Force kernel_gs_base reloading before EFER changes, as control
3645          * of this msr depends on is_long_mode().
3646          */
3647         vmx_load_host_state(to_vmx(vcpu));
3648         vcpu->arch.efer = efer;
3649         if (efer & EFER_LMA) {
3650                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3651                 msr->data = efer;
3652         } else {
3653                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3654
3655                 msr->data = efer & ~EFER_LME;
3656         }
3657         setup_msrs(vmx);
3658 }
3659
3660 #ifdef CONFIG_X86_64
3661
3662 static void enter_lmode(struct kvm_vcpu *vcpu)
3663 {
3664         u32 guest_tr_ar;
3665
3666         vmx_segment_cache_clear(to_vmx(vcpu));
3667
3668         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3669         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3670                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3671                                      __func__);
3672                 vmcs_write32(GUEST_TR_AR_BYTES,
3673                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3674                              | VMX_AR_TYPE_BUSY_64_TSS);
3675         }
3676         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3677 }
3678
3679 static void exit_lmode(struct kvm_vcpu *vcpu)
3680 {
3681         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3682         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3683 }
3684
3685 #endif
3686
3687 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3688 {
3689         vpid_sync_context(vpid);
3690         if (enable_ept) {
3691                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3692                         return;
3693                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3694         }
3695 }
3696
3697 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3698 {
3699         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3700 }
3701
3702 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3703 {
3704         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3705
3706         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3707         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3708 }
3709
3710 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3711 {
3712         if (enable_ept && is_paging(vcpu))
3713                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3714         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3715 }
3716
3717 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3718 {
3719         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3720
3721         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3722         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3723 }
3724
3725 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3726 {
3727         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3728
3729         if (!test_bit(VCPU_EXREG_PDPTR,
3730                       (unsigned long *)&vcpu->arch.regs_dirty))
3731                 return;
3732
3733         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3734                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3735                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3736                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3737                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3738         }
3739 }
3740
3741 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3742 {
3743         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3744
3745         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3746                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3747                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3748                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3749                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3750         }
3751
3752         __set_bit(VCPU_EXREG_PDPTR,
3753                   (unsigned long *)&vcpu->arch.regs_avail);
3754         __set_bit(VCPU_EXREG_PDPTR,
3755                   (unsigned long *)&vcpu->arch.regs_dirty);
3756 }
3757
3758 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3759
3760 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3761                                         unsigned long cr0,
3762                                         struct kvm_vcpu *vcpu)
3763 {
3764         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3765                 vmx_decache_cr3(vcpu);
3766         if (!(cr0 & X86_CR0_PG)) {
3767                 /* From paging/starting to nonpaging */
3768                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3769                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3770                              (CPU_BASED_CR3_LOAD_EXITING |
3771                               CPU_BASED_CR3_STORE_EXITING));
3772                 vcpu->arch.cr0 = cr0;
3773                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3774         } else if (!is_paging(vcpu)) {
3775                 /* From nonpaging to paging */
3776                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3777                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3778                              ~(CPU_BASED_CR3_LOAD_EXITING |
3779                                CPU_BASED_CR3_STORE_EXITING));
3780                 vcpu->arch.cr0 = cr0;
3781                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3782         }
3783
3784         if (!(cr0 & X86_CR0_WP))
3785                 *hw_cr0 &= ~X86_CR0_WP;
3786 }
3787
3788 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3789 {
3790         struct vcpu_vmx *vmx = to_vmx(vcpu);
3791         unsigned long hw_cr0;
3792
3793         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3794         if (enable_unrestricted_guest)
3795                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3796         else {
3797                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3798
3799                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3800                         enter_pmode(vcpu);
3801
3802                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3803                         enter_rmode(vcpu);
3804         }
3805
3806 #ifdef CONFIG_X86_64
3807         if (vcpu->arch.efer & EFER_LME) {
3808                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3809                         enter_lmode(vcpu);
3810                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3811                         exit_lmode(vcpu);
3812         }
3813 #endif
3814
3815         if (enable_ept)
3816                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3817
3818         if (!vcpu->fpu_active)
3819                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3820
3821         vmcs_writel(CR0_READ_SHADOW, cr0);
3822         vmcs_writel(GUEST_CR0, hw_cr0);
3823         vcpu->arch.cr0 = cr0;
3824
3825         /* depends on vcpu->arch.cr0 to be set to a new value */
3826         vmx->emulation_required = emulation_required(vcpu);
3827 }
3828
3829 static u64 construct_eptp(unsigned long root_hpa)
3830 {
3831         u64 eptp;
3832
3833         /* TODO write the value reading from MSR */
3834         eptp = VMX_EPT_DEFAULT_MT |
3835                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3836         if (enable_ept_ad_bits)
3837                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3838         eptp |= (root_hpa & PAGE_MASK);
3839
3840         return eptp;
3841 }
3842
3843 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3844 {
3845         unsigned long guest_cr3;
3846         u64 eptp;
3847
3848         guest_cr3 = cr3;
3849         if (enable_ept) {
3850                 eptp = construct_eptp(cr3);
3851                 vmcs_write64(EPT_POINTER, eptp);
3852                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3853                         guest_cr3 = kvm_read_cr3(vcpu);
3854                 else
3855                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3856                 ept_load_pdptrs(vcpu);
3857         }
3858
3859         vmx_flush_tlb(vcpu);
3860         vmcs_writel(GUEST_CR3, guest_cr3);
3861 }
3862
3863 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3864 {
3865         /*
3866          * Pass through host's Machine Check Enable value to hw_cr4, which
3867          * is in force while we are in guest mode.  Do not let guests control
3868          * this bit, even if host CR4.MCE == 0.
3869          */
3870         unsigned long hw_cr4 =
3871                 (cr4_read_shadow() & X86_CR4_MCE) |
3872                 (cr4 & ~X86_CR4_MCE) |
3873                 (to_vmx(vcpu)->rmode.vm86_active ?
3874                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3875
3876         if (cr4 & X86_CR4_VMXE) {
3877                 /*
3878                  * To use VMXON (and later other VMX instructions), a guest
3879                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3880                  * So basically the check on whether to allow nested VMX
3881                  * is here.
3882                  */
3883                 if (!nested_vmx_allowed(vcpu))
3884                         return 1;
3885         }
3886         if (to_vmx(vcpu)->nested.vmxon &&
3887             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3888                 return 1;
3889
3890         vcpu->arch.cr4 = cr4;
3891         if (enable_ept) {
3892                 if (!is_paging(vcpu)) {
3893                         hw_cr4 &= ~X86_CR4_PAE;
3894                         hw_cr4 |= X86_CR4_PSE;
3895                 } else if (!(cr4 & X86_CR4_PAE)) {
3896                         hw_cr4 &= ~X86_CR4_PAE;
3897                 }
3898         }
3899
3900         if (!enable_unrestricted_guest && !is_paging(vcpu))
3901                 /*
3902                  * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
3903                  * hardware.  To emulate this behavior, SMEP/SMAP/PKU needs
3904                  * to be manually disabled when guest switches to non-paging
3905                  * mode.
3906                  *
3907                  * If !enable_unrestricted_guest, the CPU is always running
3908                  * with CR0.PG=1 and CR4 needs to be modified.
3909                  * If enable_unrestricted_guest, the CPU automatically
3910                  * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
3911                  */
3912                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
3913
3914         vmcs_writel(CR4_READ_SHADOW, cr4);
3915         vmcs_writel(GUEST_CR4, hw_cr4);
3916         return 0;
3917 }
3918
3919 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3920                             struct kvm_segment *var, int seg)
3921 {
3922         struct vcpu_vmx *vmx = to_vmx(vcpu);
3923         u32 ar;
3924
3925         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3926                 *var = vmx->rmode.segs[seg];
3927                 if (seg == VCPU_SREG_TR
3928                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3929                         return;
3930                 var->base = vmx_read_guest_seg_base(vmx, seg);
3931                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3932                 return;
3933         }
3934         var->base = vmx_read_guest_seg_base(vmx, seg);
3935         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3936         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3937         ar = vmx_read_guest_seg_ar(vmx, seg);
3938         var->unusable = (ar >> 16) & 1;
3939         var->type = ar & 15;
3940         var->s = (ar >> 4) & 1;
3941         var->dpl = (ar >> 5) & 3;
3942         /*
3943          * Some userspaces do not preserve unusable property. Since usable
3944          * segment has to be present according to VMX spec we can use present
3945          * property to amend userspace bug by making unusable segment always
3946          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3947          * segment as unusable.
3948          */
3949         var->present = !var->unusable;
3950         var->avl = (ar >> 12) & 1;
3951         var->l = (ar >> 13) & 1;
3952         var->db = (ar >> 14) & 1;
3953         var->g = (ar >> 15) & 1;
3954 }
3955
3956 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3957 {
3958         struct kvm_segment s;
3959
3960         if (to_vmx(vcpu)->rmode.vm86_active) {
3961                 vmx_get_segment(vcpu, &s, seg);
3962                 return s.base;
3963         }
3964         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3965 }
3966
3967 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3968 {
3969         struct vcpu_vmx *vmx = to_vmx(vcpu);
3970
3971         if (unlikely(vmx->rmode.vm86_active))
3972                 return 0;
3973         else {
3974                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3975                 return VMX_AR_DPL(ar);
3976         }
3977 }
3978
3979 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3980 {
3981         u32 ar;
3982
3983         if (var->unusable || !var->present)
3984                 ar = 1 << 16;
3985         else {
3986                 ar = var->type & 15;
3987                 ar |= (var->s & 1) << 4;
3988                 ar |= (var->dpl & 3) << 5;
3989                 ar |= (var->present & 1) << 7;
3990                 ar |= (var->avl & 1) << 12;
3991                 ar |= (var->l & 1) << 13;
3992                 ar |= (var->db & 1) << 14;
3993                 ar |= (var->g & 1) << 15;
3994         }
3995
3996         return ar;
3997 }
3998
3999 static void vmx_set_segment(struct kvm_vcpu *vcpu,
4000                             struct kvm_segment *var, int seg)
4001 {
4002         struct vcpu_vmx *vmx = to_vmx(vcpu);
4003         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4004
4005         vmx_segment_cache_clear(vmx);
4006
4007         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
4008                 vmx->rmode.segs[seg] = *var;
4009                 if (seg == VCPU_SREG_TR)
4010                         vmcs_write16(sf->selector, var->selector);
4011                 else if (var->s)
4012                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
4013                 goto out;
4014         }
4015
4016         vmcs_writel(sf->base, var->base);
4017         vmcs_write32(sf->limit, var->limit);
4018         vmcs_write16(sf->selector, var->selector);
4019
4020         /*
4021          *   Fix the "Accessed" bit in AR field of segment registers for older
4022          * qemu binaries.
4023          *   IA32 arch specifies that at the time of processor reset the
4024          * "Accessed" bit in the AR field of segment registers is 1. And qemu
4025          * is setting it to 0 in the userland code. This causes invalid guest
4026          * state vmexit when "unrestricted guest" mode is turned on.
4027          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
4028          * tree. Newer qemu binaries with that qemu fix would not need this
4029          * kvm hack.
4030          */
4031         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
4032                 var->type |= 0x1; /* Accessed */
4033
4034         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
4035
4036 out:
4037         vmx->emulation_required = emulation_required(vcpu);
4038 }
4039
4040 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
4041 {
4042         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
4043
4044         *db = (ar >> 14) & 1;
4045         *l = (ar >> 13) & 1;
4046 }
4047
4048 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4049 {
4050         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
4051         dt->address = vmcs_readl(GUEST_IDTR_BASE);
4052 }
4053
4054 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4055 {
4056         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
4057         vmcs_writel(GUEST_IDTR_BASE, dt->address);
4058 }
4059
4060 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4061 {
4062         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
4063         dt->address = vmcs_readl(GUEST_GDTR_BASE);
4064 }
4065
4066 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
4067 {
4068         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
4069         vmcs_writel(GUEST_GDTR_BASE, dt->address);
4070 }
4071
4072 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
4073 {
4074         struct kvm_segment var;
4075         u32 ar;
4076
4077         vmx_get_segment(vcpu, &var, seg);
4078         var.dpl = 0x3;
4079         if (seg == VCPU_SREG_CS)
4080                 var.type = 0x3;
4081         ar = vmx_segment_access_rights(&var);
4082
4083         if (var.base != (var.selector << 4))
4084                 return false;
4085         if (var.limit != 0xffff)
4086                 return false;
4087         if (ar != 0xf3)
4088                 return false;
4089
4090         return true;
4091 }
4092
4093 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4094 {
4095         struct kvm_segment cs;
4096         unsigned int cs_rpl;
4097
4098         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4099         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4100
4101         if (cs.unusable)
4102                 return false;
4103         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4104                 return false;
4105         if (!cs.s)
4106                 return false;
4107         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4108                 if (cs.dpl > cs_rpl)
4109                         return false;
4110         } else {
4111                 if (cs.dpl != cs_rpl)
4112                         return false;
4113         }
4114         if (!cs.present)
4115                 return false;
4116
4117         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4118         return true;
4119 }
4120
4121 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4122 {
4123         struct kvm_segment ss;
4124         unsigned int ss_rpl;
4125
4126         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4127         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4128
4129         if (ss.unusable)
4130                 return true;
4131         if (ss.type != 3 && ss.type != 7)
4132                 return false;
4133         if (!ss.s)
4134                 return false;
4135         if (ss.dpl != ss_rpl) /* DPL != RPL */
4136                 return false;
4137         if (!ss.present)
4138                 return false;
4139
4140         return true;
4141 }
4142
4143 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4144 {
4145         struct kvm_segment var;
4146         unsigned int rpl;
4147
4148         vmx_get_segment(vcpu, &var, seg);
4149         rpl = var.selector & SEGMENT_RPL_MASK;
4150
4151         if (var.unusable)
4152                 return true;
4153         if (!var.s)
4154                 return false;
4155         if (!var.present)
4156                 return false;
4157         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4158                 if (var.dpl < rpl) /* DPL < RPL */
4159                         return false;
4160         }
4161
4162         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4163          * rights flags
4164          */
4165         return true;
4166 }
4167
4168 static bool tr_valid(struct kvm_vcpu *vcpu)
4169 {
4170         struct kvm_segment tr;
4171
4172         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4173
4174         if (tr.unusable)
4175                 return false;
4176         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4177                 return false;
4178         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4179                 return false;
4180         if (!tr.present)
4181                 return false;
4182
4183         return true;
4184 }
4185
4186 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4187 {
4188         struct kvm_segment ldtr;
4189
4190         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4191
4192         if (ldtr.unusable)
4193                 return true;
4194         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4195                 return false;
4196         if (ldtr.type != 2)
4197                 return false;
4198         if (!ldtr.present)
4199                 return false;
4200
4201         return true;
4202 }
4203
4204 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4205 {
4206         struct kvm_segment cs, ss;
4207
4208         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4209         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4210
4211         return ((cs.selector & SEGMENT_RPL_MASK) ==
4212                  (ss.selector & SEGMENT_RPL_MASK));
4213 }
4214
4215 /*
4216  * Check if guest state is valid. Returns true if valid, false if
4217  * not.
4218  * We assume that registers are always usable
4219  */
4220 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4221 {
4222         if (enable_unrestricted_guest)
4223                 return true;
4224
4225         /* real mode guest state checks */
4226         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4227                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4228                         return false;
4229                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4230                         return false;
4231                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4232                         return false;
4233                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4234                         return false;
4235                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4236                         return false;
4237                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4238                         return false;
4239         } else {
4240         /* protected mode guest state checks */
4241                 if (!cs_ss_rpl_check(vcpu))
4242                         return false;
4243                 if (!code_segment_valid(vcpu))
4244                         return false;
4245                 if (!stack_segment_valid(vcpu))
4246                         return false;
4247                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4248                         return false;
4249                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4250                         return false;
4251                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4252                         return false;
4253                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4254                         return false;
4255                 if (!tr_valid(vcpu))
4256                         return false;
4257                 if (!ldtr_valid(vcpu))
4258                         return false;
4259         }
4260         /* TODO:
4261          * - Add checks on RIP
4262          * - Add checks on RFLAGS
4263          */
4264
4265         return true;
4266 }
4267
4268 static int init_rmode_tss(struct kvm *kvm)
4269 {
4270         gfn_t fn;
4271         u16 data = 0;
4272         int idx, r;
4273
4274         idx = srcu_read_lock(&kvm->srcu);
4275         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4276         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4277         if (r < 0)
4278                 goto out;
4279         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4280         r = kvm_write_guest_page(kvm, fn++, &data,
4281                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4282         if (r < 0)
4283                 goto out;
4284         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4285         if (r < 0)
4286                 goto out;
4287         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4288         if (r < 0)
4289                 goto out;
4290         data = ~0;
4291         r = kvm_write_guest_page(kvm, fn, &data,
4292                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4293                                  sizeof(u8));
4294 out:
4295         srcu_read_unlock(&kvm->srcu, idx);
4296         return r;
4297 }
4298
4299 static int init_rmode_identity_map(struct kvm *kvm)
4300 {
4301         int i, idx, r = 0;
4302         kvm_pfn_t identity_map_pfn;
4303         u32 tmp;
4304
4305         if (!enable_ept)
4306                 return 0;
4307
4308         /* Protect kvm->arch.ept_identity_pagetable_done. */
4309         mutex_lock(&kvm->slots_lock);
4310
4311         if (likely(kvm->arch.ept_identity_pagetable_done))
4312                 goto out2;
4313
4314         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4315
4316         r = alloc_identity_pagetable(kvm);
4317         if (r < 0)
4318                 goto out2;
4319
4320         idx = srcu_read_lock(&kvm->srcu);
4321         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4322         if (r < 0)
4323                 goto out;
4324         /* Set up identity-mapping pagetable for EPT in real mode */
4325         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4326                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4327                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4328                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4329                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4330                 if (r < 0)
4331                         goto out;
4332         }
4333         kvm->arch.ept_identity_pagetable_done = true;
4334
4335 out:
4336         srcu_read_unlock(&kvm->srcu, idx);
4337
4338 out2:
4339         mutex_unlock(&kvm->slots_lock);
4340         return r;
4341 }
4342
4343 static void seg_setup(int seg)
4344 {
4345         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4346         unsigned int ar;
4347
4348         vmcs_write16(sf->selector, 0);
4349         vmcs_writel(sf->base, 0);
4350         vmcs_write32(sf->limit, 0xffff);
4351         ar = 0x93;
4352         if (seg == VCPU_SREG_CS)
4353                 ar |= 0x08; /* code segment */
4354
4355         vmcs_write32(sf->ar_bytes, ar);
4356 }
4357
4358 static int alloc_apic_access_page(struct kvm *kvm)
4359 {
4360         struct page *page;
4361         int r = 0;
4362
4363         mutex_lock(&kvm->slots_lock);
4364         if (kvm->arch.apic_access_page_done)
4365                 goto out;
4366         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4367                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4368         if (r)
4369                 goto out;
4370
4371         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4372         if (is_error_page(page)) {
4373                 r = -EFAULT;
4374                 goto out;
4375         }
4376
4377         /*
4378          * Do not pin the page in memory, so that memory hot-unplug
4379          * is able to migrate it.
4380          */
4381         put_page(page);
4382         kvm->arch.apic_access_page_done = true;
4383 out:
4384         mutex_unlock(&kvm->slots_lock);
4385         return r;
4386 }
4387
4388 static int alloc_identity_pagetable(struct kvm *kvm)
4389 {
4390         /* Called with kvm->slots_lock held. */
4391
4392         int r = 0;
4393
4394         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4395
4396         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4397                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4398
4399         return r;
4400 }
4401
4402 static int allocate_vpid(void)
4403 {
4404         int vpid;
4405
4406         if (!enable_vpid)
4407                 return 0;
4408         spin_lock(&vmx_vpid_lock);
4409         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4410         if (vpid < VMX_NR_VPIDS)
4411                 __set_bit(vpid, vmx_vpid_bitmap);
4412         else
4413                 vpid = 0;
4414         spin_unlock(&vmx_vpid_lock);
4415         return vpid;
4416 }
4417
4418 static void free_vpid(int vpid)
4419 {
4420         if (!enable_vpid || vpid == 0)
4421                 return;
4422         spin_lock(&vmx_vpid_lock);
4423         __clear_bit(vpid, vmx_vpid_bitmap);
4424         spin_unlock(&vmx_vpid_lock);
4425 }
4426
4427 #define MSR_TYPE_R      1
4428 #define MSR_TYPE_W      2
4429 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4430                                                 u32 msr, int type)
4431 {
4432         int f = sizeof(unsigned long);
4433
4434         if (!cpu_has_vmx_msr_bitmap())
4435                 return;
4436
4437         /*
4438          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4439          * have the write-low and read-high bitmap offsets the wrong way round.
4440          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4441          */
4442         if (msr <= 0x1fff) {
4443                 if (type & MSR_TYPE_R)
4444                         /* read-low */
4445                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4446
4447                 if (type & MSR_TYPE_W)
4448                         /* write-low */
4449                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4450
4451         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4452                 msr &= 0x1fff;
4453                 if (type & MSR_TYPE_R)
4454                         /* read-high */
4455                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4456
4457                 if (type & MSR_TYPE_W)
4458                         /* write-high */
4459                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4460
4461         }
4462 }
4463
4464 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4465                                                 u32 msr, int type)
4466 {
4467         int f = sizeof(unsigned long);
4468
4469         if (!cpu_has_vmx_msr_bitmap())
4470                 return;
4471
4472         /*
4473          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4474          * have the write-low and read-high bitmap offsets the wrong way round.
4475          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4476          */
4477         if (msr <= 0x1fff) {
4478                 if (type & MSR_TYPE_R)
4479                         /* read-low */
4480                         __set_bit(msr, msr_bitmap + 0x000 / f);
4481
4482                 if (type & MSR_TYPE_W)
4483                         /* write-low */
4484                         __set_bit(msr, msr_bitmap + 0x800 / f);
4485
4486         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4487                 msr &= 0x1fff;
4488                 if (type & MSR_TYPE_R)
4489                         /* read-high */
4490                         __set_bit(msr, msr_bitmap + 0x400 / f);
4491
4492                 if (type & MSR_TYPE_W)
4493                         /* write-high */
4494                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4495
4496         }
4497 }
4498
4499 /*
4500  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4501  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4502  */
4503 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4504                                                unsigned long *msr_bitmap_nested,
4505                                                u32 msr, int type)
4506 {
4507         int f = sizeof(unsigned long);
4508
4509         if (!cpu_has_vmx_msr_bitmap()) {
4510                 WARN_ON(1);
4511                 return;
4512         }
4513
4514         /*
4515          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4516          * have the write-low and read-high bitmap offsets the wrong way round.
4517          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4518          */
4519         if (msr <= 0x1fff) {
4520                 if (type & MSR_TYPE_R &&
4521                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4522                         /* read-low */
4523                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4524
4525                 if (type & MSR_TYPE_W &&
4526                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4527                         /* write-low */
4528                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4529
4530         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4531                 msr &= 0x1fff;
4532                 if (type & MSR_TYPE_R &&
4533                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4534                         /* read-high */
4535                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4536
4537                 if (type & MSR_TYPE_W &&
4538                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4539                         /* write-high */
4540                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4541
4542         }
4543 }
4544
4545 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4546 {
4547         if (!longmode_only)
4548                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4549                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4550         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4551                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4552 }
4553
4554 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4555 {
4556         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4557                         msr, MSR_TYPE_R);
4558         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4559                         msr, MSR_TYPE_R);
4560 }
4561
4562 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4563 {
4564         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4565                         msr, MSR_TYPE_R);
4566         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4567                         msr, MSR_TYPE_R);
4568 }
4569
4570 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4571 {
4572         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4573                         msr, MSR_TYPE_W);
4574         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4575                         msr, MSR_TYPE_W);
4576 }
4577
4578 static bool vmx_get_enable_apicv(void)
4579 {
4580         return enable_apicv;
4581 }
4582
4583 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4584 {
4585         struct vcpu_vmx *vmx = to_vmx(vcpu);
4586         int max_irr;
4587         void *vapic_page;
4588         u16 status;
4589
4590         if (vmx->nested.pi_desc &&
4591             vmx->nested.pi_pending) {
4592                 vmx->nested.pi_pending = false;
4593                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4594                         return 0;
4595
4596                 max_irr = find_last_bit(
4597                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4598
4599                 if (max_irr == 256)
4600                         return 0;
4601
4602                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4603                 if (!vapic_page) {
4604                         WARN_ON(1);
4605                         return -ENOMEM;
4606                 }
4607                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4608                 kunmap(vmx->nested.virtual_apic_page);
4609
4610                 status = vmcs_read16(GUEST_INTR_STATUS);
4611                 if ((u8)max_irr > ((u8)status & 0xff)) {
4612                         status &= ~0xff;
4613                         status |= (u8)max_irr;
4614                         vmcs_write16(GUEST_INTR_STATUS, status);
4615                 }
4616         }
4617         return 0;
4618 }
4619
4620 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4621 {
4622 #ifdef CONFIG_SMP
4623         if (vcpu->mode == IN_GUEST_MODE) {
4624                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4625
4626                 /*
4627                  * Currently, we don't support urgent interrupt,
4628                  * all interrupts are recognized as non-urgent
4629                  * interrupt, so we cannot post interrupts when
4630                  * 'SN' is set.
4631                  *
4632                  * If the vcpu is in guest mode, it means it is
4633                  * running instead of being scheduled out and
4634                  * waiting in the run queue, and that's the only
4635                  * case when 'SN' is set currently, warning if
4636                  * 'SN' is set.
4637                  */
4638                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4639
4640                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4641                                 POSTED_INTR_VECTOR);
4642                 return true;
4643         }
4644 #endif
4645         return false;
4646 }
4647
4648 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4649                                                 int vector)
4650 {
4651         struct vcpu_vmx *vmx = to_vmx(vcpu);
4652
4653         if (is_guest_mode(vcpu) &&
4654             vector == vmx->nested.posted_intr_nv) {
4655                 /* the PIR and ON have been set by L1. */
4656                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4657                 /*
4658                  * If a posted intr is not recognized by hardware,
4659                  * we will accomplish it in the next vmentry.
4660                  */
4661                 vmx->nested.pi_pending = true;
4662                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4663                 return 0;
4664         }
4665         return -1;
4666 }
4667 /*
4668  * Send interrupt to vcpu via posted interrupt way.
4669  * 1. If target vcpu is running(non-root mode), send posted interrupt
4670  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4671  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4672  * interrupt from PIR in next vmentry.
4673  */
4674 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4675 {
4676         struct vcpu_vmx *vmx = to_vmx(vcpu);
4677         int r;
4678
4679         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4680         if (!r)
4681                 return;
4682
4683         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4684                 return;
4685
4686         r = pi_test_and_set_on(&vmx->pi_desc);
4687         kvm_make_request(KVM_REQ_EVENT, vcpu);
4688         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4689                 kvm_vcpu_kick(vcpu);
4690 }
4691
4692 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4693 {
4694         struct vcpu_vmx *vmx = to_vmx(vcpu);
4695
4696         if (!pi_test_and_clear_on(&vmx->pi_desc))
4697                 return;
4698
4699         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4700 }
4701
4702 /*
4703  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4704  * will not change in the lifetime of the guest.
4705  * Note that host-state that does change is set elsewhere. E.g., host-state
4706  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4707  */
4708 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4709 {
4710         u32 low32, high32;
4711         unsigned long tmpl;
4712         struct desc_ptr dt;
4713         unsigned long cr4;
4714
4715         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4716         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4717
4718         /* Save the most likely value for this task's CR4 in the VMCS. */
4719         cr4 = cr4_read_shadow();
4720         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4721         vmx->host_state.vmcs_host_cr4 = cr4;
4722
4723         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4724 #ifdef CONFIG_X86_64
4725         /*
4726          * Load null selectors, so we can avoid reloading them in
4727          * __vmx_load_host_state(), in case userspace uses the null selectors
4728          * too (the expected case).
4729          */
4730         vmcs_write16(HOST_DS_SELECTOR, 0);
4731         vmcs_write16(HOST_ES_SELECTOR, 0);
4732 #else
4733         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4734         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4735 #endif
4736         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4737         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4738
4739         native_store_idt(&dt);
4740         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4741         vmx->host_idt_base = dt.address;
4742
4743         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4744
4745         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4746         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4747         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4748         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4749
4750         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4751                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4752                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4753         }
4754 }
4755
4756 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4757 {
4758         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4759         if (enable_ept)
4760                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4761         if (is_guest_mode(&vmx->vcpu))
4762                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4763                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4764         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4765 }
4766
4767 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4768 {
4769         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4770
4771         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4772                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4773         return pin_based_exec_ctrl;
4774 }
4775
4776 static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
4777 {
4778         struct vcpu_vmx *vmx = to_vmx(vcpu);
4779
4780         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4781 }
4782
4783 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4784 {
4785         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4786
4787         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4788                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4789
4790         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4791                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4792 #ifdef CONFIG_X86_64
4793                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4794                                 CPU_BASED_CR8_LOAD_EXITING;
4795 #endif
4796         }
4797         if (!enable_ept)
4798                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4799                                 CPU_BASED_CR3_LOAD_EXITING  |
4800                                 CPU_BASED_INVLPG_EXITING;
4801         return exec_control;
4802 }
4803
4804 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4805 {
4806         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4807         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4808                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4809         if (vmx->vpid == 0)
4810                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4811         if (!enable_ept) {
4812                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4813                 enable_unrestricted_guest = 0;
4814                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4815                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4816         }
4817         if (!enable_unrestricted_guest)
4818                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4819         if (!ple_gap)
4820                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4821         if (!kvm_vcpu_apicv_active(&vmx->vcpu))
4822                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4823                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4824         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4825         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4826            (handle_vmptrld).
4827            We can NOT enable shadow_vmcs here because we don't have yet
4828            a current VMCS12
4829         */
4830         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4831
4832         if (!enable_pml)
4833                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4834
4835         /* Currently, we allow L1 guest to directly run pcommit instruction. */
4836         exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4837
4838         return exec_control;
4839 }
4840
4841 static void ept_set_mmio_spte_mask(void)
4842 {
4843         /*
4844          * EPT Misconfigurations can be generated if the value of bits 2:0
4845          * of an EPT paging-structure entry is 110b (write/execute).
4846          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4847          * spte.
4848          */
4849         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4850 }
4851
4852 #define VMX_XSS_EXIT_BITMAP 0
4853 /*
4854  * Sets up the vmcs for emulated real mode.
4855  */
4856 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4857 {
4858 #ifdef CONFIG_X86_64
4859         unsigned long a;
4860 #endif
4861         int i;
4862
4863         /* I/O */
4864         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4865         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4866
4867         if (enable_shadow_vmcs) {
4868                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4869                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4870         }
4871         if (cpu_has_vmx_msr_bitmap())
4872                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4873
4874         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4875
4876         /* Control */
4877         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4878
4879         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4880
4881         if (cpu_has_secondary_exec_ctrls())
4882                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4883                                 vmx_secondary_exec_control(vmx));
4884
4885         if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
4886                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4887                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4888                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4889                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4890
4891                 vmcs_write16(GUEST_INTR_STATUS, 0);
4892
4893                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4894                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4895         }
4896
4897         if (ple_gap) {
4898                 vmcs_write32(PLE_GAP, ple_gap);
4899                 vmx->ple_window = ple_window;
4900                 vmx->ple_window_dirty = true;
4901         }
4902
4903         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4904         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4905         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4906
4907         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4908         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4909         vmx_set_constant_host_state(vmx);
4910 #ifdef CONFIG_X86_64
4911         rdmsrl(MSR_FS_BASE, a);
4912         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4913         rdmsrl(MSR_GS_BASE, a);
4914         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4915 #else
4916         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4917         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4918 #endif
4919
4920         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4921         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4922         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4923         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4924         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4925
4926         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4927                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4928
4929         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4930                 u32 index = vmx_msr_index[i];
4931                 u32 data_low, data_high;
4932                 int j = vmx->nmsrs;
4933
4934                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4935                         continue;
4936                 if (wrmsr_safe(index, data_low, data_high) < 0)
4937                         continue;
4938                 vmx->guest_msrs[j].index = i;
4939                 vmx->guest_msrs[j].data = 0;
4940                 vmx->guest_msrs[j].mask = -1ull;
4941                 ++vmx->nmsrs;
4942         }
4943
4944
4945         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4946
4947         /* 22.2.1, 20.8.1 */
4948         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4949
4950         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4951         set_cr4_guest_host_mask(vmx);
4952
4953         if (vmx_xsaves_supported())
4954                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4955
4956         return 0;
4957 }
4958
4959 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4960 {
4961         struct vcpu_vmx *vmx = to_vmx(vcpu);
4962         struct msr_data apic_base_msr;
4963         u64 cr0;
4964
4965         vmx->rmode.vm86_active = 0;
4966
4967         vmx->soft_vnmi_blocked = 0;
4968
4969         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4970         kvm_set_cr8(vcpu, 0);
4971
4972         if (!init_event) {
4973                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4974                                      MSR_IA32_APICBASE_ENABLE;
4975                 if (kvm_vcpu_is_reset_bsp(vcpu))
4976                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4977                 apic_base_msr.host_initiated = true;
4978                 kvm_set_apic_base(vcpu, &apic_base_msr);
4979         }
4980
4981         vmx_segment_cache_clear(vmx);
4982
4983         seg_setup(VCPU_SREG_CS);
4984         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4985         vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
4986
4987         seg_setup(VCPU_SREG_DS);
4988         seg_setup(VCPU_SREG_ES);
4989         seg_setup(VCPU_SREG_FS);
4990         seg_setup(VCPU_SREG_GS);
4991         seg_setup(VCPU_SREG_SS);
4992
4993         vmcs_write16(GUEST_TR_SELECTOR, 0);
4994         vmcs_writel(GUEST_TR_BASE, 0);
4995         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4996         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4997
4998         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4999         vmcs_writel(GUEST_LDTR_BASE, 0);
5000         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
5001         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
5002
5003         if (!init_event) {
5004                 vmcs_write32(GUEST_SYSENTER_CS, 0);
5005                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
5006                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
5007                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
5008         }
5009
5010         vmcs_writel(GUEST_RFLAGS, 0x02);
5011         kvm_rip_write(vcpu, 0xfff0);
5012
5013         vmcs_writel(GUEST_GDTR_BASE, 0);
5014         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
5015
5016         vmcs_writel(GUEST_IDTR_BASE, 0);
5017         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
5018
5019         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
5020         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
5021         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
5022
5023         setup_msrs(vmx);
5024
5025         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
5026
5027         if (cpu_has_vmx_tpr_shadow() && !init_event) {
5028                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
5029                 if (cpu_need_tpr_shadow(vcpu))
5030                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
5031                                      __pa(vcpu->arch.apic->regs));
5032                 vmcs_write32(TPR_THRESHOLD, 0);
5033         }
5034
5035         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
5036
5037         if (kvm_vcpu_apicv_active(vcpu))
5038                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
5039
5040         if (vmx->vpid != 0)
5041                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
5042
5043         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
5044         vmx_set_cr0(vcpu, cr0); /* enter rmode */
5045         vmx->vcpu.arch.cr0 = cr0;
5046         vmx_set_cr4(vcpu, 0);
5047         vmx_set_efer(vcpu, 0);
5048         vmx_fpu_activate(vcpu);
5049         update_exception_bitmap(vcpu);
5050
5051         vpid_sync_context(vmx->vpid);
5052 }
5053
5054 /*
5055  * In nested virtualization, check if L1 asked to exit on external interrupts.
5056  * For most existing hypervisors, this will always return true.
5057  */
5058 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
5059 {
5060         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5061                 PIN_BASED_EXT_INTR_MASK;
5062 }
5063
5064 /*
5065  * In nested virtualization, check if L1 has set
5066  * VM_EXIT_ACK_INTR_ON_EXIT
5067  */
5068 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
5069 {
5070         return get_vmcs12(vcpu)->vm_exit_controls &
5071                 VM_EXIT_ACK_INTR_ON_EXIT;
5072 }
5073
5074 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
5075 {
5076         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
5077                 PIN_BASED_NMI_EXITING;
5078 }
5079
5080 static void enable_irq_window(struct kvm_vcpu *vcpu)
5081 {
5082         u32 cpu_based_vm_exec_control;
5083
5084         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5085         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
5086         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5087 }
5088
5089 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5090 {
5091         u32 cpu_based_vm_exec_control;
5092
5093         if (!cpu_has_virtual_nmis() ||
5094             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5095                 enable_irq_window(vcpu);
5096                 return;
5097         }
5098
5099         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5100         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5101         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5102 }
5103
5104 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5105 {
5106         struct vcpu_vmx *vmx = to_vmx(vcpu);
5107         uint32_t intr;
5108         int irq = vcpu->arch.interrupt.nr;
5109
5110         trace_kvm_inj_virq(irq);
5111
5112         ++vcpu->stat.irq_injections;
5113         if (vmx->rmode.vm86_active) {
5114                 int inc_eip = 0;
5115                 if (vcpu->arch.interrupt.soft)
5116                         inc_eip = vcpu->arch.event_exit_inst_len;
5117                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5118                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5119                 return;
5120         }
5121         intr = irq | INTR_INFO_VALID_MASK;
5122         if (vcpu->arch.interrupt.soft) {
5123                 intr |= INTR_TYPE_SOFT_INTR;
5124                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5125                              vmx->vcpu.arch.event_exit_inst_len);
5126         } else
5127                 intr |= INTR_TYPE_EXT_INTR;
5128         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5129 }
5130
5131 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5132 {
5133         struct vcpu_vmx *vmx = to_vmx(vcpu);
5134
5135         if (is_guest_mode(vcpu))
5136                 return;
5137
5138         if (!cpu_has_virtual_nmis()) {
5139                 /*
5140                  * Tracking the NMI-blocked state in software is built upon
5141                  * finding the next open IRQ window. This, in turn, depends on
5142                  * well-behaving guests: They have to keep IRQs disabled at
5143                  * least as long as the NMI handler runs. Otherwise we may
5144                  * cause NMI nesting, maybe breaking the guest. But as this is
5145                  * highly unlikely, we can live with the residual risk.
5146                  */
5147                 vmx->soft_vnmi_blocked = 1;
5148                 vmx->vnmi_blocked_time = 0;
5149         }
5150
5151         ++vcpu->stat.nmi_injections;
5152         vmx->nmi_known_unmasked = false;
5153         if (vmx->rmode.vm86_active) {
5154                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5155                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5156                 return;
5157         }
5158         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5159                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5160 }
5161
5162 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5163 {
5164         if (!cpu_has_virtual_nmis())
5165                 return to_vmx(vcpu)->soft_vnmi_blocked;
5166         if (to_vmx(vcpu)->nmi_known_unmasked)
5167                 return false;
5168         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5169 }
5170
5171 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5172 {
5173         struct vcpu_vmx *vmx = to_vmx(vcpu);
5174
5175         if (!cpu_has_virtual_nmis()) {
5176                 if (vmx->soft_vnmi_blocked != masked) {
5177                         vmx->soft_vnmi_blocked = masked;
5178                         vmx->vnmi_blocked_time = 0;
5179                 }
5180         } else {
5181                 vmx->nmi_known_unmasked = !masked;
5182                 if (masked)
5183                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5184                                       GUEST_INTR_STATE_NMI);
5185                 else
5186                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5187                                         GUEST_INTR_STATE_NMI);
5188         }
5189 }
5190
5191 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5192 {
5193         if (to_vmx(vcpu)->nested.nested_run_pending)
5194                 return 0;
5195
5196         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5197                 return 0;
5198
5199         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5200                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5201                    | GUEST_INTR_STATE_NMI));
5202 }
5203
5204 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5205 {
5206         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5207                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5208                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5209                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5210 }
5211
5212 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5213 {
5214         int ret;
5215
5216         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5217                                     PAGE_SIZE * 3);
5218         if (ret)
5219                 return ret;
5220         kvm->arch.tss_addr = addr;
5221         return init_rmode_tss(kvm);
5222 }
5223
5224 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5225 {
5226         switch (vec) {
5227         case BP_VECTOR:
5228                 /*
5229                  * Update instruction length as we may reinject the exception
5230                  * from user space while in guest debugging mode.
5231                  */
5232                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5233                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5234                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5235                         return false;
5236                 /* fall through */
5237         case DB_VECTOR:
5238                 if (vcpu->guest_debug &
5239                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5240                         return false;
5241                 /* fall through */
5242         case DE_VECTOR:
5243         case OF_VECTOR:
5244         case BR_VECTOR:
5245         case UD_VECTOR:
5246         case DF_VECTOR:
5247         case SS_VECTOR:
5248         case GP_VECTOR:
5249         case MF_VECTOR:
5250                 return true;
5251         break;
5252         }
5253         return false;
5254 }
5255
5256 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5257                                   int vec, u32 err_code)
5258 {
5259         /*
5260          * Instruction with address size override prefix opcode 0x67
5261          * Cause the #SS fault with 0 error code in VM86 mode.
5262          */
5263         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5264                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5265                         if (vcpu->arch.halt_request) {
5266                                 vcpu->arch.halt_request = 0;
5267                                 return kvm_vcpu_halt(vcpu);
5268                         }
5269                         return 1;
5270                 }
5271                 return 0;
5272         }
5273
5274         /*
5275          * Forward all other exceptions that are valid in real mode.
5276          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5277          *        the required debugging infrastructure rework.
5278          */
5279         kvm_queue_exception(vcpu, vec);
5280         return 1;
5281 }
5282
5283 /*
5284  * Trigger machine check on the host. We assume all the MSRs are already set up
5285  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5286  * We pass a fake environment to the machine check handler because we want
5287  * the guest to be always treated like user space, no matter what context
5288  * it used internally.
5289  */
5290 static void kvm_machine_check(void)
5291 {
5292 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5293         struct pt_regs regs = {
5294                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5295                 .flags = X86_EFLAGS_IF,
5296         };
5297
5298         do_machine_check(&regs, 0);
5299 #endif
5300 }
5301
5302 static int handle_machine_check(struct kvm_vcpu *vcpu)
5303 {
5304         /* already handled by vcpu_run */
5305         return 1;
5306 }
5307
5308 static int handle_exception(struct kvm_vcpu *vcpu)
5309 {
5310         struct vcpu_vmx *vmx = to_vmx(vcpu);
5311         struct kvm_run *kvm_run = vcpu->run;
5312         u32 intr_info, ex_no, error_code;
5313         unsigned long cr2, rip, dr6;
5314         u32 vect_info;
5315         enum emulation_result er;
5316
5317         vect_info = vmx->idt_vectoring_info;
5318         intr_info = vmx->exit_intr_info;
5319
5320         if (is_machine_check(intr_info))
5321                 return handle_machine_check(vcpu);
5322
5323         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5324                 return 1;  /* already handled by vmx_vcpu_run() */
5325
5326         if (is_no_device(intr_info)) {
5327                 vmx_fpu_activate(vcpu);
5328                 return 1;
5329         }
5330
5331         if (is_invalid_opcode(intr_info)) {
5332                 if (is_guest_mode(vcpu)) {
5333                         kvm_queue_exception(vcpu, UD_VECTOR);
5334                         return 1;
5335                 }
5336                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5337                 if (er != EMULATE_DONE)
5338                         kvm_queue_exception(vcpu, UD_VECTOR);
5339                 return 1;
5340         }
5341
5342         error_code = 0;
5343         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5344                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5345
5346         /*
5347          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5348          * MMIO, it is better to report an internal error.
5349          * See the comments in vmx_handle_exit.
5350          */
5351         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5352             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5353                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5354                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5355                 vcpu->run->internal.ndata = 3;
5356                 vcpu->run->internal.data[0] = vect_info;
5357                 vcpu->run->internal.data[1] = intr_info;
5358                 vcpu->run->internal.data[2] = error_code;
5359                 return 0;
5360         }
5361
5362         if (is_page_fault(intr_info)) {
5363                 /* EPT won't cause page fault directly */
5364                 BUG_ON(enable_ept);
5365                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5366                 trace_kvm_page_fault(cr2, error_code);
5367
5368                 if (kvm_event_needs_reinjection(vcpu))
5369                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5370                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5371         }
5372
5373         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5374
5375         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5376                 return handle_rmode_exception(vcpu, ex_no, error_code);
5377
5378         switch (ex_no) {
5379         case AC_VECTOR:
5380                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5381                 return 1;
5382         case DB_VECTOR:
5383                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5384                 if (!(vcpu->guest_debug &
5385                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5386                         vcpu->arch.dr6 &= ~15;
5387                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5388                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5389                                 skip_emulated_instruction(vcpu);
5390
5391                         kvm_queue_exception(vcpu, DB_VECTOR);
5392                         return 1;
5393                 }
5394                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5395                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5396                 /* fall through */
5397         case BP_VECTOR:
5398                 /*
5399                  * Update instruction length as we may reinject #BP from
5400                  * user space while in guest debugging mode. Reading it for
5401                  * #DB as well causes no harm, it is not used in that case.
5402                  */
5403                 vmx->vcpu.arch.event_exit_inst_len =
5404                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5405                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5406                 rip = kvm_rip_read(vcpu);
5407                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5408                 kvm_run->debug.arch.exception = ex_no;
5409                 break;
5410         default:
5411                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5412                 kvm_run->ex.exception = ex_no;
5413                 kvm_run->ex.error_code = error_code;
5414                 break;
5415         }
5416         return 0;
5417 }
5418
5419 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5420 {
5421         ++vcpu->stat.irq_exits;
5422         return 1;
5423 }
5424
5425 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5426 {
5427         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5428         return 0;
5429 }
5430
5431 static int handle_io(struct kvm_vcpu *vcpu)
5432 {
5433         unsigned long exit_qualification;
5434         int size, in, string;
5435         unsigned port;
5436
5437         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5438         string = (exit_qualification & 16) != 0;
5439         in = (exit_qualification & 8) != 0;
5440
5441         ++vcpu->stat.io_exits;
5442
5443         if (string || in)
5444                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5445
5446         port = exit_qualification >> 16;
5447         size = (exit_qualification & 7) + 1;
5448         skip_emulated_instruction(vcpu);
5449
5450         return kvm_fast_pio_out(vcpu, size, port);
5451 }
5452
5453 static void
5454 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5455 {
5456         /*
5457          * Patch in the VMCALL instruction:
5458          */
5459         hypercall[0] = 0x0f;
5460         hypercall[1] = 0x01;
5461         hypercall[2] = 0xc1;
5462 }
5463
5464 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5465 {
5466         unsigned long always_on = VMXON_CR0_ALWAYSON;
5467         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5468
5469         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5470                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5471             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5472                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5473         return (val & always_on) == always_on;
5474 }
5475
5476 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5477 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5478 {
5479         if (is_guest_mode(vcpu)) {
5480                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5481                 unsigned long orig_val = val;
5482
5483                 /*
5484                  * We get here when L2 changed cr0 in a way that did not change
5485                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5486                  * but did change L0 shadowed bits. So we first calculate the
5487                  * effective cr0 value that L1 would like to write into the
5488                  * hardware. It consists of the L2-owned bits from the new
5489                  * value combined with the L1-owned bits from L1's guest_cr0.
5490                  */
5491                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5492                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5493
5494                 if (!nested_cr0_valid(vcpu, val))
5495                         return 1;
5496
5497                 if (kvm_set_cr0(vcpu, val))
5498                         return 1;
5499                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5500                 return 0;
5501         } else {
5502                 if (to_vmx(vcpu)->nested.vmxon &&
5503                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5504                         return 1;
5505                 return kvm_set_cr0(vcpu, val);
5506         }
5507 }
5508
5509 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5510 {
5511         if (is_guest_mode(vcpu)) {
5512                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5513                 unsigned long orig_val = val;
5514
5515                 /* analogously to handle_set_cr0 */
5516                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5517                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5518                 if (kvm_set_cr4(vcpu, val))
5519                         return 1;
5520                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5521                 return 0;
5522         } else
5523                 return kvm_set_cr4(vcpu, val);
5524 }
5525
5526 /* called to set cr0 as approriate for clts instruction exit. */
5527 static void handle_clts(struct kvm_vcpu *vcpu)
5528 {
5529         if (is_guest_mode(vcpu)) {
5530                 /*
5531                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5532                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5533                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5534                  */
5535                 vmcs_writel(CR0_READ_SHADOW,
5536                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5537                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5538         } else
5539                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5540 }
5541
5542 static int handle_cr(struct kvm_vcpu *vcpu)
5543 {
5544         unsigned long exit_qualification, val;
5545         int cr;
5546         int reg;
5547         int err;
5548
5549         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5550         cr = exit_qualification & 15;
5551         reg = (exit_qualification >> 8) & 15;
5552         switch ((exit_qualification >> 4) & 3) {
5553         case 0: /* mov to cr */
5554                 val = kvm_register_readl(vcpu, reg);
5555                 trace_kvm_cr_write(cr, val);
5556                 switch (cr) {
5557                 case 0:
5558                         err = handle_set_cr0(vcpu, val);
5559                         kvm_complete_insn_gp(vcpu, err);
5560                         return 1;
5561                 case 3:
5562                         err = kvm_set_cr3(vcpu, val);
5563                         kvm_complete_insn_gp(vcpu, err);
5564                         return 1;
5565                 case 4:
5566                         err = handle_set_cr4(vcpu, val);
5567                         kvm_complete_insn_gp(vcpu, err);
5568                         return 1;
5569                 case 8: {
5570                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5571                                 u8 cr8 = (u8)val;
5572                                 err = kvm_set_cr8(vcpu, cr8);
5573                                 kvm_complete_insn_gp(vcpu, err);
5574                                 if (lapic_in_kernel(vcpu))
5575                                         return 1;
5576                                 if (cr8_prev <= cr8)
5577                                         return 1;
5578                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5579                                 return 0;
5580                         }
5581                 }
5582                 break;
5583         case 2: /* clts */
5584                 handle_clts(vcpu);
5585                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5586                 skip_emulated_instruction(vcpu);
5587                 vmx_fpu_activate(vcpu);
5588                 return 1;
5589         case 1: /*mov from cr*/
5590                 switch (cr) {
5591                 case 3:
5592                         val = kvm_read_cr3(vcpu);
5593                         kvm_register_write(vcpu, reg, val);
5594                         trace_kvm_cr_read(cr, val);
5595                         skip_emulated_instruction(vcpu);
5596                         return 1;
5597                 case 8:
5598                         val = kvm_get_cr8(vcpu);
5599                         kvm_register_write(vcpu, reg, val);
5600                         trace_kvm_cr_read(cr, val);
5601                         skip_emulated_instruction(vcpu);
5602                         return 1;
5603                 }
5604                 break;
5605         case 3: /* lmsw */
5606                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5607                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5608                 kvm_lmsw(vcpu, val);
5609
5610                 skip_emulated_instruction(vcpu);
5611                 return 1;
5612         default:
5613                 break;
5614         }
5615         vcpu->run->exit_reason = 0;
5616         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5617                (int)(exit_qualification >> 4) & 3, cr);
5618         return 0;
5619 }
5620
5621 static int handle_dr(struct kvm_vcpu *vcpu)
5622 {
5623         unsigned long exit_qualification;
5624         int dr, dr7, reg;
5625
5626         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5627         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5628
5629         /* First, if DR does not exist, trigger UD */
5630         if (!kvm_require_dr(vcpu, dr))
5631                 return 1;
5632
5633         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5634         if (!kvm_require_cpl(vcpu, 0))
5635                 return 1;
5636         dr7 = vmcs_readl(GUEST_DR7);
5637         if (dr7 & DR7_GD) {
5638                 /*
5639                  * As the vm-exit takes precedence over the debug trap, we
5640                  * need to emulate the latter, either for the host or the
5641                  * guest debugging itself.
5642                  */
5643                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5644                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5645                         vcpu->run->debug.arch.dr7 = dr7;
5646                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5647                         vcpu->run->debug.arch.exception = DB_VECTOR;
5648                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5649                         return 0;
5650                 } else {
5651                         vcpu->arch.dr6 &= ~15;
5652                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5653                         kvm_queue_exception(vcpu, DB_VECTOR);
5654                         return 1;
5655                 }
5656         }
5657
5658         if (vcpu->guest_debug == 0) {
5659                 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
5660                                 CPU_BASED_MOV_DR_EXITING);
5661
5662                 /*
5663                  * No more DR vmexits; force a reload of the debug registers
5664                  * and reenter on this instruction.  The next vmexit will
5665                  * retrieve the full state of the debug registers.
5666                  */
5667                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5668                 return 1;
5669         }
5670
5671         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5672         if (exit_qualification & TYPE_MOV_FROM_DR) {
5673                 unsigned long val;
5674
5675                 if (kvm_get_dr(vcpu, dr, &val))
5676                         return 1;
5677                 kvm_register_write(vcpu, reg, val);
5678         } else
5679                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5680                         return 1;
5681
5682         skip_emulated_instruction(vcpu);
5683         return 1;
5684 }
5685
5686 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5687 {
5688         return vcpu->arch.dr6;
5689 }
5690
5691 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5692 {
5693 }
5694
5695 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5696 {
5697         get_debugreg(vcpu->arch.db[0], 0);
5698         get_debugreg(vcpu->arch.db[1], 1);
5699         get_debugreg(vcpu->arch.db[2], 2);
5700         get_debugreg(vcpu->arch.db[3], 3);
5701         get_debugreg(vcpu->arch.dr6, 6);
5702         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5703
5704         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5705         vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
5706 }
5707
5708 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5709 {
5710         vmcs_writel(GUEST_DR7, val);
5711 }
5712
5713 static int handle_cpuid(struct kvm_vcpu *vcpu)
5714 {
5715         kvm_emulate_cpuid(vcpu);
5716         return 1;
5717 }
5718
5719 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5720 {
5721         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5722         struct msr_data msr_info;
5723
5724         msr_info.index = ecx;
5725         msr_info.host_initiated = false;
5726         if (vmx_get_msr(vcpu, &msr_info)) {
5727                 trace_kvm_msr_read_ex(ecx);
5728                 kvm_inject_gp(vcpu, 0);
5729                 return 1;
5730         }
5731
5732         trace_kvm_msr_read(ecx, msr_info.data);
5733
5734         /* FIXME: handling of bits 32:63 of rax, rdx */
5735         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5736         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5737         skip_emulated_instruction(vcpu);
5738         return 1;
5739 }
5740
5741 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5742 {
5743         struct msr_data msr;
5744         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5745         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5746                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5747
5748         msr.data = data;
5749         msr.index = ecx;
5750         msr.host_initiated = false;
5751         if (kvm_set_msr(vcpu, &msr) != 0) {
5752                 trace_kvm_msr_write_ex(ecx, data);
5753                 kvm_inject_gp(vcpu, 0);
5754                 return 1;
5755         }
5756
5757         trace_kvm_msr_write(ecx, data);
5758         skip_emulated_instruction(vcpu);
5759         return 1;
5760 }
5761
5762 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5763 {
5764         kvm_make_request(KVM_REQ_EVENT, vcpu);
5765         return 1;
5766 }
5767
5768 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5769 {
5770         u32 cpu_based_vm_exec_control;
5771
5772         /* clear pending irq */
5773         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5774         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5775         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5776
5777         kvm_make_request(KVM_REQ_EVENT, vcpu);
5778
5779         ++vcpu->stat.irq_window_exits;
5780         return 1;
5781 }
5782
5783 static int handle_halt(struct kvm_vcpu *vcpu)
5784 {
5785         return kvm_emulate_halt(vcpu);
5786 }
5787
5788 static int handle_vmcall(struct kvm_vcpu *vcpu)
5789 {
5790         return kvm_emulate_hypercall(vcpu);
5791 }
5792
5793 static int handle_invd(struct kvm_vcpu *vcpu)
5794 {
5795         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5796 }
5797
5798 static int handle_invlpg(struct kvm_vcpu *vcpu)
5799 {
5800         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5801
5802         kvm_mmu_invlpg(vcpu, exit_qualification);
5803         skip_emulated_instruction(vcpu);
5804         return 1;
5805 }
5806
5807 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5808 {
5809         int err;
5810
5811         err = kvm_rdpmc(vcpu);
5812         kvm_complete_insn_gp(vcpu, err);
5813
5814         return 1;
5815 }
5816
5817 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5818 {
5819         kvm_emulate_wbinvd(vcpu);
5820         return 1;
5821 }
5822
5823 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5824 {
5825         u64 new_bv = kvm_read_edx_eax(vcpu);
5826         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5827
5828         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5829                 skip_emulated_instruction(vcpu);
5830         return 1;
5831 }
5832
5833 static int handle_xsaves(struct kvm_vcpu *vcpu)
5834 {
5835         skip_emulated_instruction(vcpu);
5836         WARN(1, "this should never happen\n");
5837         return 1;
5838 }
5839
5840 static int handle_xrstors(struct kvm_vcpu *vcpu)
5841 {
5842         skip_emulated_instruction(vcpu);
5843         WARN(1, "this should never happen\n");
5844         return 1;
5845 }
5846
5847 static int handle_apic_access(struct kvm_vcpu *vcpu)
5848 {
5849         if (likely(fasteoi)) {
5850                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5851                 int access_type, offset;
5852
5853                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5854                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5855                 /*
5856                  * Sane guest uses MOV to write EOI, with written value
5857                  * not cared. So make a short-circuit here by avoiding
5858                  * heavy instruction emulation.
5859                  */
5860                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5861                     (offset == APIC_EOI)) {
5862                         kvm_lapic_set_eoi(vcpu);
5863                         skip_emulated_instruction(vcpu);
5864                         return 1;
5865                 }
5866         }
5867         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5868 }
5869
5870 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5871 {
5872         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5873         int vector = exit_qualification & 0xff;
5874
5875         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5876         kvm_apic_set_eoi_accelerated(vcpu, vector);
5877         return 1;
5878 }
5879
5880 static int handle_apic_write(struct kvm_vcpu *vcpu)
5881 {
5882         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5883         u32 offset = exit_qualification & 0xfff;
5884
5885         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5886         kvm_apic_write_nodecode(vcpu, offset);
5887         return 1;
5888 }
5889
5890 static int handle_task_switch(struct kvm_vcpu *vcpu)
5891 {
5892         struct vcpu_vmx *vmx = to_vmx(vcpu);
5893         unsigned long exit_qualification;
5894         bool has_error_code = false;
5895         u32 error_code = 0;
5896         u16 tss_selector;
5897         int reason, type, idt_v, idt_index;
5898
5899         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5900         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5901         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5902
5903         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5904
5905         reason = (u32)exit_qualification >> 30;
5906         if (reason == TASK_SWITCH_GATE && idt_v) {
5907                 switch (type) {
5908                 case INTR_TYPE_NMI_INTR:
5909                         vcpu->arch.nmi_injected = false;
5910                         vmx_set_nmi_mask(vcpu, true);
5911                         break;
5912                 case INTR_TYPE_EXT_INTR:
5913                 case INTR_TYPE_SOFT_INTR:
5914                         kvm_clear_interrupt_queue(vcpu);
5915                         break;
5916                 case INTR_TYPE_HARD_EXCEPTION:
5917                         if (vmx->idt_vectoring_info &
5918                             VECTORING_INFO_DELIVER_CODE_MASK) {
5919                                 has_error_code = true;
5920                                 error_code =
5921                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5922                         }
5923                         /* fall through */
5924                 case INTR_TYPE_SOFT_EXCEPTION:
5925                         kvm_clear_exception_queue(vcpu);
5926                         break;
5927                 default:
5928                         break;
5929                 }
5930         }
5931         tss_selector = exit_qualification;
5932
5933         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5934                        type != INTR_TYPE_EXT_INTR &&
5935                        type != INTR_TYPE_NMI_INTR))
5936                 skip_emulated_instruction(vcpu);
5937
5938         if (kvm_task_switch(vcpu, tss_selector,
5939                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5940                             has_error_code, error_code) == EMULATE_FAIL) {
5941                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5942                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5943                 vcpu->run->internal.ndata = 0;
5944                 return 0;
5945         }
5946
5947         /*
5948          * TODO: What about debug traps on tss switch?
5949          *       Are we supposed to inject them and update dr6?
5950          */
5951
5952         return 1;
5953 }
5954
5955 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5956 {
5957         unsigned long exit_qualification;
5958         gpa_t gpa;
5959         u32 error_code;
5960         int gla_validity;
5961
5962         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5963
5964         gla_validity = (exit_qualification >> 7) & 0x3;
5965         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5966                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5967                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5968                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5969                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5970                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5971                         (long unsigned int)exit_qualification);
5972                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5973                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5974                 return 0;
5975         }
5976
5977         /*
5978          * EPT violation happened while executing iret from NMI,
5979          * "blocked by NMI" bit has to be set before next VM entry.
5980          * There are errata that may cause this bit to not be set:
5981          * AAK134, BY25.
5982          */
5983         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5984                         cpu_has_virtual_nmis() &&
5985                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5986                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5987
5988         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5989         trace_kvm_page_fault(gpa, exit_qualification);
5990
5991         /* It is a write fault? */
5992         error_code = exit_qualification & PFERR_WRITE_MASK;
5993         /* It is a fetch fault? */
5994         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5995         /* ept page table is present? */
5996         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5997
5998         vcpu->arch.exit_qualification = exit_qualification;
5999
6000         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
6001 }
6002
6003 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
6004 {
6005         int ret;
6006         gpa_t gpa;
6007
6008         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
6009         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
6010                 skip_emulated_instruction(vcpu);
6011                 trace_kvm_fast_mmio(gpa);
6012                 return 1;
6013         }
6014
6015         ret = handle_mmio_page_fault(vcpu, gpa, true);
6016         if (likely(ret == RET_MMIO_PF_EMULATE))
6017                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
6018                                               EMULATE_DONE;
6019
6020         if (unlikely(ret == RET_MMIO_PF_INVALID))
6021                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
6022
6023         if (unlikely(ret == RET_MMIO_PF_RETRY))
6024                 return 1;
6025
6026         /* It is the real ept misconfig */
6027         WARN_ON(1);
6028
6029         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
6030         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
6031
6032         return 0;
6033 }
6034
6035 static int handle_nmi_window(struct kvm_vcpu *vcpu)
6036 {
6037         u32 cpu_based_vm_exec_control;
6038
6039         /* clear pending NMI */
6040         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6041         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6042         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
6043         ++vcpu->stat.nmi_window_exits;
6044         kvm_make_request(KVM_REQ_EVENT, vcpu);
6045
6046         return 1;
6047 }
6048
6049 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
6050 {
6051         struct vcpu_vmx *vmx = to_vmx(vcpu);
6052         enum emulation_result err = EMULATE_DONE;
6053         int ret = 1;
6054         u32 cpu_exec_ctrl;
6055         bool intr_window_requested;
6056         unsigned count = 130;
6057
6058         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
6059         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
6060
6061         while (vmx->emulation_required && count-- != 0) {
6062                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
6063                         return handle_interrupt_window(&vmx->vcpu);
6064
6065                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
6066                         return 1;
6067
6068                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
6069
6070                 if (err == EMULATE_USER_EXIT) {
6071                         ++vcpu->stat.mmio_exits;
6072                         ret = 0;
6073                         goto out;
6074                 }
6075
6076                 if (err != EMULATE_DONE) {
6077                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6078                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6079                         vcpu->run->internal.ndata = 0;
6080                         return 0;
6081                 }
6082
6083                 if (vcpu->arch.halt_request) {
6084                         vcpu->arch.halt_request = 0;
6085                         ret = kvm_vcpu_halt(vcpu);
6086                         goto out;
6087                 }
6088
6089                 if (signal_pending(current))
6090                         goto out;
6091                 if (need_resched())
6092                         schedule();
6093         }
6094
6095 out:
6096         return ret;
6097 }
6098
6099 static int __grow_ple_window(int val)
6100 {
6101         if (ple_window_grow < 1)
6102                 return ple_window;
6103
6104         val = min(val, ple_window_actual_max);
6105
6106         if (ple_window_grow < ple_window)
6107                 val *= ple_window_grow;
6108         else
6109                 val += ple_window_grow;
6110
6111         return val;
6112 }
6113
6114 static int __shrink_ple_window(int val, int modifier, int minimum)
6115 {
6116         if (modifier < 1)
6117                 return ple_window;
6118
6119         if (modifier < ple_window)
6120                 val /= modifier;
6121         else
6122                 val -= modifier;
6123
6124         return max(val, minimum);
6125 }
6126
6127 static void grow_ple_window(struct kvm_vcpu *vcpu)
6128 {
6129         struct vcpu_vmx *vmx = to_vmx(vcpu);
6130         int old = vmx->ple_window;
6131
6132         vmx->ple_window = __grow_ple_window(old);
6133
6134         if (vmx->ple_window != old)
6135                 vmx->ple_window_dirty = true;
6136
6137         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6138 }
6139
6140 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6141 {
6142         struct vcpu_vmx *vmx = to_vmx(vcpu);
6143         int old = vmx->ple_window;
6144
6145         vmx->ple_window = __shrink_ple_window(old,
6146                                               ple_window_shrink, ple_window);
6147
6148         if (vmx->ple_window != old)
6149                 vmx->ple_window_dirty = true;
6150
6151         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6152 }
6153
6154 /*
6155  * ple_window_actual_max is computed to be one grow_ple_window() below
6156  * ple_window_max. (See __grow_ple_window for the reason.)
6157  * This prevents overflows, because ple_window_max is int.
6158  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6159  * this process.
6160  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6161  */
6162 static void update_ple_window_actual_max(void)
6163 {
6164         ple_window_actual_max =
6165                         __shrink_ple_window(max(ple_window_max, ple_window),
6166                                             ple_window_grow, INT_MIN);
6167 }
6168
6169 /*
6170  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6171  */
6172 static void wakeup_handler(void)
6173 {
6174         struct kvm_vcpu *vcpu;
6175         int cpu = smp_processor_id();
6176
6177         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6178         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6179                         blocked_vcpu_list) {
6180                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6181
6182                 if (pi_test_on(pi_desc) == 1)
6183                         kvm_vcpu_kick(vcpu);
6184         }
6185         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6186 }
6187
6188 static __init int hardware_setup(void)
6189 {
6190         int r = -ENOMEM, i, msr;
6191
6192         rdmsrl_safe(MSR_EFER, &host_efer);
6193
6194         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6195                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6196
6197         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6198         if (!vmx_io_bitmap_a)
6199                 return r;
6200
6201         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6202         if (!vmx_io_bitmap_b)
6203                 goto out;
6204
6205         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6206         if (!vmx_msr_bitmap_legacy)
6207                 goto out1;
6208
6209         vmx_msr_bitmap_legacy_x2apic =
6210                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6211         if (!vmx_msr_bitmap_legacy_x2apic)
6212                 goto out2;
6213
6214         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6215         if (!vmx_msr_bitmap_longmode)
6216                 goto out3;
6217
6218         vmx_msr_bitmap_longmode_x2apic =
6219                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6220         if (!vmx_msr_bitmap_longmode_x2apic)
6221                 goto out4;
6222
6223         if (nested) {
6224                 vmx_msr_bitmap_nested =
6225                         (unsigned long *)__get_free_page(GFP_KERNEL);
6226                 if (!vmx_msr_bitmap_nested)
6227                         goto out5;
6228         }
6229
6230         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6231         if (!vmx_vmread_bitmap)
6232                 goto out6;
6233
6234         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6235         if (!vmx_vmwrite_bitmap)
6236                 goto out7;
6237
6238         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6239         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6240
6241         /*
6242          * Allow direct access to the PC debug port (it is often used for I/O
6243          * delays, but the vmexits simply slow things down).
6244          */
6245         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6246         clear_bit(0x80, vmx_io_bitmap_a);
6247
6248         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6249
6250         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6251         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6252         if (nested)
6253                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6254
6255         if (setup_vmcs_config(&vmcs_config) < 0) {
6256                 r = -EIO;
6257                 goto out8;
6258         }
6259
6260         if (boot_cpu_has(X86_FEATURE_NX))
6261                 kvm_enable_efer_bits(EFER_NX);
6262
6263         if (!cpu_has_vmx_vpid())
6264                 enable_vpid = 0;
6265         if (!cpu_has_vmx_shadow_vmcs())
6266                 enable_shadow_vmcs = 0;
6267         if (enable_shadow_vmcs)
6268                 init_vmcs_shadow_fields();
6269
6270         if (!cpu_has_vmx_ept() ||
6271             !cpu_has_vmx_ept_4levels()) {
6272                 enable_ept = 0;
6273                 enable_unrestricted_guest = 0;
6274                 enable_ept_ad_bits = 0;
6275         }
6276
6277         if (!cpu_has_vmx_ept_ad_bits())
6278                 enable_ept_ad_bits = 0;
6279
6280         if (!cpu_has_vmx_unrestricted_guest())
6281                 enable_unrestricted_guest = 0;
6282
6283         if (!cpu_has_vmx_flexpriority())
6284                 flexpriority_enabled = 0;
6285
6286         /*
6287          * set_apic_access_page_addr() is used to reload apic access
6288          * page upon invalidation.  No need to do anything if not
6289          * using the APIC_ACCESS_ADDR VMCS field.
6290          */
6291         if (!flexpriority_enabled)
6292                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6293
6294         if (!cpu_has_vmx_tpr_shadow())
6295                 kvm_x86_ops->update_cr8_intercept = NULL;
6296
6297         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6298                 kvm_disable_largepages();
6299
6300         if (!cpu_has_vmx_ple())
6301                 ple_gap = 0;
6302
6303         if (!cpu_has_vmx_apicv())
6304                 enable_apicv = 0;
6305
6306         if (cpu_has_vmx_tsc_scaling()) {
6307                 kvm_has_tsc_control = true;
6308                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6309                 kvm_tsc_scaling_ratio_frac_bits = 48;
6310         }
6311
6312         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6313         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6314         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6315         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6316         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6317         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6318         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6319
6320         memcpy(vmx_msr_bitmap_legacy_x2apic,
6321                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6322         memcpy(vmx_msr_bitmap_longmode_x2apic,
6323                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6324
6325         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6326
6327         if (enable_apicv) {
6328                 for (msr = 0x800; msr <= 0x8ff; msr++)
6329                         vmx_disable_intercept_msr_read_x2apic(msr);
6330
6331                 /* According SDM, in x2apic mode, the whole id reg is used.
6332                  * But in KVM, it only use the highest eight bits. Need to
6333                  * intercept it */
6334                 vmx_enable_intercept_msr_read_x2apic(0x802);
6335                 /* TMCCT */
6336                 vmx_enable_intercept_msr_read_x2apic(0x839);
6337                 /* TPR */
6338                 vmx_disable_intercept_msr_write_x2apic(0x808);
6339                 /* EOI */
6340                 vmx_disable_intercept_msr_write_x2apic(0x80b);
6341                 /* SELF-IPI */
6342                 vmx_disable_intercept_msr_write_x2apic(0x83f);
6343         }
6344
6345         if (enable_ept) {
6346                 kvm_mmu_set_mask_ptes(0ull,
6347                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6348                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6349                         0ull, VMX_EPT_EXECUTABLE_MASK);
6350                 ept_set_mmio_spte_mask();
6351                 kvm_enable_tdp();
6352         } else
6353                 kvm_disable_tdp();
6354
6355         update_ple_window_actual_max();
6356
6357         /*
6358          * Only enable PML when hardware supports PML feature, and both EPT
6359          * and EPT A/D bit features are enabled -- PML depends on them to work.
6360          */
6361         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6362                 enable_pml = 0;
6363
6364         if (!enable_pml) {
6365                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6366                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6367                 kvm_x86_ops->flush_log_dirty = NULL;
6368                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6369         }
6370
6371         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6372
6373         return alloc_kvm_area();
6374
6375 out8:
6376         free_page((unsigned long)vmx_vmwrite_bitmap);
6377 out7:
6378         free_page((unsigned long)vmx_vmread_bitmap);
6379 out6:
6380         if (nested)
6381                 free_page((unsigned long)vmx_msr_bitmap_nested);
6382 out5:
6383         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6384 out4:
6385         free_page((unsigned long)vmx_msr_bitmap_longmode);
6386 out3:
6387         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6388 out2:
6389         free_page((unsigned long)vmx_msr_bitmap_legacy);
6390 out1:
6391         free_page((unsigned long)vmx_io_bitmap_b);
6392 out:
6393         free_page((unsigned long)vmx_io_bitmap_a);
6394
6395     return r;
6396 }
6397
6398 static __exit void hardware_unsetup(void)
6399 {
6400         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6401         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6402         free_page((unsigned long)vmx_msr_bitmap_legacy);
6403         free_page((unsigned long)vmx_msr_bitmap_longmode);
6404         free_page((unsigned long)vmx_io_bitmap_b);
6405         free_page((unsigned long)vmx_io_bitmap_a);
6406         free_page((unsigned long)vmx_vmwrite_bitmap);
6407         free_page((unsigned long)vmx_vmread_bitmap);
6408         if (nested)
6409                 free_page((unsigned long)vmx_msr_bitmap_nested);
6410
6411         free_kvm_area();
6412 }
6413
6414 /*
6415  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6416  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6417  */
6418 static int handle_pause(struct kvm_vcpu *vcpu)
6419 {
6420         if (ple_gap)
6421                 grow_ple_window(vcpu);
6422
6423         skip_emulated_instruction(vcpu);
6424         kvm_vcpu_on_spin(vcpu);
6425
6426         return 1;
6427 }
6428
6429 static int handle_nop(struct kvm_vcpu *vcpu)
6430 {
6431         skip_emulated_instruction(vcpu);
6432         return 1;
6433 }
6434
6435 static int handle_mwait(struct kvm_vcpu *vcpu)
6436 {
6437         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6438         return handle_nop(vcpu);
6439 }
6440
6441 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6442 {
6443         return 1;
6444 }
6445
6446 static int handle_monitor(struct kvm_vcpu *vcpu)
6447 {
6448         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6449         return handle_nop(vcpu);
6450 }
6451
6452 /*
6453  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6454  * We could reuse a single VMCS for all the L2 guests, but we also want the
6455  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6456  * allows keeping them loaded on the processor, and in the future will allow
6457  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6458  * every entry if they never change.
6459  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6460  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6461  *
6462  * The following functions allocate and free a vmcs02 in this pool.
6463  */
6464
6465 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6466 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6467 {
6468         struct vmcs02_list *item;
6469         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6470                 if (item->vmptr == vmx->nested.current_vmptr) {
6471                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6472                         return &item->vmcs02;
6473                 }
6474
6475         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6476                 /* Recycle the least recently used VMCS. */
6477                 item = list_last_entry(&vmx->nested.vmcs02_pool,
6478                                        struct vmcs02_list, list);
6479                 item->vmptr = vmx->nested.current_vmptr;
6480                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6481                 return &item->vmcs02;
6482         }
6483
6484         /* Create a new VMCS */
6485         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6486         if (!item)
6487                 return NULL;
6488         item->vmcs02.vmcs = alloc_vmcs();
6489         if (!item->vmcs02.vmcs) {
6490                 kfree(item);
6491                 return NULL;
6492         }
6493         loaded_vmcs_init(&item->vmcs02);
6494         item->vmptr = vmx->nested.current_vmptr;
6495         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6496         vmx->nested.vmcs02_num++;
6497         return &item->vmcs02;
6498 }
6499
6500 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6501 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6502 {
6503         struct vmcs02_list *item;
6504         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6505                 if (item->vmptr == vmptr) {
6506                         free_loaded_vmcs(&item->vmcs02);
6507                         list_del(&item->list);
6508                         kfree(item);
6509                         vmx->nested.vmcs02_num--;
6510                         return;
6511                 }
6512 }
6513
6514 /*
6515  * Free all VMCSs saved for this vcpu, except the one pointed by
6516  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6517  * must be &vmx->vmcs01.
6518  */
6519 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6520 {
6521         struct vmcs02_list *item, *n;
6522
6523         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6524         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6525                 /*
6526                  * Something will leak if the above WARN triggers.  Better than
6527                  * a use-after-free.
6528                  */
6529                 if (vmx->loaded_vmcs == &item->vmcs02)
6530                         continue;
6531
6532                 free_loaded_vmcs(&item->vmcs02);
6533                 list_del(&item->list);
6534                 kfree(item);
6535                 vmx->nested.vmcs02_num--;
6536         }
6537 }
6538
6539 /*
6540  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6541  * set the success or error code of an emulated VMX instruction, as specified
6542  * by Vol 2B, VMX Instruction Reference, "Conventions".
6543  */
6544 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6545 {
6546         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6547                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6548                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6549 }
6550
6551 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6552 {
6553         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6554                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6555                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6556                         | X86_EFLAGS_CF);
6557 }
6558
6559 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6560                                         u32 vm_instruction_error)
6561 {
6562         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6563                 /*
6564                  * failValid writes the error number to the current VMCS, which
6565                  * can't be done there isn't a current VMCS.
6566                  */
6567                 nested_vmx_failInvalid(vcpu);
6568                 return;
6569         }
6570         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6571                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6572                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6573                         | X86_EFLAGS_ZF);
6574         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6575         /*
6576          * We don't need to force a shadow sync because
6577          * VM_INSTRUCTION_ERROR is not shadowed
6578          */
6579 }
6580
6581 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6582 {
6583         /* TODO: not to reset guest simply here. */
6584         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6585         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6586 }
6587
6588 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6589 {
6590         struct vcpu_vmx *vmx =
6591                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6592
6593         vmx->nested.preemption_timer_expired = true;
6594         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6595         kvm_vcpu_kick(&vmx->vcpu);
6596
6597         return HRTIMER_NORESTART;
6598 }
6599
6600 /*
6601  * Decode the memory-address operand of a vmx instruction, as recorded on an
6602  * exit caused by such an instruction (run by a guest hypervisor).
6603  * On success, returns 0. When the operand is invalid, returns 1 and throws
6604  * #UD or #GP.
6605  */
6606 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6607                                  unsigned long exit_qualification,
6608                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6609 {
6610         gva_t off;
6611         bool exn;
6612         struct kvm_segment s;
6613
6614         /*
6615          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6616          * Execution", on an exit, vmx_instruction_info holds most of the
6617          * addressing components of the operand. Only the displacement part
6618          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6619          * For how an actual address is calculated from all these components,
6620          * refer to Vol. 1, "Operand Addressing".
6621          */
6622         int  scaling = vmx_instruction_info & 3;
6623         int  addr_size = (vmx_instruction_info >> 7) & 7;
6624         bool is_reg = vmx_instruction_info & (1u << 10);
6625         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6626         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6627         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6628         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6629         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6630
6631         if (is_reg) {
6632                 kvm_queue_exception(vcpu, UD_VECTOR);
6633                 return 1;
6634         }
6635
6636         /* Addr = segment_base + offset */
6637         /* offset = base + [index * scale] + displacement */
6638         off = exit_qualification; /* holds the displacement */
6639         if (base_is_valid)
6640                 off += kvm_register_read(vcpu, base_reg);
6641         if (index_is_valid)
6642                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6643         vmx_get_segment(vcpu, &s, seg_reg);
6644         *ret = s.base + off;
6645
6646         if (addr_size == 1) /* 32 bit */
6647                 *ret &= 0xffffffff;
6648
6649         /* Checks for #GP/#SS exceptions. */
6650         exn = false;
6651         if (is_protmode(vcpu)) {
6652                 /* Protected mode: apply checks for segment validity in the
6653                  * following order:
6654                  * - segment type check (#GP(0) may be thrown)
6655                  * - usability check (#GP(0)/#SS(0))
6656                  * - limit check (#GP(0)/#SS(0))
6657                  */
6658                 if (wr)
6659                         /* #GP(0) if the destination operand is located in a
6660                          * read-only data segment or any code segment.
6661                          */
6662                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6663                 else
6664                         /* #GP(0) if the source operand is located in an
6665                          * execute-only code segment
6666                          */
6667                         exn = ((s.type & 0xa) == 8);
6668         }
6669         if (exn) {
6670                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6671                 return 1;
6672         }
6673         if (is_long_mode(vcpu)) {
6674                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6675                  * non-canonical form. This is an only check for long mode.
6676                  */
6677                 exn = is_noncanonical_address(*ret);
6678         } else if (is_protmode(vcpu)) {
6679                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6680                  */
6681                 exn = (s.unusable != 0);
6682                 /* Protected mode: #GP(0)/#SS(0) if the memory
6683                  * operand is outside the segment limit.
6684                  */
6685                 exn = exn || (off + sizeof(u64) > s.limit);
6686         }
6687         if (exn) {
6688                 kvm_queue_exception_e(vcpu,
6689                                       seg_reg == VCPU_SREG_SS ?
6690                                                 SS_VECTOR : GP_VECTOR,
6691                                       0);
6692                 return 1;
6693         }
6694
6695         return 0;
6696 }
6697
6698 /*
6699  * This function performs the various checks including
6700  * - if it's 4KB aligned
6701  * - No bits beyond the physical address width are set
6702  * - Returns 0 on success or else 1
6703  * (Intel SDM Section 30.3)
6704  */
6705 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6706                                   gpa_t *vmpointer)
6707 {
6708         gva_t gva;
6709         gpa_t vmptr;
6710         struct x86_exception e;
6711         struct page *page;
6712         struct vcpu_vmx *vmx = to_vmx(vcpu);
6713         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6714
6715         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6716                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6717                 return 1;
6718
6719         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6720                                 sizeof(vmptr), &e)) {
6721                 kvm_inject_page_fault(vcpu, &e);
6722                 return 1;
6723         }
6724
6725         switch (exit_reason) {
6726         case EXIT_REASON_VMON:
6727                 /*
6728                  * SDM 3: 24.11.5
6729                  * The first 4 bytes of VMXON region contain the supported
6730                  * VMCS revision identifier
6731                  *
6732                  * Note - IA32_VMX_BASIC[48] will never be 1
6733                  * for the nested case;
6734                  * which replaces physical address width with 32
6735                  *
6736                  */
6737                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6738                         nested_vmx_failInvalid(vcpu);
6739                         skip_emulated_instruction(vcpu);
6740                         return 1;
6741                 }
6742
6743                 page = nested_get_page(vcpu, vmptr);
6744                 if (page == NULL ||
6745                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6746                         nested_vmx_failInvalid(vcpu);
6747                         kunmap(page);
6748                         skip_emulated_instruction(vcpu);
6749                         return 1;
6750                 }
6751                 kunmap(page);
6752                 vmx->nested.vmxon_ptr = vmptr;
6753                 break;
6754         case EXIT_REASON_VMCLEAR:
6755                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6756                         nested_vmx_failValid(vcpu,
6757                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6758                         skip_emulated_instruction(vcpu);
6759                         return 1;
6760                 }
6761
6762                 if (vmptr == vmx->nested.vmxon_ptr) {
6763                         nested_vmx_failValid(vcpu,
6764                                              VMXERR_VMCLEAR_VMXON_POINTER);
6765                         skip_emulated_instruction(vcpu);
6766                         return 1;
6767                 }
6768                 break;
6769         case EXIT_REASON_VMPTRLD:
6770                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6771                         nested_vmx_failValid(vcpu,
6772                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6773                         skip_emulated_instruction(vcpu);
6774                         return 1;
6775                 }
6776
6777                 if (vmptr == vmx->nested.vmxon_ptr) {
6778                         nested_vmx_failValid(vcpu,
6779                                              VMXERR_VMCLEAR_VMXON_POINTER);
6780                         skip_emulated_instruction(vcpu);
6781                         return 1;
6782                 }
6783                 break;
6784         default:
6785                 return 1; /* shouldn't happen */
6786         }
6787
6788         if (vmpointer)
6789                 *vmpointer = vmptr;
6790         return 0;
6791 }
6792
6793 /*
6794  * Emulate the VMXON instruction.
6795  * Currently, we just remember that VMX is active, and do not save or even
6796  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6797  * do not currently need to store anything in that guest-allocated memory
6798  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6799  * argument is different from the VMXON pointer (which the spec says they do).
6800  */
6801 static int handle_vmon(struct kvm_vcpu *vcpu)
6802 {
6803         struct kvm_segment cs;
6804         struct vcpu_vmx *vmx = to_vmx(vcpu);
6805         struct vmcs *shadow_vmcs;
6806         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6807                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6808
6809         /* The Intel VMX Instruction Reference lists a bunch of bits that
6810          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6811          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6812          * Otherwise, we should fail with #UD. We test these now:
6813          */
6814         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6815             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6816             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6817                 kvm_queue_exception(vcpu, UD_VECTOR);
6818                 return 1;
6819         }
6820
6821         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6822         if (is_long_mode(vcpu) && !cs.l) {
6823                 kvm_queue_exception(vcpu, UD_VECTOR);
6824                 return 1;
6825         }
6826
6827         if (vmx_get_cpl(vcpu)) {
6828                 kvm_inject_gp(vcpu, 0);
6829                 return 1;
6830         }
6831
6832         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6833                 return 1;
6834
6835         if (vmx->nested.vmxon) {
6836                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6837                 skip_emulated_instruction(vcpu);
6838                 return 1;
6839         }
6840
6841         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6842                         != VMXON_NEEDED_FEATURES) {
6843                 kvm_inject_gp(vcpu, 0);
6844                 return 1;
6845         }
6846
6847         if (enable_shadow_vmcs) {
6848                 shadow_vmcs = alloc_vmcs();
6849                 if (!shadow_vmcs)
6850                         return -ENOMEM;
6851                 /* mark vmcs as shadow */
6852                 shadow_vmcs->revision_id |= (1u << 31);
6853                 /* init shadow vmcs */
6854                 vmcs_clear(shadow_vmcs);
6855                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6856         }
6857
6858         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6859         vmx->nested.vmcs02_num = 0;
6860
6861         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6862                      HRTIMER_MODE_REL);
6863         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6864
6865         vmx->nested.vmxon = true;
6866
6867         skip_emulated_instruction(vcpu);
6868         nested_vmx_succeed(vcpu);
6869         return 1;
6870 }
6871
6872 /*
6873  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6874  * for running VMX instructions (except VMXON, whose prerequisites are
6875  * slightly different). It also specifies what exception to inject otherwise.
6876  */
6877 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6878 {
6879         struct kvm_segment cs;
6880         struct vcpu_vmx *vmx = to_vmx(vcpu);
6881
6882         if (!vmx->nested.vmxon) {
6883                 kvm_queue_exception(vcpu, UD_VECTOR);
6884                 return 0;
6885         }
6886
6887         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6888         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6889             (is_long_mode(vcpu) && !cs.l)) {
6890                 kvm_queue_exception(vcpu, UD_VECTOR);
6891                 return 0;
6892         }
6893
6894         if (vmx_get_cpl(vcpu)) {
6895                 kvm_inject_gp(vcpu, 0);
6896                 return 0;
6897         }
6898
6899         return 1;
6900 }
6901
6902 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6903 {
6904         if (vmx->nested.current_vmptr == -1ull)
6905                 return;
6906
6907         /* current_vmptr and current_vmcs12 are always set/reset together */
6908         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6909                 return;
6910
6911         if (enable_shadow_vmcs) {
6912                 /* copy to memory all shadowed fields in case
6913                    they were modified */
6914                 copy_shadow_to_vmcs12(vmx);
6915                 vmx->nested.sync_shadow_vmcs = false;
6916                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6917                                 SECONDARY_EXEC_SHADOW_VMCS);
6918                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6919         }
6920         vmx->nested.posted_intr_nv = -1;
6921         kunmap(vmx->nested.current_vmcs12_page);
6922         nested_release_page(vmx->nested.current_vmcs12_page);
6923         vmx->nested.current_vmptr = -1ull;
6924         vmx->nested.current_vmcs12 = NULL;
6925 }
6926
6927 /*
6928  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6929  * just stops using VMX.
6930  */
6931 static void free_nested(struct vcpu_vmx *vmx)
6932 {
6933         if (!vmx->nested.vmxon)
6934                 return;
6935
6936         vmx->nested.vmxon = false;
6937         free_vpid(vmx->nested.vpid02);
6938         nested_release_vmcs12(vmx);
6939         if (enable_shadow_vmcs)
6940                 free_vmcs(vmx->nested.current_shadow_vmcs);
6941         /* Unpin physical memory we referred to in current vmcs02 */
6942         if (vmx->nested.apic_access_page) {
6943                 nested_release_page(vmx->nested.apic_access_page);
6944                 vmx->nested.apic_access_page = NULL;
6945         }
6946         if (vmx->nested.virtual_apic_page) {
6947                 nested_release_page(vmx->nested.virtual_apic_page);
6948                 vmx->nested.virtual_apic_page = NULL;
6949         }
6950         if (vmx->nested.pi_desc_page) {
6951                 kunmap(vmx->nested.pi_desc_page);
6952                 nested_release_page(vmx->nested.pi_desc_page);
6953                 vmx->nested.pi_desc_page = NULL;
6954                 vmx->nested.pi_desc = NULL;
6955         }
6956
6957         nested_free_all_saved_vmcss(vmx);
6958 }
6959
6960 /* Emulate the VMXOFF instruction */
6961 static int handle_vmoff(struct kvm_vcpu *vcpu)
6962 {
6963         if (!nested_vmx_check_permission(vcpu))
6964                 return 1;
6965         free_nested(to_vmx(vcpu));
6966         skip_emulated_instruction(vcpu);
6967         nested_vmx_succeed(vcpu);
6968         return 1;
6969 }
6970
6971 /* Emulate the VMCLEAR instruction */
6972 static int handle_vmclear(struct kvm_vcpu *vcpu)
6973 {
6974         struct vcpu_vmx *vmx = to_vmx(vcpu);
6975         gpa_t vmptr;
6976         struct vmcs12 *vmcs12;
6977         struct page *page;
6978
6979         if (!nested_vmx_check_permission(vcpu))
6980                 return 1;
6981
6982         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6983                 return 1;
6984
6985         if (vmptr == vmx->nested.current_vmptr)
6986                 nested_release_vmcs12(vmx);
6987
6988         page = nested_get_page(vcpu, vmptr);
6989         if (page == NULL) {
6990                 /*
6991                  * For accurate processor emulation, VMCLEAR beyond available
6992                  * physical memory should do nothing at all. However, it is
6993                  * possible that a nested vmx bug, not a guest hypervisor bug,
6994                  * resulted in this case, so let's shut down before doing any
6995                  * more damage:
6996                  */
6997                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6998                 return 1;
6999         }
7000         vmcs12 = kmap(page);
7001         vmcs12->launch_state = 0;
7002         kunmap(page);
7003         nested_release_page(page);
7004
7005         nested_free_vmcs02(vmx, vmptr);
7006
7007         skip_emulated_instruction(vcpu);
7008         nested_vmx_succeed(vcpu);
7009         return 1;
7010 }
7011
7012 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
7013
7014 /* Emulate the VMLAUNCH instruction */
7015 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
7016 {
7017         return nested_vmx_run(vcpu, true);
7018 }
7019
7020 /* Emulate the VMRESUME instruction */
7021 static int handle_vmresume(struct kvm_vcpu *vcpu)
7022 {
7023
7024         return nested_vmx_run(vcpu, false);
7025 }
7026
7027 enum vmcs_field_type {
7028         VMCS_FIELD_TYPE_U16 = 0,
7029         VMCS_FIELD_TYPE_U64 = 1,
7030         VMCS_FIELD_TYPE_U32 = 2,
7031         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
7032 };
7033
7034 static inline int vmcs_field_type(unsigned long field)
7035 {
7036         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
7037                 return VMCS_FIELD_TYPE_U32;
7038         return (field >> 13) & 0x3 ;
7039 }
7040
7041 static inline int vmcs_field_readonly(unsigned long field)
7042 {
7043         return (((field >> 10) & 0x3) == 1);
7044 }
7045
7046 /*
7047  * Read a vmcs12 field. Since these can have varying lengths and we return
7048  * one type, we chose the biggest type (u64) and zero-extend the return value
7049  * to that size. Note that the caller, handle_vmread, might need to use only
7050  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
7051  * 64-bit fields are to be returned).
7052  */
7053 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
7054                                   unsigned long field, u64 *ret)
7055 {
7056         short offset = vmcs_field_to_offset(field);
7057         char *p;
7058
7059         if (offset < 0)
7060                 return offset;
7061
7062         p = ((char *)(get_vmcs12(vcpu))) + offset;
7063
7064         switch (vmcs_field_type(field)) {
7065         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7066                 *ret = *((natural_width *)p);
7067                 return 0;
7068         case VMCS_FIELD_TYPE_U16:
7069                 *ret = *((u16 *)p);
7070                 return 0;
7071         case VMCS_FIELD_TYPE_U32:
7072                 *ret = *((u32 *)p);
7073                 return 0;
7074         case VMCS_FIELD_TYPE_U64:
7075                 *ret = *((u64 *)p);
7076                 return 0;
7077         default:
7078                 WARN_ON(1);
7079                 return -ENOENT;
7080         }
7081 }
7082
7083
7084 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7085                                    unsigned long field, u64 field_value){
7086         short offset = vmcs_field_to_offset(field);
7087         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7088         if (offset < 0)
7089                 return offset;
7090
7091         switch (vmcs_field_type(field)) {
7092         case VMCS_FIELD_TYPE_U16:
7093                 *(u16 *)p = field_value;
7094                 return 0;
7095         case VMCS_FIELD_TYPE_U32:
7096                 *(u32 *)p = field_value;
7097                 return 0;
7098         case VMCS_FIELD_TYPE_U64:
7099                 *(u64 *)p = field_value;
7100                 return 0;
7101         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7102                 *(natural_width *)p = field_value;
7103                 return 0;
7104         default:
7105                 WARN_ON(1);
7106                 return -ENOENT;
7107         }
7108
7109 }
7110
7111 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7112 {
7113         int i;
7114         unsigned long field;
7115         u64 field_value;
7116         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7117         const unsigned long *fields = shadow_read_write_fields;
7118         const int num_fields = max_shadow_read_write_fields;
7119
7120         preempt_disable();
7121
7122         vmcs_load(shadow_vmcs);
7123
7124         for (i = 0; i < num_fields; i++) {
7125                 field = fields[i];
7126                 switch (vmcs_field_type(field)) {
7127                 case VMCS_FIELD_TYPE_U16:
7128                         field_value = vmcs_read16(field);
7129                         break;
7130                 case VMCS_FIELD_TYPE_U32:
7131                         field_value = vmcs_read32(field);
7132                         break;
7133                 case VMCS_FIELD_TYPE_U64:
7134                         field_value = vmcs_read64(field);
7135                         break;
7136                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7137                         field_value = vmcs_readl(field);
7138                         break;
7139                 default:
7140                         WARN_ON(1);
7141                         continue;
7142                 }
7143                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7144         }
7145
7146         vmcs_clear(shadow_vmcs);
7147         vmcs_load(vmx->loaded_vmcs->vmcs);
7148
7149         preempt_enable();
7150 }
7151
7152 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7153 {
7154         const unsigned long *fields[] = {
7155                 shadow_read_write_fields,
7156                 shadow_read_only_fields
7157         };
7158         const int max_fields[] = {
7159                 max_shadow_read_write_fields,
7160                 max_shadow_read_only_fields
7161         };
7162         int i, q;
7163         unsigned long field;
7164         u64 field_value = 0;
7165         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7166
7167         vmcs_load(shadow_vmcs);
7168
7169         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7170                 for (i = 0; i < max_fields[q]; i++) {
7171                         field = fields[q][i];
7172                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7173
7174                         switch (vmcs_field_type(field)) {
7175                         case VMCS_FIELD_TYPE_U16:
7176                                 vmcs_write16(field, (u16)field_value);
7177                                 break;
7178                         case VMCS_FIELD_TYPE_U32:
7179                                 vmcs_write32(field, (u32)field_value);
7180                                 break;
7181                         case VMCS_FIELD_TYPE_U64:
7182                                 vmcs_write64(field, (u64)field_value);
7183                                 break;
7184                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7185                                 vmcs_writel(field, (long)field_value);
7186                                 break;
7187                         default:
7188                                 WARN_ON(1);
7189                                 break;
7190                         }
7191                 }
7192         }
7193
7194         vmcs_clear(shadow_vmcs);
7195         vmcs_load(vmx->loaded_vmcs->vmcs);
7196 }
7197
7198 /*
7199  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7200  * used before) all generate the same failure when it is missing.
7201  */
7202 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7203 {
7204         struct vcpu_vmx *vmx = to_vmx(vcpu);
7205         if (vmx->nested.current_vmptr == -1ull) {
7206                 nested_vmx_failInvalid(vcpu);
7207                 skip_emulated_instruction(vcpu);
7208                 return 0;
7209         }
7210         return 1;
7211 }
7212
7213 static int handle_vmread(struct kvm_vcpu *vcpu)
7214 {
7215         unsigned long field;
7216         u64 field_value;
7217         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7218         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7219         gva_t gva = 0;
7220
7221         if (!nested_vmx_check_permission(vcpu) ||
7222             !nested_vmx_check_vmcs12(vcpu))
7223                 return 1;
7224
7225         /* Decode instruction info and find the field to read */
7226         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7227         /* Read the field, zero-extended to a u64 field_value */
7228         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7229                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7230                 skip_emulated_instruction(vcpu);
7231                 return 1;
7232         }
7233         /*
7234          * Now copy part of this value to register or memory, as requested.
7235          * Note that the number of bits actually copied is 32 or 64 depending
7236          * on the guest's mode (32 or 64 bit), not on the given field's length.
7237          */
7238         if (vmx_instruction_info & (1u << 10)) {
7239                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7240                         field_value);
7241         } else {
7242                 if (get_vmx_mem_address(vcpu, exit_qualification,
7243                                 vmx_instruction_info, true, &gva))
7244                         return 1;
7245                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7246                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7247                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7248         }
7249
7250         nested_vmx_succeed(vcpu);
7251         skip_emulated_instruction(vcpu);
7252         return 1;
7253 }
7254
7255
7256 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7257 {
7258         unsigned long field;
7259         gva_t gva;
7260         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7261         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7262         /* The value to write might be 32 or 64 bits, depending on L1's long
7263          * mode, and eventually we need to write that into a field of several
7264          * possible lengths. The code below first zero-extends the value to 64
7265          * bit (field_value), and then copies only the approriate number of
7266          * bits into the vmcs12 field.
7267          */
7268         u64 field_value = 0;
7269         struct x86_exception e;
7270
7271         if (!nested_vmx_check_permission(vcpu) ||
7272             !nested_vmx_check_vmcs12(vcpu))
7273                 return 1;
7274
7275         if (vmx_instruction_info & (1u << 10))
7276                 field_value = kvm_register_readl(vcpu,
7277                         (((vmx_instruction_info) >> 3) & 0xf));
7278         else {
7279                 if (get_vmx_mem_address(vcpu, exit_qualification,
7280                                 vmx_instruction_info, false, &gva))
7281                         return 1;
7282                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7283                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7284                         kvm_inject_page_fault(vcpu, &e);
7285                         return 1;
7286                 }
7287         }
7288
7289
7290         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7291         if (vmcs_field_readonly(field)) {
7292                 nested_vmx_failValid(vcpu,
7293                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7294                 skip_emulated_instruction(vcpu);
7295                 return 1;
7296         }
7297
7298         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7299                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7300                 skip_emulated_instruction(vcpu);
7301                 return 1;
7302         }
7303
7304         nested_vmx_succeed(vcpu);
7305         skip_emulated_instruction(vcpu);
7306         return 1;
7307 }
7308
7309 /* Emulate the VMPTRLD instruction */
7310 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7311 {
7312         struct vcpu_vmx *vmx = to_vmx(vcpu);
7313         gpa_t vmptr;
7314
7315         if (!nested_vmx_check_permission(vcpu))
7316                 return 1;
7317
7318         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7319                 return 1;
7320
7321         if (vmx->nested.current_vmptr != vmptr) {
7322                 struct vmcs12 *new_vmcs12;
7323                 struct page *page;
7324                 page = nested_get_page(vcpu, vmptr);
7325                 if (page == NULL) {
7326                         nested_vmx_failInvalid(vcpu);
7327                         skip_emulated_instruction(vcpu);
7328                         return 1;
7329                 }
7330                 new_vmcs12 = kmap(page);
7331                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7332                         kunmap(page);
7333                         nested_release_page_clean(page);
7334                         nested_vmx_failValid(vcpu,
7335                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7336                         skip_emulated_instruction(vcpu);
7337                         return 1;
7338                 }
7339
7340                 nested_release_vmcs12(vmx);
7341                 vmx->nested.current_vmptr = vmptr;
7342                 vmx->nested.current_vmcs12 = new_vmcs12;
7343                 vmx->nested.current_vmcs12_page = page;
7344                 if (enable_shadow_vmcs) {
7345                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7346                                       SECONDARY_EXEC_SHADOW_VMCS);
7347                         vmcs_write64(VMCS_LINK_POINTER,
7348                                      __pa(vmx->nested.current_shadow_vmcs));
7349                         vmx->nested.sync_shadow_vmcs = true;
7350                 }
7351         }
7352
7353         nested_vmx_succeed(vcpu);
7354         skip_emulated_instruction(vcpu);
7355         return 1;
7356 }
7357
7358 /* Emulate the VMPTRST instruction */
7359 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7360 {
7361         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7362         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7363         gva_t vmcs_gva;
7364         struct x86_exception e;
7365
7366         if (!nested_vmx_check_permission(vcpu))
7367                 return 1;
7368
7369         if (get_vmx_mem_address(vcpu, exit_qualification,
7370                         vmx_instruction_info, true, &vmcs_gva))
7371                 return 1;
7372         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7373         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7374                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7375                                  sizeof(u64), &e)) {
7376                 kvm_inject_page_fault(vcpu, &e);
7377                 return 1;
7378         }
7379         nested_vmx_succeed(vcpu);
7380         skip_emulated_instruction(vcpu);
7381         return 1;
7382 }
7383
7384 /* Emulate the INVEPT instruction */
7385 static int handle_invept(struct kvm_vcpu *vcpu)
7386 {
7387         struct vcpu_vmx *vmx = to_vmx(vcpu);
7388         u32 vmx_instruction_info, types;
7389         unsigned long type;
7390         gva_t gva;
7391         struct x86_exception e;
7392         struct {
7393                 u64 eptp, gpa;
7394         } operand;
7395
7396         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7397               SECONDARY_EXEC_ENABLE_EPT) ||
7398             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7399                 kvm_queue_exception(vcpu, UD_VECTOR);
7400                 return 1;
7401         }
7402
7403         if (!nested_vmx_check_permission(vcpu))
7404                 return 1;
7405
7406         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7407                 kvm_queue_exception(vcpu, UD_VECTOR);
7408                 return 1;
7409         }
7410
7411         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7412         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7413
7414         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7415
7416         if (!(types & (1UL << type))) {
7417                 nested_vmx_failValid(vcpu,
7418                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7419                 skip_emulated_instruction(vcpu);
7420                 return 1;
7421         }
7422
7423         /* According to the Intel VMX instruction reference, the memory
7424          * operand is read even if it isn't needed (e.g., for type==global)
7425          */
7426         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7427                         vmx_instruction_info, false, &gva))
7428                 return 1;
7429         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7430                                 sizeof(operand), &e)) {
7431                 kvm_inject_page_fault(vcpu, &e);
7432                 return 1;
7433         }
7434
7435         switch (type) {
7436         case VMX_EPT_EXTENT_GLOBAL:
7437                 kvm_mmu_sync_roots(vcpu);
7438                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7439                 nested_vmx_succeed(vcpu);
7440                 break;
7441         default:
7442                 /* Trap single context invalidation invept calls */
7443                 BUG_ON(1);
7444                 break;
7445         }
7446
7447         skip_emulated_instruction(vcpu);
7448         return 1;
7449 }
7450
7451 static int handle_invvpid(struct kvm_vcpu *vcpu)
7452 {
7453         struct vcpu_vmx *vmx = to_vmx(vcpu);
7454         u32 vmx_instruction_info;
7455         unsigned long type, types;
7456         gva_t gva;
7457         struct x86_exception e;
7458         int vpid;
7459
7460         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7461               SECONDARY_EXEC_ENABLE_VPID) ||
7462                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7463                 kvm_queue_exception(vcpu, UD_VECTOR);
7464                 return 1;
7465         }
7466
7467         if (!nested_vmx_check_permission(vcpu))
7468                 return 1;
7469
7470         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7471         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7472
7473         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7474
7475         if (!(types & (1UL << type))) {
7476                 nested_vmx_failValid(vcpu,
7477                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7478                 skip_emulated_instruction(vcpu);
7479                 return 1;
7480         }
7481
7482         /* according to the intel vmx instruction reference, the memory
7483          * operand is read even if it isn't needed (e.g., for type==global)
7484          */
7485         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7486                         vmx_instruction_info, false, &gva))
7487                 return 1;
7488         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7489                                 sizeof(u32), &e)) {
7490                 kvm_inject_page_fault(vcpu, &e);
7491                 return 1;
7492         }
7493
7494         switch (type) {
7495         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7496                 /*
7497                  * Old versions of KVM use the single-context version so we
7498                  * have to support it; just treat it the same as all-context.
7499                  */
7500         case VMX_VPID_EXTENT_ALL_CONTEXT:
7501                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7502                 nested_vmx_succeed(vcpu);
7503                 break;
7504         default:
7505                 /* Trap individual address invalidation invvpid calls */
7506                 BUG_ON(1);
7507                 break;
7508         }
7509
7510         skip_emulated_instruction(vcpu);
7511         return 1;
7512 }
7513
7514 static int handle_pml_full(struct kvm_vcpu *vcpu)
7515 {
7516         unsigned long exit_qualification;
7517
7518         trace_kvm_pml_full(vcpu->vcpu_id);
7519
7520         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7521
7522         /*
7523          * PML buffer FULL happened while executing iret from NMI,
7524          * "blocked by NMI" bit has to be set before next VM entry.
7525          */
7526         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7527                         cpu_has_virtual_nmis() &&
7528                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7529                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7530                                 GUEST_INTR_STATE_NMI);
7531
7532         /*
7533          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7534          * here.., and there's no userspace involvement needed for PML.
7535          */
7536         return 1;
7537 }
7538
7539 static int handle_pcommit(struct kvm_vcpu *vcpu)
7540 {
7541         /* we never catch pcommit instruct for L1 guest. */
7542         WARN_ON(1);
7543         return 1;
7544 }
7545
7546 /*
7547  * The exit handlers return 1 if the exit was handled fully and guest execution
7548  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7549  * to be done to userspace and return 0.
7550  */
7551 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7552         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7553         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7554         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7555         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7556         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7557         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7558         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7559         [EXIT_REASON_CPUID]                   = handle_cpuid,
7560         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7561         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7562         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7563         [EXIT_REASON_HLT]                     = handle_halt,
7564         [EXIT_REASON_INVD]                    = handle_invd,
7565         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7566         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7567         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7568         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7569         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7570         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7571         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7572         [EXIT_REASON_VMREAD]                  = handle_vmread,
7573         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7574         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7575         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7576         [EXIT_REASON_VMON]                    = handle_vmon,
7577         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7578         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7579         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7580         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7581         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7582         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7583         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7584         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7585         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7586         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7587         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7588         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7589         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7590         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7591         [EXIT_REASON_INVEPT]                  = handle_invept,
7592         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7593         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7594         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7595         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7596         [EXIT_REASON_PCOMMIT]                 = handle_pcommit,
7597 };
7598
7599 static const int kvm_vmx_max_exit_handlers =
7600         ARRAY_SIZE(kvm_vmx_exit_handlers);
7601
7602 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7603                                        struct vmcs12 *vmcs12)
7604 {
7605         unsigned long exit_qualification;
7606         gpa_t bitmap, last_bitmap;
7607         unsigned int port;
7608         int size;
7609         u8 b;
7610
7611         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7612                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7613
7614         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7615
7616         port = exit_qualification >> 16;
7617         size = (exit_qualification & 7) + 1;
7618
7619         last_bitmap = (gpa_t)-1;
7620         b = -1;
7621
7622         while (size > 0) {
7623                 if (port < 0x8000)
7624                         bitmap = vmcs12->io_bitmap_a;
7625                 else if (port < 0x10000)
7626                         bitmap = vmcs12->io_bitmap_b;
7627                 else
7628                         return true;
7629                 bitmap += (port & 0x7fff) / 8;
7630
7631                 if (last_bitmap != bitmap)
7632                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7633                                 return true;
7634                 if (b & (1 << (port & 7)))
7635                         return true;
7636
7637                 port++;
7638                 size--;
7639                 last_bitmap = bitmap;
7640         }
7641
7642         return false;
7643 }
7644
7645 /*
7646  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7647  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7648  * disinterest in the current event (read or write a specific MSR) by using an
7649  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7650  */
7651 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7652         struct vmcs12 *vmcs12, u32 exit_reason)
7653 {
7654         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7655         gpa_t bitmap;
7656
7657         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7658                 return true;
7659
7660         /*
7661          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7662          * for the four combinations of read/write and low/high MSR numbers.
7663          * First we need to figure out which of the four to use:
7664          */
7665         bitmap = vmcs12->msr_bitmap;
7666         if (exit_reason == EXIT_REASON_MSR_WRITE)
7667                 bitmap += 2048;
7668         if (msr_index >= 0xc0000000) {
7669                 msr_index -= 0xc0000000;
7670                 bitmap += 1024;
7671         }
7672
7673         /* Then read the msr_index'th bit from this bitmap: */
7674         if (msr_index < 1024*8) {
7675                 unsigned char b;
7676                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7677                         return true;
7678                 return 1 & (b >> (msr_index & 7));
7679         } else
7680                 return true; /* let L1 handle the wrong parameter */
7681 }
7682
7683 /*
7684  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7685  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7686  * intercept (via guest_host_mask etc.) the current event.
7687  */
7688 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7689         struct vmcs12 *vmcs12)
7690 {
7691         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7692         int cr = exit_qualification & 15;
7693         int reg = (exit_qualification >> 8) & 15;
7694         unsigned long val = kvm_register_readl(vcpu, reg);
7695
7696         switch ((exit_qualification >> 4) & 3) {
7697         case 0: /* mov to cr */
7698                 switch (cr) {
7699                 case 0:
7700                         if (vmcs12->cr0_guest_host_mask &
7701                             (val ^ vmcs12->cr0_read_shadow))
7702                                 return true;
7703                         break;
7704                 case 3:
7705                         if ((vmcs12->cr3_target_count >= 1 &&
7706                                         vmcs12->cr3_target_value0 == val) ||
7707                                 (vmcs12->cr3_target_count >= 2 &&
7708                                         vmcs12->cr3_target_value1 == val) ||
7709                                 (vmcs12->cr3_target_count >= 3 &&
7710                                         vmcs12->cr3_target_value2 == val) ||
7711                                 (vmcs12->cr3_target_count >= 4 &&
7712                                         vmcs12->cr3_target_value3 == val))
7713                                 return false;
7714                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7715                                 return true;
7716                         break;
7717                 case 4:
7718                         if (vmcs12->cr4_guest_host_mask &
7719                             (vmcs12->cr4_read_shadow ^ val))
7720                                 return true;
7721                         break;
7722                 case 8:
7723                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7724                                 return true;
7725                         break;
7726                 }
7727                 break;
7728         case 2: /* clts */
7729                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7730                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7731                         return true;
7732                 break;
7733         case 1: /* mov from cr */
7734                 switch (cr) {
7735                 case 3:
7736                         if (vmcs12->cpu_based_vm_exec_control &
7737                             CPU_BASED_CR3_STORE_EXITING)
7738                                 return true;
7739                         break;
7740                 case 8:
7741                         if (vmcs12->cpu_based_vm_exec_control &
7742                             CPU_BASED_CR8_STORE_EXITING)
7743                                 return true;
7744                         break;
7745                 }
7746                 break;
7747         case 3: /* lmsw */
7748                 /*
7749                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7750                  * cr0. Other attempted changes are ignored, with no exit.
7751                  */
7752                 if (vmcs12->cr0_guest_host_mask & 0xe &
7753                     (val ^ vmcs12->cr0_read_shadow))
7754                         return true;
7755                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7756                     !(vmcs12->cr0_read_shadow & 0x1) &&
7757                     (val & 0x1))
7758                         return true;
7759                 break;
7760         }
7761         return false;
7762 }
7763
7764 /*
7765  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7766  * should handle it ourselves in L0 (and then continue L2). Only call this
7767  * when in is_guest_mode (L2).
7768  */
7769 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7770 {
7771         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7772         struct vcpu_vmx *vmx = to_vmx(vcpu);
7773         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7774         u32 exit_reason = vmx->exit_reason;
7775
7776         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7777                                 vmcs_readl(EXIT_QUALIFICATION),
7778                                 vmx->idt_vectoring_info,
7779                                 intr_info,
7780                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7781                                 KVM_ISA_VMX);
7782
7783         if (vmx->nested.nested_run_pending)
7784                 return false;
7785
7786         if (unlikely(vmx->fail)) {
7787                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7788                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7789                 return true;
7790         }
7791
7792         switch (exit_reason) {
7793         case EXIT_REASON_EXCEPTION_NMI:
7794                 if (!is_exception(intr_info))
7795                         return false;
7796                 else if (is_page_fault(intr_info))
7797                         return enable_ept;
7798                 else if (is_no_device(intr_info) &&
7799                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7800                         return false;
7801                 else if (is_debug(intr_info) &&
7802                          vcpu->guest_debug &
7803                          (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
7804                         return false;
7805                 else if (is_breakpoint(intr_info) &&
7806                          vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
7807                         return false;
7808                 return vmcs12->exception_bitmap &
7809                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7810         case EXIT_REASON_EXTERNAL_INTERRUPT:
7811                 return false;
7812         case EXIT_REASON_TRIPLE_FAULT:
7813                 return true;
7814         case EXIT_REASON_PENDING_INTERRUPT:
7815                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7816         case EXIT_REASON_NMI_WINDOW:
7817                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7818         case EXIT_REASON_TASK_SWITCH:
7819                 return true;
7820         case EXIT_REASON_CPUID:
7821                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7822                         return false;
7823                 return true;
7824         case EXIT_REASON_HLT:
7825                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7826         case EXIT_REASON_INVD:
7827                 return true;
7828         case EXIT_REASON_INVLPG:
7829                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7830         case EXIT_REASON_RDPMC:
7831                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7832         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7833                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7834         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7835         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7836         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7837         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7838         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7839         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7840                 /*
7841                  * VMX instructions trap unconditionally. This allows L1 to
7842                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7843                  */
7844                 return true;
7845         case EXIT_REASON_CR_ACCESS:
7846                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7847         case EXIT_REASON_DR_ACCESS:
7848                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7849         case EXIT_REASON_IO_INSTRUCTION:
7850                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7851         case EXIT_REASON_MSR_READ:
7852         case EXIT_REASON_MSR_WRITE:
7853                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7854         case EXIT_REASON_INVALID_STATE:
7855                 return true;
7856         case EXIT_REASON_MWAIT_INSTRUCTION:
7857                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7858         case EXIT_REASON_MONITOR_TRAP_FLAG:
7859                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7860         case EXIT_REASON_MONITOR_INSTRUCTION:
7861                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7862         case EXIT_REASON_PAUSE_INSTRUCTION:
7863                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7864                         nested_cpu_has2(vmcs12,
7865                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7866         case EXIT_REASON_MCE_DURING_VMENTRY:
7867                 return false;
7868         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7869                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7870         case EXIT_REASON_APIC_ACCESS:
7871                 return nested_cpu_has2(vmcs12,
7872                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7873         case EXIT_REASON_APIC_WRITE:
7874         case EXIT_REASON_EOI_INDUCED:
7875                 /* apic_write and eoi_induced should exit unconditionally. */
7876                 return true;
7877         case EXIT_REASON_EPT_VIOLATION:
7878                 /*
7879                  * L0 always deals with the EPT violation. If nested EPT is
7880                  * used, and the nested mmu code discovers that the address is
7881                  * missing in the guest EPT table (EPT12), the EPT violation
7882                  * will be injected with nested_ept_inject_page_fault()
7883                  */
7884                 return false;
7885         case EXIT_REASON_EPT_MISCONFIG:
7886                 /*
7887                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7888                  * table (shadow on EPT) or a merged EPT table that L0 built
7889                  * (EPT on EPT). So any problems with the structure of the
7890                  * table is L0's fault.
7891                  */
7892                 return false;
7893         case EXIT_REASON_WBINVD:
7894                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7895         case EXIT_REASON_XSETBV:
7896                 return true;
7897         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7898                 /*
7899                  * This should never happen, since it is not possible to
7900                  * set XSS to a non-zero value---neither in L1 nor in L2.
7901                  * If if it were, XSS would have to be checked against
7902                  * the XSS exit bitmap in vmcs12.
7903                  */
7904                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7905         case EXIT_REASON_PCOMMIT:
7906                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
7907         default:
7908                 return true;
7909         }
7910 }
7911
7912 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7913 {
7914         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7915         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7916 }
7917
7918 static int vmx_create_pml_buffer(struct vcpu_vmx *vmx)
7919 {
7920         struct page *pml_pg;
7921
7922         pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7923         if (!pml_pg)
7924                 return -ENOMEM;
7925
7926         vmx->pml_pg = pml_pg;
7927
7928         vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7929         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7930
7931         return 0;
7932 }
7933
7934 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
7935 {
7936         if (vmx->pml_pg) {
7937                 __free_page(vmx->pml_pg);
7938                 vmx->pml_pg = NULL;
7939         }
7940 }
7941
7942 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
7943 {
7944         struct vcpu_vmx *vmx = to_vmx(vcpu);
7945         u64 *pml_buf;
7946         u16 pml_idx;
7947
7948         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7949
7950         /* Do nothing if PML buffer is empty */
7951         if (pml_idx == (PML_ENTITY_NUM - 1))
7952                 return;
7953
7954         /* PML index always points to next available PML buffer entity */
7955         if (pml_idx >= PML_ENTITY_NUM)
7956                 pml_idx = 0;
7957         else
7958                 pml_idx++;
7959
7960         pml_buf = page_address(vmx->pml_pg);
7961         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7962                 u64 gpa;
7963
7964                 gpa = pml_buf[pml_idx];
7965                 WARN_ON(gpa & (PAGE_SIZE - 1));
7966                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
7967         }
7968
7969         /* reset PML index */
7970         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7971 }
7972
7973 /*
7974  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7975  * Called before reporting dirty_bitmap to userspace.
7976  */
7977 static void kvm_flush_pml_buffers(struct kvm *kvm)
7978 {
7979         int i;
7980         struct kvm_vcpu *vcpu;
7981         /*
7982          * We only need to kick vcpu out of guest mode here, as PML buffer
7983          * is flushed at beginning of all VMEXITs, and it's obvious that only
7984          * vcpus running in guest are possible to have unflushed GPAs in PML
7985          * buffer.
7986          */
7987         kvm_for_each_vcpu(i, vcpu, kvm)
7988                 kvm_vcpu_kick(vcpu);
7989 }
7990
7991 static void vmx_dump_sel(char *name, uint32_t sel)
7992 {
7993         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7994                name, vmcs_read32(sel),
7995                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7996                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7997                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7998 }
7999
8000 static void vmx_dump_dtsel(char *name, uint32_t limit)
8001 {
8002         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
8003                name, vmcs_read32(limit),
8004                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
8005 }
8006
8007 static void dump_vmcs(void)
8008 {
8009         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
8010         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
8011         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
8012         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
8013         u32 secondary_exec_control = 0;
8014         unsigned long cr4 = vmcs_readl(GUEST_CR4);
8015         u64 efer = vmcs_read64(GUEST_IA32_EFER);
8016         int i, n;
8017
8018         if (cpu_has_secondary_exec_ctrls())
8019                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8020
8021         pr_err("*** Guest State ***\n");
8022         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8023                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
8024                vmcs_readl(CR0_GUEST_HOST_MASK));
8025         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
8026                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
8027         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
8028         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
8029             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
8030         {
8031                 pr_err("PDPTR0 = 0x%016llx  PDPTR1 = 0x%016llx\n",
8032                        vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
8033                 pr_err("PDPTR2 = 0x%016llx  PDPTR3 = 0x%016llx\n",
8034                        vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
8035         }
8036         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
8037                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
8038         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
8039                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
8040         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8041                vmcs_readl(GUEST_SYSENTER_ESP),
8042                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
8043         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
8044         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
8045         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
8046         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
8047         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
8048         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
8049         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
8050         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
8051         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
8052         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
8053         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
8054             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
8055                 pr_err("EFER =     0x%016llx  PAT = 0x%016llx\n",
8056                        efer, vmcs_read64(GUEST_IA32_PAT));
8057         pr_err("DebugCtl = 0x%016llx  DebugExceptions = 0x%016lx\n",
8058                vmcs_read64(GUEST_IA32_DEBUGCTL),
8059                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
8060         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
8061                 pr_err("PerfGlobCtl = 0x%016llx\n",
8062                        vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
8063         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
8064                 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
8065         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
8066                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
8067                vmcs_read32(GUEST_ACTIVITY_STATE));
8068         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
8069                 pr_err("InterruptStatus = %04x\n",
8070                        vmcs_read16(GUEST_INTR_STATUS));
8071
8072         pr_err("*** Host State ***\n");
8073         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
8074                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
8075         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8076                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8077                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8078                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8079                vmcs_read16(HOST_TR_SELECTOR));
8080         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8081                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8082                vmcs_readl(HOST_TR_BASE));
8083         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8084                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8085         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8086                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8087                vmcs_readl(HOST_CR4));
8088         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8089                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8090                vmcs_read32(HOST_IA32_SYSENTER_CS),
8091                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8092         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8093                 pr_err("EFER = 0x%016llx  PAT = 0x%016llx\n",
8094                        vmcs_read64(HOST_IA32_EFER),
8095                        vmcs_read64(HOST_IA32_PAT));
8096         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8097                 pr_err("PerfGlobCtl = 0x%016llx\n",
8098                        vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
8099
8100         pr_err("*** Control State ***\n");
8101         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8102                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8103         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8104         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8105                vmcs_read32(EXCEPTION_BITMAP),
8106                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8107                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8108         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8109                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8110                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8111                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8112         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8113                vmcs_read32(VM_EXIT_INTR_INFO),
8114                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8115                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8116         pr_err("        reason=%08x qualification=%016lx\n",
8117                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8118         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8119                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8120                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8121         pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
8122         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8123                 pr_err("TSC Multiplier = 0x%016llx\n",
8124                        vmcs_read64(TSC_MULTIPLIER));
8125         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8126                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8127         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8128                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8129         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8130                 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
8131         n = vmcs_read32(CR3_TARGET_COUNT);
8132         for (i = 0; i + 1 < n; i += 4)
8133                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8134                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8135                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8136         if (i < n)
8137                 pr_err("CR3 target%u=%016lx\n",
8138                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8139         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8140                 pr_err("PLE Gap=%08x Window=%08x\n",
8141                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8142         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8143                 pr_err("Virtual processor ID = 0x%04x\n",
8144                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8145 }
8146
8147 /*
8148  * The guest has exited.  See if we can fix it or if we need userspace
8149  * assistance.
8150  */
8151 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8152 {
8153         struct vcpu_vmx *vmx = to_vmx(vcpu);
8154         u32 exit_reason = vmx->exit_reason;
8155         u32 vectoring_info = vmx->idt_vectoring_info;
8156
8157         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8158
8159         /*
8160          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8161          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8162          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8163          * mode as if vcpus is in root mode, the PML buffer must has been
8164          * flushed already.
8165          */
8166         if (enable_pml)
8167                 vmx_flush_pml_buffer(vcpu);
8168
8169         /* If guest state is invalid, start emulating */
8170         if (vmx->emulation_required)
8171                 return handle_invalid_guest_state(vcpu);
8172
8173         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8174                 nested_vmx_vmexit(vcpu, exit_reason,
8175                                   vmcs_read32(VM_EXIT_INTR_INFO),
8176                                   vmcs_readl(EXIT_QUALIFICATION));
8177                 return 1;
8178         }
8179
8180         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8181                 dump_vmcs();
8182                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8183                 vcpu->run->fail_entry.hardware_entry_failure_reason
8184                         = exit_reason;
8185                 return 0;
8186         }
8187
8188         if (unlikely(vmx->fail)) {
8189                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8190                 vcpu->run->fail_entry.hardware_entry_failure_reason
8191                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8192                 return 0;
8193         }
8194
8195         /*
8196          * Note:
8197          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8198          * delivery event since it indicates guest is accessing MMIO.
8199          * The vm-exit can be triggered again after return to guest that
8200          * will cause infinite loop.
8201          */
8202         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8203                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8204                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8205                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8206                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8207                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8208                 vcpu->run->internal.ndata = 2;
8209                 vcpu->run->internal.data[0] = vectoring_info;
8210                 vcpu->run->internal.data[1] = exit_reason;
8211                 return 0;
8212         }
8213
8214         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8215             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8216                                         get_vmcs12(vcpu))))) {
8217                 if (vmx_interrupt_allowed(vcpu)) {
8218                         vmx->soft_vnmi_blocked = 0;
8219                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8220                            vcpu->arch.nmi_pending) {
8221                         /*
8222                          * This CPU don't support us in finding the end of an
8223                          * NMI-blocked window if the guest runs with IRQs
8224                          * disabled. So we pull the trigger after 1 s of
8225                          * futile waiting, but inform the user about this.
8226                          */
8227                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8228                                "state on VCPU %d after 1 s timeout\n",
8229                                __func__, vcpu->vcpu_id);
8230                         vmx->soft_vnmi_blocked = 0;
8231                 }
8232         }
8233
8234         if (exit_reason < kvm_vmx_max_exit_handlers
8235             && kvm_vmx_exit_handlers[exit_reason])
8236                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8237         else {
8238                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8239                 kvm_queue_exception(vcpu, UD_VECTOR);
8240                 return 1;
8241         }
8242 }
8243
8244 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8245 {
8246         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8247
8248         if (is_guest_mode(vcpu) &&
8249                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8250                 return;
8251
8252         if (irr == -1 || tpr < irr) {
8253                 vmcs_write32(TPR_THRESHOLD, 0);
8254                 return;
8255         }
8256
8257         vmcs_write32(TPR_THRESHOLD, irr);
8258 }
8259
8260 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8261 {
8262         u32 sec_exec_control;
8263
8264         /*
8265          * There is not point to enable virtualize x2apic without enable
8266          * apicv
8267          */
8268         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8269                                 !kvm_vcpu_apicv_active(vcpu))
8270                 return;
8271
8272         if (!cpu_need_tpr_shadow(vcpu))
8273                 return;
8274
8275         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8276
8277         if (set) {
8278                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8279                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8280         } else {
8281                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8282                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8283         }
8284         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8285
8286         vmx_set_msr_bitmap(vcpu);
8287 }
8288
8289 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8290 {
8291         struct vcpu_vmx *vmx = to_vmx(vcpu);
8292
8293         /*
8294          * Currently we do not handle the nested case where L2 has an
8295          * APIC access page of its own; that page is still pinned.
8296          * Hence, we skip the case where the VCPU is in guest mode _and_
8297          * L1 prepared an APIC access page for L2.
8298          *
8299          * For the case where L1 and L2 share the same APIC access page
8300          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8301          * in the vmcs12), this function will only update either the vmcs01
8302          * or the vmcs02.  If the former, the vmcs02 will be updated by
8303          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8304          * the next L2->L1 exit.
8305          */
8306         if (!is_guest_mode(vcpu) ||
8307             !nested_cpu_has2(vmx->nested.current_vmcs12,
8308                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8309                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8310 }
8311
8312 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8313 {
8314         u16 status;
8315         u8 old;
8316
8317         if (isr == -1)
8318                 isr = 0;
8319
8320         status = vmcs_read16(GUEST_INTR_STATUS);
8321         old = status >> 8;
8322         if (isr != old) {
8323                 status &= 0xff;
8324                 status |= isr << 8;
8325                 vmcs_write16(GUEST_INTR_STATUS, status);
8326         }
8327 }
8328
8329 static void vmx_set_rvi(int vector)
8330 {
8331         u16 status;
8332         u8 old;
8333
8334         if (vector == -1)
8335                 vector = 0;
8336
8337         status = vmcs_read16(GUEST_INTR_STATUS);
8338         old = (u8)status & 0xff;
8339         if ((u8)vector != old) {
8340                 status &= ~0xff;
8341                 status |= (u8)vector;
8342                 vmcs_write16(GUEST_INTR_STATUS, status);
8343         }
8344 }
8345
8346 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8347 {
8348         if (!is_guest_mode(vcpu)) {
8349                 vmx_set_rvi(max_irr);
8350                 return;
8351         }
8352
8353         if (max_irr == -1)
8354                 return;
8355
8356         /*
8357          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8358          * handles it.
8359          */
8360         if (nested_exit_on_intr(vcpu))
8361                 return;
8362
8363         /*
8364          * Else, fall back to pre-APICv interrupt injection since L2
8365          * is run without virtual interrupt delivery.
8366          */
8367         if (!kvm_event_needs_reinjection(vcpu) &&
8368             vmx_interrupt_allowed(vcpu)) {
8369                 kvm_queue_interrupt(vcpu, max_irr, false);
8370                 vmx_inject_irq(vcpu);
8371         }
8372 }
8373
8374 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
8375 {
8376         if (!kvm_vcpu_apicv_active(vcpu))
8377                 return;
8378
8379         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8380         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8381         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8382         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8383 }
8384
8385 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8386 {
8387         u32 exit_intr_info;
8388
8389         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8390               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8391                 return;
8392
8393         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8394         exit_intr_info = vmx->exit_intr_info;
8395
8396         /* Handle machine checks before interrupts are enabled */
8397         if (is_machine_check(exit_intr_info))
8398                 kvm_machine_check();
8399
8400         /* We need to handle NMIs before interrupts are enabled */
8401         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8402             (exit_intr_info & INTR_INFO_VALID_MASK)) {
8403                 kvm_before_handle_nmi(&vmx->vcpu);
8404                 asm("int $2");
8405                 kvm_after_handle_nmi(&vmx->vcpu);
8406         }
8407 }
8408
8409 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8410 {
8411         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8412         register void *__sp asm(_ASM_SP);
8413
8414         /*
8415          * If external interrupt exists, IF bit is set in rflags/eflags on the
8416          * interrupt stack frame, and interrupt will be enabled on a return
8417          * from interrupt handler.
8418          */
8419         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8420                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8421                 unsigned int vector;
8422                 unsigned long entry;
8423                 gate_desc *desc;
8424                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8425 #ifdef CONFIG_X86_64
8426                 unsigned long tmp;
8427 #endif
8428
8429                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8430                 desc = (gate_desc *)vmx->host_idt_base + vector;
8431                 entry = gate_offset(*desc);
8432                 asm volatile(
8433 #ifdef CONFIG_X86_64
8434                         "mov %%" _ASM_SP ", %[sp]\n\t"
8435                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8436                         "push $%c[ss]\n\t"
8437                         "push %[sp]\n\t"
8438 #endif
8439                         "pushf\n\t"
8440                         "orl $0x200, (%%" _ASM_SP ")\n\t"
8441                         __ASM_SIZE(push) " $%c[cs]\n\t"
8442                         "call *%[entry]\n\t"
8443                         :
8444 #ifdef CONFIG_X86_64
8445                         [sp]"=&r"(tmp),
8446 #endif
8447                         "+r"(__sp)
8448                         :
8449                         [entry]"r"(entry),
8450                         [ss]"i"(__KERNEL_DS),
8451                         [cs]"i"(__KERNEL_CS)
8452                         );
8453         } else
8454                 local_irq_enable();
8455 }
8456
8457 static bool vmx_has_high_real_mode_segbase(void)
8458 {
8459         return enable_unrestricted_guest || emulate_invalid_guest_state;
8460 }
8461
8462 static bool vmx_mpx_supported(void)
8463 {
8464         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8465                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8466 }
8467
8468 static bool vmx_xsaves_supported(void)
8469 {
8470         return vmcs_config.cpu_based_2nd_exec_ctrl &
8471                 SECONDARY_EXEC_XSAVES;
8472 }
8473
8474 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8475 {
8476         u32 exit_intr_info;
8477         bool unblock_nmi;
8478         u8 vector;
8479         bool idtv_info_valid;
8480
8481         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8482
8483         if (cpu_has_virtual_nmis()) {
8484                 if (vmx->nmi_known_unmasked)
8485                         return;
8486                 /*
8487                  * Can't use vmx->exit_intr_info since we're not sure what
8488                  * the exit reason is.
8489                  */
8490                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8491                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8492                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8493                 /*
8494                  * SDM 3: 27.7.1.2 (September 2008)
8495                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8496                  * a guest IRET fault.
8497                  * SDM 3: 23.2.2 (September 2008)
8498                  * Bit 12 is undefined in any of the following cases:
8499                  *  If the VM exit sets the valid bit in the IDT-vectoring
8500                  *   information field.
8501                  *  If the VM exit is due to a double fault.
8502                  */
8503                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8504                     vector != DF_VECTOR && !idtv_info_valid)
8505                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8506                                       GUEST_INTR_STATE_NMI);
8507                 else
8508                         vmx->nmi_known_unmasked =
8509                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8510                                   & GUEST_INTR_STATE_NMI);
8511         } else if (unlikely(vmx->soft_vnmi_blocked))
8512                 vmx->vnmi_blocked_time +=
8513                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8514 }
8515
8516 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8517                                       u32 idt_vectoring_info,
8518                                       int instr_len_field,
8519                                       int error_code_field)
8520 {
8521         u8 vector;
8522         int type;
8523         bool idtv_info_valid;
8524
8525         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8526
8527         vcpu->arch.nmi_injected = false;
8528         kvm_clear_exception_queue(vcpu);
8529         kvm_clear_interrupt_queue(vcpu);
8530
8531         if (!idtv_info_valid)
8532                 return;
8533
8534         kvm_make_request(KVM_REQ_EVENT, vcpu);
8535
8536         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8537         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8538
8539         switch (type) {
8540         case INTR_TYPE_NMI_INTR:
8541                 vcpu->arch.nmi_injected = true;
8542                 /*
8543                  * SDM 3: 27.7.1.2 (September 2008)
8544                  * Clear bit "block by NMI" before VM entry if a NMI
8545                  * delivery faulted.
8546                  */
8547                 vmx_set_nmi_mask(vcpu, false);
8548                 break;
8549         case INTR_TYPE_SOFT_EXCEPTION:
8550                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8551                 /* fall through */
8552         case INTR_TYPE_HARD_EXCEPTION:
8553                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8554                         u32 err = vmcs_read32(error_code_field);
8555                         kvm_requeue_exception_e(vcpu, vector, err);
8556                 } else
8557                         kvm_requeue_exception(vcpu, vector);
8558                 break;
8559         case INTR_TYPE_SOFT_INTR:
8560                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8561                 /* fall through */
8562         case INTR_TYPE_EXT_INTR:
8563                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8564                 break;
8565         default:
8566                 break;
8567         }
8568 }
8569
8570 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8571 {
8572         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8573                                   VM_EXIT_INSTRUCTION_LEN,
8574                                   IDT_VECTORING_ERROR_CODE);
8575 }
8576
8577 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8578 {
8579         __vmx_complete_interrupts(vcpu,
8580                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8581                                   VM_ENTRY_INSTRUCTION_LEN,
8582                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8583
8584         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8585 }
8586
8587 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8588 {
8589         int i, nr_msrs;
8590         struct perf_guest_switch_msr *msrs;
8591
8592         msrs = perf_guest_get_msrs(&nr_msrs);
8593
8594         if (!msrs)
8595                 return;
8596
8597         for (i = 0; i < nr_msrs; i++)
8598                 if (msrs[i].host == msrs[i].guest)
8599                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8600                 else
8601                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8602                                         msrs[i].host);
8603 }
8604
8605 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8606 {
8607         struct vcpu_vmx *vmx = to_vmx(vcpu);
8608         unsigned long debugctlmsr, cr4;
8609
8610         /* Record the guest's net vcpu time for enforced NMI injections. */
8611         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8612                 vmx->entry_time = ktime_get();
8613
8614         /* Don't enter VMX if guest state is invalid, let the exit handler
8615            start emulation until we arrive back to a valid state */
8616         if (vmx->emulation_required)
8617                 return;
8618
8619         if (vmx->ple_window_dirty) {
8620                 vmx->ple_window_dirty = false;
8621                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8622         }
8623
8624         if (vmx->nested.sync_shadow_vmcs) {
8625                 copy_vmcs12_to_shadow(vmx);
8626                 vmx->nested.sync_shadow_vmcs = false;
8627         }
8628
8629         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8630                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8631         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8632                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8633
8634         cr4 = cr4_read_shadow();
8635         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8636                 vmcs_writel(HOST_CR4, cr4);
8637                 vmx->host_state.vmcs_host_cr4 = cr4;
8638         }
8639
8640         /* When single-stepping over STI and MOV SS, we must clear the
8641          * corresponding interruptibility bits in the guest state. Otherwise
8642          * vmentry fails as it then expects bit 14 (BS) in pending debug
8643          * exceptions being set, but that's not correct for the guest debugging
8644          * case. */
8645         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8646                 vmx_set_interrupt_shadow(vcpu, 0);
8647
8648         if (vmx->guest_pkru_valid)
8649                 __write_pkru(vmx->guest_pkru);
8650
8651         atomic_switch_perf_msrs(vmx);
8652         debugctlmsr = get_debugctlmsr();
8653
8654         vmx->__launched = vmx->loaded_vmcs->launched;
8655         asm(
8656                 /* Store host registers */
8657                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8658                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8659                 "push %%" _ASM_CX " \n\t"
8660                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8661                 "je 1f \n\t"
8662                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8663                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8664                 "1: \n\t"
8665                 /* Reload cr2 if changed */
8666                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8667                 "mov %%cr2, %%" _ASM_DX " \n\t"
8668                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8669                 "je 2f \n\t"
8670                 "mov %%" _ASM_AX", %%cr2 \n\t"
8671                 "2: \n\t"
8672                 /* Check if vmlaunch of vmresume is needed */
8673                 "cmpl $0, %c[launched](%0) \n\t"
8674                 /* Load guest registers.  Don't clobber flags. */
8675                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8676                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8677                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8678                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8679                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8680                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8681 #ifdef CONFIG_X86_64
8682                 "mov %c[r8](%0),  %%r8  \n\t"
8683                 "mov %c[r9](%0),  %%r9  \n\t"
8684                 "mov %c[r10](%0), %%r10 \n\t"
8685                 "mov %c[r11](%0), %%r11 \n\t"
8686                 "mov %c[r12](%0), %%r12 \n\t"
8687                 "mov %c[r13](%0), %%r13 \n\t"
8688                 "mov %c[r14](%0), %%r14 \n\t"
8689                 "mov %c[r15](%0), %%r15 \n\t"
8690 #endif
8691                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8692
8693                 /* Enter guest mode */
8694                 "jne 1f \n\t"
8695                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8696                 "jmp 2f \n\t"
8697                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8698                 "2: "
8699                 /* Save guest registers, load host registers, keep flags */
8700                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8701                 "pop %0 \n\t"
8702                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8703                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8704                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8705                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8706                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8707                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8708                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8709 #ifdef CONFIG_X86_64
8710                 "mov %%r8,  %c[r8](%0) \n\t"
8711                 "mov %%r9,  %c[r9](%0) \n\t"
8712                 "mov %%r10, %c[r10](%0) \n\t"
8713                 "mov %%r11, %c[r11](%0) \n\t"
8714                 "mov %%r12, %c[r12](%0) \n\t"
8715                 "mov %%r13, %c[r13](%0) \n\t"
8716                 "mov %%r14, %c[r14](%0) \n\t"
8717                 "mov %%r15, %c[r15](%0) \n\t"
8718 #endif
8719                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8720                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8721
8722                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8723                 "setbe %c[fail](%0) \n\t"
8724                 ".pushsection .rodata \n\t"
8725                 ".global vmx_return \n\t"
8726                 "vmx_return: " _ASM_PTR " 2b \n\t"
8727                 ".popsection"
8728               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8729                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8730                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8731                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8732                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8733                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8734                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8735                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8736                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8737                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8738                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8739 #ifdef CONFIG_X86_64
8740                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8741                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8742                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8743                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8744                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8745                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8746                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8747                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8748 #endif
8749                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8750                 [wordsize]"i"(sizeof(ulong))
8751               : "cc", "memory"
8752 #ifdef CONFIG_X86_64
8753                 , "rax", "rbx", "rdi", "rsi"
8754                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8755 #else
8756                 , "eax", "ebx", "edi", "esi"
8757 #endif
8758               );
8759
8760         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8761         if (debugctlmsr)
8762                 update_debugctlmsr(debugctlmsr);
8763
8764 #ifndef CONFIG_X86_64
8765         /*
8766          * The sysexit path does not restore ds/es, so we must set them to
8767          * a reasonable value ourselves.
8768          *
8769          * We can't defer this to vmx_load_host_state() since that function
8770          * may be executed in interrupt context, which saves and restore segments
8771          * around it, nullifying its effect.
8772          */
8773         loadsegment(ds, __USER_DS);
8774         loadsegment(es, __USER_DS);
8775 #endif
8776
8777         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8778                                   | (1 << VCPU_EXREG_RFLAGS)
8779                                   | (1 << VCPU_EXREG_PDPTR)
8780                                   | (1 << VCPU_EXREG_SEGMENTS)
8781                                   | (1 << VCPU_EXREG_CR3));
8782         vcpu->arch.regs_dirty = 0;
8783
8784         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8785
8786         vmx->loaded_vmcs->launched = 1;
8787
8788         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8789
8790         /*
8791          * eager fpu is enabled if PKEY is supported and CR4 is switched
8792          * back on host, so it is safe to read guest PKRU from current
8793          * XSAVE.
8794          */
8795         if (boot_cpu_has(X86_FEATURE_OSPKE)) {
8796                 vmx->guest_pkru = __read_pkru();
8797                 if (vmx->guest_pkru != vmx->host_pkru) {
8798                         vmx->guest_pkru_valid = true;
8799                         __write_pkru(vmx->host_pkru);
8800                 } else
8801                         vmx->guest_pkru_valid = false;
8802         }
8803
8804         /*
8805          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8806          * we did not inject a still-pending event to L1 now because of
8807          * nested_run_pending, we need to re-enable this bit.
8808          */
8809         if (vmx->nested.nested_run_pending)
8810                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8811
8812         vmx->nested.nested_run_pending = 0;
8813
8814         vmx_complete_atomic_exit(vmx);
8815         vmx_recover_nmi_blocking(vmx);
8816         vmx_complete_interrupts(vmx);
8817 }
8818
8819 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8820 {
8821         struct vcpu_vmx *vmx = to_vmx(vcpu);
8822         int cpu;
8823
8824         if (vmx->loaded_vmcs == &vmx->vmcs01)
8825                 return;
8826
8827         cpu = get_cpu();
8828         vmx->loaded_vmcs = &vmx->vmcs01;
8829         vmx_vcpu_put(vcpu);
8830         vmx_vcpu_load(vcpu, cpu);
8831         vcpu->cpu = cpu;
8832         put_cpu();
8833 }
8834
8835 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8836 {
8837         struct vcpu_vmx *vmx = to_vmx(vcpu);
8838
8839         if (enable_pml)
8840                 vmx_destroy_pml_buffer(vmx);
8841         free_vpid(vmx->vpid);
8842         leave_guest_mode(vcpu);
8843         vmx_load_vmcs01(vcpu);
8844         free_nested(vmx);
8845         free_loaded_vmcs(vmx->loaded_vmcs);
8846         kfree(vmx->guest_msrs);
8847         kvm_vcpu_uninit(vcpu);
8848         kmem_cache_free(kvm_vcpu_cache, vmx);
8849 }
8850
8851 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8852 {
8853         int err;
8854         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8855         int cpu;
8856
8857         if (!vmx)
8858                 return ERR_PTR(-ENOMEM);
8859
8860         vmx->vpid = allocate_vpid();
8861
8862         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8863         if (err)
8864                 goto free_vcpu;
8865
8866         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8867         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8868                      > PAGE_SIZE);
8869
8870         err = -ENOMEM;
8871         if (!vmx->guest_msrs) {
8872                 goto uninit_vcpu;
8873         }
8874
8875         vmx->loaded_vmcs = &vmx->vmcs01;
8876         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8877         if (!vmx->loaded_vmcs->vmcs)
8878                 goto free_msrs;
8879         if (!vmm_exclusive)
8880                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8881         loaded_vmcs_init(vmx->loaded_vmcs);
8882         if (!vmm_exclusive)
8883                 kvm_cpu_vmxoff();
8884
8885         cpu = get_cpu();
8886         vmx_vcpu_load(&vmx->vcpu, cpu);
8887         vmx->vcpu.cpu = cpu;
8888         err = vmx_vcpu_setup(vmx);
8889         vmx_vcpu_put(&vmx->vcpu);
8890         put_cpu();
8891         if (err)
8892                 goto free_vmcs;
8893         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
8894                 err = alloc_apic_access_page(kvm);
8895                 if (err)
8896                         goto free_vmcs;
8897         }
8898
8899         if (enable_ept) {
8900                 if (!kvm->arch.ept_identity_map_addr)
8901                         kvm->arch.ept_identity_map_addr =
8902                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8903                 err = init_rmode_identity_map(kvm);
8904                 if (err)
8905                         goto free_vmcs;
8906         }
8907
8908         if (nested) {
8909                 nested_vmx_setup_ctls_msrs(vmx);
8910                 vmx->nested.vpid02 = allocate_vpid();
8911         }
8912
8913         vmx->nested.posted_intr_nv = -1;
8914         vmx->nested.current_vmptr = -1ull;
8915         vmx->nested.current_vmcs12 = NULL;
8916
8917         /*
8918          * If PML is turned on, failure on enabling PML just results in failure
8919          * of creating the vcpu, therefore we can simplify PML logic (by
8920          * avoiding dealing with cases, such as enabling PML partially on vcpus
8921          * for the guest, etc.
8922          */
8923         if (enable_pml) {
8924                 err = vmx_create_pml_buffer(vmx);
8925                 if (err)
8926                         goto free_vmcs;
8927         }
8928
8929         return &vmx->vcpu;
8930
8931 free_vmcs:
8932         free_vpid(vmx->nested.vpid02);
8933         free_loaded_vmcs(vmx->loaded_vmcs);
8934 free_msrs:
8935         kfree(vmx->guest_msrs);
8936 uninit_vcpu:
8937         kvm_vcpu_uninit(&vmx->vcpu);
8938 free_vcpu:
8939         free_vpid(vmx->vpid);
8940         kmem_cache_free(kvm_vcpu_cache, vmx);
8941         return ERR_PTR(err);
8942 }
8943
8944 static void __init vmx_check_processor_compat(void *rtn)
8945 {
8946         struct vmcs_config vmcs_conf;
8947
8948         *(int *)rtn = 0;
8949         if (setup_vmcs_config(&vmcs_conf) < 0)
8950                 *(int *)rtn = -EIO;
8951         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8952                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8953                                 smp_processor_id());
8954                 *(int *)rtn = -EIO;
8955         }
8956 }
8957
8958 static int get_ept_level(void)
8959 {
8960         return VMX_EPT_DEFAULT_GAW + 1;
8961 }
8962
8963 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8964 {
8965         u8 cache;
8966         u64 ipat = 0;
8967
8968         /* For VT-d and EPT combination
8969          * 1. MMIO: always map as UC
8970          * 2. EPT with VT-d:
8971          *   a. VT-d without snooping control feature: can't guarantee the
8972          *      result, try to trust guest.
8973          *   b. VT-d with snooping control feature: snooping control feature of
8974          *      VT-d engine can guarantee the cache correctness. Just set it
8975          *      to WB to keep consistent with host. So the same as item 3.
8976          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8977          *    consistent with host MTRR
8978          */
8979         if (is_mmio) {
8980                 cache = MTRR_TYPE_UNCACHABLE;
8981                 goto exit;
8982         }
8983
8984         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
8985                 ipat = VMX_EPT_IPAT_BIT;
8986                 cache = MTRR_TYPE_WRBACK;
8987                 goto exit;
8988         }
8989
8990         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8991                 ipat = VMX_EPT_IPAT_BIT;
8992                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
8993                         cache = MTRR_TYPE_WRBACK;
8994                 else
8995                         cache = MTRR_TYPE_UNCACHABLE;
8996                 goto exit;
8997         }
8998
8999         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
9000
9001 exit:
9002         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
9003 }
9004
9005 static int vmx_get_lpage_level(void)
9006 {
9007         if (enable_ept && !cpu_has_vmx_ept_1g_page())
9008                 return PT_DIRECTORY_LEVEL;
9009         else
9010                 /* For shadow and EPT supported 1GB page */
9011                 return PT_PDPE_LEVEL;
9012 }
9013
9014 static void vmcs_set_secondary_exec_control(u32 new_ctl)
9015 {
9016         /*
9017          * These bits in the secondary execution controls field
9018          * are dynamic, the others are mostly based on the hypervisor
9019          * architecture and the guest's CPUID.  Do not touch the
9020          * dynamic bits.
9021          */
9022         u32 mask =
9023                 SECONDARY_EXEC_SHADOW_VMCS |
9024                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
9025                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9026
9027         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
9028
9029         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
9030                      (new_ctl & ~mask) | (cur_ctl & mask));
9031 }
9032
9033 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
9034 {
9035         struct kvm_cpuid_entry2 *best;
9036         struct vcpu_vmx *vmx = to_vmx(vcpu);
9037         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
9038
9039         if (vmx_rdtscp_supported()) {
9040                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
9041                 if (!rdtscp_enabled)
9042                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
9043
9044                 if (nested) {
9045                         if (rdtscp_enabled)
9046                                 vmx->nested.nested_vmx_secondary_ctls_high |=
9047                                         SECONDARY_EXEC_RDTSCP;
9048                         else
9049                                 vmx->nested.nested_vmx_secondary_ctls_high &=
9050                                         ~SECONDARY_EXEC_RDTSCP;
9051                 }
9052         }
9053
9054         /* Exposing INVPCID only when PCID is exposed */
9055         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
9056         if (vmx_invpcid_supported() &&
9057             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
9058             !guest_cpuid_has_pcid(vcpu))) {
9059                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
9060
9061                 if (best)
9062                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
9063         }
9064
9065         if (cpu_has_secondary_exec_ctrls())
9066                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
9067
9068         if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
9069                 if (guest_cpuid_has_pcommit(vcpu))
9070                         vmx->nested.nested_vmx_secondary_ctls_high |=
9071                                 SECONDARY_EXEC_PCOMMIT;
9072                 else
9073                         vmx->nested.nested_vmx_secondary_ctls_high &=
9074                                 ~SECONDARY_EXEC_PCOMMIT;
9075         }
9076 }
9077
9078 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
9079 {
9080         if (func == 1 && nested)
9081                 entry->ecx |= bit(X86_FEATURE_VMX);
9082 }
9083
9084 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
9085                 struct x86_exception *fault)
9086 {
9087         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9088         u32 exit_reason;
9089
9090         if (fault->error_code & PFERR_RSVD_MASK)
9091                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
9092         else
9093                 exit_reason = EXIT_REASON_EPT_VIOLATION;
9094         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9095         vmcs12->guest_physical_address = fault->address;
9096 }
9097
9098 /* Callbacks for nested_ept_init_mmu_context: */
9099
9100 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9101 {
9102         /* return the page table to be shadowed - in our case, EPT12 */
9103         return get_vmcs12(vcpu)->ept_pointer;
9104 }
9105
9106 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9107 {
9108         WARN_ON(mmu_is_nested(vcpu));
9109         kvm_init_shadow_ept_mmu(vcpu,
9110                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9111                         VMX_EPT_EXECUTE_ONLY_BIT);
9112         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9113         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9114         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9115
9116         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9117 }
9118
9119 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9120 {
9121         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9122 }
9123
9124 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9125                                             u16 error_code)
9126 {
9127         bool inequality, bit;
9128
9129         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9130         inequality =
9131                 (error_code & vmcs12->page_fault_error_code_mask) !=
9132                  vmcs12->page_fault_error_code_match;
9133         return inequality ^ bit;
9134 }
9135
9136 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9137                 struct x86_exception *fault)
9138 {
9139         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9140
9141         WARN_ON(!is_guest_mode(vcpu));
9142
9143         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9144                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9145                                   vmcs_read32(VM_EXIT_INTR_INFO),
9146                                   vmcs_readl(EXIT_QUALIFICATION));
9147         else
9148                 kvm_inject_page_fault(vcpu, fault);
9149 }
9150
9151 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9152                                         struct vmcs12 *vmcs12)
9153 {
9154         struct vcpu_vmx *vmx = to_vmx(vcpu);
9155         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9156
9157         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9158                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9159                     vmcs12->apic_access_addr >> maxphyaddr)
9160                         return false;
9161
9162                 /*
9163                  * Translate L1 physical address to host physical
9164                  * address for vmcs02. Keep the page pinned, so this
9165                  * physical address remains valid. We keep a reference
9166                  * to it so we can release it later.
9167                  */
9168                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9169                         nested_release_page(vmx->nested.apic_access_page);
9170                 vmx->nested.apic_access_page =
9171                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9172         }
9173
9174         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9175                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9176                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9177                         return false;
9178
9179                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9180                         nested_release_page(vmx->nested.virtual_apic_page);
9181                 vmx->nested.virtual_apic_page =
9182                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9183
9184                 /*
9185                  * Failing the vm entry is _not_ what the processor does
9186                  * but it's basically the only possibility we have.
9187                  * We could still enter the guest if CR8 load exits are
9188                  * enabled, CR8 store exits are enabled, and virtualize APIC
9189                  * access is disabled; in this case the processor would never
9190                  * use the TPR shadow and we could simply clear the bit from
9191                  * the execution control.  But such a configuration is useless,
9192                  * so let's keep the code simple.
9193                  */
9194                 if (!vmx->nested.virtual_apic_page)
9195                         return false;
9196         }
9197
9198         if (nested_cpu_has_posted_intr(vmcs12)) {
9199                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9200                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9201                         return false;
9202
9203                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9204                         kunmap(vmx->nested.pi_desc_page);
9205                         nested_release_page(vmx->nested.pi_desc_page);
9206                 }
9207                 vmx->nested.pi_desc_page =
9208                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9209                 if (!vmx->nested.pi_desc_page)
9210                         return false;
9211
9212                 vmx->nested.pi_desc =
9213                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9214                 if (!vmx->nested.pi_desc) {
9215                         nested_release_page_clean(vmx->nested.pi_desc_page);
9216                         return false;
9217                 }
9218                 vmx->nested.pi_desc =
9219                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9220                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9221                         (PAGE_SIZE - 1)));
9222         }
9223
9224         return true;
9225 }
9226
9227 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9228 {
9229         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9230         struct vcpu_vmx *vmx = to_vmx(vcpu);
9231
9232         if (vcpu->arch.virtual_tsc_khz == 0)
9233                 return;
9234
9235         /* Make sure short timeouts reliably trigger an immediate vmexit.
9236          * hrtimer_start does not guarantee this. */
9237         if (preemption_timeout <= 1) {
9238                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9239                 return;
9240         }
9241
9242         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9243         preemption_timeout *= 1000000;
9244         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9245         hrtimer_start(&vmx->nested.preemption_timer,
9246                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9247 }
9248
9249 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9250                                                 struct vmcs12 *vmcs12)
9251 {
9252         int maxphyaddr;
9253         u64 addr;
9254
9255         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9256                 return 0;
9257
9258         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9259                 WARN_ON(1);
9260                 return -EINVAL;
9261         }
9262         maxphyaddr = cpuid_maxphyaddr(vcpu);
9263
9264         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9265            ((addr + PAGE_SIZE) >> maxphyaddr))
9266                 return -EINVAL;
9267
9268         return 0;
9269 }
9270
9271 /*
9272  * Merge L0's and L1's MSR bitmap, return false to indicate that
9273  * we do not use the hardware.
9274  */
9275 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9276                                                struct vmcs12 *vmcs12)
9277 {
9278         int msr;
9279         struct page *page;
9280         unsigned long *msr_bitmap;
9281
9282         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9283                 return false;
9284
9285         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9286         if (!page) {
9287                 WARN_ON(1);
9288                 return false;
9289         }
9290         msr_bitmap = (unsigned long *)kmap(page);
9291         if (!msr_bitmap) {
9292                 nested_release_page_clean(page);
9293                 WARN_ON(1);
9294                 return false;
9295         }
9296
9297         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9298                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9299                         for (msr = 0x800; msr <= 0x8ff; msr++)
9300                                 nested_vmx_disable_intercept_for_msr(
9301                                         msr_bitmap,
9302                                         vmx_msr_bitmap_nested,
9303                                         msr, MSR_TYPE_R);
9304                 /* TPR is allowed */
9305                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9306                                 vmx_msr_bitmap_nested,
9307                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9308                                 MSR_TYPE_R | MSR_TYPE_W);
9309                 if (nested_cpu_has_vid(vmcs12)) {
9310                         /* EOI and self-IPI are allowed */
9311                         nested_vmx_disable_intercept_for_msr(
9312                                 msr_bitmap,
9313                                 vmx_msr_bitmap_nested,
9314                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9315                                 MSR_TYPE_W);
9316                         nested_vmx_disable_intercept_for_msr(
9317                                 msr_bitmap,
9318                                 vmx_msr_bitmap_nested,
9319                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9320                                 MSR_TYPE_W);
9321                 }
9322         } else {
9323                 /*
9324                  * Enable reading intercept of all the x2apic
9325                  * MSRs. We should not rely on vmcs12 to do any
9326                  * optimizations here, it may have been modified
9327                  * by L1.
9328                  */
9329                 for (msr = 0x800; msr <= 0x8ff; msr++)
9330                         __vmx_enable_intercept_for_msr(
9331                                 vmx_msr_bitmap_nested,
9332                                 msr,
9333                                 MSR_TYPE_R);
9334
9335                 __vmx_enable_intercept_for_msr(
9336                                 vmx_msr_bitmap_nested,
9337                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9338                                 MSR_TYPE_W);
9339                 __vmx_enable_intercept_for_msr(
9340                                 vmx_msr_bitmap_nested,
9341                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9342                                 MSR_TYPE_W);
9343                 __vmx_enable_intercept_for_msr(
9344                                 vmx_msr_bitmap_nested,
9345                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9346                                 MSR_TYPE_W);
9347         }
9348         kunmap(page);
9349         nested_release_page_clean(page);
9350
9351         return true;
9352 }
9353
9354 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9355                                            struct vmcs12 *vmcs12)
9356 {
9357         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9358             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9359             !nested_cpu_has_vid(vmcs12) &&
9360             !nested_cpu_has_posted_intr(vmcs12))
9361                 return 0;
9362
9363         /*
9364          * If virtualize x2apic mode is enabled,
9365          * virtualize apic access must be disabled.
9366          */
9367         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9368             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9369                 return -EINVAL;
9370
9371         /*
9372          * If virtual interrupt delivery is enabled,
9373          * we must exit on external interrupts.
9374          */
9375         if (nested_cpu_has_vid(vmcs12) &&
9376            !nested_exit_on_intr(vcpu))
9377                 return -EINVAL;
9378
9379         /*
9380          * bits 15:8 should be zero in posted_intr_nv,
9381          * the descriptor address has been already checked
9382          * in nested_get_vmcs12_pages.
9383          */
9384         if (nested_cpu_has_posted_intr(vmcs12) &&
9385            (!nested_cpu_has_vid(vmcs12) ||
9386             !nested_exit_intr_ack_set(vcpu) ||
9387             vmcs12->posted_intr_nv & 0xff00))
9388                 return -EINVAL;
9389
9390         /* tpr shadow is needed by all apicv features. */
9391         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9392                 return -EINVAL;
9393
9394         return 0;
9395 }
9396
9397 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9398                                        unsigned long count_field,
9399                                        unsigned long addr_field)
9400 {
9401         int maxphyaddr;
9402         u64 count, addr;
9403
9404         if (vmcs12_read_any(vcpu, count_field, &count) ||
9405             vmcs12_read_any(vcpu, addr_field, &addr)) {
9406                 WARN_ON(1);
9407                 return -EINVAL;
9408         }
9409         if (count == 0)
9410                 return 0;
9411         maxphyaddr = cpuid_maxphyaddr(vcpu);
9412         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9413             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9414                 pr_warn_ratelimited(
9415                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9416                         addr_field, maxphyaddr, count, addr);
9417                 return -EINVAL;
9418         }
9419         return 0;
9420 }
9421
9422 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9423                                                 struct vmcs12 *vmcs12)
9424 {
9425         if (vmcs12->vm_exit_msr_load_count == 0 &&
9426             vmcs12->vm_exit_msr_store_count == 0 &&
9427             vmcs12->vm_entry_msr_load_count == 0)
9428                 return 0; /* Fast path */
9429         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9430                                         VM_EXIT_MSR_LOAD_ADDR) ||
9431             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9432                                         VM_EXIT_MSR_STORE_ADDR) ||
9433             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9434                                         VM_ENTRY_MSR_LOAD_ADDR))
9435                 return -EINVAL;
9436         return 0;
9437 }
9438
9439 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9440                                        struct vmx_msr_entry *e)
9441 {
9442         /* x2APIC MSR accesses are not allowed */
9443         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9444                 return -EINVAL;
9445         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9446             e->index == MSR_IA32_UCODE_REV)
9447                 return -EINVAL;
9448         if (e->reserved != 0)
9449                 return -EINVAL;
9450         return 0;
9451 }
9452
9453 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9454                                      struct vmx_msr_entry *e)
9455 {
9456         if (e->index == MSR_FS_BASE ||
9457             e->index == MSR_GS_BASE ||
9458             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9459             nested_vmx_msr_check_common(vcpu, e))
9460                 return -EINVAL;
9461         return 0;
9462 }
9463
9464 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9465                                       struct vmx_msr_entry *e)
9466 {
9467         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9468             nested_vmx_msr_check_common(vcpu, e))
9469                 return -EINVAL;
9470         return 0;
9471 }
9472
9473 /*
9474  * Load guest's/host's msr at nested entry/exit.
9475  * return 0 for success, entry index for failure.
9476  */
9477 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9478 {
9479         u32 i;
9480         struct vmx_msr_entry e;
9481         struct msr_data msr;
9482
9483         msr.host_initiated = false;
9484         for (i = 0; i < count; i++) {
9485                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9486                                         &e, sizeof(e))) {
9487                         pr_warn_ratelimited(
9488                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9489                                 __func__, i, gpa + i * sizeof(e));
9490                         goto fail;
9491                 }
9492                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9493                         pr_warn_ratelimited(
9494                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9495                                 __func__, i, e.index, e.reserved);
9496                         goto fail;
9497                 }
9498                 msr.index = e.index;
9499                 msr.data = e.value;
9500                 if (kvm_set_msr(vcpu, &msr)) {
9501                         pr_warn_ratelimited(
9502                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9503                                 __func__, i, e.index, e.value);
9504                         goto fail;
9505                 }
9506         }
9507         return 0;
9508 fail:
9509         return i + 1;
9510 }
9511
9512 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9513 {
9514         u32 i;
9515         struct vmx_msr_entry e;
9516
9517         for (i = 0; i < count; i++) {
9518                 struct msr_data msr_info;
9519                 if (kvm_vcpu_read_guest(vcpu,
9520                                         gpa + i * sizeof(e),
9521                                         &e, 2 * sizeof(u32))) {
9522                         pr_warn_ratelimited(
9523                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9524                                 __func__, i, gpa + i * sizeof(e));
9525                         return -EINVAL;
9526                 }
9527                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9528                         pr_warn_ratelimited(
9529                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9530                                 __func__, i, e.index, e.reserved);
9531                         return -EINVAL;
9532                 }
9533                 msr_info.host_initiated = false;
9534                 msr_info.index = e.index;
9535                 if (kvm_get_msr(vcpu, &msr_info)) {
9536                         pr_warn_ratelimited(
9537                                 "%s cannot read MSR (%u, 0x%x)\n",
9538                                 __func__, i, e.index);
9539                         return -EINVAL;
9540                 }
9541                 if (kvm_vcpu_write_guest(vcpu,
9542                                          gpa + i * sizeof(e) +
9543                                              offsetof(struct vmx_msr_entry, value),
9544                                          &msr_info.data, sizeof(msr_info.data))) {
9545                         pr_warn_ratelimited(
9546                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9547                                 __func__, i, e.index, msr_info.data);
9548                         return -EINVAL;
9549                 }
9550         }
9551         return 0;
9552 }
9553
9554 /*
9555  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9556  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9557  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9558  * guest in a way that will both be appropriate to L1's requests, and our
9559  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9560  * function also has additional necessary side-effects, like setting various
9561  * vcpu->arch fields.
9562  */
9563 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9564 {
9565         struct vcpu_vmx *vmx = to_vmx(vcpu);
9566         u32 exec_control;
9567
9568         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9569         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9570         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9571         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9572         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9573         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9574         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9575         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9576         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9577         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9578         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9579         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9580         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9581         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9582         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9583         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9584         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9585         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9586         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9587         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9588         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9589         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9590         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9591         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9592         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9593         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9594         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9595         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9596         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9597         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9598         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9599         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9600         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9601         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9602         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9603         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9604
9605         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9606                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9607                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9608         } else {
9609                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9610                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9611         }
9612         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9613                 vmcs12->vm_entry_intr_info_field);
9614         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9615                 vmcs12->vm_entry_exception_error_code);
9616         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9617                 vmcs12->vm_entry_instruction_len);
9618         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9619                 vmcs12->guest_interruptibility_info);
9620         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9621         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9622         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9623                 vmcs12->guest_pending_dbg_exceptions);
9624         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9625         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9626
9627         if (nested_cpu_has_xsaves(vmcs12))
9628                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9629         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9630
9631         exec_control = vmcs12->pin_based_vm_exec_control;
9632         exec_control |= vmcs_config.pin_based_exec_ctrl;
9633         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9634
9635         if (nested_cpu_has_posted_intr(vmcs12)) {
9636                 /*
9637                  * Note that we use L0's vector here and in
9638                  * vmx_deliver_nested_posted_interrupt.
9639                  */
9640                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9641                 vmx->nested.pi_pending = false;
9642                 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9643                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9644                         page_to_phys(vmx->nested.pi_desc_page) +
9645                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9646                         (PAGE_SIZE - 1)));
9647         } else
9648                 exec_control &= ~PIN_BASED_POSTED_INTR;
9649
9650         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9651
9652         vmx->nested.preemption_timer_expired = false;
9653         if (nested_cpu_has_preemption_timer(vmcs12))
9654                 vmx_start_preemption_timer(vcpu);
9655
9656         /*
9657          * Whether page-faults are trapped is determined by a combination of
9658          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9659          * If enable_ept, L0 doesn't care about page faults and we should
9660          * set all of these to L1's desires. However, if !enable_ept, L0 does
9661          * care about (at least some) page faults, and because it is not easy
9662          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9663          * to exit on each and every L2 page fault. This is done by setting
9664          * MASK=MATCH=0 and (see below) EB.PF=1.
9665          * Note that below we don't need special code to set EB.PF beyond the
9666          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9667          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9668          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9669          *
9670          * A problem with this approach (when !enable_ept) is that L1 may be
9671          * injected with more page faults than it asked for. This could have
9672          * caused problems, but in practice existing hypervisors don't care.
9673          * To fix this, we will need to emulate the PFEC checking (on the L1
9674          * page tables), using walk_addr(), when injecting PFs to L1.
9675          */
9676         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9677                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9678         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9679                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9680
9681         if (cpu_has_secondary_exec_ctrls()) {
9682                 exec_control = vmx_secondary_exec_control(vmx);
9683
9684                 /* Take the following fields only from vmcs12 */
9685                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9686                                   SECONDARY_EXEC_RDTSCP |
9687                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9688                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
9689                                   SECONDARY_EXEC_PCOMMIT);
9690                 if (nested_cpu_has(vmcs12,
9691                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9692                         exec_control |= vmcs12->secondary_vm_exec_control;
9693
9694                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9695                         /*
9696                          * If translation failed, no matter: This feature asks
9697                          * to exit when accessing the given address, and if it
9698                          * can never be accessed, this feature won't do
9699                          * anything anyway.
9700                          */
9701                         if (!vmx->nested.apic_access_page)
9702                                 exec_control &=
9703                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9704                         else
9705                                 vmcs_write64(APIC_ACCESS_ADDR,
9706                                   page_to_phys(vmx->nested.apic_access_page));
9707                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9708                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9709                         exec_control |=
9710                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9711                         kvm_vcpu_reload_apic_access_page(vcpu);
9712                 }
9713
9714                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9715                         vmcs_write64(EOI_EXIT_BITMAP0,
9716                                 vmcs12->eoi_exit_bitmap0);
9717                         vmcs_write64(EOI_EXIT_BITMAP1,
9718                                 vmcs12->eoi_exit_bitmap1);
9719                         vmcs_write64(EOI_EXIT_BITMAP2,
9720                                 vmcs12->eoi_exit_bitmap2);
9721                         vmcs_write64(EOI_EXIT_BITMAP3,
9722                                 vmcs12->eoi_exit_bitmap3);
9723                         vmcs_write16(GUEST_INTR_STATUS,
9724                                 vmcs12->guest_intr_status);
9725                 }
9726
9727                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9728         }
9729
9730
9731         /*
9732          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9733          * Some constant fields are set here by vmx_set_constant_host_state().
9734          * Other fields are different per CPU, and will be set later when
9735          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9736          */
9737         vmx_set_constant_host_state(vmx);
9738
9739         /*
9740          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9741          * entry, but only if the current (host) sp changed from the value
9742          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9743          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9744          * here we just force the write to happen on entry.
9745          */
9746         vmx->host_rsp = 0;
9747
9748         exec_control = vmx_exec_control(vmx); /* L0's desires */
9749         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9750         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9751         exec_control &= ~CPU_BASED_TPR_SHADOW;
9752         exec_control |= vmcs12->cpu_based_vm_exec_control;
9753
9754         if (exec_control & CPU_BASED_TPR_SHADOW) {
9755                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9756                                 page_to_phys(vmx->nested.virtual_apic_page));
9757                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9758         }
9759
9760         if (cpu_has_vmx_msr_bitmap() &&
9761             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9762                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9763                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9764         } else
9765                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9766
9767         /*
9768          * Merging of IO bitmap not currently supported.
9769          * Rather, exit every time.
9770          */
9771         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9772         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9773
9774         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9775
9776         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9777          * bitwise-or of what L1 wants to trap for L2, and what we want to
9778          * trap. Note that CR0.TS also needs updating - we do this later.
9779          */
9780         update_exception_bitmap(vcpu);
9781         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9782         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9783
9784         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9785          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9786          * bits are further modified by vmx_set_efer() below.
9787          */
9788         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9789
9790         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9791          * emulated by vmx_set_efer(), below.
9792          */
9793         vm_entry_controls_init(vmx,
9794                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9795                         ~VM_ENTRY_IA32E_MODE) |
9796                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9797
9798         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9799                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9800                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9801         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9802                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9803
9804
9805         set_cr4_guest_host_mask(vmx);
9806
9807         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9808                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9809
9810         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9811                 vmcs_write64(TSC_OFFSET,
9812                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9813         else
9814                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9815
9816         if (enable_vpid) {
9817                 /*
9818                  * There is no direct mapping between vpid02 and vpid12, the
9819                  * vpid02 is per-vCPU for L0 and reused while the value of
9820                  * vpid12 is changed w/ one invvpid during nested vmentry.
9821                  * The vpid12 is allocated by L1 for L2, so it will not
9822                  * influence global bitmap(for vpid01 and vpid02 allocation)
9823                  * even if spawn a lot of nested vCPUs.
9824                  */
9825                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9826                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9827                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9828                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9829                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9830                         }
9831                 } else {
9832                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9833                         vmx_flush_tlb(vcpu);
9834                 }
9835
9836         }
9837
9838         if (nested_cpu_has_ept(vmcs12)) {
9839                 kvm_mmu_unload(vcpu);
9840                 nested_ept_init_mmu_context(vcpu);
9841         }
9842
9843         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9844                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9845         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9846                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9847         else
9848                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9849         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9850         vmx_set_efer(vcpu, vcpu->arch.efer);
9851
9852         /*
9853          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9854          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9855          * The CR0_READ_SHADOW is what L2 should have expected to read given
9856          * the specifications by L1; It's not enough to take
9857          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9858          * have more bits than L1 expected.
9859          */
9860         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9861         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9862
9863         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9864         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9865
9866         /* shadow page tables on either EPT or shadow page tables */
9867         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9868         kvm_mmu_reset_context(vcpu);
9869
9870         if (!enable_ept)
9871                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9872
9873         /*
9874          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9875          */
9876         if (enable_ept) {
9877                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9878                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9879                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9880                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9881         }
9882
9883         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9884         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9885 }
9886
9887 /*
9888  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9889  * for running an L2 nested guest.
9890  */
9891 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9892 {
9893         struct vmcs12 *vmcs12;
9894         struct vcpu_vmx *vmx = to_vmx(vcpu);
9895         int cpu;
9896         struct loaded_vmcs *vmcs02;
9897         bool ia32e;
9898         u32 msr_entry_idx;
9899
9900         if (!nested_vmx_check_permission(vcpu) ||
9901             !nested_vmx_check_vmcs12(vcpu))
9902                 return 1;
9903
9904         skip_emulated_instruction(vcpu);
9905         vmcs12 = get_vmcs12(vcpu);
9906
9907         if (enable_shadow_vmcs)
9908                 copy_shadow_to_vmcs12(vmx);
9909
9910         /*
9911          * The nested entry process starts with enforcing various prerequisites
9912          * on vmcs12 as required by the Intel SDM, and act appropriately when
9913          * they fail: As the SDM explains, some conditions should cause the
9914          * instruction to fail, while others will cause the instruction to seem
9915          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9916          * To speed up the normal (success) code path, we should avoid checking
9917          * for misconfigurations which will anyway be caught by the processor
9918          * when using the merged vmcs02.
9919          */
9920         if (vmcs12->launch_state == launch) {
9921                 nested_vmx_failValid(vcpu,
9922                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9923                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9924                 return 1;
9925         }
9926
9927         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9928             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9929                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9930                 return 1;
9931         }
9932
9933         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9934                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9935                 return 1;
9936         }
9937
9938         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9939                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9940                 return 1;
9941         }
9942
9943         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9944                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9945                 return 1;
9946         }
9947
9948         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9949                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9950                 return 1;
9951         }
9952
9953         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9954                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9955                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9956             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9957                                 vmx->nested.nested_vmx_secondary_ctls_low,
9958                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9959             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9960                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9961                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9962             !vmx_control_verify(vmcs12->vm_exit_controls,
9963                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9964                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9965             !vmx_control_verify(vmcs12->vm_entry_controls,
9966                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9967                                 vmx->nested.nested_vmx_entry_ctls_high))
9968         {
9969                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9970                 return 1;
9971         }
9972
9973         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9974             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9975                 nested_vmx_failValid(vcpu,
9976                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9977                 return 1;
9978         }
9979
9980         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9981             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9982                 nested_vmx_entry_failure(vcpu, vmcs12,
9983                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9984                 return 1;
9985         }
9986         if (vmcs12->vmcs_link_pointer != -1ull) {
9987                 nested_vmx_entry_failure(vcpu, vmcs12,
9988                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9989                 return 1;
9990         }
9991
9992         /*
9993          * If the load IA32_EFER VM-entry control is 1, the following checks
9994          * are performed on the field for the IA32_EFER MSR:
9995          * - Bits reserved in the IA32_EFER MSR must be 0.
9996          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9997          *   the IA-32e mode guest VM-exit control. It must also be identical
9998          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9999          *   CR0.PG) is 1.
10000          */
10001         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
10002                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
10003                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
10004                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
10005                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
10006                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
10007                         nested_vmx_entry_failure(vcpu, vmcs12,
10008                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10009                         return 1;
10010                 }
10011         }
10012
10013         /*
10014          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
10015          * IA32_EFER MSR must be 0 in the field for that register. In addition,
10016          * the values of the LMA and LME bits in the field must each be that of
10017          * the host address-space size VM-exit control.
10018          */
10019         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
10020                 ia32e = (vmcs12->vm_exit_controls &
10021                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
10022                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
10023                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
10024                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
10025                         nested_vmx_entry_failure(vcpu, vmcs12,
10026                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
10027                         return 1;
10028                 }
10029         }
10030
10031         /*
10032          * We're finally done with prerequisite checking, and can start with
10033          * the nested entry.
10034          */
10035
10036         vmcs02 = nested_get_current_vmcs02(vmx);
10037         if (!vmcs02)
10038                 return -ENOMEM;
10039
10040         enter_guest_mode(vcpu);
10041
10042         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
10043
10044         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
10045                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10046
10047         cpu = get_cpu();
10048         vmx->loaded_vmcs = vmcs02;
10049         vmx_vcpu_put(vcpu);
10050         vmx_vcpu_load(vcpu, cpu);
10051         vcpu->cpu = cpu;
10052         put_cpu();
10053
10054         vmx_segment_cache_clear(vmx);
10055
10056         prepare_vmcs02(vcpu, vmcs12);
10057
10058         msr_entry_idx = nested_vmx_load_msr(vcpu,
10059                                             vmcs12->vm_entry_msr_load_addr,
10060                                             vmcs12->vm_entry_msr_load_count);
10061         if (msr_entry_idx) {
10062                 leave_guest_mode(vcpu);
10063                 vmx_load_vmcs01(vcpu);
10064                 nested_vmx_entry_failure(vcpu, vmcs12,
10065                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
10066                 return 1;
10067         }
10068
10069         vmcs12->launch_state = 1;
10070
10071         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
10072                 return kvm_vcpu_halt(vcpu);
10073
10074         vmx->nested.nested_run_pending = 1;
10075
10076         /*
10077          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
10078          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
10079          * returned as far as L1 is concerned. It will only return (and set
10080          * the success flag) when L2 exits (see nested_vmx_vmexit()).
10081          */
10082         return 1;
10083 }
10084
10085 /*
10086  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
10087  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
10088  * This function returns the new value we should put in vmcs12.guest_cr0.
10089  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
10090  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
10091  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
10092  *     didn't trap the bit, because if L1 did, so would L0).
10093  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
10094  *     been modified by L2, and L1 knows it. So just leave the old value of
10095  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10096  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10097  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10098  *     changed these bits, and therefore they need to be updated, but L0
10099  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10100  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10101  */
10102 static inline unsigned long
10103 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10104 {
10105         return
10106         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10107         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10108         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10109                         vcpu->arch.cr0_guest_owned_bits));
10110 }
10111
10112 static inline unsigned long
10113 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10114 {
10115         return
10116         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10117         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10118         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10119                         vcpu->arch.cr4_guest_owned_bits));
10120 }
10121
10122 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10123                                        struct vmcs12 *vmcs12)
10124 {
10125         u32 idt_vectoring;
10126         unsigned int nr;
10127
10128         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10129                 nr = vcpu->arch.exception.nr;
10130                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10131
10132                 if (kvm_exception_is_soft(nr)) {
10133                         vmcs12->vm_exit_instruction_len =
10134                                 vcpu->arch.event_exit_inst_len;
10135                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10136                 } else
10137                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10138
10139                 if (vcpu->arch.exception.has_error_code) {
10140                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10141                         vmcs12->idt_vectoring_error_code =
10142                                 vcpu->arch.exception.error_code;
10143                 }
10144
10145                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10146         } else if (vcpu->arch.nmi_injected) {
10147                 vmcs12->idt_vectoring_info_field =
10148                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10149         } else if (vcpu->arch.interrupt.pending) {
10150                 nr = vcpu->arch.interrupt.nr;
10151                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10152
10153                 if (vcpu->arch.interrupt.soft) {
10154                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10155                         vmcs12->vm_entry_instruction_len =
10156                                 vcpu->arch.event_exit_inst_len;
10157                 } else
10158                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10159
10160                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10161         }
10162 }
10163
10164 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10165 {
10166         struct vcpu_vmx *vmx = to_vmx(vcpu);
10167
10168         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10169             vmx->nested.preemption_timer_expired) {
10170                 if (vmx->nested.nested_run_pending)
10171                         return -EBUSY;
10172                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10173                 return 0;
10174         }
10175
10176         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10177                 if (vmx->nested.nested_run_pending ||
10178                     vcpu->arch.interrupt.pending)
10179                         return -EBUSY;
10180                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10181                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10182                                   INTR_INFO_VALID_MASK, 0);
10183                 /*
10184                  * The NMI-triggered VM exit counts as injection:
10185                  * clear this one and block further NMIs.
10186                  */
10187                 vcpu->arch.nmi_pending = 0;
10188                 vmx_set_nmi_mask(vcpu, true);
10189                 return 0;
10190         }
10191
10192         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10193             nested_exit_on_intr(vcpu)) {
10194                 if (vmx->nested.nested_run_pending)
10195                         return -EBUSY;
10196                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10197                 return 0;
10198         }
10199
10200         return vmx_complete_nested_posted_interrupt(vcpu);
10201 }
10202
10203 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10204 {
10205         ktime_t remaining =
10206                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10207         u64 value;
10208
10209         if (ktime_to_ns(remaining) <= 0)
10210                 return 0;
10211
10212         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10213         do_div(value, 1000000);
10214         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10215 }
10216
10217 /*
10218  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10219  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10220  * and this function updates it to reflect the changes to the guest state while
10221  * L2 was running (and perhaps made some exits which were handled directly by L0
10222  * without going back to L1), and to reflect the exit reason.
10223  * Note that we do not have to copy here all VMCS fields, just those that
10224  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10225  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10226  * which already writes to vmcs12 directly.
10227  */
10228 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10229                            u32 exit_reason, u32 exit_intr_info,
10230                            unsigned long exit_qualification)
10231 {
10232         /* update guest state fields: */
10233         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10234         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10235
10236         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10237         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10238         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10239
10240         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10241         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10242         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10243         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10244         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10245         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10246         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10247         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10248         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10249         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10250         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10251         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10252         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10253         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10254         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10255         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10256         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10257         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10258         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10259         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10260         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10261         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10262         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10263         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10264         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10265         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10266         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10267         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10268         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10269         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10270         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10271         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10272         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10273         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10274         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10275         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10276
10277         vmcs12->guest_interruptibility_info =
10278                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10279         vmcs12->guest_pending_dbg_exceptions =
10280                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10281         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10282                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10283         else
10284                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10285
10286         if (nested_cpu_has_preemption_timer(vmcs12)) {
10287                 if (vmcs12->vm_exit_controls &
10288                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10289                         vmcs12->vmx_preemption_timer_value =
10290                                 vmx_get_preemption_timer_value(vcpu);
10291                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10292         }
10293
10294         /*
10295          * In some cases (usually, nested EPT), L2 is allowed to change its
10296          * own CR3 without exiting. If it has changed it, we must keep it.
10297          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10298          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10299          *
10300          * Additionally, restore L2's PDPTR to vmcs12.
10301          */
10302         if (enable_ept) {
10303                 vmcs12->guest_cr3 = vmcs_readl(GUEST_CR3);
10304                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10305                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10306                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10307                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10308         }
10309
10310         if (nested_cpu_has_vid(vmcs12))
10311                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10312
10313         vmcs12->vm_entry_controls =
10314                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10315                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10316
10317         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10318                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10319                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10320         }
10321
10322         /* TODO: These cannot have changed unless we have MSR bitmaps and
10323          * the relevant bit asks not to trap the change */
10324         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10325                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10326         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10327                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10328         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10329         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10330         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10331         if (kvm_mpx_supported())
10332                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10333         if (nested_cpu_has_xsaves(vmcs12))
10334                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10335
10336         /* update exit information fields: */
10337
10338         vmcs12->vm_exit_reason = exit_reason;
10339         vmcs12->exit_qualification = exit_qualification;
10340
10341         vmcs12->vm_exit_intr_info = exit_intr_info;
10342         if ((vmcs12->vm_exit_intr_info &
10343              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10344             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10345                 vmcs12->vm_exit_intr_error_code =
10346                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10347         vmcs12->idt_vectoring_info_field = 0;
10348         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10349         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10350
10351         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10352                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10353                  * instead of reading the real value. */
10354                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10355
10356                 /*
10357                  * Transfer the event that L0 or L1 may wanted to inject into
10358                  * L2 to IDT_VECTORING_INFO_FIELD.
10359                  */
10360                 vmcs12_save_pending_event(vcpu, vmcs12);
10361         }
10362
10363         /*
10364          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10365          * preserved above and would only end up incorrectly in L1.
10366          */
10367         vcpu->arch.nmi_injected = false;
10368         kvm_clear_exception_queue(vcpu);
10369         kvm_clear_interrupt_queue(vcpu);
10370 }
10371
10372 /*
10373  * A part of what we need to when the nested L2 guest exits and we want to
10374  * run its L1 parent, is to reset L1's guest state to the host state specified
10375  * in vmcs12.
10376  * This function is to be called not only on normal nested exit, but also on
10377  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10378  * Failures During or After Loading Guest State").
10379  * This function should be called when the active VMCS is L1's (vmcs01).
10380  */
10381 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10382                                    struct vmcs12 *vmcs12)
10383 {
10384         struct kvm_segment seg;
10385
10386         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10387                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10388         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10389                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10390         else
10391                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10392         vmx_set_efer(vcpu, vcpu->arch.efer);
10393
10394         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10395         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10396         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10397         /*
10398          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10399          * actually changed, because it depends on the current state of
10400          * fpu_active (which may have changed).
10401          * Note that vmx_set_cr0 refers to efer set above.
10402          */
10403         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10404         /*
10405          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10406          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10407          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10408          */
10409         update_exception_bitmap(vcpu);
10410         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10411         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10412
10413         /*
10414          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10415          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10416          */
10417         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10418         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10419
10420         nested_ept_uninit_mmu_context(vcpu);
10421
10422         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10423         kvm_mmu_reset_context(vcpu);
10424
10425         if (!enable_ept)
10426                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10427
10428         if (enable_vpid) {
10429                 /*
10430                  * Trivially support vpid by letting L2s share their parent
10431                  * L1's vpid. TODO: move to a more elaborate solution, giving
10432                  * each L2 its own vpid and exposing the vpid feature to L1.
10433                  */
10434                 vmx_flush_tlb(vcpu);
10435         }
10436
10437
10438         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10439         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10440         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10441         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10442         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10443
10444         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10445         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10446                 vmcs_write64(GUEST_BNDCFGS, 0);
10447
10448         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10449                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10450                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10451         }
10452         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10453                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10454                         vmcs12->host_ia32_perf_global_ctrl);
10455
10456         /* Set L1 segment info according to Intel SDM
10457             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10458         seg = (struct kvm_segment) {
10459                 .base = 0,
10460                 .limit = 0xFFFFFFFF,
10461                 .selector = vmcs12->host_cs_selector,
10462                 .type = 11,
10463                 .present = 1,
10464                 .s = 1,
10465                 .g = 1
10466         };
10467         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10468                 seg.l = 1;
10469         else
10470                 seg.db = 1;
10471         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10472         seg = (struct kvm_segment) {
10473                 .base = 0,
10474                 .limit = 0xFFFFFFFF,
10475                 .type = 3,
10476                 .present = 1,
10477                 .s = 1,
10478                 .db = 1,
10479                 .g = 1
10480         };
10481         seg.selector = vmcs12->host_ds_selector;
10482         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10483         seg.selector = vmcs12->host_es_selector;
10484         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10485         seg.selector = vmcs12->host_ss_selector;
10486         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10487         seg.selector = vmcs12->host_fs_selector;
10488         seg.base = vmcs12->host_fs_base;
10489         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10490         seg.selector = vmcs12->host_gs_selector;
10491         seg.base = vmcs12->host_gs_base;
10492         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10493         seg = (struct kvm_segment) {
10494                 .base = vmcs12->host_tr_base,
10495                 .limit = 0x67,
10496                 .selector = vmcs12->host_tr_selector,
10497                 .type = 11,
10498                 .present = 1
10499         };
10500         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10501
10502         kvm_set_dr(vcpu, 7, 0x400);
10503         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10504
10505         if (cpu_has_vmx_msr_bitmap())
10506                 vmx_set_msr_bitmap(vcpu);
10507
10508         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10509                                 vmcs12->vm_exit_msr_load_count))
10510                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10511 }
10512
10513 /*
10514  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10515  * and modify vmcs12 to make it see what it would expect to see there if
10516  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10517  */
10518 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10519                               u32 exit_intr_info,
10520                               unsigned long exit_qualification)
10521 {
10522         struct vcpu_vmx *vmx = to_vmx(vcpu);
10523         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10524
10525         /* trying to cancel vmlaunch/vmresume is a bug */
10526         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10527
10528         leave_guest_mode(vcpu);
10529         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10530                        exit_qualification);
10531
10532         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10533                                  vmcs12->vm_exit_msr_store_count))
10534                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10535
10536         vmx_load_vmcs01(vcpu);
10537
10538         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10539             && nested_exit_intr_ack_set(vcpu)) {
10540                 int irq = kvm_cpu_get_interrupt(vcpu);
10541                 WARN_ON(irq < 0);
10542                 vmcs12->vm_exit_intr_info = irq |
10543                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10544         }
10545
10546         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10547                                        vmcs12->exit_qualification,
10548                                        vmcs12->idt_vectoring_info_field,
10549                                        vmcs12->vm_exit_intr_info,
10550                                        vmcs12->vm_exit_intr_error_code,
10551                                        KVM_ISA_VMX);
10552
10553         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10554         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10555         vmx_segment_cache_clear(vmx);
10556
10557         /* if no vmcs02 cache requested, remove the one we used */
10558         if (VMCS02_POOL_SIZE == 0)
10559                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10560
10561         load_vmcs12_host_state(vcpu, vmcs12);
10562
10563         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10564         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10565
10566         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10567         vmx->host_rsp = 0;
10568
10569         /* Unpin physical memory we referred to in vmcs02 */
10570         if (vmx->nested.apic_access_page) {
10571                 nested_release_page(vmx->nested.apic_access_page);
10572                 vmx->nested.apic_access_page = NULL;
10573         }
10574         if (vmx->nested.virtual_apic_page) {
10575                 nested_release_page(vmx->nested.virtual_apic_page);
10576                 vmx->nested.virtual_apic_page = NULL;
10577         }
10578         if (vmx->nested.pi_desc_page) {
10579                 kunmap(vmx->nested.pi_desc_page);
10580                 nested_release_page(vmx->nested.pi_desc_page);
10581                 vmx->nested.pi_desc_page = NULL;
10582                 vmx->nested.pi_desc = NULL;
10583         }
10584
10585         /*
10586          * We are now running in L2, mmu_notifier will force to reload the
10587          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10588          */
10589         kvm_vcpu_reload_apic_access_page(vcpu);
10590
10591         /*
10592          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10593          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10594          * success or failure flag accordingly.
10595          */
10596         if (unlikely(vmx->fail)) {
10597                 vmx->fail = 0;
10598                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10599         } else
10600                 nested_vmx_succeed(vcpu);
10601         if (enable_shadow_vmcs)
10602                 vmx->nested.sync_shadow_vmcs = true;
10603
10604         /* in case we halted in L2 */
10605         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10606 }
10607
10608 /*
10609  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10610  */
10611 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10612 {
10613         if (is_guest_mode(vcpu))
10614                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10615         free_nested(to_vmx(vcpu));
10616 }
10617
10618 /*
10619  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10620  * 23.7 "VM-entry failures during or after loading guest state" (this also
10621  * lists the acceptable exit-reason and exit-qualification parameters).
10622  * It should only be called before L2 actually succeeded to run, and when
10623  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10624  */
10625 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10626                         struct vmcs12 *vmcs12,
10627                         u32 reason, unsigned long qualification)
10628 {
10629         load_vmcs12_host_state(vcpu, vmcs12);
10630         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10631         vmcs12->exit_qualification = qualification;
10632         nested_vmx_succeed(vcpu);
10633         if (enable_shadow_vmcs)
10634                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10635 }
10636
10637 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10638                                struct x86_instruction_info *info,
10639                                enum x86_intercept_stage stage)
10640 {
10641         return X86EMUL_CONTINUE;
10642 }
10643
10644 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10645 {
10646         if (ple_gap)
10647                 shrink_ple_window(vcpu);
10648 }
10649
10650 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10651                                      struct kvm_memory_slot *slot)
10652 {
10653         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10654         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10655 }
10656
10657 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10658                                        struct kvm_memory_slot *slot)
10659 {
10660         kvm_mmu_slot_set_dirty(kvm, slot);
10661 }
10662
10663 static void vmx_flush_log_dirty(struct kvm *kvm)
10664 {
10665         kvm_flush_pml_buffers(kvm);
10666 }
10667
10668 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10669                                            struct kvm_memory_slot *memslot,
10670                                            gfn_t offset, unsigned long mask)
10671 {
10672         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10673 }
10674
10675 /*
10676  * This routine does the following things for vCPU which is going
10677  * to be blocked if VT-d PI is enabled.
10678  * - Store the vCPU to the wakeup list, so when interrupts happen
10679  *   we can find the right vCPU to wake up.
10680  * - Change the Posted-interrupt descriptor as below:
10681  *      'NDST' <-- vcpu->pre_pcpu
10682  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10683  * - If 'ON' is set during this process, which means at least one
10684  *   interrupt is posted for this vCPU, we cannot block it, in
10685  *   this case, return 1, otherwise, return 0.
10686  *
10687  */
10688 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10689 {
10690         unsigned long flags;
10691         unsigned int dest;
10692         struct pi_desc old, new;
10693         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10694
10695         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10696                 !irq_remapping_cap(IRQ_POSTING_CAP))
10697                 return 0;
10698
10699         vcpu->pre_pcpu = vcpu->cpu;
10700         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10701                           vcpu->pre_pcpu), flags);
10702         list_add_tail(&vcpu->blocked_vcpu_list,
10703                       &per_cpu(blocked_vcpu_on_cpu,
10704                       vcpu->pre_pcpu));
10705         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10706                                vcpu->pre_pcpu), flags);
10707
10708         do {
10709                 old.control = new.control = pi_desc->control;
10710
10711                 /*
10712                  * We should not block the vCPU if
10713                  * an interrupt is posted for it.
10714                  */
10715                 if (pi_test_on(pi_desc) == 1) {
10716                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10717                                           vcpu->pre_pcpu), flags);
10718                         list_del(&vcpu->blocked_vcpu_list);
10719                         spin_unlock_irqrestore(
10720                                         &per_cpu(blocked_vcpu_on_cpu_lock,
10721                                         vcpu->pre_pcpu), flags);
10722                         vcpu->pre_pcpu = -1;
10723
10724                         return 1;
10725                 }
10726
10727                 WARN((pi_desc->sn == 1),
10728                      "Warning: SN field of posted-interrupts "
10729                      "is set before blocking\n");
10730
10731                 /*
10732                  * Since vCPU can be preempted during this process,
10733                  * vcpu->cpu could be different with pre_pcpu, we
10734                  * need to set pre_pcpu as the destination of wakeup
10735                  * notification event, then we can find the right vCPU
10736                  * to wakeup in wakeup handler if interrupts happen
10737                  * when the vCPU is in blocked state.
10738                  */
10739                 dest = cpu_physical_id(vcpu->pre_pcpu);
10740
10741                 if (x2apic_enabled())
10742                         new.ndst = dest;
10743                 else
10744                         new.ndst = (dest << 8) & 0xFF00;
10745
10746                 /* set 'NV' to 'wakeup vector' */
10747                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10748         } while (cmpxchg(&pi_desc->control, old.control,
10749                         new.control) != old.control);
10750
10751         return 0;
10752 }
10753
10754 static void vmx_post_block(struct kvm_vcpu *vcpu)
10755 {
10756         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10757         struct pi_desc old, new;
10758         unsigned int dest;
10759         unsigned long flags;
10760
10761         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10762                 !irq_remapping_cap(IRQ_POSTING_CAP))
10763                 return;
10764
10765         do {
10766                 old.control = new.control = pi_desc->control;
10767
10768                 dest = cpu_physical_id(vcpu->cpu);
10769
10770                 if (x2apic_enabled())
10771                         new.ndst = dest;
10772                 else
10773                         new.ndst = (dest << 8) & 0xFF00;
10774
10775                 /* Allow posting non-urgent interrupts */
10776                 new.sn = 0;
10777
10778                 /* set 'NV' to 'notification vector' */
10779                 new.nv = POSTED_INTR_VECTOR;
10780         } while (cmpxchg(&pi_desc->control, old.control,
10781                         new.control) != old.control);
10782
10783         if(vcpu->pre_pcpu != -1) {
10784                 spin_lock_irqsave(
10785                         &per_cpu(blocked_vcpu_on_cpu_lock,
10786                         vcpu->pre_pcpu), flags);
10787                 list_del(&vcpu->blocked_vcpu_list);
10788                 spin_unlock_irqrestore(
10789                         &per_cpu(blocked_vcpu_on_cpu_lock,
10790                         vcpu->pre_pcpu), flags);
10791                 vcpu->pre_pcpu = -1;
10792         }
10793 }
10794
10795 /*
10796  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10797  *
10798  * @kvm: kvm
10799  * @host_irq: host irq of the interrupt
10800  * @guest_irq: gsi of the interrupt
10801  * @set: set or unset PI
10802  * returns 0 on success, < 0 on failure
10803  */
10804 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10805                               uint32_t guest_irq, bool set)
10806 {
10807         struct kvm_kernel_irq_routing_entry *e;
10808         struct kvm_irq_routing_table *irq_rt;
10809         struct kvm_lapic_irq irq;
10810         struct kvm_vcpu *vcpu;
10811         struct vcpu_data vcpu_info;
10812         int idx, ret = -EINVAL;
10813
10814         if (!kvm_arch_has_assigned_device(kvm) ||
10815                 !irq_remapping_cap(IRQ_POSTING_CAP))
10816                 return 0;
10817
10818         idx = srcu_read_lock(&kvm->irq_srcu);
10819         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10820         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10821
10822         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10823                 if (e->type != KVM_IRQ_ROUTING_MSI)
10824                         continue;
10825                 /*
10826                  * VT-d PI cannot support posting multicast/broadcast
10827                  * interrupts to a vCPU, we still use interrupt remapping
10828                  * for these kind of interrupts.
10829                  *
10830                  * For lowest-priority interrupts, we only support
10831                  * those with single CPU as the destination, e.g. user
10832                  * configures the interrupts via /proc/irq or uses
10833                  * irqbalance to make the interrupts single-CPU.
10834                  *
10835                  * We will support full lowest-priority interrupt later.
10836                  */
10837
10838                 kvm_set_msi_irq(e, &irq);
10839                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
10840                         /*
10841                          * Make sure the IRTE is in remapped mode if
10842                          * we don't handle it in posted mode.
10843                          */
10844                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10845                         if (ret < 0) {
10846                                 printk(KERN_INFO
10847                                    "failed to back to remapped mode, irq: %u\n",
10848                                    host_irq);
10849                                 goto out;
10850                         }
10851
10852                         continue;
10853                 }
10854
10855                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10856                 vcpu_info.vector = irq.vector;
10857
10858                 trace_kvm_pi_irte_update(vcpu->vcpu_id, host_irq, e->gsi,
10859                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10860
10861                 if (set)
10862                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10863                 else {
10864                         /* suppress notification event before unposting */
10865                         pi_set_sn(vcpu_to_pi_desc(vcpu));
10866                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10867                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
10868                 }
10869
10870                 if (ret < 0) {
10871                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
10872                                         __func__);
10873                         goto out;
10874                 }
10875         }
10876
10877         ret = 0;
10878 out:
10879         srcu_read_unlock(&kvm->irq_srcu, idx);
10880         return ret;
10881 }
10882
10883 static struct kvm_x86_ops vmx_x86_ops = {
10884         .cpu_has_kvm_support = cpu_has_kvm_support,
10885         .disabled_by_bios = vmx_disabled_by_bios,
10886         .hardware_setup = hardware_setup,
10887         .hardware_unsetup = hardware_unsetup,
10888         .check_processor_compatibility = vmx_check_processor_compat,
10889         .hardware_enable = hardware_enable,
10890         .hardware_disable = hardware_disable,
10891         .cpu_has_accelerated_tpr = report_flexpriority,
10892         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
10893
10894         .vcpu_create = vmx_create_vcpu,
10895         .vcpu_free = vmx_free_vcpu,
10896         .vcpu_reset = vmx_vcpu_reset,
10897
10898         .prepare_guest_switch = vmx_save_host_state,
10899         .vcpu_load = vmx_vcpu_load,
10900         .vcpu_put = vmx_vcpu_put,
10901
10902         .update_bp_intercept = update_exception_bitmap,
10903         .get_msr = vmx_get_msr,
10904         .set_msr = vmx_set_msr,
10905         .get_segment_base = vmx_get_segment_base,
10906         .get_segment = vmx_get_segment,
10907         .set_segment = vmx_set_segment,
10908         .get_cpl = vmx_get_cpl,
10909         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10910         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10911         .decache_cr3 = vmx_decache_cr3,
10912         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10913         .set_cr0 = vmx_set_cr0,
10914         .set_cr3 = vmx_set_cr3,
10915         .set_cr4 = vmx_set_cr4,
10916         .set_efer = vmx_set_efer,
10917         .get_idt = vmx_get_idt,
10918         .set_idt = vmx_set_idt,
10919         .get_gdt = vmx_get_gdt,
10920         .set_gdt = vmx_set_gdt,
10921         .get_dr6 = vmx_get_dr6,
10922         .set_dr6 = vmx_set_dr6,
10923         .set_dr7 = vmx_set_dr7,
10924         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10925         .cache_reg = vmx_cache_reg,
10926         .get_rflags = vmx_get_rflags,
10927         .set_rflags = vmx_set_rflags,
10928         .fpu_activate = vmx_fpu_activate,
10929         .fpu_deactivate = vmx_fpu_deactivate,
10930
10931         .tlb_flush = vmx_flush_tlb,
10932
10933         .run = vmx_vcpu_run,
10934         .handle_exit = vmx_handle_exit,
10935         .skip_emulated_instruction = skip_emulated_instruction,
10936         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10937         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10938         .patch_hypercall = vmx_patch_hypercall,
10939         .set_irq = vmx_inject_irq,
10940         .set_nmi = vmx_inject_nmi,
10941         .queue_exception = vmx_queue_exception,
10942         .cancel_injection = vmx_cancel_injection,
10943         .interrupt_allowed = vmx_interrupt_allowed,
10944         .nmi_allowed = vmx_nmi_allowed,
10945         .get_nmi_mask = vmx_get_nmi_mask,
10946         .set_nmi_mask = vmx_set_nmi_mask,
10947         .enable_nmi_window = enable_nmi_window,
10948         .enable_irq_window = enable_irq_window,
10949         .update_cr8_intercept = update_cr8_intercept,
10950         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10951         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10952         .get_enable_apicv = vmx_get_enable_apicv,
10953         .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
10954         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10955         .hwapic_irr_update = vmx_hwapic_irr_update,
10956         .hwapic_isr_update = vmx_hwapic_isr_update,
10957         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10958         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10959
10960         .set_tss_addr = vmx_set_tss_addr,
10961         .get_tdp_level = get_ept_level,
10962         .get_mt_mask = vmx_get_mt_mask,
10963
10964         .get_exit_info = vmx_get_exit_info,
10965
10966         .get_lpage_level = vmx_get_lpage_level,
10967
10968         .cpuid_update = vmx_cpuid_update,
10969
10970         .rdtscp_supported = vmx_rdtscp_supported,
10971         .invpcid_supported = vmx_invpcid_supported,
10972
10973         .set_supported_cpuid = vmx_set_supported_cpuid,
10974
10975         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10976
10977         .read_tsc_offset = vmx_read_tsc_offset,
10978         .write_tsc_offset = vmx_write_tsc_offset,
10979         .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
10980         .read_l1_tsc = vmx_read_l1_tsc,
10981
10982         .set_tdp_cr3 = vmx_set_cr3,
10983
10984         .check_intercept = vmx_check_intercept,
10985         .handle_external_intr = vmx_handle_external_intr,
10986         .mpx_supported = vmx_mpx_supported,
10987         .xsaves_supported = vmx_xsaves_supported,
10988
10989         .check_nested_events = vmx_check_nested_events,
10990
10991         .sched_in = vmx_sched_in,
10992
10993         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10994         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10995         .flush_log_dirty = vmx_flush_log_dirty,
10996         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10997
10998         .pre_block = vmx_pre_block,
10999         .post_block = vmx_post_block,
11000
11001         .pmu_ops = &intel_pmu_ops,
11002
11003         .update_pi_irte = vmx_update_pi_irte,
11004 };
11005
11006 static int __init vmx_init(void)
11007 {
11008         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
11009                      __alignof__(struct vcpu_vmx), THIS_MODULE);
11010         if (r)
11011                 return r;
11012
11013 #ifdef CONFIG_KEXEC_CORE
11014         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
11015                            crash_vmclear_local_loaded_vmcss);
11016 #endif
11017
11018         return 0;
11019 }
11020
11021 static void __exit vmx_exit(void)
11022 {
11023 #ifdef CONFIG_KEXEC_CORE
11024         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
11025         synchronize_rcu();
11026 #endif
11027
11028         kvm_exit();
11029 }
11030
11031 module_init(vmx_init)
11032 module_exit(vmx_exit)