arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "cpuid.h"
  22
  23 #include <linux/kvm_host.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/mm.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29 #include <linux/moduleparam.h>
  30 #include <linux/mod_devicetable.h>
  31 #include <linux/trace_events.h>
  32 #include <linux/slab.h>
  33 #include <linux/tboot.h>
  34 #include <linux/hrtimer.h>
  35 #include "kvm_cache_regs.h"
  36 #include "x86.h"
  37
  38 #include <asm/cpu.h>
  39 #include <asm/io.h>
  40 #include <asm/desc.h>
  41 #include <asm/vmx.h>
  42 #include <asm/virtext.h>
  43 #include <asm/mce.h>
  44 #include <asm/fpu/internal.h>
  45 #include <asm/perf_event.h>
  46 #include <asm/debugreg.h>
  47 #include <asm/kexec.h>
  48 #include <asm/apic.h>
  49 #include <asm/irq_remapping.h>
  50
  51 #include "trace.h"
  52 #include "pmu.h"
  53
  54 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  55 #define __ex_clear(x, reg) \
  56         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  57
  58 MODULE_AUTHOR("Qumranet");
  59 MODULE_LICENSE("GPL");
  60
  61 static const struct x86_cpu_id vmx_cpu_id[] = {
  62         X86_FEATURE_MATCH(X86_FEATURE_VMX),
  63         {}
  64 };
  65 MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
  66
  67 static bool __read_mostly enable_vpid = 1;
  68 module_param_named(vpid, enable_vpid, bool, 0444);
  69
  70 static bool __read_mostly flexpriority_enabled = 1;
  71 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  72
  73 static bool __read_mostly enable_ept = 1;
  74 module_param_named(ept, enable_ept, bool, S_IRUGO);
  75
  76 static bool __read_mostly enable_unrestricted_guest = 1;
  77 module_param_named(unrestricted_guest,
  78                         enable_unrestricted_guest, bool, S_IRUGO);
  79
  80 static bool __read_mostly enable_ept_ad_bits = 1;
  81 module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
  82
  83 static bool __read_mostly emulate_invalid_guest_state = true;
  84 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  85
  86 static bool __read_mostly vmm_exclusive = 1;
  87 module_param(vmm_exclusive, bool, S_IRUGO);
  88
  89 static bool __read_mostly fasteoi = 1;
  90 module_param(fasteoi, bool, S_IRUGO);
  91
  92 static bool __read_mostly enable_apicv = 1;
  93 module_param(enable_apicv, bool, S_IRUGO);
  94
  95 static bool __read_mostly enable_shadow_vmcs = 1;
  96 module_param_named(enable_shadow_vmcs, enable_shadow_vmcs, bool, S_IRUGO);
  97 /*
  98  * If nested=1, nested virtualization is supported, i.e., guests may use
  99  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
 100  * use VMX instructions.
 101  */
 102 static bool __read_mostly nested = 0;
 103 module_param(nested, bool, S_IRUGO);
 104
 105 static u64 __read_mostly host_xss;
 106
 107 static bool __read_mostly enable_pml = 1;
 108 module_param_named(pml, enable_pml, bool, S_IRUGO);
 109
 110 #define KVM_VMX_TSC_MULTIPLIER_MAX     0xffffffffffffffffULL
 111
 112 #define KVM_GUEST_CR0_MASK (X86_CR0_NW | X86_CR0_CD)
 113 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST (X86_CR0_WP | X86_CR0_NE)
 114 #define KVM_VM_CR0_ALWAYS_ON                                            \
 115         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
 116 #define KVM_CR4_GUEST_OWNED_BITS                                      \
 117         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
 118          | X86_CR4_OSXMMEXCPT | X86_CR4_TSD)
 119
 120 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
 121 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 122
 123 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 124
 125 #define VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE 5
 126
 127 /*
 128  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 129  * ple_gap:    upper bound on the amount of time between two successive
 130  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 131  *             According to test, this time is usually smaller than 128 cycles.
 132  * ple_window: upper bound on the amount of time a guest is allowed to execute
 133  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 134  *             less than 2^12 cycles
 135  * Time is measured based on a counter that runs at the same rate as the TSC,
 136  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 137  */
 138 #define KVM_VMX_DEFAULT_PLE_GAP           128
 139 #define KVM_VMX_DEFAULT_PLE_WINDOW        4096
 140 #define KVM_VMX_DEFAULT_PLE_WINDOW_GROW   2
 141 #define KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK 0
 142 #define KVM_VMX_DEFAULT_PLE_WINDOW_MAX    \
 143                 INT_MAX / KVM_VMX_DEFAULT_PLE_WINDOW_GROW
 144
 145 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 146 module_param(ple_gap, int, S_IRUGO);
 147
 148 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 149 module_param(ple_window, int, S_IRUGO);
 150
 151 /* Default doubles per-vcpu window every exit. */
 152 static int ple_window_grow = KVM_VMX_DEFAULT_PLE_WINDOW_GROW;
 153 module_param(ple_window_grow, int, S_IRUGO);
 154
 155 /* Default resets per-vcpu window every exit to ple_window. */
 156 static int ple_window_shrink = KVM_VMX_DEFAULT_PLE_WINDOW_SHRINK;
 157 module_param(ple_window_shrink, int, S_IRUGO);
 158
 159 /* Default is to compute the maximum so we can never overflow. */
 160 static int ple_window_actual_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 161 static int ple_window_max        = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
 162 module_param(ple_window_max, int, S_IRUGO);
 163
 164 extern const ulong vmx_return;
 165
 166 #define NR_AUTOLOAD_MSRS 8
 167 #define VMCS02_POOL_SIZE 1
 168
 169 struct vmcs {
 170         u32 revision_id;
 171         u32 abort;
 172         char data[0];
 173 };
 174
 175 /*
 176  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 177  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 178  * loaded on this CPU (so we can clear them if the CPU goes down).
 179  */
 180 struct loaded_vmcs {
 181         struct vmcs *vmcs;
 182         int cpu;
 183         int launched;
 184         struct list_head loaded_vmcss_on_cpu_link;
 185 };
 186
 187 struct shared_msr_entry {
 188         unsigned index;
 189         u64 data;
 190         u64 mask;
 191 };
 192
 193 /*
 194  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 195  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 196  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 197  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 198  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 199  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 200  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 201  * underlying hardware which will be used to run L2.
 202  * This structure is packed to ensure that its layout is identical across
 203  * machines (necessary for live migration).
 204  * If there are changes in this struct, VMCS12_REVISION must be changed.
 205  */
 206 typedef u64 natural_width;
 207 struct __packed vmcs12 {
 208         /* According to the Intel spec, a VMCS region must start with the
 209          * following two fields. Then follow implementation-specific data.
 210          */
 211         u32 revision_id;
 212         u32 abort;
 213
 214         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 215         u32 padding[7]; /* room for future expansion */
 216
 217         u64 io_bitmap_a;
 218         u64 io_bitmap_b;
 219         u64 msr_bitmap;
 220         u64 vm_exit_msr_store_addr;
 221         u64 vm_exit_msr_load_addr;
 222         u64 vm_entry_msr_load_addr;
 223         u64 tsc_offset;
 224         u64 virtual_apic_page_addr;
 225         u64 apic_access_addr;
 226         u64 posted_intr_desc_addr;
 227         u64 ept_pointer;
 228         u64 eoi_exit_bitmap0;
 229         u64 eoi_exit_bitmap1;
 230         u64 eoi_exit_bitmap2;
 231         u64 eoi_exit_bitmap3;
 232         u64 xss_exit_bitmap;
 233         u64 guest_physical_address;
 234         u64 vmcs_link_pointer;
 235         u64 guest_ia32_debugctl;
 236         u64 guest_ia32_pat;
 237         u64 guest_ia32_efer;
 238         u64 guest_ia32_perf_global_ctrl;
 239         u64 guest_pdptr0;
 240         u64 guest_pdptr1;
 241         u64 guest_pdptr2;
 242         u64 guest_pdptr3;
 243         u64 guest_bndcfgs;
 244         u64 host_ia32_pat;
 245         u64 host_ia32_efer;
 246         u64 host_ia32_perf_global_ctrl;
 247         u64 padding64[8]; /* room for future expansion */
 248         /*
 249          * To allow migration of L1 (complete with its L2 guests) between
 250          * machines of different natural widths (32 or 64 bit), we cannot have
 251          * unsigned long fields with no explict size. We use u64 (aliased
 252          * natural_width) instead. Luckily, x86 is little-endian.
 253          */
 254         natural_width cr0_guest_host_mask;
 255         natural_width cr4_guest_host_mask;
 256         natural_width cr0_read_shadow;
 257         natural_width cr4_read_shadow;
 258         natural_width cr3_target_value0;
 259         natural_width cr3_target_value1;
 260         natural_width cr3_target_value2;
 261         natural_width cr3_target_value3;
 262         natural_width exit_qualification;
 263         natural_width guest_linear_address;
 264         natural_width guest_cr0;
 265         natural_width guest_cr3;
 266         natural_width guest_cr4;
 267         natural_width guest_es_base;
 268         natural_width guest_cs_base;
 269         natural_width guest_ss_base;
 270         natural_width guest_ds_base;
 271         natural_width guest_fs_base;
 272         natural_width guest_gs_base;
 273         natural_width guest_ldtr_base;
 274         natural_width guest_tr_base;
 275         natural_width guest_gdtr_base;
 276         natural_width guest_idtr_base;
 277         natural_width guest_dr7;
 278         natural_width guest_rsp;
 279         natural_width guest_rip;
 280         natural_width guest_rflags;
 281         natural_width guest_pending_dbg_exceptions;
 282         natural_width guest_sysenter_esp;
 283         natural_width guest_sysenter_eip;
 284         natural_width host_cr0;
 285         natural_width host_cr3;
 286         natural_width host_cr4;
 287         natural_width host_fs_base;
 288         natural_width host_gs_base;
 289         natural_width host_tr_base;
 290         natural_width host_gdtr_base;
 291         natural_width host_idtr_base;
 292         natural_width host_ia32_sysenter_esp;
 293         natural_width host_ia32_sysenter_eip;
 294         natural_width host_rsp;
 295         natural_width host_rip;
 296         natural_width paddingl[8]; /* room for future expansion */
 297         u32 pin_based_vm_exec_control;
 298         u32 cpu_based_vm_exec_control;
 299         u32 exception_bitmap;
 300         u32 page_fault_error_code_mask;
 301         u32 page_fault_error_code_match;
 302         u32 cr3_target_count;
 303         u32 vm_exit_controls;
 304         u32 vm_exit_msr_store_count;
 305         u32 vm_exit_msr_load_count;
 306         u32 vm_entry_controls;
 307         u32 vm_entry_msr_load_count;
 308         u32 vm_entry_intr_info_field;
 309         u32 vm_entry_exception_error_code;
 310         u32 vm_entry_instruction_len;
 311         u32 tpr_threshold;
 312         u32 secondary_vm_exec_control;
 313         u32 vm_instruction_error;
 314         u32 vm_exit_reason;
 315         u32 vm_exit_intr_info;
 316         u32 vm_exit_intr_error_code;
 317         u32 idt_vectoring_info_field;
 318         u32 idt_vectoring_error_code;
 319         u32 vm_exit_instruction_len;
 320         u32 vmx_instruction_info;
 321         u32 guest_es_limit;
 322         u32 guest_cs_limit;
 323         u32 guest_ss_limit;
 324         u32 guest_ds_limit;
 325         u32 guest_fs_limit;
 326         u32 guest_gs_limit;
 327         u32 guest_ldtr_limit;
 328         u32 guest_tr_limit;
 329         u32 guest_gdtr_limit;
 330         u32 guest_idtr_limit;
 331         u32 guest_es_ar_bytes;
 332         u32 guest_cs_ar_bytes;
 333         u32 guest_ss_ar_bytes;
 334         u32 guest_ds_ar_bytes;
 335         u32 guest_fs_ar_bytes;
 336         u32 guest_gs_ar_bytes;
 337         u32 guest_ldtr_ar_bytes;
 338         u32 guest_tr_ar_bytes;
 339         u32 guest_interruptibility_info;
 340         u32 guest_activity_state;
 341         u32 guest_sysenter_cs;
 342         u32 host_ia32_sysenter_cs;
 343         u32 vmx_preemption_timer_value;
 344         u32 padding32[7]; /* room for future expansion */
 345         u16 virtual_processor_id;
 346         u16 posted_intr_nv;
 347         u16 guest_es_selector;
 348         u16 guest_cs_selector;
 349         u16 guest_ss_selector;
 350         u16 guest_ds_selector;
 351         u16 guest_fs_selector;
 352         u16 guest_gs_selector;
 353         u16 guest_ldtr_selector;
 354         u16 guest_tr_selector;
 355         u16 guest_intr_status;
 356         u16 host_es_selector;
 357         u16 host_cs_selector;
 358         u16 host_ss_selector;
 359         u16 host_ds_selector;
 360         u16 host_fs_selector;
 361         u16 host_gs_selector;
 362         u16 host_tr_selector;
 363 };
 364
 365 /*
 366  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 367  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 368  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 369  */
 370 #define VMCS12_REVISION 0x11e57ed0
 371
 372 /*
 373  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 374  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 375  * current implementation, 4K are reserved to avoid future complications.
 376  */
 377 #define VMCS12_SIZE 0x1000
 378
 379 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 380 struct vmcs02_list {
 381         struct list_head list;
 382         gpa_t vmptr;
 383         struct loaded_vmcs vmcs02;
 384 };
 385
 386 /*
 387  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 388  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 389  */
 390 struct nested_vmx {
 391         /* Has the level1 guest done vmxon? */
 392         bool vmxon;
 393         gpa_t vmxon_ptr;
 394
 395         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 396         gpa_t current_vmptr;
 397         /* The host-usable pointer to the above */
 398         struct page *current_vmcs12_page;
 399         struct vmcs12 *current_vmcs12;
 400         struct vmcs *current_shadow_vmcs;
 401         /*
 402          * Indicates if the shadow vmcs must be updated with the
 403          * data hold by vmcs12
 404          */
 405         bool sync_shadow_vmcs;
 406
 407         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 408         struct list_head vmcs02_pool;
 409         int vmcs02_num;
 410         u64 vmcs01_tsc_offset;
 411         /* L2 must run next, and mustn't decide to exit to L1. */
 412         bool nested_run_pending;
 413         /*
 414          * Guest pages referred to in vmcs02 with host-physical pointers, so
 415          * we must keep them pinned while L2 runs.
 416          */
 417         struct page *apic_access_page;
 418         struct page *virtual_apic_page;
 419         struct page *pi_desc_page;
 420         struct pi_desc *pi_desc;
 421         bool pi_pending;
 422         u16 posted_intr_nv;
 423         u64 msr_ia32_feature_control;
 424
 425         struct hrtimer preemption_timer;
 426         bool preemption_timer_expired;
 427
 428         /* to migrate it to L2 if VM_ENTRY_LOAD_DEBUG_CONTROLS is off */
 429         u64 vmcs01_debugctl;
 430
 431         u16 vpid02;
 432         u16 last_vpid;
 433
 434         u32 nested_vmx_procbased_ctls_low;
 435         u32 nested_vmx_procbased_ctls_high;
 436         u32 nested_vmx_true_procbased_ctls_low;
 437         u32 nested_vmx_secondary_ctls_low;
 438         u32 nested_vmx_secondary_ctls_high;
 439         u32 nested_vmx_pinbased_ctls_low;
 440         u32 nested_vmx_pinbased_ctls_high;
 441         u32 nested_vmx_exit_ctls_low;
 442         u32 nested_vmx_exit_ctls_high;
 443         u32 nested_vmx_true_exit_ctls_low;
 444         u32 nested_vmx_entry_ctls_low;
 445         u32 nested_vmx_entry_ctls_high;
 446         u32 nested_vmx_true_entry_ctls_low;
 447         u32 nested_vmx_misc_low;
 448         u32 nested_vmx_misc_high;
 449         u32 nested_vmx_ept_caps;
 450         u32 nested_vmx_vpid_caps;
 451 };
 452
 453 #define POSTED_INTR_ON  0
 454 #define POSTED_INTR_SN  1
 455
 456 /* Posted-Interrupt Descriptor */
 457 struct pi_desc {
 458         u32 pir[8];     /* Posted interrupt requested */
 459         union {
 460                 struct {
 461                                 /* bit 256 - Outstanding Notification */
 462                         u16     on      : 1,
 463                                 /* bit 257 - Suppress Notification */
 464                                 sn      : 1,
 465                                 /* bit 271:258 - Reserved */
 466                                 rsvd_1  : 14;
 467                                 /* bit 279:272 - Notification Vector */
 468                         u8      nv;
 469                                 /* bit 287:280 - Reserved */
 470                         u8      rsvd_2;
 471                                 /* bit 319:288 - Notification Destination */
 472                         u32     ndst;
 473                 };
 474                 u64 control;
 475         };
 476         u32 rsvd[6];
 477 } __aligned(64);
 478
 479 static bool pi_test_and_set_on(struct pi_desc *pi_desc)
 480 {
 481         return test_and_set_bit(POSTED_INTR_ON,
 482                         (unsigned long *)&pi_desc->control);
 483 }
 484
 485 static bool pi_test_and_clear_on(struct pi_desc *pi_desc)
 486 {
 487         return test_and_clear_bit(POSTED_INTR_ON,
 488                         (unsigned long *)&pi_desc->control);
 489 }
 490
 491 static int pi_test_and_set_pir(int vector, struct pi_desc *pi_desc)
 492 {
 493         return test_and_set_bit(vector, (unsigned long *)pi_desc->pir);
 494 }
 495
 496 static inline void pi_clear_sn(struct pi_desc *pi_desc)
 497 {
 498         return clear_bit(POSTED_INTR_SN,
 499                         (unsigned long *)&pi_desc->control);
 500 }
 501
 502 static inline void pi_set_sn(struct pi_desc *pi_desc)
 503 {
 504         return set_bit(POSTED_INTR_SN,
 505                         (unsigned long *)&pi_desc->control);
 506 }
 507
 508 static inline int pi_test_on(struct pi_desc *pi_desc)
 509 {
 510         return test_bit(POSTED_INTR_ON,
 511                         (unsigned long *)&pi_desc->control);
 512 }
 513
 514 static inline int pi_test_sn(struct pi_desc *pi_desc)
 515 {
 516         return test_bit(POSTED_INTR_SN,
 517                         (unsigned long *)&pi_desc->control);
 518 }
 519
 520 struct vcpu_vmx {
 521         struct kvm_vcpu       vcpu;
 522         unsigned long         host_rsp;
 523         u8                    fail;
 524         bool                  nmi_known_unmasked;
 525         u32                   exit_intr_info;
 526         u32                   idt_vectoring_info;
 527         ulong                 rflags;
 528         struct shared_msr_entry *guest_msrs;
 529         int                   nmsrs;
 530         int                   save_nmsrs;
 531         unsigned long         host_idt_base;
 532 #ifdef CONFIG_X86_64
 533         u64                   msr_host_kernel_gs_base;
 534         u64                   msr_guest_kernel_gs_base;
 535 #endif
 536         u32 vm_entry_controls_shadow;
 537         u32 vm_exit_controls_shadow;
 538         /*
 539          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 540          * non-nested (L1) guest, it always points to vmcs01. For a nested
 541          * guest (L2), it points to a different VMCS.
 542          */
 543         struct loaded_vmcs    vmcs01;
 544         struct loaded_vmcs   *loaded_vmcs;
 545         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 546         struct msr_autoload {
 547                 unsigned nr;
 548                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 549                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 550         } msr_autoload;
 551         struct {
 552                 int           loaded;
 553                 u16           fs_sel, gs_sel, ldt_sel;
 554 #ifdef CONFIG_X86_64
 555                 u16           ds_sel, es_sel;
 556 #endif
 557                 int           gs_ldt_reload_needed;
 558                 int           fs_reload_needed;
 559                 u64           msr_host_bndcfgs;
 560                 unsigned long vmcs_host_cr4;    /* May not match real cr4 */
 561         } host_state;
 562         struct {
 563                 int vm86_active;
 564                 ulong save_rflags;
 565                 struct kvm_segment segs[8];
 566         } rmode;
 567         struct {
 568                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 569                 struct kvm_save_segment {
 570                         u16 selector;
 571                         unsigned long base;
 572                         u32 limit;
 573                         u32 ar;
 574                 } seg[8];
 575         } segment_cache;
 576         int vpid;
 577         bool emulation_required;
 578
 579         /* Support for vnmi-less CPUs */
 580         int soft_vnmi_blocked;
 581         ktime_t entry_time;
 582         s64 vnmi_blocked_time;
 583         u32 exit_reason;
 584
 585         /* Posted interrupt descriptor */
 586         struct pi_desc pi_desc;
 587
 588         /* Support for a guest hypervisor (nested VMX) */
 589         struct nested_vmx nested;
 590
 591         /* Dynamic PLE window. */
 592         int ple_window;
 593         bool ple_window_dirty;
 594
 595         /* Support for PML */
 596 #define PML_ENTITY_NUM          512
 597         struct page *pml_pg;
 598
 599         u64 current_tsc_ratio;
 600 };
 601
 602 enum segment_cache_field {
 603         SEG_FIELD_SEL = 0,
 604         SEG_FIELD_BASE = 1,
 605         SEG_FIELD_LIMIT = 2,
 606         SEG_FIELD_AR = 3,
 607
 608         SEG_FIELD_NR = 4
 609 };
 610
 611 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 612 {
 613         return container_of(vcpu, struct vcpu_vmx, vcpu);
 614 }
 615
 616 static struct pi_desc *vcpu_to_pi_desc(struct kvm_vcpu *vcpu)
 617 {
 618         return &(to_vmx(vcpu)->pi_desc);
 619 }
 620
 621 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 622 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 623 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 624                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 625
 626
 627 static unsigned long shadow_read_only_fields[] = {
 628         /*
 629          * We do NOT shadow fields that are modified when L0
 630          * traps and emulates any vmx instruction (e.g. VMPTRLD,
 631          * VMXON...) executed by L1.
 632          * For example, VM_INSTRUCTION_ERROR is read
 633          * by L1 if a vmx instruction fails (part of the error path).
 634          * Note the code assumes this logic. If for some reason
 635          * we start shadowing these fields then we need to
 636          * force a shadow sync when L0 emulates vmx instructions
 637          * (e.g. force a sync if VM_INSTRUCTION_ERROR is modified
 638          * by nested_vmx_failValid)
 639          */
 640         VM_EXIT_REASON,
 641         VM_EXIT_INTR_INFO,
 642         VM_EXIT_INSTRUCTION_LEN,
 643         IDT_VECTORING_INFO_FIELD,
 644         IDT_VECTORING_ERROR_CODE,
 645         VM_EXIT_INTR_ERROR_CODE,
 646         EXIT_QUALIFICATION,
 647         GUEST_LINEAR_ADDRESS,
 648         GUEST_PHYSICAL_ADDRESS
 649 };
 650 static int max_shadow_read_only_fields =
 651         ARRAY_SIZE(shadow_read_only_fields);
 652
 653 static unsigned long shadow_read_write_fields[] = {
 654         TPR_THRESHOLD,
 655         GUEST_RIP,
 656         GUEST_RSP,
 657         GUEST_CR0,
 658         GUEST_CR3,
 659         GUEST_CR4,
 660         GUEST_INTERRUPTIBILITY_INFO,
 661         GUEST_RFLAGS,
 662         GUEST_CS_SELECTOR,
 663         GUEST_CS_AR_BYTES,
 664         GUEST_CS_LIMIT,
 665         GUEST_CS_BASE,
 666         GUEST_ES_BASE,
 667         GUEST_BNDCFGS,
 668         CR0_GUEST_HOST_MASK,
 669         CR0_READ_SHADOW,
 670         CR4_READ_SHADOW,
 671         TSC_OFFSET,
 672         EXCEPTION_BITMAP,
 673         CPU_BASED_VM_EXEC_CONTROL,
 674         VM_ENTRY_EXCEPTION_ERROR_CODE,
 675         VM_ENTRY_INTR_INFO_FIELD,
 676         VM_ENTRY_INSTRUCTION_LEN,
 677         VM_ENTRY_EXCEPTION_ERROR_CODE,
 678         HOST_FS_BASE,
 679         HOST_GS_BASE,
 680         HOST_FS_SELECTOR,
 681         HOST_GS_SELECTOR
 682 };
 683 static int max_shadow_read_write_fields =
 684         ARRAY_SIZE(shadow_read_write_fields);
 685
 686 static const unsigned short vmcs_field_to_offset_table[] = {
 687         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 688         FIELD(POSTED_INTR_NV, posted_intr_nv),
 689         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 690         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 691         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 692         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 693         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 694         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 695         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 696         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 697         FIELD(GUEST_INTR_STATUS, guest_intr_status),
 698         FIELD(HOST_ES_SELECTOR, host_es_selector),
 699         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 700         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 701         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 702         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 703         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 704         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 705         FIELD64(IO_BITMAP_A, io_bitmap_a),
 706         FIELD64(IO_BITMAP_B, io_bitmap_b),
 707         FIELD64(MSR_BITMAP, msr_bitmap),
 708         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 709         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 710         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 711         FIELD64(TSC_OFFSET, tsc_offset),
 712         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 713         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 714         FIELD64(POSTED_INTR_DESC_ADDR, posted_intr_desc_addr),
 715         FIELD64(EPT_POINTER, ept_pointer),
 716         FIELD64(EOI_EXIT_BITMAP0, eoi_exit_bitmap0),
 717         FIELD64(EOI_EXIT_BITMAP1, eoi_exit_bitmap1),
 718         FIELD64(EOI_EXIT_BITMAP2, eoi_exit_bitmap2),
 719         FIELD64(EOI_EXIT_BITMAP3, eoi_exit_bitmap3),
 720         FIELD64(XSS_EXIT_BITMAP, xss_exit_bitmap),
 721         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 722         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 723         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 724         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 725         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 726         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 727         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 728         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 729         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 730         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 731         FIELD64(GUEST_BNDCFGS, guest_bndcfgs),
 732         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 733         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 734         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 735         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 736         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 737         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 738         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 739         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 740         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 741         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 742         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 743         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 744         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 745         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 746         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 747         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 748         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 749         FIELD(TPR_THRESHOLD, tpr_threshold),
 750         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 751         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 752         FIELD(VM_EXIT_REASON, vm_exit_reason),
 753         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 754         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 755         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 756         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 757         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 758         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 759         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 760         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 761         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 762         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 763         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 764         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 765         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 766         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 767         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 768         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 769         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 770         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 771         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 772         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 773         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 774         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 775         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 776         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 777         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 778         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 779         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 780         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 781         FIELD(VMX_PREEMPTION_TIMER_VALUE, vmx_preemption_timer_value),
 782         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 783         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 784         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 785         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 786         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 787         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 788         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 789         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 790         FIELD(EXIT_QUALIFICATION, exit_qualification),
 791         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 792         FIELD(GUEST_CR0, guest_cr0),
 793         FIELD(GUEST_CR3, guest_cr3),
 794         FIELD(GUEST_CR4, guest_cr4),
 795         FIELD(GUEST_ES_BASE, guest_es_base),
 796         FIELD(GUEST_CS_BASE, guest_cs_base),
 797         FIELD(GUEST_SS_BASE, guest_ss_base),
 798         FIELD(GUEST_DS_BASE, guest_ds_base),
 799         FIELD(GUEST_FS_BASE, guest_fs_base),
 800         FIELD(GUEST_GS_BASE, guest_gs_base),
 801         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 802         FIELD(GUEST_TR_BASE, guest_tr_base),
 803         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 804         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 805         FIELD(GUEST_DR7, guest_dr7),
 806         FIELD(GUEST_RSP, guest_rsp),
 807         FIELD(GUEST_RIP, guest_rip),
 808         FIELD(GUEST_RFLAGS, guest_rflags),
 809         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 810         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 811         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 812         FIELD(HOST_CR0, host_cr0),
 813         FIELD(HOST_CR3, host_cr3),
 814         FIELD(HOST_CR4, host_cr4),
 815         FIELD(HOST_FS_BASE, host_fs_base),
 816         FIELD(HOST_GS_BASE, host_gs_base),
 817         FIELD(HOST_TR_BASE, host_tr_base),
 818         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 819         FIELD(HOST_IDTR_BASE, host_idtr_base),
 820         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 821         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 822         FIELD(HOST_RSP, host_rsp),
 823         FIELD(HOST_RIP, host_rip),
 824 };
 825
 826 static inline short vmcs_field_to_offset(unsigned long field)
 827 {
 828         BUILD_BUG_ON(ARRAY_SIZE(vmcs_field_to_offset_table) > SHRT_MAX);
 829
 830         if (field >= ARRAY_SIZE(vmcs_field_to_offset_table) ||
 831             vmcs_field_to_offset_table[field] == 0)
 832                 return -ENOENT;
 833
 834         return vmcs_field_to_offset_table[field];
 835 }
 836
 837 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 838 {
 839         return to_vmx(vcpu)->nested.current_vmcs12;
 840 }
 841
 842 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 843 {
 844         struct page *page = kvm_vcpu_gfn_to_page(vcpu, addr >> PAGE_SHIFT);
 845         if (is_error_page(page))
 846                 return NULL;
 847
 848         return page;
 849 }
 850
 851 static void nested_release_page(struct page *page)
 852 {
 853         kvm_release_page_dirty(page);
 854 }
 855
 856 static void nested_release_page_clean(struct page *page)
 857 {
 858         kvm_release_page_clean(page);
 859 }
 860
 861 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu);
 862 static u64 construct_eptp(unsigned long root_hpa);
 863 static void kvm_cpu_vmxon(u64 addr);
 864 static void kvm_cpu_vmxoff(void);
 865 static bool vmx_mpx_supported(void);
 866 static bool vmx_xsaves_supported(void);
 867 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu);
 868 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 869 static void vmx_set_segment(struct kvm_vcpu *vcpu,
 870                             struct kvm_segment *var, int seg);
 871 static void vmx_get_segment(struct kvm_vcpu *vcpu,
 872                             struct kvm_segment *var, int seg);
 873 static bool guest_state_valid(struct kvm_vcpu *vcpu);
 874 static u32 vmx_segment_access_rights(struct kvm_segment *var);
 875 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu);
 876 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx);
 877 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx);
 878 static int alloc_identity_pagetable(struct kvm *kvm);
 879
 880 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 881 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 882 /*
 883  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 884  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 885  */
 886 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 887 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 888
 889 /*
 890  * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
 891  * can find which vCPU should be waken up.
 892  */
 893 static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
 894 static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
 895
 896 static unsigned long *vmx_io_bitmap_a;
 897 static unsigned long *vmx_io_bitmap_b;
 898 static unsigned long *vmx_msr_bitmap_legacy;
 899 static unsigned long *vmx_msr_bitmap_longmode;
 900 static unsigned long *vmx_msr_bitmap_legacy_x2apic;
 901 static unsigned long *vmx_msr_bitmap_longmode_x2apic;
 902 static unsigned long *vmx_msr_bitmap_nested;
 903 static unsigned long *vmx_vmread_bitmap;
 904 static unsigned long *vmx_vmwrite_bitmap;
 905
 906 static bool cpu_has_load_ia32_efer;
 907 static bool cpu_has_load_perf_global_ctrl;
 908
 909 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 910 static DEFINE_SPINLOCK(vmx_vpid_lock);
 911
 912 static struct vmcs_config {
 913         int size;
 914         int order;
 915         u32 revision_id;
 916         u32 pin_based_exec_ctrl;
 917         u32 cpu_based_exec_ctrl;
 918         u32 cpu_based_2nd_exec_ctrl;
 919         u32 vmexit_ctrl;
 920         u32 vmentry_ctrl;
 921 } vmcs_config;
 922
 923 static struct vmx_capability {
 924         u32 ept;
 925         u32 vpid;
 926 } vmx_capability;
 927
 928 #define VMX_SEGMENT_FIELD(seg)                                  \
 929         [VCPU_SREG_##seg] = {                                   \
 930                 .selector = GUEST_##seg##_SELECTOR,             \
 931                 .base = GUEST_##seg##_BASE,                     \
 932                 .limit = GUEST_##seg##_LIMIT,                   \
 933                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 934         }
 935
 936 static const struct kvm_vmx_segment_field {
 937         unsigned selector;
 938         unsigned base;
 939         unsigned limit;
 940         unsigned ar_bytes;
 941 } kvm_vmx_segment_fields[] = {
 942         VMX_SEGMENT_FIELD(CS),
 943         VMX_SEGMENT_FIELD(DS),
 944         VMX_SEGMENT_FIELD(ES),
 945         VMX_SEGMENT_FIELD(FS),
 946         VMX_SEGMENT_FIELD(GS),
 947         VMX_SEGMENT_FIELD(SS),
 948         VMX_SEGMENT_FIELD(TR),
 949         VMX_SEGMENT_FIELD(LDTR),
 950 };
 951
 952 static u64 host_efer;
 953
 954 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 955
 956 /*
 957  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 958  * away by decrementing the array size.
 959  */
 960 static const u32 vmx_msr_index[] = {
 961 #ifdef CONFIG_X86_64
 962         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 963 #endif
 964         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 965 };
 966
 967 static inline bool is_page_fault(u32 intr_info)
 968 {
 969         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 970                              INTR_INFO_VALID_MASK)) ==
 971                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 972 }
 973
 974 static inline bool is_no_device(u32 intr_info)
 975 {
 976         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 977                              INTR_INFO_VALID_MASK)) ==
 978                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 979 }
 980
 981 static inline bool is_invalid_opcode(u32 intr_info)
 982 {
 983         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 984                              INTR_INFO_VALID_MASK)) ==
 985                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 986 }
 987
 988 static inline bool is_external_interrupt(u32 intr_info)
 989 {
 990         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 991                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 992 }
 993
 994 static inline bool is_machine_check(u32 intr_info)
 995 {
 996         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 997                              INTR_INFO_VALID_MASK)) ==
 998                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 999 }
1000
1001 static inline bool cpu_has_vmx_msr_bitmap(void)
1002 {
1003         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
1004 }
1005
1006 static inline bool cpu_has_vmx_tpr_shadow(void)
1007 {
1008         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
1009 }
1010
1011 static inline bool cpu_need_tpr_shadow(struct kvm_vcpu *vcpu)
1012 {
1013         return cpu_has_vmx_tpr_shadow() && lapic_in_kernel(vcpu);
1014 }
1015
1016 static inline bool cpu_has_secondary_exec_ctrls(void)
1017 {
1018         return vmcs_config.cpu_based_exec_ctrl &
1019                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1020 }
1021
1022 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
1023 {
1024         return vmcs_config.cpu_based_2nd_exec_ctrl &
1025                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1026 }
1027
1028 static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
1029 {
1030         return vmcs_config.cpu_based_2nd_exec_ctrl &
1031                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
1032 }
1033
1034 static inline bool cpu_has_vmx_apic_register_virt(void)
1035 {
1036         return vmcs_config.cpu_based_2nd_exec_ctrl &
1037                 SECONDARY_EXEC_APIC_REGISTER_VIRT;
1038 }
1039
1040 static inline bool cpu_has_vmx_virtual_intr_delivery(void)
1041 {
1042         return vmcs_config.cpu_based_2nd_exec_ctrl &
1043                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;
1044 }
1045
1046 static inline bool cpu_has_vmx_posted_intr(void)
1047 {
1048         return IS_ENABLED(CONFIG_X86_LOCAL_APIC) &&
1049                 vmcs_config.pin_based_exec_ctrl & PIN_BASED_POSTED_INTR;
1050 }
1051
1052 static inline bool cpu_has_vmx_apicv(void)
1053 {
1054         return cpu_has_vmx_apic_register_virt() &&
1055                 cpu_has_vmx_virtual_intr_delivery() &&
1056                 cpu_has_vmx_posted_intr();
1057 }
1058
1059 static inline bool cpu_has_vmx_flexpriority(void)
1060 {
1061         return cpu_has_vmx_tpr_shadow() &&
1062                 cpu_has_vmx_virtualize_apic_accesses();
1063 }
1064
1065 static inline bool cpu_has_vmx_ept_execute_only(void)
1066 {
1067         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
1068 }
1069
1070 static inline bool cpu_has_vmx_ept_2m_page(void)
1071 {
1072         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
1073 }
1074
1075 static inline bool cpu_has_vmx_ept_1g_page(void)
1076 {
1077         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
1078 }
1079
1080 static inline bool cpu_has_vmx_ept_4levels(void)
1081 {
1082         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
1083 }
1084
1085 static inline bool cpu_has_vmx_ept_ad_bits(void)
1086 {
1087         return vmx_capability.ept & VMX_EPT_AD_BIT;
1088 }
1089
1090 static inline bool cpu_has_vmx_invept_context(void)
1091 {
1092         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
1093 }
1094
1095 static inline bool cpu_has_vmx_invept_global(void)
1096 {
1097         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
1098 }
1099
1100 static inline bool cpu_has_vmx_invvpid_single(void)
1101 {
1102         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
1103 }
1104
1105 static inline bool cpu_has_vmx_invvpid_global(void)
1106 {
1107         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
1108 }
1109
1110 static inline bool cpu_has_vmx_ept(void)
1111 {
1112         return vmcs_config.cpu_based_2nd_exec_ctrl &
1113                 SECONDARY_EXEC_ENABLE_EPT;
1114 }
1115
1116 static inline bool cpu_has_vmx_unrestricted_guest(void)
1117 {
1118         return vmcs_config.cpu_based_2nd_exec_ctrl &
1119                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1120 }
1121
1122 static inline bool cpu_has_vmx_ple(void)
1123 {
1124         return vmcs_config.cpu_based_2nd_exec_ctrl &
1125                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
1126 }
1127
1128 static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
1129 {
1130         return flexpriority_enabled && lapic_in_kernel(vcpu);
1131 }
1132
1133 static inline bool cpu_has_vmx_vpid(void)
1134 {
1135         return vmcs_config.cpu_based_2nd_exec_ctrl &
1136                 SECONDARY_EXEC_ENABLE_VPID;
1137 }
1138
1139 static inline bool cpu_has_vmx_rdtscp(void)
1140 {
1141         return vmcs_config.cpu_based_2nd_exec_ctrl &
1142                 SECONDARY_EXEC_RDTSCP;
1143 }
1144
1145 static inline bool cpu_has_vmx_invpcid(void)
1146 {
1147         return vmcs_config.cpu_based_2nd_exec_ctrl &
1148                 SECONDARY_EXEC_ENABLE_INVPCID;
1149 }
1150
1151 static inline bool cpu_has_virtual_nmis(void)
1152 {
1153         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
1154 }
1155
1156 static inline bool cpu_has_vmx_wbinvd_exit(void)
1157 {
1158         return vmcs_config.cpu_based_2nd_exec_ctrl &
1159                 SECONDARY_EXEC_WBINVD_EXITING;
1160 }
1161
1162 static inline bool cpu_has_vmx_shadow_vmcs(void)
1163 {
1164         u64 vmx_msr;
1165         rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
1166         /* check if the cpu supports writing r/o exit information fields */
1167         if (!(vmx_msr & MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS))
1168                 return false;
1169
1170         return vmcs_config.cpu_based_2nd_exec_ctrl &
1171                 SECONDARY_EXEC_SHADOW_VMCS;
1172 }
1173
1174 static inline bool cpu_has_vmx_pml(void)
1175 {
1176         return vmcs_config.cpu_based_2nd_exec_ctrl & SECONDARY_EXEC_ENABLE_PML;
1177 }
1178
1179 static inline bool cpu_has_vmx_tsc_scaling(void)
1180 {
1181         return vmcs_config.cpu_based_2nd_exec_ctrl &
1182                 SECONDARY_EXEC_TSC_SCALING;
1183 }
1184
1185 static inline bool report_flexpriority(void)
1186 {
1187         return flexpriority_enabled;
1188 }
1189
1190 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
1191 {
1192         return vmcs12->cpu_based_vm_exec_control & bit;
1193 }
1194
1195 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
1196 {
1197         return (vmcs12->cpu_based_vm_exec_control &
1198                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
1199                 (vmcs12->secondary_vm_exec_control & bit);
1200 }
1201
1202 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12)
1203 {
1204         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
1205 }
1206
1207 static inline bool nested_cpu_has_preemption_timer(struct vmcs12 *vmcs12)
1208 {
1209         return vmcs12->pin_based_vm_exec_control &
1210                 PIN_BASED_VMX_PREEMPTION_TIMER;
1211 }
1212
1213 static inline int nested_cpu_has_ept(struct vmcs12 *vmcs12)
1214 {
1215         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_EPT);
1216 }
1217
1218 static inline bool nested_cpu_has_xsaves(struct vmcs12 *vmcs12)
1219 {
1220         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES) &&
1221                 vmx_xsaves_supported();
1222 }
1223
1224 static inline bool nested_cpu_has_virt_x2apic_mode(struct vmcs12 *vmcs12)
1225 {
1226         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
1227 }
1228
1229 static inline bool nested_cpu_has_vpid(struct vmcs12 *vmcs12)
1230 {
1231         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_ENABLE_VPID);
1232 }
1233
1234 static inline bool nested_cpu_has_apic_reg_virt(struct vmcs12 *vmcs12)
1235 {
1236         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_APIC_REGISTER_VIRT);
1237 }
1238
1239 static inline bool nested_cpu_has_vid(struct vmcs12 *vmcs12)
1240 {
1241         return nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
1242 }
1243
1244 static inline bool nested_cpu_has_posted_intr(struct vmcs12 *vmcs12)
1245 {
1246         return vmcs12->pin_based_vm_exec_control & PIN_BASED_POSTED_INTR;
1247 }
1248
1249 static inline bool is_exception(u32 intr_info)
1250 {
1251         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
1252                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
1253 }
1254
1255 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
1256                               u32 exit_intr_info,
1257                               unsigned long exit_qualification);
1258 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
1259                         struct vmcs12 *vmcs12,
1260                         u32 reason, unsigned long qualification);
1261
1262 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
1263 {
1264         int i;
1265
1266         for (i = 0; i < vmx->nmsrs; ++i)
1267                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
1268                         return i;
1269         return -1;
1270 }
1271
1272 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
1273 {
1274     struct {
1275         u64 vpid : 16;
1276         u64 rsvd : 48;
1277         u64 gva;
1278     } operand = { vpid, 0, gva };
1279
1280     asm volatile (__ex(ASM_VMX_INVVPID)
1281                   /* CF==1 or ZF==1 --> rc = -1 */
1282                   "; ja 1f ; ud2 ; 1:"
1283                   : : "a"(&operand), "c"(ext) : "cc", "memory");
1284 }
1285
1286 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
1287 {
1288         struct {
1289                 u64 eptp, gpa;
1290         } operand = {eptp, gpa};
1291
1292         asm volatile (__ex(ASM_VMX_INVEPT)
1293                         /* CF==1 or ZF==1 --> rc = -1 */
1294                         "; ja 1f ; ud2 ; 1:\n"
1295                         : : "a" (&operand), "c" (ext) : "cc", "memory");
1296 }
1297
1298 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
1299 {
1300         int i;
1301
1302         i = __find_msr_index(vmx, msr);
1303         if (i >= 0)
1304                 return &vmx->guest_msrs[i];
1305         return NULL;
1306 }
1307
1308 static void vmcs_clear(struct vmcs *vmcs)
1309 {
1310         u64 phys_addr = __pa(vmcs);
1311         u8 error;
1312
1313         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
1314                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1315                       : "cc", "memory");
1316         if (error)
1317                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
1318                        vmcs, phys_addr);
1319 }
1320
1321 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
1322 {
1323         vmcs_clear(loaded_vmcs->vmcs);
1324         loaded_vmcs->cpu = -1;
1325         loaded_vmcs->launched = 0;
1326 }
1327
1328 static void vmcs_load(struct vmcs *vmcs)
1329 {
1330         u64 phys_addr = __pa(vmcs);
1331         u8 error;
1332
1333         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
1334                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
1335                         : "cc", "memory");
1336         if (error)
1337                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
1338                        vmcs, phys_addr);
1339 }
1340
1341 #ifdef CONFIG_KEXEC_CORE
1342 /*
1343  * This bitmap is used to indicate whether the vmclear
1344  * operation is enabled on all cpus. All disabled by
1345  * default.
1346  */
1347 static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
1348
1349 static inline void crash_enable_local_vmclear(int cpu)
1350 {
1351         cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
1352 }
1353
1354 static inline void crash_disable_local_vmclear(int cpu)
1355 {
1356         cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
1357 }
1358
1359 static inline int crash_local_vmclear_enabled(int cpu)
1360 {
1361         return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
1362 }
1363
1364 static void crash_vmclear_local_loaded_vmcss(void)
1365 {
1366         int cpu = raw_smp_processor_id();
1367         struct loaded_vmcs *v;
1368
1369         if (!crash_local_vmclear_enabled(cpu))
1370                 return;
1371
1372         list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
1373                             loaded_vmcss_on_cpu_link)
1374                 vmcs_clear(v->vmcs);
1375 }
1376 #else
1377 static inline void crash_enable_local_vmclear(int cpu) { }
1378 static inline void crash_disable_local_vmclear(int cpu) { }
1379 #endif /* CONFIG_KEXEC_CORE */
1380
1381 static void __loaded_vmcs_clear(void *arg)
1382 {
1383         struct loaded_vmcs *loaded_vmcs = arg;
1384         int cpu = raw_smp_processor_id();
1385
1386         if (loaded_vmcs->cpu != cpu)
1387                 return; /* vcpu migration can race with cpu offline */
1388         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
1389                 per_cpu(current_vmcs, cpu) = NULL;
1390         crash_disable_local_vmclear(cpu);
1391         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
1392
1393         /*
1394          * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
1395          * is before setting loaded_vmcs->vcpu to -1 which is done in
1396          * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
1397          * then adds the vmcs into percpu list before it is deleted.
1398          */
1399         smp_wmb();
1400
1401         loaded_vmcs_init(loaded_vmcs);
1402         crash_enable_local_vmclear(cpu);
1403 }
1404
1405 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
1406 {
1407         int cpu = loaded_vmcs->cpu;
1408
1409         if (cpu != -1)
1410                 smp_call_function_single(cpu,
1411                          __loaded_vmcs_clear, loaded_vmcs, 1);
1412 }
1413
1414 static inline void vpid_sync_vcpu_single(int vpid)
1415 {
1416         if (vpid == 0)
1417                 return;
1418
1419         if (cpu_has_vmx_invvpid_single())
1420                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
1421 }
1422
1423 static inline void vpid_sync_vcpu_global(void)
1424 {
1425         if (cpu_has_vmx_invvpid_global())
1426                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1427 }
1428
1429 static inline void vpid_sync_context(int vpid)
1430 {
1431         if (cpu_has_vmx_invvpid_single())
1432                 vpid_sync_vcpu_single(vpid);
1433         else
1434                 vpid_sync_vcpu_global();
1435 }
1436
1437 static inline void ept_sync_global(void)
1438 {
1439         if (cpu_has_vmx_invept_global())
1440                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1441 }
1442
1443 static inline void ept_sync_context(u64 eptp)
1444 {
1445         if (enable_ept) {
1446                 if (cpu_has_vmx_invept_context())
1447                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1448                 else
1449                         ept_sync_global();
1450         }
1451 }
1452
1453 static __always_inline unsigned long vmcs_readl(unsigned long field)
1454 {
1455         unsigned long value;
1456
1457         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1458                       : "=a"(value) : "d"(field) : "cc");
1459         return value;
1460 }
1461
1462 static __always_inline u16 vmcs_read16(unsigned long field)
1463 {
1464         return vmcs_readl(field);
1465 }
1466
1467 static __always_inline u32 vmcs_read32(unsigned long field)
1468 {
1469         return vmcs_readl(field);
1470 }
1471
1472 static __always_inline u64 vmcs_read64(unsigned long field)
1473 {
1474 #ifdef CONFIG_X86_64
1475         return vmcs_readl(field);
1476 #else
1477         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1478 #endif
1479 }
1480
1481 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1482 {
1483         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1484                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1485         dump_stack();
1486 }
1487
1488 static void vmcs_writel(unsigned long field, unsigned long value)
1489 {
1490         u8 error;
1491
1492         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1493                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1494         if (unlikely(error))
1495                 vmwrite_error(field, value);
1496 }
1497
1498 static void vmcs_write16(unsigned long field, u16 value)
1499 {
1500         vmcs_writel(field, value);
1501 }
1502
1503 static void vmcs_write32(unsigned long field, u32 value)
1504 {
1505         vmcs_writel(field, value);
1506 }
1507
1508 static void vmcs_write64(unsigned long field, u64 value)
1509 {
1510         vmcs_writel(field, value);
1511 #ifndef CONFIG_X86_64
1512         asm volatile ("");
1513         vmcs_writel(field+1, value >> 32);
1514 #endif
1515 }
1516
1517 static void vmcs_clear_bits(unsigned long field, u32 mask)
1518 {
1519         vmcs_writel(field, vmcs_readl(field) & ~mask);
1520 }
1521
1522 static void vmcs_set_bits(unsigned long field, u32 mask)
1523 {
1524         vmcs_writel(field, vmcs_readl(field) | mask);
1525 }
1526
1527 static inline void vm_entry_controls_init(struct vcpu_vmx *vmx, u32 val)
1528 {
1529         vmcs_write32(VM_ENTRY_CONTROLS, val);
1530         vmx->vm_entry_controls_shadow = val;
1531 }
1532
1533 static inline void vm_entry_controls_set(struct vcpu_vmx *vmx, u32 val)
1534 {
1535         if (vmx->vm_entry_controls_shadow != val)
1536                 vm_entry_controls_init(vmx, val);
1537 }
1538
1539 static inline u32 vm_entry_controls_get(struct vcpu_vmx *vmx)
1540 {
1541         return vmx->vm_entry_controls_shadow;
1542 }
1543
1544
1545 static inline void vm_entry_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1546 {
1547         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) | val);
1548 }
1549
1550 static inline void vm_entry_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1551 {
1552         vm_entry_controls_set(vmx, vm_entry_controls_get(vmx) & ~val);
1553 }
1554
1555 static inline void vm_exit_controls_init(struct vcpu_vmx *vmx, u32 val)
1556 {
1557         vmcs_write32(VM_EXIT_CONTROLS, val);
1558         vmx->vm_exit_controls_shadow = val;
1559 }
1560
1561 static inline void vm_exit_controls_set(struct vcpu_vmx *vmx, u32 val)
1562 {
1563         if (vmx->vm_exit_controls_shadow != val)
1564                 vm_exit_controls_init(vmx, val);
1565 }
1566
1567 static inline u32 vm_exit_controls_get(struct vcpu_vmx *vmx)
1568 {
1569         return vmx->vm_exit_controls_shadow;
1570 }
1571
1572
1573 static inline void vm_exit_controls_setbit(struct vcpu_vmx *vmx, u32 val)
1574 {
1575         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) | val);
1576 }
1577
1578 static inline void vm_exit_controls_clearbit(struct vcpu_vmx *vmx, u32 val)
1579 {
1580         vm_exit_controls_set(vmx, vm_exit_controls_get(vmx) & ~val);
1581 }
1582
1583 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1584 {
1585         vmx->segment_cache.bitmask = 0;
1586 }
1587
1588 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1589                                        unsigned field)
1590 {
1591         bool ret;
1592         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1593
1594         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1595                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1596                 vmx->segment_cache.bitmask = 0;
1597         }
1598         ret = vmx->segment_cache.bitmask & mask;
1599         vmx->segment_cache.bitmask |= mask;
1600         return ret;
1601 }
1602
1603 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1604 {
1605         u16 *p = &vmx->segment_cache.seg[seg].selector;
1606
1607         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1608                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1609         return *p;
1610 }
1611
1612 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1613 {
1614         ulong *p = &vmx->segment_cache.seg[seg].base;
1615
1616         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1617                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1618         return *p;
1619 }
1620
1621 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1622 {
1623         u32 *p = &vmx->segment_cache.seg[seg].limit;
1624
1625         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1626                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1627         return *p;
1628 }
1629
1630 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1631 {
1632         u32 *p = &vmx->segment_cache.seg[seg].ar;
1633
1634         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1635                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1636         return *p;
1637 }
1638
1639 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1640 {
1641         u32 eb;
1642
1643         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1644              (1u << NM_VECTOR) | (1u << DB_VECTOR) | (1u << AC_VECTOR);
1645         if ((vcpu->guest_debug &
1646              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1647             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1648                 eb |= 1u << BP_VECTOR;
1649         if (to_vmx(vcpu)->rmode.vm86_active)
1650                 eb = ~0;
1651         if (enable_ept)
1652                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1653         if (vcpu->fpu_active)
1654                 eb &= ~(1u << NM_VECTOR);
1655
1656         /* When we are running a nested L2 guest and L1 specified for it a
1657          * certain exception bitmap, we must trap the same exceptions and pass
1658          * them to L1. When running L2, we will only handle the exceptions
1659          * specified above if L1 did not want them.
1660          */
1661         if (is_guest_mode(vcpu))
1662                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1663
1664         vmcs_write32(EXCEPTION_BITMAP, eb);
1665 }
1666
1667 static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1668                 unsigned long entry, unsigned long exit)
1669 {
1670         vm_entry_controls_clearbit(vmx, entry);
1671         vm_exit_controls_clearbit(vmx, exit);
1672 }
1673
1674 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1675 {
1676         unsigned i;
1677         struct msr_autoload *m = &vmx->msr_autoload;
1678
1679         switch (msr) {
1680         case MSR_EFER:
1681                 if (cpu_has_load_ia32_efer) {
1682                         clear_atomic_switch_msr_special(vmx,
1683                                         VM_ENTRY_LOAD_IA32_EFER,
1684                                         VM_EXIT_LOAD_IA32_EFER);
1685                         return;
1686                 }
1687                 break;
1688         case MSR_CORE_PERF_GLOBAL_CTRL:
1689                 if (cpu_has_load_perf_global_ctrl) {
1690                         clear_atomic_switch_msr_special(vmx,
1691                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1692                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1693                         return;
1694                 }
1695                 break;
1696         }
1697
1698         for (i = 0; i < m->nr; ++i)
1699                 if (m->guest[i].index == msr)
1700                         break;
1701
1702         if (i == m->nr)
1703                 return;
1704         --m->nr;
1705         m->guest[i] = m->guest[m->nr];
1706         m->host[i] = m->host[m->nr];
1707         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1708         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1709 }
1710
1711 static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
1712                 unsigned long entry, unsigned long exit,
1713                 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
1714                 u64 guest_val, u64 host_val)
1715 {
1716         vmcs_write64(guest_val_vmcs, guest_val);
1717         vmcs_write64(host_val_vmcs, host_val);
1718         vm_entry_controls_setbit(vmx, entry);
1719         vm_exit_controls_setbit(vmx, exit);
1720 }
1721
1722 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1723                                   u64 guest_val, u64 host_val)
1724 {
1725         unsigned i;
1726         struct msr_autoload *m = &vmx->msr_autoload;
1727
1728         switch (msr) {
1729         case MSR_EFER:
1730                 if (cpu_has_load_ia32_efer) {
1731                         add_atomic_switch_msr_special(vmx,
1732                                         VM_ENTRY_LOAD_IA32_EFER,
1733                                         VM_EXIT_LOAD_IA32_EFER,
1734                                         GUEST_IA32_EFER,
1735                                         HOST_IA32_EFER,
1736                                         guest_val, host_val);
1737                         return;
1738                 }
1739                 break;
1740         case MSR_CORE_PERF_GLOBAL_CTRL:
1741                 if (cpu_has_load_perf_global_ctrl) {
1742                         add_atomic_switch_msr_special(vmx,
1743                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1744                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1745                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1746                                         HOST_IA32_PERF_GLOBAL_CTRL,
1747                                         guest_val, host_val);
1748                         return;
1749                 }
1750                 break;
1751         case MSR_IA32_PEBS_ENABLE:
1752                 /* PEBS needs a quiescent period after being disabled (to write
1753                  * a record).  Disabling PEBS through VMX MSR swapping doesn't
1754                  * provide that period, so a CPU could write host's record into
1755                  * guest's memory.
1756                  */
1757                 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
1758         }
1759
1760         for (i = 0; i < m->nr; ++i)
1761                 if (m->guest[i].index == msr)
1762                         break;
1763
1764         if (i == NR_AUTOLOAD_MSRS) {
1765                 printk_once(KERN_WARNING "Not enough msr switch entries. "
1766                                 "Can't add msr %x\n", msr);
1767                 return;
1768         } else if (i == m->nr) {
1769                 ++m->nr;
1770                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1771                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1772         }
1773
1774         m->guest[i].index = msr;
1775         m->guest[i].value = guest_val;
1776         m->host[i].index = msr;
1777         m->host[i].value = host_val;
1778 }
1779
1780 static void reload_tss(void)
1781 {
1782         /*
1783          * VT restores TR but not its size.  Useless.
1784          */
1785         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1786         struct desc_struct *descs;
1787
1788         descs = (void *)gdt->address;
1789         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1790         load_TR_desc();
1791 }
1792
1793 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1794 {
1795         u64 guest_efer = vmx->vcpu.arch.efer;
1796         u64 ignore_bits = 0;
1797
1798         if (!enable_ept) {
1799                 /*
1800                  * NX is needed to handle CR0.WP=1, CR4.SMEP=1.  Testing
1801                  * host CPUID is more efficient than testing guest CPUID
1802                  * or CR4.  Host SMEP is anyway a requirement for guest SMEP.
1803                  */
1804                 if (boot_cpu_has(X86_FEATURE_SMEP))
1805                         guest_efer |= EFER_NX;
1806                 else if (!(guest_efer & EFER_NX))
1807                         ignore_bits |= EFER_NX;
1808         }
1809
1810         /*
1811          * LMA and LME handled by hardware; SCE meaningless outside long mode.
1812          */
1813         ignore_bits |= EFER_SCE;
1814 #ifdef CONFIG_X86_64
1815         ignore_bits |= EFER_LMA | EFER_LME;
1816         /* SCE is meaningful only in long mode on Intel */
1817         if (guest_efer & EFER_LMA)
1818                 ignore_bits &= ~(u64)EFER_SCE;
1819 #endif
1820
1821         clear_atomic_switch_msr(vmx, MSR_EFER);
1822
1823         /*
1824          * On EPT, we can't emulate NX, so we must switch EFER atomically.
1825          * On CPUs that support "load IA32_EFER", always switch EFER
1826          * atomically, since it's faster than switching it manually.
1827          */
1828         if (cpu_has_load_ia32_efer ||
1829             (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
1830                 if (!(guest_efer & EFER_LMA))
1831                         guest_efer &= ~EFER_LME;
1832                 if (guest_efer != host_efer)
1833                         add_atomic_switch_msr(vmx, MSR_EFER,
1834                                               guest_efer, host_efer);
1835                 return false;
1836         } else {
1837                 guest_efer &= ~ignore_bits;
1838                 guest_efer |= host_efer & ignore_bits;
1839
1840                 vmx->guest_msrs[efer_offset].data = guest_efer;
1841                 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1842
1843                 return true;
1844         }
1845 }
1846
1847 static unsigned long segment_base(u16 selector)
1848 {
1849         struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
1850         struct desc_struct *d;
1851         unsigned long table_base;
1852         unsigned long v;
1853
1854         if (!(selector & ~3))
1855                 return 0;
1856
1857         table_base = gdt->address;
1858
1859         if (selector & 4) {           /* from ldt */
1860                 u16 ldt_selector = kvm_read_ldt();
1861
1862                 if (!(ldt_selector & ~3))
1863                         return 0;
1864
1865                 table_base = segment_base(ldt_selector);
1866         }
1867         d = (struct desc_struct *)(table_base + (selector & ~7));
1868         v = get_desc_base(d);
1869 #ifdef CONFIG_X86_64
1870        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1871                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1872 #endif
1873         return v;
1874 }
1875
1876 static inline unsigned long kvm_read_tr_base(void)
1877 {
1878         u16 tr;
1879         asm("str %0" : "=g"(tr));
1880         return segment_base(tr);
1881 }
1882
1883 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1884 {
1885         struct vcpu_vmx *vmx = to_vmx(vcpu);
1886         int i;
1887
1888         if (vmx->host_state.loaded)
1889                 return;
1890
1891         vmx->host_state.loaded = 1;
1892         /*
1893          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1894          * allow segment selectors with cpl > 0 or ti == 1.
1895          */
1896         vmx->host_state.ldt_sel = kvm_read_ldt();
1897         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1898         savesegment(fs, vmx->host_state.fs_sel);
1899         if (!(vmx->host_state.fs_sel & 7)) {
1900                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1901                 vmx->host_state.fs_reload_needed = 0;
1902         } else {
1903                 vmcs_write16(HOST_FS_SELECTOR, 0);
1904                 vmx->host_state.fs_reload_needed = 1;
1905         }
1906         savesegment(gs, vmx->host_state.gs_sel);
1907         if (!(vmx->host_state.gs_sel & 7))
1908                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1909         else {
1910                 vmcs_write16(HOST_GS_SELECTOR, 0);
1911                 vmx->host_state.gs_ldt_reload_needed = 1;
1912         }
1913
1914 #ifdef CONFIG_X86_64
1915         savesegment(ds, vmx->host_state.ds_sel);
1916         savesegment(es, vmx->host_state.es_sel);
1917 #endif
1918
1919 #ifdef CONFIG_X86_64
1920         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1921         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1922 #else
1923         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1924         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1925 #endif
1926
1927 #ifdef CONFIG_X86_64
1928         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1929         if (is_long_mode(&vmx->vcpu))
1930                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1931 #endif
1932         if (boot_cpu_has(X86_FEATURE_MPX))
1933                 rdmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1934         for (i = 0; i < vmx->save_nmsrs; ++i)
1935                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1936                                    vmx->guest_msrs[i].data,
1937                                    vmx->guest_msrs[i].mask);
1938 }
1939
1940 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1941 {
1942         if (!vmx->host_state.loaded)
1943                 return;
1944
1945         ++vmx->vcpu.stat.host_state_reload;
1946         vmx->host_state.loaded = 0;
1947 #ifdef CONFIG_X86_64
1948         if (is_long_mode(&vmx->vcpu))
1949                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1950 #endif
1951         if (vmx->host_state.gs_ldt_reload_needed) {
1952                 kvm_load_ldt(vmx->host_state.ldt_sel);
1953 #ifdef CONFIG_X86_64
1954                 load_gs_index(vmx->host_state.gs_sel);
1955 #else
1956                 loadsegment(gs, vmx->host_state.gs_sel);
1957 #endif
1958         }
1959         if (vmx->host_state.fs_reload_needed)
1960                 loadsegment(fs, vmx->host_state.fs_sel);
1961 #ifdef CONFIG_X86_64
1962         if (unlikely(vmx->host_state.ds_sel | vmx->host_state.es_sel)) {
1963                 loadsegment(ds, vmx->host_state.ds_sel);
1964                 loadsegment(es, vmx->host_state.es_sel);
1965         }
1966 #endif
1967         reload_tss();
1968 #ifdef CONFIG_X86_64
1969         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1970 #endif
1971         if (vmx->host_state.msr_host_bndcfgs)
1972                 wrmsrl(MSR_IA32_BNDCFGS, vmx->host_state.msr_host_bndcfgs);
1973         /*
1974          * If the FPU is not active (through the host task or
1975          * the guest vcpu), then restore the cr0.TS bit.
1976          */
1977         if (!fpregs_active() && !vmx->vcpu.guest_fpu_loaded)
1978                 stts();
1979         load_gdt(this_cpu_ptr(&host_gdt));
1980 }
1981
1982 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1983 {
1984         preempt_disable();
1985         __vmx_load_host_state(vmx);
1986         preempt_enable();
1987 }
1988
1989 static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1990 {
1991         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1992         struct pi_desc old, new;
1993         unsigned int dest;
1994
1995         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
1996                 !irq_remapping_cap(IRQ_POSTING_CAP))
1997                 return;
1998
1999         do {
2000                 old.control = new.control = pi_desc->control;
2001
2002                 /*
2003                  * If 'nv' field is POSTED_INTR_WAKEUP_VECTOR, there
2004                  * are two possible cases:
2005                  * 1. After running 'pre_block', context switch
2006                  *    happened. For this case, 'sn' was set in
2007                  *    vmx_vcpu_put(), so we need to clear it here.
2008                  * 2. After running 'pre_block', we were blocked,
2009                  *    and woken up by some other guy. For this case,
2010                  *    we don't need to do anything, 'pi_post_block'
2011                  *    will do everything for us. However, we cannot
2012                  *    check whether it is case #1 or case #2 here
2013                  *    (maybe, not needed), so we also clear sn here,
2014                  *    I think it is not a big deal.
2015                  */
2016                 if (pi_desc->nv != POSTED_INTR_WAKEUP_VECTOR) {
2017                         if (vcpu->cpu != cpu) {
2018                                 dest = cpu_physical_id(cpu);
2019
2020                                 if (x2apic_enabled())
2021                                         new.ndst = dest;
2022                                 else
2023                                         new.ndst = (dest << 8) & 0xFF00;
2024                         }
2025
2026                         /* set 'NV' to 'notification vector' */
2027                         new.nv = POSTED_INTR_VECTOR;
2028                 }
2029
2030                 /* Allow posting non-urgent interrupts */
2031                 new.sn = 0;
2032         } while (cmpxchg(&pi_desc->control, old.control,
2033                         new.control) != old.control);
2034 }
2035 /*
2036  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
2037  * vcpu mutex is already taken.
2038  */
2039 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2040 {
2041         struct vcpu_vmx *vmx = to_vmx(vcpu);
2042         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2043
2044         if (!vmm_exclusive)
2045                 kvm_cpu_vmxon(phys_addr);
2046         else if (vmx->loaded_vmcs->cpu != cpu)
2047                 loaded_vmcs_clear(vmx->loaded_vmcs);
2048
2049         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
2050                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
2051                 vmcs_load(vmx->loaded_vmcs->vmcs);
2052         }
2053
2054         if (vmx->loaded_vmcs->cpu != cpu) {
2055                 struct desc_ptr *gdt = this_cpu_ptr(&host_gdt);
2056                 unsigned long sysenter_esp;
2057
2058                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2059                 local_irq_disable();
2060                 crash_disable_local_vmclear(cpu);
2061
2062                 /*
2063                  * Read loaded_vmcs->cpu should be before fetching
2064                  * loaded_vmcs->loaded_vmcss_on_cpu_link.
2065                  * See the comments in __loaded_vmcs_clear().
2066                  */
2067                 smp_rmb();
2068
2069                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
2070                          &per_cpu(loaded_vmcss_on_cpu, cpu));
2071                 crash_enable_local_vmclear(cpu);
2072                 local_irq_enable();
2073
2074                 /*
2075                  * Linux uses per-cpu TSS and GDT, so set these when switching
2076                  * processors.
2077                  */
2078                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
2079                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
2080
2081                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
2082                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
2083
2084                 vmx->loaded_vmcs->cpu = cpu;
2085         }
2086
2087         /* Setup TSC multiplier */
2088         if (kvm_has_tsc_control &&
2089             vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio) {
2090                 vmx->current_tsc_ratio = vcpu->arch.tsc_scaling_ratio;
2091                 vmcs_write64(TSC_MULTIPLIER, vmx->current_tsc_ratio);
2092         }
2093
2094         vmx_vcpu_pi_load(vcpu, cpu);
2095 }
2096
2097 static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
2098 {
2099         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
2100
2101         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
2102                 !irq_remapping_cap(IRQ_POSTING_CAP))
2103                 return;
2104
2105         /* Set SN when the vCPU is preempted */
2106         if (vcpu->preempted)
2107                 pi_set_sn(pi_desc);
2108 }
2109
2110 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
2111 {
2112         vmx_vcpu_pi_put(vcpu);
2113
2114         __vmx_load_host_state(to_vmx(vcpu));
2115         if (!vmm_exclusive) {
2116                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
2117                 vcpu->cpu = -1;
2118                 kvm_cpu_vmxoff();
2119         }
2120 }
2121
2122 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
2123 {
2124         ulong cr0;
2125
2126         if (vcpu->fpu_active)
2127                 return;
2128         vcpu->fpu_active = 1;
2129         cr0 = vmcs_readl(GUEST_CR0);
2130         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
2131         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
2132         vmcs_writel(GUEST_CR0, cr0);
2133         update_exception_bitmap(vcpu);
2134         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
2135         if (is_guest_mode(vcpu))
2136                 vcpu->arch.cr0_guest_owned_bits &=
2137                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
2138         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2139 }
2140
2141 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
2142
2143 /*
2144  * Return the cr0 value that a nested guest would read. This is a combination
2145  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
2146  * its hypervisor (cr0_read_shadow).
2147  */
2148 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
2149 {
2150         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
2151                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
2152 }
2153 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
2154 {
2155         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
2156                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
2157 }
2158
2159 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
2160 {
2161         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
2162          * set this *before* calling this function.
2163          */
2164         vmx_decache_cr0_guest_bits(vcpu);
2165         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
2166         update_exception_bitmap(vcpu);
2167         vcpu->arch.cr0_guest_owned_bits = 0;
2168         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
2169         if (is_guest_mode(vcpu)) {
2170                 /*
2171                  * L1's specified read shadow might not contain the TS bit,
2172                  * so now that we turned on shadowing of this bit, we need to
2173                  * set this bit of the shadow. Like in nested_vmx_run we need
2174                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
2175                  * up-to-date here because we just decached cr0.TS (and we'll
2176                  * only update vmcs12->guest_cr0 on nested exit).
2177                  */
2178                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2179                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
2180                         (vcpu->arch.cr0 & X86_CR0_TS);
2181                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
2182         } else
2183                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2184 }
2185
2186 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
2187 {
2188         unsigned long rflags, save_rflags;
2189
2190         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
2191                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2192                 rflags = vmcs_readl(GUEST_RFLAGS);
2193                 if (to_vmx(vcpu)->rmode.vm86_active) {
2194                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2195                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
2196                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2197                 }
2198                 to_vmx(vcpu)->rflags = rflags;
2199         }
2200         return to_vmx(vcpu)->rflags;
2201 }
2202
2203 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
2204 {
2205         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
2206         to_vmx(vcpu)->rflags = rflags;
2207         if (to_vmx(vcpu)->rmode.vm86_active) {
2208                 to_vmx(vcpu)->rmode.save_rflags = rflags;
2209                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2210         }
2211         vmcs_writel(GUEST_RFLAGS, rflags);
2212 }
2213
2214 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2215 {
2216         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2217         int ret = 0;
2218
2219         if (interruptibility & GUEST_INTR_STATE_STI)
2220                 ret |= KVM_X86_SHADOW_INT_STI;
2221         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
2222                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2223
2224         return ret;
2225 }
2226
2227 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2228 {
2229         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
2230         u32 interruptibility = interruptibility_old;
2231
2232         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
2233
2234         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2235                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
2236         else if (mask & KVM_X86_SHADOW_INT_STI)
2237                 interruptibility |= GUEST_INTR_STATE_STI;
2238
2239         if ((interruptibility != interruptibility_old))
2240                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
2241 }
2242
2243 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
2244 {
2245         unsigned long rip;
2246
2247         rip = kvm_rip_read(vcpu);
2248         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2249         kvm_rip_write(vcpu, rip);
2250
2251         /* skipping an emulated instruction also counts */
2252         vmx_set_interrupt_shadow(vcpu, 0);
2253 }
2254
2255 /*
2256  * KVM wants to inject page-faults which it got to the guest. This function
2257  * checks whether in a nested guest, we need to inject them to L1 or L2.
2258  */
2259 static int nested_vmx_check_exception(struct kvm_vcpu *vcpu, unsigned nr)
2260 {
2261         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
2262
2263         if (!(vmcs12->exception_bitmap & (1u << nr)))
2264                 return 0;
2265
2266         nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
2267                           vmcs_read32(VM_EXIT_INTR_INFO),
2268                           vmcs_readl(EXIT_QUALIFICATION));
2269         return 1;
2270 }
2271
2272 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
2273                                 bool has_error_code, u32 error_code,
2274                                 bool reinject)
2275 {
2276         struct vcpu_vmx *vmx = to_vmx(vcpu);
2277         u32 intr_info = nr | INTR_INFO_VALID_MASK;
2278
2279         if (!reinject && is_guest_mode(vcpu) &&
2280             nested_vmx_check_exception(vcpu, nr))
2281                 return;
2282
2283         if (has_error_code) {
2284                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
2285                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
2286         }
2287
2288         if (vmx->rmode.vm86_active) {
2289                 int inc_eip = 0;
2290                 if (kvm_exception_is_soft(nr))
2291                         inc_eip = vcpu->arch.event_exit_inst_len;
2292                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
2293                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2294                 return;
2295         }
2296
2297         if (kvm_exception_is_soft(nr)) {
2298                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2299                              vmx->vcpu.arch.event_exit_inst_len);
2300                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
2301         } else
2302                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
2303
2304         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
2305 }
2306
2307 static bool vmx_rdtscp_supported(void)
2308 {
2309         return cpu_has_vmx_rdtscp();
2310 }
2311
2312 static bool vmx_invpcid_supported(void)
2313 {
2314         return cpu_has_vmx_invpcid() && enable_ept;
2315 }
2316
2317 /*
2318  * Swap MSR entry in host/guest MSR entry array.
2319  */
2320 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
2321 {
2322         struct shared_msr_entry tmp;
2323
2324         tmp = vmx->guest_msrs[to];
2325         vmx->guest_msrs[to] = vmx->guest_msrs[from];
2326         vmx->guest_msrs[from] = tmp;
2327 }
2328
2329 static void vmx_set_msr_bitmap(struct kvm_vcpu *vcpu)
2330 {
2331         unsigned long *msr_bitmap;
2332
2333         if (is_guest_mode(vcpu))
2334                 msr_bitmap = vmx_msr_bitmap_nested;
2335         else if (vcpu->arch.apic_base & X2APIC_ENABLE) {
2336                 if (is_long_mode(vcpu))
2337                         msr_bitmap = vmx_msr_bitmap_longmode_x2apic;
2338                 else
2339                         msr_bitmap = vmx_msr_bitmap_legacy_x2apic;
2340         } else {
2341                 if (is_long_mode(vcpu))
2342                         msr_bitmap = vmx_msr_bitmap_longmode;
2343                 else
2344                         msr_bitmap = vmx_msr_bitmap_legacy;
2345         }
2346
2347         vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
2348 }
2349
2350 /*
2351  * Set up the vmcs to automatically save and restore system
2352  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
2353  * mode, as fiddling with msrs is very expensive.
2354  */
2355 static void setup_msrs(struct vcpu_vmx *vmx)
2356 {
2357         int save_nmsrs, index;
2358
2359         save_nmsrs = 0;
2360 #ifdef CONFIG_X86_64
2361         if (is_long_mode(&vmx->vcpu)) {
2362                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
2363                 if (index >= 0)
2364                         move_msr_up(vmx, index, save_nmsrs++);
2365                 index = __find_msr_index(vmx, MSR_LSTAR);
2366                 if (index >= 0)
2367                         move_msr_up(vmx, index, save_nmsrs++);
2368                 index = __find_msr_index(vmx, MSR_CSTAR);
2369                 if (index >= 0)
2370                         move_msr_up(vmx, index, save_nmsrs++);
2371                 index = __find_msr_index(vmx, MSR_TSC_AUX);
2372                 if (index >= 0 && guest_cpuid_has_rdtscp(&vmx->vcpu))
2373                         move_msr_up(vmx, index, save_nmsrs++);
2374                 /*
2375                  * MSR_STAR is only needed on long mode guests, and only
2376                  * if efer.sce is enabled.
2377                  */
2378                 index = __find_msr_index(vmx, MSR_STAR);
2379                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
2380                         move_msr_up(vmx, index, save_nmsrs++);
2381         }
2382 #endif
2383         index = __find_msr_index(vmx, MSR_EFER);
2384         if (index >= 0 && update_transition_efer(vmx, index))
2385                 move_msr_up(vmx, index, save_nmsrs++);
2386
2387         vmx->save_nmsrs = save_nmsrs;
2388
2389         if (cpu_has_vmx_msr_bitmap())
2390                 vmx_set_msr_bitmap(&vmx->vcpu);
2391 }
2392
2393 /*
2394  * reads and returns guest's timestamp counter "register"
2395  * guest_tsc = (host_tsc * tsc multiplier) >> 48 + tsc_offset
2396  * -- Intel TSC Scaling for Virtualization White Paper, sec 1.3
2397  */
2398 static u64 guest_read_tsc(struct kvm_vcpu *vcpu)
2399 {
2400         u64 host_tsc, tsc_offset;
2401
2402         host_tsc = rdtsc();
2403         tsc_offset = vmcs_read64(TSC_OFFSET);
2404         return kvm_scale_tsc(vcpu, host_tsc) + tsc_offset;
2405 }
2406
2407 /*
2408  * Like guest_read_tsc, but always returns L1's notion of the timestamp
2409  * counter, even if a nested guest (L2) is currently running.
2410  */
2411 static u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
2412 {
2413         u64 tsc_offset;
2414
2415         tsc_offset = is_guest_mode(vcpu) ?
2416                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
2417                 vmcs_read64(TSC_OFFSET);
2418         return host_tsc + tsc_offset;
2419 }
2420
2421 static u64 vmx_read_tsc_offset(struct kvm_vcpu *vcpu)
2422 {
2423         return vmcs_read64(TSC_OFFSET);
2424 }
2425
2426 /*
2427  * writes 'offset' into guest's timestamp counter offset register
2428  */
2429 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
2430 {
2431         if (is_guest_mode(vcpu)) {
2432                 /*
2433                  * We're here if L1 chose not to trap WRMSR to TSC. According
2434                  * to the spec, this should set L1's TSC; The offset that L1
2435                  * set for L2 remains unchanged, and still needs to be added
2436                  * to the newly set TSC to get L2's TSC.
2437                  */
2438                 struct vmcs12 *vmcs12;
2439                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
2440                 /* recalculate vmcs02.TSC_OFFSET: */
2441                 vmcs12 = get_vmcs12(vcpu);
2442                 vmcs_write64(TSC_OFFSET, offset +
2443                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
2444                          vmcs12->tsc_offset : 0));
2445         } else {
2446                 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
2447                                            vmcs_read64(TSC_OFFSET), offset);
2448                 vmcs_write64(TSC_OFFSET, offset);
2449         }
2450 }
2451
2452 static void vmx_adjust_tsc_offset_guest(struct kvm_vcpu *vcpu, s64 adjustment)
2453 {
2454         u64 offset = vmcs_read64(TSC_OFFSET);
2455
2456         vmcs_write64(TSC_OFFSET, offset + adjustment);
2457         if (is_guest_mode(vcpu)) {
2458                 /* Even when running L2, the adjustment needs to apply to L1 */
2459                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
2460         } else
2461                 trace_kvm_write_tsc_offset(vcpu->vcpu_id, offset,
2462                                            offset + adjustment);
2463 }
2464
2465 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
2466 {
2467         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
2468         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
2469 }
2470
2471 /*
2472  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
2473  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
2474  * all guests if the "nested" module option is off, and can also be disabled
2475  * for a single guest by disabling its VMX cpuid bit.
2476  */
2477 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
2478 {
2479         return nested && guest_cpuid_has_vmx(vcpu);
2480 }
2481
2482 /*
2483  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
2484  * returned for the various VMX controls MSRs when nested VMX is enabled.
2485  * The same values should also be used to verify that vmcs12 control fields are
2486  * valid during nested entry from L1 to L2.
2487  * Each of these control msrs has a low and high 32-bit half: A low bit is on
2488  * if the corresponding bit in the (32-bit) control field *must* be on, and a
2489  * bit in the high half is on if the corresponding bit in the control field
2490  * may be on. See also vmx_control_verify().
2491  */
2492 static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx *vmx)
2493 {
2494         /*
2495          * Note that as a general rule, the high half of the MSRs (bits in
2496          * the control fields which may be 1) should be initialized by the
2497          * intersection of the underlying hardware's MSR (i.e., features which
2498          * can be supported) and the list of features we want to expose -
2499          * because they are known to be properly supported in our code.
2500          * Also, usually, the low half of the MSRs (bits which must be 1) can
2501          * be set to 0, meaning that L1 may turn off any of these bits. The
2502          * reason is that if one of these bits is necessary, it will appear
2503          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
2504          * fields of vmcs01 and vmcs02, will turn these bits off - and
2505          * nested_vmx_exit_handled() will not pass related exits to L1.
2506          * These rules have exceptions below.
2507          */
2508
2509         /* pin-based controls */
2510         rdmsr(MSR_IA32_VMX_PINBASED_CTLS,
2511                 vmx->nested.nested_vmx_pinbased_ctls_low,
2512                 vmx->nested.nested_vmx_pinbased_ctls_high);
2513         vmx->nested.nested_vmx_pinbased_ctls_low |=
2514                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2515         vmx->nested.nested_vmx_pinbased_ctls_high &=
2516                 PIN_BASED_EXT_INTR_MASK |
2517                 PIN_BASED_NMI_EXITING |
2518                 PIN_BASED_VIRTUAL_NMIS;
2519         vmx->nested.nested_vmx_pinbased_ctls_high |=
2520                 PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2521                 PIN_BASED_VMX_PREEMPTION_TIMER;
2522         if (vmx_cpu_uses_apicv(&vmx->vcpu))
2523                 vmx->nested.nested_vmx_pinbased_ctls_high |=
2524                         PIN_BASED_POSTED_INTR;
2525
2526         /* exit controls */
2527         rdmsr(MSR_IA32_VMX_EXIT_CTLS,
2528                 vmx->nested.nested_vmx_exit_ctls_low,
2529                 vmx->nested.nested_vmx_exit_ctls_high);
2530         vmx->nested.nested_vmx_exit_ctls_low =
2531                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR;
2532
2533         vmx->nested.nested_vmx_exit_ctls_high &=
2534 #ifdef CONFIG_X86_64
2535                 VM_EXIT_HOST_ADDR_SPACE_SIZE |
2536 #endif
2537                 VM_EXIT_LOAD_IA32_PAT | VM_EXIT_SAVE_IA32_PAT;
2538         vmx->nested.nested_vmx_exit_ctls_high |=
2539                 VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR |
2540                 VM_EXIT_LOAD_IA32_EFER | VM_EXIT_SAVE_IA32_EFER |
2541                 VM_EXIT_SAVE_VMX_PREEMPTION_TIMER | VM_EXIT_ACK_INTR_ON_EXIT;
2542
2543         if (vmx_mpx_supported())
2544                 vmx->nested.nested_vmx_exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
2545
2546         /* We support free control of debug control saving. */
2547         vmx->nested.nested_vmx_true_exit_ctls_low =
2548                 vmx->nested.nested_vmx_exit_ctls_low &
2549                 ~VM_EXIT_SAVE_DEBUG_CONTROLS;
2550
2551         /* entry controls */
2552         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
2553                 vmx->nested.nested_vmx_entry_ctls_low,
2554                 vmx->nested.nested_vmx_entry_ctls_high);
2555         vmx->nested.nested_vmx_entry_ctls_low =
2556                 VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR;
2557         vmx->nested.nested_vmx_entry_ctls_high &=
2558 #ifdef CONFIG_X86_64
2559                 VM_ENTRY_IA32E_MODE |
2560 #endif
2561                 VM_ENTRY_LOAD_IA32_PAT;
2562         vmx->nested.nested_vmx_entry_ctls_high |=
2563                 (VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR | VM_ENTRY_LOAD_IA32_EFER);
2564         if (vmx_mpx_supported())
2565                 vmx->nested.nested_vmx_entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
2566
2567         /* We support free control of debug control loading. */
2568         vmx->nested.nested_vmx_true_entry_ctls_low =
2569                 vmx->nested.nested_vmx_entry_ctls_low &
2570                 ~VM_ENTRY_LOAD_DEBUG_CONTROLS;
2571
2572         /* cpu-based controls */
2573         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
2574                 vmx->nested.nested_vmx_procbased_ctls_low,
2575                 vmx->nested.nested_vmx_procbased_ctls_high);
2576         vmx->nested.nested_vmx_procbased_ctls_low =
2577                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR;
2578         vmx->nested.nested_vmx_procbased_ctls_high &=
2579                 CPU_BASED_VIRTUAL_INTR_PENDING |
2580                 CPU_BASED_VIRTUAL_NMI_PENDING | CPU_BASED_USE_TSC_OFFSETING |
2581                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
2582                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
2583                 CPU_BASED_CR3_STORE_EXITING |
2584 #ifdef CONFIG_X86_64
2585                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
2586 #endif
2587                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
2588                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_TRAP_FLAG |
2589                 CPU_BASED_MONITOR_EXITING | CPU_BASED_RDPMC_EXITING |
2590                 CPU_BASED_RDTSC_EXITING | CPU_BASED_PAUSE_EXITING |
2591                 CPU_BASED_TPR_SHADOW | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2592         /*
2593          * We can allow some features even when not supported by the
2594          * hardware. For example, L1 can specify an MSR bitmap - and we
2595          * can use it to avoid exits to L1 - even when L0 runs L2
2596          * without MSR bitmaps.
2597          */
2598         vmx->nested.nested_vmx_procbased_ctls_high |=
2599                 CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR |
2600                 CPU_BASED_USE_MSR_BITMAPS;
2601
2602         /* We support free control of CR3 access interception. */
2603         vmx->nested.nested_vmx_true_procbased_ctls_low =
2604                 vmx->nested.nested_vmx_procbased_ctls_low &
2605                 ~(CPU_BASED_CR3_LOAD_EXITING | CPU_BASED_CR3_STORE_EXITING);
2606
2607         /* secondary cpu-based controls */
2608         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
2609                 vmx->nested.nested_vmx_secondary_ctls_low,
2610                 vmx->nested.nested_vmx_secondary_ctls_high);
2611         vmx->nested.nested_vmx_secondary_ctls_low = 0;
2612         vmx->nested.nested_vmx_secondary_ctls_high &=
2613                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2614                 SECONDARY_EXEC_RDTSCP |
2615                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2616                 SECONDARY_EXEC_ENABLE_VPID |
2617                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
2618                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
2619                 SECONDARY_EXEC_WBINVD_EXITING |
2620                 SECONDARY_EXEC_XSAVES |
2621                 SECONDARY_EXEC_PCOMMIT;
2622
2623         if (enable_ept) {
2624                 /* nested EPT: emulate EPT also to L1 */
2625                 vmx->nested.nested_vmx_secondary_ctls_high |=
2626                         SECONDARY_EXEC_ENABLE_EPT;
2627                 vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
2628                          VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
2629                          VMX_EPT_INVEPT_BIT;
2630                 vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
2631                 /*
2632                  * For nested guests, we don't do anything specific
2633                  * for single context invalidation. Hence, only advertise
2634                  * support for global context invalidation.
2635                  */
2636                 vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
2637         } else
2638                 vmx->nested.nested_vmx_ept_caps = 0;
2639
2640         /*
2641          * Old versions of KVM use the single-context version without
2642          * checking for support, so declare that it is supported even
2643          * though it is treated as global context.  The alternative is
2644          * not failing the single-context invvpid, and it is worse.
2645          */
2646         if (enable_vpid)
2647                 vmx->nested.nested_vmx_vpid_caps = VMX_VPID_INVVPID_BIT |
2648                                 VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT |
2649                                 VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
2650         else
2651                 vmx->nested.nested_vmx_vpid_caps = 0;
2652
2653         if (enable_unrestricted_guest)
2654                 vmx->nested.nested_vmx_secondary_ctls_high |=
2655                         SECONDARY_EXEC_UNRESTRICTED_GUEST;
2656
2657         /* miscellaneous data */
2658         rdmsr(MSR_IA32_VMX_MISC,
2659                 vmx->nested.nested_vmx_misc_low,
2660                 vmx->nested.nested_vmx_misc_high);
2661         vmx->nested.nested_vmx_misc_low &= VMX_MISC_SAVE_EFER_LMA;
2662         vmx->nested.nested_vmx_misc_low |=
2663                 VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE |
2664                 VMX_MISC_ACTIVITY_HLT;
2665         vmx->nested.nested_vmx_misc_high = 0;
2666 }
2667
2668 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
2669 {
2670         /*
2671          * Bits 0 in high must be 0, and bits 1 in low must be 1.
2672          */
2673         return ((control & high) | low) == control;
2674 }
2675
2676 static inline u64 vmx_control_msr(u32 low, u32 high)
2677 {
2678         return low | ((u64)high << 32);
2679 }
2680
2681 /* Returns 0 on success, non-0 otherwise. */
2682 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2683 {
2684         struct vcpu_vmx *vmx = to_vmx(vcpu);
2685
2686         switch (msr_index) {
2687         case MSR_IA32_VMX_BASIC:
2688                 /*
2689                  * This MSR reports some information about VMX support. We
2690                  * should return information about the VMX we emulate for the
2691                  * guest, and the VMCS structure we give it - not about the
2692                  * VMX support of the underlying hardware.
2693                  */
2694                 *pdata = VMCS12_REVISION | VMX_BASIC_TRUE_CTLS |
2695                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2696                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2697                 break;
2698         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2699         case MSR_IA32_VMX_PINBASED_CTLS:
2700                 *pdata = vmx_control_msr(
2701                         vmx->nested.nested_vmx_pinbased_ctls_low,
2702                         vmx->nested.nested_vmx_pinbased_ctls_high);
2703                 break;
2704         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2705                 *pdata = vmx_control_msr(
2706                         vmx->nested.nested_vmx_true_procbased_ctls_low,
2707                         vmx->nested.nested_vmx_procbased_ctls_high);
2708                 break;
2709         case MSR_IA32_VMX_PROCBASED_CTLS:
2710                 *pdata = vmx_control_msr(
2711                         vmx->nested.nested_vmx_procbased_ctls_low,
2712                         vmx->nested.nested_vmx_procbased_ctls_high);
2713                 break;
2714         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2715                 *pdata = vmx_control_msr(
2716                         vmx->nested.nested_vmx_true_exit_ctls_low,
2717                         vmx->nested.nested_vmx_exit_ctls_high);
2718                 break;
2719         case MSR_IA32_VMX_EXIT_CTLS:
2720                 *pdata = vmx_control_msr(
2721                         vmx->nested.nested_vmx_exit_ctls_low,
2722                         vmx->nested.nested_vmx_exit_ctls_high);
2723                 break;
2724         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2725                 *pdata = vmx_control_msr(
2726                         vmx->nested.nested_vmx_true_entry_ctls_low,
2727                         vmx->nested.nested_vmx_entry_ctls_high);
2728                 break;
2729         case MSR_IA32_VMX_ENTRY_CTLS:
2730                 *pdata = vmx_control_msr(
2731                         vmx->nested.nested_vmx_entry_ctls_low,
2732                         vmx->nested.nested_vmx_entry_ctls_high);
2733                 break;
2734         case MSR_IA32_VMX_MISC:
2735                 *pdata = vmx_control_msr(
2736                         vmx->nested.nested_vmx_misc_low,
2737                         vmx->nested.nested_vmx_misc_high);
2738                 break;
2739         /*
2740          * These MSRs specify bits which the guest must keep fixed (on or off)
2741          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2742          * We picked the standard core2 setting.
2743          */
2744 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2745 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2746         case MSR_IA32_VMX_CR0_FIXED0:
2747                 *pdata = VMXON_CR0_ALWAYSON;
2748                 break;
2749         case MSR_IA32_VMX_CR0_FIXED1:
2750                 *pdata = -1ULL;
2751                 break;
2752         case MSR_IA32_VMX_CR4_FIXED0:
2753                 *pdata = VMXON_CR4_ALWAYSON;
2754                 break;
2755         case MSR_IA32_VMX_CR4_FIXED1:
2756                 *pdata = -1ULL;
2757                 break;
2758         case MSR_IA32_VMX_VMCS_ENUM:
2759                 *pdata = 0x2e; /* highest index: VMX_PREEMPTION_TIMER_VALUE */
2760                 break;
2761         case MSR_IA32_VMX_PROCBASED_CTLS2:
2762                 *pdata = vmx_control_msr(
2763                         vmx->nested.nested_vmx_secondary_ctls_low,
2764                         vmx->nested.nested_vmx_secondary_ctls_high);
2765                 break;
2766         case MSR_IA32_VMX_EPT_VPID_CAP:
2767                 /* Currently, no nested vpid support */
2768                 *pdata = vmx->nested.nested_vmx_ept_caps |
2769                         ((u64)vmx->nested.nested_vmx_vpid_caps << 32);
2770                 break;
2771         default:
2772                 return 1;
2773         }
2774
2775         return 0;
2776 }
2777
2778 /*
2779  * Reads an msr value (of 'msr_index') into 'pdata'.
2780  * Returns 0 on success, non-0 otherwise.
2781  * Assumes vcpu_load() was already called.
2782  */
2783 static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2784 {
2785         struct shared_msr_entry *msr;
2786
2787         switch (msr_info->index) {
2788 #ifdef CONFIG_X86_64
2789         case MSR_FS_BASE:
2790                 msr_info->data = vmcs_readl(GUEST_FS_BASE);
2791                 break;
2792         case MSR_GS_BASE:
2793                 msr_info->data = vmcs_readl(GUEST_GS_BASE);
2794                 break;
2795         case MSR_KERNEL_GS_BASE:
2796                 vmx_load_host_state(to_vmx(vcpu));
2797                 msr_info->data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2798                 break;
2799 #endif
2800         case MSR_EFER:
2801                 return kvm_get_msr_common(vcpu, msr_info);
2802         case MSR_IA32_TSC:
2803                 msr_info->data = guest_read_tsc(vcpu);
2804                 break;
2805         case MSR_IA32_SYSENTER_CS:
2806                 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
2807                 break;
2808         case MSR_IA32_SYSENTER_EIP:
2809                 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
2810                 break;
2811         case MSR_IA32_SYSENTER_ESP:
2812                 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
2813                 break;
2814         case MSR_IA32_BNDCFGS:
2815                 if (!vmx_mpx_supported())
2816                         return 1;
2817                 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
2818                 break;
2819         case MSR_IA32_FEATURE_CONTROL:
2820                 if (!nested_vmx_allowed(vcpu))
2821                         return 1;
2822                 msr_info->data = to_vmx(vcpu)->nested.msr_ia32_feature_control;
2823                 break;
2824         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2825                 if (!nested_vmx_allowed(vcpu))
2826                         return 1;
2827                 return vmx_get_vmx_msr(vcpu, msr_info->index, &msr_info->data);
2828         case MSR_IA32_XSS:
2829                 if (!vmx_xsaves_supported())
2830                         return 1;
2831                 msr_info->data = vcpu->arch.ia32_xss;
2832                 break;
2833         case MSR_TSC_AUX:
2834                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2835                         return 1;
2836                 /* Otherwise falls through */
2837         default:
2838                 msr = find_msr_entry(to_vmx(vcpu), msr_info->index);
2839                 if (msr) {
2840                         msr_info->data = msr->data;
2841                         break;
2842                 }
2843                 return kvm_get_msr_common(vcpu, msr_info);
2844         }
2845
2846         return 0;
2847 }
2848
2849 static void vmx_leave_nested(struct kvm_vcpu *vcpu);
2850
2851 /*
2852  * Writes msr value into into the appropriate "register".
2853  * Returns 0 on success, non-0 otherwise.
2854  * Assumes vcpu_load() was already called.
2855  */
2856 static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2857 {
2858         struct vcpu_vmx *vmx = to_vmx(vcpu);
2859         struct shared_msr_entry *msr;
2860         int ret = 0;
2861         u32 msr_index = msr_info->index;
2862         u64 data = msr_info->data;
2863
2864         switch (msr_index) {
2865         case MSR_EFER:
2866                 ret = kvm_set_msr_common(vcpu, msr_info);
2867                 break;
2868 #ifdef CONFIG_X86_64
2869         case MSR_FS_BASE:
2870                 vmx_segment_cache_clear(vmx);
2871                 vmcs_writel(GUEST_FS_BASE, data);
2872                 break;
2873         case MSR_GS_BASE:
2874                 vmx_segment_cache_clear(vmx);
2875                 vmcs_writel(GUEST_GS_BASE, data);
2876                 break;
2877         case MSR_KERNEL_GS_BASE:
2878                 vmx_load_host_state(vmx);
2879                 vmx->msr_guest_kernel_gs_base = data;
2880                 break;
2881 #endif
2882         case MSR_IA32_SYSENTER_CS:
2883                 vmcs_write32(GUEST_SYSENTER_CS, data);
2884                 break;
2885         case MSR_IA32_SYSENTER_EIP:
2886                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2887                 break;
2888         case MSR_IA32_SYSENTER_ESP:
2889                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2890                 break;
2891         case MSR_IA32_BNDCFGS:
2892                 if (!vmx_mpx_supported())
2893                         return 1;
2894                 vmcs_write64(GUEST_BNDCFGS, data);
2895                 break;
2896         case MSR_IA32_TSC:
2897                 kvm_write_tsc(vcpu, msr_info);
2898                 break;
2899         case MSR_IA32_CR_PAT:
2900                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2901                         if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2902                                 return 1;
2903                         vmcs_write64(GUEST_IA32_PAT, data);
2904                         vcpu->arch.pat = data;
2905                         break;
2906                 }
2907                 ret = kvm_set_msr_common(vcpu, msr_info);
2908                 break;
2909         case MSR_IA32_TSC_ADJUST:
2910                 ret = kvm_set_msr_common(vcpu, msr_info);
2911                 break;
2912         case MSR_IA32_FEATURE_CONTROL:
2913                 if (!nested_vmx_allowed(vcpu) ||
2914                     (to_vmx(vcpu)->nested.msr_ia32_feature_control &
2915                      FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
2916                         return 1;
2917                 vmx->nested.msr_ia32_feature_control = data;
2918                 if (msr_info->host_initiated && data == 0)
2919                         vmx_leave_nested(vcpu);
2920                 break;
2921         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
2922                 return 1; /* they are read-only */
2923         case MSR_IA32_XSS:
2924                 if (!vmx_xsaves_supported())
2925                         return 1;
2926                 /*
2927                  * The only supported bit as of Skylake is bit 8, but
2928                  * it is not supported on KVM.
2929                  */
2930                 if (data != 0)
2931                         return 1;
2932                 vcpu->arch.ia32_xss = data;
2933                 if (vcpu->arch.ia32_xss != host_xss)
2934                         add_atomic_switch_msr(vmx, MSR_IA32_XSS,
2935                                 vcpu->arch.ia32_xss, host_xss);
2936                 else
2937                         clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
2938                 break;
2939         case MSR_TSC_AUX:
2940                 if (!guest_cpuid_has_rdtscp(vcpu) && !msr_info->host_initiated)
2941                         return 1;
2942                 /* Check reserved bit, higher 32 bits should be zero */
2943                 if ((data >> 32) != 0)
2944                         return 1;
2945                 /* Otherwise falls through */
2946         default:
2947                 msr = find_msr_entry(vmx, msr_index);
2948                 if (msr) {
2949                         u64 old_msr_data = msr->data;
2950                         msr->data = data;
2951                         if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
2952                                 preempt_disable();
2953                                 ret = kvm_set_shared_msr(msr->index, msr->data,
2954                                                          msr->mask);
2955                                 preempt_enable();
2956                                 if (ret)
2957                                         msr->data = old_msr_data;
2958                         }
2959                         break;
2960                 }
2961                 ret = kvm_set_msr_common(vcpu, msr_info);
2962         }
2963
2964         return ret;
2965 }
2966
2967 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2968 {
2969         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2970         switch (reg) {
2971         case VCPU_REGS_RSP:
2972                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2973                 break;
2974         case VCPU_REGS_RIP:
2975                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2976                 break;
2977         case VCPU_EXREG_PDPTR:
2978                 if (enable_ept)
2979                         ept_save_pdptrs(vcpu);
2980                 break;
2981         default:
2982                 break;
2983         }
2984 }
2985
2986 static __init int cpu_has_kvm_support(void)
2987 {
2988         return cpu_has_vmx();
2989 }
2990
2991 static __init int vmx_disabled_by_bios(void)
2992 {
2993         u64 msr;
2994
2995         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2996         if (msr & FEATURE_CONTROL_LOCKED) {
2997                 /* launched w/ TXT and VMX disabled */
2998                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2999                         && tboot_enabled())
3000                         return 1;
3001                 /* launched w/o TXT and VMX only enabled w/ TXT */
3002                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3003                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
3004                         && !tboot_enabled()) {
3005                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
3006                                 "activate TXT before enabling KVM\n");
3007                         return 1;
3008                 }
3009                 /* launched w/o TXT and VMX disabled */
3010                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
3011                         && !tboot_enabled())
3012                         return 1;
3013         }
3014
3015         return 0;
3016 }
3017
3018 static void kvm_cpu_vmxon(u64 addr)
3019 {
3020         asm volatile (ASM_VMX_VMXON_RAX
3021                         : : "a"(&addr), "m"(addr)
3022                         : "memory", "cc");
3023 }
3024
3025 static int hardware_enable(void)
3026 {
3027         int cpu = raw_smp_processor_id();
3028         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
3029         u64 old, test_bits;
3030
3031         if (cr4_read_shadow() & X86_CR4_VMXE)
3032                 return -EBUSY;
3033
3034         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
3035         INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
3036         spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
3037
3038         /*
3039          * Now we can enable the vmclear operation in kdump
3040          * since the loaded_vmcss_on_cpu list on this cpu
3041          * has been initialized.
3042          *
3043          * Though the cpu is not in VMX operation now, there
3044          * is no problem to enable the vmclear operation
3045          * for the loaded_vmcss_on_cpu list is empty!
3046          */
3047         crash_enable_local_vmclear(cpu);
3048
3049         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
3050
3051         test_bits = FEATURE_CONTROL_LOCKED;
3052         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
3053         if (tboot_enabled())
3054                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
3055
3056         if ((old & test_bits) != test_bits) {
3057                 /* enable and lock */
3058                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
3059         }
3060         cr4_set_bits(X86_CR4_VMXE);
3061
3062         if (vmm_exclusive) {
3063                 kvm_cpu_vmxon(phys_addr);
3064                 ept_sync_global();
3065         }
3066
3067         native_store_gdt(this_cpu_ptr(&host_gdt));
3068
3069         return 0;
3070 }
3071
3072 static void vmclear_local_loaded_vmcss(void)
3073 {
3074         int cpu = raw_smp_processor_id();
3075         struct loaded_vmcs *v, *n;
3076
3077         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
3078                                  loaded_vmcss_on_cpu_link)
3079                 __loaded_vmcs_clear(v);
3080 }
3081
3082
3083 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
3084  * tricks.
3085  */
3086 static void kvm_cpu_vmxoff(void)
3087 {
3088         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
3089 }
3090
3091 static void hardware_disable(void)
3092 {
3093         if (vmm_exclusive) {
3094                 vmclear_local_loaded_vmcss();
3095                 kvm_cpu_vmxoff();
3096         }
3097         cr4_clear_bits(X86_CR4_VMXE);
3098 }
3099
3100 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
3101                                       u32 msr, u32 *result)
3102 {
3103         u32 vmx_msr_low, vmx_msr_high;
3104         u32 ctl = ctl_min | ctl_opt;
3105
3106         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3107
3108         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
3109         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
3110
3111         /* Ensure minimum (required) set of control bits are supported. */
3112         if (ctl_min & ~ctl)
3113                 return -EIO;
3114
3115         *result = ctl;
3116         return 0;
3117 }
3118
3119 static __init bool allow_1_setting(u32 msr, u32 ctl)
3120 {
3121         u32 vmx_msr_low, vmx_msr_high;
3122
3123         rdmsr(msr, vmx_msr_low, vmx_msr_high);
3124         return vmx_msr_high & ctl;
3125 }
3126
3127 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
3128 {
3129         u32 vmx_msr_low, vmx_msr_high;
3130         u32 min, opt, min2, opt2;
3131         u32 _pin_based_exec_control = 0;
3132         u32 _cpu_based_exec_control = 0;
3133         u32 _cpu_based_2nd_exec_control = 0;
3134         u32 _vmexit_control = 0;
3135         u32 _vmentry_control = 0;
3136
3137         min = CPU_BASED_HLT_EXITING |
3138 #ifdef CONFIG_X86_64
3139               CPU_BASED_CR8_LOAD_EXITING |
3140               CPU_BASED_CR8_STORE_EXITING |
3141 #endif
3142               CPU_BASED_CR3_LOAD_EXITING |
3143               CPU_BASED_CR3_STORE_EXITING |
3144               CPU_BASED_USE_IO_BITMAPS |
3145               CPU_BASED_MOV_DR_EXITING |
3146               CPU_BASED_USE_TSC_OFFSETING |
3147               CPU_BASED_MWAIT_EXITING |
3148               CPU_BASED_MONITOR_EXITING |
3149               CPU_BASED_INVLPG_EXITING |
3150               CPU_BASED_RDPMC_EXITING;
3151
3152         opt = CPU_BASED_TPR_SHADOW |
3153               CPU_BASED_USE_MSR_BITMAPS |
3154               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
3155         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
3156                                 &_cpu_based_exec_control) < 0)
3157                 return -EIO;
3158 #ifdef CONFIG_X86_64
3159         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3160                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
3161                                            ~CPU_BASED_CR8_STORE_EXITING;
3162 #endif
3163         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
3164                 min2 = 0;
3165                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
3166                         SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3167                         SECONDARY_EXEC_WBINVD_EXITING |
3168                         SECONDARY_EXEC_ENABLE_VPID |
3169                         SECONDARY_EXEC_ENABLE_EPT |
3170                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
3171                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
3172                         SECONDARY_EXEC_RDTSCP |
3173                         SECONDARY_EXEC_ENABLE_INVPCID |
3174                         SECONDARY_EXEC_APIC_REGISTER_VIRT |
3175                         SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
3176                         SECONDARY_EXEC_SHADOW_VMCS |
3177                         SECONDARY_EXEC_XSAVES |
3178                         SECONDARY_EXEC_ENABLE_PML |
3179                         SECONDARY_EXEC_PCOMMIT |
3180                         SECONDARY_EXEC_TSC_SCALING;
3181                 if (adjust_vmx_controls(min2, opt2,
3182                                         MSR_IA32_VMX_PROCBASED_CTLS2,
3183                                         &_cpu_based_2nd_exec_control) < 0)
3184                         return -EIO;
3185         }
3186 #ifndef CONFIG_X86_64
3187         if (!(_cpu_based_2nd_exec_control &
3188                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
3189                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
3190 #endif
3191
3192         if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
3193                 _cpu_based_2nd_exec_control &= ~(
3194                                 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3195                                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
3196                                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3197
3198         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
3199                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
3200                    enabled */
3201                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
3202                                              CPU_BASED_CR3_STORE_EXITING |
3203                                              CPU_BASED_INVLPG_EXITING);
3204                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
3205                       vmx_capability.ept, vmx_capability.vpid);
3206         }
3207
3208         min = VM_EXIT_SAVE_DEBUG_CONTROLS;
3209 #ifdef CONFIG_X86_64
3210         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
3211 #endif
3212         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT |
3213                 VM_EXIT_ACK_INTR_ON_EXIT | VM_EXIT_CLEAR_BNDCFGS;
3214         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
3215                                 &_vmexit_control) < 0)
3216                 return -EIO;
3217
3218         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
3219         opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR;
3220         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
3221                                 &_pin_based_exec_control) < 0)
3222                 return -EIO;
3223
3224         if (!(_cpu_based_2nd_exec_control &
3225                 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) ||
3226                 !(_vmexit_control & VM_EXIT_ACK_INTR_ON_EXIT))
3227                 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
3228
3229         min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
3230         opt = VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_BNDCFGS;
3231         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
3232                                 &_vmentry_control) < 0)
3233                 return -EIO;
3234
3235         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
3236
3237         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
3238         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
3239                 return -EIO;
3240
3241 #ifdef CONFIG_X86_64
3242         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
3243         if (vmx_msr_high & (1u<<16))
3244                 return -EIO;
3245 #endif
3246
3247         /* Require Write-Back (WB) memory type for VMCS accesses. */
3248         if (((vmx_msr_high >> 18) & 15) != 6)
3249                 return -EIO;
3250
3251         vmcs_conf->size = vmx_msr_high & 0x1fff;
3252         vmcs_conf->order = get_order(vmcs_config.size);
3253         vmcs_conf->revision_id = vmx_msr_low;
3254
3255         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
3256         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
3257         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
3258         vmcs_conf->vmexit_ctrl         = _vmexit_control;
3259         vmcs_conf->vmentry_ctrl        = _vmentry_control;
3260
3261         cpu_has_load_ia32_efer =
3262                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3263                                 VM_ENTRY_LOAD_IA32_EFER)
3264                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3265                                    VM_EXIT_LOAD_IA32_EFER);
3266
3267         cpu_has_load_perf_global_ctrl =
3268                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
3269                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
3270                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
3271                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
3272
3273         /*
3274          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
3275          * but due to arrata below it can't be used. Workaround is to use
3276          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
3277          *
3278          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
3279          *
3280          * AAK155             (model 26)
3281          * AAP115             (model 30)
3282          * AAT100             (model 37)
3283          * BC86,AAY89,BD102   (model 44)
3284          * BA97               (model 46)
3285          *
3286          */
3287         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
3288                 switch (boot_cpu_data.x86_model) {
3289                 case 26:
3290                 case 30:
3291                 case 37:
3292                 case 44:
3293                 case 46:
3294                         cpu_has_load_perf_global_ctrl = false;
3295                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
3296                                         "does not work properly. Using workaround\n");
3297                         break;
3298                 default:
3299                         break;
3300                 }
3301         }
3302
3303         if (cpu_has_xsaves)
3304                 rdmsrl(MSR_IA32_XSS, host_xss);
3305
3306         return 0;
3307 }
3308
3309 static struct vmcs *alloc_vmcs_cpu(int cpu)
3310 {
3311         int node = cpu_to_node(cpu);
3312         struct page *pages;
3313         struct vmcs *vmcs;
3314
3315         pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
3316         if (!pages)
3317                 return NULL;
3318         vmcs = page_address(pages);
3319         memset(vmcs, 0, vmcs_config.size);
3320         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
3321         return vmcs;
3322 }
3323
3324 static struct vmcs *alloc_vmcs(void)
3325 {
3326         return alloc_vmcs_cpu(raw_smp_processor_id());
3327 }
3328
3329 static void free_vmcs(struct vmcs *vmcs)
3330 {
3331         free_pages((unsigned long)vmcs, vmcs_config.order);
3332 }
3333
3334 /*
3335  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
3336  */
3337 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
3338 {
3339         if (!loaded_vmcs->vmcs)
3340                 return;
3341         loaded_vmcs_clear(loaded_vmcs);
3342         free_vmcs(loaded_vmcs->vmcs);
3343         loaded_vmcs->vmcs = NULL;
3344 }
3345
3346 static void free_kvm_area(void)
3347 {
3348         int cpu;
3349
3350         for_each_possible_cpu(cpu) {
3351                 free_vmcs(per_cpu(vmxarea, cpu));
3352                 per_cpu(vmxarea, cpu) = NULL;
3353         }
3354 }
3355
3356 static void init_vmcs_shadow_fields(void)
3357 {
3358         int i, j;
3359
3360         /* No checks for read only fields yet */
3361
3362         for (i = j = 0; i < max_shadow_read_write_fields; i++) {
3363                 switch (shadow_read_write_fields[i]) {
3364                 case GUEST_BNDCFGS:
3365                         if (!vmx_mpx_supported())
3366                                 continue;
3367                         break;
3368                 default:
3369                         break;
3370                 }
3371
3372                 if (j < i)
3373                         shadow_read_write_fields[j] =
3374                                 shadow_read_write_fields[i];
3375                 j++;
3376         }
3377         max_shadow_read_write_fields = j;
3378
3379         /* shadowed fields guest access without vmexit */
3380         for (i = 0; i < max_shadow_read_write_fields; i++) {
3381                 clear_bit(shadow_read_write_fields[i],
3382                           vmx_vmwrite_bitmap);
3383                 clear_bit(shadow_read_write_fields[i],
3384                           vmx_vmread_bitmap);
3385         }
3386         for (i = 0; i < max_shadow_read_only_fields; i++)
3387                 clear_bit(shadow_read_only_fields[i],
3388                           vmx_vmread_bitmap);
3389 }
3390
3391 static __init int alloc_kvm_area(void)
3392 {
3393         int cpu;
3394
3395         for_each_possible_cpu(cpu) {
3396                 struct vmcs *vmcs;
3397
3398                 vmcs = alloc_vmcs_cpu(cpu);
3399                 if (!vmcs) {
3400                         free_kvm_area();
3401                         return -ENOMEM;
3402                 }
3403
3404                 per_cpu(vmxarea, cpu) = vmcs;
3405         }
3406         return 0;
3407 }
3408
3409 static bool emulation_required(struct kvm_vcpu *vcpu)
3410 {
3411         return emulate_invalid_guest_state && !guest_state_valid(vcpu);
3412 }
3413
3414 static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
3415                 struct kvm_segment *save)
3416 {
3417         if (!emulate_invalid_guest_state) {
3418                 /*
3419                  * CS and SS RPL should be equal during guest entry according
3420                  * to VMX spec, but in reality it is not always so. Since vcpu
3421                  * is in the middle of the transition from real mode to
3422                  * protected mode it is safe to assume that RPL 0 is a good
3423                  * default value.
3424                  */
3425                 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
3426                         save->selector &= ~SEGMENT_RPL_MASK;
3427                 save->dpl = save->selector & SEGMENT_RPL_MASK;
3428                 save->s = 1;
3429         }
3430         vmx_set_segment(vcpu, save, seg);
3431 }
3432
3433 static void enter_pmode(struct kvm_vcpu *vcpu)
3434 {
3435         unsigned long flags;
3436         struct vcpu_vmx *vmx = to_vmx(vcpu);
3437
3438         /*
3439          * Update real mode segment cache. It may be not up-to-date if sement
3440          * register was written while vcpu was in a guest mode.
3441          */
3442         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3443         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3444         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3445         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3446         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3447         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3448
3449         vmx->rmode.vm86_active = 0;
3450
3451         vmx_segment_cache_clear(vmx);
3452
3453         vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3454
3455         flags = vmcs_readl(GUEST_RFLAGS);
3456         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
3457         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
3458         vmcs_writel(GUEST_RFLAGS, flags);
3459
3460         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
3461                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
3462
3463         update_exception_bitmap(vcpu);
3464
3465         fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3466         fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3467         fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3468         fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3469         fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3470         fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3471 }
3472
3473 static void fix_rmode_seg(int seg, struct kvm_segment *save)
3474 {
3475         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3476         struct kvm_segment var = *save;
3477
3478         var.dpl = 0x3;
3479         if (seg == VCPU_SREG_CS)
3480                 var.type = 0x3;
3481
3482         if (!emulate_invalid_guest_state) {
3483                 var.selector = var.base >> 4;
3484                 var.base = var.base & 0xffff0;
3485                 var.limit = 0xffff;
3486                 var.g = 0;
3487                 var.db = 0;
3488                 var.present = 1;
3489                 var.s = 1;
3490                 var.l = 0;
3491                 var.unusable = 0;
3492                 var.type = 0x3;
3493                 var.avl = 0;
3494                 if (save->base & 0xf)
3495                         printk_once(KERN_WARNING "kvm: segment base is not "
3496                                         "paragraph aligned when entering "
3497                                         "protected mode (seg=%d)", seg);
3498         }
3499
3500         vmcs_write16(sf->selector, var.selector);
3501         vmcs_write32(sf->base, var.base);
3502         vmcs_write32(sf->limit, var.limit);
3503         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
3504 }
3505
3506 static void enter_rmode(struct kvm_vcpu *vcpu)
3507 {
3508         unsigned long flags;
3509         struct vcpu_vmx *vmx = to_vmx(vcpu);
3510
3511         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
3512         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
3513         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
3514         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
3515         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
3516         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
3517         vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
3518
3519         vmx->rmode.vm86_active = 1;
3520
3521         /*
3522          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
3523          * vcpu. Warn the user that an update is overdue.
3524          */
3525         if (!vcpu->kvm->arch.tss_addr)
3526                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
3527                              "called before entering vcpu\n");
3528
3529         vmx_segment_cache_clear(vmx);
3530
3531         vmcs_writel(GUEST_TR_BASE, vcpu->kvm->arch.tss_addr);
3532         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
3533         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3534
3535         flags = vmcs_readl(GUEST_RFLAGS);
3536         vmx->rmode.save_rflags = flags;
3537
3538         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
3539
3540         vmcs_writel(GUEST_RFLAGS, flags);
3541         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
3542         update_exception_bitmap(vcpu);
3543
3544         fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
3545         fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
3546         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
3547         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
3548         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
3549         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
3550
3551         kvm_mmu_reset_context(vcpu);
3552 }
3553
3554 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
3555 {
3556         struct vcpu_vmx *vmx = to_vmx(vcpu);
3557         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
3558
3559         if (!msr)
3560                 return;
3561
3562         /*
3563          * Force kernel_gs_base reloading before EFER changes, as control
3564          * of this msr depends on is_long_mode().
3565          */
3566         vmx_load_host_state(to_vmx(vcpu));
3567         vcpu->arch.efer = efer;
3568         if (efer & EFER_LMA) {
3569                 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3570                 msr->data = efer;
3571         } else {
3572                 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3573
3574                 msr->data = efer & ~EFER_LME;
3575         }
3576         setup_msrs(vmx);
3577 }
3578
3579 #ifdef CONFIG_X86_64
3580
3581 static void enter_lmode(struct kvm_vcpu *vcpu)
3582 {
3583         u32 guest_tr_ar;
3584
3585         vmx_segment_cache_clear(to_vmx(vcpu));
3586
3587         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
3588         if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
3589                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
3590                                      __func__);
3591                 vmcs_write32(GUEST_TR_AR_BYTES,
3592                              (guest_tr_ar & ~VMX_AR_TYPE_MASK)
3593                              | VMX_AR_TYPE_BUSY_64_TSS);
3594         }
3595         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
3596 }
3597
3598 static void exit_lmode(struct kvm_vcpu *vcpu)
3599 {
3600         vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
3601         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
3602 }
3603
3604 #endif
3605
3606 static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
3607 {
3608         vpid_sync_context(vpid);
3609         if (enable_ept) {
3610                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
3611                         return;
3612                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
3613         }
3614 }
3615
3616 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
3617 {
3618         __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
3619 }
3620
3621 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
3622 {
3623         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
3624
3625         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
3626         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
3627 }
3628
3629 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
3630 {
3631         if (enable_ept && is_paging(vcpu))
3632                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3633         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
3634 }
3635
3636 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
3637 {
3638         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
3639
3640         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
3641         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
3642 }
3643
3644 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
3645 {
3646         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3647
3648         if (!test_bit(VCPU_EXREG_PDPTR,
3649                       (unsigned long *)&vcpu->arch.regs_dirty))
3650                 return;
3651
3652         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3653                 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
3654                 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
3655                 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
3656                 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
3657         }
3658 }
3659
3660 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
3661 {
3662         struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
3663
3664         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
3665                 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
3666                 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
3667                 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
3668                 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
3669         }
3670
3671         __set_bit(VCPU_EXREG_PDPTR,
3672                   (unsigned long *)&vcpu->arch.regs_avail);
3673         __set_bit(VCPU_EXREG_PDPTR,
3674                   (unsigned long *)&vcpu->arch.regs_dirty);
3675 }
3676
3677 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
3678
3679 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
3680                                         unsigned long cr0,
3681                                         struct kvm_vcpu *vcpu)
3682 {
3683         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3684                 vmx_decache_cr3(vcpu);
3685         if (!(cr0 & X86_CR0_PG)) {
3686                 /* From paging/starting to nonpaging */
3687                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3688                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
3689                              (CPU_BASED_CR3_LOAD_EXITING |
3690                               CPU_BASED_CR3_STORE_EXITING));
3691                 vcpu->arch.cr0 = cr0;
3692                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3693         } else if (!is_paging(vcpu)) {
3694                 /* From nonpaging to paging */
3695                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
3696                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
3697                              ~(CPU_BASED_CR3_LOAD_EXITING |
3698                                CPU_BASED_CR3_STORE_EXITING));
3699                 vcpu->arch.cr0 = cr0;
3700                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
3701         }
3702
3703         if (!(cr0 & X86_CR0_WP))
3704                 *hw_cr0 &= ~X86_CR0_WP;
3705 }
3706
3707 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
3708 {
3709         struct vcpu_vmx *vmx = to_vmx(vcpu);
3710         unsigned long hw_cr0;
3711
3712         hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK);
3713         if (enable_unrestricted_guest)
3714                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
3715         else {
3716                 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
3717
3718                 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
3719                         enter_pmode(vcpu);
3720
3721                 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
3722                         enter_rmode(vcpu);
3723         }
3724
3725 #ifdef CONFIG_X86_64
3726         if (vcpu->arch.efer & EFER_LME) {
3727                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
3728                         enter_lmode(vcpu);
3729                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
3730                         exit_lmode(vcpu);
3731         }
3732 #endif
3733
3734         if (enable_ept)
3735                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
3736
3737         if (!vcpu->fpu_active)
3738                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
3739
3740         vmcs_writel(CR0_READ_SHADOW, cr0);
3741         vmcs_writel(GUEST_CR0, hw_cr0);
3742         vcpu->arch.cr0 = cr0;
3743
3744         /* depends on vcpu->arch.cr0 to be set to a new value */
3745         vmx->emulation_required = emulation_required(vcpu);
3746 }
3747
3748 static u64 construct_eptp(unsigned long root_hpa)
3749 {
3750         u64 eptp;
3751
3752         /* TODO write the value reading from MSR */
3753         eptp = VMX_EPT_DEFAULT_MT |
3754                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3755         if (enable_ept_ad_bits)
3756                 eptp |= VMX_EPT_AD_ENABLE_BIT;
3757         eptp |= (root_hpa & PAGE_MASK);
3758
3759         return eptp;
3760 }
3761
3762 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3763 {
3764         unsigned long guest_cr3;
3765         u64 eptp;
3766
3767         guest_cr3 = cr3;
3768         if (enable_ept) {
3769                 eptp = construct_eptp(cr3);
3770                 vmcs_write64(EPT_POINTER, eptp);
3771                 if (is_paging(vcpu) || is_guest_mode(vcpu))
3772                         guest_cr3 = kvm_read_cr3(vcpu);
3773                 else
3774                         guest_cr3 = vcpu->kvm->arch.ept_identity_map_addr;
3775                 ept_load_pdptrs(vcpu);
3776         }
3777
3778         vmx_flush_tlb(vcpu);
3779         vmcs_writel(GUEST_CR3, guest_cr3);
3780 }
3781
3782 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3783 {
3784         /*
3785          * Pass through host's Machine Check Enable value to hw_cr4, which
3786          * is in force while we are in guest mode.  Do not let guests control
3787          * this bit, even if host CR4.MCE == 0.
3788          */
3789         unsigned long hw_cr4 =
3790                 (cr4_read_shadow() & X86_CR4_MCE) |
3791                 (cr4 & ~X86_CR4_MCE) |
3792                 (to_vmx(vcpu)->rmode.vm86_active ?
3793                  KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3794
3795         if (cr4 & X86_CR4_VMXE) {
3796                 /*
3797                  * To use VMXON (and later other VMX instructions), a guest
3798                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3799                  * So basically the check on whether to allow nested VMX
3800                  * is here.
3801                  */
3802                 if (!nested_vmx_allowed(vcpu))
3803                         return 1;
3804         }
3805         if (to_vmx(vcpu)->nested.vmxon &&
3806             ((cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON))
3807                 return 1;
3808
3809         vcpu->arch.cr4 = cr4;
3810         if (enable_ept) {
3811                 if (!is_paging(vcpu)) {
3812                         hw_cr4 &= ~X86_CR4_PAE;
3813                         hw_cr4 |= X86_CR4_PSE;
3814                 } else if (!(cr4 & X86_CR4_PAE)) {
3815                         hw_cr4 &= ~X86_CR4_PAE;
3816                 }
3817         }
3818
3819         if (!enable_unrestricted_guest && !is_paging(vcpu))
3820                 /*
3821                  * SMEP/SMAP is disabled if CPU is in non-paging mode in
3822                  * hardware.  However KVM always uses paging mode without
3823                  * unrestricted guest.
3824                  * To emulate this behavior, SMEP/SMAP needs to be manually
3825                  * disabled when guest switches to non-paging mode.
3826                  */
3827                 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP);
3828
3829         vmcs_writel(CR4_READ_SHADOW, cr4);
3830         vmcs_writel(GUEST_CR4, hw_cr4);
3831         return 0;
3832 }
3833
3834 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3835                             struct kvm_segment *var, int seg)
3836 {
3837         struct vcpu_vmx *vmx = to_vmx(vcpu);
3838         u32 ar;
3839
3840         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3841                 *var = vmx->rmode.segs[seg];
3842                 if (seg == VCPU_SREG_TR
3843                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3844                         return;
3845                 var->base = vmx_read_guest_seg_base(vmx, seg);
3846                 var->selector = vmx_read_guest_seg_selector(vmx, seg);
3847                 return;
3848         }
3849         var->base = vmx_read_guest_seg_base(vmx, seg);
3850         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3851         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3852         ar = vmx_read_guest_seg_ar(vmx, seg);
3853         var->unusable = (ar >> 16) & 1;
3854         var->type = ar & 15;
3855         var->s = (ar >> 4) & 1;
3856         var->dpl = (ar >> 5) & 3;
3857         /*
3858          * Some userspaces do not preserve unusable property. Since usable
3859          * segment has to be present according to VMX spec we can use present
3860          * property to amend userspace bug by making unusable segment always
3861          * nonpresent. vmx_segment_access_rights() already marks nonpresent
3862          * segment as unusable.
3863          */
3864         var->present = !var->unusable;
3865         var->avl = (ar >> 12) & 1;
3866         var->l = (ar >> 13) & 1;
3867         var->db = (ar >> 14) & 1;
3868         var->g = (ar >> 15) & 1;
3869 }
3870
3871 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3872 {
3873         struct kvm_segment s;
3874
3875         if (to_vmx(vcpu)->rmode.vm86_active) {
3876                 vmx_get_segment(vcpu, &s, seg);
3877                 return s.base;
3878         }
3879         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3880 }
3881
3882 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3883 {
3884         struct vcpu_vmx *vmx = to_vmx(vcpu);
3885
3886         if (unlikely(vmx->rmode.vm86_active))
3887                 return 0;
3888         else {
3889                 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
3890                 return VMX_AR_DPL(ar);
3891         }
3892 }
3893
3894 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3895 {
3896         u32 ar;
3897
3898         if (var->unusable || !var->present)
3899                 ar = 1 << 16;
3900         else {
3901                 ar = var->type & 15;
3902                 ar |= (var->s & 1) << 4;
3903                 ar |= (var->dpl & 3) << 5;
3904                 ar |= (var->present & 1) << 7;
3905                 ar |= (var->avl & 1) << 12;
3906                 ar |= (var->l & 1) << 13;
3907                 ar |= (var->db & 1) << 14;
3908                 ar |= (var->g & 1) << 15;
3909         }
3910
3911         return ar;
3912 }
3913
3914 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3915                             struct kvm_segment *var, int seg)
3916 {
3917         struct vcpu_vmx *vmx = to_vmx(vcpu);
3918         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3919
3920         vmx_segment_cache_clear(vmx);
3921
3922         if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
3923                 vmx->rmode.segs[seg] = *var;
3924                 if (seg == VCPU_SREG_TR)
3925                         vmcs_write16(sf->selector, var->selector);
3926                 else if (var->s)
3927                         fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
3928                 goto out;
3929         }
3930
3931         vmcs_writel(sf->base, var->base);
3932         vmcs_write32(sf->limit, var->limit);
3933         vmcs_write16(sf->selector, var->selector);
3934
3935         /*
3936          *   Fix the "Accessed" bit in AR field of segment registers for older
3937          * qemu binaries.
3938          *   IA32 arch specifies that at the time of processor reset the
3939          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3940          * is setting it to 0 in the userland code. This causes invalid guest
3941          * state vmexit when "unrestricted guest" mode is turned on.
3942          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3943          * tree. Newer qemu binaries with that qemu fix would not need this
3944          * kvm hack.
3945          */
3946         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3947                 var->type |= 0x1; /* Accessed */
3948
3949         vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
3950
3951 out:
3952         vmx->emulation_required = emulation_required(vcpu);
3953 }
3954
3955 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3956 {
3957         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3958
3959         *db = (ar >> 14) & 1;
3960         *l = (ar >> 13) & 1;
3961 }
3962
3963 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3964 {
3965         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3966         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3967 }
3968
3969 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3970 {
3971         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3972         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3973 }
3974
3975 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3976 {
3977         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3978         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3979 }
3980
3981 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3982 {
3983         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3984         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3985 }
3986
3987 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3988 {
3989         struct kvm_segment var;
3990         u32 ar;
3991
3992         vmx_get_segment(vcpu, &var, seg);
3993         var.dpl = 0x3;
3994         if (seg == VCPU_SREG_CS)
3995                 var.type = 0x3;
3996         ar = vmx_segment_access_rights(&var);
3997
3998         if (var.base != (var.selector << 4))
3999                 return false;
4000         if (var.limit != 0xffff)
4001                 return false;
4002         if (ar != 0xf3)
4003                 return false;
4004
4005         return true;
4006 }
4007
4008 static bool code_segment_valid(struct kvm_vcpu *vcpu)
4009 {
4010         struct kvm_segment cs;
4011         unsigned int cs_rpl;
4012
4013         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4014         cs_rpl = cs.selector & SEGMENT_RPL_MASK;
4015
4016         if (cs.unusable)
4017                 return false;
4018         if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
4019                 return false;
4020         if (!cs.s)
4021                 return false;
4022         if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
4023                 if (cs.dpl > cs_rpl)
4024                         return false;
4025         } else {
4026                 if (cs.dpl != cs_rpl)
4027                         return false;
4028         }
4029         if (!cs.present)
4030                 return false;
4031
4032         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
4033         return true;
4034 }
4035
4036 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
4037 {
4038         struct kvm_segment ss;
4039         unsigned int ss_rpl;
4040
4041         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4042         ss_rpl = ss.selector & SEGMENT_RPL_MASK;
4043
4044         if (ss.unusable)
4045                 return true;
4046         if (ss.type != 3 && ss.type != 7)
4047                 return false;
4048         if (!ss.s)
4049                 return false;
4050         if (ss.dpl != ss_rpl) /* DPL != RPL */
4051                 return false;
4052         if (!ss.present)
4053                 return false;
4054
4055         return true;
4056 }
4057
4058 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
4059 {
4060         struct kvm_segment var;
4061         unsigned int rpl;
4062
4063         vmx_get_segment(vcpu, &var, seg);
4064         rpl = var.selector & SEGMENT_RPL_MASK;
4065
4066         if (var.unusable)
4067                 return true;
4068         if (!var.s)
4069                 return false;
4070         if (!var.present)
4071                 return false;
4072         if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
4073                 if (var.dpl < rpl) /* DPL < RPL */
4074                         return false;
4075         }
4076
4077         /* TODO: Add other members to kvm_segment_field to allow checking for other access
4078          * rights flags
4079          */
4080         return true;
4081 }
4082
4083 static bool tr_valid(struct kvm_vcpu *vcpu)
4084 {
4085         struct kvm_segment tr;
4086
4087         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
4088
4089         if (tr.unusable)
4090                 return false;
4091         if (tr.selector & SEGMENT_TI_MASK)      /* TI = 1 */
4092                 return false;
4093         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
4094                 return false;
4095         if (!tr.present)
4096                 return false;
4097
4098         return true;
4099 }
4100
4101 static bool ldtr_valid(struct kvm_vcpu *vcpu)
4102 {
4103         struct kvm_segment ldtr;
4104
4105         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
4106
4107         if (ldtr.unusable)
4108                 return true;
4109         if (ldtr.selector & SEGMENT_TI_MASK)    /* TI = 1 */
4110                 return false;
4111         if (ldtr.type != 2)
4112                 return false;
4113         if (!ldtr.present)
4114                 return false;
4115
4116         return true;
4117 }
4118
4119 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
4120 {
4121         struct kvm_segment cs, ss;
4122
4123         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4124         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
4125
4126         return ((cs.selector & SEGMENT_RPL_MASK) ==
4127                  (ss.selector & SEGMENT_RPL_MASK));
4128 }
4129
4130 /*
4131  * Check if guest state is valid. Returns true if valid, false if
4132  * not.
4133  * We assume that registers are always usable
4134  */
4135 static bool guest_state_valid(struct kvm_vcpu *vcpu)
4136 {
4137         if (enable_unrestricted_guest)
4138                 return true;
4139
4140         /* real mode guest state checks */
4141         if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4142                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
4143                         return false;
4144                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
4145                         return false;
4146                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
4147                         return false;
4148                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
4149                         return false;
4150                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
4151                         return false;
4152                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
4153                         return false;
4154         } else {
4155         /* protected mode guest state checks */
4156                 if (!cs_ss_rpl_check(vcpu))
4157                         return false;
4158                 if (!code_segment_valid(vcpu))
4159                         return false;
4160                 if (!stack_segment_valid(vcpu))
4161                         return false;
4162                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
4163                         return false;
4164                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
4165                         return false;
4166                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
4167                         return false;
4168                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
4169                         return false;
4170                 if (!tr_valid(vcpu))
4171                         return false;
4172                 if (!ldtr_valid(vcpu))
4173                         return false;
4174         }
4175         /* TODO:
4176          * - Add checks on RIP
4177          * - Add checks on RFLAGS
4178          */
4179
4180         return true;
4181 }
4182
4183 static int init_rmode_tss(struct kvm *kvm)
4184 {
4185         gfn_t fn;
4186         u16 data = 0;
4187         int idx, r;
4188
4189         idx = srcu_read_lock(&kvm->srcu);
4190         fn = kvm->arch.tss_addr >> PAGE_SHIFT;
4191         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4192         if (r < 0)
4193                 goto out;
4194         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
4195         r = kvm_write_guest_page(kvm, fn++, &data,
4196                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
4197         if (r < 0)
4198                 goto out;
4199         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
4200         if (r < 0)
4201                 goto out;
4202         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
4203         if (r < 0)
4204                 goto out;
4205         data = ~0;
4206         r = kvm_write_guest_page(kvm, fn, &data,
4207                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
4208                                  sizeof(u8));
4209 out:
4210         srcu_read_unlock(&kvm->srcu, idx);
4211         return r;
4212 }
4213
4214 static int init_rmode_identity_map(struct kvm *kvm)
4215 {
4216         int i, idx, r = 0;
4217         pfn_t identity_map_pfn;
4218         u32 tmp;
4219
4220         if (!enable_ept)
4221                 return 0;
4222
4223         /* Protect kvm->arch.ept_identity_pagetable_done. */
4224         mutex_lock(&kvm->slots_lock);
4225
4226         if (likely(kvm->arch.ept_identity_pagetable_done))
4227                 goto out2;
4228
4229         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
4230
4231         r = alloc_identity_pagetable(kvm);
4232         if (r < 0)
4233                 goto out2;
4234
4235         idx = srcu_read_lock(&kvm->srcu);
4236         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
4237         if (r < 0)
4238                 goto out;
4239         /* Set up identity-mapping pagetable for EPT in real mode */
4240         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
4241                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
4242                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
4243                 r = kvm_write_guest_page(kvm, identity_map_pfn,
4244                                 &tmp, i * sizeof(tmp), sizeof(tmp));
4245                 if (r < 0)
4246                         goto out;
4247         }
4248         kvm->arch.ept_identity_pagetable_done = true;
4249
4250 out:
4251         srcu_read_unlock(&kvm->srcu, idx);
4252
4253 out2:
4254         mutex_unlock(&kvm->slots_lock);
4255         return r;
4256 }
4257
4258 static void seg_setup(int seg)
4259 {
4260         const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
4261         unsigned int ar;
4262
4263         vmcs_write16(sf->selector, 0);
4264         vmcs_writel(sf->base, 0);
4265         vmcs_write32(sf->limit, 0xffff);
4266         ar = 0x93;
4267         if (seg == VCPU_SREG_CS)
4268                 ar |= 0x08; /* code segment */
4269
4270         vmcs_write32(sf->ar_bytes, ar);
4271 }
4272
4273 static int alloc_apic_access_page(struct kvm *kvm)
4274 {
4275         struct page *page;
4276         int r = 0;
4277
4278         mutex_lock(&kvm->slots_lock);
4279         if (kvm->arch.apic_access_page_done)
4280                 goto out;
4281         r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
4282                                     APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
4283         if (r)
4284                 goto out;
4285
4286         page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4287         if (is_error_page(page)) {
4288                 r = -EFAULT;
4289                 goto out;
4290         }
4291
4292         /*
4293          * Do not pin the page in memory, so that memory hot-unplug
4294          * is able to migrate it.
4295          */
4296         put_page(page);
4297         kvm->arch.apic_access_page_done = true;
4298 out:
4299         mutex_unlock(&kvm->slots_lock);
4300         return r;
4301 }
4302
4303 static int alloc_identity_pagetable(struct kvm *kvm)
4304 {
4305         /* Called with kvm->slots_lock held. */
4306
4307         int r = 0;
4308
4309         BUG_ON(kvm->arch.ept_identity_pagetable_done);
4310
4311         r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
4312                                     kvm->arch.ept_identity_map_addr, PAGE_SIZE);
4313
4314         return r;
4315 }
4316
4317 static int allocate_vpid(void)
4318 {
4319         int vpid;
4320
4321         if (!enable_vpid)
4322                 return 0;
4323         spin_lock(&vmx_vpid_lock);
4324         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
4325         if (vpid < VMX_NR_VPIDS)
4326                 __set_bit(vpid, vmx_vpid_bitmap);
4327         else
4328                 vpid = 0;
4329         spin_unlock(&vmx_vpid_lock);
4330         return vpid;
4331 }
4332
4333 static void free_vpid(int vpid)
4334 {
4335         if (!enable_vpid || vpid == 0)
4336                 return;
4337         spin_lock(&vmx_vpid_lock);
4338         __clear_bit(vpid, vmx_vpid_bitmap);
4339         spin_unlock(&vmx_vpid_lock);
4340 }
4341
4342 #define MSR_TYPE_R      1
4343 #define MSR_TYPE_W      2
4344 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
4345                                                 u32 msr, int type)
4346 {
4347         int f = sizeof(unsigned long);
4348
4349         if (!cpu_has_vmx_msr_bitmap())
4350                 return;
4351
4352         /*
4353          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4354          * have the write-low and read-high bitmap offsets the wrong way round.
4355          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4356          */
4357         if (msr <= 0x1fff) {
4358                 if (type & MSR_TYPE_R)
4359                         /* read-low */
4360                         __clear_bit(msr, msr_bitmap + 0x000 / f);
4361
4362                 if (type & MSR_TYPE_W)
4363                         /* write-low */
4364                         __clear_bit(msr, msr_bitmap + 0x800 / f);
4365
4366         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4367                 msr &= 0x1fff;
4368                 if (type & MSR_TYPE_R)
4369                         /* read-high */
4370                         __clear_bit(msr, msr_bitmap + 0x400 / f);
4371
4372                 if (type & MSR_TYPE_W)
4373                         /* write-high */
4374                         __clear_bit(msr, msr_bitmap + 0xc00 / f);
4375
4376         }
4377 }
4378
4379 static void __vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
4380                                                 u32 msr, int type)
4381 {
4382         int f = sizeof(unsigned long);
4383
4384         if (!cpu_has_vmx_msr_bitmap())
4385                 return;
4386
4387         /*
4388          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4389          * have the write-low and read-high bitmap offsets the wrong way round.
4390          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4391          */
4392         if (msr <= 0x1fff) {
4393                 if (type & MSR_TYPE_R)
4394                         /* read-low */
4395                         __set_bit(msr, msr_bitmap + 0x000 / f);
4396
4397                 if (type & MSR_TYPE_W)
4398                         /* write-low */
4399                         __set_bit(msr, msr_bitmap + 0x800 / f);
4400
4401         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4402                 msr &= 0x1fff;
4403                 if (type & MSR_TYPE_R)
4404                         /* read-high */
4405                         __set_bit(msr, msr_bitmap + 0x400 / f);
4406
4407                 if (type & MSR_TYPE_W)
4408                         /* write-high */
4409                         __set_bit(msr, msr_bitmap + 0xc00 / f);
4410
4411         }
4412 }
4413
4414 /*
4415  * If a msr is allowed by L0, we should check whether it is allowed by L1.
4416  * The corresponding bit will be cleared unless both of L0 and L1 allow it.
4417  */
4418 static void nested_vmx_disable_intercept_for_msr(unsigned long *msr_bitmap_l1,
4419                                                unsigned long *msr_bitmap_nested,
4420                                                u32 msr, int type)
4421 {
4422         int f = sizeof(unsigned long);
4423
4424         if (!cpu_has_vmx_msr_bitmap()) {
4425                 WARN_ON(1);
4426                 return;
4427         }
4428
4429         /*
4430          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
4431          * have the write-low and read-high bitmap offsets the wrong way round.
4432          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
4433          */
4434         if (msr <= 0x1fff) {
4435                 if (type & MSR_TYPE_R &&
4436                    !test_bit(msr, msr_bitmap_l1 + 0x000 / f))
4437                         /* read-low */
4438                         __clear_bit(msr, msr_bitmap_nested + 0x000 / f);
4439
4440                 if (type & MSR_TYPE_W &&
4441                    !test_bit(msr, msr_bitmap_l1 + 0x800 / f))
4442                         /* write-low */
4443                         __clear_bit(msr, msr_bitmap_nested + 0x800 / f);
4444
4445         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
4446                 msr &= 0x1fff;
4447                 if (type & MSR_TYPE_R &&
4448                    !test_bit(msr, msr_bitmap_l1 + 0x400 / f))
4449                         /* read-high */
4450                         __clear_bit(msr, msr_bitmap_nested + 0x400 / f);
4451
4452                 if (type & MSR_TYPE_W &&
4453                    !test_bit(msr, msr_bitmap_l1 + 0xc00 / f))
4454                         /* write-high */
4455                         __clear_bit(msr, msr_bitmap_nested + 0xc00 / f);
4456
4457         }
4458 }
4459
4460 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
4461 {
4462         if (!longmode_only)
4463                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy,
4464                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4465         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode,
4466                                                 msr, MSR_TYPE_R | MSR_TYPE_W);
4467 }
4468
4469 static void vmx_enable_intercept_msr_read_x2apic(u32 msr)
4470 {
4471         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4472                         msr, MSR_TYPE_R);
4473         __vmx_enable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4474                         msr, MSR_TYPE_R);
4475 }
4476
4477 static void vmx_disable_intercept_msr_read_x2apic(u32 msr)
4478 {
4479         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4480                         msr, MSR_TYPE_R);
4481         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4482                         msr, MSR_TYPE_R);
4483 }
4484
4485 static void vmx_disable_intercept_msr_write_x2apic(u32 msr)
4486 {
4487         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy_x2apic,
4488                         msr, MSR_TYPE_W);
4489         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode_x2apic,
4490                         msr, MSR_TYPE_W);
4491 }
4492
4493 static int vmx_cpu_uses_apicv(struct kvm_vcpu *vcpu)
4494 {
4495         return enable_apicv && lapic_in_kernel(vcpu);
4496 }
4497
4498 static int vmx_complete_nested_posted_interrupt(struct kvm_vcpu *vcpu)
4499 {
4500         struct vcpu_vmx *vmx = to_vmx(vcpu);
4501         int max_irr;
4502         void *vapic_page;
4503         u16 status;
4504
4505         if (vmx->nested.pi_desc &&
4506             vmx->nested.pi_pending) {
4507                 vmx->nested.pi_pending = false;
4508                 if (!pi_test_and_clear_on(vmx->nested.pi_desc))
4509                         return 0;
4510
4511                 max_irr = find_last_bit(
4512                         (unsigned long *)vmx->nested.pi_desc->pir, 256);
4513
4514                 if (max_irr == 256)
4515                         return 0;
4516
4517                 vapic_page = kmap(vmx->nested.virtual_apic_page);
4518                 if (!vapic_page) {
4519                         WARN_ON(1);
4520                         return -ENOMEM;
4521                 }
4522                 __kvm_apic_update_irr(vmx->nested.pi_desc->pir, vapic_page);
4523                 kunmap(vmx->nested.virtual_apic_page);
4524
4525                 status = vmcs_read16(GUEST_INTR_STATUS);
4526                 if ((u8)max_irr > ((u8)status & 0xff)) {
4527                         status &= ~0xff;
4528                         status |= (u8)max_irr;
4529                         vmcs_write16(GUEST_INTR_STATUS, status);
4530                 }
4531         }
4532         return 0;
4533 }
4534
4535 static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu)
4536 {
4537 #ifdef CONFIG_SMP
4538         if (vcpu->mode == IN_GUEST_MODE) {
4539                 struct vcpu_vmx *vmx = to_vmx(vcpu);
4540
4541                 /*
4542                  * Currently, we don't support urgent interrupt,
4543                  * all interrupts are recognized as non-urgent
4544                  * interrupt, so we cannot post interrupts when
4545                  * 'SN' is set.
4546                  *
4547                  * If the vcpu is in guest mode, it means it is
4548                  * running instead of being scheduled out and
4549                  * waiting in the run queue, and that's the only
4550                  * case when 'SN' is set currently, warning if
4551                  * 'SN' is set.
4552                  */
4553                 WARN_ON_ONCE(pi_test_sn(&vmx->pi_desc));
4554
4555                 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu),
4556                                 POSTED_INTR_VECTOR);
4557                 return true;
4558         }
4559 #endif
4560         return false;
4561 }
4562
4563 static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
4564                                                 int vector)
4565 {
4566         struct vcpu_vmx *vmx = to_vmx(vcpu);
4567
4568         if (is_guest_mode(vcpu) &&
4569             vector == vmx->nested.posted_intr_nv) {
4570                 /* the PIR and ON have been set by L1. */
4571                 kvm_vcpu_trigger_posted_interrupt(vcpu);
4572                 /*
4573                  * If a posted intr is not recognized by hardware,
4574                  * we will accomplish it in the next vmentry.
4575                  */
4576                 vmx->nested.pi_pending = true;
4577                 kvm_make_request(KVM_REQ_EVENT, vcpu);
4578                 return 0;
4579         }
4580         return -1;
4581 }
4582 /*
4583  * Send interrupt to vcpu via posted interrupt way.
4584  * 1. If target vcpu is running(non-root mode), send posted interrupt
4585  * notification to vcpu and hardware will sync PIR to vIRR atomically.
4586  * 2. If target vcpu isn't running(root mode), kick it to pick up the
4587  * interrupt from PIR in next vmentry.
4588  */
4589 static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
4590 {
4591         struct vcpu_vmx *vmx = to_vmx(vcpu);
4592         int r;
4593
4594         r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
4595         if (!r)
4596                 return;
4597
4598         if (pi_test_and_set_pir(vector, &vmx->pi_desc))
4599                 return;
4600
4601         r = pi_test_and_set_on(&vmx->pi_desc);
4602         kvm_make_request(KVM_REQ_EVENT, vcpu);
4603         if (r || !kvm_vcpu_trigger_posted_interrupt(vcpu))
4604                 kvm_vcpu_kick(vcpu);
4605 }
4606
4607 static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
4608 {
4609         struct vcpu_vmx *vmx = to_vmx(vcpu);
4610
4611         if (!pi_test_and_clear_on(&vmx->pi_desc))
4612                 return;
4613
4614         kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
4615 }
4616
4617 static void vmx_sync_pir_to_irr_dummy(struct kvm_vcpu *vcpu)
4618 {
4619         return;
4620 }
4621
4622 /*
4623  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
4624  * will not change in the lifetime of the guest.
4625  * Note that host-state that does change is set elsewhere. E.g., host-state
4626  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
4627  */
4628 static void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
4629 {
4630         u32 low32, high32;
4631         unsigned long tmpl;
4632         struct desc_ptr dt;
4633         unsigned long cr4;
4634
4635         vmcs_writel(HOST_CR0, read_cr0() & ~X86_CR0_TS);  /* 22.2.3 */
4636         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
4637
4638         /* Save the most likely value for this task's CR4 in the VMCS. */
4639         cr4 = cr4_read_shadow();
4640         vmcs_writel(HOST_CR4, cr4);                     /* 22.2.3, 22.2.5 */
4641         vmx->host_state.vmcs_host_cr4 = cr4;
4642
4643         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
4644 #ifdef CONFIG_X86_64
4645         /*
4646          * Load null selectors, so we can avoid reloading them in
4647          * __vmx_load_host_state(), in case userspace uses the null selectors
4648          * too (the expected case).
4649          */
4650         vmcs_write16(HOST_DS_SELECTOR, 0);
4651         vmcs_write16(HOST_ES_SELECTOR, 0);
4652 #else
4653         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4654         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4655 #endif
4656         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
4657         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
4658
4659         native_store_idt(&dt);
4660         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
4661         vmx->host_idt_base = dt.address;
4662
4663         vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
4664
4665         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
4666         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
4667         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
4668         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
4669
4670         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
4671                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
4672                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
4673         }
4674 }
4675
4676 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
4677 {
4678         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
4679         if (enable_ept)
4680                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4681         if (is_guest_mode(&vmx->vcpu))
4682                 vmx->vcpu.arch.cr4_guest_owned_bits &=
4683                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
4684         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
4685 }
4686
4687 static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
4688 {
4689         u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
4690
4691         if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4692                 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
4693         return pin_based_exec_ctrl;
4694 }
4695
4696 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
4697 {
4698         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
4699
4700         if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
4701                 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
4702
4703         if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
4704                 exec_control &= ~CPU_BASED_TPR_SHADOW;
4705 #ifdef CONFIG_X86_64
4706                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
4707                                 CPU_BASED_CR8_LOAD_EXITING;
4708 #endif
4709         }
4710         if (!enable_ept)
4711                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
4712                                 CPU_BASED_CR3_LOAD_EXITING  |
4713                                 CPU_BASED_INVLPG_EXITING;
4714         return exec_control;
4715 }
4716
4717 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
4718 {
4719         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
4720         if (!cpu_need_virtualize_apic_accesses(&vmx->vcpu))
4721                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
4722         if (vmx->vpid == 0)
4723                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
4724         if (!enable_ept) {
4725                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
4726                 enable_unrestricted_guest = 0;
4727                 /* Enable INVPCID for non-ept guests may cause performance regression. */
4728                 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
4729         }
4730         if (!enable_unrestricted_guest)
4731                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4732         if (!ple_gap)
4733                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
4734         if (!vmx_cpu_uses_apicv(&vmx->vcpu))
4735                 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
4736                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
4737         exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
4738         /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
4739            (handle_vmptrld).
4740            We can NOT enable shadow_vmcs here because we don't have yet
4741            a current VMCS12
4742         */
4743         exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
4744
4745         if (!enable_pml)
4746                 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
4747
4748         /* Currently, we allow L1 guest to directly run pcommit instruction. */
4749         exec_control &= ~SECONDARY_EXEC_PCOMMIT;
4750
4751         return exec_control;
4752 }
4753
4754 static void ept_set_mmio_spte_mask(void)
4755 {
4756         /*
4757          * EPT Misconfigurations can be generated if the value of bits 2:0
4758          * of an EPT paging-structure entry is 110b (write/execute).
4759          * Also, magic bits (0x3ull << 62) is set to quickly identify mmio
4760          * spte.
4761          */
4762         kvm_mmu_set_mmio_spte_mask((0x3ull << 62) | 0x6ull);
4763 }
4764
4765 #define VMX_XSS_EXIT_BITMAP 0
4766 /*
4767  * Sets up the vmcs for emulated real mode.
4768  */
4769 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
4770 {
4771 #ifdef CONFIG_X86_64
4772         unsigned long a;
4773 #endif
4774         int i;
4775
4776         /* I/O */
4777         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
4778         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
4779
4780         if (enable_shadow_vmcs) {
4781                 vmcs_write64(VMREAD_BITMAP, __pa(vmx_vmread_bitmap));
4782                 vmcs_write64(VMWRITE_BITMAP, __pa(vmx_vmwrite_bitmap));
4783         }
4784         if (cpu_has_vmx_msr_bitmap())
4785                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
4786
4787         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
4788
4789         /* Control */
4790         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
4791
4792         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
4793
4794         if (cpu_has_secondary_exec_ctrls())
4795                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4796                                 vmx_secondary_exec_control(vmx));
4797
4798         if (vmx_cpu_uses_apicv(&vmx->vcpu)) {
4799                 vmcs_write64(EOI_EXIT_BITMAP0, 0);
4800                 vmcs_write64(EOI_EXIT_BITMAP1, 0);
4801                 vmcs_write64(EOI_EXIT_BITMAP2, 0);
4802                 vmcs_write64(EOI_EXIT_BITMAP3, 0);
4803
4804                 vmcs_write16(GUEST_INTR_STATUS, 0);
4805
4806                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
4807                 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
4808         }
4809
4810         if (ple_gap) {
4811                 vmcs_write32(PLE_GAP, ple_gap);
4812                 vmx->ple_window = ple_window;
4813                 vmx->ple_window_dirty = true;
4814         }
4815
4816         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
4817         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
4818         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
4819
4820         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
4821         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
4822         vmx_set_constant_host_state(vmx);
4823 #ifdef CONFIG_X86_64
4824         rdmsrl(MSR_FS_BASE, a);
4825         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
4826         rdmsrl(MSR_GS_BASE, a);
4827         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
4828 #else
4829         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
4830         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
4831 #endif
4832
4833         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
4834         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
4835         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
4836         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
4837         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
4838
4839         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
4840                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
4841
4842         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
4843                 u32 index = vmx_msr_index[i];
4844                 u32 data_low, data_high;
4845                 int j = vmx->nmsrs;
4846
4847                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
4848                         continue;
4849                 if (wrmsr_safe(index, data_low, data_high) < 0)
4850                         continue;
4851                 vmx->guest_msrs[j].index = i;
4852                 vmx->guest_msrs[j].data = 0;
4853                 vmx->guest_msrs[j].mask = -1ull;
4854                 ++vmx->nmsrs;
4855         }
4856
4857
4858         vm_exit_controls_init(vmx, vmcs_config.vmexit_ctrl);
4859
4860         /* 22.2.1, 20.8.1 */
4861         vm_entry_controls_init(vmx, vmcs_config.vmentry_ctrl);
4862
4863         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4864         set_cr4_guest_host_mask(vmx);
4865
4866         if (vmx_xsaves_supported())
4867                 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
4868
4869         return 0;
4870 }
4871
4872 static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
4873 {
4874         struct vcpu_vmx *vmx = to_vmx(vcpu);
4875         struct msr_data apic_base_msr;
4876         u64 cr0;
4877
4878         vmx->rmode.vm86_active = 0;
4879
4880         vmx->soft_vnmi_blocked = 0;
4881
4882         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
4883         kvm_set_cr8(vcpu, 0);
4884
4885         if (!init_event) {
4886                 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
4887                                      MSR_IA32_APICBASE_ENABLE;
4888                 if (kvm_vcpu_is_reset_bsp(vcpu))
4889                         apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
4890                 apic_base_msr.host_initiated = true;
4891                 kvm_set_apic_base(vcpu, &apic_base_msr);
4892         }
4893
4894         vmx_segment_cache_clear(vmx);
4895
4896         seg_setup(VCPU_SREG_CS);
4897         vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
4898         vmcs_write32(GUEST_CS_BASE, 0xffff0000);
4899
4900         seg_setup(VCPU_SREG_DS);
4901         seg_setup(VCPU_SREG_ES);
4902         seg_setup(VCPU_SREG_FS);
4903         seg_setup(VCPU_SREG_GS);
4904         seg_setup(VCPU_SREG_SS);
4905
4906         vmcs_write16(GUEST_TR_SELECTOR, 0);
4907         vmcs_writel(GUEST_TR_BASE, 0);
4908         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
4909         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
4910
4911         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
4912         vmcs_writel(GUEST_LDTR_BASE, 0);
4913         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
4914         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
4915
4916         if (!init_event) {
4917                 vmcs_write32(GUEST_SYSENTER_CS, 0);
4918                 vmcs_writel(GUEST_SYSENTER_ESP, 0);
4919                 vmcs_writel(GUEST_SYSENTER_EIP, 0);
4920                 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
4921         }
4922
4923         vmcs_writel(GUEST_RFLAGS, 0x02);
4924         kvm_rip_write(vcpu, 0xfff0);
4925
4926         vmcs_writel(GUEST_GDTR_BASE, 0);
4927         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
4928
4929         vmcs_writel(GUEST_IDTR_BASE, 0);
4930         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
4931
4932         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
4933         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
4934         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
4935
4936         setup_msrs(vmx);
4937
4938         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
4939
4940         if (cpu_has_vmx_tpr_shadow() && !init_event) {
4941                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
4942                 if (cpu_need_tpr_shadow(vcpu))
4943                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
4944                                      __pa(vcpu->arch.apic->regs));
4945                 vmcs_write32(TPR_THRESHOLD, 0);
4946         }
4947
4948         kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
4949
4950         if (vmx_cpu_uses_apicv(vcpu))
4951                 memset(&vmx->pi_desc, 0, sizeof(struct pi_desc));
4952
4953         if (vmx->vpid != 0)
4954                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
4955
4956         cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4957         vmx_set_cr0(vcpu, cr0); /* enter rmode */
4958         vmx->vcpu.arch.cr0 = cr0;
4959         vmx_set_cr4(vcpu, 0);
4960         vmx_set_efer(vcpu, 0);
4961         vmx_fpu_activate(vcpu);
4962         update_exception_bitmap(vcpu);
4963
4964         vpid_sync_context(vmx->vpid);
4965 }
4966
4967 /*
4968  * In nested virtualization, check if L1 asked to exit on external interrupts.
4969  * For most existing hypervisors, this will always return true.
4970  */
4971 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
4972 {
4973         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4974                 PIN_BASED_EXT_INTR_MASK;
4975 }
4976
4977 /*
4978  * In nested virtualization, check if L1 has set
4979  * VM_EXIT_ACK_INTR_ON_EXIT
4980  */
4981 static bool nested_exit_intr_ack_set(struct kvm_vcpu *vcpu)
4982 {
4983         return get_vmcs12(vcpu)->vm_exit_controls &
4984                 VM_EXIT_ACK_INTR_ON_EXIT;
4985 }
4986
4987 static bool nested_exit_on_nmi(struct kvm_vcpu *vcpu)
4988 {
4989         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
4990                 PIN_BASED_NMI_EXITING;
4991 }
4992
4993 static void enable_irq_window(struct kvm_vcpu *vcpu)
4994 {
4995         u32 cpu_based_vm_exec_control;
4996
4997         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4998         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
4999         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5000 }
5001
5002 static void enable_nmi_window(struct kvm_vcpu *vcpu)
5003 {
5004         u32 cpu_based_vm_exec_control;
5005
5006         if (!cpu_has_virtual_nmis() ||
5007             vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
5008                 enable_irq_window(vcpu);
5009                 return;
5010         }
5011
5012         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5013         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
5014         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5015 }
5016
5017 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
5018 {
5019         struct vcpu_vmx *vmx = to_vmx(vcpu);
5020         uint32_t intr;
5021         int irq = vcpu->arch.interrupt.nr;
5022
5023         trace_kvm_inj_virq(irq);
5024
5025         ++vcpu->stat.irq_injections;
5026         if (vmx->rmode.vm86_active) {
5027                 int inc_eip = 0;
5028                 if (vcpu->arch.interrupt.soft)
5029                         inc_eip = vcpu->arch.event_exit_inst_len;
5030                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
5031                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5032                 return;
5033         }
5034         intr = irq | INTR_INFO_VALID_MASK;
5035         if (vcpu->arch.interrupt.soft) {
5036                 intr |= INTR_TYPE_SOFT_INTR;
5037                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5038                              vmx->vcpu.arch.event_exit_inst_len);
5039         } else
5040                 intr |= INTR_TYPE_EXT_INTR;
5041         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
5042 }
5043
5044 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
5045 {
5046         struct vcpu_vmx *vmx = to_vmx(vcpu);
5047
5048         if (is_guest_mode(vcpu))
5049                 return;
5050
5051         if (!cpu_has_virtual_nmis()) {
5052                 /*
5053                  * Tracking the NMI-blocked state in software is built upon
5054                  * finding the next open IRQ window. This, in turn, depends on
5055                  * well-behaving guests: They have to keep IRQs disabled at
5056                  * least as long as the NMI handler runs. Otherwise we may
5057                  * cause NMI nesting, maybe breaking the guest. But as this is
5058                  * highly unlikely, we can live with the residual risk.
5059                  */
5060                 vmx->soft_vnmi_blocked = 1;
5061                 vmx->vnmi_blocked_time = 0;
5062         }
5063
5064         ++vcpu->stat.nmi_injections;
5065         vmx->nmi_known_unmasked = false;
5066         if (vmx->rmode.vm86_active) {
5067                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
5068                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5069                 return;
5070         }
5071         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5072                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
5073 }
5074
5075 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
5076 {
5077         if (!cpu_has_virtual_nmis())
5078                 return to_vmx(vcpu)->soft_vnmi_blocked;
5079         if (to_vmx(vcpu)->nmi_known_unmasked)
5080                 return false;
5081         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
5082 }
5083
5084 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
5085 {
5086         struct vcpu_vmx *vmx = to_vmx(vcpu);
5087
5088         if (!cpu_has_virtual_nmis()) {
5089                 if (vmx->soft_vnmi_blocked != masked) {
5090                         vmx->soft_vnmi_blocked = masked;
5091                         vmx->vnmi_blocked_time = 0;
5092                 }
5093         } else {
5094                 vmx->nmi_known_unmasked = !masked;
5095                 if (masked)
5096                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5097                                       GUEST_INTR_STATE_NMI);
5098                 else
5099                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
5100                                         GUEST_INTR_STATE_NMI);
5101         }
5102 }
5103
5104 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
5105 {
5106         if (to_vmx(vcpu)->nested.nested_run_pending)
5107                 return 0;
5108
5109         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
5110                 return 0;
5111
5112         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5113                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
5114                    | GUEST_INTR_STATE_NMI));
5115 }
5116
5117 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
5118 {
5119         return (!to_vmx(vcpu)->nested.nested_run_pending &&
5120                 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
5121                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
5122                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
5123 }
5124
5125 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
5126 {
5127         int ret;
5128
5129         ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
5130                                     PAGE_SIZE * 3);
5131         if (ret)
5132                 return ret;
5133         kvm->arch.tss_addr = addr;
5134         return init_rmode_tss(kvm);
5135 }
5136
5137 static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
5138 {
5139         switch (vec) {
5140         case BP_VECTOR:
5141                 /*
5142                  * Update instruction length as we may reinject the exception
5143                  * from user space while in guest debugging mode.
5144                  */
5145                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
5146                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5147                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
5148                         return false;
5149                 /* fall through */
5150         case DB_VECTOR:
5151                 if (vcpu->guest_debug &
5152                         (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
5153                         return false;
5154                 /* fall through */
5155         case DE_VECTOR:
5156         case OF_VECTOR:
5157         case BR_VECTOR:
5158         case UD_VECTOR:
5159         case DF_VECTOR:
5160         case SS_VECTOR:
5161         case GP_VECTOR:
5162         case MF_VECTOR:
5163                 return true;
5164         break;
5165         }
5166         return false;
5167 }
5168
5169 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
5170                                   int vec, u32 err_code)
5171 {
5172         /*
5173          * Instruction with address size override prefix opcode 0x67
5174          * Cause the #SS fault with 0 error code in VM86 mode.
5175          */
5176         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
5177                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE) {
5178                         if (vcpu->arch.halt_request) {
5179                                 vcpu->arch.halt_request = 0;
5180                                 return kvm_vcpu_halt(vcpu);
5181                         }
5182                         return 1;
5183                 }
5184                 return 0;
5185         }
5186
5187         /*
5188          * Forward all other exceptions that are valid in real mode.
5189          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
5190          *        the required debugging infrastructure rework.
5191          */
5192         kvm_queue_exception(vcpu, vec);
5193         return 1;
5194 }
5195
5196 /*
5197  * Trigger machine check on the host. We assume all the MSRs are already set up
5198  * by the CPU and that we still run on the same CPU as the MCE occurred on.
5199  * We pass a fake environment to the machine check handler because we want
5200  * the guest to be always treated like user space, no matter what context
5201  * it used internally.
5202  */
5203 static void kvm_machine_check(void)
5204 {
5205 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
5206         struct pt_regs regs = {
5207                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
5208                 .flags = X86_EFLAGS_IF,
5209         };
5210
5211         do_machine_check(&regs, 0);
5212 #endif
5213 }
5214
5215 static int handle_machine_check(struct kvm_vcpu *vcpu)
5216 {
5217         /* already handled by vcpu_run */
5218         return 1;
5219 }
5220
5221 static int handle_exception(struct kvm_vcpu *vcpu)
5222 {
5223         struct vcpu_vmx *vmx = to_vmx(vcpu);
5224         struct kvm_run *kvm_run = vcpu->run;
5225         u32 intr_info, ex_no, error_code;
5226         unsigned long cr2, rip, dr6;
5227         u32 vect_info;
5228         enum emulation_result er;
5229
5230         vect_info = vmx->idt_vectoring_info;
5231         intr_info = vmx->exit_intr_info;
5232
5233         if (is_machine_check(intr_info))
5234                 return handle_machine_check(vcpu);
5235
5236         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
5237                 return 1;  /* already handled by vmx_vcpu_run() */
5238
5239         if (is_no_device(intr_info)) {
5240                 vmx_fpu_activate(vcpu);
5241                 return 1;
5242         }
5243
5244         if (is_invalid_opcode(intr_info)) {
5245                 if (is_guest_mode(vcpu)) {
5246                         kvm_queue_exception(vcpu, UD_VECTOR);
5247                         return 1;
5248                 }
5249                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
5250                 if (er != EMULATE_DONE)
5251                         kvm_queue_exception(vcpu, UD_VECTOR);
5252                 return 1;
5253         }
5254
5255         error_code = 0;
5256         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
5257                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
5258
5259         /*
5260          * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
5261          * MMIO, it is better to report an internal error.
5262          * See the comments in vmx_handle_exit.
5263          */
5264         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
5265             !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
5266                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5267                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
5268                 vcpu->run->internal.ndata = 3;
5269                 vcpu->run->internal.data[0] = vect_info;
5270                 vcpu->run->internal.data[1] = intr_info;
5271                 vcpu->run->internal.data[2] = error_code;
5272                 return 0;
5273         }
5274
5275         if (is_page_fault(intr_info)) {
5276                 /* EPT won't cause page fault directly */
5277                 BUG_ON(enable_ept);
5278                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
5279                 trace_kvm_page_fault(cr2, error_code);
5280
5281                 if (kvm_event_needs_reinjection(vcpu))
5282                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
5283                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
5284         }
5285
5286         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
5287
5288         if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
5289                 return handle_rmode_exception(vcpu, ex_no, error_code);
5290
5291         switch (ex_no) {
5292         case AC_VECTOR:
5293                 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
5294                 return 1;
5295         case DB_VECTOR:
5296                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
5297                 if (!(vcpu->guest_debug &
5298                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
5299                         vcpu->arch.dr6 &= ~15;
5300                         vcpu->arch.dr6 |= dr6 | DR6_RTM;
5301                         if (!(dr6 & ~DR6_RESERVED)) /* icebp */
5302                                 skip_emulated_instruction(vcpu);
5303
5304                         kvm_queue_exception(vcpu, DB_VECTOR);
5305                         return 1;
5306                 }
5307                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5308                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
5309                 /* fall through */
5310         case BP_VECTOR:
5311                 /*
5312                  * Update instruction length as we may reinject #BP from
5313                  * user space while in guest debugging mode. Reading it for
5314                  * #DB as well causes no harm, it is not used in that case.
5315                  */
5316                 vmx->vcpu.arch.event_exit_inst_len =
5317                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5318                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5319                 rip = kvm_rip_read(vcpu);
5320                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
5321                 kvm_run->debug.arch.exception = ex_no;
5322                 break;
5323         default:
5324                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
5325                 kvm_run->ex.exception = ex_no;
5326                 kvm_run->ex.error_code = error_code;
5327                 break;
5328         }
5329         return 0;
5330 }
5331
5332 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
5333 {
5334         ++vcpu->stat.irq_exits;
5335         return 1;
5336 }
5337
5338 static int handle_triple_fault(struct kvm_vcpu *vcpu)
5339 {
5340         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
5341         return 0;
5342 }
5343
5344 static int handle_io(struct kvm_vcpu *vcpu)
5345 {
5346         unsigned long exit_qualification;
5347         int size, in, string;
5348         unsigned port;
5349
5350         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5351         string = (exit_qualification & 16) != 0;
5352         in = (exit_qualification & 8) != 0;
5353
5354         ++vcpu->stat.io_exits;
5355
5356         if (string || in)
5357                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5358
5359         port = exit_qualification >> 16;
5360         size = (exit_qualification & 7) + 1;
5361         skip_emulated_instruction(vcpu);
5362
5363         return kvm_fast_pio_out(vcpu, size, port);
5364 }
5365
5366 static void
5367 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
5368 {
5369         /*
5370          * Patch in the VMCALL instruction:
5371          */
5372         hypercall[0] = 0x0f;
5373         hypercall[1] = 0x01;
5374         hypercall[2] = 0xc1;
5375 }
5376
5377 static bool nested_cr0_valid(struct kvm_vcpu *vcpu, unsigned long val)
5378 {
5379         unsigned long always_on = VMXON_CR0_ALWAYSON;
5380         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5381
5382         if (to_vmx(vcpu)->nested.nested_vmx_secondary_ctls_high &
5383                 SECONDARY_EXEC_UNRESTRICTED_GUEST &&
5384             nested_cpu_has2(vmcs12, SECONDARY_EXEC_UNRESTRICTED_GUEST))
5385                 always_on &= ~(X86_CR0_PE | X86_CR0_PG);
5386         return (val & always_on) == always_on;
5387 }
5388
5389 /* called to set cr0 as appropriate for a mov-to-cr0 exit. */
5390 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
5391 {
5392         if (is_guest_mode(vcpu)) {
5393                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5394                 unsigned long orig_val = val;
5395
5396                 /*
5397                  * We get here when L2 changed cr0 in a way that did not change
5398                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
5399                  * but did change L0 shadowed bits. So we first calculate the
5400                  * effective cr0 value that L1 would like to write into the
5401                  * hardware. It consists of the L2-owned bits from the new
5402                  * value combined with the L1-owned bits from L1's guest_cr0.
5403                  */
5404                 val = (val & ~vmcs12->cr0_guest_host_mask) |
5405                         (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
5406
5407                 if (!nested_cr0_valid(vcpu, val))
5408                         return 1;
5409
5410                 if (kvm_set_cr0(vcpu, val))
5411                         return 1;
5412                 vmcs_writel(CR0_READ_SHADOW, orig_val);
5413                 return 0;
5414         } else {
5415                 if (to_vmx(vcpu)->nested.vmxon &&
5416                     ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
5417                         return 1;
5418                 return kvm_set_cr0(vcpu, val);
5419         }
5420 }
5421
5422 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
5423 {
5424         if (is_guest_mode(vcpu)) {
5425                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5426                 unsigned long orig_val = val;
5427
5428                 /* analogously to handle_set_cr0 */
5429                 val = (val & ~vmcs12->cr4_guest_host_mask) |
5430                         (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
5431                 if (kvm_set_cr4(vcpu, val))
5432                         return 1;
5433                 vmcs_writel(CR4_READ_SHADOW, orig_val);
5434                 return 0;
5435         } else
5436                 return kvm_set_cr4(vcpu, val);
5437 }
5438
5439 /* called to set cr0 as approriate for clts instruction exit. */
5440 static void handle_clts(struct kvm_vcpu *vcpu)
5441 {
5442         if (is_guest_mode(vcpu)) {
5443                 /*
5444                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
5445                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
5446                  * just pretend it's off (also in arch.cr0 for fpu_activate).
5447                  */
5448                 vmcs_writel(CR0_READ_SHADOW,
5449                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
5450                 vcpu->arch.cr0 &= ~X86_CR0_TS;
5451         } else
5452                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
5453 }
5454
5455 static int handle_cr(struct kvm_vcpu *vcpu)
5456 {
5457         unsigned long exit_qualification, val;
5458         int cr;
5459         int reg;
5460         int err;
5461
5462         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5463         cr = exit_qualification & 15;
5464         reg = (exit_qualification >> 8) & 15;
5465         switch ((exit_qualification >> 4) & 3) {
5466         case 0: /* mov to cr */
5467                 val = kvm_register_readl(vcpu, reg);
5468                 trace_kvm_cr_write(cr, val);
5469                 switch (cr) {
5470                 case 0:
5471                         err = handle_set_cr0(vcpu, val);
5472                         kvm_complete_insn_gp(vcpu, err);
5473                         return 1;
5474                 case 3:
5475                         err = kvm_set_cr3(vcpu, val);
5476                         kvm_complete_insn_gp(vcpu, err);
5477                         return 1;
5478                 case 4:
5479                         err = handle_set_cr4(vcpu, val);
5480                         kvm_complete_insn_gp(vcpu, err);
5481                         return 1;
5482                 case 8: {
5483                                 u8 cr8_prev = kvm_get_cr8(vcpu);
5484                                 u8 cr8 = (u8)val;
5485                                 err = kvm_set_cr8(vcpu, cr8);
5486                                 kvm_complete_insn_gp(vcpu, err);
5487                                 if (lapic_in_kernel(vcpu))
5488                                         return 1;
5489                                 if (cr8_prev <= cr8)
5490                                         return 1;
5491                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
5492                                 return 0;
5493                         }
5494                 }
5495                 break;
5496         case 2: /* clts */
5497                 handle_clts(vcpu);
5498                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
5499                 skip_emulated_instruction(vcpu);
5500                 vmx_fpu_activate(vcpu);
5501                 return 1;
5502         case 1: /*mov from cr*/
5503                 switch (cr) {
5504                 case 3:
5505                         val = kvm_read_cr3(vcpu);
5506                         kvm_register_write(vcpu, reg, val);
5507                         trace_kvm_cr_read(cr, val);
5508                         skip_emulated_instruction(vcpu);
5509                         return 1;
5510                 case 8:
5511                         val = kvm_get_cr8(vcpu);
5512                         kvm_register_write(vcpu, reg, val);
5513                         trace_kvm_cr_read(cr, val);
5514                         skip_emulated_instruction(vcpu);
5515                         return 1;
5516                 }
5517                 break;
5518         case 3: /* lmsw */
5519                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
5520                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
5521                 kvm_lmsw(vcpu, val);
5522
5523                 skip_emulated_instruction(vcpu);
5524                 return 1;
5525         default:
5526                 break;
5527         }
5528         vcpu->run->exit_reason = 0;
5529         vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
5530                (int)(exit_qualification >> 4) & 3, cr);
5531         return 0;
5532 }
5533
5534 static int handle_dr(struct kvm_vcpu *vcpu)
5535 {
5536         unsigned long exit_qualification;
5537         int dr, dr7, reg;
5538
5539         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5540         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
5541
5542         /* First, if DR does not exist, trigger UD */
5543         if (!kvm_require_dr(vcpu, dr))
5544                 return 1;
5545
5546         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
5547         if (!kvm_require_cpl(vcpu, 0))
5548                 return 1;
5549         dr7 = vmcs_readl(GUEST_DR7);
5550         if (dr7 & DR7_GD) {
5551                 /*
5552                  * As the vm-exit takes precedence over the debug trap, we
5553                  * need to emulate the latter, either for the host or the
5554                  * guest debugging itself.
5555                  */
5556                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
5557                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
5558                         vcpu->run->debug.arch.dr7 = dr7;
5559                         vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
5560                         vcpu->run->debug.arch.exception = DB_VECTOR;
5561                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
5562                         return 0;
5563                 } else {
5564                         vcpu->arch.dr6 &= ~15;
5565                         vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
5566                         kvm_queue_exception(vcpu, DB_VECTOR);
5567                         return 1;
5568                 }
5569         }
5570
5571         if (vcpu->guest_debug == 0) {
5572                 u32 cpu_based_vm_exec_control;
5573
5574                 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5575                 cpu_based_vm_exec_control &= ~CPU_BASED_MOV_DR_EXITING;
5576                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5577
5578                 /*
5579                  * No more DR vmexits; force a reload of the debug registers
5580                  * and reenter on this instruction.  The next vmexit will
5581                  * retrieve the full state of the debug registers.
5582                  */
5583                 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
5584                 return 1;
5585         }
5586
5587         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
5588         if (exit_qualification & TYPE_MOV_FROM_DR) {
5589                 unsigned long val;
5590
5591                 if (kvm_get_dr(vcpu, dr, &val))
5592                         return 1;
5593                 kvm_register_write(vcpu, reg, val);
5594         } else
5595                 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
5596                         return 1;
5597
5598         skip_emulated_instruction(vcpu);
5599         return 1;
5600 }
5601
5602 static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
5603 {
5604         return vcpu->arch.dr6;
5605 }
5606
5607 static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
5608 {
5609 }
5610
5611 static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
5612 {
5613         u32 cpu_based_vm_exec_control;
5614
5615         get_debugreg(vcpu->arch.db[0], 0);
5616         get_debugreg(vcpu->arch.db[1], 1);
5617         get_debugreg(vcpu->arch.db[2], 2);
5618         get_debugreg(vcpu->arch.db[3], 3);
5619         get_debugreg(vcpu->arch.dr6, 6);
5620         vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
5621
5622         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
5623
5624         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5625         cpu_based_vm_exec_control |= CPU_BASED_MOV_DR_EXITING;
5626         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5627 }
5628
5629 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
5630 {
5631         vmcs_writel(GUEST_DR7, val);
5632 }
5633
5634 static int handle_cpuid(struct kvm_vcpu *vcpu)
5635 {
5636         kvm_emulate_cpuid(vcpu);
5637         return 1;
5638 }
5639
5640 static int handle_rdmsr(struct kvm_vcpu *vcpu)
5641 {
5642         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5643         struct msr_data msr_info;
5644
5645         msr_info.index = ecx;
5646         msr_info.host_initiated = false;
5647         if (vmx_get_msr(vcpu, &msr_info)) {
5648                 trace_kvm_msr_read_ex(ecx);
5649                 kvm_inject_gp(vcpu, 0);
5650                 return 1;
5651         }
5652
5653         trace_kvm_msr_read(ecx, msr_info.data);
5654
5655         /* FIXME: handling of bits 32:63 of rax, rdx */
5656         vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
5657         vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
5658         skip_emulated_instruction(vcpu);
5659         return 1;
5660 }
5661
5662 static int handle_wrmsr(struct kvm_vcpu *vcpu)
5663 {
5664         struct msr_data msr;
5665         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
5666         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
5667                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
5668
5669         msr.data = data;
5670         msr.index = ecx;
5671         msr.host_initiated = false;
5672         if (kvm_set_msr(vcpu, &msr) != 0) {
5673                 trace_kvm_msr_write_ex(ecx, data);
5674                 kvm_inject_gp(vcpu, 0);
5675                 return 1;
5676         }
5677
5678         trace_kvm_msr_write(ecx, data);
5679         skip_emulated_instruction(vcpu);
5680         return 1;
5681 }
5682
5683 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
5684 {
5685         kvm_make_request(KVM_REQ_EVENT, vcpu);
5686         return 1;
5687 }
5688
5689 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
5690 {
5691         u32 cpu_based_vm_exec_control;
5692
5693         /* clear pending irq */
5694         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5695         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
5696         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5697
5698         kvm_make_request(KVM_REQ_EVENT, vcpu);
5699
5700         ++vcpu->stat.irq_window_exits;
5701         return 1;
5702 }
5703
5704 static int handle_halt(struct kvm_vcpu *vcpu)
5705 {
5706         return kvm_emulate_halt(vcpu);
5707 }
5708
5709 static int handle_vmcall(struct kvm_vcpu *vcpu)
5710 {
5711         kvm_emulate_hypercall(vcpu);
5712         return 1;
5713 }
5714
5715 static int handle_invd(struct kvm_vcpu *vcpu)
5716 {
5717         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5718 }
5719
5720 static int handle_invlpg(struct kvm_vcpu *vcpu)
5721 {
5722         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5723
5724         kvm_mmu_invlpg(vcpu, exit_qualification);
5725         skip_emulated_instruction(vcpu);
5726         return 1;
5727 }
5728
5729 static int handle_rdpmc(struct kvm_vcpu *vcpu)
5730 {
5731         int err;
5732
5733         err = kvm_rdpmc(vcpu);
5734         kvm_complete_insn_gp(vcpu, err);
5735
5736         return 1;
5737 }
5738
5739 static int handle_wbinvd(struct kvm_vcpu *vcpu)
5740 {
5741         kvm_emulate_wbinvd(vcpu);
5742         return 1;
5743 }
5744
5745 static int handle_xsetbv(struct kvm_vcpu *vcpu)
5746 {
5747         u64 new_bv = kvm_read_edx_eax(vcpu);
5748         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
5749
5750         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
5751                 skip_emulated_instruction(vcpu);
5752         return 1;
5753 }
5754
5755 static int handle_xsaves(struct kvm_vcpu *vcpu)
5756 {
5757         skip_emulated_instruction(vcpu);
5758         WARN(1, "this should never happen\n");
5759         return 1;
5760 }
5761
5762 static int handle_xrstors(struct kvm_vcpu *vcpu)
5763 {
5764         skip_emulated_instruction(vcpu);
5765         WARN(1, "this should never happen\n");
5766         return 1;
5767 }
5768
5769 static int handle_apic_access(struct kvm_vcpu *vcpu)
5770 {
5771         if (likely(fasteoi)) {
5772                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5773                 int access_type, offset;
5774
5775                 access_type = exit_qualification & APIC_ACCESS_TYPE;
5776                 offset = exit_qualification & APIC_ACCESS_OFFSET;
5777                 /*
5778                  * Sane guest uses MOV to write EOI, with written value
5779                  * not cared. So make a short-circuit here by avoiding
5780                  * heavy instruction emulation.
5781                  */
5782                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
5783                     (offset == APIC_EOI)) {
5784                         kvm_lapic_set_eoi(vcpu);
5785                         skip_emulated_instruction(vcpu);
5786                         return 1;
5787                 }
5788         }
5789         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
5790 }
5791
5792 static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
5793 {
5794         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5795         int vector = exit_qualification & 0xff;
5796
5797         /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
5798         kvm_apic_set_eoi_accelerated(vcpu, vector);
5799         return 1;
5800 }
5801
5802 static int handle_apic_write(struct kvm_vcpu *vcpu)
5803 {
5804         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5805         u32 offset = exit_qualification & 0xfff;
5806
5807         /* APIC-write VM exit is trap-like and thus no need to adjust IP */
5808         kvm_apic_write_nodecode(vcpu, offset);
5809         return 1;
5810 }
5811
5812 static int handle_task_switch(struct kvm_vcpu *vcpu)
5813 {
5814         struct vcpu_vmx *vmx = to_vmx(vcpu);
5815         unsigned long exit_qualification;
5816         bool has_error_code = false;
5817         u32 error_code = 0;
5818         u16 tss_selector;
5819         int reason, type, idt_v, idt_index;
5820
5821         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
5822         idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
5823         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
5824
5825         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5826
5827         reason = (u32)exit_qualification >> 30;
5828         if (reason == TASK_SWITCH_GATE && idt_v) {
5829                 switch (type) {
5830                 case INTR_TYPE_NMI_INTR:
5831                         vcpu->arch.nmi_injected = false;
5832                         vmx_set_nmi_mask(vcpu, true);
5833                         break;
5834                 case INTR_TYPE_EXT_INTR:
5835                 case INTR_TYPE_SOFT_INTR:
5836                         kvm_clear_interrupt_queue(vcpu);
5837                         break;
5838                 case INTR_TYPE_HARD_EXCEPTION:
5839                         if (vmx->idt_vectoring_info &
5840                             VECTORING_INFO_DELIVER_CODE_MASK) {
5841                                 has_error_code = true;
5842                                 error_code =
5843                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
5844                         }
5845                         /* fall through */
5846                 case INTR_TYPE_SOFT_EXCEPTION:
5847                         kvm_clear_exception_queue(vcpu);
5848                         break;
5849                 default:
5850                         break;
5851                 }
5852         }
5853         tss_selector = exit_qualification;
5854
5855         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
5856                        type != INTR_TYPE_EXT_INTR &&
5857                        type != INTR_TYPE_NMI_INTR))
5858                 skip_emulated_instruction(vcpu);
5859
5860         if (kvm_task_switch(vcpu, tss_selector,
5861                             type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
5862                             has_error_code, error_code) == EMULATE_FAIL) {
5863                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5864                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
5865                 vcpu->run->internal.ndata = 0;
5866                 return 0;
5867         }
5868
5869         /*
5870          * TODO: What about debug traps on tss switch?
5871          *       Are we supposed to inject them and update dr6?
5872          */
5873
5874         return 1;
5875 }
5876
5877 static int handle_ept_violation(struct kvm_vcpu *vcpu)
5878 {
5879         unsigned long exit_qualification;
5880         gpa_t gpa;
5881         u32 error_code;
5882         int gla_validity;
5883
5884         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5885
5886         gla_validity = (exit_qualification >> 7) & 0x3;
5887         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
5888                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
5889                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
5890                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
5891                         vmcs_readl(GUEST_LINEAR_ADDRESS));
5892                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
5893                         (long unsigned int)exit_qualification);
5894                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5895                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
5896                 return 0;
5897         }
5898
5899         /*
5900          * EPT violation happened while executing iret from NMI,
5901          * "blocked by NMI" bit has to be set before next VM entry.
5902          * There are errata that may cause this bit to not be set:
5903          * AAK134, BY25.
5904          */
5905         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5906                         cpu_has_virtual_nmis() &&
5907                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5908                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
5909
5910         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5911         trace_kvm_page_fault(gpa, exit_qualification);
5912
5913         /* It is a write fault? */
5914         error_code = exit_qualification & PFERR_WRITE_MASK;
5915         /* It is a fetch fault? */
5916         error_code |= (exit_qualification << 2) & PFERR_FETCH_MASK;
5917         /* ept page table is present? */
5918         error_code |= (exit_qualification >> 3) & PFERR_PRESENT_MASK;
5919
5920         vcpu->arch.exit_qualification = exit_qualification;
5921
5922         return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
5923 }
5924
5925 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
5926 {
5927         int ret;
5928         gpa_t gpa;
5929
5930         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5931         if (!kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
5932                 skip_emulated_instruction(vcpu);
5933                 trace_kvm_fast_mmio(gpa);
5934                 return 1;
5935         }
5936
5937         ret = handle_mmio_page_fault(vcpu, gpa, true);
5938         if (likely(ret == RET_MMIO_PF_EMULATE))
5939                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
5940                                               EMULATE_DONE;
5941
5942         if (unlikely(ret == RET_MMIO_PF_INVALID))
5943                 return kvm_mmu_page_fault(vcpu, gpa, 0, NULL, 0);
5944
5945         if (unlikely(ret == RET_MMIO_PF_RETRY))
5946                 return 1;
5947
5948         /* It is the real ept misconfig */
5949         WARN_ON(1);
5950
5951         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5952         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
5953
5954         return 0;
5955 }
5956
5957 static int handle_nmi_window(struct kvm_vcpu *vcpu)
5958 {
5959         u32 cpu_based_vm_exec_control;
5960
5961         /* clear pending NMI */
5962         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5963         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
5964         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
5965         ++vcpu->stat.nmi_window_exits;
5966         kvm_make_request(KVM_REQ_EVENT, vcpu);
5967
5968         return 1;
5969 }
5970
5971 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
5972 {
5973         struct vcpu_vmx *vmx = to_vmx(vcpu);
5974         enum emulation_result err = EMULATE_DONE;
5975         int ret = 1;
5976         u32 cpu_exec_ctrl;
5977         bool intr_window_requested;
5978         unsigned count = 130;
5979
5980         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5981         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
5982
5983         while (vmx->emulation_required && count-- != 0) {
5984                 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
5985                         return handle_interrupt_window(&vmx->vcpu);
5986
5987                 if (test_bit(KVM_REQ_EVENT, &vcpu->requests))
5988                         return 1;
5989
5990                 err = emulate_instruction(vcpu, EMULTYPE_NO_REEXECUTE);
5991
5992                 if (err == EMULATE_USER_EXIT) {
5993                         ++vcpu->stat.mmio_exits;
5994                         ret = 0;
5995                         goto out;
5996                 }
5997
5998                 if (err != EMULATE_DONE) {
5999                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
6000                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
6001                         vcpu->run->internal.ndata = 0;
6002                         return 0;
6003                 }
6004
6005                 if (vcpu->arch.halt_request) {
6006                         vcpu->arch.halt_request = 0;
6007                         ret = kvm_vcpu_halt(vcpu);
6008                         goto out;
6009                 }
6010
6011                 if (signal_pending(current))
6012                         goto out;
6013                 if (need_resched())
6014                         schedule();
6015         }
6016
6017 out:
6018         return ret;
6019 }
6020
6021 static int __grow_ple_window(int val)
6022 {
6023         if (ple_window_grow < 1)
6024                 return ple_window;
6025
6026         val = min(val, ple_window_actual_max);
6027
6028         if (ple_window_grow < ple_window)
6029                 val *= ple_window_grow;
6030         else
6031                 val += ple_window_grow;
6032
6033         return val;
6034 }
6035
6036 static int __shrink_ple_window(int val, int modifier, int minimum)
6037 {
6038         if (modifier < 1)
6039                 return ple_window;
6040
6041         if (modifier < ple_window)
6042                 val /= modifier;
6043         else
6044                 val -= modifier;
6045
6046         return max(val, minimum);
6047 }
6048
6049 static void grow_ple_window(struct kvm_vcpu *vcpu)
6050 {
6051         struct vcpu_vmx *vmx = to_vmx(vcpu);
6052         int old = vmx->ple_window;
6053
6054         vmx->ple_window = __grow_ple_window(old);
6055
6056         if (vmx->ple_window != old)
6057                 vmx->ple_window_dirty = true;
6058
6059         trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
6060 }
6061
6062 static void shrink_ple_window(struct kvm_vcpu *vcpu)
6063 {
6064         struct vcpu_vmx *vmx = to_vmx(vcpu);
6065         int old = vmx->ple_window;
6066
6067         vmx->ple_window = __shrink_ple_window(old,
6068                                               ple_window_shrink, ple_window);
6069
6070         if (vmx->ple_window != old)
6071                 vmx->ple_window_dirty = true;
6072
6073         trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
6074 }
6075
6076 /*
6077  * ple_window_actual_max is computed to be one grow_ple_window() below
6078  * ple_window_max. (See __grow_ple_window for the reason.)
6079  * This prevents overflows, because ple_window_max is int.
6080  * ple_window_max effectively rounded down to a multiple of ple_window_grow in
6081  * this process.
6082  * ple_window_max is also prevented from setting vmx->ple_window < ple_window.
6083  */
6084 static void update_ple_window_actual_max(void)
6085 {
6086         ple_window_actual_max =
6087                         __shrink_ple_window(max(ple_window_max, ple_window),
6088                                             ple_window_grow, INT_MIN);
6089 }
6090
6091 /*
6092  * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
6093  */
6094 static void wakeup_handler(void)
6095 {
6096         struct kvm_vcpu *vcpu;
6097         int cpu = smp_processor_id();
6098
6099         spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6100         list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
6101                         blocked_vcpu_list) {
6102                 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6103
6104                 if (pi_test_on(pi_desc) == 1)
6105                         kvm_vcpu_kick(vcpu);
6106         }
6107         spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
6108 }
6109
6110 static __init int hardware_setup(void)
6111 {
6112         int r = -ENOMEM, i, msr;
6113
6114         rdmsrl_safe(MSR_EFER, &host_efer);
6115
6116         for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
6117                 kvm_define_shared_msr(i, vmx_msr_index[i]);
6118
6119         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
6120         if (!vmx_io_bitmap_a)
6121                 return r;
6122
6123         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
6124         if (!vmx_io_bitmap_b)
6125                 goto out;
6126
6127         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
6128         if (!vmx_msr_bitmap_legacy)
6129                 goto out1;
6130
6131         vmx_msr_bitmap_legacy_x2apic =
6132                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6133         if (!vmx_msr_bitmap_legacy_x2apic)
6134                 goto out2;
6135
6136         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
6137         if (!vmx_msr_bitmap_longmode)
6138                 goto out3;
6139
6140         vmx_msr_bitmap_longmode_x2apic =
6141                                 (unsigned long *)__get_free_page(GFP_KERNEL);
6142         if (!vmx_msr_bitmap_longmode_x2apic)
6143                 goto out4;
6144
6145         if (nested) {
6146                 vmx_msr_bitmap_nested =
6147                         (unsigned long *)__get_free_page(GFP_KERNEL);
6148                 if (!vmx_msr_bitmap_nested)
6149                         goto out5;
6150         }
6151
6152         vmx_vmread_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6153         if (!vmx_vmread_bitmap)
6154                 goto out6;
6155
6156         vmx_vmwrite_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
6157         if (!vmx_vmwrite_bitmap)
6158                 goto out7;
6159
6160         memset(vmx_vmread_bitmap, 0xff, PAGE_SIZE);
6161         memset(vmx_vmwrite_bitmap, 0xff, PAGE_SIZE);
6162
6163         /*
6164          * Allow direct access to the PC debug port (it is often used for I/O
6165          * delays, but the vmexits simply slow things down).
6166          */
6167         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
6168         clear_bit(0x80, vmx_io_bitmap_a);
6169
6170         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
6171
6172         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
6173         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
6174         if (nested)
6175                 memset(vmx_msr_bitmap_nested, 0xff, PAGE_SIZE);
6176
6177         if (setup_vmcs_config(&vmcs_config) < 0) {
6178                 r = -EIO;
6179                 goto out8;
6180         }
6181
6182         if (boot_cpu_has(X86_FEATURE_NX))
6183                 kvm_enable_efer_bits(EFER_NX);
6184
6185         if (!cpu_has_vmx_vpid())
6186                 enable_vpid = 0;
6187         if (!cpu_has_vmx_shadow_vmcs())
6188                 enable_shadow_vmcs = 0;
6189         if (enable_shadow_vmcs)
6190                 init_vmcs_shadow_fields();
6191
6192         if (!cpu_has_vmx_ept() ||
6193             !cpu_has_vmx_ept_4levels()) {
6194                 enable_ept = 0;
6195                 enable_unrestricted_guest = 0;
6196                 enable_ept_ad_bits = 0;
6197         }
6198
6199         if (!cpu_has_vmx_ept_ad_bits())
6200                 enable_ept_ad_bits = 0;
6201
6202         if (!cpu_has_vmx_unrestricted_guest())
6203                 enable_unrestricted_guest = 0;
6204
6205         if (!cpu_has_vmx_flexpriority())
6206                 flexpriority_enabled = 0;
6207
6208         /*
6209          * set_apic_access_page_addr() is used to reload apic access
6210          * page upon invalidation.  No need to do anything if not
6211          * using the APIC_ACCESS_ADDR VMCS field.
6212          */
6213         if (!flexpriority_enabled)
6214                 kvm_x86_ops->set_apic_access_page_addr = NULL;
6215
6216         if (!cpu_has_vmx_tpr_shadow())
6217                 kvm_x86_ops->update_cr8_intercept = NULL;
6218
6219         if (enable_ept && !cpu_has_vmx_ept_2m_page())
6220                 kvm_disable_largepages();
6221
6222         if (!cpu_has_vmx_ple())
6223                 ple_gap = 0;
6224
6225         if (!cpu_has_vmx_apicv())
6226                 enable_apicv = 0;
6227
6228         if (cpu_has_vmx_tsc_scaling()) {
6229                 kvm_has_tsc_control = true;
6230                 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
6231                 kvm_tsc_scaling_ratio_frac_bits = 48;
6232         }
6233
6234         if (enable_apicv)
6235                 kvm_x86_ops->update_cr8_intercept = NULL;
6236         else {
6237                 kvm_x86_ops->hwapic_irr_update = NULL;
6238                 kvm_x86_ops->hwapic_isr_update = NULL;
6239                 kvm_x86_ops->deliver_posted_interrupt = NULL;
6240                 kvm_x86_ops->sync_pir_to_irr = vmx_sync_pir_to_irr_dummy;
6241         }
6242
6243         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
6244         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
6245         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
6246         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
6247         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
6248         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
6249         vmx_disable_intercept_for_msr(MSR_IA32_BNDCFGS, true);
6250
6251         memcpy(vmx_msr_bitmap_legacy_x2apic,
6252                         vmx_msr_bitmap_legacy, PAGE_SIZE);
6253         memcpy(vmx_msr_bitmap_longmode_x2apic,
6254                         vmx_msr_bitmap_longmode, PAGE_SIZE);
6255
6256         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
6257
6258         if (enable_apicv) {
6259                 for (msr = 0x800; msr <= 0x8ff; msr++)
6260                         vmx_disable_intercept_msr_read_x2apic(msr);
6261
6262                 /* According SDM, in x2apic mode, the whole id reg is used.
6263                  * But in KVM, it only use the highest eight bits. Need to
6264                  * intercept it */
6265                 vmx_enable_intercept_msr_read_x2apic(0x802);
6266                 /* TMCCT */
6267                 vmx_enable_intercept_msr_read_x2apic(0x839);
6268                 /* TPR */
6269                 vmx_disable_intercept_msr_write_x2apic(0x808);
6270                 /* EOI */
6271                 vmx_disable_intercept_msr_write_x2apic(0x80b);
6272                 /* SELF-IPI */
6273                 vmx_disable_intercept_msr_write_x2apic(0x83f);
6274         }
6275
6276         if (enable_ept) {
6277                 kvm_mmu_set_mask_ptes(0ull,
6278                         (enable_ept_ad_bits) ? VMX_EPT_ACCESS_BIT : 0ull,
6279                         (enable_ept_ad_bits) ? VMX_EPT_DIRTY_BIT : 0ull,
6280                         0ull, VMX_EPT_EXECUTABLE_MASK);
6281                 ept_set_mmio_spte_mask();
6282                 kvm_enable_tdp();
6283         } else
6284                 kvm_disable_tdp();
6285
6286         update_ple_window_actual_max();
6287
6288         /*
6289          * Only enable PML when hardware supports PML feature, and both EPT
6290          * and EPT A/D bit features are enabled -- PML depends on them to work.
6291          */
6292         if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
6293                 enable_pml = 0;
6294
6295         if (!enable_pml) {
6296                 kvm_x86_ops->slot_enable_log_dirty = NULL;
6297                 kvm_x86_ops->slot_disable_log_dirty = NULL;
6298                 kvm_x86_ops->flush_log_dirty = NULL;
6299                 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
6300         }
6301
6302         kvm_set_posted_intr_wakeup_handler(wakeup_handler);
6303
6304         return alloc_kvm_area();
6305
6306 out8:
6307         free_page((unsigned long)vmx_vmwrite_bitmap);
6308 out7:
6309         free_page((unsigned long)vmx_vmread_bitmap);
6310 out6:
6311         if (nested)
6312                 free_page((unsigned long)vmx_msr_bitmap_nested);
6313 out5:
6314         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6315 out4:
6316         free_page((unsigned long)vmx_msr_bitmap_longmode);
6317 out3:
6318         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6319 out2:
6320         free_page((unsigned long)vmx_msr_bitmap_legacy);
6321 out1:
6322         free_page((unsigned long)vmx_io_bitmap_b);
6323 out:
6324         free_page((unsigned long)vmx_io_bitmap_a);
6325
6326     return r;
6327 }
6328
6329 static __exit void hardware_unsetup(void)
6330 {
6331         free_page((unsigned long)vmx_msr_bitmap_legacy_x2apic);
6332         free_page((unsigned long)vmx_msr_bitmap_longmode_x2apic);
6333         free_page((unsigned long)vmx_msr_bitmap_legacy);
6334         free_page((unsigned long)vmx_msr_bitmap_longmode);
6335         free_page((unsigned long)vmx_io_bitmap_b);
6336         free_page((unsigned long)vmx_io_bitmap_a);
6337         free_page((unsigned long)vmx_vmwrite_bitmap);
6338         free_page((unsigned long)vmx_vmread_bitmap);
6339         if (nested)
6340                 free_page((unsigned long)vmx_msr_bitmap_nested);
6341
6342         free_kvm_area();
6343 }
6344
6345 /*
6346  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
6347  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
6348  */
6349 static int handle_pause(struct kvm_vcpu *vcpu)
6350 {
6351         if (ple_gap)
6352                 grow_ple_window(vcpu);
6353
6354         skip_emulated_instruction(vcpu);
6355         kvm_vcpu_on_spin(vcpu);
6356
6357         return 1;
6358 }
6359
6360 static int handle_nop(struct kvm_vcpu *vcpu)
6361 {
6362         skip_emulated_instruction(vcpu);
6363         return 1;
6364 }
6365
6366 static int handle_mwait(struct kvm_vcpu *vcpu)
6367 {
6368         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
6369         return handle_nop(vcpu);
6370 }
6371
6372 static int handle_monitor_trap(struct kvm_vcpu *vcpu)
6373 {
6374         return 1;
6375 }
6376
6377 static int handle_monitor(struct kvm_vcpu *vcpu)
6378 {
6379         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
6380         return handle_nop(vcpu);
6381 }
6382
6383 /*
6384  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
6385  * We could reuse a single VMCS for all the L2 guests, but we also want the
6386  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
6387  * allows keeping them loaded on the processor, and in the future will allow
6388  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
6389  * every entry if they never change.
6390  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
6391  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
6392  *
6393  * The following functions allocate and free a vmcs02 in this pool.
6394  */
6395
6396 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
6397 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
6398 {
6399         struct vmcs02_list *item;
6400         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6401                 if (item->vmptr == vmx->nested.current_vmptr) {
6402                         list_move(&item->list, &vmx->nested.vmcs02_pool);
6403                         return &item->vmcs02;
6404                 }
6405
6406         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
6407                 /* Recycle the least recently used VMCS. */
6408                 item = list_entry(vmx->nested.vmcs02_pool.prev,
6409                         struct vmcs02_list, list);
6410                 item->vmptr = vmx->nested.current_vmptr;
6411                 list_move(&item->list, &vmx->nested.vmcs02_pool);
6412                 return &item->vmcs02;
6413         }
6414
6415         /* Create a new VMCS */
6416         item = kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
6417         if (!item)
6418                 return NULL;
6419         item->vmcs02.vmcs = alloc_vmcs();
6420         if (!item->vmcs02.vmcs) {
6421                 kfree(item);
6422                 return NULL;
6423         }
6424         loaded_vmcs_init(&item->vmcs02);
6425         item->vmptr = vmx->nested.current_vmptr;
6426         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
6427         vmx->nested.vmcs02_num++;
6428         return &item->vmcs02;
6429 }
6430
6431 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
6432 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
6433 {
6434         struct vmcs02_list *item;
6435         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
6436                 if (item->vmptr == vmptr) {
6437                         free_loaded_vmcs(&item->vmcs02);
6438                         list_del(&item->list);
6439                         kfree(item);
6440                         vmx->nested.vmcs02_num--;
6441                         return;
6442                 }
6443 }
6444
6445 /*
6446  * Free all VMCSs saved for this vcpu, except the one pointed by
6447  * vmx->loaded_vmcs. We must be running L1, so vmx->loaded_vmcs
6448  * must be &vmx->vmcs01.
6449  */
6450 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
6451 {
6452         struct vmcs02_list *item, *n;
6453
6454         WARN_ON(vmx->loaded_vmcs != &vmx->vmcs01);
6455         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
6456                 /*
6457                  * Something will leak if the above WARN triggers.  Better than
6458                  * a use-after-free.
6459                  */
6460                 if (vmx->loaded_vmcs == &item->vmcs02)
6461                         continue;
6462
6463                 free_loaded_vmcs(&item->vmcs02);
6464                 list_del(&item->list);
6465                 kfree(item);
6466                 vmx->nested.vmcs02_num--;
6467         }
6468 }
6469
6470 /*
6471  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
6472  * set the success or error code of an emulated VMX instruction, as specified
6473  * by Vol 2B, VMX Instruction Reference, "Conventions".
6474  */
6475 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
6476 {
6477         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
6478                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6479                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
6480 }
6481
6482 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
6483 {
6484         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6485                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
6486                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6487                         | X86_EFLAGS_CF);
6488 }
6489
6490 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
6491                                         u32 vm_instruction_error)
6492 {
6493         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
6494                 /*
6495                  * failValid writes the error number to the current VMCS, which
6496                  * can't be done there isn't a current VMCS.
6497                  */
6498                 nested_vmx_failInvalid(vcpu);
6499                 return;
6500         }
6501         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
6502                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
6503                             X86_EFLAGS_SF | X86_EFLAGS_OF))
6504                         | X86_EFLAGS_ZF);
6505         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
6506         /*
6507          * We don't need to force a shadow sync because
6508          * VM_INSTRUCTION_ERROR is not shadowed
6509          */
6510 }
6511
6512 static void nested_vmx_abort(struct kvm_vcpu *vcpu, u32 indicator)
6513 {
6514         /* TODO: not to reset guest simply here. */
6515         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6516         pr_warn("kvm: nested vmx abort, indicator %d\n", indicator);
6517 }
6518
6519 static enum hrtimer_restart vmx_preemption_timer_fn(struct hrtimer *timer)
6520 {
6521         struct vcpu_vmx *vmx =
6522                 container_of(timer, struct vcpu_vmx, nested.preemption_timer);
6523
6524         vmx->nested.preemption_timer_expired = true;
6525         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6526         kvm_vcpu_kick(&vmx->vcpu);
6527
6528         return HRTIMER_NORESTART;
6529 }
6530
6531 /*
6532  * Decode the memory-address operand of a vmx instruction, as recorded on an
6533  * exit caused by such an instruction (run by a guest hypervisor).
6534  * On success, returns 0. When the operand is invalid, returns 1 and throws
6535  * #UD or #GP.
6536  */
6537 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
6538                                  unsigned long exit_qualification,
6539                                  u32 vmx_instruction_info, bool wr, gva_t *ret)
6540 {
6541         gva_t off;
6542         bool exn;
6543         struct kvm_segment s;
6544
6545         /*
6546          * According to Vol. 3B, "Information for VM Exits Due to Instruction
6547          * Execution", on an exit, vmx_instruction_info holds most of the
6548          * addressing components of the operand. Only the displacement part
6549          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
6550          * For how an actual address is calculated from all these components,
6551          * refer to Vol. 1, "Operand Addressing".
6552          */
6553         int  scaling = vmx_instruction_info & 3;
6554         int  addr_size = (vmx_instruction_info >> 7) & 7;
6555         bool is_reg = vmx_instruction_info & (1u << 10);
6556         int  seg_reg = (vmx_instruction_info >> 15) & 7;
6557         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
6558         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
6559         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
6560         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
6561
6562         if (is_reg) {
6563                 kvm_queue_exception(vcpu, UD_VECTOR);
6564                 return 1;
6565         }
6566
6567         /* Addr = segment_base + offset */
6568         /* offset = base + [index * scale] + displacement */
6569         off = exit_qualification; /* holds the displacement */
6570         if (base_is_valid)
6571                 off += kvm_register_read(vcpu, base_reg);
6572         if (index_is_valid)
6573                 off += kvm_register_read(vcpu, index_reg)<<scaling;
6574         vmx_get_segment(vcpu, &s, seg_reg);
6575         *ret = s.base + off;
6576
6577         if (addr_size == 1) /* 32 bit */
6578                 *ret &= 0xffffffff;
6579
6580         /* Checks for #GP/#SS exceptions. */
6581         exn = false;
6582         if (is_protmode(vcpu)) {
6583                 /* Protected mode: apply checks for segment validity in the
6584                  * following order:
6585                  * - segment type check (#GP(0) may be thrown)
6586                  * - usability check (#GP(0)/#SS(0))
6587                  * - limit check (#GP(0)/#SS(0))
6588                  */
6589                 if (wr)
6590                         /* #GP(0) if the destination operand is located in a
6591                          * read-only data segment or any code segment.
6592                          */
6593                         exn = ((s.type & 0xa) == 0 || (s.type & 8));
6594                 else
6595                         /* #GP(0) if the source operand is located in an
6596                          * execute-only code segment
6597                          */
6598                         exn = ((s.type & 0xa) == 8);
6599         }
6600         if (exn) {
6601                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
6602                 return 1;
6603         }
6604         if (is_long_mode(vcpu)) {
6605                 /* Long mode: #GP(0)/#SS(0) if the memory address is in a
6606                  * non-canonical form. This is an only check for long mode.
6607                  */
6608                 exn = is_noncanonical_address(*ret);
6609         } else if (is_protmode(vcpu)) {
6610                 /* Protected mode: #GP(0)/#SS(0) if the segment is unusable.
6611                  */
6612                 exn = (s.unusable != 0);
6613                 /* Protected mode: #GP(0)/#SS(0) if the memory
6614                  * operand is outside the segment limit.
6615                  */
6616                 exn = exn || (off + sizeof(u64) > s.limit);
6617         }
6618         if (exn) {
6619                 kvm_queue_exception_e(vcpu,
6620                                       seg_reg == VCPU_SREG_SS ?
6621                                                 SS_VECTOR : GP_VECTOR,
6622                                       0);
6623                 return 1;
6624         }
6625
6626         return 0;
6627 }
6628
6629 /*
6630  * This function performs the various checks including
6631  * - if it's 4KB aligned
6632  * - No bits beyond the physical address width are set
6633  * - Returns 0 on success or else 1
6634  * (Intel SDM Section 30.3)
6635  */
6636 static int nested_vmx_check_vmptr(struct kvm_vcpu *vcpu, int exit_reason,
6637                                   gpa_t *vmpointer)
6638 {
6639         gva_t gva;
6640         gpa_t vmptr;
6641         struct x86_exception e;
6642         struct page *page;
6643         struct vcpu_vmx *vmx = to_vmx(vcpu);
6644         int maxphyaddr = cpuid_maxphyaddr(vcpu);
6645
6646         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
6647                         vmcs_read32(VMX_INSTRUCTION_INFO), false, &gva))
6648                 return 1;
6649
6650         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
6651                                 sizeof(vmptr), &e)) {
6652                 kvm_inject_page_fault(vcpu, &e);
6653                 return 1;
6654         }
6655
6656         switch (exit_reason) {
6657         case EXIT_REASON_VMON:
6658                 /*
6659                  * SDM 3: 24.11.5
6660                  * The first 4 bytes of VMXON region contain the supported
6661                  * VMCS revision identifier
6662                  *
6663                  * Note - IA32_VMX_BASIC[48] will never be 1
6664                  * for the nested case;
6665                  * which replaces physical address width with 32
6666                  *
6667                  */
6668                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6669                         nested_vmx_failInvalid(vcpu);
6670                         skip_emulated_instruction(vcpu);
6671                         return 1;
6672                 }
6673
6674                 page = nested_get_page(vcpu, vmptr);
6675                 if (page == NULL ||
6676                     *(u32 *)kmap(page) != VMCS12_REVISION) {
6677                         nested_vmx_failInvalid(vcpu);
6678                         kunmap(page);
6679                         skip_emulated_instruction(vcpu);
6680                         return 1;
6681                 }
6682                 kunmap(page);
6683                 vmx->nested.vmxon_ptr = vmptr;
6684                 break;
6685         case EXIT_REASON_VMCLEAR:
6686                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6687                         nested_vmx_failValid(vcpu,
6688                                              VMXERR_VMCLEAR_INVALID_ADDRESS);
6689                         skip_emulated_instruction(vcpu);
6690                         return 1;
6691                 }
6692
6693                 if (vmptr == vmx->nested.vmxon_ptr) {
6694                         nested_vmx_failValid(vcpu,
6695                                              VMXERR_VMCLEAR_VMXON_POINTER);
6696                         skip_emulated_instruction(vcpu);
6697                         return 1;
6698                 }
6699                 break;
6700         case EXIT_REASON_VMPTRLD:
6701                 if (!PAGE_ALIGNED(vmptr) || (vmptr >> maxphyaddr)) {
6702                         nested_vmx_failValid(vcpu,
6703                                              VMXERR_VMPTRLD_INVALID_ADDRESS);
6704                         skip_emulated_instruction(vcpu);
6705                         return 1;
6706                 }
6707
6708                 if (vmptr == vmx->nested.vmxon_ptr) {
6709                         nested_vmx_failValid(vcpu,
6710                                              VMXERR_VMCLEAR_VMXON_POINTER);
6711                         skip_emulated_instruction(vcpu);
6712                         return 1;
6713                 }
6714                 break;
6715         default:
6716                 return 1; /* shouldn't happen */
6717         }
6718
6719         if (vmpointer)
6720                 *vmpointer = vmptr;
6721         return 0;
6722 }
6723
6724 /*
6725  * Emulate the VMXON instruction.
6726  * Currently, we just remember that VMX is active, and do not save or even
6727  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
6728  * do not currently need to store anything in that guest-allocated memory
6729  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
6730  * argument is different from the VMXON pointer (which the spec says they do).
6731  */
6732 static int handle_vmon(struct kvm_vcpu *vcpu)
6733 {
6734         struct kvm_segment cs;
6735         struct vcpu_vmx *vmx = to_vmx(vcpu);
6736         struct vmcs *shadow_vmcs;
6737         const u64 VMXON_NEEDED_FEATURES = FEATURE_CONTROL_LOCKED
6738                 | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6739
6740         /* The Intel VMX Instruction Reference lists a bunch of bits that
6741          * are prerequisite to running VMXON, most notably cr4.VMXE must be
6742          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
6743          * Otherwise, we should fail with #UD. We test these now:
6744          */
6745         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
6746             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
6747             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
6748                 kvm_queue_exception(vcpu, UD_VECTOR);
6749                 return 1;
6750         }
6751
6752         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6753         if (is_long_mode(vcpu) && !cs.l) {
6754                 kvm_queue_exception(vcpu, UD_VECTOR);
6755                 return 1;
6756         }
6757
6758         if (vmx_get_cpl(vcpu)) {
6759                 kvm_inject_gp(vcpu, 0);
6760                 return 1;
6761         }
6762
6763         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMON, NULL))
6764                 return 1;
6765
6766         if (vmx->nested.vmxon) {
6767                 nested_vmx_failValid(vcpu, VMXERR_VMXON_IN_VMX_ROOT_OPERATION);
6768                 skip_emulated_instruction(vcpu);
6769                 return 1;
6770         }
6771
6772         if ((vmx->nested.msr_ia32_feature_control & VMXON_NEEDED_FEATURES)
6773                         != VMXON_NEEDED_FEATURES) {
6774                 kvm_inject_gp(vcpu, 0);
6775                 return 1;
6776         }
6777
6778         if (enable_shadow_vmcs) {
6779                 shadow_vmcs = alloc_vmcs();
6780                 if (!shadow_vmcs)
6781                         return -ENOMEM;
6782                 /* mark vmcs as shadow */
6783                 shadow_vmcs->revision_id |= (1u << 31);
6784                 /* init shadow vmcs */
6785                 vmcs_clear(shadow_vmcs);
6786                 vmx->nested.current_shadow_vmcs = shadow_vmcs;
6787         }
6788
6789         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
6790         vmx->nested.vmcs02_num = 0;
6791
6792         hrtimer_init(&vmx->nested.preemption_timer, CLOCK_MONOTONIC,
6793                      HRTIMER_MODE_REL);
6794         vmx->nested.preemption_timer.function = vmx_preemption_timer_fn;
6795
6796         vmx->nested.vmxon = true;
6797
6798         skip_emulated_instruction(vcpu);
6799         nested_vmx_succeed(vcpu);
6800         return 1;
6801 }
6802
6803 /*
6804  * Intel's VMX Instruction Reference specifies a common set of prerequisites
6805  * for running VMX instructions (except VMXON, whose prerequisites are
6806  * slightly different). It also specifies what exception to inject otherwise.
6807  */
6808 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
6809 {
6810         struct kvm_segment cs;
6811         struct vcpu_vmx *vmx = to_vmx(vcpu);
6812
6813         if (!vmx->nested.vmxon) {
6814                 kvm_queue_exception(vcpu, UD_VECTOR);
6815                 return 0;
6816         }
6817
6818         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
6819         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
6820             (is_long_mode(vcpu) && !cs.l)) {
6821                 kvm_queue_exception(vcpu, UD_VECTOR);
6822                 return 0;
6823         }
6824
6825         if (vmx_get_cpl(vcpu)) {
6826                 kvm_inject_gp(vcpu, 0);
6827                 return 0;
6828         }
6829
6830         return 1;
6831 }
6832
6833 static inline void nested_release_vmcs12(struct vcpu_vmx *vmx)
6834 {
6835         if (vmx->nested.current_vmptr == -1ull)
6836                 return;
6837
6838         /* current_vmptr and current_vmcs12 are always set/reset together */
6839         if (WARN_ON(vmx->nested.current_vmcs12 == NULL))
6840                 return;
6841
6842         if (enable_shadow_vmcs) {
6843                 /* copy to memory all shadowed fields in case
6844                    they were modified */
6845                 copy_shadow_to_vmcs12(vmx);
6846                 vmx->nested.sync_shadow_vmcs = false;
6847                 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
6848                                 SECONDARY_EXEC_SHADOW_VMCS);
6849                 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6850         }
6851         vmx->nested.posted_intr_nv = -1;
6852         kunmap(vmx->nested.current_vmcs12_page);
6853         nested_release_page(vmx->nested.current_vmcs12_page);
6854         vmx->nested.current_vmptr = -1ull;
6855         vmx->nested.current_vmcs12 = NULL;
6856 }
6857
6858 /*
6859  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
6860  * just stops using VMX.
6861  */
6862 static void free_nested(struct vcpu_vmx *vmx)
6863 {
6864         if (!vmx->nested.vmxon)
6865                 return;
6866
6867         vmx->nested.vmxon = false;
6868         free_vpid(vmx->nested.vpid02);
6869         nested_release_vmcs12(vmx);
6870         if (enable_shadow_vmcs)
6871                 free_vmcs(vmx->nested.current_shadow_vmcs);
6872         /* Unpin physical memory we referred to in current vmcs02 */
6873         if (vmx->nested.apic_access_page) {
6874                 nested_release_page(vmx->nested.apic_access_page);
6875                 vmx->nested.apic_access_page = NULL;
6876         }
6877         if (vmx->nested.virtual_apic_page) {
6878                 nested_release_page(vmx->nested.virtual_apic_page);
6879                 vmx->nested.virtual_apic_page = NULL;
6880         }
6881         if (vmx->nested.pi_desc_page) {
6882                 kunmap(vmx->nested.pi_desc_page);
6883                 nested_release_page(vmx->nested.pi_desc_page);
6884                 vmx->nested.pi_desc_page = NULL;
6885                 vmx->nested.pi_desc = NULL;
6886         }
6887
6888         nested_free_all_saved_vmcss(vmx);
6889 }
6890
6891 /* Emulate the VMXOFF instruction */
6892 static int handle_vmoff(struct kvm_vcpu *vcpu)
6893 {
6894         if (!nested_vmx_check_permission(vcpu))
6895                 return 1;
6896         free_nested(to_vmx(vcpu));
6897         skip_emulated_instruction(vcpu);
6898         nested_vmx_succeed(vcpu);
6899         return 1;
6900 }
6901
6902 /* Emulate the VMCLEAR instruction */
6903 static int handle_vmclear(struct kvm_vcpu *vcpu)
6904 {
6905         struct vcpu_vmx *vmx = to_vmx(vcpu);
6906         gpa_t vmptr;
6907         struct vmcs12 *vmcs12;
6908         struct page *page;
6909
6910         if (!nested_vmx_check_permission(vcpu))
6911                 return 1;
6912
6913         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMCLEAR, &vmptr))
6914                 return 1;
6915
6916         if (vmptr == vmx->nested.current_vmptr)
6917                 nested_release_vmcs12(vmx);
6918
6919         page = nested_get_page(vcpu, vmptr);
6920         if (page == NULL) {
6921                 /*
6922                  * For accurate processor emulation, VMCLEAR beyond available
6923                  * physical memory should do nothing at all. However, it is
6924                  * possible that a nested vmx bug, not a guest hypervisor bug,
6925                  * resulted in this case, so let's shut down before doing any
6926                  * more damage:
6927                  */
6928                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
6929                 return 1;
6930         }
6931         vmcs12 = kmap(page);
6932         vmcs12->launch_state = 0;
6933         kunmap(page);
6934         nested_release_page(page);
6935
6936         nested_free_vmcs02(vmx, vmptr);
6937
6938         skip_emulated_instruction(vcpu);
6939         nested_vmx_succeed(vcpu);
6940         return 1;
6941 }
6942
6943 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
6944
6945 /* Emulate the VMLAUNCH instruction */
6946 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
6947 {
6948         return nested_vmx_run(vcpu, true);
6949 }
6950
6951 /* Emulate the VMRESUME instruction */
6952 static int handle_vmresume(struct kvm_vcpu *vcpu)
6953 {
6954
6955         return nested_vmx_run(vcpu, false);
6956 }
6957
6958 enum vmcs_field_type {
6959         VMCS_FIELD_TYPE_U16 = 0,
6960         VMCS_FIELD_TYPE_U64 = 1,
6961         VMCS_FIELD_TYPE_U32 = 2,
6962         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
6963 };
6964
6965 static inline int vmcs_field_type(unsigned long field)
6966 {
6967         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
6968                 return VMCS_FIELD_TYPE_U32;
6969         return (field >> 13) & 0x3 ;
6970 }
6971
6972 static inline int vmcs_field_readonly(unsigned long field)
6973 {
6974         return (((field >> 10) & 0x3) == 1);
6975 }
6976
6977 /*
6978  * Read a vmcs12 field. Since these can have varying lengths and we return
6979  * one type, we chose the biggest type (u64) and zero-extend the return value
6980  * to that size. Note that the caller, handle_vmread, might need to use only
6981  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
6982  * 64-bit fields are to be returned).
6983  */
6984 static inline int vmcs12_read_any(struct kvm_vcpu *vcpu,
6985                                   unsigned long field, u64 *ret)
6986 {
6987         short offset = vmcs_field_to_offset(field);
6988         char *p;
6989
6990         if (offset < 0)
6991                 return offset;
6992
6993         p = ((char *)(get_vmcs12(vcpu))) + offset;
6994
6995         switch (vmcs_field_type(field)) {
6996         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
6997                 *ret = *((natural_width *)p);
6998                 return 0;
6999         case VMCS_FIELD_TYPE_U16:
7000                 *ret = *((u16 *)p);
7001                 return 0;
7002         case VMCS_FIELD_TYPE_U32:
7003                 *ret = *((u32 *)p);
7004                 return 0;
7005         case VMCS_FIELD_TYPE_U64:
7006                 *ret = *((u64 *)p);
7007                 return 0;
7008         default:
7009                 WARN_ON(1);
7010                 return -ENOENT;
7011         }
7012 }
7013
7014
7015 static inline int vmcs12_write_any(struct kvm_vcpu *vcpu,
7016                                    unsigned long field, u64 field_value){
7017         short offset = vmcs_field_to_offset(field);
7018         char *p = ((char *) get_vmcs12(vcpu)) + offset;
7019         if (offset < 0)
7020                 return offset;
7021
7022         switch (vmcs_field_type(field)) {
7023         case VMCS_FIELD_TYPE_U16:
7024                 *(u16 *)p = field_value;
7025                 return 0;
7026         case VMCS_FIELD_TYPE_U32:
7027                 *(u32 *)p = field_value;
7028                 return 0;
7029         case VMCS_FIELD_TYPE_U64:
7030                 *(u64 *)p = field_value;
7031                 return 0;
7032         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7033                 *(natural_width *)p = field_value;
7034                 return 0;
7035         default:
7036                 WARN_ON(1);
7037                 return -ENOENT;
7038         }
7039
7040 }
7041
7042 static void copy_shadow_to_vmcs12(struct vcpu_vmx *vmx)
7043 {
7044         int i;
7045         unsigned long field;
7046         u64 field_value;
7047         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7048         const unsigned long *fields = shadow_read_write_fields;
7049         const int num_fields = max_shadow_read_write_fields;
7050
7051         preempt_disable();
7052
7053         vmcs_load(shadow_vmcs);
7054
7055         for (i = 0; i < num_fields; i++) {
7056                 field = fields[i];
7057                 switch (vmcs_field_type(field)) {
7058                 case VMCS_FIELD_TYPE_U16:
7059                         field_value = vmcs_read16(field);
7060                         break;
7061                 case VMCS_FIELD_TYPE_U32:
7062                         field_value = vmcs_read32(field);
7063                         break;
7064                 case VMCS_FIELD_TYPE_U64:
7065                         field_value = vmcs_read64(field);
7066                         break;
7067                 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7068                         field_value = vmcs_readl(field);
7069                         break;
7070                 default:
7071                         WARN_ON(1);
7072                         continue;
7073                 }
7074                 vmcs12_write_any(&vmx->vcpu, field, field_value);
7075         }
7076
7077         vmcs_clear(shadow_vmcs);
7078         vmcs_load(vmx->loaded_vmcs->vmcs);
7079
7080         preempt_enable();
7081 }
7082
7083 static void copy_vmcs12_to_shadow(struct vcpu_vmx *vmx)
7084 {
7085         const unsigned long *fields[] = {
7086                 shadow_read_write_fields,
7087                 shadow_read_only_fields
7088         };
7089         const int max_fields[] = {
7090                 max_shadow_read_write_fields,
7091                 max_shadow_read_only_fields
7092         };
7093         int i, q;
7094         unsigned long field;
7095         u64 field_value = 0;
7096         struct vmcs *shadow_vmcs = vmx->nested.current_shadow_vmcs;
7097
7098         vmcs_load(shadow_vmcs);
7099
7100         for (q = 0; q < ARRAY_SIZE(fields); q++) {
7101                 for (i = 0; i < max_fields[q]; i++) {
7102                         field = fields[q][i];
7103                         vmcs12_read_any(&vmx->vcpu, field, &field_value);
7104
7105                         switch (vmcs_field_type(field)) {
7106                         case VMCS_FIELD_TYPE_U16:
7107                                 vmcs_write16(field, (u16)field_value);
7108                                 break;
7109                         case VMCS_FIELD_TYPE_U32:
7110                                 vmcs_write32(field, (u32)field_value);
7111                                 break;
7112                         case VMCS_FIELD_TYPE_U64:
7113                                 vmcs_write64(field, (u64)field_value);
7114                                 break;
7115                         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
7116                                 vmcs_writel(field, (long)field_value);
7117                                 break;
7118                         default:
7119                                 WARN_ON(1);
7120                                 break;
7121                         }
7122                 }
7123         }
7124
7125         vmcs_clear(shadow_vmcs);
7126         vmcs_load(vmx->loaded_vmcs->vmcs);
7127 }
7128
7129 /*
7130  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
7131  * used before) all generate the same failure when it is missing.
7132  */
7133 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
7134 {
7135         struct vcpu_vmx *vmx = to_vmx(vcpu);
7136         if (vmx->nested.current_vmptr == -1ull) {
7137                 nested_vmx_failInvalid(vcpu);
7138                 skip_emulated_instruction(vcpu);
7139                 return 0;
7140         }
7141         return 1;
7142 }
7143
7144 static int handle_vmread(struct kvm_vcpu *vcpu)
7145 {
7146         unsigned long field;
7147         u64 field_value;
7148         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7149         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7150         gva_t gva = 0;
7151
7152         if (!nested_vmx_check_permission(vcpu) ||
7153             !nested_vmx_check_vmcs12(vcpu))
7154                 return 1;
7155
7156         /* Decode instruction info and find the field to read */
7157         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7158         /* Read the field, zero-extended to a u64 field_value */
7159         if (vmcs12_read_any(vcpu, field, &field_value) < 0) {
7160                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7161                 skip_emulated_instruction(vcpu);
7162                 return 1;
7163         }
7164         /*
7165          * Now copy part of this value to register or memory, as requested.
7166          * Note that the number of bits actually copied is 32 or 64 depending
7167          * on the guest's mode (32 or 64 bit), not on the given field's length.
7168          */
7169         if (vmx_instruction_info & (1u << 10)) {
7170                 kvm_register_writel(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
7171                         field_value);
7172         } else {
7173                 if (get_vmx_mem_address(vcpu, exit_qualification,
7174                                 vmx_instruction_info, true, &gva))
7175                         return 1;
7176                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
7177                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
7178                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
7179         }
7180
7181         nested_vmx_succeed(vcpu);
7182         skip_emulated_instruction(vcpu);
7183         return 1;
7184 }
7185
7186
7187 static int handle_vmwrite(struct kvm_vcpu *vcpu)
7188 {
7189         unsigned long field;
7190         gva_t gva;
7191         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7192         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7193         /* The value to write might be 32 or 64 bits, depending on L1's long
7194          * mode, and eventually we need to write that into a field of several
7195          * possible lengths. The code below first zero-extends the value to 64
7196          * bit (field_value), and then copies only the approriate number of
7197          * bits into the vmcs12 field.
7198          */
7199         u64 field_value = 0;
7200         struct x86_exception e;
7201
7202         if (!nested_vmx_check_permission(vcpu) ||
7203             !nested_vmx_check_vmcs12(vcpu))
7204                 return 1;
7205
7206         if (vmx_instruction_info & (1u << 10))
7207                 field_value = kvm_register_readl(vcpu,
7208                         (((vmx_instruction_info) >> 3) & 0xf));
7209         else {
7210                 if (get_vmx_mem_address(vcpu, exit_qualification,
7211                                 vmx_instruction_info, false, &gva))
7212                         return 1;
7213                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
7214                            &field_value, (is_64_bit_mode(vcpu) ? 8 : 4), &e)) {
7215                         kvm_inject_page_fault(vcpu, &e);
7216                         return 1;
7217                 }
7218         }
7219
7220
7221         field = kvm_register_readl(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
7222         if (vmcs_field_readonly(field)) {
7223                 nested_vmx_failValid(vcpu,
7224                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
7225                 skip_emulated_instruction(vcpu);
7226                 return 1;
7227         }
7228
7229         if (vmcs12_write_any(vcpu, field, field_value) < 0) {
7230                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
7231                 skip_emulated_instruction(vcpu);
7232                 return 1;
7233         }
7234
7235         nested_vmx_succeed(vcpu);
7236         skip_emulated_instruction(vcpu);
7237         return 1;
7238 }
7239
7240 /* Emulate the VMPTRLD instruction */
7241 static int handle_vmptrld(struct kvm_vcpu *vcpu)
7242 {
7243         struct vcpu_vmx *vmx = to_vmx(vcpu);
7244         gpa_t vmptr;
7245
7246         if (!nested_vmx_check_permission(vcpu))
7247                 return 1;
7248
7249         if (nested_vmx_check_vmptr(vcpu, EXIT_REASON_VMPTRLD, &vmptr))
7250                 return 1;
7251
7252         if (vmx->nested.current_vmptr != vmptr) {
7253                 struct vmcs12 *new_vmcs12;
7254                 struct page *page;
7255                 page = nested_get_page(vcpu, vmptr);
7256                 if (page == NULL) {
7257                         nested_vmx_failInvalid(vcpu);
7258                         skip_emulated_instruction(vcpu);
7259                         return 1;
7260                 }
7261                 new_vmcs12 = kmap(page);
7262                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
7263                         kunmap(page);
7264                         nested_release_page_clean(page);
7265                         nested_vmx_failValid(vcpu,
7266                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
7267                         skip_emulated_instruction(vcpu);
7268                         return 1;
7269                 }
7270
7271                 nested_release_vmcs12(vmx);
7272                 vmx->nested.current_vmptr = vmptr;
7273                 vmx->nested.current_vmcs12 = new_vmcs12;
7274                 vmx->nested.current_vmcs12_page = page;
7275                 if (enable_shadow_vmcs) {
7276                         vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
7277                                       SECONDARY_EXEC_SHADOW_VMCS);
7278                         vmcs_write64(VMCS_LINK_POINTER,
7279                                      __pa(vmx->nested.current_shadow_vmcs));
7280                         vmx->nested.sync_shadow_vmcs = true;
7281                 }
7282         }
7283
7284         nested_vmx_succeed(vcpu);
7285         skip_emulated_instruction(vcpu);
7286         return 1;
7287 }
7288
7289 /* Emulate the VMPTRST instruction */
7290 static int handle_vmptrst(struct kvm_vcpu *vcpu)
7291 {
7292         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7293         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7294         gva_t vmcs_gva;
7295         struct x86_exception e;
7296
7297         if (!nested_vmx_check_permission(vcpu))
7298                 return 1;
7299
7300         if (get_vmx_mem_address(vcpu, exit_qualification,
7301                         vmx_instruction_info, true, &vmcs_gva))
7302                 return 1;
7303         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
7304         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
7305                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
7306                                  sizeof(u64), &e)) {
7307                 kvm_inject_page_fault(vcpu, &e);
7308                 return 1;
7309         }
7310         nested_vmx_succeed(vcpu);
7311         skip_emulated_instruction(vcpu);
7312         return 1;
7313 }
7314
7315 /* Emulate the INVEPT instruction */
7316 static int handle_invept(struct kvm_vcpu *vcpu)
7317 {
7318         struct vcpu_vmx *vmx = to_vmx(vcpu);
7319         u32 vmx_instruction_info, types;
7320         unsigned long type;
7321         gva_t gva;
7322         struct x86_exception e;
7323         struct {
7324                 u64 eptp, gpa;
7325         } operand;
7326
7327         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7328               SECONDARY_EXEC_ENABLE_EPT) ||
7329             !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
7330                 kvm_queue_exception(vcpu, UD_VECTOR);
7331                 return 1;
7332         }
7333
7334         if (!nested_vmx_check_permission(vcpu))
7335                 return 1;
7336
7337         if (!kvm_read_cr0_bits(vcpu, X86_CR0_PE)) {
7338                 kvm_queue_exception(vcpu, UD_VECTOR);
7339                 return 1;
7340         }
7341
7342         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7343         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7344
7345         types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
7346
7347         if (!(types & (1UL << type))) {
7348                 nested_vmx_failValid(vcpu,
7349                                 VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7350                 skip_emulated_instruction(vcpu);
7351                 return 1;
7352         }
7353
7354         /* According to the Intel VMX instruction reference, the memory
7355          * operand is read even if it isn't needed (e.g., for type==global)
7356          */
7357         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7358                         vmx_instruction_info, false, &gva))
7359                 return 1;
7360         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &operand,
7361                                 sizeof(operand), &e)) {
7362                 kvm_inject_page_fault(vcpu, &e);
7363                 return 1;
7364         }
7365
7366         switch (type) {
7367         case VMX_EPT_EXTENT_GLOBAL:
7368                 kvm_mmu_sync_roots(vcpu);
7369                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
7370                 nested_vmx_succeed(vcpu);
7371                 break;
7372         default:
7373                 /* Trap single context invalidation invept calls */
7374                 BUG_ON(1);
7375                 break;
7376         }
7377
7378         skip_emulated_instruction(vcpu);
7379         return 1;
7380 }
7381
7382 static int handle_invvpid(struct kvm_vcpu *vcpu)
7383 {
7384         struct vcpu_vmx *vmx = to_vmx(vcpu);
7385         u32 vmx_instruction_info;
7386         unsigned long type, types;
7387         gva_t gva;
7388         struct x86_exception e;
7389         int vpid;
7390
7391         if (!(vmx->nested.nested_vmx_secondary_ctls_high &
7392               SECONDARY_EXEC_ENABLE_VPID) ||
7393                         !(vmx->nested.nested_vmx_vpid_caps & VMX_VPID_INVVPID_BIT)) {
7394                 kvm_queue_exception(vcpu, UD_VECTOR);
7395                 return 1;
7396         }
7397
7398         if (!nested_vmx_check_permission(vcpu))
7399                 return 1;
7400
7401         vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
7402         type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
7403
7404         types = (vmx->nested.nested_vmx_vpid_caps >> 8) & 0x7;
7405
7406         if (!(types & (1UL << type))) {
7407                 nested_vmx_failValid(vcpu,
7408                         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID);
7409                 skip_emulated_instruction(vcpu);
7410                 return 1;
7411         }
7412
7413         /* according to the intel vmx instruction reference, the memory
7414          * operand is read even if it isn't needed (e.g., for type==global)
7415          */
7416         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
7417                         vmx_instruction_info, false, &gva))
7418                 return 1;
7419         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vpid,
7420                                 sizeof(u32), &e)) {
7421                 kvm_inject_page_fault(vcpu, &e);
7422                 return 1;
7423         }
7424
7425         switch (type) {
7426         case VMX_VPID_EXTENT_SINGLE_CONTEXT:
7427                 /*
7428                  * Old versions of KVM use the single-context version so we
7429                  * have to support it; just treat it the same as all-context.
7430                  */
7431         case VMX_VPID_EXTENT_ALL_CONTEXT:
7432                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
7433                 nested_vmx_succeed(vcpu);
7434                 break;
7435         default:
7436                 /* Trap individual address invalidation invvpid calls */
7437                 BUG_ON(1);
7438                 break;
7439         }
7440
7441         skip_emulated_instruction(vcpu);
7442         return 1;
7443 }
7444
7445 static int handle_pml_full(struct kvm_vcpu *vcpu)
7446 {
7447         unsigned long exit_qualification;
7448
7449         trace_kvm_pml_full(vcpu->vcpu_id);
7450
7451         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7452
7453         /*
7454          * PML buffer FULL happened while executing iret from NMI,
7455          * "blocked by NMI" bit has to be set before next VM entry.
7456          */
7457         if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
7458                         cpu_has_virtual_nmis() &&
7459                         (exit_qualification & INTR_INFO_UNBLOCK_NMI))
7460                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
7461                                 GUEST_INTR_STATE_NMI);
7462
7463         /*
7464          * PML buffer already flushed at beginning of VMEXIT. Nothing to do
7465          * here.., and there's no userspace involvement needed for PML.
7466          */
7467         return 1;
7468 }
7469
7470 static int handle_pcommit(struct kvm_vcpu *vcpu)
7471 {
7472         /* we never catch pcommit instruct for L1 guest. */
7473         WARN_ON(1);
7474         return 1;
7475 }
7476
7477 /*
7478  * The exit handlers return 1 if the exit was handled fully and guest execution
7479  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
7480  * to be done to userspace and return 0.
7481  */
7482 static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
7483         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
7484         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
7485         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
7486         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
7487         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
7488         [EXIT_REASON_CR_ACCESS]               = handle_cr,
7489         [EXIT_REASON_DR_ACCESS]               = handle_dr,
7490         [EXIT_REASON_CPUID]                   = handle_cpuid,
7491         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
7492         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
7493         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
7494         [EXIT_REASON_HLT]                     = handle_halt,
7495         [EXIT_REASON_INVD]                    = handle_invd,
7496         [EXIT_REASON_INVLPG]                  = handle_invlpg,
7497         [EXIT_REASON_RDPMC]                   = handle_rdpmc,
7498         [EXIT_REASON_VMCALL]                  = handle_vmcall,
7499         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
7500         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
7501         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
7502         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
7503         [EXIT_REASON_VMREAD]                  = handle_vmread,
7504         [EXIT_REASON_VMRESUME]                = handle_vmresume,
7505         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
7506         [EXIT_REASON_VMOFF]                   = handle_vmoff,
7507         [EXIT_REASON_VMON]                    = handle_vmon,
7508         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
7509         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
7510         [EXIT_REASON_APIC_WRITE]              = handle_apic_write,
7511         [EXIT_REASON_EOI_INDUCED]             = handle_apic_eoi_induced,
7512         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
7513         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
7514         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
7515         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
7516         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
7517         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
7518         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
7519         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_mwait,
7520         [EXIT_REASON_MONITOR_TRAP_FLAG]       = handle_monitor_trap,
7521         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_monitor,
7522         [EXIT_REASON_INVEPT]                  = handle_invept,
7523         [EXIT_REASON_INVVPID]                 = handle_invvpid,
7524         [EXIT_REASON_XSAVES]                  = handle_xsaves,
7525         [EXIT_REASON_XRSTORS]                 = handle_xrstors,
7526         [EXIT_REASON_PML_FULL]                = handle_pml_full,
7527         [EXIT_REASON_PCOMMIT]                 = handle_pcommit,
7528 };
7529
7530 static const int kvm_vmx_max_exit_handlers =
7531         ARRAY_SIZE(kvm_vmx_exit_handlers);
7532
7533 static bool nested_vmx_exit_handled_io(struct kvm_vcpu *vcpu,
7534                                        struct vmcs12 *vmcs12)
7535 {
7536         unsigned long exit_qualification;
7537         gpa_t bitmap, last_bitmap;
7538         unsigned int port;
7539         int size;
7540         u8 b;
7541
7542         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_IO_BITMAPS))
7543                 return nested_cpu_has(vmcs12, CPU_BASED_UNCOND_IO_EXITING);
7544
7545         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7546
7547         port = exit_qualification >> 16;
7548         size = (exit_qualification & 7) + 1;
7549
7550         last_bitmap = (gpa_t)-1;
7551         b = -1;
7552
7553         while (size > 0) {
7554                 if (port < 0x8000)
7555                         bitmap = vmcs12->io_bitmap_a;
7556                 else if (port < 0x10000)
7557                         bitmap = vmcs12->io_bitmap_b;
7558                 else
7559                         return true;
7560                 bitmap += (port & 0x7fff) / 8;
7561
7562                 if (last_bitmap != bitmap)
7563                         if (kvm_vcpu_read_guest(vcpu, bitmap, &b, 1))
7564                                 return true;
7565                 if (b & (1 << (port & 7)))
7566                         return true;
7567
7568                 port++;
7569                 size--;
7570                 last_bitmap = bitmap;
7571         }
7572
7573         return false;
7574 }
7575
7576 /*
7577  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
7578  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
7579  * disinterest in the current event (read or write a specific MSR) by using an
7580  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
7581  */
7582 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
7583         struct vmcs12 *vmcs12, u32 exit_reason)
7584 {
7585         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
7586         gpa_t bitmap;
7587
7588         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
7589                 return true;
7590
7591         /*
7592          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
7593          * for the four combinations of read/write and low/high MSR numbers.
7594          * First we need to figure out which of the four to use:
7595          */
7596         bitmap = vmcs12->msr_bitmap;
7597         if (exit_reason == EXIT_REASON_MSR_WRITE)
7598                 bitmap += 2048;
7599         if (msr_index >= 0xc0000000) {
7600                 msr_index -= 0xc0000000;
7601                 bitmap += 1024;
7602         }
7603
7604         /* Then read the msr_index'th bit from this bitmap: */
7605         if (msr_index < 1024*8) {
7606                 unsigned char b;
7607                 if (kvm_vcpu_read_guest(vcpu, bitmap + msr_index/8, &b, 1))
7608                         return true;
7609                 return 1 & (b >> (msr_index & 7));
7610         } else
7611                 return true; /* let L1 handle the wrong parameter */
7612 }
7613
7614 /*
7615  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
7616  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
7617  * intercept (via guest_host_mask etc.) the current event.
7618  */
7619 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
7620         struct vmcs12 *vmcs12)
7621 {
7622         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
7623         int cr = exit_qualification & 15;
7624         int reg = (exit_qualification >> 8) & 15;
7625         unsigned long val = kvm_register_readl(vcpu, reg);
7626
7627         switch ((exit_qualification >> 4) & 3) {
7628         case 0: /* mov to cr */
7629                 switch (cr) {
7630                 case 0:
7631                         if (vmcs12->cr0_guest_host_mask &
7632                             (val ^ vmcs12->cr0_read_shadow))
7633                                 return true;
7634                         break;
7635                 case 3:
7636                         if ((vmcs12->cr3_target_count >= 1 &&
7637                                         vmcs12->cr3_target_value0 == val) ||
7638                                 (vmcs12->cr3_target_count >= 2 &&
7639                                         vmcs12->cr3_target_value1 == val) ||
7640                                 (vmcs12->cr3_target_count >= 3 &&
7641                                         vmcs12->cr3_target_value2 == val) ||
7642                                 (vmcs12->cr3_target_count >= 4 &&
7643                                         vmcs12->cr3_target_value3 == val))
7644                                 return false;
7645                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
7646                                 return true;
7647                         break;
7648                 case 4:
7649                         if (vmcs12->cr4_guest_host_mask &
7650                             (vmcs12->cr4_read_shadow ^ val))
7651                                 return true;
7652                         break;
7653                 case 8:
7654                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
7655                                 return true;
7656                         break;
7657                 }
7658                 break;
7659         case 2: /* clts */
7660                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
7661                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
7662                         return true;
7663                 break;
7664         case 1: /* mov from cr */
7665                 switch (cr) {
7666                 case 3:
7667                         if (vmcs12->cpu_based_vm_exec_control &
7668                             CPU_BASED_CR3_STORE_EXITING)
7669                                 return true;
7670                         break;
7671                 case 8:
7672                         if (vmcs12->cpu_based_vm_exec_control &
7673                             CPU_BASED_CR8_STORE_EXITING)
7674                                 return true;
7675                         break;
7676                 }
7677                 break;
7678         case 3: /* lmsw */
7679                 /*
7680                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
7681                  * cr0. Other attempted changes are ignored, with no exit.
7682                  */
7683                 if (vmcs12->cr0_guest_host_mask & 0xe &
7684                     (val ^ vmcs12->cr0_read_shadow))
7685                         return true;
7686                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
7687                     !(vmcs12->cr0_read_shadow & 0x1) &&
7688                     (val & 0x1))
7689                         return true;
7690                 break;
7691         }
7692         return false;
7693 }
7694
7695 /*
7696  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
7697  * should handle it ourselves in L0 (and then continue L2). Only call this
7698  * when in is_guest_mode (L2).
7699  */
7700 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
7701 {
7702         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
7703         struct vcpu_vmx *vmx = to_vmx(vcpu);
7704         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7705         u32 exit_reason = vmx->exit_reason;
7706
7707         trace_kvm_nested_vmexit(kvm_rip_read(vcpu), exit_reason,
7708                                 vmcs_readl(EXIT_QUALIFICATION),
7709                                 vmx->idt_vectoring_info,
7710                                 intr_info,
7711                                 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
7712                                 KVM_ISA_VMX);
7713
7714         if (vmx->nested.nested_run_pending)
7715                 return false;
7716
7717         if (unlikely(vmx->fail)) {
7718                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
7719                                     vmcs_read32(VM_INSTRUCTION_ERROR));
7720                 return true;
7721         }
7722
7723         switch (exit_reason) {
7724         case EXIT_REASON_EXCEPTION_NMI:
7725                 if (!is_exception(intr_info))
7726                         return false;
7727                 else if (is_page_fault(intr_info))
7728                         return enable_ept;
7729                 else if (is_no_device(intr_info) &&
7730                          !(vmcs12->guest_cr0 & X86_CR0_TS))
7731                         return false;
7732                 return vmcs12->exception_bitmap &
7733                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
7734         case EXIT_REASON_EXTERNAL_INTERRUPT:
7735                 return false;
7736         case EXIT_REASON_TRIPLE_FAULT:
7737                 return true;
7738         case EXIT_REASON_PENDING_INTERRUPT:
7739                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_INTR_PENDING);
7740         case EXIT_REASON_NMI_WINDOW:
7741                 return nested_cpu_has(vmcs12, CPU_BASED_VIRTUAL_NMI_PENDING);
7742         case EXIT_REASON_TASK_SWITCH:
7743                 return true;
7744         case EXIT_REASON_CPUID:
7745                 if (kvm_register_read(vcpu, VCPU_REGS_RAX) == 0xa)
7746                         return false;
7747                 return true;
7748         case EXIT_REASON_HLT:
7749                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
7750         case EXIT_REASON_INVD:
7751                 return true;
7752         case EXIT_REASON_INVLPG:
7753                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
7754         case EXIT_REASON_RDPMC:
7755                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
7756         case EXIT_REASON_RDTSC: case EXIT_REASON_RDTSCP:
7757                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
7758         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
7759         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
7760         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
7761         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
7762         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
7763         case EXIT_REASON_INVEPT: case EXIT_REASON_INVVPID:
7764                 /*
7765                  * VMX instructions trap unconditionally. This allows L1 to
7766                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
7767                  */
7768                 return true;
7769         case EXIT_REASON_CR_ACCESS:
7770                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
7771         case EXIT_REASON_DR_ACCESS:
7772                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
7773         case EXIT_REASON_IO_INSTRUCTION:
7774                 return nested_vmx_exit_handled_io(vcpu, vmcs12);
7775         case EXIT_REASON_MSR_READ:
7776         case EXIT_REASON_MSR_WRITE:
7777                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
7778         case EXIT_REASON_INVALID_STATE:
7779                 return true;
7780         case EXIT_REASON_MWAIT_INSTRUCTION:
7781                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
7782         case EXIT_REASON_MONITOR_TRAP_FLAG:
7783                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_TRAP_FLAG);
7784         case EXIT_REASON_MONITOR_INSTRUCTION:
7785                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
7786         case EXIT_REASON_PAUSE_INSTRUCTION:
7787                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
7788                         nested_cpu_has2(vmcs12,
7789                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
7790         case EXIT_REASON_MCE_DURING_VMENTRY:
7791                 return false;
7792         case EXIT_REASON_TPR_BELOW_THRESHOLD:
7793                 return nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW);
7794         case EXIT_REASON_APIC_ACCESS:
7795                 return nested_cpu_has2(vmcs12,
7796                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
7797         case EXIT_REASON_APIC_WRITE:
7798         case EXIT_REASON_EOI_INDUCED:
7799                 /* apic_write and eoi_induced should exit unconditionally. */
7800                 return true;
7801         case EXIT_REASON_EPT_VIOLATION:
7802                 /*
7803                  * L0 always deals with the EPT violation. If nested EPT is
7804                  * used, and the nested mmu code discovers that the address is
7805                  * missing in the guest EPT table (EPT12), the EPT violation
7806                  * will be injected with nested_ept_inject_page_fault()
7807                  */
7808                 return false;
7809         case EXIT_REASON_EPT_MISCONFIG:
7810                 /*
7811                  * L2 never uses directly L1's EPT, but rather L0's own EPT
7812                  * table (shadow on EPT) or a merged EPT table that L0 built
7813                  * (EPT on EPT). So any problems with the structure of the
7814                  * table is L0's fault.
7815                  */
7816                 return false;
7817         case EXIT_REASON_WBINVD:
7818                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
7819         case EXIT_REASON_XSETBV:
7820                 return true;
7821         case EXIT_REASON_XSAVES: case EXIT_REASON_XRSTORS:
7822                 /*
7823                  * This should never happen, since it is not possible to
7824                  * set XSS to a non-zero value---neither in L1 nor in L2.
7825                  * If if it were, XSS would have to be checked against
7826                  * the XSS exit bitmap in vmcs12.
7827                  */
7828                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_XSAVES);
7829         case EXIT_REASON_PCOMMIT:
7830                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_PCOMMIT);
7831         default:
7832                 return true;
7833         }
7834 }
7835
7836 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
7837 {
7838         *info1 = vmcs_readl(EXIT_QUALIFICATION);
7839         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
7840 }
7841
7842 static int vmx_create_pml_buffer(struct vcpu_vmx *vmx)
7843 {
7844         struct page *pml_pg;
7845
7846         pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
7847         if (!pml_pg)
7848                 return -ENOMEM;
7849
7850         vmx->pml_pg = pml_pg;
7851
7852         vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
7853         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7854
7855         return 0;
7856 }
7857
7858 static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
7859 {
7860         if (vmx->pml_pg) {
7861                 __free_page(vmx->pml_pg);
7862                 vmx->pml_pg = NULL;
7863         }
7864 }
7865
7866 static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
7867 {
7868         struct vcpu_vmx *vmx = to_vmx(vcpu);
7869         u64 *pml_buf;
7870         u16 pml_idx;
7871
7872         pml_idx = vmcs_read16(GUEST_PML_INDEX);
7873
7874         /* Do nothing if PML buffer is empty */
7875         if (pml_idx == (PML_ENTITY_NUM - 1))
7876                 return;
7877
7878         /* PML index always points to next available PML buffer entity */
7879         if (pml_idx >= PML_ENTITY_NUM)
7880                 pml_idx = 0;
7881         else
7882                 pml_idx++;
7883
7884         pml_buf = page_address(vmx->pml_pg);
7885         for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
7886                 u64 gpa;
7887
7888                 gpa = pml_buf[pml_idx];
7889                 WARN_ON(gpa & (PAGE_SIZE - 1));
7890                 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
7891         }
7892
7893         /* reset PML index */
7894         vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
7895 }
7896
7897 /*
7898  * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
7899  * Called before reporting dirty_bitmap to userspace.
7900  */
7901 static void kvm_flush_pml_buffers(struct kvm *kvm)
7902 {
7903         int i;
7904         struct kvm_vcpu *vcpu;
7905         /*
7906          * We only need to kick vcpu out of guest mode here, as PML buffer
7907          * is flushed at beginning of all VMEXITs, and it's obvious that only
7908          * vcpus running in guest are possible to have unflushed GPAs in PML
7909          * buffer.
7910          */
7911         kvm_for_each_vcpu(i, vcpu, kvm)
7912                 kvm_vcpu_kick(vcpu);
7913 }
7914
7915 static void vmx_dump_sel(char *name, uint32_t sel)
7916 {
7917         pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
7918                name, vmcs_read32(sel),
7919                vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
7920                vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
7921                vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
7922 }
7923
7924 static void vmx_dump_dtsel(char *name, uint32_t limit)
7925 {
7926         pr_err("%s                           limit=0x%08x, base=0x%016lx\n",
7927                name, vmcs_read32(limit),
7928                vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
7929 }
7930
7931 static void dump_vmcs(void)
7932 {
7933         u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
7934         u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
7935         u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
7936         u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
7937         u32 secondary_exec_control = 0;
7938         unsigned long cr4 = vmcs_readl(GUEST_CR4);
7939         u64 efer = vmcs_readl(GUEST_IA32_EFER);
7940         int i, n;
7941
7942         if (cpu_has_secondary_exec_ctrls())
7943                 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
7944
7945         pr_err("*** Guest State ***\n");
7946         pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7947                vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
7948                vmcs_readl(CR0_GUEST_HOST_MASK));
7949         pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
7950                cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
7951         pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
7952         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
7953             (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
7954         {
7955                 pr_err("PDPTR0 = 0x%016lx  PDPTR1 = 0x%016lx\n",
7956                        vmcs_readl(GUEST_PDPTR0), vmcs_readl(GUEST_PDPTR1));
7957                 pr_err("PDPTR2 = 0x%016lx  PDPTR3 = 0x%016lx\n",
7958                        vmcs_readl(GUEST_PDPTR2), vmcs_readl(GUEST_PDPTR3));
7959         }
7960         pr_err("RSP = 0x%016lx  RIP = 0x%016lx\n",
7961                vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
7962         pr_err("RFLAGS=0x%08lx         DR7 = 0x%016lx\n",
7963                vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
7964         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
7965                vmcs_readl(GUEST_SYSENTER_ESP),
7966                vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
7967         vmx_dump_sel("CS:  ", GUEST_CS_SELECTOR);
7968         vmx_dump_sel("DS:  ", GUEST_DS_SELECTOR);
7969         vmx_dump_sel("SS:  ", GUEST_SS_SELECTOR);
7970         vmx_dump_sel("ES:  ", GUEST_ES_SELECTOR);
7971         vmx_dump_sel("FS:  ", GUEST_FS_SELECTOR);
7972         vmx_dump_sel("GS:  ", GUEST_GS_SELECTOR);
7973         vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
7974         vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
7975         vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
7976         vmx_dump_sel("TR:  ", GUEST_TR_SELECTOR);
7977         if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
7978             (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
7979                 pr_err("EFER =     0x%016llx  PAT = 0x%016lx\n",
7980                        efer, vmcs_readl(GUEST_IA32_PAT));
7981         pr_err("DebugCtl = 0x%016lx  DebugExceptions = 0x%016lx\n",
7982                vmcs_readl(GUEST_IA32_DEBUGCTL),
7983                vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
7984         if (vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
7985                 pr_err("PerfGlobCtl = 0x%016lx\n",
7986                        vmcs_readl(GUEST_IA32_PERF_GLOBAL_CTRL));
7987         if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
7988                 pr_err("BndCfgS = 0x%016lx\n", vmcs_readl(GUEST_BNDCFGS));
7989         pr_err("Interruptibility = %08x  ActivityState = %08x\n",
7990                vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
7991                vmcs_read32(GUEST_ACTIVITY_STATE));
7992         if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
7993                 pr_err("InterruptStatus = %04x\n",
7994                        vmcs_read16(GUEST_INTR_STATUS));
7995
7996         pr_err("*** Host State ***\n");
7997         pr_err("RIP = 0x%016lx  RSP = 0x%016lx\n",
7998                vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
7999         pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
8000                vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
8001                vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
8002                vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
8003                vmcs_read16(HOST_TR_SELECTOR));
8004         pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
8005                vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
8006                vmcs_readl(HOST_TR_BASE));
8007         pr_err("GDTBase=%016lx IDTBase=%016lx\n",
8008                vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
8009         pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
8010                vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
8011                vmcs_readl(HOST_CR4));
8012         pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
8013                vmcs_readl(HOST_IA32_SYSENTER_ESP),
8014                vmcs_read32(HOST_IA32_SYSENTER_CS),
8015                vmcs_readl(HOST_IA32_SYSENTER_EIP));
8016         if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
8017                 pr_err("EFER = 0x%016lx  PAT = 0x%016lx\n",
8018                        vmcs_readl(HOST_IA32_EFER), vmcs_readl(HOST_IA32_PAT));
8019         if (vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
8020                 pr_err("PerfGlobCtl = 0x%016lx\n",
8021                        vmcs_readl(HOST_IA32_PERF_GLOBAL_CTRL));
8022
8023         pr_err("*** Control State ***\n");
8024         pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
8025                pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
8026         pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
8027         pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
8028                vmcs_read32(EXCEPTION_BITMAP),
8029                vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
8030                vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
8031         pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
8032                vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8033                vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
8034                vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
8035         pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
8036                vmcs_read32(VM_EXIT_INTR_INFO),
8037                vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
8038                vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
8039         pr_err("        reason=%08x qualification=%016lx\n",
8040                vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
8041         pr_err("IDTVectoring: info=%08x errcode=%08x\n",
8042                vmcs_read32(IDT_VECTORING_INFO_FIELD),
8043                vmcs_read32(IDT_VECTORING_ERROR_CODE));
8044         pr_err("TSC Offset = 0x%016lx\n", vmcs_readl(TSC_OFFSET));
8045         if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
8046                 pr_err("TSC Multiplier = 0x%016lx\n",
8047                        vmcs_readl(TSC_MULTIPLIER));
8048         if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
8049                 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
8050         if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
8051                 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
8052         if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
8053                 pr_err("EPT pointer = 0x%016lx\n", vmcs_readl(EPT_POINTER));
8054         n = vmcs_read32(CR3_TARGET_COUNT);
8055         for (i = 0; i + 1 < n; i += 4)
8056                 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
8057                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
8058                        i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
8059         if (i < n)
8060                 pr_err("CR3 target%u=%016lx\n",
8061                        i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
8062         if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
8063                 pr_err("PLE Gap=%08x Window=%08x\n",
8064                        vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
8065         if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
8066                 pr_err("Virtual processor ID = 0x%04x\n",
8067                        vmcs_read16(VIRTUAL_PROCESSOR_ID));
8068 }
8069
8070 /*
8071  * The guest has exited.  See if we can fix it or if we need userspace
8072  * assistance.
8073  */
8074 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
8075 {
8076         struct vcpu_vmx *vmx = to_vmx(vcpu);
8077         u32 exit_reason = vmx->exit_reason;
8078         u32 vectoring_info = vmx->idt_vectoring_info;
8079
8080         trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
8081
8082         /*
8083          * Flush logged GPAs PML buffer, this will make dirty_bitmap more
8084          * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
8085          * querying dirty_bitmap, we only need to kick all vcpus out of guest
8086          * mode as if vcpus is in root mode, the PML buffer must has been
8087          * flushed already.
8088          */
8089         if (enable_pml)
8090                 vmx_flush_pml_buffer(vcpu);
8091
8092         /* If guest state is invalid, start emulating */
8093         if (vmx->emulation_required)
8094                 return handle_invalid_guest_state(vcpu);
8095
8096         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
8097                 nested_vmx_vmexit(vcpu, exit_reason,
8098                                   vmcs_read32(VM_EXIT_INTR_INFO),
8099                                   vmcs_readl(EXIT_QUALIFICATION));
8100                 return 1;
8101         }
8102
8103         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
8104                 dump_vmcs();
8105                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8106                 vcpu->run->fail_entry.hardware_entry_failure_reason
8107                         = exit_reason;
8108                 return 0;
8109         }
8110
8111         if (unlikely(vmx->fail)) {
8112                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
8113                 vcpu->run->fail_entry.hardware_entry_failure_reason
8114                         = vmcs_read32(VM_INSTRUCTION_ERROR);
8115                 return 0;
8116         }
8117
8118         /*
8119          * Note:
8120          * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
8121          * delivery event since it indicates guest is accessing MMIO.
8122          * The vm-exit can be triggered again after return to guest that
8123          * will cause infinite loop.
8124          */
8125         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
8126                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
8127                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
8128                         exit_reason != EXIT_REASON_TASK_SWITCH)) {
8129                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
8130                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
8131                 vcpu->run->internal.ndata = 2;
8132                 vcpu->run->internal.data[0] = vectoring_info;
8133                 vcpu->run->internal.data[1] = exit_reason;
8134                 return 0;
8135         }
8136
8137         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
8138             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
8139                                         get_vmcs12(vcpu))))) {
8140                 if (vmx_interrupt_allowed(vcpu)) {
8141                         vmx->soft_vnmi_blocked = 0;
8142                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
8143                            vcpu->arch.nmi_pending) {
8144                         /*
8145                          * This CPU don't support us in finding the end of an
8146                          * NMI-blocked window if the guest runs with IRQs
8147                          * disabled. So we pull the trigger after 1 s of
8148                          * futile waiting, but inform the user about this.
8149                          */
8150                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
8151                                "state on VCPU %d after 1 s timeout\n",
8152                                __func__, vcpu->vcpu_id);
8153                         vmx->soft_vnmi_blocked = 0;
8154                 }
8155         }
8156
8157         if (exit_reason < kvm_vmx_max_exit_handlers
8158             && kvm_vmx_exit_handlers[exit_reason])
8159                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
8160         else {
8161                 WARN_ONCE(1, "vmx: unexpected exit reason 0x%x\n", exit_reason);
8162                 kvm_queue_exception(vcpu, UD_VECTOR);
8163                 return 1;
8164         }
8165 }
8166
8167 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
8168 {
8169         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8170
8171         if (is_guest_mode(vcpu) &&
8172                 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
8173                 return;
8174
8175         if (irr == -1 || tpr < irr) {
8176                 vmcs_write32(TPR_THRESHOLD, 0);
8177                 return;
8178         }
8179
8180         vmcs_write32(TPR_THRESHOLD, irr);
8181 }
8182
8183 static void vmx_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
8184 {
8185         u32 sec_exec_control;
8186
8187         /*
8188          * There is not point to enable virtualize x2apic without enable
8189          * apicv
8190          */
8191         if (!cpu_has_vmx_virtualize_x2apic_mode() ||
8192                                 !vmx_cpu_uses_apicv(vcpu))
8193                 return;
8194
8195         if (!cpu_need_tpr_shadow(vcpu))
8196                 return;
8197
8198         sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8199
8200         if (set) {
8201                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8202                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8203         } else {
8204                 sec_exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
8205                 sec_exec_control |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8206         }
8207         vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
8208
8209         vmx_set_msr_bitmap(vcpu);
8210 }
8211
8212 static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
8213 {
8214         struct vcpu_vmx *vmx = to_vmx(vcpu);
8215
8216         /*
8217          * Currently we do not handle the nested case where L2 has an
8218          * APIC access page of its own; that page is still pinned.
8219          * Hence, we skip the case where the VCPU is in guest mode _and_
8220          * L1 prepared an APIC access page for L2.
8221          *
8222          * For the case where L1 and L2 share the same APIC access page
8223          * (flexpriority=Y but SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES clear
8224          * in the vmcs12), this function will only update either the vmcs01
8225          * or the vmcs02.  If the former, the vmcs02 will be updated by
8226          * prepare_vmcs02.  If the latter, the vmcs01 will be updated in
8227          * the next L2->L1 exit.
8228          */
8229         if (!is_guest_mode(vcpu) ||
8230             !nested_cpu_has2(vmx->nested.current_vmcs12,
8231                              SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
8232                 vmcs_write64(APIC_ACCESS_ADDR, hpa);
8233 }
8234
8235 static void vmx_hwapic_isr_update(struct kvm *kvm, int isr)
8236 {
8237         u16 status;
8238         u8 old;
8239
8240         if (isr == -1)
8241                 isr = 0;
8242
8243         status = vmcs_read16(GUEST_INTR_STATUS);
8244         old = status >> 8;
8245         if (isr != old) {
8246                 status &= 0xff;
8247                 status |= isr << 8;
8248                 vmcs_write16(GUEST_INTR_STATUS, status);
8249         }
8250 }
8251
8252 static void vmx_set_rvi(int vector)
8253 {
8254         u16 status;
8255         u8 old;
8256
8257         if (vector == -1)
8258                 vector = 0;
8259
8260         status = vmcs_read16(GUEST_INTR_STATUS);
8261         old = (u8)status & 0xff;
8262         if ((u8)vector != old) {
8263                 status &= ~0xff;
8264                 status |= (u8)vector;
8265                 vmcs_write16(GUEST_INTR_STATUS, status);
8266         }
8267 }
8268
8269 static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
8270 {
8271         if (!is_guest_mode(vcpu)) {
8272                 vmx_set_rvi(max_irr);
8273                 return;
8274         }
8275
8276         if (max_irr == -1)
8277                 return;
8278
8279         /*
8280          * In guest mode.  If a vmexit is needed, vmx_check_nested_events
8281          * handles it.
8282          */
8283         if (nested_exit_on_intr(vcpu))
8284                 return;
8285
8286         /*
8287          * Else, fall back to pre-APICv interrupt injection since L2
8288          * is run without virtual interrupt delivery.
8289          */
8290         if (!kvm_event_needs_reinjection(vcpu) &&
8291             vmx_interrupt_allowed(vcpu)) {
8292                 kvm_queue_interrupt(vcpu, max_irr, false);
8293                 vmx_inject_irq(vcpu);
8294         }
8295 }
8296
8297 static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu)
8298 {
8299         u64 *eoi_exit_bitmap = vcpu->arch.eoi_exit_bitmap;
8300         if (!vmx_cpu_uses_apicv(vcpu))
8301                 return;
8302
8303         vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
8304         vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
8305         vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
8306         vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8307 }
8308
8309 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
8310 {
8311         u32 exit_intr_info;
8312
8313         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
8314               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
8315                 return;
8316
8317         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8318         exit_intr_info = vmx->exit_intr_info;
8319
8320         /* Handle machine checks before interrupts are enabled */
8321         if (is_machine_check(exit_intr_info))
8322                 kvm_machine_check();
8323
8324         /* We need to handle NMIs before interrupts are enabled */
8325         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
8326             (exit_intr_info & INTR_INFO_VALID_MASK)) {
8327                 kvm_before_handle_nmi(&vmx->vcpu);
8328                 asm("int $2");
8329                 kvm_after_handle_nmi(&vmx->vcpu);
8330         }
8331 }
8332
8333 static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
8334 {
8335         u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8336
8337         /*
8338          * If external interrupt exists, IF bit is set in rflags/eflags on the
8339          * interrupt stack frame, and interrupt will be enabled on a return
8340          * from interrupt handler.
8341          */
8342         if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
8343                         == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
8344                 unsigned int vector;
8345                 unsigned long entry;
8346                 gate_desc *desc;
8347                 struct vcpu_vmx *vmx = to_vmx(vcpu);
8348 #ifdef CONFIG_X86_64
8349                 unsigned long tmp;
8350 #endif
8351
8352                 vector =  exit_intr_info & INTR_INFO_VECTOR_MASK;
8353                 desc = (gate_desc *)vmx->host_idt_base + vector;
8354                 entry = gate_offset(*desc);
8355                 asm volatile(
8356 #ifdef CONFIG_X86_64
8357                         "mov %%" _ASM_SP ", %[sp]\n\t"
8358                         "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
8359                         "push $%c[ss]\n\t"
8360                         "push %[sp]\n\t"
8361 #endif
8362                         "pushf\n\t"
8363                         "orl $0x200, (%%" _ASM_SP ")\n\t"
8364                         __ASM_SIZE(push) " $%c[cs]\n\t"
8365                         "call *%[entry]\n\t"
8366                         :
8367 #ifdef CONFIG_X86_64
8368                         [sp]"=&r"(tmp)
8369 #endif
8370                         :
8371                         [entry]"r"(entry),
8372                         [ss]"i"(__KERNEL_DS),
8373                         [cs]"i"(__KERNEL_CS)
8374                         );
8375         } else
8376                 local_irq_enable();
8377 }
8378
8379 static bool vmx_has_high_real_mode_segbase(void)
8380 {
8381         return enable_unrestricted_guest || emulate_invalid_guest_state;
8382 }
8383
8384 static bool vmx_mpx_supported(void)
8385 {
8386         return (vmcs_config.vmexit_ctrl & VM_EXIT_CLEAR_BNDCFGS) &&
8387                 (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_BNDCFGS);
8388 }
8389
8390 static bool vmx_xsaves_supported(void)
8391 {
8392         return vmcs_config.cpu_based_2nd_exec_ctrl &
8393                 SECONDARY_EXEC_XSAVES;
8394 }
8395
8396 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
8397 {
8398         u32 exit_intr_info;
8399         bool unblock_nmi;
8400         u8 vector;
8401         bool idtv_info_valid;
8402
8403         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8404
8405         if (cpu_has_virtual_nmis()) {
8406                 if (vmx->nmi_known_unmasked)
8407                         return;
8408                 /*
8409                  * Can't use vmx->exit_intr_info since we're not sure what
8410                  * the exit reason is.
8411                  */
8412                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
8413                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
8414                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
8415                 /*
8416                  * SDM 3: 27.7.1.2 (September 2008)
8417                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
8418                  * a guest IRET fault.
8419                  * SDM 3: 23.2.2 (September 2008)
8420                  * Bit 12 is undefined in any of the following cases:
8421                  *  If the VM exit sets the valid bit in the IDT-vectoring
8422                  *   information field.
8423                  *  If the VM exit is due to a double fault.
8424                  */
8425                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
8426                     vector != DF_VECTOR && !idtv_info_valid)
8427                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
8428                                       GUEST_INTR_STATE_NMI);
8429                 else
8430                         vmx->nmi_known_unmasked =
8431                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
8432                                   & GUEST_INTR_STATE_NMI);
8433         } else if (unlikely(vmx->soft_vnmi_blocked))
8434                 vmx->vnmi_blocked_time +=
8435                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
8436 }
8437
8438 static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
8439                                       u32 idt_vectoring_info,
8440                                       int instr_len_field,
8441                                       int error_code_field)
8442 {
8443         u8 vector;
8444         int type;
8445         bool idtv_info_valid;
8446
8447         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
8448
8449         vcpu->arch.nmi_injected = false;
8450         kvm_clear_exception_queue(vcpu);
8451         kvm_clear_interrupt_queue(vcpu);
8452
8453         if (!idtv_info_valid)
8454                 return;
8455
8456         kvm_make_request(KVM_REQ_EVENT, vcpu);
8457
8458         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
8459         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
8460
8461         switch (type) {
8462         case INTR_TYPE_NMI_INTR:
8463                 vcpu->arch.nmi_injected = true;
8464                 /*
8465                  * SDM 3: 27.7.1.2 (September 2008)
8466                  * Clear bit "block by NMI" before VM entry if a NMI
8467                  * delivery faulted.
8468                  */
8469                 vmx_set_nmi_mask(vcpu, false);
8470                 break;
8471         case INTR_TYPE_SOFT_EXCEPTION:
8472                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8473                 /* fall through */
8474         case INTR_TYPE_HARD_EXCEPTION:
8475                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
8476                         u32 err = vmcs_read32(error_code_field);
8477                         kvm_requeue_exception_e(vcpu, vector, err);
8478                 } else
8479                         kvm_requeue_exception(vcpu, vector);
8480                 break;
8481         case INTR_TYPE_SOFT_INTR:
8482                 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
8483                 /* fall through */
8484         case INTR_TYPE_EXT_INTR:
8485                 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
8486                 break;
8487         default:
8488                 break;
8489         }
8490 }
8491
8492 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
8493 {
8494         __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
8495                                   VM_EXIT_INSTRUCTION_LEN,
8496                                   IDT_VECTORING_ERROR_CODE);
8497 }
8498
8499 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
8500 {
8501         __vmx_complete_interrupts(vcpu,
8502                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
8503                                   VM_ENTRY_INSTRUCTION_LEN,
8504                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
8505
8506         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
8507 }
8508
8509 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
8510 {
8511         int i, nr_msrs;
8512         struct perf_guest_switch_msr *msrs;
8513
8514         msrs = perf_guest_get_msrs(&nr_msrs);
8515
8516         if (!msrs)
8517                 return;
8518
8519         for (i = 0; i < nr_msrs; i++)
8520                 if (msrs[i].host == msrs[i].guest)
8521                         clear_atomic_switch_msr(vmx, msrs[i].msr);
8522                 else
8523                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
8524                                         msrs[i].host);
8525 }
8526
8527 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
8528 {
8529         struct vcpu_vmx *vmx = to_vmx(vcpu);
8530         unsigned long debugctlmsr, cr4;
8531
8532         /* Record the guest's net vcpu time for enforced NMI injections. */
8533         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
8534                 vmx->entry_time = ktime_get();
8535
8536         /* Don't enter VMX if guest state is invalid, let the exit handler
8537            start emulation until we arrive back to a valid state */
8538         if (vmx->emulation_required)
8539                 return;
8540
8541         if (vmx->ple_window_dirty) {
8542                 vmx->ple_window_dirty = false;
8543                 vmcs_write32(PLE_WINDOW, vmx->ple_window);
8544         }
8545
8546         if (vmx->nested.sync_shadow_vmcs) {
8547                 copy_vmcs12_to_shadow(vmx);
8548                 vmx->nested.sync_shadow_vmcs = false;
8549         }
8550
8551         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
8552                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
8553         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
8554                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
8555
8556         cr4 = cr4_read_shadow();
8557         if (unlikely(cr4 != vmx->host_state.vmcs_host_cr4)) {
8558                 vmcs_writel(HOST_CR4, cr4);
8559                 vmx->host_state.vmcs_host_cr4 = cr4;
8560         }
8561
8562         /* When single-stepping over STI and MOV SS, we must clear the
8563          * corresponding interruptibility bits in the guest state. Otherwise
8564          * vmentry fails as it then expects bit 14 (BS) in pending debug
8565          * exceptions being set, but that's not correct for the guest debugging
8566          * case. */
8567         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
8568                 vmx_set_interrupt_shadow(vcpu, 0);
8569
8570         atomic_switch_perf_msrs(vmx);
8571         debugctlmsr = get_debugctlmsr();
8572
8573         vmx->__launched = vmx->loaded_vmcs->launched;
8574         asm(
8575                 /* Store host registers */
8576                 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
8577                 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
8578                 "push %%" _ASM_CX " \n\t"
8579                 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8580                 "je 1f \n\t"
8581                 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
8582                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
8583                 "1: \n\t"
8584                 /* Reload cr2 if changed */
8585                 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
8586                 "mov %%cr2, %%" _ASM_DX " \n\t"
8587                 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
8588                 "je 2f \n\t"
8589                 "mov %%" _ASM_AX", %%cr2 \n\t"
8590                 "2: \n\t"
8591                 /* Check if vmlaunch of vmresume is needed */
8592                 "cmpl $0, %c[launched](%0) \n\t"
8593                 /* Load guest registers.  Don't clobber flags. */
8594                 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
8595                 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
8596                 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
8597                 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
8598                 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
8599                 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
8600 #ifdef CONFIG_X86_64
8601                 "mov %c[r8](%0),  %%r8  \n\t"
8602                 "mov %c[r9](%0),  %%r9  \n\t"
8603                 "mov %c[r10](%0), %%r10 \n\t"
8604                 "mov %c[r11](%0), %%r11 \n\t"
8605                 "mov %c[r12](%0), %%r12 \n\t"
8606                 "mov %c[r13](%0), %%r13 \n\t"
8607                 "mov %c[r14](%0), %%r14 \n\t"
8608                 "mov %c[r15](%0), %%r15 \n\t"
8609 #endif
8610                 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
8611
8612                 /* Enter guest mode */
8613                 "jne 1f \n\t"
8614                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
8615                 "jmp 2f \n\t"
8616                 "1: " __ex(ASM_VMX_VMRESUME) "\n\t"
8617                 "2: "
8618                 /* Save guest registers, load host registers, keep flags */
8619                 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
8620                 "pop %0 \n\t"
8621                 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
8622                 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
8623                 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
8624                 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
8625                 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
8626                 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
8627                 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
8628 #ifdef CONFIG_X86_64
8629                 "mov %%r8,  %c[r8](%0) \n\t"
8630                 "mov %%r9,  %c[r9](%0) \n\t"
8631                 "mov %%r10, %c[r10](%0) \n\t"
8632                 "mov %%r11, %c[r11](%0) \n\t"
8633                 "mov %%r12, %c[r12](%0) \n\t"
8634                 "mov %%r13, %c[r13](%0) \n\t"
8635                 "mov %%r14, %c[r14](%0) \n\t"
8636                 "mov %%r15, %c[r15](%0) \n\t"
8637 #endif
8638                 "mov %%cr2, %%" _ASM_AX "   \n\t"
8639                 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
8640
8641                 "pop  %%" _ASM_BP "; pop  %%" _ASM_DX " \n\t"
8642                 "setbe %c[fail](%0) \n\t"
8643                 ".pushsection .rodata \n\t"
8644                 ".global vmx_return \n\t"
8645                 "vmx_return: " _ASM_PTR " 2b \n\t"
8646                 ".popsection"
8647               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
8648                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
8649                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
8650                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
8651                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
8652                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
8653                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
8654                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
8655                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
8656                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
8657                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
8658 #ifdef CONFIG_X86_64
8659                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
8660                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
8661                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
8662                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
8663                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
8664                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
8665                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
8666                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
8667 #endif
8668                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
8669                 [wordsize]"i"(sizeof(ulong))
8670               : "cc", "memory"
8671 #ifdef CONFIG_X86_64
8672                 , "rax", "rbx", "rdi", "rsi"
8673                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
8674 #else
8675                 , "eax", "ebx", "edi", "esi"
8676 #endif
8677               );
8678
8679         /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
8680         if (debugctlmsr)
8681                 update_debugctlmsr(debugctlmsr);
8682
8683 #ifndef CONFIG_X86_64
8684         /*
8685          * The sysexit path does not restore ds/es, so we must set them to
8686          * a reasonable value ourselves.
8687          *
8688          * We can't defer this to vmx_load_host_state() since that function
8689          * may be executed in interrupt context, which saves and restore segments
8690          * around it, nullifying its effect.
8691          */
8692         loadsegment(ds, __USER_DS);
8693         loadsegment(es, __USER_DS);
8694 #endif
8695
8696         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
8697                                   | (1 << VCPU_EXREG_RFLAGS)
8698                                   | (1 << VCPU_EXREG_PDPTR)
8699                                   | (1 << VCPU_EXREG_SEGMENTS)
8700                                   | (1 << VCPU_EXREG_CR3));
8701         vcpu->arch.regs_dirty = 0;
8702
8703         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
8704
8705         vmx->loaded_vmcs->launched = 1;
8706
8707         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
8708
8709         /*
8710          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
8711          * we did not inject a still-pending event to L1 now because of
8712          * nested_run_pending, we need to re-enable this bit.
8713          */
8714         if (vmx->nested.nested_run_pending)
8715                 kvm_make_request(KVM_REQ_EVENT, vcpu);
8716
8717         vmx->nested.nested_run_pending = 0;
8718
8719         vmx_complete_atomic_exit(vmx);
8720         vmx_recover_nmi_blocking(vmx);
8721         vmx_complete_interrupts(vmx);
8722 }
8723
8724 static void vmx_load_vmcs01(struct kvm_vcpu *vcpu)
8725 {
8726         struct vcpu_vmx *vmx = to_vmx(vcpu);
8727         int cpu;
8728
8729         if (vmx->loaded_vmcs == &vmx->vmcs01)
8730                 return;
8731
8732         cpu = get_cpu();
8733         vmx->loaded_vmcs = &vmx->vmcs01;
8734         vmx_vcpu_put(vcpu);
8735         vmx_vcpu_load(vcpu, cpu);
8736         vcpu->cpu = cpu;
8737         put_cpu();
8738 }
8739
8740 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
8741 {
8742         struct vcpu_vmx *vmx = to_vmx(vcpu);
8743
8744         if (enable_pml)
8745                 vmx_destroy_pml_buffer(vmx);
8746         free_vpid(vmx->vpid);
8747         leave_guest_mode(vcpu);
8748         vmx_load_vmcs01(vcpu);
8749         free_nested(vmx);
8750         free_loaded_vmcs(vmx->loaded_vmcs);
8751         kfree(vmx->guest_msrs);
8752         kvm_vcpu_uninit(vcpu);
8753         kmem_cache_free(kvm_vcpu_cache, vmx);
8754 }
8755
8756 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
8757 {
8758         int err;
8759         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
8760         int cpu;
8761
8762         if (!vmx)
8763                 return ERR_PTR(-ENOMEM);
8764
8765         vmx->vpid = allocate_vpid();
8766
8767         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
8768         if (err)
8769                 goto free_vcpu;
8770
8771         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
8772         BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
8773                      > PAGE_SIZE);
8774
8775         err = -ENOMEM;
8776         if (!vmx->guest_msrs) {
8777                 goto uninit_vcpu;
8778         }
8779
8780         vmx->loaded_vmcs = &vmx->vmcs01;
8781         vmx->loaded_vmcs->vmcs = alloc_vmcs();
8782         if (!vmx->loaded_vmcs->vmcs)
8783                 goto free_msrs;
8784         if (!vmm_exclusive)
8785                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
8786         loaded_vmcs_init(vmx->loaded_vmcs);
8787         if (!vmm_exclusive)
8788                 kvm_cpu_vmxoff();
8789
8790         cpu = get_cpu();
8791         vmx_vcpu_load(&vmx->vcpu, cpu);
8792         vmx->vcpu.cpu = cpu;
8793         err = vmx_vcpu_setup(vmx);
8794         vmx_vcpu_put(&vmx->vcpu);
8795         put_cpu();
8796         if (err)
8797                 goto free_vmcs;
8798         if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
8799                 err = alloc_apic_access_page(kvm);
8800                 if (err)
8801                         goto free_vmcs;
8802         }
8803
8804         if (enable_ept) {
8805                 if (!kvm->arch.ept_identity_map_addr)
8806                         kvm->arch.ept_identity_map_addr =
8807                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
8808                 err = init_rmode_identity_map(kvm);
8809                 if (err)
8810                         goto free_vmcs;
8811         }
8812
8813         if (nested) {
8814                 nested_vmx_setup_ctls_msrs(vmx);
8815                 vmx->nested.vpid02 = allocate_vpid();
8816         }
8817
8818         vmx->nested.posted_intr_nv = -1;
8819         vmx->nested.current_vmptr = -1ull;
8820         vmx->nested.current_vmcs12 = NULL;
8821
8822         /*
8823          * If PML is turned on, failure on enabling PML just results in failure
8824          * of creating the vcpu, therefore we can simplify PML logic (by
8825          * avoiding dealing with cases, such as enabling PML partially on vcpus
8826          * for the guest, etc.
8827          */
8828         if (enable_pml) {
8829                 err = vmx_create_pml_buffer(vmx);
8830                 if (err)
8831                         goto free_vmcs;
8832         }
8833
8834         return &vmx->vcpu;
8835
8836 free_vmcs:
8837         free_vpid(vmx->nested.vpid02);
8838         free_loaded_vmcs(vmx->loaded_vmcs);
8839 free_msrs:
8840         kfree(vmx->guest_msrs);
8841 uninit_vcpu:
8842         kvm_vcpu_uninit(&vmx->vcpu);
8843 free_vcpu:
8844         free_vpid(vmx->vpid);
8845         kmem_cache_free(kvm_vcpu_cache, vmx);
8846         return ERR_PTR(err);
8847 }
8848
8849 static void __init vmx_check_processor_compat(void *rtn)
8850 {
8851         struct vmcs_config vmcs_conf;
8852
8853         *(int *)rtn = 0;
8854         if (setup_vmcs_config(&vmcs_conf) < 0)
8855                 *(int *)rtn = -EIO;
8856         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
8857                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
8858                                 smp_processor_id());
8859                 *(int *)rtn = -EIO;
8860         }
8861 }
8862
8863 static int get_ept_level(void)
8864 {
8865         return VMX_EPT_DEFAULT_GAW + 1;
8866 }
8867
8868 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
8869 {
8870         u8 cache;
8871         u64 ipat = 0;
8872
8873         /* For VT-d and EPT combination
8874          * 1. MMIO: always map as UC
8875          * 2. EPT with VT-d:
8876          *   a. VT-d without snooping control feature: can't guarantee the
8877          *      result, try to trust guest.
8878          *   b. VT-d with snooping control feature: snooping control feature of
8879          *      VT-d engine can guarantee the cache correctness. Just set it
8880          *      to WB to keep consistent with host. So the same as item 3.
8881          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
8882          *    consistent with host MTRR
8883          */
8884         if (is_mmio) {
8885                 cache = MTRR_TYPE_UNCACHABLE;
8886                 goto exit;
8887         }
8888
8889         if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
8890                 ipat = VMX_EPT_IPAT_BIT;
8891                 cache = MTRR_TYPE_WRBACK;
8892                 goto exit;
8893         }
8894
8895         if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
8896                 ipat = VMX_EPT_IPAT_BIT;
8897                 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
8898                         cache = MTRR_TYPE_WRBACK;
8899                 else
8900                         cache = MTRR_TYPE_UNCACHABLE;
8901                 goto exit;
8902         }
8903
8904         cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
8905
8906 exit:
8907         return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
8908 }
8909
8910 static int vmx_get_lpage_level(void)
8911 {
8912         if (enable_ept && !cpu_has_vmx_ept_1g_page())
8913                 return PT_DIRECTORY_LEVEL;
8914         else
8915                 /* For shadow and EPT supported 1GB page */
8916                 return PT_PDPE_LEVEL;
8917 }
8918
8919 static void vmcs_set_secondary_exec_control(u32 new_ctl)
8920 {
8921         /*
8922          * These bits in the secondary execution controls field
8923          * are dynamic, the others are mostly based on the hypervisor
8924          * architecture and the guest's CPUID.  Do not touch the
8925          * dynamic bits.
8926          */
8927         u32 mask =
8928                 SECONDARY_EXEC_SHADOW_VMCS |
8929                 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
8930                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
8931
8932         u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
8933
8934         vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
8935                      (new_ctl & ~mask) | (cur_ctl & mask));
8936 }
8937
8938 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
8939 {
8940         struct kvm_cpuid_entry2 *best;
8941         struct vcpu_vmx *vmx = to_vmx(vcpu);
8942         u32 secondary_exec_ctl = vmx_secondary_exec_control(vmx);
8943
8944         if (vmx_rdtscp_supported()) {
8945                 bool rdtscp_enabled = guest_cpuid_has_rdtscp(vcpu);
8946                 if (!rdtscp_enabled)
8947                         secondary_exec_ctl &= ~SECONDARY_EXEC_RDTSCP;
8948
8949                 if (nested) {
8950                         if (rdtscp_enabled)
8951                                 vmx->nested.nested_vmx_secondary_ctls_high |=
8952                                         SECONDARY_EXEC_RDTSCP;
8953                         else
8954                                 vmx->nested.nested_vmx_secondary_ctls_high &=
8955                                         ~SECONDARY_EXEC_RDTSCP;
8956                 }
8957         }
8958
8959         /* Exposing INVPCID only when PCID is exposed */
8960         best = kvm_find_cpuid_entry(vcpu, 0x7, 0);
8961         if (vmx_invpcid_supported() &&
8962             (!best || !(best->ebx & bit(X86_FEATURE_INVPCID)) ||
8963             !guest_cpuid_has_pcid(vcpu))) {
8964                 secondary_exec_ctl &= ~SECONDARY_EXEC_ENABLE_INVPCID;
8965
8966                 if (best)
8967                         best->ebx &= ~bit(X86_FEATURE_INVPCID);
8968         }
8969
8970         if (cpu_has_secondary_exec_ctrls())
8971                 vmcs_set_secondary_exec_control(secondary_exec_ctl);
8972
8973         if (static_cpu_has(X86_FEATURE_PCOMMIT) && nested) {
8974                 if (guest_cpuid_has_pcommit(vcpu))
8975                         vmx->nested.nested_vmx_secondary_ctls_high |=
8976                                 SECONDARY_EXEC_PCOMMIT;
8977                 else
8978                         vmx->nested.nested_vmx_secondary_ctls_high &=
8979                                 ~SECONDARY_EXEC_PCOMMIT;
8980         }
8981 }
8982
8983 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
8984 {
8985         if (func == 1 && nested)
8986                 entry->ecx |= bit(X86_FEATURE_VMX);
8987 }
8988
8989 static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
8990                 struct x86_exception *fault)
8991 {
8992         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
8993         u32 exit_reason;
8994
8995         if (fault->error_code & PFERR_RSVD_MASK)
8996                 exit_reason = EXIT_REASON_EPT_MISCONFIG;
8997         else
8998                 exit_reason = EXIT_REASON_EPT_VIOLATION;
8999         nested_vmx_vmexit(vcpu, exit_reason, 0, vcpu->arch.exit_qualification);
9000         vmcs12->guest_physical_address = fault->address;
9001 }
9002
9003 /* Callbacks for nested_ept_init_mmu_context: */
9004
9005 static unsigned long nested_ept_get_cr3(struct kvm_vcpu *vcpu)
9006 {
9007         /* return the page table to be shadowed - in our case, EPT12 */
9008         return get_vmcs12(vcpu)->ept_pointer;
9009 }
9010
9011 static void nested_ept_init_mmu_context(struct kvm_vcpu *vcpu)
9012 {
9013         WARN_ON(mmu_is_nested(vcpu));
9014         kvm_init_shadow_ept_mmu(vcpu,
9015                         to_vmx(vcpu)->nested.nested_vmx_ept_caps &
9016                         VMX_EPT_EXECUTE_ONLY_BIT);
9017         vcpu->arch.mmu.set_cr3           = vmx_set_cr3;
9018         vcpu->arch.mmu.get_cr3           = nested_ept_get_cr3;
9019         vcpu->arch.mmu.inject_page_fault = nested_ept_inject_page_fault;
9020
9021         vcpu->arch.walk_mmu              = &vcpu->arch.nested_mmu;
9022 }
9023
9024 static void nested_ept_uninit_mmu_context(struct kvm_vcpu *vcpu)
9025 {
9026         vcpu->arch.walk_mmu = &vcpu->arch.mmu;
9027 }
9028
9029 static bool nested_vmx_is_page_fault_vmexit(struct vmcs12 *vmcs12,
9030                                             u16 error_code)
9031 {
9032         bool inequality, bit;
9033
9034         bit = (vmcs12->exception_bitmap & (1u << PF_VECTOR)) != 0;
9035         inequality =
9036                 (error_code & vmcs12->page_fault_error_code_mask) !=
9037                  vmcs12->page_fault_error_code_match;
9038         return inequality ^ bit;
9039 }
9040
9041 static void vmx_inject_page_fault_nested(struct kvm_vcpu *vcpu,
9042                 struct x86_exception *fault)
9043 {
9044         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
9045
9046         WARN_ON(!is_guest_mode(vcpu));
9047
9048         if (nested_vmx_is_page_fault_vmexit(vmcs12, fault->error_code))
9049                 nested_vmx_vmexit(vcpu, to_vmx(vcpu)->exit_reason,
9050                                   vmcs_read32(VM_EXIT_INTR_INFO),
9051                                   vmcs_readl(EXIT_QUALIFICATION));
9052         else
9053                 kvm_inject_page_fault(vcpu, fault);
9054 }
9055
9056 static bool nested_get_vmcs12_pages(struct kvm_vcpu *vcpu,
9057                                         struct vmcs12 *vmcs12)
9058 {
9059         struct vcpu_vmx *vmx = to_vmx(vcpu);
9060         int maxphyaddr = cpuid_maxphyaddr(vcpu);
9061
9062         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)) {
9063                 if (!PAGE_ALIGNED(vmcs12->apic_access_addr) ||
9064                     vmcs12->apic_access_addr >> maxphyaddr)
9065                         return false;
9066
9067                 /*
9068                  * Translate L1 physical address to host physical
9069                  * address for vmcs02. Keep the page pinned, so this
9070                  * physical address remains valid. We keep a reference
9071                  * to it so we can release it later.
9072                  */
9073                 if (vmx->nested.apic_access_page) /* shouldn't happen */
9074                         nested_release_page(vmx->nested.apic_access_page);
9075                 vmx->nested.apic_access_page =
9076                         nested_get_page(vcpu, vmcs12->apic_access_addr);
9077         }
9078
9079         if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW)) {
9080                 if (!PAGE_ALIGNED(vmcs12->virtual_apic_page_addr) ||
9081                     vmcs12->virtual_apic_page_addr >> maxphyaddr)
9082                         return false;
9083
9084                 if (vmx->nested.virtual_apic_page) /* shouldn't happen */
9085                         nested_release_page(vmx->nested.virtual_apic_page);
9086                 vmx->nested.virtual_apic_page =
9087                         nested_get_page(vcpu, vmcs12->virtual_apic_page_addr);
9088
9089                 /*
9090                  * Failing the vm entry is _not_ what the processor does
9091                  * but it's basically the only possibility we have.
9092                  * We could still enter the guest if CR8 load exits are
9093                  * enabled, CR8 store exits are enabled, and virtualize APIC
9094                  * access is disabled; in this case the processor would never
9095                  * use the TPR shadow and we could simply clear the bit from
9096                  * the execution control.  But such a configuration is useless,
9097                  * so let's keep the code simple.
9098                  */
9099                 if (!vmx->nested.virtual_apic_page)
9100                         return false;
9101         }
9102
9103         if (nested_cpu_has_posted_intr(vmcs12)) {
9104                 if (!IS_ALIGNED(vmcs12->posted_intr_desc_addr, 64) ||
9105                     vmcs12->posted_intr_desc_addr >> maxphyaddr)
9106                         return false;
9107
9108                 if (vmx->nested.pi_desc_page) { /* shouldn't happen */
9109                         kunmap(vmx->nested.pi_desc_page);
9110                         nested_release_page(vmx->nested.pi_desc_page);
9111                 }
9112                 vmx->nested.pi_desc_page =
9113                         nested_get_page(vcpu, vmcs12->posted_intr_desc_addr);
9114                 if (!vmx->nested.pi_desc_page)
9115                         return false;
9116
9117                 vmx->nested.pi_desc =
9118                         (struct pi_desc *)kmap(vmx->nested.pi_desc_page);
9119                 if (!vmx->nested.pi_desc) {
9120                         nested_release_page_clean(vmx->nested.pi_desc_page);
9121                         return false;
9122                 }
9123                 vmx->nested.pi_desc =
9124                         (struct pi_desc *)((void *)vmx->nested.pi_desc +
9125                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9126                         (PAGE_SIZE - 1)));
9127         }
9128
9129         return true;
9130 }
9131
9132 static void vmx_start_preemption_timer(struct kvm_vcpu *vcpu)
9133 {
9134         u64 preemption_timeout = get_vmcs12(vcpu)->vmx_preemption_timer_value;
9135         struct vcpu_vmx *vmx = to_vmx(vcpu);
9136
9137         if (vcpu->arch.virtual_tsc_khz == 0)
9138                 return;
9139
9140         /* Make sure short timeouts reliably trigger an immediate vmexit.
9141          * hrtimer_start does not guarantee this. */
9142         if (preemption_timeout <= 1) {
9143                 vmx_preemption_timer_fn(&vmx->nested.preemption_timer);
9144                 return;
9145         }
9146
9147         preemption_timeout <<= VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
9148         preemption_timeout *= 1000000;
9149         do_div(preemption_timeout, vcpu->arch.virtual_tsc_khz);
9150         hrtimer_start(&vmx->nested.preemption_timer,
9151                       ns_to_ktime(preemption_timeout), HRTIMER_MODE_REL);
9152 }
9153
9154 static int nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu,
9155                                                 struct vmcs12 *vmcs12)
9156 {
9157         int maxphyaddr;
9158         u64 addr;
9159
9160         if (!nested_cpu_has(vmcs12, CPU_BASED_USE_MSR_BITMAPS))
9161                 return 0;
9162
9163         if (vmcs12_read_any(vcpu, MSR_BITMAP, &addr)) {
9164                 WARN_ON(1);
9165                 return -EINVAL;
9166         }
9167         maxphyaddr = cpuid_maxphyaddr(vcpu);
9168
9169         if (!PAGE_ALIGNED(vmcs12->msr_bitmap) ||
9170            ((addr + PAGE_SIZE) >> maxphyaddr))
9171                 return -EINVAL;
9172
9173         return 0;
9174 }
9175
9176 /*
9177  * Merge L0's and L1's MSR bitmap, return false to indicate that
9178  * we do not use the hardware.
9179  */
9180 static inline bool nested_vmx_merge_msr_bitmap(struct kvm_vcpu *vcpu,
9181                                                struct vmcs12 *vmcs12)
9182 {
9183         int msr;
9184         struct page *page;
9185         unsigned long *msr_bitmap;
9186
9187         if (!nested_cpu_has_virt_x2apic_mode(vmcs12))
9188                 return false;
9189
9190         page = nested_get_page(vcpu, vmcs12->msr_bitmap);
9191         if (!page) {
9192                 WARN_ON(1);
9193                 return false;
9194         }
9195         msr_bitmap = (unsigned long *)kmap(page);
9196         if (!msr_bitmap) {
9197                 nested_release_page_clean(page);
9198                 WARN_ON(1);
9199                 return false;
9200         }
9201
9202         if (nested_cpu_has_virt_x2apic_mode(vmcs12)) {
9203                 if (nested_cpu_has_apic_reg_virt(vmcs12))
9204                         for (msr = 0x800; msr <= 0x8ff; msr++)
9205                                 nested_vmx_disable_intercept_for_msr(
9206                                         msr_bitmap,
9207                                         vmx_msr_bitmap_nested,
9208                                         msr, MSR_TYPE_R);
9209                 /* TPR is allowed */
9210                 nested_vmx_disable_intercept_for_msr(msr_bitmap,
9211                                 vmx_msr_bitmap_nested,
9212                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9213                                 MSR_TYPE_R | MSR_TYPE_W);
9214                 if (nested_cpu_has_vid(vmcs12)) {
9215                         /* EOI and self-IPI are allowed */
9216                         nested_vmx_disable_intercept_for_msr(
9217                                 msr_bitmap,
9218                                 vmx_msr_bitmap_nested,
9219                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9220                                 MSR_TYPE_W);
9221                         nested_vmx_disable_intercept_for_msr(
9222                                 msr_bitmap,
9223                                 vmx_msr_bitmap_nested,
9224                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9225                                 MSR_TYPE_W);
9226                 }
9227         } else {
9228                 /*
9229                  * Enable reading intercept of all the x2apic
9230                  * MSRs. We should not rely on vmcs12 to do any
9231                  * optimizations here, it may have been modified
9232                  * by L1.
9233                  */
9234                 for (msr = 0x800; msr <= 0x8ff; msr++)
9235                         __vmx_enable_intercept_for_msr(
9236                                 vmx_msr_bitmap_nested,
9237                                 msr,
9238                                 MSR_TYPE_R);
9239
9240                 __vmx_enable_intercept_for_msr(
9241                                 vmx_msr_bitmap_nested,
9242                                 APIC_BASE_MSR + (APIC_TASKPRI >> 4),
9243                                 MSR_TYPE_W);
9244                 __vmx_enable_intercept_for_msr(
9245                                 vmx_msr_bitmap_nested,
9246                                 APIC_BASE_MSR + (APIC_EOI >> 4),
9247                                 MSR_TYPE_W);
9248                 __vmx_enable_intercept_for_msr(
9249                                 vmx_msr_bitmap_nested,
9250                                 APIC_BASE_MSR + (APIC_SELF_IPI >> 4),
9251                                 MSR_TYPE_W);
9252         }
9253         kunmap(page);
9254         nested_release_page_clean(page);
9255
9256         return true;
9257 }
9258
9259 static int nested_vmx_check_apicv_controls(struct kvm_vcpu *vcpu,
9260                                            struct vmcs12 *vmcs12)
9261 {
9262         if (!nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9263             !nested_cpu_has_apic_reg_virt(vmcs12) &&
9264             !nested_cpu_has_vid(vmcs12) &&
9265             !nested_cpu_has_posted_intr(vmcs12))
9266                 return 0;
9267
9268         /*
9269          * If virtualize x2apic mode is enabled,
9270          * virtualize apic access must be disabled.
9271          */
9272         if (nested_cpu_has_virt_x2apic_mode(vmcs12) &&
9273             nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
9274                 return -EINVAL;
9275
9276         /*
9277          * If virtual interrupt delivery is enabled,
9278          * we must exit on external interrupts.
9279          */
9280         if (nested_cpu_has_vid(vmcs12) &&
9281            !nested_exit_on_intr(vcpu))
9282                 return -EINVAL;
9283
9284         /*
9285          * bits 15:8 should be zero in posted_intr_nv,
9286          * the descriptor address has been already checked
9287          * in nested_get_vmcs12_pages.
9288          */
9289         if (nested_cpu_has_posted_intr(vmcs12) &&
9290            (!nested_cpu_has_vid(vmcs12) ||
9291             !nested_exit_intr_ack_set(vcpu) ||
9292             vmcs12->posted_intr_nv & 0xff00))
9293                 return -EINVAL;
9294
9295         /* tpr shadow is needed by all apicv features. */
9296         if (!nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
9297                 return -EINVAL;
9298
9299         return 0;
9300 }
9301
9302 static int nested_vmx_check_msr_switch(struct kvm_vcpu *vcpu,
9303                                        unsigned long count_field,
9304                                        unsigned long addr_field)
9305 {
9306         int maxphyaddr;
9307         u64 count, addr;
9308
9309         if (vmcs12_read_any(vcpu, count_field, &count) ||
9310             vmcs12_read_any(vcpu, addr_field, &addr)) {
9311                 WARN_ON(1);
9312                 return -EINVAL;
9313         }
9314         if (count == 0)
9315                 return 0;
9316         maxphyaddr = cpuid_maxphyaddr(vcpu);
9317         if (!IS_ALIGNED(addr, 16) || addr >> maxphyaddr ||
9318             (addr + count * sizeof(struct vmx_msr_entry) - 1) >> maxphyaddr) {
9319                 pr_warn_ratelimited(
9320                         "nVMX: invalid MSR switch (0x%lx, %d, %llu, 0x%08llx)",
9321                         addr_field, maxphyaddr, count, addr);
9322                 return -EINVAL;
9323         }
9324         return 0;
9325 }
9326
9327 static int nested_vmx_check_msr_switch_controls(struct kvm_vcpu *vcpu,
9328                                                 struct vmcs12 *vmcs12)
9329 {
9330         if (vmcs12->vm_exit_msr_load_count == 0 &&
9331             vmcs12->vm_exit_msr_store_count == 0 &&
9332             vmcs12->vm_entry_msr_load_count == 0)
9333                 return 0; /* Fast path */
9334         if (nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_LOAD_COUNT,
9335                                         VM_EXIT_MSR_LOAD_ADDR) ||
9336             nested_vmx_check_msr_switch(vcpu, VM_EXIT_MSR_STORE_COUNT,
9337                                         VM_EXIT_MSR_STORE_ADDR) ||
9338             nested_vmx_check_msr_switch(vcpu, VM_ENTRY_MSR_LOAD_COUNT,
9339                                         VM_ENTRY_MSR_LOAD_ADDR))
9340                 return -EINVAL;
9341         return 0;
9342 }
9343
9344 static int nested_vmx_msr_check_common(struct kvm_vcpu *vcpu,
9345                                        struct vmx_msr_entry *e)
9346 {
9347         /* x2APIC MSR accesses are not allowed */
9348         if (vcpu->arch.apic_base & X2APIC_ENABLE && e->index >> 8 == 0x8)
9349                 return -EINVAL;
9350         if (e->index == MSR_IA32_UCODE_WRITE || /* SDM Table 35-2 */
9351             e->index == MSR_IA32_UCODE_REV)
9352                 return -EINVAL;
9353         if (e->reserved != 0)
9354                 return -EINVAL;
9355         return 0;
9356 }
9357
9358 static int nested_vmx_load_msr_check(struct kvm_vcpu *vcpu,
9359                                      struct vmx_msr_entry *e)
9360 {
9361         if (e->index == MSR_FS_BASE ||
9362             e->index == MSR_GS_BASE ||
9363             e->index == MSR_IA32_SMM_MONITOR_CTL || /* SMM is not supported */
9364             nested_vmx_msr_check_common(vcpu, e))
9365                 return -EINVAL;
9366         return 0;
9367 }
9368
9369 static int nested_vmx_store_msr_check(struct kvm_vcpu *vcpu,
9370                                       struct vmx_msr_entry *e)
9371 {
9372         if (e->index == MSR_IA32_SMBASE || /* SMM is not supported */
9373             nested_vmx_msr_check_common(vcpu, e))
9374                 return -EINVAL;
9375         return 0;
9376 }
9377
9378 /*
9379  * Load guest's/host's msr at nested entry/exit.
9380  * return 0 for success, entry index for failure.
9381  */
9382 static u32 nested_vmx_load_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9383 {
9384         u32 i;
9385         struct vmx_msr_entry e;
9386         struct msr_data msr;
9387
9388         msr.host_initiated = false;
9389         for (i = 0; i < count; i++) {
9390                 if (kvm_vcpu_read_guest(vcpu, gpa + i * sizeof(e),
9391                                         &e, sizeof(e))) {
9392                         pr_warn_ratelimited(
9393                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9394                                 __func__, i, gpa + i * sizeof(e));
9395                         goto fail;
9396                 }
9397                 if (nested_vmx_load_msr_check(vcpu, &e)) {
9398                         pr_warn_ratelimited(
9399                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9400                                 __func__, i, e.index, e.reserved);
9401                         goto fail;
9402                 }
9403                 msr.index = e.index;
9404                 msr.data = e.value;
9405                 if (kvm_set_msr(vcpu, &msr)) {
9406                         pr_warn_ratelimited(
9407                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9408                                 __func__, i, e.index, e.value);
9409                         goto fail;
9410                 }
9411         }
9412         return 0;
9413 fail:
9414         return i + 1;
9415 }
9416
9417 static int nested_vmx_store_msr(struct kvm_vcpu *vcpu, u64 gpa, u32 count)
9418 {
9419         u32 i;
9420         struct vmx_msr_entry e;
9421
9422         for (i = 0; i < count; i++) {
9423                 struct msr_data msr_info;
9424                 if (kvm_vcpu_read_guest(vcpu,
9425                                         gpa + i * sizeof(e),
9426                                         &e, 2 * sizeof(u32))) {
9427                         pr_warn_ratelimited(
9428                                 "%s cannot read MSR entry (%u, 0x%08llx)\n",
9429                                 __func__, i, gpa + i * sizeof(e));
9430                         return -EINVAL;
9431                 }
9432                 if (nested_vmx_store_msr_check(vcpu, &e)) {
9433                         pr_warn_ratelimited(
9434                                 "%s check failed (%u, 0x%x, 0x%x)\n",
9435                                 __func__, i, e.index, e.reserved);
9436                         return -EINVAL;
9437                 }
9438                 msr_info.host_initiated = false;
9439                 msr_info.index = e.index;
9440                 if (kvm_get_msr(vcpu, &msr_info)) {
9441                         pr_warn_ratelimited(
9442                                 "%s cannot read MSR (%u, 0x%x)\n",
9443                                 __func__, i, e.index);
9444                         return -EINVAL;
9445                 }
9446                 if (kvm_vcpu_write_guest(vcpu,
9447                                          gpa + i * sizeof(e) +
9448                                              offsetof(struct vmx_msr_entry, value),
9449                                          &msr_info.data, sizeof(msr_info.data))) {
9450                         pr_warn_ratelimited(
9451                                 "%s cannot write MSR (%u, 0x%x, 0x%llx)\n",
9452                                 __func__, i, e.index, msr_info.data);
9453                         return -EINVAL;
9454                 }
9455         }
9456         return 0;
9457 }
9458
9459 /*
9460  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
9461  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
9462  * with L0's requirements for its guest (a.k.a. vmcs01), so we can run the L2
9463  * guest in a way that will both be appropriate to L1's requests, and our
9464  * needs. In addition to modifying the active vmcs (which is vmcs02), this
9465  * function also has additional necessary side-effects, like setting various
9466  * vcpu->arch fields.
9467  */
9468 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
9469 {
9470         struct vcpu_vmx *vmx = to_vmx(vcpu);
9471         u32 exec_control;
9472
9473         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
9474         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
9475         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
9476         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
9477         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
9478         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
9479         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
9480         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
9481         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
9482         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
9483         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
9484         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
9485         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
9486         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
9487         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
9488         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
9489         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
9490         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
9491         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
9492         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
9493         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
9494         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
9495         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
9496         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
9497         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
9498         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
9499         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
9500         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
9501         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
9502         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
9503         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
9504         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
9505         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
9506         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
9507         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
9508         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
9509
9510         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS) {
9511                 kvm_set_dr(vcpu, 7, vmcs12->guest_dr7);
9512                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
9513         } else {
9514                 kvm_set_dr(vcpu, 7, vcpu->arch.dr7);
9515                 vmcs_write64(GUEST_IA32_DEBUGCTL, vmx->nested.vmcs01_debugctl);
9516         }
9517         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
9518                 vmcs12->vm_entry_intr_info_field);
9519         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
9520                 vmcs12->vm_entry_exception_error_code);
9521         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
9522                 vmcs12->vm_entry_instruction_len);
9523         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
9524                 vmcs12->guest_interruptibility_info);
9525         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
9526         vmx_set_rflags(vcpu, vmcs12->guest_rflags);
9527         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
9528                 vmcs12->guest_pending_dbg_exceptions);
9529         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
9530         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
9531
9532         if (nested_cpu_has_xsaves(vmcs12))
9533                 vmcs_write64(XSS_EXIT_BITMAP, vmcs12->xss_exit_bitmap);
9534         vmcs_write64(VMCS_LINK_POINTER, -1ull);
9535
9536         exec_control = vmcs12->pin_based_vm_exec_control;
9537         exec_control |= vmcs_config.pin_based_exec_ctrl;
9538         exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
9539
9540         if (nested_cpu_has_posted_intr(vmcs12)) {
9541                 /*
9542                  * Note that we use L0's vector here and in
9543                  * vmx_deliver_nested_posted_interrupt.
9544                  */
9545                 vmx->nested.posted_intr_nv = vmcs12->posted_intr_nv;
9546                 vmx->nested.pi_pending = false;
9547                 vmcs_write64(POSTED_INTR_NV, POSTED_INTR_VECTOR);
9548                 vmcs_write64(POSTED_INTR_DESC_ADDR,
9549                         page_to_phys(vmx->nested.pi_desc_page) +
9550                         (unsigned long)(vmcs12->posted_intr_desc_addr &
9551                         (PAGE_SIZE - 1)));
9552         } else
9553                 exec_control &= ~PIN_BASED_POSTED_INTR;
9554
9555         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, exec_control);
9556
9557         vmx->nested.preemption_timer_expired = false;
9558         if (nested_cpu_has_preemption_timer(vmcs12))
9559                 vmx_start_preemption_timer(vcpu);
9560
9561         /*
9562          * Whether page-faults are trapped is determined by a combination of
9563          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
9564          * If enable_ept, L0 doesn't care about page faults and we should
9565          * set all of these to L1's desires. However, if !enable_ept, L0 does
9566          * care about (at least some) page faults, and because it is not easy
9567          * (if at all possible?) to merge L0 and L1's desires, we simply ask
9568          * to exit on each and every L2 page fault. This is done by setting
9569          * MASK=MATCH=0 and (see below) EB.PF=1.
9570          * Note that below we don't need special code to set EB.PF beyond the
9571          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
9572          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
9573          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
9574          *
9575          * A problem with this approach (when !enable_ept) is that L1 may be
9576          * injected with more page faults than it asked for. This could have
9577          * caused problems, but in practice existing hypervisors don't care.
9578          * To fix this, we will need to emulate the PFEC checking (on the L1
9579          * page tables), using walk_addr(), when injecting PFs to L1.
9580          */
9581         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
9582                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
9583         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
9584                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
9585
9586         if (cpu_has_secondary_exec_ctrls()) {
9587                 exec_control = vmx_secondary_exec_control(vmx);
9588
9589                 /* Take the following fields only from vmcs12 */
9590                 exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
9591                                   SECONDARY_EXEC_RDTSCP |
9592                                   SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
9593                                   SECONDARY_EXEC_APIC_REGISTER_VIRT |
9594                                   SECONDARY_EXEC_PCOMMIT);
9595                 if (nested_cpu_has(vmcs12,
9596                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
9597                         exec_control |= vmcs12->secondary_vm_exec_control;
9598
9599                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
9600                         /*
9601                          * If translation failed, no matter: This feature asks
9602                          * to exit when accessing the given address, and if it
9603                          * can never be accessed, this feature won't do
9604                          * anything anyway.
9605                          */
9606                         if (!vmx->nested.apic_access_page)
9607                                 exec_control &=
9608                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9609                         else
9610                                 vmcs_write64(APIC_ACCESS_ADDR,
9611                                   page_to_phys(vmx->nested.apic_access_page));
9612                 } else if (!(nested_cpu_has_virt_x2apic_mode(vmcs12)) &&
9613                             cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
9614                         exec_control |=
9615                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
9616                         kvm_vcpu_reload_apic_access_page(vcpu);
9617                 }
9618
9619                 if (exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY) {
9620                         vmcs_write64(EOI_EXIT_BITMAP0,
9621                                 vmcs12->eoi_exit_bitmap0);
9622                         vmcs_write64(EOI_EXIT_BITMAP1,
9623                                 vmcs12->eoi_exit_bitmap1);
9624                         vmcs_write64(EOI_EXIT_BITMAP2,
9625                                 vmcs12->eoi_exit_bitmap2);
9626                         vmcs_write64(EOI_EXIT_BITMAP3,
9627                                 vmcs12->eoi_exit_bitmap3);
9628                         vmcs_write16(GUEST_INTR_STATUS,
9629                                 vmcs12->guest_intr_status);
9630                 }
9631
9632                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
9633         }
9634
9635
9636         /*
9637          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
9638          * Some constant fields are set here by vmx_set_constant_host_state().
9639          * Other fields are different per CPU, and will be set later when
9640          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
9641          */
9642         vmx_set_constant_host_state(vmx);
9643
9644         /*
9645          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
9646          * entry, but only if the current (host) sp changed from the value
9647          * we wrote last (vmx->host_rsp). This cache is no longer relevant
9648          * if we switch vmcs, and rather than hold a separate cache per vmcs,
9649          * here we just force the write to happen on entry.
9650          */
9651         vmx->host_rsp = 0;
9652
9653         exec_control = vmx_exec_control(vmx); /* L0's desires */
9654         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
9655         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
9656         exec_control &= ~CPU_BASED_TPR_SHADOW;
9657         exec_control |= vmcs12->cpu_based_vm_exec_control;
9658
9659         if (exec_control & CPU_BASED_TPR_SHADOW) {
9660                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
9661                                 page_to_phys(vmx->nested.virtual_apic_page));
9662                 vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
9663         }
9664
9665         if (cpu_has_vmx_msr_bitmap() &&
9666             exec_control & CPU_BASED_USE_MSR_BITMAPS) {
9667                 nested_vmx_merge_msr_bitmap(vcpu, vmcs12);
9668                 /* MSR_BITMAP will be set by following vmx_set_efer. */
9669         } else
9670                 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
9671
9672         /*
9673          * Merging of IO bitmap not currently supported.
9674          * Rather, exit every time.
9675          */
9676         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
9677         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
9678
9679         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
9680
9681         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
9682          * bitwise-or of what L1 wants to trap for L2, and what we want to
9683          * trap. Note that CR0.TS also needs updating - we do this later.
9684          */
9685         update_exception_bitmap(vcpu);
9686         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
9687         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
9688
9689         /* L2->L1 exit controls are emulated - the hardware exit is to L0 so
9690          * we should use its exit controls. Note that VM_EXIT_LOAD_IA32_EFER
9691          * bits are further modified by vmx_set_efer() below.
9692          */
9693         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
9694
9695         /* vmcs12's VM_ENTRY_LOAD_IA32_EFER and VM_ENTRY_IA32E_MODE are
9696          * emulated by vmx_set_efer(), below.
9697          */
9698         vm_entry_controls_init(vmx,
9699                 (vmcs12->vm_entry_controls & ~VM_ENTRY_LOAD_IA32_EFER &
9700                         ~VM_ENTRY_IA32E_MODE) |
9701                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
9702
9703         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT) {
9704                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
9705                 vcpu->arch.pat = vmcs12->guest_ia32_pat;
9706         } else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
9707                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
9708
9709
9710         set_cr4_guest_host_mask(vmx);
9711
9712         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_BNDCFGS)
9713                 vmcs_write64(GUEST_BNDCFGS, vmcs12->guest_bndcfgs);
9714
9715         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
9716                 vmcs_write64(TSC_OFFSET,
9717                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
9718         else
9719                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
9720
9721         if (enable_vpid) {
9722                 /*
9723                  * There is no direct mapping between vpid02 and vpid12, the
9724                  * vpid02 is per-vCPU for L0 and reused while the value of
9725                  * vpid12 is changed w/ one invvpid during nested vmentry.
9726                  * The vpid12 is allocated by L1 for L2, so it will not
9727                  * influence global bitmap(for vpid01 and vpid02 allocation)
9728                  * even if spawn a lot of nested vCPUs.
9729                  */
9730                 if (nested_cpu_has_vpid(vmcs12) && vmx->nested.vpid02) {
9731                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->nested.vpid02);
9732                         if (vmcs12->virtual_processor_id != vmx->nested.last_vpid) {
9733                                 vmx->nested.last_vpid = vmcs12->virtual_processor_id;
9734                                 __vmx_flush_tlb(vcpu, to_vmx(vcpu)->nested.vpid02);
9735                         }
9736                 } else {
9737                         vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
9738                         vmx_flush_tlb(vcpu);
9739                 }
9740
9741         }
9742
9743         if (nested_cpu_has_ept(vmcs12)) {
9744                 kvm_mmu_unload(vcpu);
9745                 nested_ept_init_mmu_context(vcpu);
9746         }
9747
9748         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
9749                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
9750         else if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
9751                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
9752         else
9753                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
9754         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
9755         vmx_set_efer(vcpu, vcpu->arch.efer);
9756
9757         /*
9758          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
9759          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
9760          * The CR0_READ_SHADOW is what L2 should have expected to read given
9761          * the specifications by L1; It's not enough to take
9762          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
9763          * have more bits than L1 expected.
9764          */
9765         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
9766         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
9767
9768         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
9769         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
9770
9771         /* shadow page tables on either EPT or shadow page tables */
9772         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
9773         kvm_mmu_reset_context(vcpu);
9774
9775         if (!enable_ept)
9776                 vcpu->arch.walk_mmu->inject_page_fault = vmx_inject_page_fault_nested;
9777
9778         /*
9779          * L1 may access the L2's PDPTR, so save them to construct vmcs12
9780          */
9781         if (enable_ept) {
9782                 vmcs_write64(GUEST_PDPTR0, vmcs12->guest_pdptr0);
9783                 vmcs_write64(GUEST_PDPTR1, vmcs12->guest_pdptr1);
9784                 vmcs_write64(GUEST_PDPTR2, vmcs12->guest_pdptr2);
9785                 vmcs_write64(GUEST_PDPTR3, vmcs12->guest_pdptr3);
9786         }
9787
9788         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
9789         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
9790 }
9791
9792 /*
9793  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
9794  * for running an L2 nested guest.
9795  */
9796 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
9797 {
9798         struct vmcs12 *vmcs12;
9799         struct vcpu_vmx *vmx = to_vmx(vcpu);
9800         int cpu;
9801         struct loaded_vmcs *vmcs02;
9802         bool ia32e;
9803         u32 msr_entry_idx;
9804
9805         if (!nested_vmx_check_permission(vcpu) ||
9806             !nested_vmx_check_vmcs12(vcpu))
9807                 return 1;
9808
9809         skip_emulated_instruction(vcpu);
9810         vmcs12 = get_vmcs12(vcpu);
9811
9812         if (enable_shadow_vmcs)
9813                 copy_shadow_to_vmcs12(vmx);
9814
9815         /*
9816          * The nested entry process starts with enforcing various prerequisites
9817          * on vmcs12 as required by the Intel SDM, and act appropriately when
9818          * they fail: As the SDM explains, some conditions should cause the
9819          * instruction to fail, while others will cause the instruction to seem
9820          * to succeed, but return an EXIT_REASON_INVALID_STATE.
9821          * To speed up the normal (success) code path, we should avoid checking
9822          * for misconfigurations which will anyway be caught by the processor
9823          * when using the merged vmcs02.
9824          */
9825         if (vmcs12->launch_state == launch) {
9826                 nested_vmx_failValid(vcpu,
9827                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
9828                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
9829                 return 1;
9830         }
9831
9832         if (vmcs12->guest_activity_state != GUEST_ACTIVITY_ACTIVE &&
9833             vmcs12->guest_activity_state != GUEST_ACTIVITY_HLT) {
9834                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9835                 return 1;
9836         }
9837
9838         if (!nested_get_vmcs12_pages(vcpu, vmcs12)) {
9839                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9840                 return 1;
9841         }
9842
9843         if (nested_vmx_check_msr_bitmap_controls(vcpu, vmcs12)) {
9844                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9845                 return 1;
9846         }
9847
9848         if (nested_vmx_check_apicv_controls(vcpu, vmcs12)) {
9849                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9850                 return 1;
9851         }
9852
9853         if (nested_vmx_check_msr_switch_controls(vcpu, vmcs12)) {
9854                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9855                 return 1;
9856         }
9857
9858         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
9859                                 vmx->nested.nested_vmx_true_procbased_ctls_low,
9860                                 vmx->nested.nested_vmx_procbased_ctls_high) ||
9861             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
9862                                 vmx->nested.nested_vmx_secondary_ctls_low,
9863                                 vmx->nested.nested_vmx_secondary_ctls_high) ||
9864             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
9865                                 vmx->nested.nested_vmx_pinbased_ctls_low,
9866                                 vmx->nested.nested_vmx_pinbased_ctls_high) ||
9867             !vmx_control_verify(vmcs12->vm_exit_controls,
9868                                 vmx->nested.nested_vmx_true_exit_ctls_low,
9869                                 vmx->nested.nested_vmx_exit_ctls_high) ||
9870             !vmx_control_verify(vmcs12->vm_entry_controls,
9871                                 vmx->nested.nested_vmx_true_entry_ctls_low,
9872                                 vmx->nested.nested_vmx_entry_ctls_high))
9873         {
9874                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
9875                 return 1;
9876         }
9877
9878         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
9879             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9880                 nested_vmx_failValid(vcpu,
9881                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
9882                 return 1;
9883         }
9884
9885         if (!nested_cr0_valid(vcpu, vmcs12->guest_cr0) ||
9886             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
9887                 nested_vmx_entry_failure(vcpu, vmcs12,
9888                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9889                 return 1;
9890         }
9891         if (vmcs12->vmcs_link_pointer != -1ull) {
9892                 nested_vmx_entry_failure(vcpu, vmcs12,
9893                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
9894                 return 1;
9895         }
9896
9897         /*
9898          * If the load IA32_EFER VM-entry control is 1, the following checks
9899          * are performed on the field for the IA32_EFER MSR:
9900          * - Bits reserved in the IA32_EFER MSR must be 0.
9901          * - Bit 10 (corresponding to IA32_EFER.LMA) must equal the value of
9902          *   the IA-32e mode guest VM-exit control. It must also be identical
9903          *   to bit 8 (LME) if bit 31 in the CR0 field (corresponding to
9904          *   CR0.PG) is 1.
9905          */
9906         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER) {
9907                 ia32e = (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE) != 0;
9908                 if (!kvm_valid_efer(vcpu, vmcs12->guest_ia32_efer) ||
9909                     ia32e != !!(vmcs12->guest_ia32_efer & EFER_LMA) ||
9910                     ((vmcs12->guest_cr0 & X86_CR0_PG) &&
9911                      ia32e != !!(vmcs12->guest_ia32_efer & EFER_LME))) {
9912                         nested_vmx_entry_failure(vcpu, vmcs12,
9913                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9914                         return 1;
9915                 }
9916         }
9917
9918         /*
9919          * If the load IA32_EFER VM-exit control is 1, bits reserved in the
9920          * IA32_EFER MSR must be 0 in the field for that register. In addition,
9921          * the values of the LMA and LME bits in the field must each be that of
9922          * the host address-space size VM-exit control.
9923          */
9924         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER) {
9925                 ia32e = (vmcs12->vm_exit_controls &
9926                          VM_EXIT_HOST_ADDR_SPACE_SIZE) != 0;
9927                 if (!kvm_valid_efer(vcpu, vmcs12->host_ia32_efer) ||
9928                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LMA) ||
9929                     ia32e != !!(vmcs12->host_ia32_efer & EFER_LME)) {
9930                         nested_vmx_entry_failure(vcpu, vmcs12,
9931                                 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
9932                         return 1;
9933                 }
9934         }
9935
9936         /*
9937          * We're finally done with prerequisite checking, and can start with
9938          * the nested entry.
9939          */
9940
9941         vmcs02 = nested_get_current_vmcs02(vmx);
9942         if (!vmcs02)
9943                 return -ENOMEM;
9944
9945         enter_guest_mode(vcpu);
9946
9947         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
9948
9949         if (!(vmcs12->vm_entry_controls & VM_ENTRY_LOAD_DEBUG_CONTROLS))
9950                 vmx->nested.vmcs01_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
9951
9952         cpu = get_cpu();
9953         vmx->loaded_vmcs = vmcs02;
9954         vmx_vcpu_put(vcpu);
9955         vmx_vcpu_load(vcpu, cpu);
9956         vcpu->cpu = cpu;
9957         put_cpu();
9958
9959         vmx_segment_cache_clear(vmx);
9960
9961         prepare_vmcs02(vcpu, vmcs12);
9962
9963         msr_entry_idx = nested_vmx_load_msr(vcpu,
9964                                             vmcs12->vm_entry_msr_load_addr,
9965                                             vmcs12->vm_entry_msr_load_count);
9966         if (msr_entry_idx) {
9967                 leave_guest_mode(vcpu);
9968                 vmx_load_vmcs01(vcpu);
9969                 nested_vmx_entry_failure(vcpu, vmcs12,
9970                                 EXIT_REASON_MSR_LOAD_FAIL, msr_entry_idx);
9971                 return 1;
9972         }
9973
9974         vmcs12->launch_state = 1;
9975
9976         if (vmcs12->guest_activity_state == GUEST_ACTIVITY_HLT)
9977                 return kvm_vcpu_halt(vcpu);
9978
9979         vmx->nested.nested_run_pending = 1;
9980
9981         /*
9982          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
9983          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
9984          * returned as far as L1 is concerned. It will only return (and set
9985          * the success flag) when L2 exits (see nested_vmx_vmexit()).
9986          */
9987         return 1;
9988 }
9989
9990 /*
9991  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
9992  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
9993  * This function returns the new value we should put in vmcs12.guest_cr0.
9994  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
9995  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
9996  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
9997  *     didn't trap the bit, because if L1 did, so would L0).
9998  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
9999  *     been modified by L2, and L1 knows it. So just leave the old value of
10000  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
10001  *     isn't relevant, because if L0 traps this bit it can set it to anything.
10002  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
10003  *     changed these bits, and therefore they need to be updated, but L0
10004  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
10005  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
10006  */
10007 static inline unsigned long
10008 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10009 {
10010         return
10011         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
10012         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
10013         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
10014                         vcpu->arch.cr0_guest_owned_bits));
10015 }
10016
10017 static inline unsigned long
10018 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
10019 {
10020         return
10021         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
10022         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
10023         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
10024                         vcpu->arch.cr4_guest_owned_bits));
10025 }
10026
10027 static void vmcs12_save_pending_event(struct kvm_vcpu *vcpu,
10028                                        struct vmcs12 *vmcs12)
10029 {
10030         u32 idt_vectoring;
10031         unsigned int nr;
10032
10033         if (vcpu->arch.exception.pending && vcpu->arch.exception.reinject) {
10034                 nr = vcpu->arch.exception.nr;
10035                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10036
10037                 if (kvm_exception_is_soft(nr)) {
10038                         vmcs12->vm_exit_instruction_len =
10039                                 vcpu->arch.event_exit_inst_len;
10040                         idt_vectoring |= INTR_TYPE_SOFT_EXCEPTION;
10041                 } else
10042                         idt_vectoring |= INTR_TYPE_HARD_EXCEPTION;
10043
10044                 if (vcpu->arch.exception.has_error_code) {
10045                         idt_vectoring |= VECTORING_INFO_DELIVER_CODE_MASK;
10046                         vmcs12->idt_vectoring_error_code =
10047                                 vcpu->arch.exception.error_code;
10048                 }
10049
10050                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10051         } else if (vcpu->arch.nmi_injected) {
10052                 vmcs12->idt_vectoring_info_field =
10053                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR;
10054         } else if (vcpu->arch.interrupt.pending) {
10055                 nr = vcpu->arch.interrupt.nr;
10056                 idt_vectoring = nr | VECTORING_INFO_VALID_MASK;
10057
10058                 if (vcpu->arch.interrupt.soft) {
10059                         idt_vectoring |= INTR_TYPE_SOFT_INTR;
10060                         vmcs12->vm_entry_instruction_len =
10061                                 vcpu->arch.event_exit_inst_len;
10062                 } else
10063                         idt_vectoring |= INTR_TYPE_EXT_INTR;
10064
10065                 vmcs12->idt_vectoring_info_field = idt_vectoring;
10066         }
10067 }
10068
10069 static int vmx_check_nested_events(struct kvm_vcpu *vcpu, bool external_intr)
10070 {
10071         struct vcpu_vmx *vmx = to_vmx(vcpu);
10072
10073         if (nested_cpu_has_preemption_timer(get_vmcs12(vcpu)) &&
10074             vmx->nested.preemption_timer_expired) {
10075                 if (vmx->nested.nested_run_pending)
10076                         return -EBUSY;
10077                 nested_vmx_vmexit(vcpu, EXIT_REASON_PREEMPTION_TIMER, 0, 0);
10078                 return 0;
10079         }
10080
10081         if (vcpu->arch.nmi_pending && nested_exit_on_nmi(vcpu)) {
10082                 if (vmx->nested.nested_run_pending ||
10083                     vcpu->arch.interrupt.pending)
10084                         return -EBUSY;
10085                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXCEPTION_NMI,
10086                                   NMI_VECTOR | INTR_TYPE_NMI_INTR |
10087                                   INTR_INFO_VALID_MASK, 0);
10088                 /*
10089                  * The NMI-triggered VM exit counts as injection:
10090                  * clear this one and block further NMIs.
10091                  */
10092                 vcpu->arch.nmi_pending = 0;
10093                 vmx_set_nmi_mask(vcpu, true);
10094                 return 0;
10095         }
10096
10097         if ((kvm_cpu_has_interrupt(vcpu) || external_intr) &&
10098             nested_exit_on_intr(vcpu)) {
10099                 if (vmx->nested.nested_run_pending)
10100                         return -EBUSY;
10101                 nested_vmx_vmexit(vcpu, EXIT_REASON_EXTERNAL_INTERRUPT, 0, 0);
10102                 return 0;
10103         }
10104
10105         return vmx_complete_nested_posted_interrupt(vcpu);
10106 }
10107
10108 static u32 vmx_get_preemption_timer_value(struct kvm_vcpu *vcpu)
10109 {
10110         ktime_t remaining =
10111                 hrtimer_get_remaining(&to_vmx(vcpu)->nested.preemption_timer);
10112         u64 value;
10113
10114         if (ktime_to_ns(remaining) <= 0)
10115                 return 0;
10116
10117         value = ktime_to_ns(remaining) * vcpu->arch.virtual_tsc_khz;
10118         do_div(value, 1000000);
10119         return value >> VMX_MISC_EMULATED_PREEMPTION_TIMER_RATE;
10120 }
10121
10122 /*
10123  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
10124  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
10125  * and this function updates it to reflect the changes to the guest state while
10126  * L2 was running (and perhaps made some exits which were handled directly by L0
10127  * without going back to L1), and to reflect the exit reason.
10128  * Note that we do not have to copy here all VMCS fields, just those that
10129  * could have changed by the L2 guest or the exit - i.e., the guest-state and
10130  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
10131  * which already writes to vmcs12 directly.
10132  */
10133 static void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12,
10134                            u32 exit_reason, u32 exit_intr_info,
10135                            unsigned long exit_qualification)
10136 {
10137         /* update guest state fields: */
10138         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
10139         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
10140
10141         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
10142         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
10143         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
10144
10145         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
10146         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
10147         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
10148         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
10149         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
10150         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
10151         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
10152         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
10153         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
10154         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
10155         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
10156         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
10157         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
10158         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
10159         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
10160         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
10161         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
10162         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
10163         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
10164         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
10165         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
10166         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
10167         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
10168         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
10169         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
10170         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
10171         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
10172         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
10173         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
10174         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
10175         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
10176         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
10177         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
10178         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
10179         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
10180         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
10181
10182         vmcs12->guest_interruptibility_info =
10183                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
10184         vmcs12->guest_pending_dbg_exceptions =
10185                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
10186         if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED)
10187                 vmcs12->guest_activity_state = GUEST_ACTIVITY_HLT;
10188         else
10189                 vmcs12->guest_activity_state = GUEST_ACTIVITY_ACTIVE;
10190
10191         if (nested_cpu_has_preemption_timer(vmcs12)) {
10192                 if (vmcs12->vm_exit_controls &
10193                     VM_EXIT_SAVE_VMX_PREEMPTION_TIMER)
10194                         vmcs12->vmx_preemption_timer_value =
10195                                 vmx_get_preemption_timer_value(vcpu);
10196                 hrtimer_cancel(&to_vmx(vcpu)->nested.preemption_timer);
10197         }
10198
10199         /*
10200          * In some cases (usually, nested EPT), L2 is allowed to change its
10201          * own CR3 without exiting. If it has changed it, we must keep it.
10202          * Of course, if L0 is using shadow page tables, GUEST_CR3 was defined
10203          * by L0, not L1 or L2, so we mustn't unconditionally copy it to vmcs12.
10204          *
10205          * Additionally, restore L2's PDPTR to vmcs12.
10206          */
10207         if (enable_ept) {
10208                 vmcs12->guest_cr3 = vmcs_read64(GUEST_CR3);
10209                 vmcs12->guest_pdptr0 = vmcs_read64(GUEST_PDPTR0);
10210                 vmcs12->guest_pdptr1 = vmcs_read64(GUEST_PDPTR1);
10211                 vmcs12->guest_pdptr2 = vmcs_read64(GUEST_PDPTR2);
10212                 vmcs12->guest_pdptr3 = vmcs_read64(GUEST_PDPTR3);
10213         }
10214
10215         if (nested_cpu_has_vid(vmcs12))
10216                 vmcs12->guest_intr_status = vmcs_read16(GUEST_INTR_STATUS);
10217
10218         vmcs12->vm_entry_controls =
10219                 (vmcs12->vm_entry_controls & ~VM_ENTRY_IA32E_MODE) |
10220                 (vm_entry_controls_get(to_vmx(vcpu)) & VM_ENTRY_IA32E_MODE);
10221
10222         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_DEBUG_CONTROLS) {
10223                 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
10224                 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
10225         }
10226
10227         /* TODO: These cannot have changed unless we have MSR bitmaps and
10228          * the relevant bit asks not to trap the change */
10229         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_PAT)
10230                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
10231         if (vmcs12->vm_exit_controls & VM_EXIT_SAVE_IA32_EFER)
10232                 vmcs12->guest_ia32_efer = vcpu->arch.efer;
10233         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
10234         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
10235         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
10236         if (vmx_mpx_supported())
10237                 vmcs12->guest_bndcfgs = vmcs_read64(GUEST_BNDCFGS);
10238         if (nested_cpu_has_xsaves(vmcs12))
10239                 vmcs12->xss_exit_bitmap = vmcs_read64(XSS_EXIT_BITMAP);
10240
10241         /* update exit information fields: */
10242
10243         vmcs12->vm_exit_reason = exit_reason;
10244         vmcs12->exit_qualification = exit_qualification;
10245
10246         vmcs12->vm_exit_intr_info = exit_intr_info;
10247         if ((vmcs12->vm_exit_intr_info &
10248              (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK)) ==
10249             (INTR_INFO_VALID_MASK | INTR_INFO_DELIVER_CODE_MASK))
10250                 vmcs12->vm_exit_intr_error_code =
10251                         vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
10252         vmcs12->idt_vectoring_info_field = 0;
10253         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
10254         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
10255
10256         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY)) {
10257                 /* vm_entry_intr_info_field is cleared on exit. Emulate this
10258                  * instead of reading the real value. */
10259                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
10260
10261                 /*
10262                  * Transfer the event that L0 or L1 may wanted to inject into
10263                  * L2 to IDT_VECTORING_INFO_FIELD.
10264                  */
10265                 vmcs12_save_pending_event(vcpu, vmcs12);
10266         }
10267
10268         /*
10269          * Drop what we picked up for L2 via vmx_complete_interrupts. It is
10270          * preserved above and would only end up incorrectly in L1.
10271          */
10272         vcpu->arch.nmi_injected = false;
10273         kvm_clear_exception_queue(vcpu);
10274         kvm_clear_interrupt_queue(vcpu);
10275 }
10276
10277 /*
10278  * A part of what we need to when the nested L2 guest exits and we want to
10279  * run its L1 parent, is to reset L1's guest state to the host state specified
10280  * in vmcs12.
10281  * This function is to be called not only on normal nested exit, but also on
10282  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
10283  * Failures During or After Loading Guest State").
10284  * This function should be called when the active VMCS is L1's (vmcs01).
10285  */
10286 static void load_vmcs12_host_state(struct kvm_vcpu *vcpu,
10287                                    struct vmcs12 *vmcs12)
10288 {
10289         struct kvm_segment seg;
10290
10291         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
10292                 vcpu->arch.efer = vmcs12->host_ia32_efer;
10293         else if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10294                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
10295         else
10296                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
10297         vmx_set_efer(vcpu, vcpu->arch.efer);
10298
10299         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
10300         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
10301         vmx_set_rflags(vcpu, X86_EFLAGS_FIXED);
10302         /*
10303          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
10304          * actually changed, because it depends on the current state of
10305          * fpu_active (which may have changed).
10306          * Note that vmx_set_cr0 refers to efer set above.
10307          */
10308         vmx_set_cr0(vcpu, vmcs12->host_cr0);
10309         /*
10310          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
10311          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
10312          * but we also need to update cr0_guest_host_mask and exception_bitmap.
10313          */
10314         update_exception_bitmap(vcpu);
10315         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
10316         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
10317
10318         /*
10319          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
10320          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
10321          */
10322         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
10323         kvm_set_cr4(vcpu, vmcs12->host_cr4);
10324
10325         nested_ept_uninit_mmu_context(vcpu);
10326
10327         kvm_set_cr3(vcpu, vmcs12->host_cr3);
10328         kvm_mmu_reset_context(vcpu);
10329
10330         if (!enable_ept)
10331                 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
10332
10333         if (enable_vpid) {
10334                 /*
10335                  * Trivially support vpid by letting L2s share their parent
10336                  * L1's vpid. TODO: move to a more elaborate solution, giving
10337                  * each L2 its own vpid and exposing the vpid feature to L1.
10338                  */
10339                 vmx_flush_tlb(vcpu);
10340         }
10341
10342
10343         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
10344         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
10345         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
10346         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
10347         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
10348
10349         /* If not VM_EXIT_CLEAR_BNDCFGS, the L2 value propagates to L1.  */
10350         if (vmcs12->vm_exit_controls & VM_EXIT_CLEAR_BNDCFGS)
10351                 vmcs_write64(GUEST_BNDCFGS, 0);
10352
10353         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT) {
10354                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
10355                 vcpu->arch.pat = vmcs12->host_ia32_pat;
10356         }
10357         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
10358                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
10359                         vmcs12->host_ia32_perf_global_ctrl);
10360
10361         /* Set L1 segment info according to Intel SDM
10362             27.5.2 Loading Host Segment and Descriptor-Table Registers */
10363         seg = (struct kvm_segment) {
10364                 .base = 0,
10365                 .limit = 0xFFFFFFFF,
10366                 .selector = vmcs12->host_cs_selector,
10367                 .type = 11,
10368                 .present = 1,
10369                 .s = 1,
10370                 .g = 1
10371         };
10372         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
10373                 seg.l = 1;
10374         else
10375                 seg.db = 1;
10376         vmx_set_segment(vcpu, &seg, VCPU_SREG_CS);
10377         seg = (struct kvm_segment) {
10378                 .base = 0,
10379                 .limit = 0xFFFFFFFF,
10380                 .type = 3,
10381                 .present = 1,
10382                 .s = 1,
10383                 .db = 1,
10384                 .g = 1
10385         };
10386         seg.selector = vmcs12->host_ds_selector;
10387         vmx_set_segment(vcpu, &seg, VCPU_SREG_DS);
10388         seg.selector = vmcs12->host_es_selector;
10389         vmx_set_segment(vcpu, &seg, VCPU_SREG_ES);
10390         seg.selector = vmcs12->host_ss_selector;
10391         vmx_set_segment(vcpu, &seg, VCPU_SREG_SS);
10392         seg.selector = vmcs12->host_fs_selector;
10393         seg.base = vmcs12->host_fs_base;
10394         vmx_set_segment(vcpu, &seg, VCPU_SREG_FS);
10395         seg.selector = vmcs12->host_gs_selector;
10396         seg.base = vmcs12->host_gs_base;
10397         vmx_set_segment(vcpu, &seg, VCPU_SREG_GS);
10398         seg = (struct kvm_segment) {
10399                 .base = vmcs12->host_tr_base,
10400                 .limit = 0x67,
10401                 .selector = vmcs12->host_tr_selector,
10402                 .type = 11,
10403                 .present = 1
10404         };
10405         vmx_set_segment(vcpu, &seg, VCPU_SREG_TR);
10406
10407         kvm_set_dr(vcpu, 7, 0x400);
10408         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
10409
10410         if (cpu_has_vmx_msr_bitmap())
10411                 vmx_set_msr_bitmap(vcpu);
10412
10413         if (nested_vmx_load_msr(vcpu, vmcs12->vm_exit_msr_load_addr,
10414                                 vmcs12->vm_exit_msr_load_count))
10415                 nested_vmx_abort(vcpu, VMX_ABORT_LOAD_HOST_MSR_FAIL);
10416 }
10417
10418 /*
10419  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
10420  * and modify vmcs12 to make it see what it would expect to see there if
10421  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
10422  */
10423 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu, u32 exit_reason,
10424                               u32 exit_intr_info,
10425                               unsigned long exit_qualification)
10426 {
10427         struct vcpu_vmx *vmx = to_vmx(vcpu);
10428         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
10429
10430         /* trying to cancel vmlaunch/vmresume is a bug */
10431         WARN_ON_ONCE(vmx->nested.nested_run_pending);
10432
10433         leave_guest_mode(vcpu);
10434         prepare_vmcs12(vcpu, vmcs12, exit_reason, exit_intr_info,
10435                        exit_qualification);
10436
10437         if (nested_vmx_store_msr(vcpu, vmcs12->vm_exit_msr_store_addr,
10438                                  vmcs12->vm_exit_msr_store_count))
10439                 nested_vmx_abort(vcpu, VMX_ABORT_SAVE_GUEST_MSR_FAIL);
10440
10441         vmx_load_vmcs01(vcpu);
10442
10443         if ((exit_reason == EXIT_REASON_EXTERNAL_INTERRUPT)
10444             && nested_exit_intr_ack_set(vcpu)) {
10445                 int irq = kvm_cpu_get_interrupt(vcpu);
10446                 WARN_ON(irq < 0);
10447                 vmcs12->vm_exit_intr_info = irq |
10448                         INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR;
10449         }
10450
10451         trace_kvm_nested_vmexit_inject(vmcs12->vm_exit_reason,
10452                                        vmcs12->exit_qualification,
10453                                        vmcs12->idt_vectoring_info_field,
10454                                        vmcs12->vm_exit_intr_info,
10455                                        vmcs12->vm_exit_intr_error_code,
10456                                        KVM_ISA_VMX);
10457
10458         vm_entry_controls_init(vmx, vmcs_read32(VM_ENTRY_CONTROLS));
10459         vm_exit_controls_init(vmx, vmcs_read32(VM_EXIT_CONTROLS));
10460         vmx_segment_cache_clear(vmx);
10461
10462         /* if no vmcs02 cache requested, remove the one we used */
10463         if (VMCS02_POOL_SIZE == 0)
10464                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
10465
10466         load_vmcs12_host_state(vcpu, vmcs12);
10467
10468         /* Update TSC_OFFSET if TSC was changed while L2 ran */
10469         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
10470
10471         /* This is needed for same reason as it was needed in prepare_vmcs02 */
10472         vmx->host_rsp = 0;
10473
10474         /* Unpin physical memory we referred to in vmcs02 */
10475         if (vmx->nested.apic_access_page) {
10476                 nested_release_page(vmx->nested.apic_access_page);
10477                 vmx->nested.apic_access_page = NULL;
10478         }
10479         if (vmx->nested.virtual_apic_page) {
10480                 nested_release_page(vmx->nested.virtual_apic_page);
10481                 vmx->nested.virtual_apic_page = NULL;
10482         }
10483         if (vmx->nested.pi_desc_page) {
10484                 kunmap(vmx->nested.pi_desc_page);
10485                 nested_release_page(vmx->nested.pi_desc_page);
10486                 vmx->nested.pi_desc_page = NULL;
10487                 vmx->nested.pi_desc = NULL;
10488         }
10489
10490         /*
10491          * We are now running in L2, mmu_notifier will force to reload the
10492          * page's hpa for L2 vmcs. Need to reload it for L1 before entering L1.
10493          */
10494         kvm_vcpu_reload_apic_access_page(vcpu);
10495
10496         /*
10497          * Exiting from L2 to L1, we're now back to L1 which thinks it just
10498          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
10499          * success or failure flag accordingly.
10500          */
10501         if (unlikely(vmx->fail)) {
10502                 vmx->fail = 0;
10503                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
10504         } else
10505                 nested_vmx_succeed(vcpu);
10506         if (enable_shadow_vmcs)
10507                 vmx->nested.sync_shadow_vmcs = true;
10508
10509         /* in case we halted in L2 */
10510         vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
10511 }
10512
10513 /*
10514  * Forcibly leave nested mode in order to be able to reset the VCPU later on.
10515  */
10516 static void vmx_leave_nested(struct kvm_vcpu *vcpu)
10517 {
10518         if (is_guest_mode(vcpu))
10519                 nested_vmx_vmexit(vcpu, -1, 0, 0);
10520         free_nested(to_vmx(vcpu));
10521 }
10522
10523 /*
10524  * L1's failure to enter L2 is a subset of a normal exit, as explained in
10525  * 23.7 "VM-entry failures during or after loading guest state" (this also
10526  * lists the acceptable exit-reason and exit-qualification parameters).
10527  * It should only be called before L2 actually succeeded to run, and when
10528  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
10529  */
10530 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
10531                         struct vmcs12 *vmcs12,
10532                         u32 reason, unsigned long qualification)
10533 {
10534         load_vmcs12_host_state(vcpu, vmcs12);
10535         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
10536         vmcs12->exit_qualification = qualification;
10537         nested_vmx_succeed(vcpu);
10538         if (enable_shadow_vmcs)
10539                 to_vmx(vcpu)->nested.sync_shadow_vmcs = true;
10540 }
10541
10542 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
10543                                struct x86_instruction_info *info,
10544                                enum x86_intercept_stage stage)
10545 {
10546         return X86EMUL_CONTINUE;
10547 }
10548
10549 static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
10550 {
10551         if (ple_gap)
10552                 shrink_ple_window(vcpu);
10553 }
10554
10555 static void vmx_slot_enable_log_dirty(struct kvm *kvm,
10556                                      struct kvm_memory_slot *slot)
10557 {
10558         kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
10559         kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
10560 }
10561
10562 static void vmx_slot_disable_log_dirty(struct kvm *kvm,
10563                                        struct kvm_memory_slot *slot)
10564 {
10565         kvm_mmu_slot_set_dirty(kvm, slot);
10566 }
10567
10568 static void vmx_flush_log_dirty(struct kvm *kvm)
10569 {
10570         kvm_flush_pml_buffers(kvm);
10571 }
10572
10573 static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
10574                                            struct kvm_memory_slot *memslot,
10575                                            gfn_t offset, unsigned long mask)
10576 {
10577         kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
10578 }
10579
10580 /*
10581  * This routine does the following things for vCPU which is going
10582  * to be blocked if VT-d PI is enabled.
10583  * - Store the vCPU to the wakeup list, so when interrupts happen
10584  *   we can find the right vCPU to wake up.
10585  * - Change the Posted-interrupt descriptor as below:
10586  *      'NDST' <-- vcpu->pre_pcpu
10587  *      'NV' <-- POSTED_INTR_WAKEUP_VECTOR
10588  * - If 'ON' is set during this process, which means at least one
10589  *   interrupt is posted for this vCPU, we cannot block it, in
10590  *   this case, return 1, otherwise, return 0.
10591  *
10592  */
10593 static int vmx_pre_block(struct kvm_vcpu *vcpu)
10594 {
10595         unsigned long flags;
10596         unsigned int dest;
10597         struct pi_desc old, new;
10598         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10599
10600         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10601                 !irq_remapping_cap(IRQ_POSTING_CAP))
10602                 return 0;
10603
10604         vcpu->pre_pcpu = vcpu->cpu;
10605         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10606                           vcpu->pre_pcpu), flags);
10607         list_add_tail(&vcpu->blocked_vcpu_list,
10608                       &per_cpu(blocked_vcpu_on_cpu,
10609                       vcpu->pre_pcpu));
10610         spin_unlock_irqrestore(&per_cpu(blocked_vcpu_on_cpu_lock,
10611                                vcpu->pre_pcpu), flags);
10612
10613         do {
10614                 old.control = new.control = pi_desc->control;
10615
10616                 /*
10617                  * We should not block the vCPU if
10618                  * an interrupt is posted for it.
10619                  */
10620                 if (pi_test_on(pi_desc) == 1) {
10621                         spin_lock_irqsave(&per_cpu(blocked_vcpu_on_cpu_lock,
10622                                           vcpu->pre_pcpu), flags);
10623                         list_del(&vcpu->blocked_vcpu_list);
10624                         spin_unlock_irqrestore(
10625                                         &per_cpu(blocked_vcpu_on_cpu_lock,
10626                                         vcpu->pre_pcpu), flags);
10627                         vcpu->pre_pcpu = -1;
10628
10629                         return 1;
10630                 }
10631
10632                 WARN((pi_desc->sn == 1),
10633                      "Warning: SN field of posted-interrupts "
10634                      "is set before blocking\n");
10635
10636                 /*
10637                  * Since vCPU can be preempted during this process,
10638                  * vcpu->cpu could be different with pre_pcpu, we
10639                  * need to set pre_pcpu as the destination of wakeup
10640                  * notification event, then we can find the right vCPU
10641                  * to wakeup in wakeup handler if interrupts happen
10642                  * when the vCPU is in blocked state.
10643                  */
10644                 dest = cpu_physical_id(vcpu->pre_pcpu);
10645
10646                 if (x2apic_enabled())
10647                         new.ndst = dest;
10648                 else
10649                         new.ndst = (dest << 8) & 0xFF00;
10650
10651                 /* set 'NV' to 'wakeup vector' */
10652                 new.nv = POSTED_INTR_WAKEUP_VECTOR;
10653         } while (cmpxchg(&pi_desc->control, old.control,
10654                         new.control) != old.control);
10655
10656         return 0;
10657 }
10658
10659 static void vmx_post_block(struct kvm_vcpu *vcpu)
10660 {
10661         struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
10662         struct pi_desc old, new;
10663         unsigned int dest;
10664         unsigned long flags;
10665
10666         if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
10667                 !irq_remapping_cap(IRQ_POSTING_CAP))
10668                 return;
10669
10670         do {
10671                 old.control = new.control = pi_desc->control;
10672
10673                 dest = cpu_physical_id(vcpu->cpu);
10674
10675                 if (x2apic_enabled())
10676                         new.ndst = dest;
10677                 else
10678                         new.ndst = (dest << 8) & 0xFF00;
10679
10680                 /* Allow posting non-urgent interrupts */
10681                 new.sn = 0;
10682
10683                 /* set 'NV' to 'notification vector' */
10684                 new.nv = POSTED_INTR_VECTOR;
10685         } while (cmpxchg(&pi_desc->control, old.control,
10686                         new.control) != old.control);
10687
10688         if(vcpu->pre_pcpu != -1) {
10689                 spin_lock_irqsave(
10690                         &per_cpu(blocked_vcpu_on_cpu_lock,
10691                         vcpu->pre_pcpu), flags);
10692                 list_del(&vcpu->blocked_vcpu_list);
10693                 spin_unlock_irqrestore(
10694                         &per_cpu(blocked_vcpu_on_cpu_lock,
10695                         vcpu->pre_pcpu), flags);
10696                 vcpu->pre_pcpu = -1;
10697         }
10698 }
10699
10700 /*
10701  * vmx_update_pi_irte - set IRTE for Posted-Interrupts
10702  *
10703  * @kvm: kvm
10704  * @host_irq: host irq of the interrupt
10705  * @guest_irq: gsi of the interrupt
10706  * @set: set or unset PI
10707  * returns 0 on success, < 0 on failure
10708  */
10709 static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
10710                               uint32_t guest_irq, bool set)
10711 {
10712         struct kvm_kernel_irq_routing_entry *e;
10713         struct kvm_irq_routing_table *irq_rt;
10714         struct kvm_lapic_irq irq;
10715         struct kvm_vcpu *vcpu;
10716         struct vcpu_data vcpu_info;
10717         int idx, ret = -EINVAL;
10718
10719         if (!kvm_arch_has_assigned_device(kvm) ||
10720                 !irq_remapping_cap(IRQ_POSTING_CAP))
10721                 return 0;
10722
10723         idx = srcu_read_lock(&kvm->irq_srcu);
10724         irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
10725         BUG_ON(guest_irq >= irq_rt->nr_rt_entries);
10726
10727         hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
10728                 if (e->type != KVM_IRQ_ROUTING_MSI)
10729                         continue;
10730                 /*
10731                  * VT-d PI cannot support posting multicast/broadcast
10732                  * interrupts to a vCPU, we still use interrupt remapping
10733                  * for these kind of interrupts.
10734                  *
10735                  * For lowest-priority interrupts, we only support
10736                  * those with single CPU as the destination, e.g. user
10737                  * configures the interrupts via /proc/irq or uses
10738                  * irqbalance to make the interrupts single-CPU.
10739                  *
10740                  * We will support full lowest-priority interrupt later.
10741                  */
10742
10743                 kvm_set_msi_irq(e, &irq);
10744                 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu))
10745                         continue;
10746
10747                 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
10748                 vcpu_info.vector = irq.vector;
10749
10750                 trace_kvm_pi_irte_update(vcpu->vcpu_id, e->gsi,
10751                                 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
10752
10753                 if (set)
10754                         ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
10755                 else {
10756                         /* suppress notification event before unposting */
10757                         pi_set_sn(vcpu_to_pi_desc(vcpu));
10758                         ret = irq_set_vcpu_affinity(host_irq, NULL);
10759                         pi_clear_sn(vcpu_to_pi_desc(vcpu));
10760                 }
10761
10762                 if (ret < 0) {
10763                         printk(KERN_INFO "%s: failed to update PI IRTE\n",
10764                                         __func__);
10765                         goto out;
10766                 }
10767         }
10768
10769         ret = 0;
10770 out:
10771         srcu_read_unlock(&kvm->irq_srcu, idx);
10772         return ret;
10773 }
10774
10775 static struct kvm_x86_ops vmx_x86_ops = {
10776         .cpu_has_kvm_support = cpu_has_kvm_support,
10777         .disabled_by_bios = vmx_disabled_by_bios,
10778         .hardware_setup = hardware_setup,
10779         .hardware_unsetup = hardware_unsetup,
10780         .check_processor_compatibility = vmx_check_processor_compat,
10781         .hardware_enable = hardware_enable,
10782         .hardware_disable = hardware_disable,
10783         .cpu_has_accelerated_tpr = report_flexpriority,
10784         .cpu_has_high_real_mode_segbase = vmx_has_high_real_mode_segbase,
10785
10786         .vcpu_create = vmx_create_vcpu,
10787         .vcpu_free = vmx_free_vcpu,
10788         .vcpu_reset = vmx_vcpu_reset,
10789
10790         .prepare_guest_switch = vmx_save_host_state,
10791         .vcpu_load = vmx_vcpu_load,
10792         .vcpu_put = vmx_vcpu_put,
10793
10794         .update_bp_intercept = update_exception_bitmap,
10795         .get_msr = vmx_get_msr,
10796         .set_msr = vmx_set_msr,
10797         .get_segment_base = vmx_get_segment_base,
10798         .get_segment = vmx_get_segment,
10799         .set_segment = vmx_set_segment,
10800         .get_cpl = vmx_get_cpl,
10801         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
10802         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
10803         .decache_cr3 = vmx_decache_cr3,
10804         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
10805         .set_cr0 = vmx_set_cr0,
10806         .set_cr3 = vmx_set_cr3,
10807         .set_cr4 = vmx_set_cr4,
10808         .set_efer = vmx_set_efer,
10809         .get_idt = vmx_get_idt,
10810         .set_idt = vmx_set_idt,
10811         .get_gdt = vmx_get_gdt,
10812         .set_gdt = vmx_set_gdt,
10813         .get_dr6 = vmx_get_dr6,
10814         .set_dr6 = vmx_set_dr6,
10815         .set_dr7 = vmx_set_dr7,
10816         .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
10817         .cache_reg = vmx_cache_reg,
10818         .get_rflags = vmx_get_rflags,
10819         .set_rflags = vmx_set_rflags,
10820         .fpu_activate = vmx_fpu_activate,
10821         .fpu_deactivate = vmx_fpu_deactivate,
10822
10823         .tlb_flush = vmx_flush_tlb,
10824
10825         .run = vmx_vcpu_run,
10826         .handle_exit = vmx_handle_exit,
10827         .skip_emulated_instruction = skip_emulated_instruction,
10828         .set_interrupt_shadow = vmx_set_interrupt_shadow,
10829         .get_interrupt_shadow = vmx_get_interrupt_shadow,
10830         .patch_hypercall = vmx_patch_hypercall,
10831         .set_irq = vmx_inject_irq,
10832         .set_nmi = vmx_inject_nmi,
10833         .queue_exception = vmx_queue_exception,
10834         .cancel_injection = vmx_cancel_injection,
10835         .interrupt_allowed = vmx_interrupt_allowed,
10836         .nmi_allowed = vmx_nmi_allowed,
10837         .get_nmi_mask = vmx_get_nmi_mask,
10838         .set_nmi_mask = vmx_set_nmi_mask,
10839         .enable_nmi_window = enable_nmi_window,
10840         .enable_irq_window = enable_irq_window,
10841         .update_cr8_intercept = update_cr8_intercept,
10842         .set_virtual_x2apic_mode = vmx_set_virtual_x2apic_mode,
10843         .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
10844         .cpu_uses_apicv = vmx_cpu_uses_apicv,
10845         .load_eoi_exitmap = vmx_load_eoi_exitmap,
10846         .hwapic_irr_update = vmx_hwapic_irr_update,
10847         .hwapic_isr_update = vmx_hwapic_isr_update,
10848         .sync_pir_to_irr = vmx_sync_pir_to_irr,
10849         .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
10850
10851         .set_tss_addr = vmx_set_tss_addr,
10852         .get_tdp_level = get_ept_level,
10853         .get_mt_mask = vmx_get_mt_mask,
10854
10855         .get_exit_info = vmx_get_exit_info,
10856
10857         .get_lpage_level = vmx_get_lpage_level,
10858
10859         .cpuid_update = vmx_cpuid_update,
10860
10861         .rdtscp_supported = vmx_rdtscp_supported,
10862         .invpcid_supported = vmx_invpcid_supported,
10863
10864         .set_supported_cpuid = vmx_set_supported_cpuid,
10865
10866         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
10867
10868         .read_tsc_offset = vmx_read_tsc_offset,
10869         .write_tsc_offset = vmx_write_tsc_offset,
10870         .adjust_tsc_offset_guest = vmx_adjust_tsc_offset_guest,
10871         .read_l1_tsc = vmx_read_l1_tsc,
10872
10873         .set_tdp_cr3 = vmx_set_cr3,
10874
10875         .check_intercept = vmx_check_intercept,
10876         .handle_external_intr = vmx_handle_external_intr,
10877         .mpx_supported = vmx_mpx_supported,
10878         .xsaves_supported = vmx_xsaves_supported,
10879
10880         .check_nested_events = vmx_check_nested_events,
10881
10882         .sched_in = vmx_sched_in,
10883
10884         .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
10885         .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
10886         .flush_log_dirty = vmx_flush_log_dirty,
10887         .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
10888
10889         .pre_block = vmx_pre_block,
10890         .post_block = vmx_post_block,
10891
10892         .pmu_ops = &intel_pmu_ops,
10893
10894         .update_pi_irte = vmx_update_pi_irte,
10895 };
10896
10897 static int __init vmx_init(void)
10898 {
10899         int r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
10900                      __alignof__(struct vcpu_vmx), THIS_MODULE);
10901         if (r)
10902                 return r;
10903
10904 #ifdef CONFIG_KEXEC_CORE
10905         rcu_assign_pointer(crash_vmclear_loaded_vmcss,
10906                            crash_vmclear_local_loaded_vmcss);
10907 #endif
10908
10909         return 0;
10910 }
10911
10912 static void __exit vmx_exit(void)
10913 {
10914 #ifdef CONFIG_KEXEC_CORE
10915         RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
10916         synchronize_rcu();
10917 #endif
10918
10919         kvm_exit();
10920 }
10921
10922 module_init(vmx_init)
10923 module_exit(vmx_exit)